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finished new 5V buck, layout

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This commit is contained in:
janik
2025-09-04 17:26:10 +07:00
parent 73e2e7840d
commit 5594ab60b3
48 changed files with 90097 additions and 19869 deletions
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4
code/.cproject
View File

@@ -24,7 +24,7 @@
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.569851536" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.493855913" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1904983327" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32G474CBTx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32G4xx_HAL_Driver/Inc | ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32G4xx/Include | ../Drivers/CMSIS/Include || || || USE_HAL_DRIVER | STM32G474xx || || Drivers | Core/Startup | Core || || || ${workspace_loc:/${ProjName}/STM32G474CBTX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || || || " valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1640224048" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="16" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1640224048" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="170" valueType="string"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1281027497" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
<builder buildPath="${workspace_loc:/C64PSU}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.735311501" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.2006906671" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
@@ -104,7 +104,7 @@
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.1043717698" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.740239677" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.382897756" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32G474CBTx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32G4xx_HAL_Driver/Inc | ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32G4xx/Include | ../Drivers/CMSIS/Include || || || USE_HAL_DRIVER | STM32G474xx || || Drivers | Core/Startup | Core || || || ${workspace_loc:/${ProjName}/STM32G474CBTX_FLASH.ld} || true || NonSecure || || secure_nsclib.o || || None || || || " valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1137781942" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="16" valueType="string"/>
<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1137781942" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="170" valueType="string"/>
<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1467828888" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
<builder buildPath="${workspace_loc:/C64PSU}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1030449639" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.819839422" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">

4
code/.mxproject
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File diff suppressed because one or more lines are too long

74
code/C64PSU.ioc
View File

@@ -147,50 +147,54 @@ ProjectManager.ToolChainLocation=
ProjectManager.UAScriptAfterPath=
ProjectManager.UAScriptBeforePath=
ProjectManager.UnderRoot=true
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_TIM1_Init-TIM1-false-HAL-true,4-MX_CORDIC_Init-CORDIC-false-HAL-true,5-MX_FMAC_Init-FMAC-false-HAL-true
RCC.AHBFreq_Value=16000000
RCC.APB1Freq_Value=16000000
RCC.APB1TimFreq_Value=16000000
RCC.APB2Freq_Value=16000000
RCC.APB2TimFreq_Value=16000000
ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_TIM1_Init-TIM1-false-HAL-true,4-MX_CORDIC_Init-CORDIC-false-HAL-true,5-MX_FMAC_Init-FMAC-false-HAL-true,6-MX_ADC3_Init-ADC3-false-HAL-true,7-MX_ADC4_Init-ADC4-false-HAL-true,8-MX_COMP5_Init-COMP5-false-HAL-true,9-MX_COMP7_Init-COMP7-false-HAL-true,10-MX_DAC1_Init-DAC1-false-HAL-true,11-MX_DAC4_Init-DAC4-false-HAL-true,12-MX_HRTIM1_Init-HRTIM1-false-HAL-true,13-MX_USART1_UART_Init-USART1-false-HAL-true
RCC.ADC12Freq_Value=170000000
RCC.ADC345Freq_Value=170000000
RCC.AHBFreq_Value=170000000
RCC.APB1Freq_Value=170000000
RCC.APB1TimFreq_Value=170000000
RCC.APB2Freq_Value=170000000
RCC.APB2TimFreq_Value=170000000
RCC.CRSFreq_Value=48000000
RCC.CortexFreq_Value=16000000
RCC.CortexFreq_Value=170000000
RCC.EXTERNAL_CLOCK_VALUE=12288000
RCC.FCLKCortexFreq_Value=16000000
RCC.FDCANFreq_Value=16000000
RCC.FCLKCortexFreq_Value=170000000
RCC.FDCANFreq_Value=170000000
RCC.FamilyName=M
RCC.HCLKFreq_Value=16000000
RCC.HRTIM1Freq_Value=16000000
RCC.HSE_VALUE=8000000
RCC.HCLKFreq_Value=170000000
RCC.HSE_VALUE=40000000
RCC.HSI48_VALUE=48000000
RCC.HSI_VALUE=16000000
RCC.I2C1Freq_Value=16000000
RCC.I2C2Freq_Value=16000000
RCC.I2C3Freq_Value=16000000
RCC.I2C4Freq_Value=16000000
RCC.I2SFreq_Value=16000000
RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HRTIM1Freq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,PWRFreq_Value,QSPIFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
RCC.LPTIM1Freq_Value=16000000
RCC.LPUART1Freq_Value=16000000
RCC.I2C1Freq_Value=170000000
RCC.I2C2Freq_Value=170000000
RCC.I2C3Freq_Value=170000000
RCC.I2C4Freq_Value=170000000
RCC.I2SFreq_Value=170000000
RCC.IPParameters=ADC12Freq_Value,ADC345Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,PWRFreq_Value,QSPIFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
RCC.LPTIM1Freq_Value=170000000
RCC.LPUART1Freq_Value=170000000
RCC.LSCOPinFreq_Value=32000
RCC.LSE_VALUE=32768
RCC.LSI_VALUE=32000
RCC.MCO1PinFreq_Value=16000000
RCC.PLLPoutputFreq_Value=32000000
RCC.PLLQoutputFreq_Value=32000000
RCC.PLLRCLKFreq_Value=32000000
RCC.PLLM=RCC_PLLM_DIV4
RCC.PLLN=34
RCC.PLLPoutputFreq_Value=170000000
RCC.PLLQoutputFreq_Value=170000000
RCC.PLLRCLKFreq_Value=170000000
RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
RCC.PWRFreq_Value=16000000
RCC.QSPIFreq_Value=16000000
RCC.RNGFreq_Value=32000000
RCC.SAI1Freq_Value=16000000
RCC.SYSCLKFreq_VALUE=16000000
RCC.USART1Freq_Value=16000000
RCC.USART2Freq_Value=16000000
RCC.USART3Freq_Value=16000000
RCC.USBFreq_Value=32000000
RCC.VCOInputFreq_Value=8000000
RCC.VCOOutputFreq_Value=64000000
RCC.PWRFreq_Value=170000000
RCC.QSPIFreq_Value=170000000
RCC.RNGFreq_Value=170000000
RCC.SAI1Freq_Value=170000000
RCC.SYSCLKFreq_VALUE=170000000
RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
RCC.USART1Freq_Value=170000000
RCC.USART2Freq_Value=170000000
RCC.USART3Freq_Value=170000000
RCC.USBFreq_Value=170000000
RCC.VCOInputFreq_Value=10000000
RCC.VCOOutputFreq_Value=340000000
SH.SharedAnalog_PB13.0=ADC3_IN5,IN5-Single-Ended
SH.SharedAnalog_PB13.1=COMP5_INP,INP
SH.SharedAnalog_PB13.ConfNb=2
@@ -222,4 +226,4 @@ VP_SYS_V_VREFBUF.Signal=SYS_V_VREFBUF
VP_TIM1_VS_ClockSourceINT.Mode=Internal
VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
board=custom
isbadioc=true
isbadioc=false

2
code/Core/Inc/main.h
View File

@@ -49,6 +49,8 @@ extern "C" {
/* USER CODE END EM */
void HAL_HRTIM_MspPostInit(HRTIM_HandleTypeDef *hhrtim);
/* Exported functions prototypes ---------------------------------------------*/
void Error_Handler(void);

12
code/Core/Inc/stm32g4xx_hal_conf.h
View File

@@ -36,15 +36,15 @@
#define HAL_MODULE_ENABLED
/*#define HAL_ADC_MODULE_ENABLED */
/*#define HAL_COMP_MODULE_ENABLED */
#define HAL_ADC_MODULE_ENABLED
#define HAL_COMP_MODULE_ENABLED
#define HAL_CORDIC_MODULE_ENABLED
/*#define HAL_CRC_MODULE_ENABLED */
/*#define HAL_CRYP_MODULE_ENABLED */
/*#define HAL_DAC_MODULE_ENABLED */
#define HAL_DAC_MODULE_ENABLED
/*#define HAL_FDCAN_MODULE_ENABLED */
#define HAL_FMAC_MODULE_ENABLED
/*#define HAL_HRTIM_MODULE_ENABLED */
#define HAL_HRTIM_MODULE_ENABLED
/*#define HAL_IRDA_MODULE_ENABLED */
/*#define HAL_IWDG_MODULE_ENABLED */
/*#define HAL_I2C_MODULE_ENABLED */
@@ -63,7 +63,7 @@
/*#define HAL_SPI_MODULE_ENABLED */
/*#define HAL_SRAM_MODULE_ENABLED */
#define HAL_TIM_MODULE_ENABLED
/*#define HAL_UART_MODULE_ENABLED */
#define HAL_UART_MODULE_ENABLED
/*#define HAL_USART_MODULE_ENABLED */
/*#define HAL_WWDG_MODULE_ENABLED */
#define HAL_GPIO_MODULE_ENABLED
@@ -115,7 +115,7 @@
* (when HSE is used as system clock source, directly or through the PLL).
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE (8000000UL) /*!< Value of the External oscillator in Hz */
#define HSE_VALUE (40000000UL) /*!< Value of the External oscillator in Hz */
#endif /* HSE_VALUE */
#if !defined (HSE_STARTUP_TIMEOUT)

524
code/Core/Src/main.c
View File

@@ -40,12 +40,25 @@
/* USER CODE END PM */
/* Private variables ---------------------------------------------------------*/
ADC_HandleTypeDef hadc3;
ADC_HandleTypeDef hadc4;
COMP_HandleTypeDef hcomp5;
COMP_HandleTypeDef hcomp7;
CORDIC_HandleTypeDef hcordic;
DAC_HandleTypeDef hdac1;
DAC_HandleTypeDef hdac4;
FMAC_HandleTypeDef hfmac;
HRTIM_HandleTypeDef hhrtim1;
TIM_HandleTypeDef htim1;
UART_HandleTypeDef huart1;
/* USER CODE BEGIN PV */
/* USER CODE END PV */
@@ -56,6 +69,14 @@ static void MX_GPIO_Init(void);
static void MX_TIM1_Init(void);
static void MX_CORDIC_Init(void);
static void MX_FMAC_Init(void);
static void MX_ADC3_Init(void);
static void MX_ADC4_Init(void);
static void MX_COMP5_Init(void);
static void MX_COMP7_Init(void);
static void MX_DAC1_Init(void);
static void MX_DAC4_Init(void);
static void MX_HRTIM1_Init(void);
static void MX_USART1_UART_Init(void);
/* USER CODE BEGIN PFP */
/* USER CODE END PFP */
@@ -97,6 +118,14 @@ int main(void)
MX_TIM1_Init();
MX_CORDIC_Init();
MX_FMAC_Init();
MX_ADC3_Init();
MX_ADC4_Init();
MX_COMP5_Init();
MX_COMP7_Init();
MX_DAC1_Init();
MX_DAC4_Init();
MX_HRTIM1_Init();
MX_USART1_UART_Init();
/* USER CODE BEGIN 2 */
/* USER CODE END 2 */
@@ -123,15 +152,20 @@ void SystemClock_Config(void)
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
RCC_OscInitStruct.PLL.PLLN = 34;
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
Error_Handler();
@@ -141,17 +175,208 @@ void SystemClock_Config(void)
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
{
Error_Handler();
}
}
/**
* @brief ADC3 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC3_Init(void)
{
/* USER CODE BEGIN ADC3_Init 0 */
/* USER CODE END ADC3_Init 0 */
ADC_MultiModeTypeDef multimode = {0};
ADC_ChannelConfTypeDef sConfig = {0};
/* USER CODE BEGIN ADC3_Init 1 */
/* USER CODE END ADC3_Init 1 */
/** Common config
*/
hadc3.Instance = ADC3;
hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
hadc3.Init.Resolution = ADC_RESOLUTION_12B;
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc3.Init.GainCompensation = 0;
hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc3.Init.LowPowerAutoWait = DISABLE;
hadc3.Init.ContinuousConvMode = DISABLE;
hadc3.Init.NbrOfConversion = 1;
hadc3.Init.DiscontinuousConvMode = DISABLE;
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc3.Init.DMAContinuousRequests = DISABLE;
hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED;
hadc3.Init.OversamplingMode = DISABLE;
if (HAL_ADC_Init(&hadc3) != HAL_OK)
{
Error_Handler();
}
/** Configure the ADC multi-mode
*/
multimode.Mode = ADC_MODE_INDEPENDENT;
if (HAL_ADCEx_MultiModeConfigChannel(&hadc3, &multimode) != HAL_OK)
{
Error_Handler();
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_5;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ADC3_Init 2 */
/* USER CODE END ADC3_Init 2 */
}
/**
* @brief ADC4 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC4_Init(void)
{
/* USER CODE BEGIN ADC4_Init 0 */
/* USER CODE END ADC4_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
/* USER CODE BEGIN ADC4_Init 1 */
/* USER CODE END ADC4_Init 1 */
/** Common config
*/
hadc4.Instance = ADC4;
hadc4.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
hadc4.Init.Resolution = ADC_RESOLUTION_12B;
hadc4.Init.DataAlign = ADC_DATAALIGN_RIGHT;
hadc4.Init.GainCompensation = 0;
hadc4.Init.ScanConvMode = ADC_SCAN_DISABLE;
hadc4.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
hadc4.Init.LowPowerAutoWait = DISABLE;
hadc4.Init.ContinuousConvMode = DISABLE;
hadc4.Init.NbrOfConversion = 1;
hadc4.Init.DiscontinuousConvMode = DISABLE;
hadc4.Init.ExternalTrigConv = ADC_SOFTWARE_START;
hadc4.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
hadc4.Init.DMAContinuousRequests = DISABLE;
hadc4.Init.Overrun = ADC_OVR_DATA_PRESERVED;
hadc4.Init.OversamplingMode = DISABLE;
if (HAL_ADC_Init(&hadc4) != HAL_OK)
{
Error_Handler();
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_4;
sConfig.Rank = ADC_REGULAR_RANK_1;
sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
sConfig.SingleDiff = ADC_SINGLE_ENDED;
sConfig.OffsetNumber = ADC_OFFSET_NONE;
sConfig.Offset = 0;
if (HAL_ADC_ConfigChannel(&hadc4, &sConfig) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN ADC4_Init 2 */
/* USER CODE END ADC4_Init 2 */
}
/**
* @brief COMP5 Initialization Function
* @param None
* @retval None
*/
static void MX_COMP5_Init(void)
{
/* USER CODE BEGIN COMP5_Init 0 */
/* USER CODE END COMP5_Init 0 */
/* USER CODE BEGIN COMP5_Init 1 */
/* USER CODE END COMP5_Init 1 */
hcomp5.Instance = COMP5;
hcomp5.Init.InputPlus = COMP_INPUT_PLUS_IO1;
hcomp5.Init.InputMinus = COMP_INPUT_MINUS_DAC1_CH2;
hcomp5.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED;
hcomp5.Init.Hysteresis = COMP_HYSTERESIS_NONE;
hcomp5.Init.BlankingSrce = COMP_BLANKINGSRC_NONE;
hcomp5.Init.TriggerMode = COMP_TRIGGERMODE_NONE;
if (HAL_COMP_Init(&hcomp5) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN COMP5_Init 2 */
/* USER CODE END COMP5_Init 2 */
}
/**
* @brief COMP7 Initialization Function
* @param None
* @retval None
*/
static void MX_COMP7_Init(void)
{
/* USER CODE BEGIN COMP7_Init 0 */
/* USER CODE END COMP7_Init 0 */
/* USER CODE BEGIN COMP7_Init 1 */
/* USER CODE END COMP7_Init 1 */
hcomp7.Instance = COMP7;
hcomp7.Init.InputPlus = COMP_INPUT_PLUS_IO1;
hcomp7.Init.InputMinus = COMP_INPUT_MINUS_DAC4_CH1;
hcomp7.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED;
hcomp7.Init.Hysteresis = COMP_HYSTERESIS_NONE;
hcomp7.Init.BlankingSrce = COMP_BLANKINGSRC_NONE;
hcomp7.Init.TriggerMode = COMP_TRIGGERMODE_NONE;
if (HAL_COMP_Init(&hcomp7) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN COMP7_Init 2 */
/* USER CODE END COMP7_Init 2 */
}
/**
* @brief CORDIC Initialization Function
* @param None
@@ -178,6 +403,100 @@ static void MX_CORDIC_Init(void)
}
/**
* @brief DAC1 Initialization Function
* @param None
* @retval None
*/
static void MX_DAC1_Init(void)
{
/* USER CODE BEGIN DAC1_Init 0 */
/* USER CODE END DAC1_Init 0 */
DAC_ChannelConfTypeDef sConfig = {0};
/* USER CODE BEGIN DAC1_Init 1 */
/* USER CODE END DAC1_Init 1 */
/** DAC Initialization
*/
hdac1.Instance = DAC1;
if (HAL_DAC_Init(&hdac1) != HAL_OK)
{
Error_Handler();
}
/** DAC channel OUT2 config
*/
sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC;
sConfig.DAC_DMADoubleDataMode = DISABLE;
sConfig.DAC_SignedFormat = DISABLE;
sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE;
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN DAC1_Init 2 */
/* USER CODE END DAC1_Init 2 */
}
/**
* @brief DAC4 Initialization Function
* @param None
* @retval None
*/
static void MX_DAC4_Init(void)
{
/* USER CODE BEGIN DAC4_Init 0 */
/* USER CODE END DAC4_Init 0 */
DAC_ChannelConfTypeDef sConfig = {0};
/* USER CODE BEGIN DAC4_Init 1 */
/* USER CODE END DAC4_Init 1 */
/** DAC Initialization
*/
hdac4.Instance = DAC4;
if (HAL_DAC_Init(&hdac4) != HAL_OK)
{
Error_Handler();
}
/** DAC channel OUT1 config
*/
sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC;
sConfig.DAC_DMADoubleDataMode = DISABLE;
sConfig.DAC_SignedFormat = DISABLE;
sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE;
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
if (HAL_DAC_ConfigChannel(&hdac4, &sConfig, DAC_CHANNEL_1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN DAC4_Init 2 */
/* USER CODE END DAC4_Init 2 */
}
/**
* @brief FMAC Initialization Function
* @param None
@@ -204,6 +523,148 @@ static void MX_FMAC_Init(void)
}
/**
* @brief HRTIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_HRTIM1_Init(void)
{
/* USER CODE BEGIN HRTIM1_Init 0 */
/* USER CODE END HRTIM1_Init 0 */
HRTIM_EventCfgTypeDef pEventCfg = {0};
HRTIM_TimeBaseCfgTypeDef pTimeBaseCfg = {0};
HRTIM_TimerCfgTypeDef pTimerCfg = {0};
HRTIM_TimerCtlTypeDef pTimerCtl = {0};
HRTIM_OutputCfgTypeDef pOutputCfg = {0};
/* USER CODE BEGIN HRTIM1_Init 1 */
/* USER CODE END HRTIM1_Init 1 */
hhrtim1.Instance = HRTIM1;
hhrtim1.Init.HRTIMInterruptResquests = HRTIM_IT_NONE;
hhrtim1.Init.SyncOptions = HRTIM_SYNCOPTION_NONE;
if (HAL_HRTIM_Init(&hhrtim1) != HAL_OK)
{
Error_Handler();
}
if (HAL_HRTIM_DLLCalibrationStart(&hhrtim1, HRTIM_CALIBRATIONRATE_3) != HAL_OK)
{
Error_Handler();
}
if (HAL_HRTIM_PollForDLLCalibration(&hhrtim1, 10) != HAL_OK)
{
Error_Handler();
}
if (HAL_HRTIM_EventPrescalerConfig(&hhrtim1, HRTIM_EVENTPRESCALER_DIV1) != HAL_OK)
{
Error_Handler();
}
pEventCfg.Source = HRTIM_EEV1SRC_COMP2_OUT;
pEventCfg.Polarity = HRTIM_EVENTPOLARITY_HIGH;
pEventCfg.Sensitivity = HRTIM_EVENTSENSITIVITY_LEVEL;
pEventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
if (HAL_HRTIM_EventConfig(&hhrtim1, HRTIM_EVENT_1, &pEventCfg) != HAL_OK)
{
Error_Handler();
}
pTimeBaseCfg.Period = 0xFFDF;
pTimeBaseCfg.RepetitionCounter = 0x00;
pTimeBaseCfg.PrescalerRatio = HRTIM_PRESCALERRATIO_MUL32;
pTimeBaseCfg.Mode = HRTIM_MODE_CONTINUOUS;
if (HAL_HRTIM_TimeBaseConfig(&hhrtim1, HRTIM_TIMERINDEX_MASTER, &pTimeBaseCfg) != HAL_OK)
{
Error_Handler();
}
pTimerCfg.InterruptRequests = HRTIM_MASTER_IT_NONE;
pTimerCfg.DMARequests = HRTIM_MASTER_DMA_NONE;
pTimerCfg.DMASrcAddress = 0x0000;
pTimerCfg.DMADstAddress = 0x0000;
pTimerCfg.DMASize = 0x1;
pTimerCfg.HalfModeEnable = HRTIM_HALFMODE_DISABLED;
pTimerCfg.InterleavedMode = HRTIM_INTERLEAVED_MODE_DISABLED;
pTimerCfg.StartOnSync = HRTIM_SYNCSTART_DISABLED;
pTimerCfg.ResetOnSync = HRTIM_SYNCRESET_DISABLED;
pTimerCfg.DACSynchro = HRTIM_DACSYNC_NONE;
pTimerCfg.PreloadEnable = HRTIM_PRELOAD_DISABLED;
pTimerCfg.UpdateGating = HRTIM_UPDATEGATING_INDEPENDENT;
pTimerCfg.BurstMode = HRTIM_TIMERBURSTMODE_MAINTAINCLOCK;
pTimerCfg.RepetitionUpdate = HRTIM_UPDATEONREPETITION_DISABLED;
pTimerCfg.ReSyncUpdate = HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL;
if (HAL_HRTIM_WaveformTimerConfig(&hhrtim1, HRTIM_TIMERINDEX_MASTER, &pTimerCfg) != HAL_OK)
{
Error_Handler();
}
if (HAL_HRTIM_TimeBaseConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pTimeBaseCfg) != HAL_OK)
{
Error_Handler();
}
pTimerCtl.UpDownMode = HRTIM_TIMERUPDOWNMODE_UP;
pTimerCtl.DualChannelDacEnable = HRTIM_TIMER_DCDE_DISABLED;
if (HAL_HRTIM_WaveformTimerControl(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pTimerCtl) != HAL_OK)
{
Error_Handler();
}
pTimerCfg.InterruptRequests = HRTIM_TIM_IT_NONE;
pTimerCfg.DMARequests = HRTIM_TIM_DMA_NONE;
pTimerCfg.PushPull = HRTIM_TIMPUSHPULLMODE_DISABLED;
pTimerCfg.FaultEnable = HRTIM_TIMFAULTENABLE_NONE;
pTimerCfg.FaultLock = HRTIM_TIMFAULTLOCK_READWRITE;
pTimerCfg.DeadTimeInsertion = HRTIM_TIMDEADTIMEINSERTION_DISABLED;
pTimerCfg.DelayedProtectionMode = HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED;
pTimerCfg.UpdateTrigger = HRTIM_TIMUPDATETRIGGER_NONE;
pTimerCfg.ResetTrigger = HRTIM_TIMRESETTRIGGER_NONE;
pTimerCfg.ResetUpdate = HRTIM_TIMUPDATEONRESET_DISABLED;
if (HAL_HRTIM_WaveformTimerConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pTimerCfg) != HAL_OK)
{
Error_Handler();
}
if (HAL_HRTIM_WaveformTimerConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pTimerCfg) != HAL_OK)
{
Error_Handler();
}
pOutputCfg.Polarity = HRTIM_OUTPUTPOLARITY_HIGH;
pOutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
pOutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
pOutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
pOutputCfg.IdleLevel = HRTIM_OUTPUTIDLELEVEL_INACTIVE;
pOutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
pOutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
pOutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, HRTIM_OUTPUT_TA1, &pOutputCfg) != HAL_OK)
{
Error_Handler();
}
if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, HRTIM_OUTPUT_TB1, &pOutputCfg) != HAL_OK)
{
Error_Handler();
}
if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, HRTIM_OUTPUT_TA2, &pOutputCfg) != HAL_OK)
{
Error_Handler();
}
if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, HRTIM_OUTPUT_TB2, &pOutputCfg) != HAL_OK)
{
Error_Handler();
}
if (HAL_HRTIM_TimeBaseConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pTimeBaseCfg) != HAL_OK)
{
Error_Handler();
}
if (HAL_HRTIM_WaveformTimerControl(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pTimerCtl) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN HRTIM1_Init 2 */
/* USER CODE END HRTIM1_Init 2 */
HAL_HRTIM_MspPostInit(&hhrtim1);
}
/**
* @brief TIM1 Initialization Function
* @param None
@@ -251,6 +712,54 @@ static void MX_TIM1_Init(void)
}
/**
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
/* USER CODE BEGIN USART1_Init 0 */
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
huart1.Init.BaudRate = 115200;
huart1.Init.WordLength = UART_WORDLENGTH_8B;
huart1.Init.StopBits = UART_STOPBITS_1;
huart1.Init.Parity = UART_PARITY_NONE;
huart1.Init.Mode = UART_MODE_TX_RX;
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
if (HAL_UART_Init(&huart1) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
{
Error_Handler();
}
if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
{
Error_Handler();
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
/**
* @brief GPIO Initialization Function
* @param None
@@ -264,6 +773,7 @@ static void MX_GPIO_Init(void)
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
__HAL_RCC_GPIOA_CLK_ENABLE();
/* USER CODE BEGIN MX_GPIO_Init_2 */

444
code/Core/Src/stm32g4xx_hal_msp.c
View File

@@ -57,6 +57,8 @@
/* USER CODE BEGIN 0 */
/* USER CODE END 0 */
void HAL_HRTIM_MspPostInit(HRTIM_HandleTypeDef *hhrtim);
/**
* Initializes the Global MSP.
*/
@@ -89,6 +91,231 @@ void HAL_MspInit(void)
/* USER CODE END MspInit 1 */
}
static uint32_t HAL_RCC_ADC345_CLK_ENABLED=0;
/**
* @brief ADC MSP Initialization
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(hadc->Instance==ADC3)
{
/* USER CODE BEGIN ADC3_MspInit 0 */
/* USER CODE END ADC3_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC345;
PeriphClkInit.Adc345ClockSelection = RCC_ADC345CLKSOURCE_SYSCLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
HAL_RCC_ADC345_CLK_ENABLED++;
if(HAL_RCC_ADC345_CLK_ENABLED==1){
__HAL_RCC_ADC345_CLK_ENABLE();
}
__HAL_RCC_GPIOB_CLK_ENABLE();
/**ADC3 GPIO Configuration
PB13 ------> ADC3_IN5
*/
GPIO_InitStruct.Pin = GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN ADC3_MspInit 1 */
/* USER CODE END ADC3_MspInit 1 */
}
else if(hadc->Instance==ADC4)
{
/* USER CODE BEGIN ADC4_MspInit 0 */
/* USER CODE END ADC4_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC345;
PeriphClkInit.Adc345ClockSelection = RCC_ADC345CLKSOURCE_SYSCLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
HAL_RCC_ADC345_CLK_ENABLED++;
if(HAL_RCC_ADC345_CLK_ENABLED==1){
__HAL_RCC_ADC345_CLK_ENABLE();
}
__HAL_RCC_GPIOB_CLK_ENABLE();
/**ADC4 GPIO Configuration
PB14 ------> ADC4_IN4
*/
GPIO_InitStruct.Pin = GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN ADC4_MspInit 1 */
/* USER CODE END ADC4_MspInit 1 */
}
}
/**
* @brief ADC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
{
if(hadc->Instance==ADC3)
{
/* USER CODE BEGIN ADC3_MspDeInit 0 */
/* USER CODE END ADC3_MspDeInit 0 */
/* Peripheral clock disable */
HAL_RCC_ADC345_CLK_ENABLED--;
if(HAL_RCC_ADC345_CLK_ENABLED==0){
__HAL_RCC_ADC345_CLK_DISABLE();
}
/**ADC3 GPIO Configuration
PB13 ------> ADC3_IN5
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
/* USER CODE BEGIN ADC3_MspDeInit 1 */
/* USER CODE END ADC3_MspDeInit 1 */
}
else if(hadc->Instance==ADC4)
{
/* USER CODE BEGIN ADC4_MspDeInit 0 */
/* USER CODE END ADC4_MspDeInit 0 */
/* Peripheral clock disable */
HAL_RCC_ADC345_CLK_ENABLED--;
if(HAL_RCC_ADC345_CLK_ENABLED==0){
__HAL_RCC_ADC345_CLK_DISABLE();
}
/**ADC4 GPIO Configuration
PB14 ------> ADC4_IN4
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14);
/* USER CODE BEGIN ADC4_MspDeInit 1 */
/* USER CODE END ADC4_MspDeInit 1 */
}
}
/**
* @brief COMP MSP Initialization
* This function configures the hardware resources used in this example
* @param hcomp: COMP handle pointer
* @retval None
*/
void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hcomp->Instance==COMP5)
{
/* USER CODE BEGIN COMP5_MspInit 0 */
/* USER CODE END COMP5_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
/**COMP5 GPIO Configuration
PB13 ------> COMP5_INP
*/
GPIO_InitStruct.Pin = GPIO_PIN_13;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN COMP5_MspInit 1 */
/* USER CODE END COMP5_MspInit 1 */
}
else if(hcomp->Instance==COMP7)
{
/* USER CODE BEGIN COMP7_MspInit 0 */
/* USER CODE END COMP7_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
/**COMP7 GPIO Configuration
PB14 ------> COMP7_INP
*/
GPIO_InitStruct.Pin = GPIO_PIN_14;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN COMP7_MspInit 1 */
/* USER CODE END COMP7_MspInit 1 */
}
}
/**
* @brief COMP MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hcomp: COMP handle pointer
* @retval None
*/
void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp)
{
if(hcomp->Instance==COMP5)
{
/* USER CODE BEGIN COMP5_MspDeInit 0 */
/* USER CODE END COMP5_MspDeInit 0 */
/**COMP5 GPIO Configuration
PB13 ------> COMP5_INP
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
/* USER CODE BEGIN COMP5_MspDeInit 1 */
/* USER CODE END COMP5_MspDeInit 1 */
}
else if(hcomp->Instance==COMP7)
{
/* USER CODE BEGIN COMP7_MspDeInit 0 */
/* USER CODE END COMP7_MspDeInit 0 */
/**COMP7 GPIO Configuration
PB14 ------> COMP7_INP
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14);
/* USER CODE BEGIN COMP7_MspDeInit 1 */
/* USER CODE END COMP7_MspDeInit 1 */
}
}
/**
* @brief CORDIC MSP Initialization
* This function configures the hardware resources used in this example
@@ -134,6 +361,72 @@ void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef* hcordic)
}
/**
* @brief DAC MSP Initialization
* This function configures the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
if(hdac->Instance==DAC1)
{
/* USER CODE BEGIN DAC1_MspInit 0 */
/* USER CODE END DAC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DAC1_CLK_ENABLE();
/* USER CODE BEGIN DAC1_MspInit 1 */
/* USER CODE END DAC1_MspInit 1 */
}
else if(hdac->Instance==DAC4)
{
/* USER CODE BEGIN DAC4_MspInit 0 */
/* USER CODE END DAC4_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DAC4_CLK_ENABLE();
/* USER CODE BEGIN DAC4_MspInit 1 */
/* USER CODE END DAC4_MspInit 1 */
}
}
/**
* @brief DAC MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
{
if(hdac->Instance==DAC1)
{
/* USER CODE BEGIN DAC1_MspDeInit 0 */
/* USER CODE END DAC1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_DAC1_CLK_DISABLE();
/* USER CODE BEGIN DAC1_MspDeInit 1 */
/* USER CODE END DAC1_MspDeInit 1 */
}
else if(hdac->Instance==DAC4)
{
/* USER CODE BEGIN DAC4_MspDeInit 0 */
/* USER CODE END DAC4_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_DAC4_CLK_DISABLE();
/* USER CODE BEGIN DAC4_MspDeInit 1 */
/* USER CODE END DAC4_MspDeInit 1 */
}
}
/**
* @brief FMAC MSP Initialization
* This function configures the hardware resources used in this example
@@ -179,6 +472,80 @@ void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef* hfmac)
}
/**
* @brief HRTIM MSP Initialization
* This function configures the hardware resources used in this example
* @param hhrtim: HRTIM handle pointer
* @retval None
*/
void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef* hhrtim)
{
if(hhrtim->Instance==HRTIM1)
{
/* USER CODE BEGIN HRTIM1_MspInit 0 */
/* USER CODE END HRTIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_HRTIM1_CLK_ENABLE();
/* USER CODE BEGIN HRTIM1_MspInit 1 */
/* USER CODE END HRTIM1_MspInit 1 */
}
}
void HAL_HRTIM_MspPostInit(HRTIM_HandleTypeDef* hhrtim)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
if(hhrtim->Instance==HRTIM1)
{
/* USER CODE BEGIN HRTIM1_MspPostInit 0 */
/* USER CODE END HRTIM1_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
/**HRTIM1 GPIO Configuration
PA8 ------> HRTIM1_CHA1
PA9 ------> HRTIM1_CHA2
PA10 ------> HRTIM1_CHB1
PA11 ------> HRTIM1_CHB2
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF13_HRTIM1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
/* USER CODE BEGIN HRTIM1_MspPostInit 1 */
/* USER CODE END HRTIM1_MspPostInit 1 */
}
}
/**
* @brief HRTIM MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param hhrtim: HRTIM handle pointer
* @retval None
*/
void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef* hhrtim)
{
if(hhrtim->Instance==HRTIM1)
{
/* USER CODE BEGIN HRTIM1_MspDeInit 0 */
/* USER CODE END HRTIM1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_HRTIM1_CLK_DISABLE();
/* USER CODE BEGIN HRTIM1_MspDeInit 1 */
/* USER CODE END HRTIM1_MspDeInit 1 */
}
}
/**
* @brief TIM_Base MSP Initialization
* This function configures the hardware resources used in this example
@@ -224,6 +591,83 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
}
/**
* @brief UART MSP Initialization
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
GPIO_InitTypeDef GPIO_InitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
if(huart->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspInit 0 */
/* USER CODE END USART1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
{
Error_Handler();
}
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
__HAL_RCC_GPIOB_CLK_ENABLE();
/**USART1 GPIO Configuration
PB6 ------> USART1_TX
PB7 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
/* USER CODE BEGIN USART1_MspInit 1 */
/* USER CODE END USART1_MspInit 1 */
}
}
/**
* @brief UART MSP De-Initialization
* This function freeze the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
{
if(huart->Instance==USART1)
{
/* USER CODE BEGIN USART1_MspDeInit 0 */
/* USER CODE END USART1_MspDeInit 0 */
/* Peripheral clock disable */
__HAL_RCC_USART1_CLK_DISABLE();
/**USART1 GPIO Configuration
PB6 ------> USART1_TX
PB7 ------> USART1_RX
*/
HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
/* USER CODE BEGIN USART1_MspDeInit 1 */
/* USER CODE END USART1_MspDeInit 1 */
}
}
/* USER CODE BEGIN 1 */
/* USER CODE END 1 */

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/**
******************************************************************************
* @file stm32g4xx_hal_dac.h
* @author MCD Application Team
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_DAC_H
#define STM32G4xx_HAL_DAC_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
#if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
/** @addtogroup DAC
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Types DAC Exported Types
* @{
*/
/**
* @brief HAL State structures definition
*/
typedef enum
{
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
} HAL_DAC_StateTypeDef;
/**
* @brief DAC handle Structure definition
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
typedef struct __DAC_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
{
DAC_TypeDef *Instance; /*!< Register base address */
__IO HAL_DAC_StateTypeDef State; /*!< DAC communication state */
HAL_LockTypeDef Lock; /*!< DAC locking object */
DMA_HandleTypeDef *DMA_Handle1; /*!< Pointer DMA handler for channel 1 */
DMA_HandleTypeDef *DMA_Handle2; /*!< Pointer DMA handler for channel 2 */
__IO uint32_t ErrorCode; /*!< DAC Error code */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
} DAC_HandleTypeDef;
/**
* @brief DAC Configuration sample and hold Channel structure definition
*/
typedef struct
{
uint32_t DAC_SampleTime ; /*!< Specifies the Sample time for the selected channel.
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
uint32_t DAC_HoldTime ; /*!< Specifies the hold time for the selected channel
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
uint32_t DAC_RefreshTime ; /*!< Specifies the refresh time for the selected channel
This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
} DAC_SampleAndHoldConfTypeDef;
/**
* @brief DAC Configuration regular Channel structure definition
*/
typedef struct
{
uint32_t DAC_HighFrequency; /*!< Specifies the frequency interface mode
This parameter can be a value of @ref DAC_HighFrequency */
FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel.
This parameter can be ENABLE or DISABLE */
FunctionalState DAC_SignedFormat; /*!< Specifies if signed format should be used or not for the selected channel.
This parameter can be ENABLE or DISABLE */
uint32_t DAC_SampleAndHold; /*!< Specifies whether the DAC mode.
This parameter can be a value of @ref DAC_SampleAndHold */
uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection.
Note: In case of sawtooth wave generation, this
trigger corresponds to the reset trigger. */
uint32_t DAC_Trigger2; /*!< Specifies the external secondary trigger for the selected DAC channel.
This parameter can be a value of @ref DAC_trigger_selection.
Note: In case of sawtooth wave generation, this
trigger corresponds to the step trigger.*/
uint32_t DAC_OutputBuffer; /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
This parameter can be a value of @ref DAC_output_buffer */
uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral.
This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
uint32_t DAC_UserTrimming; /*!< Specifies the trimming mode
This parameter must be a value of @ref DAC_UserTrimming
DAC_UserTrimming is either factory or user trimming */
uint32_t DAC_TrimmingValue; /*!< Specifies the offset trimming value
i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
DAC_SampleAndHoldConfTypeDef DAC_SampleAndHoldConfig; /*!< Sample and Hold settings */
} DAC_ChannelConfTypeDef;
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/**
* @brief HAL DAC Callback ID enumeration definition
*/
typedef enum
{
HAL_DAC_CH1_COMPLETE_CB_ID = 0x00U, /*!< DAC CH1 Complete Callback ID */
HAL_DAC_CH1_HALF_COMPLETE_CB_ID = 0x01U, /*!< DAC CH1 half Complete Callback ID */
HAL_DAC_CH1_ERROR_ID = 0x02U, /*!< DAC CH1 error Callback ID */
HAL_DAC_CH1_UNDERRUN_CB_ID = 0x03U, /*!< DAC CH1 underrun Callback ID */
HAL_DAC_CH2_COMPLETE_CB_ID = 0x04U, /*!< DAC CH2 Complete Callback ID */
HAL_DAC_CH2_HALF_COMPLETE_CB_ID = 0x05U, /*!< DAC CH2 half Complete Callback ID */
HAL_DAC_CH2_ERROR_ID = 0x06U, /*!< DAC CH2 error Callback ID */
HAL_DAC_CH2_UNDERRUN_CB_ID = 0x07U, /*!< DAC CH2 underrun Callback ID */
HAL_DAC_MSPINIT_CB_ID = 0x08U, /*!< DAC MspInit Callback ID */
HAL_DAC_MSPDEINIT_CB_ID = 0x09U, /*!< DAC MspDeInit Callback ID */
HAL_DAC_ALL_CB_ID = 0x0AU /*!< DAC All ID */
} HAL_DAC_CallbackIDTypeDef;
/**
* @brief HAL DAC Callback pointer definition
*/
typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DAC_Exported_Constants DAC Exported Constants
* @{
*/
/** @defgroup DAC_Error_Code DAC Error Code
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DMA underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DMA underrun error */
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
#define HAL_DAC_ERROR_TIMEOUT 0x08U /*!< Timeout error */
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define HAL_DAC_ERROR_INVALID_CALLBACK 0x10U /*!< Invalid callback error */
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @defgroup DAC_trigger_selection DAC trigger selection
* @{
*/
#define DAC_TRIGGER_NONE 0x00000000UL /*!< DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
#define DAC_TRIGGER_SOFTWARE ( DAC_CR_TEN1) /*!< DAC (all) conversion started by software trigger for DAC channel */
#define DAC_TRIGGER_T1_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: TIM1 TRGO selected as external conversion trigger for DAC channel. */
#define DAC_TRIGGER_T8_TRGO ( DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1/2/4: TIM8 TRGO selected as external conversion trigger for DAC channel. Refer to device datasheet for DACx availability. */
#define DAC_TRIGGER_T7_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): TIM7 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T15_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM15 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T2_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM4 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_EXT_IT9 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line9 event selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger */
#define DAC_TRIGGER_EXT_IT10 ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): EXTI Line10 event selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger */
#define DAC_TRIGGER_T6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM6 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T3_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TEN1) /*!< DAC (all): TIM3 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_HRTIM_RST_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_STEP_TRG1 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_RST_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_STEP_TRG2 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_RST_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_STEP_TRG3 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_RST_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_STEP_TRG4 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_RST_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_STEP_TRG5 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_RST_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_STEP_TRG6 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_TRG01 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1&4: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
#define DAC_TRIGGER_HRTIM_TRG02 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC2: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
#define DAC_TRIGGER_HRTIM_TRG03 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
/**
* @}
*/
/** @defgroup DAC_output_buffer DAC output buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE 0x00000000U
#define DAC_OUTPUTBUFFER_DISABLE (DAC_MCR_MODE1_1)
/**
* @}
*/
/** @defgroup DAC_Channel_selection DAC Channel selection
* @{
*/
#define DAC_CHANNEL_1 0x00000000U
#define DAC_CHANNEL_2 0x00000010U
/**
* @}
*/
/** @defgroup DAC_data_alignment DAC data alignment
* @{
*/
#define DAC_ALIGN_12B_R 0x00000000U
#define DAC_ALIGN_12B_L 0x00000004U
#define DAC_ALIGN_8B_R 0x00000008U
/**
* @}
*/
/** @defgroup DAC_flags_definition DAC flags definition
* @{
*/
#define DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1)
#define DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2)
#define DAC_FLAG_DAC1RDY (DAC_SR_DAC1RDY)
#define DAC_FLAG_DAC2RDY (DAC_SR_DAC2RDY)
/**
* @}
*/
/** @defgroup DAC_IT_definition DAC IT definition
* @{
*/
#define DAC_IT_DMAUDR1 (DAC_SR_DMAUDR1)
#define DAC_IT_DMAUDR2 (DAC_SR_DMAUDR2)
/**
* @}
*/
/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
* @{
*/
#define DAC_CHIPCONNECT_EXTERNAL (1UL << 0) /*!< DAC channel output is connected to an external pin.*/
#define DAC_CHIPCONNECT_INTERNAL (1UL << 1) /*!< DAC channel output is connected to on-chip peripherals (via
internal paths) and to an external pin. */
#define DAC_CHIPCONNECT_BOTH (1UL << 2) /*!< DAC channel output is connected to on-chip peripherals (via
internal paths) and to an external pin.
Note: this connection is not available in mode normal
with buffer disabled. */
/**
* @}
*/
/** @defgroup DAC_UserTrimming DAC User Trimming
* @{
*/
#define DAC_TRIMMING_FACTORY (0x00000000UL) /*!< Factory trimming */
#define DAC_TRIMMING_USER (0x00000001UL) /*!< User trimming */
/**
* @}
*/
/** @defgroup DAC_SampleAndHold DAC power mode
* @{
*/
#define DAC_SAMPLEANDHOLD_DISABLE (0x00000000UL)
#define DAC_SAMPLEANDHOLD_ENABLE (DAC_MCR_MODE1_2)
/**
* @}
*/
/** @defgroup DAC_HighFrequency DAC high frequency interface mode
* @{
*/
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE 0x00000000UL /*!< High frequency interface mode disabled */
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ (DAC_MCR_HFSEL_0) /*!< High frequency interface mode compatible to AHB>80MHz enabled */
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ (DAC_MCR_HFSEL_1) /*!< High frequency interface mode compatible to AHB>160MHz enabled */
#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC 0x00000002UL /*!< High frequency interface mode automatic */
/**
* @}
*/
/**
* @}
*/
/* Delay for DAC channel voltage settling time from DAC channel startup */
/* (transition from disable to enable). */
/* Note: DAC channel startup time depends on board application environment: */
/* impedance connected to DAC channel output. */
/* The delay below is specified under conditions: */
/* - voltage maximum transition (lowest to highest value) */
/* - until voltage reaches final value +-1LSB */
/* - DAC channel output buffer enabled */
/* - load impedance of 5kOhm (min), 50pF (max) */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tWAKEUP"). */
/* Unit: us */
#define DAC_DELAY_STARTUP_US (15UL) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
/* Exported macro ------------------------------------------------------------*/
/** @defgroup DAC_Exported_Macros DAC Exported Macros
* @{
*/
/** @brief Reset DAC handle state.
* @param __HANDLE__ specifies the DAC handle.
* @retval None
*/
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do { \
(__HANDLE__)->State = HAL_DAC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \
} while(0)
#else
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/** @brief Enable the DAC channel.
* @param __HANDLE__ specifies the DAC handle.
* @param __DAC_Channel__ specifies the DAC channel
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
/** @brief Disable the DAC channel.
* @param __HANDLE__ specifies the DAC handle
* @param __DAC_Channel__ specifies the DAC channel.
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
/** @brief Set DHR12R1 alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment.
* @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
/** @brief Enable the DAC interrupt.
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/** @brief Disable the DAC interrupt.
* @param __HANDLE__ specifies the DAC handle
* @param __INTERRUPT__ specifies the DAC interrupt.
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/** @brief Check whether the specified DAC interrupt source is enabled or not.
* @param __HANDLE__ DAC handle
* @param __INTERRUPT__ DAC interrupt source to check
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval State of interruption (SET or RESET)
*/
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
& (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to get.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
* @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag
* @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag.
* @param __HANDLE__ specifies the DAC handle.
* @param __FLAG__ specifies the DAC flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
* @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
*
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval None
*/
#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DAC_Private_Macros DAC Private Macros
* @{
*/
#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
((STATE) == DAC_OUTPUTBUFFER_DISABLE))
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
#define IS_DAC_CHANNEL(DACX, CHANNEL) \
(((DACX) == DAC2) ? \
((CHANNEL) == DAC_CHANNEL_1) \
: \
(((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2)))
#elif defined(STM32G411xB) || defined(STM32G411xC)
#define IS_DAC_CHANNEL(DACX, CHANNEL) \
(((DACX) == DAC1) ? \
((CHANNEL) == DAC_CHANNEL_1) \
: \
(((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2)))
#else
#define IS_DAC_CHANNEL(DACX, CHANNEL) \
(((CHANNEL) == DAC_CHANNEL_1) || \
((CHANNEL) == DAC_CHANNEL_2))
#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx */
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
((ALIGN) == DAC_ALIGN_12B_L) || \
((ALIGN) == DAC_ALIGN_8B_R))
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
#define IS_DAC_REFRESHTIME(TIME) ((TIME) <= 0x000000FFUL)
/**
* @}
*/
/* Include DAC HAL Extended module */
#include "stm32g4xx_hal_dac_ex.h"
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DAC_Exported_Functions
* @{
*/
/** @addtogroup DAC_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions *****************************/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
uint32_t Alignment);
HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* DAC callback registering/unregistering */
HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
pDAC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
/**
* @}
*/
/** @addtogroup DAC_Exported_Functions_Group4
* @{
*/
/* Peripheral State and Error functions ***************************************/
HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
/**
* @}
*/
/**
* @}
*/
/** @defgroup DAC_Private_Functions DAC Private Functions
* @{
*/
void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
#endif /* DAC1 || DAC2 || DAC3 || DAC4 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_DAC_H */

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/**
******************************************************************************
* @file stm32g4xx_hal_dac_ex.h
* @author MCD Application Team
* @brief Header file of DAC HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_DAC_EX_H
#define STM32G4xx_HAL_DAC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
#if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
/** @addtogroup DACEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/**
* @brief HAL State structures definition
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
* @{
*/
/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 0x00000000UL /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TRIANGLEAMPLITUDE_1 0x00000000UL /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
#define DAC_TRIANGLEAMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 7 */
#define DAC_TRIANGLEAMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
#define DAC_TRIANGLEAMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Select max triangle amplitude of 31 */
#define DAC_TRIANGLEAMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
#define DAC_TRIANGLEAMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 127 */
#define DAC_TRIANGLEAMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
#define DAC_TRIANGLEAMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Select max triangle amplitude of 511 */
#define DAC_TRIANGLEAMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
#define DAC_TRIANGLEAMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Select max triangle amplitude of 2047 */
#define DAC_TRIANGLEAMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
/**
* @}
*/
/** @defgroup DACEx_SawtoothPolarityMode DAC Sawtooth polarity mode
* @{
*/
#define DAC_SAWTOOTH_POLARITY_DECREMENT 0x00000000UL /*!< Sawtooth wave generation, polarity is decrement */
#define DAC_SAWTOOTH_POLARITY_INCREMENT (DAC_STR1_STDIR1) /*!< Sawtooth wave generation, polarity is increment */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DACEx_Private_Macros DACEx Private Macros
* @{
*/
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx)
#define IS_DAC_TRIGGER(DACX, TRIGGER) \
(((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG1) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG2) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG3) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG4) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG5) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG6) || \
(((DACX) == DAC1) && \
(((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01)) \
) || \
(((DACX) == DAC2) && \
(((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_TRG02)) \
) || \
(((DACX) == DAC3) && \
(((TRIGGER) == DAC_TRIGGER_T1_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_TRG03)) \
) || \
(((DACX) == DAC4) && \
(((TRIGGER) == DAC_TRIGGER_T8_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01)) \
) \
)
#else
#define IS_DAC_TRIGGER(DACX, TRIGGER) \
(((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
(((DACX) == DAC3) ? \
((TRIGGER) == DAC_TRIGGER_T1_TRGO) \
: ((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
) \
)
#endif /* STM32G414xx || STM32G474xx || STM32G484xx */
#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx)
#define IS_DAC_TRIGGER2(DACX, TRIGGER) \
(((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT10) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG1) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG2) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG3) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG4) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG5) || \
((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG6) || \
(((DACX) == DAC1) && \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
) || \
(((DACX) == DAC2) && \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
) || \
(((DACX) == DAC3) && \
((TRIGGER) == DAC_TRIGGER_T1_TRGO) \
) || \
(((DACX) == DAC4) && \
((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
) \
)
#else
#define IS_DAC_TRIGGER2(DACX, TRIGGER) \
(((TRIGGER) == DAC_TRIGGER_NONE) || \
((TRIGGER) == DAC_TRIGGER_SOFTWARE) || \
((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T15_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
((TRIGGER) == DAC_TRIGGER_EXT_IT10) || \
((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
((TRIGGER) == DAC_TRIGGER_T3_TRGO) || \
(((DACX) == DAC3) ? \
((TRIGGER) == DAC_TRIGGER_T1_TRGO) \
:((TRIGGER) == DAC_TRIGGER_T8_TRGO) \
) \
)
#endif /* STM32G414xx || STM32G474xx || STM32G484xx */
#define IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE) || \
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ) || \
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ) || \
((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC))
#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
#define IS_DAC_HOLDTIME(TIME) ((TIME) <= 0x000003FFU)
#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
((CONNECT) == DAC_CHIPCONNECT_BOTH))
#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
((TRIMMING) == DAC_TRIMMING_USER))
#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
#define IS_DAC_SAWTOOTH_POLARITY(POLARITY) (((POLARITY) == DAC_SAWTOOTH_POLARITY_DECREMENT) || \
((POLARITY) == DAC_SAWTOOTH_POLARITY_INCREMENT))
#define IS_DAC_RESET_DATA(DATA) ((DATA) <= 0x00000FFFUL)
#define IS_DAC_STEP_DATA(DATA) ((DATA) <= 0x0000FFFFUL)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/* Extended features functions ***********************************************/
/** @addtogroup DACEx_Exported_Functions
* @{
*/
/** @addtogroup DACEx_Exported_Functions_Group2
* @{
*/
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity,
uint32_t ResetData, uint32_t StepData);
HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
const uint32_t *pData, uint32_t Length, uint32_t Alignment);
HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
/**
* @}
*/
/** @addtogroup DACEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
uint32_t NewTrimmingValue);
uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel);
/**
* @}
*/
/**
* @}
*/
/** @addtogroup DACEx_Private_Functions
* @{
*/
/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
/* are called by HAL_DAC_Start_DMA */
void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
/**
* @}
*/
/**
* @}
*/
#endif /* DAC1 || DAC2 || DAC3 || DAC4 */
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_DAC_EX_H */

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/**
******************************************************************************
* @file stm32g4xx_hal_uart_ex.h
* @author MCD Application Team
* @brief Header file of UART HAL Extended module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_HAL_UART_EX_H
#define STM32G4xx_HAL_UART_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx_hal_def.h"
/** @addtogroup STM32G4xx_HAL_Driver
* @{
*/
/** @addtogroup UARTEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
* @{
*/
/**
* @brief UART wake up from stop mode parameters
*/
typedef struct
{
uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
be filled up. */
uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long.
This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */
uint8_t Address; /*!< UART/USART node address (7-bit long max). */
} UART_WakeUpTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
* @{
*/
/** @defgroup UARTEx_Word_Length UARTEx Word Length
* @{
*/
#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */
#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */
#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */
/**
* @}
*/
/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
* @{
*/
#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */
#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */
/**
* @}
*/
/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
* @brief UART FIFO mode
* @{
*/
#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */
/**
* @}
*/
/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
* @brief UART TXFIFO threshold level
* @{
*/
#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */
#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */
#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */
#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */
#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */
/**
* @}
*/
/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
* @brief UART RXFIFO threshold level
* @{
*/
#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */
#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */
#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */
#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */
#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup UARTEx_Exported_Functions
* @{
*/
/** @addtogroup UARTEx_Exported_Functions_Group1
* @{
*/
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
uint32_t DeassertionTime);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group2
* @{
*/
void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
/**
* @}
*/
/** @addtogroup UARTEx_Exported_Functions_Group3
* @{
*/
/* Peripheral Control functions **********************************************/
HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
uint32_t Timeout);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
/**
* @}
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
* @{
*/
/** @brief Report the UART clock source.
* @param __HANDLE__ specifies the UART Handle.
* @param __CLOCKSOURCE__ output variable.
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#if defined(UART5) && defined(USART3)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART5CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART5CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART5CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined(UART5) && !defined(USART3)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART5) \
{ \
switch(__HAL_RCC_GET_UART5_SOURCE()) \
{ \
case RCC_UART5CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART5CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART5CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART5CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined(UART4) && defined(USART3)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined(UART4) && !defined(USART3)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == UART4) \
{ \
switch(__HAL_RCC_GET_UART4_SOURCE()) \
{ \
case RCC_UART4CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_UART4CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_UART4CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_UART4CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#elif defined(USART3)
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART3) \
{ \
switch(__HAL_RCC_GET_USART3_SOURCE()) \
{ \
case RCC_USART3CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART3CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART3CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART3CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#else
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
do { \
if((__HANDLE__)->Instance == USART1) \
{ \
switch(__HAL_RCC_GET_USART1_SOURCE()) \
{ \
case RCC_USART1CLKSOURCE_PCLK2: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2; \
break; \
case RCC_USART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == USART2) \
{ \
switch(__HAL_RCC_GET_USART2_SOURCE()) \
{ \
case RCC_USART2CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_USART2CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_USART2CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_USART2CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else if((__HANDLE__)->Instance == LPUART1) \
{ \
switch(__HAL_RCC_GET_LPUART1_SOURCE()) \
{ \
case RCC_LPUART1CLKSOURCE_PCLK1: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1; \
break; \
case RCC_LPUART1CLKSOURCE_HSI: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI; \
break; \
case RCC_LPUART1CLKSOURCE_SYSCLK: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK; \
break; \
case RCC_LPUART1CLKSOURCE_LSE: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE; \
break; \
default: \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
break; \
} \
} \
else \
{ \
(__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED; \
} \
} while(0U)
#endif /* UART5 && !USART3 */
/** @brief Report the UART mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
* @note If PCE = 1, the parity bit is not included in the data extracted
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
* @param __HANDLE__ specifies the UART Handle.
* @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
*/
#define UART_MASK_COMPUTATION(__HANDLE__) \
do { \
if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x01FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x00FFU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
} \
else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \
{ \
if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \
{ \
(__HANDLE__)->Mask = 0x007FU ; \
} \
else \
{ \
(__HANDLE__)->Mask = 0x003FU ; \
} \
} \
else \
{ \
(__HANDLE__)->Mask = 0x0000U; \
} \
} while(0U)
/**
* @brief Ensure that UART frame length is valid.
* @param __LENGTH__ UART frame length.
* @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
*/
#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
((__LENGTH__) == UART_WORDLENGTH_8B) || \
((__LENGTH__) == UART_WORDLENGTH_9B))
/**
* @brief Ensure that UART wake-up address length is valid.
* @param __ADDRESS__ UART wake-up address length.
* @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
*/
#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
/**
* @brief Ensure that UART TXFIFO threshold level is valid.
* @param __THRESHOLD__ UART TXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
/**
* @brief Ensure that UART RXFIFO threshold level is valid.
* @param __THRESHOLD__ UART RXFIFO threshold level.
* @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
*/
#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_HAL_UART_EX_H */

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/**
******************************************************************************
* @file stm32g4xx_ll_comp.h
* @author MCD Application Team
* @brief Header file of COMP LL module.
******************************************************************************
* @attention
*
* Copyright (c) 2019 STMicroelectronics.
* All rights reserved.
*
* This software is licensed under terms that can be found in the LICENSE file
* in the root directory of this software component.
* If no LICENSE file comes with this software, it is provided AS-IS.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef STM32G4xx_LL_COMP_H
#define STM32G4xx_LL_COMP_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32g4xx.h"
/** @addtogroup STM32G4xx_LL_Driver
* @{
*/
/** @defgroup COMP_LL COMP
* @{
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup COMP_LL_Private_Macros COMP Private Macros
* @{
*/
/**
* @}
*/
/* Exported types ------------------------------------------------------------*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
* @{
*/
/**
* @brief Structure definition of some features of COMP instance.
*/
typedef struct
{
uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input).
This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
This feature can be modified afterwards using unitary function
@ref LL_COMP_SetInputPlus(). */
uint32_t InputMinus; /*!< Set comparator input minus (inverting input).
This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
This feature can be modified afterwards using unitary function
@ref LL_COMP_SetInputMinus(). */
uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus.
This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
This feature can be modified afterwards using unitary function
@ref LL_COMP_SetInputHysteresis(). */
uint32_t OutputPolarity; /*!< Set comparator output polarity.
This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
This feature can be modified afterwards using unitary function
@ref LL_COMP_SetOutputPolarity(). */
uint32_t OutputBlankingSource; /*!< Set comparator blanking source.
This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
This feature can be modified afterwards using unitary function
@ref LL_COMP_SetOutputBlankingSource(). */
} LL_COMP_InitTypeDef;
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/* Exported constants --------------------------------------------------------*/
/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
* @{
*/
/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
* @{
*/
#define LL_COMP_INPUT_PLUS_IO1 (0x00000000UL) /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA7 for COMP2, pin PA0 for COMP3, pin PB0 for COMP4, pin PB13 for COMP5, pin PB11 for COMP6, pin PB14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_INPUT_PLUS_IO2 (COMP_CSR_INPSEL) /*!< Comparator input plus connected to IO2 (pin PB1 for COMP1, pin PA3 for COMP2, pin PC1 for COMP3, pin PE7 for COMP4, pin PD12 for COMP5, pin PD11 for COMP6, pin PD14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
/**
* @}
*/
/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
* @{
*/
#define LL_COMP_INPUT_MINUS_1_4VREFINT ( COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/4 VrefInt */
#define LL_COMP_INPUT_MINUS_1_2VREFINT ( COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 1/2 VrefInt */
#define LL_COMP_INPUT_MINUS_3_4VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_SCALEN | COMP_CSR_BRGEN) /*!< Comparator input minus connected to 3/4 VrefInt */
#define LL_COMP_INPUT_MINUS_VREFINT ( COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN ) /*!< Comparator input minus connected to VrefInt */
#define LL_COMP_INPUT_MINUS_DAC1_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 Channel 1 for COMP1/3/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_DAC1_CH2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC1 Channel 2 for COMP2/5. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_DAC2_CH1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to DAC2 Channel 1 for COMP6/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_DAC3_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC3 Channel 1 for COMP1/3. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_DAC3_CH2 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC3 Channel 2 for COMP2/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_DAC4_CH1 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC4 Channel 1 for COMP5/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_DAC4_CH2 (COMP_CSR_INMSEL_2 ) /*!< Comparator input minus connected to DAC4 Channel 2 for COMP6. Note: For COMPx & DACx instances availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_IO1 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 ) /*!< Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_INPUT_MINUS_IO2 (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0) /*!< Comparator input minus connected to IO2 (pin PA0 for COMP1, pin PA2 for COMP2, pin PC0 for COMP3, pin PB2 for COMP4, pin PD13 for COMP5, pin PB15 for COMP6, pin PB12 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
/**
* @}
*/
/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
* @{
*/
#define LL_COMP_HYSTERESIS_NONE (0x00000000UL) /*!< No hysteresis */
#define LL_COMP_HYSTERESIS_10MV ( COMP_CSR_HYST_0) /*!< Hysteresis level 10mV */
#define LL_COMP_HYSTERESIS_20MV ( COMP_CSR_HYST_1 ) /*!< Hysteresis level 20mV */
#define LL_COMP_HYSTERESIS_30MV ( COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 30mV */
#define LL_COMP_HYSTERESIS_40MV (COMP_CSR_HYST_2 ) /*!< Hysteresis level 40mV */
#define LL_COMP_HYSTERESIS_50MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_0) /*!< Hysteresis level 50mV */
#define LL_COMP_HYSTERESIS_60MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 ) /*!< Hysteresis level 60mV */
#define LL_COMP_HYSTERESIS_70MV (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 70mV */
#define LL_COMP_HYSTERESIS_LOW LL_COMP_HYSTERESIS_10MV /*!< Hysteresis level low */
#define LL_COMP_HYSTERESIS_MEDIUM LL_COMP_HYSTERESIS_40MV /*!< Hysteresis level medium */
#define LL_COMP_HYSTERESIS_HIGH LL_COMP_HYSTERESIS_70MV /*!< Hysteresis level high */
/**
* @}
*/
/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
* @{
*/
#define LL_COMP_OUTPUTPOL_NONINVERTED (0x00000000UL) /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
#define LL_COMP_OUTPUTPOL_INVERTED (COMP_CSR_POLARITY) /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
/**
* @}
*/
/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
* @{
*/
#define LL_COMP_BLANKINGSRC_NONE (0x00000000UL) /*!<Comparator output without blanking */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6 ( COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7 ( COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 ( COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2 ) /*!< Comparator output blanking source TIM15 OC3 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM20_OC5 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM20 OC5 (Common to all COMP instances). Note: For TIM20 instance availability, please refer to datasheet */
#define LL_COMP_BLANKINGSRC_TIM15_OC1 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 ) /*!< Comparator output blanking source TIM15 OC1 (Common to all COMP instances). */
#define LL_COMP_BLANKINGSRC_TIM4_OC3 (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0) /*!< Comparator output blanking source TIM4 OC3 (Common to all COMP instances). */
/**
* @}
*/
/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
* @{
*/
#define LL_COMP_OUTPUT_LEVEL_LOW (0x00000000UL) /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
#define LL_COMP_OUTPUT_LEVEL_HIGH (0x00000001UL) /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
/**
* @}
*/
/** @defgroup COMP_LL_EC_HW_DELAYS Definitions of COMP hardware constraints delays
* @note Only COMP peripheral HW delays are defined in COMP LL driver driver,
* not timeout values.
* For details on delays values, refer to descriptions in source code
* above each literal definition.
* @{
*/
/* Delay for comparator startup time. */
/* Note: Delay required to reach propagation delay specification. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART"). */
/* Unit: us */
#define LL_COMP_DELAY_STARTUP_US ( 5UL) /*!< Delay for COMP startup time */
/* Delay for comparator voltage scaler stabilization time. */
/* Note: Voltage scaler is used when selecting comparator input */
/* based on VrefInt: VrefInt or subdivision of VrefInt. */
/* Literal set to maximum value (refer to device datasheet, */
/* parameter "tSTART_SCALER"). */
/* Unit: us */
#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL) /*!< Delay for COMP voltage scaler stabilization time */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
* @{
*/
/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
* @{
*/
/**
* @brief Write a value in COMP register
* @param __INSTANCE__ comparator instance
* @param __REG__ Register to be written
* @param __VALUE__ Value to be written in the register
* @retval None
*/
#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
/**
* @brief Read a value in COMP register
* @param __INSTANCE__ comparator instance
* @param __REG__ Register to be read
* @retval Register value
*/
#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
/**
* @}
*/
/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
* @{
*/
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
* @{
*/
/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
* @{
*/
/**
* @brief Set comparator inputs minus (inverting) and plus (non-inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @note On this STM32 series, scaler bridge is configurable:
* to optimize power consumption, this function enables the
* voltage scaler bridge only when required
* (when selecting comparator input based on VrefInt: VrefInt or
* subdivision of VrefInt).
* - For scaler bridge power consumption values,
* refer to device datasheet, parameter "IDDA(SCALER)".
* - Voltage scaler requires a delay for voltage stabilization.
* Refer to device datasheet, parameter "tSTART_SCALER".
* - Scaler bridge is common for all comparator instances,
* therefore if at least one of the comparator instance
* is requiring the scaler bridge, it remains enabled.
* @rmtoll CSR INMSEL LL_COMP_ConfigInputs\n
* CSR INPSEL LL_COMP_ConfigInputs\n
* CSR BRGEN LL_COMP_ConfigInputs\n
* CSR SCALEN LL_COMP_ConfigInputs
* @param COMPx Comparator instance
* @param InputMinus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 (1,3,4)
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (2,5)
* @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (6,7)
* @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH1 (1,3)
* @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH2 (2,4)
* @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH1 (5,7)
* @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH2 (6)
* (a,b...) Only available for COMPa, COMPb...
* For COMPx & DACx instances availability, please refer to datasheet
* @arg @ref LL_COMP_INPUT_MINUS_IO1
* @arg @ref LL_COMP_INPUT_MINUS_IO2
* @param InputPlus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_PLUS_IO1
* @arg @ref LL_COMP_INPUT_PLUS_IO2
* @retval None
*/
__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
{
MODIFY_REG(COMPx->CSR,
COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN,
InputMinus | InputPlus);
}
/**
* @brief Set comparator input plus (non-inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @rmtoll CSR INPSEL LL_COMP_SetInputPlus
* @param COMPx Comparator instance
* @param InputPlus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_PLUS_IO1
* @arg @ref LL_COMP_INPUT_PLUS_IO2
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus);
}
/**
* @brief Get comparator input plus (non-inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @rmtoll CSR INPSEL LL_COMP_GetInputPlus
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_INPUT_PLUS_IO1
* @arg @ref LL_COMP_INPUT_PLUS_IO2
*/
__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
}
/**
* @brief Set comparator input minus (inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @note On this STM32 series, scaler bridge is configurable:
* to optimize power consumption, this function enables the
* voltage scaler bridge only when required
* (when selecting comparator input based on VrefInt: VrefInt or
* subdivision of VrefInt).
* - For scaler bridge power consumption values,
* refer to device datasheet, parameter "IDDA(SCALER)".
* - Voltage scaler requires a delay for voltage stabilization.
* Refer to device datasheet, parameter "tSTART_SCALER".
* - Scaler bridge is common for all comparator instances,
* therefore if at least one of the comparator instance
* is requiring the scaler bridge, it remains enabled.
* @rmtoll CSR INMSEL LL_COMP_SetInputMinus\n
* CSR BRGEN LL_COMP_SetInputMinus\n
* CSR SCALEN LL_COMP_SetInputMinus
* @param COMPx Comparator instance
* @param InputMinus This parameter can be one of the following values:
* @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 (1,3,4)
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (2,5)
* @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (6,7)
* @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH1 (1,3)
* @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH2 (2,4)
* @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH1 (5,7)
* @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH2 (6)
* (a,b...) Only available for COMPa, COMPb...
* For COMPx & DACx instances availability, please refer to datasheet
* @arg @ref LL_COMP_INPUT_MINUS_IO1
* @arg @ref LL_COMP_INPUT_MINUS_IO2
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
}
/**
* @brief Get comparator input minus (inverting).
* @note In case of comparator input selected to be connected to IO:
* GPIO pins are specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @rmtoll CSR INMSEL LL_COMP_GetInputMinus\n
* CSR BRGEN LL_COMP_GetInputMinus\n
* CSR SCALEN LL_COMP_GetInputMinus
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_VREFINT
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1 (1,3,4)
* @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 (2,5)
* @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1 (6,7)
* @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH1 (1,3)
* @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH2 (2,4)
* @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH1 (5,7)
* @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH2 (6)
* (a,b...) Only available for COMPa, COMPb...
* For COMPx & DACx instances availability, please refer to datasheet
* @arg @ref LL_COMP_INPUT_MINUS_IO1
* @arg @ref LL_COMP_INPUT_MINUS_IO2
*/
__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
}
/**
* @brief Set comparator instance hysteresis mode of the input minus (inverting input).
* @rmtoll CSR HYST LL_COMP_SetInputHysteresis
* @param COMPx Comparator instance
* @param InputHysteresis This parameter can be one of the following values:
* @arg @ref LL_COMP_HYSTERESIS_NONE
* @arg @ref LL_COMP_HYSTERESIS_10MV
* @arg @ref LL_COMP_HYSTERESIS_20MV
* @arg @ref LL_COMP_HYSTERESIS_30MV
* @arg @ref LL_COMP_HYSTERESIS_40MV
* @arg @ref LL_COMP_HYSTERESIS_50MV
* @arg @ref LL_COMP_HYSTERESIS_60MV
* @arg @ref LL_COMP_HYSTERESIS_70MV
* @arg @ref LL_COMP_HYSTERESIS_LOW
* @arg @ref LL_COMP_HYSTERESIS_MEDIUM
* @arg @ref LL_COMP_HYSTERESIS_HIGH
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis);
}
/**
* @brief Get comparator instance hysteresis mode of the minus (inverting) input.
* @rmtoll CSR HYST LL_COMP_GetInputHysteresis
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_HYSTERESIS_NONE
* @arg @ref LL_COMP_HYSTERESIS_10MV
* @arg @ref LL_COMP_HYSTERESIS_20MV
* @arg @ref LL_COMP_HYSTERESIS_30MV
* @arg @ref LL_COMP_HYSTERESIS_40MV
* @arg @ref LL_COMP_HYSTERESIS_50MV
* @arg @ref LL_COMP_HYSTERESIS_60MV
* @arg @ref LL_COMP_HYSTERESIS_70MV
*/
__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
}
/**
* @}
*/
/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
* @{
*/
/**
* @brief Set comparator instance output polarity.
* @rmtoll CSR POLARITY LL_COMP_SetOutputPolarity
* @param COMPx Comparator instance
* @param OutputPolarity This parameter can be one of the following values:
* @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
* @arg @ref LL_COMP_OUTPUTPOL_INVERTED
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity);
}
/**
* @brief Get comparator instance output polarity.
* @rmtoll CSR POLARITY LL_COMP_GetOutputPolarity
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
* @arg @ref LL_COMP_OUTPUTPOL_INVERTED
*/
__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
}
/**
* @brief Set comparator instance blanking source.
* @note Blanking source may be specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @note Availability of parameters of blanking source from timer
* depends on timers availability on the selected device.
* @rmtoll CSR BLANKING LL_COMP_SetOutputBlankingSource
* @param COMPx Comparator instance
* @param BlankingSource This parameter can be one of the following values:
* @arg @ref LL_COMP_BLANKINGSRC_NONE
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM20_OC5
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
* @arg @ref LL_COMP_BLANKINGSRC_TIM4_OC3
*
* On STM32G4 series, blanking sources are linked to COMP instance (except
* those without COMPx suffix that are common to all instances)
* Note: For COMPx & TIMx instances availability, please refer to datasheet
* @retval None
*/
__STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
{
MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKING, BlankingSource);
}
/**
* @brief Get comparator instance blanking source.
* @note Availability of parameters of blanking source from timer
* depends on timers availability on the selected device.
* @note Blanking source may be specific to each comparator instance.
* Refer to description of parameters or to reference manual.
* @rmtoll CSR BLANKING LL_COMP_GetOutputBlankingSource
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_BLANKINGSRC_NONE
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7
* @arg @ref LL_COMP_BLANKINGSRC_TIM20_OC5
* @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
* @arg @ref LL_COMP_BLANKINGSRC_TIM4_OC3
*
* On STM32G4 series, blanking sources are linked to COMP instance (except
* those without COMPx suffix that are common to all instances)
* Note: For COMPx & TIMx instances availability, please refer to datasheet
*/
__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING));
}
/**
* @}
*/
/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
* @{
*/
/**
* @brief Enable comparator instance.
* @note After enable from off state, comparator requires a delay
* to reach reach propagation delay specification.
* Refer to device datasheet, parameter "tSTART".
* @rmtoll CSR EN LL_COMP_Enable
* @param COMPx Comparator instance
* @retval None
*/
__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
{
SET_BIT(COMPx->CSR, COMP_CSR_EN);
}
/**
* @brief Disable comparator instance.
* @rmtoll CSR EN LL_COMP_Disable
* @param COMPx Comparator instance
* @retval None
*/
__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
{
CLEAR_BIT(COMPx->CSR, COMP_CSR_EN);
}
/**
* @brief Get comparator enable state
* (0: COMP is disabled, 1: COMP is enabled)
* @rmtoll CSR EN LL_COMP_IsEnabled
* @param COMPx Comparator instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx)
{
return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL);
}
/**
* @brief Lock comparator instance.
* @note Once locked, comparator configuration can be accessed in read-only.
* @note The only way to unlock the comparator is a device hardware reset.
* @rmtoll CSR LOCK LL_COMP_Lock
* @param COMPx Comparator instance
* @retval None
*/
__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
{
SET_BIT(COMPx->CSR, COMP_CSR_LOCK);
}
/**
* @brief Get comparator lock state
* (0: COMP is unlocked, 1: COMP is locked).
* @note Once locked, comparator configuration can be accessed in read-only.
* @note The only way to unlock the comparator is a device hardware reset.
* @rmtoll CSR LOCK LL_COMP_IsLocked
* @param COMPx Comparator instance
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx)
{
return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL);
}
/**
* @brief Read comparator instance output level.
* @note On this STM32 series, comparator 'value' is taken before
* polarity and blanking are applied, thus:
* - Comparator output is low when the input plus
* is at a lower voltage than the input minus
* - Comparator output is high when the input plus
* is at a higher voltage than the input minus
* @rmtoll CSR VALUE LL_COMP_ReadOutputLevel
* @param COMPx Comparator instance
* @retval Returned value can be one of the following values:
* @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
* @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
*/
__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx)
{
return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
>> COMP_CSR_VALUE_Pos);
}
/**
* @}
*/
#if defined(USE_FULL_LL_DRIVER)
/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
* @{
*/
ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct);
void LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
/**
* @}
*/
#endif /* USE_FULL_LL_DRIVER */
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* STM32G4xx_LL_COMP_H */

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"lib_footprint_mismatch|193598800|48920399|e20c6d70-ca25-4b4b-b942-da573dc77771|00000000-0000-0000-0000-000000000000",
""
],
[
"lib_footprint_mismatch|199745600|83094700|b085309a-34f8-4979-822d-d3f895291474|00000000-0000-0000-0000-000000000000",
""
]
],
"meta": {
"version": 2
},
@@ -125,7 +194,7 @@
"max_error": 0.005,
"min_clearance": 0.0,
"min_connection": 0.0,
"min_copper_edge_clearance": 0.5,
"min_copper_edge_clearance": 0.45,
"min_groove_width": 0.0,
"min_hole_clearance": 0.25,
"min_hole_to_hole": 0.25,

7563
kicad/c64psu/c64psu.kicad_sch
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File diff suppressed because it is too large Load Diff

249
kicad/c64psu/lib/LIB_TPP363082-T6TR/TPP363082-T6TR/KiCad/TPP363082-T6TR.bak Normal file
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@@ -0,0 +1,249 @@
(kicad_symbol_lib
(version 20241209)
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279
kicad/c64psu/lib/LIB_TPP363082-T6TR/TPP363082-T6TR/KiCad/TPP363082-T6TR.kicad_sym
View File

@@ -1,70 +1,249 @@
(kicad_symbol_lib (version 20211014) (generator SamacSys_ECAD_Model)
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(effects (font (size 1.27 1.27)) (justify left top))
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0
kicad/c64psu/~_autosave-c64psu.kicad_pcb.lck → kicad/c64psu/~c64psu.kicad_sch.lck
View File