From 5594ab60b3c3f4177b88c500f0a83fb763fc6b3a Mon Sep 17 00:00:00 2001
From: janik <janikoltmanns1184@gmail.com>
Date: Thu, 4 Sep 2025 17:26:10 +0700
Subject: [PATCH] finished new 5V buck, layout

---
 code/.cproject                                |     4 +-
 code/.mxproject                               |     4 +-
 code/C64PSU.ioc                               |    74 +-
 code/Core/Inc/main.h                          |     2 +
 code/Core/Inc/stm32g4xx_hal_conf.h            |    12 +-
 code/Core/Src/main.c                          |   524 +-
 code/Core/Src/stm32g4xx_hal_msp.c             |   446 +-
 .../Inc/stm32g4xx_hal_adc.h                   |  2318 ++
 .../Inc/stm32g4xx_hal_adc_ex.h                |  1570 +
 .../Inc/stm32g4xx_hal_comp.h                  |  1404 +
 .../Inc/stm32g4xx_hal_dac.h                   |   638 +
 .../Inc/stm32g4xx_hal_dac_ex.h                |   345 +
 .../Inc/stm32g4xx_hal_hrtim.h                 |  5153 ++++
 .../Inc/stm32g4xx_hal_uart.h                  |  1745 ++
 .../Inc/stm32g4xx_hal_uart_ex.h               |   929 +
 .../Inc/stm32g4xx_ll_adc.h                    |  9204 ++++++
 .../Inc/stm32g4xx_ll_comp.h                   |   757 +
 .../Inc/stm32g4xx_ll_dac.h                    |  2676 ++
 .../Inc/stm32g4xx_ll_hrtim.h                  | 13905 +++++++++
 .../Inc/stm32g4xx_ll_lpuart.h                 |  2658 ++
 .../Inc/stm32g4xx_ll_usart.h                  |  4399 +++
 .../Src/stm32g4xx_hal_adc.c                   |  3716 +++
 .../Src/stm32g4xx_hal_adc_ex.c                |  2384 ++
 .../Src/stm32g4xx_hal_comp.c                  |  1099 +
 .../Src/stm32g4xx_hal_dac.c                   |  1749 ++
 .../Src/stm32g4xx_hal_dac_ex.c                |  1184 +
 .../Src/stm32g4xx_hal_hrtim.c                 | 11077 +++++++
 .../Src/stm32g4xx_hal_uart.c                  |  4695 +++
 .../Src/stm32g4xx_hal_uart_ex.c               |  1042 +
 .../Src/stm32g4xx_ll_adc.c                    |  1419 +
 kicad/c64psu/#auto_saved_files#               |     1 +
 .../c64psu-2025-08-11_151728.zip              |   Bin 96097 -> 0 bytes
 .../c64psu-2025-08-11_160700.zip              |   Bin 96014 -> 0 bytes
 .../c64psu-2025-08-11_161254.zip              |   Bin 96105 -> 0 bytes
 .../c64psu-2025-08-11_162650.zip              |   Bin 96189 -> 0 bytes
 .../c64psu-2025-08-12_134611.zip              |   Bin 112580 -> 0 bytes
 .../c64psu-2025-09-04_160538.zip              |   Bin 0 -> 295278 bytes
 .../c64psu-2025-09-04_162408.zip              |   Bin 0 -> 294769 bytes
 .../c64psu-2025-09-04_162921.zip              |   Bin 0 -> 292661 bytes
 .../c64psu-2025-09-04_165059.zip              |   Bin 0 -> 292475 bytes
 .../c64psu-2025-09-04_165602.zip              |   Bin 0 -> 293652 bytes
 kicad/c64psu/c64psu.kicad_pcb                 | 24621 +++++++---------
 kicad/c64psu/c64psu.kicad_prl                 |     2 +-
 kicad/c64psu/c64psu.kicad_pro                 |    75 +-
 kicad/c64psu/c64psu.kicad_sch                 |  7569 ++---
 .../TPP363082-T6TR/KiCad/TPP363082-T6TR.bak   |   249 +
 .../KiCad/TPP363082-T6TR.kicad_sym            |   317 +-
 ...su.kicad_pcb.lck => ~c64psu.kicad_sch.lck} |     0
 48 files changed, 90097 insertions(+), 19869 deletions(-)
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_hrtim.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_comp.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dac.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_hrtim.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_comp.c
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_hrtim.c
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c
 create mode 100644 code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c
 create mode 100644 kicad/c64psu/#auto_saved_files#
 delete mode 100644 kicad/c64psu/c64psu-backups/c64psu-2025-08-11_151728.zip
 delete mode 100644 kicad/c64psu/c64psu-backups/c64psu-2025-08-11_160700.zip
 delete mode 100644 kicad/c64psu/c64psu-backups/c64psu-2025-08-11_161254.zip
 delete mode 100644 kicad/c64psu/c64psu-backups/c64psu-2025-08-11_162650.zip
 delete mode 100644 kicad/c64psu/c64psu-backups/c64psu-2025-08-12_134611.zip
 create mode 100644 kicad/c64psu/c64psu-backups/c64psu-2025-09-04_160538.zip
 create mode 100644 kicad/c64psu/c64psu-backups/c64psu-2025-09-04_162408.zip
 create mode 100644 kicad/c64psu/c64psu-backups/c64psu-2025-09-04_162921.zip
 create mode 100644 kicad/c64psu/c64psu-backups/c64psu-2025-09-04_165059.zip
 create mode 100644 kicad/c64psu/c64psu-backups/c64psu-2025-09-04_165602.zip
 create mode 100644 kicad/c64psu/lib/LIB_TPP363082-T6TR/TPP363082-T6TR/KiCad/TPP363082-T6TR.bak
 rename kicad/c64psu/{~_autosave-c64psu.kicad_pcb.lck => ~c64psu.kicad_sch.lck} (100%)

diff --git a/code/.cproject b/code/.cproject
index 082a294..9e45330 100644
--- a/code/.cproject
+++ b/code/.cproject
@@ -24,7 +24,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.569851536" name="Floating-point ABI" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.493855913" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1904983327" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32G474CBTx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32G4xx_HAL_Driver/Inc | ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32G4xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32G474xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32G474CBTX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1640224048" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="16" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1640224048" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="170" valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1281027497" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/C64PSU}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.735311501" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.2006906671" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
@@ -104,7 +104,7 @@
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.1043717698" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi" useByScannerDiscovery="true" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.floatabi.value.hard" valueType="enumerated"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.740239677" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
 							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.382897756" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32G474CBTx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32G4xx_HAL_Driver/Inc | ../Drivers/STM32G4xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32G4xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32G474xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32G474CBTX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1137781942" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="16" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.1137781942" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="170" valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1467828888" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
 							<builder buildPath="${workspace_loc:/C64PSU}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1030449639" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.819839422" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
diff --git a/code/.mxproject b/code/.mxproject
index 2bcf663..c4af406 100644
--- a/code/.mxproject
+++ b/code/.mxproject
@@ -1,8 +1,8 @@
 [PreviousLibFiles]
-LibFiles=Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_cordic.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_cordic.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_def.h;Drivers\STM32G4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_bus.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_system.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_utils.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_crs.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ramfunc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dmamux.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_fmac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_fmac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_tim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim_ex.h;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cordic.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_fmac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_cordic.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_cordic.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_def.h;Drivers\STM32G4xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_rcc_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_bus.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_rcc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_system.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_utils.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_crs.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_flash_ramfunc.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_gpio_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dmamux.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_fmac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_fmac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_tim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim_ex.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\stm32g474xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\system_stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\system_stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
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\stm32g4xx_hal_gpio_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_gpio.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_exti.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dma_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dma.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dmamux.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_pwr_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_pwr.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_cortex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_comp.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_comp.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_cordic.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_cordic.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_dac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_dac_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_fmac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_fmac.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_hrtim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_hrtim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_tim.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_tim_ex.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_uart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_usart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_ll_lpuart.h;Drivers\STM32G4xx_HAL_Driver\Inc\stm32g4xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\stm32g474xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\system_stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Include\system_stm32g4xx.h;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
 
 [PreviousUsedCubeIDEFiles]
-SourceFiles=Core\Src\main.c;Core\Src\stm32g4xx_it.c;Core\Src\stm32g4xx_hal_msp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cordic.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_fmac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Core\Src\system_stm32g4xx.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cordic.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_fmac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Core\Src\system_stm32g4xx.c;;;
+SourceFiles=Core\Src\main.c;Core\Src\stm32g4xx_it.c;Core\Src\stm32g4xx_hal_msp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_adc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_adc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_adc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_comp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cordic.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_fmac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_hrtim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Core\Src\system_stm32g4xx.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_adc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_adc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_ll_adc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_rcc_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_flash_ramfunc.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_gpio.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_exti.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dma_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_pwr_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cortex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_comp.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_cordic.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_dac_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_fmac.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_hrtim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_tim_ex.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart.c;Drivers\STM32G4xx_HAL_Driver\Src\stm32g4xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32G4xx\Source\Templates\system_stm32g4xx.c;Core\Src\system_stm32g4xx.c;;;
 HeaderPath=Drivers\STM32G4xx_HAL_Driver\Inc;Drivers\STM32G4xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32G4xx\Include;Drivers\CMSIS\Include;Core\Inc;
 CDefines=USE_HAL_DRIVER;STM32G474xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
 
diff --git a/code/C64PSU.ioc b/code/C64PSU.ioc
index 34e2649..8b5ebff 100644
--- a/code/C64PSU.ioc
+++ b/code/C64PSU.ioc
@@ -147,50 +147,54 @@ ProjectManager.ToolChainLocation=
 ProjectManager.UAScriptAfterPath=
 ProjectManager.UAScriptBeforePath=
 ProjectManager.UnderRoot=true
-ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_TIM1_Init-TIM1-false-HAL-true,4-MX_CORDIC_Init-CORDIC-false-HAL-true,5-MX_FMAC_Init-FMAC-false-HAL-true
-RCC.AHBFreq_Value=16000000
-RCC.APB1Freq_Value=16000000
-RCC.APB1TimFreq_Value=16000000
-RCC.APB2Freq_Value=16000000
-RCC.APB2TimFreq_Value=16000000
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_TIM1_Init-TIM1-false-HAL-true,4-MX_CORDIC_Init-CORDIC-false-HAL-true,5-MX_FMAC_Init-FMAC-false-HAL-true,6-MX_ADC3_Init-ADC3-false-HAL-true,7-MX_ADC4_Init-ADC4-false-HAL-true,8-MX_COMP5_Init-COMP5-false-HAL-true,9-MX_COMP7_Init-COMP7-false-HAL-true,10-MX_DAC1_Init-DAC1-false-HAL-true,11-MX_DAC4_Init-DAC4-false-HAL-true,12-MX_HRTIM1_Init-HRTIM1-false-HAL-true,13-MX_USART1_UART_Init-USART1-false-HAL-true
+RCC.ADC12Freq_Value=170000000
+RCC.ADC345Freq_Value=170000000
+RCC.AHBFreq_Value=170000000
+RCC.APB1Freq_Value=170000000
+RCC.APB1TimFreq_Value=170000000
+RCC.APB2Freq_Value=170000000
+RCC.APB2TimFreq_Value=170000000
 RCC.CRSFreq_Value=48000000
-RCC.CortexFreq_Value=16000000
+RCC.CortexFreq_Value=170000000
 RCC.EXTERNAL_CLOCK_VALUE=12288000
-RCC.FCLKCortexFreq_Value=16000000
-RCC.FDCANFreq_Value=16000000
+RCC.FCLKCortexFreq_Value=170000000
+RCC.FDCANFreq_Value=170000000
 RCC.FamilyName=M
-RCC.HCLKFreq_Value=16000000
-RCC.HRTIM1Freq_Value=16000000
-RCC.HSE_VALUE=8000000
+RCC.HCLKFreq_Value=170000000
+RCC.HSE_VALUE=40000000
 RCC.HSI48_VALUE=48000000
 RCC.HSI_VALUE=16000000
-RCC.I2C1Freq_Value=16000000
-RCC.I2C2Freq_Value=16000000
-RCC.I2C3Freq_Value=16000000
-RCC.I2C4Freq_Value=16000000
-RCC.I2SFreq_Value=16000000
-RCC.IPParameters=AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HRTIM1Freq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,PWRFreq_Value,QSPIFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
-RCC.LPTIM1Freq_Value=16000000
-RCC.LPUART1Freq_Value=16000000
+RCC.I2C1Freq_Value=170000000
+RCC.I2C2Freq_Value=170000000
+RCC.I2C3Freq_Value=170000000
+RCC.I2C4Freq_Value=170000000
+RCC.I2SFreq_Value=170000000
+RCC.IPParameters=ADC12Freq_Value,ADC345Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,CRSFreq_Value,CortexFreq_Value,EXTERNAL_CLOCK_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,I2SFreq_Value,LPTIM1Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSE_VALUE,LSI_VALUE,MCO1PinFreq_Value,PLLM,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,PLLSourceVirtual,PWRFreq_Value,QSPIFreq_Value,RNGFreq_Value,SAI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInputFreq_Value,VCOOutputFreq_Value
+RCC.LPTIM1Freq_Value=170000000
+RCC.LPUART1Freq_Value=170000000
 RCC.LSCOPinFreq_Value=32000
 RCC.LSE_VALUE=32768
 RCC.LSI_VALUE=32000
 RCC.MCO1PinFreq_Value=16000000
-RCC.PLLPoutputFreq_Value=32000000
-RCC.PLLQoutputFreq_Value=32000000
-RCC.PLLRCLKFreq_Value=32000000
+RCC.PLLM=RCC_PLLM_DIV4
+RCC.PLLN=34
+RCC.PLLPoutputFreq_Value=170000000
+RCC.PLLQoutputFreq_Value=170000000
+RCC.PLLRCLKFreq_Value=170000000
 RCC.PLLSourceVirtual=RCC_PLLSOURCE_HSE
-RCC.PWRFreq_Value=16000000
-RCC.QSPIFreq_Value=16000000
-RCC.RNGFreq_Value=32000000
-RCC.SAI1Freq_Value=16000000
-RCC.SYSCLKFreq_VALUE=16000000
-RCC.USART1Freq_Value=16000000
-RCC.USART2Freq_Value=16000000
-RCC.USART3Freq_Value=16000000
-RCC.USBFreq_Value=32000000
-RCC.VCOInputFreq_Value=8000000
-RCC.VCOOutputFreq_Value=64000000
+RCC.PWRFreq_Value=170000000
+RCC.QSPIFreq_Value=170000000
+RCC.RNGFreq_Value=170000000
+RCC.SAI1Freq_Value=170000000
+RCC.SYSCLKFreq_VALUE=170000000
+RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
+RCC.USART1Freq_Value=170000000
+RCC.USART2Freq_Value=170000000
+RCC.USART3Freq_Value=170000000
+RCC.USBFreq_Value=170000000
+RCC.VCOInputFreq_Value=10000000
+RCC.VCOOutputFreq_Value=340000000
 SH.SharedAnalog_PB13.0=ADC3_IN5,IN5-Single-Ended
 SH.SharedAnalog_PB13.1=COMP5_INP,INP
 SH.SharedAnalog_PB13.ConfNb=2
@@ -222,4 +226,4 @@ VP_SYS_V_VREFBUF.Signal=SYS_V_VREFBUF
 VP_TIM1_VS_ClockSourceINT.Mode=Internal
 VP_TIM1_VS_ClockSourceINT.Signal=TIM1_VS_ClockSourceINT
 board=custom
-isbadioc=true
+isbadioc=false
diff --git a/code/Core/Inc/main.h b/code/Core/Inc/main.h
index ed8b4e4..f5e7245 100644
--- a/code/Core/Inc/main.h
+++ b/code/Core/Inc/main.h
@@ -49,6 +49,8 @@ extern "C" {
 
 /* USER CODE END EM */
 
+void HAL_HRTIM_MspPostInit(HRTIM_HandleTypeDef *hhrtim);
+
 /* Exported functions prototypes ---------------------------------------------*/
 void Error_Handler(void);
 
diff --git a/code/Core/Inc/stm32g4xx_hal_conf.h b/code/Core/Inc/stm32g4xx_hal_conf.h
index f29ee34..fbd2872 100644
--- a/code/Core/Inc/stm32g4xx_hal_conf.h
+++ b/code/Core/Inc/stm32g4xx_hal_conf.h
@@ -36,15 +36,15 @@
 
 #define HAL_MODULE_ENABLED
 
-  /*#define HAL_ADC_MODULE_ENABLED   */
-/*#define HAL_COMP_MODULE_ENABLED   */
+  #define HAL_ADC_MODULE_ENABLED
+#define HAL_COMP_MODULE_ENABLED
 #define HAL_CORDIC_MODULE_ENABLED
 /*#define HAL_CRC_MODULE_ENABLED   */
 /*#define HAL_CRYP_MODULE_ENABLED   */
-/*#define HAL_DAC_MODULE_ENABLED   */
+#define HAL_DAC_MODULE_ENABLED
 /*#define HAL_FDCAN_MODULE_ENABLED   */
 #define HAL_FMAC_MODULE_ENABLED
-/*#define HAL_HRTIM_MODULE_ENABLED   */
+#define HAL_HRTIM_MODULE_ENABLED
 /*#define HAL_IRDA_MODULE_ENABLED   */
 /*#define HAL_IWDG_MODULE_ENABLED   */
 /*#define HAL_I2C_MODULE_ENABLED   */
@@ -63,7 +63,7 @@
 /*#define HAL_SPI_MODULE_ENABLED   */
 /*#define HAL_SRAM_MODULE_ENABLED   */
 #define HAL_TIM_MODULE_ENABLED
-/*#define HAL_UART_MODULE_ENABLED   */
+#define HAL_UART_MODULE_ENABLED
 /*#define HAL_USART_MODULE_ENABLED   */
 /*#define HAL_WWDG_MODULE_ENABLED   */
 #define HAL_GPIO_MODULE_ENABLED
@@ -115,7 +115,7 @@
   *        (when HSE is used as system clock source, directly or through the PLL).
   */
 #if !defined  (HSE_VALUE)
-  #define HSE_VALUE    (8000000UL) /*!< Value of the External oscillator in Hz */
+  #define HSE_VALUE    (40000000UL) /*!< Value of the External oscillator in Hz */
 #endif /* HSE_VALUE */
 
 #if !defined  (HSE_STARTUP_TIMEOUT)
diff --git a/code/Core/Src/main.c b/code/Core/Src/main.c
index a9be332..0e685f3 100644
--- a/code/Core/Src/main.c
+++ b/code/Core/Src/main.c
@@ -40,12 +40,25 @@
 /* USER CODE END PM */
 
 /* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc3;
+ADC_HandleTypeDef hadc4;
+
+COMP_HandleTypeDef hcomp5;
+COMP_HandleTypeDef hcomp7;
+
 CORDIC_HandleTypeDef hcordic;
 
+DAC_HandleTypeDef hdac1;
+DAC_HandleTypeDef hdac4;
+
 FMAC_HandleTypeDef hfmac;
 
+HRTIM_HandleTypeDef hhrtim1;
+
 TIM_HandleTypeDef htim1;
 
+UART_HandleTypeDef huart1;
+
 /* USER CODE BEGIN PV */
 
 /* USER CODE END PV */
@@ -56,6 +69,14 @@ static void MX_GPIO_Init(void);
 static void MX_TIM1_Init(void);
 static void MX_CORDIC_Init(void);
 static void MX_FMAC_Init(void);
+static void MX_ADC3_Init(void);
+static void MX_ADC4_Init(void);
+static void MX_COMP5_Init(void);
+static void MX_COMP7_Init(void);
+static void MX_DAC1_Init(void);
+static void MX_DAC4_Init(void);
+static void MX_HRTIM1_Init(void);
+static void MX_USART1_UART_Init(void);
 /* USER CODE BEGIN PFP */
 
 /* USER CODE END PFP */
@@ -97,6 +118,14 @@ int main(void)
   MX_TIM1_Init();
   MX_CORDIC_Init();
   MX_FMAC_Init();
+  MX_ADC3_Init();
+  MX_ADC4_Init();
+  MX_COMP5_Init();
+  MX_COMP7_Init();
+  MX_DAC1_Init();
+  MX_DAC4_Init();
+  MX_HRTIM1_Init();
+  MX_USART1_UART_Init();
   /* USER CODE BEGIN 2 */
 
   /* USER CODE END 2 */
@@ -123,15 +152,20 @@ void SystemClock_Config(void)
 
   /** Configure the main internal regulator output voltage
   */
-  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
+  HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
 
   /** Initializes the RCC Oscillators according to the specified parameters
   * in the RCC_OscInitTypeDef structure.
   */
-  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
-  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+  RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+  RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+  RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
+  RCC_OscInitStruct.PLL.PLLN = 34;
+  RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
+  RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
+  RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
   {
     Error_Handler();
@@ -141,17 +175,208 @@ void SystemClock_Config(void)
   */
   RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
                               |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
   RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
   RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
   RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
   {
     Error_Handler();
   }
 }
 
+/**
+  * @brief ADC3 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC3_Init(void)
+{
+
+  /* USER CODE BEGIN ADC3_Init 0 */
+
+  /* USER CODE END ADC3_Init 0 */
+
+  ADC_MultiModeTypeDef multimode = {0};
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC3_Init 1 */
+
+  /* USER CODE END ADC3_Init 1 */
+
+  /** Common config
+  */
+  hadc3.Instance = ADC3;
+  hadc3.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
+  hadc3.Init.Resolution = ADC_RESOLUTION_12B;
+  hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc3.Init.GainCompensation = 0;
+  hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  hadc3.Init.LowPowerAutoWait = DISABLE;
+  hadc3.Init.ContinuousConvMode = DISABLE;
+  hadc3.Init.NbrOfConversion = 1;
+  hadc3.Init.DiscontinuousConvMode = DISABLE;
+  hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+  hadc3.Init.DMAContinuousRequests = DISABLE;
+  hadc3.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+  hadc3.Init.OversamplingMode = DISABLE;
+  if (HAL_ADC_Init(&hadc3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure the ADC multi-mode
+  */
+  multimode.Mode = ADC_MODE_INDEPENDENT;
+  if (HAL_ADCEx_MultiModeConfigChannel(&hadc3, &multimode) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_5;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
+  sConfig.SingleDiff = ADC_SINGLE_ENDED;
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;
+  sConfig.Offset = 0;
+  if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC3_Init 2 */
+
+  /* USER CODE END ADC3_Init 2 */
+
+}
+
+/**
+  * @brief ADC4 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC4_Init(void)
+{
+
+  /* USER CODE BEGIN ADC4_Init 0 */
+
+  /* USER CODE END ADC4_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC4_Init 1 */
+
+  /* USER CODE END ADC4_Init 1 */
+
+  /** Common config
+  */
+  hadc4.Instance = ADC4;
+  hadc4.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4;
+  hadc4.Init.Resolution = ADC_RESOLUTION_12B;
+  hadc4.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc4.Init.GainCompensation = 0;
+  hadc4.Init.ScanConvMode = ADC_SCAN_DISABLE;
+  hadc4.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  hadc4.Init.LowPowerAutoWait = DISABLE;
+  hadc4.Init.ContinuousConvMode = DISABLE;
+  hadc4.Init.NbrOfConversion = 1;
+  hadc4.Init.DiscontinuousConvMode = DISABLE;
+  hadc4.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc4.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+  hadc4.Init.DMAContinuousRequests = DISABLE;
+  hadc4.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+  hadc4.Init.OversamplingMode = DISABLE;
+  if (HAL_ADC_Init(&hadc4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_4;
+  sConfig.Rank = ADC_REGULAR_RANK_1;
+  sConfig.SamplingTime = ADC_SAMPLETIME_2CYCLES_5;
+  sConfig.SingleDiff = ADC_SINGLE_ENDED;
+  sConfig.OffsetNumber = ADC_OFFSET_NONE;
+  sConfig.Offset = 0;
+  if (HAL_ADC_ConfigChannel(&hadc4, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC4_Init 2 */
+
+  /* USER CODE END ADC4_Init 2 */
+
+}
+
+/**
+  * @brief COMP5 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_COMP5_Init(void)
+{
+
+  /* USER CODE BEGIN COMP5_Init 0 */
+
+  /* USER CODE END COMP5_Init 0 */
+
+  /* USER CODE BEGIN COMP5_Init 1 */
+
+  /* USER CODE END COMP5_Init 1 */
+  hcomp5.Instance = COMP5;
+  hcomp5.Init.InputPlus = COMP_INPUT_PLUS_IO1;
+  hcomp5.Init.InputMinus = COMP_INPUT_MINUS_DAC1_CH2;
+  hcomp5.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED;
+  hcomp5.Init.Hysteresis = COMP_HYSTERESIS_NONE;
+  hcomp5.Init.BlankingSrce = COMP_BLANKINGSRC_NONE;
+  hcomp5.Init.TriggerMode = COMP_TRIGGERMODE_NONE;
+  if (HAL_COMP_Init(&hcomp5) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN COMP5_Init 2 */
+
+  /* USER CODE END COMP5_Init 2 */
+
+}
+
+/**
+  * @brief COMP7 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_COMP7_Init(void)
+{
+
+  /* USER CODE BEGIN COMP7_Init 0 */
+
+  /* USER CODE END COMP7_Init 0 */
+
+  /* USER CODE BEGIN COMP7_Init 1 */
+
+  /* USER CODE END COMP7_Init 1 */
+  hcomp7.Instance = COMP7;
+  hcomp7.Init.InputPlus = COMP_INPUT_PLUS_IO1;
+  hcomp7.Init.InputMinus = COMP_INPUT_MINUS_DAC4_CH1;
+  hcomp7.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED;
+  hcomp7.Init.Hysteresis = COMP_HYSTERESIS_NONE;
+  hcomp7.Init.BlankingSrce = COMP_BLANKINGSRC_NONE;
+  hcomp7.Init.TriggerMode = COMP_TRIGGERMODE_NONE;
+  if (HAL_COMP_Init(&hcomp7) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN COMP7_Init 2 */
+
+  /* USER CODE END COMP7_Init 2 */
+
+}
+
 /**
   * @brief CORDIC Initialization Function
   * @param None
@@ -178,6 +403,100 @@ static void MX_CORDIC_Init(void)
 
 }
 
+/**
+  * @brief DAC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_DAC1_Init(void)
+{
+
+  /* USER CODE BEGIN DAC1_Init 0 */
+
+  /* USER CODE END DAC1_Init 0 */
+
+  DAC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN DAC1_Init 1 */
+
+  /* USER CODE END DAC1_Init 1 */
+
+  /** DAC Initialization
+  */
+  hdac1.Instance = DAC1;
+  if (HAL_DAC_Init(&hdac1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** DAC channel OUT2 config
+  */
+  sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC;
+  sConfig.DAC_DMADoubleDataMode = DISABLE;
+  sConfig.DAC_SignedFormat = DISABLE;
+  sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
+  sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
+  sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE;
+  sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
+  sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
+  sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
+  if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN DAC1_Init 2 */
+
+  /* USER CODE END DAC1_Init 2 */
+
+}
+
+/**
+  * @brief DAC4 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_DAC4_Init(void)
+{
+
+  /* USER CODE BEGIN DAC4_Init 0 */
+
+  /* USER CODE END DAC4_Init 0 */
+
+  DAC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN DAC4_Init 1 */
+
+  /* USER CODE END DAC4_Init 1 */
+
+  /** DAC Initialization
+  */
+  hdac4.Instance = DAC4;
+  if (HAL_DAC_Init(&hdac4) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** DAC channel OUT1 config
+  */
+  sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC;
+  sConfig.DAC_DMADoubleDataMode = DISABLE;
+  sConfig.DAC_SignedFormat = DISABLE;
+  sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
+  sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
+  sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE;
+  sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
+  sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
+  sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
+  if (HAL_DAC_ConfigChannel(&hdac4, &sConfig, DAC_CHANNEL_1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN DAC4_Init 2 */
+
+  /* USER CODE END DAC4_Init 2 */
+
+}
+
 /**
   * @brief FMAC Initialization Function
   * @param None
@@ -204,6 +523,148 @@ static void MX_FMAC_Init(void)
 
 }
 
+/**
+  * @brief HRTIM1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_HRTIM1_Init(void)
+{
+
+  /* USER CODE BEGIN HRTIM1_Init 0 */
+
+  /* USER CODE END HRTIM1_Init 0 */
+
+  HRTIM_EventCfgTypeDef pEventCfg = {0};
+  HRTIM_TimeBaseCfgTypeDef pTimeBaseCfg = {0};
+  HRTIM_TimerCfgTypeDef pTimerCfg = {0};
+  HRTIM_TimerCtlTypeDef pTimerCtl = {0};
+  HRTIM_OutputCfgTypeDef pOutputCfg = {0};
+
+  /* USER CODE BEGIN HRTIM1_Init 1 */
+
+  /* USER CODE END HRTIM1_Init 1 */
+  hhrtim1.Instance = HRTIM1;
+  hhrtim1.Init.HRTIMInterruptResquests = HRTIM_IT_NONE;
+  hhrtim1.Init.SyncOptions = HRTIM_SYNCOPTION_NONE;
+  if (HAL_HRTIM_Init(&hhrtim1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_HRTIM_DLLCalibrationStart(&hhrtim1, HRTIM_CALIBRATIONRATE_3) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_HRTIM_PollForDLLCalibration(&hhrtim1, 10) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_HRTIM_EventPrescalerConfig(&hhrtim1, HRTIM_EVENTPRESCALER_DIV1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  pEventCfg.Source = HRTIM_EEV1SRC_COMP2_OUT;
+  pEventCfg.Polarity = HRTIM_EVENTPOLARITY_HIGH;
+  pEventCfg.Sensitivity = HRTIM_EVENTSENSITIVITY_LEVEL;
+  pEventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
+  if (HAL_HRTIM_EventConfig(&hhrtim1, HRTIM_EVENT_1, &pEventCfg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  pTimeBaseCfg.Period = 0xFFDF;
+  pTimeBaseCfg.RepetitionCounter = 0x00;
+  pTimeBaseCfg.PrescalerRatio = HRTIM_PRESCALERRATIO_MUL32;
+  pTimeBaseCfg.Mode = HRTIM_MODE_CONTINUOUS;
+  if (HAL_HRTIM_TimeBaseConfig(&hhrtim1, HRTIM_TIMERINDEX_MASTER, &pTimeBaseCfg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  pTimerCfg.InterruptRequests = HRTIM_MASTER_IT_NONE;
+  pTimerCfg.DMARequests = HRTIM_MASTER_DMA_NONE;
+  pTimerCfg.DMASrcAddress = 0x0000;
+  pTimerCfg.DMADstAddress = 0x0000;
+  pTimerCfg.DMASize = 0x1;
+  pTimerCfg.HalfModeEnable = HRTIM_HALFMODE_DISABLED;
+  pTimerCfg.InterleavedMode = HRTIM_INTERLEAVED_MODE_DISABLED;
+  pTimerCfg.StartOnSync = HRTIM_SYNCSTART_DISABLED;
+  pTimerCfg.ResetOnSync = HRTIM_SYNCRESET_DISABLED;
+  pTimerCfg.DACSynchro = HRTIM_DACSYNC_NONE;
+  pTimerCfg.PreloadEnable = HRTIM_PRELOAD_DISABLED;
+  pTimerCfg.UpdateGating = HRTIM_UPDATEGATING_INDEPENDENT;
+  pTimerCfg.BurstMode = HRTIM_TIMERBURSTMODE_MAINTAINCLOCK;
+  pTimerCfg.RepetitionUpdate = HRTIM_UPDATEONREPETITION_DISABLED;
+  pTimerCfg.ReSyncUpdate = HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL;
+  if (HAL_HRTIM_WaveformTimerConfig(&hhrtim1, HRTIM_TIMERINDEX_MASTER, &pTimerCfg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_HRTIM_TimeBaseConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pTimeBaseCfg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  pTimerCtl.UpDownMode = HRTIM_TIMERUPDOWNMODE_UP;
+  pTimerCtl.DualChannelDacEnable = HRTIM_TIMER_DCDE_DISABLED;
+  if (HAL_HRTIM_WaveformTimerControl(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pTimerCtl) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  pTimerCfg.InterruptRequests = HRTIM_TIM_IT_NONE;
+  pTimerCfg.DMARequests = HRTIM_TIM_DMA_NONE;
+  pTimerCfg.PushPull = HRTIM_TIMPUSHPULLMODE_DISABLED;
+  pTimerCfg.FaultEnable = HRTIM_TIMFAULTENABLE_NONE;
+  pTimerCfg.FaultLock = HRTIM_TIMFAULTLOCK_READWRITE;
+  pTimerCfg.DeadTimeInsertion = HRTIM_TIMDEADTIMEINSERTION_DISABLED;
+  pTimerCfg.DelayedProtectionMode = HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED;
+  pTimerCfg.UpdateTrigger = HRTIM_TIMUPDATETRIGGER_NONE;
+  pTimerCfg.ResetTrigger = HRTIM_TIMRESETTRIGGER_NONE;
+  pTimerCfg.ResetUpdate = HRTIM_TIMUPDATEONRESET_DISABLED;
+  if (HAL_HRTIM_WaveformTimerConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pTimerCfg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_HRTIM_WaveformTimerConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pTimerCfg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  pOutputCfg.Polarity = HRTIM_OUTPUTPOLARITY_HIGH;
+  pOutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
+  pOutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
+  pOutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+  pOutputCfg.IdleLevel = HRTIM_OUTPUTIDLELEVEL_INACTIVE;
+  pOutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
+  pOutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+  pOutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+  if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, HRTIM_OUTPUT_TA1, &pOutputCfg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, HRTIM_OUTPUT_TB1, &pOutputCfg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, HRTIM_OUTPUT_TA2, &pOutputCfg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, HRTIM_OUTPUT_TB2, &pOutputCfg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_HRTIM_TimeBaseConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pTimeBaseCfg) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_HRTIM_WaveformTimerControl(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pTimerCtl) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN HRTIM1_Init 2 */
+
+  /* USER CODE END HRTIM1_Init 2 */
+  HAL_HRTIM_MspPostInit(&hhrtim1);
+
+}
+
 /**
   * @brief TIM1 Initialization Function
   * @param None
@@ -251,6 +712,54 @@ static void MX_TIM1_Init(void)
 
 }
 
+/**
+  * @brief USART1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_USART1_UART_Init(void)
+{
+
+  /* USER CODE BEGIN USART1_Init 0 */
+
+  /* USER CODE END USART1_Init 0 */
+
+  /* USER CODE BEGIN USART1_Init 1 */
+
+  /* USER CODE END USART1_Init 1 */
+  huart1.Instance = USART1;
+  huart1.Init.BaudRate = 115200;
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+  huart1.Init.StopBits = UART_STOPBITS_1;
+  huart1.Init.Parity = UART_PARITY_NONE;
+  huart1.Init.Mode = UART_MODE_TX_RX;
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN USART1_Init 2 */
+
+  /* USER CODE END USART1_Init 2 */
+
+}
+
 /**
   * @brief GPIO Initialization Function
   * @param None
@@ -264,6 +773,7 @@ static void MX_GPIO_Init(void)
 
   /* GPIO Ports Clock Enable */
   __HAL_RCC_GPIOF_CLK_ENABLE();
+  __HAL_RCC_GPIOB_CLK_ENABLE();
   __HAL_RCC_GPIOA_CLK_ENABLE();
 
   /* USER CODE BEGIN MX_GPIO_Init_2 */
diff --git a/code/Core/Src/stm32g4xx_hal_msp.c b/code/Core/Src/stm32g4xx_hal_msp.c
index 1335053..41db2ef 100644
--- a/code/Core/Src/stm32g4xx_hal_msp.c
+++ b/code/Core/Src/stm32g4xx_hal_msp.c
@@ -57,7 +57,9 @@
 /* USER CODE BEGIN 0 */
 
 /* USER CODE END 0 */
-/**
+
+void HAL_HRTIM_MspPostInit(HRTIM_HandleTypeDef *hhrtim);
+                    /**
   * Initializes the Global MSP.
   */
 void HAL_MspInit(void)
@@ -89,6 +91,231 @@ void HAL_MspInit(void)
   /* USER CODE END MspInit 1 */
 }
 
+static uint32_t HAL_RCC_ADC345_CLK_ENABLED=0;
+
+/**
+  * @brief ADC MSP Initialization
+  * This function configures the hardware resources used in this example
+  * @param hadc: ADC handle pointer
+  * @retval None
+  */
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(hadc->Instance==ADC3)
+  {
+    /* USER CODE BEGIN ADC3_MspInit 0 */
+
+    /* USER CODE END ADC3_MspInit 0 */
+
+  /** Initializes the peripherals clocks
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC345;
+    PeriphClkInit.Adc345ClockSelection = RCC_ADC345CLKSOURCE_SYSCLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    HAL_RCC_ADC345_CLK_ENABLED++;
+    if(HAL_RCC_ADC345_CLK_ENABLED==1){
+      __HAL_RCC_ADC345_CLK_ENABLE();
+    }
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**ADC3 GPIO Configuration
+    PB13     ------> ADC3_IN5
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_13;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USER CODE BEGIN ADC3_MspInit 1 */
+
+    /* USER CODE END ADC3_MspInit 1 */
+  }
+  else if(hadc->Instance==ADC4)
+  {
+    /* USER CODE BEGIN ADC4_MspInit 0 */
+
+    /* USER CODE END ADC4_MspInit 0 */
+
+  /** Initializes the peripherals clocks
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC345;
+    PeriphClkInit.Adc345ClockSelection = RCC_ADC345CLKSOURCE_SYSCLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    HAL_RCC_ADC345_CLK_ENABLED++;
+    if(HAL_RCC_ADC345_CLK_ENABLED==1){
+      __HAL_RCC_ADC345_CLK_ENABLE();
+    }
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**ADC4 GPIO Configuration
+    PB14     ------> ADC4_IN4
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_14;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USER CODE BEGIN ADC4_MspInit 1 */
+
+    /* USER CODE END ADC4_MspInit 1 */
+  }
+
+}
+
+/**
+  * @brief ADC MSP De-Initialization
+  * This function freeze the hardware resources used in this example
+  * @param hadc: ADC handle pointer
+  * @retval None
+  */
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  if(hadc->Instance==ADC3)
+  {
+    /* USER CODE BEGIN ADC3_MspDeInit 0 */
+
+    /* USER CODE END ADC3_MspDeInit 0 */
+    /* Peripheral clock disable */
+    HAL_RCC_ADC345_CLK_ENABLED--;
+    if(HAL_RCC_ADC345_CLK_ENABLED==0){
+      __HAL_RCC_ADC345_CLK_DISABLE();
+    }
+
+    /**ADC3 GPIO Configuration
+    PB13     ------> ADC3_IN5
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
+
+    /* USER CODE BEGIN ADC3_MspDeInit 1 */
+
+    /* USER CODE END ADC3_MspDeInit 1 */
+  }
+  else if(hadc->Instance==ADC4)
+  {
+    /* USER CODE BEGIN ADC4_MspDeInit 0 */
+
+    /* USER CODE END ADC4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    HAL_RCC_ADC345_CLK_ENABLED--;
+    if(HAL_RCC_ADC345_CLK_ENABLED==0){
+      __HAL_RCC_ADC345_CLK_DISABLE();
+    }
+
+    /**ADC4 GPIO Configuration
+    PB14     ------> ADC4_IN4
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14);
+
+    /* USER CODE BEGIN ADC4_MspDeInit 1 */
+
+    /* USER CODE END ADC4_MspDeInit 1 */
+  }
+
+}
+
+/**
+  * @brief COMP MSP Initialization
+  * This function configures the hardware resources used in this example
+  * @param hcomp: COMP handle pointer
+  * @retval None
+  */
+void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hcomp->Instance==COMP5)
+  {
+    /* USER CODE BEGIN COMP5_MspInit 0 */
+
+    /* USER CODE END COMP5_MspInit 0 */
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**COMP5 GPIO Configuration
+    PB13     ------> COMP5_INP
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_13;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USER CODE BEGIN COMP5_MspInit 1 */
+
+    /* USER CODE END COMP5_MspInit 1 */
+  }
+  else if(hcomp->Instance==COMP7)
+  {
+    /* USER CODE BEGIN COMP7_MspInit 0 */
+
+    /* USER CODE END COMP7_MspInit 0 */
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**COMP7 GPIO Configuration
+    PB14     ------> COMP7_INP
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_14;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USER CODE BEGIN COMP7_MspInit 1 */
+
+    /* USER CODE END COMP7_MspInit 1 */
+  }
+
+}
+
+/**
+  * @brief COMP MSP De-Initialization
+  * This function freeze the hardware resources used in this example
+  * @param hcomp: COMP handle pointer
+  * @retval None
+  */
+void HAL_COMP_MspDeInit(COMP_HandleTypeDef* hcomp)
+{
+  if(hcomp->Instance==COMP5)
+  {
+    /* USER CODE BEGIN COMP5_MspDeInit 0 */
+
+    /* USER CODE END COMP5_MspDeInit 0 */
+
+    /**COMP5 GPIO Configuration
+    PB13     ------> COMP5_INP
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_13);
+
+    /* USER CODE BEGIN COMP5_MspDeInit 1 */
+
+    /* USER CODE END COMP5_MspDeInit 1 */
+  }
+  else if(hcomp->Instance==COMP7)
+  {
+    /* USER CODE BEGIN COMP7_MspDeInit 0 */
+
+    /* USER CODE END COMP7_MspDeInit 0 */
+
+    /**COMP7 GPIO Configuration
+    PB14     ------> COMP7_INP
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_14);
+
+    /* USER CODE BEGIN COMP7_MspDeInit 1 */
+
+    /* USER CODE END COMP7_MspDeInit 1 */
+  }
+
+}
+
 /**
   * @brief CORDIC MSP Initialization
   * This function configures the hardware resources used in this example
@@ -134,6 +361,72 @@ void HAL_CORDIC_MspDeInit(CORDIC_HandleTypeDef* hcordic)
 
 }
 
+/**
+  * @brief DAC MSP Initialization
+  * This function configures the hardware resources used in this example
+  * @param hdac: DAC handle pointer
+  * @retval None
+  */
+void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
+{
+  if(hdac->Instance==DAC1)
+  {
+    /* USER CODE BEGIN DAC1_MspInit 0 */
+
+    /* USER CODE END DAC1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_DAC1_CLK_ENABLE();
+    /* USER CODE BEGIN DAC1_MspInit 1 */
+
+    /* USER CODE END DAC1_MspInit 1 */
+  }
+  else if(hdac->Instance==DAC4)
+  {
+    /* USER CODE BEGIN DAC4_MspInit 0 */
+
+    /* USER CODE END DAC4_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_DAC4_CLK_ENABLE();
+    /* USER CODE BEGIN DAC4_MspInit 1 */
+
+    /* USER CODE END DAC4_MspInit 1 */
+  }
+
+}
+
+/**
+  * @brief DAC MSP De-Initialization
+  * This function freeze the hardware resources used in this example
+  * @param hdac: DAC handle pointer
+  * @retval None
+  */
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
+{
+  if(hdac->Instance==DAC1)
+  {
+    /* USER CODE BEGIN DAC1_MspDeInit 0 */
+
+    /* USER CODE END DAC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_DAC1_CLK_DISABLE();
+    /* USER CODE BEGIN DAC1_MspDeInit 1 */
+
+    /* USER CODE END DAC1_MspDeInit 1 */
+  }
+  else if(hdac->Instance==DAC4)
+  {
+    /* USER CODE BEGIN DAC4_MspDeInit 0 */
+
+    /* USER CODE END DAC4_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_DAC4_CLK_DISABLE();
+    /* USER CODE BEGIN DAC4_MspDeInit 1 */
+
+    /* USER CODE END DAC4_MspDeInit 1 */
+  }
+
+}
+
 /**
   * @brief FMAC MSP Initialization
   * This function configures the hardware resources used in this example
@@ -179,6 +472,80 @@ void HAL_FMAC_MspDeInit(FMAC_HandleTypeDef* hfmac)
 
 }
 
+/**
+  * @brief HRTIM MSP Initialization
+  * This function configures the hardware resources used in this example
+  * @param hhrtim: HRTIM handle pointer
+  * @retval None
+  */
+void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef* hhrtim)
+{
+  if(hhrtim->Instance==HRTIM1)
+  {
+    /* USER CODE BEGIN HRTIM1_MspInit 0 */
+
+    /* USER CODE END HRTIM1_MspInit 0 */
+    /* Peripheral clock enable */
+    __HAL_RCC_HRTIM1_CLK_ENABLE();
+    /* USER CODE BEGIN HRTIM1_MspInit 1 */
+
+    /* USER CODE END HRTIM1_MspInit 1 */
+
+  }
+
+}
+
+void HAL_HRTIM_MspPostInit(HRTIM_HandleTypeDef* hhrtim)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  if(hhrtim->Instance==HRTIM1)
+  {
+    /* USER CODE BEGIN HRTIM1_MspPostInit 0 */
+
+    /* USER CODE END HRTIM1_MspPostInit 0 */
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    /**HRTIM1 GPIO Configuration
+    PA8     ------> HRTIM1_CHA1
+    PA9     ------> HRTIM1_CHA2
+    PA10     ------> HRTIM1_CHB1
+    PA11     ------> HRTIM1_CHB2
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
+    GPIO_InitStruct.Alternate = GPIO_AF13_HRTIM1;
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+
+    /* USER CODE BEGIN HRTIM1_MspPostInit 1 */
+
+    /* USER CODE END HRTIM1_MspPostInit 1 */
+  }
+
+}
+/**
+  * @brief HRTIM MSP De-Initialization
+  * This function freeze the hardware resources used in this example
+  * @param hhrtim: HRTIM handle pointer
+  * @retval None
+  */
+void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef* hhrtim)
+{
+  if(hhrtim->Instance==HRTIM1)
+  {
+    /* USER CODE BEGIN HRTIM1_MspDeInit 0 */
+
+    /* USER CODE END HRTIM1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_HRTIM1_CLK_DISABLE();
+    /* USER CODE BEGIN HRTIM1_MspDeInit 1 */
+
+    /* USER CODE END HRTIM1_MspDeInit 1 */
+  }
+
+}
+
 /**
   * @brief TIM_Base MSP Initialization
   * This function configures the hardware resources used in this example
@@ -224,6 +591,83 @@ void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef* htim_base)
 
 }
 
+/**
+  * @brief UART MSP Initialization
+  * This function configures the hardware resources used in this example
+  * @param huart: UART handle pointer
+  * @retval None
+  */
+void HAL_UART_MspInit(UART_HandleTypeDef* huart)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(huart->Instance==USART1)
+  {
+    /* USER CODE BEGIN USART1_MspInit 0 */
+
+    /* USER CODE END USART1_MspInit 0 */
+
+  /** Initializes the peripherals clocks
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+    PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_USART1_CLK_ENABLE();
+
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**USART1 GPIO Configuration
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX
+    */
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+    GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+
+    /* USER CODE BEGIN USART1_MspInit 1 */
+
+    /* USER CODE END USART1_MspInit 1 */
+
+  }
+
+}
+
+/**
+  * @brief UART MSP De-Initialization
+  * This function freeze the hardware resources used in this example
+  * @param huart: UART handle pointer
+  * @retval None
+  */
+void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
+{
+  if(huart->Instance==USART1)
+  {
+    /* USER CODE BEGIN USART1_MspDeInit 0 */
+
+    /* USER CODE END USART1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_USART1_CLK_DISABLE();
+
+    /**USART1 GPIO Configuration
+    PB6     ------> USART1_TX
+    PB7     ------> USART1_RX
+    */
+    HAL_GPIO_DeInit(GPIOB, GPIO_PIN_6|GPIO_PIN_7);
+
+    /* USER CODE BEGIN USART1_MspDeInit 1 */
+
+    /* USER CODE END USART1_MspDeInit 1 */
+  }
+
+}
+
 /* USER CODE BEGIN 1 */
 
 /* USER CODE END 1 */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h
new file mode 100644
index 0000000..bcddc5f
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc.h
@@ -0,0 +1,2318 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_ADC_H
+#define STM32G4xx_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/* Include low level driver */
+#include "stm32g4xx_ll_adc.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  ADC group regular oversampling structure definition
+  */
+typedef struct
+{
+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+
+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+
+  uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
+
+  uint32_t OversamplingStopReset;         /*!< Selects the regular oversampling mode.
+                                               The oversampling is either temporary stopped or reset upon an injected
+                                               sequence interruption.
+                                               If oversampling is enabled on both regular and injected groups, this
+                                               parameter is discarded and forced to setting
+                                               "ADC_REGOVERSAMPLING_RESUMED_MODE" (the oversampling buffer is zeroed
+                                               during injection sequence).
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
+
+} ADC_OversamplingTypeDef;
+
+/**
+  * @brief  Structure definition of ADC instance and ADC group regular.
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,
+  *            GainCompensation, ScanConvMode, EOCSelection, LowPowerAutoWait.
+  *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,
+  *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling,
+  *            SamplingMode.
+  * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled
+  *          - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled
+  *            without conversion on going on group regular.
+  *          - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going
+  *            on groups regular and injected.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another
+  *         parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous
+                                       clock derived from system clock or PLL (Refer to reference manual for list of
+                                       clocks available)) and clock prescaler.
+                                       This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
+                                       Note: The ADC clock configuration is common to all ADC instances.
+                                       Note: In case of usage of channels on injected group, ADC frequency should be
+                                             lower than AHB clock frequency /4 for resolution 12 or 10 bits,
+                                                        AHB clock frequency /3 for resolution 8 bits,
+                                                        AHB clock frequency /2 for resolution 6 bits.
+                                       Note: In case of synchronous clock mode based on HCLK/1, the configuration must
+                                             be enabled only if the system clock has a 50% duty clock cycle (APB
+                                             prescaler configured inside RCC  must be bypassed and PCLK clock must have
+                                             50% duty cycle). Refer to reference manual for details.
+                                       Note: In case of usage of asynchronous clock, the selected clock must be
+                                             preliminarily enabled at RCC top level.
+                                       Note: This parameter can be modified only if all ADC instances are disabled. */
+
+  uint32_t Resolution;            /*!< Configure the ADC resolution.
+                                       This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
+
+  uint32_t DataAlign;             /*!< Specify ADC data alignment in conversion data register (right or left).
+                                       Refer to reference manual for alignments formats versus resolutions.
+                                       This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
+
+  uint32_t GainCompensation;      /*!< Specify the ADC gain compensation coefficient to be applied to ADC raw conversion
+                                       data, based on following formula:
+                                         DATA = DATA(raw) * (gain compensation coef) / 4096
+                                       "2.12" bit format, unsigned: 2 bits exponents / 12 bits mantissa
+                                       Gain step is 1/4096 = 0.000244
+                                       Gain range is 0.0000 to 3.999756
+                                       This parameter value can be
+                                        0           Gain compensation will be disabled and coefficient set to 0
+                                        1 -> 0x3FFF Gain compensation will be enabled and coefficient set to specified
+                                                    value
+                                       Note: Gain compensation when enabled is applied to all channels. */
+
+  uint32_t ScanConvMode;          /*!< Configure the sequencer of ADC groups regular and injected.
+                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have
+                                       main sequence subdivided in successive parts.
+                                       If disabled: Conversion is performed in single mode (one channel converted, the
+                                                    one defined in rank 1). Parameters 'NbrOfConversion' and
+                                                    'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
+                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined
+                                                    by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each
+                                                    channel in sequencer). Scan direction is upward: from rank 1 to
+                                                    rank 'n'.
+                                       This parameter can be a value of @ref ADC_Scan_mode */
+
+  uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and
+                                       interruption: end of unitary conversion or end of sequence conversions.
+                                       This parameter can be a value of @ref ADC_EOCSelection. */
+
+  FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the
+                                       previous conversion (for ADC group regular) or previous sequence (for ADC group
+                                       injected) has been retrieved by user software, using function HAL_ADC_GetValue()
+                                       or HAL_ADCEx_InjectedGetValue().
+                                       This feature automatically adapts the frequency of ADC conversions triggers to
+                                       the speed of the system that reads the data. Moreover, this avoids risk of
+                                       overrun for low frequency applications.
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(),
+                                             HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC
+                                             flag (by CPU to free the IRQ pending event or by DMA).
+                                             Auto wait will work but fort a very short time, discarding its intended
+                                             benefit (except specific case of high load of CPU or DMA transfers which
+                                             can justify usage of auto wait).
+                                             Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on,
+                                             when ADC conversion data is needed:
+                                             use HAL_ADC_PollForConversion() to ensure that conversion is completed and
+                                             HAL_ADC_GetValue() to retrieve conversion result and trig another
+                                             conversion start. (in case of usage of ADC group injected, use the
+                                             equivalent functions HAL_ADCExInjected_Start(),
+                                             HAL_ADCEx_InjectedGetValue(), ...). */
+
+  FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion)
+                                           or continuous mode for ADC group regular, after the first ADC conversion
+                                           start trigger occurred (software start or external trigger). This parameter
+                                           can be set to ENABLE or DISABLE. */
+
+  uint32_t NbrOfConversion;       /*!< Specify the number of ranks that will be converted within the regular group
+                                       sequencer.
+                                       This parameter is dependent on ScanConvMode:
+                                        - sequencer configured to fully configurable:
+                                          Number of ranks in the scan sequence is configurable using this parameter.
+                                          Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to
+                                                parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
+                                                Afterwards, when all needed sequencer ranks are set, parameter
+                                                'NbrOfConversion' can be updated without modifying configuration of
+                                                sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded).
+                                        - sequencer configured to not fully configurable:
+                                          Number of ranks in the scan sequence is defined by number of channels set in
+                                          the sequence. This parameter is discarded.
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8.
+                                       Note: This parameter must be modified when no conversion is on going on regular
+                                             group (ADC disabled, or ADC enabled without continuous mode or external
+                                             trigger that could launch a conversion). */
+
+  FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed
+                                              in Complete-sequence/Discontinuous-sequence (main sequence subdivided in
+                                              successive parts).
+                                              Discontinuous mode is used only if sequencer is enabled (parameter
+                                              'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                              Discontinuous mode can be enabled only if continuous mode is disabled.
+                                              If continuous mode is enabled, this parameter setting is discarded.
+                                              This parameter can be set to ENABLE or DISABLE.
+                                              Note: On this STM32 series, ADC group regular number of discontinuous
+                                                    ranks increment is fixed to one-by-one. */
+
+  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the main sequence
+                                       of ADC group regular (parameter NbrOfConversion) will be subdivided.
+                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
+
+  uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion
+                                       start.
+                                       If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger
+                                       is used instead.
+                                       This parameter can be a value of @ref ADC_regular_external_trigger_source.
+                                       Caution: external trigger source is common to all ADC instances. */
+
+  uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start
+                                       If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
+                                       This parameter can be a value of @ref ADC_regular_external_trigger_edge */
+
+  uint32_t SamplingMode;          /*!< Select the sampling mode to be used for ADC group regular conversion.
+                                       This parameter can be a value of @ref ADC_regular_sampling_mode */
+
+  FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA
+                                              transfer stops when number of conversions is reached) or in continuous
+                                              mode (DMA transfer unlimited, whatever number of conversions).
+                                              This parameter can be set to ENABLE or DISABLE.
+                                              Note: In continuous mode, DMA must be configured in circular mode.
+                                                    Otherwise an overrun will be triggered when DMA buffer maximum
+                                                    pointer is reached. */
+
+  uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
+                                       This parameter applies to ADC group regular only.
+                                       This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
+                                       Note: In case of overrun set to data preserved and usage with programming model
+                                             with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of
+                                             conversion flags, this induces the release of the preserved data. If
+                                             needed, this data can be saved in function HAL_ADC_ConvCpltCallback(),
+                                             placed in user program code (called before end of conversion flags clear)
+                                       Note: Error reporting with respect to the conversion mode:
+                                             - Usage with ADC conversion by polling for event or interruption: Error is
+                                               reported only if overrun is set to data preserved. If overrun is set to
+                                               data overwritten, user can willingly not read all the converted data,
+                                               this is not considered as an erroneous case.
+                                             - Usage with ADC conversion by DMA: Error is reported whatever overrun
+                                               setting (DMA is expected to process all data from data register). */
+
+  FunctionalState OversamplingMode;       /*!< Specify whether the oversampling feature is enabled or disabled.
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: This parameter can be modified only if there is no conversion is
+                                                     ongoing on ADC groups regular and injected */
+
+  ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.
+                                               Caution: this setting overwrites the previous oversampling configuration
+                                                        if oversampling is already enabled. */
+
+} ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of ADC channel for regular group
+  * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')
+  *          - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion
+  *            on going on regular group.
+  *          - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on
+  *            regular and injected groups.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another
+  *         parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
+                                        This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+                                        Note: Depending on devices and ADC instances, some channels may not be available
+                                              on device package pins. Refer to device datasheet for channels
+                                              availability. */
+
+  uint32_t Rank;                   /*!< Specify the rank in the regular group sequencer.
+                                        This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS
+                                        Note: to disable a channel or change order of conversion sequencer, rank
+                                        containing a previous channel setting can be overwritten by the new channel
+                                        setting (or parameter number of conversions adjusted) */
+
+  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
+                                        Unit: ADC clock cycles
+                                        Conversion time is the addition of sampling time and processing time
+                                        (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
+                                        8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+                                        This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
+                                        Caution: This parameter applies to a channel that can be used into regular
+                                                 and/or injected group. It overwrites the last setting.
+                                        Note: In case of usage of internal measurement channels (VrefInt, Vbat, ...),
+                                              sampling time constraints must be respected (sampling time can be adjusted
+                                              in function of ADC clock frequency and sampling time setting).
+                                              Refer to device datasheet for timings values. */
+
+  uint32_t SingleDiff;             /*!< Select single-ended or differential input.
+                                        In differential mode: Differential measurement is carried out between the
+                                        selected channel 'i' (positive input) and channel 'i+1' (negative input).
+                                        Only channel 'i' has to be configured, channel 'i+1' is configured automatically
+                                        This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING
+                                        Caution: This parameter applies to a channel that can be used in a regular
+                                                 and/or injected group.
+                                                 It overwrites the last setting.
+                                        Note: Refer to Reference Manual to ensure the selected channel is available in
+                                              differential mode.
+                                        Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is
+                                              not usable separately.
+                                        Note: This parameter must be modified when ADC is disabled (before ADC start
+                                              conversion or after ADC stop conversion).
+                                              If ADC is enabled, this parameter setting is bypassed without error
+                                              reporting (as it can be the expected behavior in case of another parameter
+                                              update on the fly) */
+
+  uint32_t OffsetNumber;           /*!< Select the offset number
+                                        This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB
+                                        Caution: Only one offset is allowed per channel. This parameter overwrites the
+                                                 last setting. */
+
+  uint32_t Offset;                 /*!< Define the offset to be applied on the raw converted data.
+                                        Offset value must be a positive number.
+                                        Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter
+                                        must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
+                                        0x3FF, 0xFF or 0x3F respectively.
+                                        Note: This parameter must be modified when no conversion is on going on both
+                                              regular and injected groups (ADC disabled, or ADC enabled without
+                                              continuous mode or external trigger that could launch a conversion). */
+
+  uint32_t OffsetSign;                /*!< Define if the offset should be subtracted (negative sign) or added (positive
+                                            sign) from or to the raw converted data.
+                                            This parameter can be a value of @ref ADCEx_OffsetSign.
+                                            Note: This parameter must be modified when no conversion is on going on both
+                                                  regular and injected groups (ADC disabled, or ADC enabled without
+                                                  continuous mode or external trigger that could launch a conversion).*/
+  FunctionalState OffsetSaturation;   /*!< Define if the offset should be saturated upon under or over flow.
+                                        This parameter value can be ENABLE or DISABLE.
+                                        Note: This parameter must be modified when no conversion is on going on both
+                                              regular and injected groups (ADC disabled, or ADC enabled without
+                                              continuous mode or external trigger that could launch a conversion). */
+
+} ADC_ChannelConfTypeDef;
+
+/**
+  * @brief  Structure definition of ADC analog watchdog
+  * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion
+               on going on ADC groups regular and injected.
+  *          - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular and
+               injected groups.
+  */
+typedef struct
+{
+  uint32_t WatchdogNumber;    /*!< Select which ADC analog watchdog is monitoring the selected channel.
+                                   For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels
+                                                          by setting parameter 'WatchdogMode')
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls
+                                                                of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+                                   This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
+
+  uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.
+                                   For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all
+                                                          channels, ADC groups regular and-or injected.
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored by applying
+                                                                successively the AWD init structure. Channels on ADC
+                                                                group regular and injected are not differentiated: Set
+                                                                value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1
+                                                                channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor
+                                                                all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no
+                                                                channel.
+                                   This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+
+  uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
+                                   For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode'
+                                                          is configured on single channel (only 1 channel can be
+                                                          monitored).
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature,
+                                                                call successively the function HAL_ADC_AnalogWDGConfig()
+                                                                for each channel to be added (or removed with value
+                                                                'ADC_ANALOGWATCHDOG_NONE').
+                                   This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
+
+  FunctionalState ITMode;     /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
+                                   This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
+                                   number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
+                                   respectively.
+                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
+                                         resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
+                                         LSB are ignored.
+                                   Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+                                         impacted: the comparison of analog watchdog thresholds is done on
+                                         oversampling final computation (after ratio and shift application):
+                                         ADC data register bitfield [15:4] (12 most significant bits). */
+
+  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
+                                   number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
+                                   respectively.
+                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
+                                         resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
+                                         LSB are ignored.
+                                   Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+                                         impacted: the comparison of analog watchdog thresholds is done on
+                                         oversampling final computation (after ratio and shift application):
+                                         ADC data register bitfield [15:4] (12 most significant bits).*/
+
+  uint32_t FilteringConfig;   /*!< Specify whether filtering should be use and the number of samples to consider.
+                                   Before setting flag or raising interrupt, analog watchdog can wait to have several
+                                   consecutive out-of-window samples. This parameter allows to configure this number.
+                                   This parameter only applies to Analog watchdog 1. For others, use value
+                                   ADC_AWD_FILTERING_NONE.
+                                   This parameter can be a value of @ref ADC_analog_watchdog_filtering_config. */
+} ADC_AnalogWDGConfTypeDef;
+
+/**
+  * @brief  ADC group injected contexts queue configuration
+  * @note   Structure intended to be used only through structure "ADC_HandleTypeDef"
+  */
+typedef struct
+{
+  uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each
+                                              HAL_ADCEx_InjectedConfigChannel() call to finally initialize
+                                              JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
+
+  uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */
+} ADC_InjectionConfigTypeDef;
+
+/** @defgroup ADC_States ADC States
+  * @{
+  */
+
+/**
+  * @brief  HAL ADC state machine: ADC states definition (bitfields)
+  * @note   ADC state machine is managed by bitfields, state must be compared
+  *         with bit by bit.
+  *         For example:
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+  */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET             (0x00000000UL)   /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY             (0x00000001UL)   /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002UL)   /*!< ADC is busy due to an internal process (initialization,
+                                                              calibration, ...) */
+#define HAL_ADC_STATE_TIMEOUT           (0x00000004UL)   /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010UL)   /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020UL)   /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA         (0x00000040UL)   /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY          (0x00000100UL)   /*!< A conversion on ADC group regular is ongoing or can occur
+                                                              (either by continuous mode, external trigger, low power
+                                                              auto power-on (if feature available), multimode ADC master
+                                                              control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC           (0x00000200UL)   /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR           (0x00000400UL)   /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 series: End Of Sampling flag
+                                                              raised  */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY          (0x00001000UL)   /*!< A conversion on ADC group injected is ongoing or can occur
+                                                              (either by auto-injection mode, external trigger, low
+                                                              power auto power-on (if feature available), multimode
+                                                              ADC master control (if feature available)) */
+#define HAL_ADC_STATE_INJ_EOC           (0x00002000UL)   /*!< Conversion data available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF         (0x00004000UL)   /*!< Injected queue overflow occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1              (0x00010000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2              (0x00020000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3              (0x00040000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000UL)   /*!< ADC in multimode slave state, controlled by another ADC
+                                                              master (when feature available) */
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  ADC handle Structure definition
+  */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+{
+  ADC_TypeDef                   *Instance;                     /*!< Register base address */
+  ADC_InitTypeDef               Init;                          /*!< ADC initialization parameters and regular
+                                                                    conversions setting */
+  DMA_HandleTypeDef             *DMA_Handle;                   /*!< Pointer DMA Handler */
+  HAL_LockTypeDef               Lock;                          /*!< ADC locking object */
+  __IO uint32_t                 State;                         /*!< ADC communication state (bitmap of ADC states) */
+  __IO uint32_t                 ErrorCode;                     /*!< ADC Error code */
+  ADC_InjectionConfigTypeDef    InjectionConfig ;              /*!< ADC injected channel configuration build-up
+                                                                  structure */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
+  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer
+                                                                                 callback */
+  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
+  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
+  void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete
+                                                                                 callback */
+  void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue
+                                                                                 overflow callback */
+  void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 2 callback */
+  void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 3 callback */
+  void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc);         /*!< ADC end of sampling callback */
+  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
+  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+} ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL ADC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
+  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
+  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
+  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */
+  HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID       = 0x05U,  /*!< ADC group injected context queue overflow callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID   = 0x06U,  /*!< ADC analog watchdog 2 callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID   = 0x07U,  /*!< ADC analog watchdog 3 callback ID */
+  HAL_ADC_END_OF_SAMPLING_CB_ID         = 0x08U,  /*!< ADC end of sampling callback ID */
+  HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID          */
+  HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID        */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL ADC Callback pointer definition
+  */
+typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+  * @{
+  */
+#define HAL_ADC_ERROR_NONE              (0x00U)   /*!< No error                                    */
+#define HAL_ADC_ERROR_INTERNAL          (0x01U)   /*!< ADC peripheral internal error (problem of clocking,
+                                                       enable/disable, erroneous state, ...)       */
+#define HAL_ADC_ERROR_OVR               (0x02U)   /*!< Overrun error                               */
+#define HAL_ADC_ERROR_DMA               (0x04U)   /*!< DMA transfer error                          */
+#define HAL_ADC_ERROR_JQOVF             (0x08U)   /*!< Injected context queue overflow error       */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
+  * @{
+  */
+
+#define ADC_CLOCK_SYNC_PCLK_DIV1           (LL_ADC_CLOCK_SYNC_PCLK_DIV1)  /*!< ADC synchronous clock from AHB clock
+                                           without prescaler */
+#define ADC_CLOCK_SYNC_PCLK_DIV2           (LL_ADC_CLOCK_SYNC_PCLK_DIV2)  /*!< ADC synchronous clock from AHB clock
+                                           with prescaler division by 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4           (LL_ADC_CLOCK_SYNC_PCLK_DIV4)  /*!< ADC synchronous clock from AHB clock
+                                           with prescaler division by 4 */
+#define ADC_CLOCK_ASYNC_DIV1               (LL_ADC_CLOCK_ASYNC_DIV1)      /*!< ADC asynchronous clock without
+                                           prescaler */
+#define ADC_CLOCK_ASYNC_DIV2               (LL_ADC_CLOCK_ASYNC_DIV2)      /*!< ADC asynchronous clock with prescaler
+                                           division by 2   */
+#define ADC_CLOCK_ASYNC_DIV4               (LL_ADC_CLOCK_ASYNC_DIV4)      /*!< ADC asynchronous clock with prescaler
+                                           division by 4   */
+#define ADC_CLOCK_ASYNC_DIV6               (LL_ADC_CLOCK_ASYNC_DIV6)      /*!< ADC asynchronous clock with prescaler
+                                           division by 6   */
+#define ADC_CLOCK_ASYNC_DIV8               (LL_ADC_CLOCK_ASYNC_DIV8)      /*!< ADC asynchronous clock with prescaler
+                                           division by 8   */
+#define ADC_CLOCK_ASYNC_DIV10              (LL_ADC_CLOCK_ASYNC_DIV10)     /*!< ADC asynchronous clock with prescaler
+                                           division by 10  */
+#define ADC_CLOCK_ASYNC_DIV12              (LL_ADC_CLOCK_ASYNC_DIV12)     /*!< ADC asynchronous clock with prescaler
+                                           division by 12  */
+#define ADC_CLOCK_ASYNC_DIV16              (LL_ADC_CLOCK_ASYNC_DIV16)     /*!< ADC asynchronous clock with prescaler
+                                           division by 16  */
+#define ADC_CLOCK_ASYNC_DIV32              (LL_ADC_CLOCK_ASYNC_DIV32)     /*!< ADC asynchronous clock with prescaler
+                                           division by 32  */
+#define ADC_CLOCK_ASYNC_DIV64              (LL_ADC_CLOCK_ASYNC_DIV64)     /*!< ADC asynchronous clock with prescaler
+                                           division by 64  */
+#define ADC_CLOCK_ASYNC_DIV128             (LL_ADC_CLOCK_ASYNC_DIV128)    /*!< ADC asynchronous clock with prescaler
+                                           division by 128 */
+#define ADC_CLOCK_ASYNC_DIV256             (LL_ADC_CLOCK_ASYNC_DIV256)    /*!< ADC asynchronous clock with prescaler
+                                           division by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_RESOLUTION  ADC instance - Resolution
+  * @{
+  */
+#define ADC_RESOLUTION_12B                 (LL_ADC_RESOLUTION_12B)  /*!< ADC resolution 12 bits */
+#define ADC_RESOLUTION_10B                 (LL_ADC_RESOLUTION_10B)  /*!< ADC resolution 10 bits */
+#define ADC_RESOLUTION_8B                  (LL_ADC_RESOLUTION_8B)   /*!< ADC resolution  8 bits */
+#define ADC_RESOLUTION_6B                  (LL_ADC_RESOLUTION_6B)   /*!< ADC resolution  6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
+  * @{
+  */
+#define ADC_DATAALIGN_RIGHT                (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned
+                                           (alignment on data register LSB bit 0)*/
+#define ADC_DATAALIGN_LEFT                 (LL_ADC_DATA_ALIGN_LEFT)  /*!< ADC conversion data alignment: left aligned
+                                           (alignment on data register MSB bit 15)*/
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode
+  * @{
+  */
+#define ADC_SCAN_DISABLE         (0x00000000UL)       /*!< Scan mode disabled */
+#define ADC_SCAN_ENABLE          (0x00000001UL)       /*!< Scan mode enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
+  * @{
+  */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_SOFTWARE_START            (LL_ADC_REG_TRIG_SOFTWARE)                  /*!< ADC group regular conversion
+                                      trigger software start */
+#define ADC_EXTERNALTRIG_T1_TRGO      (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)             /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM1 TRGO. */
+#define ADC_EXTERNALTRIG_T1_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM1 TRGO2. */
+#define ADC_EXTERNALTRIG_T1_CC1       (LL_ADC_REG_TRIG_EXT_TIM1_CH1)              /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM1 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T1_CC2       (LL_ADC_REG_TRIG_EXT_TIM1_CH2)              /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM1 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIG_T1_CC3       (LL_ADC_REG_TRIG_EXT_TIM1_CH3)              /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM1 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIG_T2_TRGO      (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)             /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM2 TRGO. */
+#define ADC_EXTERNALTRIG_T2_CC1       (LL_ADC_REG_TRIG_EXT_TIM2_CH1)              /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM2 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T2_CC2       (LL_ADC_REG_TRIG_EXT_TIM2_CH2)              /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM2 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIG_T2_CC3       (LL_ADC_REG_TRIG_EXT_TIM2_CH3)              /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM2 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIG_T3_TRGO      (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)             /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM3 TRGO. */
+#define ADC_EXTERNALTRIG_T3_CC1       (LL_ADC_REG_TRIG_EXT_TIM3_CH1)              /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM3 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T3_CC4       (LL_ADC_REG_TRIG_EXT_TIM3_CH4)              /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM3 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIG_T4_TRGO      (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)             /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM4 TRGO. */
+#define ADC_EXTERNALTRIG_T4_CC1       (LL_ADC_REG_TRIG_EXT_TIM4_CH1)              /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM4 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T4_CC4       (LL_ADC_REG_TRIG_EXT_TIM4_CH4)              /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM4 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIG_T6_TRGO      (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)             /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM6 TRGO. */
+#define ADC_EXTERNALTRIG_T7_TRGO      (LL_ADC_REG_TRIG_EXT_TIM7_TRGO)             /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM7 TRGO. */
+#define ADC_EXTERNALTRIG_T8_TRGO      (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)             /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM8 TRGO. */
+#define ADC_EXTERNALTRIG_T8_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM8 TRGO2. */
+#define ADC_EXTERNALTRIG_T8_CC1       (LL_ADC_REG_TRIG_EXT_TIM8_CH1)              /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM8 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T15_TRGO     (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM15 TRGO. */
+#define ADC_EXTERNALTRIG_T20_TRGO     (LL_ADC_REG_TRIG_EXT_TIM20_TRGO)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM20 TRGO. */
+#define ADC_EXTERNALTRIG_T20_TRGO2    (LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)           /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM20 TRGO2. */
+#define ADC_EXTERNALTRIG_T20_CC1      (LL_ADC_REG_TRIG_EXT_TIM20_CH1)             /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM20 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIG_T20_CC2      (LL_ADC_REG_TRIG_EXT_TIM20_CH2)             /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM20 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIG_T20_CC3      (LL_ADC_REG_TRIG_EXT_TIM20_CH3)             /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM20 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIG_HRTIM_TRG1   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: HRTIMER ADC trigger 1 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG2   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG2)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: HRTIMER ADC trigger 2 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG3   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: HRTIMER ADC trigger 3 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG4   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG4)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: HRTIMER ADC trigger 4 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG5   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG5)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: HRTIMER ADC trigger 5 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG6   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG6)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: HRTIMER ADC trigger 6 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG7   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG7)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: HRTIMER ADC trigger 7 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG8   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG8)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: HRTIMER ADC trigger 8 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG9   (LL_ADC_REG_TRIG_EXT_HRTIM_TRG9)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: HRTIMER ADC trigger 9 event. */
+#define ADC_EXTERNALTRIG_HRTIM_TRG10  (LL_ADC_REG_TRIG_EXT_HRTIM_TRG10)           /*!< ADC group regular conversion
+                                      trigger from external peripheral: HRTIMER ADC trigger 10 event. */
+#define ADC_EXTERNALTRIG_EXT_IT2      (LL_ADC_REG_TRIG_EXT_EXTI_LINE2)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: external interrupt line 2. */
+#define ADC_EXTERNALTRIG_EXT_IT11     (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)           /*!< ADC group regular conversion
+                                      trigger from external peripheral: external interrupt line 11. */
+#define ADC_EXTERNALTRIG_LPTIM_OUT    (LL_ADC_REG_TRIG_EXT_LPTIM_OUT)             /*!< ADC group regular conversion
+                                      trigger from external peripheral: LPTIMER OUT event. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
+  * @{
+  */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000UL)                      /*!< ADC group regular trigger
+                                                disabled (SW start)*/
+#define ADC_EXTERNALTRIGCONVEDGE_RISING         (LL_ADC_REG_TRIG_EXT_RISING)        /*!< ADC group regular conversion
+                                                trigger polarity set to rising edge */
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING        (LL_ADC_REG_TRIG_EXT_FALLING)       /*!< ADC group regular conversion
+                                                trigger polarity set to falling edge */
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion
+                                                trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_sampling_mode ADC group regular sampling mode
+  * @{
+  */
+#define ADC_SAMPLING_MODE_NORMAL                (0x00000000UL)      /*!< ADC conversions sampling phase duration is
+                                                defined using  @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME */
+#define ADC_SAMPLING_MODE_BULB                  (ADC_CFGR2_BULB)    /*!< ADC conversions sampling phase starts
+                                                immediately after end of conversion, and stops upon trigger event.
+                                                Note: First conversion is using minimal sampling time
+                                                      (see @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME) */
+#define ADC_SAMPLING_MODE_TRIGGER_CONTROLED     (ADC_CFGR2_SMPTRIG) /*!< ADC conversions sampling phase is controlled
+                                                by trigger events:
+                                                Trigger rising edge  = start sampling
+                                                Trigger falling edge = stop sampling and start conversion */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
+  * @{
+  */
+#define ADC_EOC_SINGLE_CONV         (ADC_ISR_EOC)                 /*!< End of unitary conversion flag  */
+#define ADC_EOC_SEQ_CONV            (ADC_ISR_EOS)                 /*!< End of sequence conversions flag    */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
+  * @{
+  */
+#define ADC_OVR_DATA_PRESERVED             (LL_ADC_REG_OVR_DATA_PRESERVED)    /*!< ADC group regular behavior in case
+                                           of overrun: data preserved */
+#define ADC_OVR_DATA_OVERWRITTEN           (LL_ADC_REG_OVR_DATA_OVERWRITTEN)  /*!< ADC group regular behavior in case
+                                           of overrun: data overwritten */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
+  * @{
+  */
+#define ADC_REGULAR_RANK_1                 (LL_ADC_REG_RANK_1)  /*!< ADC group regular sequencer rank 1 */
+#define ADC_REGULAR_RANK_2                 (LL_ADC_REG_RANK_2)  /*!< ADC group regular sequencer rank 2 */
+#define ADC_REGULAR_RANK_3                 (LL_ADC_REG_RANK_3)  /*!< ADC group regular sequencer rank 3 */
+#define ADC_REGULAR_RANK_4                 (LL_ADC_REG_RANK_4)  /*!< ADC group regular sequencer rank 4 */
+#define ADC_REGULAR_RANK_5                 (LL_ADC_REG_RANK_5)  /*!< ADC group regular sequencer rank 5 */
+#define ADC_REGULAR_RANK_6                 (LL_ADC_REG_RANK_6)  /*!< ADC group regular sequencer rank 6 */
+#define ADC_REGULAR_RANK_7                 (LL_ADC_REG_RANK_7)  /*!< ADC group regular sequencer rank 7 */
+#define ADC_REGULAR_RANK_8                 (LL_ADC_REG_RANK_8)  /*!< ADC group regular sequencer rank 8 */
+#define ADC_REGULAR_RANK_9                 (LL_ADC_REG_RANK_9)  /*!< ADC group regular sequencer rank 9 */
+#define ADC_REGULAR_RANK_10                (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */
+#define ADC_REGULAR_RANK_11                (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */
+#define ADC_REGULAR_RANK_12                (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */
+#define ADC_REGULAR_RANK_13                (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */
+#define ADC_REGULAR_RANK_14                (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */
+#define ADC_REGULAR_RANK_15                (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */
+#define ADC_REGULAR_RANK_16                (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+  * @{
+  */
+#define ADC_SAMPLETIME_2CYCLES_5         (LL_ADC_SAMPLINGTIME_2CYCLES_5)    /*!< Sampling time 2.5 ADC clock cycles */
+#define ADC_SAMPLETIME_6CYCLES_5         (LL_ADC_SAMPLINGTIME_6CYCLES_5)    /*!< Sampling time 6.5 ADC clock cycles */
+#define ADC_SAMPLETIME_12CYCLES_5        (LL_ADC_SAMPLINGTIME_12CYCLES_5)   /*!< Sampling time 12.5 ADC clock cycles */
+#define ADC_SAMPLETIME_24CYCLES_5        (LL_ADC_SAMPLINGTIME_24CYCLES_5)   /*!< Sampling time 24.5 ADC clock cycles */
+#define ADC_SAMPLETIME_47CYCLES_5        (LL_ADC_SAMPLINGTIME_47CYCLES_5)   /*!< Sampling time 47.5 ADC clock cycles */
+#define ADC_SAMPLETIME_92CYCLES_5        (LL_ADC_SAMPLINGTIME_92CYCLES_5)   /*!< Sampling time 92.5 ADC clock cycles */
+#define ADC_SAMPLETIME_247CYCLES_5       (LL_ADC_SAMPLINGTIME_247CYCLES_5)  /*!< Sampling time 247.5 ADC clock cycles */
+#define ADC_SAMPLETIME_640CYCLES_5       (LL_ADC_SAMPLINGTIME_640CYCLES_5)  /*!< Sampling time 640.5 ADC clock cycles */
+#define ADC_SAMPLETIME_3CYCLES_5         (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5
+                                         ADC clock cycles. If selected, this sampling time replaces sampling time
+                                         2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_CHANNEL  ADC instance - Channel number
+  * @{
+  */
+/* Note: VrefInt, TempSensor and Vbat internal channels are not available on  */
+/*        all ADC instances (refer to Reference Manual).                      */
+#define ADC_CHANNEL_0                      (LL_ADC_CHANNEL_0)              /*!< External channel (GPIO pin) ADCx_IN0  */
+#define ADC_CHANNEL_1                      (LL_ADC_CHANNEL_1)              /*!< External channel (GPIO pin) ADCx_IN1  */
+#define ADC_CHANNEL_2                      (LL_ADC_CHANNEL_2)              /*!< External channel (GPIO pin) ADCx_IN2  */
+#define ADC_CHANNEL_3                      (LL_ADC_CHANNEL_3)              /*!< External channel (GPIO pin) ADCx_IN3  */
+#define ADC_CHANNEL_4                      (LL_ADC_CHANNEL_4)              /*!< External channel (GPIO pin) ADCx_IN4  */
+#define ADC_CHANNEL_5                      (LL_ADC_CHANNEL_5)              /*!< External channel (GPIO pin) ADCx_IN5  */
+#define ADC_CHANNEL_6                      (LL_ADC_CHANNEL_6)              /*!< External channel (GPIO pin) ADCx_IN6  */
+#define ADC_CHANNEL_7                      (LL_ADC_CHANNEL_7)              /*!< External channel (GPIO pin) ADCx_IN7  */
+#define ADC_CHANNEL_8                      (LL_ADC_CHANNEL_8)              /*!< External channel (GPIO pin) ADCx_IN8  */
+#define ADC_CHANNEL_9                      (LL_ADC_CHANNEL_9)              /*!< External channel (GPIO pin) ADCx_IN9  */
+#define ADC_CHANNEL_10                     (LL_ADC_CHANNEL_10)             /*!< External channel (GPIO pin) ADCx_IN10 */
+#define ADC_CHANNEL_11                     (LL_ADC_CHANNEL_11)             /*!< External channel (GPIO pin) ADCx_IN11 */
+#define ADC_CHANNEL_12                     (LL_ADC_CHANNEL_12)             /*!< External channel (GPIO pin) ADCx_IN12 */
+#define ADC_CHANNEL_13                     (LL_ADC_CHANNEL_13)             /*!< External channel (GPIO pin) ADCx_IN13 */
+#define ADC_CHANNEL_14                     (LL_ADC_CHANNEL_14)             /*!< External channel (GPIO pin) ADCx_IN14 */
+#define ADC_CHANNEL_15                     (LL_ADC_CHANNEL_15)             /*!< External channel (GPIO pin) ADCx_IN15 */
+#define ADC_CHANNEL_16                     (LL_ADC_CHANNEL_16)             /*!< External channel (GPIO pin) ADCx_IN16 */
+#define ADC_CHANNEL_17                     (LL_ADC_CHANNEL_17)             /*!< External channel (GPIO pin) ADCx_IN17 */
+#define ADC_CHANNEL_18                     (LL_ADC_CHANNEL_18)             /*!< External channel (GPIO pin) ADCx_IN18 */
+#define ADC_CHANNEL_VREFINT                (LL_ADC_CHANNEL_VREFINT)        /*!< Internal channel VrefInt: Internal
+                                           voltage reference. On this STM32 series, ADC channel available on all
+                                           instances but ADC2. */
+#define ADC_CHANNEL_TEMPSENSOR_ADC1        (LL_ADC_CHANNEL_TEMPSENSOR_ADC1) /*!< Internal channel Temperature sensor.
+                                           On this STM32 series, ADC channel available only on ADC1 instance. */
+#define ADC_CHANNEL_TEMPSENSOR_ADC5        (LL_ADC_CHANNEL_TEMPSENSOR_ADC5) /*!< Internal channel Temperature sensor.
+                                           On this STM32 series, ADC channel available only on ADC5 instance.
+                                           Refer to device datasheet for ADC5 availability */
+#define ADC_CHANNEL_VBAT                   (LL_ADC_CHANNEL_VBAT)           /*!< Internal channel Vbat/3: Vbat voltage
+                                           through a divider ladder of factor 1/3 to have channel voltage always below
+                                           Vdda.
+                                           On this STM32 series, ADC channel available on all Instances but ADC2 & ADC4.
+                                           Refer to device datasheet for ADC4 availability */
+#define ADC_CHANNEL_VOPAMP1                (LL_ADC_CHANNEL_VOPAMP1)        /*!< Internal channel OPAMP1 output.
+                                           On this STM32 series, ADC channel available only on ADC1 instance. */
+#define ADC_CHANNEL_VOPAMP2                (LL_ADC_CHANNEL_VOPAMP2)        /*!< Internal channel OPAMP2 output.
+                                           On this STM32 series, ADC channel available only on ADC2 instance. */
+#define ADC_CHANNEL_VOPAMP3_ADC2           (LL_ADC_CHANNEL_VOPAMP3_ADC2)   /*!< Internal channel OPAMP3 output.
+                                           On this STM32 series, ADC channel available only on ADC2 instance. */
+#define ADC_CHANNEL_VOPAMP3_ADC3           (LL_ADC_CHANNEL_VOPAMP3_ADC3)   /*!< Internal channel OPAMP3 output.
+                                           On this STM32 series, ADC channel available only on ADC3 instance.
+                                           Refer to device datasheet for ADC3 availability */
+#define ADC_CHANNEL_VOPAMP4                (LL_ADC_CHANNEL_VOPAMP4)        /*!< Internal channel OPAMP4 output.
+                                           On this STM32 series, ADC channel available only on ADC5 instance.
+                                           Refer to device datasheet for ADC5 availability */
+#define ADC_CHANNEL_VOPAMP5                (LL_ADC_CHANNEL_VOPAMP5)        /*!< Internal channel OPAMP5 output.
+                                           On this STM32 series, ADC channel available only on ADC5 instance.
+                                           Refer to device datasheet for ADC5 availability */
+#define ADC_CHANNEL_VOPAMP6                (LL_ADC_CHANNEL_VOPAMP6)        /*!< Internal channel OPAMP6 output.
+                                           On this STM32 series, ADC channel available only on ADC4 instance.
+                                           Refer to device datasheet for ADC4 availability */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number
+  * @{
+  */
+#define ADC_ANALOGWATCHDOG_1               (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
+#define ADC_ANALOGWATCHDOG_2               (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
+#define ADC_ANALOGWATCHDOG_3               (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_filtering_config ADC analog watchdog (AWD) filtering configuration
+  * @{
+  */
+#define ADC_AWD_FILTERING_NONE          (0x00000000UL)                            /*!< ADC AWD no filtering, one
+out-of-window sample to raise flag or interrupt */
+#define ADC_AWD_FILTERING_2SAMPLES      ((ADC_TR1_AWDFILT_0))                     /*!< ADC AWD 2 consecutives
+                                        out-of-window samples to raise flag or interrupt */
+#define ADC_AWD_FILTERING_3SAMPLES      ((ADC_TR1_AWDFILT_1))                     /*!< ADC AWD 3 consecutives
+                                        out-of-window samples to raise flag or interrupt */
+#define ADC_AWD_FILTERING_4SAMPLES      ((ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 4 consecutives
+                                        out-of-window samples to raise flag or interrupt */
+#define ADC_AWD_FILTERING_5SAMPLES      ((ADC_TR1_AWDFILT_2))                     /*!< ADC AWD 5 consecutives
+                                        out-of-window samples to raise flag or interrupt */
+#define ADC_AWD_FILTERING_6SAMPLES      ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0)) /*!< ADC AWD 6 consecutives
+                                        out-of-window samples to raise flag or interrupt */
+#define ADC_AWD_FILTERING_7SAMPLES      ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1)) /*!< ADC AWD 7 consecutives
+                                        out-of-window samples to raise flag or interrupt */
+#define ADC_AWD_FILTERING_8SAMPLES      ((ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \
+                                          | ADC_TR1_AWDFILT_0))                     /*!< ADC AWD 8 consecutives
+                                        out-of-window samples to raise flag or interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode
+  * @{
+  */
+#define ADC_ANALOGWATCHDOG_NONE                 (0x00000000UL)                         /*!< ADC AWD not selected */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG           (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)   /*!< ADC AWD applied to a regular
+                                                group single channel */
+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC         (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)  /*!< ADC AWD applied to an
+                                                injected group single channel */
+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN\
+                                                 | ADC_CFGR_JAWD1EN)                    /*!< ADC AWD applied to a regular
+                                                and injected groups single channel */
+#define ADC_ANALOGWATCHDOG_ALL_REG              (ADC_CFGR_AWD1EN)                      /*!< ADC AWD applied to regular
+                                                group all channels */
+#define ADC_ANALOGWATCHDOG_ALL_INJEC            (ADC_CFGR_JAWD1EN)                     /*!< ADC AWD applied to injected
+                                                group all channels */
+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC         (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)   /*!< ADC AWD applied to regular
+                                                and injected groups all channels */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_RATIO  Oversampling - Ratio
+  * @{
+  */
+/**
+  * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed
+  *       to result as the ADC oversampling conversion data (before potential shift)
+  */
+#define ADC_OVERSAMPLING_RATIO_2           (LL_ADC_OVS_RATIO_2)    /*!< ADC oversampling ratio    2 */
+#define ADC_OVERSAMPLING_RATIO_4           (LL_ADC_OVS_RATIO_4)    /*!< ADC oversampling ratio    4 */
+#define ADC_OVERSAMPLING_RATIO_8           (LL_ADC_OVS_RATIO_8)    /*!< ADC oversampling ratio    8 */
+#define ADC_OVERSAMPLING_RATIO_16          (LL_ADC_OVS_RATIO_16)   /*!< ADC oversampling ratio   16 */
+#define ADC_OVERSAMPLING_RATIO_32          (LL_ADC_OVS_RATIO_32)   /*!< ADC oversampling ratio   32 */
+#define ADC_OVERSAMPLING_RATIO_64          (LL_ADC_OVS_RATIO_64)   /*!< ADC oversampling ratio   64 */
+#define ADC_OVERSAMPLING_RATIO_128         (LL_ADC_OVS_RATIO_128)  /*!< ADC oversampling ratio  128 */
+#define ADC_OVERSAMPLING_RATIO_256         (LL_ADC_OVS_RATIO_256)  /*!< ADC oversampling ratio  256 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_SHIFT  Oversampling - Data shift
+  * @{
+  */
+/**
+  * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling
+  *       conversion data)
+  */
+#define ADC_RIGHTBITSHIFT_NONE             (LL_ADC_OVS_SHIFT_NONE)    /*!< ADC oversampling no shift   */
+#define ADC_RIGHTBITSHIFT_1                (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */
+#define ADC_RIGHTBITSHIFT_2                (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */
+#define ADC_RIGHTBITSHIFT_3                (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */
+#define ADC_RIGHTBITSHIFT_4                (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */
+#define ADC_RIGHTBITSHIFT_5                (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */
+#define ADC_RIGHTBITSHIFT_6                (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */
+#define ADC_RIGHTBITSHIFT_7                (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */
+#define ADC_RIGHTBITSHIFT_8                (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
+  * @{
+  */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER   (LL_ADC_OVS_REG_CONT)          /*!< ADC oversampling discontinuous mode:
+                                           continuous mode (all conversions of OVS ratio are done from 1 trigger) */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER    (LL_ADC_OVS_REG_DISCONT)       /*!< ADC oversampling discontinuous mode:
+                                           discontinuous mode (each conversion of OVS ratio needs a trigger) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG  Oversampling - Oversampling scope for ADC group regular
+  * @{
+  */
+#define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained
+                                           during injection sequence */
+#define ADC_REGOVERSAMPLING_RESUMED_MODE   (LL_ADC_OVS_GRP_REGULAR_RESUMED)   /*!< Oversampling buffer zeroed during
+                                           injection sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Event_type ADC Event type
+  * @{
+  */
+/**
+  * @note Analog watchdog 1 is available on all stm32 series
+  *       Analog watchdog 2 and 3 are not available on all series
+  */
+#define ADC_EOSMP_EVENT          (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
+#define ADC_AWD1_EVENT           (ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog)       */
+#define ADC_AWD2_EVENT           (ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog) */
+#define ADC_AWD3_EVENT           (ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog) */
+#define ADC_OVR_EVENT            (ADC_FLAG_OVR)   /*!< ADC overrun event */
+#define ADC_JQOVF_EVENT          (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */
+/**
+  * @}
+  */
+#define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility
+                                                          with other STM32 devices having only one analog watchdog */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+  * @{
+  */
+#define ADC_IT_RDY           ADC_IER_ADRDYIE    /*!< ADC Ready interrupt source */
+#define ADC_IT_EOSMP         ADC_IER_EOSMPIE    /*!< ADC End of sampling interrupt source */
+#define ADC_IT_EOC           ADC_IER_EOCIE      /*!< ADC End of regular conversion interrupt source */
+#define ADC_IT_EOS           ADC_IER_EOSIE      /*!< ADC End of regular sequence of conversions interrupt source */
+#define ADC_IT_OVR           ADC_IER_OVRIE      /*!< ADC overrun interrupt source */
+#define ADC_IT_JEOC          ADC_IER_JEOCIE     /*!< ADC End of injected conversion interrupt source */
+#define ADC_IT_JEOS          ADC_IER_JEOSIE     /*!< ADC End of injected sequence of conversions interrupt source */
+#define ADC_IT_AWD1          ADC_IER_AWD1IE     /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
+#define ADC_IT_AWD2          ADC_IER_AWD2IE     /*!< ADC Analog watchdog 2 interrupt source (additional analog
+                             watchdog) */
+#define ADC_IT_AWD3          ADC_IER_AWD3IE     /*!< ADC Analog watchdog 3 interrupt source (additional analog
+                             watchdog) */
+#define ADC_IT_JQOVF         ADC_IER_JQOVFIE    /*!< ADC Injected Context Queue Overflow interrupt source */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+  * @{
+  */
+#define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
+#define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
+#define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */
+#define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */
+#define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog) */
+#define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */
+#define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */
+#define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+  * @{
+  */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+  * @brief Return resolution bits in CFGR register RES[1:0] field.
+  * @param __HANDLE__ ADC handle
+  * @retval Value of bitfield RES in CFGR register.
+  */
+#define ADC_GET_RESOLUTION(__HANDLE__)                                         \
+  (LL_ADC_GetResolution((__HANDLE__)->Instance))
+
+/**
+  * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+  * @brief Simultaneously clear and set specific bits of the handle State.
+  * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+  *        the first parameter is the ADC handle State, the second parameter is the
+  *        bit field to clear, the third and last parameter is the bit field to set.
+  * @retval None
+  */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+  * @brief Verify that a given value is aligned with the ADC resolution range.
+  * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
+  * @param __ADC_VALUE__ value checked against the resolution.
+  * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
+  */
+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
+  ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
+
+/**
+  * @brief Verify the length of the scheduled regular conversions group.
+  * @param __LENGTH__ number of programmed conversions.
+  * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions)
+  *         or RESET (__LENGTH__ is null or too large)
+  */
+#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
+
+
+/**
+  * @brief Verify the number of scheduled regular conversions in discontinuous mode.
+  * @param NUMBER number of scheduled regular conversions in discontinuous mode.
+  * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode)
+  *         or RESET (NUMBER is null or too large)
+  */
+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
+
+
+/**
+  * @brief Verify the ADC clock setting.
+  * @param __ADC_CLOCK__ programmed ADC clock.
+  * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)
+  */
+#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \
+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
+
+/**
+  * @brief Verify the ADC resolution setting.
+  * @param __RESOLUTION__ programmed ADC resolution.
+  * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+  */
+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)  || \
+                                           ((__RESOLUTION__) == ADC_RESOLUTION_6B)    )
+
+/**
+  * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
+  * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
+  * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
+  */
+#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
+                                                    ((__RESOLUTION__) == ADC_RESOLUTION_6B)   )
+
+/**
+  * @brief Verify the ADC converted data alignment.
+  * @param __ALIGN__ programmed ADC converted data alignment.
+  * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
+  */
+#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
+                                      ((__ALIGN__) == ADC_DATAALIGN_LEFT)    )
+
+/**
+  * @brief Verify the ADC gain compensation.
+  * @param __GAIN_COMPENSATION__ programmed ADC gain compensation coefficient.
+  * @retval SET (__GAIN_COMPENSATION__ is a valid value) or RESET (__GAIN_COMPENSATION__ is invalid)
+  */
+#define IS_ADC_GAIN_COMPENSATION(__GAIN_COMPENSATION__) ((__GAIN_COMPENSATION__) <= 16393UL)
+
+/**
+  * @brief Verify the ADC scan mode.
+  * @param __SCAN_MODE__ programmed ADC scan mode.
+  * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)
+  */
+#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
+                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )
+
+/**
+  * @brief Verify the ADC edge trigger setting for regular group.
+  * @param __EDGE__ programmed ADC edge trigger setting.
+  * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+  */
+#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
+
+/**
+  * @brief Verify the ADC regular conversions external trigger.
+  * @param __HANDLE__ ADC handle
+  * @param __REGTRIG__ programmed ADC regular conversions external trigger.
+  * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2)       || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG1)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG3)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG5)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG6)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG7)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG8)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG9)      || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG10)     || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
+                                                 ((((__HANDLE__)->Instance == ADC1) || \
+                                                   ((__HANDLE__)->Instance == ADC2)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2)       || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3)       || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)))    || \
+                                                 ((((__HANDLE__)->Instance == ADC3) || \
+                                                   ((__HANDLE__)->Instance == ADC4) || \
+                                                   ((__HANDLE__)->Instance == ADC5)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG2)    || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_HRTIM_TRG4)    || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2)))     || \
+                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2)       || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
+                                                 ((((__HANDLE__)->Instance == ADC1) || \
+                                                   ((__HANDLE__)->Instance == ADC2)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2)       || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3)       || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)))    || \
+                                                 ((((__HANDLE__)->Instance == ADC3) || \
+                                                   ((__HANDLE__)->Instance == ADC4) || \
+                                                   ((__HANDLE__)->Instance == ADC5)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2)))     || \
+                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )
+#elif defined(STM32G471xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
+                                                 ((((__HANDLE__)->Instance == ADC1) || \
+                                                   ((__HANDLE__)->Instance == ADC2)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)))    || \
+                                                 ((((__HANDLE__)->Instance == ADC3)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2)))     || \
+                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )
+#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)        || \
+                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
+#define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)          || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T7_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO)        || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_TRGO2)       || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC1)         || \
+                                                 ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM_OUT)       || \
+                                                 ((((__HANDLE__)->Instance == ADC1) || \
+                                                   ((__HANDLE__)->Instance == ADC2)) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC2)       || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T20_CC3)       || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)))    || \
+                                                 (((__HANDLE__)->Instance == ADC3) && \
+                                                  (((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC3)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_CC1)        || \
+                                                   ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT2)))     || \
+                                                 ((__REGTRIG__) == ADC_SOFTWARE_START)           )
+#endif /* STM32G4xx */
+
+/**
+  * @brief Verify the ADC regular conversions external trigger.
+  * @param __SAMPLINGMODE__ programmed ADC regular conversions external trigger.
+  * @retval SET (__SAMPLINGMODE__ is a valid value) or RESET (__SAMPLINGMODE__ is invalid)
+  */
+#define IS_ADC_SAMPLINGMODE(__SAMPLINGMODE__) (((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_NORMAL)          || \
+                                               ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_BULB)            || \
+                                               ((__SAMPLINGMODE__) == ADC_SAMPLING_MODE_TRIGGER_CONTROLED)  )
+
+/**
+  * @brief Verify the ADC regular conversions check for converted data availability.
+  * @param __EOC_SELECTION__ converted data availability check.
+  * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)
+  */
+#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \
+                                                 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)  )
+
+/**
+  * @brief Verify the ADC regular conversions overrun handling.
+  * @param __OVR__ ADC regular conversions overrun handling.
+  * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)
+  */
+#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \
+                                 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )
+
+/**
+  * @brief Verify the ADC conversions sampling time.
+  * @param __TIME__ ADC conversions sampling time.
+  * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)
+  */
+#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \
+                                      ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5)   || \
+                                      ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5)   || \
+                                      ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5)  || \
+                                      ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \
+                                      ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5)   )
+
+/**
+  * @brief Verify the ADC regular channel setting.
+  * @param  __CHANNEL__ programmed ADC regular channel.
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \
+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )
+
+/**
+  * @}
+  */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Fixed timeout values for ADC conversion (including sampling time)        */
+/* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111        */
+/* Maximum conversion time is 12.5 + Maximum sampling time                  */
+/*                       or 12.5  + 640.5 = 653 ADC clock cycles            */
+/* Minimum ADC Clock frequency is 0.14 MHz                                  */
+/* Maximum conversion time is                                               */
+/*              653 / 0.14 MHz = 4.66 ms                                    */
+#define ADC_STOP_CONVERSION_TIMEOUT     ( 5UL)     /*!< ADC stop time-out value */
+
+/* Delay for temperature sensor stabilization time.                         */
+/* Maximum delay is 120us (refer device datasheet, parameter tSTART).       */
+/* Unit: us                                                                 */
+#define ADC_TEMPSENSOR_DELAY_US         (LL_ADC_DELAY_TEMPSENSOR_STAB_US)
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+  * @{
+  */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user.                                                                */
+
+/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
+  * @{
+  */
+
+/** @brief  Reset ADC handle state.
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  do{                                                                          \
+    (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
+    (__HANDLE__)->MspInitCallback = NULL;                                      \
+    (__HANDLE__)->MspDeInitCallback = NULL;                                    \
+  } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @brief Enable ADC interrupt.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC Interrupt
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
+  *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
+  (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+  * @brief Disable ADC interrupt.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC Interrupt
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
+  *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
+  (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC interrupt source to check
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source
+  *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.
+  * @retval State of interruption (SET or RESET)
+  */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
+  (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief Check whether the specified ADC flag is set or not.
+  * @param __HANDLE__ ADC handle
+  * @param __FLAG__ ADC flag
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_FLAG_RDY     ADC Ready flag
+  *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
+  *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
+  *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
+  *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag
+  *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.
+  * @retval State of flag (TRUE or FALSE).
+  */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
+  ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief Clear the specified ADC flag.
+  * @param __HANDLE__ ADC handle
+  * @param __FLAG__ ADC flag
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_FLAG_RDY     ADC Ready flag
+  *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
+  *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
+  *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
+  *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag
+  *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.
+  * @retval None
+  */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
+  (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get ADC channel number in decimal format
+  *         from literals ADC_CHANNEL_x.
+  * @note   Example:
+  *           __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
+  *           will return decimal number "4".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned, either defined with number
+  *         or with bitfield (only one bit must be set).
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1                 (8)
+  *         @arg @ref ADC_CHANNEL_2                 (8)
+  *         @arg @ref ADC_CHANNEL_3                 (8)
+  *         @arg @ref ADC_CHANNEL_4                 (8)
+  *         @arg @ref ADC_CHANNEL_5                 (8)
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *            (fADC) to convert in 12-bit resolution.\n
+  * @retval Value between Min_Data=0 and Max_Data=18
+  */
+#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                           \
+  __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
+
+/**
+  * @brief  Helper macro to get ADC channel in literal format ADC_CHANNEL_x
+  *         from number in decimal format.
+  * @note   Example:
+  *           __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+  *           will return a data equivalent to "ADC_CHANNEL_4".
+  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1                 (8)
+  *         @arg @ref ADC_CHANNEL_2                 (8)
+  *         @arg @ref ADC_CHANNEL_3                 (8)
+  *         @arg @ref ADC_CHANNEL_4                 (8)
+  *         @arg @ref ADC_CHANNEL_5                 (8)
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *          -  On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
+  *             more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC)
+  *             to convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                        \
+  __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
+
+/**
+  * @brief  Helper macro to determine whether the selected channel
+  *         corresponds to literal definitions of driver.
+  * @note   The different literal definitions of ADC channels are:
+  *         - ADC internal channel:
+  *           ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
+  *         - ADC external channel (channel connected to a GPIO pin):
+  *           ADC_CHANNEL_1, ADC_CHANNEL_2, ...
+  * @note   The channel parameter must be a value defined from literal
+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+  *         ADC_CHANNEL_TEMPSENSOR, ...),
+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
+  *         must not be a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1                 (8)
+  *         @arg @ref ADC_CHANNEL_2                 (8)
+  *         @arg @ref ADC_CHANNEL_3                 (8)
+  *         @arg @ref ADC_CHANNEL_4                 (8)
+  *         @arg @ref ADC_CHANNEL_5                 (8)
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *            (fADC) to convert in 12-bit resolution.\n
+  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
+  *         connected to a GPIO pin).
+  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+  */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                             \
+  __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
+
+/**
+  * @brief  Helper macro to convert a channel defined from parameter
+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+  *         ADC_CHANNEL_TEMPSENSOR, ...),
+  *         to its equivalent parameter definition of a ADC external channel
+  *         (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
+  * @note   The channel parameter can be, additionally to a value
+  *         defined from parameter definition of a ADC internal channel
+  *         (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
+  *         a value defined from parameter definition of
+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is returned
+  *         from ADC registers.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1                 (8)
+  *         @arg @ref ADC_CHANNEL_2                 (8)
+  *         @arg @ref ADC_CHANNEL_3                 (8)
+  *         @arg @ref ADC_CHANNEL_4                 (8)
+  *         @arg @ref ADC_CHANNEL_5                 (8)
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *            (fADC) to convert in 12-bit resolution.\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  */
+#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                    \
+  __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
+
+/**
+  * @brief  Helper macro to determine whether the internal channel
+  *         selected is available on the ADC instance selected.
+  * @note   The channel parameter must be a value defined from parameter
+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+  *         ADC_CHANNEL_TEMPSENSOR, ...),
+  *         must not be a value defined from parameter definition of
+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __ADC_INSTANCE__ ADC instance
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+  *         Value "1" if the internal channel selected is available on the ADC instance selected.
+  */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Helper macro to get the ADC multimode conversion data of ADC master
+  *         or ADC slave from raw value with both ADC conversion data concatenated.
+  * @note   This macro is intended to be used when multimode transfer by DMA
+  *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+  *         In this case the transferred data need to processed with this macro
+  *         to separate the conversion data of ADC master and ADC slave.
+  * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_MASTER
+  *         @arg @ref LL_ADC_MULTI_SLAVE
+  * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \
+  __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Helper macro to select the ADC common instance
+  *         to which is belonging the selected ADC instance.
+  * @note   ADC common register instance can be used for:
+  *         - Set parameters common to several ADC instances
+  *         - Multimode (for devices with several ADC instances)
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @param  __ADCx__ ADC instance
+  * @retval ADC common register instance
+  */
+#define __HAL_ADC_COMMON_INSTANCE(__ADCx__)                                    \
+  __LL_ADC_COMMON_INSTANCE((__ADCx__))
+
+/**
+  * @brief  Helper macro to check if all ADC instances sharing the same
+  *         ADC common instance are disabled.
+  * @note   This check is required by functions with setting conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @note   On devices with only 1 ADC common instance, parameter of this macro
+  *         is useless and can be ignored (parameter kept for compatibility
+  *         with devices featuring several ADC common instances).
+  * @param  __ADCXY_COMMON__ ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value "0" if all ADC instances sharing the same ADC common instance
+  *         are disabled.
+  *         Value "1" if at least one ADC instance sharing the same ADC common instance
+  *         is enabled.
+  */
+#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
+
+/**
+  * @brief  Helper macro to define the ADC conversion data full-scale digital
+  *         value corresponding to the selected ADC resolution.
+  * @note   ADC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data full-scale digital value
+  */
+#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+  __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to convert the ADC conversion data from
+  *         a resolution to another resolution.
+  * @param  __DATA__ ADC conversion data to be converted
+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data to the requested resolution
+  */
+#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+                                          __ADC_RESOLUTION_CURRENT__,\
+                                          __ADC_RESOLUTION_TARGET__) \
+__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
+                                 (__ADC_RESOLUTION_CURRENT__),\
+                                 (__ADC_RESOLUTION_TARGET__))
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                       __ADC_DATA__,\
+                                       __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+                              (__ADC_DATA__),\
+                              (__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value)
+  *         in differential ended mode.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __HAL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                            __ADC_DATA__,\
+                                            __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+                                   (__ADC_DATA__),\
+                                   (__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to calculate analog reference voltage (Vref+)
+  *         (unit: mVolt) from ADC conversion data of internal voltage
+  *         reference VrefInt.
+  * @note   Computation is using VrefInt calibration value
+  *         stored in system memory for each device during production.
+  * @note   This voltage depends on user board environment: voltage level
+  *         connected to pin Vref+.
+  *         On devices with small package, the pin Vref+ is not present
+  *         and internally bonded to pin Vdda.
+  * @note   On this STM32 series, calibration data of internal voltage reference
+  *         VrefInt corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         internal voltage reference VrefInt.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *         of internal voltage reference VrefInt (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval Analog reference voltage (unit: mV)
+  */
+#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+                                          __ADC_RESOLUTION__) \
+__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
+                                 (__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor calibration values
+  *         stored in system memory for each device during production.
+  * @note   Calculation formula:
+  *           Temperature = ((TS_ADC_DATA - TS_CAL1)
+  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
+  *                Avg_Slope = (TS_CAL2 - TS_CAL1)
+  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL1 (calibrated in factory)
+  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL2 (calibrated in factory)
+  *         Caution: Calculation relevancy under reserve that calibration
+  *                  parameters are correct (address and data).
+  *                  To calculate temperature using temperature sensor
+  *                  datasheet typical values (generic values less, therefore
+  *                  less accurate than calibrated values),
+  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   On this STM32 series, calibration data of temperature sensor
+  *         corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         temperature sensor.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+  *                                 temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
+  *                                 sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+                                   __TEMPSENSOR_ADC_DATA__,\
+                                   __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\
+                          (__TEMPSENSOR_ADC_DATA__),\
+                          (__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor typical values
+  *         (refer to device datasheet).
+  * @note   Calculation formula:
+  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+  *                         / Avg_Slope + CALx_TEMP
+  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
+  *                                   (unit: digital value)
+  *                Avg_Slope        = temperature sensor slope
+  *                                   (unit: uV/Degree Celsius)
+  *                TS_TYP_CALx_VOLT = temperature sensor digital value at
+  *                                   temperature CALx_TEMP (unit: mV)
+  *         Caution: Calculation relevancy under reserve the temperature sensor
+  *                  of the current device has characteristics in line with
+  *                  datasheet typical values.
+  *                  If temperature sensor calibration values are available on
+  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+  *                  temperature calculation will be more accurate using
+  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   ADC measurement data must correspond to a resolution of 12bits
+  *         (full scale digital value 4095). If not the case, the data must be
+  *         preliminarily rescaled to an equivalent resolution of 12 bits.
+  * @param  __TEMPSENSOR_TYP_AVGSLOPE__    Device datasheet data: Temperature sensor slope typical value
+                                           (unit: uV/DegCelsius).
+  *                                        On STM32G4, refer to device datasheet parameter "Avg_Slope".
+  * @param  __TEMPSENSOR_TYP_CALX_V__      Device datasheet data: Temperature sensor voltage typical value (at
+                                           temperature and Vref+ defined in parameters below) (unit: mV).
+  *                                        On STM32G4, refer to device datasheet parameter "V30"
+                                           (corresponding to TS_CAL1).
+  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see
+                                                                 parameter above) is corresponding (unit: mV)
+  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+                                              __TEMPSENSOR_TYP_CALX_V__,\
+                                              __TEMPSENSOR_CALX_TEMP__,\
+                                              __VREFANALOG_VOLTAGE__,\
+                                              __TEMPSENSOR_ADC_DATA__,\
+                                              __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
+                                     (__TEMPSENSOR_TYP_CALX_V__),\
+                                     (__TEMPSENSOR_CALX_TEMP__),\
+                                     (__VREFANALOG_VOLTAGE__),\
+                                     (__TEMPSENSOR_ADC_DATA__),\
+                                     (__ADC_RESOLUTION__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Include ADC HAL Extended module */
+#include "stm32g4xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+  * @brief    Initialization and Configuration functions
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+                                           pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions  *****************************************************/
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t                HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
+
+/* ADC sampling control */
+HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig);
+HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc,
+                                                const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig);
+
+/**
+  * @}
+  */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+  * @{
+  */
+uint32_t                HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
+uint32_t                HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @addtogroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+void ADC_DMAError(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32G4xx_HAL_ADC_H */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h
new file mode 100644
index 0000000..440c223
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_adc_ex.h
@@ -0,0 +1,1570 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_adc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_ADC_EX_H
+#define STM32G4xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
+  * @{
+  */
+
+/**
+  * @brief  ADC Injected Conversion Oversampling structure definition
+  */
+typedef struct
+{
+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+
+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+} ADC_InjOversamplingTypeDef;
+
+/**
+  * @brief  Structure definition of ADC group injected and ADC channel affected to ADC group injected
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff,
+  *            InjectedOffsetNumber, InjectedOffset, InjectedOffsetSign, InjectedOffsetSaturation
+  *          - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion,
+  *            InjectedDiscontinuousConvMode,
+  *            AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge,
+  *            InjecOversamplingMode, InjecOversampling.
+  * @note   The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter
+  *            'InjectedSingleDiff')
+  *          - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled
+  *            without conversion on going on injected group.
+  *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'InjectedOffsetSign',
+  *            'InjectedOffsetSaturation', 'AutoInjectedConv': ADC enabled without conversion on going on regular and
+  *            injected groups.
+  *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv',
+  *            'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
+  *            on ADC groups regular and injected.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another
+  *         parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t InjectedChannel;               /*!< Specifies the channel to configure into ADC group injected.
+                                               This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+                                               Note: Depending on devices and ADC instances, some channels may not be
+                                                     available on device package pins. Refer to device datasheet for
+                                                     channels availability. */
+
+  uint32_t InjectedRank;                  /*!< Specifies the rank in the ADC group injected sequencer.
+                                               This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
+                                               Note: to disable a channel or change order of conversion sequencer,
+                                                     rank containing a previous channel setting can be overwritten by
+                                                     the new channel setting (or parameter number of conversions
+                                                     adjusted) */
+
+  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
+                                               Unit: ADC clock cycles.
+                                               Conversion time is the addition of sampling time and processing time
+                                               (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits,
+                                               8.5 cycles at 8 bits, 6.5 cycles at 6 bits).
+                                               This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.
+                                               Caution: This parameter applies to a channel that can be used in a
+                                                        regular and/or injected group. It overwrites the last setting.
+                                               Note: In case of usage of internal measurement channels (VrefInt, ...),
+                                                     sampling time constraints must be respected (sampling time can be
+                                                     adjusted in function of ADC clock frequency and sampling time
+                                                     setting). Refer to device datasheet for timings values. */
+
+  uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.
+                                               In differential mode: Differential measurement is between the selected
+                                               channel 'i' (positive input) and channel 'i+1' (negative input).
+                                               Only channel 'i' has to be configured, channel 'i+1' is configured
+                                               automatically.
+                                               This parameter must be a value of
+                                               @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.
+                                               Caution: This parameter applies to a channel that can be used in a
+                                               regular and/or injected group. It overwrites the last setting.
+                                               Note: Refer to Reference Manual to ensure the selected channel is
+                                                     available in differential mode.
+                                               Note: When configuring a channel 'i' in differential mode, the channel
+                                                     'i+1' is not usable separately.
+                                               Note: This parameter must be modified when ADC is disabled (before ADC
+                                                     start conversion or after ADC stop conversion).
+                                               If ADC is enabled, this parameter setting is bypassed without error
+                                               reporting (as it can be the expected behavior in case of another
+                                               parameter update on the fly) */
+
+  uint32_t InjectedOffsetNumber;          /*!< Selects the offset number.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.
+                                               Caution: Only one offset is allowed per channel. This parameter
+                                                        overwrites the last setting. */
+
+  uint32_t InjectedOffset;                /*!< Defines the offset to be applied on the raw converted data.
+                                               Offset value must be a positive number.
+                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits), this
+                                               parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
+                                               0x3FF, 0xFF or 0x3F respectively.
+                                               Note: This parameter must be modified when no conversion is on going
+                                                     on both regular and injected groups (ADC disabled, or ADC enabled
+                                                     without continuous mode or external trigger that could launch a
+                                                     conversion). */
+
+  uint32_t InjectedOffsetSign;                /*!< Define if the offset should be subtracted (negative sign) or added
+                                                  (positive sign) from or to the raw converted data.
+                                                  This parameter can be a value of @ref ADCEx_OffsetSign.
+                                                  Note: This parameter must be modified when no conversion is on going
+                                                        on both regular and injected groups (ADC disabled, or ADC
+                                                        enabled without continuous mode or external trigger that could
+                                                        launch a conversion). */
+  FunctionalState InjectedOffsetSaturation;   /*!< Define if the offset should be saturated upon under or over flow.
+                                               This parameter value can be ENABLE or DISABLE.
+                                               Note: This parameter must be modified when no conversion is on going
+                                                     on both regular and injected groups (ADC disabled, or ADC enabled
+                                                     without continuous mode or external trigger that could launch a
+                                                     conversion). */
+
+  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the ADC group
+                                               injected sequencer.
+                                               To use the injected group sequencer and convert several ranks, parameter
+                                               'ScanConvMode' must be enabled.
+                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.
+                                               Caution: this setting impacts the entire injected group. Therefore,
+                                               call of HAL_ADCEx_InjectedConfigChannel() to configure a channel on
+                                               injected group can impact the configuration of other channels previously
+                                               set. */
+
+  FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected
+                                               is performed in Complete-sequence/Discontinuous-sequence
+                                               (main sequence subdivided in successive parts).
+                                               Discontinuous mode is used only if sequencer is enabled (parameter
+                                               'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                               Discontinuous mode can be enabled only if continuous mode is disabled.
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: This parameter must be modified when ADC is disabled (before ADC
+                                               start conversion or after ADC stop conversion).
+                                               Note: For injected group, discontinuous mode converts the sequence
+                                               channel by channel (discontinuous length fixed to 1 rank).
+                                               Caution: this setting impacts the entire injected group. Therefore,
+                                                        call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the
+                                                        configuration of other channels previously set. */
+
+  FunctionalState AutoInjectedConv;       /*!< Enables or disables the selected ADC group injected automatic conversion
+                                               after regular one
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: To use Automatic injected conversion, discontinuous mode must
+                                                     be disabled ('DiscontinuousConvMode' and
+                                                     'InjectedDiscontinuousConvMode' set to DISABLE)
+                                               Note: To use Automatic injected conversion, injected group external
+                                                     triggers must be disabled ('ExternalTrigInjecConv' set to
+                                                     ADC_INJECTED_SOFTWARE_START)
+                                               Note: In case of DMA used with regular group: if DMA configured in
+                                                     normal mode (single shot) JAUTO will be stopped upon DMA transfer
+                                                     complete.
+                                                     To maintain JAUTO always enabled, DMA must be configured in
+                                                     circular mode.
+                                               Caution: this setting impacts the entire injected group. Therefore,
+                                                        call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
+                                                        on injected group can impact the configuration of other channels
+                                                        previously set. */
+
+  FunctionalState QueueInjectedContext;   /*!< Specifies whether the context queue feature is enabled.
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               If context queue is enabled, injected sequencer&channels configurations
+                                               are queued on up to 2 contexts. If a
+                                               new injected context is set when queue is full, error is triggered by
+                                               interruption and through function
+                                               'HAL_ADCEx_InjectedQueueOverflowCallback'.
+                                               Caution: This feature request that the sequence is fully configured
+                                                        before injected conversion start.
+                                                        Therefore, configure channels with as many calls to
+                                                        HAL_ADCEx_InjectedConfigChannel() as the
+                                                        'InjectedNbrOfConversion' parameter.
+                                               Caution: this setting impacts the entire injected group. Therefore,
+                                                        call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the
+                                                        configuration of other channels previously set.
+                                               Note: This parameter must be modified when ADC is disabled (before ADC
+                                                     start conversion or after ADC stop conversion). */
+
+  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of
+                                               injected group.
+                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled
+                                               and software trigger is used instead.
+                                               This parameter can be a value of
+                                               @ref ADC_injected_external_trigger_source.
+                                               Caution: this setting impacts the entire injected group. Therefore,
+                                                        call of HAL_ADCEx_InjectedConfigChannel() to configure a channel
+                                                        on injected group can impact the configuration of other channels
+                                                        previously set. */
+
+  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
+                                               This parameter can be a value of @ref ADC_injected_external_trigger_edge.
+                                               If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter
+                                               is discarded.
+                                               Caution: this setting impacts the entire injected group. Therefore,
+                                                        call of HAL_ADCEx_InjectedConfigChannel() to
+                                                        configure a channel on injected group can impact the
+                                                        configuration of other channels previously set. */
+
+  FunctionalState InjecOversamplingMode;         /*!< Specifies whether the oversampling feature is enabled or disabled.
+                                                      This parameter can be set to ENABLE or DISABLE.
+                                                      Note: This parameter can be modified only if there is no
+                                                      conversion is ongoing (both ADSTART and JADSTART cleared). */
+
+  ADC_InjOversamplingTypeDef  InjecOversampling; /*!< Specifies the Oversampling parameters.
+                                                      Caution: this setting overwrites the previous oversampling
+                                                               configuration if oversampling already enabled.
+                                                      Note: This parameter can be modified only if there is no
+                                                            conversion is ongoing (both ADSTART and JADSTART cleared).*/
+} ADC_InjectionConfTypeDef;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Structure definition of ADC multimode
+  * @note   The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state
+  *         (both Master and Slave ADCs).
+  *         Both Master and Slave ADCs must be disabled.
+  */
+typedef struct
+{
+  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multimode.
+                                   This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */
+
+  uint32_t DMAAccessMode;     /*!< Configures the DMA mode for multimode ADC:
+                                   selection whether 2 DMA channels (each ADC uses its own DMA channel) or 1 DMA channel
+                                   (one DMA channel for both ADC, DMA of ADC master).
+                                   This parameter can be a value of @ref ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION. */
+
+  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.
+                                   This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.
+                                   Delay range depends on selected resolution:
+                                    from 1 to 12 clock cycles for 12 bits, from 1 to 10 clock cycles for 10 bits,
+                                    from 1 to 8 clock cycles for 8 bits, from 1 to 6 clock cycles for 6 bits.     */
+} ADC_MultiModeTypeDef;
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source
+  * @{
+  */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_INJECTED_SOFTWARE_START        (LL_ADC_INJ_TRIG_SOFTWARE)            /*!< ADC group injected conversion
+                                           trigger software start */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM1 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T1_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM1 TRGO2. */
+#define ADC_EXTERNALTRIGINJEC_T1_CC3       (LL_ADC_INJ_TRIG_EXT_TIM1_CH3)        /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM1 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T1_CC4       (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)        /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM1 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T2_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM2 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T2_CC1       (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)        /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM2 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T3_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM3 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T3_CC1       (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)        /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM3 channel 1 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC3       (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)        /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM3 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T3_CC4       (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)        /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM3 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T4_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM4 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T4_CC3       (LL_ADC_INJ_TRIG_EXT_TIM4_CH3)        /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM4 channel 3 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T4_CC4       (LL_ADC_INJ_TRIG_EXT_TIM4_CH4)        /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM4 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T6_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM6 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T7_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM7 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM8 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T8_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM8 TRGO2. */
+#define ADC_EXTERNALTRIGINJEC_T8_CC2       (LL_ADC_INJ_TRIG_EXT_TIM8_CH2)        /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM8 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T8_CC4       (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)        /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM8 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T15_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM15 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T16_CC1      (LL_ADC_INJ_TRIG_EXT_TIM16_CH1)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM8 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T20_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM20 TRGO. */
+#define ADC_EXTERNALTRIGINJEC_T20_TRGO2    (LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)     /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM20 TRGO2. */
+#define ADC_EXTERNALTRIGINJEC_T20_CC2      (LL_ADC_INJ_TRIG_EXT_TIM20_CH2)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM20 channel 2 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_T20_CC4      (LL_ADC_INJ_TRIG_EXT_TIM20_CH4)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: TIM20 channel 4 event (capture compare). */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG1   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: HRTIMER ADC trigger 1 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG2   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: HRTIMER ADC trigger 2 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG3   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: HRTIMER ADC trigger 3 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG4   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: HRTIMER ADC trigger 4 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG5   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: HRTIMER ADC trigger 5 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG6   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: HRTIMER ADC trigger 6 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG7   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: HRTIMER ADC trigger 7 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG8   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: HRTIMER ADC trigger 8 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG9   (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: HRTIMER ADC trigger 9 event. */
+#define ADC_EXTERNALTRIGINJEC_HRTIM_TRG10  (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10)     /*!< ADC group injected conversion
+                                           trigger from external peripheral: HRTIMER ADC trigger 10 event. */
+#define ADC_EXTERNALTRIGINJEC_EXT_IT3      (LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)      /*!< ADC group injected conversion
+                                           trigger from external peripheral: external interrupt line 3. */
+#define ADC_EXTERNALTRIGINJEC_EXT_IT15     (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)     /*!< ADC group injected conversion
+                                           trigger from external peripheral: external interrupt line 15. */
+#define ADC_EXTERNALTRIGINJEC_LPTIM_OUT    (LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)       /*!< ADC group injected conversion
+                                           trigger from external peripheral: LPTIMER OUT event. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
+  * @{
+  */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           (0x00000000UL)        /*!< Injected conversions trigger
+                                                      disabled (SW start)*/
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         (ADC_JSQR_JEXTEN_0)   /*!< Injected conversions trigger
+                                                      polarity set to rising edge */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        (ADC_JSQR_JEXTEN_1)   /*!< Injected conversions trigger
+                                                      polarity set to falling edge */
+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  (ADC_JSQR_JEXTEN)     /*!< Injected conversions trigger
+                                                      polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
+  * @{
+  */
+#define ADC_SINGLE_ENDED                (LL_ADC_SINGLE_ENDED)         /*!< ADC channel ending set to single ended */
+#define ADC_DIFFERENTIAL_ENDED          (LL_ADC_DIFFERENTIAL_ENDED)   /*!< ADC channel ending set to differential */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OFFSET_NB  ADC instance - Offset number
+  * @{
+  */
+#define ADC_OFFSET_NONE              (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected
+                                     ADC channel */
+#define ADC_OFFSET_1                 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which
+                                     the offset programmed will be applied (independently of channel mapped
+                                     on ADC group regular or group injected) */
+#define ADC_OFFSET_2                 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which
+                                     the offset programmed will be applied (independently of channel mapped
+                                     on ADC group regular or group injected) */
+#define ADC_OFFSET_3                 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which
+                                     the offset programmed will be applied (independently of channel mapped
+                                     on ADC group regular or group injected) */
+#define ADC_OFFSET_4                 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which
+                                     the offset programmed will be applied (independently of channel mapped
+                                     on ADC group regular or group injected) */
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_OffsetSign ADC Extended Offset Sign
+  * @{
+  */
+#define ADC_OFFSET_SIGN_NEGATIVE      (0x00000000UL)         /*!< Offset sign negative, offset is subtracted */
+#define ADC_OFFSET_SIGN_POSITIVE      (ADC_OFR1_OFFSETPOS)   /*!< Offset sign positive, offset is added  */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
+  * @{
+  */
+#define ADC_INJECTED_RANK_1                (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */
+#define ADC_INJECTED_RANK_2                (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */
+#define ADC_INJECTED_RANK_3                (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */
+#define ADC_INJECTED_RANK_4                (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */
+/**
+  * @}
+  */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_HAL_EC_MULTI_MODE  Multimode - Mode
+  * @{
+  */
+#define ADC_MODE_INDEPENDENT               (LL_ADC_MULTI_INDEPENDENT)          /*!< ADC dual mode disabled
+                                           (ADC independent mode) */
+#define ADC_DUALMODE_REGSIMULT             (LL_ADC_MULTI_DUAL_REG_SIMULT)      /*!< ADC dual mode enabled: group regular
+                                           simultaneous */
+#define ADC_DUALMODE_INTERL                (LL_ADC_MULTI_DUAL_REG_INTERL)      /*!< ADC dual mode enabled: Combined
+                                           group regular interleaved */
+#define ADC_DUALMODE_INJECSIMULT           (LL_ADC_MULTI_DUAL_INJ_SIMULT)      /*!< ADC dual mode enabled: group
+                                           injected simultaneous */
+#define ADC_DUALMODE_ALTERTRIG             (LL_ADC_MULTI_DUAL_INJ_ALTERN)      /*!< ADC dual mode enabled: group
+                                           injected alternate trigger. Works only with external triggers (not internal
+                                           SW start) */
+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined
+                                           group regular simultaneous + group injected simultaneous */
+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG   (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined
+                                           group regular simultaneous + group injected alternate trigger */
+#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined
+                                           group regular interleaved + group injected simultaneous */
+
+/** @defgroup ADC_HAL_EC_MULTI_DMA_TRANSFER_RESOLUTION  Multimode - DMA transfer mode depending on ADC resolution
+  * @{
+  */
+#define ADC_DMAACCESSMODE_DISABLED         (0x00000000UL)     /*!< DMA multimode disabled: each ADC uses its own
+                                           DMA channel */
+#define ADC_DMAACCESSMODE_12_10_BITS       (ADC_CCR_MDMA_1)   /*!< DMA multimode enabled (one DMA channel for both ADC,
+                                           DMA of ADC master) for 12 and 10 bits resolution */
+#define ADC_DMAACCESSMODE_8_6_BITS         (ADC_CCR_MDMA)     /*!< DMA multimode enabled (one DMA channel for both ADC,
+                                           DMA of ADC master) for 8 and 6 bits resolution */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
+  * @{
+  */
+#define ADC_TWOSAMPLINGDELAY_1CYCLE        (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)    /*!< ADC multimode delay between two
+                                           sampling phases: 1 ADC clock cycle */
+#define ADC_TWOSAMPLINGDELAY_2CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 2 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_3CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 3 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_4CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 4 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_5CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 5 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_6CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 6 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_7CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 7 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_8CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 8 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_9CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)   /*!< ADC multimode delay between two
+                                           sampling phases: 9 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_10CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)  /*!< ADC multimode delay between two
+                                           sampling phases: 10 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_11CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)  /*!< ADC multimode delay between two
+                                           sampling phases: 11 ADC clock cycles */
+#define ADC_TWOSAMPLINGDELAY_12CYCLES      (LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)  /*!< ADC multimode delay between two
+                                           sampling phases: 12 ADC clock cycles */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/** @defgroup ADC_HAL_EC_GROUPS  ADC instance - Groups
+  * @{
+  */
+#define ADC_REGULAR_GROUP                  (LL_ADC_GROUP_REGULAR)          /*!< ADC group regular (available on
+                                                                                all STM32 devices) */
+#define ADC_INJECTED_GROUP                 (LL_ADC_GROUP_INJECTED)         /*!< ADC group injected (not available on
+                                                                                all STM32 devices) */
+#define ADC_REGULAR_INJECTED_GROUP         (LL_ADC_GROUP_REGULAR_INJECTED) /*!< ADC both groups regular and injected */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_CFGR_fields ADCx CFGR fields
+  * @{
+  */
+#define ADC_CFGR_FIELDS    (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\
+                            ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\
+                            ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\
+                            ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\
+                            ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\
+                            ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )
+/**
+  * @}
+  */
+
+/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
+  * @{
+  */
+#if defined(ADC_SMPR1_SMPPLUS)
+#define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
+                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
+                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
+                             ADC_SMPR1_SMP0 | ADC_SMPR1_SMPPLUS)
+#else
+#define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\
+                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\
+                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\
+                             ADC_SMPR1_SMP0)
+#endif /* ADC_SMPR1_SMPPLUS */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
+  * @{
+  */
+/* ADC_CFGR fields of parameters that can be updated when no conversion
+   (neither regular nor injected) is on-going  */
+#define ADC_CFGR_FIELDS_2  ((ADC_CFGR_DMACFG | ADC_CFGR_AUTDLY))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros
+  * @{
+  */
+
+/** @brief  Force ADC instance in multimode mode independent (multimode disable).
+  * @note   This macro must be used only in case of transition from multimode
+  *         to mode independent and in case of unknown previous state,
+  *         to ensure ADC configuration is in mode independent.
+  * @note   Standard way of multimode configuration change is done from
+  *         HAL ADC handle of ADC master using function
+  *         "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".
+  *         Usage of this macro is not the Standard way of multimode
+  *         configuration and can lead to have HAL ADC handles status
+  *         misaligned. Usage of this macro must be limited to cases
+  *         mentioned above.
+  * @param __HANDLE__ ADC handle.
+  * @retval None
+  */
+#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__)                                 \
+  LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)
+
+/**
+  * @}
+  */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
+  * @{
+  */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+  * @brief Test if conversion trigger of injected group is software start
+  *        or external trigger.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (software start) or RESET (external trigger).
+  */
+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
+  (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)
+
+/**
+  * @brief Check whether or not ADC is independent.
+  * @param __HANDLE__ ADC handle.
+  * @note  When multimode feature is not available, the macro always returns SET.
+  * @retval SET (ADC is independent) or RESET (ADC is not).
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define ADC_IS_INDEPENDENT(__HANDLE__)    \
+  ( ( ( ((__HANDLE__)->Instance) == ADC5) \
+    )?                                    \
+    SET                                   \
+    :                                     \
+    RESET                                 \
+  )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
+#define ADC_IS_INDEPENDENT(__HANDLE__)    \
+  ( ( ( ((__HANDLE__)->Instance) == ADC3) \
+    )?                                    \
+    SET                                   \
+    :                                     \
+    RESET                                 \
+  )
+#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#define ADC_IS_INDEPENDENT(__HANDLE__) (RESET)
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
+
+/**
+  * @brief Set the selected injected Channel rank.
+  * @param __CHANNELNB__ Channel number.
+  * @param __RANKNB__ Rank number.
+  * @retval None
+  */
+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) \
+  ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) \
+   << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))
+
+/**
+  * @brief Configure ADC injected context queue
+  * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.
+  * @retval None
+  */
+#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) \
+  ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)
+
+/**
+  * @brief Configure ADC discontinuous conversion mode for injected group
+  * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.
+  * @retval None
+  */
+#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) \
+  ((__INJECT_DISCONTINUOUS_MODE__) <<  ADC_CFGR_JDISCEN_Pos)
+
+/**
+  * @brief Configure ADC discontinuous conversion mode for regular group
+  * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.
+  * @retval None
+  */
+#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) \
+  ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)
+
+/**
+  * @brief Configure the number of discontinuous conversions for regular group.
+  * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.
+  * @retval None
+  */
+#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) \
+  (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)
+
+/**
+  * @brief Configure the ADC auto delay mode.
+  * @param __AUTOWAIT__ Auto delay bit enable or disable.
+  * @retval None
+  */
+#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)
+
+/**
+  * @brief Configure ADC continuous conversion mode.
+  * @param __CONTINUOUS_MODE__ Continuous mode.
+  * @retval None
+  */
+#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)
+
+/**
+  * @brief Configure the ADC DMA continuous request.
+  * @param __DMACONTREQ_MODE__ DMA continuous request mode.
+  * @retval None
+  */
+#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) <<  ADC_CFGR_DMACFG_Pos)
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief Configure the ADC DMA continuous request for ADC multimode.
+  * @param __DMACONTREQ_MODE__ DMA continuous request mode.
+  * @retval None
+  */
+#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief Shift the offset with respect to the selected ADC resolution.
+  * @note   Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+  *         If resolution 12 bits, no shift.
+  *         If resolution 10 bits, shift of 2 ranks on the left.
+  *         If resolution 8 bits, shift of 4 ranks on the left.
+  *         If resolution 6 bits, shift of 6 ranks on the left.
+  *         Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
+  * @param __HANDLE__ ADC handle
+  * @param __OFFSET__ Value to be shifted
+  * @retval None
+  */
+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
+  ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
+
+/**
+  * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
+  * @note  Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+  *        If resolution 12 bits, no shift.
+  *        If resolution 10 bits, shift of 2 ranks on the left.
+  *        If resolution 8 bits, shift of 4 ranks on the left.
+  *        If resolution 6 bits, shift of 6 ranks on the left.
+  *        Therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)).
+  * @param __HANDLE__ ADC handle
+  * @param __THRESHOLD__ Value to be shifted
+  * @retval None
+  */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
+  ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
+
+/**
+  * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
+  * @note  Thresholds have to be left-aligned on bit 7.
+  *        If resolution 12 bits, shift of 4 ranks on the right (the 4 LSB are discarded).
+  *        If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded).
+  *        If resolution 8 bits, no shift.
+  *        If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0).
+  * @param __HANDLE__ ADC handle
+  * @param __THRESHOLD__ Value to be shifted
+  * @retval None
+  */
+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                       \
+  ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0))                    ? \
+   ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
+   ((__THRESHOLD__) << 2UL)                                                                                 \
+  )
+
+/**
+  * @brief Clear Common Control Register.
+  * @param __HANDLE__ ADC handle.
+  * @retval None
+  */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, \
+                                                                ADC_CCR_CKMODE    | \
+                                                                ADC_CCR_PRESC     | \
+                                                                ADC_CCR_VBATSEL   | \
+                                                                ADC_CCR_VSENSESEL | \
+                                                                ADC_CCR_VREFEN    | \
+                                                                ADC_CCR_MDMA      | \
+                                                                ADC_CCR_DMACFG    | \
+                                                                ADC_CCR_DELAY     | \
+                                                                ADC_CCR_DUAL)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+/**
+  * @brief Set handle instance of the ADC slave associated to the ADC master.
+  * @param __HANDLE_MASTER__ ADC master handle.
+  * @param __HANDLE_SLAVE__ ADC slave handle.
+  * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is
+  *       set to NULL.
+  * @retval None
+  */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
+  ( ((__HANDLE_MASTER__)->Instance == ADC1) ?                            \
+    ((__HANDLE_SLAVE__)->Instance = ADC2)                                \
+    :                                                                    \
+    ((__HANDLE_MASTER__)->Instance == ADC3) ?                            \
+    ((__HANDLE_SLAVE__)->Instance = ADC4)                                \
+    :                                                                    \
+    ((__HANDLE_SLAVE__)->Instance = NULL)                                \
+  )
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
+/**
+  * @brief Set handle instance of the ADC slave associated to the ADC master.
+  * @param __HANDLE_MASTER__ ADC master handle.
+  * @param __HANDLE_SLAVE__ ADC slave handle.
+  * @note if __HANDLE_MASTER__ is the handle of a slave ADC or an independent ADC, __HANDLE_SLAVE__ instance is set
+  *       to NULL.
+  * @retval None
+  */
+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \
+  ( ((__HANDLE_MASTER__)->Instance == ADC1) ?                            \
+    ((__HANDLE_SLAVE__)->Instance = ADC2)                                \
+    :                                                                    \
+    ((__HANDLE_SLAVE__)->Instance = NULL)                                \
+  )
+#endif /* STM32G4xx */
+
+
+/**
+  * @brief Verify the ADC instance connected to the temperature sensor.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__) \
+  ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC5))
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
+
+/**
+  * @brief Verify the ADC instance connected to the battery voltage VBAT.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__) \
+  ((((__HANDLE__)->Instance) != ADC2) || (((__HANDLE__)->Instance) != ADC4))
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) != ADC2)
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC1)
+#endif /* STM32G4xx */
+
+/**
+  * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.
+  * @param __HANDLE__ ADC handle.
+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)
+  */
+#define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) != ADC2)
+
+/**
+  * @brief Verify the length of scheduled injected conversions group.
+  * @param __LENGTH__ number of programmed conversions.
+  * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions)
+  *         or RESET (__LENGTH__ is null or too large)
+  */
+#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
+
+/**
+  * @brief Calibration factor size verification (7 bits maximum).
+  * @param __CALIBRATION_FACTOR__ Calibration factor value.
+  * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
+  */
+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
+
+
+/**
+  * @brief Verify the ADC channel setting.
+  * @param __HANDLE__ ADC handle.
+  * @param __CHANNEL__ programmed ADC channel.
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (      ( ((__CHANNEL__) == ADC_CHANNEL_0)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_1)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))              || \
+                                                        ((((__HANDLE__)->Instance) == ADC1)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_17)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))   || \
+                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3)     || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC4)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC5)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP5)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC5)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP4)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
+#elif defined(STM32G471xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (      ( ((__CHANNEL__) == ADC_CHANNEL_0)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_1)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))              || \
+                                                        ((((__HANDLE__)->Instance) == ADC1)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_13)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_17)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))   || \
+                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3)     || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (      ( ((__CHANNEL__) == ADC_CHANNEL_0)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_1)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))              || \
+                                                        ((((__HANDLE__)->Instance) == ADC1)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_13)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_17)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2))))
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__)  (      ( ((__CHANNEL__) == ADC_CHANNEL_0)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_1)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)                || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))              || \
+                                                        ((((__HANDLE__)->Instance) == ADC1)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP1)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR_ADC1)  || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VBAT)             || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_13)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP2)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_17)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC2)))   || \
+                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_VOPAMP3_ADC3)     || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_16)               || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VOPAMP6)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_VREFINT))))
+#endif /* defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) */
+
+/**
+  * @brief Verify the ADC channel setting in differential mode.
+  * @param __HANDLE__ ADC handle.
+  * @param __CHANNEL__ programmed ADC channel.
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)  ( ( ((__CHANNEL__) == ADC_CHANNEL_1)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14))         || \
+                                                        ((((__HANDLE__)->Instance) == ADC1)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)))         || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC4)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC5)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))) )
+#elif defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)  ( ( ((__CHANNEL__) == ADC_CHANNEL_1)           || \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14))         || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13)))        || \
+                                                        ((((__HANDLE__)->Instance) == ADC3)  && \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_15))) )
+#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__)  ( ( ((__CHANNEL__) == ADC_CHANNEL_1)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_2)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_3)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_4)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_5)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_6)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_7)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_8)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_9)           || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_10)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_11)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_14))         || \
+                                                        ((((__HANDLE__)->Instance) == ADC2)  && \
+                                                         (((__CHANNEL__) == ADC_CHANNEL_12)          || \
+                                                          ((__CHANNEL__) == ADC_CHANNEL_13))) )
+#endif /* STM32G4xx */
+
+/**
+  * @brief Verify the ADC single-ended input or differential mode setting.
+  * @param __SING_DIFF__ programmed channel setting.
+  * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
+  */
+#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \
+                                                   ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )
+
+/**
+  * @brief Verify the ADC offset management setting.
+  * @param __OFFSET_NUMBER__ ADC offset management.
+  * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
+  */
+#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \
+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )
+
+/**
+  * @brief Verify the ADC offset sign setting.
+  * @param __OFFSET_SIGN__ ADC offset sign.
+  * @retval SET (__OFFSET_SIGN__ is valid) or RESET (__OFFSET_SIGN__ is invalid)
+  */
+#define IS_ADC_OFFSET_SIGN(__OFFSET_SIGN__)     (((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_NEGATIVE) || \
+                                                 ((__OFFSET_SIGN__) == ADC_OFFSET_SIGN_POSITIVE)    )
+
+/**
+  * @brief Verify the ADC injected channel setting.
+  * @param __CHANNEL__ programmed ADC injected channel.
+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
+  */
+#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )
+
+/**
+  * @brief Verify the ADC injected conversions external trigger.
+  * @param __HANDLE__ ADC handle.
+  * @param __INJTRIG__ programmed ADC injected conversions external trigger.
+  * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2)      || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG2)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG4)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG5)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG6)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG7)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG8)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG9)     || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG10)    || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
+                                                       ((((__HANDLE__)->Instance == ADC1) || \
+                                                         ((__HANDLE__)->Instance == ADC2)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)))   || \
+                                                       ((((__HANDLE__)->Instance == ADC3) || \
+                                                         ((__HANDLE__)->Instance == ADC4) || \
+                                                         ((__HANDLE__)->Instance == ADC5)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG1)   || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_HRTIM_TRG3)   || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3)))    || \
+                                                       ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2)      || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
+                                                       ((((__HANDLE__)->Instance == ADC1) || \
+                                                         ((__HANDLE__)->Instance == ADC2)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)))   || \
+                                                       ((((__HANDLE__)->Instance == ADC3) || \
+                                                         ((__HANDLE__)->Instance == ADC4) || \
+                                                         ((__HANDLE__)->Instance == ADC5)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3)))    || \
+                                                       ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
+#elif defined(STM32G471xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
+                                                       ((((__HANDLE__)->Instance == ADC1) || \
+                                                         ((__HANDLE__)->Instance == ADC2)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)))   || \
+                                                       ((((__HANDLE__)->Instance == ADC3)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3)))    || \
+                                                       ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
+#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
+                                                       ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
+#define IS_ADC_EXTTRIGINJEC(__HANDLE__, __INJTRIG__)  (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T7_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)        || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)         || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO)       || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_TRGO2)      || \
+                                                       ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_LPTIM_OUT)      || \
+                                                       ((((__HANDLE__)->Instance == ADC1) || \
+                                                         ((__HANDLE__)->Instance == ADC2)) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T16_CC1)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC4)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)))   || \
+                                                       (((__HANDLE__)->Instance == ADC3) && \
+                                                        (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC3)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_CC4)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC2)       || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T20_CC2)      || \
+                                                         ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT3)))    || \
+                                                       ((__INJTRIG__) == ADC_INJECTED_SOFTWARE_START)          )
+#endif /* STM32G4xx */
+
+/**
+  * @brief Verify the ADC edge trigger setting for injected group.
+  * @param __EDGE__ programmed ADC edge trigger setting.
+  * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
+  */
+#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief Verify the ADC multimode setting.
+  * @param __MODE__ programmed ADC multimode setting.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)               || \
+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \
+                                    ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \
+                                    ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \
+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \
+                                    ((__MODE__) == ADC_DUALMODE_INTERL)                || \
+                                    ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )
+
+/**
+  * @brief Verify the ADC multimode DMA access setting.
+  * @param __MODE__ programmed ADC multimode DMA access setting.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_DMA_ACCESS_MULTIMODE(__MODE__) (((__MODE__) == ADC_DMAACCESSMODE_DISABLED)   || \
+                                               ((__MODE__) == ADC_DMAACCESSMODE_12_10_BITS) || \
+                                               ((__MODE__) == ADC_DMAACCESSMODE_8_6_BITS)     )
+
+/**
+  * @brief Verify the ADC multimode delay setting.
+  * @param __DELAY__ programmed ADC multimode delay setting.
+  * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)
+  */
+#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)  || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES)   )
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief Verify the ADC analog watchdog setting.
+  * @param __WATCHDOG__ programmed ADC analog watchdog setting.
+  * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)
+  */
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
+                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
+                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )
+
+/**
+  * @brief Verify the ADC analog watchdog mode setting.
+  * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.
+  * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)
+  */
+#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)            || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)      || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)    || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)         || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)       || \
+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)      )
+
+/**
+  * @brief Verify the ADC analog watchdog filtering setting.
+  * @param __FILTERING_MODE__ programmed ADC analog watchdog mode setting.
+  * @retval SET (__FILTERING_MODE__ is valid) or RESET (__FILTERING_MODE__ is invalid)
+  */
+#define IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(__FILTERING_MODE__) \
+  (((__FILTERING_MODE__) == ADC_AWD_FILTERING_NONE)            || \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_2SAMPLES)        || \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_3SAMPLES)        || \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_4SAMPLES)        || \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_5SAMPLES)        || \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_6SAMPLES)        || \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_7SAMPLES)        || \
+   ((__FILTERING_MODE__) == ADC_AWD_FILTERING_8SAMPLES)           )
+
+
+/**
+  * @brief Verify the ADC conversion (regular or injected or both).
+  * @param __CONVERSION__ ADC conversion group.
+  * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
+  */
+#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)         || \
+                                                 ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \
+                                                 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )
+
+/**
+  * @brief Verify the ADC event type.
+  * @param __EVENT__ ADC event.
+  * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
+  */
+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT)  || \
+                                      ((__EVENT__) == ADC_AWD_EVENT)    || \
+                                      ((__EVENT__) == ADC_AWD2_EVENT)   || \
+                                      ((__EVENT__) == ADC_AWD3_EVENT)   || \
+                                      ((__EVENT__) == ADC_OVR_EVENT)    || \
+                                      ((__EVENT__) == ADC_JQOVF_EVENT)  )
+
+/**
+  * @brief Verify the ADC oversampling ratio.
+  * @param __RATIO__ programmed ADC oversampling ratio.
+  * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
+  */
+#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__)      (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
+
+/**
+  * @brief Verify the ADC oversampling shift.
+  * @param __SHIFT__ programmed ADC oversampling shift.
+  * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
+  */
+#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))
+
+/**
+  * @brief Verify the ADC oversampling triggered mode.
+  * @param __MODE__ programmed ADC oversampling triggered mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
+
+/**
+  * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
+  * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
+                                               ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
+
+/**
+  * @brief Verify the DFSDM mode configuration.
+  * @param __HANDLE__ ADC handle.
+  * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
+  *      this reason, the input parameter is the ADC handle and not the configuration parameter
+  *      directly.
+  * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
+  */
+#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
+
+/**
+  * @brief Return the DFSDM configuration mode.
+  * @param __HANDLE__ ADC handle.
+  * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
+  *       For this reason, the input parameter is the ADC handle and not the configuration parameter
+  *       directly.
+  * @retval DFSDM configuration mode
+  */
+#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+  * @{
+  */
+/* IO operation functions *****************************************************/
+
+/* ADC calibration */
+HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+uint32_t                HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
+HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+                                                       uint32_t CalibrationFactor);
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* ADC multimode */
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+uint32_t                HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t                HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
+
+/* ADC group regular conversions stop */
+HAL_StatusTypeDef       HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef       HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @addtogroup ADCEx_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
+                                                        const ADC_InjectionConfTypeDef *pConfigInjected);
+#if defined(ADC_MULTIMODE_SUPPORT)
+HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc,
+                                                         const ADC_MultiModeTypeDef *pMultimode);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_ADC_EX_H */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h
new file mode 100644
index 0000000..3480b28
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_comp.h
@@ -0,0 +1,1404 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_comp.h
+  * @author  MCD Application Team
+  * @brief   Header file of COMP HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_COMP_H
+#define STM32G4xx_HAL_COMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+#include "stm32g4xx_ll_exti.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+
+/** @addtogroup COMP
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Types COMP Exported Types
+  * @{
+  */
+
+/**
+  * @brief  COMP Init structure definition
+  */
+typedef struct
+{
+
+  uint32_t InputPlus;          /*!< Set comparator input plus (non-inverting input).
+                                    This parameter can be a value of @ref COMP_InputPlus */
+
+  uint32_t InputMinus;         /*!< Set comparator input minus (inverting input).
+                                    This parameter can be a value of @ref COMP_InputMinus */
+
+  uint32_t Hysteresis;         /*!< Set comparator hysteresis mode of the input minus.
+                                    This parameter can be a value of @ref COMP_Hysteresis */
+
+  uint32_t OutputPol;          /*!< Set comparator output polarity.
+                                    This parameter can be a value of @ref COMP_OutputPolarity */
+
+  uint32_t BlankingSrce;       /*!< Set comparator blanking source.
+                                    This parameter can be a value of @ref COMP_BlankingSrce */
+
+  uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).
+                                    This parameter can be a value of @ref COMP_EXTI_TriggerMode */
+
+} COMP_InitTypeDef;
+
+/**
+  * @brief  HAL COMP state machine: HAL COMP states definition
+  */
+#define COMP_STATE_BITFIELD_LOCK  (0x10U)
+typedef enum
+{
+  HAL_COMP_STATE_RESET             = 0x00U,                                             /*!< COMP not yet initialized                             */
+  HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */
+  HAL_COMP_STATE_READY             = 0x01U,                                             /*!< COMP initialized and ready for use                   */
+  HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */
+  HAL_COMP_STATE_BUSY              = 0x02U,                                             /*!< COMP is running                                      */
+  HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */
+} HAL_COMP_StateTypeDef;
+
+/**
+  * @brief  COMP Handle Structure definition
+  */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+typedef struct __COMP_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+{
+  COMP_TypeDef       *Instance;       /*!< Register base address    */
+  COMP_InitTypeDef   Init;            /*!< COMP required parameters */
+  HAL_LockTypeDef    Lock;            /*!< Locking object           */
+  __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
+  __IO uint32_t      ErrorCode;       /*!< COMP error code */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+  void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP trigger callback */
+  void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP Msp Init callback */
+  void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+} COMP_HandleTypeDef;
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL COMP Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_COMP_TRIGGER_CB_ID                = 0x00U,  /*!< COMP trigger callback ID */
+  HAL_COMP_MSPINIT_CB_ID                = 0x01U,  /*!< COMP Msp Init callback ID */
+  HAL_COMP_MSPDEINIT_CB_ID              = 0x02U   /*!< COMP Msp DeInit callback ID */
+} HAL_COMP_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL COMP Callback pointer definition
+  */
+typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */
+
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_Exported_Constants COMP Exported Constants
+  * @{
+  */
+
+/** @defgroup COMP_Error_Code COMP Error Code
+  * @{
+  */
+#define HAL_COMP_ERROR_NONE             (0x00UL)  /*!< No error */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01UL)  /*!< Invalid Callback error */
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)
+  * @{
+  */
+#define COMP_INPUT_PLUS_IO1            (0x00000000UL)         /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA7 for COMP2, pin PA0 for COMP3, pin PB0 for COMP4, pin PB13 for COMP5, pin PB11 for COMP6, pin PB14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
+#define COMP_INPUT_PLUS_IO2            (COMP_CSR_INPSEL)      /*!< Comparator input plus connected to IO2 (pin PB1 for COMP1, pin PA3 for COMP2, pin PC1 for COMP3, pin PE7 for COMP4, pin PD12 for COMP5, pin PD11 for COMP6, pin PD14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_InputMinus COMP input minus (inverting input)
+  * @{
+  */
+#define COMP_INPUT_MINUS_1_4VREFINT    (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt */
+#define COMP_INPUT_MINUS_1_2VREFINT    (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt */
+#define COMP_INPUT_MINUS_3_4VREFINT    (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt */
+#define COMP_INPUT_MINUS_VREFINT       (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
+#define COMP_INPUT_MINUS_DAC1_CH1      (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 Channel 1 for COMP1/3/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define COMP_INPUT_MINUS_DAC1_CH2      (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 Channel 2 for COMP2/5. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define COMP_INPUT_MINUS_DAC2_CH1      (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC2 Channel 1 for COMP6/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define COMP_INPUT_MINUS_DAC3_CH1      (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC3 Channel 1 for COMP1/3. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define COMP_INPUT_MINUS_DAC3_CH2      (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC3 Channel 2 for COMP2/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define COMP_INPUT_MINUS_DAC4_CH1      (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC4 Channel 1 for COMP5/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define COMP_INPUT_MINUS_DAC4_CH2      (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC4 Channel 2 for COMP6. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define COMP_INPUT_MINUS_IO1           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
+#define COMP_INPUT_MINUS_IO2           (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PA0 for COMP1, pin PA2 for COMP2, pin PC0 for COMP3, pin PB2 for COMP4, pin PD13 for COMP5, pin PB15 for COMP6, pin PB12 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Hysteresis COMP hysteresis
+  * @{
+  */
+#define COMP_HYSTERESIS_NONE           (0x00000000UL)                                        /*!< No hysteresis */
+#define COMP_HYSTERESIS_10MV           (                                    COMP_CSR_HYST_0) /*!< Hysteresis level 10mV */
+#define COMP_HYSTERESIS_20MV           (                  COMP_CSR_HYST_1                  ) /*!< Hysteresis level 20mV */
+#define COMP_HYSTERESIS_30MV           (                  COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 30mV */
+#define COMP_HYSTERESIS_40MV           (COMP_CSR_HYST_2                                    ) /*!< Hysteresis level 40mV */
+#define COMP_HYSTERESIS_50MV           (COMP_CSR_HYST_2                   | COMP_CSR_HYST_0) /*!< Hysteresis level 50mV */
+#define COMP_HYSTERESIS_60MV           (COMP_CSR_HYST_2 | COMP_CSR_HYST_1                  ) /*!< Hysteresis level 60mV */
+#define COMP_HYSTERESIS_70MV           (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 70mV */
+#define COMP_HYSTERESIS_LOW            COMP_HYSTERESIS_10MV  /*!< Hysteresis level low */
+#define COMP_HYSTERESIS_MEDIUM         COMP_HYSTERESIS_40MV  /*!< Hysteresis level medium */
+#define COMP_HYSTERESIS_HIGH           COMP_HYSTERESIS_70MV  /*!< Hysteresis level high */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputPolarity COMP output Polarity
+  * @{
+  */
+#define COMP_OUTPUTPOL_NONINVERTED     (0x00000000UL)         /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */
+#define COMP_OUTPUTPOL_INVERTED        (COMP_CSR_POLARITY)    /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_BlankingSrce  COMP blanking source
+  * @{
+  */
+#define COMP_BLANKINGSRC_NONE            (0x00000000UL)          /*!<Comparator output without blanking */
+#define COMP_BLANKINGSRC_TIM1_OC5_COMP1  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM1_OC5_COMP2  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM1_OC5_COMP3  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM1_OC5_COMP4  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM1_OC5_COMP5  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM1_OC5_COMP6  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM1_OC5_COMP7  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM2_OC3_COMP1  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM2_OC3_COMP2  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM2_OC3_COMP5  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM2_OC4_COMP3  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM2_OC4_COMP6  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM3_OC3_COMP1  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM3_OC3_COMP2  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM3_OC3_COMP3  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM3_OC3_COMP5  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM3_OC3_COMP7  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM3_OC4_COMP4  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM8_OC5_COMP1  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP1). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM8_OC5_COMP2  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM8_OC5_COMP3  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP3). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM8_OC5_COMP4  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM8_OC5_COMP5  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP5). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM8_OC5_COMP6  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM8_OC5_COMP7  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM15_OC1_COMP4 (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM15_OC2_COMP6 (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM15 OC3 (specific to COMP instance: COMP7). Note: For COMPx & TIMx instances availability, please refer to datasheet */
+#define COMP_BLANKINGSRC_TIM20_OC5       (COMP_CSR_BLANKING_2 |                       COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM20 OC5 (Common to all COMP instances) */
+#define COMP_BLANKINGSRC_TIM15_OC1       (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM15 OC1 (Common to all COMP instances) */
+#define COMP_BLANKINGSRC_TIM4_OC3        (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM4 OC3 (Common to all COMP instances) */
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_OutputLevel COMP Output Level
+  * @{
+  */
+/* Note: Comparator output level values are fixed to "0" and "1",             */
+/* corresponding COMP register bit is managed by HAL function to match        */
+/* with these values (independently of bit position in register).             */
+
+/* When output polarity is not inverted, comparator output is low when
+   the input plus is at a lower voltage than the input minus */
+#define COMP_OUTPUT_LEVEL_LOW              (0x00000000UL)
+/* When output polarity is not inverted, comparator output is high when
+   the input plus is at a higher voltage than the input minus */
+#define COMP_OUTPUT_LEVEL_HIGH             (0x00000001UL)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI
+  * @{
+  */
+#define COMP_TRIGGERMODE_NONE                 (0x00000000UL)                                            /*!< Comparator output triggering no External Interrupt Line */
+#define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */
+#define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */
+#define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */
+#define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */
+#define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */
+#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_Exported_Macros COMP Exported Macros
+  * @{
+  */
+
+/** @defgroup COMP_Handle_Management  COMP Handle Management
+  * @{
+  */
+
+/** @brief  Reset COMP handle state.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                  \
+                                                      (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \
+                                                      (__HANDLE__)->MspInitCallback = NULL;            \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;          \
+                                                    } while(0)
+#else
+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+
+/**
+  * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").
+  * @param __HANDLE__ COMP handle
+  * @retval None
+  */
+#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
+
+/**
+  * @brief  Enable the specified comparator.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_ENABLE(__HANDLE__)       SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
+
+/**
+  * @brief  Disable the specified comparator.
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_DISABLE(__HANDLE__)      CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN)
+
+/**
+  * @brief  Lock the specified comparator configuration.
+  * @note   Using this macro induce HAL COMP handle state machine being no
+  *         more in line with COMP instance state.
+  *         To keep HAL COMP handle state machine updated, it is recommended
+  *         to use function "HAL_COMP_Lock')".
+  * @param  __HANDLE__  COMP handle
+  * @retval None
+  */
+#define __HAL_COMP_LOCK(__HANDLE__)         SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK)
+
+/**
+  * @brief  Check whether the specified comparator is locked.
+  * @param  __HANDLE__  COMP handle
+  * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked
+  */
+#define __HAL_COMP_IS_LOCKED(__HANDLE__)    (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK)
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exti_Management  COMP external interrupt line management
+  * @{
+  */
+/**
+  * @brief  Enable the COMP1 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do {                                                        \
+                                                                LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1);   \
+                                                                LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);  \
+                                                              } while(0)
+
+/**
+  * @brief  Disable the COMP1 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do {                                                       \
+                                                                 LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
+                                                                 LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\
+                                                               } while(0)
+
+/**
+  * @brief  Enable the COMP1 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Generate a software interrupt on the COMP1 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP1 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Disable the COMP1 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Check whether the COMP1 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP1_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Clear the COMP1 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP1)
+
+/**
+  * @brief  Enable the COMP2 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do {                                                        \
+                                                                LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2);   \
+                                                                LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);  \
+                                                              } while(0)
+
+/**
+  * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do {                                                       \
+                                                                 LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \
+                                                                 LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\
+                                                               } while(0)
+
+/**
+  * @brief  Enable the COMP2 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Generate a software interrupt on the COMP2 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP2 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Disable the COMP2 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Check whether the COMP2 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP2_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Clear the COMP2 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP2)
+
+/**
+  * @brief  Enable the COMP3 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
+
+/**
+  * @brief  Disable the COMP3 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3)
+
+/**
+  * @brief  Enable the COMP3 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
+
+/**
+  * @brief  Disable the COMP3 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3)
+
+/**
+  * @brief  Enable the COMP3 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_RISING_FALLING_EDGE() do {                                                        \
+                                                                LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP3);   \
+                                                                LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP3);  \
+                                                              } while(0)
+
+/**
+  * @brief  Disable the COMP3 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_RISING_FALLING_EDGE() do {                                                       \
+                                                                 LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP3); \
+                                                                 LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP3);\
+                                                               } while(0)
+
+/**
+  * @brief  Enable the COMP3 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP3)
+
+/**
+  * @brief  Disable the COMP3 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP3)
+
+/**
+  * @brief  Generate a software interrupt on the COMP3 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP3_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP3)
+
+/**
+  * @brief  Enable the COMP3 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP3_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP3)
+
+/**
+  * @brief  Disable the COMP3 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP3_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP3)
+
+/**
+  * @brief  Check whether the COMP3 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP3_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP3)
+
+/**
+  * @brief  Clear the COMP3 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP3_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP3)
+
+/**
+  * @brief  Enable the COMP4 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)
+
+/**
+  * @brief  Disable the COMP4 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4)
+
+/**
+  * @brief  Enable the COMP4 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)
+
+/**
+  * @brief  Disable the COMP4 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4)
+
+/**
+  * @brief  Enable the COMP4 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_RISING_FALLING_EDGE() do {                                                        \
+                                                                LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP4);   \
+                                                                LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP4);  \
+                                                              } while(0)
+
+/**
+  * @brief  Disable the COMP4 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_RISING_FALLING_EDGE() do {                                                       \
+                                                                 LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP4); \
+                                                                 LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP4);\
+                                                               } while(0)
+
+/**
+  * @brief  Enable the COMP4 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP4)
+
+/**
+  * @brief  Disable the COMP4 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP4)
+
+/**
+  * @brief  Generate a software interrupt on the COMP4 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP4_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP4)
+
+/**
+  * @brief  Enable the COMP4 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP4_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP4)
+
+/**
+  * @brief  Disable the COMP4 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP4_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP4)
+
+/**
+  * @brief  Check whether the COMP4 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP4_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP4)
+
+/**
+  * @brief  Clear the COMP4 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP4_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP4)
+
+#if  defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+/**
+  * @brief  Enable the COMP5 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5)
+
+/**
+  * @brief  Disable the COMP5 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5)
+
+/**
+  * @brief  Enable the COMP5 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5)
+
+/**
+  * @brief  Disable the COMP5 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5)
+
+/**
+  * @brief  Enable the COMP5 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_RISING_FALLING_EDGE() do {                                                        \
+                                                                LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP5);   \
+                                                                LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP5);  \
+                                                              } while(0)
+
+/**
+  * @brief  Disable the COMP5 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_RISING_FALLING_EDGE() do {                                                       \
+                                                                 LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP5); \
+                                                                 LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP5);\
+                                                               } while(0)
+
+/**
+  * @brief  Enable the COMP5 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_0_31(COMP_EXTI_LINE_COMP5)
+
+/**
+  * @brief  Disable the COMP5 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_0_31(COMP_EXTI_LINE_COMP5)
+
+/**
+  * @brief  Generate a software interrupt on the COMP5 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP5_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_0_31(COMP_EXTI_LINE_COMP5)
+
+/**
+  * @brief  Enable the COMP5 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP5_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_0_31(COMP_EXTI_LINE_COMP5)
+
+/**
+  * @brief  Disable the COMP5 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP5_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_0_31(COMP_EXTI_LINE_COMP5)
+
+/**
+  * @brief  Check whether the COMP5 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP5_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_0_31(COMP_EXTI_LINE_COMP5)
+
+/**
+  * @brief  Clear the COMP5 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP5_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_0_31(COMP_EXTI_LINE_COMP5)
+
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
+#if  defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+/**
+  * @brief  Enable the COMP6 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6)
+
+/**
+  * @brief  Disable the COMP6 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6)
+
+/**
+  * @brief  Enable the COMP6 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6)
+
+/**
+  * @brief  Disable the COMP6 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6)
+
+/**
+  * @brief  Enable the COMP6 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_RISING_FALLING_EDGE() do {                                                        \
+                                                                LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP6);  \
+                                                                LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP6); \
+                                                              } while(0)
+
+/**
+  * @brief  Disable the COMP6 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_RISING_FALLING_EDGE() do {                                                       \
+                                                                 LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP6);\
+                                                                 LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP6);\
+                                                               } while(0)
+
+/**
+  * @brief  Enable the COMP6 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_32_63(COMP_EXTI_LINE_COMP6)
+
+/**
+  * @brief  Disable the COMP6 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_32_63(COMP_EXTI_LINE_COMP6)
+
+/**
+  * @brief  Generate a software interrupt on the COMP6 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP6_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_32_63(COMP_EXTI_LINE_COMP6)
+
+/**
+  * @brief  Enable the COMP6 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP6_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_32_63(COMP_EXTI_LINE_COMP6)
+
+/**
+  * @brief  Disable the COMP6 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP6_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_32_63(COMP_EXTI_LINE_COMP6)
+
+/**
+  * @brief  Check whether the COMP6 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP6_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_32_63(COMP_EXTI_LINE_COMP6)
+
+/**
+  * @brief  Clear the COMP6 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP6)
+
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx*/
+#if  defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+/**
+  * @brief  Enable the COMP7 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()    LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7)
+
+/**
+  * @brief  Disable the COMP7 EXTI line rising edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()   LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7)
+
+/**
+  * @brief  Enable the COMP7 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()   LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7)
+
+/**
+  * @brief  Disable the COMP7 EXTI line falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()  LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7)
+
+/**
+  * @brief  Enable the COMP7 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_RISING_FALLING_EDGE() do {                                                        \
+                                                                LL_EXTI_EnableRisingTrig_32_63(COMP_EXTI_LINE_COMP7);  \
+                                                                LL_EXTI_EnableFallingTrig_32_63(COMP_EXTI_LINE_COMP7); \
+                                                              } while(0)
+
+/**
+  * @brief  Disable the COMP7 EXTI line rising & falling edge trigger.
+  * @retval None
+  */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_RISING_FALLING_EDGE() do {                                                       \
+                                                                 LL_EXTI_DisableRisingTrig_32_63(COMP_EXTI_LINE_COMP7);\
+                                                                 LL_EXTI_DisableFallingTrig_32_63(COMP_EXTI_LINE_COMP7);\
+                                                               } while(0)
+
+/**
+  * @brief  Enable the COMP7 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_IT()             LL_EXTI_EnableIT_32_63(COMP_EXTI_LINE_COMP7)
+
+/**
+  * @brief  Disable the COMP7 EXTI line in interrupt mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_IT()            LL_EXTI_DisableIT_32_63(COMP_EXTI_LINE_COMP7)
+
+/**
+  * @brief  Generate a software interrupt on the COMP7 EXTI line.
+  * @retval None
+  */
+#define __HAL_COMP_COMP7_EXTI_GENERATE_SWIT()         LL_EXTI_GenerateSWI_32_63(COMP_EXTI_LINE_COMP7)
+
+/**
+  * @brief  Enable the COMP7 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP7_EXTI_ENABLE_EVENT()          LL_EXTI_EnableEvent_32_63(COMP_EXTI_LINE_COMP7)
+
+/**
+  * @brief  Disable the COMP7 EXTI line in event mode.
+  * @retval None
+  */
+#define __HAL_COMP_COMP7_EXTI_DISABLE_EVENT()         LL_EXTI_DisableEvent_32_63(COMP_EXTI_LINE_COMP7)
+
+/**
+  * @brief  Check whether the COMP7 EXTI line flag is set.
+  * @retval RESET or SET
+  */
+#define __HAL_COMP_COMP7_EXTI_GET_FLAG()              LL_EXTI_IsActiveFlag_32_63(COMP_EXTI_LINE_COMP7)
+
+/**
+  * @brief  Clear the COMP7 EXTI flag.
+  * @retval None
+  */
+#define __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()            LL_EXTI_ClearFlag_32_63(COMP_EXTI_LINE_COMP7)
+
+#endif /* STM32G414xx ||  STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Private types -------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup COMP_Private_Constants COMP Private Constants
+  * @{
+  */
+
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+  * @{
+  */
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
+#define COMP_EXTI_LINE_COMP1           (LL_EXTI_LINE_21)  /*!< EXTI line 21 connected to COMP1 output. Note: For COMPx instance availability, please refer to datasheet */
+#define COMP_EXTI_LINE_COMP2           (LL_EXTI_LINE_22)  /*!< EXTI line 22 connected to COMP2 output. Note: For COMPx instance availability, please refer to datasheet */
+#define COMP_EXTI_LINE_COMP3           (LL_EXTI_LINE_29)  /*!< EXTI line 29 connected to COMP3 output. Note: For COMPx instance availability, please refer to datasheet */
+#define COMP_EXTI_LINE_COMP4           (LL_EXTI_LINE_30)  /*!< EXTI line 30 connected to COMP4 output. Note: For COMPx instance availability, please refer to datasheet */
+#elif defined(STM32G411xB) || defined(STM32G411xC)
+#define COMP_EXTI_LINE_COMP1           (LL_EXTI_LINE_21)  /*!< EXTI line 21 connected to COMP1 output. Note: For COMPx instance availability, please refer to datasheet */
+#define COMP_EXTI_LINE_COMP2           (LL_EXTI_LINE_22)  /*!< EXTI line 22 connected to COMP2 output. Note: For COMPx instance availability, please refer to datasheet */
+#define COMP_EXTI_LINE_COMP3           (LL_EXTI_LINE_29)  /*!< EXTI line 29 connected to COMP3 output. Note: For COMPx instance availability, please refer to datasheet */
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx || STM32GBK1CB || STM32G431xx || STM32G441xx || STM32G471xx || STM32G491xx || STM32G4A1xx */
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define COMP_EXTI_LINE_COMP5           (LL_EXTI_LINE_31)  /*!< EXTI line 31 connected to COMP5 output. Note: For COMPx instance availability, please refer to datasheet */
+#define COMP_EXTI_LINE_COMP6           (LL_EXTI_LINE_32)  /*!< EXTI line 32 connected to COMP6 output. Note: For COMPx instance availability, please refer to datasheet */
+#define COMP_EXTI_LINE_COMP7           (LL_EXTI_LINE_33)  /*!< EXTI line 33 connected to COMP7 output. Note: For COMPx instance availability, please refer to datasheet */
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_ExtiLine COMP EXTI Lines
+  * @{
+  */
+#define COMP_EXTI_IT                        (0x00000001UL)  /*!< EXTI line event with interruption */
+#define COMP_EXTI_EVENT                     (0x00000002UL)  /*!< EXTI line event only (without interruption) */
+#define COMP_EXTI_RISING                    (0x00000010UL)  /*!< EXTI line event on rising edge */
+#define COMP_EXTI_FALLING                   (0x00000020UL)  /*!< EXTI line event on falling edge */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_Private_Macros COMP Private Macros
+  * @{
+  */
+
+/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
+  * @{
+  */
+/**
+  * @brief  Get the specified EXTI line for a comparator instance.
+  * @param  __INSTANCE__  specifies the COMP instance.
+  * @retval value of @ref COMP_ExtiLine
+  */
+#if  defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
+                                             :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
+                                             :((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
+                                             :((__INSTANCE__) == COMP4) ? COMP_EXTI_LINE_COMP4 \
+                                             :((__INSTANCE__) == COMP5) ? COMP_EXTI_LINE_COMP5 \
+                                             :((__INSTANCE__) == COMP6) ? COMP_EXTI_LINE_COMP6 \
+                                             : COMP_EXTI_LINE_COMP7)
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
+#define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
+                                             :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
+                                             :((__INSTANCE__) == COMP3) ? COMP_EXTI_LINE_COMP3 \
+                                             : COMP_EXTI_LINE_COMP4)
+#elif defined(STM32G411xB) || defined(STM32G411xC)
+#define COMP_GET_EXTI_LINE(__INSTANCE__)    (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1  \
+                                             :((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 \
+                                             : COMP_EXTI_LINE_COMP3)
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_IS_COMP_Private_Definitions COMP private macros to check input parameters
+  * @{
+  */
+#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \
+                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))
+
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
+                                                                 (((__COMP_INSTANCE__) == COMP1)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1))    \
+                                                                 )                                                      || \
+                                                                 (((__COMP_INSTANCE__) == COMP2)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2))    \
+                                                                 )                                                      || \
+                                                                 (((__COMP_INSTANCE__) == COMP3)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1))    \
+                                                                 )                                                      || \
+                                                                 (((__COMP_INSTANCE__) == COMP4)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2))    \
+                                                                 )                                                      || \
+                                                                 (((__COMP_INSTANCE__) == COMP5)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1))    \
+                                                                 )                                                      || \
+                                                                 (((__COMP_INSTANCE__) == COMP6)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH2))    \
+                                                                 )                                                      || \
+                                                                 (((__COMP_INSTANCE__) == COMP7)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC2_CH1)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC4_CH1))    \
+                                                                 ))
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx) || defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
+                                                                 (((__COMP_INSTANCE__) == COMP1)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1))    \
+                                                                 )                                                      || \
+                                                                 (((__COMP_INSTANCE__) == COMP2)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2))    \
+                                                                 )                                                      || \
+                                                                 (((__COMP_INSTANCE__) == COMP3)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1))    \
+                                                                 )                                                      || \
+                                                                 (((__COMP_INSTANCE__) == COMP4)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2))    \
+                                                                 ))
+#elif defined(STM32G411xB) || defined(STM32G411xC)
+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \
+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)         || \
+                                                                 (((__COMP_INSTANCE__) == COMP1)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1))    \
+                                                                 )                                                      || \
+                                                                 (((__COMP_INSTANCE__) == COMP2)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH2))    \
+                                                                 )                                                      || \
+                                                                 (((__COMP_INSTANCE__) == COMP3)                        && \
+                                                                  (((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)  || \
+                                                                   ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC3_CH1))    \
+                                                                 ))
+#endif
+
+
+#define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_10MV)   || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_20MV)   || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_30MV)   || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_40MV)   || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_50MV)   || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_60MV)   || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_70MV)   || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \
+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))
+
+#define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \
+                                             ((__POL__) == COMP_OUTPUTPOL_INVERTED))
+
+/* Note: Output blanking source depends on COMP instances     */
+/*       Better use IS_COMP_BLANKINGSRC_INSTANCE instead      */
+/*       Macro kept for compatibility with other STM32 series */
+#define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)                    \
+  (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)                  \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7)     \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4)    \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6)    \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7)    \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5)          \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1)          \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3)           \
+  )
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
+  ((((__INSTANCE__) == COMP1) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1)))        \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP2) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)))        \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP3) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3)))        \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP4) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4)))       \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP5) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP5)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP5)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP5)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP5)))        \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP6) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP6)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP6)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP6)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP6)))       \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP7) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP7)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP7)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP7)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC2_COMP7)))       \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5)              \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1)              \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3)               \
+  )
+#elif defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx) || defined(STM32G471xx)
+#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
+  ((((__INSTANCE__) == COMP1) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1)))        \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP2) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)))        \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP3) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3)))        \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP4) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4)))       \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1)              \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3)               \
+  )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
+  ((((__INSTANCE__) == COMP1) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1)))        \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP2) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)))        \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP3) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3)))        \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP4) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP4)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4_COMP4)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP4)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1_COMP4)))       \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5)              \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1)              \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3)               \
+  )
+#elif defined(STM32G411xB) || defined(STM32G411xC)
+#define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__)  \
+  ((((__INSTANCE__) == COMP1) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP1)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP1)))        \
+   ||                                                                           \
+    (((__INSTANCE__) == COMP2) &&                                               \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP2)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3_COMP2)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP2)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP2)))        \
+   ||                                                                           \
+   (((__INSTANCE__) == COMP3) &&                                                \
+    (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE)            ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5_COMP3)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC4_COMP3)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3_COMP3)  ||      \
+     ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5_COMP3)))        \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM20_OC5)              \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1)              \
+   || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM4_OC3)               \
+  )
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx || STM32G483xx */
+
+#define IS_COMP_TRIGGERMODE(__MODE__)       (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \
+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))
+
+#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \
+                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup COMP_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup COMP_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  **********************************/
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
+                                            pCOMP_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/* IO operation functions  *****************************************************/
+/** @addtogroup COMP_Exported_Functions_Group2
+  * @{
+  */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
+void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* Peripheral Control functions  ************************************************/
+/** @addtogroup COMP_Exported_Functions_Group3
+  * @{
+  */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
+uint32_t          HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp);
+/* Callback in interrupt mode */
+void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/* Peripheral State functions  **************************************************/
+/** @addtogroup COMP_Exported_Functions_Group4
+  * @{
+  */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp);
+uint32_t              HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_COMP_H */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h
new file mode 100644
index 0000000..8049f97
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac.h
@@ -0,0 +1,638 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_dac.h
+  * @author  MCD Application Team
+  * @brief   Header file of DAC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_DAC_H
+#define STM32G4xx_HAL_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+#if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Types DAC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */
+  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */
+  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */
+  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */
+  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */
+
+} HAL_DAC_StateTypeDef;
+
+/**
+  * @brief  DAC handle Structure definition
+  */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+typedef struct __DAC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+{
+  DAC_TypeDef                 *Instance;     /*!< Register base address             */
+
+  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
+
+  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
+
+  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
+
+  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */
+
+  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  void (* ConvCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+  void (* ConvHalfCpltCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+  void (* ErrorCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+  void (* DMAUnderrunCallbackCh1)(struct __DAC_HandleTypeDef *hdac);
+
+  void (* ConvCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+  void (* ConvHalfCpltCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+  void (* ErrorCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+  void (* DMAUnderrunCallbackCh2)(struct __DAC_HandleTypeDef *hdac);
+
+
+  void (* MspInitCallback)(struct __DAC_HandleTypeDef *hdac);
+  void (* MspDeInitCallback)(struct __DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+} DAC_HandleTypeDef;
+
+/**
+  * @brief   DAC Configuration sample and hold Channel structure definition
+  */
+typedef struct
+{
+  uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
+
+  uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */
+
+  uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel
+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.
+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
+} DAC_SampleAndHoldConfTypeDef;
+
+/**
+  * @brief   DAC Configuration regular Channel structure definition
+  */
+typedef struct
+{
+  uint32_t DAC_HighFrequency;            /*!< Specifies the frequency interface mode
+                                              This parameter can be a value of @ref DAC_HighFrequency */
+
+  FunctionalState DAC_DMADoubleDataMode; /*!< Specifies if DMA double data mode should be enabled or not for the selected channel.
+                                              This parameter can be ENABLE or DISABLE */
+
+  FunctionalState DAC_SignedFormat;      /*!< Specifies if signed format should be used or not for the selected channel.
+                                              This parameter can be ENABLE or DISABLE */
+
+  uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.
+                                              This parameter can be a value of @ref DAC_SampleAndHold */
+
+  uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.
+                                              This parameter can be a value of @ref DAC_trigger_selection.
+                                              Note: In case of sawtooth wave generation, this
+                                              trigger corresponds to the reset trigger. */
+
+  uint32_t DAC_Trigger2;                 /*!< Specifies the external secondary trigger for the selected DAC channel.
+                                              This parameter can be a value of @ref DAC_trigger_selection.
+                                              Note: In case of sawtooth wave generation, this
+                                              trigger corresponds to the step trigger.*/
+
+  uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                               This parameter can be a value of @ref DAC_output_buffer */
+
+  uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral.
+                                              This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */
+
+  uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode
+                                              This parameter must be a value of @ref DAC_UserTrimming
+                                              DAC_UserTrimming is either factory or user trimming */
+
+  uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value
+                                               i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.
+                                               This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
+  DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */
+} DAC_ChannelConfTypeDef;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL DAC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_DAC_CH1_COMPLETE_CB_ID                 = 0x00U,  /*!< DAC CH1 Complete Callback ID      */
+  HAL_DAC_CH1_HALF_COMPLETE_CB_ID            = 0x01U,  /*!< DAC CH1 half Complete Callback ID */
+  HAL_DAC_CH1_ERROR_ID                       = 0x02U,  /*!< DAC CH1 error Callback ID         */
+  HAL_DAC_CH1_UNDERRUN_CB_ID                 = 0x03U,  /*!< DAC CH1 underrun Callback ID      */
+
+  HAL_DAC_CH2_COMPLETE_CB_ID                 = 0x04U,  /*!< DAC CH2 Complete Callback ID      */
+  HAL_DAC_CH2_HALF_COMPLETE_CB_ID            = 0x05U,  /*!< DAC CH2 half Complete Callback ID */
+  HAL_DAC_CH2_ERROR_ID                       = 0x06U,  /*!< DAC CH2 error Callback ID         */
+  HAL_DAC_CH2_UNDERRUN_CB_ID                 = 0x07U,  /*!< DAC CH2 underrun Callback ID      */
+
+  HAL_DAC_MSPINIT_CB_ID                      = 0x08U,  /*!< DAC MspInit Callback ID           */
+  HAL_DAC_MSPDEINIT_CB_ID                    = 0x09U,  /*!< DAC MspDeInit Callback ID         */
+  HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */
+} HAL_DAC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL DAC Callback pointer definition
+  */
+typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants DAC Exported Constants
+  * @{
+  */
+
+/** @defgroup DAC_Error_Code DAC Error Code
+  * @{
+  */
+#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DMA underrun error   */
+#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DMA underrun error   */
+#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */
+#define  HAL_DAC_ERROR_TIMEOUT           0x08U    /*!< Timeout error                     */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_trigger_selection DAC trigger selection
+  * @{
+  */
+#define DAC_TRIGGER_NONE                0x00000000UL                                                                      /*!< DAC (all) conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */
+#define DAC_TRIGGER_SOFTWARE            (                                                                    DAC_CR_TEN1) /*!< DAC (all) conversion started by software trigger for DAC channel */
+#define DAC_TRIGGER_T1_TRGO             (                                                   DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: TIM1 TRGO selected as external conversion trigger for DAC channel. */
+#define DAC_TRIGGER_T8_TRGO             (                                                   DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1/2/4: TIM8 TRGO selected as external conversion trigger for DAC channel. Refer to device datasheet for DACx availability. */
+#define DAC_TRIGGER_T7_TRGO             (                                  DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T15_TRGO            (                                  DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM15 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T2_TRGO             (                 DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< DAC (all): TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T4_TRGO             (                 DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_EXT_IT9             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): EXTI Line9 event selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger */
+#define DAC_TRIGGER_EXT_IT10            (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): EXTI Line10 event selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger */
+#define DAC_TRIGGER_T6_TRGO             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_T3_TRGO             (DAC_CR_TSEL1_3                                                    | DAC_CR_TEN1) /*!< DAC (all): TIM3 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_TRIGGER_HRTIM_RST_TRG1      (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_STEP_TRG1     (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 1 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_RST_TRG2      (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_STEP_TRG2     (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 2 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_RST_TRG3      (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_STEP_TRG3     (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 3 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_RST_TRG4      (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_STEP_TRG4     (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 4 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_RST_TRG5      (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_STEP_TRG5     (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 5 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_RST_TRG6      (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): HRTIM RST TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_STEP_TRG6     (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< DAC (all): HRTIM STEP TRIG 6 selected as external conversion trigger for DAC channel. Note: only to be used as step (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_TRG01         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC1&4: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define DAC_TRIGGER_HRTIM_TRG02         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC2: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
+#define DAC_TRIGGER_HRTIM_TRG03         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< DAC3: HRTIM TRIG OUT 1 selected as external conversion trigger for DAC channel. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer DAC output buffer
+  * @{
+  */
+#define DAC_OUTPUTBUFFER_ENABLE            0x00000000U
+#define DAC_OUTPUTBUFFER_DISABLE           (DAC_MCR_MODE1_1)
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection DAC Channel selection
+  * @{
+  */
+#define DAC_CHANNEL_1                      0x00000000U
+
+#define DAC_CHANNEL_2                      0x00000010U
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignment DAC data alignment
+  * @{
+  */
+#define DAC_ALIGN_12B_R                    0x00000000U
+#define DAC_ALIGN_12B_L                    0x00000004U
+#define DAC_ALIGN_8B_R                     0x00000008U
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_flags_definition DAC flags definition
+  * @{
+  */
+#define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)
+
+#define DAC_FLAG_DMAUDR2                   (DAC_SR_DMAUDR2)
+
+#define DAC_FLAG_DAC1RDY                   (DAC_SR_DAC1RDY)
+
+#define DAC_FLAG_DAC2RDY                   (DAC_SR_DAC2RDY)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_IT_definition  DAC IT definition
+  * @{
+  */
+#define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)
+
+#define DAC_IT_DMAUDR2                   (DAC_SR_DMAUDR2)
+
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral
+  * @{
+  */
+#define DAC_CHIPCONNECT_EXTERNAL       (1UL << 0) /*!< DAC channel output is connected to an external pin.*/
+#define DAC_CHIPCONNECT_INTERNAL       (1UL << 1) /*!< DAC channel  output is connected to on-chip peripherals (via
+                                                       internal paths) and to an external pin. */
+#define DAC_CHIPCONNECT_BOTH           (1UL << 2) /*!< DAC channel  output is connected to on-chip peripherals (via
+                                                       internal paths) and to an external pin.
+                                                       Note: this connection is not available in mode normal
+                                                             with buffer disabled. */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_UserTrimming DAC User Trimming
+  * @{
+  */
+#define DAC_TRIMMING_FACTORY        (0x00000000UL)        /*!< Factory trimming */
+#define DAC_TRIMMING_USER           (0x00000001UL)        /*!< User trimming */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_SampleAndHold DAC power mode
+  * @{
+  */
+#define DAC_SAMPLEANDHOLD_DISABLE     (0x00000000UL)
+#define DAC_SAMPLEANDHOLD_ENABLE      (DAC_MCR_MODE1_2)
+
+/**
+  * @}
+  */
+/** @defgroup DAC_HighFrequency DAC high frequency interface mode
+  * @{
+  */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE        0x00000000UL       /*!< High frequency interface mode disabled */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ    (DAC_MCR_HFSEL_0)  /*!< High frequency interface mode compatible to AHB>80MHz enabled */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ   (DAC_MCR_HFSEL_1)  /*!< High frequency interface mode compatible to AHB>160MHz enabled */
+#define DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC      0x00000002UL       /*!< High frequency interface mode automatic */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Delay for DAC channel voltage settling time from DAC channel startup       */
+/* (transition from disable to enable).                                       */
+/* Note: DAC channel startup time depends on board application environment:   */
+/*       impedance connected to DAC channel output.                           */
+/*       The delay below is specified under conditions:                       */
+/*        - voltage maximum transition (lowest to highest value)              */
+/*        - until voltage reaches final value +-1LSB                          */
+/*        - DAC channel output buffer enabled                                 */
+/*        - load impedance of 5kOhm (min), 50pF (max)                         */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tWAKEUP").                                                      */
+/* Unit: us                                                                   */
+#define DAC_DELAY_STARTUP_US          (15UL)  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Macros DAC Exported Macros
+  * @{
+  */
+
+/** @brief Reset DAC handle state.
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @retval None
+  */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \
+                                                      (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \
+                                                      (__HANDLE__)->MspInitCallback   = NULL;                \
+                                                      (__HANDLE__)->MspDeInitCallback = NULL;                \
+                                                     } while(0)
+#else
+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/** @brief Enable the DAC channel.
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @param  __DAC_Channel__ specifies the DAC channel
+  * @retval None
+  */
+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
+  ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
+
+/** @brief Disable the DAC channel.
+  * @param  __HANDLE__ specifies the DAC handle
+  * @param  __DAC_Channel__ specifies the DAC channel.
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
+  ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))
+
+/** @brief Set DHR12R1 alignment.
+  * @param  __ALIGNMENT__ specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))
+
+
+/** @brief  Set DHR12R2 alignment.
+  * @param  __ALIGNMENT__ specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))
+
+
+/** @brief  Set DHR12RD alignment.
+  * @param  __ALIGNMENT__ specifies the DAC alignment
+  * @retval None
+  */
+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))
+
+/** @brief Enable the DAC interrupt.
+  * @param  __HANDLE__ specifies the DAC handle
+  * @param  __INTERRUPT__ specifies the DAC interrupt.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
+
+/** @brief Disable the DAC interrupt.
+  * @param  __HANDLE__ specifies the DAC handle
+  * @param  __INTERRUPT__ specifies the DAC interrupt.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
+
+/** @brief  Check whether the specified DAC interrupt source is enabled or not.
+  * @param __HANDLE__ DAC handle
+  * @param __INTERRUPT__ DAC interrupt source to check
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt
+  *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval State of interruption (SET or RESET)
+  */
+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR\
+                                                             & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/** @brief  Get the selected DAC's flag status.
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @param  __FLAG__ specifies the DAC flag to get.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
+  *            @arg DAC_FLAG_DAC1RDY DAC channel 1 ready status flag
+  *            @arg DAC_FLAG_DAC2RDY DAC channel 2 ready status flag (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Clear the DAC's flag.
+  * @param  __HANDLE__ specifies the DAC handle.
+  * @param  __FLAG__ specifies the DAC flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag
+  *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Macros DAC Private Macros
+  * @{
+  */
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
+                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
+
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx)
+#define IS_DAC_CHANNEL(DACX, CHANNEL)        \
+  (((DACX) == DAC2) ?                  \
+   ((CHANNEL) == DAC_CHANNEL_1)        \
+   :                                    \
+   (((CHANNEL) == DAC_CHANNEL_1)    || \
+    ((CHANNEL) == DAC_CHANNEL_2)))
+#elif defined(STM32G411xB) || defined(STM32G411xC)
+#define IS_DAC_CHANNEL(DACX, CHANNEL)        \
+  (((DACX) == DAC1) ?                  \
+   ((CHANNEL) == DAC_CHANNEL_1)        \
+   :                                    \
+   (((CHANNEL) == DAC_CHANNEL_1)    || \
+    ((CHANNEL) == DAC_CHANNEL_2)))
+#else
+#define IS_DAC_CHANNEL(DACX, CHANNEL)        \
+  (((CHANNEL) == DAC_CHANNEL_1)     || \
+   ((CHANNEL) == DAC_CHANNEL_2))
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx || STM32G473xx */
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
+                             ((ALIGN) == DAC_ALIGN_12B_L) || \
+                             ((ALIGN) == DAC_ALIGN_8B_R))
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)
+
+#define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x000000FFUL)
+
+/**
+  * @}
+  */
+
+/* Include DAC HAL Extended module */
+#include "stm32g4xx_hal_dac_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @addtogroup DAC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+  * @{
+  */
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);
+void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);
+
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
+                                    uint32_t Alignment);
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
+
+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/* DAC callback registering/unregistering */
+HAL_StatusTypeDef     HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
+                                               pDAC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
+                                        const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group4
+  * @{
+  */
+/* Peripheral State and Error functions ***************************************/
+HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac);
+uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Private_Functions DAC Private Functions
+  * @{
+  */
+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 || DAC2 || DAC3 || DAC4 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32G4xx_HAL_DAC_H */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h
new file mode 100644
index 0000000..bbc7f57
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_dac_ex.h
@@ -0,0 +1,345 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_dac_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of DAC HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_DAC_EX_H
+#define STM32G4xx_HAL_DAC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+#if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
+
+/** @addtogroup DACEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+  * @brief  HAL State structures definition
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
+  * @{
+  */
+
+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude
+  * @{
+  */
+#define DAC_LFSRUNMASK_BIT0                0x00000000UL                                                        /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUNMASK_BITS1_0             (                                                   DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS2_0             (                                  DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS3_0             (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS4_0             (                 DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS5_0             (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS6_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS7_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                   ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TRIANGLEAMPLITUDE_1            0x00000000UL                                                        /*!< Select max triangle amplitude of 1 */
+#define DAC_TRIANGLEAMPLITUDE_3            (                                                   DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
+#define DAC_TRIANGLEAMPLITUDE_7            (                                  DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */
+#define DAC_TRIANGLEAMPLITUDE_15           (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
+#define DAC_TRIANGLEAMPLITUDE_31           (                 DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */
+#define DAC_TRIANGLEAMPLITUDE_63           (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
+#define DAC_TRIANGLEAMPLITUDE_127          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */
+#define DAC_TRIANGLEAMPLITUDE_255          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
+#define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                   ) /*!< Select max triangle amplitude of 511 */
+#define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
+
+/**
+  * @}
+  */
+
+/** @defgroup DACEx_SawtoothPolarityMode DAC Sawtooth polarity mode
+  * @{
+  */
+#define DAC_SAWTOOTH_POLARITY_DECREMENT        0x00000000UL            /*!< Sawtooth wave generation, polarity is decrement */
+#define DAC_SAWTOOTH_POLARITY_INCREMENT        (DAC_STR1_STDIR1)       /*!< Sawtooth wave generation, polarity is increment */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup DACEx_Private_Macros DACEx Private Macros
+  * @{
+  */
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_DAC_TRIGGER(DACX, TRIGGER) \
+  (((TRIGGER) == DAC_TRIGGER_NONE)           || \
+   ((TRIGGER) == DAC_TRIGGER_SOFTWARE)       || \
+   ((TRIGGER) == DAC_TRIGGER_T7_TRGO)        || \
+   ((TRIGGER) == DAC_TRIGGER_T15_TRGO)       || \
+   ((TRIGGER) == DAC_TRIGGER_T2_TRGO)        || \
+   ((TRIGGER) == DAC_TRIGGER_T4_TRGO)        || \
+   ((TRIGGER) == DAC_TRIGGER_EXT_IT9)        || \
+   ((TRIGGER) == DAC_TRIGGER_T6_TRGO)        || \
+   ((TRIGGER) == DAC_TRIGGER_T3_TRGO)        || \
+   ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG1) || \
+   ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG2) || \
+   ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG3) || \
+   ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG4) || \
+   ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG5) || \
+   ((TRIGGER) == DAC_TRIGGER_HRTIM_RST_TRG6) || \
+   (((DACX) == DAC1) &&                         \
+    (((TRIGGER) == DAC_TRIGGER_T8_TRGO)      || \
+     ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01))     \
+   )                                         || \
+   (((DACX) == DAC2) &&                         \
+    (((TRIGGER) == DAC_TRIGGER_T8_TRGO)      || \
+     ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG02))     \
+   )                                         || \
+   (((DACX) == DAC3) &&                         \
+    (((TRIGGER) == DAC_TRIGGER_T1_TRGO)      || \
+     ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG03))     \
+   )                                         || \
+   (((DACX) == DAC4) &&                         \
+    (((TRIGGER) == DAC_TRIGGER_T8_TRGO)      || \
+     ((TRIGGER) == DAC_TRIGGER_HRTIM_TRG01))     \
+   )                                            \
+  )
+#else
+#define IS_DAC_TRIGGER(DACX, TRIGGER) \
+  (((TRIGGER) == DAC_TRIGGER_NONE)           || \
+   ((TRIGGER) == DAC_TRIGGER_SOFTWARE)       || \
+   ((TRIGGER) == DAC_TRIGGER_T7_TRGO)        || \
+   ((TRIGGER) == DAC_TRIGGER_T15_TRGO)       || \
+   ((TRIGGER) == DAC_TRIGGER_T2_TRGO)        || \
+   ((TRIGGER) == DAC_TRIGGER_T4_TRGO)        || \
+   ((TRIGGER) == DAC_TRIGGER_EXT_IT9)        || \
+   ((TRIGGER) == DAC_TRIGGER_T6_TRGO)        || \
+   ((TRIGGER) == DAC_TRIGGER_T3_TRGO)        || \
+   (((DACX) == DAC3) ?                          \
+    ((TRIGGER) == DAC_TRIGGER_T1_TRGO)          \
+    : ((TRIGGER) == DAC_TRIGGER_T8_TRGO)        \
+   )                                            \
+  )
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx */
+
+#if defined(STM32G414xx) || defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_DAC_TRIGGER2(DACX, TRIGGER) \
+  (((TRIGGER) == DAC_TRIGGER_NONE)            || \
+   ((TRIGGER) == DAC_TRIGGER_SOFTWARE)        || \
+   ((TRIGGER) == DAC_TRIGGER_T7_TRGO)         || \
+   ((TRIGGER) == DAC_TRIGGER_T15_TRGO)        || \
+   ((TRIGGER) == DAC_TRIGGER_T2_TRGO)         || \
+   ((TRIGGER) == DAC_TRIGGER_T4_TRGO)         || \
+   ((TRIGGER) == DAC_TRIGGER_EXT_IT10)        || \
+   ((TRIGGER) == DAC_TRIGGER_T6_TRGO)         || \
+   ((TRIGGER) == DAC_TRIGGER_T3_TRGO)         || \
+   ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG1) || \
+   ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG2) || \
+   ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG3) || \
+   ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG4) || \
+   ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG5) || \
+   ((TRIGGER) == DAC_TRIGGER_HRTIM_STEP_TRG6) || \
+   (((DACX) == DAC1) &&                          \
+    ((TRIGGER) == DAC_TRIGGER_T8_TRGO)           \
+   ) ||                                          \
+   (((DACX) == DAC2) &&                          \
+    ((TRIGGER) == DAC_TRIGGER_T8_TRGO)           \
+   ) ||                                          \
+   (((DACX) == DAC3) &&                          \
+    ((TRIGGER) == DAC_TRIGGER_T1_TRGO)           \
+   ) ||                                          \
+   (((DACX) == DAC4) &&                          \
+    ((TRIGGER) == DAC_TRIGGER_T8_TRGO)           \
+   )                                             \
+  )
+#else
+#define IS_DAC_TRIGGER2(DACX, TRIGGER) \
+  (((TRIGGER) == DAC_TRIGGER_NONE)            || \
+   ((TRIGGER) == DAC_TRIGGER_SOFTWARE)        || \
+   ((TRIGGER) == DAC_TRIGGER_T7_TRGO)         || \
+   ((TRIGGER) == DAC_TRIGGER_T15_TRGO)        || \
+   ((TRIGGER) == DAC_TRIGGER_T2_TRGO)         || \
+   ((TRIGGER) == DAC_TRIGGER_T4_TRGO)         || \
+   ((TRIGGER) == DAC_TRIGGER_EXT_IT10)        || \
+   ((TRIGGER) == DAC_TRIGGER_T6_TRGO)         || \
+   ((TRIGGER) == DAC_TRIGGER_T3_TRGO)         || \
+   (((DACX) == DAC3) ?                           \
+    ((TRIGGER) == DAC_TRIGGER_T1_TRGO)           \
+    :((TRIGGER) == DAC_TRIGGER_T8_TRGO)          \
+   )                                             \
+  )
+#endif /* STM32G414xx || STM32G474xx || STM32G484xx */
+#define  IS_DAC_HIGH_FREQUENCY_MODE(MODE) (((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE)         || \
+                                           ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ)     || \
+                                           ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ)    || \
+                                           ((MODE) == DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC))
+
+#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)
+
+#define IS_DAC_HOLDTIME(TIME)   ((TIME) <= 0x000003FFU)
+
+#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \
+                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))
+
+#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
+
+#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)
+
+#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \
+                                         ((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \
+                                         ((CONNECT) == DAC_CHIPCONNECT_BOTH))
+
+#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \
+                                   ((TRIMMING) == DAC_TRIMMING_USER))
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
+
+#define IS_DAC_SAWTOOTH_POLARITY(POLARITY) (((POLARITY) == DAC_SAWTOOTH_POLARITY_DECREMENT) || \
+                                            ((POLARITY) == DAC_SAWTOOTH_POLARITY_INCREMENT))
+
+#define IS_DAC_RESET_DATA(DATA) ((DATA) <= 0x00000FFFUL)
+#define IS_DAC_STEP_DATA(DATA)  ((DATA) <= 0x0000FFFFUL)
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/* Extended features functions ***********************************************/
+
+/** @addtogroup DACEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DACEx_Exported_Functions_Group2
+  * @{
+  */
+/* IO operation functions *****************************************************/
+
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);
+HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity,
+                                                 uint32_t ResetData, uint32_t StepData);
+HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel);
+
+HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);
+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
+                                          const uint32_t *pData, uint32_t Length, uint32_t Alignment);
+HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
+uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac);
+
+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);
+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup DACEx_Exported_Functions_Group3
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
+                                            uint32_t NewTrimmingValue);
+uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DACEx_Private_Functions
+  * @{
+  */
+
+/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */
+/* are called by HAL_DAC_Start_DMA */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 || DAC2 || DAC3 || DAC4 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_DAC_EX_H */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_hrtim.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_hrtim.h
new file mode 100644
index 0000000..2deb9d8
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_hrtim.h
@@ -0,0 +1,5153 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_hrtim.h
+  * @author  MCD Application Team
+  * @brief   Header file of HRTIM HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_HRTIM_H
+#define STM32G4xx_HAL_HRTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+#if defined(HRTIM1)
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup HRTIM HRTIM
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
+  * @{
+  */
+/** @defgroup HRTIM_Max_Timer HRTIM Max Timer
+  * @{
+  */
+#define MAX_HRTIM_TIMER 7U
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Exported_Types HRTIM Exported Types
+  * @{
+  */
+
+/**
+  * @brief  HRTIM Configuration Structure definition - Time base related parameters
+  */
+typedef struct
+{
+  uint32_t HRTIMInterruptRequests;  /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
+                                          This parameter can be any combination of  @ref HRTIM_Common_Interrupt_Enable */
+  uint32_t SyncOptions;              /*!< Specifies how the HRTIM instance handles the external synchronization signals.
+                                          The HRTIM instance can be configured to act as a slave (waiting for a trigger
+                                          to be synchronized) or a master (generating a synchronization signal) or both.
+                                          This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
+  uint32_t SyncInputSource;          /*!< Specifies the external synchronization input source (significant only when
+                                          the HRTIM instance is configured as a slave).
+                                          This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
+  uint32_t SyncOutputSource;         /*!< Specifies the source and event to be sent on the external synchronization outputs
+                                         (significant only when the HRTIM instance is configured as a master).
+                                          This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
+  uint32_t SyncOutputPolarity;       /*!< Specifies the conditioning of the event to be sent on the external synchronization
+                                          outputs (significant only when the HRTIM instance is configured as a master).
+                                          This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
+} HRTIM_InitTypeDef;
+
+/**
+  * @brief  HAL State structures definition
+  */
+typedef enum
+{
+  HAL_HRTIM_STATE_RESET            = 0x00U,    /*!< Peripheral is not yet Initialized                  */
+  HAL_HRTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use           */
+  HAL_HRTIM_STATE_BUSY             = 0x02U,    /*!< an internal process is ongoing                     */
+  HAL_HRTIM_STATE_TIMEOUT          = 0x06U,    /*!< Timeout state                                      */
+  HAL_HRTIM_STATE_ERROR            = 0x07U,    /*!< Error state                                        */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+  HAL_HRTIM_STATE_INVALID_CALLBACK = 0x08U    /*!< Invalid Callback error */
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+} HAL_HRTIM_StateTypeDef;
+
+/**
+  * @brief HRTIM Timer Structure definition
+  */
+typedef struct
+{
+  uint32_t CaptureTrigger1;       /*!< Event(s) triggering capture unit 1.
+                                       When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
+                                       When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
+  uint32_t CaptureTrigger2;       /*!< Event(s) triggering capture unit 2.
+                                       When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
+                                       When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
+  uint32_t InterruptRequests;     /*!< Interrupts requests enabled for the timer. */
+  uint32_t DMARequests;           /*!< DMA requests enabled for the timer. */
+  uint32_t DMASrcAddress;          /*!< Address of the source address of the DMA transfer. */
+  uint32_t DMADstAddress;          /*!< Address of the destination address of the DMA transfer. */
+  uint32_t DMASize;                /*!< Size of the DMA transfer */
+} HRTIM_TimerParamTypeDef;
+
+/**
+  * @brief  HRTIM Handle Structure definition
+  */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+typedef struct __HRTIM_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+{
+  HRTIM_TypeDef               *Instance;                     /*!< Register base address */
+
+  HRTIM_InitTypeDef            Init;                         /*!< HRTIM required parameters */
+
+  HRTIM_TimerParamTypeDef      TimerParam[MAX_HRTIM_TIMER];  /*!< HRTIM timers - including the master - parameters */
+
+  HAL_LockTypeDef              Lock;                         /*!< Locking object          */
+
+  __IO HAL_HRTIM_StateTypeDef  State;                        /*!< HRTIM communication state */
+
+  DMA_HandleTypeDef           *hdmaMaster;                   /*!< Master timer DMA handle parameters */
+  DMA_HandleTypeDef           *hdmaTimerA;                   /*!< Timer A DMA handle parameters */
+  DMA_HandleTypeDef           *hdmaTimerB;                   /*!< Timer B DMA handle parameters */
+  DMA_HandleTypeDef           *hdmaTimerC;                   /*!< Timer C DMA handle parameters */
+  DMA_HandleTypeDef           *hdmaTimerD;                   /*!< Timer D DMA handle parameters */
+  DMA_HandleTypeDef           *hdmaTimerE;                   /*!< Timer E DMA handle parameters */
+  DMA_HandleTypeDef           *hdmaTimerF;                   /*!< Timer F DMA handle parameters */
+
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+  void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 1 interrupt callback function pointer                         */
+  void (* Fault2Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 2 interrupt callback function pointer                         */
+  void (* Fault3Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 3 interrupt callback function pointer                         */
+  void (* Fault4Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 4 interrupt callback function pointer                         */
+  void (* Fault5Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 5 interrupt callback function pointer                         */
+  void (* Fault6Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 6 interrupt callback function pointer                         */
+  void (* SystemFaultCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                          /*!< System fault interrupt callback function pointer                    */
+  void (* DLLCalibrationReadyCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                   /*!< DLL Ready interrupt callback function pointer                       */
+  void (* BurstModePeriodCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                      /*!< Burst mode period interrupt callback function pointer               */
+  void (* SynchronizationEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                 /*!< Sync Input interrupt callback function pointer                      */
+  void (* ErrorCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                                /*!< DMA error callback function pointer                                 */
+
+  void (* RegistersUpdateCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);   /*!< Timer x Update interrupt callback function pointer                  */
+  void (* RepetitionEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);   /*!< Timer x Repetition interrupt callback function pointer              */
+  void (* Compare1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 1 match interrupt callback function pointer         */
+  void (* Compare2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 2 match interrupt callback function pointer         */
+  void (* Compare3EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 3 match interrupt callback function pointer         */
+  void (* Compare4EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 4 match interrupt callback function pointer         */
+  void (* Capture1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Capture 1 interrupts callback function pointer              */
+  void (* Capture2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Capture 2 interrupts callback function pointer              */
+  void (* DelayedProtectionCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Delayed protection interrupt callback function pointer      */
+  void (* CounterResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x counter reset/roll-over interrupt callback function pointer */
+  void (* Output1SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);        /*!< Timer x output 1 set interrupt callback function pointer            */
+  void (* Output1ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x output 1 reset interrupt callback function pointer          */
+  void (* Output2SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);        /*!< Timer x output 2 set interrupt callback function pointer            */
+  void (* Output2ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x output 2 reset interrupt callback function pointer          */
+  void (* BurstDMATransferCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);  /*!< Timer x Burst DMA completed interrupt callback function pointer     */
+
+  void (* MspInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                              /*!< HRTIM MspInit callback function pointer                             */
+  void (* MspDeInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                            /*!< HRTIM MspInit callback function pointer                             */
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+} HRTIM_HandleTypeDef;
+
+/**
+  * @brief  Simple output compare mode configuration definition
+  */
+typedef struct
+{
+  uint32_t Period;                   /*!< Specifies the timer period.
+                                          The period value must be above 3 periods of the fHRTIM clock.
+                                          Maximum value is = 0xFFDFU */
+  uint32_t RepetitionCounter;        /*!< Specifies the timer repetition period.
+                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+  uint32_t PrescalerRatio;           /*!< Specifies the timer clock prescaler ratio.
+                                          This parameter can be any value of @ref HRTIM_Prescaler_Ratio   */
+  uint32_t Mode;                     /*!< Specifies the counter operating mode.
+                                          This parameter can be any value of @ref HRTIM_Counter_Operating_Mode   */
+} HRTIM_TimeBaseCfgTypeDef;
+
+/**
+  * @brief  Simple output compare mode configuration definition
+  */
+typedef struct
+{
+  uint32_t Mode;       /*!< Specifies the output compare mode (toggle, active, inactive).
+                            This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
+  uint32_t Pulse;      /*!< Specifies the compare value to be loaded into the Compare Register.
+                            The compare value must be above or equal to 3 periods of the fHRTIM clock */
+  uint32_t Polarity;   /*!< Specifies the output polarity.
+                            This parameter can be any value of @ref HRTIM_Output_Polarity */
+  uint32_t IdleLevel;  /*!< Specifies whether the output level is active or inactive when in IDLE state.
+                            This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
+} HRTIM_SimpleOCChannelCfgTypeDef;
+
+/**
+  * @brief  Simple PWM output mode configuration definition
+  */
+typedef struct
+{
+  uint32_t Pulse;            /*!< Specifies the compare value to be loaded into the Compare Register.
+                                  The compare value must be above or equal to 3 periods of the fHRTIM clock */
+  uint32_t Polarity;        /*!< Specifies the output polarity.
+                                 This parameter can be any value of @ref HRTIM_Output_Polarity */
+  uint32_t IdleLevel;       /*!< Specifies whether the output level is active or inactive when in IDLE state.
+                                 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
+} HRTIM_SimplePWMChannelCfgTypeDef;
+
+/**
+  * @brief  Simple capture mode configuration definition
+  */
+typedef struct
+{
+  uint32_t Event;             /*!< Specifies the external event triggering the capture.
+                                   This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
+  uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity).
+                                   This parameter can be a value of @ref HRTIM_External_Event_Polarity */
+  uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event.
+                                   This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
+  uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
+                                   This parameter can be a value of @ref HRTIM_External_Event_Filter */
+} HRTIM_SimpleCaptureChannelCfgTypeDef;
+
+/**
+  * @brief  Simple One Pulse mode configuration definition
+  */
+typedef struct
+{
+  uint32_t Pulse;             /*!< Specifies the compare value to be loaded into the Compare Register.
+                                   The compare value must be above or equal to 3 periods of the fHRTIM clock */
+  uint32_t OutputPolarity;    /*!< Specifies the output polarity.
+                                   This parameter can be any value of @ref HRTIM_Output_Polarity */
+  uint32_t OutputIdleLevel;   /*!< Specifies whether the output level is active or inactive when in IDLE state.
+                                   This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
+  uint32_t Event;             /*!< Specifies the external event triggering the pulse generation.
+                                   This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
+  uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity).
+                                   This parameter can be a value of @ref HRTIM_External_Event_Polarity */
+  uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event.
+                                   This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
+  uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
+                                   This parameter can be a value of @ref HRTIM_External_Event_Filter */
+} HRTIM_SimpleOnePulseChannelCfgTypeDef;
+
+/**
+  * @brief  Timer configuration definition
+  */
+typedef struct
+{
+  uint32_t InterruptRequests;      /*!< Relevant for all HRTIM timers, including the master.
+                                       Specifies which interrupts requests must enabled for the timer.
+                                       This parameter can be any combination of  @ref HRTIM_Master_Interrupt_Enable
+                                       or @ref HRTIM_Timing_Unit_Interrupt_Enable */
+  uint32_t DMARequests;            /*!< Relevant for all HRTIM timers, including the master.
+                                       Specifies which DMA requests must be enabled for the timer.
+                                       This parameter can be any combination of  @ref HRTIM_Master_DMA_Request_Enable
+                                       or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
+  uint32_t DMASrcAddress;          /*!< Relevant for all HRTIM timers, including the master.
+                                       Specifies the address of the source address of the DMA transfer */
+  uint32_t DMADstAddress;          /*!< Relevant for all HRTIM timers, including the master.
+                                       Specifies the address of the destination address of the DMA transfer */
+  uint32_t DMASize;                /*!< Relevant for all HRTIM timers, including the master.
+                                       Specifies the size of the DMA transfer */
+  uint32_t HalfModeEnable;         /*!< Relevant for all HRTIM timers, including the master.
+                                        Specifies whether or not half mode is enabled
+                                        This parameter can be any value of @ref HRTIM_Half_Mode_Enable  */
+  uint32_t InterleavedMode;         /*!< Relevant for all HRTIM timers, including the master.
+                                        Specifies whether or not half mode is enabled
+                                        This parameter can be any value of @ref HRTIM_Interleaved_Mode  */
+  uint32_t StartOnSync;            /*!< Relevant for all HRTIM timers, including the master.
+                                       Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
+                                        This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event  */
+  uint32_t ResetOnSync;            /*!< Relevant for all HRTIM timers, including the master.
+                                        Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
+                                        This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event  */
+  uint32_t DACSynchro;             /*!< Relevant for all HRTIM timers, including the master.
+                                        Indicates whether or not the a DAC synchronization event is generated.
+                                        This parameter can be any value of @ref HRTIM_DAC_Synchronization   */
+  uint32_t PreloadEnable;          /*!< Relevant for all HRTIM timers, including the master.
+                                        Specifies whether or not register preload is enabled.
+                                        This parameter can be any value of @ref HRTIM_Register_Preload_Enable  */
+  uint32_t UpdateGating;           /*!< Relevant for all HRTIM timers, including the master.
+                                        Specifies how the update occurs with respect to a burst DMA transaction or
+                                        update enable inputs (Slave timers only).
+                                        This parameter can be any value of @ref HRTIM_Update_Gating   */
+  uint32_t BurstMode;              /*!< Relevant for all HRTIM timers, including the master.
+                                        Specifies how the timer behaves during a burst mode operation.
+                                        This parameter can be any value of @ref HRTIM_Timer_Burst_Mode  */
+  uint32_t RepetitionUpdate;       /*!< Relevant for all HRTIM timers, including the master.
+                                        Specifies whether or not registers update is triggered by the repetition event.
+                                        This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
+  uint32_t PushPull;               /*!< Relevant for Timer A to Timer F.
+                                        Specifies whether or not the push-pull mode is enabled.
+                                        This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
+  uint32_t FaultEnable;            /*!< Relevant for Timer A to Timer F.
+                                        Specifies which fault channels are enabled for the timer.
+                                        This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling  */
+  uint32_t FaultLock;              /*!< Relevant for Timer A to Timer F.
+                                        Specifies whether or not fault enabling status is write protected.
+                                        This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
+  uint32_t DeadTimeInsertion;      /*!< Relevant for Timer A to Timer F.
+                                        Specifies whether or not dead-time insertion is enabled for the timer.
+                                        This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
+  uint32_t DelayedProtectionMode;  /*!< Relevant for Timer A to Timer F.
+                                        Specifies the delayed protection mode.
+                                        This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
+  uint32_t BalancedIdleAutomaticResume; /*!< Indicates whether or not outputs are automatically re-enabled after a balanced idle event.
+                                             This parameters can be any value of @ref HRTIM_Output_Balanced_Idle_Auto_Resume */
+  uint32_t UpdateTrigger;          /*!< Relevant for Timer A to Timer F.
+                                        Specifies source(s) triggering the timer registers update.
+                                        This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
+  uint32_t ResetTrigger;           /*!< Relevant for Timer A to Timer F.
+                                        Specifies source(s) triggering the timer counter reset.
+                                        This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
+  uint32_t ResetUpdate;           /*!<  Relevant for Timer A to Timer F.
+                                        Specifies whether or not registers update is triggered when the timer counter is reset.
+                                        This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
+  uint32_t ReSyncUpdate;          /*!<  Relevant for Timer A to Timer F.
+                                        Specifies whether update source is coming from the timing unit @ref HRTIM_Timer_ReSyncUpdate */
+
+} HRTIM_TimerCfgTypeDef;
+
+/**
+  * @brief  Timer control definition
+  */
+typedef struct
+{
+  uint32_t UpDownMode;            /*!<  Relevant for Timer A to Timer F.
+                                        Specifies whether or not counter is operating in up or up-down counting mode.
+                                        This parameter can be a value of @ref HRTIM_Timer_UpDown_Mode */
+  uint32_t TrigHalf;              /*!<  Relevant for Timer A to Timer F.
+                                        Specifies whether or not compare 2 is operating in Trigger half mode.
+                                        This parameter can be a value of @ref HRTIM_Timer_TrigHalf_Mode */
+  uint32_t GreaterCMP3;           /*!<  Relevant for Timer A to Timer F.
+                                        Specifies whether or not compare 3 is operating in compare match or greater mode.
+                                        This parameter can be a value of @ref HRTIM_Timer_GreaterCMP3_Mode */
+  uint32_t GreaterCMP1;           /*!<  Relevant for Timer A to Timer F.
+                                        Specifies whether or not compare 1 is operating in compare match or greater mode.
+                                        This parameter can be a value of @ref HRTIM_Timer_GreaterCMP1_Mode */
+  uint32_t DualChannelDacReset;   /*!<  Relevant for Timer A to Timer F.
+                                        Specifies how the hrtim_dac_reset_trgx trigger is generated.
+                                        This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Reset */
+  uint32_t DualChannelDacStep;    /*!<  Relevant for Timer A to Timer F.
+                                        Specifies how the hrtim_dac_step_trgx trigger is generated.
+                                        This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Step */
+  uint32_t DualChannelDacEnable;  /*!<  Relevant for Timer A to Timer F.
+                                        Enables or not the dual channel DAC triggering mechanism.
+                                        This parameter can be a value of @ref HRTIM_Timer_DualChannelDac_Enable */
+} HRTIM_TimerCtlTypeDef;
+
+/**
+  * @brief  Compare unit configuration definition
+  */
+typedef struct
+{
+  uint32_t CompareValue;         /*!< Specifies the compare value of the timer compare unit.
+                                      The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
+                                      The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
+  uint32_t AutoDelayedMode;      /*!< Specifies the auto delayed mode for compare unit 2 or 4.
+                                      This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
+  uint32_t AutoDelayedTimeout;   /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
+                                      CompareValue +  AutoDelayedTimeout must be less than 0xFFFFU */
+} HRTIM_CompareCfgTypeDef;
+
+/**
+  * @brief  Capture unit content definition
+  */
+typedef struct
+{
+  uint32_t Value;     /*!< Holds the counter value when the capture event occurred.
+                           This parameter can be a number between 0x0 and 0xFFFFU */
+  uint32_t Dir ;     /*!< Holds the counting direction value  when the capture event occurred.
+                           This parameter can be a value of @ref HRTIM_Timer_UpDown_Mode  */
+} HRTIM_CaptureValueTypeDef;
+
+/**
+  * @brief  Capture unit configuration definition
+  */
+typedef struct
+{
+  uint64_t Trigger;          /*!< Specifies source(s) triggering the capture.
+                                  This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
+} HRTIM_CaptureCfgTypeDef;
+
+/**
+  * @brief  Output configuration definition
+  */
+typedef struct
+{
+  uint32_t Polarity;                    /*!< Specifies the output polarity.
+                                             This parameter can be any value of @ref HRTIM_Output_Polarity */
+  uint32_t SetSource;                   /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
+                                             This parameter can be a combination of @ref HRTIM_Output_Set_Source */
+  uint32_t ResetSource;                 /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
+                                             This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
+  uint32_t IdleMode;                    /*!< Specifies whether or not the output is affected by a burst mode operation.
+                                             This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
+  uint32_t IdleLevel;                   /*!< Specifies whether the output level is active or inactive when in IDLE state.
+                                             This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
+  uint32_t FaultLevel;                  /*!< Specifies whether the output level is active or inactive when in FAULT state.
+                                             This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
+  uint32_t ChopperModeEnable;           /*!< Indicates whether or not the chopper mode is enabled
+                                             This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
+  uint32_t BurstModeEntryDelayed;       /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
+                                             This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
+} HRTIM_OutputCfgTypeDef;
+
+/**
+  * @brief  External event filtering in timing units configuration definition
+  */
+typedef struct
+{
+  uint32_t Filter;       /*!< Specifies the type of event filtering within the timing unit.
+                             This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
+  uint32_t Latch;       /*!< Specifies whether or not the signal is latched.
+                             This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
+} HRTIM_TimerEventFilteringCfgTypeDef;
+
+/**
+  * @brief  Dead time feature configuration definition
+  */
+typedef struct
+{
+  uint32_t Prescaler;        /*!< Specifies the dead-time prescaler.
+                                  This parameter can be a value of @ref  HRTIM_Deadtime_Prescaler_Ratio */
+  uint32_t RisingValue;      /*!< Specifies the dead-time following a rising edge.
+                                  This parameter can be a number between 0x0 and 0x1FFU */
+  uint32_t RisingSign;       /*!< Specifies whether the dead-time is positive or negative on rising edge.
+                                  This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
+  uint32_t RisingLock;       /*!< Specifies whether or not dead-time rising settings (value and sign) are write protected.
+                                  This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
+  uint32_t RisingSignLock;   /*!< Specifies whether or not dead-time rising sign is write protected.
+                                  This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
+  uint32_t FallingValue;     /*!< Specifies the dead-time following a falling edge.
+                                  This parameter can be a number between 0x0 and 0x1FFU */
+  uint32_t FallingSign;      /*!< Specifies whether the dead-time is positive or negative on falling edge.
+                                  This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
+  uint32_t FallingLock;      /*!< Specifies whether or not dead-time falling settings (value and sign) are write protected.
+                                  This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
+  uint32_t FallingSignLock;  /*!< Specifies whether or not dead-time falling sign is write protected.
+                                  This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
+} HRTIM_DeadTimeCfgTypeDef;
+
+/**
+  * @brief  Chopper mode configuration definition
+  */
+typedef struct
+{
+  uint32_t CarrierFreq;  /*!< Specifies the Timer carrier frequency value.
+                              This parameter can be a value of @ref HRTIM_Chopper_Frequency */
+  uint32_t DutyCycle;    /*!< Specifies the Timer chopper duty cycle value.
+                              This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
+  uint32_t StartPulse;   /*!< Specifies the Timer pulse width value.
+                              This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
+} HRTIM_ChopperModeCfgTypeDef;
+
+/**
+  * @brief  External event channel configuration definition
+  */
+typedef struct
+{
+  uint32_t Source;        /*!< Identifies the source of the external event.
+                               This parameter can be a value of @ref HRTIM_External_Event_Sources */
+  uint32_t Polarity;      /*!< Specifies the polarity of the external event (in case of level sensitivity).
+                               This parameter can be a value of @ref HRTIM_External_Event_Polarity */
+  uint32_t Sensitivity;   /*!< Specifies the sensitivity of the external event.
+                               This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
+  uint32_t Filter;        /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
+                               This parameter can be a value of @ref HRTIM_External_Event_Filter */
+  uint32_t FastMode;      /*!< Indicates whether or not low latency mode is enabled for the external event.
+                               This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
+} HRTIM_EventCfgTypeDef;
+
+/**
+  * @brief  Fault channel configuration definition
+  */
+typedef struct
+{
+  uint32_t Source;        /*!< Identifies the source of the fault.
+                               This parameter can be a value of @ref HRTIM_Fault_Sources */
+  uint32_t Polarity;      /*!< Specifies the polarity of the fault event.
+                               This parameter can be a value of @ref HRTIM_Fault_Polarity */
+  uint32_t Filter;        /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
+                               This parameter can be a value of @ref HRTIM_Fault_Filter */
+  uint32_t Lock;          /*!< Indicates whether or not fault programming bits are write protected.
+                               This parameter can be a value of @ref HRTIM_Fault_Lock */
+} HRTIM_FaultCfgTypeDef;
+
+typedef struct
+{
+  uint32_t Threshold;     /*!< Specifies the Fault counter Threshold.
+                               This parameter can be a number between 0x0 and 0xF  */
+  uint32_t ResetMode;     /*!< Specifies the reset mode of a fault event counter.
+                               This parameter can be a value of @ref HRTIM_Fault_ResetMode */
+  uint32_t BlankingSource;/*!< Specifies the blanking source of a fault event.
+                               This parameter can be a value of @ref HRTIM_Fault_Blanking */
+} HRTIM_FaultBlankingCfgTypeDef;
+
+/**
+  * @brief  Burst mode configuration definition
+  */
+typedef struct
+{
+  uint32_t Mode;           /*!< Specifies the burst mode operating mode.
+                                This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
+  uint32_t ClockSource;    /*!< Specifies the burst mode clock source.
+                                This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
+  uint32_t Prescaler;      /*!< Specifies the burst mode prescaler.
+                                This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
+  uint32_t PreloadEnable;  /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
+                                This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable  */
+  uint32_t Trigger;        /*!< Specifies the event(s) triggering the burst operation.
+                                This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger  */
+  uint32_t IdleDuration;   /*!< Specifies number of periods during which the selected timers are in idle state.
+                                This parameter can be a number between 0x0 and 0xFFFF  */
+  uint32_t Period;         /*!< Specifies burst mode repetition period.
+                                This parameter can be a number between 0x1 and 0xFFFF  */
+} HRTIM_BurstModeCfgTypeDef;
+
+/**
+  * @brief  ADC trigger configuration definition
+  */
+typedef struct
+{
+  uint32_t UpdateSource;  /*!< Specifies the ADC trigger update source.
+                               This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source  */
+  uint32_t Trigger;       /*!< Specifies the event(s) triggering the ADC conversion.
+                               This parameter can be a combination of @ref HRTIM_ADC_Trigger_Event  */
+} HRTIM_ADCTriggerCfgTypeDef;
+
+/**
+  * @brief  External Event Counter A or B configuration definition
+  */
+typedef struct
+{
+  uint32_t ResetMode;      /*!< Specifies the External Event Counter A or B Reset Mode.
+                                This parameter can be a value of @ref HRTIM_Timer_External_Event_ResetMode  */
+  uint32_t Source;         /*!< Specifies the External Event Counter source selection.
+                                This parameter can be one of @ref HRTIM_External_Event_Channels  */
+  uint32_t Counter;        /*!< Specifies the External Event Counter Threshold.
+                                This parameter can be a number between 0x0 and 0x3F  */
+} HRTIM_ExternalEventCfgTypeDef;
+
+
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL HRTIM Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_HRTIM_FAULT1CALLBACK_CB_ID               = 0x00U, /*!< Fault 1 interrupt callback ID                         */
+  HAL_HRTIM_FAULT2CALLBACK_CB_ID               = 0x01U, /*!< Fault 2 interrupt callback ID                         */
+  HAL_HRTIM_FAULT3CALLBACK_CB_ID               = 0x02U, /*!< Fault 3 interrupt callback ID                         */
+  HAL_HRTIM_FAULT4CALLBACK_CB_ID               = 0x03U, /*!< Fault 4 interrupt callback ID                         */
+  HAL_HRTIM_FAULT5CALLBACK_CB_ID               = 0x04U, /*!< Fault 5 interrupt callback ID                         */
+  HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID          = 0x05U, /*!< System fault interrupt callback ID                    */
+  HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID   = 0x06U, /*!< DLL Ready interrupt callback ID                       */
+  HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID      = 0x07U, /*!< Burst mode period interrupt callback ID               */
+  HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID = 0x08U, /*!< Sync Input interrupt callback ID                      */
+  HAL_HRTIM_ERRORCALLBACK_CB_ID                = 0x09U, /*!< DMA error callback ID                                 */
+
+  HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID      = 0x10U, /*!< Timer x Update interrupt callback ID                  */
+  HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID      = 0x11U, /*!< Timer x Repetition interrupt callback ID              */
+  HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID        = 0x12U, /*!< Timer x Compare 1 match interrupt callback ID         */
+  HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID        = 0x13U, /*!< Timer x Compare 2 match interrupt callback ID         */
+  HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID        = 0x14U, /*!< Timer x Compare 3 match interrupt callback ID         */
+  HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID        = 0x15U, /*!< Timer x Compare 4 match interrupt callback ID         */
+  HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID        = 0x16U, /*!< Timer x Capture 1 interrupts callback ID              */
+  HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID        = 0x17U, /*!< Timer x Capture 2 interrupts callback ID              */
+  HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID    = 0x18U, /*!< Timer x Delayed protection interrupt callback ID      */
+  HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID         = 0x19U, /*!< Timer x counter reset/roll-over interrupt callback ID */
+  HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID           = 0x1AU, /*!< Timer x output 1 set interrupt callback ID            */
+  HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID         = 0x1BU, /*!< Timer x output 1 reset interrupt callback ID          */
+  HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID           = 0x1CU, /*!< Timer x output 2 set interrupt callback ID            */
+  HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID         = 0x1DU, /*!< Timer x output 2 reset interrupt callback ID          */
+  HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID     = 0x1EU, /*!< Timer x Burst DMA completed interrupt callback ID     */
+
+  HAL_HRTIM_MSPINIT_CB_ID                      = 0x20U, /*!< HRTIM MspInit callback ID                             */
+  HAL_HRTIM_MSPDEINIT_CB_ID                    = 0x21U, /*!< HRTIM MspInit callback ID                             */
+  HAL_HRTIM_FAULT6CALLBACK_CB_ID               = 0x22U, /*!< Fault 6 interrupt callback ID                         */
+} HAL_HRTIM_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL HRTIM Callback function pointer definitions
+  */
+typedef void (* pHRTIM_CallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim);       /*!< HRTIM related callback function pointer         */
+
+typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!< HRTIM Timer x related callback function pointer */
+                                            uint32_t TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
+  * @{
+  */
+
+/** @defgroup HRTIM_Timer_Index HRTIM Timer Index
+  * @{
+  * @brief Constants defining the timer indexes
+  */
+#define HRTIM_TIMERINDEX_TIMER_A 0x0U   /*!< Index used to access timer A registers */
+#define HRTIM_TIMERINDEX_TIMER_B 0x1U   /*!< Index used to access timer B registers */
+#define HRTIM_TIMERINDEX_TIMER_C 0x2U   /*!< Index used to access timer C registers */
+#define HRTIM_TIMERINDEX_TIMER_D 0x3U   /*!< Index used to access timer D registers */
+#define HRTIM_TIMERINDEX_TIMER_E 0x4U   /*!< Index used to access timer E registers */
+#define HRTIM_TIMERINDEX_TIMER_F 0x5U   /*!< Index used to access timer F registers */
+#define HRTIM_TIMERINDEX_MASTER  0x6U   /*!< Index used to access master registers  */
+#define HRTIM_TIMERINDEX_COMMON  0xFFU  /*!< Index used to access HRTIM common registers */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
+  * @{
+  * @brief Constants defining timer identifiers
+  */
+#define HRTIM_TIMERID_MASTER  (HRTIM_MCR_MCEN)   /*!< Master identifier  */
+#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN)  /*!< Timer A identifier */
+#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN)  /*!< Timer B identifier */
+#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN)  /*!< Timer C identifier */
+#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN)  /*!< Timer D identifier */
+#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN)  /*!< Timer E identifier */
+#define HRTIM_TIMERID_TIMER_F (HRTIM_MCR_TFCEN)  /*!< Timer F identifier */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
+  * @{
+  * @brief Constants defining compare unit identifiers
+  */
+#define HRTIM_COMPAREUNIT_1 0x00000001U  /*!< Compare unit 1 identifier */
+#define HRTIM_COMPAREUNIT_2 0x00000002U  /*!< Compare unit 2 identifier */
+#define HRTIM_COMPAREUNIT_3 0x00000004U  /*!< Compare unit 3 identifier */
+#define HRTIM_COMPAREUNIT_4 0x00000008U  /*!< Compare unit 4 identifier */
+/**
+  * @}
+ */
+
+/** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
+  * @{
+  * @brief Constants defining capture unit identifiers
+  */
+#define HRTIM_CAPTUREUNIT_1 0x00000001U  /*!< Capture unit 1 identifier */
+#define HRTIM_CAPTUREUNIT_2 0x00000002U  /*!< Capture unit 2 identifier */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_Output HRTIM Timer Output
+  * @{
+  * @brief Constants defining timer output identifiers
+  */
+#define HRTIM_OUTPUT_TA1  0x00000001U  /*!< Timer A - Output 1 identifier */
+#define HRTIM_OUTPUT_TA2  0x00000002U  /*!< Timer A - Output 2 identifier */
+#define HRTIM_OUTPUT_TB1  0x00000004U  /*!< Timer B - Output 1 identifier */
+#define HRTIM_OUTPUT_TB2  0x00000008U  /*!< Timer B - Output 2 identifier */
+#define HRTIM_OUTPUT_TC1  0x00000010U  /*!< Timer C - Output 1 identifier */
+#define HRTIM_OUTPUT_TC2  0x00000020U  /*!< Timer C - Output 2 identifier */
+#define HRTIM_OUTPUT_TD1  0x00000040U  /*!< Timer D - Output 1 identifier */
+#define HRTIM_OUTPUT_TD2  0x00000080U  /*!< Timer D - Output 2 identifier */
+#define HRTIM_OUTPUT_TE1  0x00000100U  /*!< Timer E - Output 1 identifier */
+#define HRTIM_OUTPUT_TE2  0x00000200U  /*!< Timer E - Output 2 identifier */
+#define HRTIM_OUTPUT_TF1  0x00000400U  /*!< Timer F - Output 1 identifier */
+#define HRTIM_OUTPUT_TF2  0x00000800U  /*!< Timer F - Output 2 identifier */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
+  * @{
+  * @brief Constants defining ADC triggers identifiers
+  */
+#define HRTIM_ADCTRIGGER_1  0x00000001U  /*!< ADC trigger 1 identifier */
+#define HRTIM_ADCTRIGGER_2  0x00000002U  /*!< ADC trigger 2 identifier */
+#define HRTIM_ADCTRIGGER_3  0x00000004U  /*!< ADC trigger 3 identifier */
+#define HRTIM_ADCTRIGGER_4  0x00000008U  /*!< ADC trigger 4 identifier */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_ADC_Ext_Trigger HRTIM ADC Extended Trigger
+  * @{
+  * @brief Constants defining ADC Extended triggers identifiers
+  */
+#define HRTIM_ADCTRIGGER_5  0x00000010U  /*!< ADC trigger 5 identifier  */
+#define HRTIM_ADCTRIGGER_6  0x00000020U  /*!< ADC trigger 6 identifier  */
+#define HRTIM_ADCTRIGGER_7  0x00000040U  /*!< ADC trigger 7 identifier  */
+#define HRTIM_ADCTRIGGER_8  0x00000080U  /*!< ADC trigger 8 identifier  */
+#define HRTIM_ADCTRIGGER_9  0x00000100U  /*!< ADC trigger 9 identifier  */
+#define HRTIM_ADCTRIGGER_10 0x00000200U  /*!< ADC trigger 10 identifier */
+
+#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
+  (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_5)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_6)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_7)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_8)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_9)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_10))
+#define IS_HRTIM_ADCEXTTRIGGER(ADCTRIGGER)\
+  (((ADCTRIGGER) == HRTIM_ADCTRIGGER_5)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_6)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_7)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_8)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_9)   || \
+   ((ADCTRIGGER) == HRTIM_ADCTRIGGER_10))
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
+  * @{
+  * @brief Constants defining external event channel identifiers
+  */
+#define HRTIM_EVENT_NONE    (0x00000000U)     /*!< Undefined event channel */
+#define HRTIM_EVENT_1       (0x00000001U)     /*!< External event channel 1  identifier */
+#define HRTIM_EVENT_2       (0x00000002U)     /*!< External event channel 2  identifier */
+#define HRTIM_EVENT_3       (0x00000003U)     /*!< External event channel 3  identifier */
+#define HRTIM_EVENT_4       (0x00000004U)     /*!< External event channel 4  identifier */
+#define HRTIM_EVENT_5       (0x00000005U)     /*!< External event channel 5  identifier */
+#define HRTIM_EVENT_6       (0x00000006U)     /*!< External event channel 6  identifier */
+#define HRTIM_EVENT_7       (0x00000007U)     /*!< External event channel 7  identifier */
+#define HRTIM_EVENT_8       (0x00000008U)     /*!< External event channel 8  identifier */
+#define HRTIM_EVENT_9       (0x00000009U)     /*!< External event channel 9  identifier */
+#define HRTIM_EVENT_10      (0x0000000AU)     /*!< External event channel 10 identifier */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
+  * @{
+  * @brief Constants defining fault channel identifiers
+  */
+#define HRTIM_FAULT_1      (0x01U)     /*!< Fault channel 1 identifier */
+#define HRTIM_FAULT_2      (0x02U)     /*!< Fault channel 2 identifier */
+#define HRTIM_FAULT_3      (0x04U)     /*!< Fault channel 3 identifier */
+#define HRTIM_FAULT_4      (0x08U)     /*!< Fault channel 4 identifier */
+#define HRTIM_FAULT_5      (0x10U)     /*!< Fault channel 5 identifier */
+#define HRTIM_FAULT_6      (0x20U)     /*!< Fault channel 6 identifier */
+/**
+  * @}
+  */
+
+
+/** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
+  * @{
+  * @brief Constants defining timer high-resolution clock prescaler ratio.
+ */
+#define HRTIM_PRESCALERRATIO_MUL32    (0x00000000U)  /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL16    (0x00000001U)  /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
+#define HRTIM_PRESCALERRATIO_MUL8     (0x00000002U)  /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)  */
+#define HRTIM_PRESCALERRATIO_MUL4     (0x00000003U)  /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)    */
+#define HRTIM_PRESCALERRATIO_MUL2     (0x00000004U)  /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)    */
+#define HRTIM_PRESCALERRATIO_DIV1     (0x00000005U)  /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)         */
+#define HRTIM_PRESCALERRATIO_DIV2     (0x00000006U)  /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)     */
+#define HRTIM_PRESCALERRATIO_DIV4     (0x00000007U)  /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)        */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
+  * @{
+  * @brief Constants defining timer counter operating mode.
+  */
+#define HRTIM_MODE_CONTINUOUS               (0x00000008U)  /*!< The timer operates in continuous (free-running) mode */
+#define HRTIM_MODE_SINGLESHOT               (0x00000000U)  /*!< The timer operates in non retriggerable single-shot mode */
+#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U)  /*!< The timer operates in retriggerable single-shot mode */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
+  * @{
+  * @brief Constants defining half mode enabling status.
+  */
+#define HRTIM_HALFMODE_DISABLED (0x00000000U)  /*!< Half mode is disabled */
+#define HRTIM_HALFMODE_ENABLED  (0x00000020U)  /*!< Half mode is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Interleaved_Mode HRTIM Interleaved Mode
+  * @{
+  * @brief Constants defining interleaved mode enabling status.
+  */
+#define HRTIM_INTERLEAVED_MODE_DISABLED      0x000U               /*!< HRTIM interleaved Mode is disabled */
+#define HRTIM_INTERLEAVED_MODE_DUAL          0x002U               /*!< HRTIM interleaved Mode is Half */
+#define HRTIM_INTERLEAVED_MODE_TRIPLE        0x003U               /*!< HRTIM interleaved Mode is Triple */
+#define HRTIM_INTERLEAVED_MODE_QUAD          0x004U               /*!< HRTIM interleaved Mode is Quad */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
+  * @{
+  * @brief Constants defining the timer behavior following the synchronization event
+  */
+#define HRTIM_SYNCSTART_DISABLED (0x00000000U)           /*!< Synchronization input event has effect on the timer */
+#define HRTIM_SYNCSTART_ENABLED  (HRTIM_MCR_SYNCSTRTM)   /*!< Synchronization input event starts the timer */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
+  * @{
+  * @brief Constants defining the timer behavior following the synchronization event
+  */
+#define HRTIM_SYNCRESET_DISABLED (0x00000000U)           /*!< Synchronization input event has effect on the timer */
+#define HRTIM_SYNCRESET_ENABLED  (HRTIM_MCR_SYNCRSTM)    /*!< Synchronization input event resets the timer */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
+  * @{
+  * @brief Constants defining on which output the DAC synchronization event is sent
+  */
+#define HRTIM_DACSYNC_NONE          0x00000000U                                 /*!< No DAC synchronization event generated */
+#define HRTIM_DACSYNC_DACTRIGOUT_1  (HRTIM_MCR_DACSYNC_0)                       /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
+#define HRTIM_DACSYNC_DACTRIGOUT_2  (HRTIM_MCR_DACSYNC_1)                       /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
+#define HRTIM_DACSYNC_DACTRIGOUT_3  (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
+  * @{
+  * @brief Constants defining whether a write access into a preloadable
+  *        register is done into the active or the preload register.
+  */
+#define HRTIM_PRELOAD_DISABLED (0x00000000U)           /*!< Preload disabled: the write access is directly done into the active register */
+#define HRTIM_PRELOAD_ENABLED  (HRTIM_MCR_PREEN)       /*!< Preload enabled: the write access is done into the preload register */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Update_Gating HRTIM Update Gating
+  * @{
+  * @brief Constants defining how the update occurs relatively to the burst DMA
+  *        transaction and the external update request on update enable inputs 1 to 3.
+  */
+#define HRTIM_UPDATEGATING_INDEPENDENT     0x00000000U                                                           /*!< Update done independently from the DMA burst transfer completion */
+#define HRTIM_UPDATEGATING_DMABURST        (HRTIM_TIMCR_UPDGAT_0)                                                /*!< Update done when the DMA burst transfer is completed */
+#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)                                                /*!< Update done on timer roll-over following a DMA burst transfer completion*/
+#define HRTIM_UPDATEGATING_UPDEN1          (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */
+#define HRTIM_UPDATEGATING_UPDEN2          (HRTIM_TIMCR_UPDGAT_2)                                                /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */
+#define HRTIM_UPDATEGATING_UPDEN3          (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */
+#define HRTIM_UPDATEGATING_UPDEN1_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)                         /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 1U */
+#define HRTIM_UPDATEGATING_UPDEN2_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)  /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 2U */
+#define HRTIM_UPDATEGATING_UPDEN3_UPDATE   (HRTIM_TIMCR_UPDGAT_3)                                                /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 3U */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
+  * @{
+  * @brief Constants defining how the timer behaves during a burst
+            mode operation.
+  */
+#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x00000000U           /*!< Timer counter clock is maintained and the timer operates normally */
+#define HRTIM_TIMERBURSTMODE_RESETCOUNTER  (HRTIM_BMCR_MTBM)     /*!< Timer counter clock is stopped and the counter is reset */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_UpDown_Mode HRTIM Timer UpDown Mode
+  * @{
+  * @brief Constants defining how the timer counter operates
+  */
+#define HRTIM_TIMERUPDOWNMODE_UP           0x00000000U           /*!< Timer counter is operating in up-counting mode */
+#define HRTIM_TIMERUPDOWNMODE_UPDOWN       0x00000001U           /*!< Timer counter is operating in up-down counting mode */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode
+  * @{
+  * @brief Constants defining how the timer counter operates
+  */
+#define HRTIM_TIMERTRIGHALF_DISABLED       0x00000000U           /*!< Timer Compare 2 register is behaving in standard mode */
+#define HRTIM_TIMERTRIGHALF_ENABLED        (HRTIM_TIMCR2_TRGHLF) /*!< Timer Compare 2 register is behaving in triggered-half mode */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_GreaterCMP3_Mode HRTIM Timer Greater than Compare 3 PWM Mode
+  * @{
+  * @brief Constants defining how the timer compare operates
+  */
+#define HRTIM_TIMERGTCMP3_EQUAL            0x00000000U           /*!< Timer Compare 3 event is generated when counter is equal */
+#define HRTIM_TIMERGTCMP3_GREATER          (HRTIM_TIMCR2_GTCMP3) /*!< Timer Compare 3 Reset event is generated when counter is greater */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_GreaterCMP1_Mode HRTIM Timer Greater than Compare 1 PWM Mode
+  * @{
+  * @brief Constants defining how the timer compare operates
+  */
+#define HRTIM_TIMERGTCMP1_EQUAL            0x00000000U           /*!< Timer Compare 1 event is generated when counter is equal */
+#define HRTIM_TIMERGTCMP1_GREATER          (HRTIM_TIMCR2_GTCMP1) /*!< Timer Compare 1 event is generated when counter is greater */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_DualChannelDac_Reset HRTIM Dual Channel Dac Reset Trigger
+  * @{
+  * @brief Constants defining when the hrtim_dac_reset_trgx trigger is generated
+  */
+#define HRTIM_TIMER_DCDR_COUNTER           0x00000000U           /*!< the trigger is generated on counter reset or roll-over event */
+#define HRTIM_TIMER_DCDR_OUT1SET           (HRTIM_TIMCR2_DCDR)   /*!< the trigger is generated on output 1 set event */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_DualChannelDac_Step HRTIM Dual Channel Dac Step Trigger
+  * @{
+  * @brief Constants defining when the hrtim_dac_step_trgx trigger is generated
+ is generated
+  */
+#define HRTIM_TIMER_DCDS_CMP2              0x00000000U           /*!< the trigger is generated on compare 2 event */
+#define HRTIM_TIMER_DCDS_OUT1RST           (HRTIM_TIMCR2_DCDS)   /*!< the trigger is generated on output 1 reset event */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_DualChannelDac_Enable HRTIM Dual Channel DAC Trigger Enable
+  * @{
+  * @brief Constants enabling the dual channel DAC triggering mechanism
+  */
+#define HRTIM_TIMER_DCDE_DISABLED          0x00000000U           /*!< the Dual channel DAC trigger is disabled */
+#define HRTIM_TIMER_DCDE_ENABLED           (HRTIM_TIMCR2_DCDE)   /*!< the Dual channel DAC trigger is enabled */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
+  * @{
+  * @brief Constants defining whether registers are updated when the timer
+  *        repetition period is completed (either due to roll-over or
+  *        reset events)
+  */
+#define HRTIM_UPDATEONREPETITION_DISABLED  0x00000000U           /*!< Update on repetition disabled */
+#define HRTIM_UPDATEONREPETITION_ENABLED   (HRTIM_MCR_MREPU)     /*!< Update on repetition enabled */
+/**
+  * @}
+  */
+
+
+/** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
+  * @{
+  * @brief Constants defining whether or not the push-pull mode is enabled for
+  *        a timer.
+  */
+#define HRTIM_TIMPUSHPULLMODE_DISABLED     0x00000000U           /*!< Push-Pull mode disabled */
+#define HRTIM_TIMPUSHPULLMODE_ENABLED      (HRTIM_TIMCR_PSHPLL)  /*!< Push-Pull mode enabled */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
+  * @{
+  * @brief Constants defining whether a fault channel is enabled for a timer
+  */
+#define HRTIM_TIMFAULTENABLE_NONE     0x00000000U           /*!< No fault enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT1   (HRTIM_FLTR_FLT1EN)   /*!< Fault 1 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT2   (HRTIM_FLTR_FLT2EN)   /*!< Fault 2 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT3   (HRTIM_FLTR_FLT3EN)   /*!< Fault 3 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT4   (HRTIM_FLTR_FLT4EN)   /*!< Fault 4 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT5   (HRTIM_FLTR_FLT5EN)   /*!< Fault 5 enabled */
+#define HRTIM_TIMFAULTENABLE_FAULT6   (HRTIM_FLTR_FLT6EN)   /*!< Fault 6 enabled */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
+  * @{
+  * @brief Constants defining whether or not fault enabling bits are write
+  *        protected for a timer
+  */
+#define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U)           /*!< Timer fault enabling bits are read/write */
+#define HRTIM_TIMFAULTLOCK_READONLY  (HRTIM_FLTR_FLTLCK)     /*!< Timer fault enabling bits are read only */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Dead-time Insertion
+  * @{
+  * @brief Constants defining whether or not fault the dead time insertion
+  *        feature is enabled for a timer
+  */
+#define HRTIM_TIMDEADTIMEINSERTION_DISABLED   (0x00000000U)           /*!< Output 1 and output 2 signals are independent */
+#define HRTIM_TIMDEADTIMEINSERTION_ENABLED    HRTIM_OUTR_DTEN         /*!< Dead-time is inserted between output 1 and output 2U */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
+  * @{
+  * @brief Constants defining all possible delayed protection modes
+  *        for a timer. Also define the source and outputs on which the delayed
+  *        protection schemes are applied
+  */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED          (0x00000000U)                                                                           /*!< No action */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6  (HRTIM_OUTR_DLYPRTEN)                                                                   /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6  (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6  (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6     (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Balanced Idle on external Event 6U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */
+
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED            (0x00000000U)                                                                             /*!< No action */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8    (HRTIM_OUTR_DLYPRTEN)                                                                     /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8    (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8    (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8       (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Balanced Idle on external Event 6U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9    (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9       (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)   /*!< Timers D, E: Balanced Idle on external Event 7U */
+
+#define HRTIM_TIMER_F_DELAYEDPROTECTION_DISABLED              (0x00000000U)                                                                             /*!< No action */
+#define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_EEV8      (HRTIM_OUTR_DLYPRTEN)                                                                     /*!< Timers F: Output 1 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_EEV8      (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers F: Output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV8      (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers F: Output 1 and output 2 delayed Idle on external Event 6U */
+#define HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV8         (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers F: Balanced Idle on external Event 6U */
+#define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers F: Output 1 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers F: Output 2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_F_DELAYEDPROTECTION_DELAYEDBOTH_EEV9      (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers F: Output 1 and output2 delayed Idle on external Event 7U */
+#define HRTIM_TIMER_F_DELAYEDPROTECTION_BALANCED_EEV9         (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)   /*!< Timers F: Balanced Idle on external Event 7U */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
+  * @{
+  * @brief Constants defining whether the registers update is done synchronously
+  *        with any other timer or master update
+  */
+#define HRTIM_TIMUPDATETRIGGER_NONE     0x00000000U          /*!< Register update is disabled */
+#define HRTIM_TIMUPDATETRIGGER_MASTER   (HRTIM_TIMCR_MSTU)   /*!< Register update is triggered by the master timer update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_A  (HRTIM_TIMCR_TAU)    /*!< Register update is triggered by the timer A update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_B  (HRTIM_TIMCR_TBU)    /*!< Register update is triggered by the timer B update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_C  (HRTIM_TIMCR_TCU)    /*!< Register update is triggered by the timer C update*/
+#define HRTIM_TIMUPDATETRIGGER_TIMER_D  (HRTIM_TIMCR_TDU)    /*!< Register update is triggered by the timer D update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_E  (HRTIM_TIMCR_TEU)    /*!< Register update is triggered by the timer E update */
+#define HRTIM_TIMUPDATETRIGGER_TIMER_F  (HRTIM_TIMCR_TFU)    /*!< Register update is triggered by the timer F update */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
+  * @{
+  * @brief Constants defining the events that can be selected to trigger the reset
+  *        of the timer counter
+  */
+#define HRTIM_TIMRESETTRIGGER_NONE        0x00000000U            /*!< No counter reset trigger */
+#define HRTIM_TIMRESETTRIGGER_UPDATE      (HRTIM_RSTR_UPDATE)    /*!< The timer counter is reset upon update event */
+#define HRTIM_TIMRESETTRIGGER_CMP2        (HRTIM_RSTR_CMP2)      /*!< The timer counter is reset upon Timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_CMP4        (HRTIM_RSTR_CMP4)      /*!< The timer counter is reset upon Timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_PER  (HRTIM_RSTR_MSTPER)    /*!< The timer counter is reset upon master timer period event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1)   /*!< The timer counter is reset upon master timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2)   /*!< The timer counter is reset upon master timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3)   /*!< The timer counter is reset upon master timer Compare 3 event */
+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4)   /*!< The timer counter is reset upon master timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_EEV_1       (HRTIM_RSTR_EXTEVNT1)  /*!< The timer counter is reset upon external event 1U */
+#define HRTIM_TIMRESETTRIGGER_EEV_2       (HRTIM_RSTR_EXTEVNT2)  /*!< The timer counter is reset upon external event 2U */
+#define HRTIM_TIMRESETTRIGGER_EEV_3       (HRTIM_RSTR_EXTEVNT3)  /*!< The timer counter is reset upon external event 3U */
+#define HRTIM_TIMRESETTRIGGER_EEV_4       (HRTIM_RSTR_EXTEVNT4)  /*!< The timer counter is reset upon external event 4U */
+#define HRTIM_TIMRESETTRIGGER_EEV_5       (HRTIM_RSTR_EXTEVNT5)  /*!< The timer counter is reset upon external event 5U */
+#define HRTIM_TIMRESETTRIGGER_EEV_6       (HRTIM_RSTR_EXTEVNT6)  /*!< The timer counter is reset upon external event 6U */
+#define HRTIM_TIMRESETTRIGGER_EEV_7       (HRTIM_RSTR_EXTEVNT7)  /*!< The timer counter is reset upon external event 7U */
+#define HRTIM_TIMRESETTRIGGER_EEV_8       (HRTIM_RSTR_EXTEVNT8)  /*!< The timer counter is reset upon external event 8U */
+#define HRTIM_TIMRESETTRIGGER_EEV_9       (HRTIM_RSTR_EXTEVNT9)  /*!< The timer counter is reset upon external event 9U */
+#define HRTIM_TIMRESETTRIGGER_EEV_10      (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */
+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER5_CMP1 (HRTIM_RSTR_TIMFCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */
+#define HRTIM_TIMRESETTRIGGER_OTHER5_CMP2 (HRTIM_RSTR_TIMFCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
+  * @{
+  * @brief Constants defining whether the register are updated upon Timerx
+  *        counter reset or roll-over to 0 after reaching the period value
+  *        in continuous mode
+  */
+#define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U           /*!< Update by timer x reset / roll-over disabled */
+#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU)    /*!< Update by timer x reset / roll-over enabled */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_RollOver_Mode HRTIM Timer RollOver Mode
+  * @{
+  * @brief Constants defining when the roll-over is generated upon Timerx
+  *        event generated when the counter is equal to 0 ('VALLEY' mode) or to HRTIM_PERxR value ('CREST' mode) or BOTH
+  *        This setting only applies when the UDM bit is set. It is not significant otherwise.
+  */
+#define HRTIM_TIM_FEROM_BOTH      0x00000000U              /*!< Roll-over event used by  */
+#define HRTIM_TIM_FEROM_CREST     (HRTIM_TIMCR2_FEROM_1)   /*!< the Fault and */
+#define HRTIM_TIM_FEROM_VALLEY    (HRTIM_TIMCR2_FEROM_0)   /*!< Event counters */
+#define HRTIM_TIM_BMROM_BOTH      0x00000000U              /*!< Roll-over event used in the Burst mode controller */
+#define HRTIM_TIM_BMROM_CREST     (HRTIM_TIMCR2_BMROM_1)   /*!< as clock  */
+#define HRTIM_TIM_BMROM_VALLEY    (HRTIM_TIMCR2_BMROM_0)   /*!< and as burst mode trigger */
+#define HRTIM_TIM_ADROM_BOTH      0x00000000U              /*!< Roll-over event which triggers */
+#define HRTIM_TIM_ADROM_CREST     (HRTIM_TIMCR2_ADROM_1)   /*!< the */
+#define HRTIM_TIM_ADROM_VALLEY    (HRTIM_TIMCR2_ADROM_0)   /*!< ADC */
+#define HRTIM_TIM_OUTROM_BOTH     0x00000000U              /*!< Roll-over event which sets and/or resets the outputs */
+#define HRTIM_TIM_OUTROM_CREST    (HRTIM_TIMCR2_OUTROM_1)  /*!< as per HRTIM_SETxyR */
+#define HRTIM_TIM_OUTROM_VALLEY   (HRTIM_TIMCR2_OUTROM_0)  /*!< and HRTIM_RSTxyR settings */
+#define HRTIM_TIM_ROM_BOTH        0x00000000U              /*!< Roll-over event with the following destinations: IRQ and DMA requests,*/
+#define HRTIM_TIM_ROM_CREST       (HRTIM_TIMCR2_ROM_1)     /*!< Update trigger (to transfer content from preload to active registers), */
+#define HRTIM_TIM_ROM_VALLEY      (HRTIM_TIMCR2_ROM_0)     /*!< repetition counter decrement and External Event filtering */
+
+#define IS_HRTIM_ROLLOVERMODE(ROLLOVER)\
+  ((((ROLLOVER) == HRTIM_TIM_FEROM_BOTH)  || ((ROLLOVER) == HRTIM_TIM_FEROM_CREST)  || ((ROLLOVER) == HRTIM_TIM_FEROM_VALLEY))  ||\
+   (((ROLLOVER) == HRTIM_TIM_ADROM_BOTH)  || ((ROLLOVER) == HRTIM_TIM_ADROM_CREST)  || ((ROLLOVER) == HRTIM_TIM_ADROM_VALLEY))  ||\
+   (((ROLLOVER) == HRTIM_TIM_BMROM_BOTH)  || ((ROLLOVER) == HRTIM_TIM_BMROM_CREST)  || ((ROLLOVER) == HRTIM_TIM_BMROM_VALLEY))  ||\
+   (((ROLLOVER) == HRTIM_TIM_OUTROM_BOTH) || ((ROLLOVER) == HRTIM_TIM_OUTROM_CREST) || ((ROLLOVER) == HRTIM_TIM_OUTROM_VALLEY)) ||\
+   (((ROLLOVER) == HRTIM_TIM_ROM_BOTH)    || ((ROLLOVER) == HRTIM_TIM_ROM_CREST)    || ((ROLLOVER) == HRTIM_TIM_ROM_VALLEY)))
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
+  * @{
+  * @brief Constants defining whether the compare register is behaving in
+  *        regular mode (compare match issued as soon as counter equal compare),
+  *        or in auto-delayed mode
+  */
+#define HRTIM_AUTODELAYEDMODE_REGULAR                 (0x00000000U)                                   /*!< standard compare mode */
+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT   (HRTIM_TIMCR_DELCMP2_0)                         /*!< Compare event generated only if a capture has occurred */
+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1)                         /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
+  * @{
+  * @brief Constants defining the behavior of the output signal when the timer
+           operates in basic output compare mode
+  */
+#define HRTIM_BASICOCMODE_TOGGLE    (0x00000001U)  /*!< Output toggles when the timer counter reaches the compare value */
+#define HRTIM_BASICOCMODE_INACTIVE  (0x00000002U)  /*!< Output forced to active level when the timer counter reaches the compare value */
+#define HRTIM_BASICOCMODE_ACTIVE    (0x00000003U)  /*!< Output forced to inactive level when the timer counter reaches the compare value */
+
+#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
+  (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE)   || \
+   ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
+   ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
+  * @{
+  * @brief Constants defining the polarity of a timer output
+  */
+#define HRTIM_OUTPUTPOLARITY_HIGH    (0x00000000U)           /*!< Output is active HIGH */
+#define HRTIM_OUTPUTPOLARITY_LOW     (HRTIM_OUTR_POL1)       /*!< Output is active LOW */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
+  * @{
+  * @brief Constants defining the events that can be selected to configure the
+  *        set crossbar of a timer output
+  */
+#define HRTIM_OUTPUTSET_NONE       0x00000000U                      /*!< Reset the output set crossbar */
+#define HRTIM_OUTPUTSET_RESYNC     (HRTIM_SET1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMPER     (HRTIM_SET1R_PER)                /*!< Timer period event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP1    (HRTIM_SET1R_CMP1)               /*!< Timer compare 1 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP2    (HRTIM_SET1R_CMP2)               /*!< Timer compare 2 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP3    (HRTIM_SET1R_CMP3)               /*!< Timer compare 3 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCMP4    (HRTIM_SET1R_CMP4)               /*!< Timer compare 4 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERPER  (HRTIM_SET1R_MSTPER)             /*!< The master timer period event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)            /*!< Master Timer compare 1 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its active state */
+#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its active state */
+/* Timer Events mapping for Timer A */
+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
+/* Timer Events mapping for Timer B */
+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
+/* Timer Events mapping for Timer C */
+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
+/* Timer Events mapping for Timer D */
+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
+/* Timer Events mapping for Timer E */
+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
+/* Timer Events mapping for Timer F */
+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_1      (HRTIM_SET1R_EXTVNT1)            /*!< External event 1 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_2      (HRTIM_SET1R_EXTVNT2)            /*!< External event 2 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_3      (HRTIM_SET1R_EXTVNT3)            /*!< External event 3 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_4      (HRTIM_SET1R_EXTVNT4)            /*!< External event 4 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_5      (HRTIM_SET1R_EXTVNT5)            /*!< External event 5 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_6      (HRTIM_SET1R_EXTVNT6)            /*!< External event 6 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_7      (HRTIM_SET1R_EXTVNT7)            /*!< External event 7 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_8      (HRTIM_SET1R_EXTVNT8)            /*!< External event 8 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_9      (HRTIM_SET1R_EXTVNT9)            /*!< External event 9 forces the output to its active state */
+#define HRTIM_OUTPUTSET_EEV_10     (HRTIM_SET1R_EXTVNT10)           /*!< External event 10 forces the output to its active state */
+#define HRTIM_OUTPUTSET_UPDATE     (HRTIM_SET1R_UPDATE)             /*!< Timer register update event forces the output to its active state */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
+  * @{
+  * @brief Constants defining the events that can be selected to configure the
+  *        reset crossbar of a timer output
+  */
+#define HRTIM_OUTPUTRESET_NONE       0x00000000U                      /*!< Reset the output reset crossbar */
+#define HRTIM_OUTPUTRESET_RESYNC     (HRTIM_RST1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMPER     (HRTIM_RST1R_PER)                /*!< Timer period event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP1    (HRTIM_RST1R_CMP1)               /*!< Timer compare 1 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP2    (HRTIM_RST1R_CMP2)               /*!< Timer compare 2 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP3    (HRTIM_RST1R_CMP3)               /*!< Timer compare 3 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCMP4    (HRTIM_RST1R_CMP4)               /*!< Timer compare 4 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERPER  (HRTIM_RST1R_MSTPER)             /*!< The master timer period event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)            /*!< Master Timer compare 1 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its inactive state */
+/* Timer Events mapping for Timer A */
+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
+/* Timer Events mapping for Timer B */
+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
+/* Timer Events mapping for Timer C */
+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
+/* Timer Events mapping for Timer D */
+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
+/* Timer Events mapping for Timer E */
+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
+/* Timer Events mapping for Timer F */
+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_1      (HRTIM_RST1R_EXTVNT1)            /*!< External event 1 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_2      (HRTIM_RST1R_EXTVNT2)            /*!< External event 2 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_3      (HRTIM_RST1R_EXTVNT3)            /*!< External event 3 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_4      (HRTIM_RST1R_EXTVNT4)            /*!< External event 4 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_5      (HRTIM_RST1R_EXTVNT5)            /*!< External event 5 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_6      (HRTIM_RST1R_EXTVNT6)            /*!< External event 6 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_7      (HRTIM_RST1R_EXTVNT7)            /*!< External event 7 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_8      (HRTIM_RST1R_EXTVNT8)            /*!< External event 8 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_9      (HRTIM_RST1R_EXTVNT9)            /*!< External event 9 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_EEV_10     (HRTIM_RST1R_EXTVNT10)           /*!< External event 10 forces the output to its inactive state */
+#define HRTIM_OUTPUTRESET_UPDATE     (HRTIM_RST1R_UPDATE)             /*!< Timer register update event forces the output to its inactive state */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
+  * @{
+  * @brief Constants defining whether or not the timer output transition to its
+           IDLE state when burst mode is entered
+  */
+#define HRTIM_OUTPUTIDLEMODE_NONE     0x00000000U           /*!< The output is not affected by the burst mode operation */
+#define HRTIM_OUTPUTIDLEMODE_IDLE     (HRTIM_OUTR_IDLM1)    /*!< The output is in idle state when requested by the burst mode controller */
+/**
+  * @}
+ */
+
+/** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
+  * @{
+  * @brief Constants defining the output level when output is in IDLE state
+  */
+#define HRTIM_OUTPUTIDLELEVEL_INACTIVE   0x00000000U           /*!< Output at inactive level when in IDLE state */
+#define HRTIM_OUTPUTIDLELEVEL_ACTIVE     (HRTIM_OUTR_IDLES1)   /*!< Output at active level when in IDLE state */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
+  * @{
+  * @brief Constants defining the output level when output is in FAULT state
+  */
+#define HRTIM_OUTPUTFAULTLEVEL_NONE      0x00000000U                                  /*!< The output is not affected by the fault input */
+#define HRTIM_OUTPUTFAULTLEVEL_ACTIVE    (HRTIM_OUTR_FAULT1_0)                        /*!< Output at active level when in FAULT state */
+#define HRTIM_OUTPUTFAULTLEVEL_INACTIVE  (HRTIM_OUTR_FAULT1_1)                        /*!< Output at inactive level when in FAULT state */
+#define HRTIM_OUTPUTFAULTLEVEL_HIGHZ     (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)  /*!< Output is tri-stated when in FAULT state */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
+  * @{
+  * @brief Constants defining whether or not chopper mode is enabled for a timer
+           output
+  */
+#define HRTIM_OUTPUTCHOPPERMODE_DISABLED   0x00000000U           /*!< Output signal is not altered  */
+#define HRTIM_OUTPUTCHOPPERMODE_ENABLED    (HRTIM_OUTR_CHP1)     /*!< Output signal is chopped by a carrier signal  */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
+  * @{
+  * @brief Constants defining the idle mode entry is delayed by forcing a
+           dead-time insertion before switching the outputs to their idle state
+  */
+#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR   0x00000000U           /*!< The programmed Idle state is applied immediately to the Output */
+#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED   (HRTIM_OUTR_DIDL1)    /*!< Dead-time is inserted on output before entering the idle mode */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Output_Balanced_Idle_Auto_Resume HRTIM Output Balanced Idle Automatic Resume
+  * @{
+  * @brief Constants defining if the outputs are automatically
+           re-enabled after a balanced idle event.
+  */
+#define HRTIM_OUTPUTBIAR_DISABLED   0x00000000U            /*!< output is not automatically re-enabled */
+#define HRTIM_OUTPUTBIAR_ENABLED    (HRTIM_OUTR_BIAR)      /*!< output is automatically re-enabled */
+/**
+  * @}
+  */
+
+
+/** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
+  * @{
+  * @brief Constants defining the events that can be selected to trigger the
+  *        capture of the timing unit counter
+  */
+#define HRTIM_CAPTURETRIGGER_NONE         0x00000000U              /*!< Capture trigger is disabled */
+#define HRTIM_CAPTURETRIGGER_UPDATE       (HRTIM_CPT1CR_UPDCPT)    /*!< The update event triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_1        (HRTIM_CPT1CR_EXEV1CPT)  /*!< The External event 1 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_2        (HRTIM_CPT1CR_EXEV2CPT)  /*!< The External event 2 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_3        (HRTIM_CPT1CR_EXEV3CPT)  /*!< The External event 3 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_4        (HRTIM_CPT1CR_EXEV4CPT)  /*!< The External event 4 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_5        (HRTIM_CPT1CR_EXEV5CPT)  /*!< The External event 5 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_6        (HRTIM_CPT1CR_EXEV6CPT)  /*!< The External event 6 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_7        (HRTIM_CPT1CR_EXEV7CPT)  /*!< The External event 7 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_8        (HRTIM_CPT1CR_EXEV8CPT)  /*!< The External event 8 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_9        (HRTIM_CPT1CR_EXEV9CPT)  /*!< The External event 9 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_EEV_10       (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
+#define HRTIM_CAPTURETRIGGER_TA1_SET      (HRTIM_CPT1CR_TA1SET)    /*!< Capture is triggered by TA1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TA1_RESET    (HRTIM_CPT1CR_TA1RST)    /*!< Capture is triggered by TA1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1  (HRTIM_CPT1CR_TIMACMP1)  /*!< Timer A Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2  (HRTIM_CPT1CR_TIMACMP2)  /*!< Timer A Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TB1_SET      (HRTIM_CPT1CR_TB1SET)    /*!< Capture is triggered by TB1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TB1_RESET    (HRTIM_CPT1CR_TB1RST)    /*!< Capture is triggered by TB1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1  (HRTIM_CPT1CR_TIMBCMP1)  /*!< Timer B Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2  (HRTIM_CPT1CR_TIMBCMP2)  /*!< Timer B Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TC1_SET      (HRTIM_CPT1CR_TC1SET)    /*!< Capture is triggered by TC1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TC1_RESET    (HRTIM_CPT1CR_TC1RST)    /*!< Capture is triggered by TC1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1  (HRTIM_CPT1CR_TIMCCMP1)  /*!< Timer C Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2  (HRTIM_CPT1CR_TIMCCMP2)  /*!< Timer C Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TD1_SET      (HRTIM_CPT1CR_TD1SET)    /*!< Capture is triggered by TD1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TD1_RESET    (HRTIM_CPT1CR_TD1RST)    /*!< Capture is triggered by TD1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1  (HRTIM_CPT1CR_TIMDCMP1)  /*!< Timer D Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2  (HRTIM_CPT1CR_TIMDCMP2)  /*!< Timer D Compare 2 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TE1_SET      (HRTIM_CPT1CR_TE1SET)    /*!< Capture is triggered by TE1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TE1_RESET    (HRTIM_CPT1CR_TE1RST)    /*!< Capture is triggered by TE1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1  (HRTIM_CPT1CR_TIMECMP1)  /*!< Timer E Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2  (HRTIM_CPT1CR_TIMECMP2)  /*!< Timer E Compare 2 triggers Capture */
+/**
+  * @}
+  */
+/** @defgroup HRTIM_Capture_Unit_TimerF_Trigger HRTIM Capture Unit TimerF Trigger
+  * @{
+  * @brief Constants defining the events that can be selected to trigger the
+  *        capture of the timing unit counter
+  */
+#define HRTIM_CAPTURETRIGGER_TF1_SET       ((uint64_t)(HRTIM_CPT1CR_TF1SET  ) << 32)  /*!< Capture is triggered by TF1 output inactive to active transition */
+#define HRTIM_CAPTURETRIGGER_TF1_RESET     ((uint64_t)(HRTIM_CPT1CR_TF1RST  ) << 32)  /*!< Capture is triggered by TF1 output active to inactive transition */
+#define HRTIM_CAPTURETRIGGER_TIMERF_CMP1   ((uint64_t)(HRTIM_CPT1CR_TIMFCMP1) << 32)  /*!< Timer F Compare 1 triggers Capture */
+#define HRTIM_CAPTURETRIGGER_TIMERF_CMP2   ((uint64_t)(HRTIM_CPT1CR_TIMFCMP2) << 32)  /*!< Timer F Compare 2 triggers Capture */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
+  * @{
+  * @brief Constants defining the event filtering applied to external events
+  *        by a timer
+  */
+#define HRTIM_TIMEEVFLT_NONE                            (0x00000000U)
+#define HRTIM_TIMEEVFLT_BLANKINGCMP1                    (HRTIM_EEFR1_EE1FLTR_0)                                                   /*!< Blanking from counter reset/roll-over to Compare 1U */
+#define HRTIM_TIMEEVFLT_BLANKINGCMP2                    (HRTIM_EEFR1_EE1FLTR_1)                                                   /*!< Blanking from counter reset/roll-over to Compare 2U */
+#define HRTIM_TIMEEVFLT_BLANKINGCMP3                    (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from counter reset/roll-over to Compare 3U */
+#define HRTIM_TIMEEVFLT_BLANKINGCMP4                    (HRTIM_EEFR1_EE1FLTR_2)                                                   /*!< Blanking from counter reset/roll-over to Compare 4U */
+/* Blanking Filter for TIMER A */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
+/* Blanking Filter for TIMER B */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
+/* Blanking Filter for TIMER C */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
+/* Blanking Filter for TIMER D */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
+/* Blanking Filter for TIMER E */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
+/* Blanking Filter for TIMER F */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
+
+#define HRTIM_TIMEEVFLT_WINDOWINGCMP2                   (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Windowing from counter reset/roll-over to Compare 2U */
+#define HRTIM_TIMEEVFLT_WINDOWINGCMP3                   (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)   /*!< Windowing from counter reset/roll-over to Compare 3U */
+#define HRTIM_TIMEEVFLT_WINDOWINGTIM                    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
+                                                         | HRTIM_EEFR1_EE1FLTR_0)   /*!< Windowing from another timing unit: TIMWIN source */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
+  * @{
+  * @brief Constants defining whether or not the external event is
+  *        memorized (latched) and generated as soon as the blanking period
+  *        is completed or the window ends
+  */
+#define HRTIM_TIMEVENTLATCH_DISABLED    (0x00000000U)           /*!< Event is ignored if it happens during a blank, or passed through during a window */
+#define HRTIM_TIMEVENTLATCH_ENABLED     HRTIM_EEFR1_EE1LTCH     /*!< Event is latched and delayed till the end of the blanking or windowing period */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_External_Event HRTIM Timer External Event Counter A or B
+  * @{
+  * @brief Constants defining the External Event Counter A or B
+  */
+#define HRTIM_EVENTCOUNTER_A    (HRTIM_EEFR3_EEVACE)           /*!< External Event Counter A */
+#define HRTIM_EVENTCOUNTER_B    (HRTIM_EEFR3_EEVBCE)           /*!< External Event Counter B */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_External_Event_ResetMode HRTIM Timer External Counter Reset Mode
+  * @{
+  * @brief Constants enabling the External Event Counter A or B Reset Mode
+  */
+#define HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL   (0x00000000U)   /*!< External Event Counter is reset on each reset / roll-over event */
+#define HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL     (0x00000001U)   /*!< External Event Counter is reset on each reset / roll-over event only
+                                                                        if no event occurs during last counting period */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_ReSyncUpdate HRTIM Timer Re-Synchronized update
+  * @{
+  * @brief Constants defining the update coming condition
+  */
+#define HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL   (0x00000000U)   /*!< update taken into account immediately */
+#define HRTIM_TIMERESYNC_UPDATE_CONDITIONAL     (0x00000001U)   /*!< update taken into account on the following Reset/Roll-over event */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio
+  * @{
+  * @brief Constants defining division ratio between the timer clock frequency
+  *        (fHRTIM) and the dead-time generator clock (fDTG)
+  */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8    (0x00000000U)                                                   /*!< fDTG = fHRTIM * 8U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4    (HRTIM_DTR_DTPRSC_0)                                            /*!< fDTG = fHRTIM * 4U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2    (HRTIM_DTR_DTPRSC_1)                                            /*!< fDTG = fHRTIM * 2U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)                       /*!< fDTG = fHRTIM / 8U */
+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16   (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)  /*!< fDTG = fHRTIM / 16U */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Dead-time Rising Sign
+  * @{
+  * @brief Constants defining whether the dead-time is positive or negative
+  *        (overlapping signal) on rising edge
+  */
+#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE    (0x00000000U)           /*!< Positive dead-time on rising edge */
+#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE    (HRTIM_DTR_SDTR)        /*!< Negative dead-time on rising edge */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Dead-time Rising Lock
+  * @{
+  * @brief Constants defining whether or not the dead-time (rising sign and
+  *        value) is write protected
+  */
+#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE    (0x00000000U)           /*!< Dead-time rising value and sign is writeable */
+#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK)       /*!< Dead-time rising value and sign is read-only */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Dead-time Rising Sign Lock
+  * @{
+  * @brief Constants defining whether or not the dead-time rising sign is write
+  *        protected
+  */
+#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE    (0x00000000U)           /*!< Dead-time rising sign is writeable */
+#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK)      /*!< Dead-time rising sign is read-only */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Dead-time Falling Sign
+  * @{
+  * @brief Constants defining whether the dead-time is positive or negative
+  *        (overlapping signal) on falling edge
+  */
+#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE    (0x00000000U)           /*!< Positive dead-time on falling edge */
+#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE    (HRTIM_DTR_SDTF)        /*!< Negative dead-time on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Dead-time Falling Lock
+  * @{
+  * @brief Constants defining whether or not the dead-time (falling sign and
+  *        value) is write protected
+  */
+#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE    (0x00000000U)           /*!< Dead-time falling value and sign is writeable */
+#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK)       /*!< Dead-time falling value and sign is read-only */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Dead-time Falling Sign Lock
+  * @{
+  * @brief Constants defining whether or not the dead-time falling sign is write
+  *        protected
+  */
+#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE    (0x00000000U)           /*!< Dead-time falling sign is writeable */
+#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK)      /*!< Dead-time falling sign is read-only */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
+  * @{
+  * @brief Constants defining the frequency of the generated high frequency carrier
+  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV16  (0x000000U)                                                                     /*!< fCHPFRQ = fHRTIM / 16  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV32  (HRTIM_CHPR_CARFRQ_0)                                                                    /*!< fCHPFRQ = fHRTIM / 32  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV48  (HRTIM_CHPR_CARFRQ_1)                                                                    /*!< fCHPFRQ = fHRTIM / 48  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV64  (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 64  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV80  (HRTIM_CHPR_CARFRQ_2)                                                                    /*!< fCHPFRQ = fHRTIM / 80  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV96  (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 96  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 112  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 128  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3)                                                                    /*!< fCHPFRQ = fHRTIM / 144  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 160  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 176  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 192  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)                                              /*!< fCHPFRQ = fHRTIM / 208  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 224  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                        /*!< fCHPFRQ = fHRTIM / 240  */
+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)  /*!< fCHPFRQ = fHRTIM / 256  */
+/**
+  * @}
+ */
+
+/** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
+  * @{
+  * @brief Constants defining the duty cycle of the generated high frequency carrier
+  *        Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
+  */
+#define HRTIM_CHOPPER_DUTYCYCLE_0    (0x000000U)                                                       /*!< Only 1st pulse is present */
+#define HRTIM_CHOPPER_DUTYCYCLE_125  (HRTIM_CHPR_CARDTY_0)                                             /*!< Duty cycle of the carrier signal is 12.5U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_250  (HRTIM_CHPR_CARDTY_1)                                             /*!< Duty cycle of the carrier signal is 25U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_375  (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 37.5U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_500  (HRTIM_CHPR_CARDTY_2)                                             /*!< Duty cycle of the carrier signal is 50U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_625  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 62.5U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_750  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)                       /*!< Duty cycle of the carrier signal is 75U % */
+#define HRTIM_CHOPPER_DUTYCYCLE_875  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
+  * @{
+  * @brief Constants defining the pulse width of the first pulse of the generated
+  *        high frequency carrier
+  */
+#define HRTIM_CHOPPER_PULSEWIDTH_16   (0x000000U)                                                                          /*!< tSTPW = tHRTIM x 16  */
+#define HRTIM_CHOPPER_PULSEWIDTH_32   (HRTIM_CHPR_STRPW_0)                                                                 /*!< tSTPW = tHRTIM x 32  */
+#define HRTIM_CHOPPER_PULSEWIDTH_48   (HRTIM_CHPR_STRPW_1)                                                                 /*!< tSTPW = tHRTIM x 48  */
+#define HRTIM_CHOPPER_PULSEWIDTH_64   (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 64  */
+#define HRTIM_CHOPPER_PULSEWIDTH_80   (HRTIM_CHPR_STRPW_2)                                                                 /*!< tSTPW = tHRTIM x 80  */
+#define HRTIM_CHOPPER_PULSEWIDTH_96   (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 96  */
+#define HRTIM_CHOPPER_PULSEWIDTH_112  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 112  */
+#define HRTIM_CHOPPER_PULSEWIDTH_128  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 128  */
+#define HRTIM_CHOPPER_PULSEWIDTH_144  (HRTIM_CHPR_STRPW_3)                                                                 /*!< tSTPW = tHRTIM x 144  */
+#define HRTIM_CHOPPER_PULSEWIDTH_160  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 160  */
+#define HRTIM_CHOPPER_PULSEWIDTH_176  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 176  */
+#define HRTIM_CHOPPER_PULSEWIDTH_192  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 192  */
+#define HRTIM_CHOPPER_PULSEWIDTH_208  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)                                            /*!< tSTPW = tHRTIM x 208  */
+#define HRTIM_CHOPPER_PULSEWIDTH_224  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 224  */
+#define HRTIM_CHOPPER_PULSEWIDTH_240  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                       /*!< tSTPW = tHRTIM x 240  */
+#define HRTIM_CHOPPER_PULSEWIDTH_256  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)  /*!< tSTPW = tHRTIM x 256  */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
+  * @{
+  * @brief Constants defining the options for synchronizing multiple HRTIM
+  *        instances, as a master unit (generating a synchronization signal)
+  *        or as a slave (waiting for a trigger to be synchronized)
+  */
+#define HRTIM_SYNCOPTION_NONE   0x00000000U   /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
+#define HRTIM_SYNCOPTION_MASTER 0x00000001U   /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
+#define HRTIM_SYNCOPTION_SLAVE  0x00000002U   /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
+  * @{
+  * @brief Constants defining defining the synchronization input source
+  */
+#define HRTIM_SYNCINPUTSOURCE_NONE           0x00000000U                                  /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
+#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT  HRTIM_MCR_SYNC_IN_1                          /*!< The HRTIM is synchronized with the on-chip timer */
+#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT  (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)  /*!< A positive pulse on SYNCIN input triggers the HRTIM */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
+  * @{
+  * @brief Constants defining the source and event to be sent on the
+  *        synchronization outputs
+  */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U                                    /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event      */
+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1  (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event  */
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START   (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1    (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event       */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
+  * @{
+  * @brief Constants defining the routing and conditioning of the synchronization output event
+  */
+#define HRTIM_SYNCOUTPUTPOLARITY_NONE      0x00000000U                                   /*!< Synchronization output event is disabled */
+#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE  (HRTIM_MCR_SYNC_OUT_1)                        /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
+#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE  (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
+  * @{
+  * @brief Constants defining available sources associated to external events
+  */
+#define HRTIM_EEV1SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 1 */
+#define HRTIM_EEV2SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 2 */
+#define HRTIM_EEV3SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 3 */
+#define HRTIM_EEV4SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 4 */
+#define HRTIM_EEV5SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 5 */
+#define HRTIM_EEV6SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 6 */
+#define HRTIM_EEV7SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 7 */
+#define HRTIM_EEV8SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 8 */
+#define HRTIM_EEV9SRC_GPIO        0x00000000U                                   /*!< External event source 1U for External Event 9 */
+#define HRTIM_EEV10SRC_GPIO       0x00000000U                                   /*!< External event source 1U for External Event 10 */
+#define HRTIM_EEV1SRC_COMP2_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 1 */
+#define HRTIM_EEV2SRC_COMP4_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 2 */
+#define HRTIM_EEV3SRC_COMP6_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 3 */
+#define HRTIM_EEV4SRC_COMP1_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 4 */
+#define HRTIM_EEV5SRC_COMP3_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 5 */
+#define HRTIM_EEV6SRC_COMP2_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 6 */
+#define HRTIM_EEV7SRC_COMP4_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 7 */
+#define HRTIM_EEV8SRC_COMP6_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 8 */
+#define HRTIM_EEV9SRC_COMP5_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 9 */
+#define HRTIM_EEV10SRC_COMP7_OUT  (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2U for External Event 10 */
+#define HRTIM_EEV1SRC_TIM1_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 1 */
+#define HRTIM_EEV2SRC_TIM2_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 2 */
+#define HRTIM_EEV3SRC_TIM3_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 3 */
+#define HRTIM_EEV4SRC_COMP5_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 4 */
+#define HRTIM_EEV5SRC_COMP7_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 5 */
+#define HRTIM_EEV6SRC_COMP1_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 6 */
+#define HRTIM_EEV7SRC_TIM7_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 7 */
+#define HRTIM_EEV8SRC_COMP3_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 8 */
+#define HRTIM_EEV9SRC_TIM15_TRGO  (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 9 */
+#define HRTIM_EEV10SRC_TIM6_TRGO  (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3U for External Event 10 */
+#define HRTIM_EEV1SRC_ADC1_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 1 */
+#define HRTIM_EEV2SRC_ADC1_AWD2   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 2 */
+#define HRTIM_EEV3SRC_ADC1_AWD3   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 3 */
+#define HRTIM_EEV4SRC_ADC2_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 4 */
+#define HRTIM_EEV5SRC_ADC2_AWD2   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 5 */
+#define HRTIM_EEV6SRC_ADC2_AWD3   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 6 */
+#define HRTIM_EEV7SRC_ADC3_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 7 */
+#define HRTIM_EEV8SRC_ADC4_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 8 */
+#define HRTIM_EEV9SRC_COMP4_OUT   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 9 */
+#define HRTIM_EEV10SRC_ADC5_AWD1  (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U for External Event 10 */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
+  * @{
+  * @brief Constants defining the polarity of an external event
+  */
+#define HRTIM_EVENTPOLARITY_HIGH    (0x00000000U)           /*!< External event is active high */
+#define HRTIM_EVENTPOLARITY_LOW     (HRTIM_EECR1_EE1POL)    /*!< External event is active low */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
+  * @{
+  * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
+  *        of an external event
+  */
+#define HRTIM_EVENTSENSITIVITY_LEVEL          (0x00000000U)                                  /*!< External event is active on level */
+#define HRTIM_EVENTSENSITIVITY_RISINGEDGE     (HRTIM_EECR1_EE1SNS_0)                         /*!< External event is active on Rising edge */
+#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE    (HRTIM_EECR1_EE1SNS_1)                         /*!< External event is active on Falling edge */
+#define HRTIM_EVENTSENSITIVITY_BOTHEDGES      (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)  /*!< External event is active on Rising and Falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
+  * @{
+  * @brief Constants defining whether or not an external event is programmed in
+           fast mode
+  */
+#define HRTIM_EVENTFASTMODE_DISABLE    (0x00000000U)               /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
+#define HRTIM_EVENTFASTMODE_ENABLE     (HRTIM_EECR1_EE1FAST)       /*!< External Event is acting asynchronously on outputs (low latency mode) */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
+  * @{
+  * @brief Constants defining the frequency used to sample an external event 6
+  *        input and the length (N) of the digital filter applied
+  */
+#define HRTIM_EVENTFILTER_NONE      (0x00000000U)                                                                         /*!< Filter disabled */
+#define HRTIM_EVENTFILTER_1         (HRTIM_EECR3_EE6F_0)                                                                  /*!< fSAMPLING= fHRTIM, N=2U */
+#define HRTIM_EVENTFILTER_2         (HRTIM_EECR3_EE6F_1)                                                                  /*!< fSAMPLING= fHRTIM, N=4U */
+#define HRTIM_EVENTFILTER_3         (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fHRTIM, N=8U */
+#define HRTIM_EVENTFILTER_4         (HRTIM_EECR3_EE6F_2)                                                                  /*!< fSAMPLING= fEEVS/2U, N=6U */
+#define HRTIM_EVENTFILTER_5         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/2U, N=8U */
+#define HRTIM_EVENTFILTER_6         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/4U, N=6U */
+#define HRTIM_EVENTFILTER_7         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/4U, N=8U */
+#define HRTIM_EVENTFILTER_8         (HRTIM_EECR3_EE6F_3)                                                                  /*!< fSAMPLING= fEEVS/8U, N=6U */
+#define HRTIM_EVENTFILTER_9         (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/8U, N=8U */
+#define HRTIM_EVENTFILTER_10        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/16U, N=5U */
+#define HRTIM_EVENTFILTER_11        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/16U, N=6U */
+#define HRTIM_EVENTFILTER_12        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)                                             /*!< fSAMPLING= fEEVS/16U, N=8U */
+#define HRTIM_EVENTFILTER_13        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_0)                       /*!< fSAMPLING= fEEVS/32U, N=5U */
+#define HRTIM_EVENTFILTER_14        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1)                       /*!< fSAMPLING= fEEVS/32U, N=6U */
+#define HRTIM_EVENTFILTER_15        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)  /*!< fSAMPLING= fEEVS/32U, N=8U */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
+  * @{
+  * @brief Constants defining division ratio between the timer clock frequency
+  *        fHRTIM) and the external event signal sampling clock (fEEVS)
+  *        used by the digital filters
+  */
+#define HRTIM_EVENTPRESCALER_DIV1    (0x00000000U)                                   /*!< fEEVS=fHRTIM */
+#define HRTIM_EVENTPRESCALER_DIV2    (HRTIM_EECR3_EEVSD_0)                           /*!< fEEVS=fHRTIM / 2U */
+#define HRTIM_EVENTPRESCALER_DIV4    (HRTIM_EECR3_EEVSD_1)                           /*!< fEEVS=fHRTIM / 4U */
+#define HRTIM_EVENTPRESCALER_DIV8    (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0)     /*!< fEEVS=fHRTIM / 8U */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
+  * @{
+  * @brief Constants defining whether a fault is triggered by any external
+  *        or internal fault source
+  */
+#define HRTIM_FAULTSOURCE_DIGITALINPUT      (0x00000000U)              /*!< Fault input is FLT input pin */
+#define HRTIM_FAULTSOURCE_INTERNAL          (0x00000001U)              /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
+#define HRTIM_FAULTSOURCE_EEVINPUT          (0x00000002U)              /*!< Fault input is EEV pin */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
+  * @{
+  * @brief Constants defining the polarity of a fault event
+  */
+#define HRTIM_FAULTPOLARITY_LOW     (0x00000000U)            /*!< Fault input is active low */
+#define HRTIM_FAULTPOLARITY_HIGH    (HRTIM_FLTINR1_FLT1P)    /*!< Fault input is active high */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Fault_Blanking HRTIM Fault Blanking Source
+  * @{
+  * @brief Constants defining the blanking source of a fault event
+  */
+#define HRTIM_FAULTBLANKINGMODE_RSTALIGNED  (0x00000000U)     /*!< Fault blanking source is Reset-aligned window */
+#define HRTIM_FAULTBLANKINGMODE_MOVING      (0x00000001U)     /*!< Fault blanking source is Moving window */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Fault_ResetMode HRTIM Fault Reset Mode
+  * @{
+  * @brief Constants defining the Counter reset mode of a fault event
+  */
+#define HRTIM_FAULTCOUNTERRST_UNCONDITIONAL  (0x00000000U)       /*!< Fault counter is reset on each reset / roll-over event */
+#define HRTIM_FAULTCOUNTERRST_CONDITIONAL    (0x00000001U)       /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last countingperiod.*/
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Fault_Blanking_Control  HRTIM Fault Blanking Control
+  * @{
+  * @brief Constants used to enable or disable the blanking mode of a fault channel
+  */
+#define HRTIM_FAULTBLANKINGCTL_DISABLED 0x00000000U /*!< No blanking on Fault */
+#define HRTIM_FAULTBLANKINGCTL_ENABLED  0x00000001U /*!< Fault blanking mode */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
+  * @{
+  * @ brief Constants defining the frequency used to sample the fault input and
+  *         the length (N) of the digital filter applied
+  */
+#define HRTIM_FAULTFILTER_NONE      (0x00000000U)                                                                                    /*!< Filter disabled */
+#define HRTIM_FAULTFILTER_1         (HRTIM_FLTINR1_FLT1F_0)                                                                          /*!< fSAMPLING= fHRTIM, N=2U */
+#define HRTIM_FAULTFILTER_2         (HRTIM_FLTINR1_FLT1F_1)                                                                          /*!< fSAMPLING= fHRTIM, N=4U */
+#define HRTIM_FAULTFILTER_3         (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fHRTIM, N=8U */
+#define HRTIM_FAULTFILTER_4         (HRTIM_FLTINR1_FLT1F_2)                                                                          /*!< fSAMPLING= fFLTS/2U, N=6U */
+#define HRTIM_FAULTFILTER_5         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/2U, N=8U */
+#define HRTIM_FAULTFILTER_6         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/4U, N=6U */
+#define HRTIM_FAULTFILTER_7         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/4U, N=8U */
+#define HRTIM_FAULTFILTER_8         (HRTIM_FLTINR1_FLT1F_3)                                                                          /*!< fSAMPLING= fFLTS/8U, N=6U */
+#define HRTIM_FAULTFILTER_9         (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/8U, N=8U */
+#define HRTIM_FAULTFILTER_10        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/16U, N=5U */
+#define HRTIM_FAULTFILTER_11        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/16U, N=6U */
+#define HRTIM_FAULTFILTER_12        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)                                                  /*!< fSAMPLING= fFLTS/16U, N=8U */
+#define HRTIM_FAULTFILTER_13        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/32U, N=5U */
+#define HRTIM_FAULTFILTER_14        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                          /*!< fSAMPLING= fFLTS/32U, N=6U */
+#define HRTIM_FAULTFILTER_15        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)  /*!< fSAMPLING= fFLTS/32U, N=8U */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Fault_Counter HRTIM Fault counter threshold value
+  * @{
+  * @ brief Constants defining the FAULT Counter threshold
+  */
+#define HRTIM_FAULTCOUNTER_NONE     ((uint32_t)0U )  /*!< Counter threshold = 0U */
+#define HRTIM_FAULTCOUNTER_1        ((uint32_t)1U )  /*!< Counter threshold = 1U */
+#define HRTIM_FAULTCOUNTER_2        ((uint32_t)2U )  /*!< Counter threshold = 2U */
+#define HRTIM_FAULTCOUNTER_3        ((uint32_t)3U )  /*!< Counter threshold = 3U */
+#define HRTIM_FAULTCOUNTER_4        ((uint32_t)4U )  /*!< Counter threshold = 4U */
+#define HRTIM_FAULTCOUNTER_5        ((uint32_t)5U )  /*!< Counter threshold = 5U */
+#define HRTIM_FAULTCOUNTER_6        ((uint32_t)6U )  /*!< Counter threshold = 6U */
+#define HRTIM_FAULTCOUNTER_7        ((uint32_t)7U )  /*!< Counter threshold = 7U */
+#define HRTIM_FAULTCOUNTER_8        ((uint32_t)8U )  /*!< Counter threshold = 8U */
+#define HRTIM_FAULTCOUNTER_9        ((uint32_t)9U )  /*!< Counter threshold = 9U */
+#define HRTIM_FAULTCOUNTER_10       ((uint32_t)10U)  /*!< Counter threshold = 10U */
+#define HRTIM_FAULTCOUNTER_11       ((uint32_t)11U)  /*!< Counter threshold = 11U */
+#define HRTIM_FAULTCOUNTER_12       ((uint32_t)12U)  /*!< Counter threshold = 12U */
+#define HRTIM_FAULTCOUNTER_13       ((uint32_t)13U)  /*!< Counter threshold = 13U */
+#define HRTIM_FAULTCOUNTER_14       ((uint32_t)14U)  /*!< Counter threshold = 14U */
+#define HRTIM_FAULTCOUNTER_15       ((uint32_t)15U)  /*!< Counter threshold = 15U */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
+  * @{
+  * @brief Constants defining whether or not the fault programming bits are
+           write protected
+  */
+#define HRTIM_FAULTLOCK_READWRITE       (0x00000000U)               /*!< Fault settings bits are read/write */
+#define HRTIM_FAULTLOCK_READONLY        (HRTIM_FLTINR1_FLT1LCK)     /*!< Fault settings bits are read only */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
+  * @{
+  * @brief Constants defining the division ratio between the timer clock
+  *        frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
+  *        by the digital filters.
+  */
+#define HRTIM_FAULTPRESCALER_DIV1    (0x00000000U)                                     /*!< fFLTS=fHRTIM */
+#define HRTIM_FAULTPRESCALER_DIV2    (HRTIM_FLTINR2_FLTSD_0)                           /*!< fFLTS=fHRTIM / 2U */
+#define HRTIM_FAULTPRESCALER_DIV4    (HRTIM_FLTINR2_FLTSD_1)                           /*!< fFLTS=fHRTIM / 4U */
+#define HRTIM_FAULTPRESCALER_DIV8    (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0)   /*!< fFLTS=fHRTIM / 8U */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
+  * @{
+  * @brief Constants defining if the burst mode is entered once or if it is
+  *        continuously operating
+  */
+#define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U)           /*!< Burst mode operates in single shot mode */
+#define HRTIM_BURSTMODE_CONTINOUS   (HRTIM_BMCR_BMOM)      /*!< Burst mode operates in continuous mode */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
+  * @{
+  * @brief Constants defining the clock source for the burst mode counter
+  */
+#define HRTIM_BURSTMODECLOCKSOURCE_MASTER     (0x00000000U)                                                   /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A    (HRTIM_BMCR_BMCLK_0)                                            /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B    (HRTIM_BMCR_BMCLK_1)                                            /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C    (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D    (HRTIM_BMCR_BMCLK_2)                                            /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_F    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)                       /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO  (HRTIM_BMCR_BMCLK_3)                                            /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
+#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM     (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)                       /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
+  * @{
+  * @brief Constants defining the prescaling ratio of the fHRTIM clock
+  *        for the burst mode controller
+  */
+#define HRTIM_BURSTMODEPRESCALER_DIV1     (0x00000000U)                                                                           /*!< fBRST = fHRTIM */
+#define HRTIM_BURSTMODEPRESCALER_DIV2     (HRTIM_BMCR_BMPRSC_0)                                                                   /*!< fBRST = fHRTIM/2U */
+#define HRTIM_BURSTMODEPRESCALER_DIV4     (HRTIM_BMCR_BMPRSC_1)                                                                   /*!< fBRST = fHRTIM/4U */
+#define HRTIM_BURSTMODEPRESCALER_DIV8     (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/8U */
+#define HRTIM_BURSTMODEPRESCALER_DIV16    (HRTIM_BMCR_BMPRSC_2)                                                                   /*!< fBRST = fHRTIM/16U */
+#define HRTIM_BURSTMODEPRESCALER_DIV32    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/32U */
+#define HRTIM_BURSTMODEPRESCALER_DIV64    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/64U */
+#define HRTIM_BURSTMODEPRESCALER_DIV128   (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/128U */
+#define HRTIM_BURSTMODEPRESCALER_DIV256   (HRTIM_BMCR_BMPRSC_3)                                                                   /*!< fBRST = fHRTIM/256U */
+#define HRTIM_BURSTMODEPRESCALER_DIV512   (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/512U */
+#define HRTIM_BURSTMODEPRESCALER_DIV1024  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/1024U */
+#define HRTIM_BURSTMODEPRESCALER_DIV2048  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/2048U*/
+#define HRTIM_BURSTMODEPRESCALER_DIV4096  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)                                             /*!< fBRST = fHRTIM/4096U */
+#define HRTIM_BURSTMODEPRESCALER_DIV8192  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/8192U */
+#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                       /*!< fBRST = fHRTIM/16384U */
+#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
+  * @{
+  * @brief Constants defining whether or not burst mode registers preload
+           mechanism is enabled, i.e. a write access into a preloadable register
+          (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
+  */
+#define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U)  /*!< Preload disabled: the write access is directly done into active registers */
+#define HRIM_BURSTMODEPRELOAD_ENABLED  (HRTIM_BMCR_BMPREN)     /*!< Preload enabled: the write access is done into preload registers */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
+  * @{
+  * @brief Constants defining the events that can be used to trig the burst
+  *        mode operation
+  */
+#define HRTIM_BURSTMODETRIGGER_NONE               0x00000000U             /*!<  No trigger */
+#define HRTIM_BURSTMODETRIGGER_MASTER_RESET       (HRTIM_BMTRGR_MSTRST)   /*!<  Master reset */
+#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION  (HRTIM_BMTRGR_MSTREP)   /*!<  Master repetition */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1        (HRTIM_BMTRGR_MSTCMP1)  /*!<  Master compare 1U */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2        (HRTIM_BMTRGR_MSTCMP2)  /*!<  Master compare 2U */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3        (HRTIM_BMTRGR_MSTCMP3)  /*!<  Master compare 3U */
+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4        (HRTIM_BMTRGR_MSTCMP4)  /*!<  Master compare 4U */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET       (HRTIM_BMTRGR_TARST)    /*!< Timer A reset  */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION  (HRTIM_BMTRGR_TAREP)    /*!< Timer A repetition  */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1        (HRTIM_BMTRGR_TACMP1)   /*!< Timer A compare 1  */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2        (HRTIM_BMTRGR_TACMP2)   /*!< Timer A compare 2  */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET       (HRTIM_BMTRGR_TBRST)    /*!< Timer B reset  */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION  (HRTIM_BMTRGR_TBREP)    /*!< Timer B repetition  */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1        (HRTIM_BMTRGR_TBCMP1)   /*!< Timer B compare 1  */
+#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2        (HRTIM_BMTRGR_TBCMP2)   /*!< Timer B compare 2  */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET       (HRTIM_BMTRGR_TCRST)    /*!< Timer C reset  */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION  (HRTIM_BMTRGR_TCREP)    /*!< Timer C repetition  */
+#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1        (HRTIM_BMTRGR_TCCMP1)   /*!< Timer C compare 1  */
+#define HRTIM_BURSTMODETRIGGER_TIMERF_RESET       (HRTIM_BMTRGR_TFRST)    /*!< Timer F reset  */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET       (HRTIM_BMTRGR_TDRST)    /*!< Timer D reset  */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION  (HRTIM_BMTRGR_TDREP)    /*!< Timer D repetition  */
+#define HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION  (HRTIM_BMTRGR_TFREP)    /*!< Timer F repetition  */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2        (HRTIM_BMTRGR_TDCMP2)   /*!< Timer D compare 2  */
+#define HRTIM_BURSTMODETRIGGER_TIMERF_CMP1        (HRTIM_BMTRGR_TFCMP1)   /*!< Timer F compare 1  */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION  (HRTIM_BMTRGR_TEREP)    /*!< Timer E repetition  */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1        (HRTIM_BMTRGR_TECMP1)   /*!< Timer E compare 1  */
+#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2        (HRTIM_BMTRGR_TECMP2)   /*!< Timer E compare 2  */
+#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7      (HRTIM_BMTRGR_TAEEV7)   /*!< Timer A period following External Event 7  */
+#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8      (HRTIM_BMTRGR_TDEEV8)   /*!< Timer D period following External Event 8  */
+#define HRTIM_BURSTMODETRIGGER_EVENT_7            (HRTIM_BMTRGR_EEV7)     /*!< External Event 7 (timer A filters applied) */
+#define HRTIM_BURSTMODETRIGGER_EVENT_8            (HRTIM_BMTRGR_EEV8)     /*!< External Event 8 (timer D filters applied)*/
+#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP       (HRTIM_BMTRGR_OCHPEV)   /*!< On-chip Event */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
+  * @{
+  * @brief constants defining the source triggering the update of the
+     HRTIM_ADCxR register (transfer from preload to active register).
+  */
+#define HRTIM_ADCTRIGGERUPDATE_MASTER  0x00000000U                                   /*!< Master timer */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)                        /*!< Timer A */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)                        /*!< Timer B */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)                        /*!< Timer D */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
+#define HRTIM_ADCTRIGGERUPDATE_TIMER_F (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_1) /*!< Timer F */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
+  * @{
+  * @brief constants defining the events triggering ADC conversion.
+  *        HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
+  *        HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
+  *        HRTIM_ADCTRIGGEREVENT579_*: ADC Triggers 5 and 7 and 9
+  *        HRTIM_ADCTRIGGEREVENT6810_*: ADC Triggers 6 and 8 and 10
+  */
+#define HRTIM_ADCTRIGGEREVENT13_NONE           0x00000000U              /*!< No ADC trigger event */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1    (HRTIM_ADC1R_AD1MC1)     /*!< ADC Trigger on master compare 1U */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2    (HRTIM_ADC1R_AD1MC2)     /*!< ADC Trigger on master compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3    (HRTIM_ADC1R_AD1MC3)     /*!< ADC Trigger on master compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4    (HRTIM_ADC1R_AD1MC4)     /*!< ADC Trigger on master compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD  (HRTIM_ADC1R_AD1MPER)    /*!< ADC Trigger on master period */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_1        (HRTIM_ADC1R_AD1EEV1)    /*!< ADC Trigger on external event 1U */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_2        (HRTIM_ADC1R_AD1EEV2)    /*!< ADC Trigger on external event 2U */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_3        (HRTIM_ADC1R_AD1EEV3)    /*!< ADC Trigger on external event 3U */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_4        (HRTIM_ADC1R_AD1EEV4)    /*!< ADC Trigger on external event 4U */
+#define HRTIM_ADCTRIGGEREVENT13_EVENT_5        (HRTIM_ADC1R_AD1EEV5)    /*!< ADC Trigger on external event 5U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP2    (HRTIM_ADC1R_AD1TFC2)    /*!< ADC Trigger on Timer F compare 2U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3    (HRTIM_ADC1R_AD1TAC3)    /*!< ADC Trigger on Timer A compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4    (HRTIM_ADC1R_AD1TAC4)    /*!< ADC Trigger on Timer A compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD  (HRTIM_ADC1R_AD1TAPER)   /*!< ADC Trigger on Timer A period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET   (HRTIM_ADC1R_AD1TARST)   /*!< ADC Trigger on Timer A reset */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP3    (HRTIM_ADC1R_AD1TFC3)    /*!< ADC Trigger on Timer F compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3    (HRTIM_ADC1R_AD1TBC3)    /*!< ADC Trigger on Timer B compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4    (HRTIM_ADC1R_AD1TBC4)    /*!< ADC Trigger on Timer B compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD  (HRTIM_ADC1R_AD1TBPER)   /*!< ADC Trigger on Timer B period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET   (HRTIM_ADC1R_AD1TBRST)   /*!< ADC Trigger on Timer B reset */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERF_CMP4    (HRTIM_ADC1R_AD1TFC4)    /*!< ADC Trigger on Timer F compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3    (HRTIM_ADC1R_AD1TCC3)    /*!< ADC Trigger on Timer C compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4    (HRTIM_ADC1R_AD1TCC4)    /*!< ADC Trigger on Timer C compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD  (HRTIM_ADC1R_AD1TCPER)   /*!< ADC Trigger on Timer C period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERF_PERIOD  (HRTIM_ADC1R_AD1TFPER)   /*!< ADC Trigger on Timer F period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3    (HRTIM_ADC1R_AD1TDC3)    /*!< ADC Trigger on Timer D compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4    (HRTIM_ADC1R_AD1TDC4)    /*!< ADC Trigger on Timer D compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD  (HRTIM_ADC1R_AD1TDPER)   /*!< ADC Trigger on Timer D period */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERF_RESET   (HRTIM_ADC1R_AD1TFRST)   /*!< ADC Trigger on Timer F reset */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3    (HRTIM_ADC1R_AD1TEC3)    /*!< ADC Trigger on Timer E compare 3U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4    (HRTIM_ADC1R_AD1TEC4)    /*!< ADC Trigger on Timer E compare 4U */
+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD  (HRTIM_ADC1R_AD1TEPER)   /*!< ADC Trigger on Timer E period */
+
+#define HRTIM_ADCTRIGGEREVENT24_NONE           0x00000000U               /*!< No ADC trigger event */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1    (HRTIM_ADC2R_AD2MC1)     /*!< ADC Trigger on master compare 1U */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2    (HRTIM_ADC2R_AD2MC2)     /*!< ADC Trigger on master compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3    (HRTIM_ADC2R_AD2MC3)     /*!< ADC Trigger on master compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4    (HRTIM_ADC2R_AD2MC4)     /*!< ADC Trigger on master compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD  (HRTIM_ADC2R_AD2MPER)    /*!< ADC Trigger on master period */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_6        (HRTIM_ADC2R_AD2EEV6)    /*!< ADC Trigger on external event 6U */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_7        (HRTIM_ADC2R_AD2EEV7)    /*!< ADC Trigger on external event 7U */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_8        (HRTIM_ADC2R_AD2EEV8)    /*!< ADC Trigger on external event 8U */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_9        (HRTIM_ADC2R_AD2EEV9)    /*!< ADC Trigger on external event 9U */
+#define HRTIM_ADCTRIGGEREVENT24_EVENT_10       (HRTIM_ADC2R_AD2EEV10)   /*!< ADC Trigger on external event 10U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2    (HRTIM_ADC2R_AD2TAC2)    /*!< ADC Trigger on Timer A compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP2    (HRTIM_ADC2R_AD2TFC2)    /*!< ADC Trigger on Timer F compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4    (HRTIM_ADC2R_AD2TAC4)    /*!< ADC Trigger on Timer A compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD  (HRTIM_ADC2R_AD2TAPER)   /*!< ADC Trigger on Timer A period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2    (HRTIM_ADC2R_AD2TBC2)    /*!< ADC Trigger on Timer B compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP3    (HRTIM_ADC2R_AD2TFC3)    /*!< ADC Trigger on Timer F compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4    (HRTIM_ADC2R_AD2TBC4)    /*!< ADC Trigger on Timer B compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD  (HRTIM_ADC2R_AD2TBPER)   /*!< ADC Trigger on Timer B period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2    (HRTIM_ADC2R_AD2TCC2)    /*!< ADC Trigger on Timer C compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERF_CMP4    (HRTIM_ADC2R_AD2TFC4)    /*!< ADC Trigger on Timer F compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4    (HRTIM_ADC2R_AD2TCC4)    /*!< ADC Trigger on Timer C compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD  (HRTIM_ADC2R_AD2TCPER)   /*!< ADC Trigger on Timer C period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET   (HRTIM_ADC2R_AD2TCRST)   /*!< ADC Trigger on Timer C reset */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2    (HRTIM_ADC2R_AD2TDC2)    /*!< ADC Trigger on Timer D compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERF_PERIOD  (HRTIM_ADC2R_AD2TFPER)   /*!< ADC Trigger on Timer F period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4    (HRTIM_ADC2R_AD2TDC4)    /*!< ADC Trigger on Timer D compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD  (HRTIM_ADC2R_AD2TDPER)   /*!< ADC Trigger on Timer D period */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET   (HRTIM_ADC2R_AD2TDRST)   /*!< ADC Trigger on Timer D reset */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2    (HRTIM_ADC2R_AD2TEC2)    /*!< ADC Trigger on Timer E compare 2U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3    (HRTIM_ADC2R_AD2TEC3)    /*!< ADC Trigger on Timer E compare 3U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4    (HRTIM_ADC2R_AD2TEC4)    /*!< ADC Trigger on Timer E compare 4U */
+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET   (HRTIM_ADC2R_AD2TERST)   /*!< ADC Trigger on Timer E reset */
+
+
+#define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP1    ((uint32_t)0x00U)  /*!< ADC Trigger on master compare 1U */
+#define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP2    ((uint32_t)0x01U)  /*!< ADC Trigger on master compare 2U */
+#define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP3    ((uint32_t)0x02U)  /*!< ADC Trigger on master compare 3U */
+#define HRTIM_ADCTRIGGEREVENT6810_MASTER_CMP4    ((uint32_t)0x03U)  /*!< ADC Trigger on master compare 4U */
+#define HRTIM_ADCTRIGGEREVENT6810_MASTER_PERIOD  ((uint32_t)0x04U)  /*!< ADC Trigger on master period */
+#define HRTIM_ADCTRIGGEREVENT6810_EVENT_6        ((uint32_t)0x05U)  /*!< ADC Trigger on external event 6U */
+#define HRTIM_ADCTRIGGEREVENT6810_EVENT_7        ((uint32_t)0x06U)  /*!< ADC Trigger on external event 7U */
+#define HRTIM_ADCTRIGGEREVENT6810_EVENT_8        ((uint32_t)0x07U)  /*!< ADC Trigger on external event 8U */
+#define HRTIM_ADCTRIGGEREVENT6810_EVENT_9        ((uint32_t)0x08U)  /*!< ADC Trigger on external event 9U */
+#define HRTIM_ADCTRIGGEREVENT6810_EVENT_10       ((uint32_t)0x09U)  /*!< ADC Trigger on external event 10U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP2    ((uint32_t)0x0AU)  /*!< ADC Trigger on Timer A compare 2U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERA_CMP4    ((uint32_t)0x0BU)  /*!< ADC Trigger on Timer A compare 4U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERA_PERIOD  ((uint32_t)0x0CU)  /*!< ADC Trigger on Timer A period */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP2    ((uint32_t)0x0DU)  /*!< ADC Trigger on Timer B compare 2U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERB_CMP4    ((uint32_t)0x0EU)  /*!< ADC Trigger on Timer B compare 4U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERB_PERIOD  ((uint32_t)0x0FU)  /*!< ADC Trigger on Timer B period */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP2    ((uint32_t)0x10U)  /*!< ADC Trigger on Timer C compare 2U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERC_CMP4    ((uint32_t)0x11U)  /*!< ADC Trigger on Timer C compare 4U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERC_PERIOD  ((uint32_t)0x12U)  /*!< ADC Trigger on Timer C period */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERC_RESET   ((uint32_t)0x13U)  /*!< ADC Trigger on Timer C reset */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP2    ((uint32_t)0x14U)  /*!< ADC Trigger on Timer D compare 2U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERD_CMP4    ((uint32_t)0x15U)  /*!< ADC Trigger on Timer D compare 4U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERD_PERIOD  ((uint32_t)0x16U)  /*!< ADC Trigger on Timer D period */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERD_RESET   ((uint32_t)0x17U)  /*!< ADC Trigger on Timer D reset */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP2    ((uint32_t)0x18U)  /*!< ADC Trigger on Timer E compare 2U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP3    ((uint32_t)0x19U)  /*!< ADC Trigger on Timer E compare 3U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERE_CMP4    ((uint32_t)0x1AU)  /*!< ADC Trigger on Timer E compare 4U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERE_RESET   ((uint32_t)0x1BU)  /*!< ADC Trigger on Timer E reset */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP2    ((uint32_t)0x1CU)  /*!< ADC Trigger on Timer F compare 2U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP3    ((uint32_t)0x1DU)  /*!< ADC Trigger on Timer F compare 3U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERF_CMP4    ((uint32_t)0x1EU)  /*!< ADC Trigger on Timer F compare 4U */
+#define HRTIM_ADCTRIGGEREVENT6810_TIMERF_PERIOD  ((uint32_t)0x1FU)  /*!< ADC Trigger on Timer F period */
+
+#define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP1    ((uint32_t)0x00U)  /*!< ADC Trigger on master compare 1U */
+#define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP2    ((uint32_t)0x01U)  /*!< ADC Trigger on master compare 2U */
+#define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP3    ((uint32_t)0x02U)  /*!< ADC Trigger on master compare 3U */
+#define HRTIM_ADCTRIGGEREVENT579_MASTER_CMP4    ((uint32_t)0x03U)  /*!< ADC Trigger on master compare 4U */
+#define HRTIM_ADCTRIGGEREVENT579_MASTER_PERIOD  ((uint32_t)0x04U)  /*!< ADC Trigger on master period */
+#define HRTIM_ADCTRIGGEREVENT579_EVENT_1        ((uint32_t)0x05U)  /*!< ADC Trigger on external event 1U */
+#define HRTIM_ADCTRIGGEREVENT579_EVENT_2        ((uint32_t)0x06U)  /*!< ADC Trigger on external event 2U */
+#define HRTIM_ADCTRIGGEREVENT579_EVENT_3        ((uint32_t)0x07U)  /*!< ADC Trigger on external event 3U */
+#define HRTIM_ADCTRIGGEREVENT579_EVENT_4        ((uint32_t)0x08U)  /*!< ADC Trigger on external event 4U */
+#define HRTIM_ADCTRIGGEREVENT579_EVENT_5        ((uint32_t)0x09U)  /*!< ADC Trigger on external event 5U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP3    ((uint32_t)0x0AU)  /*!< ADC Trigger on Timer A compare 3U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERA_CMP4    ((uint32_t)0x0BU)  /*!< ADC Trigger on Timer A compare 4U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERA_PERIOD  ((uint32_t)0x0CU)  /*!< ADC Trigger on Timer A period */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERA_RESET   ((uint32_t)0x0DU)  /*!< ADC Trigger on Timer A reset */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP3    ((uint32_t)0x0EU)  /*!< ADC Trigger on Timer B compare 3U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERB_CMP4    ((uint32_t)0x0FU)  /*!< ADC Trigger on Timer B compare 4U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERB_PERIOD  ((uint32_t)0x10U)  /*!< ADC Trigger on Timer B period */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERB_RESET   ((uint32_t)0x11U)  /*!< ADC Trigger on Timer B reset */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP3    ((uint32_t)0x12U)  /*!< ADC Trigger on Timer C compare 3U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERC_CMP4    ((uint32_t)0x13U)  /*!< ADC Trigger on Timer C compare 4U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERC_PERIOD  ((uint32_t)0x14U)  /*!< ADC Trigger on Timer C period */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP3    ((uint32_t)0x15U)  /*!< ADC Trigger on Timer D compare 3U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERD_CMP4    ((uint32_t)0x16U)  /*!< ADC Trigger on Timer D compare 4U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERD_PERIOD  ((uint32_t)0x17U)  /*!< ADC Trigger on Timer D period */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP3    ((uint32_t)0x18U)  /*!< ADC Trigger on Timer E compare 3U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERE_CMP4    ((uint32_t)0x19U)  /*!< ADC Trigger on Timer E compare 4U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERE_PERIOD  ((uint32_t)0x1AU)  /*!< ADC Trigger on Timer E period */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP2    ((uint32_t)0x1BU)  /*!< ADC Trigger on Timer F compare 2U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP3    ((uint32_t)0x1CU)  /*!< ADC Trigger on Timer F compare 3U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERF_CMP4    ((uint32_t)0x1DU)  /*!< ADC Trigger on Timer F compare 4U */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERF_PERIOD  ((uint32_t)0x1EU)  /*!< ADC Trigger on Timer F period */
+#define HRTIM_ADCTRIGGEREVENT579_TIMERF_RESET   ((uint32_t)0x1FU)  /*!< ADC Trigger on Timer F reset */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate
+  * @{
+  * @brief Constants defining the DLL calibration periods (in micro seconds)
+  */
+#define HRTIM_SINGLE_CALIBRATION    0xFFFFFFFFU                                    /*!< Non periodic DLL calibration */
+#define HRTIM_CALIBRATIONRATE_0     0x00000000U                                    /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
+#define HRTIM_CALIBRATIONRATE_1     (HRTIM_DLLCR_CALRTE_0)                         /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
+#define HRTIM_CALIBRATIONRATE_2     (HRTIM_DLLCR_CALRTE_1)                         /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
+#define HRTIM_CALIBRATIONRATE_3     (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)  /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
+  * @{
+  * @brief Constants defining the registers that can be written during a burst
+  *        DMA operation
+  */
+#define HRTIM_BURSTDMA_NONE  0x00000000U               /*!< No register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CR    (HRTIM_BDTUPR_TIMCR)      /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_ICR   (HRTIM_BDTUPR_TIMICR)     /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_DIER  (HRTIM_BDTUPR_TIMDIER)    /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CNT   (HRTIM_BDTUPR_TIMCNT)     /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_PER   (HRTIM_BDTUPR_TIMPER)     /*!< MPER or PERxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_REP   (HRTIM_BDTUPR_TIMREP)     /*!< MREPR or REPxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP1  (HRTIM_BDTUPR_TIMCMP1)    /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP2  (HRTIM_BDTUPR_TIMCMP2)    /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP3  (HRTIM_BDTUPR_TIMCMP3)    /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CMP4  (HRTIM_BDTUPR_TIMCMP4)    /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_DTR   (HRTIM_BDTUPR_TIMDTR)     /*!< TDxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R)   /*!< SET1R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R)   /*!< RST1R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R)   /*!< SET2R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R)   /*!< RST1R register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1)   /*!< EEFxR1 register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2)   /*!< EEFxR2 register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_RSTR  (HRTIM_BDTUPR_TIMRSTR)    /*!< RSTxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CHPR  (HRTIM_BDTUPR_TIMCHPR)    /*!< CHPxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_OUTR  (HRTIM_BDTUPR_TIMOUTR)    /*!< OUTxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_FLTR  (HRTIM_BDTUPR_TIMFLTR)    /*!< FLTxR register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_CR2   (HRTIM_BDTUPR_TIMCR2)     /*!< TIMxCR2 register is updated by Burst DMA accesses */
+#define HRTIM_BURSTDMA_EEFR3 (HRTIM_BDTUPR_TIMEEFR3)   /*!< EEFxR3 register is updated by Burst DMA accesses */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
+  * @{
+  * @brief Constants used to enable or disable the burst mode controller
+  */
+#define HRTIM_BURSTMODECTL_DISABLED 0x00000000U          /*!< Burst mode disabled */
+#define HRTIM_BURSTMODECTL_ENABLED  (HRTIM_BMCR_BME)     /*!< Burst mode enabled */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Fault_Mode_Control  HRTIM Fault Mode Control
+  * @{
+  * @brief Constants used to enable or disable a fault channel
+  */
+#define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */
+#define HRTIM_FAULTMODECTL_ENABLED  0x00000001U /*!< Fault channel is  enabled */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
+  * @{
+  * @brief Constants used to force timer registers update
+  */
+#define HRTIM_TIMERUPDATE_MASTER    (HRTIM_CR2_MSWU)     /*!< Force an immediate transfer from the preload to the active register in the master timer */
+#define HRTIM_TIMERUPDATE_A         (HRTIM_CR2_TASWU)    /*!< Force an immediate transfer from the preload to the active register in the timer A */
+#define HRTIM_TIMERUPDATE_B         (HRTIM_CR2_TBSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer B */
+#define HRTIM_TIMERUPDATE_C         (HRTIM_CR2_TCSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer C */
+#define HRTIM_TIMERUPDATE_D         (HRTIM_CR2_TDSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer D */
+#define HRTIM_TIMERUPDATE_E         (HRTIM_CR2_TESWU)    /*!< Force an immediate transfer from the preload to the active register in the timer E */
+#define HRTIM_TIMERUPDATE_F         (HRTIM_CR2_TFSWU)    /*!< Forces an immediate transfer from the preload to the active register in the timer F */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Software_Timer_SwapOutput  HRTIM Software Timer swap Output
+  * @{
+  * @brief Constants used to swap the output of the timer registers
+  */
+#define HRTIM_TIMERSWAP_A         (HRTIM_CR2_SWPA)    /*!< Swap the output of the Timer A */
+#define HRTIM_TIMERSWAP_B         (HRTIM_CR2_SWPB)    /*!< Swap the output of the Timer B */
+#define HRTIM_TIMERSWAP_C         (HRTIM_CR2_SWPC)    /*!< Swap the output of the Timer C */
+#define HRTIM_TIMERSWAP_D         (HRTIM_CR2_SWPD)    /*!< Swap the output of the Timer D */
+#define HRTIM_TIMERSWAP_E         (HRTIM_CR2_SWPE)    /*!< Swap the output of the Timer E */
+#define HRTIM_TIMERSWAP_F         (HRTIM_CR2_SWPF)    /*!< Swap the output of the Timer F */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
+  * @{
+  * @brief Constants used to force timer counter reset
+  */
+#define HRTIM_TIMERRESET_MASTER    (HRTIM_CR2_MRST)     /*!< Reset the master timer counter */
+#define HRTIM_TIMERRESET_TIMER_A   (HRTIM_CR2_TARST)    /*!< Reset the timer A counter */
+#define HRTIM_TIMERRESET_TIMER_B   (HRTIM_CR2_TBRST)    /*!< Reset the timer B counter */
+#define HRTIM_TIMERRESET_TIMER_C   (HRTIM_CR2_TCRST)    /*!< Reset the timer C counter */
+#define HRTIM_TIMERRESET_TIMER_D   (HRTIM_CR2_TDRST)    /*!< Reset the timer D counter */
+#define HRTIM_TIMERRESET_TIMER_E   (HRTIM_CR2_TERST)    /*!< Reset the timer E counter */
+#define HRTIM_TIMERRESET_TIMER_F   (HRTIM_CR2_TFRST)    /*!< Reset the timer F counter */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Output_Level HRTIM Output Level
+  * @{
+  * @brief Constants defining the level of a timer output
+  */
+#define HRTIM_OUTPUTLEVEL_ACTIVE     (0x00000001U) /*!< Force the output to its active state */
+#define HRTIM_OUTPUTLEVEL_INACTIVE   (0x00000002U) /*!< Force the output to its inactive state */
+
+#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
+  (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE)  || \
+   ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Output_State HRTIM Output State
+  * @{
+  * @brief Constants defining the state of a timer output
+  */
+#define HRTIM_OUTPUTSTATE_IDLE     (0x00000001U)  /*!< Main operating mode, where the output can take the active or
+                                                              inactive level as programmed in the crossbar unit */
+#define HRTIM_OUTPUTSTATE_RUN      (0x00000002U)  /*!< Default operating state (e.g. after an HRTIM reset, when the
+                                                              outputs are disabled by software or during a burst mode operation */
+#define HRTIM_OUTPUTSTATE_FAULT    (0x00000003U)  /*!< Safety state, entered in case of a shut-down request on
+                                                              FAULTx inputs */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
+  * @{
+  * @brief Constants defining the operating state of the burst mode controller
+  */
+#define HRTIM_BURSTMODESTATUS_NORMAL   0x00000000U          /*!< Normal operation */
+#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT)   /*!< Burst operation on-going */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
+  * @{
+  * @brief Constants defining on which output the signal is currently applied
+  *        in push-pull mode
+  */
+#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1    0x00000000U            /*!< Signal applied on output 1 and output 2 forced inactive */
+#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2   (HRTIM_TIMISR_CPPSTAT)  /*!< Signal applied on output 2 and output 1 forced inactive */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
+  * @{
+  * @brief Constants defining on which output the signal was applied, in
+  *        push-pull mode balanced fault mode or delayed idle mode, when the
+  *        protection was triggered
+  */
+#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1    0x00000000U               /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
+#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2   (HRTIM_TIMISR_IPPSTAT)     /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
+  * @{
+  */
+#define HRTIM_IT_NONE           0x00000000U           /*!< No interrupt enabled */
+#define HRTIM_IT_FLT1           HRTIM_IER_FLT1        /*!< Fault 1 interrupt enable */
+#define HRTIM_IT_FLT2           HRTIM_IER_FLT2        /*!< Fault 2 interrupt enable */
+#define HRTIM_IT_FLT3           HRTIM_IER_FLT3        /*!< Fault 3 interrupt enable */
+#define HRTIM_IT_FLT4           HRTIM_IER_FLT4        /*!< Fault 4 interrupt enable */
+#define HRTIM_IT_FLT5           HRTIM_IER_FLT5        /*!< Fault 5 interrupt enable */
+#define HRTIM_IT_FLT6           HRTIM_IER_FLT6        /*!< Fault 6 interrupt enable */
+#define HRTIM_IT_SYSFLT         HRTIM_IER_SYSFLT      /*!< System Fault interrupt enable */
+#define HRTIM_IT_DLLRDY         HRTIM_IER_DLLRDY      /*!< DLL ready interrupt enable */
+#define HRTIM_IT_BMPER          HRTIM_IER_BMPER       /*!<  Burst mode period interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
+  * @{
+  */
+#define HRTIM_MASTER_IT_NONE         0x00000000U           /*!< No interrupt enabled */
+#define HRTIM_MASTER_IT_MCMP1        HRTIM_MDIER_MCMP1IE   /*!< Master compare 1 interrupt enable */
+#define HRTIM_MASTER_IT_MCMP2        HRTIM_MDIER_MCMP2IE   /*!< Master compare 2 interrupt enable */
+#define HRTIM_MASTER_IT_MCMP3        HRTIM_MDIER_MCMP3IE   /*!< Master compare 3 interrupt enable */
+#define HRTIM_MASTER_IT_MCMP4        HRTIM_MDIER_MCMP4IE   /*!< Master compare 4 interrupt enable */
+#define HRTIM_MASTER_IT_MREP         HRTIM_MDIER_MREPIE    /*!< Master Repetition interrupt enable */
+#define HRTIM_MASTER_IT_SYNC         HRTIM_MDIER_SYNCIE    /*!< Synchronization input interrupt enable */
+#define HRTIM_MASTER_IT_MUPD         HRTIM_MDIER_MUPDIE    /*!< Master update interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
+  * @{
+  */
+#define HRTIM_TIM_IT_NONE       0x00000000U               /*!< No interrupt enabled */
+#define HRTIM_TIM_IT_CMP1       HRTIM_TIMDIER_CMP1IE      /*!< Timer compare 1 interrupt enable */
+#define HRTIM_TIM_IT_CMP2       HRTIM_TIMDIER_CMP2IE      /*!< Timer compare 2 interrupt enable */
+#define HRTIM_TIM_IT_CMP3       HRTIM_TIMDIER_CMP3IE      /*!< Timer compare 3 interrupt enable */
+#define HRTIM_TIM_IT_CMP4       HRTIM_TIMDIER_CMP4IE      /*!< Timer compare 4 interrupt enable */
+#define HRTIM_TIM_IT_REP        HRTIM_TIMDIER_REPIE       /*!< Timer repetition interrupt enable */
+#define HRTIM_TIM_IT_UPD        HRTIM_TIMDIER_UPDIE       /*!< Timer update interrupt enable */
+#define HRTIM_TIM_IT_CPT1       HRTIM_TIMDIER_CPT1IE      /*!< Timer capture 1 interrupt enable */
+#define HRTIM_TIM_IT_CPT2       HRTIM_TIMDIER_CPT2IE      /*!< Timer capture 2 interrupt enable */
+#define HRTIM_TIM_IT_SET1       HRTIM_TIMDIER_SET1IE      /*!< Timer output 1 set interrupt enable */
+#define HRTIM_TIM_IT_RST1       HRTIM_TIMDIER_RST1IE      /*!< Timer output 1 reset interrupt enable */
+#define HRTIM_TIM_IT_SET2       HRTIM_TIMDIER_SET2IE      /*!< Timer output 2 set interrupt enable */
+#define HRTIM_TIM_IT_RST2       HRTIM_TIMDIER_RST2IE      /*!< Timer output 2 reset interrupt enable */
+#define HRTIM_TIM_IT_RST        HRTIM_TIMDIER_RSTIE       /*!< Timer reset interrupt enable */
+#define HRTIM_TIM_IT_DLYPRT     HRTIM_TIMDIER_DLYPRTIE    /*!< Timer delay protection interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
+  * @{
+  */
+#define HRTIM_FLAG_FLT1           HRTIM_ISR_FLT1    /*!< Fault 1 interrupt flag */
+#define HRTIM_FLAG_FLT2           HRTIM_ISR_FLT2    /*!< Fault 2 interrupt flag */
+#define HRTIM_FLAG_FLT3           HRTIM_ISR_FLT3    /*!< Fault 3 interrupt flag */
+#define HRTIM_FLAG_FLT4           HRTIM_ISR_FLT4    /*!< Fault 4 interrupt flag */
+#define HRTIM_FLAG_FLT5           HRTIM_ISR_FLT5    /*!< Fault 5 interrupt flag */
+#define HRTIM_FLAG_FLT6           HRTIM_ISR_FLT6    /*!< Fault 6 interrupt flag */
+#define HRTIM_FLAG_SYSFLT         HRTIM_ISR_SYSFLT  /*!< System Fault interrupt flag */
+#define HRTIM_FLAG_DLLRDY         HRTIM_ISR_DLLRDY  /*!< DLL ready interrupt flag */
+#define HRTIM_FLAG_BMPER          HRTIM_ISR_BMPER   /*!< Burst mode period interrupt flag */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
+  * @{
+  */
+#define HRTIM_MASTER_FLAG_MCMP1        HRTIM_MISR_MCMP1    /*!< Master compare 1 interrupt flag */
+#define HRTIM_MASTER_FLAG_MCMP2        HRTIM_MISR_MCMP2    /*!< Master compare 2 interrupt flag */
+#define HRTIM_MASTER_FLAG_MCMP3        HRTIM_MISR_MCMP3    /*!< Master compare 3 interrupt flag */
+#define HRTIM_MASTER_FLAG_MCMP4        HRTIM_MISR_MCMP4    /*!< Master compare 4 interrupt flag */
+#define HRTIM_MASTER_FLAG_MREP         HRTIM_MISR_MREP     /*!< Master Repetition interrupt flag */
+#define HRTIM_MASTER_FLAG_SYNC         HRTIM_MISR_SYNC     /*!< Synchronization input interrupt flag */
+#define HRTIM_MASTER_FLAG_MUPD         HRTIM_MISR_MUPD     /*!< Master update interrupt flag */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
+  * @{
+  */
+#define HRTIM_TIM_FLAG_CMP1       HRTIM_TIMISR_CMP1      /*!< Timer compare 1 interrupt flag */
+#define HRTIM_TIM_FLAG_CMP2       HRTIM_TIMISR_CMP2      /*!< Timer compare 2 interrupt flag */
+#define HRTIM_TIM_FLAG_CMP3       HRTIM_TIMISR_CMP3      /*!< Timer compare 3 interrupt flag */
+#define HRTIM_TIM_FLAG_CMP4       HRTIM_TIMISR_CMP4      /*!< Timer compare 4 interrupt flag */
+#define HRTIM_TIM_FLAG_REP        HRTIM_TIMISR_REP       /*!< Timer repetition interrupt flag */
+#define HRTIM_TIM_FLAG_UPD        HRTIM_TIMISR_UPD       /*!< Timer update interrupt flag */
+#define HRTIM_TIM_FLAG_CPT1       HRTIM_TIMISR_CPT1      /*!< Timer capture 1 interrupt flag */
+#define HRTIM_TIM_FLAG_CPT2       HRTIM_TIMISR_CPT2      /*!< Timer capture 2 interrupt flag */
+#define HRTIM_TIM_FLAG_SET1       HRTIM_TIMISR_SET1      /*!< Timer output 1 set interrupt flag */
+#define HRTIM_TIM_FLAG_RST1       HRTIM_TIMISR_RST1      /*!< Timer output 1 reset interrupt flag */
+#define HRTIM_TIM_FLAG_SET2       HRTIM_TIMISR_SET2      /*!< Timer output 2 set interrupt flag */
+#define HRTIM_TIM_FLAG_RST2       HRTIM_TIMISR_RST2      /*!< Timer output 2 reset interrupt flag */
+#define HRTIM_TIM_FLAG_RST        HRTIM_TIMISR_RST       /*!< Timer reset interrupt flag */
+#define HRTIM_TIM_FLAG_DLYPRT     HRTIM_TIMISR_DLYPRT    /*!< Timer delay protection interrupt flag */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
+  * @{
+  */
+#define HRTIM_MASTER_DMA_NONE         0x00000000U            /*!< No DMA request enable */
+#define HRTIM_MASTER_DMA_MCMP1        HRTIM_MDIER_MCMP1DE    /*!< Master compare 1 DMA request enable */
+#define HRTIM_MASTER_DMA_MCMP2        HRTIM_MDIER_MCMP2DE    /*!< Master compare 2 DMA request enable */
+#define HRTIM_MASTER_DMA_MCMP3        HRTIM_MDIER_MCMP3DE    /*!< Master compare 3 DMA request enable */
+#define HRTIM_MASTER_DMA_MCMP4        HRTIM_MDIER_MCMP4DE    /*!< Master compare 4 DMA request enable */
+#define HRTIM_MASTER_DMA_MREP         HRTIM_MDIER_MREPDE     /*!< Master Repetition DMA request enable */
+#define HRTIM_MASTER_DMA_SYNC         HRTIM_MDIER_SYNCDE     /*!< Synchronization input DMA request enable */
+#define HRTIM_MASTER_DMA_MUPD         HRTIM_MDIER_MUPDDE     /*!< Master update DMA request enable */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
+  * @{
+  */
+#define HRTIM_TIM_DMA_NONE       0x00000000U               /*!< No DMA request enable */
+#define HRTIM_TIM_DMA_CMP1       HRTIM_TIMDIER_CMP1DE      /*!< Timer compare 1 DMA request enable */
+#define HRTIM_TIM_DMA_CMP2       HRTIM_TIMDIER_CMP2DE      /*!< Timer compare 2 DMA request enable */
+#define HRTIM_TIM_DMA_CMP3       HRTIM_TIMDIER_CMP3DE      /*!< Timer compare 3 DMA request enable */
+#define HRTIM_TIM_DMA_CMP4       HRTIM_TIMDIER_CMP4DE      /*!< Timer compare 4 DMA request enable */
+#define HRTIM_TIM_DMA_REP        HRTIM_TIMDIER_REPDE       /*!< Timer repetition DMA request enable */
+#define HRTIM_TIM_DMA_UPD        HRTIM_TIMDIER_UPDDE       /*!< Timer update DMA request enable */
+#define HRTIM_TIM_DMA_CPT1       HRTIM_TIMDIER_CPT1DE      /*!< Timer capture 1 DMA request enable */
+#define HRTIM_TIM_DMA_CPT2       HRTIM_TIMDIER_CPT2DE      /*!< Timer capture 2 DMA request enable */
+#define HRTIM_TIM_DMA_SET1       HRTIM_TIMDIER_SET1DE      /*!< Timer output 1 set DMA request enable */
+#define HRTIM_TIM_DMA_RST1       HRTIM_TIMDIER_RST1DE      /*!< Timer output 1 reset DMA request enable */
+#define HRTIM_TIM_DMA_SET2       HRTIM_TIMDIER_SET2DE      /*!< Timer output 2 set DMA request enable */
+#define HRTIM_TIM_DMA_RST2       HRTIM_TIMDIER_RST2DE      /*!< Timer output 2 reset DMA request enable */
+#define HRTIM_TIM_DMA_RST        HRTIM_TIMDIER_RSTDE       /*!< Timer reset DMA request enable */
+#define HRTIM_TIM_DMA_DLYPRT     HRTIM_TIMDIER_DLYPRTDE    /*!< Timer delay protection DMA request enable */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private Constants --------------------------------------------------------*/
+/** @addtogroup HRTIM_Private_Constants
+  * @{
+  */
+#define HRTIM_CAPTUREFTRIGGER_NONE         0x00000000U                  /*!< 32bit value Capture trigger is disabled */
+#define HRTIM_CAPTUREFTRIGGER_TF1_SET      (HRTIM_CPT1CR_TF1SET)        /*!< 32bit value Capture is triggered by TF1 output inactive to active transition */
+#define HRTIM_CAPTUREFTRIGGER_TF1_RESET    (HRTIM_CPT1CR_TF1RST)        /*!< 32bit value Capture is triggered by TF1 output active to inactive transition */
+#define HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1  (HRTIM_CPT1CR_TIMFCMP1)      /*!< 32bit value Timer F Compare 1 triggers Capture */
+#define HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2  (HRTIM_CPT1CR_TIMFCMP2)      /*!< 32bit value Timer F Compare 2 triggers Capture */
+/**
+  * @}
+ */
+
+/* Private macros --------------------------------------------------------*/
+/** @addtogroup HRTIM_Private_Macros
+  * @{
+  */
+#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
+  (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER)   || \
+   ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
+   ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
+   ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
+   ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
+   ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)  || \
+   ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F))
+
+#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
+  (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \
+   ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \
+   ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \
+   ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \
+   ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E)  || \
+   ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_F))
+
+#define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFF80FFFFU) == 0x00000000U)
+
+#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
+  (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1)  || \
+   ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2)  || \
+   ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3)  || \
+   ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
+
+#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
+  (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1)   || \
+   ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
+
+#define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFF000U) == 0x00000000U)
+
+#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
+  ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&   \
+    (((OUTPUT) == HRTIM_OUTPUT_TA1) ||          \
+     ((OUTPUT) == HRTIM_OUTPUT_TA2)))           \
+   ||                                           \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&    \
+    (((OUTPUT) == HRTIM_OUTPUT_TB1) ||          \
+     ((OUTPUT) == HRTIM_OUTPUT_TB2)))           \
+   ||                                           \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&    \
+    (((OUTPUT) == HRTIM_OUTPUT_TC1) ||          \
+     ((OUTPUT) == HRTIM_OUTPUT_TC2)))           \
+   ||                                           \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&    \
+    (((OUTPUT) == HRTIM_OUTPUT_TD1) ||          \
+     ((OUTPUT) == HRTIM_OUTPUT_TD2)))           \
+   ||                                           \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&    \
+    (((OUTPUT) == HRTIM_OUTPUT_TE1) ||          \
+     ((OUTPUT) == HRTIM_OUTPUT_TE2)))           \
+   ||                                           \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) &&    \
+    (((OUTPUT) == HRTIM_OUTPUT_TF1) ||          \
+     ((OUTPUT) == HRTIM_OUTPUT_TF2))))
+
+#define IS_HRTIM_TIMEEVENT(EVENT)\
+  (((EVENT) == HRTIM_EVENTCOUNTER_A)   || \
+   ((EVENT) == HRTIM_EVENTCOUNTER_B))
+
+#define IS_HRTIM_TIMEEVENT_RESETMODE(EVENT)\
+  (((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL)   || \
+   ((EVENT) == HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL))
+
+#define IS_HRTIM_TIMSYNCUPDATE(EVENT)\
+  (((EVENT) == HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL)   || \
+   ((EVENT) == HRTIM_TIMERESYNC_UPDATE_CONDITIONAL))
+
+#define IS_HRTIM_TIMEEVENT_COUNTER(COUNTER)\
+  ((((COUNTER) > (uint32_t)0x00U) && ((COUNTER) <= (uint32_t)0x3FU)) ||\
+   ((COUNTER) == (uint32_t)0x00U))
+
+#define IS_HRTIM_TIMEEVENT_SOURCE(SOURCE)\
+  (((SOURCE) >= (uint32_t)0x00U) && ((SOURCE) <= (uint32_t)0x9U))
+
+#define IS_HRTIM_EVENT(EVENT)\
+  (((EVENT) == HRTIM_EVENT_NONE)|| \
+   ((EVENT) == HRTIM_EVENT_1)   || \
+   ((EVENT) == HRTIM_EVENT_2)   || \
+   ((EVENT) == HRTIM_EVENT_3)   || \
+   ((EVENT) == HRTIM_EVENT_4)   || \
+   ((EVENT) == HRTIM_EVENT_5)   || \
+   ((EVENT) == HRTIM_EVENT_6)   || \
+   ((EVENT) == HRTIM_EVENT_7)   || \
+   ((EVENT) == HRTIM_EVENT_8)   || \
+   ((EVENT) == HRTIM_EVENT_9)   || \
+   ((EVENT) == HRTIM_EVENT_10))
+
+#define IS_HRTIM_FAULT(FAULT)\
+  (((FAULT) == HRTIM_FAULT_1)   || \
+   ((FAULT) == HRTIM_FAULT_2)   || \
+   ((FAULT) == HRTIM_FAULT_3)   || \
+   ((FAULT) == HRTIM_FAULT_4)   || \
+   ((FAULT) == HRTIM_FAULT_5)   || \
+   ((FAULT) == HRTIM_FAULT_6))
+
+#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
+  (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
+   ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
+   ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8)  || \
+   ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4)  || \
+   ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2)  || \
+   ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1)  || \
+   ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2)  || \
+   ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
+
+#define IS_HRTIM_MODE(MODE)\
+  (((MODE) == HRTIM_MODE_CONTINUOUS)  ||  \
+   ((MODE) == HRTIM_MODE_SINGLESHOT) || \
+   ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
+
+#define IS_HRTIM_MODE_ONEPULSE(MODE)\
+  (((MODE) == HRTIM_MODE_SINGLESHOT) || \
+   ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
+
+
+#define IS_HRTIM_HALFMODE(HALFMODE)\
+  (((HALFMODE) == HRTIM_HALFMODE_DISABLED)  ||  \
+   ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
+
+#define IS_HRTIM_INTERLEAVEDMODE(INTLVDMODE)\
+  (((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED)  ||  \
+   ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DUAL)   ||  \
+   ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED)   ||  \
+   ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_TRIPLE)   ||  \
+   ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_DISABLED)   ||  \
+   ((INTLVDMODE) == HRTIM_INTERLEAVED_MODE_QUAD))
+
+#define IS_HRTIM_SYNCSTART(SYNCSTART)\
+  (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED)  ||  \
+   ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
+
+#define IS_HRTIM_SYNCRESET(SYNCRESET)\
+  (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED)  ||  \
+   ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
+
+#define IS_HRTIM_DACSYNC(DACSYNC)\
+  (((DACSYNC) == HRTIM_DACSYNC_NONE)          ||  \
+   ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1)  ||  \
+   ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2)  ||  \
+   ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
+
+#define IS_HRTIM_PRELOAD(PRELOAD)\
+  (((PRELOAD) == HRTIM_PRELOAD_DISABLED)  ||  \
+   ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
+
+#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
+  (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
+   ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
+   ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
+
+#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
+  (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \
+   ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \
+   ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)  ||  \
+   ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1)           ||  \
+   ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2)           ||  \
+   ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3)           ||  \
+   ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE)    ||  \
+   ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE)    ||  \
+   ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
+
+#define IS_HRTIM_TIMERBURSTMODE(MODE)                               \
+  (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK)  || \
+   ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
+#define IS_HRTIM_TIMERUPDOWNMODE(MODE)                               \
+  (((MODE) == HRTIM_TIMERUPDOWNMODE_UP)  || \
+   ((MODE) == HRTIM_TIMERUPDOWNMODE_UPDOWN))
+
+#define IS_HRTIM_TIMERTRGHLFMODE(MODE)                               \
+  (((MODE) == HRTIM_TIMERTRIGHALF_DISABLED)  || \
+   ((MODE) == HRTIM_TIMERTRIGHALF_ENABLED))
+
+#define IS_HRTIM_TIMERGTCMP3(MODE)                               \
+  (((MODE) == HRTIM_TIMERGTCMP3_EQUAL)  || \
+   ((MODE) == HRTIM_TIMERGTCMP3_GREATER))
+
+#define IS_HRTIM_TIMERGTCMP1(MODE)                               \
+  (((MODE) == HRTIM_TIMERGTCMP1_EQUAL)  || \
+   ((MODE) == HRTIM_TIMERGTCMP1_GREATER))
+
+#define IS_HRTIM_DUALDAC_RESET(DUALCHANNELDAC)                               \
+  (((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_COUNTER)  || \
+   ((DUALCHANNELDAC) == HRTIM_TIMER_DCDR_OUT1SET))
+
+#define IS_HRTIM_DUALDAC_STEP(DUALCHANNELDAC)                               \
+  (((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_CMP2)  || \
+   ((DUALCHANNELDAC) == HRTIM_TIMER_DCDS_OUT1RST))
+
+#define IS_HRTIM_DUALDAC_ENABLE(DUALCHANNELDAC)                               \
+  (((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_DISABLED)  || \
+   ((DUALCHANNELDAC) == HRTIM_TIMER_DCDE_ENABLED ))
+
+#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION)                               \
+  (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED)  || \
+   ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
+
+#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
+  (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
+   ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
+#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFC0U) == 0x00000000U)
+
+#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
+  (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
+   ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
+
+#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
+  (((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
+   ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))
+
+#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
+  ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED)          || \
+    ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6)  || \
+    ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6)  || \
+    ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6)  || \
+    ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
+    ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
+    ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7))    \
+   ||                                                                           \
+   (((TIMPUSHPULLMODE) ==  HRTIM_TIMPUSHPULLMODE_ENABLED) &&                    \
+    (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)     || \
+     ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
+
+#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE06FFFFU) == 0x00000000U)
+
+#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x00000000U) == 0x00000000U)
+
+
+#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET)                       \
+  (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
+   ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
+
+#define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
+  (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                  || \
+   ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)    || \
+   ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)  || \
+   ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
+
+/* Auto delayed mode is only available for compare units 2 and 4U */
+#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE)     \
+  ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) &&                                 \
+    (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
+     ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
+     ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
+     ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))   \
+   ||                                                                         \
+   (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) &&                                 \
+    (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \
+     ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \
+     ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \
+     ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
+
+#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
+  (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
+   ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
+
+#define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU)
+
+#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
+  (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE)             || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC)           || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER)           || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1)          || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2)          || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3)          || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4)          || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER)        || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1)       || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2)       || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3)       || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4)       || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1) || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2) || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2) || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3) || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1) || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2) || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3) || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4) || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4) || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1)            || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2)            || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3)            || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4)            || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5)            || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6)            || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7)            || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8)            || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9)            || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10)           || \
+   ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
+
+#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
+  (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE)             || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC)           || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER)           || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1)          || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2)          || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3)          || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4)          || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER)        || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1)       || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2)       || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3)       || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4)       || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1) || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2) || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2) || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3) || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1) || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2) || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3) || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4) || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4) || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1)            || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2)            || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3)            || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4)            || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5)            || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6)            || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7)            || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8)            || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9)            || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10)           || \
+   ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
+
+#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
+  (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
+   ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
+
+#define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
+  (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
+   ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
+
+#define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
+  (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE)     || \
+   ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE)   || \
+   ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
+   ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
+
+#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
+  (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED)  || \
+   ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
+
+#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
+  (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR)  || \
+   ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
+
+#define IS_HRTIM_OUTPUTBALANCEDIDLE(OUTPUTBIAR)\
+  (((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_DISABLED)  || \
+   ((OUTPUTBIAR) == HRTIM_OUTPUTBIAR_ENABLED))
+
+#define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER)    \
+  (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE)          || \
+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE)         || \
+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1)          || \
+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2)          || \
+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3)          || \
+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4)          || \
+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5)          || \
+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6)          || \
+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7)          || \
+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8)          || \
+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9)          || \
+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10)            \
+   ||                                                           \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&                    \
+    (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
+   ||                                                          \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&                    \
+    (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
+   ||                                                          \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&                    \
+    (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
+   ||                                                          \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&                    \
+    (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \
+   ||                                                          \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&                    \
+    (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2)))  \
+   ||                                                          \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) &&                    \
+    (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
+     ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))))
+
+#define IS_HRTIM_TIMER_CAPTUREFTRIGGER(TIMER, CAPTUREFTRIGGER)    \
+  (  ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_NONE)        || \
+     ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_SET)     || \
+     ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TF1_RESET)   || \
+     ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP1) || \
+     ((CAPTUREFTRIGGER) == HRTIM_CAPTUREFTRIGGER_TIMERF_CMP2))
+
+#define IS_HRTIM_TIMEVENTFILTER(TIMER,TIMEVENTFILTER)\
+  (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_NONE)           || \
+   ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP1)   || \
+   ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP2)   || \
+   ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP3)   || \
+   ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKINGCMP4)   || \
+   ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP2)  || \
+   ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGCMP3)  || \
+   ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_WINDOWINGTIM)      \
+   ||                                                             \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&                     \
+    (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF1_TIMBCMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF2_TIMBCMP4)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF3_TIMBOUT2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF4_TIMCCMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF5_TIMCCMP4)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF6_TIMFCMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF7_TIMDCMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMAEEF8_TIMECMP2)))   \
+   ||                                                           \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&                     \
+    (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF1_TIMACMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF2_TIMACMP4)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF3_TIMAOUT2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF4_TIMCCMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF5_TIMCCMP2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF6_TIMFCMP2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF7_TIMDCMP2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMBEEF8_TIMECMP1)))   \
+   ||                                                           \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&                     \
+    (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF1_TIMACMP2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF2_TIMBCMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF3_TIMBCMP4)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF4_TIMFCMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF5_TIMDCMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF6_TIMDCMP4)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF7_TIMDOUT2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMCEEF8_TIMECMP4)))   \
+   ||                                                           \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&                     \
+    (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF1_TIMACMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF2_TIMBCMP2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF3_TIMCCMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF4_TIMCCMP2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF5_TIMCOUT2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF6_TIMECMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF7_TIMECMP4)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMDEEF8_TIMFCMP4)))   \
+   ||                                                           \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&                     \
+    (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF1_TIMACMP2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF2_TIMBCMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF3_TIMCCMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF4_TIMFCMP4)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF5_TIMFOUT2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF6_TIMDCMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF7_TIMDCMP4)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMEEEF8_TIMDOUT2)))   \
+   ||                                                           \
+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) &&                     \
+    (((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF1_TIMACMP4)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF2_TIMBCMP2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF3_TIMCCMP4)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF4_TIMDCMP2)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF5_TIMDCMP4)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF6_TIMECMP1)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF7_TIMECMP4)  || \
+     ((TIMEVENTFILTER) == HRTIM_TIMEEVFLT_BLANKING_TIMFEEF8_TIMEOUT2))))
+
+#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
+  (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
+   ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
+
+#define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
+  (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
+   ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
+   ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
+   ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
+   ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
+   ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
+   ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
+   ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
+
+#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
+  (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE)    || \
+   ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
+
+#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
+  (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE)    || \
+   ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
+
+#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
+  (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE)    || \
+   ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
+
+#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
+  (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE)    || \
+   ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
+
+#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
+  (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE)    || \
+   ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
+
+#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
+  (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE)    || \
+   ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
+
+#define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
+  (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16)    || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32)    || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48)    || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64)    || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80)    || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96)    || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112)   || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128)   || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144)   || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160)   || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176)   || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192)   || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208)   || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224)   || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240)   || \
+   ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
+
+#define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
+  (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0)    || \
+   ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125)  || \
+   ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250)  || \
+   ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375)  || \
+   ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500)  || \
+   ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625)  || \
+   ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750)  || \
+   ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
+
+#define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
+  (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16)   || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32)   || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48)   || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64)   || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80)   || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96)   || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112)  || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128)  || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144)  || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160)  || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176)  || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192)  || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208)  || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224)  || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240)  || \
+   ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
+
+#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
+  (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE)             || \
+   ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT)    || \
+   ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
+
+#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
+  (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START)  || \
+   ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1)   || \
+   ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START)    || \
+   ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
+
+#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
+  (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE)  || \
+   ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE)  || \
+   ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
+
+#define IS_HRTIM_EVENTSRC(EVENT, EVENTSRC)                      \
+  ((((EVENT) == HRTIM_EVENT_1) &&                             \
+    (((EVENTSRC) == HRTIM_EEV1SRC_GPIO      )   || \
+     ((EVENTSRC) == HRTIM_EEV1SRC_COMP2_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV1SRC_TIM1_TRGO )   || \
+     ((EVENTSRC) == HRTIM_EEV1SRC_ADC1_AWD1 )))    \
+   ||                                                          \
+   (((EVENT) == HRTIM_EVENT_2) &&                             \
+    (((EVENTSRC) == HRTIM_EEV2SRC_GPIO      )   || \
+     ((EVENTSRC) == HRTIM_EEV2SRC_COMP4_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV2SRC_TIM2_TRGO )   || \
+     ((EVENTSRC) == HRTIM_EEV2SRC_ADC1_AWD2 )))    \
+   ||                                                          \
+   (((EVENT) == HRTIM_EVENT_3) &&                             \
+    (((EVENTSRC) == HRTIM_EEV3SRC_GPIO      )   || \
+     ((EVENTSRC) == HRTIM_EEV3SRC_COMP6_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV3SRC_TIM3_TRGO )   || \
+     ((EVENTSRC) == HRTIM_EEV3SRC_ADC1_AWD3 )))    \
+   ||                                                          \
+   (((EVENT) == HRTIM_EVENT_4) &&                             \
+    (((EVENTSRC) == HRTIM_EEV4SRC_GPIO      )   || \
+     ((EVENTSRC) == HRTIM_EEV4SRC_COMP1_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV4SRC_COMP5_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV4SRC_ADC2_AWD1 )))    \
+   ||                                                          \
+   (((EVENT) == HRTIM_EVENT_5) &&                             \
+    (((EVENTSRC) == HRTIM_EEV5SRC_GPIO      )   || \
+     ((EVENTSRC) == HRTIM_EEV5SRC_COMP3_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV5SRC_COMP7_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV5SRC_ADC2_AWD2 )))    \
+   ||                                                          \
+   (((EVENT) == HRTIM_EVENT_6) &&                             \
+    (((EVENTSRC) == HRTIM_EEV6SRC_GPIO      )   || \
+     ((EVENTSRC) == HRTIM_EEV6SRC_COMP2_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV6SRC_COMP1_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV6SRC_ADC2_AWD3 )))    \
+   ||                                                          \
+   (((EVENT) == HRTIM_EVENT_7) &&                             \
+    (((EVENTSRC) == HRTIM_EEV7SRC_GPIO      )   || \
+     ((EVENTSRC) == HRTIM_EEV7SRC_COMP4_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV7SRC_TIM7_TRGO )   || \
+     ((EVENTSRC) == HRTIM_EEV7SRC_ADC3_AWD1 )))    \
+   ||                                                          \
+   (((EVENT) == HRTIM_EVENT_8) &&                             \
+    (((EVENTSRC) == HRTIM_EEV8SRC_GPIO      )   || \
+     ((EVENTSRC) == HRTIM_EEV8SRC_COMP6_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV8SRC_COMP3_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV8SRC_ADC4_AWD1 )))    \
+   ||                                                          \
+   (((EVENT) == HRTIM_EVENT_9) &&                             \
+    (((EVENTSRC) == HRTIM_EEV9SRC_GPIO      )   || \
+     ((EVENTSRC) == HRTIM_EEV9SRC_COMP5_OUT )   || \
+     ((EVENTSRC) == HRTIM_EEV9SRC_TIM15_TRGO)   || \
+     ((EVENTSRC) == HRTIM_EEV9SRC_COMP4_OUT )))    \
+   ||                                                          \
+   (((EVENT) == HRTIM_EVENT_10) &&                            \
+    (((EVENTSRC) == HRTIM_EEV10SRC_GPIO     )   || \
+     ((EVENTSRC) == HRTIM_EEV10SRC_COMP7_OUT)   || \
+     ((EVENTSRC) == HRTIM_EEV10SRC_TIM6_TRGO)   || \
+     ((EVENTSRC) == HRTIM_EEV10SRC_ADC5_AWD1))))
+
+#define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
+  ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)  &&      \
+    (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH)  ||           \
+     ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW)))              \
+   ||                                                            \
+   (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
+    ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
+    ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
+
+#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
+  (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)       || \
+   ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE)  || \
+   ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
+   ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
+
+#define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
+  (((((EVENT) == HRTIM_EVENT_1) ||                 \
+     ((EVENT) == HRTIM_EVENT_2) ||                 \
+     ((EVENT) == HRTIM_EVENT_3) ||                 \
+     ((EVENT) == HRTIM_EVENT_4) ||                 \
+     ((EVENT) == HRTIM_EVENT_5)) &&                \
+    (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
+     ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
+   ||                                               \
+   (((EVENT) == HRTIM_EVENT_6) ||                   \
+    ((EVENT) == HRTIM_EVENT_7) ||                   \
+    ((EVENT) == HRTIM_EVENT_8) ||                   \
+    ((EVENT) == HRTIM_EVENT_9) ||                   \
+    ((EVENT) == HRTIM_EVENT_10)))
+
+
+#define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
+  ((((EVENT) == HRTIM_EVENT_1) ||            \
+    ((EVENT) == HRTIM_EVENT_2) ||            \
+    ((EVENT) == HRTIM_EVENT_3) ||            \
+    ((EVENT) == HRTIM_EVENT_4) ||            \
+    ((EVENT) == HRTIM_EVENT_5))              \
+   ||                                        \
+   ((((EVENT) == HRTIM_EVENT_6) ||            \
+     ((EVENT) == HRTIM_EVENT_7) ||            \
+     ((EVENT) == HRTIM_EVENT_8) ||            \
+     ((EVENT) == HRTIM_EVENT_9) ||            \
+     ((EVENT) == HRTIM_EVENT_10)) &&          \
+    (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
+     ((FILTER) == HRTIM_EVENTFILTER_1)     || \
+     ((FILTER) == HRTIM_EVENTFILTER_2)     || \
+     ((FILTER) == HRTIM_EVENTFILTER_3)     || \
+     ((FILTER) == HRTIM_EVENTFILTER_4)     || \
+     ((FILTER) == HRTIM_EVENTFILTER_5)     || \
+     ((FILTER) == HRTIM_EVENTFILTER_6)     || \
+     ((FILTER) == HRTIM_EVENTFILTER_7)     || \
+     ((FILTER) == HRTIM_EVENTFILTER_8)     || \
+     ((FILTER) == HRTIM_EVENTFILTER_9)     || \
+     ((FILTER) == HRTIM_EVENTFILTER_10)    || \
+     ((FILTER) == HRTIM_EVENTFILTER_11)    || \
+     ((FILTER) == HRTIM_EVENTFILTER_12)    || \
+     ((FILTER) == HRTIM_EVENTFILTER_13)    || \
+     ((FILTER) == HRTIM_EVENTFILTER_14)    || \
+     ((FILTER) == HRTIM_EVENTFILTER_15))))
+
+#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
+  (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1)  || \
+   ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2)   || \
+   ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4)   || \
+   ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
+
+#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
+  (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
+   ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL) || \
+   ((FAULTSOURCE) == HRTIM_FAULTSOURCE_EEVINPUT))
+
+#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
+  (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
+   ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
+
+#define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
+  (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED)  || \
+   ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
+
+#define IS_HRTIM_FAULTBLANKNGMODE(FAULTBLANKINGMODE)\
+  (((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_RSTALIGNED) || \
+   ((FAULTBLANKINGMODE) == HRTIM_FAULTBLANKINGMODE_MOVING))
+
+#define IS_HRTIM_FAULTBLANKING(FAULTBLANKINGCTL)\
+  (((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_DISABLED)  || \
+   ((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKING_ENABLED))
+
+#define IS_HRTIM_FAULTCOUNTERRST(HRTIM_FAULTCOUNTERRST)\
+  (((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_UNCONDITIONAL) || \
+   ((HRTIM_FAULTCOUNTERRST) == HRTIM_FAULTCOUNTERRST_CONDITIONAL))
+
+#define IS_HRTIM_FAULTBLANKINGCTL(FAULTBLANKINGCTL)\
+  (((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_DISABLED)  || \
+   ((FAULTBLANKINGCTL) == HRTIM_FAULTBLANKINGCTL_ENABLED))
+
+#define IS_HRTIM_FAULTCOUNTER(FAULTCOUNTER)\
+  (((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_NONE) || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_1)    || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_2)    || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_3)    || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_4)    || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_5)    || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_6)    || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_7)    || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_8)    || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_9)    || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_10)   || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_11)   || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_12)   || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_13)   || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_14)   || \
+   ((FAULTCOUNTER) == HRTIM_FAULTCOUNTER_15))
+
+#define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
+  (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_1)    || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_2)    || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_3)    || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_4)    || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_5)    || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_6)    || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_7)    || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_8)    || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_9)    || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_10)   || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_11)   || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_12)   || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_13)   || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_14)   || \
+   ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
+
+#define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
+  (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
+   ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
+
+#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
+  (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1)  || \
+   ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2)   || \
+   ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4)   || \
+   ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
+
+#define IS_HRTIM_BURSTMODE(BURSTMODE)\
+  (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT)  || \
+   ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
+
+#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
+  (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER)      || \
+   ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A)     || \
+   ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B)     || \
+   ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C)     || \
+   ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D)     || \
+   ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E)     || \
+   ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_F)     || \
+   ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC)    || \
+   ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC)    || \
+   ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO)   || \
+   ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
+
+#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
+  (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1)     || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2)     || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4)     || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8)     || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16)    || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32)    || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64)    || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128)   || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256)   || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512)   || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024)  || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048)  || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096)  || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192)  || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
+   ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
+
+#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
+  (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED)  || \
+   ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
+
+#define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
+  (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE)               || \
+   ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET)       || \
+   ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION)  || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP1)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP2)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP3)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP4)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_RESET)      || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP1)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP2)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_RESET)      || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP1)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP2)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_RESET)      || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_CMP1)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERF_RESET)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_RESET)      || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERF_REPETITION) || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_CMP2)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERF_CMP1)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP1)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP2)       || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7)     || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8)     || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_7)           || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_8)           || \
+   ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
+
+#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
+  (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER)   || \
+   ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A)  || \
+   ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B)  || \
+   ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C)  || \
+   ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D)  || \
+   ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E)  || \
+   ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_F))
+
+#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
+  (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
+   ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_0)  || \
+   ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_1)  || \
+   ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_2)  || \
+   ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_3))
+
+#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA)                                            \
+  ((((TIMER) == HRTIM_TIMERINDEX_MASTER)  && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \
+   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
+   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
+   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
+   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
+   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)) \
+   || (((TIMER) == HRTIM_TIMERINDEX_TIMER_F) && (((BURSTDMA) & 0xFF800000U) == 0x00000000U)))
+
+#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
+  (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED)  || \
+   ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
+
+#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFF80U) == 0x00000000U)
+
+#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFF80FFU) == 0x00000000U)
+
+#define IS_HRTIM_TIMERSWAP(TIMERSWAP) (((TIMERSWAP) & 0xFFC0FFFFU) == 0x00000000U)
+
+#define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFF80U) == 0x00000000U)
+
+#define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
+
+
+#define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U)
+
+
+#define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
+
+#define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
+  * @{
+  */
+
+/**
+  * @brief  configures the actual direction of the counter to UP counting mode
+  * @param   __HANDLE__ : HRTIM handle.
+  * @param   __TIMER__  : Timer index
+  *                   This parameter can be a combination of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval none
+  */
+#define __HAL_HRTIM_COUNTER_MODE_UP(__HANDLE__, __TIMERS__)\
+  do {\
+    if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
+    {\
+      CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
+    {\
+      CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
+    {\
+      CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
+    {\
+      CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
+    {\
+      CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
+    {\
+      CLEAR_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
+    }\
+  } while(0U)
+
+/**
+  * @brief  configures the actual direction of the counter to UP-DOWN counting mode
+  * @param   __HANDLE__ : HRTIM handle.
+  * @param   __TIMER__  : Timer index
+  *                   This parameter can be a combination of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval none
+  */
+#define __HAL_HRTIM_COUNTER_MODE_UPDOWN(__HANDLE__, __TIMERS__)\
+  do {\
+    if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
+    {\
+      SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_A)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
+    {\
+      SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_B)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
+    {\
+      SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_C)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
+    {\
+      SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_D)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
+    {\
+      SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_E)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
+    {\
+      SET_BIT((__HANDLE__)->Instance->sTimerxRegs[(HRTIM_TIMERINDEX_TIMER_F)].TIMxCR2 , (HRTIM_TIMCR2_UDM)); \
+    }\
+  } while(0U)
+
+/**
+  * @brief  swap the output of the timer
+  *         HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
+  *         HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
+  * @param   __HANDLE__ : HRTIM handle.
+  * @param   __TIMER__  : Timer index
+  *                   This parameter can be a combination of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval none
+ */
+#define __HAL_HRTIM_TIMER_OUTPUT_SWAP(__HANDLE__, __TIMERS__)\
+  do {\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
+    {\
+      SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
+    {\
+      SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
+    {\
+      SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
+    {\
+      SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
+    {\
+      SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\
+    {\
+      SET_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \
+    }\
+  } while(0U)
+
+/**
+  * @brief  Un-swap the output of the timer
+  *         HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
+  *         HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
+  * @param   __HANDLE__ : HRTIM handle.
+  * @param   __TIMER__  : Timer index
+  *                   This parameter can be a combination of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval none
+
+  */
+#define __HAL_HRTIM_TIMER_OUTPUT_NOSWAP(__HANDLE__, __TIMERS__)\
+  do {\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
+    {\
+      CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPA)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
+    {\
+      CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPB)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
+    {\
+      CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPC)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
+    {\
+      CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPD)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
+    {\
+      CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPE)); \
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\
+    {\
+      CLEAR_BIT((__HANDLE__)->Instance->sCommonRegs.CR2 , (HRTIM_CR2_SWPF)); \
+    }\
+  } while(0U)
+
+/** @brief Reset HRTIM handle state
+  * @param  __HANDLE__ HRTIM handle.
+  * @retval None
+  */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__)                do{                                                       \
+                                                                      (__HANDLE__)->State             = HAL_HRTIM_STATE_RESET; \
+                                                                      (__HANDLE__)->MspInitCallback   = NULL;                  \
+                                                                      (__HANDLE__)->MspDeInitCallback = NULL;                 \
+                                                                    } while(0)
+#else
+#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
+#endif
+
+/** @brief  Enables or disables the timer counter(s)
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __TIMERS__ timers to enable/disable
+  *        This parameter can be any combinations of the following values:
+  *            @arg HRTIM_TIMERID_MASTER: Master timer identifier
+  *            @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
+  *            @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
+  *            @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
+  *            @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
+  *            @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
+  *            @arg HRTIM_TIMERID_TIMER_F: Timer F identifier
+  * @retval None
+  */
+#define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__)   ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
+
+/* The counter of a timing unit is disabled only if all the timer outputs */
+/* are disabled and no capture is configured                              */
+#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
+#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
+#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
+#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
+#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
+#define HRTIM_TFOEN_MASK (HRTIM_OENR_TF2OEN | HRTIM_OENR_TF1OEN)
+#define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
+  do {\
+    if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
+    {\
+      ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
+    {\
+      if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\
+      {\
+        ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
+      }\
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
+    {\
+      if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\
+      {\
+        ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
+      }\
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
+    {\
+      if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\
+      {\
+        ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
+      }\
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
+    {\
+      if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\
+      {\
+        ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
+      }\
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
+    {\
+      if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\
+      {\
+        ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
+      }\
+    }\
+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_F) == HRTIM_TIMERID_TIMER_F)\
+    {\
+      if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TFOEN_MASK) == (uint32_t)RESET)\
+      {\
+        ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_F);\
+      }\
+    }\
+  } while(0U)
+
+/** @brief  Enables the External Event counter
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __TIMERS__ timers to enable/disable
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier
+  * @param  Event external event Counter A or B for which timer event must be enabled
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_EVENTCOUNTER_A
+  *                    @arg HRTIM_EVENTCOUNTER_B
+  * @retval None
+  */
+#define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_ENABLE(__HANDLE__, __TIMER__, __EVENT__)\
+  do {\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
+      }\
+      if (((__EVENT__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACE;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCE;\
+      }\
+    }\
+  } while(0U)
+
+/** @brief  Disables the External Event counter
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __TIMERS__ timers to enable/disable
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier
+  * @param  Event external event A or B for which timer event must be disabled
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_EVENTCOUNTER_A
+  *                    @arg HRTIM_EVENTCOUNTER_B
+  * @retval None
+  */
+#define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_DISABLE(__HANDLE__, __TIMER__, __EVENT__)\
+  do {\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVACE;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) &= ~HRTIM_EEFR3_EEVBCE;\
+      }\
+    }\
+  } while(0U)
+
+/** @brief  Resets the External Event counter
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __TIMERS__ timers to enable/disable
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_TIMERINDEX_TIMER_A: Timer A identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_B: Timer B identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_C: Timer C identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_D: Timer D identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_E: Timer E identifier
+  *            @arg HRTIM_TIMERINDEX_TIMER_F: Timer F identifier
+  * @param  Event external event A or B for which timer event must be reset
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_EVENTCOUNTER_A
+  *                    @arg HRTIM_EVENTCOUNTER_B
+  * @retval None
+  */
+#define __HAL_HRTIM_EXTERNAL_EVENT_COUNTER_RESET(__HANDLE__, __TIMER__, __EVENT__)\
+  do {\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_A) == HRTIM_TIMERINDEX_TIMER_A)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_B) == HRTIM_TIMERINDEX_TIMER_B)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_C) == HRTIM_TIMERINDEX_TIMER_C)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_C].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_D) == HRTIM_TIMERINDEX_TIMER_D)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_D].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_E) == HRTIM_TIMERINDEX_TIMER_E)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_E].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
+      }\
+    }\
+    if (((__TIMER__) & HRTIM_TIMERINDEX_TIMER_F) == HRTIM_TIMERINDEX_TIMER_F)\
+    {\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_A) == HRTIM_EVENTCOUNTER_A)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVACRES;\
+      }\
+      if (((__EVENT__) & HRTIM_EVENTCOUNTER_B) == HRTIM_EVENTCOUNTER_B)\
+      {\
+        ((__HANDLE__)->Instance->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_F].EEFxR3) |= HRTIM_EEFR3_EEVBCRES;\
+      }\
+    }\
+  } while(0U)
+
+
+/** @brief  Enables or disables the specified HRTIM common interrupts.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
+  *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
+  *            @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
+  *            @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
+  *            @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
+  *            @arg HRTIM_IT_FLT6: Fault 6 interrupt enable
+  *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
+  *            @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
+  *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
+  * @retval None
+  */
+#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
+#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
+
+/** @brief  Enables or disables the specified HRTIM Master timer interrupts.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
+  *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
+  *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
+  *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
+  *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
+  *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
+  *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
+  * @retval None
+  */
+#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER \
+                                                                   |= (__INTERRUPT__))
+#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER \
+                                                                  &= ~(__INTERRUPT__))
+
+/** @brief  Enables or disables the specified HRTIM Timerx interrupts.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __TIMER__ specified the timing unit (Timer A to F)
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
+  *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
+  *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
+  *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
+  *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
+  *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
+  *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
+  *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
+  *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
+  *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
+  *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
+  *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
+  *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
+  *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
+  * @retval None
+  */
+#define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
+#define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
+
+/** @brief  Checks if the specified HRTIM common interrupt  source  is enabled or disabled.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to check.
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
+  *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
+  *            @arg HRTIM_IT_FLT3: Fault 3 enable
+  *            @arg HRTIM_IT_FLT4: Fault 4 enable
+  *            @arg HRTIM_IT_FLT5: Fault 5 enable
+  *            @arg HRTIM_IT_FLT6: Fault 6 enable
+  *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
+  *            @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
+  *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sCommonRegs.IER &\
+                                                                   (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks if the specified HRTIM Master interrupt source  is enabled or disabled.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __INTERRUPT__ specifies the interrupt source to check.
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
+  *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
+  *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
+  *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
+  *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
+  *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
+  *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sMasterRegs.MDIER &\
+                                                                          (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Checks if the specified HRTIM Timerx interrupt source  is enabled or disabled.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __TIMER__ specified the timing unit (Timer A to F)
+  * @param  __INTERRUPT__ specifies the interrupt source to check.
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
+  *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
+  *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
+  *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
+  *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
+  *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
+  *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
+  *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
+  *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
+  *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
+  *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
+  *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
+  *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
+  *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
+  *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
+  *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
+  *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
+  *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
+  *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
+  *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
+  *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
+  */
+#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &\
+    (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief  Clears the specified HRTIM common pending flag.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
+  *            @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
+  *            @arg HRTIM_IT_FLT3: Fault 3 clear flag
+  *            @arg HRTIM_IT_FLT4: Fault 4 clear flag
+  *            @arg HRTIM_IT_FLT5: Fault 5 clear flag
+  *            @arg HRTIM_IT_FLT6: Fault 6 clear flag
+  *            @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
+  *            @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
+  *            @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
+  * @retval None
+  */
+#define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
+
+/** @brief  Clears the specified HRTIM Master pending flag.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
+  *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
+  *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
+  *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
+  *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
+  *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
+  *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
+  * @retval None
+  */
+#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MICR\
+                                                                  = (__INTERRUPT__))
+
+/** @brief  Clears the specified HRTIM Timerx pending flag.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __TIMER__ specified the timing unit (Timer A to F)
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
+  *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
+  *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
+  *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
+  *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
+  *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
+  *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
+  *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
+  *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
+  *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
+  *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
+  *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
+  *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
+  *            @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
+  * @retval None
+  */
+#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\
+                                                                            = (__INTERRUPT__))
+
+/* DMA HANDLING */
+/** @brief  Enables or disables the specified HRTIM Master timer DMA requests.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __DMA__ specifies the DMA request to enable or disable.
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request enable
+  *            @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request enable
+  *            @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request enable
+  *            @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request enable
+  *            @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request enable
+  *            @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request enable
+  *            @arg HRTIM_MASTER_DMA_MUPD: Master update DMA request enable
+  * @retval None
+  */
+#define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
+#define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
+
+/** @brief  Enables or disables the specified HRTIM Timerx DMA requests.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
+  * @param  __TIMER__ specified the timing unit (Timer A to F)
+  * @param  __DMA__ specifies the DMA request to enable or disable.
+  *        This parameter can be one of the following values:
+  *            @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request enable
+  *            @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request enable
+  *            @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request enable
+  *            @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request enable
+  *            @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request enable
+  *            @arg HRTIM_TIM_DMA_UPD: Timer update DMA request enable
+  *            @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request enable
+  *            @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request enable
+  *            @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request enable
+  *            @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request enable
+  *            @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request enable
+  *            @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request enable
+  *            @arg HRTIM_TIM_DMA_RST: Timer reset DMA request enable
+  *            @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request enable
+  * @retval None
+  */
+#define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
+#define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
+
+#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sCommonRegs.ISR &\
+                                                            (__FLAG__)) == (__FLAG__))
+#define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
+
+#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sMasterRegs.MISR &\
+                                                                   (__FLAG__)) == (__FLAG__))
+#define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
+
+#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__,  __TIMER__, __FLAG__)        (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR &\
+                                                                              (__FLAG__)) == (__FLAG__))
+#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__,  __TIMER__, __FLAG__)      ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR\
+                                                                             = (__FLAG__))
+
+/** @brief  Sets the HRTIM timer Counter Register value on runtime
+  * @param  __HANDLE__ HRTIM Handle.
+  * @param  __TIMER__ HRTIM timer
+  *                   This parameter can be one of the following values:
+  *                   @arg 0x6 for master timer
+  *                   @arg 0x0 to 0x5 for timers A to F
+  * @param  __COUNTER__ specifies the Counter Register new value.
+  * @retval None
+  */
+#define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
+   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
+
+/** @brief  Gets the HRTIM timer Counter Register value on runtime
+  * @param  __HANDLE__ HRTIM Handle.
+  * @param  __TIMER__ HRTIM timer
+  *                   This parameter can be one of the following values:
+  *                   @arg 0x6 for master timer
+  *                   @arg 0x0 to 0x5 for timers A to F
+  * @retval HRTIM timer Counter Register value
+  */
+#define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
+   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
+
+/** @brief  Sets the HRTIM timer Period value on runtime
+  * @param  __HANDLE__ HRTIM Handle.
+  * @param  __TIMER__ HRTIM timer
+  *                   This parameter can be one of the following values:
+  *                   @arg 0x6 for master timer
+  *                   @arg 0x0 to 0x5 for timers A to F
+  * @param  __PERIOD__ specifies the Period Register new value.
+  * @retval None
+  */
+#define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
+   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
+
+/** @brief  Gets the HRTIM timer Period Register value on runtime
+  * @param  __HANDLE__ HRTIM Handle.
+  * @param  __TIMER__ HRTIM timer
+  *                   This parameter can be one of the following values:
+  *                   @arg 0x6 for master timer
+  *                   @arg 0x0 to 0x5 for timers A to F
+  * @retval timer Period Register
+  */
+#define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
+   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
+
+/** @brief  Sets the HRTIM timer clock prescaler value on runtime
+  * @param  __HANDLE__ HRTIM Handle.
+  * @param  __TIMER__ HRTIM timer
+  *                   This parameter can be one of the following values:
+  *                   @arg 0x6 for master timer
+  *                   @arg 0x0 to 0x5 for timers A to F
+  * @param  __PRESCALER__ specifies the clock prescaler new value.
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
+  *                   @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
+  *                   @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
+  *                   @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
+  *                   @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
+  *                   @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
+  *                   @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
+  *                   @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
+  * @retval None
+  */
+#define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\
+   (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))
+
+/** @brief  Gets the HRTIM timer clock prescaler value on runtime
+  * @param  __HANDLE__ HRTIM Handle.
+  * @param  __TIMER__ HRTIM timer
+  *                   This parameter can be one of the following values:
+  *                   @arg 0x6 for master timer
+  *                   @arg 0x0 to 0x5 for timers A to F
+  * @retval timer clock prescaler value
+  */
+#define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
+   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR  & HRTIM_TIMCR_CK_PSC))
+
+/** @brief  Sets the HRTIM timer Compare Register value on runtime
+  * @param  __HANDLE__ HRTIM Handle.
+  * @param  __TIMER__ HRTIM timer
+  *                   This parameter can be one of the following values:
+  *                   @arg 0x0 to 0x5 for timers A to F
+  * @param  __COMPAREUNIT__ timer compare unit
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+  *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+  *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+  *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+  * @param  __COMPARE__ specifies the Compare new value.
+  * @retval None
+  */
+#define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
+   (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
+    ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
+    ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
+    ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
+   : \
+   (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
+    ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
+    ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
+    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
+
+/** @brief  Gets the HRTIM timer Compare Register value on runtime
+  * @param  __HANDLE__ HRTIM Handle.
+  * @param  __TIMER__ HRTIM timer
+  *                   This parameter can be one of the following values:
+  *                   @arg 0x0 to 0x5 for timers A to F
+  * @param  __COMPAREUNIT__ timer compare unit
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+  *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+  *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+  *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+  * @retval Compare value
+  */
+#define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
+   (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
+    ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
+    ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
+    ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
+   : \
+   (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
+    ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
+    ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
+    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
+
+/**
+  * @brief  Enables the Fault Counter
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Fault fault input to enable
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_FAULT_1: Fault input 1
+  *                    @arg HRTIM_FAULT_2: Fault input 2
+  *                    @arg HRTIM_FAULT_3: Fault input 3
+  *                    @arg HRTIM_FAULT_4: Fault input 4
+  *                    @arg HRTIM_FAULT_5: Fault input 5
+  *                    @arg HRTIM_FAULT_6: Fault input 6
+  * @note This function must be called when fault is not enabled
+  * @retval HAL status
+  */
+#define __HAL_HRTIM_FAULT_BLANKING_ENABLE(__HANDLE__, __FAULT__)\
+  do {\
+    if (((__FAULT__) & HRTIM_FAULT_1) == HRTIM_FAULT_1)\
+    {\
+      ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT1BLKE;\
+    }\
+    if (((__FAULT__) & HRTIM_FAULT_2) == HRTIM_FAULT_2)\
+    {\
+      ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT2BLKE;\
+    }\
+    if (((__FAULT__) & HRTIM_FAULT_3) == HRTIM_FAULT_3)\
+    {\
+      ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT3BLKE;\
+    }\
+    if (((__FAULT__) & HRTIM_FAULT_4) == HRTIM_FAULT_4)\
+    {\
+      ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) |= HRTIM_FLTINR3_FLT4BLKE;\
+    }\
+    if (((__FAULT__) & HRTIM_FAULT_5) == HRTIM_FAULT_5)\
+    {\
+      ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT5BLKE;\
+    }\
+    if (((__FAULT__) & HRTIM_FAULT_6) == HRTIM_FAULT_6)\
+    {\
+      ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) |= HRTIM_FLTINR4_FLT6BLKE;\
+    }\
+  } while(0U)
+
+/**
+  * @brief  Disables the Fault Counter
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Fault fault input to disable
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_FAULT_1: Fault input 1
+  *                    @arg HRTIM_FAULT_2: Fault input 2
+  *                    @arg HRTIM_FAULT_3: Fault input 3
+  *                    @arg HRTIM_FAULT_4: Fault input 4
+  *                    @arg HRTIM_FAULT_5: Fault input 5
+  *                    @arg HRTIM_FAULT_6: Fault input 6
+  * @retval HAL status
+  */
+#define __HAL_HRTIM_FAULT_BLANKING_DISABLE(__HANDLE__, __FAULT__)\
+  do {\
+    if (((__FAULT__) & HRTIM_FAULT_1) == HRTIM_FAULT_1)\
+    {\
+      ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT1BLKE;\
+    }\
+    if (((__FAULT__) & HRTIM_FAULT_2) == HRTIM_FAULT_2)\
+    {\
+      ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT2BLKE;\
+    }\
+    if (((__FAULT__) & HRTIM_FAULT_3) == HRTIM_FAULT_3)\
+    {\
+      ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT3BLKE;\
+    }\
+    if (((__FAULT__) & HRTIM_FAULT_4) == HRTIM_FAULT_4)\
+    {\
+      ((__HANDLE__)->Instance->sCommonRegs.FLTINR3) &= ~HRTIM_FLTINR3_FLT4BLKE;\
+    }\
+    if (((__FAULT__) & HRTIM_FAULT_5) == HRTIM_FAULT_5)\
+    {\
+      ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT5BLKE;\
+    }\
+    if (((__FAULT__) & HRTIM_FAULT_6) == HRTIM_FAULT_6)\
+    {\
+      ((__HANDLE__)->Instance->sCommonRegs.FLTINR4) &= ~HRTIM_FLTINR4_FLT6BLKE;\
+    }\
+  } while(0U)
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup HRTIM_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup HRTIM_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and Configuration functions  ********************************/
+HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);
+
+HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim);
+
+void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);
+
+void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);
+
+HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx,
+                                           const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t CalibrationRate);
+
+HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t CalibrationRate);
+
+HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t Timeout);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HRTIM_Exported_Functions_Group2
+  * @{
+  */
+
+/* Simple time base related functions  *****************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t TimerIdx,
+                                                uint32_t SrcAddr,
+                                                uint32_t DestAddr,
+                                                uint32_t Length);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HRTIM_Exported_Functions_Group3
+  * @{
+  */
+/* Simple output compare related functions  ************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t OCChannel,
+                                                  const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
+                                          uint32_t TimerIdx,
+                                          uint32_t OCChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
+                                         uint32_t TimerIdx,
+                                         uint32_t OCChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             uint32_t OCChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx,
+                                            uint32_t OCChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx,
+                                              uint32_t OCChannel,
+                                              uint32_t SrcAddr,
+                                              uint32_t DestAddr,
+                                              uint32_t Length);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             uint32_t OCChannel);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HRTIM_Exported_Functions_Group4
+  * @{
+  */
+/* Simple PWM output related functions  ****************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t TimerIdx,
+                                                   uint32_t PWMChannel,
+                                                   const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx,
+                                           uint32_t PWMChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
+                                          uint32_t TimerIdx,
+                                          uint32_t PWMChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx,
+                                              uint32_t PWMChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             uint32_t PWMChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx,
+                                               uint32_t PWMChannel,
+                                               uint32_t SrcAddr,
+                                               uint32_t DestAddr,
+                                               uint32_t Length);
+
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx,
+                                              uint32_t PWMChannel);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HRTIM_Exported_Functions_Group5
+  * @{
+  */
+/* Simple capture related functions  *******************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                       uint32_t TimerIdx,
+                                                       uint32_t CaptureChannel,
+                                                       const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx,
+                                               uint32_t CaptureChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx,
+                                              uint32_t CaptureChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t CaptureChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t TimerIdx,
+                                                 uint32_t CaptureChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t TimerIdx,
+                                                   uint32_t CaptureChannel,
+                                                   uint32_t SrcAddr,
+                                                   uint32_t DestAddr,
+                                                   uint32_t Length);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t CaptureChannel);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HRTIM_Exported_Functions_Group6
+  * @{
+  */
+/* Simple one pulse related functions  *****************************************/
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                        uint32_t TimerIdx,
+                                                        uint32_t OnePulseChannel,
+                                                        const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t TimerIdx,
+                                                uint32_t OnePulseChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx,
+                                               uint32_t OnePulseChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t TimerIdx,
+                                                   uint32_t OnePulseChannel);
+
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t OnePulseChannel);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HRTIM_Exported_Functions_Group7
+  * @{
+  */
+HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
+                                            const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
+                                        uint32_t Event,
+                                        const HRTIM_EventCfgTypeDef *pEventCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t Prescaler);
+
+HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
+                                        uint32_t Fault,
+                                        const HRTIM_FaultCfgTypeDef *pFaultCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t Prescaler);
+
+HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef *hhrtim,
+                                                         uint32_t Fault,
+                                                         const HRTIM_FaultBlankingCfgTypeDef *pFaultBlkCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t Fault,
+                                               const HRTIM_FaultBlankingCfgTypeDef *pFaultBlkCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t Fault);
+
+HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t Timers);
+void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim,
+                            uint32_t Faults,
+                            uint32_t Enable);
+
+HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t ADCTrigger,
+                                             const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t ADCTrigger,
+                                                uint32_t Postscaler);
+
+HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx,
+                                               uint32_t RollOverCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t Timers);
+/**
+  * @}
+  */
+
+/** @addtogroup HRTIM_Exported_Functions_Group8
+  * @{
+  */
+/* Waveform related functions *************************************************/
+HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t TimerIdx,
+                                                const HRTIM_TimerCfgTypeDef *pTimerCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t TimerIdx,
+                                                 const HRTIM_TimerCtlTypeDef *pTimerCtl);
+
+HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                      uint32_t TimerIdx,
+                                                      const HRTIM_TimerCtlTypeDef *pTimerCtl);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t CompareUnit,
+                                                  const HRTIM_CompareCfgTypeDef *pCompareCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t CaptureUnit,
+                                                  const HRTIM_CaptureCfgTypeDef *pCaptureCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t TimerIdx,
+                                                 uint32_t Output,
+                                                 const HRTIM_OutputCfgTypeDef *pOutputCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t TimerIdx,
+                                                   uint32_t Output,
+                                                   uint32_t OutputLevel);
+
+HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                      uint32_t TimerIdx,
+                                                      uint32_t Event,
+                                                      const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t EventCounter,
+                                                  const HRTIM_ExternalEventCfgTypeDef *pTimerExternalEventCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t EventCounter);
+
+HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t TimerIdx,
+                                                   uint32_t EventCounter);
+
+HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t TimerIdx,
+                                                 uint32_t EventCounter);
+
+HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx,
+                                           const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx,
+                                              const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg);
+
+HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx,
+                                           uint32_t RegistersToUpdate);
+
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t OutputsToStart);
+
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t OutputsToStop);
+
+HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
+                                         uint32_t Enable);
+
+HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);
+
+HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx,
+                                            uint32_t CaptureUnit);
+
+HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
+                                          uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             uint32_t BurstBufferAddress,
+                                             uint32_t BurstBufferLength);
+
+HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
+                                         uint32_t Timers);
+
+HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
+                                          uint32_t Timers);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HRTIM_Exported_Functions_Group9
+  * @{
+  */
+/* HRTIM peripheral state functions */
+HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim);
+
+uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim,
+                                    uint32_t TimerIdx,
+                                    uint32_t CaptureUnit);
+
+uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef *hhrtim,
+                                  uint32_t TimerIdx,
+                                  uint32_t CaptureUnit);
+
+HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t TimerIdx,
+                                                uint32_t CaptureUnit);
+
+uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim,
+                                          uint32_t TimerIdx,
+                                          uint32_t Output);
+
+uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim,
+                                          uint32_t TimerIdx,
+                                          uint32_t Output);
+
+uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx,
+                                              uint32_t Output);
+
+uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim);
+
+uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx);
+
+uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
+                                         uint32_t TimerIdx);
+
+/**
+  * @}
+  */
+
+/** @addtogroup HRTIM_Exported_Functions_Group10
+  * @{
+  */
+/* IRQ handler */
+void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
+                          uint32_t TimerIdx);
+
+/* HRTIM events related callback functions */
+void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);
+void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);
+
+/* Timer events related callback functions */
+void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
+                                       uint32_t TimerIdx);
+void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                       uint32_t TimerIdx);
+void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                     uint32_t TimerIdx);
+void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                     uint32_t TimerIdx);
+void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                     uint32_t TimerIdx);
+void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                     uint32_t TimerIdx);
+void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                     uint32_t TimerIdx);
+void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                     uint32_t TimerIdx);
+void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
+                                         uint32_t TimerIdx);
+void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
+                                    uint32_t TimerIdx);
+void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
+                                  uint32_t TimerIdx);
+void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
+                                    uint32_t TimerIdx);
+void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
+                                  uint32_t TimerIdx);
+void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
+                                    uint32_t TimerIdx);
+void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
+                                        uint32_t TimerIdx);
+void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);
+
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef        *hhrtim,
+                                             HAL_HRTIM_CallbackIDTypeDef CallbackID,
+                                             pHRTIM_CallbackTypeDef      pCallback);
+
+HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef        *hhrtim,
+                                               HAL_HRTIM_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef         *hhrtim,
+                                                 HAL_HRTIM_CallbackIDTypeDef  CallbackID,
+                                                 pHRTIM_TIMxCallbackTypeDef   pCallback);
+
+HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef        *hhrtim,
+                                                   HAL_HRTIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HRTIM1 */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_HRTIM_H */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h
new file mode 100644
index 0000000..2f308b3
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart.h
@@ -0,0 +1,1745 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_uart.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_UART_H
+#define STM32G4xx_HAL_UART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UART_Exported_Types UART Exported Types
+  * @{
+  */
+
+/**
+  * @brief UART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t BaudRate;                /*!< This member configures the UART communication baud rate.
+                                         The baud rate register is computed using the following formula:
+                                         LPUART:
+                                         =======
+                                         Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))
+                                         where lpuart_ker_ck_pres is the UART input clock divided by a prescaler
+                                         UART:
+                                         =====
+                                         - If oversampling is 16 or in LIN mode,
+                                            Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))
+                                         - If oversampling is 8,
+                                            Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) /
+                                            ((huart->Init.BaudRate)))[15:4]
+                                            Baud Rate Register[3] =  0
+                                            Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) /
+                                            ((huart->Init.BaudRate)))[3:0]) >> 1
+                                         where uart_ker_ck_pres is the UART input clock divided by a prescaler */
+
+  uint32_t WordLength;              /*!< Specifies the number of data bits transmitted or received in a frame.
+                                         This parameter can be a value of @ref UARTEx_Word_Length. */
+
+  uint32_t StopBits;                /*!< Specifies the number of stop bits transmitted.
+                                         This parameter can be a value of @ref UART_Stop_Bits. */
+
+  uint32_t Parity;                  /*!< Specifies the parity mode.
+                                         This parameter can be a value of @ref UART_Parity
+                                         @note When parity is enabled, the computed parity is inserted
+                                               at the MSB position of the transmitted data (9th bit when
+                                               the word length is set to 9 data bits; 8th bit when the
+                                               word length is set to 8 data bits). */
+
+  uint32_t Mode;                    /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.
+                                         This parameter can be a value of @ref UART_Mode. */
+
+  uint32_t HwFlowCtl;               /*!< Specifies whether the hardware flow control mode is enabled
+                                         or disabled.
+                                         This parameter can be a value of @ref UART_Hardware_Flow_Control. */
+
+  uint32_t OverSampling;            /*!< Specifies whether the Over sampling 8 is enabled or disabled,
+                                         to achieve higher speed (up to f_PCLK/8).
+                                         This parameter can be a value of @ref UART_Over_Sampling. */
+
+  uint32_t OneBitSampling;          /*!< Specifies whether a single sample or three samples' majority vote is selected.
+                                         Selecting the single sample method increases the receiver tolerance to clock
+                                         deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */
+
+  uint32_t ClockPrescaler;          /*!< Specifies the prescaler value used to divide the UART clock source.
+                                         This parameter can be a value of @ref UART_ClockPrescaler. */
+
+} UART_InitTypeDef;
+
+/**
+  * @brief  UART Advanced Features initialization structure definition
+  */
+typedef struct
+{
+  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several
+                                       Advanced Features may be initialized at the same time .
+                                       This parameter can be a value of
+                                       @ref UART_Advanced_Features_Initialization_Type. */
+
+  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Tx_Inv. */
+
+  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.
+                                       This parameter can be a value of @ref UART_Rx_Inv. */
+
+  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic
+                                       vs negative/inverted logic).
+                                       This parameter can be a value of @ref UART_Data_Inv. */
+
+  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.
+                                       This parameter can be a value of @ref UART_Rx_Tx_Swap. */
+
+  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.
+                                       This parameter can be a value of @ref UART_Overrun_Disable. */
+
+  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.
+                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */
+
+  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.
+                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable. */
+
+  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate
+                                       detection is carried out.
+                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */
+
+  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.
+                                       This parameter can be a value of @ref UART_MSB_First. */
+} UART_AdvFeatureInitTypeDef;
+
+/**
+  * @brief HAL UART State definition
+  * @note  HAL UART State value is a combination of 2 different substates:
+  *        gState and RxState (see @ref UART_State_Definition).
+  *        - gState contains UART state information related to global Handle management
+  *          and also information related to Tx operations.
+  *          gState value coding follow below described bitmap :
+  *          b7-b6  Error information
+  *             00 : No Error
+  *             01 : (Not Used)
+  *             10 : Timeout
+  *             11 : Error
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized. HAL UART Init function already called)
+  *          b4-b3  (not used)
+  *             xx : Should be set to 00
+  *          b2     Intrinsic process state
+  *             0  : Ready
+  *             1  : Busy (Peripheral busy with some configuration or internal operations)
+  *          b1     (not used)
+  *             x  : Should be set to 0
+  *          b0     Tx state
+  *             0  : Ready (no Tx operation ongoing)
+  *             1  : Busy (Tx operation ongoing)
+  *        - RxState contains information related to Rx operations.
+  *          RxState value coding follow below described bitmap :
+  *          b7-b6  (not used)
+  *             xx : Should be set to 00
+  *          b5     Peripheral initialization status
+  *             0  : Reset (Peripheral not initialized)
+  *             1  : Init done (Peripheral initialized)
+  *          b4-b2  (not used)
+  *            xxx : Should be set to 000
+  *          b1     Rx state
+  *             0  : Ready (no Rx operation ongoing)
+  *             1  : Busy (Rx operation ongoing)
+  *          b0     (not used)
+  *             x  : Should be set to 0.
+  */
+typedef uint32_t HAL_UART_StateTypeDef;
+
+/**
+  * @brief UART clock sources definition
+  */
+typedef enum
+{
+  UART_CLOCKSOURCE_PCLK1      = 0x00U,    /*!< PCLK1 clock source  */
+  UART_CLOCKSOURCE_PCLK2      = 0x01U,    /*!< PCLK2 clock source  */
+  UART_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source    */
+  UART_CLOCKSOURCE_SYSCLK     = 0x04U,    /*!< SYSCLK clock source */
+  UART_CLOCKSOURCE_LSE        = 0x08U,    /*!< LSE clock source       */
+  UART_CLOCKSOURCE_UNDEFINED  = 0x10U     /*!< Undefined clock source */
+} UART_ClockSourceTypeDef;
+
+/**
+  * @brief HAL UART Reception type definition
+  * @note  HAL UART Reception type value aims to identify which type of Reception is ongoing.
+  *        This parameter can be a value of @ref UART_Reception_Type_Values :
+  *           HAL_UART_RECEPTION_STANDARD         = 0x00U,
+  *           HAL_UART_RECEPTION_TOIDLE           = 0x01U,
+  *           HAL_UART_RECEPTION_TORTO            = 0x02U,
+  *           HAL_UART_RECEPTION_TOCHARMATCH      = 0x03U,
+  */
+typedef uint32_t HAL_UART_RxTypeTypeDef;
+
+/**
+  * @brief HAL UART Rx Event type definition
+  * @note  HAL UART Rx Event type value aims to identify which type of Event has occurred
+  *        leading to call of the RxEvent callback.
+  *        This parameter can be a value of @ref UART_RxEvent_Type_Values :
+  *           HAL_UART_RXEVENT_TC                 = 0x00U,
+  *           HAL_UART_RXEVENT_HT                 = 0x01U,
+  *           HAL_UART_RXEVENT_IDLE               = 0x02U,
+  */
+typedef uint32_t HAL_UART_RxEventTypeTypeDef;
+
+/**
+  * @brief  UART handle Structure definition
+  */
+typedef struct __UART_HandleTypeDef
+{
+  USART_TypeDef            *Instance;                /*!< UART registers base address        */
+
+  UART_InitTypeDef         Init;                     /*!< UART communication parameters      */
+
+  UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */
+
+  const uint8_t            *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */
+
+  uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */
+
+  __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */
+
+  uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */
+
+  uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */
+
+  __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */
+
+  uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */
+
+  uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.
+                                                          This parameter can be a value of @ref UARTEx_FIFO_mode. */
+
+  uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */
+
+  uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */
+
+  __IO HAL_UART_RxTypeTypeDef ReceptionType;         /*!< Type of ongoing reception          */
+
+  __IO HAL_UART_RxEventTypeTypeDef RxEventType;      /*!< Type of Rx Event                   */
+
+  void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */
+
+  void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */
+
+  DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */
+
+  DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */
+
+  HAL_LockTypeDef           Lock;                    /*!< Locking object                     */
+
+  __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management
+                                                          and also related to Tx operations. This parameter
+                                                          can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations. This
+                                                          parameter can be a value of @ref HAL_UART_StateTypeDef */
+
+  __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */
+  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */
+  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */
+  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */
+  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */
+  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */
+  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */
+  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */
+  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */
+  void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */
+  void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */
+  void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback     */
+
+  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */
+  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */
+#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+} UART_HandleTypeDef;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL UART Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */
+  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */
+  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */
+  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */
+  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */
+  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */
+  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */
+  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */
+  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */
+  HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */
+  HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */
+
+  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */
+  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */
+
+} HAL_UART_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL UART Callback pointer definition
+  */
+typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */
+typedef  void (*pUART_RxEventCallbackTypeDef)
+(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UART_Exported_Constants UART Exported Constants
+  * @{
+  */
+
+/** @defgroup UART_State_Definition UART State Code Definition
+  * @{
+  */
+#define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized
+                                                          Value is allowed for gState and RxState */
+#define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use
+                                                          Value is allowed for gState and RxState */
+#define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing
+                                                          Value is allowed for RxState only */
+#define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing
+                                                          Not to be used for neither gState nor RxState.Value is result
+                                                          of combination (Or) between gState and RxState values */
+#define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state
+                                                          Value is allowed for gState only */
+#define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error
+                                                          Value is allowed for gState only */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Error_Definition   UART Error Definition
+  * @{
+  */
+#define  HAL_UART_ERROR_NONE             (0x00000000U)    /*!< No error                */
+#define  HAL_UART_ERROR_PE               (0x00000001U)    /*!< Parity error            */
+#define  HAL_UART_ERROR_NE               (0x00000002U)    /*!< Noise error             */
+#define  HAL_UART_ERROR_FE               (0x00000004U)    /*!< Frame error             */
+#define  HAL_UART_ERROR_ORE              (0x00000008U)    /*!< Overrun error           */
+#define  HAL_UART_ERROR_DMA              (0x00000010U)    /*!< DMA transfer error      */
+#define  HAL_UART_ERROR_RTO              (0x00000020U)    /*!< Receiver Timeout error  */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define  HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U)    /*!< Invalid Callback error  */
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
+  * @{
+  */
+#define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */
+#define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */
+#define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */
+#define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Parity  UART Parity
+  * @{
+  */
+#define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */
+#define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */
+#define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
+  * @{
+  */
+#define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */
+#define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */
+#define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */
+#define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mode UART Transfer Mode
+  * @{
+  */
+#define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */
+#define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */
+#define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */
+/**
+  * @}
+  */
+
+/** @defgroup UART_State  UART State
+  * @{
+  */
+#define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */
+#define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Over_Sampling UART Over Sampling
+  * @{
+  */
+#define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */
+#define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method
+  * @{
+  */
+#define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */
+#define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_ClockPrescaler  UART Clock Prescaler
+  * @{
+  */
+#define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */
+#define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */
+#define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */
+#define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */
+#define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */
+#define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */
+#define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */
+#define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */
+#define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */
+#define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */
+#define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */
+#define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection
+                                                                              on start bit              */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection
+                                                                              on falling edge           */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection
+                                                                              on 0x7F frame detection   */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection
+                                                                              on 0x55 frame detection   */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout
+  * @{
+  */
+#define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */
+#define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN    UART Local Interconnection Network mode
+  * @{
+  */
+#define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */
+#define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection
+  * @{
+  */
+#define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */
+#define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Tx    UART DMA Tx
+  * @{
+  */
+#define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */
+#define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Rx   UART DMA Rx
+  * @{
+  */
+#define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */
+#define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection
+  * @{
+  */
+#define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */
+#define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods
+  * @{
+  */
+#define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */
+#define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Request_Parameters UART Request Parameters
+  * @{
+  */
+#define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */
+#define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */
+#define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */
+#define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */
+#define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type
+  * @{
+  */
+#define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */
+#define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */
+#define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */
+#define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */
+#define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */
+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */
+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */
+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */
+#define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */
+#define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */
+#define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion
+  * @{
+  */
+#define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */
+#define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap
+  * @{
+  */
+#define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */
+#define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable
+  * @{
+  */
+#define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */
+#define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */
+/**
+  * @}
+  */
+
+/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable
+  * @{
+  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */
+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error
+  * @{
+  */
+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */
+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */
+/**
+  * @}
+  */
+
+/** @defgroup UART_MSB_First   UART Advanced Feature MSB First
+  * @{
+  */
+#define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received
+                                                                         first disable                      */
+#define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received
+                                                                         first enable                       */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */
+#define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable
+  * @{
+  */
+#define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */
+#define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register
+  * @{
+  */
+#define UART_CR2_ADDRESS_LSB_POS             24U             /*!< UART address-matching LSB position in CR2 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection
+  * @{
+  */
+#define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                     */
+#define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                   */
+#define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register
+                                                                         not empty or RXFIFO is not empty            */
+/**
+  * @}
+  */
+
+/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity
+  * @{
+  */
+#define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */
+#define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB
+                                                          position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register
+  * @{
+  */
+#define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB
+                                                          position in CR1 register */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask
+  * @{
+  */
+#define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */
+/**
+  * @}
+  */
+
+/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value
+  * @{
+  */
+#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Flags     UART Status Flags
+  *        Elements values convention: 0xXXXX
+  *           - 0xXXXX  : Flag mask in the ISR register
+  * @{
+  */
+#define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */
+#define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */
+#define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */
+#define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */
+#define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */
+#define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */
+#define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */
+#define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */
+#define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */
+#define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */
+#define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */
+#define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */
+#define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */
+#define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */
+#define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */
+#define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */
+#define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */
+#define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */
+#define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */
+#define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */
+#define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */
+#define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */
+#define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */
+#define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */
+#define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */
+#define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */
+#define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Interrupt_definition   UART Interrupts Definition
+  *        Elements values convention: 000ZZZZZ0XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *           - ZZZZZ  : Flag position in the ISR register(5bits)
+  *        Elements values convention: 000000000XXYYYYYb
+  *           - YYYYY  : Interrupt source position in the XX register (5bits)
+  *           - XX  : Interrupt source register (2bits)
+  *                 - 01: CR1 register
+  *                 - 10: CR2 register
+  *                 - 11: CR3 register
+  *        Elements values convention: 0000ZZZZ00000000b
+  *           - ZZZZ  : Flag position in the ISR register(4bits)
+  * @{
+  */
+#define UART_IT_PE                          0x0028U              /*!< UART parity error interruption                 */
+#define UART_IT_TXE                         0x0727U              /*!< UART transmit data register empty interruption */
+#define UART_IT_TXFNF                       0x0727U              /*!< UART TX FIFO not full interruption             */
+#define UART_IT_TC                          0x0626U              /*!< UART transmission complete interruption        */
+#define UART_IT_RXNE                        0x0525U              /*!< UART read data register not empty interruption */
+#define UART_IT_RXFNE                       0x0525U              /*!< UART RXFIFO not empty interruption             */
+#define UART_IT_IDLE                        0x0424U              /*!< UART idle interruption                         */
+#define UART_IT_LBD                         0x0846U              /*!< UART LIN break detection interruption          */
+#define UART_IT_CTS                         0x096AU              /*!< UART CTS interruption                          */
+#define UART_IT_CM                          0x112EU              /*!< UART character match interruption              */
+#define UART_IT_WUF                         0x1476U              /*!< UART wake-up from stop mode interruption       */
+#define UART_IT_RXFF                        0x183FU              /*!< UART RXFIFO full interruption                  */
+#define UART_IT_TXFE                        0x173EU              /*!< UART TXFIFO empty interruption                 */
+#define UART_IT_RXFT                        0x1A7CU              /*!< UART RXFIFO threshold reached interruption     */
+#define UART_IT_TXFT                        0x1B77U              /*!< UART TXFIFO threshold reached interruption     */
+#define UART_IT_RTO                         0x0B3AU              /*!< UART receiver timeout interruption             */
+
+#define UART_IT_ERR                         0x0060U              /*!< UART error interruption                        */
+
+#define UART_IT_ORE                         0x0300U              /*!< UART overrun error interruption                */
+#define UART_IT_NE                          0x0200U              /*!< UART noise error interruption                  */
+#define UART_IT_FE                          0x0100U              /*!< UART frame error interruption                  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags
+  * @{
+  */
+#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */
+#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */
+#define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */
+#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */
+#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */
+#define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */
+#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */
+#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */
+#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */
+#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */
+#define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */
+#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */
+/**
+  * @}
+  */
+
+/** @defgroup UART_Reception_Type_Values  UART Reception type values
+  * @{
+  */
+#define HAL_UART_RECEPTION_STANDARD          (0x00000000U)             /*!< Standard reception                       */
+#define HAL_UART_RECEPTION_TOIDLE            (0x00000001U)             /*!< Reception till completion or IDLE event  */
+#define HAL_UART_RECEPTION_TORTO             (0x00000002U)             /*!< Reception till completion or RTO event   */
+#define HAL_UART_RECEPTION_TOCHARMATCH       (0x00000003U)             /*!< Reception till completion or CM event    */
+/**
+  * @}
+  */
+
+/** @defgroup UART_RxEvent_Type_Values  UART RxEvent type values
+  * @{
+  */
+#define HAL_UART_RXEVENT_TC                  (0x00000000U)             /*!< RxEvent linked to Transfer Complete event */
+#define HAL_UART_RXEVENT_HT                  (0x00000001U)             /*!< RxEvent linked to Half Transfer event     */
+#define HAL_UART_RXEVENT_IDLE                (0x00000002U)             /*!< RxEvent linked to IDLE event              */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/** @defgroup UART_Exported_Macros UART Exported Macros
+  * @{
+  */
+
+/** @brief  Reset UART handle states.
+  * @param  __HANDLE__ UART handle.
+  * @retval None
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                       (__HANDLE__)->MspInitCallback = NULL;             \
+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \
+                                                     } while(0U)
+#else
+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \
+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \
+                                                     } while(0U)
+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */
+
+/** @brief  Flush the UART Data registers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \
+  do{                \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \
+    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \
+  }  while(0U)
+
+/** @brief  Clear the specified UART pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *          This parameter can be any combination of the following values:
+  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag
+  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag
+  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
+
+/** @brief  Clear the UART PE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)
+
+/** @brief  Clear the UART FE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)
+
+/** @brief  Clear the UART NE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)
+
+/** @brief  Clear the UART ORE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)
+
+/** @brief  Clear the UART IDLE pending flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)
+
+/** @brief  Clear the UART TX FIFO empty clear flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)
+
+/** @brief  Check whether the specified UART flag is set or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __FLAG__ specifies the flag to check.
+  *        This parameter can be one of the following values:
+  *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag
+  *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag
+  *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag
+  *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag
+  *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag
+  *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag
+  *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag
+  *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)
+  *            @arg @ref UART_FLAG_SBKF  Send Break flag
+  *            @arg @ref UART_FLAG_CMF   Character match flag
+  *            @arg @ref UART_FLAG_BUSY  Busy flag
+  *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag
+  *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag
+  *            @arg @ref UART_FLAG_CTS   CTS Change flag
+  *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag
+  *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag
+  *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag
+  *            @arg @ref UART_FLAG_TC    Transmission Complete flag
+  *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag
+  *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag
+  *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag
+  *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag
+  *            @arg @ref UART_FLAG_ORE   Overrun Error flag
+  *            @arg @ref UART_FLAG_NE    Noise Error flag
+  *            @arg @ref UART_FLAG_FE    Framing Error flag
+  *            @arg @ref UART_FLAG_PE    Parity Error flag
+  * @retval The new state of __FLAG__ (TRUE or FALSE).
+  */
+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
+
+/** @brief  Enable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (\
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
+                                                           ((__HANDLE__)->Instance->CR1 |= (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
+                                                           ((__HANDLE__)->Instance->CR2 |= (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 |= (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief  Disable the specified UART interrupt.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval None
+  */
+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (\
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\
+                                                           ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\
+                                                           ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))): \
+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\
+                                                               ((__INTERRUPT__) & UART_IT_MASK))))
+
+/** @brief  Check whether the specified UART interrupt has occurred or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\
+                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)
+
+/** @brief  Check whether the specified UART interrupt source is enabled or not.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __INTERRUPT__ specifies the UART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt
+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt
+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt
+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt
+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt
+  *            @arg @ref UART_IT_CM    Character match interrupt
+  *            @arg @ref UART_IT_CTS   CTS change interrupt
+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt
+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt
+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt
+  *            @arg @ref UART_IT_TC    Transmission complete interrupt
+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt
+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt
+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt
+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt
+  *            @arg @ref UART_IT_PE    Parity Error interrupt
+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)
+  * @retval The new state of __INTERRUPT__ (SET or RESET).
+  */
+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\
+                                                                (__HANDLE__)->Instance->CR1 : \
+                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\
+                                                                 (__HANDLE__)->Instance->CR2 : \
+                                                                 (__HANDLE__)->Instance->CR3)) & (1U <<\
+                                                                     (((uint16_t)(__INTERRUPT__)) &\
+                                                                      UART_IT_MASK)))  != RESET) ? SET : RESET)
+
+/** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
+  *                       to clear the corresponding interrupt
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag
+  *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag
+  *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag
+  *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag
+  *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag
+  *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag
+  *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag
+  *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag
+  *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag
+  *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag
+  *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag
+  *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag
+  * @retval None
+  */
+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
+
+/** @brief  Set a specific UART request flag.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __REQ__ specifies the request flag to set
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request
+  *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request
+  *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request
+  *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request
+  *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request
+  * @retval None
+  */
+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
+
+/** @brief  Enable the UART one bit sample method.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
+
+/** @brief  Disable the UART one bit sample method.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)
+
+/** @brief  Enable UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
+
+/** @brief  Disable UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
+
+/** @brief  Enable CTS flow control.
+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)               \
+  do{                                                             \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;               \
+  } while(0U)
+
+/** @brief  Disable CTS flow control.
+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)               \
+  do{                                                              \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);             \
+  } while(0U)
+
+/** @brief  Enable RTS flow control.
+  * @note   This macro allows to enable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)              \
+  do{                                                            \
+    ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \
+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;              \
+  } while(0U)
+
+/** @brief  Disable RTS flow control.
+  * @note   This macro allows to disable RTS hardware flow control for a given UART instance,
+  *         without need to call HAL_UART_Init() function.
+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.
+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need
+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :
+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )
+  *           - macro could only be called when corresponding UART instance is disabled
+  *             (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable
+  *              macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None
+  */
+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)              \
+  do{                                                             \
+    ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\
+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);            \
+  } while(0U)
+/**
+  * @}
+  */
+
+/* Private macros --------------------------------------------------------*/
+/** @defgroup UART_Private_Macros   UART Private Macros
+  * @{
+  */
+/** @brief  Get UART clock division factor from clock prescaler value.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval UART clock division factor
+  */
+#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \
+  (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \
+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U)
+
+/** @brief  BRR division operation to set BRR register with LPUART.
+  * @param  __PCLK__ LPUART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                        \
+  ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \
+               (uint32_t)((__BAUD__)/2U)) / (__BAUD__))                                \
+  )
+
+/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                        \
+  (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.
+  * @param  __PCLK__ UART clock.
+  * @param  __BAUD__ Baud rate set by the user.
+  * @param  __CLOCKPRESCALER__ UART prescaler value.
+  * @retval Division result
+  */
+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)                       \
+  ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__))
+
+/** @brief  Check whether or not UART instance is Low Power UART.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)
+  */
+#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))
+
+/** @brief  Check UART Baud rate.
+  * @param  __BAUDRATE__ Baudrate specified by the user.
+  *         The maximum Baud Rate is derived from the maximum clock on G4 (i.e. 150 MHz)
+  *         divided by the smallest oversampling used on the USART (i.e. 8)
+  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)
+  */
+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 18750001U)
+
+/** @brief  Check UART assertion time.
+  * @param  __TIME__ 5-bit value assertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)
+
+/** @brief  Check UART deassertion time.
+  * @param  __TIME__ 5-bit value deassertion time.
+  * @retval Test result (TRUE or FALSE).
+  */
+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)
+
+/**
+  * @brief Ensure that UART frame number of stop bits is valid.
+  * @param __STOPBITS__ UART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \
+                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \
+                                        ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that LPUART frame number of stop bits is valid.
+  * @param __STOPBITS__ LPUART frame number of stop bits.
+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)
+  */
+#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \
+                                          ((__STOPBITS__) == UART_STOPBITS_2))
+
+/**
+  * @brief Ensure that UART frame parity is valid.
+  * @param __PARITY__ UART frame parity.
+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
+  */
+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \
+                                    ((__PARITY__) == UART_PARITY_EVEN) || \
+                                    ((__PARITY__) == UART_PARITY_ODD))
+
+/**
+  * @brief Ensure that UART hardware flow control is valid.
+  * @param __CONTROL__ UART hardware flow control.
+  * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)
+  */
+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\
+  (((__CONTROL__) == UART_HWCONTROL_NONE) || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \
+   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))
+
+/**
+  * @brief Ensure that UART communication mode is valid.
+  * @param __MODE__ UART communication mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
+
+/**
+  * @brief Ensure that UART state is valid.
+  * @param __STATE__ UART state.
+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
+  */
+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \
+                                  ((__STATE__) == UART_STATE_ENABLE))
+
+/**
+  * @brief Ensure that UART oversampling is valid.
+  * @param __SAMPLING__ UART oversampling.
+  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)
+  */
+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \
+                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))
+
+/**
+  * @brief Ensure that UART frame sampling is valid.
+  * @param __ONEBIT__ UART frame sampling.
+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
+  */
+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \
+                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate detection mode is valid.
+  * @param __MODE__ UART auto Baud rate detection mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \
+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))
+
+/**
+  * @brief Ensure that UART receiver timeout setting is valid.
+  * @param __TIMEOUT__ UART receiver timeout setting.
+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)
+  */
+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \
+                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))
+
+/** @brief  Check the receiver timeout value.
+  * @note   The maximum UART receiver timeout value is 0xFFFFFF.
+  * @param  __TIMEOUTVALUE__ receiver timeout value.
+  * @retval Test result (TRUE or FALSE)
+  */
+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)
+
+/**
+  * @brief Ensure that UART LIN state is valid.
+  * @param __LIN__ UART LIN state.
+  * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)
+  */
+#define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \
+                                     ((__LIN__) == UART_LIN_ENABLE))
+
+/**
+  * @brief Ensure that UART LIN break detection length is valid.
+  * @param __LENGTH__ UART LIN break detection length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \
+                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))
+
+/**
+  * @brief Ensure that UART DMA TX state is valid.
+  * @param __DMATX__ UART DMA TX state.
+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
+  */
+#define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \
+                                       ((__DMATX__) == UART_DMA_TX_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA RX state is valid.
+  * @param __DMARX__ UART DMA RX state.
+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
+  */
+#define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \
+                                       ((__DMARX__) == UART_DMA_RX_ENABLE))
+
+/**
+  * @brief Ensure that UART half-duplex state is valid.
+  * @param __HDSEL__ UART half-duplex state.
+  * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)
+  */
+#define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \
+                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up method is valid.
+  * @param __WAKEUP__ UART wake-up method .
+  * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)
+  */
+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \
+                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))
+
+/**
+  * @brief Ensure that UART request parameter is valid.
+  * @param __PARAM__ UART request parameter.
+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
+  */
+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \
+                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \
+                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \
+                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \
+                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))
+
+/**
+  * @brief Ensure that UART advanced features initialization is valid.
+  * @param __INIT__ UART advanced features initialization.
+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \
+                                                            UART_ADVFEATURE_TXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_RXINVERT_INIT          | \
+                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \
+                                                            UART_ADVFEATURE_SWAP_INIT              | \
+                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \
+                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \
+                                                            UART_ADVFEATURE_MSBFIRST_INIT))
+
+/**
+  * @brief Ensure that UART frame TX inversion setting is valid.
+  * @param __TXINV__ UART frame TX inversion setting.
+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \
+                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX inversion setting is valid.
+  * @param __RXINV__ UART frame RX inversion setting.
+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \
+                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame data inversion setting is valid.
+  * @param __DATAINV__ UART frame data inversion setting.
+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \
+                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))
+
+/**
+  * @brief Ensure that UART frame RX/TX pins swap setting is valid.
+  * @param __SWAP__ UART frame RX/TX pins swap setting.
+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \
+                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))
+
+/**
+  * @brief Ensure that UART frame overrun setting is valid.
+  * @param __OVERRUN__ UART frame overrun setting.
+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)
+  */
+#define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \
+                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))
+
+/**
+  * @brief Ensure that UART auto Baud rate state is valid.
+  * @param __AUTOBAUDRATE__ UART auto Baud rate state.
+  * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \
+                                                            UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \
+                                                           ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))
+
+/**
+  * @brief Ensure that UART DMA enabling or disabling on error setting is valid.
+  * @param __DMA__ UART DMA enabling or disabling on error setting.
+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \
+                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))
+
+/**
+  * @brief Ensure that UART frame MSB first setting is valid.
+  * @param __MSBFIRST__ UART frame MSB first setting.
+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \
+                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))
+
+/**
+  * @brief Ensure that UART stop mode state is valid.
+  * @param __STOPMODE__ UART stop mode state.
+  * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)
+  */
+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \
+                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART mute mode state is valid.
+  * @param __MUTE__ UART mute mode state.
+  * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)
+  */
+#define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \
+                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))
+
+/**
+  * @brief Ensure that UART wake-up selection is valid.
+  * @param __WAKE__ UART wake-up selection.
+  * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)
+  */
+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \
+                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))
+
+/**
+  * @brief Ensure that UART driver enable polarity is valid.
+  * @param __POLARITY__ UART driver enable polarity.
+  * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)
+  */
+#define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \
+                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))
+
+/**
+  * @brief Ensure that UART Prescaler is valid.
+  * @param __CLOCKPRESCALER__ UART Prescaler value.
+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)
+  */
+#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \
+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))
+
+/**
+  * @}
+  */
+
+/* Include UART HAL Extended module */
+#include "stm32g4xx_hal_uart_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspInit(UART_HandleTypeDef *huart);
+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
+
+/* Callbacks Register/UnRegister functions  ***********************************/
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);
+
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions
+  * @{
+  */
+
+/* IO operation functions *****************************************************/
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
+/* Transfer Abort functions */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);
+
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);
+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
+  * @{
+  */
+
+/* Peripheral Control functions  ************************************************/
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  * @{
+  */
+
+/* Peripheral State and Errors functions  **************************************************/
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart);
+uint32_t              HAL_UART_GetError(const UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions -----------------------------------------------------------*/
+/** @addtogroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void              UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout);
+void              UART_AdvFeatureConfig(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+/**
+  * @}
+  */
+
+/* Private variables -----------------------------------------------------------*/
+/** @defgroup UART_Private_variables UART Private variables
+  * @{
+  */
+/* Prescaler Table used in BRR computation macros.
+   Declared as extern here to allow use of private UART macros, outside of HAL UART functions */
+extern const uint16_t UARTPrescTable[12];
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_UART_H */
+
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
new file mode 100644
index 0000000..0c56e27
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_hal_uart_ex.h
@@ -0,0 +1,929 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_uart_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of UART HAL Extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_HAL_UART_EX_H
+#define STM32G4xx_HAL_UART_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal_def.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup UARTEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types
+  * @{
+  */
+
+/**
+  * @brief  UART wake up from stop mode parameters
+  */
+typedef struct
+{
+  uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).
+                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.
+                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must
+                                    be filled up. */
+
+  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.
+                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */
+
+  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */
+} UART_WakeUpTypeDef;
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants
+  * @{
+  */
+
+/** @defgroup UARTEx_Word_Length UARTEx Word Length
+  * @{
+  */
+#define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */
+#define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */
+#define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length
+  * @{
+  */
+#define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */
+#define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode
+  * @brief    UART FIFO mode
+  * @{
+  */
+#define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */
+#define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level
+  * @brief    UART TXFIFO threshold level
+  * @{
+  */
+#define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TX FIFO reaches 1/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TX FIFO reaches 1/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TX FIFO reaches 1/2 of its depth */
+#define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */
+#define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TX FIFO reaches 7/8 of its depth */
+#define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty            */
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level
+  * @brief    UART RXFIFO threshold level
+  * @{
+  */
+#define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RX FIFO reaches 1/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RX FIFO reaches 1/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RX FIFO reaches 1/2 of its depth */
+#define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */
+#define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RX FIFO reaches 7/8 of its depth */
+#define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full             */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup UARTEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group1
+  * @{
+  */
+
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group2
+  * @{
+  */
+
+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);
+
+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);
+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Exported_Functions_Group3
+  * @{
+  */
+
+/* Peripheral Control functions  **********************************************/
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);
+
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);
+
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);
+
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+                                           uint32_t Timeout);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
+
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros
+  * @{
+  */
+
+/** @brief  Report the UART clock source.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @param  __CLOCKSOURCE__ output variable.
+  * @retval UART clocking source, written in __CLOCKSOURCE__.
+  */
+#if defined(UART5) && defined(USART3)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART5)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \
+      {                                                       \
+        case RCC_UART5CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#elif defined(UART5) && !defined(USART3)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART5)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \
+      {                                                       \
+        case RCC_UART5CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART5CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#elif defined(UART4) && defined(USART3)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#elif defined(UART4) && !defined(USART3)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == UART4)                  \
+    {                                                         \
+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \
+      {                                                       \
+        case RCC_UART4CLKSOURCE_PCLK1:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_HSI:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_SYSCLK:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_UART4CLKSOURCE_LSE:                          \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#elif defined(USART3)
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART3)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \
+      {                                                       \
+        case RCC_USART3CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART3CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#else
+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \
+  do {                                                        \
+    if((__HANDLE__)->Instance == USART1)                      \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \
+      {                                                       \
+        case RCC_USART1CLKSOURCE_PCLK2:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK2;         \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART1CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == USART2)                 \
+    {                                                         \
+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \
+      {                                                       \
+        case RCC_USART2CLKSOURCE_PCLK1:                       \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_HSI:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_SYSCLK:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_USART2CLKSOURCE_LSE:                         \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else if((__HANDLE__)->Instance == LPUART1)                \
+    {                                                         \
+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \
+      {                                                       \
+        case RCC_LPUART1CLKSOURCE_PCLK1:                      \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PCLK1;         \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_HSI:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_SYSCLK:                     \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_SYSCLK;        \
+          break;                                              \
+        case RCC_LPUART1CLKSOURCE_LSE:                        \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \
+          break;                                              \
+        default:                                              \
+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \
+          break;                                              \
+      }                                                       \
+    }                                                         \
+    else                                                      \
+    {                                                         \
+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \
+    }                                                         \
+  } while(0U)
+#endif /* UART5 && !USART3 */
+
+/** @brief  Report the UART mask to apply to retrieve the received data
+  *         according to the word length and to the parity bits activation.
+  * @note   If PCE = 1, the parity bit is not included in the data extracted
+  *         by the reception API().
+  *         This masking operation is not carried out in the case of
+  *         DMA transfers.
+  * @param  __HANDLE__ specifies the UART Handle.
+  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.
+  */
+#define UART_MASK_COMPUTATION(__HANDLE__)                             \
+  do {                                                                \
+    if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x01FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x00FFU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \
+    {                                                                 \
+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x007FU ;                                \
+      }                                                               \
+      else                                                            \
+      {                                                               \
+        (__HANDLE__)->Mask = 0x003FU ;                                \
+      }                                                               \
+    }                                                                 \
+    else                                                              \
+    {                                                                 \
+      (__HANDLE__)->Mask = 0x0000U;                                   \
+    }                                                                 \
+  } while(0U)
+
+/**
+  * @brief Ensure that UART frame length is valid.
+  * @param __LENGTH__ UART frame length.
+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
+  */
+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \
+                                         ((__LENGTH__) == UART_WORDLENGTH_9B))
+
+/**
+  * @brief Ensure that UART wake-up address length is valid.
+  * @param __ADDRESS__ UART wake-up address length.
+  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)
+  */
+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \
+                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))
+
+/**
+  * @brief Ensure that UART TXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART TXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))
+
+/**
+  * @brief Ensure that UART RXFIFO threshold level is valid.
+  * @param __THRESHOLD__ UART RXFIFO threshold level.
+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)
+  */
+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \
+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_HAL_UART_EX_H */
+
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h
new file mode 100644
index 0000000..72c7104
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_adc.h
@@ -0,0 +1,9204 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_ADC_H
+#define STM32G4xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
+
+/** @defgroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Internal mask for ADC group regular sequencer:                             */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
+/* - sequencer register offset                                                */
+/* - sequencer rank bits position into the selected register                  */
+
+/* Internal register offset for ADC group regular sequencer configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SQR1_REGOFFSET                 (0x00000000UL)
+#define ADC_SQR2_REGOFFSET                 (0x00000100UL)
+#define ADC_SQR3_REGOFFSET                 (0x00000200UL)
+#define ADC_SQR4_REGOFFSET                 (0x00000300UL)
+
+#define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET \
+                                            | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)
+#define ADC_SQRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK*/
+#define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted  */
+/* into ADC group regular sequencer ranks literals definition.                */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ1_Pos)
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ2_Pos)
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ3_Pos)
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (ADC_SQR1_SQ4_Pos)
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ5_Pos)
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ6_Pos)
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ7_Pos)
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ8_Pos)
+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (ADC_SQR2_SQ9_Pos)
+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS (ADC_SQR3_SQ10_Pos)
+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS (ADC_SQR3_SQ11_Pos)
+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (ADC_SQR3_SQ12_Pos)
+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (ADC_SQR3_SQ13_Pos)
+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (ADC_SQR3_SQ14_Pos)
+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS (ADC_SQR4_SQ15_Pos)
+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS (ADC_SQR4_SQ16_Pos)
+
+
+
+/* Internal mask for ADC group injected sequencer:                            */
+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */
+/* - data register offset                                                     */
+/* - sequencer rank bits position into the selected register                  */
+
+/* Internal register offset for ADC group injected data register */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_JDR1_REGOFFSET                 (0x00000000UL)
+#define ADC_JDR2_REGOFFSET                 (0x00000100UL)
+#define ADC_JDR3_REGOFFSET                 (0x00000200UL)
+#define ADC_JDR4_REGOFFSET                 (0x00000300UL)
+
+#define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET \
+                                            | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)
+#define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+#define ADC_JDRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK*/
+
+/* Definition of ADC group injected sequencer bits information to be inserted */
+/* into ADC group injected sequencer ranks literals definition.               */
+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ1_Pos)
+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ2_Pos)
+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ3_Pos)
+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ4_Pos)
+
+
+
+/* Internal mask for ADC group regular trigger:                               */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
+/* - regular trigger source                                                   */
+/* - regular trigger edge                                                     */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT      (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for
+                                                                 compatibility with some ADC on other STM32 series
+                                                                 having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible                  */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_SOURCE_MASK           (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \
+                                            ((ADC_CFGR_EXTSEL)                            << (4U * 1UL)) | \
+                                            ((ADC_CFGR_EXTSEL)                            << (4U * 2UL)) | \
+                                            ((ADC_CFGR_EXTSEL)                            << (4U * 3UL))  )
+
+/* Mask containing trigger edge masks for each of possible                    */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_EDGE_MASK             (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \
+                                            ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1UL)) | \
+                                            ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2UL)) | \
+                                            ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3UL))  )
+
+/* Definition of ADC group regular trigger bits information.                  */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  (ADC_CFGR_EXTSEL_Pos)
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (ADC_CFGR_EXTEN_Pos)
+
+
+
+/* Internal mask for ADC group injected trigger:                              */
+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */
+/* - injected trigger source                                                  */
+/* - injected trigger edge                                                    */
+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for
+                                                                  compatibility with some ADC on other STM32 series
+                                                                  having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible                  */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_INJ_TRIG_SOURCE_MASK           (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \
+                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \
+                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \
+                                            ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )
+
+/* Mask containing trigger edge masks for each of possible                    */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_INJ_TRIG_EDGE_MASK             (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \
+                                            ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
+                                            ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
+                                            ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
+
+/* Definition of ADC group injected trigger bits information.                 */
+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  (ADC_JSQR_JEXTSEL_Pos)
+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   (ADC_JSQR_JEXTEN_Pos)
+
+
+
+
+
+
+/* Internal mask for ADC channel:                                             */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
+/* - channel identifier defined by number                                     */
+/* - channel identifier defined by bitfield                                   */
+/* - channel differentiation between external channels (connected to          */
+/*   GPIO pins) and internal channels (connected to internal paths)           */
+/* - channel sampling time defined by SMPRx register offset                   */
+/*   and SMPx bits positions into SMPRx register                              */
+#define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)
+#define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (ADC_CFGR_AWD1CH_Pos)
+#define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK \
+                                            | ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
+  >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_2       (0x00080000UL) /* Marker of internal channel for other ADC instances, in case
+                                                             of different ADC internal channels mapped on same channel
+                                                             number on different ADC instances */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_ID_INTERNAL_CH_2)
+
+/* Internal register offset for ADC channel sampling time configuration */
+/* (offset placed into a spare area of literal definition) */
+#define ADC_SMPR1_REGOFFSET                (0x00000000UL)
+#define ADC_SMPR2_REGOFFSET                (0x02000000UL)
+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)
+#define ADC_SMPRX_REGOFFSET_POS            (25UL)           /* Position of bits ADC_SMPRx_REGOFFSET
+                                                               in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */
+
+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000UL)
+#define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK"
+                                                               position in register */
+
+/* Definition of channels ID number information to be inserted into           */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_NUMBER               (0x00000000UL)
+#define ADC_CHANNEL_1_NUMBER               (ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER               (ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_3_NUMBER               (ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER               (ADC_CFGR_AWD1CH_2)
+#define ADC_CHANNEL_5_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_7_NUMBER               (ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER               (ADC_CFGR_AWD1CH_3)
+#define ADC_CHANNEL_9_NUMBER               (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_11_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2)
+#define ADC_CHANNEL_13_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1)
+#define ADC_CHANNEL_15_NUMBER              (ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | \
+                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4)
+#define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4 | ADC_CFGR_AWD1CH_1)
+
+/* Definition of channels ID bitfield information to be inserted into         */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)
+#define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)
+#define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)
+#define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)
+#define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)
+#define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)
+#define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)
+#define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)
+#define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)
+#define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)
+#define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)
+#define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)
+#define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)
+#define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)
+#define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)
+#define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)
+#define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)
+#define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)
+#define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)
+
+/* Definition of channels sampling time information to be inserted into       */
+/* channels literals definition.                                              */
+/* Value shifted are equivalent to bitfield "ADC_SMPRx_SMPy" position         */
+/* in register.                                                               */
+#define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+#define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS))
+
+
+/* Internal mask for ADC mode single or differential ended:                   */
+/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */
+/* the relevant bits for:                                                     */
+/* (concatenation of multiple bits used in different registers)               */
+/* - ADC calibration: calibration start, calibration factor get or set        */
+/* - ADC channels: set each ADC channel ending mode                           */
+#define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)
+#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)
+#define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */
+#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen
+                                           to perform of shift when single mode is selected, shift value out of
+                                           channels bits range. */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000UL) /* Selection of 1 bit to discriminate differential mode:
+                                           mask of bit */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16UL)         /* Selection of 1 bit to discriminate differential mode:
+                                           position of bit */
+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit
+                                           ADC_SINGLEDIFF_CALIB_F_BIT_D to perform a shift of 4 ranks */
+
+/* Internal mask for ADC analog watchdog:                                     */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
+/* (concatenation of multiple bits used in different analog watchdogs,        */
+/* (feature of several watchdogs not available on all STM32 series)).         */
+/* - analog watchdog 1: monitored channel defined by number,                  */
+/*   selection of ADC group (ADC groups regular and-or injected).             */
+/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
+/*   selection on groups.                                                     */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)
+#define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)
+#define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)
+
+/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
+/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
+#define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
+#define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
+
+#define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
+#define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+
+#define ADC_AWD_CRX_REGOFFSET_POS          (20UL)                      /* Position of bits ADC_AWD_CRx_REGOFFSET
+                                                                          in ADC_AWD_CRX_REGOFFSET_MASK */
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
+#define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
+#define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)      /* Position of bits ADC_SQRx_REGOFFSET
+                                                                               in ADC_AWD_TRX_REGOFFSET_MASK */
+#define ADC_AWD_TRX_BIT_HIGH_MASK          (0x00010000UL)                   /* Selection of 1 bit to discriminate
+                                                                               threshold high: mask of bit */
+#define ADC_AWD_TRX_BIT_HIGH_POS           (16UL)                           /* Selection of 1 bit to discriminate
+                                                                               threshold high: position of bit */
+#define ADC_AWD_TRX_BIT_HIGH_SHIFT4        (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
+                                                                               position to perform a shift of 4 ranks */
+
+/* Internal mask for ADC offset:                                              */
+/* Internal register offset for ADC offset instance configuration */
+#define ADC_OFR1_REGOFFSET                 (0x00000000UL)
+#define ADC_OFR2_REGOFFSET                 (0x00000001UL)
+#define ADC_OFR3_REGOFFSET                 (0x00000002UL)
+#define ADC_OFR4_REGOFFSET                 (0x00000003UL)
+#define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET \
+                                            | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)
+
+
+/* ADC registers bits positions */
+#define ADC_CFGR_RES_BITOFFSET_POS         (ADC_CFGR_RES_Pos)
+#define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (ADC_CFGR_AWD1SGL_Pos)
+#define ADC_CFGR_AWD1EN_BITOFFSET_POS      (ADC_CFGR_AWD1EN_Pos)
+#define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (ADC_CFGR_JAWD1EN_Pos)
+#define ADC_TR1_HT1_BITOFFSET_POS          (ADC_TR1_HT1_Pos)
+
+
+/* ADC registers bits groups */
+#define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \
+                                            | ADC_CR_JADSTART | ADC_CR_JADSTP \
+                                            | ADC_CR_ADSTART | ADC_CR_ADSTP)            /* ADC register CR bits with
+                                           HW property "rs": Software can read as well as set this bit.
+                                           Writing '0' has no effect on the bit value. */
+
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of
+                                           parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
+                                           (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF                   (3000UL)                     /* Analog voltage reference (Vref+) value
+                                           with which VrefInt has been calibrated in production
+                                           (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32G4,
+                                           temperature sensor ADC raw data acquired at temperature  30 DegC
+                                           (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FFF75CAUL)) /* Address of parameter TS_CAL2: On STM32G4,
+                                           temperature sensor ADC raw data acquired at temperature 110 DegC
+                                           (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Temperature at which temperature sensor
+                                           has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR
+                                           (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL2_TEMP               (110L)                       /* Temperature at which temperature sensor
+                                           has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR
+                                           (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG          (3000UL)                     /* Analog voltage reference (Vref+) value
+                                           with which temperature sensor has been calibrated in production
+                                           (tolerance +-10 mV) (unit: mV). */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Driver macro reserved for internal use: set a pointer to
+  *         a register from a register basis from which an offset
+  *         is applied.
+  * @param  __REG__ Register basis from which the offset is applied.
+  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+  * @retval Pointer to register address
+  */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
+  ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of ADC common parameters
+  *         and multimode
+  *         (all ADC instances belonging to the same ADC common instance).
+  * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
+  *         is conditioned to ADC instances state (all ADC instances
+  *         sharing the same ADC common instance):
+  *         All ADC instances sharing the same ADC common instance must be
+  *         disabled.
+  */
+typedef struct
+{
+  uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
+                                             This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
+                                             @note On this STM32 series, if ADC group injected is used, some clock ratio
+                                                   constraints between ADC clock and AHB clock must be respected.
+                                                   Refer to reference manual.
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetCommonClock(). */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode
+                                             (for devices with several ADC instances).
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetMultimode(). */
+
+  uint32_t MultiDMATransfer;            /*!< Set ADC multimode conversion data transfer: no transfer or transfer by DMA.
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetMultiDMATransfer(). */
+
+  uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.
+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetMultiTwoSamplingDelay(). */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Affects both group regular and group injected (availability
+  *         of ADC group injected depends on STM32 series).
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 series. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t Resolution;                  /*!< Set ADC resolution.
+                                             This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetResolution(). */
+
+  uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
+                                             This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetDataAlignment(). */
+
+  uint32_t LowPowerMode;                /*!< Set ADC low power mode.
+                                             This parameter can be a value of @ref ADC_LL_EC_LP_MODE
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetLowPowerMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 series. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or
+                                             from external peripheral (timer event, external interrupt line).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+                                             @note On this STM32 series, setting trigger source to external trigger also
+                                                   set trigger polarity to rising edge(default setting for compatibility
+                                                   with some ADC on other STM32 series having this setting set by HW
+                                                   default value).
+                                                   In case of need to modify trigger edge, use function
+                                                   @ref LL_ADC_REG_SetTriggerEdge().
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetTriggerSource(). */
+
+  uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetSequencerLength(). */
+
+  uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
+                                             and scan conversions interrupted every selected number of ranks.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+                                             @note This parameter has an effect only if group regular sequencer is
+                                                    enabled (scan length of 2 ranks or more).
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+  uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
+                                             conversions are performed in single mode (one conversion per trigger) or in
+                                             continuous mode (after the first trigger, following conversions launched
+                                             successively automatically).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+                                             Note: It is not possible to enable both ADC group regular continuous mode
+                                                   and discontinuous mode.
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetContinuousMode(). */
+
+  uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer
+                                             by DMA, and DMA requests mode.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetDMATransfer(). */
+
+  uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
+                                             data preserved or overwritten.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetOverrun(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC group injected.
+  * @note   These parameters have an impact on ADC scope: ADC group injected.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "INJ").
+  * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 series. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start)
+                                             or from external peripheral (timer event, external interrupt line).
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE
+                                             @note On this STM32 series, setting trigger source to external trigger also
+                                                   set trigger polarity to rising edge (default setting for
+                                                   compatibility with some ADC on other STM32 series having this
+                                                   setting set by HW default value).
+                                                   In case of need to modify trigger edge, use function
+                                                   @ref LL_ADC_INJ_SetTriggerEdge().
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_INJ_SetTriggerSource(). */
+
+  uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_INJ_SetSequencerLength(). */
+
+  uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided
+                                             and scan conversions interrupted every selected number of ranks.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE
+                                             @note This parameter has an effect only if group injected sequencer is
+                                                   enabled (scan length of 2 ranks or more).
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_INJ_SetSequencerDiscont(). */
+
+  uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group
+                                             regular.
+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO
+                                             Note: This parameter must be set to set to independent trigger if injected
+                                                   trigger source is set to an external trigger.
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_INJ_SetTrigAuto(). */
+
+} LL_ADC_INJ_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+  * @brief    Flags defines which can be used with LL_ADC_ReadReg function
+  * @{
+  */
+#define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
+#define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary
+                                           conversion */
+#define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence
+                                           conversions */
+#define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
+#define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary
+                                                                   conversion */
+#define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence
+                                                                   conversions */
+#define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue
+                                                                   overflow */
+#define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
+#define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
+#define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */
+#define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */
+#define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of
+                                                                   unitary conversion */
+#define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave group regular end of
+                                                                   unitary conversion */
+#define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master group regular end of
+                                                                   sequence conversions */
+#define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave group regular end of
+                                                                   sequence conversions */
+#define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master group regular
+                                                                   overrun */
+#define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave group regular
+                                                                   overrun */
+#define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master group regular end of
+                                                                   sampling phase */
+#define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave group regular end of
+                                                                   sampling phase */
+#define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master group injected end of
+                                                                   unitary conversion */
+#define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave group injected end of
+                                                                   unitary conversion */
+#define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master group injected end of
+                                                                   sequence conversions */
+#define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave group injected end of
+                                                                   sequence conversions */
+#define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master group injected
+                                                                   contexts queue overflow */
+#define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave group injected
+                                                                   contexts queue overflow */
+#define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master analog watchdog 1
+                                                                   of the ADC master */
+#define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave analog watchdog 1
+                                                                   of the ADC slave */
+#define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master analog watchdog 2
+                                                                   of the ADC master */
+#define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave analog watchdog 2
+                                                                   of the ADC slave */
+#define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master analog watchdog 3
+                                                                   of the ADC master */
+#define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave analog watchdog 3
+                                                                   of the ADC slave */
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+  * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
+  * @{
+  */
+#define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
+#define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary
+                                                                   conversion */
+#define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence
+                                                                   conversions */
+#define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling
+                                                                   phase */
+#define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary
+                                                                   conversion */
+#define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence
+                                                                   conversions */
+#define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue
+                                                                   overflow */
+#define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */
+#define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */
+#define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
+  * @{
+  */
+/* List of ADC registers intended to be used (most commonly) with             */
+/* DMA transfer.                                                              */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
+#define LL_ADC_DMA_REG_REGULAR_DATA        (0x00000000UL)      /* ADC group regular conversion data register
+                                           (corresponding to register DR) to be used with ADC configured in independent
+                                           mode. Without DMA transfer, register accessed by LL function
+                                           @ref LL_ADC_REG_ReadConversionData32() and other
+                                           functions @ref LL_ADC_REG_ReadConversionDatax() */
+#if defined(ADC_MULTIMODE_SUPPORT)
+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI  (0x00000001UL)      /* ADC group regular conversion data register
+                                           (corresponding to register CDR) to be used with ADC configured in multimode
+                                           (available on STM32 devices with several ADC instances).
+                                           Without DMA transfer, register accessed by LL function
+                                           @ref LL_ADC_REG_ReadMultiConversionData32() */
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
+  * @{
+  */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                    /*!< ADC synchronous clock derived from
+                                           AHB clock without prescaler */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1)                    /*!< ADC synchronous clock derived from
+                                           AHB clock with prescaler division by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0) /*!< ADC synchronous clock derived from
+                                           AHB clock with prescaler division by 4 */
+#define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                      /*!< ADC asynchronous clock without
+                                           prescaler */
+#define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with
+                                           prescaler division by 2 */
+#define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with
+                                           prescaler division by 4 */
+#define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
+                                           prescaler division by 6 */
+#define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2)                   /*!< ADC asynchronous clock with
+                                           prescaler division by 8 */
+#define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
+                                           prescaler division by 10 */
+#define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
+                                           prescaler division by 12 */
+#define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
+                                            | ADC_CCR_PRESC_0)                  /*!< ADC asynchronous clock with
+                                           prescaler division by 16  */
+#define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                   /*!< ADC asynchronous clock with
+                                           prescaler division by 32 */
+#define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
+                                           prescaler division by 64 */
+#define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
+                                           prescaler division by 128 */
+#define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
+                                            | ADC_CCR_PRESC_0)                  /*!< ADC asynchronous clock with
+                                           prescaler division by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
+  * @{
+  */
+/* Note: Other measurement paths to internal channels may be available        */
+/*       (connections to other peripherals).                                  */
+/*       If they are not listed below, they do not require any specific       */
+/*       path enable. In this case, Access to measurement path is done        */
+/*       only by selecting the corresponding ADC internal channel.            */
+#define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)       /*!< ADC measurement paths all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)     /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_VSENSESEL)  /*!< ADC measurement path to internal channel
+                                                                     temperature sensor */
+#define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATSEL)    /*!< ADC measurement path to internal channel Vbat */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
+  * @{
+  */
+#define LL_ADC_RESOLUTION_12B              (0x00000000UL)                      /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B              (                 ADC_CFGR_RES_0)   /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_1                 )   /*!< ADC resolution  8 bits */
+#define LL_ADC_RESOLUTION_6B               (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)   /*!< ADC resolution  6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
+  * @{
+  */
+#define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000UL)     /*!< ADC conversion data alignment: right aligned
+                                           (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR_ALIGN)   /*!< ADC conversion data alignment: left aligned
+                                           (alignment on data register MSB bit 15)*/
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
+  * @{
+  */
+#define LL_ADC_LP_MODE_NONE                (0x00000000UL)     /*!< No ADC low power mode activated */
+#define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)  /*!< ADC low power mode auto delay: Dynamic low power
+                                           mode, ADC conversions are performed only when necessary
+                                           (when previous ADC conversion data is read).
+                                           See description with function @ref LL_ADC_SetLowPowerMode(). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset instance
+  * @{
+  */
+#define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset instance 1: ADC channel and offset level
+                                           to which the offset programmed will be applied (independently of channel
+                                           mapped on ADC group regular or injected) */
+#define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset instance 2: ADC channel and offset level
+                                           to which the offset programmed will be applied (independently of channel
+                                           mapped on ADC group regular or injected) */
+#define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset instance 3: ADC channel and offset level
+                                           to which the offset programmed will be applied (independently of channel
+                                           mapped on ADC group regular or injected) */
+#define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset instance 4: ADC channel and offset level
+                                           to which the offset programmed will be applied (independently of channel
+                                           mapped on ADC group regular or injected) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_STATE ADC instance - Offset state
+  * @{
+  */
+#define LL_ADC_OFFSET_DISABLE              (0x00000000UL)         /*!< ADC offset disabled
+                                           (setting offset instance wise) */
+#define LL_ADC_OFFSET_ENABLE               (ADC_OFR1_OFFSET1_EN)  /*!< ADC offset enabled
+                                           (setting offset instance wise) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_SIGN ADC instance - Offset sign
+  * @{
+  */
+#define LL_ADC_OFFSET_SIGN_NEGATIVE        (0x00000000UL)       /*!< ADC offset is negative */
+#define LL_ADC_OFFSET_SIGN_POSITIVE        (ADC_OFR1_OFFSETPOS) /*!< ADC offset is positive */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OFFSET_SATURATION ADC instance - Offset saturation mode
+  * @{
+  */
+#define LL_ADC_OFFSET_SATURATION_DISABLE   (0x00000000UL)     /*!< ADC offset saturation is disabled (among ADC
+                                           selected offset instance 1, 2, 3 or 4) */
+#define LL_ADC_OFFSET_SATURATION_ENABLE    (ADC_OFR1_SATEN)   /*!< ADC offset saturation is enabled (among ADC
+                                           selected offset instance 1, 2, 3 or 4) */
+/**
+  * @}
+  */
+/** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
+  * @{
+  */
+#define LL_ADC_GROUP_REGULAR               (0x00000001UL)     /*!< ADC group regular (available on all STM32 devices) */
+#define LL_ADC_GROUP_INJECTED              (0x00000002UL)     /*!< ADC group injected (not available on all STM32
+                                           devices)*/
+#define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL)     /*!< ADC both groups regular and injected */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
+  * @{
+  */
+#define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP \
+                                            | ADC_CHANNEL_0_BITFIELD)                       /*!< ADC channel ADCx_IN0 */
+#define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP \
+                                            | ADC_CHANNEL_1_BITFIELD)                       /*!< ADC channel ADCx_IN1 */
+#define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP \
+                                            | ADC_CHANNEL_2_BITFIELD)                       /*!< ADC channel ADCx_IN2 */
+#define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP \
+                                            | ADC_CHANNEL_3_BITFIELD)                       /*!< ADC channel ADCx_IN3 */
+#define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP \
+                                            | ADC_CHANNEL_4_BITFIELD)                       /*!< ADC channel ADCx_IN4 */
+#define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP \
+                                            | ADC_CHANNEL_5_BITFIELD)                       /*!< ADC channel ADCx_IN5 */
+#define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP \
+                                            | ADC_CHANNEL_6_BITFIELD)                       /*!< ADC channel ADCx_IN6 */
+#define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP \
+                                            | ADC_CHANNEL_7_BITFIELD)                       /*!< ADC channel ADCx_IN7 */
+#define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP \
+                                            | ADC_CHANNEL_8_BITFIELD)                       /*!< ADC channel ADCx_IN8 */
+#define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP \
+                                            | ADC_CHANNEL_9_BITFIELD)                       /*!< ADC channel ADCx_IN9 */
+#define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP \
+                                            | ADC_CHANNEL_10_BITFIELD)                      /*!< ADC channel ADCx_IN10 */
+#define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP \
+                                            | ADC_CHANNEL_11_BITFIELD)                      /*!< ADC channel ADCx_IN11 */
+#define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP \
+                                            | ADC_CHANNEL_12_BITFIELD)                      /*!< ADC channel ADCx_IN12 */
+#define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP \
+                                            | ADC_CHANNEL_13_BITFIELD)                      /*!< ADC channel ADCx_IN13 */
+#define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP \
+                                            | ADC_CHANNEL_14_BITFIELD)                      /*!< ADC channel ADCx_IN14 */
+#define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP \
+                                            | ADC_CHANNEL_15_BITFIELD)                      /*!< ADC channel ADCx_IN15 */
+#define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | \
+                                           ADC_CHANNEL_16_BITFIELD)                        /*!< ADC channel ADCx_IN16 */
+#define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | \
+                                           ADC_CHANNEL_17_BITFIELD)                        /*!< ADC channel ADCx_IN17 */
+#define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | \
+                                           ADC_CHANNEL_18_BITFIELD)                        /*!< ADC channel ADCx_IN18 */
+#define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
+                                           connected to VrefInt: Internal voltage reference.
+                                           On this STM32 series, ADC channel available on all instances but ADC2. */
+#define LL_ADC_CHANNEL_TEMPSENSOR_ADC1     (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
+                                           connected to internal temperature sensor.
+                                           On this STM32 series, ADC channel available only on ADC1 instance. */
+#define LL_ADC_CHANNEL_TEMPSENSOR_ADC5     (LL_ADC_CHANNEL_4  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
+                                           connected to internal temperature sensor.
+                                           On this STM32 series, ADC channel available only on ADC5 instance.
+                                           Refer to device datasheet for ADC5 availability */
+#define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
+                                           connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3
+                                           to have channel voltage always below Vdda. On this STM32 series, ADC channel
+                                           available on all ADC instances but ADC2 & ADC4. Refer to device datasheet
+                                           for ADC4 availability */
+#define LL_ADC_CHANNEL_VOPAMP1             (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
+                                           connected to OPAMP1 output.
+                                           On this STM32 series, ADC channel available only on ADC1 instance. */
+#define LL_ADC_CHANNEL_VOPAMP2             (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH | \
+                                           ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP2
+                                           output. On this STM32 series, ADC channel available only on ADC2 instance. */
+#define LL_ADC_CHANNEL_VOPAMP3_ADC2        (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | \
+                                           ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3
+                                           output. On this STM32 series, ADC channel available only on ADC2 instance. */
+#define LL_ADC_CHANNEL_VOPAMP3_ADC3        (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH | \
+                                           ADC_CHANNEL_ID_INTERNAL_CH_2) /*!< ADC internal channel connected to OPAMP3
+                                           output. On this STM32 series, ADC channel available only on ADC3 instance.
+                                           Refer to device datasheet for ADC3 availability */
+#define LL_ADC_CHANNEL_VOPAMP4             (LL_ADC_CHANNEL_5  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
+connected to OPAMP4 output. On this STM32 series, ADC channel available only on ADC5 instance.
+Refer to device datasheet for ADC5 & OPAMP4 availability */
+#define LL_ADC_CHANNEL_VOPAMP5             (LL_ADC_CHANNEL_3  | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel
+connected to OPAMP5 output. On this STM32 series, ADC channel available only on ADC5 instance.
+Refer to device datasheet for ADC5 & OPAMP5 availability */
+#define LL_ADC_CHANNEL_VOPAMP6             (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH | \
+                                           ADC_CHANNEL_ID_INTERNAL_CH_2)                    /*!< ADC internal channel
+                                           connected to OPAMP6 output.
+                                           On this STM32 series, ADC channel available only on ADC4 instance.
+                                           Refer to device datasheet for ADC4 & OPAMP6 availability */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
+  * @{
+  */
+#define LL_ADC_REG_TRIG_SOFTWARE           (0x00000000UL)                                        /*!< ADC group regular
+                                           conversion trigger internal: SW start. */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM1 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM1 TRGO2.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM1 channel 1 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM1 channel 2 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3       (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM1 channel 3 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | \
+                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM2 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH1       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
+                                           ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           conversion trigger from external peripheral: TIM2 channel 1 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM2 channel 2 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM2_CH3       (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM2 channel 3 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM3 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH1       (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM3 channel 1 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4       (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
+                                           ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM3 channel 4 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM4 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH1       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM4 channel 1 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4       (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM4 channel 4 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
+                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM6 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM7_TRGO      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
+                                           ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           conversion trigger from external peripheral: TIM7 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
+                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM8 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2     (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM8 TRGO2.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM8_CH1       (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM8 channel 1 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | \
+                                           ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM15 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO     (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)  /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM20 TRGO.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, TIM20 is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_TIM20_TRGO2    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM20 TRGO2.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, TIM20 is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH1      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM20 channel 1 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, TIM20 is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH2      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
+                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM20 channel 2 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC1/2 instances, and TIM20 is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_TIM20_CH3      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: TIM20 channel 3 event (capture
+                                           compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC1/2 instances, and TIM20 is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
+                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
+                                           conversion trigger from external peripheral: HRTIMER ADC trigger 1 event.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG2     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | \
+                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
+                                           conversion trigger from external peripheral: HRTIMER ADC trigger 2 event.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC3/4/5 instances, and HRTIM is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
+                                           ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
+                                           conversion trigger from external peripheral: HRTIMER ADC trigger 3 event.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG4     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: HRTIMER ADC trigger 4 event.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC3/4/5 instances, and HRTIM is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG5     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | \
+                                           ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: HRTIMER ADC trigger 5 event.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG6     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: HRTIMER ADC trigger 6 event.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG7     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
+                                           ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
+                                           conversion trigger from external peripheral: HRTIMER ADC trigger 7 event.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG8     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
+                                           ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
+                                           conversion trigger from external peripheral: HRTIMER ADC trigger 8 event.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG9     (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
+                                           ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: HRTIMER ADC trigger 9 event.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG10    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
+                                           ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group regular
+                                           conversion trigger from external peripheral: HRTIMER ADC trigger 10 event.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices.
+                                           Refer to device datasheet for more details */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11    (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: external interrupt line 11.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC1/2 instances */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE2     (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: external interrupt line 2.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on
+                                           ADC3/4/5 instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_REG_TRIG_EXT_LPTIM_OUT      (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_3 | \
+                                           ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | \
+                                           ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular
+                                           conversion trigger from external peripheral: LPTIMER OUT event.
+                                           Trigger edge set to rising edge (default setting). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
+  * @{
+  */
+#define LL_ADC_REG_TRIG_EXT_RISING         (ADC_CFGR_EXTEN_0)                      /*!< ADC group regular conversion
+                                           trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1)                      /*!< ADC group regular conversion
+                                           trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion
+                                           trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SAMPLING_MODE  ADC group regular - Sampling mode
+  * @{
+  */
+#define LL_ADC_REG_SAMPLING_MODE_NORMAL               (0x00000000UL)       /*!< ADC conversions sampling phase duration
+                                           is defined using  @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME */
+#define LL_ADC_REG_SAMPLING_MODE_BULB                 (ADC_CFGR2_BULB)     /*!< ADC conversions sampling phase starts
+                                           immediately after end of conversion, and stops upon trigger event.
+                                           Note: First conversion is using minimal sampling time
+                                           (see @ref ADC_LL_EC_CHANNEL_SAMPLINGTIME) */
+#define LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED    (ADC_CFGR2_SMPTRIG)  /*!< ADC conversions sampling phase is
+                                           controlled by trigger events: trigger rising edge for start sampling,
+                                           trigger falling edge for stop sampling and start conversion */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
+  * @{
+  */
+#define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)     /*!< ADC conversions performed in single mode:
+                                           one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)    /*!< ADC conversions performed in continuous mode:
+                                           after the first trigger, following conversions launched successively
+                                           automatically */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
+  * @{
+  */
+#define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000UL)     /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED    (ADC_CFGR_DMAEN)   /*!< ADC conversion data are transferred by DMA
+                                           in limited mode (one shot mode): DMA transfer requests are stopped when
+                                           number of DMA data transfers (number of ADC conversions) is reached.
+                                           This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMACFG | ADC_CFGR_DMAEN)    /*!< ADC conversion data are
+                                           transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
+                                           whatever number of DMA data transferred (number of ADC conversions).
+                                           This ADC mode is intended to be used with DMA mode circular. */
+/**
+  * @}
+  */
+
+#if defined(ADC_SMPR1_SMPPLUS)
+/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON_CONFIG ADC instance - ADC sampling time common configuration
+  * @{
+  */
+#define LL_ADC_SAMPLINGTIME_COMMON_DEFAULT      (0x00000000UL)      /*!< ADC sampling time let to default settings. */
+#define LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5 (ADC_SMPR1_SMPPLUS) /*!< ADC additional sampling time 3.5 ADC clock
+                                           cycles replacing 2.5 ADC clock cycles (this applies to all channels mapped
+                                           with selection sampling time 2.5 ADC clock cycles, whatever channels mapped
+                                           on ADC groups regular or injected). */
+/**
+  * @}
+  */
+#endif /* ADC_SMPR1_SMPPLUS */
+
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
+  * @{
+  */
+#define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)     /*!< ADC group regular behavior in case of overrun:
+                                                                   data preserved */
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)  /*!< ADC group regular behavior in case of overrun:
+                                                                   data overwritten */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
+  * @{
+  */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000UL)                 /*!< ADC group regular sequencer disable
+                                           (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (ADC_SQR1_L_0)                 /*!< ADC group regular sequencer enable
+                                           with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (ADC_SQR1_L_1)                 /*!< ADC group regular sequencer enable
+                                           with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (ADC_SQR1_L_1 | ADC_SQR1_L_0)  /*!< ADC group regular sequencer enable
+                                           with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (ADC_SQR1_L_2)                 /*!< ADC group regular sequencer enable
+                                           with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (ADC_SQR1_L_2 | ADC_SQR1_L_0)  /*!< ADC group regular sequencer enable
+                                           with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (ADC_SQR1_L_2 | ADC_SQR1_L_1) /*!< ADC group regular sequencer enable
+                                           with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (ADC_SQR1_L_2 | ADC_SQR1_L_1 \
+                                            | ADC_SQR1_L_0)                /*!< ADC group regular sequencer enable
+                                           with 8 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3)                 /*!< ADC group regular sequencer enable
+                                           with 9 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_0)  /*!< ADC group regular sequencer enable
+                                           with 10 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1)  /*!< ADC group regular sequencer enable
+                                           with 11 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_1 \
+                                            | ADC_SQR1_L_0)                /*!< ADC group regular sequencer enable
+                                           with 12 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2)  /*!< ADC group regular sequencer enable
+                                           with 13 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
+                                            | ADC_SQR1_L_0)                /*!< ADC group regular sequencer enable
+                                           with 14 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
+                                            | ADC_SQR1_L_1)                /*!< ADC group regular sequencerenable
+                                           with 15 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 \
+                                            | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable
+                                                                              with 16 ranks in the sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
+  * @{
+  */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                          /*!< ADC group regular sequencer
+                                           discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK       (ADC_CFGR_DISCEN)                       /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every rank */
+#define LL_ADC_REG_SEQ_DISCONT_2RANKS      (ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)  /*!< ADC group regular sequencer
+                                           discontinuous mode enabled with sequence interruption every 2 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_3RANKS      (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCEN)  /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every 3 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_4RANKS      (ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 \
+                                            | ADC_CFGR_DISCEN)                       /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every 4 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCEN)   /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every 5 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_0 \
+                                            | ADC_CFGR_DISCEN)                       /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every 6 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
+                                            | ADC_CFGR_DISCEN)                       /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every 7 ranks */
+#define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 \
+                                            | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN)  /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every 8 ranks */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
+  * @{
+  */
+#define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 1 */
+#define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 2 */
+#define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 3 */
+#define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 4 */
+#define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 5 */
+#define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 6 */
+#define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 7 */
+#define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 8 */
+#define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group
+                                           regular sequencer rank 9 */
+#define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 10 */
+#define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 11 */
+#define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 12 */
+#define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 13 */
+#define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 14 */
+#define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 15 */
+#define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group
+                                           regular sequencer rank 16 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000UL)                                        /*!< ADC group injected
+                                           conversion trigger internal: SW start. */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                          /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM1 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM1 TRGO2.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
+                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM1
+                                           channel 3 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5
+                                           instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM1
+                                           channel 4 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM2 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM2
+                                           channel 1 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2
+                                           instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM3 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
+                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM3
+                                           channel 1 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2
+                                           instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
+                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM3
+                                           channel 3 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2
+                                           instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM3
+                                           channel 4 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2
+                                           instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM4 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH3       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM4
+                                           channel 3 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5
+                                           instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_INJ_TRIG_EXT_TIM4_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM4
+                                           channel 4 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5
+                                           instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
+                                           ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM6 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM7_TRGO      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
+                                           ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM7 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM8 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM8 TRGO2.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH2       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM8
+                                           channel 2 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5
+                                           instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
+                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM8
+                                           channel 4 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
+                                           ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM15 TRGO.
+                                           Trigger edge set to rising edge (default setting). */
+#define LL_ADC_INJ_TRIG_EXT_TIM16_CH1      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
+                                           ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM8
+                                           channel 4 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2
+                                           instances */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO     (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                     /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM20 TRGO.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, TIM20 is not available on all devices. Refer to
+                                           device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2    (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM20 TRGO2.
+                                           Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, TIM20 is not available on all devices. Refer to
+                                           device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_CH2      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM20
+                                           channel 2 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Trigger available only on ADC3/4/5 instances. On this STM32 series, TIM20 is
+                                           not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_TIM20_CH4      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: TIM20
+                                           channel 4 event (capture compare: input capture or output capture).
+                                           Trigger edge set to rising edge (default setting).
+                                           Trigger available only on ADC1/2 instances. On this STM32 series, TIM20 is
+                                           not available on all devices. Refer to device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
+                                           ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER
+                                           ADC trigger 1 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5
+                                           instances, and HRTIM is not available on all devices. Refer to device
+                                           datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | \
+                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC
+                                           trigger 2 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to
+                                           device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
+                                           ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER
+                                           ADC trigger 3 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5
+                                           instances, and HRTIM is not available on all devices. Refer to device
+                                           datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC
+                                           trigger 4 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to
+                                           device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
+                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC
+                                           trigger 5 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to
+                                           device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
+                                           ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC
+                                           trigger 6 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to
+                                           device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | \
+                                           ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC
+                                           trigger 7 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to
+                                           device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC
+                                           trigger 8 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to
+                                           device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
+                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC
+                                           trigger 9 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices. Refer to
+                                           device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10    (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
+                                           ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: HRTIMER ADC
+                                           trigger 10 event. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, HRTIM is not available on all devices.Refer to
+                                           device datasheet for more details */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE3     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | \
+                                           ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                      /*!<
+                                           ADC group injected conversion trigger from external peripheral: external
+                                           interrupt line 3. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC3/4/5
+                                           instances. Refer to device datasheet for ADCx availability */
+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | \
+                                           ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                           /*!<
+                                           ADC group injected conversion trigger from external peripheral: external
+                                           interrupt line 15. Trigger edge set to rising edge (default setting).
+                                           Note: On this STM32 series, this trigger is available only on ADC1/2
+                                           instances. */
+#define LL_ADC_INJ_TRIG_EXT_LPTIM_OUT      (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_3 | \
+                                           ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT) /*!<
+                                           ADC group injected conversion trigger from external peripheral: LPTIMER OUT
+                                           event. Trigger edge set to rising edge (default setting). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
+                                           trigger polarity set to rising edge */
+#define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion
+                                           trigger polarity set to falling edge */
+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion
+                                           trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode
+  * @{
+  */
+#define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000UL)     /*!< ADC group injected conversion trigger independent.
+                                           Setting mandatory if ADC group injected injected trigger source is set to
+                                           an external trigger. */
+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)   /*!< ADC group injected conversion trigger from ADC group
+                                           regular. Setting compliant only with group injected trigger source set to
+                                           SW start, without any further action on  ADC group injected conversion start
+                                           or stop: in this case, ADC group injected is controlled only from ADC group
+                                           regular. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode
+  * @{
+  */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL)   /* Group injected sequence context queue is enabled
+                                           and can contain up to 2 contexts. When all contexts have been processed,
+                                           the queue maintains the last context active perpetually. */
+#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)   /* Group injected sequence context queue is enabled
+                                           and can contain up to 2 contexts. When all contexts have been processed,
+                                           the queue is empty and injected group triggers are disabled. */
+#define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS) /* Group injected sequence context queue is disabled:
+                                           only 1 sequence can be configured and is active perpetually. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length
+  * @{
+  */
+#define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                  /*!< ADC group injected sequencer disable
+                                           (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
+                                           with 2 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable
+                                           with 3 ranks in the sequence */
+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable
+                                           with 4 ranks in the sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode
+  * @{
+  */
+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000UL)     /*!< ADC group injected sequencer discontinuous mode
+                                           disable */
+#define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN) /*!< ADC group injected sequencer discontinuous mode
+                                           enable with sequence interruption every rank */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks
+  * @{
+  */
+#define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET \
+                                            | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 1 */
+#define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET \
+                                            | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 2 */
+#define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET \
+                                            | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 3 */
+#define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET \
+                                            | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group inj. sequencer rank 4 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+  * @{
+  */
+#define LL_ADC_SAMPLINGTIME_2CYCLES_5      (0x00000000UL)       /*!< Sampling time 2.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_6CYCLES_5      (ADC_SMPR2_SMP10_0)  /*!< Sampling time 6.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_12CYCLES_5     (ADC_SMPR2_SMP10_1)  /*!< Sampling time 12.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_24CYCLES_5     (ADC_SMPR2_SMP10_1 \
+                                            | ADC_SMPR2_SMP10_0) /*!< Sampling time 24.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_47CYCLES_5     (ADC_SMPR2_SMP10_2)  /*!< Sampling time 47.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_92CYCLES_5     (ADC_SMPR2_SMP10_2 \
+                                            | ADC_SMPR2_SMP10_0) /*!< Sampling time 92.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_247CYCLES_5    (ADC_SMPR2_SMP10_2 \
+                                            | ADC_SMPR2_SMP10_1) /*!< Sampling time 247.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_640CYCLES_5    (ADC_SMPR2_SMP10_2 \
+                                            | ADC_SMPR2_SMP10_1 \
+                                            | ADC_SMPR2_SMP10_0) /*!< Sampling time 640.5 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending
+  * @{
+  */
+#define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending
+                                           set to single ended (literal also used to set calibration mode) */
+#define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending
+                                           set to differential (literal also used to set calibration mode) */
+#define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending
+                                           set to both single ended and differential (literal used only to set
+                                           calibration factors) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+  * @{
+  */
+#define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK \
+                                            | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+#define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
+#define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
+  * @{
+  */
+#define LL_ADC_AWD_DISABLE                 (0x00000000UL)                           /*!< ADC analog watchdog monitoring
+                                           disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_CFGR_AWD1EN)                       /*!< ADC analog watchdog monitoring
+                                           of all channels, converted by group regular only */
+#define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_CFGR_JAWD1EN)                      /*!< ADC analog watchdog monitoring
+                                           of all channels, converted by group injected only */
+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN)    /*!< ADC analog watchdog monitoring
+                                           of all channels, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN0, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN0, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN1, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN1, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN2, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN2, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN3, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN3, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN4, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN4, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN5, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN5, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN6, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN6, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN7, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN7, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN8, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN8, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN9, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN9, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN10, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)\
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN10, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN11, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN11, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN12, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN12, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN13, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN13, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN14, converted by group only */
+#define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN14, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           monitoring of ADC channel ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN15, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN15, converted by either group
+                                           regular or injected */
+#define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN16, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN16, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN17, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN17, converted by either group regular or injected */
+#define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN18, converted by group injected only */
+#define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN18, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to VrefInt: Internal
+                                           voltage reference, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to VrefInt: Internal
+                                           voltage reference, converted by group injected only */
+#define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to VrefInt: Internal
+                                           voltage reference, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG     ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC1 internal channel connected to internal temperature sensor,
+                                           converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ     ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                    /*!< ADC analog
+                                           of ADC1 internal channel connected to internal temperature sensor,
+                                           converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC1 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC1 internal channel connected to internal temperature sensor,
+                                           converted by either group regular or injected */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG     ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC5 internal channel connected to internal temperature sensor,
+                                           converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ     ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog
+                                           of ADC5 internal channel connected to internal temperature sensor,
+                                           converted by group injected only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR_ADC5 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC5 internal channel connected to internal temperature sensor,
+                                           converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to Vbat/3: Vbat
+                                           voltage through a divider ladder of factor 1/3 to have channel voltage always below
+                                           Vdda, converted by group regular only */
+#define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to Vbat/3: Vbat
+                                           voltage through a divider ladder of factor 1/3 to have channel voltage always below
+                                           Vdda, converted by group injected only */
+#define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to Vbat/3: Vbat
+                                           voltage through a divider ladder of factor 1/3 to have channel voltage always below
+                                           Vdda */
+#define LL_ADC_AWD_CH_VOPAMP1_REG          ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP1 output,
+                                           channel specific to ADC1, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP1_INJ          ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP1 output,
+                                           channel specific to ADC1, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP1_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP1       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP1 output,
+                                           channel specific to ADC1, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP2_REG          ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP2_INJ          ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP2 output,
+                                           channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP2_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP2       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP2 output,
+                                           channel specific to ADC2, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP3 output,
+                                           channel specific to ADC2, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP3 output,
+                                           channel specific to ADC2, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC2  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP3 output,
+                                           channel specific to ADC2, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP3 output,
+                                           channel specific to ADC3, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP3 output,
+                                           channel specific to ADC3, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ ((LL_ADC_CHANNEL_VOPAMP3_ADC3  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP3 output,
+                                           channel specific to ADC3, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP4_REG          ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP4 output,
+                                           channel specific to ADC5, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP4_INJ          ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP4 output,
+                                           channel specific to ADC5, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP4_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP4       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP4 output,
+                                           channel specific to ADC5, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP5_REG          ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP5 output,
+                                           channel specific to ADC5, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP5_INJ          ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP5 output,
+                                           channel specific to ADC5, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP5_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP5       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP5 output,
+                                           channel specific to ADC5, converted by either group regular or injected */
+#define LL_ADC_AWD_CH_VOPAMP6_REG          ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)    /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP6 output,
+                                           channel specific to ADC4, converted by group regular only */
+#define LL_ADC_AWD_CH_VOPAMP6_INJ          ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)   /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP6 output,
+                                           channel specific to ADC4, converted by group injected only */
+#define LL_ADC_AWD_CH_VOPAMP6_REG_INJ      ((LL_ADC_CHANNEL_VOPAMP6       & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN \
+                                            | ADC_CFGR_AWD1SGL)                      /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to OPAMP6 output,
+                                           channel specific to ADC4, converted by either group regular or injected */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
+  * @{
+  */
+#define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_TR1_HT1)      /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW           (ADC_TR1_LT1)      /*!< ADC analog watchdog threshold low */
+#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_TR1_HT1 \
+                                            | ADC_TR1_LT1)     /*!< ADC analog watchdog both thresholds high and low
+                                           concatenated into the same data */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_FILTERING_CONFIG  Analog watchdog - filtering config
+  * @{
+  */
+#define LL_ADC_AWD_FILTERING_NONE          (0x00000000UL)                          /*!< ADC analog watchdog no filtering,
+                                           one out-of-window sample is needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_2SAMPLES      (ADC_TR1_AWDFILT_0)                     /*!< ADC analog watchdog 2
+                                           out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_3SAMPLES      (ADC_TR1_AWDFILT_1)                     /*!< ADC analog watchdog 3
+                                           consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_4SAMPLES      (ADC_TR1_AWDFILT_1 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 4
+                                           consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_5SAMPLES      (ADC_TR1_AWDFILT_2)                     /*!< ADC analog watchdog 5
+                                           consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_6SAMPLES      (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_0) /*!< ADC analog watchdog 6
+                                           consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_7SAMPLES      (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1) /*!< ADC analog watchdog 7
+                                           consecutives out-of-window samples are needed to raise flag or interrupt */
+#define LL_ADC_AWD_FILTERING_8SAMPLES      (ADC_TR1_AWDFILT_2 | ADC_TR1_AWDFILT_1 \
+                                            | ADC_TR1_AWDFILT_0)                    /*!< ADC analog watchdog 8
+                                           consecutives out-of-window samples are needed to raise flag or interrupt */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
+  * @{
+  */
+#define LL_ADC_OVS_DISABLE                 (0x00000000UL)                      /*!< ADC oversampling disabled. */
+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (ADC_CFGR2_ROVSE)                   /*!< ADC oversampling on conversions of
+                                           ADC group regular. If group injected interrupts group regular:
+                                           when ADC group injected is triggered, the oversampling on ADC group regular
+                                           is temporary stopped and continued afterwards. */
+#define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
+                                           ADC group regular. If group injected interrupts group regular:
+                                           when ADC group injected is triggered, the oversampling on ADC group regular
+                                           is resumed from start (oversampler buffer reset). */
+#define LL_ADC_OVS_GRP_INJECTED            (ADC_CFGR2_JOVSE)                   /*!< ADC oversampling on conversions of
+                                           ADC group injected. */
+#define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of
+                                           both ADC groups regular and injected. If group injected interrupting group
+                                           regular: when ADC group injected is triggered, the oversampling on ADC group
+                                           regular is resumed from start (oversampler buffer reset). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
+  * @{
+  */
+#define LL_ADC_OVS_REG_CONT                (0x00000000UL)     /*!< ADC oversampling discontinuous mode: continuous mode
+(all conversions of oversampling ratio are done from 1 trigger) */
+#define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)  /*!< ADC oversampling discontinuous mode: discontinuous
+                                           mode (each conversion of oversampling ratio needs a trigger) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
+  * @{
+  */
+#define LL_ADC_OVS_RATIO_2                 (0x00000000UL)                        /*!< ADC oversampling ratio of 2
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_4                 (ADC_CFGR2_OVSR_0)                    /*!< ADC oversampling ratio of 4
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_8                 (ADC_CFGR2_OVSR_1)                    /*!< ADC oversampling ratio of 8
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_16                (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2)                    /*!< ADC oversampling ratio of 32
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
+                                            | ADC_CFGR2_OVSR_0)                   /*!< ADC oversampling ratio of 256
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data right shift
+  * @{
+  */
+#define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                        /*!< ADC oversampling no shift
+                                           (sum of the ADC conversions data is not divided to result as oversampling
+                                           conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_1           (ADC_CFGR2_OVSS_0)                    /*!< ADC oversampling right shift of 1
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 2
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_2           (ADC_CFGR2_OVSS_1)                    /*!< ADC oversampling right shift of 2
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 4
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_3           (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 8
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_4           (ADC_CFGR2_OVSS_2)                    /*!< ADC oversampling right shift of 4
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 16
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_5           (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 32
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_6           (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 64
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_7           (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
+                                            | ADC_CFGR2_OVSS_0)                   /*!< ADC oversampling right shift of 7
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 128
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3)                    /*!< ADC oversampling right shift of 8
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 256
+                                           to result as oversampling conversion data) */
+/**
+  * @}
+  */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode
+  * @{
+  */
+#define LL_ADC_MULTI_INDEPENDENT           (0x00000000UL)                    /*!< ADC dual mode disabled (ADC
+                                           independent mode) */
+#define LL_ADC_MULTI_DUAL_REG_SIMULT       (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1) /*!< ADC dual mode enabled: group regular
+                                           simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_INTERL       (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 \
+                                            | ADC_CCR_DUAL_0)                  /*!< ADC dual mode enabled: Combined group
+                                           regular interleaved */
+#define LL_ADC_MULTI_DUAL_INJ_SIMULT       (ADC_CCR_DUAL_2 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
+                                           simultaneous */
+#define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected
+                                           alternate trigger. Works only with external triggers (not SW start) */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (ADC_CCR_DUAL_0)                  /*!< ADC dual mode enabled: Combined group
+                                           regular simultaneous + group injected simultaneous */
+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (ADC_CCR_DUAL_1)                  /*!< ADC dual mode enabled: Combined group
+                                           regular simultaneous + group injected alternate trigger */
+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group
+                                           regular interleaved + group injected simultaneous */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer
+  * @{
+  */
+#define LL_ADC_MULTI_REG_DMA_EACH_ADC        (0x00000000UL)                    /*!< ADC multimode group regular
+                                             conversions are transferred by DMA: each ADC uses its own DMA channel,
+                                             with its individual DMA transfer settings */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B (ADC_CCR_MDMA_1)                  /*!< ADC multimode group regular
+                                             conversions are transferred by DMA, one DMA channel for both ADC(DMA of
+                                             ADC master), in limited mode (one shot mode): DMA transfer requests
+                                             are stopped when number of DMA data transfers (number of ADC conversions)
+                                             is reached. This ADC mode is intended to be used with DMA mode
+                                             non-circular. Setting for ADC resolution of 12 and 10 bits */
+#define LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B   (ADC_CCR_MDMA_1 | ADC_CCR_MDMA_0) /*!< ADC multimode group regular
+                                             conversions are transferred by DMA, one DMA channel for both ADC(DMA of
+                                             ADC master), in limited mode (one shot mode): DMA transfer requests
+                                             are stopped when number of DMA data transfers (number of ADC conversions)
+                                             is reached. This ADC mode is intended to be used with DMA mode
+                                             non-circular. Setting for ADC resolution of 8 and 6 bits */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B (ADC_CCR_DMACFG | ADC_CCR_MDMA_1) /*!< ADC multimode group regular
+                                             conversions are transferred by DMA, one DMA channel for both ADC(DMA of
+                                             ADC master), in unlimited mode: DMA transfer requests are unlimited,
+                                             whatever number of DMA data transferred (number of ADC conversions).
+                                             This ADC mode is intended to be used with DMA mode circular.
+                                             Setting for ADC resolution of 12 and 10 bits */
+#define LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B   (ADC_CCR_DMACFG | ADC_CCR_MDMA_1 \
+                                              | ADC_CCR_MDMA_0)                 /*!< ADC multimode group regular
+                                             conversions are transferred by DMA, one DMA channel for both ADC (DMA of
+                                             ADC master), in unlimited mode: DMA transfer requests are unlimited,
+                                             whatever number of DMA data transferred (number of ADC conversions).
+                                             This ADC mode is intended to be used with DMA mode circular.
+                                             Setting for ADC resolution of 8 and 6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases
+  * @{
+  */
+#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE   (0x00000000UL)                      /*!< ADC multimode delay between two
+                                           sampling phases: 1 ADC clock cycle */
+#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES  (ADC_CCR_DELAY_0)                   /*!< ADC multimode delay between two
+                                           sampling phases: 2 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES  (ADC_CCR_DELAY_1)                   /*!< ADC multimode delay between two
+                                           sampling phases: 3 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES  (ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
+                                           sampling phases: 4 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES  (ADC_CCR_DELAY_2)                   /*!< ADC multimode delay between two
+                                           sampling phases: 5 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
+                                           sampling phases: 6 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
+                                           sampling phases: 7 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 \
+                                            | ADC_CCR_DELAY_0)                  /*!< ADC multimode delay between two
+                                           sampling phases: 8 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (ADC_CCR_DELAY_3)                   /*!< ADC multimode delay between two
+                                           sampling phases: 9 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two
+                                           sampling phases: 10 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1) /*!< ADC multimode delay between two
+                                           sampling phases: 11 ADC clock cycles */
+#define LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 \
+                                            | ADC_CCR_DELAY_0)                  /*!< ADC multimode delay between two
+                                           sampling phases: 12 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave
+  * @{
+  */
+#define LL_ADC_MULTI_MASTER                (ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
+                                           instances: ADC master */
+#define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV) /*!< In multimode, selection among several ADC
+                                           instances: ADC slave */
+#define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV \
+                                            | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC
+                                           instances: both ADC master and ADC slave */
+/**
+  * @}
+  */
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/** @defgroup ADC_LL_EC_HELPER_MACRO  Definitions of constants used by helper macro
+  * @{
+  */
+#define LL_ADC_TEMPERATURE_CALC_ERROR      ((int16_t)0x7FFF)  /* Temperature calculation error using helper macro
+                                                                 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
+                                                                 calibration parameters. This value is coded on 16 bits
+                                                                 (to fit on signed word or double word) and corresponds
+                                                                 to an inconsistent temperature value. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
+  * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
+/*       not timeout values.                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Indications for estimation of ADC timeout delays, for this           */
+/*       STM32 series:                                                        */
+/*       - ADC calibration time: maximum delay is 112/fADC.                   */
+/*         (refer to device datasheet, parameter "tCAL")                      */
+/*       - ADC enable time: maximum delay is 1 conversion cycle.              */
+/*         (refer to device datasheet, parameter "tSTAB")                     */
+/*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
+/*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
+/*         cycles                                                             */
+/*       - ADC conversion time: duration depending on ADC clock and ADC       */
+/*         configuration.                                                     */
+/*         (refer to device reference manual, section "Timing")               */
+
+/* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "tADCVREG_STUP").                                                */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)           /*!< Delay for ADC stabilization time (ADC voltage
+                                                              regulator start-up time) */
+
+/* Delay for internal voltage reference stabilization time.                   */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "tstart_vrefint").                                               */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_VREFINT_STAB_US           ( 12UL)        /*!< Delay for internal voltage reference stabilization
+                                                                   time */
+
+/* Delay for temperature sensor stabilization time.                           */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US        (120UL)        /*!< Delay for temperature sensor stabilization time */
+#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL)        /*!< Delay for temperature sensor buffer stabilization
+                                                                   time (starting from ADC enable, refer to
+                                                                   @ref LL_ADC_Enable()) */
+
+/* Delay required between ADC end of calibration and ADC enable.              */
+/* Note: On this STM32 series, a minimum number of ADC clock cycles           */
+/*       are required between ADC end of calibration and ADC enable.          */
+/*       Wait time can be computed in user application by waiting for the     */
+/*       equivalent number of CPU cycles, by taking into account              */
+/*       ratio of CPU clock versus ADC clock prescalers.                      */
+/* Unit: ADC clock cycles.                                                    */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES   (  4UL)        /*!< Delay required between ADC end of calibration
+                                                                   and ADC enable */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+  * @{
+  */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get ADC channel number in decimal format
+  *         from literals LL_ADC_CHANNEL_x.
+  * @note   Example:
+  *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+  *           will return decimal number "4".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned, either defined with number
+  *         or with bitfield (only one bit must be set).
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  * @retval Value between Min_Data=0 and Max_Data=18
+  */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \
+  ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ?                               \
+   (                                                                                       \
+       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \
+   )                                                                                       \
+   :                                                                                       \
+   (                                                                                       \
+       (uint32_t)POSITION_VAL((__CHANNEL__))                                               \
+   )                                                                                       \
+  )
+
+/**
+  * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+  *         from number in decimal format.
+  * @note   Example:
+  *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+  *           will return a data equivalent to "LL_ADC_CHANNEL_4".
+  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
+  *             more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                  \
+  (((__DECIMAL_NB__) <= 9UL) ?                                                                          \
+   (                                                                                                    \
+       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |          \
+       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                              |          \
+       (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))           \
+   )                                                                                                    \
+   :                                                                                                    \
+   (                                                                                                    \
+       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                      | \
+       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                       | \
+       (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \
+   )                                                                                                    \
+  )
+
+/**
+  * @brief  Helper macro to determine whether the selected channel
+  *         corresponds to literal definitions of driver.
+  * @note   The different literal definitions of ADC channels are:
+  *         - ADC internal channel:
+  *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+  *         - ADC external channel (channel connected to a GPIO pin):
+  *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+  * @note   The channel parameter must be a value defined from literal
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+  *         must not be a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel
+                      connected to a GPIO pin).
+  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+  */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
+  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
+
+/**
+  * @brief  Helper macro to convert a channel defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         to its equivalent parameter definition of a ADC external channel
+  *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+  * @note   The channel parameter can be, additionally to a value
+  *         defined from parameter definition of a ADC internal channel
+  *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is returned
+  *         from ADC registers.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
+  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+  * @brief  Helper macro to determine whether the internal channel
+  *         selected is available on the ADC instance selected.
+  * @note   The channel parameter must be a value defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         must not be a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __ADC_INSTANCE__ ADC instance
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+  *         Value "1" if the internal channel selected is available on the ADC instance selected.
+  */
+#if defined(STM32G474xx) || defined(STM32G484xx) || defined(STM32G473xx) || defined(STM32G483xx)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  ((((__ADC_INSTANCE__) == ADC1)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC2)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC3)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC4)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC5)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP5)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC5) ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP4)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+  )
+#elif defined(STM32G471xx)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  ((((__ADC_INSTANCE__) == ADC1)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC2)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC3)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+  )
+#elif defined(STM32G411xB) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  ((((__ADC_INSTANCE__) == ADC1)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC2)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+      )                                                                        \
+   )                                                                           \
+  )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx) || defined(STM32G411xC)
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  ((((__ADC_INSTANCE__) == ADC1)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP1)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR_ADC1) ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)            ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC2)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP2)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC2)                          \
+      )                                                                        \
+   )                                                                           \
+   ||                                                                          \
+   (((__ADC_INSTANCE__) == ADC3)                                               \
+    &&(                                                                        \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP3_ADC3)    ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VOPAMP6)         ||                    \
+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \
+      )                                                                        \
+   )                                                                           \
+  )
+#endif /* STM32G4xx */
+
+/**
+  * @brief  Helper macro to define ADC analog watchdog parameter:
+  *         define a single channel to monitor with analog watchdog
+  *         from sequencer channel and groups definition.
+  * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+  *         Example:
+  *           LL_ADC_SetAnalogWDMonitChannels(
+  *             ADC1, LL_ADC_AWD1,
+  *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
+  *             more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  * @param  __GROUP__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_GROUP_REGULAR
+  *         @arg @ref LL_ADC_GROUP_INJECTED
+  *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG  (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ  (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG  (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ  (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(6)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(6)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (6)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ         (1)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ         (2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ    (2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     (0)(3)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     (0)(3)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ    (3)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ         (5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ         (5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG          (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ          (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ         (4)
+  *
+  *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
+  (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \
+   ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                         \
+   :                                                                                                      \
+   ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                                 \
+   ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                        \
+   :                                                                                                      \
+   (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)        \
+  )
+
+/**
+  * @brief  Helper macro to set the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
+  *         or @ref LL_ADC_SetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to set the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           LL_ADC_SetAnalogWDThresholds
+  *            (< ADCx param >,
+  *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+  ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+
+/**
+  * @brief  Helper macro to get the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to get the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+  *            (LL_ADC_RESOLUTION_8B,
+  *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+  ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))
+
+/**
+  * @brief  Helper macro to get the ADC analog watchdog threshold high
+  *         or low from raw value containing both thresholds concatenated.
+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+  *         Example, to get analog watchdog threshold high from the register raw value:
+  *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
+  * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)                            \
+  (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
+   & LL_ADC_AWD_THRESHOLD_LOW)
+
+/**
+  * @brief  Helper macro to set the ADC calibration value with both single ended
+  *         and differential modes calibration factors concatenated.
+  * @note   To be used with function @ref LL_ADC_SetCalibrationFactor().
+  *         Example, to set calibration factors single ended to 0x55
+  *         and differential ended to 0x2A:
+  *           LL_ADC_SetCalibrationFactor(
+  *             ADC1,
+  *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))
+  * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F
+  * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \
+  (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Helper macro to get the ADC multimode conversion data of ADC master
+  *         or ADC slave from raw value with both ADC conversion data concatenated.
+  * @note   This macro is intended to be used when multimode transfer by DMA
+  *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().
+  *         In this case the transferred data need to processed with this macro
+  *         to separate the conversion data of ADC master and ADC slave.
+  * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_MASTER
+  *         @arg @ref LL_ADC_MULTI_SLAVE
+  * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \
+  (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Helper macro to select, from a ADC instance, to which ADC instance
+  *         it has a dependence in multimode (ADC master of the corresponding
+  *         ADC common instance).
+  * @note   In case of device with multimode available and a mix of
+  *         ADC instances compliant and not compliant with multimode feature,
+  *         ADC instances not compliant with multimode feature are
+  *         considered as master instances (do not depend to
+  *         any other ADC instance).
+  * @param  __ADCx__ ADC instance
+  * @retval __ADCx__ ADC instance master of the corresponding ADC common instance
+  */
+#if defined(ADC5)
+#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+  ( ( ((__ADCx__) == ADC2)                                                     \
+    )?                                                                         \
+    (ADC1)                                                                     \
+    :                                                                          \
+    ( ( ((__ADCx__) == ADC4)                                                   \
+      )?                                                                       \
+      (ADC3)                                                                   \
+      :                                                                        \
+      (__ADCx__)                                                               \
+    )                                                                          \
+  )
+#else
+#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \
+  ( ( ((__ADCx__) == ADC2)                                                     \
+    )?                                                                         \
+    (ADC1)                                                                     \
+    :                                                                          \
+    (__ADCx__)                                                                 \
+  )
+#endif /* ADC5 */
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Helper macro to select the ADC common instance
+  *         to which is belonging the selected ADC instance.
+  * @note   ADC common register instance can be used for:
+  *         - Set parameters common to several ADC instances
+  *         - Multimode (for devices with several ADC instances)
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @param  __ADCx__ ADC instance
+  * @retval ADC common register instance
+  */
+#if defined(ADC345_COMMON)
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
+  ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2))                              \
+    ? (                                                                        \
+       (ADC12_COMMON)                                                          \
+      )                                                                        \
+      :                                                                        \
+      (                                                                        \
+       (ADC345_COMMON)                                                         \
+      )                                                                        \
+  )
+#else
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)  (ADC12_COMMON)
+#endif /* ADC345_COMMON */
+/**
+  * @brief  Helper macro to check if all ADC instances sharing the same
+  *         ADC common instance are disabled.
+  * @note   This check is required by functions with setting conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @note   On devices with only 1 ADC common instance, parameter of this macro
+  *         is useless and can be ignored (parameter kept for compatibility
+  *         with devices featuring several ADC common instances).
+  * @param  __ADCXY_COMMON__ ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value "0" if all ADC instances sharing the same ADC common instance
+  *         are disabled.
+  *         Value "1" if at least one ADC instance sharing the same ADC common instance
+  *         is enabled.
+  */
+#if defined(ADC345_COMMON)
+#if defined(ADC4) &&  defined(ADC5)
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
+    ? (                                                                        \
+       (LL_ADC_IsEnabled(ADC1) |                                               \
+        LL_ADC_IsEnabled(ADC2)  )                                              \
+      )                                                                        \
+      :                                                                        \
+      (                                                                        \
+       (LL_ADC_IsEnabled(ADC3) |                                               \
+        LL_ADC_IsEnabled(ADC4) |                                               \
+        LL_ADC_IsEnabled(ADC5)  )                                              \
+      )                                                                        \
+  )
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \
+    ? (                                                                        \
+       (LL_ADC_IsEnabled(ADC1) |                                               \
+        LL_ADC_IsEnabled(ADC2)  )                                              \
+      )                                                                        \
+      :                                                                        \
+      (LL_ADC_IsEnabled(ADC3))                                                 \
+  )
+#endif /* ADC4 && ADC5 */
+#else
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))
+#endif /* ADC345_COMMON */
+
+/**
+  * @brief  Helper macro to define the ADC conversion data full-scale digital
+  *         value corresponding to the selected ADC resolution.
+  * @note   ADC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
+  */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+  (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))
+
+/**
+  * @brief  Helper macro to convert the ADC conversion data from
+  *         a resolution to another resolution.
+  * @param  __DATA__ ADC conversion data to be converted
+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data to the requested resolution
+  */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+                                         __ADC_RESOLUTION_CURRENT__,\
+                                         __ADC_RESOLUTION_TARGET__)          \
+(((__DATA__)                                                                 \
+  << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \
+)
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                      __ADC_DATA__,\
+                                      __ADC_RESOLUTION__)                    \
+((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
+)
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value) in
+  *         differential ended mode.
+  * @note   ADC data from ADC data register is unsigned and centered around
+  *         middle code in. Converted voltage can be positive or negative
+  *         depending on differential input voltages.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_ADC_CALC_DIFF_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                           __ADC_DATA__,\
+                                           __ADC_RESOLUTION__)\
+((int32_t)((__ADC_DATA__) << 1U) * (int32_t)(__VREFANALOG_VOLTAGE__)\
+ / (int32_t)(__LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))\
+ - (int32_t)(__VREFANALOG_VOLTAGE__))
+
+/**
+  * @brief  Helper macro to calculate analog reference voltage (Vref+)
+  *         (unit: mVolt) from ADC conversion data of internal voltage
+  *         reference VrefInt.
+  * @note   Computation is using VrefInt calibration value
+  *         stored in system memory for each device during production.
+  * @note   This voltage depends on user board environment: voltage level
+  *         connected to pin Vref+.
+  *         On devices with small package, the pin Vref+ is not present
+  *         and internally bonded to pin Vdda.
+  * @note   On this STM32 series, calibration data of internal voltage reference
+  *         VrefInt corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         internal voltage reference VrefInt.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *         of internal voltage reference VrefInt (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Analog reference voltage (unit: mV)
+  */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+                                         __ADC_RESOLUTION__)                 \
+(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
+                                    (__ADC_RESOLUTION__),                    \
+                                    LL_ADC_RESOLUTION_12B)                   \
+)
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor calibration values
+  *         stored in system memory for each device during production.
+  * @note   Calculation formula:
+  *           Temperature = ((TS_ADC_DATA - TS_CAL1)
+  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))
+  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP
+  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC
+  *                Avg_Slope = (TS_CAL2 - TS_CAL1)
+  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)
+  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL1 (calibrated in factory)
+  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature
+  *                            TEMP_DEGC_CAL2 (calibrated in factory)
+  *         Caution: Calculation relevancy under reserve that calibration
+  *                  parameters are correct (address and data).
+  *                  To calculate temperature using temperature sensor
+  *                  datasheet typical values (generic values less, therefore
+  *                  less accurate than calibrated values),
+  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   On this STM32 series, calibration data of temperature sensor
+  *         corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         temperature sensor.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal
+  *                                 temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature
+  *                                 sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  *         In case or error, value LL_ADC_TEMPERATURE_CALC_ERROR is returned (inconsistent temperature value)
+  */
+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
+                                  __TEMPSENSOR_ADC_DATA__,\
+                                  __ADC_RESOLUTION__)\
+((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ?       \
+ (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \
+                                                   (__ADC_RESOLUTION__),          \
+                                                   LL_ADC_RESOLUTION_12B)         \
+                  * (__VREFANALOG_VOLTAGE__))                                     \
+                 / TEMPSENSOR_CAL_VREFANALOG)                                     \
+       - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \
+    ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \
+   ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \
+  ) + TEMPSENSOR_CAL1_TEMP                                                        \
+ )                                                                                \
+ :                                                                                \
+ ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR)                                         \
+)
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor typical values
+  *         (refer to device datasheet).
+  * @note   Calculation formula:
+  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+  *                         / Avg_Slope + CALx_TEMP
+  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
+  *                                   (unit: digital value)
+  *                Avg_Slope        = temperature sensor slope
+  *                                   (unit: uV/Degree Celsius)
+  *                TS_TYP_CALx_VOLT = temperature sensor digital value at
+  *                                   temperature CALx_TEMP (unit: mV)
+  *         Caution: Calculation relevancy under reserve the temperature sensor
+  *                  of the current device has characteristics in line with
+  *                  datasheet typical values.
+  *                  If temperature sensor calibration values are available on
+  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),
+  *                  temperature calculation will be more accurate using
+  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   ADC measurement data must correspond to a resolution of 12 bits
+  *         (full scale digital value 4095). If not the case, the data must be
+  *         preliminarily rescaled to an equivalent resolution of 12 bits.
+  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value
+  *                                       (unit: uV/DegCelsius).
+  *                                       On STM32G4, refer to device datasheet parameter "Avg_Slope".
+  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value
+  *                                       (at temperature and Vref+ defined in parameters below) (unit: mV).
+  *                                       On STM32G4, refer to datasheet parameter "V30" (corresponding to TS_CAL1).
+  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage
+  *                                       (see parameter above) is corresponding (unit: mV)
+  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) value (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+                                             __TEMPSENSOR_TYP_CALX_V__,\
+                                             __TEMPSENSOR_CALX_TEMP__,\
+                                             __VREFANALOG_VOLTAGE__,\
+                                             __TEMPSENSOR_ADC_DATA__,\
+                                             __ADC_RESOLUTION__)            \
+(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
+               / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
+              * 1000UL)                                                     \
+    -                                                                       \
+    (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
+              * 1000UL)                                                     \
+   )                                                                        \
+  ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                \
+ ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                    \
+)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+  * @{
+  */
+/* Note: LL ADC functions to set DMA transfer are located into sections of    */
+/*       configuration of ADC instance, groups and multimode (if available):  */
+/*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
+
+/**
+  * @brief  Function to help to configure DMA transfer from ADC: retrieve the
+  *         ADC register address from ADC instance and a list of ADC registers
+  *         intended to be used (most commonly) with DMA transfer.
+  * @note   These ADC registers are data registers:
+  *         when ADC conversion data is available in ADC data registers,
+  *         ADC generates a DMA transfer request.
+  * @note   This macro is intended to be used with LL DMA driver, refer to
+  *         function "LL_DMA_ConfigAddresses()".
+  *         Example:
+  *           LL_DMA_ConfigAddresses(DMA1,
+  *                                  LL_DMA_CHANNEL_1,
+  *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+  *                                  (uint32_t)&< array or variable >,
+  *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+  * @note   For devices with several ADC: in multimode, some devices
+  *         use a different data register outside of ADC instance scope
+  *         (common data register). This macro manages this register difference,
+  *         only ADC instance has to be set as parameter.
+  * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n
+  *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n
+  *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr
+  * @param  ADCx ADC instance
+  * @param  Register This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)
+  *
+  *         (1) Available on devices with several ADC instances.
+  * @retval ADC register address
+  */
+#if defined(ADC_MULTIMODE_SUPPORT)
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
+{
+  uint32_t data_reg_addr;
+
+  if (Register == LL_ADC_DMA_REG_REGULAR_DATA)
+  {
+    /* Retrieve address of register DR */
+    data_reg_addr = (uint32_t) &(ADCx->DR);
+  }
+  else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */
+  {
+    /* Retrieve address of register CDR */
+    data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);
+  }
+
+  return data_reg_addr;
+}
+#else
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
+{
+  /* Prevent unused argument(s) compilation warning */
+  (void)(Register);
+
+  /* Retrieve address of register DR */
+  return (uint32_t) &(ADCx->DR);
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
+  *           ADC instances
+  * @{
+  */
+
+/**
+  * @brief  Set parameter common to several ADC: Clock source and prescaler.
+  * @note   On this STM32 series, if ADC group injected is used, some
+  *         clock ratio constraints between ADC clock and AHB clock
+  *         must be respected.
+  *         Refer to reference manual.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n
+  *         CCR      PRESC          LL_ADC_SetCommonClock
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  CommonClock This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: Clock source and prescaler.
+  * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n
+  *         CCR      PRESC          LL_ADC_GetCommonClock
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Configure all paths (overwrite current configuration).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  *         The values not selected are removed from configuration.
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay is required for internal voltage reference and
+  *         temperature sensor stabilization time.
+  *         Refer to device datasheet.
+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+  *         Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
+  *         @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
+  *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalCh\n
+  *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Add paths to the current configuration.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay is required for internal voltage reference and
+  *         temperature sensor stabilization time.
+  *         Refer to device datasheet.
+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+  *         Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
+  *         @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChAdd\n
+  *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalChAdd\n
+  *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalChAdd
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  SET_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Remove paths to the current configuration.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChRem\n
+  *         CCR      VSENSESEL      LL_ADC_SetCommonPathInternalChRem\n
+  *         CCR      VBATSEL        LL_ADC_SetCommonPathInternalChRem
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: measurement path to internal
+  *         channels (VrefInt, temperature sensor, ...).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
+  *         CCR      VSENSESEL      LL_ADC_GetCommonPathInternalCh\n
+  *         CCR      VBATSEL        LL_ADC_GetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Set ADC calibration factor in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   This function is intended to set calibration parameters
+  *         without having to perform a new calibration using
+  *         @ref LL_ADC_StartCalibration().
+  * @note   For devices with differential mode available:
+  *         Calibration of offset is specific to each of
+  *         single-ended and differential modes
+  *         (calibration factor must be specified for each of these
+  *         differential modes, if used afterwards and if the application
+  *         requires their calibration).
+  * @note   In case of setting calibration factors of both modes single ended
+  *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):
+  *         both calibration factors must be concatenated.
+  *         To perform this processing, use helper macro
+  *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled, without calibration on going, without conversion
+  *         on going on group regular.
+  * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationFactor\n
+  *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationFactor
+  * @param  ADCx ADC instance
+  * @param  SingleDiff This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED
+  * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)
+{
+  MODIFY_REG(ADCx->CALFACT,
+             SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,
+             CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK)
+                                    >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4)
+                                   & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));
+}
+
+/**
+  * @brief  Get ADC calibration factor in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   Calibration factors are set by hardware after performing
+  *         a calibration run using function @ref LL_ADC_StartCalibration().
+  * @note   For devices with differential mode available:
+  *         Calibration of offset is specific to each of
+  *         single-ended and differential modes
+  * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationFactor\n
+  *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationFactor
+  * @param  ADCx ADC instance
+  * @param  SingleDiff This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval Value between Min_Data=0x00 and Max_Data=0x7F
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+  /* Retrieve bits with position in register depending on parameter           */
+  /* "SingleDiff".                                                            */
+  /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */
+  /* containing other bits reserved for other purpose.                        */
+  return (uint32_t)(READ_BIT(ADCx->CALFACT,
+                             (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK))
+                    >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >>
+                        ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));
+}
+
+/**
+  * @brief  Set ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     RES            LL_ADC_SetResolution
+  * @param  ADCx ADC instance
+  * @param  Resolution This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);
+}
+
+/**
+  * @brief  Get ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CFGR     RES            LL_ADC_GetResolution
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));
+}
+
+/**
+  * @brief  Set ADC conversion data alignment.
+  * @note   Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     ALIGN          LL_ADC_SetDataAlignment
+  * @param  ADCx ADC instance
+  * @param  DataAlignment This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_ALIGN, DataAlignment);
+}
+
+/**
+  * @brief  Get ADC conversion data alignment.
+  * @note   Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CFGR     ALIGN          LL_ADC_GetDataAlignment
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_ALIGN));
+}
+
+/**
+  * @brief  Set ADC low power mode.
+  * @note   Description of ADC low power modes:
+  *         - ADC low power mode "auto wait": Dynamic low power mode,
+  *           ADC conversions occurrences are limited to the minimum necessary
+  *           in order to reduce power consumption.
+  *           New ADC conversion starts only when the previous
+  *           unitary conversion data (for ADC group regular)
+  *           or previous sequence conversions data (for ADC group injected)
+  *           has been retrieved by user software.
+  *           In the meantime, ADC remains idle: does not performs any
+  *           other conversion.
+  *           This mode allows to automatically adapt the ADC conversions
+  *           triggers to the speed of the software that reads the data.
+  *           Moreover, this avoids risk of overrun for low frequency
+  *           applications.
+  *           How to use this low power mode:
+  *           - It is not recommended to use with interruption or DMA
+  *             since these modes have to clear immediately the EOC flag
+  *             (by CPU to free the IRQ pending event or by DMA).
+  *             Auto wait will work but fort a very short time, discarding
+  *             its intended benefit (except specific case of high load of CPU
+  *             or DMA transfers which can justify usage of auto wait).
+  *           - Do use with polling: 1. Start conversion,
+  *             2. Later on, when conversion data is needed: poll for end of
+  *             conversion  to ensure that conversion is completed and
+  *             retrieve ADC conversion data. This will trig another
+  *             ADC conversion start.
+  * @note   With ADC low power mode "auto wait", the ADC conversion data read
+  *         is corresponding to previous ADC conversion start, independently
+  *         of delay during which ADC was idle.
+  *         Therefore, the ADC conversion data may be outdated: does not
+  *         correspond to the current voltage level on the selected
+  *         ADC channel.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode
+  * @param  ADCx ADC instance
+  * @param  LowPowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_LP_MODE_NONE
+  *         @arg @ref LL_ADC_LP_AUTOWAIT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);
+}
+
+/**
+  * @brief  Get ADC low power mode:
+  * @note   Description of ADC low power modes:
+  *         - ADC low power mode "auto wait": Dynamic low power mode,
+  *           ADC conversions occurrences are limited to the minimum necessary
+  *           in order to reduce power consumption.
+  *           New ADC conversion starts only when the previous
+  *           unitary conversion data (for ADC group regular)
+  *           or previous sequence conversions data (for ADC group injected)
+  *           has been retrieved by user software.
+  *           In the meantime, ADC remains idle: does not performs any
+  *           other conversion.
+  *           This mode allows to automatically adapt the ADC conversions
+  *           triggers to the speed of the software that reads the data.
+  *           Moreover, this avoids risk of overrun for low frequency
+  *           applications.
+  *           How to use this low power mode:
+  *           - It is not recommended to use with interruption or DMA
+  *             since these modes have to clear immediately the EOC flag
+  *             (by CPU to free the IRQ pending event or by DMA).
+  *             Auto wait will work but fort a very short time, discarding
+  *             its intended benefit (except specific case of high load of CPU
+  *             or DMA transfers which can justify usage of auto wait).
+  *           - Do use with polling: 1. Start conversion,
+  *             2. Later on, when conversion data is needed: poll for end of
+  *             conversion  to ensure that conversion is completed and
+  *             retrieve ADC conversion data. This will trig another
+  *             ADC conversion start.
+  * @note   With ADC low power mode "auto wait", the ADC conversion data read
+  *         is corresponding to previous ADC conversion start, independently
+  *         of delay during which ADC was idle.
+  *         Therefore, the ADC conversion data may be outdated: does not
+  *         correspond to the current voltage level on the selected
+  *         ADC channel.
+  * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_LP_MODE_NONE
+  *         @arg @ref LL_ADC_LP_AUTOWAIT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));
+}
+
+/**
+  * @brief  Set ADC selected offset instance 1, 2, 3 or 4.
+  * @note   This function set the 2 items of offset configuration:
+  *         - ADC channel to which the offset programmed will be applied
+  *           (independently of channel mapped on ADC group regular
+  *           or group injected)
+  *         - Offset level (offset to be subtracted from the raw
+  *           converted data).
+  * @note   Caution: Offset format is dependent to ADC resolution:
+  *         offset has to be left-aligned on bit 11, the LSB (right bits)
+  *         are set to 0.
+  * @note   This function enables the offset, by default. It can be forced
+  *         to disable state using function LL_ADC_SetOffsetState().
+  * @note   If a channel is mapped on several offsets numbers, only the offset
+  *         with the lowest value is considered for the subtraction.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @note   On STM32G4, some fast channels are available: fast analog inputs
+  *         coming from GPIO pads (ADC_IN1..5).
+  * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n
+  *         OFR1     OFFSET1        LL_ADC_SetOffset\n
+  *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n
+  *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n
+  *         OFR2     OFFSET2        LL_ADC_SetOffset\n
+  *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n
+  *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n
+  *         OFR3     OFFSET3        LL_ADC_SetOffset\n
+  *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n
+  *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n
+  *         OFR4     OFFSET4        LL_ADC_SetOffset\n
+  *         OFR4     OFFSET4_EN     LL_ADC_SetOffset
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  MODIFY_REG(*preg,
+             ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
+             ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
+}
+
+/**
+  * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
+  *         Channel to which the offset programmed will be applied
+  *         (independently of channel mapped on ADC group regular
+  *         or group injected)
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @note   On STM32G4, some fast channels are available: fast analog inputs
+  *         coming from GPIO pads (ADC_IN1..5).
+  * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n
+  *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n
+  *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n
+  *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
+  *             more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
+}
+
+/**
+  * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
+  *         Offset level (offset to be subtracted from the raw
+  *         converted data).
+  * @note   Caution: Offset format is dependent to ADC resolution:
+  *         offset has to be left-aligned on bit 11, the LSB (right bits)
+  *         are set to 0.
+  * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n
+  *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n
+  *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n
+  *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(const ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);
+}
+
+/**
+  * @brief  Set for the ADC selected offset instance 1, 2, 3 or 4:
+  *         force offset state disable or enable
+  *         without modifying offset channel or offset value.
+  * @note   This function should be needed only in case of offset to be
+  *         enabled-disabled dynamically, and should not be needed in other cases:
+  *         function LL_ADC_SetOffset() automatically enables the offset.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll OFR1     OFFSET1_EN     LL_ADC_SetOffsetState\n
+  *         OFR2     OFFSET2_EN     LL_ADC_SetOffsetState\n
+  *         OFR3     OFFSET3_EN     LL_ADC_SetOffsetState\n
+  *         OFR4     OFFSET4_EN     LL_ADC_SetOffsetState
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  OffsetState This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_DISABLE
+  *         @arg @ref LL_ADC_OFFSET_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  MODIFY_REG(*preg,
+             ADC_OFR1_OFFSET1_EN,
+             OffsetState);
+}
+
+/**
+  * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
+  *         offset state disabled or enabled.
+  * @rmtoll OFR1     OFFSET1_EN     LL_ADC_GetOffsetState\n
+  *         OFR2     OFFSET2_EN     LL_ADC_GetOffsetState\n
+  *         OFR3     OFFSET3_EN     LL_ADC_GetOffsetState\n
+  *         OFR4     OFFSET4_EN     LL_ADC_GetOffsetState
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_DISABLE
+  *         @arg @ref LL_ADC_OFFSET_ENABLE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetState(const ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_EN);
+}
+
+/**
+  * @brief  Set for the ADC selected offset instance 1, 2, 3 or 4:
+  *         choose offset sign.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll OFR1     OFFSETPOS      LL_ADC_SetOffsetSign\n
+  *         OFR2     OFFSETPOS      LL_ADC_SetOffsetSign\n
+  *         OFR3     OFFSETPOS      LL_ADC_SetOffsetSign\n
+  *         OFR4     OFFSETPOS      LL_ADC_SetOffsetSign
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  OffsetSign This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+  *         @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  MODIFY_REG(*preg,
+             ADC_OFR1_OFFSETPOS,
+             OffsetSign);
+}
+
+/**
+  * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
+  *         offset sign if positive or negative.
+  * @rmtoll OFR1     OFFSETPOS      LL_ADC_GetOffsetSign\n
+  *         OFR2     OFFSETPOS      LL_ADC_GetOffsetSign\n
+  *         OFR3     OFFSETPOS      LL_ADC_GetOffsetSign\n
+  *         OFR4     OFFSETPOS      LL_ADC_GetOffsetSign
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
+  *         @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSign(const ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSETPOS);
+}
+
+/**
+  * @brief  Set for the ADC selected offset instance 1, 2, 3 or 4:
+  *         choose offset saturation mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll OFR1     SATEN          LL_ADC_SetOffsetSaturation\n
+  *         OFR2     SATEN          LL_ADC_SetOffsetSaturation\n
+  *         OFR3     SATEN          LL_ADC_SetOffsetSaturation\n
+  *         OFR4     SATEN          LL_ADC_SetOffsetSaturation
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @param  OffsetSaturation This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
+  *         @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
+{
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  MODIFY_REG(*preg,
+             ADC_OFR1_SATEN,
+             OffsetSaturation);
+}
+
+/**
+  * @brief  Get for the ADC selected offset instance 1, 2, 3 or 4:
+  *         offset saturation if enabled or disabled.
+  * @rmtoll OFR1     SATEN          LL_ADC_GetOffsetSaturation\n
+  *         OFR2     SATEN          LL_ADC_GetOffsetSaturation\n
+  *         OFR3     SATEN          LL_ADC_GetOffsetSaturation\n
+  *         OFR4     SATEN          LL_ADC_GetOffsetSaturation
+  * @param  ADCx ADC instance
+  * @param  Offsety This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_1
+  *         @arg @ref LL_ADC_OFFSET_2
+  *         @arg @ref LL_ADC_OFFSET_3
+  *         @arg @ref LL_ADC_OFFSET_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
+  *         @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSaturation(const ADC_TypeDef *ADCx, uint32_t Offsety)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
+
+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_SATEN);
+}
+
+/**
+  * @brief  Set ADC gain compensation.
+  * @note   This function set the gain compensation coefficient
+  *         that is applied to raw converted data using the formula:
+  *           DATA = DATA(raw) * (gain compensation coef) / 4096
+  * @note   This function enables the gain compensation if given
+  *         coefficient is above 0, otherwise it disables it.
+  * @note   Gain compensation when enabled is applied to all channels.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll GCOMP    GCOMPCOEFF     LL_ADC_SetGainCompensation\n
+  *         CFGR2    GCOMP          LL_ADC_SetGainCompensation
+  * @param  ADCx ADC instance
+  * @param  GainCompensation This parameter can be:
+  *         0           Gain compensation will be disabled and value set to 0
+  *         1 -> 16393  Gain compensation will be enabled with specified value
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetGainCompensation(ADC_TypeDef *ADCx, uint32_t GainCompensation)
+{
+  MODIFY_REG(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF, GainCompensation);
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_GCOMP, ((GainCompensation == 0UL) ? 0UL : 1UL) << ADC_CFGR2_GCOMP_Pos);
+}
+
+/**
+  * @brief  Get the ADC gain compensation value
+  * @rmtoll GCOMP    GCOMPCOEFF     LL_ADC_GetGainCompensation\n
+  *         CFGR2    GCOMP          LL_ADC_GetGainCompensation
+  * @param  ADCx ADC instance
+  * @retval Returned value can be:
+  *         0           Gain compensation is disabled
+  *         1 -> 16393  Gain compensation is enabled with returned value
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetGainCompensation(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CFGR2, ADC_CFGR2_GCOMP) == ADC_CFGR2_GCOMP) ?
+          READ_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF) : 0UL);
+}
+
+#if defined(ADC_SMPR1_SMPPLUS)
+/**
+  * @brief  Set ADC sampling time common configuration impacting
+  *         settings of sampling time channel wise.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll SMPR1    SMPPLUS        LL_ADC_SetSamplingTimeCommonConfig
+  * @param  ADCx ADC instance
+  * @param  SamplingTimeCommonConfig This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
+{
+  MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
+}
+
+/**
+  * @brief  Get ADC sampling time common configuration impacting
+  *         settings of sampling time channel wise.
+  * @rmtoll SMPR1    SMPPLUS        LL_ADC_GetSamplingTimeCommonConfig
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonConfig(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->SMPR1, ADC_SMPR1_SMPPLUS));
+}
+#endif /* ADC_SMPR1_SMPPLUS */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Set ADC group regular conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   On this STM32 series, setting trigger source to external trigger
+  *         also set trigger polarity to rising edge
+  *         (default setting for compatibility with some ADC on other
+  *         STM32 series having this setting set by HW default value).
+  *         In case of need to modify trigger edge, use
+  *         function @ref LL_ADC_REG_SetTriggerEdge().
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n
+  *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2       (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3       (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2      (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4      (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11     (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2      (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
+  *
+  *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+  *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
+  *             more details.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   To determine whether group regular trigger source is
+  *         internal (SW start) or external, without detail
+  *         of which peripheral is selected as external trigger,
+  *         (equivalent to
+  *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+  *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n
+  *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH3        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4        (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_CH1        (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH2       (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM20_CH3       (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG2      (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG4      (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG5
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG6
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG7
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG8
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG9
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG10
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11     (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE2      (2)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM_OUT
+  *
+  *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+  *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
+  *             more details.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
+{
+  __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);
+
+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+  /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */
+  uint32_t shift_exten = ((trigger_source & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+  /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */
+  /* to match with triggers literals definition.                              */
+  return ((trigger_source
+           & (ADC_REG_TRIG_SOURCE_MASK >> shift_exten) & ADC_CFGR_EXTSEL)
+          | ((ADC_REG_TRIG_EDGE_MASK >> shift_exten) & ADC_CFGR_EXTEN)
+         );
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source internal (SW start)
+  *         or external.
+  * @note   In case of group regular trigger source set to external trigger,
+  *         to determine which peripheral is selected as external trigger,
+  *         use function @ref LL_ADC_REG_GetTriggerSource().
+  * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
+  * @param  ADCx ADC instance
+  * @retval Value "0" if trigger source external trigger
+  *         Value "1" if trigger source SW start.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge
+  * @param  ADCx ADC instance
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));
+}
+
+/**
+  * @brief  Set ADC sampling mode.
+  * @note   This function set the ADC conversion sampling mode
+  * @note   This mode applies to regular group only.
+  * @note   Set sampling mode is applied to all conversion of regular group.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR2    BULB           LL_ADC_REG_SetSamplingMode\n
+  *         CFGR2    SMPTRIG        LL_ADC_REG_SetSamplingMode
+  * @param  ADCx ADC instance
+  * @param  SamplingMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSamplingMode(ADC_TypeDef *ADCx, uint32_t SamplingMode)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, SamplingMode);
+}
+
+/**
+  * @brief  Get the ADC sampling mode
+  * @rmtoll CFGR2    BULB           LL_ADC_REG_GetSamplingMode\n
+  *         CFGR2    SMPTRIG        LL_ADC_REG_GetSamplingMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_NORMAL
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_BULB
+  *         @arg @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSamplingMode(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG));
+}
+
+/**
+  * @brief  Set ADC group regular sequencer length and scan direction.
+  * @note   Description of ADC group regular sequencer features:
+  *         - For devices with sequencer fully configurable
+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are configurable.
+  *           This function performs configuration of:
+  *           - Sequence length: Number of ranks in the scan sequence.
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from rank 1 to rank n).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerRanks()".
+  *         - For devices with sequencer not fully configurable
+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are defined by channel number.
+  *           This function performs configuration of:
+  *           - Sequence length: Number of ranks in the scan sequence is
+  *             defined by number of channels set in the sequence,
+  *             rank of each channel is fixed by channel HW number.
+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from lowest channel number to
+  *             highest channel number).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerChannels()".
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength
+  * @param  ADCx ADC instance
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+  MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer length and scan direction.
+  * @note   Description of ADC group regular sequencer features:
+  *         - For devices with sequencer fully configurable
+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are configurable.
+  *           This function retrieves:
+  *           - Sequence length: Number of ranks in the scan sequence.
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from rank 1 to rank n).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerRanks()".
+  *         - For devices with sequencer not fully configurable
+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are defined by channel number.
+  *           This function retrieves:
+  *           - Sequence length: Number of ranks in the scan sequence is
+  *             defined by number of channels set in the sequence,
+  *             rank of each channel is fixed by channel HW number.
+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from lowest channel number to
+  *             highest channel number).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerChannels()".
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));
+}
+
+/**
+  * @brief  Set ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @note   It is not possible to enable both ADC group regular
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   It is not possible to enable both ADC auto-injected mode
+  *         and ADC group regular sequencer discontinuous mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n
+  *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @param  SeqDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n
+  *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));
+}
+
+/**
+  * @brief  Set ADC group regular sequence: channel on the selected
+  *         scan sequence rank.
+  * @note   This function performs configuration of:
+  *         - Channels ordering into each rank of scan sequence:
+  *           whatever channel can be placed into whatever rank.
+  * @note   On this STM32 series, ADC group regular sequencer is
+  *         fully configurable: sequencer length and each rank
+  *         affectation to a channel are configurable.
+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n
+  *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_RANK_1
+  *         @arg @ref LL_ADC_REG_RANK_2
+  *         @arg @ref LL_ADC_REG_RANK_3
+  *         @arg @ref LL_ADC_REG_RANK_4
+  *         @arg @ref LL_ADC_REG_RANK_5
+  *         @arg @ref LL_ADC_REG_RANK_6
+  *         @arg @ref LL_ADC_REG_RANK_7
+  *         @arg @ref LL_ADC_REG_RANK_8
+  *         @arg @ref LL_ADC_REG_RANK_9
+  *         @arg @ref LL_ADC_REG_RANK_10
+  *         @arg @ref LL_ADC_REG_RANK_11
+  *         @arg @ref LL_ADC_REG_RANK_12
+  *         @arg @ref LL_ADC_REG_RANK_13
+  *         @arg @ref LL_ADC_REG_RANK_14
+  *         @arg @ref LL_ADC_REG_RANK_15
+  *         @arg @ref LL_ADC_REG_RANK_16
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+  /* Set bits with content of parameter "Channel" with bits position          */
+  /* in register and register position depending on parameter "Rank".         */
+  /* Parameters "Rank" and "Channel" are used with masks because containing   */
+  /* other bits reserved for other purpose.                                   */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
+                                             ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+
+  MODIFY_REG(*preg,
+             ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+             << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+}
+
+/**
+  * @brief  Get ADC group regular sequence: channel on the selected
+  *         scan sequence rank.
+  * @note   On this STM32 series, ADC group regular sequencer is
+  *         fully configurable: sequencer length and each rank
+  *         affectation to a channel are configurable.
+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n
+  *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_RANK_1
+  *         @arg @ref LL_ADC_REG_RANK_2
+  *         @arg @ref LL_ADC_REG_RANK_3
+  *         @arg @ref LL_ADC_REG_RANK_4
+  *         @arg @ref LL_ADC_REG_RANK_5
+  *         @arg @ref LL_ADC_REG_RANK_6
+  *         @arg @ref LL_ADC_REG_RANK_7
+  *         @arg @ref LL_ADC_REG_RANK_8
+  *         @arg @ref LL_ADC_REG_RANK_9
+  *         @arg @ref LL_ADC_REG_RANK_10
+  *         @arg @ref LL_ADC_REG_RANK_11
+  *         @arg @ref LL_ADC_REG_RANK_12
+  *         @arg @ref LL_ADC_REG_RANK_13
+  *         @arg @ref LL_ADC_REG_RANK_14
+  *         @arg @ref LL_ADC_REG_RANK_15
+  *         @arg @ref LL_ADC_REG_RANK_16
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
+  *             more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
+                                                   ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
+
+  return (uint32_t)((READ_BIT(*preg,
+                              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+                     >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+                   );
+}
+
+/**
+  * @brief  Set ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @note   It is not possible to enable both ADC group regular
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode
+  * @param  ADCx ADC instance
+  * @param  Continuous This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);
+}
+
+/**
+  * @brief  Get ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));
+}
+
+/**
+  * @brief  Set ADC group regular conversion data transfer: no transfer or
+  *         transfer by DMA, and DMA requests mode.
+  * @note   If transfer by DMA selected, specifies the DMA requests
+  *         mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *        (overrun flag and interruption if enabled).
+  * @note   For devices with several ADC instances: ADC multimode DMA
+  *         settings are available using function @ref LL_ADC_SetMultiDMATransfer().
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_ADC_DMA_GetRegAddr().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     DMAEN          LL_ADC_REG_SetDMATransfer\n
+  *         CFGR     DMACFG         LL_ADC_REG_SetDMATransfer
+  * @param  ADCx ADC instance
+  * @param  DMATransfer This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG, DMATransfer);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data transfer: no transfer or
+  *         transfer by DMA, and DMA requests mode.
+  * @note   If transfer by DMA selected, specifies the DMA requests
+  *         mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   For devices with several ADC instances: ADC multimode DMA
+  *         settings are available using function @ref LL_ADC_GetMultiDMATransfer().
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_ADC_DMA_GetRegAddr().
+  * @rmtoll CFGR     DMAEN          LL_ADC_REG_GetDMATransfer\n
+  *         CFGR     DMACFG         LL_ADC_REG_GetDMATransfer
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMAEN | ADC_CFGR_DMACFG));
+}
+
+/**
+  * @brief  Set ADC group regular behavior in case of overrun:
+  *         data preserved or overwritten.
+  * @note   Compatibility with devices without feature overrun:
+  *         other devices without this feature have a behavior
+  *         equivalent to data overwritten.
+  *         The default setting of overrun is data preserved.
+  *         Therefore, for compatibility with all devices, parameter
+  *         overrun should be set to data overwritten.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun
+  * @param  ADCx ADC instance
+  * @param  Overrun This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);
+}
+
+/**
+  * @brief  Get ADC group regular behavior in case of overrun:
+  *         data preserved or overwritten.
+  * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected
+  * @{
+  */
+
+/**
+  * @brief  Set ADC group injected conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   On this STM32 series, setting trigger source to external trigger
+  *         also set trigger polarity to rising edge
+  *         (default setting for compatibility with some ADC on other
+  *         STM32 series having this setting set by HW default value).
+  *         In case of need to modify trigger edge, use
+  *         function @ref LL_ADC_INJ_SetTriggerEdge().
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n
+  *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+  *
+  *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+  *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
+  *             more details.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   To determine whether group injected trigger source is
+  *         internal (SW start) or external, without detail
+  *         of which peripheral is selected as external trigger,
+  *         (equivalent to
+  *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")
+  *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n
+  *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+  *
+  *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+  *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
+  *             more details.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(const ADC_TypeDef *ADCx)
+{
+  __IO uint32_t trigger_source = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);
+
+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+  /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */
+  uint32_t shift_jexten = ((trigger_source & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+  /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */
+  /* to match with triggers literals definition.                              */
+  return ((trigger_source
+           & (ADC_INJ_TRIG_SOURCE_MASK >> shift_jexten) & ADC_JSQR_JEXTSEL)
+          | ((ADC_INJ_TRIG_EDGE_MASK >> shift_jexten) & ADC_JSQR_JEXTEN)
+         );
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger source internal (SW start)
+            or external
+  * @note   In case of group injected trigger source set to external trigger,
+  *         to determine which peripheral is selected as external trigger,
+  *         use function @ref LL_ADC_INJ_GetTriggerSource.
+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart
+  * @param  ADCx ADC instance
+  * @retval Value "0" if trigger source external trigger
+  *         Value "1" if trigger source SW start.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set ADC group injected conversion trigger polarity.
+  *         Applicable only for trigger source set to external trigger.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge
+  * @param  ADCx ADC instance
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger polarity.
+  *         Applicable only for trigger source set to external trigger.
+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));
+}
+
+/**
+  * @brief  Set ADC group injected sequencer length and scan direction.
+  * @note   This function performs configuration of:
+  *         - Sequence length: Number of ranks in the scan sequence.
+  *         - Sequence direction: Unless specified in parameters, sequencer
+  *           scan direction is forward (from rank 1 to rank n).
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength
+  * @param  ADCx ADC instance
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);
+}
+
+/**
+  * @brief  Get ADC group injected sequencer length and scan direction.
+  * @note   This function retrieves:
+  *         - Sequence length: Number of ranks in the scan sequence.
+  *         - Sequence direction: Unless specified in parameters, sequencer
+  *           scan direction is forward (from rank 1 to rank n).
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));
+}
+
+/**
+  * @brief  Set ADC group injected sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @note   It is not possible to enable both ADC group injected
+  *         auto-injected mode and sequencer discontinuous mode.
+  * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @param  SeqDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);
+}
+
+/**
+  * @brief  Get ADC group injected sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));
+}
+
+/**
+  * @brief  Set ADC group injected sequence: channel on the selected
+  *         sequence rank.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On STM32G4, some fast channels are available: fast analog inputs
+  *         coming from GPIO pads (ADC_IN1..5).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n
+  *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+  /* Set bits with content of parameter "Channel" with bits position          */
+  /* in register depending on parameter "Rank".                               */
+  /* Parameters "Rank" and "Channel" are used with masks because containing   */
+  /* other bits reserved for other purpose.                                   */
+  MODIFY_REG(ADCx->JSQR,
+             (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+             << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),
+             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+             << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));
+}
+
+/**
+  * @brief  Get ADC group injected sequence: channel on the selected
+  *         sequence rank.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n
+  *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n
+  *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n
+  *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
+  *             more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  *         (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
+  *                      comparison with internal channel parameter to be done
+  *                      using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  return (uint32_t)((READ_BIT(ADCx->JSQR,
+                              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+                              << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))
+                     >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS
+                   );
+}
+
+/**
+  * @brief  Set ADC group injected conversion trigger:
+  *         independent or from ADC group regular.
+  * @note   This mode can be used to extend number of data registers
+  *         updated after one ADC conversion trigger and with data
+  *         permanently kept (not erased by successive conversions of scan of
+  *         ADC sequencer ranks), up to 5 data registers:
+  *         1 data register on ADC group regular, 4 data registers
+  *         on ADC group injected.
+  * @note   If ADC group injected injected trigger source is set to an
+  *         external trigger, this feature must be must be set to
+  *         independent trigger.
+  *         ADC group injected automatic trigger is compliant only with
+  *         group injected trigger source set to SW start, without any
+  *         further action on  ADC group injected conversion start or stop:
+  *         in this case, ADC group injected is controlled only
+  *         from ADC group regular.
+  * @note   It is not possible to enable both ADC group injected
+  *         auto-injected mode and sequencer discontinuous mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto
+  * @param  ADCx ADC instance
+  * @param  TrigAuto This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);
+}
+
+/**
+  * @brief  Get ADC group injected conversion trigger:
+  *         independent or from ADC group regular.
+  * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT
+  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));
+}
+
+/**
+  * @brief  Set ADC group injected contexts queue mode.
+  * @note   A context is a setting of group injected sequencer:
+  *         - group injected trigger
+  *         - sequencer length
+  *         - sequencer ranks
+  *         If contexts queue is disabled:
+  *         - only 1 sequence can be configured
+  *           and is active perpetually.
+  *         If contexts queue is enabled:
+  *         - up to 2 contexts can be queued
+  *           and are checked in and out as a FIFO stack (first-in, first-out).
+  *         - If a new context is set when queues is full, error is triggered
+  *           by interruption "Injected Queue Overflow".
+  *         - Two behaviors are possible when all contexts have been processed:
+  *           the contexts queue can maintain the last context active perpetually
+  *           or can be empty and injected group triggers are disabled.
+  *         - Triggers can be only external (not internal SW start)
+  *         - Caution: The sequence must be fully configured in one time
+  *           (one write of register JSQR makes a check-in of a new context
+  *           into the queue).
+  *           Therefore functions to set separately injected trigger and
+  *           sequencer channels cannot be used, register JSQR must be set
+  *           using function @ref LL_ADC_INJ_ConfigQueueContext().
+  * @note   This parameter can be modified only when no conversion is on going
+  *         on either groups regular or injected.
+  * @note   A modification of the context mode (bit JQDIS) causes the contexts
+  *         queue to be flushed and the register JSQR is cleared.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n
+  *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode
+  * @param  ADCx ADC instance
+  * @param  QueueMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)
+{
+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);
+}
+
+/**
+  * @brief  Get ADC group injected context queue mode.
+  * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n
+  *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE
+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE
+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));
+}
+
+/**
+  * @brief  Set one context on ADC group injected that will be checked in
+  *         contexts queue.
+  * @note   A context is a setting of group injected sequencer:
+  *         - group injected trigger
+  *         - sequencer length
+  *         - sequencer ranks
+  *         This function is intended to be used when contexts queue is enabled,
+  *         because the sequence must be fully configured in one time
+  *         (functions to set separately injected trigger and sequencer channels
+  *         cannot be used):
+  *         Refer to function @ref LL_ADC_INJ_SetQueueMode().
+  * @note   In the contexts queue, only the active context can be read.
+  *         The parameters of this function can be read using functions:
+  *         @arg @ref LL_ADC_INJ_GetTriggerSource()
+  *         @arg @ref LL_ADC_INJ_GetTriggerEdge()
+  *         @arg @ref LL_ADC_INJ_GetSequencerRanks()
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On STM32G4, some fast channels are available: fast analog inputs
+  *         coming from GPIO pads (ADC_IN1..5).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must not be disabled. Can be enabled with or without conversion
+  *         on going on either groups regular or injected.
+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n
+  *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH3         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4         (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH3         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_CH4         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH2         (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM16_CH1        (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH2        (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM20_CH4        (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE3       (2)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15      (1)
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM_OUT
+  *
+  *         (1) On STM32G4 series, parameter not available on all ADC instances: ADC1, ADC2.\n
+  *         (2) On STM32G4 series, parameter not available on all ADC instances: ADC3, ADC4, ADC5.
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet for
+  *             more details.
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING
+  *
+  *         Note: This parameter is discarded in case of SW start:
+  *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS
+  * @param  Rank1_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  * @param  Rank2_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  * @param  Rank3_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  * @param  Rank4_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,
+                                                   uint32_t TriggerSource,
+                                                   uint32_t ExternalTriggerEdge,
+                                                   uint32_t SequencerNbRanks,
+                                                   uint32_t Rank1_Channel,
+                                                   uint32_t Rank2_Channel,
+                                                   uint32_t Rank3_Channel,
+                                                   uint32_t Rank4_Channel)
+{
+  /* Set bits with content of parameter "Rankx_Channel" with bits position    */
+  /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */
+  /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */
+  /* because containing other bits reserved for other purpose.                */
+  /* If parameter "TriggerSource" is set to SW start, then parameter          */
+  /* "ExternalTriggerEdge" is discarded.                                      */
+  uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);
+  MODIFY_REG(ADCx->JSQR,
+             ADC_JSQR_JEXTSEL |
+             ADC_JSQR_JEXTEN  |
+             ADC_JSQR_JSQ4    |
+             ADC_JSQR_JSQ3    |
+             ADC_JSQR_JSQ2    |
+             ADC_JSQR_JSQ1    |
+             ADC_JSQR_JL,
+             (TriggerSource & ADC_JSQR_JEXTSEL)          |
+             (ExternalTriggerEdge * (is_trigger_not_sw)) |
+             (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+              << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+             (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+              << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+             (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+              << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+             (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+              << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |
+             SequencerNbRanks
+            );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+  * @{
+  */
+
+/**
+  * @brief  Set sampling time of the selected ADC channel
+  *         Unit: ADC clock cycles.
+  * @note   On this device, sampling time is on channel scope: independently
+  *         of channel mapped on ADC group regular or injected.
+  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
+  *         converted:
+  *         sampling time constraints must be respected (sampling time can be
+  *         adjusted in function of ADC clock frequency and sampling time
+  *         setting).
+  *         Refer to device datasheet for timings values (parameters TS_vrefint,
+  *         TS_temp, ...).
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         On this STM32 series, ADC processing time is:
+  *         - 12.5 ADC clock cycles at ADC resolution 12 bits
+  *         - 10.5 ADC clock cycles at ADC resolution 10 bits
+  *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+  *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+  * @note   In case of ADC conversion of internal channel (VrefInt,
+  *         temperature sensor, ...), a sampling time minimum value
+  *         is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n
+  *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  * @param  SamplingTime This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)
+  *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
+  *
+  *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles
+  *             can be replaced by 3.5 ADC clock cycles.
+  *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
+{
+  /* Set bits with content of parameter "SamplingTime" with bits position     */
+  /* in register and register position depending on parameter "Channel".      */
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
+                                             ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
+
+  MODIFY_REG(*preg,
+             ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
+             SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
+}
+
+/**
+  * @brief  Get sampling time of the selected ADC channel
+  *         Unit: ADC clock cycles.
+  * @note   On this device, sampling time is on channel scope: independently
+  *         of channel mapped on ADC group regular or injected.
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         On this STM32 series, ADC processing time is:
+  *         - 12.5 ADC clock cycles at ADC resolution 12 bits
+  *         - 10.5 ADC clock cycles at ADC resolution 10 bits
+  *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+  *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+  * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n
+  *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_2                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_3                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_4                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_5                 (8)
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_VREFINT           (7)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC1   (1)
+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR_ADC5   (5)
+  *         @arg @ref LL_ADC_CHANNEL_VBAT              (6)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP1           (1)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP2           (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC2      (2)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP3_ADC3      (3)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP4           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP5           (5)
+  *         @arg @ref LL_ADC_CHANNEL_VOPAMP6           (4)
+  *
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  *         (8) On STM32G4, fast channel allows: 2.5 (sampling) + 12.5 (conversion) = 15 ADC clock cycles (fADC) to
+  *             convert in 12-bit resolution.
+  *             Other channels are slow channels  allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
+  *             (fADC) to convert in 12-bit resolution.\n
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5   (1)
+  *         @arg @ref LL_ADC_SAMPLINGTIME_6CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_24CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_47CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_92CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_247CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_640CYCLES_5
+  *
+  *         (1) On some devices, ADC sampling time 2.5 ADC clock cycles
+  *             can be replaced by 3.5 ADC clock cycles.
+  *             Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK)
+                                                                 >> ADC_SMPRX_REGOFFSET_POS));
+
+  return (uint32_t)(READ_BIT(*preg,
+                             ADC_SMPR1_SMP0
+                             << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))
+                    >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)
+                   );
+}
+
+/**
+  * @brief  Set mode single-ended or differential input of the selected
+  *         ADC channel.
+  * @note   Channel ending is on channel scope: independently of channel mapped
+  *         on ADC group regular or injected.
+  *         In differential mode: Differential measurement is carried out
+  *         between the selected channel 'i' (positive input) and
+  *         channel 'i+1' (negative input). Only channel 'i' has to be
+  *         configured, channel 'i+1' is configured automatically.
+  * @note   Refer to Reference Manual to ensure the selected channel is
+  *         available in differential mode.
+  *         For example, internal channels (VrefInt, TempSensor, ...) are
+  *         not available in differential mode.
+  * @note   When configuring a channel 'i' in differential mode,
+  *         the channel 'i+1' is not usable separately.
+  * @note   On STM32G4, some channels are internally fixed to single-ended inputs
+  *         configuration:
+  *         - ADC1: Channels 12, 15, 16, 17 and 18
+  *         - ADC2: Channels 15, 17 and 18
+  *         - ADC3: Channels 12, 16, 17 and 18            (1)
+  *         - ADC4: Channels 16, 17 and 18                (1)
+  *         - ADC5: Channels 2, 3, 4, 16, 17 and 18       (1)
+  *         (1) ADC3/4/5 are not available on all devices, refer to device datasheet
+  *             for more details.
+  * @note   For ADC channels configured in differential mode, both inputs
+  *         should be biased at (Vref+)/2 +/-200mV.
+  *         (Vref+ is the analog voltage reference)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll DIFSEL   DIFSEL         LL_ADC_SetChannelSingleDiff
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  * @param  SingleDiff This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
+{
+  /* Bits of channels in single or differential mode are set only for         */
+  /* differential mode (for single mode, mask of bits allowed to be set is    */
+  /* shifted out of range of bits of channels in single or differential mode. */
+  MODIFY_REG(ADCx->DIFSEL,
+             Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
+             (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
+             & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
+}
+
+/**
+  * @brief  Get mode single-ended or differential input of the selected
+  *         ADC channel.
+  * @note   When configuring a channel 'i' in differential mode,
+  *         the channel 'i+1' is not usable separately.
+  *         Therefore, to ensure a channel is configured in single-ended mode,
+  *         the configuration of channel itself and the channel 'i-1' must be
+  *         read back (to ensure that the selected channel channel has not been
+  *         configured in differential mode by the previous channel).
+  * @note   Refer to Reference Manual to ensure the selected channel is
+  *         available in differential mode.
+  *         For example, internal channels (VrefInt, TempSensor, ...) are
+  *         not available in differential mode.
+  * @note   When configuring a channel 'i' in differential mode,
+  *         the channel 'i+1' is not usable separately.
+  * @note   On STM32G4, some channels are internally fixed to single-ended inputs
+  *         configuration:
+  *         - ADC1: Channels 12, 15, 16, 17 and 18
+  *         - ADC2: Channels 15, 17 and 18
+  *         - ADC3: Channels 12, 16, 17 and 18            (1)
+  *         - ADC4: Channels 16, 17 and 18                (1)
+  *         - ADC5: Channels 2, 3, 4, 16, 17 and 18       (1)
+  *         (1) ADC3/4/5 are not available on all devices, refer to device datasheet
+  *             for more details.
+  * @note   One or several values can be selected. In this case, the value
+  *         returned is null if all channels are in single ended-mode.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSingleDiff
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  * @retval 0: channel in single-ended mode, else: channel in differential mode
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(const ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+  * @{
+  */
+
+/**
+  * @brief  Set ADC analog watchdog monitored channels:
+  *         a single channel, multiple channels or all channels,
+  *         on ADC groups regular and-or injected.
+  * @note   Once monitored channels are selected, analog watchdog
+  *         is enabled.
+  * @note   In case of need to define a single channel to monitor
+  *         with analog watchdog from sequencer channel definition,
+  *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+  * @note   On this STM32 series, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+  *             the 2 LSB are ignored.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n
+  *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
+  *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDChannelGroup This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG  (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_INJ  (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC1_REG_INJ (1)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG  (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_INJ  (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_ADC5_REG_INJ (5)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(6)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(6)
+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (6)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_INJ          (0)(1)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP1_REG_INJ         (1)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG          (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_INJ          (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP2_REG_INJ         (2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG     (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_INJ     (0)(2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC2_REG_INJ    (2)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG     (0)(3)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_INJ     (0)(3)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP3_ADC3_REG_INJ    (3)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_INJ          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP4_REG_INJ         (5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_INJ          (0)(5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP5_REG_INJ         (5)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG          (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_INJ          (0)(4)
+  *         @arg @ref LL_ADC_AWD_CH_VOPAMP6_REG_INJ         (4)
+  *
+  *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.\n
+  *         (1) On STM32G4, parameter available only on ADC instance: ADC1.\n
+  *         (2) On STM32G4, parameter available only on ADC instance: ADC2.\n
+  *         (3) On STM32G4, parameter available only on ADC instance: ADC3.\n
+  *         (4) On STM32G4, parameter available only on ADC instance: ADC4.\n
+  *         (5) On STM32G4, parameter available only on ADC instance: ADC5.\n
+  *         (6) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC5.\n
+  *         (7) On STM32G4, parameter available only on ADC instances: ADC1, ADC3, ADC4, ADC5.\n
+  *             On this STM32 series, all ADCx are not available on all devices. Refer to device datasheet
+  *             for more details.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
+{
+  /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
+  /* in register and register position depending on parameter "AWDy".         */
+  /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
+  /* containing other bits reserved for other purpose.                        */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
+                                             ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+                                             + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
+                                                * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+  MODIFY_REG(*preg,
+             (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+             AWDChannelGroup & AWDy);
+}
+
+/**
+  * @brief  Get ADC analog watchdog monitored channel.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Applicable only when the analog watchdog is set to monitor
+  *           one channel.
+  * @note   On this STM32 series, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+  *             the 2 LSB are ignored.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n
+  *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
+  *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2 (1)
+  *         @arg @ref LL_ADC_AWD3 (1)
+  *
+  *         (1) On this AWD number, monitored channel can be retrieved
+  *             if only 1 channel is programmed (or none or all channels).
+  *             This function cannot retrieve monitored channel if
+  *             multiple channels are programmed simultaneously
+  *             by bitfield.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ
+  *
+  *         (0) On STM32G4, parameter available only on analog watchdog number: AWD1.
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR,
+                                                   ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+                                                   + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
+                                                      * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+  uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
+
+  /* If "analog_wd_monit_channels" == 0, then the selected AWD is disabled       */
+  /* (parameter value LL_ADC_AWD_DISABLE).                                    */
+  /* Else, the selected AWD is enabled and is monitoring a group of channels  */
+  /* or a single channel.                                                     */
+  if (analog_wd_monit_channels != 0UL)
+  {
+    if (AWDy == LL_ADC_AWD1)
+    {
+      if ((analog_wd_monit_channels & ADC_CFGR_AWD1SGL) == 0UL)
+      {
+        /* AWD monitoring a group of channels */
+        analog_wd_monit_channels = ((analog_wd_monit_channels
+                                     | (ADC_AWD_CR23_CHANNEL_MASK)
+                                    )
+                                    & (~(ADC_CFGR_AWD1CH))
+                                   );
+      }
+      else
+      {
+        /* AWD monitoring a single channel */
+        analog_wd_monit_channels = (analog_wd_monit_channels
+                                    | (ADC_AWD2CR_AWD2CH_0 << (analog_wd_monit_channels >> ADC_CFGR_AWD1CH_Pos))
+                                   );
+      }
+    }
+    else
+    {
+      if ((analog_wd_monit_channels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
+      {
+        /* AWD monitoring a group of channels */
+        analog_wd_monit_channels = (ADC_AWD_CR23_CHANNEL_MASK
+                                    | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))
+                                   );
+      }
+      else
+      {
+        /* AWD monitoring a single channel */
+        /* AWD monitoring a group of channels */
+        analog_wd_monit_channels = (analog_wd_monit_channels
+                                    | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)
+                                    | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(analog_wd_monit_channels) << ADC_CFGR_AWD1CH_Pos)
+                                   );
+      }
+    }
+  }
+
+  return analog_wd_monit_channels;
+}
+
+/**
+  * @brief  Set ADC analog watchdog thresholds value of both thresholds
+  *         high and low.
+  * @note   If value of only one threshold high or low must be set,
+  *         use function @ref LL_ADC_SetAnalogWDThresholds().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @note   On this STM32 series, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+  *             the 2 LSB are ignored.
+  * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
+  *         impacted: the comparison of analog watchdog thresholds is done on
+  *         oversampling final computation (after ratio and shift application):
+  *         ADC data register bitfield [15:4] (12 most significant bits).
+  *         Examples:
+  *         - Oversampling ratio and shift selected to have ADC conversion data
+  *           on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
+  *           ADC analog watchdog thresholds must be divided by 16.
+  *         - Oversampling ratio and shift selected to have ADC conversion data
+  *           on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
+  *           ADC analog watchdog thresholds must be divided by 4.
+  *         - Oversampling ratio and shift selected to have ADC conversion data
+  *           on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
+  *           ADC analog watchdog thresholds match directly to ADC data register.
+  * @rmtoll TR1      HT1            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR2      HT2            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR3      HT3            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR1      LT1            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR2      LT2            LL_ADC_ConfigAnalogWDThresholds\n
+  *         TR3      LT3            LL_ADC_ConfigAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
+                                                     uint32_t AWDThresholdLowValue)
+{
+  /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
+  /* position in register and register position depending on parameter        */
+  /* "AWDy".                                                                  */
+  /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
+  /* containing other bits reserved for other purpose.                        */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+                                             ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+
+  MODIFY_REG(*preg,
+             ADC_TR1_HT1 | ADC_TR1_LT1,
+             (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
+}
+
+/**
+  * @brief  Set ADC analog watchdog threshold value of threshold
+  *         high or low.
+  * @note   If values of both thresholds high or low must be set,
+  *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @note   On this STM32 series, there are 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC groups regular and-or injected.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is
+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits
+  *             the 2 LSB are ignored.
+  * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
+  *         impacted: the comparison of analog watchdog thresholds is done on
+  *         oversampling final computation (after ratio and shift application):
+  *         ADC data register bitfield [15:4] (12 most significant bits).
+  *         Examples:
+  *         - Oversampling ratio and shift selected to have ADC conversion data
+  *           on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
+  *           ADC analog watchdog thresholds must be divided by 16.
+  *         - Oversampling ratio and shift selected to have ADC conversion data
+  *           on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
+  *           ADC analog watchdog thresholds must be divided by 4.
+  *         - Oversampling ratio and shift selected to have ADC conversion data
+  *           on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
+  *           ADC analog watchdog thresholds match directly to ADC data register.
+  * @note   On this STM32 series, setting of this feature is not conditioned to
+  *         ADC state:
+  *         ADC can be disabled, enabled with or without conversion on going
+  *         on either ADC groups regular or injected.
+  * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n
+  *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n
+  *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n
+  *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n
+  *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n
+  *         TR3      LT3            LL_ADC_SetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
+                                                  uint32_t AWDThresholdValue)
+{
+  /* Set bits with content of parameter "AWDThresholdValue" with bits         */
+  /* position in register and register position depending on parameters       */
+  /* "AWDThresholdsHighLow" and "AWDy".                                       */
+  /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
+  /* containing other bits reserved for other purpose.                        */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+                                             ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+
+  MODIFY_REG(*preg,
+             AWDThresholdsHighLow,
+             AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
+}
+
+/**
+  * @brief  Get ADC analog watchdog threshold value of threshold high,
+  *         threshold low or raw data with ADC thresholds high and low
+  *         concatenated.
+  * @note   If raw data with ADC thresholds high and low is retrieved,
+  *         the data of each threshold high or low can be isolated
+  *         using helper macro:
+  *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+  * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n
+  *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n
+  *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n
+  *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n
+  *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n
+  *         TR3      LT3            LL_ADC_GetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx,
+                                                      uint32_t AWDy, uint32_t AWDThresholdsHighLow)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->TR1,
+                                                   ((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS));
+
+  return (uint32_t)(READ_BIT(*preg,
+                             (AWDThresholdsHighLow | ADC_TR1_LT1))
+                    >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)
+                        & ~(AWDThresholdsHighLow & ADC_TR1_LT1)));
+}
+
+/**
+  * @brief  Set ADC analog watchdog filtering configuration
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @note   On this STM32 series, this feature is only available on first
+  *         analog watchdog (AWD1)
+  * @rmtoll TR1      AWDFILT        LL_ADC_SetAWDFilteringConfiguration
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  * @param  FilteringConfig This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_FILTERING_NONE
+  *         @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAWDFilteringConfiguration(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t FilteringConfig)
+{
+  /* Prevent unused argument(s) compilation warning */
+  (void)(AWDy);
+  MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT, FilteringConfig);
+}
+
+/**
+  * @brief  Get ADC analog watchdog filtering configuration
+  * @note   On this STM32 series, this feature is only available on first
+  *         analog watchdog (AWD1)
+  * @rmtoll TR1      AWDFILT        LL_ADC_GetAWDFilteringConfiguration
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  * @retval Returned value can be:
+  *         @arg @ref LL_ADC_AWD_FILTERING_NONE
+  *         @arg @ref LL_ADC_AWD_FILTERING_2SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_3SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_4SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_5SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_6SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_7SAMPLES
+  *         @arg @ref LL_ADC_AWD_FILTERING_8SAMPLES
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAWDFilteringConfiguration(const ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+  /* Prevent unused argument(s) compilation warning */
+  (void)(AWDy);
+  return (uint32_t)(READ_BIT(ADCx->TR1, ADC_TR1_AWDFILT));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
+  * @{
+  */
+
+/**
+  * @brief  Set ADC oversampling scope: ADC groups regular and-or injected
+  *         (availability of ADC group injected depends on STM32 series).
+  * @note   If both groups regular and injected are selected,
+  *         specify behavior of ADC group injected interrupting
+  *         group regular: when ADC group injected is triggered,
+  *         the oversampling on ADC group regular is either
+  *         temporary stopped and continued, or resumed from start
+  *         (oversampler buffer reset).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n
+  *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n
+  *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope
+  * @param  ADCx ADC instance
+  * @param  OvsScope This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_DISABLE
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+  *         @arg @ref LL_ADC_OVS_GRP_INJECTED
+  *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);
+}
+
+/**
+  * @brief  Get ADC oversampling scope: ADC groups regular and-or injected
+  *         (availability of ADC group injected depends on STM32 series).
+  * @note   If both groups regular and injected are selected,
+  *         specify behavior of ADC group injected interrupting
+  *         group regular: when ADC group injected is triggered,
+  *         the oversampling on ADC group regular is either
+  *         temporary stopped and continued, or resumed from start
+  *         (oversampler buffer reset).
+  * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n
+  *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n
+  *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_DISABLE
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED
+  *         @arg @ref LL_ADC_OVS_GRP_INJECTED
+  *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));
+}
+
+/**
+  * @brief  Set ADC oversampling discontinuous mode (triggered mode)
+  *         on the selected ADC group.
+  * @note   Number of oversampled conversions are done either in:
+  *         - continuous mode (all conversions of oversampling ratio
+  *           are done from 1 trigger)
+  *         - discontinuous mode (each conversion of oversampling ratio
+  *           needs a trigger)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @note   On this STM32 series, oversampling discontinuous mode
+  *         (triggered mode) can be used only when oversampling is
+  *         set on group regular only and in resumed mode.
+  * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont
+  * @param  ADCx ADC instance
+  * @param  OverSamplingDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_REG_CONT
+  *         @arg @ref LL_ADC_OVS_REG_DISCONT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);
+}
+
+/**
+  * @brief  Get ADC oversampling discontinuous mode (triggered mode)
+  *         on the selected ADC group.
+  * @note   Number of oversampled conversions are done either in:
+  *         - continuous mode (all conversions of oversampling ratio
+  *           are done from 1 trigger)
+  *         - discontinuous mode (each conversion of oversampling ratio
+  *           needs a trigger)
+  * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_REG_CONT
+  *         @arg @ref LL_ADC_OVS_REG_DISCONT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));
+}
+
+/**
+  * @brief  Set ADC oversampling
+  *         (impacting both ADC groups regular and injected)
+  * @note   This function set the 2 items of oversampling configuration:
+  *         - ratio
+  *         - shift
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
+  *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
+  * @param  ADCx ADC instance
+  * @param  Ratio This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_RATIO_2
+  *         @arg @ref LL_ADC_OVS_RATIO_4
+  *         @arg @ref LL_ADC_OVS_RATIO_8
+  *         @arg @ref LL_ADC_OVS_RATIO_16
+  *         @arg @ref LL_ADC_OVS_RATIO_32
+  *         @arg @ref LL_ADC_OVS_RATIO_64
+  *         @arg @ref LL_ADC_OVS_RATIO_128
+  *         @arg @ref LL_ADC_OVS_RATIO_256
+  * @param  Shift This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
+{
+  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
+}
+
+/**
+  * @brief  Get ADC oversampling ratio
+  *        (impacting both ADC groups regular and injected)
+  * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
+  * @param  ADCx ADC instance
+  * @retval Ratio This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_RATIO_2
+  *         @arg @ref LL_ADC_OVS_RATIO_4
+  *         @arg @ref LL_ADC_OVS_RATIO_8
+  *         @arg @ref LL_ADC_OVS_RATIO_16
+  *         @arg @ref LL_ADC_OVS_RATIO_32
+  *         @arg @ref LL_ADC_OVS_RATIO_64
+  *         @arg @ref LL_ADC_OVS_RATIO_128
+  *         @arg @ref LL_ADC_OVS_RATIO_256
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
+}
+
+/**
+  * @brief  Get ADC oversampling shift
+  *        (impacting both ADC groups regular and injected)
+  * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
+  * @param  ADCx ADC instance
+  * @retval Shift This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode
+  * @{
+  */
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Set ADC multimode configuration to operate in independent mode
+  *         or multimode (for devices with several ADC instances).
+  * @note   If multimode configuration: the selected ADC instance is
+  *         either master or slave depending on hardware.
+  *         Refer to reference manual.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      DUAL           LL_ADC_SetMultimode
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  Multimode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);
+}
+
+/**
+  * @brief  Get ADC multimode configuration to operate in independent mode
+  *         or multimode (for devices with several ADC instances).
+  * @note   If multimode configuration: the selected ADC instance is
+  *         either master or slave depending on hardware.
+  *         Refer to reference manual.
+  * @rmtoll CCR      DUAL           LL_ADC_GetMultimode
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_INDEPENDENT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT
+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
+}
+
+/**
+  * @brief  Set ADC multimode conversion data transfer: no transfer
+  *         or transfer by DMA.
+  * @note   If ADC multimode transfer by DMA is not selected:
+  *         each ADC uses its own DMA channel, with its individual
+  *         DMA transfer settings.
+  *         If ADC multimode transfer by DMA is selected:
+  *         One DMA channel is used for both ADC (DMA of ADC master)
+  *         Specifies the DMA requests mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   How to retrieve multimode conversion data:
+  *         Whatever multimode transfer by DMA setting: using function
+  *         @ref LL_ADC_REG_ReadMultiConversionData32().
+  *         If ADC multimode transfer by DMA is selected: conversion data
+  *         is a raw data with ADC master and slave concatenated.
+  *         A macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled
+  *         or enabled without conversion on going on group regular.
+  * @rmtoll CCR      MDMA           LL_ADC_SetMultiDMATransfer\n
+  *         CCR      DMACFG         LL_ADC_SetMultiDMATransfer
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  MultiDMATransfer This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG, MultiDMATransfer);
+}
+
+/**
+  * @brief  Get ADC multimode conversion data transfer: no transfer
+  *         or transfer by DMA.
+  * @note   If ADC multimode transfer by DMA is not selected:
+  *         each ADC uses its own DMA channel, with its individual
+  *         DMA transfer settings.
+  *         If ADC multimode transfer by DMA is selected:
+  *         One DMA channel is used for both ADC (DMA of ADC master)
+  *         Specifies the DMA requests mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   How to retrieve multimode conversion data:
+  *         Whatever multimode transfer by DMA setting: using function
+  *         @ref LL_ADC_REG_ReadMultiConversionData32().
+  *         If ADC multimode transfer by DMA is selected: conversion data
+  *         is a raw data with ADC master and slave concatenated.
+  *         A macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  * @rmtoll CCR      MDMA           LL_ADC_GetMultiDMATransfer\n
+  *         CCR      DMACFG         LL_ADC_GetMultiDMATransfer
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B
+  *         @arg @ref LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG));
+}
+
+/**
+  * @brief  Set ADC multimode delay between 2 sampling phases.
+  * @note   The sampling delay range depends on ADC resolution:
+  *         - ADC resolution 12 bits can have maximum delay of 12 cycles.
+  *         - ADC resolution 10 bits can have maximum delay of 10 cycles.
+  *         - ADC resolution  8 bits can have maximum delay of  8 cycles.
+  *         - ADC resolution  6 bits can have maximum delay of  6 cycles.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  MultiTwoSamplingDelay This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+  *
+  *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+  *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+  *         (3) Parameter available only if ADC resolution is 12 bits.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);
+}
+
+/**
+  * @brief  Get ADC multimode delay between 2 sampling phases.
+  * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (1)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES  (1)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES (2)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES (3)
+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES (3)
+  *
+  *         (1) Parameter available only if ADC resolution is 12, 10 or 8 bits.\n
+  *         (2) Parameter available only if ADC resolution is 12 or 10 bits.\n
+  *         (3) Parameter available only if ADC resolution is 12 bits.
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Put ADC instance in deep power down state.
+  * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
+  *         state, the internal analog calibration is lost. After exiting from
+  *         deep power down, calibration must be relaunched or calibration factor
+  *         (preliminarily saved) must be set back into calibration register.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_DEEPPWD);
+}
+
+/**
+  * @brief  Disable ADC deep power down mode.
+  * @note   In case of ADC calibration necessary: When ADC is in deep-power-down
+  *         state, the internal analog calibration is lost. After exiting from
+  *         deep power down, calibration must be relaunched or calibration factor
+  *         (preliminarily saved) must be set back into calibration register.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+  * @brief  Get the selected ADC instance deep power down state.
+  * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: deep power down is disabled, 1: deep power down is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable ADC instance internal voltage regulator.
+  * @note   On this STM32 series, after ADC internal voltage regulator enable,
+  *         a delay for ADC internal voltage regulator stabilization
+  *         is required before performing a ADC calibration or ADC enable.
+  *         Refer to device datasheet, parameter tADCVREG_STUP.
+  *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADVREGEN);
+}
+
+/**
+  * @brief  Disable ADC internal voltage regulator.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+  * @brief  Get the selected ADC instance internal voltage regulator state.
+  * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the selected ADC instance.
+  * @note   On this STM32 series, after ADC enable, a delay for
+  *         ADC internal analog stabilization is required before performing a
+  *         ADC conversion start.
+  *         Refer to device datasheet, parameter tSTAB.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
+  * @rmtoll CR       ADEN           LL_ADC_Enable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADEN);
+}
+
+/**
+  * @brief  Disable the selected ADC instance.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be not disabled. Must be enabled without conversion on going
+  *         on either groups regular or injected.
+  * @rmtoll CR       ADDIS          LL_ADC_Disable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADDIS);
+}
+
+/**
+  * @brief  Get the selected ADC instance enable state.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll CR       ADEN           LL_ADC_IsEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: ADC is disabled, 1: ADC is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the selected ADC instance disable state.
+  * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no ADC disable command on going.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Start ADC calibration in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   On this STM32 series, a minimum number of ADC clock cycles
+  *         are required between ADC end of calibration and ADC enable.
+  *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+  * @note   For devices with differential mode available:
+  *         Calibration of offset is specific to each of
+  *         single-ended and differential modes
+  *         (calibration run must be performed for each of these
+  *         differential modes, if used afterwards and if the application
+  *         requires their calibration).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n
+  *         CR       ADCALDIF       LL_ADC_StartCalibration
+  * @param  ADCx ADC instance
+  * @param  SingleDiff This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SINGLE_ENDED
+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t SingleDiff)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADCAL | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));
+}
+
+/**
+  * @brief  Get ADC calibration state.
+  * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
+  * @param  ADCx ADC instance
+  * @retval 0: calibration complete, 1: calibration in progress.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Start ADC group regular conversion.
+  * @note   On this STM32 series, this function is relevant for both
+  *         internal trigger (SW start) and external trigger:
+  *         - If ADC trigger has been set to software start, ADC conversion
+  *           starts immediately.
+  *         - If ADC trigger has been set to external trigger, ADC conversion
+  *           will start at next trigger event (on the selected trigger edge)
+  *           following the ADC start conversion command.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group regular,
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADSTART);
+}
+
+/**
+  * @brief  Stop ADC group regular conversion.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled with conversion on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADSTP);
+}
+
+/**
+  * @brief  Get ADC group regular conversion state.
+  * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get ADC group regular command of conversion stop state
+  * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no command of conversion stop is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Start ADC sampling phase for sampling time trigger mode
+  * @note   This function is relevant only when
+  *         - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+  *           using @ref LL_ADC_REG_SetSamplingMode
+  *         - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group regular,
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CFGR2    SWTRIG         LL_ADC_REG_StartSamplingPhase
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StartSamplingPhase(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+}
+
+/**
+  * @brief  Stop ADC sampling phase for sampling time trigger mode and start conversion
+  * @note   This function is relevant only when
+  *         - @ref LL_ADC_REG_SAMPLING_MODE_TRIGGER_CONTROLED has been set
+  *           using @ref LL_ADC_REG_SetSamplingMode
+  *         - @ref LL_ADC_REG_TRIG_SOFTWARE is used as trigger source
+  *         - @ref LL_ADC_REG_StartSamplingPhase has been called to start
+  *           the sampling phase
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group regular,
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CFGR2    SWTRIG         LL_ADC_REG_StopSamplingPhase
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StopSamplingPhase(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_SWTRIG);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         all ADC configurations: all ADC resolutions and
+  *         all oversampling increased data width (for devices
+  *         with feature oversampling).
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 12 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 10 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 8 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 6 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData6
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Get ADC multimode conversion data of ADC master, ADC slave
+  *         or raw data with ADC master and slave concatenated.
+  * @note   If raw data with ADC master and slave concatenated is retrieved,
+  *         a macro is available to get the conversion data of
+  *         ADC master or ADC slave: see helper macro
+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().
+  *         (however this macro is mainly intended for multimode
+  *         transfer by DMA, because this function can do the same
+  *         by getting multimode conversion data of ADC master or ADC slave
+  *         separately).
+  * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n
+  *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  ConversionData This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_MULTI_MASTER
+  *         @arg @ref LL_ADC_MULTI_SLAVE
+  *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(const ADC_Common_TypeDef *ADCxy_COMMON,
+                                                              uint32_t ConversionData)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,
+                             ConversionData)
+                    >> (POSITION_VAL(ConversionData) & 0x1FUL)
+                   );
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected
+  * @{
+  */
+
+/**
+  * @brief  Start ADC group injected conversion.
+  * @note   On this STM32 series, this function is relevant for both
+  *         internal trigger (SW start) and external trigger:
+  *         - If ADC trigger has been set to software start, ADC conversion
+  *           starts immediately.
+  *         - If ADC trigger has been set to external trigger, ADC conversion
+  *           will start at next trigger event (on the selected trigger edge)
+  *           following the ADC start conversion command.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group injected,
+  *         without conversion stop command on going on group injected,
+  *         without ADC disable command on going.
+  * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_JADSTART);
+}
+
+/**
+  * @brief  Stop ADC group injected conversion.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled with conversion on going on group injected,
+  *         without ADC disable command on going.
+  * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_JADSTP);
+}
+
+/**
+  * @brief  Get ADC group injected conversion state.
+  * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group injected.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get ADC group injected command of conversion stop state
+  * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no command of conversion stop is on going on ADC group injected.
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         all ADC configurations: all ADC resolutions and
+  *         all oversampling increased data width (for devices
+  *         with feature oversampling).
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
+                                                   ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint32_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 12 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
+                                                   ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint16_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 10 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
+                                                   ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint16_t)(READ_BIT(*preg,
+                             ADC_JDR1_JDATA)
+                   );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 8 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
+                                                   ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint8_t)(READ_BIT(*preg,
+                            ADC_JDR1_JDATA)
+                  );
+}
+
+/**
+  * @brief  Get ADC group injected conversion data, range fit for
+  *         ADC resolution 6 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.
+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData6\n
+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData6
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_INJ_RANK_1
+  *         @arg @ref LL_ADC_INJ_RANK_2
+  *         @arg @ref LL_ADC_INJ_RANK_3
+  *         @arg @ref LL_ADC_INJ_RANK_4
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData6(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1,
+                                                   ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));
+
+  return (uint8_t)(READ_BIT(*preg,
+                            ADC_JDR1_JDATA)
+                  );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+  * @{
+  */
+
+/**
+  * @brief  Get flag ADC ready.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular end of unitary conversion.
+  * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular end of sequence conversions.
+  * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular overrun.
+  * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular end of sampling phase.
+  * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group injected end of unitary conversion.
+  * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group injected end of sequence conversions.
+  * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group injected contexts queue overflow.
+  * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 1 flag
+  * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 2.
+  * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 3.
+  * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear flag ADC ready.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of unitary conversion.
+  * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of sequence conversions.
+  * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
+}
+
+/**
+  * @brief  Clear flag ADC group regular overrun.
+  * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of sampling phase.
+  * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
+}
+
+/**
+  * @brief  Clear flag ADC group injected end of unitary conversion.
+  * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);
+}
+
+/**
+  * @brief  Clear flag ADC group injected end of sequence conversions.
+  * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);
+}
+
+/**
+  * @brief  Clear flag ADC group injected contexts queue overflow.
+  * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 1.
+  * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 2.
+  * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 3.
+  * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Get flag multimode ADC ready of the ADC master.
+  * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC ready of the ADC slave.
+  * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.
+  * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.
+  * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.
+  * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.
+  * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular overrun of the ADC master.
+  * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular overrun of the ADC slave.
+  * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.
+  * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.
+  * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.
+  * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.
+  * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.
+  * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.
+  * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.
+  * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.
+  * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.
+  * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode analog watchdog 1 of the ADC slave.
+  * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.
+  * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.
+  * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.
+  * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.
+  * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of sequence conversions.
+  * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+  * @brief  Enable ADC group regular interruption overrun.
+  * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of sampling.
+  * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+  * @brief  Enable interruption ADC group injected end of unitary conversion.
+  * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+  * @brief  Enable interruption ADC group injected end of sequence conversions.
+  * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+  * @brief  Enable interruption ADC group injected context queue overflow.
+  * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 1.
+  * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 2.
+  * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 3.
+  * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+  * @brief  Disable interruption ADC ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of sequence conversions.
+  * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular overrun.
+  * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of sampling.
+  * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);
+}
+
+/**
+  * @brief  Disable interruption ADC group injected end of sequence conversions.
+  * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);
+}
+
+/**
+  * @brief  Disable interruption ADC group injected context queue overflow.
+  * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 1.
+  * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 2.
+  * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 3.
+  * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+  * @brief  Get state of interruption ADC ready
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of unitary conversion
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of sequence conversions
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular overrun
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of sampling
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group injected end of unitary conversion
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group injected end of sequence conversions
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group injected context queue overflow interrupt state
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC analog watchdog 1
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption Get ADC analog watchdog 2
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption Get ADC analog watchdog 3
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
+void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct);
+
+/* De-initialization of ADC instance, ADC group regular and ADC group injected */
+/* (availability of ADC group injected depends on STM32 series) */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct);
+void        LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
+void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct);
+
+/* Initialization of some features of ADC instance and ADC group injected */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
+void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_ADC_H */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_comp.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_comp.h
new file mode 100644
index 0000000..0a7ca2d
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_comp.h
@@ -0,0 +1,757 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_comp.h
+  * @author  MCD Application Team
+  * @brief   Header file of COMP LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_COMP_H
+#define STM32G4xx_LL_COMP_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+
+
+/** @defgroup COMP_LL COMP
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Private_Macros COMP Private Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of COMP instance.
+  */
+typedef struct
+{
+  uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).
+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_COMP_SetInputPlus(). */
+
+  uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).
+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS
+                                             This feature can be modified afterwards using unitary function
+                                              @ref LL_COMP_SetInputMinus(). */
+
+  uint32_t InputHysteresis;             /*!< Set comparator hysteresis mode of the input minus.
+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_COMP_SetInputHysteresis(). */
+
+  uint32_t OutputPolarity;              /*!< Set comparator output polarity.
+                                             This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_COMP_SetOutputPolarity(). */
+
+  uint32_t OutputBlankingSource;        /*!< Set comparator blanking source.
+                                             This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_COMP_SetOutputBlankingSource(). */
+
+} LL_COMP_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants
+  * @{
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection
+  * @{
+  */
+#define LL_COMP_INPUT_PLUS_IO1          (0x00000000UL)                          /*!< Comparator input plus connected to IO1 (pin PA1 for COMP1, pin PA7 for COMP2, pin PA0 for COMP3, pin PB0 for COMP4, pin PB13 for COMP5, pin PB11 for COMP6, pin PB14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_INPUT_PLUS_IO2          (COMP_CSR_INPSEL)                       /*!< Comparator input plus connected to IO2 (pin PB1 for COMP1, pin PA3 for COMP2, pin PC1 for COMP3, pin PE7 for COMP4, pin PD12 for COMP5, pin PD11 for COMP6, pin PD14 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection
+  * @{
+  */
+#define LL_COMP_INPUT_MINUS_1_4VREFINT  (                                                            COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/4 VrefInt  */
+#define LL_COMP_INPUT_MINUS_1_2VREFINT  (                                        COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 1/2 VrefInt  */
+#define LL_COMP_INPUT_MINUS_3_4VREFINT  (                    COMP_CSR_INMSEL_1                     | COMP_CSR_SCALEN | COMP_CSR_BRGEN)        /*!< Comparator input minus connected to 3/4 VrefInt  */
+#define LL_COMP_INPUT_MINUS_VREFINT     (                    COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0 | COMP_CSR_SCALEN                 )        /*!< Comparator input minus connected to VrefInt */
+#define LL_COMP_INPUT_MINUS_DAC1_CH1    (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 Channel 1 for COMP1/3/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define LL_COMP_INPUT_MINUS_DAC1_CH2    (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC1 Channel 2 for COMP2/5. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define LL_COMP_INPUT_MINUS_DAC2_CH1    (COMP_CSR_INMSEL_2                     | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to DAC2 Channel 1 for COMP6/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define LL_COMP_INPUT_MINUS_DAC3_CH1    (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC3 Channel 1 for COMP1/3. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define LL_COMP_INPUT_MINUS_DAC3_CH2    (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC3 Channel 2 for COMP2/4. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define LL_COMP_INPUT_MINUS_DAC4_CH1    (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC4 Channel 1 for COMP5/7. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define LL_COMP_INPUT_MINUS_DAC4_CH2    (COMP_CSR_INMSEL_2                                        )                                           /*!< Comparator input minus connected to DAC4 Channel 2 for COMP6. Note: For COMPx & DACx instances availability, please refer to datasheet */
+#define LL_COMP_INPUT_MINUS_IO1         (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1                    )                                           /*!< Comparator input minus connected to IO1 (pin PA4 for COMP1, pin PA5 for COMP2, pin PF1 for COMP3, pin PE8 for COMP4, pin PB10 for COMP5, pin PD10 for COMP6, pin PD15 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_INPUT_MINUS_IO2         (COMP_CSR_INMSEL_2 | COMP_CSR_INMSEL_1 | COMP_CSR_INMSEL_0)                                           /*!< Comparator input minus connected to IO2 (pin PA0 for COMP1, pin PA2 for COMP2, pin PC0 for COMP3, pin PB2 for COMP4, pin PD13 for COMP5, pin PB15 for COMP6, pin PB12 for COMP7). Note: For COMPx instance availability, please refer to datasheet */
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis
+  * @{
+  */
+#define LL_COMP_HYSTERESIS_NONE         (0x00000000UL)                                       /*!< No hysteresis */
+#define LL_COMP_HYSTERESIS_10MV         (                                    COMP_CSR_HYST_0) /*!< Hysteresis level 10mV */
+#define LL_COMP_HYSTERESIS_20MV         (                  COMP_CSR_HYST_1                  ) /*!< Hysteresis level 20mV */
+#define LL_COMP_HYSTERESIS_30MV         (                  COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 30mV */
+#define LL_COMP_HYSTERESIS_40MV         (COMP_CSR_HYST_2                                    ) /*!< Hysteresis level 40mV */
+#define LL_COMP_HYSTERESIS_50MV         (COMP_CSR_HYST_2                   | COMP_CSR_HYST_0) /*!< Hysteresis level 50mV */
+#define LL_COMP_HYSTERESIS_60MV         (COMP_CSR_HYST_2 | COMP_CSR_HYST_1                  ) /*!< Hysteresis level 60mV */
+#define LL_COMP_HYSTERESIS_70MV         (COMP_CSR_HYST_2 | COMP_CSR_HYST_1 | COMP_CSR_HYST_0) /*!< Hysteresis level 70mV */
+#define LL_COMP_HYSTERESIS_LOW          LL_COMP_HYSTERESIS_10MV /*!< Hysteresis level low */
+#define LL_COMP_HYSTERESIS_MEDIUM       LL_COMP_HYSTERESIS_40MV /*!< Hysteresis level medium */
+#define LL_COMP_HYSTERESIS_HIGH         LL_COMP_HYSTERESIS_70MV /*!< Hysteresis level high */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity
+  * @{
+  */
+#define LL_COMP_OUTPUTPOL_NONINVERTED   (0x00000000UL)          /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */
+#define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CSR_POLARITY)     /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source
+  * @{
+  */
+#define LL_COMP_BLANKINGSRC_NONE            (0x00000000UL)          /*!<Comparator output without blanking */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM1 OC5 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM2 OC3 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM2 OC4 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7  (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC3 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM3 OC4 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP1). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP2). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3  (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP3). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP5). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6  (                                            COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7  (                      COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM8 OC5 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4 (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM15 OC1 (specific to COMP instance: COMP4). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6 (                      COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM15 OC2 (specific to COMP instance: COMP6). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7 (COMP_CSR_BLANKING_2                                            )   /*!< Comparator output blanking source TIM15 OC3 (specific to COMP instance: COMP7). Note: For COMPx instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM20_OC5       (COMP_CSR_BLANKING_2 |                       COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM20 OC5 (Common to all COMP instances). Note: For TIM20 instance availability, please refer to datasheet */
+#define LL_COMP_BLANKINGSRC_TIM15_OC1       (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1                      )   /*!< Comparator output blanking source TIM15 OC1 (Common to all COMP instances). */
+#define LL_COMP_BLANKINGSRC_TIM4_OC3        (COMP_CSR_BLANKING_2 | COMP_CSR_BLANKING_1 | COMP_CSR_BLANKING_0)   /*!< Comparator output blanking source TIM4 OC3 (Common to all COMP instances). */
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level
+  * @{
+  */
+#define LL_COMP_OUTPUT_LEVEL_LOW        (0x00000000UL)          /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */
+#define LL_COMP_OUTPUT_LEVEL_HIGH       (0x00000001UL)          /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays
+  * @note   Only COMP peripheral HW delays are defined in COMP LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+
+/* Delay for comparator startup time.                                         */
+/* Note: Delay required to reach propagation delay specification.             */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define LL_COMP_DELAY_STARTUP_US          (  5UL) /*!< Delay for COMP startup time */
+
+/* Delay for comparator voltage scaler stabilization time.                    */
+/* Note: Voltage scaler is used when selecting comparator input               */
+/*       based on VrefInt: VrefInt or subdivision of VrefInt.                 */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART_SCALER").                                                */
+/* Unit: us                                                                   */
+#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL) /*!< Delay for COMP voltage scaler stabilization time */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros
+  * @{
+  */
+/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro
+  * @{
+  */
+
+/**
+  * @brief  Write a value in COMP register
+  * @param  __INSTANCE__ comparator instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in COMP register
+  * @param  __INSTANCE__ comparator instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions
+  * @{
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs
+  * @{
+  */
+
+/**
+  * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @note   On this STM32 series, scaler bridge is configurable:
+  *         to optimize power consumption, this function enables the
+  *         voltage scaler bridge only when required
+  *         (when selecting comparator input based on VrefInt: VrefInt or
+  *         subdivision of VrefInt).
+  *         - For scaler bridge power consumption values,
+  *           refer to device datasheet, parameter "IDDA(SCALER)".
+  *         - Voltage scaler requires a delay for voltage stabilization.
+  *           Refer to device datasheet, parameter "tSTART_SCALER".
+  *         - Scaler bridge is common for all comparator instances,
+  *           therefore if at least one of the comparator instance
+  *           is requiring the scaler bridge, it remains enabled.
+  * @rmtoll CSR      INMSEL         LL_COMP_ConfigInputs\n
+  *         CSR      INPSEL         LL_COMP_ConfigInputs\n
+  *         CSR      BRGEN          LL_COMP_ConfigInputs\n
+  *         CSR      SCALEN         LL_COMP_ConfigInputs
+  * @param  COMPx Comparator instance
+  * @param  InputMinus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1   (1,3,4)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2   (2,5)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1   (6,7)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH1   (1,3)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH2   (2,4)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH1   (5,7)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH2   (6)
+  *         (a,b...) Only available for COMPa, COMPb...
+  *                  For COMPx & DACx instances availability, please refer to datasheet
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2
+  * @param  InputPlus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)
+{
+  MODIFY_REG(COMPx->CSR,
+             COMP_CSR_INMSEL | COMP_CSR_INPSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN,
+             InputMinus | InputPlus);
+}
+
+/**
+  * @brief  Set comparator input plus (non-inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll CSR      INPSEL         LL_COMP_SetInputPlus
+  * @param  COMPx Comparator instance
+  * @param  InputPlus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_INPSEL, InputPlus);
+}
+
+/**
+  * @brief  Get comparator input plus (non-inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll CSR      INPSEL         LL_COMP_GetInputPlus
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1
+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(const COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INPSEL));
+}
+
+/**
+  * @brief  Set comparator input minus (inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @note   On this STM32 series, scaler bridge is configurable:
+  *         to optimize power consumption, this function enables the
+  *         voltage scaler bridge only when required
+  *         (when selecting comparator input based on VrefInt: VrefInt or
+  *         subdivision of VrefInt).
+  *         - For scaler bridge power consumption values,
+  *           refer to device datasheet, parameter "IDDA(SCALER)".
+  *         - Voltage scaler requires a delay for voltage stabilization.
+  *           Refer to device datasheet, parameter "tSTART_SCALER".
+  *         - Scaler bridge is common for all comparator instances,
+  *           therefore if at least one of the comparator instance
+  *           is requiring the scaler bridge, it remains enabled.
+  * @rmtoll CSR      INMSEL         LL_COMP_SetInputMinus\n
+  *         CSR      BRGEN          LL_COMP_SetInputMinus\n
+  *         CSR      SCALEN         LL_COMP_SetInputMinus
+  * @param  COMPx Comparator instance
+  * @param  InputMinus This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1   (1,3,4)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2   (2,5)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1   (6,7)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH1   (1,3)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH2   (2,4)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH1   (5,7)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH2   (6)
+  *         (a,b...) Only available for COMPa, COMPb...
+  *                  For COMPx & DACx instances availability, please refer to datasheet
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN, InputMinus);
+}
+
+/**
+  * @brief  Get comparator input minus (inverting).
+  * @note   In case of comparator input selected to be connected to IO:
+  *         GPIO pins are specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll CSR      INMSEL         LL_COMP_GetInputMinus\n
+  *         CSR      BRGEN          LL_COMP_GetInputMinus\n
+  *         CSR      SCALEN         LL_COMP_GetInputMinus
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1   (1,3,4)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2   (2,5)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC2_CH1   (6,7)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH1   (1,3)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC3_CH2   (2,4)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH1   (5,7)
+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC4_CH2   (6)
+  *         (a,b...) Only available for COMPa, COMPb...
+  *                  For COMPx & DACx instances availability, please refer to datasheet
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1
+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(const COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_INMSEL | COMP_CSR_SCALEN | COMP_CSR_BRGEN));
+}
+
+/**
+  * @brief  Set comparator instance hysteresis mode of the input minus (inverting input).
+  * @rmtoll CSR      HYST           LL_COMP_SetInputHysteresis
+  * @param  COMPx Comparator instance
+  * @param  InputHysteresis This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_HYSTERESIS_NONE
+  *         @arg @ref LL_COMP_HYSTERESIS_10MV
+  *         @arg @ref LL_COMP_HYSTERESIS_20MV
+  *         @arg @ref LL_COMP_HYSTERESIS_30MV
+  *         @arg @ref LL_COMP_HYSTERESIS_40MV
+  *         @arg @ref LL_COMP_HYSTERESIS_50MV
+  *         @arg @ref LL_COMP_HYSTERESIS_60MV
+  *         @arg @ref LL_COMP_HYSTERESIS_70MV
+  *         @arg @ref LL_COMP_HYSTERESIS_LOW
+  *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM
+  *         @arg @ref LL_COMP_HYSTERESIS_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_HYST, InputHysteresis);
+}
+
+/**
+  * @brief  Get comparator instance hysteresis mode of the minus (inverting) input.
+  * @rmtoll CSR      HYST           LL_COMP_GetInputHysteresis
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_HYSTERESIS_NONE
+  *         @arg @ref LL_COMP_HYSTERESIS_10MV
+  *         @arg @ref LL_COMP_HYSTERESIS_20MV
+  *         @arg @ref LL_COMP_HYSTERESIS_30MV
+  *         @arg @ref LL_COMP_HYSTERESIS_40MV
+  *         @arg @ref LL_COMP_HYSTERESIS_50MV
+  *         @arg @ref LL_COMP_HYSTERESIS_60MV
+  *         @arg @ref LL_COMP_HYSTERESIS_70MV
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(const COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_HYST));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output
+  * @{
+  */
+
+/**
+  * @brief  Set comparator instance output polarity.
+  * @rmtoll CSR      POLARITY       LL_COMP_SetOutputPolarity
+  * @param  COMPx Comparator instance
+  * @param  OutputPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+  *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_POLARITY, OutputPolarity);
+}
+
+/**
+  * @brief  Get comparator instance output polarity.
+  * @rmtoll CSR      POLARITY       LL_COMP_GetOutputPolarity
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED
+  *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(const COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_POLARITY));
+}
+
+/**
+  * @brief  Set comparator instance blanking source.
+  * @note   Blanking source may be specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @note   Availability of parameters of blanking source from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CSR      BLANKING       LL_COMP_SetOutputBlankingSource
+  * @param  COMPx Comparator instance
+  * @param  BlankingSource This parameter can be one of the following values:
+  *         @arg @ref LL_COMP_BLANKINGSRC_NONE
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM20_OC5
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM4_OC3
+  *
+  *         On STM32G4 series, blanking sources are linked to COMP instance (except
+  *         those without COMPx suffix that are common to all instances)
+  *         Note: For COMPx & TIMx instances availability, please refer to datasheet
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)
+{
+  MODIFY_REG(COMPx->CSR, COMP_CSR_BLANKING, BlankingSource);
+}
+
+/**
+  * @brief  Get comparator instance blanking source.
+  * @note   Availability of parameters of blanking source from timer
+  *         depends on timers availability on the selected device.
+  * @note   Blanking source may be specific to each comparator instance.
+  *         Refer to description of parameters or to reference manual.
+  * @rmtoll CSR      BLANKING       LL_COMP_GetOutputBlankingSource
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_BLANKINGSRC_NONE
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP1
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP2
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP3
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP4
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP5
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP6
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5_COMP7
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP1
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP2
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3_COMP5
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP3
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC4_COMP6
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP1
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP2
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP3
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP5
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3_COMP7
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4_COMP4
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP1
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP2
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP3
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP4
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP5
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP6
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5_COMP7
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1_COMP4
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP6
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC2_COMP7
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM20_OC5
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1
+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM4_OC3
+  *
+  *         On STM32G4 series, blanking sources are linked to COMP instance (except
+  *         those without COMPx suffix that are common to all instances)
+  *         Note: For COMPx & TIMx instances availability, please refer to datasheet
+  */
+__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(const COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_BLANKING));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_LL_EF_Operation Operation on comparator instance
+  * @{
+  */
+
+/**
+  * @brief  Enable comparator instance.
+  * @note   After enable from off state, comparator requires a delay
+  *         to reach reach propagation delay specification.
+  *         Refer to device datasheet, parameter "tSTART".
+  * @rmtoll CSR      EN             LL_COMP_Enable
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)
+{
+  SET_BIT(COMPx->CSR, COMP_CSR_EN);
+}
+
+/**
+  * @brief  Disable comparator instance.
+  * @rmtoll CSR      EN             LL_COMP_Disable
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)
+{
+  CLEAR_BIT(COMPx->CSR, COMP_CSR_EN);
+}
+
+/**
+  * @brief  Get comparator enable state
+  *         (0: COMP is disabled, 1: COMP is enabled)
+  * @rmtoll CSR      EN             LL_COMP_IsEnabled
+  * @param  COMPx Comparator instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_COMP_IsEnabled(const COMP_TypeDef *COMPx)
+{
+  return ((READ_BIT(COMPx->CSR, COMP_CSR_EN) == (COMP_CSR_EN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Lock comparator instance.
+  * @note   Once locked, comparator configuration can be accessed in read-only.
+  * @note   The only way to unlock the comparator is a device hardware reset.
+  * @rmtoll CSR      LOCK           LL_COMP_Lock
+  * @param  COMPx Comparator instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)
+{
+  SET_BIT(COMPx->CSR, COMP_CSR_LOCK);
+}
+
+/**
+  * @brief  Get comparator lock state
+  *         (0: COMP is unlocked, 1: COMP is locked).
+  * @note   Once locked, comparator configuration can be accessed in read-only.
+  * @note   The only way to unlock the comparator is a device hardware reset.
+  * @rmtoll CSR      LOCK           LL_COMP_IsLocked
+  * @param  COMPx Comparator instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_COMP_IsLocked(const COMP_TypeDef *COMPx)
+{
+  return ((READ_BIT(COMPx->CSR, COMP_CSR_LOCK) == (COMP_CSR_LOCK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Read comparator instance output level.
+  * @note   On this STM32 series, comparator 'value' is taken before
+  *         polarity and blanking are applied, thus:
+  *          - Comparator output is low when the input plus
+  *            is at a lower voltage than the input minus
+  *          - Comparator output is high when the input plus
+  *            is at a higher voltage than the input minus
+  * @rmtoll CSR      VALUE          LL_COMP_ReadOutputLevel
+  * @param  COMPx Comparator instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW
+  *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH
+  */
+__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(const COMP_TypeDef *COMPx)
+{
+  return (uint32_t)(READ_BIT(COMPx->CSR, COMP_CSR_VALUE)
+                    >> COMP_CSR_VALUE_Pos);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);
+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, const LL_COMP_InitTypeDef *COMP_InitStruct);
+void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_COMP_H */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dac.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dac.h
new file mode 100644
index 0000000..47f4964
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_dac.h
@@ -0,0 +1,2676 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_dac.h
+  * @author  MCD Application Team
+  * @brief   Header file of DAC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_DAC_H
+#define STM32G4xx_LL_DAC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
+
+/** @defgroup DAC_LL DAC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Constants DAC Private Constants
+  * @{
+  */
+
+/* Internal masks for DAC channels definition */
+/* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */
+/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR, STMODR    */
+/* - channel bits position into register SWTRIG                               */
+/* - channel bits position into register SWTRIGB                              */
+/* - channel register offset of data holding register DHRx                    */
+/* - channel register offset of data output register DORx                     */
+/* - channel register offset of sample-and-hold sample time register SHSRx    */
+/* - channel register offset of sawtooth register STRx                        */
+#define DAC_CR_CH1_BITOFFSET           0UL   /* Position of channel bits into registers
+                                                CR, MCR, CCR, SHHR, SHRR, STMODR of channel 1 */
+#define DAC_CR_CH2_BITOFFSET           16UL  /* Position of channel bits into registers
+                                                CR, MCR, CCR, SHHR, SHRR, STMODR of channel 2 */
+#define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)
+
+#define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */
+#define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */
+#define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)
+
+#define DAC_SWTRB_CH1                  (DAC_SWTRIGR_SWTRIGB1) /* Channel bit into register SWTRIGRB of channel 1.*/
+#define DAC_SWTRB_CH2                  (DAC_SWTRIGR_SWTRIGB2) /* Channel bit into register SWTRIGR of channel 2.*/
+#define DAC_SWTRB_CHX_MASK             (DAC_SWTRB_CH1 | DAC_SWTRB_CH2)
+
+#define DAC_REG_DHR12R1_REGOFFSET      0x00000000UL            /* Register DHR12Rx channel 1 taken as reference */
+#define DAC_REG_DHR12L1_REGOFFSET      0x00100000UL            /* Register offset of DHR12Lx channel 1 versus
+                                                                  DHR12Rx channel 1 (shifted left of 20 bits)   */
+#define DAC_REG_DHR8R1_REGOFFSET       0x02000000UL            /* Register offset of DHR8Rx  channel 1 versus
+                                                                  DHR12Rx channel 1 (shifted left of 24 bits)   */
+
+#define DAC_REG_DHR12R2_REGOFFSET      0x30000000UL            /* Register offset of DHR12Rx channel 2 versus
+                                                                  DHR12Rx channel 1 (shifted left of 28 bits)   */
+#define DAC_REG_DHR12L2_REGOFFSET      0x00400000UL            /* Register offset of DHR12Lx channel 2 versus
+                                                                  DHR12Rx channel 1 (shifted left of 20 bits)   */
+#define DAC_REG_DHR8R2_REGOFFSET       0x05000000UL            /* Register offset of DHR8Rx  channel 2 versus
+                                                                  DHR12Rx channel 1 (shifted left of 24 bits)   */
+
+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL
+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL
+#define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000UL
+#define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK\
+                                        | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)
+
+#define DAC_REG_DOR1_REGOFFSET         0x00000000UL            /* Register DORx channel 1 taken as reference */
+
+#define DAC_REG_DOR2_REGOFFSET         0x00000020UL            /* Register offset of DORx channel 1 versus
+                                                                  DORx channel 2 (shifted left of 5 bits)    */
+#define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)
+
+#define DAC_REG_SHSR1_REGOFFSET        0x00000000UL            /* Register SHSRx channel 1 taken as reference */
+#define DAC_REG_SHSR2_REGOFFSET        0x00000040UL            /* Register offset of SHSRx channel 1 versus
+                                                                  SHSRx channel 2 (shifted left of 6 bits)    */
+#define DAC_REG_SHSRX_REGOFFSET_MASK   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)
+
+#define DAC_REG_STR1_REGOFFSET         0x00000000UL            /* Register STRx channel 1 taken as reference  */
+#define DAC_REG_STR2_REGOFFSET         0x00000080UL            /* Register offset of STRx channel 1 versus
+                                                                  STRx channel 2 (shifted left of 7 bits)     */
+#define DAC_REG_STRX_REGOFFSET_MASK   (DAC_REG_STR1_REGOFFSET | DAC_REG_STR2_REGOFFSET)
+
+#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0         0x0000000FUL /* Mask of data hold registers offset (DHR12Rx,
+                                                                   DHR12Lx, DHR8Rx, ...) when shifted to position 0 */
+#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0        0x00000001UL /* Mask of DORx registers offset when shifted
+                                                                   to position 0                                    */
+#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0       0x00000001UL /* Mask of SHSRx registers offset when shifted
+                                                                   to position 0                                    */
+#define DAC_REG_STRX_REGOFFSET_MASK_POSBIT0        0x00000001UL /* Mask of STRx registers offset when shifted
+                                                                   to position 0                                    */
+
+#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS           28UL  /* Position of bits register offset of DHR12Rx
+                                                                   channel 1 or 2 versus DHR12Rx channel 1
+                                                                   (shifted left of 28 bits)                   */
+#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS           20UL  /* Position of bits register offset of DHR12Lx
+                                                                   channel 1 or 2 versus DHR12Rx channel 1
+                                                                   (shifted left of 20 bits)                   */
+#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS            24UL  /* Position of bits register offset of DHR8Rx
+                                                                   channel 1 or 2 versus DHR12Rx channel 1
+                                                                   (shifted left of 24 bits)                   */
+#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS               5UL  /* Position of bits register offset of DORx
+                                                                   channel 1 or 2 versus DORx channel 1
+                                                                   (shifted left of 5 bits)                    */
+#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS              6UL  /* Position of bits register offset of SHSRx
+                                                                   channel 1 or 2 versus SHSRx channel 1
+                                                                   (shifted left of 6 bits)                    */
+#define DAC_REG_STRX_REGOFFSET_BITOFFSET_POS               7UL  /* Position of bits register offset of STRx
+                                                                   channel 1 or 2 versus STRx channel 1
+                                                                   (shifted left of 7 bits)                    */
+
+/* DAC registers bits positions */
+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                DAC_DHR12RD_DACC2DHR_Pos
+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                DAC_DHR12LD_DACC2DHR_Pos
+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                 DAC_DHR8RD_DACC2DHR_Pos
+
+/* Miscellaneous data */
+#define DAC_DIGITAL_SCALE_12BITS                  4095UL   /* Full-scale digital value with a resolution of 12
+                                                              bits (voltage range determined by analog voltage
+                                                              references Vref+ and Vref-, refer to reference manual) */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Private_Macros DAC Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Driver macro reserved for internal use: set a pointer to
+  *         a register from a register basis from which an offset
+  *         is applied.
+  * @param  __REG__ Register basis from which the offset is applied.
+  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+  * @retval Pointer to register address
+  */
+#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
+  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of DAC instance.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel:
+                                             internal (SW start) or from external peripheral
+                                             (timer event, external interrupt line).
+                                             This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
+
+                                             This feature can be modified afterwards using unitary
+                                             function @ref LL_DAC_SetTriggerSource().
+                                             @note If waveform automatic generation mode is set to sawtooth,
+                                             this parameter is used as sawtooth RESET trigger */
+
+  uint32_t TriggerSource2;              /*!< Set the conversion secondary trigger source for the selected DAC channel:
+                                             internal (SW start) or from external peripheral
+                                             (timer event, external interrupt line).
+                                             This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE
+
+                                             This feature can be modified afterwards using unitary
+                                             function @ref LL_DAC_SetTriggerSource2().
+                                             @note If waveform automatic generation mode is set to sawtooth,
+                                             this parameter is used as sawtooth step trigger */
+
+  uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.
+                                             This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE
+
+                                             This feature can be modified afterwards using unitary
+                                             function @ref LL_DAC_SetWaveAutoGeneration(). */
+
+  uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.
+                                             If waveform automatic generation mode is set to noise, this parameter
+                                             can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS
+                                             If waveform automatic generation mode is set to triangle,
+                                             this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE
+                                             If waveform automatic generation mode is set to sawtooth, this parameter
+                                             host the sawtooth configuration: polarity, reset data, increment data.
+                                             Use __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG macro to set this parameter value.
+                                             @note If waveform automatic generation mode is disabled,
+                                              this parameter is discarded.
+
+                                             This feature can be modified afterwards using unitary
+                                             function @ref LL_DAC_SetWaveNoiseLFSR(),
+                                             @ref LL_DAC_SetWaveTriangleAmplitude(),
+                                             @ref LL_DAC_SetWaveSawtoothPolarity(),
+                                             @ref LL_DAC_SetWaveSawtoothResetData()
+                                             or @ref LL_DAC_SetWaveSawtoothStepData(),
+                                             depending on the wave automatic generation selected. */
+
+  uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.
+                                             This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER
+
+                                             This feature can be modified afterwards using unitary
+                                             function @ref LL_DAC_SetOutputBuffer(). */
+
+  uint32_t OutputConnection;            /*!< Set the output connection for the selected DAC channel.
+                                             This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION
+
+                                             This feature can be modified afterwards using unitary
+                                             function @ref LL_DAC_SetOutputConnection(). */
+
+  uint32_t OutputMode;                  /*!< Set the output mode normal or sample-and-hold for the selected DAC
+                                             channel. This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE
+
+                                             This feature can be modified afterwards using unitary
+                                             function @ref LL_DAC_SetOutputMode(). */
+} LL_DAC_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants
+  * @{
+  */
+
+/** @defgroup DAC_LL_EC_GET_FLAG DAC flags
+  * @brief    Flags defines which can be used with LL_DAC_ReadReg function
+  * @{
+  */
+/* DAC channel 1 flags */
+#define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */
+#define LL_DAC_FLAG_CAL1                   (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */
+#define LL_DAC_FLAG_BWST1                  (DAC_SR_BWST1)     /*!< DAC channel 1 flag busy writing sample time */
+#define LL_DAC_FLAG_DAC1RDY                (DAC_SR_DAC1RDY)   /*!< DAC channel 1 flag ready */
+#define LL_DAC_FLAG_DORSTAT1               (DAC_SR_DORSTAT1)  /*!< DAC channel 1 flag output register */
+
+/* DAC channel 2 flags */
+#define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */
+#define LL_DAC_FLAG_CAL2                   (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */
+#define LL_DAC_FLAG_BWST2                  (DAC_SR_BWST2)     /*!< DAC channel 2 flag busy writing sample time */
+#define LL_DAC_FLAG_DAC2RDY                (DAC_SR_DAC2RDY)   /*!< DAC channel 2 flag ready */
+#define LL_DAC_FLAG_DORSTAT2               (DAC_SR_DORSTAT2)  /*!< DAC channel 2 flag output register */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_IT DAC interruptions
+  * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions
+  * @{
+  */
+#define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */
+
+#define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_CHANNEL DAC channels
+  * @{
+  */
+#define LL_DAC_CHANNEL_1                   (DAC_REG_STR1_REGOFFSET | DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1 | DAC_SWTRB_CH1) /*!< DAC channel 1 */
+#define LL_DAC_CHANNEL_2                   (DAC_REG_STR2_REGOFFSET | DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2 | DAC_SWTRB_CH2) /*!< DAC channel 2 */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_HIGH_FREQUENCY_MODE DAC high frequency interface mode
+  * @brief    High frequency interface mode defines that can be used
+  *           with LL_DAC_SetHighFrequencyMode and LL_DAC_GetHighFrequencyMode
+  * @{
+  */
+#define LL_DAC_HIGH_FREQ_MODE_DISABLE         0x00000000UL       /*!< High frequency interface mode disabled */
+#define LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ     (DAC_MCR_HFSEL_0)  /*!< High frequency interface mode compatible to AHB>80MHz enabled */
+#define LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ    (DAC_MCR_HFSEL_1)  /*!< High frequency interface mode compatible to AHB>160MHz enabled */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode
+  * @{
+  */
+#define LL_DAC_MODE_NORMAL_OPERATION       0x00000000UL            /*!< DAC channel in mode normal operation */
+#define LL_DAC_MODE_CALIBRATION            (DAC_CR_CEN1)           /*!< DAC channel in mode calibration */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source
+  * @{
+  */
+#define LL_DAC_TRIG_SOFTWARE                  0x00000000UL                                                        /*!< DAC (all) channel conversion trigger internal (SW start) */
+#define LL_DAC_TRIG_EXT_TIM1_TRGO             (                                                   DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: TIM1 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM8_TRGO             (                                                   DAC_CR_TSEL1_0) /*!< DAC1/2/4 channel conversion trigger from external peripheral: TIM8 TRGO. Refer to device datasheet for DACx instance availability. */
+#define LL_DAC_TRIG_EXT_TIM7_TRGO             (                                  DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM7 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM15_TRGO            (                                  DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM15 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM2_TRGO             (                 DAC_CR_TSEL1_2                                  ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM2 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM4_TRGO             (                 DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM4 TRGO. */
+#define LL_DAC_TRIG_EXT_EXTI_LINE9            (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 9. Note: only to be used as update or reset (sawtooth generation) trigger */
+#define LL_DAC_TRIG_EXT_EXTI_LINE10           (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: external interrupt line 10. Note: only to be used as increment (sawtooth generation) trigger */
+#define LL_DAC_TRIG_EXT_TIM6_TRGO             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: TIM6 TRGO. */
+#define LL_DAC_TRIG_EXT_TIM3_TRGO             (DAC_CR_TSEL1_3                                                   ) /*!< DAC (all) channel conversion trigger from external peripheral: TIM3 TRGO. */
+#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1       (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG1  (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG1        (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG1 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2       (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG2  (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG2        (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG2 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3       (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG3  (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG3        (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG3 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4       (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                  ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG4  (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG4        (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                  ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG4 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5       (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG5  (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG5        (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG5 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6       (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC STEP TRIG6  (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_RST_TRG6        (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC (all) channel conversion trigger from external peripheral: HRTIM DAC RESET TRIG6 (only available for sawtooth wave generation). On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_TRGO1           (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC1&4 channel conversion trigger from external peripheral: HRTIM1 DACTRG1. Note: only to be used as update or reset (sawtooth generation) trigger. Refer to device datasheet for DACx instance availability. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+#define LL_DAC_TRIG_EXT_HRTIM_TRGO2           (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC2 channel conversion trigger from external peripheral: HRTIM1 DACTRG2. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported and DAC2 instance present (refer to device datasheet for supported features list and DAC2 instance availability) */
+#define LL_DAC_TRIG_EXT_HRTIM_TRGO3           (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC3 channel conversion trigger from external peripheral: HRTIM1 DACTRG3. Note: only to be used as update or reset (sawtooth generation) trigger. On this STM32 series, parameter only available if HRTIM feature is supported (refer to device datasheet for supported features list) */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode
+  * @{
+  */
+#define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000UL                    /*!< DAC channel wave auto generation mode disabled. */
+#define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (               DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1               ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */
+#define LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH (DAC_CR_WAVE1_1|DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated sawtooth waveform. */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits
+  * @{
+  */
+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000UL                                                        /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */
+#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude
+  * @{
+  */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000UL                                                        /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */
+#define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_SAWTOOTH_POLARITY_MODE DAC wave generation - Sawtooth polarity mode
+  * @{
+  */
+#define LL_DAC_SAWTOOTH_POLARITY_DECREMENT          0x00000000UL            /*!< Sawtooth wave generation, polarity is decrement */
+#define LL_DAC_SAWTOOTH_POLARITY_INCREMENT          (DAC_STR1_STDIR1)       /*!< Sawtooth wave generation, polarity is increment */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode
+  * @{
+  */
+#define LL_DAC_OUTPUT_MODE_NORMAL          0x00000000UL            /*!< The selected DAC channel output is on mode normal. */
+#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)       /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer
+  * @{
+  */
+#define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000UL            /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */
+#define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_MCR_MODE1_1)       /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection
+  * @{
+  */
+#define LL_DAC_OUTPUT_CONNECT_GPIO         0x00000000UL            /*!< The selected DAC channel output is connected to external pin */
+#define LL_DAC_OUTPUT_CONNECT_INTERNAL     (DAC_MCR_MODE1_0)       /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 series, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_SIGNED_FORMAT DAC channel signed format
+  * @{
+  */
+#define LL_DAC_SIGNED_FORMAT_DISABLE       0x00000000UL            /*!< The selected DAC channel data format is not signed */
+#define LL_DAC_SIGNED_FORMAT_ENABLE        (DAC_MCR_SINFORMAT1)    /*!< The selected DAC channel data format is signed */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution
+  * @{
+  */
+#define LL_DAC_RESOLUTION_12B              0x00000000UL            /*!< DAC channel resolution 12 bits */
+#define LL_DAC_RESOLUTION_8B               0x00000002UL            /*!< DAC channel resolution 8 bits */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose
+  * @{
+  */
+/* List of DAC registers intended to be used (most commonly) with             */
+/* DMA transfer.                                                              */
+/* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */
+#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */
+#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */
+#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS  /*!< DAC channel data holding register 8 bits right aligned */
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays
+  * @note   Only DAC peripheral HW delays are defined in DAC LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+
+/* Delay for DAC channel voltage settling time from DAC channel startup       */
+/* (transition from disable to enable).                                       */
+/* Note: DAC channel startup time depends on board application environment:   */
+/*       impedance connected to DAC channel output.                           */
+/*       The delay below is specified under conditions:                       */
+/*        - voltage maximum transition (lowest to highest value)              */
+/*        - until voltage reaches final value +-1LSB                          */
+/*        - DAC channel output buffer enabled                                 */
+/*        - load impedance of 5kOhm (min), 50pF (max)                         */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tWAKEUP").                                                      */
+/* Unit: us                                                                   */
+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             8UL  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */
+
+/* Delay for DAC channel voltage settling time.                               */
+/* Note: DAC channel startup time depends on board application environment:   */
+/*       impedance connected to DAC channel output.                           */
+/*       The delay below is specified under conditions:                       */
+/*        - voltage maximum transition (lowest to highest value)              */
+/*        - until voltage reaches final value +-1LSB                          */
+/*        - DAC channel output buffer enabled                                 */
+/*        - load impedance of 5kOhm min, 50pF max                             */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSETTLING").                                                    */
+/* Unit: us                                                                   */
+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US                     3UL /*!< Delay for DAC channel voltage settling time */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros
+  * @{
+  */
+
+/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in DAC register
+  * @param  __INSTANCE__ DAC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in DAC register
+  * @param  __INSTANCE__ DAC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get DAC channel number in decimal format
+  *         from literals LL_DAC_CHANNEL_x.
+  *         Example:
+  *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)
+  *            will return decimal number "1".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval 1...2
+  */
+#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \
+  ((__CHANNEL__) & DAC_SWTR_CHX_MASK)
+
+/**
+  * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x
+  *         from number in decimal format.
+  *         Example:
+  *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)
+  *           will return a data equivalent to "LL_DAC_CHANNEL_1".
+  * @note  If the input parameter does not correspond to a DAC channel,
+  *        this macro returns value '0'.
+  * @param  __DECIMAL_NB__ 1...2
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  */
+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)\
+  (((__DECIMAL_NB__) == 1UL)? (LL_DAC_CHANNEL_1  ):(((__DECIMAL_NB__) == 2UL) ? ( LL_DAC_CHANNEL_2):(0UL)))
+
+/**
+  * @brief  Helper macro to define the DAC conversion data full-scale digital
+  *         value corresponding to the selected DAC resolution.
+  * @note   DAC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_RESOLUTION_12B
+  *         @arg @ref LL_DAC_RESOLUTION_8B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \
+  ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))
+
+/**
+  * @brief  Helper macro to calculate the DAC conversion data (unit: digital
+  *         value) corresponding to a voltage (unit: mVolt).
+  * @note   This helper macro is intended to provide input data in voltage
+  *         rather than digital value,
+  *         to be used with LL DAC functions such as
+  *         @ref LL_DAC_ConvertData12RightAligned().
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel
+  *                         (unit: mVolt).
+  * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_RESOLUTION_12B
+  *         @arg @ref LL_DAC_RESOLUTION_8B
+  * @retval DAC conversion data (unit: digital value)
+  */
+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__)     \
+  ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                                      \
+   / (__VREFANALOG_VOLTAGE__)                                                                          \
+  )
+
+/**
+  * @brief  Helper macro to format sawtooth wave generation configuration
+  *         value to be filled into WaveAutoGenerationConfig  parameter of @ref LL_DAC_InitTypeDef.
+  * @note   This helper will format information to fit in DAC_STRx register.
+  * @param  __POLARITY__ sawtooth wave polarity (must be value of @ref DAC_LL_EC_SAWTOOTH_POLARITY_MODE)
+  * @param  __RESET_DATA__ sawtooth reset data.
+  * @param  __STEP_DATA__ sawtooth step data
+  * @retval Sawtooth configuration organized in DAC_STRx compatible format.
+  */
+#define __LL_DAC_FORMAT_SAWTOOTHWAVECONFIG(__POLARITY__, __RESET_DATA__, __STEP_DATA__)               \
+  ( (((__STEP_DATA__) << DAC_STR1_STINCDATA1_Pos) & DAC_STR1_STINCDATA1_Msk)                          \
+    | ((__POLARITY__) & DAC_STR1_STDIR1_Msk)                                                          \
+    | (((__RESET_DATA__) << DAC_STR1_STRSTDATA1_Pos) & DAC_STR1_STRSTDATA1_Msk)                       \
+  )
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions
+  * @{
+  */
+/** @defgroup DAC_LL_EF_Channel_Configuration Configuration of DAC instance
+  * @{
+  */
+/**
+  * @brief  Set the high frequency interface mode for the selected DAC instance
+  * @rmtoll MCR      HFSEL          LL_DAC_SetHighFrequencyMode
+  * @param  DACx DAC instance
+  * @param  HighFreqMode This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
+  *         @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
+  *         @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetHighFrequencyMode(DAC_TypeDef *DACx, uint32_t HighFreqMode)
+{
+  MODIFY_REG(DACx->MCR, DAC_MCR_HFSEL, HighFreqMode);
+}
+
+/**
+  * @brief  Get the high frequency interface mode for the selected DAC instance
+  * @rmtoll MCR      HFSEL          LL_DAC_GetHighFrequencyMode
+  * @param  DACx DAC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_HIGH_FREQ_MODE_DISABLE
+  *         @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_80MHZ
+  *         @arg @ref LL_DAC_HIGH_FREQ_MODE_ABOVE_160MHZ
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetHighFrequencyMode(const DAC_TypeDef *DACx)
+{
+  return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_HFSEL));
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels
+  * @{
+  */
+
+/**
+  * @brief  Set the operating mode for the selected DAC channel:
+  *         calibration or normal operating mode.
+  * @rmtoll CR       CEN1           LL_DAC_SetMode\n
+  *         CR       CEN2           LL_DAC_SetMode
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  ChannelMode This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
+  *         @arg @ref LL_DAC_MODE_CALIBRATION
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the operating mode for the selected DAC channel:
+  *         calibration or normal operating mode.
+  * @rmtoll CR       CEN1           LL_DAC_GetMode\n
+  *         CR       CEN2           LL_DAC_GetMode
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION
+  *         @arg @ref LL_DAC_MODE_CALIBRATION
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the offset trimming value for the selected DAC channel.
+  *         Trimming has an impact when output buffer is enabled
+  *         and is intended to replace factory calibration default values.
+  * @rmtoll CCR      OTRIM1         LL_DAC_SetTrimmingValue\n
+  *         CCR      OTRIM2         LL_DAC_SetTrimmingValue
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)
+{
+  MODIFY_REG(DACx->CCR,
+             DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the offset trimming value for the selected DAC channel.
+  *         Trimming has an impact when output buffer is enabled
+  *         and is intended to replace factory calibration default values.
+  * @rmtoll CCR      OTRIM1         LL_DAC_GetTrimmingValue\n
+  *         CCR      OTRIM2         LL_DAC_GetTrimmingValue
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the conversion trigger source for the selected DAC channel.
+  * @note   For conversion trigger source to be effective, DAC trigger
+  *         must be enabled using function @ref LL_DAC_EnableTrigger().
+  * @note   To set conversion trigger source, DAC channel must be disabled.
+  *         Otherwise, the setting is discarded.
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n
+  *         CR       TSEL2          LL_DAC_SetTriggerSource
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_TRIG_SOFTWARE
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO            (1)
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO            (2)
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1          (3) (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2          (4) (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3          (1) (5)
+  *
+  *         (1) On this STM32 series, parameter only available on DAC3.
+  *         (2) On this STM32 series, parameter only available on DAC1/2/4.
+  *         (3) On this STM32 series, parameter only available on DAC1&4.
+  *         (4) On this STM32 series, parameter only available on DAC2.
+  *          Refer to device datasheet for DACx instances availability.
+  *         (5) On this STM32 series, parameter not available on all devices.
+  *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the conversion trigger source for the selected DAC channel.
+  * @note   For conversion trigger source to be effective, DAC trigger
+  *         must be enabled using function @ref LL_DAC_EnableTrigger().
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n
+  *         CR       TSEL2          LL_DAC_GetTriggerSource
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_TRIG_SOFTWARE
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO            (1)
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO            (2)
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1          (3) (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2          (4) (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3          (1) (5)
+  *
+  *         (1) On this STM32 series, parameter only available on DAC3.
+  *         (2) On this STM32 series, parameter only available on DAC1/2/4.
+  *         (3) On this STM32 series, parameter only available on DAC1&4.
+  *         (4) On this STM32 series, parameter only available on DAC2.
+  *          Refer to device datasheet for DACx instances availability.
+  *         (5) On this STM32 series, parameter not available on all devices.
+  *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the waveform automatic generation mode
+  *         for the selected DAC channel.
+  * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n
+  *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  WaveAutoGeneration This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the waveform automatic generation mode
+  *         for the selected DAC channel.
+  * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n
+  *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE
+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_SAWTOOTH
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the noise waveform generation for the selected DAC channel:
+  *         Noise mode and parameters LFSR (linear feedback shift register).
+  * @note   For wave generation to be effective, DAC channel
+  *         wave generation mode must be enabled using
+  *         function @ref LL_DAC_SetWaveAutoGeneration().
+  * @note   This setting can be set when the selected DAC channel is disabled
+  *         (otherwise, the setting operation is ignored).
+  * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n
+  *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  NoiseLFSRMask This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the noise waveform generation for the selected DAC channel:
+  *         Noise mode and parameters LFSR (linear feedback shift register).
+  * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n
+  *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0
+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the triangle waveform generation for the selected DAC channel:
+  *         triangle mode and amplitude.
+  * @note   For wave generation to be effective, DAC channel
+  *         wave generation mode must be enabled using
+  *         function @ref LL_DAC_SetWaveAutoGeneration().
+  * @note   This setting can be set when the selected DAC channel is disabled
+  *         (otherwise, the setting operation is ignored).
+  * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n
+  *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  TriangleAmplitude This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,
+                                                     uint32_t TriangleAmplitude)
+{
+  MODIFY_REG(DACx->CR,
+             DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the triangle waveform generation for the selected DAC channel:
+  *         triangle mode and amplitude.
+  * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n
+  *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047
+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the swatooth waveform generation polarity.
+  * @note   For wave generation to be effective, DAC channel
+  *         wave generation mode must be enabled using
+  *         function @ref LL_DAC_SetWaveAutoGeneration().
+  * @note   This setting can be set when the selected DAC channel is disabled
+  *         (otherwise, the setting operation is ignored).
+  * @rmtoll STR1     STDIR1         LL_DAC_SetWaveSawtoothPolarity\n
+  *         STR2     STDIR2         LL_DAC_SetWaveSawtoothPolarity
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT
+  *         @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveSawtoothPolarity(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Polarity)
+{
+  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
+                                             (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) &
+                                             DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
+
+  MODIFY_REG(*preg,
+             DAC_STR1_STDIR1,
+             Polarity);
+}
+
+/**
+  * @brief  Get the sawtooth waveform generation polarity.
+  * @rmtoll STR1     STDIR1         LL_DAC_GetWaveSawtoothPolarity\n
+  *         STR2     STDIR2         LL_DAC_GetWaveSawtoothPolarity
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_SAWTOOTH_POLARITY_DECREMENT
+  *         @arg @ref LL_DAC_SAWTOOTH_POLARITY_INCREMENT
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothPolarity(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
+                                                   (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS)
+                                                   & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
+
+  return (uint32_t) READ_BIT(*preg, DAC_STR1_STDIR1);
+}
+
+/**
+  * @brief  Set the swatooth waveform generation reset data.
+  * @note   For wave generation to be effective, DAC channel
+  *         wave generation mode must be enabled using
+  *         function @ref LL_DAC_SetWaveAutoGeneration().
+  * @note   This setting can be set when the selected DAC channel is disabled
+  *         (otherwise, the setting operation is ignored).
+  * @rmtoll STR1     STRSTDATA1     LL_DAC_SetWaveSawtoothResetData\n
+  *         STR2     STRSTDATA2     LL_DAC_SetWaveSawtoothResetData
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  ResetData This parameter is the sawtooth reset value.
+  *         Range is from 0 to DAC full range 4095 (0xFFF)
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveSawtoothResetData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ResetData)
+{
+  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
+                                             (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) &
+                                             DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
+
+  MODIFY_REG(*preg,
+             DAC_STR1_STRSTDATA1,
+             ResetData << DAC_STR1_STRSTDATA1_Pos);
+}
+
+/**
+  * @brief  Get the sawtooth waveform generation reset data.
+  * @rmtoll STR1     STRSTDATA1     LL_DAC_GetWaveSawtoothResetData\n
+  *         STR2     STRSTDATA2     LL_DAC_GetWaveSawtoothResetData
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value is the sawtooth reset value.
+  *         Range is from 0 to DAC full range 4095 (0xFFF)
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
+                                                   (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS)
+                                                   & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
+
+  return (uint32_t)(READ_BIT(*preg, DAC_STR1_STRSTDATA1) >> DAC_STR1_STRSTDATA1_Pos);
+}
+
+/**
+  * @brief  Set the sawtooth waveform generation step data.
+  * @note   For wave generation to be effective, DAC channel
+  *         wave generation mode must be enabled using
+  *         function @ref LL_DAC_SetWaveAutoGeneration().
+  * @note   This setting can be set when the selected DAC channel is disabled
+  *         (otherwise, the setting operation is ignored).
+  * @rmtoll STR1     STINCDATA1     LL_DAC_SetWaveSawtoothStepData\n
+  *         STR2     STINCDATA2     LL_DAC_SetWaveSawtoothStepData
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  StepData This parameter is the sawtooth step value.
+  *         12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
+  *         Step value step is 1/16 = 0.0625
+  *         Step value range is 0.0000 to 4095.9375 (0xFFF.F)
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveSawtoothStepData(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t StepData)
+{
+  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
+                                             (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS) &
+                                             DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
+
+  MODIFY_REG(*preg,
+             DAC_STR1_STINCDATA1,
+             StepData << DAC_STR1_STINCDATA1_Pos);
+}
+
+/**
+  * @brief  Get the sawtooth waveform generation step data.
+  * @rmtoll STR1     STINCDATA1     LL_DAC_GetWaveSawtoothStepData\n
+  *         STR2     STINCDATA2     LL_DAC_GetWaveSawtoothStepData
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value is the sawtooth step value.
+  *         12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
+  *         Step value step is 1/16 = 0.0625
+  *         Step value range is 0.0000 to 4095.9375 (0xFFF.F)
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->STR1,
+                                                   (DAC_Channel >> DAC_REG_STRX_REGOFFSET_BITOFFSET_POS)
+                                                   & DAC_REG_STRX_REGOFFSET_MASK_POSBIT0);
+
+  return (uint32_t)(READ_BIT(*preg, DAC_STR1_STINCDATA1) >> DAC_STR1_STINCDATA1_Pos);
+}
+
+/**
+  * @brief  Set the sawtooth waveform generation reset trigger source.
+  * @note   For wave generation to be effective, DAC channel
+  *         wave generation mode must be enabled using
+  *         function @ref LL_DAC_SetWaveAutoGeneration().
+  * @note   This setting can be set when the selected DAC channel is disabled
+  *         (otherwise, the setting operation is ignored).
+  * @rmtoll STMODR   STRSTTRIGSEL1  LL_DAC_SetWaveSawtoothResetTriggerSource\n
+  *         STMODR   STRSTTRIGSEL2  LL_DAC_SetWaveSawtoothResetTriggerSource
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_TRIG_SOFTWARE
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO            (1)
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO            (2)
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1          (3) (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2          (4) (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3          (1) (5)
+  *
+  *         (1) On this STM32 series, parameter only available on DAC3.
+  *         (2) On this STM32 series, parameter only available on DAC1/2/4.
+  *         (3) On this STM32 series, parameter only available on DAC1&4.
+  *         (4) On this STM32 series, parameter only available on DAC2.
+  *          Refer to device datasheet for DACx instances availability.
+  *         (5) On this STM32 series, parameter not available on all devices.
+  *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveSawtoothResetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel,
+                                                              uint32_t TriggerSource)
+{
+  MODIFY_REG(DACx->STMODR,
+             DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             (   ((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos)
+              << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) ));
+}
+
+/**
+  * @brief  Get the sawtooth waveform generation reset trigger source.
+  * @rmtoll STMODR   STRSTTRIGSEL1  LL_DAC_GetWaveSawtoothResetTriggerSource\n
+  *         STMODR   STRSTTRIGSEL2  LL_DAC_GetWaveSawtoothResetTriggerSource
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_TRIG_SOFTWARE
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO            (1)
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO            (2)
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG1           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG2           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG3           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG4           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG5           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_RST_TRG6           (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1          (3) (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2          (4) (5)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO3          (1) (5)
+  *
+  *         (1) On this STM32 series, parameter only available on DAC3.
+  *         (2) On this STM32 series, parameter only available on DAC1/2/4.
+  *         (3) On this STM32 series, parameter only available on DAC1&4.
+  *         (4) On this STM32 series, parameter only available on DAC2.
+  *          Refer to device datasheet for DACx instances availability.
+  *         (5) On this STM32 series, parameter not available on all devices.
+  *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothResetTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)((READ_BIT(DACx->STMODR,
+                              DAC_STMODR_STRSTTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                             )
+                     >> (DAC_STMODR_STRSTTRIGSEL1_Pos + (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    ) << DAC_CR_TSEL1_Pos);
+}
+
+/**
+  * @brief  Set the swatooth waveform generation step trigger source.
+  * @note   For wave generation to be effective, DAC channel
+  *         wave generation mode must be enabled using
+  *         function @ref LL_DAC_SetWaveAutoGeneration().
+  * @note   This setting can be set when the selected DAC channel is disabled
+  *         (otherwise, the setting operation is ignored).
+  * @rmtoll STMODR   STINCTRIGSEL1  LL_DAC_SetWaveSawtoothStepTriggerSource\n
+  *         STMODR   STINCTRIGSEL2  LL_DAC_SetWaveSawtoothStepTriggerSource
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_TRIG_SOFTWARE
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO            (1)
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO            (2)
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE10
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1      (3)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2      (3)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3      (3)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4      (3)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5      (3)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6      (3)
+  *
+  *         (1) On this STM32 series, parameter only available on DAC3.
+  *         (2) On this STM32 series, parameter only available on DAC1/2/4.
+  *          Refer to device datasheet for DACx instances availability.
+  *         (3) On this STM32 series, parameter not available on all devices.
+  *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetWaveSawtoothStepTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel,
+                                                             uint32_t TriggerSource)
+{
+  MODIFY_REG(DACx->STMODR,
+             DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             (   ((TriggerSource >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos)
+              << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+             ));
+}
+
+/**
+  * @brief  Get the sawtooth waveform generation step trigger source.
+  * @rmtoll STMODR   STINCTRIGSEL1  LL_DAC_GetWaveSawtoothStepTriggerSource\n
+  *         STMODR   STINCTRIGSEL2  LL_DAC_GetWaveSawtoothStepTriggerSource
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_TRIG_SOFTWARE
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO            (1)
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO            (2)
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE10
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG1      (3)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG2      (3)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG3      (3)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG4      (3)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG5      (3)
+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_STEP_TRG6      (3)
+  *
+  *         (1) On this STM32 series, parameter only available on DAC3.
+  *         (2) On this STM32 series, parameter only available on DAC1/2/4.
+  *          Refer to device datasheet for DACx instances availability.
+  *         (3) On this STM32 series, parameter not available on all devices.
+  *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetWaveSawtoothStepTriggerSource(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)((READ_BIT(DACx->STMODR,
+                              DAC_STMODR_STINCTRIGSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                             )
+                     >> (DAC_STMODR_STINCTRIGSEL1_Pos + (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    ) << DAC_CR_TSEL1_Pos);
+}
+
+/**
+  * @brief  Set the output for the selected DAC channel.
+  * @note   This function set several features:
+  *         - mode normal or sample-and-hold
+  *         - buffer
+  *         - connection to GPIO or internal path.
+  *         These features can also be set individually using
+  *         dedicated functions:
+  *         - @ref LL_DAC_SetOutputBuffer()
+  *         - @ref LL_DAC_SetOutputMode()
+  *         - @ref LL_DAC_SetOutputConnection()
+  * @note   On this STM32 series, output connection depends on output mode
+  *         (normal or sample and hold) and output buffer state.
+  *         - if output connection is set to internal path and output buffer
+  *           is enabled (whatever output mode):
+  *           output connection is also connected to GPIO pin
+  *           (both connections to GPIO pin and internal path).
+  *         - if output connection is set to GPIO pin, output buffer
+  *           is disabled, output mode set to sample and hold:
+  *           output connection is also connected to internal path
+  *           (both connections to GPIO pin and internal path).
+  * @note   Mode sample-and-hold requires an external capacitor
+  *         to be connected between DAC channel output and ground.
+  *         Capacitor value depends on load on DAC channel output and
+  *         sample-and-hold timings configured.
+  *         As indication, capacitor typical value is 100nF
+  *         (refer to device datasheet, parameter "CSH").
+  * @rmtoll CR       MODE1          LL_DAC_ConfigOutput\n
+  *         CR       MODE2          LL_DAC_ConfigOutput
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  OutputMode This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
+  *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
+  * @param  OutputBuffer This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+  * @param  OutputConnection This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,
+                                         uint32_t OutputBuffer, uint32_t OutputConnection)
+{
+  MODIFY_REG(DACx->MCR,
+             (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Set the output mode normal or sample-and-hold
+  *         for the selected DAC channel.
+  * @note   Mode sample-and-hold requires an external capacitor
+  *         to be connected between DAC channel output and ground.
+  *         Capacitor value depends on load on DAC channel output and
+  *         sample-and-hold timings configured.
+  *         As indication, capacitor typical value is 100nF
+  *         (refer to device datasheet, parameter "CSH").
+  * @rmtoll CR       MODE1          LL_DAC_SetOutputMode\n
+  *         CR       MODE2          LL_DAC_SetOutputMode
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  OutputMode This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
+  *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)
+{
+  MODIFY_REG(DACx->MCR,
+             (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the output mode normal or sample-and-hold for the selected DAC channel.
+  * @rmtoll CR       MODE1          LL_DAC_GetOutputMode\n
+  *         CR       MODE2          LL_DAC_GetOutputMode
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL
+  *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the output buffer for the selected DAC channel.
+  * @note   On this STM32 series, when buffer is enabled, its offset can be
+  *         trimmed: factory calibration default values can be
+  *         replaced by user trimming values, using function
+  *         @ref LL_DAC_SetTrimmingValue().
+  * @rmtoll CR       MODE1          LL_DAC_SetOutputBuffer\n
+  *         CR       MODE2          LL_DAC_SetOutputBuffer
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  OutputBuffer This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)
+{
+  MODIFY_REG(DACx->MCR,
+             (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the output buffer state for the selected DAC channel.
+  * @rmtoll CR       MODE1          LL_DAC_GetOutputBuffer\n
+  *         CR       MODE2          LL_DAC_GetOutputBuffer
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE
+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the output connection for the selected DAC channel.
+  * @note   On this STM32 series, output connection depends on output mode (normal or
+  *         sample and hold) and output buffer state.
+  *         - if output connection is set to internal path and output buffer
+  *           is enabled (whatever output mode):
+  *           output connection is also connected to GPIO pin
+  *           (both connections to GPIO pin and internal path).
+  *         - if output connection is set to GPIO pin, output buffer
+  *           is disabled, output mode set to sample and hold:
+  *           output connection is also connected to internal path
+  *           (both connections to GPIO pin and internal path).
+  * @rmtoll CR       MODE1          LL_DAC_SetOutputConnection\n
+  *         CR       MODE2          LL_DAC_SetOutputConnection
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  OutputConnection This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)
+{
+  MODIFY_REG(DACx->MCR,
+             (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the output connection for the selected DAC channel.
+  * @note   On this STM32 series, output connection depends on output mode (normal or
+  *         sample and hold) and output buffer state.
+  *         - if output connection is set to internal path and output buffer
+  *           is enabled (whatever output mode):
+  *           output connection is also connected to GPIO pin
+  *           (both connections to GPIO pin and internal path).
+  *         - if output connection is set to GPIO pin, output buffer
+  *           is disabled, output mode set to sample and hold:
+  *           output connection is also connected to internal path
+  *           (both connections to GPIO pin and internal path).
+  * @rmtoll CR       MODE1          LL_DAC_GetOutputConnection\n
+  *         CR       MODE2          LL_DAC_GetOutputConnection
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO
+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the sample-and-hold timing for the selected DAC channel:
+  *         sample time
+  * @note   Sample time must be set when DAC channel is disabled
+  *         or during DAC operation when DAC channel flag BWSTx is reset,
+  *         otherwise the setting is ignored.
+  *         Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".
+  * @rmtoll SHSR1    TSAMPLE1       LL_DAC_SetSampleAndHoldSampleTime\n
+  *         SHSR2    TSAMPLE2       LL_DAC_SetSampleAndHoldSampleTime
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)
+{
+  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
+                                             & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
+
+  MODIFY_REG(*preg, DAC_SHSR1_TSAMPLE1, SampleTime);
+}
+
+/**
+  * @brief  Get the sample-and-hold timing for the selected DAC channel:
+  *         sample time
+  * @rmtoll SHSR1    TSAMPLE1       LL_DAC_GetSampleAndHoldSampleTime\n
+  *         SHSR2    TSAMPLE2       LL_DAC_GetSampleAndHoldSampleTime
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS)
+                                                   & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);
+
+  return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);
+}
+
+/**
+  * @brief  Set the sample-and-hold timing for the selected DAC channel:
+  *         hold time
+  * @rmtoll SHHR     THOLD1         LL_DAC_SetSampleAndHoldHoldTime\n
+  *         SHHR     THOLD2         LL_DAC_SetSampleAndHoldHoldTime
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)
+{
+  MODIFY_REG(DACx->SHHR,
+             DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the sample-and-hold timing for the selected DAC channel:
+  *         hold time
+  * @rmtoll SHHR     THOLD1         LL_DAC_GetSampleAndHoldHoldTime\n
+  *         SHHR     THOLD2         LL_DAC_GetSampleAndHoldHoldTime
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the sample-and-hold timing for the selected DAC channel:
+  *         refresh time
+  * @rmtoll SHRR     TREFRESH1      LL_DAC_SetSampleAndHoldRefreshTime\n
+  *         SHRR     TREFRESH2      LL_DAC_SetSampleAndHoldRefreshTime
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)
+{
+  MODIFY_REG(DACx->SHRR,
+             DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the sample-and-hold timing for the selected DAC channel:
+  *         refresh time
+  * @rmtoll SHRR     TREFRESH1      LL_DAC_GetSampleAndHoldRefreshTime\n
+  *         SHRR     TREFRESH2      LL_DAC_GetSampleAndHoldRefreshTime
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @brief  Set the signed format for the selected DAC channel.
+  * @note   On this STM32 series, signed format can be used to inject
+  *         Q1.15, Q1.11, Q1.7 signed format data to DAC.
+  *         Ex when using 12bits data format (Q1.11 is used):
+  *             0x800 will output 0v level
+  *             0xFFF will output mid-scale level
+  *             0x000 will output mid-scale level
+  *             0x7FF will output full-scale level
+  * @rmtoll MCR      SINFORMAT1     LL_DAC_SetSignedFormat\n
+  *         MCR      SINFORMAT2     LL_DAC_SetSignedFormat
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  SignedFormat This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
+  *         @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_SetSignedFormat(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SignedFormat)
+{
+  MODIFY_REG(DACx->MCR,
+             DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),
+             SignedFormat << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get the signed format state for the selected DAC channel.
+  * @rmtoll MCR      SINFORMAT1     LL_DAC_GetSignedFormat\n
+  *         MCR      SINFORMAT2     LL_DAC_GetSignedFormat
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_DAC_SIGNED_FORMAT_ENABLE
+  *         @arg @ref LL_DAC_SIGNED_FORMAT_DISABLE
+  */
+__STATIC_INLINE uint32_t LL_DAC_GetSignedFormat(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_SINFORMAT1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)
+                   );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_DMA_Management DMA Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DAC DMA transfer request of the selected channel.
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_DAC_DMA_GetRegAddr().
+  * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n
+  *         CR       DMAEN2         LL_DAC_EnableDMAReq
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->CR,
+          DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Disable DAC DMA transfer request of the selected channel.
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_DAC_DMA_GetRegAddr().
+  * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n
+  *         CR       DMAEN2         LL_DAC_DisableDMAReq
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  CLEAR_BIT(DACx->CR,
+            DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get DAC DMA transfer request state of the selected channel.
+  *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)
+  * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n
+  *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return ((READ_BIT(DACx->CR,
+                    DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+           == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DAC DMA Double data mode of the selected channel.
+  * @rmtoll MCR      DMADOUBLE1     LL_DAC_EnableDMADoubleDataMode\n
+  *         MCR      DMADOUBLE2     LL_DAC_EnableDMADoubleDataMode
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->MCR,
+          DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Disable DAC DMA Double data mode of the selected channel.
+  * @rmtoll MCR      DMADOUBLE1     LL_DAC_DisableDMADoubleDataMode\n
+  *         MCR      DMADOUBLE2     LL_DAC_DisableDMADoubleDataMode
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableDMADoubleDataMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  CLEAR_BIT(DACx->MCR,
+            DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get DAC DMA double data mode state of the selected channel.
+  *         (0: DAC DMA double data mode is disabled, 1: DAC DMA double data mode is enabled)
+  * @rmtoll MCR      DMADOUBLE1     LL_DAC_IsDMADoubleDataModeEnabled\n
+  *         MCR      DMADOUBLE2     LL_DAC_IsDMADoubleDataModeEnabled
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsDMADoubleDataModeEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return ((READ_BIT(DACx->MCR,
+                    DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+           == (DAC_MCR_DMADOUBLE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Function to help to configure DMA transfer to DAC: retrieve the
+  *         DAC register address from DAC instance and a list of DAC registers
+  *         intended to be used (most commonly) with DMA transfer.
+  * @note   These DAC registers are data holding registers:
+  *         when DAC conversion is requested, DAC generates a DMA transfer
+  *         request to have data available in DAC data holding registers.
+  * @note   This macro is intended to be used with LL DMA driver, refer to
+  *         function "LL_DMA_ConfigAddresses()".
+  *         Example:
+  *           LL_DMA_ConfigAddresses(DMA1,
+  *                                  LL_DMA_CHANNEL_1,
+  *                                  (uint32_t)&< array or variable >,
+  *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1,
+  *                                  LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),
+  *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);
+  * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n
+  *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  Register This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED
+  *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED
+  *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED
+  * @retval DAC register address
+  */
+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(const DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)
+{
+  /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */
+  /* DAC channel selected.                                                    */
+  return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, ((DAC_Channel >> (Register & 0x1FUL))
+                                                            & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));
+}
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_Operation Operation on DAC channels
+  * @{
+  */
+
+/**
+  * @brief  Enable DAC selected channel.
+  * @rmtoll CR       EN1            LL_DAC_Enable\n
+  *         CR       EN2            LL_DAC_Enable
+  * @note   After enable from off state, DAC channel requires a delay
+  *         for output voltage to reach accuracy +/- 1 LSB.
+  *         Refer to device datasheet, parameter "tWAKEUP".
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->CR,
+          DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Disable DAC selected channel.
+  * @rmtoll CR       EN1            LL_DAC_Disable\n
+  *         CR       EN2            LL_DAC_Disable
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  CLEAR_BIT(DACx->CR,
+            DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get DAC enable state of the selected channel.
+  *         (0: DAC channel is disabled, 1: DAC channel is enabled)
+  * @rmtoll CR       EN1            LL_DAC_IsEnabled\n
+  *         CR       EN2            LL_DAC_IsEnabled
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return ((READ_BIT(DACx->CR,
+                    DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+           == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get DAC ready for conversion state of the selected channel.
+  *         (0: DAC channel is not ready, 1: DAC channel is ready)
+  * @rmtoll SR       DAC1RDY        LL_DAC_IsReady\n
+  *         SR       DAC2RDY        LL_DAC_IsReady
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsReady(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return ((READ_BIT(DACx->SR,
+                    DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+           == (DAC_SR_DAC1RDY << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DAC trigger of the selected channel.
+  * @note   - If DAC trigger is disabled, DAC conversion is performed
+  *           automatically once the data holding register is updated,
+  *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+  *           @ref LL_DAC_ConvertData12RightAligned(), ...
+  *         - If DAC trigger is enabled, DAC conversion is performed
+  *           only when a hardware of software trigger event is occurring.
+  *           Select trigger source using
+  *           function @ref LL_DAC_SetTriggerSource().
+  * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n
+  *         CR       TEN2           LL_DAC_EnableTrigger
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->CR,
+          DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Disable DAC trigger of the selected channel.
+  * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n
+  *         CR       TEN2           LL_DAC_DisableTrigger
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  CLEAR_BIT(DACx->CR,
+            DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));
+}
+
+/**
+  * @brief  Get DAC trigger state of the selected channel.
+  *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)
+  * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n
+  *         CR       TEN2           LL_DAC_IsTriggerEnabled
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  return ((READ_BIT(DACx->CR,
+                    DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))
+           == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Trig DAC conversion by software for the selected DAC channel.
+  * @note   Preliminarily, DAC trigger must be set to software trigger
+  *         using function
+  *           @ref LL_DAC_Init()
+  *           @ref LL_DAC_SetTriggerSource()
+  *           @ref LL_DAC_SetWaveSawtoothResetTriggerSource() (1)
+  *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
+  *         and DAC trigger must be enabled using
+  *         function @ref LL_DAC_EnableTrigger().
+  *
+  *           (1) In case, Sawtooth wave generation has been configured.
+  * @note   For devices featuring DAC with 2 channels: this function
+  *         can perform a SW start of both DAC channels simultaneously.
+  *         Two channels can be selected as parameter.
+  *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
+  * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n
+  *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion
+  * @param  DACx DAC instance
+  * @param  DAC_Channel  This parameter can a combination of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->SWTRIGR,
+          (DAC_Channel & DAC_SWTR_CHX_MASK));
+}
+
+/**
+  * @brief  Trig DAC conversion by secondary software trigger for the selected DAC channel.
+  * @note   Preliminarily, DAC secondary trigger must be set to software trigger
+  *         using function
+  *           @ref LL_DAC_Init()
+  *           @ref LL_DAC_SetWaveSawtoothStepTriggerSource() (1)
+  *         with parameter "LL_DAC_TRIGGER_SOFTWARE".
+  *         and DAC trigger must be enabled using
+  *         function @ref LL_DAC_EnableTrigger().
+  *
+  *           (1) In case, Sawtooth wave generation has been configured.
+  * @note   For devices featuring DAC with 2 channels: this function
+  *         can perform a SW start of both DAC channels simultaneously.
+  *         Two channels can be selected as parameter.
+  *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)
+  * @rmtoll SWTRIGR  SWTRIGB1       LL_DAC_TrigSWConversion2\n
+  *         SWTRIGR  SWTRIGB2       LL_DAC_TrigSWConversion2
+  * @param  DACx DAC instance
+  * @param  DAC_Channel  This parameter can a combination of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_TrigSWConversion2(DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  SET_BIT(DACx->SWTRIGR,
+          (DAC_Channel & DAC_SWTRB_CHX_MASK));
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 12 bits left alignment (LSB aligned on bit 0),
+  *         for the selected DAC channel.
+  * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n
+  *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS)
+                                             & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+
+  MODIFY_REG(*preg, DAC_DHR12R1_DACC1DHR, Data);
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 12 bits left alignment (MSB aligned on bit 15),
+  *         for the selected DAC channel.
+  * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n
+  *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS)
+                                             & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+
+  MODIFY_REG(*preg, DAC_DHR12L1_DACC1DHR, Data);
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 8 bits left alignment (LSB aligned on bit 0),
+  *         for the selected DAC channel.
+  * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n
+  *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)
+{
+  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS)
+                                             & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);
+
+  MODIFY_REG(*preg, DAC_DHR8R1_DACC1DHR, Data);
+}
+
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 12 bits left alignment (LSB aligned on bit 0),
+  *         for both DAC channels.
+  * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n
+  *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned
+  * @param  DACx DAC instance
+  * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
+                                                          uint32_t DataChannel2)
+{
+  MODIFY_REG(DACx->DHR12RD,
+             (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),
+             ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 12 bits left alignment (MSB aligned on bit 15),
+  *         for both DAC channels.
+  * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n
+  *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned
+  * @param  DACx DAC instance
+  * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
+                                                         uint32_t DataChannel2)
+{
+  /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */
+  /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */
+  /*       the 4 LSB must be taken into account for the shift value.          */
+  MODIFY_REG(DACx->DHR12LD,
+             (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),
+             ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));
+}
+
+/**
+  * @brief  Set the data to be loaded in the data holding register
+  *         in format 8 bits left alignment (LSB aligned on bit 0),
+  *         for both DAC channels.
+  * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n
+  *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned
+  * @param  DACx DAC instance
+  * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF
+  * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,
+                                                         uint32_t DataChannel2)
+{
+  MODIFY_REG(DACx->DHR8RD,
+             (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),
+             ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));
+}
+
+
+/**
+  * @brief  Retrieve output data currently generated for the selected DAC channel.
+  * @note   Whatever alignment and resolution settings
+  *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":
+  *         @ref LL_DAC_ConvertData12RightAligned(), ...),
+  *         output data format is 12 bits right aligned (LSB aligned on bit 0).
+  * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n
+  *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData
+  * @param  DACx DAC instance
+  * @param  DAC_Channel This parameter can be one of the following values:
+  *         @arg @ref LL_DAC_CHANNEL_1
+  *         @arg @ref LL_DAC_CHANNEL_2 (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(const DAC_TypeDef *DACx, uint32_t DAC_Channel)
+{
+  __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS)
+                                                   & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);
+
+  return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management
+  * @{
+  */
+
+/**
+  * @brief  Get DAC calibration offset flag for DAC channel 1
+  * @rmtoll SR       CAL_FLAG1      LL_DAC_IsActiveFlag_CAL1
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(const DAC_TypeDef *DACx)
+{
+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Get DAC calibration offset flag for DAC channel 2
+  * @rmtoll SR       CAL_FLAG2      LL_DAC_IsActiveFlag_CAL2
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(const DAC_TypeDef *DACx)
+{
+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Get DAC busy writing sample time flag for DAC channel 1
+  * @rmtoll SR       BWST1          LL_DAC_IsActiveFlag_BWST1
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(const DAC_TypeDef *DACx)
+{
+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get DAC busy writing sample time flag for DAC channel 2
+  * @rmtoll SR       BWST2          LL_DAC_IsActiveFlag_BWST2
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(const DAC_TypeDef *DACx)
+{
+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Get DAC ready status flag for DAC channel 1
+  * @rmtoll SR       DAC1RDY        LL_DAC_IsActiveFlag_DAC1RDY
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC1RDY(const DAC_TypeDef *DACx)
+{
+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC1RDY) == (LL_DAC_FLAG_DAC1RDY)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Get DAC ready status flag for DAC channel 2
+  * @rmtoll SR       DAC2RDY        LL_DAC_IsActiveFlag_DAC2RDY
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DAC2RDY(const DAC_TypeDef *DACx)
+{
+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DAC2RDY) == (LL_DAC_FLAG_DAC2RDY)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Get DAC output register status flag for DAC channel 1
+  * @rmtoll SR       DORSTAT1       LL_DAC_IsActiveFlag_DORSTAT1
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT1(const DAC_TypeDef *DACx)
+{
+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT1) == (LL_DAC_FLAG_DORSTAT1)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Get DAC output register status flag for DAC channel 2
+  * @rmtoll SR       DORSTAT2       LL_DAC_IsActiveFlag_DORSTAT2
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DORSTAT2(const DAC_TypeDef *DACx)
+{
+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DORSTAT2) == (LL_DAC_FLAG_DORSTAT2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get DAC underrun flag for DAC channel 1
+  * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(const DAC_TypeDef *DACx)
+{
+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Get DAC underrun flag for DAC channel 2
+  * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(const DAC_TypeDef *DACx)
+{
+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Clear DAC underrun flag for DAC channel 1
+  * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)
+{
+  WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);
+}
+
+
+/**
+  * @brief  Clear DAC underrun flag for DAC channel 2
+  * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)
+{
+  WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_LL_EF_IT_Management IT management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA underrun interrupt for DAC channel 1
+  * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+  SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+
+/**
+  * @brief  Enable DMA underrun interrupt for DAC channel 2
+  * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+  SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+
+
+/**
+  * @brief  Disable DMA underrun interrupt for DAC channel 1
+  * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)
+{
+  CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);
+}
+
+
+/**
+  * @brief  Disable DMA underrun interrupt for DAC channel 2
+  * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)
+{
+  CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);
+}
+
+
+/**
+  * @brief  Get DMA underrun interrupt for DAC channel 1
+  * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx)
+{
+  return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Get DMA underrun interrupt for DAC channel 2
+  * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2
+  * @param  DACx DAC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(const DAC_TypeDef *DACx)
+{
+  return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx);
+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct);
+void        LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 || DAC2 || DAC3 || DAC4 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_DAC_H */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_hrtim.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_hrtim.h
new file mode 100644
index 0000000..22dceb4
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_hrtim.h
@@ -0,0 +1,13905 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_hrtim.h
+  * @author  MCD Application Team
+  * @brief   Header file of HRTIM LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_HRTIM_H
+#define STM32G4xx_LL_HRTIM_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (HRTIM1)
+
+/** @defgroup HRTIM_LL HRTIM
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables
+  * @{
+  */
+static const uint16_t REG_OFFSET_TAB_TIMER[] =
+{
+  0x00U,   /* 0: MASTER  */
+  0x80U,   /* 1: TIMER A */
+  0x100U,  /* 2: TIMER B */
+  0x180U,  /* 3: TIMER C */
+  0x200U,  /* 4: TIMER D */
+  0x280U,  /* 5: TIMER E */
+  0x300U,  /* 6: TIMER F */
+};
+
+static const uint8_t REG_OFFSET_TAB_ADCER[] =
+{
+  0x00U,    /* LL_HRTIM_ADCTRIG_1:  HRTIM_ADC1R */
+  0x04U,    /* LL_HRTIM_ADCTRIG_2:  HRTIM_ADC2R */
+  0x08U,    /* LL_HRTIM_ADCTRIG_3:  HRTIM_ADC3R */
+  0x0CU,    /* LL_HRTIM_ADCTRIG_4:  HRTIM_ADC4R */
+  0x3CU,    /* LL_HRTIM_ADCTRIG_5:  HRTIM_ADCER */
+  0x3CU,    /* LL_HRTIM_ADCTRIG_6:  HRTIM_ADCER */
+  0x3CU,    /* LL_HRTIM_ADCTRIG_7:  HRTIM_ADCER */
+  0x3CU,    /* LL_HRTIM_ADCTRIG_8:  HRTIM_ADCER */
+  0x3CU,    /* LL_HRTIM_ADCTRIG_9:  HRTIM_ADCER */
+  0x3CU,    /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCER */
+};
+
+static const uint8_t REG_OFFSET_TAB_ADCUR[] =
+{
+  0x00U,    /* LL_HRTIM_ADCTRIG_1:  HRTIM_CR1   */
+  0x00U,    /* LL_HRTIM_ADCTRIG_2:  HRTIM_CR1   */
+  0x00U,    /* LL_HRTIM_ADCTRIG_3:  HRTIM_CR1   */
+  0x00U,    /* LL_HRTIM_ADCTRIG_4:  HRTIM_CR1   */
+  0x7CU,    /* LL_HRTIM_ADCTRIG_5:  HRTIM_ADCUR */
+  0x7CU,    /* LL_HRTIM_ADCTRIG_6:  HRTIM_ADCUR */
+  0x7CU,    /* LL_HRTIM_ADCTRIG_7:  HRTIM_ADCUR */
+  0x7CU,    /* LL_HRTIM_ADCTRIG_8:  HRTIM_ADCUR */
+  0x7CU,    /* LL_HRTIM_ADCTRIG_9:  HRTIM_ADCUR */
+  0x7CU,    /* LL_HRTIM_ADCTRIG_10: HRTIM_ADCUR */
+};
+
+static const uint8_t REG_SHIFT_TAB_ADCER[] =
+{
+  0,   /* LL_HRTIM_ADCTRIG_1  */
+  0,   /* LL_HRTIM_ADCTRIG_2  */
+  0,   /* LL_HRTIM_ADCTRIG_3  */
+  0,   /* LL_HRTIM_ADCTRIG_4  */
+  0,   /* LL_HRTIM_ADCTRIG_5  */
+  5,   /* LL_HRTIM_ADCTRIG_6  */
+  10,  /* LL_HRTIM_ADCTRIG_7  */
+  16,  /* LL_HRTIM_ADCTRIG_8  */
+  21,  /* LL_HRTIM_ADCTRIG_9  */
+  26   /* LL_HRTIM_ADCTRIG_10 */
+};
+
+static const uint8_t REG_SHIFT_TAB_ADCUR[] =
+{
+  16,   /* LL_HRTIM_ADCTRIG_1  */
+  19,   /* LL_HRTIM_ADCTRIG_2  */
+  22,   /* LL_HRTIM_ADCTRIG_3  */
+  25,   /* LL_HRTIM_ADCTRIG_4  */
+  0,    /* LL_HRTIM_ADCTRIG_5  */
+  4,    /* LL_HRTIM_ADCTRIG_6  */
+  8,    /* LL_HRTIM_ADCTRIG_7  */
+  12,   /* LL_HRTIM_ADCTRIG_8  */
+  16,   /* LL_HRTIM_ADCTRIG_9  */
+  20    /* LL_HRTIM_ADCTRIG_10 */
+};
+
+static const uint32_t REG_MASK_TAB_ADCER[] =
+{
+  0xFFFFFFFFU,   /* LL_HRTIM_ADCTRIG_1  */
+  0xFFFFFFFFU,   /* LL_HRTIM_ADCTRIG_2  */
+  0xFFFFFFFFU,   /* LL_HRTIM_ADCTRIG_3  */
+  0xFFFFFFFFU,   /* LL_HRTIM_ADCTRIG_4  */
+  0x0000001FU,   /* LL_HRTIM_ADCTRIG_5  */
+  0x000003E0U,   /* LL_HRTIM_ADCTRIG_6  */
+  0x00007C00U,   /* LL_HRTIM_ADCTRIG_7  */
+  0x001F0000U,   /* LL_HRTIM_ADCTRIG_8  */
+  0x03E00000U,   /* LL_HRTIM_ADCTRIG_9  */
+  0x7C000000U    /* LL_HRTIM_ADCTRIG_10 */
+};
+
+static const uint32_t REG_MASK_TAB_ADCUR[] =
+{
+  0x00070000U,   /* LL_HRTIM_ADCTRIG_1  */
+  0x00380000U,   /* LL_HRTIM_ADCTRIG_2  */
+  0x01C00000U,   /* LL_HRTIM_ADCTRIG_3  */
+  0x0E000000U,   /* LL_HRTIM_ADCTRIG_4  */
+  0x00000007U,   /* LL_HRTIM_ADCTRIG_5  */
+  0x00000070U,   /* LL_HRTIM_ADCTRIG_6  */
+  0x00000700U,   /* LL_HRTIM_ADCTRIG_7  */
+  0x00007000U,   /* LL_HRTIM_ADCTRIG_8  */
+  0x00070000U,   /* LL_HRTIM_ADCTRIG_9  */
+  0x00700000U    /* LL_HRTIM_ADCTRIG_10 */
+};
+
+static const uint8_t REG_OFFSET_TAB_ADCPSx[] =
+{
+  0U,    /* 0: HRTIM_ADC1R  */
+  6U,    /* 1: HRTIM_ADC2R  */
+  12U,   /* 2: HRTIM_ADC3R  */
+  18U,   /* 3: HRTIM_ADC4R  */
+  24U,   /* 4: HRTIM_ADC5R  */
+  32U,   /* 5: HRTIM_ADC6R  */
+  38U,   /* 6: HRTIM_ADC7R  */
+  44U,   /* 7: HRTIM_ADC8R  */
+  50U,   /* 8: HRTIM_ADC9R  */
+  56U    /* 9: HRTIM_ADC10R */
+};
+
+static const uint16_t REG_OFFSET_TAB_SETxR[] =
+{
+  0x00U,   /* 0: TA1 */
+  0x08U,   /* 1: TA2 */
+  0x80U,   /* 2: TB1 */
+  0x88U,   /* 3: TB2 */
+  0x100U,  /* 4: TC1 */
+  0x108U,  /* 5: TC2 */
+  0x180U,  /* 6: TD1 */
+  0x188U,  /* 7: TD2 */
+  0x200U,  /* 8: TE1 */
+  0x208U,  /* 9: TE2 */
+  0x280U,  /* 10: TF1 */
+  0x288U   /* 11: TF2 */
+};
+
+static const uint16_t REG_OFFSET_TAB_OUTxR[] =
+{
+  0x00U,   /*  0: TA1 */
+  0x00U,   /*  1: TA2 */
+  0x80U,   /*  2: TB1 */
+  0x80U,   /*  3: TB2 */
+  0x100U,  /*  4: TC1 */
+  0x100U,  /*  5: TC2 */
+  0x180U,  /*  6: TD1 */
+  0x180U,  /*  7: TD2 */
+  0x200U,  /*  8: TE1 */
+  0x200U,  /*  9: TE2 */
+  0x280U,  /* 10: TF1 */
+  0x280U   /* 11: TF2 */
+};
+
+static const uint8_t REG_OFFSET_TAB_EECR[] =
+{
+  0x00U, /* LL_HRTIM_EVENT_1 */
+  0x00U, /* LL_HRTIM_EVENT_2 */
+  0x00U, /* LL_HRTIM_EVENT_3 */
+  0x00U, /* LL_HRTIM_EVENT_4 */
+  0x00U, /* LL_HRTIM_EVENT_5 */
+  0x04U, /* LL_HRTIM_EVENT_6 */
+  0x04U, /* LL_HRTIM_EVENT_7 */
+  0x04U, /* LL_HRTIM_EVENT_8 */
+  0x04U, /* LL_HRTIM_EVENT_9 */
+  0x04U  /* LL_HRTIM_EVENT_10 */
+};
+
+static const uint8_t REG_OFFSET_TAB_FLTINR[] =
+{
+  0x00U, /* LL_HRTIM_FAULT_1 */
+  0x00U, /* LL_HRTIM_FAULT_2 */
+  0x00U, /* LL_HRTIM_FAULT_3 */
+  0x00U, /* LL_HRTIM_FAULT_4 */
+  0x04U, /* LL_HRTIM_FAULT_5 */
+  0x04U  /* LL_HRTIM_FAULT_6 */
+};
+
+static const uint32_t REG_MASK_TAB_UPDATETRIG[] =
+{
+  0x20000000U,  /* 0: MASTER  */
+  0x01FF0000U,  /* 1: TIMER A */
+  0x01FF0000U,  /* 2: TIMER B */
+  0x01FF0000U,  /* 3: TIMER C */
+  0x01FF0000U,  /* 4: TIMER D */
+  0x01FF0000U,  /* 5: TIMER E */
+  0x01FF0000U,  /* 5: TIMER E */
+  0x01FF0000U   /* 6: TIMER F */
+};
+
+static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =
+{
+  12U, /* 0: MASTER  */
+  0U,  /* 1: TIMER A */
+  0U,  /* 2: TIMER B  */
+  0U,  /* 3: TIMER C */
+  0U,  /* 4: TIMER D  */
+  0U,  /* 5: TIMER E */
+  0U   /* 6: TIMER F */
+};
+
+static const uint8_t REG_SHIFT_TAB_EExSRC[] =
+{
+  0U,  /* LL_HRTIM_EVENT_1  */
+  6U,  /* LL_HRTIM_EVENT_2  */
+  12U, /* LL_HRTIM_EVENT_3  */
+  18U, /* LL_HRTIM_EVENT_4  */
+  24U, /* LL_HRTIM_EVENT_5  */
+  0U,  /* LL_HRTIM_EVENT_6  */
+  6U,  /* LL_HRTIM_EVENT_7  */
+  12U, /* LL_HRTIM_EVENT_8  */
+  18U, /* LL_HRTIM_EVENT_9  */
+  24U  /* LL_HRTIM_EVENT_10 */
+};
+
+static const uint32_t REG_MASK_TAB_UPDATEGATING[] =
+{
+  HRTIM_MCR_BRSTDMA,   /* 0: MASTER  */
+  HRTIM_TIMCR_UPDGAT,  /* 1: TIMER A */
+  HRTIM_TIMCR_UPDGAT,  /* 2: TIMER B  */
+  HRTIM_TIMCR_UPDGAT,  /* 3: TIMER C */
+  HRTIM_TIMCR_UPDGAT,  /* 4: TIMER D  */
+  HRTIM_TIMCR_UPDGAT,  /* 5: TIMER E */
+  HRTIM_TIMCR_UPDGAT   /* 6: TIMER F */
+};
+
+static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =
+{
+  2U, /* 0: MASTER  */
+  0U, /* 1: TIMER A */
+  0U, /* 2: TIMER B  */
+  0U, /* 3: TIMER C */
+  0U, /* 4: TIMER D  */
+  0U, /* 5: TIMER E */
+  0U  /* 6: TIMER F */
+};
+
+static const uint8_t REG_SHIFT_TAB_OUTxR[] =
+{
+  0U,  /* 0: TA1  */
+  16U, /* 1: TA2 */
+  0U,  /* 2: TB1  */
+  16U, /* 3: TB2 */
+  0U,  /* 4: TC1  */
+  16U, /* 5: TC2 */
+  0U,  /* 6: TD1  */
+  16U, /* 7: TD2 */
+  0U,  /* 8: TE1  */
+  16U, /* 9: TE2 */
+  0U,  /* 10: TF1  */
+  16U  /* 11: TF2 */
+};
+
+static const uint8_t REG_SHIFT_TAB_OxSTAT[] =
+{
+  0U,  /* 0: TA1  */
+  1U,  /* 1: TA2 */
+  0U,  /* 2: TB1  */
+  1U,  /* 3: TB2 */
+  0U,  /* 4: TC1  */
+  1U,  /* 5: TC2 */
+  0U,  /* 6: TD1  */
+  1U,  /* 7: TD2 */
+  0U,  /* 8: TE1  */
+  1U,  /* 9: TE2 */
+  0U,  /* 10: TF1  */
+  1U   /* 11: TF2 */
+};
+
+static const uint8_t REG_SHIFT_TAB_FLTxE[] =
+{
+  0U,   /* LL_HRTIM_FAULT_1 */
+  8U,   /* LL_HRTIM_FAULT_2 */
+  16U,  /* LL_HRTIM_FAULT_3 */
+  24U,  /* LL_HRTIM_FAULT_4 */
+  0U,   /* LL_HRTIM_FAULT_5 */
+  8U    /* LL_HRTIM_FAULT_6 */
+};
+
+static const uint8_t REG_SHIFT_TAB_FLTxF[] =
+{
+  0U,   /* LL_HRTIM_FAULT_1 */
+  8U,   /* LL_HRTIM_FAULT_2 */
+  16U,  /* LL_HRTIM_FAULT_3 */
+  24U,  /* LL_HRTIM_FAULT_4 */
+  32U,  /* LL_HRTIM_FAULT_5 */
+  40U   /* LL_HRTIM_FAULT_6 */
+};
+
+static const uint8_t REG_SHIFT_TAB_FLTxCNT[] =
+{
+  2U,   /* LL_HRTIM_FAULT_1 */
+  10U,  /* LL_HRTIM_FAULT_2 */
+  18U,  /* LL_HRTIM_FAULT_3 */
+  26U,  /* LL_HRTIM_FAULT_4 */
+  2U,   /* LL_HRTIM_FAULT_5 */
+  10U   /* LL_HRTIM_FAULT_6 */
+};
+
+static const uint8_t REG_SHIFT_TAB_FLTx[] =
+{
+  0,  /* LL_HRTIM_FAULT_1 */
+  1,  /* LL_HRTIM_FAULT_2 */
+  2,  /* LL_HRTIM_FAULT_3 */
+  3,  /* LL_HRTIM_FAULT_4 */
+  4,  /* LL_HRTIM_FAULT_5 */
+  5   /* LL_HRTIM_FAULT_6 */
+};
+
+static const uint8_t REG_SHIFT_TAB_INTLVD[] =
+{
+  0U,  /* 0: MASTER  */
+  1U,  /* 1: TIMER A */
+  1U,  /* 2: TIMER B */
+  1U,  /* 3: TIMER C */
+  1U,  /* 4: TIMER D */
+  1U,  /* 5: TIMER E */
+  1U,  /* 6: TIMER F */
+};
+
+static const uint32_t REG_MASK_TAB_INTLVD[] =
+{
+  0x000000E0U,  /* 0: MASTER  */
+  0x000001A0U,  /* 1: TIMER A */
+  0x000001A0U,  /* 2: TIMER B */
+  0x000001A0U,  /* 3: TIMER C */
+  0x000001A0U,  /* 4: TIMER D */
+  0x000001A0U,  /* 5: TIMER E */
+  0x000001A0U,  /* 6: TIMER F */
+};
+
+static const uint8_t REG_SHIFT_TAB_CPT[] =
+{
+  12U,  /* 1: TIMER A */
+  16U,  /* 2: TIMER B */
+  20U,  /* 3: TIMER C */
+  24U,  /* 4: TIMER D */
+  28U,  /* 5: TIMER E */
+  32U,  /* 6: TIMER F */
+};
+
+static const uint32_t REG_MASK_TAB_CPT[] =
+{
+  0xFFFF0000U,  /* 1: TIMER A */
+  0xFFF0F000U,  /* 2: TIMER B */
+  0xFF0FF000U,  /* 3: TIMER C */
+  0xF0FFF000U,  /* 4: TIMER D */
+  0x0FFFF000U,  /* 5: TIMER E */
+  0xFFFFF000U,  /* 6: TIMER F */
+};
+
+/**
+  * @}
+  */
+
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants
+  * @{
+  */
+#define HRTIM_CR1_UDIS_MASK   ((uint32_t)(HRTIM_CR1_MUDIS  |\
+                                          HRTIM_CR1_TAUDIS |\
+                                          HRTIM_CR1_TBUDIS |\
+                                          HRTIM_CR1_TCUDIS |\
+                                          HRTIM_CR1_TDUDIS |\
+                                          HRTIM_CR1_TEUDIS |\
+                                          HRTIM_CR1_TFUDIS))
+
+#define HRTIM_CR2_SWUPD_MASK   ((uint32_t)(HRTIM_CR2_MSWU |\
+                                           HRTIM_CR2_TASWU |\
+                                           HRTIM_CR2_TBSWU |\
+                                           HRTIM_CR2_TCSWU |\
+                                           HRTIM_CR2_TDSWU |\
+                                           HRTIM_CR2_TESWU |\
+                                           HRTIM_CR2_TFSWU))
+
+#define HRTIM_CR2_SWAP_MASK   ((uint32_t)(HRTIM_CR2_SWPA |\
+                                          HRTIM_CR2_SWPB |\
+                                          HRTIM_CR2_SWPC |\
+                                          HRTIM_CR2_SWPD |\
+                                          HRTIM_CR2_SWPE |\
+                                          HRTIM_CR2_SWPF))
+
+#define HRTIM_CR2_SWRST_MASK   ((uint32_t)(HRTIM_CR2_MRST |\
+                                           HRTIM_CR2_TARST |\
+                                           HRTIM_CR2_TBRST |\
+                                           HRTIM_CR2_TCRST |\
+                                           HRTIM_CR2_TDRST |\
+                                           HRTIM_CR2_TERST |\
+                                           HRTIM_CR2_TFRST))
+
+#define HRTIM_OENR_OEN_MASK   ((uint32_t)(HRTIM_OENR_TA1OEN |\
+                                          HRTIM_OENR_TA2OEN |\
+                                          HRTIM_OENR_TB1OEN |\
+                                          HRTIM_OENR_TB2OEN |\
+                                          HRTIM_OENR_TC1OEN |\
+                                          HRTIM_OENR_TC2OEN |\
+                                          HRTIM_OENR_TD1OEN |\
+                                          HRTIM_OENR_TD2OEN |\
+                                          HRTIM_OENR_TE1OEN |\
+                                          HRTIM_OENR_TE2OEN |\
+                                          HRTIM_OENR_TF1OEN |\
+                                          HRTIM_OENR_TF2OEN))
+
+#define HRTIM_OENR_ODIS_MASK  ((uint32_t)(HRTIM_ODISR_TA1ODIS  |\
+                                          HRTIM_ODISR_TA2ODIS  |\
+                                          HRTIM_ODISR_TB1ODIS  |\
+                                          HRTIM_ODISR_TB2ODIS  |\
+                                          HRTIM_ODISR_TC1ODIS  |\
+                                          HRTIM_ODISR_TC2ODIS  |\
+                                          HRTIM_ODISR_TD1ODIS  |\
+                                          HRTIM_ODISR_TD2ODIS  |\
+                                          HRTIM_ODISR_TE1ODIS  |\
+                                          HRTIM_ODISR_TE2ODIS  |\
+                                          HRTIM_ODISR_TF1ODIS  |\
+                                          HRTIM_ODISR_TF2ODIS))
+
+#define HRTIM_OUT_CONFIG_MASK  ((uint32_t)(HRTIM_OUTR_POL1   |\
+                                           HRTIM_OUTR_IDLM1  |\
+                                           HRTIM_OUTR_IDLES1 |\
+                                           HRTIM_OUTR_FAULT1 |\
+                                           HRTIM_OUTR_CHP1   |\
+                                           HRTIM_OUTR_DIDL1))
+
+#define HRTIM_EE_CONFIG_MASK   ((uint32_t)(HRTIM_EECR1_EE1SRC |\
+                                           HRTIM_EECR1_EE1POL |\
+                                           HRTIM_EECR1_EE1SNS |\
+                                           HRTIM_EECR1_EE1FAST))
+
+#define HRTIM_FLT_CONFIG_MASK   ((uint32_t)(HRTIM_FLTINR1_FLT1P |\
+                                            HRTIM_FLTINR1_FLT1SRC_0 ))
+
+#define HRTIM_FLT_SRC_1_MASK   ((uint32_t)(HRTIM_FLTINR2_FLT6SRC_1 |\
+                                           HRTIM_FLTINR2_FLT5SRC_1 |\
+                                           HRTIM_FLTINR2_FLT4SRC_1 |\
+                                           HRTIM_FLTINR2_FLT3SRC_1 |\
+                                           HRTIM_FLTINR2_FLT2SRC_1 |\
+                                           HRTIM_FLTINR2_FLT1SRC_1))
+
+#define HRTIM_BM_CONFIG_MASK   ((uint32_t)( HRTIM_BMCR_BMPRSC |\
+                                            HRTIM_BMCR_BMCLK  |\
+                                            HRTIM_BMCR_BMOM))
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants
+  * @{
+  */
+
+/** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_HRTIM_ReadReg function
+  * @{
+  */
+#define LL_HRTIM_ISR_FLT1                  HRTIM_ISR_FLT1
+#define LL_HRTIM_ISR_FLT2                  HRTIM_ISR_FLT2
+#define LL_HRTIM_ISR_FLT3                  HRTIM_ISR_FLT3
+#define LL_HRTIM_ISR_FLT4                  HRTIM_ISR_FLT4
+#define LL_HRTIM_ISR_FLT5                  HRTIM_ISR_FLT5
+#define LL_HRTIM_ISR_FLT6                  HRTIM_ISR_FLT6
+#define LL_HRTIM_ISR_SYSFLT                HRTIM_ISR_SYSFLT
+#define LL_HRTIM_ISR_DLLRDY                HRTIM_ISR_DLLRDY
+#define LL_HRTIM_ISR_BMPER                 HRTIM_ISR_BMPER
+
+#define LL_HRTIM_MISR_MCMP1                HRTIM_MISR_MCMP1
+#define LL_HRTIM_MISR_MCMP2                HRTIM_MISR_MCMP2
+#define LL_HRTIM_MISR_MCMP3                HRTIM_MISR_MCMP3
+#define LL_HRTIM_MISR_MCMP4                HRTIM_MISR_MCMP4
+#define LL_HRTIM_MISR_MREP                 HRTIM_MISR_MREP
+#define LL_HRTIM_MISR_SYNC                 HRTIM_MISR_SYNC
+#define LL_HRTIM_MISR_MUPD                 HRTIM_MISR_MUPD
+
+#define LL_HRTIM_TIMISR_CMP1               HRTIM_TIMISR_CMP1
+#define LL_HRTIM_TIMISR_CMP2               HRTIM_TIMISR_CMP2
+#define LL_HRTIM_TIMISR_CMP3               HRTIM_TIMISR_CMP3
+#define LL_HRTIM_TIMISR_CMP4               HRTIM_TIMISR_CMP4
+#define LL_HRTIM_TIMISR_REP                HRTIM_TIMISR_REP
+#define LL_HRTIM_TIMISR_UPD                HRTIM_TIMISR_UPD
+#define LL_HRTIM_TIMISR_CPT1               HRTIM_TIMISR_CPT1
+#define LL_HRTIM_TIMISR_CPT2               HRTIM_TIMISR_CPT2
+#define LL_HRTIM_TIMISR_SET1               HRTIM_TIMISR_SET1
+#define LL_HRTIM_TIMISR_RST1               HRTIM_TIMISR_RST1
+#define LL_HRTIM_TIMISR_SET2               HRTIM_TIMISR_SET2
+#define LL_HRTIM_TIMISR_RST2               HRTIM_TIMISR_RST2
+#define LL_HRTIM_TIMISR_RST                HRTIM_TIMISR_RST
+#define LL_HRTIM_TIMISR_DLYPRT             HRTIM_TIMISR_DLYPRT
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions
+  * @{
+  */
+#define LL_HRTIM_IER_FLT1IE                HRTIM_IER_FLT1IE
+#define LL_HRTIM_IER_FLT2IE                HRTIM_IER_FLT2IE
+#define LL_HRTIM_IER_FLT3IE                HRTIM_IER_FLT3IE
+#define LL_HRTIM_IER_FLT4IE                HRTIM_IER_FLT4IE
+#define LL_HRTIM_IER_FLT5IE                HRTIM_IER_FLT5IE
+#define LL_HRTIM_IER_FLT6IE                HRTIM_IER_FLT6IE
+#define LL_HRTIM_IER_SYSFLTIE              HRTIM_IER_SYSFLTIE
+#define LL_HRTIM_IER_DLLRDYIE              HRTIM_IER_DLLRDYIE
+#define LL_HRTIM_IER_BMPERIE               HRTIM_IER_BMPERIE
+
+#define LL_HRTIM_MDIER_MCMP1IE             HRTIM_MDIER_MCMP1IE
+#define LL_HRTIM_MDIER_MCMP2IE             HRTIM_MDIER_MCMP2IE
+#define LL_HRTIM_MDIER_MCMP3IE             HRTIM_MDIER_MCMP3IE
+#define LL_HRTIM_MDIER_MCMP4IE             HRTIM_MDIER_MCMP4IE
+#define LL_HRTIM_MDIER_MREPIE              HRTIM_MDIER_MREPIE
+#define LL_HRTIM_MDIER_SYNCIE              HRTIM_MDIER_SYNCIE
+#define LL_HRTIM_MDIER_MUPDIE              HRTIM_MDIER_MUPDIE
+
+#define LL_HRTIM_TIMDIER_CMP1IE            HRTIM_TIMDIER_CMP1IE
+#define LL_HRTIM_TIMDIER_CMP2IE            HRTIM_TIMDIER_CMP2IE
+#define LL_HRTIM_TIMDIER_CMP3IE            HRTIM_TIMDIER_CMP3IE
+#define LL_HRTIM_TIMDIER_CMP4IE            HRTIM_TIMDIER_CMP4IE
+#define LL_HRTIM_TIMDIER_REPIE             HRTIM_TIMDIER_REPIE
+#define LL_HRTIM_TIMDIER_UPDIE             HRTIM_TIMDIER_UPDIE
+#define LL_HRTIM_TIMDIER_CPT1IE            HRTIM_TIMDIER_CPT1IE
+#define LL_HRTIM_TIMDIER_CPT2IE            HRTIM_TIMDIER_CPT2IE
+#define LL_HRTIM_TIMDIER_SET1IE            HRTIM_TIMDIER_SET1IE
+#define LL_HRTIM_TIMDIER_RST1IE            HRTIM_TIMDIER_RST1IE
+#define LL_HRTIM_TIMDIER_SET2IE            HRTIM_TIMDIER_SET2IE
+#define LL_HRTIM_TIMDIER_RST2IE            HRTIM_TIMDIER_RST2IE
+#define LL_HRTIM_TIMDIER_RSTIE             HRTIM_TIMDIER_RSTIE
+#define LL_HRTIM_TIMDIER_DLYPRTIE          HRTIM_TIMDIER_DLYPRTIE
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_SYNCIN_SRC  SYNCHRONIZATION INPUT SOURCE
+  * @{
+  * @brief Constants defining defining the synchronization input source.
+  */
+#define LL_HRTIM_SYNCIN_SRC_NONE            0x00000000U                      /*!< HRTIM is not synchronized and runs in standalone mode */
+#define LL_HRTIM_SYNCIN_SRC_TIM_EVENT       (HRTIM_MCR_SYNC_IN_1)                        /*!< The HRTIM is synchronized with the on-chip timer */
+#define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT  (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)  /*!< A positive pulse on SYNCIN input triggers the HRTIM */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_SYNCOUT_SRC  SYNCHRONIZATION OUTPUT SOURCE
+  * @{
+  * @brief Constants defining the source and event to be sent on the synchronization output.
+  */
+#define LL_HRTIM_SYNCOUT_SRC_MASTER_START  0x00000000U                                    /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer start event      */
+#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1   (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon master timer compare 1 event  */
+#define LL_HRTIM_SYNCOUT_SRC_TIMA_START    (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A start or reset events */
+#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1     (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on HRTIM_SCOUT output and hrtim_out_sync2 upon timer A compare 1 event       */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY  SYNCHRONIZATION OUTPUT POLARITY
+  * @{
+  * @brief Constants defining the routing and conditioning of the synchronization output event.
+  */
+#define LL_HRTIM_SYNCOUT_DISABLED     0x00000000U                         /*!< Synchronization output event is disabled */
+#define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1)                        /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
+#define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_TIMER  TIMER ID
+  * @{
+  * @brief Constants identifying a timing unit.
+  */
+#define LL_HRTIM_TIMER_NONE                0U   /*!< Master timer identifier */
+#define LL_HRTIM_TIMER_MASTER              HRTIM_MCR_MCEN   /*!< Master timer identifier */
+#define LL_HRTIM_TIMER_A                   HRTIM_MCR_TACEN  /*!< Timer A identifier */
+#define LL_HRTIM_TIMER_B                   HRTIM_MCR_TBCEN  /*!< Timer B identifier */
+#define LL_HRTIM_TIMER_C                   HRTIM_MCR_TCCEN  /*!< Timer C identifier */
+#define LL_HRTIM_TIMER_D                   HRTIM_MCR_TDCEN  /*!< Timer D identifier */
+#define LL_HRTIM_TIMER_E                   HRTIM_MCR_TECEN  /*!< Timer E identifier */
+#define LL_HRTIM_TIMER_F                   HRTIM_MCR_TFCEN  /*!< Timer F identifier */
+
+#define LL_HRTIM_TIMER_X                  (HRTIM_MCR_TFCEN | HRTIM_MCR_TACEN |\
+                                           HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\
+                                           HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )
+#define LL_HRTIM_TIMER_ALL                (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_OUTPUT  OUTPUT ID
+  * @{
+  * @brief Constants identifying an HRTIM output.
+  */
+#define LL_HRTIM_OUTPUT_TA1                HRTIM_OENR_TA1OEN  /*!< Timer A - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TA2                HRTIM_OENR_TA2OEN  /*!< Timer A - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TB1                HRTIM_OENR_TB1OEN  /*!< Timer B - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TB2                HRTIM_OENR_TB2OEN  /*!< Timer B - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TC1                HRTIM_OENR_TC1OEN  /*!< Timer C - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TC2                HRTIM_OENR_TC2OEN  /*!< Timer C - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TD1                HRTIM_OENR_TD1OEN  /*!< Timer D - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TD2                HRTIM_OENR_TD2OEN  /*!< Timer D - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TE1                HRTIM_OENR_TE1OEN  /*!< Timer E - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TE2                HRTIM_OENR_TE2OEN  /*!< Timer E - Output 2 identifier */
+#define LL_HRTIM_OUTPUT_TF1                HRTIM_OENR_TF1OEN  /*!< Timer F - Output 1 identifier */
+#define LL_HRTIM_OUTPUT_TF2                HRTIM_OENR_TF2OEN  /*!< Timer F - Output 2 identifier */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_COMPAREUNIT  COMPARE UNIT ID
+  * @{
+  * @brief Constants identifying a compare unit.
+  */
+#define LL_HRTIM_COMPAREUNIT_2             HRTIM_TIMCR_DELCMP2  /*!< Compare unit 2 identifier */
+#define LL_HRTIM_COMPAREUNIT_4             HRTIM_TIMCR_DELCMP4  /*!< Compare unit 4 identifier */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_CAPTUREUNIT  CAPTURE UNIT ID
+  * @{
+  * @brief Constants identifying a capture unit.
+  */
+#define LL_HRTIM_CAPTUREUNIT_1             0  /*!< Capture unit 1 identifier */
+#define LL_HRTIM_CAPTUREUNIT_2             1  /*!< Capture unit 2 identifier */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_FAULT  FAULT ID
+  * @{
+  * @brief Constants identifying a fault channel.
+  */
+#define LL_HRTIM_FAULT_1      HRTIM_FLTR_FLT1EN     /*!< Fault channel 1 identifier */
+#define LL_HRTIM_FAULT_2      HRTIM_FLTR_FLT2EN     /*!< Fault channel 2 identifier */
+#define LL_HRTIM_FAULT_3      HRTIM_FLTR_FLT3EN     /*!< Fault channel 3 identifier */
+#define LL_HRTIM_FAULT_4      HRTIM_FLTR_FLT4EN     /*!< Fault channel 4 identifier */
+#define LL_HRTIM_FAULT_5      HRTIM_FLTR_FLT5EN     /*!< Fault channel 5 identifier */
+#define LL_HRTIM_FAULT_6      HRTIM_FLTR_FLT6EN     /*!< Fault channel 6 identifier */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_EVENT  EXTERNAL EVENT ID
+  * @{
+  * @brief Constants identifying an external event channel.
+  */
+#define LL_HRTIM_EVENT_1        ((uint32_t)0x00000001U)     /*!< External event channel 1 identifier */
+#define LL_HRTIM_EVENT_2        ((uint32_t)0x00000002U)     /*!< External event channel 2 identifier */
+#define LL_HRTIM_EVENT_3        ((uint32_t)0x00000004U)     /*!< External event channel 3 identifier */
+#define LL_HRTIM_EVENT_4        ((uint32_t)0x00000008U)     /*!< External event channel 4 identifier */
+#define LL_HRTIM_EVENT_5        ((uint32_t)0x00000010U)     /*!< External event channel 5 identifier */
+#define LL_HRTIM_EVENT_6        ((uint32_t)0x00000020U)     /*!< External event channel 6 identifier */
+#define LL_HRTIM_EVENT_7        ((uint32_t)0x00000040U)     /*!< External event channel 7 identifier */
+#define LL_HRTIM_EVENT_8        ((uint32_t)0x00000080U)     /*!< External event channel 8 identifier */
+#define LL_HRTIM_EVENT_9        ((uint32_t)0x00000100U)     /*!< External event channel 9 identifier */
+#define LL_HRTIM_EVENT_10       ((uint32_t)0x00000200U)     /*!< External event channel 10 identifier */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_OUTPUTSTATE  OUTPUT STATE
+  * @{
+  * @brief Constants defining the state of an HRTIM output.
+  */
+#define LL_HRTIM_OUTPUTSTATE_IDLE          ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */
+#define LL_HRTIM_OUTPUTSTATE_RUN           ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */
+#define LL_HRTIM_OUTPUTSTATE_FAULT         ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_ADCTRIG  ADC TRIGGER
+  * @{
+  * @brief Constants identifying an ADC trigger.
+  */
+#define LL_HRTIM_ADCTRIG_1              ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */
+#define LL_HRTIM_ADCTRIG_2              ((uint32_t)0x00000001U)  /*!< ADC trigger 2 identifier */
+#define LL_HRTIM_ADCTRIG_3              ((uint32_t)0x00000002U)  /*!< ADC trigger 3 identifier */
+#define LL_HRTIM_ADCTRIG_4              ((uint32_t)0x00000003U)  /*!< ADC trigger 4 identifier */
+#define LL_HRTIM_ADCTRIG_5              ((uint32_t)0x00000004U)  /*!< ADC trigger 5 identifier */
+#define LL_HRTIM_ADCTRIG_6              ((uint32_t)0x00000005U)  /*!< ADC trigger 6 identifier */
+#define LL_HRTIM_ADCTRIG_7              ((uint32_t)0x00000006U)  /*!< ADC trigger 7 identifier */
+#define LL_HRTIM_ADCTRIG_8              ((uint32_t)0x00000007U)  /*!< ADC trigger 8 identifier */
+#define LL_HRTIM_ADCTRIG_9              ((uint32_t)0x00000008U)  /*!< ADC trigger 9 identifier */
+#define LL_HRTIM_ADCTRIG_10             ((uint32_t)0x00000009U)  /*!< ADC trigger 10 identifier */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE
+  * @{
+  * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).
+  */
+#define LL_HRTIM_ADCTRIG_UPDATE_MASTER  0x00000000U  /*!< HRTIM_ADCxR register update is triggered by the Master timer */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A 0x00000001U  /*!< HRTIM_ADCxR register update is triggered by the Timer A */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B 0x00000002U  /*!< HRTIM_ADCxR register update is triggered by the Timer B */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C 0x00000003U  /*!< HRTIM_ADCxR register update is triggered by the Timer C */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D 0x00000004U  /*!< HRTIM_ADCxR register update is triggered by the Timer D */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E 0x00000005U  /*!< HRTIM_ADCxR register update is triggered by the Timer E */
+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_F 0x00000006U  /*!< HRTIM_ADCxR register update is triggered by the Timer F */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13  ADC TRIGGER 1/3 SOURCE
+  * @{
+  * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.
+  */
+#define LL_HRTIM_ADCTRIG_SRC13_NONE           0x00000000U              /*!< No ADC trigger event */
+#define LL_HRTIM_ADCTRIG_SRC13_MCMP1          HRTIM_ADC1R_AD1MC1       /*!< ADC Trigger on master compare 1 */
+#define LL_HRTIM_ADCTRIG_SRC13_MCMP2          HRTIM_ADC1R_AD1MC2       /*!< ADC Trigger on master compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_MCMP3          HRTIM_ADC1R_AD1MC3       /*!< ADC Trigger on master compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_MCMP4          HRTIM_ADC1R_AD1MC4       /*!< ADC Trigger on master compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_MPER           HRTIM_ADC1R_AD1MPER      /*!< ADC Trigger on master period */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV1           HRTIM_ADC1R_AD1EEV1      /*!< ADC Trigger on external event 1 */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV2           HRTIM_ADC1R_AD1EEV2      /*!< ADC Trigger on external event 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV3           HRTIM_ADC1R_AD1EEV3      /*!< ADC Trigger on external event 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV4           HRTIM_ADC1R_AD1EEV4      /*!< ADC Trigger on external event 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_EEV5           HRTIM_ADC1R_AD1EEV5      /*!< ADC Trigger on external event 5 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2       HRTIM_ADC1R_AD1TFC2      /*!< ADC Trigger on Timer F compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3       HRTIM_ADC1R_AD1TAC3      /*!< ADC Trigger on Timer A compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4       HRTIM_ADC1R_AD1TAC4      /*!< ADC Trigger on Timer A compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMAPER        HRTIM_ADC1R_AD1TAPER     /*!< ADC Trigger on Timer A period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMARST        HRTIM_ADC1R_AD1TARST     /*!< ADC Trigger on Timer A reset */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3       HRTIM_ADC1R_AD1TFC3      /*!< ADC Trigger on Timer F compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3       HRTIM_ADC1R_AD1TBC3      /*!< ADC Trigger on Timer B compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4       HRTIM_ADC1R_AD1TBC4      /*!< ADC Trigger on Timer B compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBPER        HRTIM_ADC1R_AD1TBPER     /*!< ADC Trigger on Timer B period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMBRST        HRTIM_ADC1R_AD1TBRST     /*!< ADC Trigger on Timer B reset */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4       HRTIM_ADC1R_AD1TFC4      /*!< ADC Trigger on Timer F compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3       HRTIM_ADC1R_AD1TCC3      /*!< ADC Trigger on Timer C compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4       HRTIM_ADC1R_AD1TCC4      /*!< ADC Trigger on Timer C compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMCPER        HRTIM_ADC1R_AD1TCPER     /*!< ADC Trigger on Timer C period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMFPER        HRTIM_ADC1R_AD1TFPER     /*!< ADC Trigger on Timer F period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3       HRTIM_ADC1R_AD1TDC3      /*!< ADC Trigger on Timer D compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4       HRTIM_ADC1R_AD1TDC4      /*!< ADC Trigger on Timer D compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMDPER        HRTIM_ADC1R_AD1TDPER     /*!< ADC Trigger on Timer D period */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMFRST        HRTIM_ADC1R_AD1TFRST     /*!< ADC Trigger on Timer F reset */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3       HRTIM_ADC1R_AD1TEC3      /*!< ADC Trigger on Timer E compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4       HRTIM_ADC1R_AD1TEC4      /*!< ADC Trigger on Timer E compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC13_TIMEPER        HRTIM_ADC1R_AD1TEPER     /*!< ADC Trigger on Timer E period */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24  ADC TRIGGER 2/4 SOURCE
+  * @{
+  * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.
+  */
+#define LL_HRTIM_ADCTRIG_SRC24_NONE           0x00000000U            /*!< No ADC trigger event */
+#define LL_HRTIM_ADCTRIG_SRC24_MCMP1          HRTIM_ADC2R_AD2MC1     /*!< ADC Trigger on master compare 1 */
+#define LL_HRTIM_ADCTRIG_SRC24_MCMP2          HRTIM_ADC2R_AD2MC2     /*!< ADC Trigger on master compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_MCMP3          HRTIM_ADC2R_AD2MC3     /*!< ADC Trigger on master compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_MCMP4          HRTIM_ADC2R_AD2MC4     /*!< ADC Trigger on master compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_MPER           HRTIM_ADC2R_AD2MPER    /*!< ADC Trigger on master period */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV6           HRTIM_ADC2R_AD2EEV6    /*!< ADC Trigger on external event 6 */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV7           HRTIM_ADC2R_AD2EEV7    /*!< ADC Trigger on external event 7 */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV8           HRTIM_ADC2R_AD2EEV8    /*!< ADC Trigger on external event 8 */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV9           HRTIM_ADC2R_AD2EEV9    /*!< ADC Trigger on external event 9 */
+#define LL_HRTIM_ADCTRIG_SRC24_EEV10          HRTIM_ADC2R_AD2EEV10   /*!< ADC Trigger on external event 10 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2       HRTIM_ADC2R_AD2TAC2    /*!< ADC Trigger on Timer A compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2       HRTIM_ADC2R_AD2TFC2    /*!< ADC Trigger on Timer F compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4       HRTIM_ADC2R_AD2TAC4    /*!< ADC Trigger on Timer A compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMAPER        HRTIM_ADC2R_AD2TAPER   /*!< ADC Trigger on Timer A period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2       HRTIM_ADC2R_AD2TBC2    /*!< ADC Trigger on Timer B compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3       HRTIM_ADC2R_AD2TFC3    /*!< ADC Trigger on Timer F compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4       HRTIM_ADC2R_AD2TBC4    /*!< ADC Trigger on Timer B compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMBPER        HRTIM_ADC2R_AD2TBPER   /*!< ADC Trigger on Timer B period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2       HRTIM_ADC2R_AD2TCC2    /*!< ADC Trigger on Timer C compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4       HRTIM_ADC2R_AD2TFC4    /*!< ADC Trigger on Timer F compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4       HRTIM_ADC2R_AD2TCC4    /*!< ADC Trigger on Timer C compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCPER        HRTIM_ADC2R_AD2TCPER   /*!< ADC Trigger on Timer C period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMCRST        HRTIM_ADC2R_AD2TCRST   /*!< ADC Trigger on Timer C reset */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2       HRTIM_ADC2R_AD2TDC2    /*!< ADC Trigger on Timer D compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMFPER        HRTIM_ADC2R_AD2TFPER   /*!< ADC Trigger on Timer F period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4       HRTIM_ADC2R_AD2TDC4    /*!< ADC Trigger on Timer D compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDPER        HRTIM_ADC2R_AD2TDPER   /*!< ADC Trigger on Timer D period */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMDRST        HRTIM_ADC2R_AD2TDRST   /*!< ADC Trigger on Timer D reset */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2       HRTIM_ADC2R_AD2TEC2    /*!< ADC Trigger on Timer E compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3       HRTIM_ADC2R_AD2TEC3    /*!< ADC Trigger on Timer E compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4       HRTIM_ADC2R_AD2TEC4    /*!< ADC Trigger on Timer E compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC24_TIMERST        HRTIM_ADC2R_AD2TERST   /*!< ADC Trigger on Timer E reset */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
+  * @{
+  * @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 6, 8 ,10.
+  */
+#define LL_HRTIM_ADCTRIG_SRC6810_MCMP1        (uint32_t)0x00                        /*!<  ADC extended Trigger on Master Compare 1 */
+#define LL_HRTIM_ADCTRIG_SRC6810_MCMP2        (uint32_t)0x01                        /*!<  ADC extended Trigger on Master Compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC6810_MCMP3        (uint32_t)0x02                        /*!<  ADC extended Trigger on Master Compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC6810_MCMP4        (uint32_t)0x03                        /*!<  ADC extended Trigger on Master Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC6810_MPER         (uint32_t)0x04                        /*!<  ADC extended Trigger on Master Period */
+#define LL_HRTIM_ADCTRIG_SRC6810_EEV6         (uint32_t)0x05                        /*!<  ADC extended Trigger on External Event 6 */
+#define LL_HRTIM_ADCTRIG_SRC6810_EEV7         (uint32_t)0x06                        /*!<  ADC extended Trigger on External Event 7 */
+#define LL_HRTIM_ADCTRIG_SRC6810_EEV8         (uint32_t)0x07                        /*!<  ADC extended Trigger on External Event 8 */
+#define LL_HRTIM_ADCTRIG_SRC6810_EEV9         (uint32_t)0x08                        /*!<  ADC extended Trigger on External Event 9 */
+#define LL_HRTIM_ADCTRIG_SRC6810_EEV10        (uint32_t)0x09                        /*!<  ADC extended Trigger on External Event 10 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2    (uint32_t)0x0A                        /*!<  ADC extended Trigger on Timer A Compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4    (uint32_t)0x0B                        /*!<  ADC extended Trigger on Timer A Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER     (uint32_t)0x0C                        /*!<  ADC extended Trigger on Timer A Period */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2    (uint32_t)0x0D                        /*!<  ADC extended Trigger on Timer B Compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4    (uint32_t)0x0E                        /*!<  ADC extended Trigger on Timer B Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER     (uint32_t)0x0F                        /*!<  ADC extended Trigger on Timer B Period */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2    (uint32_t)0x10                        /*!<  ADC extended Trigger on Timer C Compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4    (uint32_t)0x11                        /*!<  ADC extended Trigger on Timer C Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER     (uint32_t)0x12                        /*!<  ADC extended Trigger on Timer C Period */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST     (uint32_t)0x13                        /*!<  ADC extended Trigger on Timer C Reset and counter roll-over */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2    (uint32_t)0x14                        /*!<  ADC extended Trigger on Timer D Compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4    (uint32_t)0x15                        /*!<  ADC extended Trigger on Timer D Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER     (uint32_t)0x16                        /*!<  ADC extended Trigger on Timer D Period */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST     (uint32_t)0x17                        /*!<  ADC extended Trigger on Timer D Reset and counter roll-over */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2    (uint32_t)0x18                        /*!<  ADC extended Trigger on Timer E Compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3    (uint32_t)0x19                        /*!<  ADC extended Trigger on Timer E Compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4    (uint32_t)0x1A                        /*!<  ADC extended Trigger on Timer E Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIME_RST     (uint32_t)0x1B                        /*!<  ADC extended Trigger on Timer E Reset and counter roll-over */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2    (uint32_t)0x1C                        /*!<  ADC extended Trigger on Timer F Compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3    (uint32_t)0x1D                        /*!<  ADC extended Trigger on Timer F Compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4    (uint32_t)0x1E                        /*!<  ADC extended Trigger on Timer F Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER     (uint32_t)0x1F                        /*!<  ADC extended Trigger on Timer F Period */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_ADC_TRIG HRTIM ADC TRIGGER SELECTION
+  * @{
+  * @brief Constants defining the selection that can be used as ADC trigger source for extended ADC 5, 7 ,9.
+  */
+#define LL_HRTIM_ADCTRIG_SRC579_MCMP1           (uint32_t)0x00                        /*!<  ADC extended Trigger on Master Compare 1 */
+#define LL_HRTIM_ADCTRIG_SRC579_MCMP2           (uint32_t)0x01                        /*!<  ADC extended Trigger on Master Compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC579_MCMP3           (uint32_t)0x02                        /*!<  ADC extended Trigger on Master Compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC579_MCMP4           (uint32_t)0x03                        /*!<  ADC extended Trigger on Master Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC579_MPER            (uint32_t)0x04                        /*!<  ADC extended Trigger on Master Period */
+#define LL_HRTIM_ADCTRIG_SRC579_EEV1            (uint32_t)0x05                        /*!<  ADC extended Trigger on External Event 1 */
+#define LL_HRTIM_ADCTRIG_SRC579_EEV2            (uint32_t)0x06                        /*!<  ADC extended Trigger on External Event 2 */
+#define LL_HRTIM_ADCTRIG_SRC579_EEV3            (uint32_t)0x07                        /*!<  ADC extended Trigger on External Event 3 */
+#define LL_HRTIM_ADCTRIG_SRC579_EEV4            (uint32_t)0x08                        /*!<  ADC extended Trigger on External Event 4 */
+#define LL_HRTIM_ADCTRIG_SRC579_EEV5            (uint32_t)0x09                        /*!<  ADC extended Trigger on External Event 5 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3       (uint32_t)0x0A                        /*!<  ADC extended Trigger on Timer A Compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4       (uint32_t)0x0B                        /*!<  ADC extended Trigger on Timer A Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMA_PER        (uint32_t)0x0C                        /*!<  ADC extended Trigger on Timer A Period */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMA_RST        (uint32_t)0x0D                        /*!<  ADC extended Trigger on Timer A Period */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3       (uint32_t)0x0E                        /*!<  ADC extended Trigger on Timer B Compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4       (uint32_t)0x0F                        /*!<  ADC extended Trigger on Timer B Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMB_PER        (uint32_t)0x10                        /*!<  ADC extended Trigger on Timer B Period */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMB_RST        (uint32_t)0x11                        /*!<  ADC extended Trigger on Timer B Reset and counter roll-over */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3       (uint32_t)0x12                        /*!<  ADC extended Trigger on Timer C Compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4       (uint32_t)0x13                        /*!<  ADC extended Trigger on Timer C Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMC_PER        (uint32_t)0x14                        /*!<  ADC extended Trigger on Timer C Period */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3       (uint32_t)0x15                        /*!<  ADC extended Trigger on Timer D Compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4       (uint32_t)0x16                        /*!<  ADC extended Trigger on Timer D Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMD_PER        (uint32_t)0x17                        /*!<  ADC extended Trigger on Timer D Period */
+#define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3       (uint32_t)0x18                        /*!<  ADC extended Trigger on Timer E Compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4       (uint32_t)0x19                        /*!<  ADC extended Trigger on Timer E Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIME_PER        (uint32_t)0x1A                        /*!<  ADC extended Trigger on Timer E Period */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2       (uint32_t)0x1B                        /*!<  ADC extended Trigger on Timer F Compare 2 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3       (uint32_t)0x1C                        /*!<  ADC extended Trigger on Timer F Compare 3 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4       (uint32_t)0x1D                        /*!<  ADC extended Trigger on Timer F Compare 4 */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMF_PER        (uint32_t)0x1E                        /*!<  ADC extended Trigger on Timer F Period */
+#define LL_HRTIM_ADCTRIG_SRC579_TIMF_RST        (uint32_t)0x1F                        /*!<  ADC extended Trigger on Timer F Reset and counter roll-over */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_DLLCALIBRATION_MODE  DLL CALIBRATION MODE
+  * @{
+  * @brief Constants defining the DLL calibration mode.
+  */
+#define LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT   0x00000000U            /*!<Calibration is performed only once */
+#define LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS   HRTIM_DLLCR_CALEN      /*!<Calibration is performed periodically */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_CALIBRATIONRATE  DLL CALIBRATION RATE
+  * @{
+  * @brief Constants defining the DLL calibration periods (in micro seconds).
+  */
+#define LL_HRTIM_DLLCALIBRATION_RATE_0         0x00000000U                                    /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (6.168 ms) */
+#define LL_HRTIM_DLLCALIBRATION_RATE_1         (HRTIM_DLLCR_CALRTE_0)                         /*!< Periodic DLL calibration: T = 131072U * tHRTIM (0.771 ms) */
+#define LL_HRTIM_DLLCALIBRATION_RATE_2         (HRTIM_DLLCR_CALRTE_1)                         /*!< Periodic DLL calibration: T = 16384U * tHRTIM (0.096 ms) */
+#define LL_HRTIM_DLLCALIBRATION_RATE_3         (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)  /*!< Periodic DLL calibration: T = 2048U * tHRTIM (0.012 ms) */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_PRESCALERRATIO  PRESCALER RATIO
+  * @{
+  * @brief Constants defining timer high-resolution clock prescaler ratio.
+  */
+#define LL_HRTIM_PRESCALERRATIO_MUL32      0x00000000U              /*!< fHRCK: fHRTIM x 32 = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)      */
+#define LL_HRTIM_PRESCALERRATIO_MUL16      ((uint32_t)0x00000001U)  /*!< fHRCK: fHRTIM x 16 = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)      */
+#define LL_HRTIM_PRESCALERRATIO_MUL8       ((uint32_t)0x00000002U)  /*!< fHRCK: fHRTIM x 8 = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)      */
+#define LL_HRTIM_PRESCALERRATIO_MUL4       ((uint32_t)0x00000003U)  /*!< fHRCK: fHRTIM x 4 = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)      */
+#define LL_HRTIM_PRESCALERRATIO_MUL2       ((uint32_t)0x00000004U)  /*!< fHRCK: fHRTIM x 2 = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)      */
+#define LL_HRTIM_PRESCALERRATIO_DIV1       ((uint32_t)0x00000005U)  /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)      */
+#define LL_HRTIM_PRESCALERRATIO_DIV2       ((uint32_t)0x00000006U)  /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)      */
+#define LL_HRTIM_PRESCALERRATIO_DIV4       ((uint32_t)0x00000007U)  /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)      */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_MODE  COUNTER MODE
+  * @{
+  * @brief Constants defining timer counter operating mode.
+  */
+#define LL_HRTIM_MODE_CONTINUOUS           ((uint32_t)0x00000008U)  /*!< The timer operates in continuous (free-running) mode */
+#define LL_HRTIM_MODE_SINGLESHOT           0x00000000U              /*!< The timer operates in non retriggerable single-shot mode */
+#define LL_HRTIM_MODE_RETRIGGERABLE        ((uint32_t)0x00000010U)  /*!< The timer operates in retriggerable single-shot mode */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_DACTRIG  DAC TRIGGER
+  * @{
+  * @brief Constants defining on which output the DAC synchronization event is sent.
+  */
+#define LL_HRTIM_DACTRIG_NONE           0x00000000U                     /*!< No DAC synchronization event generated */
+#define LL_HRTIM_DACTRIG_DACTRIGOUT_1   (HRTIM_MCR_DACSYNC_0)                       /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
+#define LL_HRTIM_DACTRIG_DACTRIGOUT_2   (HRTIM_MCR_DACSYNC_1)                       /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
+#define LL_HRTIM_DACTRIG_DACTRIGOUT_3   (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_UPDATETRIG  UPDATE TRIGGER
+  * @{
+  * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.
+  */
+#define LL_HRTIM_UPDATETRIG_NONE        0x00000000U            /*!< Register update is disabled */
+#define LL_HRTIM_UPDATETRIG_MASTER      HRTIM_TIMCR_MSTU       /*!< Register update is triggered by the master timer update */
+#define LL_HRTIM_UPDATETRIG_TIMER_A     HRTIM_TIMCR_TAU        /*!< Register update is triggered by the timer A update */
+#define LL_HRTIM_UPDATETRIG_TIMER_B     HRTIM_TIMCR_TBU        /*!< Register update is triggered by the timer B update */
+#define LL_HRTIM_UPDATETRIG_TIMER_C     HRTIM_TIMCR_TCU        /*!< Register update is triggered by the timer C update*/
+#define LL_HRTIM_UPDATETRIG_TIMER_D     HRTIM_TIMCR_TDU        /*!< Register update is triggered by the timer D update */
+#define LL_HRTIM_UPDATETRIG_TIMER_E     HRTIM_TIMCR_TEU        /*!< Register update is triggered by the timer E update */
+#define LL_HRTIM_UPDATETRIG_TIMER_F     HRTIM_TIMCR_TFU        /*!< Register update is triggered by the timer F update */
+#define LL_HRTIM_UPDATETRIG_REPETITION  HRTIM_TIMCR_TREPU      /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/
+#define LL_HRTIM_UPDATETRIG_RESET       HRTIM_TIMCR_TRSTU      /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_UPDATEGATING  UPDATE GATING
+  * @{
+  * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.
+  */
+#define LL_HRTIM_UPDATEGATING_INDEPENDENT     0x00000000U                                               /*!< Update done independently from the DMA burst transfer completion */
+#define LL_HRTIM_UPDATEGATING_DMABURST        (HRTIM_TIMCR_UPDGAT_0)                                                /*!< Update done when the DMA burst transfer is completed */
+#define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)                                                /*!< Update done on timer roll-over following a DMA burst transfer completion*/
+#define LL_HRTIM_UPDATEGATING_UPDEN1          (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */
+#define LL_HRTIM_UPDATEGATING_UPDEN2          (HRTIM_TIMCR_UPDGAT_2)                                                /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */
+#define LL_HRTIM_UPDATEGATING_UPDEN3          (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */
+#define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)                         /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 1 */
+#define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)  /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */
+#define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE   (HRTIM_TIMCR_UPDGAT_3)                                                /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_COMPAREMODE  COMPARE MODE
+  * @{
+  * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.
+  */
+#define LL_HRTIM_COMPAREMODE_REGULAR          0x00000000U                         /*!< standard compare mode */
+#define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT  (HRTIM_TIMCR_DELCMP2_0)                         /*!< Compare event generated only if a capture has occurred */
+#define LL_HRTIM_COMPAREMODE_DELAY_CMP1       (HRTIM_TIMCR_DELCMP2_1)                         /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
+#define LL_HRTIM_COMPAREMODE_DELAY_CMP3       (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_RESETTRIG  RESET TRIGGER
+  * @{
+  * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.
+  */
+#define LL_HRTIM_RESETTRIG_NONE        0x00000000U            /*!< No counter reset trigger */
+#define LL_HRTIM_RESETTRIG_UPDATE      HRTIM_RSTR_UPDATE      /*!< The timer counter is reset upon update event */
+#define LL_HRTIM_RESETTRIG_CMP2        HRTIM_RSTR_CMP2        /*!< The timer counter is reset upon Timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_CMP4        HRTIM_RSTR_CMP4        /*!< The timer counter is reset upon Timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_MASTER_PER  HRTIM_RSTR_MSTPER      /*!< The timer counter is reset upon master timer period event */
+#define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1     /*!< The timer counter is reset upon master timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2     /*!< The timer counter is reset upon master timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3     /*!< The timer counter is reset upon master timer Compare 3 event */
+#define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4     /*!< The timer counter is reset upon master timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_EEV_1       HRTIM_RSTR_EXTEVNT1    /*!< The timer counter is reset upon external event 1 */
+#define LL_HRTIM_RESETTRIG_EEV_2       HRTIM_RSTR_EXTEVNT2    /*!< The timer counter is reset upon external event 2 */
+#define LL_HRTIM_RESETTRIG_EEV_3       HRTIM_RSTR_EXTEVNT3    /*!< The timer counter is reset upon external event 3 */
+#define LL_HRTIM_RESETTRIG_EEV_4       HRTIM_RSTR_EXTEVNT4    /*!< The timer counter is reset upon external event 4 */
+#define LL_HRTIM_RESETTRIG_EEV_5       HRTIM_RSTR_EXTEVNT5    /*!< The timer counter is reset upon external event 5 */
+#define LL_HRTIM_RESETTRIG_EEV_6       HRTIM_RSTR_EXTEVNT6    /*!< The timer counter is reset upon external event 6 */
+#define LL_HRTIM_RESETTRIG_EEV_7       HRTIM_RSTR_EXTEVNT7    /*!< The timer counter is reset upon external event 7 */
+#define LL_HRTIM_RESETTRIG_EEV_8       HRTIM_RSTR_EXTEVNT8    /*!< The timer counter is reset upon external event 8 */
+#define LL_HRTIM_RESETTRIG_EEV_9       HRTIM_RSTR_EXTEVNT9    /*!< The timer counter is reset upon external event 9 */
+#define LL_HRTIM_RESETTRIG_EEV_10      HRTIM_RSTR_EXTEVNT10   /*!< The timer counter is reset upon external event 10 */
+#define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
+#define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4    /*!< The timer counter is reset upon other timer Compare 4 event */
+#define LL_HRTIM_RESETTRIG_OTHER5_CMP1 HRTIM_RSTR_TIMFCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */
+#define LL_HRTIM_RESETTRIG_OTHER5_CMP2 HRTIM_RSTR_TIMFCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_CAPTURETRIG  CAPTURE TRIGGER
+  * @{
+  * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.
+  */
+#define LL_HRTIM_CAPTURETRIG_NONE       (uint64_t)0                               /*!< Capture trigger is disabled */
+#define LL_HRTIM_CAPTURETRIG_SW         (uint64_t)HRTIM_CPT1CR_SWCPT              /*!< The sw event triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_UPDATE     (uint64_t)HRTIM_CPT1CR_UPDCPT             /*!< The update event triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_1      (uint64_t)HRTIM_CPT1CR_EXEV1CPT           /*!< The External event 1 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_2      (uint64_t)HRTIM_CPT1CR_EXEV2CPT           /*!< The External event 2 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_3      (uint64_t)HRTIM_CPT1CR_EXEV3CPT           /*!< The External event 3 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_4      (uint64_t)HRTIM_CPT1CR_EXEV4CPT           /*!< The External event 4 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_5      (uint64_t)HRTIM_CPT1CR_EXEV5CPT           /*!< The External event 5 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_6      (uint64_t)HRTIM_CPT1CR_EXEV6CPT           /*!< The External event 6 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_7      (uint64_t)HRTIM_CPT1CR_EXEV7CPT           /*!< The External event 7 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_8      (uint64_t)HRTIM_CPT1CR_EXEV8CPT           /*!< The External event 8 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_9      (uint64_t)HRTIM_CPT1CR_EXEV9CPT           /*!< The External event 9 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_EEV_10     (uint64_t)HRTIM_CPT1CR_EXEV10CPT          /*!< The External event 10 triggers the Capture */
+#define LL_HRTIM_CAPTURETRIG_TA1_SET     (uint64_t)(HRTIM_CPT1CR_TA1SET   ) <<32  /*!< Capture is triggered by TA1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TA1_RESET   (uint64_t)(HRTIM_CPT1CR_TA1RST   ) <<32  /*!< Capture is triggered by TA1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMA_CMP1   (uint64_t)(HRTIM_CPT1CR_TIMACMP1 ) <<32  /*!< Timer A Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMA_CMP2   (uint64_t)(HRTIM_CPT1CR_TIMACMP2 ) <<32  /*!< Timer A Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TB1_SET     (uint64_t)(HRTIM_CPT1CR_TB1SET   ) <<32  /*!< Capture is triggered by TB1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TB1_RESET   (uint64_t)(HRTIM_CPT1CR_TB1RST   ) <<32  /*!< Capture is triggered by TB1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMB_CMP1   (uint64_t)(HRTIM_CPT1CR_TIMBCMP1 ) <<32  /*!< Timer B Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMB_CMP2   (uint64_t)(HRTIM_CPT1CR_TIMBCMP2 ) <<32  /*!< Timer B Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TC1_SET     (uint64_t)(HRTIM_CPT1CR_TC1SET   ) <<32  /*!< Capture is triggered by TC1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TC1_RESET   (uint64_t)(HRTIM_CPT1CR_TC1RST   ) <<32  /*!< Capture is triggered by TC1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMC_CMP1   (uint64_t)(HRTIM_CPT1CR_TIMCCMP1 ) <<32  /*!< Timer C Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMC_CMP2   (uint64_t)(HRTIM_CPT1CR_TIMCCMP2 ) <<32  /*!< Timer C Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TD1_SET     (uint64_t)(HRTIM_CPT1CR_TD1SET   ) <<32  /*!< Capture is triggered by TD1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TD1_RESET   (uint64_t)(HRTIM_CPT1CR_TD1RST   ) <<32  /*!< Capture is triggered by TD1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMD_CMP1   (uint64_t)(HRTIM_CPT1CR_TIMDCMP1 ) <<32  /*!< Timer D Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMD_CMP2   (uint64_t)(HRTIM_CPT1CR_TIMDCMP2 ) <<32  /*!< Timer D Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TE1_SET     (uint64_t)(HRTIM_CPT1CR_TE1SET   ) <<32  /*!< Capture is triggered by TE1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TE1_RESET   (uint64_t)(HRTIM_CPT1CR_TE1RST   ) <<32  /*!< Capture is triggered by TE1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIME_CMP1   (uint64_t)(HRTIM_CPT1CR_TIMECMP1 ) <<32  /*!< Timer E Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIME_CMP2   (uint64_t)(HRTIM_CPT1CR_TIMECMP2 ) <<32  /*!< Timer E Compare 2 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TF1_SET     (uint64_t)(HRTIM_CPT1CR_TF1SET   ) <<32  /*!< Capture is triggered by TF1 output inactive to active transition */
+#define LL_HRTIM_CAPTURETRIG_TF1_RESET   (uint64_t)(HRTIM_CPT1CR_TF1RST   ) <<32  /*!< Capture is triggered by TF1 output active to inactive transition */
+#define LL_HRTIM_CAPTURETRIG_TIMF_CMP1   (uint64_t)(HRTIM_CPT1CR_TIMFCMP1 ) <<32  /*!< Timer F Compare 1 triggers Capture */
+#define LL_HRTIM_CAPTURETRIG_TIMF_CMP2   (uint64_t)(HRTIM_CPT1CR_TIMFCMP2 ) <<32  /*!< Timer F Compare 2 triggers Capture */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_DLYPRT  DELAYED PROTECTION (DLYPRT) MODE
+  * @{
+  * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).
+  */
+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6  0x00000000U                                            /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */
+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6  (HRTIM_OUTR_DLYPRT_0)                                             /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */
+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6  (HRTIM_OUTR_DLYPRT_1)                                             /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */
+#define LL_HRTIM_DLYPRT_BALANCED_EEV6   (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)                       /*!< Timers A, B, C: Balanced Idle on external Event 6 */
+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7  (HRTIM_OUTR_DLYPRT_2)                                             /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */
+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0)                       /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */
+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1)                       /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */
+#define LL_HRTIM_DLYPRT_BALANCED_EEV7   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */
+
+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8  0x00000000U                                             /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */
+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8  (HRTIM_OUTR_DLYPRT_0)                                               /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */
+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8  (HRTIM_OUTR_DLYPRT_1)                                               /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */
+#define LL_HRTIM_DLYPRT_BALANCED_EEV8   (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)                         /*!< Timers D, E: Balanced Idle on external Event 8 */
+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9  (HRTIM_OUTR_DLYPRT_2)                                               /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */
+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0)                         /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */
+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1)                         /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */
+#define LL_HRTIM_DLYPRT_BALANCED_EEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)   /*!< Timers D, E: Balanced Idle on external Event 9 */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_BURSTMODE  BURST MODE
+  * @{
+  * @brief Constants defining how the timer behaves during a burst mode operation.
+  */
+#define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */
+#define LL_HRTIM_BURSTMODE_RESETCOUNTER  (HRTIM_BMCR_MTBM)  /*!< Timer counter clock is stopped and the counter is reset */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_BURSTDMA  BURST DMA
+  * @{
+  * @brief Constants defining the registers that can be written during a burst DMA operation.
+  */
+#define LL_HRTIM_BURSTDMA_NONE     0x00000000U               /*!< No register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCR      (HRTIM_BDMUPR_MCR)        /*!< MCR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MICR     (HRTIM_BDMUPR_MICR)       /*!< MICR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MDIER    (HRTIM_BDMUPR_MDIER)      /*!< MDIER register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCNT     (HRTIM_BDMUPR_MCNT)       /*!< MCNTR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MPER     (HRTIM_BDMUPR_MPER)       /*!< MPER register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MREP     (HRTIM_BDMUPR_MREP)       /*!< MREPR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCMP1    (HRTIM_BDMUPR_MCMP1)      /*!< MCMP1R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCMP2    (HRTIM_BDMUPR_MCMP2)      /*!< MCMP2R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCMP3    (HRTIM_BDMUPR_MCMP3)      /*!< MCMP3R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_MCMP4    (HRTIM_BDMUPR_MCMP4)      /*!< MCMP4R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMMCR   (HRTIM_BDTUPR_TIMCR)      /*!< TIMxCR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMICR   (HRTIM_BDTUPR_TIMICR)     /*!< TIMxICR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMDIER  (HRTIM_BDTUPR_TIMDIER)    /*!< TIMxDIER register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCNT   (HRTIM_BDTUPR_TIMCNT)     /*!< CNTxCR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMPER   (HRTIM_BDTUPR_TIMPER)     /*!< PERxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMREP   (HRTIM_BDTUPR_TIMREP)     /*!< REPxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCMP1  (HRTIM_BDTUPR_TIMCMP1)    /*!< CMP1xR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCMP2  (HRTIM_BDTUPR_TIMCMP2)    /*!< CMP2xR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCMP3  (HRTIM_BDTUPR_TIMCMP3)    /*!< CMP3xR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCMP4  (HRTIM_BDTUPR_TIMCMP4)    /*!< CMP4xR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMDTR   (HRTIM_BDTUPR_TIMDTR)     /*!< DTxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R)   /*!< SET1R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R)   /*!< RST1R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R)   /*!< SET2R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R)   /*!< RST1R register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1)   /*!< EEFxR1 register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2)   /*!< EEFxR2 register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMRSTR  (HRTIM_BDTUPR_TIMRSTR)    /*!< RSTxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMCHPR  (HRTIM_BDTUPR_TIMCHPR)    /*!< CHPxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMOUTR  (HRTIM_BDTUPR_TIMOUTR)    /*!< OUTxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_TIMFLTR  (HRTIM_BDTUPR_TIMFLTR)    /*!< FLTxR register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_CR2      (HRTIM_BDTUPR_TIMCR2)     /*!< TIMxCR2 register is updated by Burst DMA accesses */
+#define LL_HRTIM_BURSTDMA_EEFR3    (HRTIM_BDTUPR_TIMEEFR3)   /*!< EEFxR3 register is updated by Burst DMA accesses */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_CPPSTAT  CURRENT PUSH-PULL STATUS
+  * @{
+  * @brief Constants defining on which output the signal is currently applied in push-pull mode.
+  */
+#define LL_HRTIM_CPPSTAT_OUTPUT1   ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */
+#define LL_HRTIM_CPPSTAT_OUTPUT2   (HRTIM_TIMISR_CPPSTAT)  /*!< Signal applied on output 2 and output 1 forced inactive */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_IPPSTAT  IDLE PUSH-PULL STATUS
+  * @{
+  * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.
+  */
+#define LL_HRTIM_IPPSTAT_OUTPUT1   ((uint32_t) 0x00000000U)    /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
+#define LL_HRTIM_IPPSTAT_OUTPUT2   (HRTIM_TIMISR_IPPSTAT)     /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER
+  * @{
+  * @brief Constants defining the event filtering applied to external events by a timer.
+  */
+#define LL_HRTIM_EEFLTR_NONE                            (0x00000000U)
+#define LL_HRTIM_EEFLTR_BLANKINGCMP1                    (HRTIM_EEFR1_EE1FLTR_0)                                                   /*!< Blanking from counter reset/roll-over to Compare 1U */
+#define LL_HRTIM_EEFLTR_BLANKINGCMP2                    (HRTIM_EEFR1_EE1FLTR_1)                                                   /*!< Blanking from counter reset/roll-over to Compare 2U */
+#define LL_HRTIM_EEFLTR_BLANKINGCMP3                    (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from counter reset/roll-over to Compare 3U */
+#define LL_HRTIM_EEFLTR_BLANKINGCMP4                    (HRTIM_EEFR1_EE1FLTR_2)                                                   /*!< Blanking from counter reset/roll-over to Compare 4U */
+/* Blanking Filter for TIMER A */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
+/* Blanking Filter for TIMER B */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
+/* Blanking Filter for TIMER C */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
+/* Blanking Filter for TIMER D */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
+/* Blanking Filter for TIMER E */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
+/* Blanking Filter for TIMER F */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR1 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR2 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4      (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR3 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2      (HRTIM_EEFR1_EE1FLTR_3)                                                   /*!< Blanking from another timing unit: TIMFLTR4 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                           /*!< Blanking from another timing unit: TIMFLTR5 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                           /*!< Blanking from another timing unit: TIMFLTR6 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Blanking from another timing unit: TIMFLTR7 source */
+#define LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2      (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                           /*!< Blanking from another timing unit: TIMFLTR8 source */
+
+#define LL_HRTIM_EEFLTR_WINDOWINGCMP2                   (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)   /*!< Windowing from counter reset/roll-over to Compare 2U */
+#define LL_HRTIM_EEFLTR_WINDOWINGCMP3                   (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)   /*!< Windowing from counter reset/roll-over to Compare 3U */
+#define LL_HRTIM_EEFLTR_WINDOWINGTIM                    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1\
+                                                         | HRTIM_EEFR1_EE1FLTR_0)   /*!< Windowing from another timing unit: TIMWIN source */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS
+  * @{
+  * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.
+  */
+#define LL_HRTIM_EELATCH_DISABLED    0x00000000U             /*!< Event is ignored if it happens during a blank, or passed through during a window */
+#define LL_HRTIM_EELATCH_ENABLED     HRTIM_EEFR1_EE1LTCH     /*!< Event is latched and delayed till the end of the blanking or windowing period */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER
+  * @{
+  * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).
+  */
+#define LL_HRTIM_DT_PRESCALER_MUL8    0x00000000U                                         /*!< fDTG = fHRTIM * 8 */
+#define LL_HRTIM_DT_PRESCALER_MUL4    (HRTIM_DTR_DTPRSC_0)                                            /*!< fDTG = fHRTIM * 4 */
+#define LL_HRTIM_DT_PRESCALER_MUL2    (HRTIM_DTR_DTPRSC_1)                                            /*!< fDTG = fHRTIM * 2 */
+#define LL_HRTIM_DT_PRESCALER_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM */
+#define LL_HRTIM_DT_PRESCALER_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2 */
+#define LL_HRTIM_DT_PRESCALER_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4 */
+#define LL_HRTIM_DT_PRESCALER_DIV8    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)                       /*!< fDTG = fHRTIM / 8 */
+#define LL_HRTIM_DT_PRESCALER_DIV16   (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)  /*!< fDTG = fHRTIM / 16 */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN
+  * @{
+  * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.
+  */
+#define LL_HRTIM_DT_RISING_POSITIVE    0x00000000U             /*!< Positive deadtime on rising edge */
+#define LL_HRTIM_DT_RISING_NEGATIVE    (HRTIM_DTR_SDTR)        /*!< Negative deadtime on rising edge */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN
+  * @{
+  * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.
+  */
+#define LL_HRTIM_DT_FALLING_POSITIVE    0x00000000U             /*!< Positive deadtime on falling edge */
+#define LL_HRTIM_DT_FALLING_NEGATIVE    (HRTIM_DTR_SDTF)        /*!< Negative deadtime on falling edge */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER
+  * @{
+  * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).
+  */
+#define LL_HRTIM_CHP_PRESCALER_DIV16  0x00000000U                                                                     /*!< fCHPFRQ = fHRTIM / 16  */
+#define LL_HRTIM_CHP_PRESCALER_DIV32  (HRTIM_CHPR_CARFRQ_0)                                                                    /*!< fCHPFRQ = fHRTIM / 32  */
+#define LL_HRTIM_CHP_PRESCALER_DIV48  (HRTIM_CHPR_CARFRQ_1)                                                                    /*!< fCHPFRQ = fHRTIM / 48  */
+#define LL_HRTIM_CHP_PRESCALER_DIV64  (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 64  */
+#define LL_HRTIM_CHP_PRESCALER_DIV80  (HRTIM_CHPR_CARFRQ_2)                                                                    /*!< fCHPFRQ = fHRTIM / 80  */
+#define LL_HRTIM_CHP_PRESCALER_DIV96  (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 96  */
+#define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 112  */
+#define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 128  */
+#define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3)                                                                    /*!< fCHPFRQ = fHRTIM / 144  */
+#define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 160  */
+#define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 176  */
+#define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 192  */
+#define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)                                              /*!< fCHPFRQ = fHRTIM / 208  */
+#define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 224  */
+#define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                        /*!< fCHPFRQ = fHRTIM / 240  */
+#define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)  /*!< fCHPFRQ = fHRTIM / 256  */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE
+  * @{
+  * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).
+  */
+#define LL_HRTIM_CHP_DUTYCYCLE_0    0x00000000U                                              /*!< Only 1st pulse is present */
+#define LL_HRTIM_CHP_DUTYCYCLE_125  (HRTIM_CHPR_CARDTY_0)                                             /*!< Duty cycle of the carrier signal is 12.5 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_250  (HRTIM_CHPR_CARDTY_1)                                             /*!< Duty cycle of the carrier signal is 25 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_375  (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 37.5 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_500  (HRTIM_CHPR_CARDTY_2)                                             /*!< Duty cycle of the carrier signal is 50 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_625  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 62.5 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_750  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)                       /*!< Duty cycle of the carrier signal is 75 % */
+#define LL_HRTIM_CHP_DUTYCYCLE_875  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH
+  * @{
+  * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.
+  */
+#define LL_HRTIM_CHP_PULSEWIDTH_16   0x00000000U                                                                 /*!< tSTPW = tHRTIM x 16  */
+#define LL_HRTIM_CHP_PULSEWIDTH_32   (HRTIM_CHPR_STRPW_0)                                                                 /*!< tSTPW = tHRTIM x 32  */
+#define LL_HRTIM_CHP_PULSEWIDTH_48   (HRTIM_CHPR_STRPW_1)                                                                 /*!< tSTPW = tHRTIM x 48  */
+#define LL_HRTIM_CHP_PULSEWIDTH_64   (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 64  */
+#define LL_HRTIM_CHP_PULSEWIDTH_80   (HRTIM_CHPR_STRPW_2)                                                                 /*!< tSTPW = tHRTIM x 80  */
+#define LL_HRTIM_CHP_PULSEWIDTH_96   (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 96  */
+#define LL_HRTIM_CHP_PULSEWIDTH_112  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 112  */
+#define LL_HRTIM_CHP_PULSEWIDTH_128  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 128  */
+#define LL_HRTIM_CHP_PULSEWIDTH_144  (HRTIM_CHPR_STRPW_3)                                                                 /*!< tSTPW = tHRTIM x 144  */
+#define LL_HRTIM_CHP_PULSEWIDTH_160  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 160  */
+#define LL_HRTIM_CHP_PULSEWIDTH_176  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 176  */
+#define LL_HRTIM_CHP_PULSEWIDTH_192  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 192  */
+#define LL_HRTIM_CHP_PULSEWIDTH_208  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)                                            /*!< tSTPW = tHRTIM x 208  */
+#define LL_HRTIM_CHP_PULSEWIDTH_224  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 224  */
+#define LL_HRTIM_CHP_PULSEWIDTH_240  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                       /*!< tSTPW = tHRTIM x 240  */
+#define LL_HRTIM_CHP_PULSEWIDTH_256  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)  /*!< tSTPW = tHRTIM x 256  */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_OUTPUTSET_INPUT OUTPUTSET INPUT
+  * @{
+  * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.
+  */
+#define LL_HRTIM_OUTPUTSET_NONE                0x00000000U             /*!< Reset the output set crossbar */
+#define LL_HRTIM_OUTPUTSET_RESYNC              (HRTIM_SET1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_TIMPER              (HRTIM_SET1R_PER)       /*!< Timer period event forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_TIMCMP1             (HRTIM_SET1R_CMP1)      /*!< Timer compare 1 event forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_TIMCMP2             (HRTIM_SET1R_CMP2)      /*!< Timer compare 2 event forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_TIMCMP3             (HRTIM_SET1R_CMP3)      /*!< Timer compare 3 event forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_TIMCMP4             (HRTIM_SET1R_CMP4)      /*!< Timer compare 4 event forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_MASTERPER           (HRTIM_SET1R_MSTPER)    /*!< The master timer period event forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_MASTERCMP1          (HRTIM_SET1R_MSTCMP1)   /*!< Master Timer compare 1 event forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_MASTERCMP2          (HRTIM_SET1R_MSTCMP2)   /*!< Master Timer compare 2 event forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_MASTERCMP3          (HRTIM_SET1R_MSTCMP3)   /*!< Master Timer compare 3 event forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_MASTERCMP4          (HRTIM_SET1R_MSTCMP4)   /*!< Master Timer compare 4 event forces an output level transition */
+/* Timer Events mapping for Timer A */
+#define LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
+/* Timer Events mapping for Timer B */
+#define LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
+/* Timer Events mapping for Timer C */
+#define LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
+/* Timer Events mapping for Timer D */
+#define LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
+/* Timer Events mapping for Timer E */
+#define LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
+/* Timer Events mapping for Timer F */
+#define LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its active state */
+#define LL_HRTIM_OUTPUTSET_EEV_1               (HRTIM_SET1R_EXTVNT1)   /*!< External event 1 forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_EEV_2               (HRTIM_SET1R_EXTVNT2)   /*!< External event 2 forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_EEV_3               (HRTIM_SET1R_EXTVNT3)   /*!< External event 3 forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_EEV_4               (HRTIM_SET1R_EXTVNT4)   /*!< External event 4 forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_EEV_5               (HRTIM_SET1R_EXTVNT5)   /*!< External event 5 forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_EEV_6               (HRTIM_SET1R_EXTVNT6)   /*!< External event 6 forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_EEV_7               (HRTIM_SET1R_EXTVNT7)   /*!< External event 7 forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_EEV_8               (HRTIM_SET1R_EXTVNT8)   /*!< External event 8 forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_EEV_9               (HRTIM_SET1R_EXTVNT9)   /*!< External event 9 forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_EEV_10              (HRTIM_SET1R_EXTVNT10)  /*!< External event 10 forces an output level transition */
+#define LL_HRTIM_OUTPUTSET_UPDATE              (HRTIM_SET1R_UPDATE)    /*!< Timer register update event forces an output level transition */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
+  * @{
+  * @brief Constants defining the events that can be selected to configure the
+  *        set crossbar of a timer output
+  */
+#define LL_HRTIM_OUTPUTRESET_NONE                0x00000000U             /*!< Reset the output reset crossbar */
+#define LL_HRTIM_OUTPUTRESET_RESYNC              (HRTIM_RST1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMPER              (HRTIM_RST1R_PER)       /*!< Timer period event forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMCMP1             (HRTIM_RST1R_CMP1)      /*!< Timer compare 1 event forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMCMP2             (HRTIM_RST1R_CMP2)      /*!< Timer compare 2 event forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMCMP3             (HRTIM_RST1R_CMP3)      /*!< Timer compare 3 event forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMCMP4             (HRTIM_RST1R_CMP4)      /*!< Timer compare 4 event forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_MASTERPER           (HRTIM_RST1R_MSTPER)    /*!< The master timer period event forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_MASTERCMP1          (HRTIM_RST1R_MSTCMP1)   /*!< Master Timer compare 1 event forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_MASTERCMP2          (HRTIM_RST1R_MSTCMP2)   /*!< Master Timer compare 2 event forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_MASTERCMP3          (HRTIM_RST1R_MSTCMP3)   /*!< Master Timer compare 3 event forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_MASTERCMP4          (HRTIM_RST1R_MSTCMP4)   /*!< Master Timer compare 4 event forces the output to its inactive state */
+/* Timer Events mapping for Timer A */
+#define LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
+/* Timer Events mapping for Timer B */
+#define LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
+/* Timer Events mapping for Timer C */
+#define LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
+/* Timer Events mapping for Timer D */
+#define LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
+/* Timer Events mapping for Timer E */
+#define LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
+/* Timer Events mapping for Timer F */
+#define LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3    (HRTIM_RST1R_TIMEVNT1)  /*!< Timer event 1 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1    (HRTIM_RST1R_TIMEVNT2)  /*!< Timer event 2 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4    (HRTIM_RST1R_TIMEVNT3)  /*!< Timer event 3 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1    (HRTIM_RST1R_TIMEVNT4)  /*!< Timer event 4 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4    (HRTIM_RST1R_TIMEVNT5)  /*!< Timer event 5 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3    (HRTIM_RST1R_TIMEVNT6)  /*!< Timer event 6 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4    (HRTIM_RST1R_TIMEVNT7)  /*!< Timer event 7 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2    (HRTIM_RST1R_TIMEVNT8)  /*!< Timer event 8 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3    (HRTIM_RST1R_TIMEVNT9)  /*!< Timer event 9 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_EEV_1               (HRTIM_RST1R_EXTVNT1)   /*!< External event 1 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_EEV_2               (HRTIM_RST1R_EXTVNT2)   /*!< External event 2 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_EEV_3               (HRTIM_RST1R_EXTVNT3)   /*!< External event 3 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_EEV_4               (HRTIM_RST1R_EXTVNT4)   /*!< External event 4 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_EEV_5               (HRTIM_RST1R_EXTVNT5)   /*!< External event 5 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_EEV_6               (HRTIM_RST1R_EXTVNT6)   /*!< External event 6 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_EEV_7               (HRTIM_RST1R_EXTVNT7)   /*!< External event 7 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_EEV_8               (HRTIM_RST1R_EXTVNT8)   /*!< External event 8 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_EEV_9               (HRTIM_RST1R_EXTVNT9)   /*!< External event 9 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_EEV_10              (HRTIM_RST1R_EXTVNT10)  /*!< External event 10 forces the output to its inactive state */
+#define LL_HRTIM_OUTPUTRESET_UPDATE              (HRTIM_RST1R_UPDATE)    /*!< Timer register update event forces the output to its inactive state */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY
+  * @{
+  * @brief Constants defining the polarity of a timer output.
+  */
+#define LL_HRTIM_OUT_POSITIVE_POLARITY    0x00000000U             /*!< Output is active HIGH */
+#define LL_HRTIM_OUT_NEGATIVE_POLARITY    (HRTIM_OUTR_POL1)       /*!< Output is active LOW */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE
+  * @{
+  * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.
+  */
+#define LL_HRTIM_OUT_NO_IDLE             0x00000000U            /*!< The output is not affected by the burst mode operation */
+#define LL_HRTIM_OUT_IDLE_WHEN_BURST     (HRTIM_OUTR_IDLM1)     /*!< The output is in idle state when requested by the burst mode controller */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_INTLVD_MODE INTLVD MODE
+  * @{
+  * @brief Constants defining the interleaved mode of an HRTIM Timer instance.
+  */
+#define LL_HRTIM_INTERLEAVED_MODE_DISABLED   0x000U              /*!< HRTIM interleaved Mode is disabled */
+#define LL_HRTIM_INTERLEAVED_MODE_DUAL       HRTIM_MCR_HALF      /*!< HRTIM interleaved Mode is Dual */
+#define LL_HRTIM_INTERLEAVED_MODE_TRIPLE     HRTIM_MCR_INTLVD_0  /*!< HRTIM interleaved Mode is Triple */
+#define LL_HRTIM_INTERLEAVED_MODE_QUAD       HRTIM_MCR_INTLVD_1  /*!< HRTIM interleaved Mode is Quad */
+/**
+  * @}
+  */
+/** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE
+  * @{
+  * @brief Constants defining the half mode of an HRTIM Timer instance.
+  */
+#define LL_HRTIM_HALF_MODE_DISABLED          0x000U              /*!< HRTIM Half Mode is disabled */
+#define LL_HRTIM_HALF_MODE_ENABLE            HRTIM_MCR_HALF      /*!< HRTIM Half Mode is Half */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL
+  * @{
+  * @brief Constants defining the output level when output is in IDLE state
+  */
+#define LL_HRTIM_OUT_IDLELEVEL_INACTIVE   0x00000000U           /*!< Output at inactive level when in IDLE state */
+#define LL_HRTIM_OUT_IDLELEVEL_ACTIVE     (HRTIM_OUTR_IDLES1)   /*!< Output at active level when in IDLE state */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE
+  * @{
+  * @brief Constants defining the output level when output is in FAULT state.
+  */
+#define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U                      /*!< The output is not affected by the fault input */
+#define LL_HRTIM_OUT_FAULTSTATE_ACTIVE    (HRTIM_OUTR_FAULT1_0)                        /*!< Output at active level when in FAULT state */
+#define LL_HRTIM_OUT_FAULTSTATE_INACTIVE  (HRTIM_OUTR_FAULT1_1)                        /*!< Output at inactive level when in FAULT state */
+#define LL_HRTIM_OUT_FAULTSTATE_HIGHZ     (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)  /*!< Output is tri-stated when in FAULT state */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE
+  * @{
+  * @brief Constants defining whether or not chopper mode is enabled for a timer output.
+  */
+#define LL_HRTIM_OUT_CHOPPERMODE_DISABLED   0x00000000U             /*!< Output signal is not altered  */
+#define LL_HRTIM_OUT_CHOPPERMODE_ENABLED    (HRTIM_OUTR_CHP1)       /*!< Output signal is chopped by a carrier signal  */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE
+  * @{
+  * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state
+during a programmable period before the output takes its idle state.
+  */
+#define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR   0x00000000U            /*!< The programmed Idle state is applied immediately to the Output */
+#define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED   (HRTIM_OUTR_DIDL1)     /*!< Deadtime is inserted on output before entering the idle mode */
+/**
+  * @}
+  */
+/** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL
+  * @{
+  * @brief Constants defining the level of a timer output.
+  */
+#define LL_HRTIM_OUT_LEVEL_INACTIVE   0x00000000U            /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */
+#define LL_HRTIM_OUT_LEVEL_ACTIVE     ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE
+  * @{
+  * @brief Constants defining available sources associated to external events.
+  */
+#define LL_HRTIM_EEV1SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 1 */
+#define LL_HRTIM_EEV2SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 2 */
+#define LL_HRTIM_EEV3SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 3 */
+#define LL_HRTIM_EEV4SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 4 */
+#define LL_HRTIM_EEV5SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 5 */
+#define LL_HRTIM_EEV6SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 6 */
+#define LL_HRTIM_EEV7SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 7 */
+#define LL_HRTIM_EEV8SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 8 */
+#define LL_HRTIM_EEV9SRC_GPIO        0x00000000U                                   /*!< External event source 1 for External Event 9 */
+#define LL_HRTIM_EEV10SRC_GPIO       0x00000000U                                   /*!< External event source 1 for External Event 10 */
+#define LL_HRTIM_EEV1SRC_COMP2_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 1 */
+#define LL_HRTIM_EEV2SRC_COMP4_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 2 */
+#define LL_HRTIM_EEV3SRC_COMP6_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 3 */
+#define LL_HRTIM_EEV4SRC_COMP1_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 4 */
+#define LL_HRTIM_EEV5SRC_COMP3_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 5 */
+#define LL_HRTIM_EEV6SRC_COMP2_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 6 */
+#define LL_HRTIM_EEV7SRC_COMP4_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 7 */
+#define LL_HRTIM_EEV8SRC_COMP6_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 8 */
+#define LL_HRTIM_EEV9SRC_COMP5_OUT   (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 9 */
+#define LL_HRTIM_EEV10SRC_COMP7_OUT  (HRTIM_EECR1_EE1SRC_0)                        /*!< External event source 2 for External Event 10 */
+#define LL_HRTIM_EEV1SRC_TIM1_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 1 */
+#define LL_HRTIM_EEV2SRC_TIM2_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 2 */
+#define LL_HRTIM_EEV3SRC_TIM3_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 3 */
+#define LL_HRTIM_EEV4SRC_COMP5_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 4 */
+#define LL_HRTIM_EEV5SRC_COMP7_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 5 */
+#define LL_HRTIM_EEV6SRC_COMP1_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 6 */
+#define LL_HRTIM_EEV7SRC_TIM7_TRGO   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 7 */
+#define LL_HRTIM_EEV8SRC_COMP3_OUT   (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 8 */
+#define LL_HRTIM_EEV9SRC_TIM15_TRGO  (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 9 */
+#define LL_HRTIM_EEV10SRC_TIM6_TRGO  (HRTIM_EECR1_EE1SRC_1)                        /*!< External event source 3 for External Event 10 */
+#define LL_HRTIM_EEV1SRC_ADC1_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 1 */
+#define LL_HRTIM_EEV2SRC_ADC1_AWD2   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 2 */
+#define LL_HRTIM_EEV3SRC_ADC1_AWD3   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 3 */
+#define LL_HRTIM_EEV4SRC_ADC2_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 4 */
+#define LL_HRTIM_EEV5SRC_ADC2_AWD2   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 5 */
+#define LL_HRTIM_EEV6SRC_ADC2_AWD3   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 6 */
+#define LL_HRTIM_EEV7SRC_ADC3_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 7 */
+#define LL_HRTIM_EEV8SRC_ADC4_AWD1   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 8 */
+#define LL_HRTIM_EEV9SRC_COMP4_OUT   (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 9 */
+#define LL_HRTIM_EEV10SRC_ADC5_AWD1  (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4 for External Event 10 */
+/**
+  * @}
+  */
+/** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY
+  * @{
+  * @brief Constants defining the polarity of an external event.
+  */
+#define LL_HRTIM_EE_POLARITY_HIGH    0x00000000U             /*!< External event is active high */
+#define LL_HRTIM_EE_POLARITY_LOW     (HRTIM_EECR1_EE1POL)    /*!< External event is active low */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY
+  * @{
+  * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.
+  */
+#define LL_HRTIM_EE_SENSITIVITY_LEVEL          0x00000000U                        /*!< External event is active on level */
+#define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE     (HRTIM_EECR1_EE1SNS_0)                         /*!< External event is active on Rising edge */
+#define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE    (HRTIM_EECR1_EE1SNS_1)                         /*!< External event is active on Falling edge */
+#define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES      (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)  /*!< External event is active on Rising and Falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE
+  * @{
+  * @brief Constants defining whether or not an external event is programmed in fast mode.
+  */
+#define LL_HRTIM_EE_FASTMODE_DISABLE         0x00000000U              /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
+#define LL_HRTIM_EE_FASTMODE_ENABLE          (HRTIM_EECR1_EE1FAST)    /*!< External Event is acting asynchronously on outputs (low latency mode) */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER
+  * @{
+  * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.
+  */
+#define LL_HRTIM_EE_FILTER_NONE      0x00000000U                                                               /*!< Filter disabled */
+#define LL_HRTIM_EE_FILTER_1         (HRTIM_EECR3_EE6F_0)                                                                  /*!< fSAMPLING = fHRTIM, N=2 */
+#define LL_HRTIM_EE_FILTER_2         (HRTIM_EECR3_EE6F_1)                                                                  /*!< fSAMPLING = fHRTIM, N=4 */
+#define LL_HRTIM_EE_FILTER_3         (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fHRTIM, N=8 */
+#define LL_HRTIM_EE_FILTER_4         (HRTIM_EECR3_EE6F_2)                                                                  /*!< fSAMPLING = fEEVS/2, N=6 */
+#define LL_HRTIM_EE_FILTER_5         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fEEVS/2, N=8 */
+#define LL_HRTIM_EE_FILTER_6         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING = fEEVS/4, N=6 */
+#define LL_HRTIM_EE_FILTER_7         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING = fEEVS/4, N=8 */
+#define LL_HRTIM_EE_FILTER_8         (HRTIM_EECR3_EE6F_3)                                                                  /*!< fSAMPLING = fEEVS/8, N=6 */
+#define LL_HRTIM_EE_FILTER_9         (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fEEVS/8, N=8 */
+#define LL_HRTIM_EE_FILTER_10        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING = fEEVS/16, N=5 */
+#define LL_HRTIM_EE_FILTER_11        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING = fEEVS/16, N=6 */
+#define LL_HRTIM_EE_FILTER_12        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)                                             /*!< fSAMPLING = fEEVS/16, N=8 */
+#define LL_HRTIM_EE_FILTER_13        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_0)                       /*!< fSAMPLING = fEEVS/32, N=5 */
+#define LL_HRTIM_EE_FILTER_14        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1)                       /*!< fSAMPLING = fEEVS/32, N=6 */
+#define LL_HRTIM_EE_FILTER_15        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)  /*!< fSAMPLING = fEEVS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER
+  * @{
+  * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.
+  */
+#define LL_HRTIM_EE_PRESCALER_DIV1    0x00000000U                     /*!< fEEVS = fHRTIM */
+#define LL_HRTIM_EE_PRESCALER_DIV2    (HRTIM_EECR3_EEVSD_0)                       /*!< fEEVS = fHRTIM / 2 */
+#define LL_HRTIM_EE_PRESCALER_DIV4    (HRTIM_EECR3_EEVSD_1)                       /*!< fEEVS = fHRTIM / 4 */
+#define LL_HRTIM_EE_PRESCALER_DIV8    (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_EE_COUNTER EXTERNAL EVENT A or B COUNTER
+  * @{
+  * @brief Constants defining the external event counter.
+  */
+#define LL_HRTIM_EE_COUNTER_A    ((uint32_t)0U)                     /*!< External Event A Counter */
+#define LL_HRTIM_EE_COUNTER_B    ((uint32_t)16U)                    /*!< External Event B Counter */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_EE_COUNTERRSTMODE EXTERNAL EVENT A or B RESET MODE
+  * @{
+  * @brief Constants defining the external event reset mode.
+  */
+#define LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL   ((uint32_t)0U)                     /*!< External Event counter is reset on each reset / roll-over event */
+#define LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL     ((uint32_t)HRTIM_EEFR3_EEVARSTM)   /*!< External Event counter is reset on each reset / roll-over event only if no event occurs during last counting period */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE
+  * @{
+  * @brief Constants defining whether a faults is be triggered by any external or internal fault source.
+  */
+#define LL_HRTIM_FLT_SRC_DIGITALINPUT         0x00000000U                /*!< Fault input is FLT input pin */
+#define LL_HRTIM_FLT_SRC_INTERNAL             HRTIM_FLTINR1_FLT1SRC_0    /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
+#define LL_HRTIM_FLT_SRC_EEVINPUT             HRTIM_FLTINR2_FLT1SRC_1    /*!< Fault input is external event  pin */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY
+  * @{
+  * @brief Constants defining the polarity of a fault event.
+  */
+#define LL_HRTIM_FLT_POLARITY_LOW     0x00000000U                /*!< Fault input is active low */
+#define LL_HRTIM_FLT_POLARITY_HIGH    (HRTIM_FLTINR1_FLT1P)      /*!< Fault input is active high */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER
+  * @{
+  * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.
+  */
+#define LL_HRTIM_FLT_FILTER_NONE      0x00000000U                                                                          /*!< Filter disabled */
+#define LL_HRTIM_FLT_FILTER_1         (HRTIM_FLTINR1_FLT1F_0)                                                                          /*!< fSAMPLING= fHRTIM, N=2 */
+#define LL_HRTIM_FLT_FILTER_2         (HRTIM_FLTINR1_FLT1F_1)                                                                          /*!< fSAMPLING= fHRTIM, N=4 */
+#define LL_HRTIM_FLT_FILTER_3         (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fHRTIM, N=8 */
+#define LL_HRTIM_FLT_FILTER_4         (HRTIM_FLTINR1_FLT1F_2)                                                                          /*!< fSAMPLING= fFLTS/2, N=6 */
+#define LL_HRTIM_FLT_FILTER_5         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/2, N=8 */
+#define LL_HRTIM_FLT_FILTER_6         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/4, N=6 */
+#define LL_HRTIM_FLT_FILTER_7         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/4, N=8 */
+#define LL_HRTIM_FLT_FILTER_8         (HRTIM_FLTINR1_FLT1F_3)                                                                          /*!< fSAMPLING= fFLTS/8, N=6 */
+#define LL_HRTIM_FLT_FILTER_9         (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/8, N=8 */
+#define LL_HRTIM_FLT_FILTER_10        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/16, N=5 */
+#define LL_HRTIM_FLT_FILTER_11        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/16, N=6 */
+#define LL_HRTIM_FLT_FILTER_12        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)                                                  /*!< fSAMPLING= fFLTS/16, N=8 */
+#define LL_HRTIM_FLT_FILTER_13        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/32, N=5 */
+#define LL_HRTIM_FLT_FILTER_14        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                          /*!< fSAMPLING= fFLTS/32, N=6 */
+#define LL_HRTIM_FLT_FILTER_15        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)  /*!< fSAMPLING= fFLTS/32, N=8 */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER
+  * @{
+  * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used  by the digital filters.
+  */
+#define LL_HRTIM_FLT_PRESCALER_DIV1    0x00000000U                                     /*!< fFLTS = fHRTIM */
+#define LL_HRTIM_FLT_PRESCALER_DIV2    (HRTIM_FLTINR2_FLTSD_0)                         /*!< fFLTS = fHRTIM / 2 */
+#define LL_HRTIM_FLT_PRESCALER_DIV4    (HRTIM_FLTINR2_FLTSD_1)                         /*!< fFLTS = fHRTIM / 4 */
+#define LL_HRTIM_FLT_PRESCALER_DIV8    (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_FLT_BLKS FAULT BLANKING Source
+  * @{
+  * @brief Constants defining the Blanking Source of a fault event.
+  */
+#define LL_HRTIM_FLT_BLANKING_RSTALIGNED            0x00000000U                /*!< Fault blanking source is Reset-aligned  */
+#define LL_HRTIM_FLT_BLANKING_MOVING                (HRTIM_FLTINR3_FLT1BLKS)   /*!< Fault blanking source is Moving window */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_FLT_RSTM FAULT Counter RESET Mode
+  * @{
+  * @brief Constants defining the Counter RESet Mode of a fault event.
+  */
+#define LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL    0x00000000U                    /*!< Fault counter is reset on each reset / roll-over event */
+#define LL_HRTIM_FLT_COUNTERRST_CONDITIONAL      (HRTIM_FLTINR3_FLT1RSTM)       /*!< Fault counter is reset on each reset / roll-over event only if no fault occurred during last counting
+period. */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE
+  * @{
+  * @brief Constants defining if the burst mode is entered once or if it is continuously operating.
+  */
+#define LL_HRTIM_BM_MODE_SINGLESHOT  0x00000000U            /*!< Burst mode operates in single shot mode */
+#define LL_HRTIM_BM_MODE_CONTINOUS   (HRTIM_BMCR_BMOM)      /*!< Burst mode operates in continuous mode */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE
+  * @{
+  * @brief Constants defining the clock source for the burst mode counter.
+  */
+#define LL_HRTIM_BM_CLKSRC_MASTER     0x00000000U                                         /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_A    (HRTIM_BMCR_BMCLK_0)                                            /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_B    (HRTIM_BMCR_BMCLK_1)                                            /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_C    (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_D    (HRTIM_BMCR_BMCLK_2)                                            /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_E    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIMER_F    (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< Timer F counter reset/roll-over is used as clock source for the burst mode counter */
+#define LL_HRTIM_BM_CLKSRC_TIM16_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)                       /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
+#define LL_HRTIM_BM_CLKSRC_TIM17_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
+#define LL_HRTIM_BM_CLKSRC_TIM7_TRGO  (HRTIM_BMCR_BMCLK_3)                                            /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
+#define LL_HRTIM_BM_CLKSRC_FHRTIM     (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)                       /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER
+  * @{
+  * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).
+  */
+#define LL_HRTIM_BM_PRESCALER_DIV1     0x00000000U                                                                 /*!< fBRST = fHRTIM */
+#define LL_HRTIM_BM_PRESCALER_DIV2     (HRTIM_BMCR_BMPRSC_0)                                                                   /*!< fBRST = fHRTIM/2 */
+#define LL_HRTIM_BM_PRESCALER_DIV4     (HRTIM_BMCR_BMPRSC_1)                                                                   /*!< fBRST = fHRTIM/4 */
+#define LL_HRTIM_BM_PRESCALER_DIV8     (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/8 */
+#define LL_HRTIM_BM_PRESCALER_DIV16    (HRTIM_BMCR_BMPRSC_2)                                                                   /*!< fBRST = fHRTIM/16 */
+#define LL_HRTIM_BM_PRESCALER_DIV32    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/32 */
+#define LL_HRTIM_BM_PRESCALER_DIV64    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/64 */
+#define LL_HRTIM_BM_PRESCALER_DIV128   (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/128 */
+#define LL_HRTIM_BM_PRESCALER_DIV256   (HRTIM_BMCR_BMPRSC_3)                                                                   /*!< fBRST = fHRTIM/256 */
+#define LL_HRTIM_BM_PRESCALER_DIV512   (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/512 */
+#define LL_HRTIM_BM_PRESCALER_DIV1024  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/1024 */
+#define LL_HRTIM_BM_PRESCALER_DIV2048  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/2048*/
+#define LL_HRTIM_BM_PRESCALER_DIV4096  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)                                             /*!< fBRST = fHRTIM/4096 */
+#define LL_HRTIM_BM_PRESCALER_DIV8192  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/8192 */
+#define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                       /*!< fBRST = fHRTIM/16384 */
+#define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER
+  * @{
+  * @brief Constants defining the events that can be used to trig the burst mode operation.
+  */
+#define LL_HRTIM_BM_TRIG_NONE               0x00000000U             /*!<  No trigger */
+#define LL_HRTIM_BM_TRIG_MASTER_RESET       (HRTIM_BMTRGR_MSTRST)   /*!<  Master timer reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_REPETITION  (HRTIM_BMTRGR_MSTREP)   /*!<  Master timer repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_CMP1        (HRTIM_BMTRGR_MSTCMP1)  /*!<  Master timer compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_CMP2        (HRTIM_BMTRGR_MSTCMP2)  /*!<  Master timer compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_CMP3        (HRTIM_BMTRGR_MSTCMP3)  /*!<  Master timer compare 3 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_MASTER_CMP4        (HRTIM_BMTRGR_MSTCMP4)  /*!<  Master timer compare 4 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_RESET         (HRTIM_BMTRGR_TARST)    /*!< Timer A reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_REPETITION    (HRTIM_BMTRGR_TAREP)    /*!< Timer A repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_CMP1          (HRTIM_BMTRGR_TACMP1)   /*!< Timer A compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_CMP2          (HRTIM_BMTRGR_TACMP2)   /*!< Timer A compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMB_RESET         (HRTIM_BMTRGR_TBRST)    /*!< Timer B reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMB_REPETITION    (HRTIM_BMTRGR_TBREP)    /*!< Timer B repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMB_CMP1          (HRTIM_BMTRGR_TBCMP1)   /*!< Timer B compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMB_CMP2          (HRTIM_BMTRGR_TBCMP2)   /*!< Timer B compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMC_RESET         (HRTIM_BMTRGR_TCRST)    /*!< Timer C resetevent is starting the burst mode operation  */
+#define LL_HRTIM_BM_TRIG_TIMC_REPETITION    (HRTIM_BMTRGR_TCREP)    /*!< Timer C repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMC_CMP1          (HRTIM_BMTRGR_TCCMP1)   /*!< Timer C compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_RESET         (HRTIM_BMTRGR_TDRST)    /*!< Timer D reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_REPETITION    (HRTIM_BMTRGR_TDREP)    /*!< Timer D repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMD_CMP2          (HRTIM_BMTRGR_TDCMP2)   /*!< Timer D compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIME_REPETITION    (HRTIM_BMTRGR_TEREP)    /*!< Timer E repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIME_CMP1          (HRTIM_BMTRGR_TECMP1)   /*!< Timer E compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIME_CMP2          (HRTIM_BMTRGR_TECMP2)   /*!< Timer E compare 2 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMF_RESET         (HRTIM_BMTRGR_TFRST)    /*!< Timer F reset event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMF_REPETITION    (HRTIM_BMTRGR_TFREP)    /*!< Timer F repetition event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMF_CMP1          (HRTIM_BMTRGR_TFCMP1)   /*!< Timer F compare 1 event is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_TIMA_EVENT7        (HRTIM_BMTRGR_TAEEV7)   /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation  */
+#define LL_HRTIM_BM_TRIG_TIMD_EVENT8        (HRTIM_BMTRGR_TDEEV8)   /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation  */
+#define LL_HRTIM_BM_TRIG_EVENT_7            (HRTIM_BMTRGR_EEV7)     /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_EVENT_8            (HRTIM_BMTRGR_EEV8)     /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */
+#define LL_HRTIM_BM_TRIG_EVENT_ONCHIP       (HRTIM_BMTRGR_OCHPEV)   /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS
+  * @{
+  * @brief Constants defining the operating state of the burst mode controller.
+  */
+#define LL_HRTIM_BM_STATUS_NORMAL             0x00000000U           /*!< Normal operation */
+#define LL_HRTIM_BM_STATUS_BURST_ONGOING      HRTIM_BMCR_BMSTAT     /*!< Burst operation on-going */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_COUNTER_MODE Counter Mode
+  * @{
+  * @brief Constants defining the Counter Up Down Mode.
+  */
+#define LL_HRTIM_COUNTING_MODE_UP                    0x00000000U           /*!< counter is operating in up-counting mode */
+#define LL_HRTIM_COUNTING_MODE_UP_DOWN               HRTIM_TIMCR2_UDM      /*!< counter is operating in up-down counting mode  */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_COUNTER_Roll-Over counter Mode
+  * @{
+  * @brief Constants defining the Roll-Over counter Mode.
+  */
+#define LL_HRTIM_ROLLOVER_MODE_PER            2U                        /*!< Event generated when counter reaches period value  ('crest' mode) */
+#define LL_HRTIM_ROLLOVER_MODE_RST            1U                        /*!< Event generated when counter equals 0 ('valley' mode) */
+#define LL_HRTIM_ROLLOVER_MODE_BOTH           0U                        /*!< Event generated when counter reach both conditions (0 or HRTIM_PERxR value) */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Timer_TrigHalf_Mode HRTIM Timer Triggered-Half Mode
+  * @{
+  * @brief Constants defining how the timer counter operates.
+  */
+#define LL_HRTIM_TRIGHALF_DISABLED        0x00000000U            /*!< Timer Compare 2 register is behaving in standard mode */
+#define LL_HRTIM_TRIGHALF_ENABLED         HRTIM_TIMCR2_TRGHLF    /*!< Timer Compare 2 register is behaving in triggered-half mode  */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_COUNTER_Compare Greater than compare PWM Mode
+  * @{
+  * @brief Constants defining the greater than compare 1 or 3 PWM Mode.
+  */
+#define LL_HRTIM_GTCMP1_EQUAL             0x00000000U            /*!< event is generated when counter is equal to compare value */
+#define LL_HRTIM_GTCMP1_GREATER           HRTIM_TIMCR2_GTCMP1    /*!< event is generated when counter is greater than compare value */
+#define LL_HRTIM_GTCMP3_EQUAL             0x00000000U            /*!< event is generated when counter is equal to compare value */
+#define LL_HRTIM_GTCMP3_GREATER           HRTIM_TIMCR2_GTCMP3    /*!< event is generated when counter is greater than compare value */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_COUNTER_DCDE Enabling the Dual Channel DAC Triggering
+  * @{
+  * @brief Constants enabling the Dual Channel DAC Reset trigger mechanism.
+  */
+#define LL_HRTIM_DCDE_DISABLED      0x00000000U              /*!<  Dual Channel DAC trigger is generated on counter reset or roll-over event */
+#define LL_HRTIM_DCDE_ENABLED       HRTIM_TIMCR2_DCDE        /*!<  Dual Channel DAC trigger is generated on output 1 set  event */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_COUNTER_DCDR Dual Channel DAC Reset Trigger
+  * @{
+  * @brief Constants defining the Dual Channel DAC Reset trigger.
+  */
+#define LL_HRTIM_DCDR_COUNTER       0x00000000U              /*!< Dual Channel DAC trigger is generated on counter reset or roll-over event */
+#define LL_HRTIM_DCDR_OUT1SET       HRTIM_TIMCR2_DCDR        /*!< Dual Channel DAC trigger is generated on output 1 set  event */
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_COUNTER_DCDS Dual Channel DAC Step trigger
+  * @{
+  * @brief Constants defining the Dual Channel DAC Step trigger.
+  */
+#define LL_HRTIM_DCDS_CMP2          0x00000000U              /*!< trigger is generated on compare 2 event */
+#define LL_HRTIM_DCDS_OUT1RST       HRTIM_TIMCR2_DCDS        /*!< trigger is generated on output 1 reset event */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros
+  * @{
+  */
+
+/** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in HRTIM register
+  * @param  __INSTANCE__ HRTIM Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in HRTIM register
+  * @param  __INSTANCE__ HRTIM Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros
+  * @{
+  */
+/**
+  * @brief  HELPER macro returning the output state from output enable/disable status
+  * @param  __OUTPUT_STATUS_EN__ output enable status
+  * @param  __OUTPUT_STATUS_DIS__ output Disable status
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE
+  *         @arg @ref LL_HRTIM_OUTPUTSTATE_RUN
+  *         @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT
+  */
+#define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\
+  (((__OUTPUT_STATUS_EN__) == 1) ?  LL_HRTIM_OUTPUTSTATE_RUN :\
+   ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions
+  * @{
+  */
+/** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control
+  * @{
+  */
+
+/**
+  * @brief  Select the HRTIM synchronization input source.
+  * @note This function must not be called when  the concerned timer(s) is (are) enabled .
+  * @rmtoll MCR          SYNCIN        LL_HRTIM_SetSyncInSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  SyncInSrc This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
+  *         @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
+  *         @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)
+{
+  MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);
+}
+
+/**
+  * @brief  Get actual HRTIM synchronization input source.
+  * @rmtoll MCR          SYNCIN        LL_HRTIM_SetSyncInSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval SyncInSrc Returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_SYNCIN_SRC_NONE
+  *         @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT
+  *         @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(const HRTIM_TypeDef *HRTIMx)
+{
+  return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));
+}
+
+/**
+  * @brief  Configure the HRTIM synchronization output.
+  * @rmtoll MCR          SYNCSRC      LL_HRTIM_ConfigSyncOut\n
+  *         MCR          SYNCOUT      LL_HRTIM_ConfigSyncOut
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Config This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED
+  *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
+  *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
+  * @param  Src This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)
+{
+  MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));
+}
+
+/**
+  * @brief  Set the routing and conditioning of the synchronization output event.
+  * @rmtoll MCR          SYNCOUT      LL_HRTIM_SetSyncOutConfig
+  * @note This function can be called only when the master timer is enabled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  SyncOutConfig This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED
+  *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
+  *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)
+{
+  MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);
+}
+
+/**
+  * @brief  Get actual routing and conditioning of the synchronization output event.
+  * @rmtoll MCR          SYNCOUT      LL_HRTIM_GetSyncOutConfig
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval SyncOutConfig Returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED
+  *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE
+  *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(const HRTIM_TypeDef *HRTIMx)
+{
+  return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));
+}
+
+/**
+  * @brief  Set the source and event to be sent on the HRTIM synchronization output.
+  * @rmtoll MCR          SYNCSRC      LL_HRTIM_SetSyncOutSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  SyncOutSrc This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)
+{
+  MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);
+}
+
+/**
+  * @brief  Get actual  source and event sent on the HRTIM synchronization output.
+  * @rmtoll MCR          SYNCSRC      LL_HRTIM_GetSyncOutSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval SyncOutSrc Returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START
+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1
+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START
+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(const HRTIM_TypeDef *HRTIMx)
+{
+  return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));
+}
+
+/**
+  * @brief  Disable (temporarily) update event generation.
+  * @rmtoll CR1          MUDIS         LL_HRTIM_SuspendUpdate\n
+  *         CR1          TAUDIS        LL_HRTIM_SuspendUpdate\n
+  *         CR1          TBUDIS        LL_HRTIM_SuspendUpdate\n
+  *         CR1          TCUDIS        LL_HRTIM_SuspendUpdate\n
+  *         CR1          TDUDIS        LL_HRTIM_SuspendUpdate\n
+  *         CR1          TEUDIS        LL_HRTIM_SuspendUpdate\n
+  *         CR1          TFUDIS        LL_HRTIM_SuspendUpdate
+  * @note Allow to temporarily disable the transfer from preload to active
+  *      registers, whatever the selected update event. This allows to modify
+  *      several registers in multiple timers.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timers This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+  /* clear register before applying the new value */
+  CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((LL_HRTIM_TIMER_ALL >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
+  SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
+}
+
+/**
+  * @brief  Enable update event generation.
+  * @rmtoll CR1          MUDIS         LL_HRTIM_ResumeUpdate\n
+  *         CR1          TAUDIS        LL_HRTIM_ResumeUpdate\n
+  *         CR1          TBUDIS        LL_HRTIM_ResumeUpdate\n
+  *         CR1          TCUDIS        LL_HRTIM_ResumeUpdate\n
+  *         CR1          TDUDIS        LL_HRTIM_ResumeUpdate\n
+  *         CR1          TEUDIS        LL_HRTIM_ResumeUpdate\n
+  *         CR1          TFUDIS        LL_HRTIM_ResumeUpdate
+  * @note The regular update event takes place.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timers This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));
+}
+
+/**
+  * @brief  Force an immediate transfer from the preload to the active register .
+  * @rmtoll CR2          MSWU          LL_HRTIM_ForceUpdate\n
+  *         CR2          TASWU         LL_HRTIM_ForceUpdate\n
+  *         CR2          TBSWU         LL_HRTIM_ForceUpdate\n
+  *         CR2          TCSWU         LL_HRTIM_ForceUpdate\n
+  *         CR2          TDSWU         LL_HRTIM_ForceUpdate\n
+  *         CR2          TESWU         LL_HRTIM_ForceUpdate\n
+  *         CR2          TFSWU         LL_HRTIM_ForceUpdate
+  * @note Any pending update request is cancelled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timers This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+  SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));
+}
+
+/**
+  * @brief  Reset the HRTIM timer(s) counter.
+  * @rmtoll CR2          MRST          LL_HRTIM_CounterReset\n
+  *         CR2          TARST         LL_HRTIM_CounterReset\n
+  *         CR2          TBRST         LL_HRTIM_CounterReset\n
+  *         CR2          TCRST         LL_HRTIM_CounterReset\n
+  *         CR2          TDRST         LL_HRTIM_CounterReset\n
+  *         CR2          TERST         LL_HRTIM_CounterReset\n
+  *         CR2          TFRST         LL_HRTIM_CounterReset
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timers This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+  SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));
+}
+
+/**
+  * @brief  enable the swap of the Timer Output.
+  * @note   the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
+  *         and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
+  * @note   This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
+  * @rmtoll CR2          SWPA         LL_HRTIM_EnableSwapOutputs\n
+  *         CR2          SWPB         LL_HRTIM_EnableSwapOutputs\n
+  *         CR2          SWPC         LL_HRTIM_EnableSwapOutputs\n
+  *         CR2          SWPD         LL_HRTIM_EnableSwapOutputs\n
+  *         CR2          SWPE         LL_HRTIM_EnableSwapOutputs\n
+  *         CR2          SWPF         LL_HRTIM_EnableSwapOutputs
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+
+  SET_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer);
+}
+
+/**
+  * @brief  disable the swap of the Timer Output.
+  * @note   the HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
+  *         and the HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
+  * @note   This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
+  * @rmtoll CR2          SWPA         LL_HRTIM_DisableSwapOutputs\n
+  *         CR2          SWPB         LL_HRTIM_DisableSwapOutputs\n
+  *         CR2          SWPC         LL_HRTIM_DisableSwapOutputs\n
+  *         CR2          SWPD         LL_HRTIM_DisableSwapOutputs\n
+  *         CR2          SWPE         LL_HRTIM_DisableSwapOutputs\n
+  *         CR2          SWPF         LL_HRTIM_DisableSwapOutputs
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableSwapOutputs(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+
+  CLEAR_BIT(HRTIMx->sCommonRegs.CR2, (HRTIM_CR2_SWPA << iTimer));
+}
+
+/**
+  * @brief  reports the Timer Outputs swap position.
+  * @note   This bit is not significant when the Push-pull mode is enabled (PSHPLL = 1)
+  * @rmtoll CR2          SWPA         LL_HRTIM_IsEnabledSwapOutputs\n
+  *         CR2          SWPB         LL_HRTIM_IsEnabledSwapOutputs\n
+  *         CR2          SWPC         LL_HRTIM_IsEnabledSwapOutputs\n
+  *         CR2          SWPD         LL_HRTIM_IsEnabledSwapOutputs\n
+  *         CR2          SWPE         LL_HRTIM_IsEnabledSwapOutputs\n
+  *         CR2          SWPF         LL_HRTIM_IsEnabledSwapOutputs
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval
+  *         1: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A2,
+  *            HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A1
+  *         0: HRTIM_SETA1R and HRTIM_RSTA1R are coding for the output A1,
+  *            HRTIM_SETA2R and HRTIM_RSTA2R are coding for the output A2
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledSwapOutputs(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos) & 0x1FU);
+
+  return (READ_BIT(HRTIMx->sCommonRegs.CR2, (uint32_t)(HRTIM_CR2_SWPA) << iTimer) >> ((HRTIM_CR2_SWPA_Pos + iTimer)));
+}
+
+/**
+  * @brief  Enable the HRTIM timer(s) output(s) .
+  * @rmtoll OENR         TA1OEN        LL_HRTIM_EnableOutput\n
+  *         OENR         TA2OEN        LL_HRTIM_EnableOutput\n
+  *         OENR         TB1OEN        LL_HRTIM_EnableOutput\n
+  *         OENR         TB2OEN        LL_HRTIM_EnableOutput\n
+  *         OENR         TC1OEN        LL_HRTIM_EnableOutput\n
+  *         OENR         TC2OEN        LL_HRTIM_EnableOutput\n
+  *         OENR         TD1OEN        LL_HRTIM_EnableOutput\n
+  *         OENR         TD2OEN        LL_HRTIM_EnableOutput\n
+  *         OENR         TE1OEN        LL_HRTIM_EnableOutput\n
+  *         OENR         TE2OEN        LL_HRTIM_EnableOutput\n
+  *         OENR         TF1OEN        LL_HRTIM_EnableOutput\n
+  *         OENR         TF2OEN        LL_HRTIM_EnableOutput
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Outputs This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
+{
+  SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));
+}
+
+/**
+  * @brief  Disable the HRTIM timer(s) output(s) .
+  * @rmtoll OENR         TA1OEN        LL_HRTIM_DisableOutput\n
+  *         OENR         TA2OEN        LL_HRTIM_DisableOutput\n
+  *         OENR         TB1OEN        LL_HRTIM_DisableOutput\n
+  *         OENR         TB2OEN        LL_HRTIM_DisableOutput\n
+  *         OENR         TC1OEN        LL_HRTIM_DisableOutput\n
+  *         OENR         TC2OEN        LL_HRTIM_DisableOutput\n
+  *         OENR         TD1OEN        LL_HRTIM_DisableOutput\n
+  *         OENR         TD2OEN        LL_HRTIM_DisableOutput\n
+  *         OENR         TE1OEN        LL_HRTIM_DisableOutput\n
+  *         OENR         TE2OEN        LL_HRTIM_DisableOutput\n
+  *         OENR         TF1OEN        LL_HRTIM_DisableOutput\n
+  *         OENR         TF2OEN        LL_HRTIM_DisableOutput
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Outputs This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)
+{
+  SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));
+}
+
+/**
+  * @brief  Indicates whether the HRTIM timer output is enabled.
+  * @rmtoll OENR         TA1OEN        LL_HRTIM_IsEnabledOutput\n
+  *         OENR         TA2OEN        LL_HRTIM_IsEnabledOutput\n
+  *         OENR         TB1OEN        LL_HRTIM_IsEnabledOutput\n
+  *         OENR         TB2OEN        LL_HRTIM_IsEnabledOutput\n
+  *         OENR         TC1OEN        LL_HRTIM_IsEnabledOutput\n
+  *         OENR         TC2OEN        LL_HRTIM_IsEnabledOutput\n
+  *         OENR         TD1OEN        LL_HRTIM_IsEnabledOutput\n
+  *         OENR         TD2OEN        LL_HRTIM_IsEnabledOutput\n
+  *         OENR         TE1OEN        LL_HRTIM_IsEnabledOutput\n
+  *         OENR         TE2OEN        LL_HRTIM_IsEnabledOutput\n
+  *         OENR         TF1OEN        LL_HRTIM_IsEnabledOutput\n
+  *         OENR         TF2OEN        LL_HRTIM_IsEnabledOutput
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Indicates whether the HRTIM timer output is disabled.
+  * @rmtoll ODISR        TA1ODIS        LL_HRTIM_IsDisabledOutput\n
+  *         ODISR        TA2ODIS        LL_HRTIM_IsDisabledOutput\n
+  *         ODISR        TB1ODIS        LL_HRTIM_IsDisabledOutput\n
+  *         ODISR        TB2ODIS        LL_HRTIM_IsDisabledOutput\n
+  *         ODISR        TC1ODIS        LL_HRTIM_IsDisabledOutput\n
+  *         ODISR        TC2ODIS        LL_HRTIM_IsDisabledOutput\n
+  *         ODISR        TD1ODIS        LL_HRTIM_IsDisabledOutput\n
+  *         ODISR        TD2ODIS        LL_HRTIM_IsDisabledOutput\n
+  *         ODISR        TE1ODIS        LL_HRTIM_IsDisabledOutput\n
+  *         ODISR        TE2ODIS        LL_HRTIM_IsDisabledOutput\n
+  *         ODISR        TF1ODIS        LL_HRTIM_IsDisabledOutput\n
+  *         ODISR        TF2ODIS        LL_HRTIM_IsDisabledOutput
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure an ADC trigger.
+  * @rmtoll CR1          ADC1USRC        LL_HRTIM_ConfigADCTrig\n
+  *         CR1          ADC2USRC        LL_HRTIM_ConfigADCTrig\n
+  *         CR1          ADC3USRC        LL_HRTIM_ConfigADCTrig\n
+  *         CR1          ADC4USRC        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1MC1         LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1MC2         LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1MC3         LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1MC4         LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1MPER        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1EEV1        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1EEV2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1EEV3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1EEV4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1EEV5        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TFC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TAC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TAC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TAPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TARST       LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TFC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TBC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TBC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TBPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TBRST       LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TFC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TCC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TCC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TCPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TFPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TDC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TDC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TDPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TFRST       LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TEC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TEC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC1R        ADC1TEPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2MC1         LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2MC2         LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2MC3         LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2MC4         LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2MPER        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2EEV6        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2EEV7        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2EEV8        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2EEV9        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2EEV10       LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TAC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TFC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TAC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TAPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TBC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TFC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TBC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TBPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TCC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TFC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TCC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TCPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TCRST       LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TDC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TFPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TDC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TDPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TDRST       LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TEC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TEC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TEC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC2R        ADC2TERST       LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3MC1         LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3MC2         LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3MC3         LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3MC4         LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3MPER        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3EEV1        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3EEV2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3EEV3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3EEV4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3EEV5        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TFC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TAC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TAC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TAPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TARST       LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TFC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TBC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TBC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TBPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TBRST       LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TFC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TCC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TCC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TCPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TFPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TDC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TDC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TDPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TFRST       LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TEC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TEC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC3R        ADC3TEPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4MC1         LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4MC2         LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4MC3         LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4MC4         LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4MPER        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4EEV6        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4EEV7        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4EEV8        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4EEV9        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4EEV10       LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TAC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TFC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TAC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TAPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TBC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TFC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TBC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TBPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TCC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TFC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TCC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TCPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TCRST       LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TDC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TFPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TDC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TDPER       LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TDRST       LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TEC2        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TEC3        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TEC4        LL_HRTIM_ConfigADCTrig\n
+  *         ADC4R        ADC4TERST       LL_HRTIM_ConfigADCTrig
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  ADCTrig This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_1
+  *         @arg @ref LL_HRTIM_ADCTRIG_2
+  *         @arg @ref LL_HRTIM_ADCTRIG_3
+  *         @arg @ref LL_HRTIM_ADCTRIG_4
+  * @param  Update This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
+  * @param  Src This parameter can be a combination of the following values:
+  *
+  *         For ADC trigger 1 and ADC trigger 3:
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
+  *
+  *         For ADC trigger 2 and ADC trigger 4:
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
+  *
+  *         For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
+  *         can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
+  *
+  *         For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
+  *         can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)
+{
+  __IO uint32_t *padcur = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
+                                                       REG_OFFSET_TAB_ADCUR[ADCTrig]));
+  __IO uint32_t *padcer = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
+                                                       REG_OFFSET_TAB_ADCER[ADCTrig]));
+  MODIFY_REG(*padcur, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
+  MODIFY_REG(*padcer, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
+}
+
+/**
+  * @brief  Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.
+  * @rmtoll CR1          ADC1USRC         LL_HRTIM_SetADCTrigUpdate\n
+  *         CR1          ADC2USRC         LL_HRTIM_SetADCTrigUpdate\n
+  *         CR1          ADC3USRC         LL_HRTIM_SetADCTrigUpdate\n
+  *         CR1          ADC4USRC         LL_HRTIM_SetADCTrigUpdate\n
+  *         ADCUR        ADC5USRC         LL_HRTIM_SetADCTrigUpdate\n
+  *         ADCUR        ADC6USRC         LL_HRTIM_SetADCTrigUpdate\n
+  *         ADCUR        ADC7USRC         LL_HRTIM_SetADCTrigUpdate\n
+  *         ADCUR        ADC8USRC         LL_HRTIM_SetADCTrigUpdate\n
+  *         ADCUR        ADC9USRC         LL_HRTIM_SetADCTrigUpdate\n
+  *         ADCUR        ADC10USRC        LL_HRTIM_SetADCTrigUpdate
+  * @note When the preload is disabled in the source timer, the HRTIM_ADCxR
+  *       registers are not preloaded either: a write access will result in an
+  *       immediate update of the trigger source.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  ADCTrig This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_1
+  *         @arg @ref LL_HRTIM_ADCTRIG_2
+  *         @arg @ref LL_HRTIM_ADCTRIG_3
+  *         @arg @ref LL_HRTIM_ADCTRIG_4
+  *         @arg @ref LL_HRTIM_ADCTRIG_5
+  *         @arg @ref LL_HRTIM_ADCTRIG_6
+  *         @arg @ref LL_HRTIM_ADCTRIG_7
+  *         @arg @ref LL_HRTIM_ADCTRIG_8
+  *         @arg @ref LL_HRTIM_ADCTRIG_9
+  *         @arg @ref LL_HRTIM_ADCTRIG_10
+  * @param  Update This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)
+{
+  __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
+                                                     REG_OFFSET_TAB_ADCUR[ADCTrig]));
+  MODIFY_REG(*preg, REG_MASK_TAB_ADCUR[ADCTrig], (Update << REG_SHIFT_TAB_ADCUR[ADCTrig]));
+}
+
+/**
+  * @brief  Get the source timer triggering the update of the HRTIM_ADCxR register.
+  * @rmtoll CR1          ADC1USRC        LL_HRTIM_GetADCTrigUpdate\n
+  *         CR1          ADC2USRC        LL_HRTIM_GetADCTrigUpdate\n
+  *         CR1          ADC3USRC        LL_HRTIM_GetADCTrigUpdate\n
+  *         CR1          ADC4USRC        LL_HRTIM_GetADCTrigUpdate\n
+  *         ADCUR        ADC5USRC        LL_HRTIM_GetADCTrigUpdate\n
+  *         ADCUR        ADC6USRC        LL_HRTIM_GetADCTrigUpdate\n
+  *         ADCUR        ADC7USRC        LL_HRTIM_GetADCTrigUpdate\n
+  *         ADCUR        ADC8USRC        LL_HRTIM_GetADCTrigUpdate\n
+  *         ADCUR        ADC9USRC        LL_HRTIM_GetADCTrigUpdate\n
+  *         ADCUR        ADC10USRC       LL_HRTIM_GetADCTrigUpdate
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  ADCTrig This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_1
+  *         @arg @ref LL_HRTIM_ADCTRIG_2
+  *         @arg @ref LL_HRTIM_ADCTRIG_3
+  *         @arg @ref LL_HRTIM_ADCTRIG_4
+  *         @arg @ref LL_HRTIM_ADCTRIG_5
+  *         @arg @ref LL_HRTIM_ADCTRIG_6
+  *         @arg @ref LL_HRTIM_ADCTRIG_7
+  *         @arg @ref LL_HRTIM_ADCTRIG_8
+  *         @arg @ref LL_HRTIM_ADCTRIG_9
+  *         @arg @ref LL_HRTIM_ADCTRIG_10
+  * @retval Update Returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E
+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_F
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
+{
+  const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.CR1) +
+                                                           REG_OFFSET_TAB_ADCUR[ADCTrig]));
+  return (READ_BIT(*preg, (REG_MASK_TAB_ADCUR[ADCTrig])) >> REG_SHIFT_TAB_ADCUR[ADCTrig]);
+}
+
+/**
+  * @brief  Specify which events (timer events and/or external events) are used as triggers for ADC conversion.
+  * @rmtoll ADC1R        ADC1MC1         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1MC2         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1MC3         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1MC4         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1MPER        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1EEV1        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1EEV2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1EEV3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1EEV4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1EEV5        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TFC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TAC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TAC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TAPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TARST       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TFC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TBC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TBC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TBPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TBRST       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TFC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TCC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TCC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TCPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TFPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TDC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TDC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TDPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TFRST       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TEC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TEC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC1R        ADC1TEPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2MC1         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2MC2         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2MC3         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2MC4         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2MPER        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2EEV6        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2EEV7        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2EEV8        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2EEV9        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2EEV10       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TAC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TFC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TAC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TAPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TBC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TFC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TBC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TBPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TCC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TFC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TCC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TCPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TCRST       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TDC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TFPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TDC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TDPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TDRST       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TEC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TEC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TEC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC2R        ADC2TERST       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3MC1         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3MC2         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3MC3         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3MC4         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3MPER        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3EEV1        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3EEV2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3EEV3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3EEV4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3EEV5        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TFC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TAC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TAC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TAPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TARST       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TFC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TBC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TBC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TBPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TBRST       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TFC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TCC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TCC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TCPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TFPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TDC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TDC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TDPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TFRST       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TEC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TEC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC3R        ADC3TEPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4MC1         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4MC2         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4MC3         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4MC4         LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4MPER        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4EEV6        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4EEV7        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4EEV8        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4EEV9        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4EEV10       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TAC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TFC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TAC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TAPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TBC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TFC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TBC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TBPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TCC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TFC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TCC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TCPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TCRST       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TDC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TFPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TDC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TDPER       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TDRST       LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TEC2        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TEC3        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TEC4        LL_HRTIM_SetADCTrigSrc\n
+  *         ADC4R        ADC4TERST       LL_HRTIM_SetADCTrigSrc\n
+  *         ADCER        ADC5TRG         LL_HRTIM_SetADCTrigSrc\n
+  *         ADCER        ADC6TRG         LL_HRTIM_SetADCTrigSrc\n
+  *         ADCER        ADC7TRG         LL_HRTIM_SetADCTrigSrc\n
+  *         ADCER        ADC8TRG         LL_HRTIM_SetADCTrigSrc\n
+  *         ADCER        ADC9TRG         LL_HRTIM_SetADCTrigSrc\n
+  *         ADCER        ADC10TRG        LL_HRTIM_SetADCTrigSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  ADCTrig This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_1
+  *         @arg @ref LL_HRTIM_ADCTRIG_2
+  *         @arg @ref LL_HRTIM_ADCTRIG_3
+  *         @arg @ref LL_HRTIM_ADCTRIG_4
+  *         @arg @ref LL_HRTIM_ADCTRIG_5
+  *         @arg @ref LL_HRTIM_ADCTRIG_6
+  *         @arg @ref LL_HRTIM_ADCTRIG_7
+  *         @arg @ref LL_HRTIM_ADCTRIG_8
+  *         @arg @ref LL_HRTIM_ADCTRIG_9
+  *         @arg @ref LL_HRTIM_ADCTRIG_10
+  * @param  Src
+  *         For ADC trigger 1 and ADC trigger 3 this parameter can be a
+  *         combination of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
+  *
+  *         For ADC trigger 2 and ADC trigger 4 this parameter can be a
+  *         combination of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
+  *
+  *         For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
+  *         can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
+  *
+  *         For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
+  *         can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)
+{
+  __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
+                                                     REG_OFFSET_TAB_ADCER[ADCTrig]));
+  MODIFY_REG(*preg, REG_MASK_TAB_ADCER[ADCTrig], (Src << REG_SHIFT_TAB_ADCER[ADCTrig]));
+}
+
+/**
+  * @brief  Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.
+  * @rmtoll ADC1R        ADC1MC1         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1MC2         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1MC3         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1MC4         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1MPER        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1EEV1        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1EEV2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1EEV3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1EEV4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1EEV5        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TFC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TAC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TAC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TAPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TARST       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TFC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TBC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TBC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TBPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TBRST       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TFC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TCC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TCC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TCPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TFPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TDC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TDC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TDPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TFRST       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TEC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TEC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC1R        ADC1TEPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2MC1         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2MC2         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2MC3         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2MC4         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2MPER        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2EEV6        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2EEV7        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2EEV8        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2EEV9        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2EEV10       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TAC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TFC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TAC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TAPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TBC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TFC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TBC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TBPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TCC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TFC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TCC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TCPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TCRST       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TDC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TFPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TDC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TDPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TDRST       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TEC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TEC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TEC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC2R        ADC2TERST       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3MC1         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3MC2         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3MC3         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3MC4         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3MPER        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3EEV1        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3EEV2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3EEV3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3EEV4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3EEV5        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TFC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TAC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TAC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TAPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TARST       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TFC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TBC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TBC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TBPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TBRST       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TFC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TCC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TCC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TCPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TFPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TDC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TDC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TDPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TFRST       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TEC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TEC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC3R        ADC3TEPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4MC1         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4MC2         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4MC3         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4MC4         LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4MPER        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4EEV6        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4EEV7        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4EEV8        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4EEV9        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4EEV10       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TAC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TFC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TAC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TAPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TBC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TFC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TBC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TBPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TCC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TFC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TCC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TCPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TCRST       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TDC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TFPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TDC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TDPER       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TDRST       LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TEC2        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TEC3        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TEC4        LL_HRTIM_GetADCTrigSrc\n
+  *         ADC4R        ADC4TERST       LL_HRTIM_GetADCTrigSrc
+  *         ADCER        ADC5TRG         LL_HRTIM_SetADCTrigSrc\n
+  *         ADCER        ADC6TRG         LL_HRTIM_SetADCTrigSrc\n
+  *         ADCER        ADC7TRG         LL_HRTIM_SetADCTrigSrc\n
+  *         ADCER        ADC8TRG         LL_HRTIM_SetADCTrigSrc\n
+  *         ADCER        ADC9TRG         LL_HRTIM_SetADCTrigSrc\n
+  *         ADCER        ADC10TRG        LL_HRTIM_SetADCTrigSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  ADCTrig This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_1
+  *         @arg @ref LL_HRTIM_ADCTRIG_2
+  *         @arg @ref LL_HRTIM_ADCTRIG_3
+  *         @arg @ref LL_HRTIM_ADCTRIG_4
+  *         @arg @ref LL_HRTIM_ADCTRIG_5
+  *         @arg @ref LL_HRTIM_ADCTRIG_6
+  *         @arg @ref LL_HRTIM_ADCTRIG_7
+  *         @arg @ref LL_HRTIM_ADCTRIG_8
+  *         @arg @ref LL_HRTIM_ADCTRIG_9
+  *         @arg @ref LL_HRTIM_ADCTRIG_10
+  * @retval Src This parameter can be a combination of the following values:
+  *
+  *         For ADC trigger 1 and ADC trigger 3 this parameter can be a
+  *         combination of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMFRST
+  *
+  *         For ADC trigger 2 and ADC trigger 4 this parameter can be a
+  *         combination of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMFPER
+  *
+  *         For ADC trigger 5, ADC trigger 7 and ADC trigger 9 this parameter
+  *         can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_MPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_EEV5
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMA_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMB_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMC_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMD_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIME_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC579_TIMF_RST
+  *
+  *         For ADC trigger 6, ADC trigger 8 and ADC trigger 10 this parameter
+  *         can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP1
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MCMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_MPER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV6
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV7
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV8
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV9
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_EEV10
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMA_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMB_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMC_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_PER
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMD_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIME_RST
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP2
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP3
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_CMP4
+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC6810_TIMF_PER
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
+{
+  const __IO uint32_t *preg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +
+                                                           REG_OFFSET_TAB_ADCER[ADCTrig]));
+  return (READ_BIT(*preg, (REG_MASK_TAB_ADCER[ADCTrig])) >> REG_SHIFT_TAB_ADCER[ADCTrig]);
+
+}
+
+
+/**
+  * @brief  Select the ADC post scaler.
+  * @note This function allows to adjust each ADC trigger rate individually.
+  * @note In center-aligned mode, the ADC trigger rate is also dependent on
+  *       ADROM[1:0] bitfield, programmed in the source timer
+  *       (see function @ref LL_HRTIM_TIM_SetADCRollOverMode)
+  * @rmtoll ADCPS2       ADC10PSC        LL_HRTIM_SetADCPostScaler\n
+  *         ADCPS2       ADC9PSC         LL_HRTIM_SetADCPostScaler\n
+  *         ADCPS2       ADC8PSC         LL_HRTIM_SetADCPostScaler\n
+  *         ADCPS2       ADC7PSC         LL_HRTIM_SetADCPostScaler\n
+  *         ADCPS2       ADC6PSC         LL_HRTIM_SetADCPostScaler\n
+  *         ADCPS1       ADC5PSC         LL_HRTIM_SetADCPostScaler\n
+  *         ADCPS1       ADC4PSC         LL_HRTIM_SetADCPostScaler\n
+  *         ADCPS1       ADC3PSC         LL_HRTIM_SetADCPostScaler\n
+  *         ADCPS1       ADC2PSC         LL_HRTIM_SetADCPostScaler\n
+  *         ADCPS1       ADC1PSC         LL_HRTIM_SetADCPostScaler
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  ADCTrig This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_1
+  *         @arg @ref LL_HRTIM_ADCTRIG_2
+  *         @arg @ref LL_HRTIM_ADCTRIG_3
+  *         @arg @ref LL_HRTIM_ADCTRIG_4
+  *         @arg @ref LL_HRTIM_ADCTRIG_5
+  *         @arg @ref LL_HRTIM_ADCTRIG_6
+  *         @arg @ref LL_HRTIM_ADCTRIG_7
+  *         @arg @ref LL_HRTIM_ADCTRIG_8
+  *         @arg @ref LL_HRTIM_ADCTRIG_9
+  *         @arg @ref LL_HRTIM_ADCTRIG_10
+  * @param  PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_SetADCPostScaler(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t PostScaler)
+{
+
+  uint64_t mask = (uint64_t)(HRTIM_ADCPS1_AD1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
+  uint64_t ratio = (uint64_t)(PostScaler) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
+
+  MODIFY_REG(HRTIMx->sCommonRegs.ADCPS1, (uint32_t)mask, (uint32_t)ratio);
+  MODIFY_REG(HRTIMx->sCommonRegs.ADCPS2, (uint32_t)(mask >> 32U), (uint32_t)(ratio >> 32U));
+
+}
+
+/**
+  * @brief  Get the selected ADC post scaler.
+  * @rmtoll ADCPS2       ADC10PSC        LL_HRTIM_GetADCPostScaler\n
+  *         ADCPS2       ADC9PSC         LL_HRTIM_GetADCPostScaler\n
+  *         ADCPS2       ADC8PSC         LL_HRTIM_GetADCPostScaler\n
+  *         ADCPS2       ADC7PSC         LL_HRTIM_GetADCPostScaler\n
+  *         ADCPS2       ADC6PSC         LL_HRTIM_GetADCPostScaler\n
+  *         ADCPS1       ADC5PSC         LL_HRTIM_GetADCPostScaler\n
+  *         ADCPS1       ADC4PSC         LL_HRTIM_GetADCPostScaler\n
+  *         ADCPS1       ADC3PSC         LL_HRTIM_GetADCPostScaler\n
+  *         ADCPS1       ADC2PSC         LL_HRTIM_GetADCPostScaler\n
+  *         ADCPS1       ADC1PSC         LL_HRTIM_GetADCPostScaler
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  ADCTrig This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ADCTRIG_1
+  *         @arg @ref LL_HRTIM_ADCTRIG_2
+  *         @arg @ref LL_HRTIM_ADCTRIG_3
+  *         @arg @ref LL_HRTIM_ADCTRIG_4
+  *         @arg @ref LL_HRTIM_ADCTRIG_5
+  *         @arg @ref LL_HRTIM_ADCTRIG_6
+  *         @arg @ref LL_HRTIM_ADCTRIG_7
+  *         @arg @ref LL_HRTIM_ADCTRIG_8
+  *         @arg @ref LL_HRTIM_ADCTRIG_9
+  *         @arg @ref LL_HRTIM_ADCTRIG_10
+  * @retval  PostScaler This parameter can be a number between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_GetADCPostScaler(const HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)
+{
+
+  uint32_t reg1 = READ_REG(HRTIMx->sCommonRegs.ADCPS1);
+  uint32_t reg2 = READ_REG(HRTIMx->sCommonRegs.ADCPS2);
+
+  uint64_t mask = (uint64_t)(HRTIM_ADCPS1_AD1PSC) << (REG_OFFSET_TAB_ADCPSx[ADCTrig]);
+  uint64_t ratio = (uint64_t)(reg1) | ((uint64_t)(reg2) << 32U);
+
+  return (uint32_t)((ratio & mask) >> (REG_OFFSET_TAB_ADCPSx[ADCTrig])) ;
+
+}
+
+/**
+  * @brief  Configure the DLL calibration mode.
+  * @rmtoll DLLCR        CALEN         LL_HRTIM_ConfigDLLCalibration\n
+  *         DLLCR        CALRTE        LL_HRTIM_ConfigDLLCalibration
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_SINGLESHOT
+  *         @arg @ref LL_HRTIM_DLLCALIBRATION_MODE_CONTINUOUS
+  * @param  Period This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_0
+  *         @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_1
+  *         @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_2
+  *         @arg @ref LL_HRTIM_DLLCALIBRATION_RATE_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ConfigDLLCalibration(HRTIM_TypeDef *HRTIMx, uint32_t Mode, uint32_t Period)
+{
+  MODIFY_REG(HRTIMx->sCommonRegs.DLLCR, (HRTIM_DLLCR_CALEN | HRTIM_DLLCR_CALRTE), (Mode | Period));
+}
+
+/**
+  * @brief  Launch DLL calibration
+  * @rmtoll DLLCR        CAL           LL_HRTIM_StartDLLCalibration
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_StartDLLCalibration(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control
+  * @{
+  */
+
+/**
+  * @brief  Enable timer(s) counter.
+  * @rmtoll MDIER        TFCEN         LL_HRTIM_TIM_CounterEnable\n
+  *         MDIER        TECEN         LL_HRTIM_TIM_CounterEnable\n
+  *         MDIER        TDCEN         LL_HRTIM_TIM_CounterEnable\n
+  *         MDIER        TCCEN         LL_HRTIM_TIM_CounterEnable\n
+  *         MDIER        TBCEN         LL_HRTIM_TIM_CounterEnable\n
+  *         MDIER        TACEN         LL_HRTIM_TIM_CounterEnable\n
+  *         MDIER        MCEN          LL_HRTIM_TIM_CounterEnable
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timers This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+  SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);
+}
+
+/**
+  * @brief  Disable timer(s) counter.
+  * @rmtoll MDIER        TFCEN         LL_HRTIM_TIM_CounterDisable\n
+  *         MDIER        TECEN         LL_HRTIM_TIM_CounterDisable\n
+  *         MDIER        TDCEN         LL_HRTIM_TIM_CounterDisable\n
+  *         MDIER        TCCEN         LL_HRTIM_TIM_CounterDisable\n
+  *         MDIER        TBCEN         LL_HRTIM_TIM_CounterDisable\n
+  *         MDIER        TACEN         LL_HRTIM_TIM_CounterDisable\n
+  *         MDIER        MCEN          LL_HRTIM_TIM_CounterDisable
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timers This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)
+{
+  CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);
+}
+
+/**
+  * @brief  Indicate whether the timer counter is enabled.
+  * @rmtoll MDIER        TFCEN         LL_HRTIM_TIM_IsCounterEnabled\n
+  *         MDIER        TECEN         LL_HRTIM_TIM_IsCounterEnabled\n
+  *         MDIER        TDCEN         LL_HRTIM_TIM_IsCounterEnabled\n
+  *         MDIER        TCCEN         LL_HRTIM_TIM_IsCounterEnabled\n
+  *         MDIER        TBCEN         LL_HRTIM_TIM_IsCounterEnabled\n
+  *         MDIER        TACEN         LL_HRTIM_TIM_IsCounterEnabled\n
+  *         MDIER        MCEN          LL_HRTIM_TIM_IsCounterEnabled
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the timer clock prescaler ratio.
+  * @rmtoll MCR        CKPSC         LL_HRTIM_TIM_SetPrescaler\n
+  *         TIMxCR     CKPSC         LL_HRTIM_TIM_SetPrescaler
+  * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].
+  * @note The prescaling ratio cannot be modified once the timer counter is enabled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);
+}
+
+/**
+  * @brief  Get the timer clock prescaler ratio
+  * @rmtoll MCR        CKPSC         LL_HRTIM_TIM_GetPrescaler\n
+  *         TIMxCR     CKPSC         LL_HRTIM_TIM_GetPrescaler
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Prescaler Returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL32
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL16
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL8
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL4
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_MUL2
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2
+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));
+}
+
+/**
+  * @brief  Set the counter operating mode mode (single-shot, continuous or re-triggerable).
+  * @rmtoll MCR        CONT         LL_HRTIM_TIM_SetCounterMode\n
+  *         MCR        RETRIG       LL_HRTIM_TIM_SetCounterMode\n
+  *         TIMxCR     CONT         LL_HRTIM_TIM_SetCounterMode\n
+  *         TIMxCR     RETRIG       LL_HRTIM_TIM_SetCounterMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_MODE_CONTINUOUS
+  *         @arg @ref LL_HRTIM_MODE_SINGLESHOT
+  *         @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);
+}
+
+/**
+  * @brief  Get the counter operating mode mode
+  * @rmtoll MCR        CONT         LL_HRTIM_TIM_GetCounterMode\n
+  *         MCR        RETRIG       LL_HRTIM_TIM_GetCounterMode\n
+  *         TIMxCR     CONT         LL_HRTIM_TIM_GetCounterMode\n
+  *         TIMxCR     RETRIG       LL_HRTIM_TIM_GetCounterMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Mode Returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_MODE_CONTINUOUS
+  *         @arg @ref LL_HRTIM_MODE_SINGLESHOT
+  *         @arg @ref LL_HRTIM_MODE_RETRIGGERABLE
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));
+}
+
+/**
+  * @brief  Enable the half duty-cycle mode.
+  * @rmtoll MCR        HALF         LL_HRTIM_TIM_EnableHalfMode\n
+  *         TIMxCR     HALF         LL_HRTIM_TIM_EnableHalfMode
+  * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)
+  *       active register is automatically updated with HRTIM_MPER/2
+  *       (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MCR_HALF);
+}
+
+/**
+  * @brief  Disable the half duty-cycle mode.
+  * @rmtoll MCR        HALF         LL_HRTIM_TIM_DisableHalfMode\n
+  *         TIMxCR     HALF         LL_HRTIM_TIM_DisableHalfMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MCR_HALF);
+  CLEAR_BIT(*pReg, HRTIM_MCR_INTLVD << REG_SHIFT_TAB_INTLVD[iTimer]);
+}
+
+/**
+  * @brief  Indicate whether half duty-cycle mode is enabled for a given timer.
+  * @rmtoll MCR        HALF         LL_HRTIM_TIM_IsEnabledHalfMode\n
+  *         TIMxCR     HALF         LL_HRTIM_TIM_IsEnabledHalfMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the Re-Syncronisation Update.
+  * @note   The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
+  *         or from a software update (TxSWU bit) is taken into account on the following reset/roll-over.
+  * @note   LL_HRTIM_ForceUpdate must be called prior programming the syncrhonization mode to force
+  *         immediate update of the slave timer registers.
+  * @rmtoll TIMxCR     RSYNCU         LL_HRTIM_TIM_EnableResyncUpdate
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMCR_RSYNCU);
+  /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
+}
+
+/**
+  * @brief  Disable the Re-Syncronisation Update.
+  * @note   The update coming from adjacent timers (when MSTU, TAU, TBU, TCU, TDU, TEU, TFU bit is set)
+  *         or from a software update (TxSWU bit) is taken into account immediately.
+  * @rmtoll TIMxCR     RSYNCU         LL_HRTIM_TIM_DisableResyncUpdate
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableResyncUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+
+  CLEAR_BIT(*pReg, HRTIM_TIMCR_RSYNCU);
+  /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
+}
+
+/**
+  * @brief  Indicate whether the Re-Syncronisation Update is enabled.
+  * @note   This bit specifies whether update source coming outside
+  *         from the timing unit must be synchronized
+  * @rmtoll TIMxCR     RSYNCU         LL_HRTIM_TIM_IsEnabledResyncUpdate
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of RSYNC bit in HRTIM_TIMxCR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResyncUpdate(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMCR_RSYNCU) == (HRTIM_TIMCR_RSYNCU)) ? 1UL : 0UL);
+  /* This bit is significant only when UPDGAT[3:0] = 0000, it is ignored otherwise */
+}
+
+/**
+  * @note Interleaved mode complements the Half mode and helps the implementation of interleaved topologies.
+  * @note When interleaved mode is enabled, the content of the compare registers is overridden.
+  * @rmtoll MCR        HALF      LL_HRTIM_TIM_SetInterleavedMode\n
+  *         MCR        INTLVD    LL_HRTIM_TIM_SetInterleavedMode\n
+  *         TIMxCR     HALF      LL_HRTIM_TIM_SetInterleavedMode\n
+  *         TIMxCR     INTLVD    LL_HRTIM_TIM_SetInterleavedMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
+  *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
+  *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
+  *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetInterleavedMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+
+  MODIFY_REG(*pReg, REG_MASK_TAB_INTLVD[iTimer],
+             ((Mode & HRTIM_MCR_HALF) | ((Mode & HRTIM_MCR_INTLVD) << REG_SHIFT_TAB_INTLVD[iTimer])));
+}
+
+/**
+  * @brief  get the Interleaved configuration.
+  * @rmtoll MCR        INTLVD         LL_HRTIM_TIM_GetInterleavedMode\n
+  *         TIMxCR     INTLVD         LL_HRTIM_TIM_GetInterleavedMode
+  * @note The interleaved Mode is Triple or Quad if HALF bit is disabled
+  *              the interleaved Mode is dual if HALF bit is set,
+
+  *              HRTIM_MCMP1R (or HRTIM_CMP1xR) active register is automatically updated
+  *              with HRTIM_MPER/2 or HRTIM_MPER/4
+  *       (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.
+
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_DISABLED
+  *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_DUAL
+  *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_TRIPLE
+  *         @arg @ref LL_HRTIM_INTERLEAVED_MODE_QUAD
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetInterleavedMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+
+  uint32_t Mode = READ_BIT(*pReg, (REG_MASK_TAB_INTLVD[iTimer]));
+  return ((Mode & HRTIM_MCR_HALF) | ((Mode  >> REG_SHIFT_TAB_INTLVD[iTimer]) &  HRTIM_MCR_INTLVD));
+}
+
+/**
+  * @brief  Enable the timer start when receiving a synchronization input event.
+  * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_EnableStartOnSync\n
+  *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_EnableStartOnSync
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
+}
+
+/**
+  * @brief  Disable the timer start when receiving a synchronization input event.
+  * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_DisableStartOnSync\n
+  *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_DisableStartOnSync
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);
+}
+
+/**
+  * @brief  Indicate whether the timer start when receiving a synchronization input event.
+  * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_IsEnabledStartOnSync\n
+  *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_IsEnabledStartOnSync
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the timer reset when receiving a synchronization input event.
+  * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_EnableResetOnSync\n
+  *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_EnableResetOnSync
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
+}
+
+/**
+  * @brief  Disable the timer reset when receiving a synchronization input event.
+  * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_DisableResetOnSync\n
+  *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_DisableResetOnSync
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);
+}
+
+/**
+  * @brief  Indicate whether the timer reset when receiving a synchronization input event.
+  * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_IsEnabledResetOnSync\n
+  *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_IsEnabledResetOnSync
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
+  * @rmtoll MCR        DACSYNC        LL_HRTIM_TIM_SetDACTrig\n
+  *         TIMxCR     DACSYNC        LL_HRTIM_TIM_SetDACTrig
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  DACTrig This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DACTRIG_NONE
+  *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
+  *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
+  *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);
+}
+
+/**
+  * @brief  Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).
+  * @rmtoll MCR        DACSYNC        LL_HRTIM_TIM_GetDACTrig\n
+  *         TIMxCR     DACSYNC        LL_HRTIM_TIM_GetDACTrig
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval DACTrig Returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_DACTRIG_NONE
+  *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1
+  *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2
+  *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));
+}
+
+/**
+  * @brief  Enable the timer registers preload mechanism.
+  * @rmtoll MCR        PREEN        LL_HRTIM_TIM_EnablePreload\n
+  *         TIMxCR     PREEN        LL_HRTIM_TIM_EnablePreload
+  * @note When the preload mode is enabled, accessed registers are shadow registers.
+  *       Their content is transferred into the active register after an update request,
+  *       either software or synchronized with an event.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MCR_PREEN);
+}
+
+/**
+  * @brief  Disable the timer registers preload mechanism.
+  * @rmtoll MCR        PREEN        LL_HRTIM_TIM_DisablePreload\n
+  *         TIMxCR     PREEN        LL_HRTIM_TIM_DisablePreload
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);
+}
+
+/**
+  * @brief  Indicate whether the timer registers preload mechanism is enabled.
+  * @rmtoll MCR        PREEN        LL_HRTIM_TIM_IsEnabledPreload\n
+  *         TIMxCR     PREEN        LL_HRTIM_TIM_IsEnabledPreload
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the timer register update trigger.
+  * @rmtoll MCR           MREPU      LL_HRTIM_TIM_SetUpdateTrig\n
+  *         TIMxCR        TAU        LL_HRTIM_TIM_SetUpdateTrig\n
+  *         TIMxCR        TBU        LL_HRTIM_TIM_SetUpdateTrig\n
+  *         TIMxCR        TCU        LL_HRTIM_TIM_SetUpdateTrig\n
+  *         TIMxCR        TDU        LL_HRTIM_TIM_SetUpdateTrig\n
+  *         TIMxCR        TEU        LL_HRTIM_TIM_SetUpdateTrig\n
+  *         TIMxCR        TFU        LL_HRTIM_TIM_SetUpdateTrig\n
+  *         TIMxCR        MSTU       LL_HRTIM_TIM_SetUpdateTrig
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  UpdateTrig This parameter can be one of the following values:
+  *
+  *         For the master timer this parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
+  *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
+  *
+  *         For timer A..F this parameter can be:
+  *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
+  *         or a combination of the following values:
+  *         @arg @ref LL_HRTIM_UPDATETRIG_MASTER
+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
+  *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
+  *         @arg @ref LL_HRTIM_UPDATETRIG_RESET
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);
+}
+
+/**
+  * @brief  Get the timer register update trigger.
+  * @rmtoll MCR           MREPU      LL_HRTIM_TIM_GetUpdateTrig\n
+  *         TIMxCR        TBU        LL_HRTIM_TIM_GetUpdateTrig\n
+  *         TIMxCR        TCU        LL_HRTIM_TIM_GetUpdateTrig\n
+  *         TIMxCR        TDU        LL_HRTIM_TIM_GetUpdateTrig\n
+  *         TIMxCR        TEU        LL_HRTIM_TIM_GetUpdateTrig\n
+  *         TIMxCR        TFU        LL_HRTIM_TIM_GetUpdateTrig\n
+  *         TIMxCR        MSTU       LL_HRTIM_TIM_GetUpdateTrig
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval UpdateTrig Returned value can be one of the following values:
+  *
+  *         For the master timer this parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
+  *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
+  *
+  *         For timer A..F this parameter can be:
+  *         @arg @ref LL_HRTIM_UPDATETRIG_NONE
+  *         or a combination of the following values:
+  *         @arg @ref LL_HRTIM_UPDATETRIG_MASTER
+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A
+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B
+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C
+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D
+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E
+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_F
+  *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION
+  *         @arg @ref LL_HRTIM_UPDATETRIG_RESET
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >>  REG_SHIFT_TAB_UPDATETRIG[iTimer]);
+}
+
+/**
+  * @brief  Set  the timer registers update condition (how the registers update occurs relatively to the burst DMA  transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).
+  * @rmtoll MCR           BRSTDMA      LL_HRTIM_TIM_SetUpdateGating\n
+  *         TIMxCR        UPDGAT       LL_HRTIM_TIM_SetUpdateGating
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  UpdateGating This parameter can be one of the following values:
+  *
+  *         For the master timer this parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
+  *
+  *         For the timer A..F this parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));
+}
+
+/**
+  * @brief  Get  the timer registers update condition.
+  * @rmtoll MCR           BRSTDMA      LL_HRTIM_TIM_GetUpdateGating\n
+  *         TIMxCR        UPDGAT       LL_HRTIM_TIM_GetUpdateGating
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval UpdateGating Returned value can be one of the following values:
+  *
+  *         For the master timer this parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
+  *
+  *         For the timer A..F this parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT
+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST
+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE
+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1
+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2
+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3
+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE
+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE
+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >>  REG_SHIFT_TAB_UPDATEGATING[iTimer]);
+}
+
+/**
+  * @brief  Enable the push-pull mode.
+  * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_EnablePushPullMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
+}
+
+/**
+  * @brief  Disable the push-pull mode.
+  * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_DisablePushPullMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);
+}
+
+/**
+  * @brief  Indicate whether the push-pull mode is enabled.
+  * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_IsEnabledPushPullMode\n
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).
+  * @rmtoll TIMxCR        DELCMP2       LL_HRTIM_TIM_SetCompareMode\n
+  *         TIMxCR        DELCMP4       LL_HRTIM_TIM_SetCompareMode
+  * @note In auto-delayed mode  the compare match occurs independently from the timer counter value.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  CompareUnit This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_COMPAREUNIT_2
+  *         @arg @ref LL_HRTIM_COMPAREUNIT_4
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
+  *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
+  *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
+  *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,
+                                                 uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
+  MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));
+}
+
+/**
+  * @brief  Get the functioning mode of the compare unit.
+  * @rmtoll TIMxCR        DELCMP2       LL_HRTIM_TIM_GetCompareMode\n
+  *         TIMxCR        DELCMP4       LL_HRTIM_TIM_GetCompareMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  CompareUnit This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_COMPAREUNIT_2
+  *         @arg @ref LL_HRTIM_COMPAREUNIT_4
+  * @retval Mode Returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_COMPAREMODE_REGULAR
+  *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT
+  *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1
+  *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);
+  return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >>  shift);
+}
+
+/**
+  * @brief  Set the timer counter value.
+  * @rmtoll MCNTR        MCNT       LL_HRTIM_TIM_SetCounter\n
+  *         CNTxR        CNTx       LL_HRTIM_TIM_SetCounter
+  * @note  This function can only be called when the timer is stopped.
+  * @note  For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least
+  *        significant bits of the counter are not significant. They cannot be
+  *        written and return 0 when read.
+  * @note The timer behavior is not guaranteed if the counter value is set above
+  *       the period.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Counter Value between 0 and 0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);
+}
+
+/**
+  * @brief  Get actual timer counter value.
+  * @rmtoll MCNTR        MCNT       LL_HRTIM_TIM_GetCounter\n
+  *         CNTxR        CNTx       LL_HRTIM_TIM_GetCounter
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Counter Value between 0 and 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));
+}
+
+/**
+  * @brief  Set the timer period value.
+  * @rmtoll MPER        MPER       LL_HRTIM_TIM_SetPeriod\n
+  *         PERxR       PERx       LL_HRTIM_TIM_SetPeriod
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Period Value between 0 and 0xFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);
+}
+
+/**
+  * @brief  Get actual timer period value.
+  * @rmtoll MPER        MPER       LL_HRTIM_TIM_GetPeriod\n
+  *         PERxR       PERx       LL_HRTIM_TIM_GetPeriod
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Period Value between 0 and 0xFFFF
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_MPER_MPER));
+}
+
+/**
+  * @brief  Set the timer repetition period value.
+  * @rmtoll MREP        MREP       LL_HRTIM_TIM_SetRepetition\n
+  *         REPxR       REPx       LL_HRTIM_TIM_SetRepetition
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Repetition Value between 0 and 0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);
+}
+
+/**
+  * @brief  Get actual timer repetition period value.
+  * @rmtoll MREP        MREP       LL_HRTIM_TIM_GetRepetition\n
+  *         REPxR       REPx       LL_HRTIM_TIM_GetRepetition
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Repetition Value between 0 and 0xFF
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_MREP_MREP));
+}
+
+/**
+  * @brief  Set the compare value of the compare unit 1.
+  * @rmtoll MCMP1R      MCMP1       LL_HRTIM_TIM_SetCompare1\n
+  *         CMP1xR      CMP1x       LL_HRTIM_TIM_SetCompare1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  CompareValue Compare value must be above or equal to 3
+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);
+}
+
+/**
+  * @brief  Get actual compare value of the compare unit 1.
+  * @rmtoll MCMP1R      MCMP1       LL_HRTIM_TIM_GetCompare1\n
+  *         CMP1xR      CMP1x       LL_HRTIM_TIM_GetCompare1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval CompareValue Compare value must be above or equal to 3
+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));
+}
+
+/**
+  * @brief  Set the compare value of the compare unit 2.
+  * @rmtoll MCMP2R      MCMP2       LL_HRTIM_TIM_SetCompare2\n
+  *         CMP2xR      CMP2x       LL_HRTIM_TIM_SetCompare2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  CompareValue Compare value must be above or equal to 3
+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);
+}
+
+/**
+  * @brief  Get actual compare value of the compare unit 2.
+  * @rmtoll MCMP2R      MCMP2       LL_HRTIM_TIM_GetCompare2\n
+  *         CMP2xR      CMP2x       LL_HRTIM_TIM_GetCompare2\n
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval CompareValue Compare value must be above or equal to 3
+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));
+}
+
+/**
+  * @brief  Set the compare value of the compare unit 3.
+  * @rmtoll MCMP3R      MCMP3       LL_HRTIM_TIM_SetCompare3\n
+  *         CMP3xR      CMP3x       LL_HRTIM_TIM_SetCompare3
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  CompareValue Compare value must be above or equal to 3
+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);
+}
+
+/**
+  * @brief  Get actual compare value of the compare unit 3.
+  * @rmtoll MCMP3R      MCMP3       LL_HRTIM_TIM_GetCompare3\n
+  *         CMP3xR      CMP3x       LL_HRTIM_TIM_GetCompare3
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval CompareValue Compare value must be above or equal to 3
+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));
+}
+
+/**
+  * @brief  Set the compare value of the compare unit 4.
+  * @rmtoll MCMP4R      MCMP4       LL_HRTIM_TIM_SetCompare4\n
+  *         CMP4xR      CMP4x       LL_HRTIM_TIM_SetCompare4
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  CompareValue Compare value must be above or equal to 3
+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);
+}
+
+/**
+  * @brief  Get actual compare value of the compare unit 4.
+  * @rmtoll MCMP4R      MCMP4       LL_HRTIM_TIM_GetCompare4\n
+  *         CMP4xR      CMP4x       LL_HRTIM_TIM_GetCompare4
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval CompareValue Compare value must be above or equal to 3
+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));
+}
+
+/**
+  * @brief  Set the reset trigger of a timer counter.
+  * @rmtoll RSTxR      UPDT           LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      CMP2           LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      CMP4           LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      MSTPER         LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      MSTCMP1        LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      MSTCMP2        LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      MSTCMP3        LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      MSTCMP4        LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      EXTEVNT1       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      EXTEVNT2       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      EXTEVNT3       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      EXTEVNT4       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      EXTEVNT5       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      EXTEVNT6       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      EXTEVNT7       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      EXTEVNT8       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      EXTEVNT9       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      EXTEVNT10      LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMBCMP1       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMBCMP2       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMBCMP4       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMCCMP1       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMCCMP2       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMCCMP4       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMDCMP1       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMDCMP2       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMDCMP4       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMECMP1       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMECMP2       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMECMP4       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMFCMP1       LL_HRTIM_TIM_SetResetTrig\n
+  *         RSTxR      TIMFCMP2       LL_HRTIM_TIM_SetResetTrig
+  * @note The reset of the timer counter can be triggered by up to 30 events
+  *       that can be selected among the following sources:
+  *         @arg The timing unit: Compare 2, Compare 4 and Update (3 events).
+  *         @arg The master timer: Reset and Compare 1..4 (5 events).
+  *         @arg The external events EXTEVNT1..10 (10 events).
+  *         @arg All other timing units (e.g. Timer B..F for timer A): Compare 1, 2 and 4 (12 events).
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  ResetTrig This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_RESETTRIG_NONE
+  *         @arg @ref LL_HRTIM_RESETTRIG_UPDATE
+  *         @arg @ref LL_HRTIM_RESETTRIG_CMP2
+  *         @arg @ref LL_HRTIM_RESETTRIG_CMP4
+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_1
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_2
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_3
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_4
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_5
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_6
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_7
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_8
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_9
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_10
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  WRITE_REG(*pReg, ResetTrig);
+}
+
+/**
+  * @brief  Get actual reset trigger of a timer counter.
+  * @rmtoll RSTxR      UPDT           LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      CMP2           LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      CMP4           LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      MSTPER         LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      MSTCMP1        LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      MSTCMP2        LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      MSTCMP3        LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      MSTCMP4        LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      EXTEVNT1       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      EXTEVNT2       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      EXTEVNT3       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      EXTEVNT4       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      EXTEVNT5       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      EXTEVNT6       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      EXTEVNT7       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      EXTEVNT8       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      EXTEVNT9       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      EXTEVNT10      LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMBCMP1       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMBCMP2       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMBCMP4       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMCCMP1       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMCCMP2       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMCCMP4       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMDCMP1       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMDCMP2       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMDCMP4       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMECMP1       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMECMP2       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMECMP4       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMFCMP1       LL_HRTIM_TIM_GetResetTrig\n
+  *         RSTxR      TIMFCMP2       LL_HRTIM_TIM_GetResetTrig
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval ResetTrig Returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_RESETTRIG_NONE
+  *         @arg @ref LL_HRTIM_RESETTRIG_UPDATE
+  *         @arg @ref LL_HRTIM_RESETTRIG_CMP2
+  *         @arg @ref LL_HRTIM_RESETTRIG_CMP4
+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER
+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1
+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2
+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3
+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_1
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_2
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_3
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_4
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_5
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_6
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_7
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_8
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_9
+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_10
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP1
+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER5_CMP2
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_REG(*pReg));
+}
+
+/**
+  * @brief  Get captured value for capture unit 1.
+  * @rmtoll CPT1xR      CPT1x           LL_HRTIM_TIM_GetCapture1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Captured value
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_REG(*pReg));
+}
+
+/**
+  * @brief  Get the counting direction when capture 1 event occurred.
+  * @rmtoll CPT1xR      DIR           LL_HRTIM_TIM_GetCapture1Direction
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Filter This parameter can be one of the following values:
+  *         @arg @ref  LL_HRTIM_COUNTING_MODE_UP
+  *         @arg @ref  LL_HRTIM_COUNTING_MODE_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1Direction(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return ((READ_BIT(*pReg, HRTIM_CPT1R_DIR) >> HRTIM_CPT1R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos);
+}
+
+/**
+  * @brief  Get captured value for capture unit 2.
+  * @rmtoll CPT2xR      CPT2x           LL_HRTIM_TIM_GetCapture2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Captured value
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_REG(*pReg));
+}
+
+/**
+  * @brief  Get the counting direction when capture 2 event occurred.
+  * @rmtoll CPT2xR      DIR           LL_HRTIM_TIM_GetCapture2Direction
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Filter This parameter can be one of the following values:
+  *         @arg @ref  LL_HRTIM_COUNTING_MODE_UP
+  *         @arg @ref  LL_HRTIM_COUNTING_MODE_UP_DOWN
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2Direction(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return ((READ_BIT(*pReg, HRTIM_CPT2R_DIR) >> HRTIM_CPT2R_DIR_Pos) << HRTIM_TIMCR2_UDM_Pos);
+}
+
+/**
+  * @brief  Set the trigger of a capture unit for a given timer.
+  * @rmtoll CPT1xCR      SWCPT            LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      UPDCPT           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      EXEV1CPT         LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      EXEV2CPT         LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      EXEV3CPT         LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      EXEV4CPT         LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      EXEV5CPT         LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      EXEV6CPT         LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      EXEV7CPT         LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      EXEV8CPT         LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      EXEV9CPT         LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      EXEV10CPT        LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TA1SET           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TA1RST           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TACMP1           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TACMP2           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TB1SET           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TB1RST           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TBCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TBCMP2           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TC1SET           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TC1RST           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TCCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TCCMP2           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TD1SET           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TD1RST           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TDCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TDCMP2           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TE1SET           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TE1RST           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TECMP1           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TECMP2           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TF1SET           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TF1RST           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TFCMP1           LL_HRTIM_TIM_SetCaptureTrig\n
+  *         CPT1xCR      TFCMP2           LL_HRTIM_TIM_SetCaptureTrig
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  CaptureUnit This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_CAPTUREUNIT_1
+  *         @arg @ref LL_HRTIM_CAPTUREUNIT_2
+  * @param  CaptureTrig This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_NONE
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_SW
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,
+                                                 uint64_t CaptureTrig)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));
+
+  uint32_t cfg1 = (uint32_t)(CaptureTrig & 0x0000000000000FFFU);
+  uint32_t cfg2 = (uint32_t)((CaptureTrig & 0xFFFFF00F00000000U) >> 32U);
+
+  cfg2 = (cfg2 & REG_MASK_TAB_CPT[iTimer]) | ((cfg2 & 0x0000000FU) << (REG_SHIFT_TAB_CPT[iTimer]));
+
+  WRITE_REG(*pReg, (cfg1 | cfg2));
+
+}
+
+/**
+  * @brief  Get actual trigger of a capture unit for a given timer.
+  * @rmtoll CPT1xCR      SWCPT            LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      UPDCPT           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      EXEV1CPT         LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      EXEV2CPT         LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      EXEV3CPT         LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      EXEV4CPT         LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      EXEV5CPT         LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      EXEV6CPT         LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      EXEV7CPT         LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      EXEV8CPT         LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      EXEV9CPT         LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      EXEV10CPT        LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TA1SET           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TA1RST           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TACMP1           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TACMP2           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TB1SET           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TB1RST           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TBCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TBCMP2           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TC1SET           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TC1RST           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TCCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TCCMP2           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TD1SET           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TD1RST           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TDCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TDCMP2           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TE1SET           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TE1RST           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TECMP1           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TECMP2           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TF1SET           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TF1RST           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TFCMP1           LL_HRTIM_TIM_GetCaptureTrig\n
+  *         CPT1xCR      TFCMP2           LL_HRTIM_TIM_GetCaptureTrig
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  CaptureUnit This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_CAPTUREUNIT_1
+  *         @arg @ref LL_HRTIM_CAPTUREUNIT_2
+  * @retval CaptureTrig This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_NONE
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_SW
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TF1_SET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TF1_RESET
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP1
+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMF_CMP2
+  */
+__STATIC_INLINE uint64_t LL_HRTIM_TIM_GetCaptureTrig(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +
+                                                           (uint32_t)REG_OFFSET_TAB_TIMER[iTimer & 0x7U] + (CaptureUnit * 4U)));
+
+  uint64_t cfg;
+  uint32_t CaptureTrig = READ_REG(*pReg);
+
+  cfg = (uint64_t)(uint32_t)(((CaptureTrig & 0xFFFFF000U) & (uint32_t)REG_MASK_TAB_CPT[iTimer]) | (((CaptureTrig & 0xFFFFF000U) & (uint32_t)~REG_MASK_TAB_CPT[iTimer]) >> (REG_SHIFT_TAB_CPT[iTimer])));
+
+  return ((uint64_t)(((uint64_t)CaptureTrig & (uint64_t)0x00000FFFU) | (uint64_t)((cfg) << 32U)));
+}
+
+/**
+  * @brief  Enable deadtime insertion for a given timer.
+  * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_EnableDeadTime
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_OUTR_DTEN);
+}
+
+/**
+  * @brief  Disable deadtime insertion for a given timer.
+  * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_DisableDeadTime
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);
+}
+
+/**
+  * @brief  Indicate whether deadtime insertion is enabled for a given timer.
+  * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_IsEnabledDeadTime
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the delayed protection (DLYPRT) mode.
+  * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_SetDLYPRTMode\n
+  *         OUTxR      DLYPRT         LL_HRTIM_TIM_SetDLYPRTMode
+  * @note   This function must be called prior enabling the delayed protection
+  * @note   Balanced Idle mode is only available in push-pull mode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  DLYPRTMode Delayed protection (DLYPRT) mode
+  *
+  *         For timers A, B and C this parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
+  *
+  *         For timers D, E and F this parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);
+}
+
+/**
+  * @brief  Get the delayed protection (DLYPRT) mode.
+  * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_GetDLYPRTMode\n
+  *         OUTxR      DLYPRT         LL_HRTIM_TIM_GetDLYPRTMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval DLYPRTMode Delayed protection (DLYPRT) mode
+  *
+  *         For timers A, B and C this parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6
+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7
+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7
+  *
+  *         For timers D, E and F this parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8
+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9
+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9
+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));
+}
+
+/**
+  * @brief  Enable delayed protection (DLYPRT) for a given timer.
+  * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_EnableDLYPRT
+  * @note   This function must not be called once the concerned timer is enabled
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
+}
+
+/**
+  * @brief  Disable delayed protection (DLYPRT) for a given timer.
+  * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_DisableDLYPRT
+  * @note   This function must not be called once the concerned timer is enabled
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);
+}
+
+/**
+  * @brief  Indicate whether delayed protection (DLYPRT) is enabled for a given timer.
+  * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_IsEnabledDLYPRT
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the Balanced Idle Automatic Resume (BIAR) for a given timer.
+  * @rmtoll OUTxR      BIAR       LL_HRTIM_TIM_EnableBIAR
+  * @note   This function must not be called once the concerned timer is enabled
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_OUTR_BIAR);
+}
+
+/**
+  * @brief  Disable the Balanced Idle Automatic Resume (BIAR) for a given timer.
+  * @rmtoll OUTxR      BIAR       LL_HRTIM_TIM_DisableBIAR
+  * @note   This function must not be called once the concerned timer is enabled
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableBIAR(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].OUTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_OUTR_BIAR);
+}
+
+/**
+  * @brief  Indicate whether the Balanced Idle Automatic Resume (BIAR) is enabled for a given timer.
+  * @rmtoll OUTxR      BIAR       LL_HRTIM_TIM_IsEnabledBIAR
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledBIAR(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_OUTR_BIAR) == (HRTIM_OUTR_BIAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the fault channel(s) for a given timer.
+  * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_EnableFault\n
+  *         FLTxR      FLT2EN       LL_HRTIM_TIM_EnableFault\n
+  *         FLTxR      FLT3EN       LL_HRTIM_TIM_EnableFault\n
+  *         FLTxR      FLT4EN       LL_HRTIM_TIM_EnableFault\n
+  *         FLTxR      FLT5EN       LL_HRTIM_TIM_EnableFault\n
+  *         FLTxR      FLT6EN       LL_HRTIM_TIM_EnableFault
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Faults This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, Faults);
+}
+
+/**
+  * @brief  Disable the fault channel(s) for a given timer.
+  * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_DisableFault\n
+  *         FLTxR      FLT2EN       LL_HRTIM_TIM_DisableFault\n
+  *         FLTxR      FLT3EN       LL_HRTIM_TIM_DisableFault\n
+  *         FLTxR      FLT4EN       LL_HRTIM_TIM_DisableFault\n
+  *         FLTxR      FLT5EN       LL_HRTIM_TIM_DisableFault\n
+  *         FLTxR      FLT6EN       LL_HRTIM_TIM_DisableFault
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Faults This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, Faults);
+}
+
+/**
+  * @brief  Indicate whether the fault channel is enabled for a given timer.
+  * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_IsEnabledFault\n
+  *         FLTxR      FLT2EN       LL_HRTIM_TIM_IsEnabledFault\n
+  *         FLTxR      FLT3EN       LL_HRTIM_TIM_IsEnabledFault\n
+  *         FLTxR      FLT4EN       LL_HRTIM_TIM_IsEnabledFault\n
+  *         FLTxR      FLT5EN       LL_HRTIM_TIM_IsEnabledFault\n
+  *         FLTxR      FLT6EN       LL_HRTIM_TIM_IsEnabledFault
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Lock the fault conditioning set-up for a given timer.
+  * @rmtoll FLTxR      FLTLCK       LL_HRTIM_TIM_LockFault
+  * @note Timer fault-related set-up is frozen until the next HRTIM or system reset
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);
+}
+
+/**
+  * @brief  Define how the timer behaves during a burst mode operation.
+  * @rmtoll BMCR      MTBM       LL_HRTIM_TIM_SetBurstModeOption\n
+  *         BMCR      TABM       LL_HRTIM_TIM_SetBurstModeOption\n
+  *         BMCR      TBBM       LL_HRTIM_TIM_SetBurstModeOption\n
+  *         BMCR      TCBM       LL_HRTIM_TIM_SetBurstModeOption\n
+  *         BMCR      TDBM       LL_HRTIM_TIM_SetBurstModeOption\n
+  *         BMCR      TEBM       LL_HRTIM_TIM_SetBurstModeOption\n
+  *         BMCR      TFBM       LL_HRTIM_TIM_SetBurstModeOption
+  * @note This function must not be called when the burst mode is enabled
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  BurtsModeOption This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
+  *         @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)
+{
+  uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
+  MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);
+}
+
+/**
+  * @brief  Retrieve how the timer behaves during a burst mode operation.
+  * @rmtoll BMCR      MCR        LL_HRTIM_TIM_GetBurstModeOption\n
+  *         BMCR      TABM       LL_HRTIM_TIM_GetBurstModeOption\n
+  *         BMCR      TBBM       LL_HRTIM_TIM_GetBurstModeOption\n
+  *         BMCR      TCBM       LL_HRTIM_TIM_GetBurstModeOption\n
+  *         BMCR      TDBM       LL_HRTIM_TIM_GetBurstModeOption\n
+  *         BMCR      TEBM       LL_HRTIM_TIM_GetBurstModeOption\n
+  *         BMCR      TFBM       LL_HRTIM_TIM_GetBurstModeOption
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval BurtsMode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK
+  *         @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);
+  return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);
+}
+
+/**
+  * @brief  Program which registers are to be written by Burst DMA transfers.
+  * @rmtoll BDMUPDR      MTBM        LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDMUPDR      MICR        LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDMUPDR      MDIER       LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDMUPDR      MCNT        LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDMUPDR      MPER        LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDMUPDR      MREP        LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDMUPDR      MCMP1       LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDMUPDR      MCMP2       LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDMUPDR      MCMP3       LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDMUPDR      MCMP4       LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxCR      LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxICR     LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxDIER    LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxCNT     LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxPER     LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxREP     LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxCMP1    LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxCMP2    LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxCMP3    LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxCMP4    LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxDTR     LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxSET1R   LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxRST1R   LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxSET2R   LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxRST2R   LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxEEFR1   LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxEEFR2   LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxRSTR    LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxOUTR    LL_HRTIM_TIM_ConfigBurstDMA\n
+  *         BDTxUPDR     TIMxLTCH    LL_HRTIM_TIM_ConfigBurstDMA
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Registers Registers to be updated by the DMA request
+  *
+  *         For Master timer this parameter can be can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_BURSTDMA_NONE
+  *         @arg @ref LL_HRTIM_BURSTDMA_MCR
+  *         @arg @ref LL_HRTIM_BURSTDMA_MICR
+  *         @arg @ref LL_HRTIM_BURSTDMA_MDIER
+  *         @arg @ref LL_HRTIM_BURSTDMA_MCNT
+  *         @arg @ref LL_HRTIM_BURSTDMA_MPER
+  *         @arg @ref LL_HRTIM_BURSTDMA_MREP
+  *         @arg @ref LL_HRTIM_BURSTDMA_MCMP1
+  *         @arg @ref LL_HRTIM_BURSTDMA_MCMP2
+  *         @arg @ref LL_HRTIM_BURSTDMA_MCMP3
+  *         @arg @ref LL_HRTIM_BURSTDMA_MCMP4
+  *
+  *         For Timers A..F this parameter can be can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_BURSTDMA_NONE
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMMCR
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMICR
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMDIER
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMCNT
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMPER
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMREP
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMDTR
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR
+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR
+  *         @arg @ref LL_HRTIM_BURSTDMA_CR2
+  *         @arg @ref LL_HRTIM_BURSTDMA_EEFR3
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)
+{
+  const uint8_t REG_OFFSET_TAB_BDTUPR[] =
+  {
+    0x00U,   /* BDMUPR ; offset = 0x000 */
+    0x04U,   /* BDAUPR ; offset = 0x05C */
+    0x08U,   /* BDBUPR ; offset = 0x060 */
+    0x0CU,   /* BDCUPR ; offset = 0x064 */
+    0x10U,   /* BDDUPR ; offset = 0x068 */
+    0x14U,   /* BDEUPR ; offset = 0x06C */
+    0x1CU    /* BDFUPR ; offset = 0x074 */
+  };
+
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + REG_OFFSET_TAB_BDTUPR[iTimer]));
+  WRITE_REG(*pReg, Registers);
+}
+
+/**
+  * @brief  Indicate on which output the signal is currently applied.
+  * @rmtoll TIMxISR      CPPSTAT        LL_HRTIM_TIM_GetCurrentPushPullStatus
+  * @note Only significant when the timer operates in push-pull mode.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval CPPSTAT This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1
+  *         @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));
+}
+
+/**
+  * @brief  Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.
+  * @rmtoll TIMxISR      IPPSTAT        LL_HRTIM_TIM_GetIdlePushPullStatus
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval IPPSTAT This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1
+  *         @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));
+}
+
+/**
+  * @brief  Set the event filter for a given timer.
+  * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_SetEventFilter\n
+  *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_SetEventFilter\n
+  *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_SetEventFilter\n
+  *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_SetEventFilter\n
+  *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_SetEventFilter\n
+  *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_SetEventFilter\n
+  *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_SetEventFilter\n
+  *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_SetEventFilter\n
+  *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_SetEventFilter\n
+  *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_SetEventFilter
+  * @note This function must not be called when the timer counter is enabled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @param  Filter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EEFLTR_NONE
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
+  *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
+
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
+  MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+  * @brief  Get actual event filter settings for a given timer.
+  * @rmtoll EEFxR1      EE1FLTR        LL_HRTIM_TIM_GetEventFilter\n
+  *         EEFxR1      EE2FLTR        LL_HRTIM_TIM_GetEventFilter\n
+  *         EEFxR1      EE3FLTR        LL_HRTIM_TIM_GetEventFilter\n
+  *         EEFxR1      EE4FLTR        LL_HRTIM_TIM_GetEventFilter\n
+  *         EEFxR1      EE5FLTR        LL_HRTIM_TIM_GetEventFilter\n
+  *         EEFxR2      EE6FLTR        LL_HRTIM_TIM_GetEventFilter\n
+  *         EEFxR2      EE7FLTR        LL_HRTIM_TIM_GetEventFilter\n
+  *         EEFxR2      EE8FLTR        LL_HRTIM_TIM_GetEventFilter\n
+  *         EEFxR2      EE9FLTR        LL_HRTIM_TIM_GetEventFilter\n
+  *         EEFxR2      EE10FLTR       LL_HRTIM_TIM_GetEventFilter
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @retval Filter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EEFLTR_NONE
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF1_TIMBCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF2_TIMBCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF3_TIMBOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF4_TIMCCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF5_TIMCCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF6_TIMFCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF7_TIMDCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMAEEF8_TIMECMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF1_TIMACMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF2_TIMACMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF3_TIMAOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF4_TIMCCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF5_TIMCCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF6_TIMFCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF7_TIMDCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMBEEF8_TIMECMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF1_TIMACMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF2_TIMBCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF3_TIMBCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF4_TIMFCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF5_TIMDCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF6_TIMDCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF7_TIMDOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMCEEF8_TIMECMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF1_TIMACMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF2_TIMBCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF3_TIMCCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF4_TIMCCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF5_TIMCOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF6_TIMECMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF7_TIMECMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMDEEF8_TIMFCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF1_TIMACMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF2_TIMBCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF3_TIMCCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF4_TIMFCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF5_TIMFOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF6_TIMDCMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF7_TIMDCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMEEEF8_TIMDOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF1_TIMACMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF2_TIMBCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF3_TIMCCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF4_TIMDCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF5_TIMDCMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF6_TIMECMP1
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF7_TIMECMP4
+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKING_TIMFEEF8_TIMEOUT2
+  *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2
+  *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3
+  *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+  * @brief  Enable or disable event latch mechanism for a given timer.
+  * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
+  *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
+  *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
+  *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
+  *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
+  *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
+  *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
+  *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
+  *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n
+  *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_SetEventLatchStatus
+  * @note This function must not be called when the timer counter is enabled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @param  LatchStatus This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EELATCH_DISABLED
+  *         @arg @ref LL_HRTIM_EELATCH_ENABLED
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,
+                                                      uint32_t LatchStatus)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
+  MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+  * @brief  Get actual event latch status for a given timer.
+  * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
+  *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
+  *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
+  *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
+  *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
+  *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
+  *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
+  *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
+  *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n
+  *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_GetEventLatchStatus
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @retval LatchStatus This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EELATCH_DISABLED
+  *         @arg @ref LL_HRTIM_EELATCH_ENABLED
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+  * @brief  Select the Trigger-Half operating mode for a given timer.
+  * @note   This bitfield defines whether the compare 2 register
+  * @note   is behaving in standard mode (compare match issued as soon as counter equal compare)
+  * @note   or in triggered-half mode
+  * @rmtoll TIMxCR2    TRGHLF      LL_HRTIM_TIM_SetTriggeredHalfMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TRIGHALF_ENABLED
+  *         @arg @ref LL_HRTIM_TRIGHALF_DISABLED
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetTriggeredHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_TIMCR2_TRGHLF, Mode);
+}
+
+/**
+  * @brief  Get the Trigger-Half operating mode for a given timer.
+  * @note   This bitfield reports whether the compare 2 register
+  * @note   is behaving in standard mode (compare match issued as soon as counter equal compare)
+  * @note   or in triggered-half mode
+  * @rmtoll TIMxCR2    TRGHLF      LL_HRTIM_TIM_GetTriggeredHalfMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TRIGHALF_ENABLED
+  *         @arg @ref LL_HRTIM_TRIGHALF_DISABLED
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetTriggeredHalfMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(* pReg, HRTIM_TIMCR2_TRGHLF));
+}
+
+/**
+  * @brief  Select the compare 1 operating mode.
+  * @note   This bit defines the compare 1 operating mode:
+  * @note   0: the compare 1 event is generated when the counter is equal to the compare value
+  * @note   1: the compare 1 event is generated when the counter is greater than the compare value
+  * @rmtoll TIMxCR2    GTCMP1      LL_HRTIM_TIM_SetComp1Mode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_GTCMP1_EQUAL
+  *         @arg @ref LL_HRTIM_GTCMP1_GREATER
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetComp1Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP1, Mode);
+}
+
+/**
+  * @brief  Get the selected compare 1 operating mode.
+  * @note   This bit reports the compare 1 operating mode:
+  * @note   0: the compare 1 event is generated when the counter is equal to the compare value
+  * @note   1: the compare 1 event is generated when the counter is greater than the compare value
+  * @rmtoll TIMxCR2    GTCMP1      LL_HRTIM_TIM_GetComp1Mode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_GTCMP1_EQUAL
+  *         @arg @ref LL_HRTIM_GTCMP1_GREATER
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp1Mode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP1));
+}
+
+/**
+  * @brief  Select the compare 3 operating mode.
+  * @note   This bit defines the compare 3 operating mode:
+  * @note   0: the compare 3 event is generated when the counter is equal to the compare value
+  * @note   1: the compare 3 event is generated when the counter is greater than the compare value
+  * @rmtoll TIMxCR2    GTCMP3      LL_HRTIM_TIM_SetComp3Mode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_GTCMP3_EQUAL
+  *         @arg @ref LL_HRTIM_GTCMP3_GREATER
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetComp3Mode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_TIMCR2_GTCMP3, (Mode));
+}
+
+/**
+  * @brief  Get the selected compare 3 operating mode.
+  * @note   This bit reports the compare 3 operating mode:
+  * @note   0: the compare 3 event is generated when the counter is equal to the compare value
+  * @note   1: the compare 3 event is generated when the counter is greater than the compare value
+  * @rmtoll TIMxCR2    GTCMP3      LL_HRTIM_TIM_GetComp1Mode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_GTCMP3_EQUAL
+  *         @arg @ref LL_HRTIM_GTCMP3_GREATER
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetComp3Mode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].TIMxCR2) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(* pReg, HRTIM_TIMCR2_GTCMP3));
+}
+
+/**
+  * @brief  Select the roll-over mode.
+  * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
+  * @note Only concerns the Roll-over event with the following destinations: Update trigger, IRQ
+  *      and DMA requests, repetition counter decrement and External Event filtering.
+  * @rmtoll TIMxCR2    ROM      LL_HRTIM_TIM_SetRollOverMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_TIMCR2_ROM, (Mode << HRTIM_TIMCR2_ROM_Pos));
+}
+
+/**
+  * @brief  Get selected the roll-over mode.
+  * @rmtoll TIMxCR2    ROM      LL_HRTIM_TIM_GetRollOverMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Mode returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_TIMCR2_ROM) >> HRTIM_TIMCR2_ROM_Pos);
+}
+
+/**
+  * @brief  Select Fault and Event roll-over mode.
+  * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
+  * @note only concerns the Roll-over event used by the Fault and Event counters.
+  * @rmtoll TIMxCR2    FEROM      LL_HRTIM_TIM_SetFaultEventRollOverMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetFaultEventRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_TIMCR2_FEROM, (Mode << HRTIM_TIMCR2_FEROM_Pos));
+}
+
+/**
+  * @brief  Get selected Fault and Event role-over mode.
+  * @rmtoll TIMxCR2    FEROM      LL_HRTIM_TIM_GetFaultEventRollOverMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval  Mode returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetFaultEventRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_TIMCR2_FEROM) >> HRTIM_TIMCR2_FEROM_Pos);
+}
+
+/**
+  * @brief  Select the Burst mode roll-over mode.
+  * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
+  * @note Only concerns the Roll-over event used in the Burst mode controller, as clock as as burst mode trigger.
+  * @rmtoll TIMxCR2    BMROM      LL_HRTIM_TIM_SetBMRollOverMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetBMRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_TIMCR2_BMROM, (Mode << HRTIM_TIMCR2_BMROM_Pos));
+}
+
+/**
+  * @brief  Get selected Burst mode roll-over mode.
+  * @rmtoll TIMxCR2    ROM      LL_HRTIM_TIM_GetBMRollOverMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval  Mode returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBMRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_TIMCR2_BMROM) >> HRTIM_TIMCR2_BMROM_Pos);
+}
+
+/**
+  * @brief  Select the ADC roll-over mode.
+  * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
+  * @note Only concerns the Roll-over event used to trigger the ADC.
+  * @rmtoll TIMxCR2    BMROM      LL_HRTIM_TIM_SetADCRollOverMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetADCRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_TIMCR2_ADROM, (Mode << HRTIM_TIMCR2_ADROM_Pos));
+}
+
+/**
+  * @brief  Get selected ADC roll-over mode.
+  * @rmtoll TIMxCR2    BMROM      LL_HRTIM_TIM_GetADCRollOverMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval  Mode returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetADCRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_TIMCR2_ADROM) >> HRTIM_TIMCR2_ADROM_Pos);
+}
+
+/**
+  * @brief  Select the ADC roll-over mode.
+  * @note Only significant in up-down counting mode (see function @ref LL_HRTIM_TIM_SetCountingMode()).
+  * @note Only concerns concerns the Roll-over event which sets and/or resets the outputs,
+  *       as per HRTIM_SETxyR and HRTIM_RSTxyR settings (see function @ref LL_HRTIM_OUT_SetOutputSetSrc()
+  *       and function @ref LL_HRTIM_OUT_SetOutputResetSrc() respectively).
+  * @rmtoll TIMxCR2    OUTROM      LL_HRTIM_TIM_SetOutputRollOverMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetOutputRollOverMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_TIMCR2_OUTROM, (Mode << HRTIM_TIMCR2_OUTROM_Pos));
+}
+
+/**
+  * @brief  Get selected ADC roll-over mode.
+  * @rmtoll TIMxCR2    OUTROM      LL_HRTIM_TIM_GetOutputRollOverMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval  Mode returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_PER
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_RST
+  *         @arg @ref LL_HRTIM_ROLLOVER_MODE_BOTH
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetOutputRollOverMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_TIMCR2_OUTROM) >> HRTIM_TIMCR2_OUTROM_Pos);
+}
+
+/**
+  * @brief  Select the counting mode.
+  * @note The up-down counting mode is available for both continuous and single-shot
+  *       (retriggerable and nonretriggerable) operating modes
+  *       (see function @ref LL_HRTIM_TIM_SetCounterMode()).
+  * @note The counter roll-over event is defined differently in-up-down counting mode to
+  *       support various operating condition.
+  *       See @ref LL_HRTIM_TIM_SetCounterMode()
+  * @rmtoll TIMxCR2    UDM      LL_HRTIM_TIM_SetCountingMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_COUNTING_MODE_UP
+  *         @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetCountingMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_TIMCR2_UDM, Mode);
+}
+
+/**
+  * @brief  Get selected counting mode.
+  * @rmtoll TIMxCR2    UDM      LL_HRTIM_TIM_GetCountingMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval  Mode returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_COUNTING_MODE_UP
+  *         @arg @ref LL_HRTIM_COUNTING_MODE_UP_DOWN
+  * @retval None
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCountingMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_TIMCR2_UDM));
+}
+
+/**
+  * @brief  Select Dual Channel DAC Reset trigger.
+  * @note Significant only when Dual channel DAC trigger is enabled
+  *       (see function @ref LL_HRTIM_TIM_EnableDualDacTrigger()).
+  * @rmtoll TIMxCR2    DCDR      LL_HRTIM_TIM_SetDualDacResetTrigger
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DCDR_COUNTER
+  *         @arg @ref LL_HRTIM_DCDR_OUT1SET
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetDualDacResetTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDR, Mode);
+}
+
+/**
+  * @brief  Get selected Dual Channel DAC Reset trigger.
+  * @rmtoll TIMxCR2    DCDR      LL_HRTIM_TIM_GetDualDacResetTrigger
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval  Trigger returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_DCDR_COUNTER
+  *         @arg @ref LL_HRTIM_DCDR_OUT1SET
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacResetTrigger(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDR));
+}
+
+/**
+  * @brief  Select Dual Channel DAC Reset trigger.
+  * @rmtoll TIMxCR2    DCDS      LL_HRTIM_TIM_SetDualDacStepTrigger
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DCDS_CMP2
+  *         @arg @ref LL_HRTIM_DCDS_OUT1RST
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetDualDacStepTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(* pReg, HRTIM_TIMCR2_DCDS, Mode);
+}
+
+/**
+  * @brief  Get selected Dual Channel DAC Reset trigger.
+  * @rmtoll TIMxCR2    DCDS      LL_HRTIM_TIM_GetDualDacStepTrigger
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval  Trigger returned value can be one of the following values:
+  *         @arg @ref LL_HRTIM_DCDS_CMP2
+  *         @arg @ref LL_HRTIM_DCDS_OUT1RST
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDualDacStepTrigger(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_TIMCR2_DCDS));
+}
+
+/**
+  * @brief  Enable Dual Channel DAC trigger.
+  * @note Only significant when balanced Idle mode is enabled (see function @ref LL_HRTIM_TIM_SetDLYPRTMode()).
+  * @rmtoll TIMxCR2      DCDE      LL_HRTIM_TIM_EnableDualDacTrigger
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(* pReg, HRTIM_TIMCR2_DCDE);
+}
+
+/**
+  * @brief  Disable Dual Channel DAC trigger.
+  * @rmtoll TIMxCR2      DCDE      LL_HRTIM_TIM_DisableDualDacTrigger
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableDualDacTrigger(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(* pReg, HRTIM_TIMCR2_DCDE);
+}
+
+/**
+  * @brief  Indicate whether Dual Channel DAC trigger is enabled for a given timer.
+  * @rmtoll TIMxCR2      DCDE      LL_HRTIM_TIM_IsEnabledDualDacTrigger
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of DCDE bit in HRTIM_TIMxCR2 register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDualDacTrigger(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR2) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(* pReg, HRTIM_TIMCR2_DCDE) == (HRTIM_TIMCR2_DCDE)) ? 1UL : 0UL);
+}
+
+
+/**
+  * @brief  Set the external event counter threshold.
+  * @note The external event is propagated to the timer only if the number
+  *       of active edges is greater than the external event counter threshold.
+  * @rmtoll EEFxR3    EEVBCNT      LL_HRTIM_TIM_SetEventCounterThreshold\n
+  *         EEFxR3    EEVACNT      LL_HRTIM_TIM_SetEventCounterThreshold
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  EventCounter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_COUNTER_A
+  *         @arg @ref LL_HRTIM_EE_COUNTER_B
+  * @param  Threshold This parameter can be a number between Min_Data=0 and Max_Data=63
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
+                                                           uint32_t Threshold)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
+
+  MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVACNT << EventCounter), Threshold << (HRTIM_EEFR3_EEVACNT_Pos + EventCounter));
+}
+
+/**
+  * @brief  Get the programmed external event counter threshold.
+  * @rmtoll EEFxR3    EEVBCNT      LL_HRTIM_TIM_GetEventCounterThreshold\n
+  *         EEFxR3    EEVACNT      LL_HRTIM_TIM_GetEventCounterThreshold
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  EventCounter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_COUNTER_A
+  *         @arg @ref LL_HRTIM_EE_COUNTER_B
+  * @retval Threshold Value between Min_Data=0 and Max_Data=63
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterThreshold(const HRTIM_TypeDef *HRTIMx, uint32_t Timer,
+                                                               uint32_t EventCounter)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
+
+  return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACNT) << EventCounter)) >> ((HRTIM_EEFR3_EEVACNT_Pos + EventCounter)))  ;
+}
+
+/**
+  * @brief  Select the external event counter source.
+  * @note External event counting is only valid for edge-sensitive
+  *       external events (See function LL_HRTIM_EE_Config() and function
+  *       LL_HRTIM_EE_SetSensitivity()).
+  * @rmtoll EEFxR3    EEVBSEL      LL_HRTIM_TIM_SetEventCounterSource\n
+  *         EEFxR3    EEVASEL      LL_HRTIM_TIM_SetEventCounterSource
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  EventCounter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_COUNTER_A
+  *         @arg @ref LL_HRTIM_EE_COUNTER_B
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterSource(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
+                                                        uint32_t Event)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
+  uint32_t iEvent = (uint32_t)(POSITION_VAL(Event));
+
+  /* register SEL value is 0 if LL_HRTIM_EVENT_1, 1 if LL_HRTIM_EVENT_1, etc
+     and 9 if LL_HRTIM_EVENT_10 */
+  MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVASEL << EventCounter), iEvent << (HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
+}
+
+/**
+  * @brief  get the selected external event counter source.
+  *       LL_HRTIM_EE_SetSensitivity()).
+  * @rmtoll EEFxR3    EEVBSEL      LL_HRTIM_TIM_GetEventCounterSource\n
+  *         EEFxR3    EEVASEL      LL_HRTIM_TIM_GetEventCounterSource
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  EventCounter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_COUNTER_A
+  *         @arg @ref LL_HRTIM_EE_COUNTER_B
+  * @retval  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterSource(const HRTIM_TypeDef *HRTIMx, uint32_t Timer,
+                                                            uint32_t EventCounter)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
+
+  uint32_t iEvent = (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVASEL) << (EventCounter))) >> ((HRTIM_EEFR3_EEVASEL_Pos + EventCounter));
+
+  /* returned value is 0 if SEL is LL_HRTIM_EVENT_1, 1 if SEL is LL_HRTIM_EVENT_1, etc
+     and 9 if SEL is LL_HRTIM_EVENT_10 */
+  return ((uint32_t)0x1U << iEvent)  ;
+}
+
+/**
+  * @brief  Select the external event counter reset mode.
+  * @rmtoll EEFxR3    EEVBRSTM      LL_HRTIM_TIM_SetEventCounterResetMode\n
+  *         EEFxR3    EEVARSTM      LL_HRTIM_TIM_SetEventCounterResetMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  EventCounter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_COUNTER_A
+  *         @arg @ref LL_HRTIM_EE_COUNTER_B
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
+  *         @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_SetEventCounterResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter,
+                                                           uint32_t Mode)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
+
+  MODIFY_REG(*pReg, (HRTIM_EEFR3_EEVARSTM << (EventCounter)), Mode << (EventCounter));
+}
+
+/**
+  * @brief  Get selected external event counter reset mode.
+  * @rmtoll EEFxR3    EEVBRSTM      LL_HRTIM_TIM_GetEventCounterResetMode\n
+  *         EEFxR3    EEVARSTM      LL_HRTIM_TIM_GetEventCounterResetMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  EventCounter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_COUNTER_A
+  *         @arg @ref LL_HRTIM_EE_COUNTER_B
+  * @retval  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_UNCONDITIONAL
+  *         @arg @ref LL_HRTIM_EE_COUNTER_RSTMODE_CONDITIONAL
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventCounterResetMode(const HRTIM_TypeDef *HRTIMx, uint32_t Timer,
+                                                               uint32_t EventCounter)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
+
+  return ((READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVARSTM) << (EventCounter))) >> (EventCounter))  ;
+}
+
+/**
+  * @brief  Reset the external event counter.
+  * @rmtoll EEFxR3    EEVACRES      LL_HRTIM_TIM_ResetEventCounter\n
+  *         EEFxR3    EEVBCRES      LL_HRTIM_TIM_ResetEventCounter
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  EventCounter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_COUNTER_A
+  *         @arg @ref LL_HRTIM_EE_COUNTER_B
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_ResetEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
+
+  SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACRES) << EventCounter);
+}
+
+/**
+  * @brief  Enable the external event counter.
+  * @rmtoll EEFxR3    EEVACE      LL_HRTIM_TIM_EnableEventCounter\n
+  *         EEFxR3    EEVBCE      LL_HRTIM_TIM_EnableEventCounter
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  EventCounter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_COUNTER_A
+  *         @arg @ref LL_HRTIM_EE_COUNTER_B
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_EnableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
+
+  SET_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter);
+}
+
+/**
+  * @brief  Disable the external event counter.
+  * @rmtoll EEFxR3    EEVACE      LL_HRTIM_TIM_DisableEventCounter\n
+  *         EEFxR3    EEVBCE      LL_HRTIM_TIM_DisableEventCounter
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  EventCounter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_COUNTER_A
+  *         @arg @ref LL_HRTIM_EE_COUNTER_B
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_TIM_DisableEventCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t EventCounter)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
+
+  CLEAR_BIT(*pReg, (HRTIM_EEFR3_EEVACE << EventCounter));
+}
+
+
+/**
+  * @brief  Indicate whether the external event counter is enabled for a given timer.
+  * @rmtoll EEFxR3    EEVACE      LL_HRTIM_TIM_IsEnabledEventCounter\n
+  *         EEFxR3    EEVBCE      LL_HRTIM_TIM_IsEnabledEventCounter
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  EventCounter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_COUNTER_A
+  *         @arg @ref LL_HRTIM_EE_COUNTER_B
+  * @retval State of EEVxCE bit in RTIM_EEFxR3 register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledEventCounter(const HRTIM_TypeDef *HRTIMx, uint32_t Timer,
+                                                            uint32_t EventCounter)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[iTimer].EEFxR3)));
+
+  uint32_t temp; /* MISRAC-2012 compliance */
+  temp = READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter);
+
+  return ((temp == ((uint32_t)(HRTIM_EEFR3_EEVACE) << EventCounter)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure the dead time insertion feature for a given timer.
+  * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_Config\n
+  *         DTxR      SDTF       LL_HRTIM_DT_Config\n
+  *         DTxR      SDRT       LL_HRTIM_DT_Config
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16
+  *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE
+  *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);
+}
+
+/**
+  * @brief  Set the deadtime prescaler value.
+  * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_SetPrescaler
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);
+}
+
+/**
+  * @brief  Get actual deadtime prescaler value.
+  * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_GetPrescaler
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL4
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL2
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV1
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV2
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV4
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV8
+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV16
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));
+}
+
+/**
+  * @brief  Set the deadtime rising value.
+  * @rmtoll DTxR      DTR       LL_HRTIM_DT_SetRisingValue
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  RisingValue Value between 0 and 0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);
+}
+
+/**
+  * @brief  Get actual deadtime rising value.
+  * @rmtoll DTxR      DTR       LL_HRTIM_DT_GetRisingValue
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval RisingValue Value between 0 and 0x1FF
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_DTR_DTR));
+}
+
+/**
+  * @brief  Set the deadtime sign on rising edge.
+  * @rmtoll DTxR      SDTR       LL_HRTIM_DT_SetRisingSign
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  RisingSign This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE
+  *         @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);
+}
+
+/**
+  * @brief  Get actual deadtime sign on rising edge.
+  * @rmtoll DTxR      SDTR       LL_HRTIM_DT_GetRisingSign
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval RisingSign This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE
+  *         @arg @ref LL_HRTIM_DT_RISING_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_DTR_SDTR));
+}
+
+/**
+  * @brief  Set the deadime falling value.
+  * @rmtoll DTxR      DTF       LL_HRTIM_DT_SetFallingValue
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  FallingValue Value between 0 and 0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);
+}
+
+/**
+  * @brief  Get actual deadtime falling value
+  * @rmtoll DTxR      DTF       LL_HRTIM_DT_GetFallingValue
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval FallingValue Value between 0 and 0x1FF
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);
+}
+
+/**
+  * @brief  Set the deadtime sign on falling edge.
+  * @rmtoll DTxR      SDTF       LL_HRTIM_DT_SetFallingSign
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  FallingSign This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
+  *         @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);
+}
+
+/**
+  * @brief  Get actual deadtime sign on falling edge.
+  * @rmtoll DTxR      SDTF       LL_HRTIM_DT_GetFallingSign
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval FallingSign This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE
+  *         @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_DTR_SDTF));
+}
+
+/**
+  * @brief  Lock the deadtime value and sign on rising edge.
+  * @rmtoll DTxR      DTRLK       LL_HRTIM_DT_LockRising
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DT_LockRising(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_DTR_DTRLK);
+}
+
+/**
+  * @brief  Lock the deadtime sign on rising edge.
+  * @rmtoll DTxR      DTRSLK       LL_HRTIM_DT_LockRisingSign
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_DTR_DTRSLK);
+}
+
+/**
+  * @brief  Lock the deadtime value and sign on falling edge.
+  * @rmtoll DTxR      DTFLK       LL_HRTIM_DT_LockFalling
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_DTR_DTFLK);
+}
+
+/**
+  * @brief  Lock the deadtime sign on falling edge.
+  * @rmtoll DTxR      DTFSLK       LL_HRTIM_DT_LockFallingSign
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_DTR_DTFSLK);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration
+  * @{
+  */
+
+/**
+  * @brief  Configure the chopper stage for a given timer.
+  * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_Config\n
+  *         CHPxR      CARDTY       LL_HRTIM_CHP_Config\n
+  *         CHPxR      STRTPW       LL_HRTIM_CHP_Config
+  * @note This function must not be called if the chopper mode is already
+  *       enabled for one of the timer outputs.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);
+}
+
+/**
+  * @brief  Set prescaler determining the carrier frequency to be added on top
+  *         of the timer output signals when chopper mode is enabled.
+  * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_SetPrescaler
+  * @note This function must not be called if the chopper mode is already
+  *       enabled for one of the timer outputs.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);
+}
+
+/**
+  * @brief  Get actual chopper stage prescaler value.
+  * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_GetPrescaler
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240
+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));
+}
+
+/**
+  * @brief  Set the chopper duty cycle.
+  * @rmtoll CHPxR      CARDTY       LL_HRTIM_CHP_SetDutyCycle
+  * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
+  * @note This function must not be called if the chopper mode is already
+  *       enabled for one of the timer outputs.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  DutyCycle This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);
+}
+
+/**
+  * @brief  Get actual chopper duty cycle.
+  * @rmtoll CHPxR      CARDTY       LL_HRTIM_CHP_GetDutyCycle
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval DutyCycle This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750
+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));
+}
+
+/**
+  * @brief  Set the start pulse width.
+  * @rmtoll CHPxR      STRPW       LL_HRTIM_CHP_SetPulseWidth
+  * @note This function must not be called if the chopper mode is already
+  *       enabled for one of the timer outputs.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @param  PulseWidth This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);
+}
+
+/**
+  * @brief  Get actual start pulse width.
+  * @rmtoll CHPxR      STRPW       LL_HRTIM_CHP_GetPulseWidth
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval PulseWidth This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240
+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+  return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EF_Output_Management Output_Management
+  * @{
+  */
+
+/**
+  * @brief  Set the timer output set source.
+  * @rmtoll SETx1R      SST          LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      RESYNC       LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      PER          LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      CMP1         LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      CMP2         LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      CMP3         LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      CMP4         LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      MSTPER       LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      UPDATE       LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      SST          LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      RESYNC       LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      PER          LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      CMP1         LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      CMP2         LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      CMP3         LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      CMP4         LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      MSTPER       LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputSetSrc\n
+  *         SETx1R      UPDATE       LL_HRTIM_OUT_SetOutputSetSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @param SetSrc This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUTSET_NONE
+  *         @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
+  *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
+  *         @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
+  *         (source = TIMy and destination = TIMx, Compare Unit = CMPz).
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
+                                                     REG_OFFSET_TAB_SETxR[iOutput]));
+  WRITE_REG(*pReg, SetSrc);
+}
+
+/**
+  * @brief  Get the timer output set source.
+  * @rmtoll SETx1R      SST          LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      RESYNC       LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      PER          LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      CMP1         LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      CMP2         LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      CMP3         LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      CMP4         LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      MSTPER       LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      UPDATE       LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      SST          LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      RESYNC       LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      PER          LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      CMP1         LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      CMP2         LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      CMP3         LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      CMP4         LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      MSTPER       LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputSetSrc\n
+  *         SETx1R      UPDATE       LL_HRTIM_OUT_GetOutputSetSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval SetSrc This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUTSET_NONE
+  *         @arg @ref LL_HRTIM_OUTPUTSET_RESYNC
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMPER
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERPER
+  *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_MASTERCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV1_TIMACMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV2_TIMACMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV5_TIMCCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_1
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_2
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_3
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_4
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_5
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_6
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_7
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_8
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_9
+  *         @arg @ref LL_HRTIM_OUTPUTSET_EEV_10
+  *         @arg @ref LL_HRTIM_OUTPUTSET_UPDATE
+  *         (source = TIMy and destination = TIMx, Compare Unit = CMPz).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
+                                                           REG_OFFSET_TAB_SETxR[iOutput]));
+  return (uint32_t) READ_REG(*pReg);
+}
+
+/**
+  * @brief  Set the timer output reset source.
+  * @rmtoll RSTx1R      RST          LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      RESYNC       LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      PER          LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      CMP1         LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      CMP2         LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      CMP3         LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      CMP4         LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      MSTPER       LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      UPDATE       LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      RST          LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      RESYNC       LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      PER          LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      CMP1         LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      CMP2         LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      CMP3         LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      CMP4         LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      MSTPER       LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputResetSrc\n
+  *         RSTx1R      UPDATE       LL_HRTIM_OUT_SetOutputResetSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @param ResetSrc This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_NONE
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
+  *         (source = TIMy and destination = TIMx, Compare Unit = CMPz).
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
+                                                     REG_OFFSET_TAB_SETxR[iOutput]));
+  WRITE_REG(*pReg, ResetSrc);
+}
+
+/**
+  * @brief  Get the timer output set source.
+  * @rmtoll RSTx1R      RST          LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      RESYNC       LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      PER          LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      CMP1         LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      CMP2         LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      CMP3         LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      CMP4         LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      MSTPER       LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      UPDATE       LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      RST          LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      RESYNC       LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      PER          LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      CMP1         LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      CMP2         LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      CMP3         LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      CMP4         LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      MSTPER       LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputResetSrc\n
+  *         RSTx1R      UPDATE       LL_HRTIM_OUT_GetOutputResetSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval ResetSrc This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_NONE
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_RESYNC
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMPER
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERPER
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_MASTERCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV5_TIMCCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_1
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_2
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_3
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_4
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_5
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_6
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_7
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_8
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_9
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_EEV_10
+  *         @arg @ref LL_HRTIM_OUTPUTRESET_UPDATE
+  *         (source = TIMy and destination = TIMx, Compare Unit = CMPz).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +
+                                                           REG_OFFSET_TAB_SETxR[iOutput]));
+  return (uint32_t) READ_REG(*pReg);
+}
+
+/**
+  * @brief  Configure a timer output.
+  * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_Config\n
+  *         OUTxR      IDLEM1        LL_HRTIM_OUT_Config\n
+  *         OUTxR      IDLES1        LL_HRTIM_OUT_Config\n
+  *         OUTxR      FAULT1        LL_HRTIM_OUT_Config\n
+  *         OUTxR      CHP1          LL_HRTIM_OUT_Config\n
+  *         OUTxR      DIDL1         LL_HRTIM_OUT_Config\n
+  *         OUTxR      POL2          LL_HRTIM_OUT_Config\n
+  *         OUTxR      IDLEM2        LL_HRTIM_OUT_Config\n
+  *         OUTxR      IDLES2        LL_HRTIM_OUT_Config\n
+  *         OUTxR      FAULT2        LL_HRTIM_OUT_Config\n
+  *         OUTxR      CHP2          LL_HRTIM_OUT_Config\n
+  *         OUTxR      DIDL2         LL_HRTIM_OUT_Config
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
+  *         @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
+  *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
+  *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
+  *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
+  MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),
+             (Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+  * @brief  Set the polarity of a timer output.
+  * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_SetPolarity\n
+  *         OUTxR      POL2          LL_HRTIM_OUT_SetPolarity
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
+  *         @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
+  MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+  * @brief  Get actual polarity of the timer output.
+  * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_GetPolarity\n
+  *         OUTxR      POL2          LL_HRTIM_OUT_GetPolarity
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY
+  *         @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                           REG_OFFSET_TAB_OUTxR[iOutput]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+  * @brief  Set the output IDLE mode.
+  * @rmtoll OUTxR      IDLEM1          LL_HRTIM_OUT_SetIdleMode\n
+  *         OUTxR      IDLEM2          LL_HRTIM_OUT_SetIdleMode
+  * @note This function must not be called when the burst mode is active
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @param  IdleMode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_NO_IDLE
+  *         @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
+  MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));
+}
+
+/**
+  * @brief  Get actual output IDLE mode.
+  * @rmtoll OUTxR      IDLEM1          LL_HRTIM_OUT_GetIdleMode\n
+  *         OUTxR      IDLEM2          LL_HRTIM_OUT_GetIdleMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval IdleMode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_NO_IDLE
+  *         @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                           REG_OFFSET_TAB_OUTxR[iOutput]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+  * @brief  Set the output IDLE level.
+  * @rmtoll OUTxR      IDLES1          LL_HRTIM_OUT_SetIdleLevel\n
+  *         OUTxR      IDLES2          LL_HRTIM_OUT_SetIdleLevel
+  * @note This function must be called prior enabling the timer.
+  * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @param  IdleLevel This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
+  *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
+  MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+  * @brief  Get actual output IDLE level.
+  * @rmtoll OUTxR      IDLES1          LL_HRTIM_OUT_GetIdleLevel\n
+  *         OUTxR      IDLES2          LL_HRTIM_OUT_GetIdleLevel
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval IdleLevel This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE
+  *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                           REG_OFFSET_TAB_OUTxR[iOutput]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+  * @brief  Set the output FAULT state.
+  * @rmtoll OUTxR      FAULT1          LL_HRTIM_OUT_SetFaultState\n
+  *         OUTxR      FAULT2          LL_HRTIM_OUT_SetFaultState
+  * @note This function must not called when the timer is enabled and a fault
+  *       channel is enabled at timer level.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @param  FaultState This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
+  MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+  * @brief  Get actual FAULT state.
+  * @rmtoll OUTxR      FAULT1          LL_HRTIM_OUT_GetFaultState\n
+  *         OUTxR      FAULT2          LL_HRTIM_OUT_GetFaultState
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval FaultState This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION
+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE
+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE
+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                           REG_OFFSET_TAB_OUTxR[iOutput]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+  * @brief  Set the output chopper mode.
+  * @rmtoll OUTxR      CHP1          LL_HRTIM_OUT_SetChopperMode\n
+  *         OUTxR      CHP2          LL_HRTIM_OUT_SetChopperMode
+  * @note This function must not called when the timer is enabled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @param  ChopperMode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
+  *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
+  MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+  * @brief  Get actual output chopper mode
+  * @rmtoll OUTxR      CHP1          LL_HRTIM_OUT_GetChopperMode\n
+  *         OUTxR      CHP2          LL_HRTIM_OUT_GetChopperMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval ChopperMode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED
+  *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                           REG_OFFSET_TAB_OUTxR[iOutput]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+  * @brief  Set the output burst mode entry mode.
+  * @rmtoll OUTxR      DIDL1          LL_HRTIM_OUT_SetBMEntryMode\n
+  *         OUTxR      DIDL2          LL_HRTIM_OUT_SetBMEntryMode
+  * @note This function must not called when the timer is enabled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @param  BMEntryMode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
+  *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                     REG_OFFSET_TAB_OUTxR[iOutput]));
+  MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));
+}
+
+/**
+  * @brief  Get actual output burst mode entry mode.
+  * @rmtoll OUTxR      DIDL1          LL_HRTIM_OUT_GetBMEntryMode\n
+  *         OUTxR      DIDL2          LL_HRTIM_OUT_GetBMEntryMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval BMEntryMode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR
+  *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +
+                                                           REG_OFFSET_TAB_OUTxR[iOutput]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);
+}
+
+/**
+  * @brief  Get the level (active or inactive) of the designated output when the
+  *         delayed protection was triggered.
+  * @rmtoll TIMxISR      O1SRSR          LL_HRTIM_OUT_GetDLYPRTOutStatus\n
+  *         TIMxISR      O2SRSR          LL_HRTIM_OUT_GetDLYPRTOutStatus
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval OutputLevel This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
+  *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
+                                                           REG_OFFSET_TAB_OUTxR[iOutput]));
+  return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
+          HRTIM_TIMISR_O1STAT_Pos);
+}
+
+/**
+  * @brief  Force the timer output to its active or inactive level.
+  * @rmtoll SETx1R      SST          LL_HRTIM_OUT_ForceLevel\n
+  *         RSTx1R      SRT          LL_HRTIM_OUT_ForceLevel\n
+  *         SETx2R      SST          LL_HRTIM_OUT_ForceLevel\n
+  *         RSTx2R      SRT          LL_HRTIM_OUT_ForceLevel
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @param  OutputLevel This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
+  *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)
+{
+  const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =
+  {
+    0x04U,   /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE  */
+    0x00U    /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE  */
+  };
+
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +
+                                                     REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));
+  SET_BIT(*pReg, HRTIM_SET1R_SST);
+}
+
+/**
+  * @brief  Get actual output level, before the output stage (chopper, polarity).
+  * @rmtoll TIMxISR     O1CPY          LL_HRTIM_OUT_GetLevel\n
+  *         TIMxISR     O2CPY          LL_HRTIM_OUT_GetLevel
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Output This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUTPUT_TA1
+  *         @arg @ref LL_HRTIM_OUTPUT_TA2
+  *         @arg @ref LL_HRTIM_OUTPUT_TB1
+  *         @arg @ref LL_HRTIM_OUTPUT_TB2
+  *         @arg @ref LL_HRTIM_OUTPUT_TC1
+  *         @arg @ref LL_HRTIM_OUTPUT_TC2
+  *         @arg @ref LL_HRTIM_OUTPUT_TD1
+  *         @arg @ref LL_HRTIM_OUTPUT_TD2
+  *         @arg @ref LL_HRTIM_OUTPUT_TE1
+  *         @arg @ref LL_HRTIM_OUTPUT_TE2
+  *         @arg @ref LL_HRTIM_OUTPUT_TF1
+  *         @arg @ref LL_HRTIM_OUTPUT_TF2
+  * @retval OutputLevel This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE
+  *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(const HRTIM_TypeDef *HRTIMx, uint32_t Output)
+{
+  uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +
+                                                           REG_OFFSET_TAB_OUTxR[iOutput]));
+  return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>
+          HRTIM_TIMISR_O1CPY_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management
+  * @{
+  */
+
+/**
+  * @brief  Configure external event conditioning.
+  * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_Config\n
+  *         EECR1     EE1POL          LL_HRTIM_EE_Config\n
+  *         EECR1     EE1SNS          LL_HRTIM_EE_Config\n
+  *         EECR1     EE1FAST         LL_HRTIM_EE_Config\n
+  *         EECR1     EE2SRC          LL_HRTIM_EE_Config\n
+  *         EECR1     EE2POL          LL_HRTIM_EE_Config\n
+  *         EECR1     EE2SNS          LL_HRTIM_EE_Config\n
+  *         EECR1     EE2FAST         LL_HRTIM_EE_Config\n
+  *         EECR1     EE3SRC          LL_HRTIM_EE_Config\n
+  *         EECR1     EE3POL          LL_HRTIM_EE_Config\n
+  *         EECR1     EE3SNS          LL_HRTIM_EE_Config\n
+  *         EECR1     EE3FAST         LL_HRTIM_EE_Config\n
+  *         EECR1     EE4SRC          LL_HRTIM_EE_Config\n
+  *         EECR1     EE4POL          LL_HRTIM_EE_Config\n
+  *         EECR1     EE4SNS          LL_HRTIM_EE_Config\n
+  *         EECR1     EE4FAST         LL_HRTIM_EE_Config\n
+  *         EECR1     EE5SRC          LL_HRTIM_EE_Config\n
+  *         EECR1     EE5POL          LL_HRTIM_EE_Config\n
+  *         EECR1     EE5SNS          LL_HRTIM_EE_Config\n
+  *         EECR1     EE5FAST         LL_HRTIM_EE_Config\n
+  *         EECR2     EE6SRC          LL_HRTIM_EE_Config\n
+  *         EECR2     EE6POL          LL_HRTIM_EE_Config\n
+  *         EECR2     EE6SNS          LL_HRTIM_EE_Config\n
+  *         EECR2     EE6FAST         LL_HRTIM_EE_Config\n
+  *         EECR2     EE7SRC          LL_HRTIM_EE_Config\n
+  *         EECR2     EE7POL          LL_HRTIM_EE_Config\n
+  *         EECR2     EE7SNS          LL_HRTIM_EE_Config\n
+  *         EECR2     EE7FAST         LL_HRTIM_EE_Config\n
+  *         EECR2     EE8SRC          LL_HRTIM_EE_Config\n
+  *         EECR2     EE8POL          LL_HRTIM_EE_Config\n
+  *         EECR2     EE8SNS          LL_HRTIM_EE_Config\n
+  *         EECR2     EE8FAST         LL_HRTIM_EE_Config\n
+  *         EECR2     EE9SRC          LL_HRTIM_EE_Config\n
+  *         EECR2     EE9POL          LL_HRTIM_EE_Config\n
+  *         EECR2     EE9SNS          LL_HRTIM_EE_Config\n
+  *         EECR2     EE9FAST         LL_HRTIM_EE_Config\n
+  *         EECR2     EE10SRC         LL_HRTIM_EE_Config\n
+  *         EECR2     EE10POL         LL_HRTIM_EE_Config\n
+  *         EECR2     EE10SNS         LL_HRTIM_EE_Config\n
+  *         EECR2     EE10FAST        LL_HRTIM_EE_Config
+  * @note This function must not be called when the timer counter is enabled.
+  * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.
+  * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg External event source 1 or External event source 2 or External event source 3 or External event source 4
+  *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW
+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
+  *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)
+{
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+                                                     REG_OFFSET_TAB_EECR[iEvent]));
+  MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),
+             (Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+  * @brief  Set the external event source.
+  * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_SetSrc\n
+  *         EECR1     EE2SRC          LL_HRTIM_EE_SetSrc\n
+  *         EECR1     EE3SRC          LL_HRTIM_EE_SetSrc\n
+  *         EECR1     EE4SRC          LL_HRTIM_EE_SetSrc\n
+  *         EECR1     EE5SRC          LL_HRTIM_EE_SetSrc\n
+  *         EECR2     EE6SRC          LL_HRTIM_EE_SetSrc\n
+  *         EECR2     EE7SRC          LL_HRTIM_EE_SetSrc\n
+  *         EECR2     EE8SRC          LL_HRTIM_EE_SetSrc\n
+  *         EECR2     EE9SRC          LL_HRTIM_EE_SetSrc\n
+  *         EECR2     EE10SRC         LL_HRTIM_EE_SetSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @param  Src This parameter can be one of the following values:
+  *         @arg External event source 1
+  *         @arg External event source 2
+  *         @arg External event source 3
+  *         @arg External event source 4
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)
+{
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+                                                     REG_OFFSET_TAB_EECR[iEvent]));
+  MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+  * @brief  Get actual external event source.
+  * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_GetSrc\n
+  *         EECR1     EE2SRC          LL_HRTIM_EE_GetSrc\n
+  *         EECR1     EE3SRC          LL_HRTIM_EE_GetSrc\n
+  *         EECR1     EE4SRC          LL_HRTIM_EE_GetSrc\n
+  *         EECR1     EE5SRC          LL_HRTIM_EE_GetSrc\n
+  *         EECR2     EE6SRC          LL_HRTIM_EE_GetSrc\n
+  *         EECR2     EE7SRC          LL_HRTIM_EE_GetSrc\n
+  *         EECR2     EE8SRC          LL_HRTIM_EE_GetSrc\n
+  *         EECR2     EE9SRC          LL_HRTIM_EE_GetSrc\n
+  *         EECR2     EE10SRC         LL_HRTIM_EE_GetSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @retval EventSrc This parameter can be one of the following values:
+  *         @arg External event source 1
+  *         @arg External event source 2
+  *         @arg External event source 3
+  *         @arg External event source 4
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+                                                           REG_OFFSET_TAB_EECR[iEvent]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+  * @brief  Set the polarity of an external event.
+  * @rmtoll EECR1     EE1POL          LL_HRTIM_EE_SetPolarity\n
+  *         EECR1     EE2POL          LL_HRTIM_EE_SetPolarity\n
+  *         EECR1     EE3POL          LL_HRTIM_EE_SetPolarity\n
+  *         EECR1     EE4POL          LL_HRTIM_EE_SetPolarity\n
+  *         EECR1     EE5POL          LL_HRTIM_EE_SetPolarity\n
+  *         EECR2     EE6POL          LL_HRTIM_EE_SetPolarity\n
+  *         EECR2     EE7POL          LL_HRTIM_EE_SetPolarity\n
+  *         EECR2     EE8POL          LL_HRTIM_EE_SetPolarity\n
+  *         EECR2     EE9POL          LL_HRTIM_EE_SetPolarity\n
+  *         EECR2     EE10POL         LL_HRTIM_EE_SetPolarity
+  * @note This function must not be called when the timer counter is enabled.
+  * @note Event polarity is only significant when event detection is level-sensitive.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH
+  *         @arg @ref LL_HRTIM_EE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)
+{
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+                                                     REG_OFFSET_TAB_EECR[iEvent]));
+  MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+  * @brief  Get actual polarity setting of an external event.
+  * @rmtoll EECR1     EE1POL          LL_HRTIM_EE_GetPolarity\n
+  *         EECR1     EE2POL          LL_HRTIM_EE_GetPolarity\n
+  *         EECR1     EE3POL          LL_HRTIM_EE_GetPolarity\n
+  *         EECR1     EE4POL          LL_HRTIM_EE_GetPolarity\n
+  *         EECR1     EE5POL          LL_HRTIM_EE_GetPolarity\n
+  *         EECR2     EE6POL          LL_HRTIM_EE_GetPolarity\n
+  *         EECR2     EE7POL          LL_HRTIM_EE_GetPolarity\n
+  *         EECR2     EE8POL          LL_HRTIM_EE_GetPolarity\n
+  *         EECR2     EE9POL          LL_HRTIM_EE_GetPolarity\n
+  *         EECR2     EE10POL         LL_HRTIM_EE_GetPolarity
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @retval Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH
+  *         @arg @ref LL_HRTIM_EE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+                                                           REG_OFFSET_TAB_EECR[iEvent]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+  * @brief  Set the sensitivity of an external event.
+  * @rmtoll EECR1     EE1SNS          LL_HRTIM_EE_SetSensitivity\n
+  *         EECR1     EE2SNS          LL_HRTIM_EE_SetSensitivity\n
+  *         EECR1     EE3SNS          LL_HRTIM_EE_SetSensitivity\n
+  *         EECR1     EE4SNS          LL_HRTIM_EE_SetSensitivity\n
+  *         EECR1     EE5SNS          LL_HRTIM_EE_SetSensitivity\n
+  *         EECR2     EE6SNS          LL_HRTIM_EE_SetSensitivity\n
+  *         EECR2     EE7SNS          LL_HRTIM_EE_SetSensitivity\n
+  *         EECR2     EE8SNS          LL_HRTIM_EE_SetSensitivity\n
+  *         EECR2     EE9SNS          LL_HRTIM_EE_SetSensitivity\n
+  *         EECR2     EE10SNS         LL_HRTIM_EE_SetSensitivity
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @param  Sensitivity This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
+  * @retval None
+  */
+
+__STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)
+{
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+                                                     REG_OFFSET_TAB_EECR[iEvent]));
+  MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+  * @brief  Get actual sensitivity setting of an external event.
+  * @rmtoll EECR1     EE1SNS          LL_HRTIM_EE_GetSensitivity\n
+  *         EECR1     EE2SNS          LL_HRTIM_EE_GetSensitivity\n
+  *         EECR1     EE3SNS          LL_HRTIM_EE_GetSensitivity\n
+  *         EECR1     EE4SNS          LL_HRTIM_EE_GetSensitivity\n
+  *         EECR1     EE5SNS          LL_HRTIM_EE_GetSensitivity\n
+  *         EECR2     EE6SNS          LL_HRTIM_EE_GetSensitivity\n
+  *         EECR2     EE7SNS          LL_HRTIM_EE_GetSensitivity\n
+  *         EECR2     EE8SNS          LL_HRTIM_EE_GetSensitivity\n
+  *         EECR2     EE9SNS          LL_HRTIM_EE_GetSensitivity\n
+  *         EECR2     EE10SNS         LL_HRTIM_EE_GetSensitivity
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @retval Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL
+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE
+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE
+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+                                                           REG_OFFSET_TAB_EECR[iEvent]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+  * @brief  Set the fast mode of an external event.
+  * @rmtoll EECR1     EE1FAST         LL_HRTIM_EE_SetFastMode\n
+  *         EECR1     EE2FAST         LL_HRTIM_EE_SetFastMode\n
+  *         EECR1     EE3FAST         LL_HRTIM_EE_SetFastMode\n
+  *         EECR1     EE4FAST         LL_HRTIM_EE_SetFastMode\n
+  *         EECR1     EE5FAST         LL_HRTIM_EE_SetFastMode\n
+  *         EECR2     EE6FAST         LL_HRTIM_EE_SetFastMode\n
+  *         EECR2     EE7FAST         LL_HRTIM_EE_SetFastMode\n
+  *         EECR2     EE8FAST         LL_HRTIM_EE_SetFastMode\n
+  *         EECR2     EE9FAST         LL_HRTIM_EE_SetFastMode\n
+  *         EECR2     EE10FAST        LL_HRTIM_EE_SetFastMode
+  * @note This function must not be called when the timer counter is enabled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  * @param  FastMode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
+  *         @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)
+{
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+                                                     REG_OFFSET_TAB_EECR[iEvent]));
+  MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+  * @brief  Get actual fast mode setting of an external event.
+  * @rmtoll EECR1     EE1FAST         LL_HRTIM_EE_GetFastMode\n
+  *         EECR1     EE2FAST         LL_HRTIM_EE_GetFastMode\n
+  *         EECR1     EE3FAST         LL_HRTIM_EE_GetFastMode\n
+  *         EECR1     EE4FAST         LL_HRTIM_EE_GetFastMode\n
+  *         EECR1     EE5FAST         LL_HRTIM_EE_GetFastMode\n
+  *         EECR2     EE6FAST         LL_HRTIM_EE_GetFastMode\n
+  *         EECR2     EE7FAST         LL_HRTIM_EE_GetFastMode\n
+  *         EECR2     EE8FAST         LL_HRTIM_EE_GetFastMode\n
+  *         EECR2     EE9FAST         LL_HRTIM_EE_GetFastMode\n
+  *         EECR2     EE10FAST        LL_HRTIM_EE_GetFastMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_1
+  *         @arg @ref LL_HRTIM_EVENT_2
+  *         @arg @ref LL_HRTIM_EVENT_3
+  *         @arg @ref LL_HRTIM_EVENT_4
+  *         @arg @ref LL_HRTIM_EVENT_5
+  * @retval FastMode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE
+  *         @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +
+                                                           REG_OFFSET_TAB_EECR[iEvent]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+  * @brief  Set the digital noise filter of a external event.
+  * @rmtoll EECR3     EE6F         LL_HRTIM_EE_SetFilter\n
+  *         EECR3     EE7F         LL_HRTIM_EE_SetFilter\n
+  *         EECR3     EE8F         LL_HRTIM_EE_SetFilter\n
+  *         EECR3     EE9F         LL_HRTIM_EE_SetFilter\n
+  *         EECR3     EE10F        LL_HRTIM_EE_SetFilter
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @param  Filter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_FILTER_NONE
+  *         @arg @ref LL_HRTIM_EE_FILTER_1
+  *         @arg @ref LL_HRTIM_EE_FILTER_2
+  *         @arg @ref LL_HRTIM_EE_FILTER_3
+  *         @arg @ref LL_HRTIM_EE_FILTER_4
+  *         @arg @ref LL_HRTIM_EE_FILTER_5
+  *         @arg @ref LL_HRTIM_EE_FILTER_6
+  *         @arg @ref LL_HRTIM_EE_FILTER_7
+  *         @arg @ref LL_HRTIM_EE_FILTER_8
+  *         @arg @ref LL_HRTIM_EE_FILTER_9
+  *         @arg @ref LL_HRTIM_EE_FILTER_10
+  *         @arg @ref LL_HRTIM_EE_FILTER_11
+  *         @arg @ref LL_HRTIM_EE_FILTER_12
+  *         @arg @ref LL_HRTIM_EE_FILTER_13
+  *         @arg @ref LL_HRTIM_EE_FILTER_14
+  *         @arg @ref LL_HRTIM_EE_FILTER_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)
+{
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));
+  MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),
+             (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));
+}
+
+/**
+  * @brief  Get actual digital noise filter setting of a external event.
+  * @rmtoll EECR3     EE6F         LL_HRTIM_EE_GetFilter\n
+  *         EECR3     EE7F         LL_HRTIM_EE_GetFilter\n
+  *         EECR3     EE8F         LL_HRTIM_EE_GetFilter\n
+  *         EECR3     EE9F         LL_HRTIM_EE_GetFilter\n
+  *         EECR3     EE10F        LL_HRTIM_EE_GetFilter
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Event This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EVENT_6
+  *         @arg @ref LL_HRTIM_EVENT_7
+  *         @arg @ref LL_HRTIM_EVENT_8
+  *         @arg @ref LL_HRTIM_EVENT_9
+  *         @arg @ref LL_HRTIM_EVENT_10
+  * @retval Filter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_FILTER_NONE
+  *         @arg @ref LL_HRTIM_EE_FILTER_1
+  *         @arg @ref LL_HRTIM_EE_FILTER_2
+  *         @arg @ref LL_HRTIM_EE_FILTER_3
+  *         @arg @ref LL_HRTIM_EE_FILTER_4
+  *         @arg @ref LL_HRTIM_EE_FILTER_5
+  *         @arg @ref LL_HRTIM_EE_FILTER_6
+  *         @arg @ref LL_HRTIM_EE_FILTER_7
+  *         @arg @ref LL_HRTIM_EE_FILTER_8
+  *         @arg @ref LL_HRTIM_EE_FILTER_9
+  *         @arg @ref LL_HRTIM_EE_FILTER_10
+  *         @arg @ref LL_HRTIM_EE_FILTER_11
+  *         @arg @ref LL_HRTIM_EE_FILTER_12
+  *         @arg @ref LL_HRTIM_EE_FILTER_13
+  *         @arg @ref LL_HRTIM_EE_FILTER_14
+  *         @arg @ref LL_HRTIM_EE_FILTER_15
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Event)
+{
+  uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));
+  return (READ_BIT(HRTIMx->sCommonRegs.EECR3,
+                   (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);
+}
+
+/**
+  * @brief  Set the external event prescaler.
+  * @rmtoll EECR3     EEVSD        LL_HRTIM_EE_SetPrescaler
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
+  * @retval None
+  */
+
+__STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
+{
+  MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);
+}
+
+/**
+  * @brief  Get actual external event prescaler setting.
+  * @rmtoll EECR3     EEVSD        LL_HRTIM_EE_GetPrescaler
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV1
+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV2
+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV4
+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV8
+  */
+
+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
+{
+  return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EF_Fault_management Fault_management
+  * @{
+  */
+/**
+  * @brief  Configure fault signal conditioning Polarity and Source.
+  * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_Config\n
+  *         FLTINR1     FLT1SRC      LL_HRTIM_FLT_Config\n
+  *         FLTINR1     FLT2P        LL_HRTIM_FLT_Config\n
+  *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_Config\n
+  *         FLTINR1     FLT3P        LL_HRTIM_FLT_Config\n
+  *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_Config\n
+  *         FLTINR1     FLT4P        LL_HRTIM_FLT_Config\n
+  *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_Config\n
+  *         FLTINR2     FLT5P        LL_HRTIM_FLT_Config\n
+  *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_Config\n
+  *         FLTINR2     FLT6P        LL_HRTIM_FLT_Config\n
+  *         FLTINR2     FLT6SRC      LL_HRTIM_FLT_Config
+  * @note This function must not be called when the fault channel is enabled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_EEVINPUT
+  *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
+  __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
+
+  uint64_t cfg;
+  uint64_t mask;
+
+  cfg = ((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_CONFIG_MASK) << REG_SHIFT_TAB_FLTxF[iFault]) |           /* this for SouRCe 0 and polarity bits */
+        (((uint64_t)((uint64_t)Configuration & (uint64_t)HRTIM_FLT_SRC_1_MASK) << REG_SHIFT_TAB_FLTx[iFault]) << 32U);      /* this for SouRCe 1 bit  */
+
+  mask = ((uint64_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) |       /* this for SouRCe 0 and polarity bits */
+         ((uint64_t)(HRTIM_FLT_SRC_1_MASK) << 32U);                                                         /* this for SouRCe bit 1 */
+
+  MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
+  MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg  >> 32U));
+
+}
+
+/**
+  * @brief  Set the source of a fault signal.
+  * @rmtoll FLTINR1     FLT1SRC      LL_HRTIM_FLT_SetSrc\n
+  *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_SetSrc\n
+  *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_SetSrc\n
+  *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_SetSrc\n
+  *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_SetSrc\n
+  *         FLTINR2     FLT6SRC      LL_HRTIM_FLT_SetSrc
+  * @note This function must not be called when the fault channel is enabled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @param  Src This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
+  *         @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
+  *         @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
+  __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
+
+  uint64_t  cfg = ((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) |        /* this for SouRCe 0 bit */
+                  (((uint64_t)((uint64_t)Src & (uint64_t)HRTIM_FLT_SRC_1_MASK)    << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe 1 bit */
+  uint64_t mask = ((uint64_t)(HRTIM_FLTINR1_FLT1SRC_0) << REG_SHIFT_TAB_FLTxF[iFault]) |        /* this for SouRCe bit 0 */
+                  (((uint64_t)(HRTIM_FLTINR2_FLT1SRC_1) << REG_SHIFT_TAB_FLTx[iFault]) << 32U); /* this for SouRCe bit 1 */
+
+  MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
+  MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg  >> 32U));
+}
+
+/**
+  * @brief  Get actual source of a fault signal.
+  * @rmtoll FLTINR1     FLT1SRC      LL_HRTIM_FLT_GetSrc\n
+  *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_GetSrc\n
+  *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_GetSrc\n
+  *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_GetSrc\n
+  *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_GetSrc\n
+  *         FLTINR2     FLT6SRC      LL_HRTIM_FLT_GetSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval Source This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT
+  *         @arg @ref LL_HRTIM_FLT_SRC_INTERNAL
+  *         @arg @ref LL_HRTIM_FLT_SRC_EEVINPUT
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
+  __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
+
+  uint64_t Src0;
+  uint32_t Src1;
+  uint32_t temp1, temp2; /* temp variables used for MISRA-C  */
+
+  /* this for SouRCe bit 1 */
+  Src1 = READ_BIT(*pReg2, HRTIM_FLT_SRC_1_MASK) >> REG_SHIFT_TAB_FLTx[iFault] ;
+  temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5SRC_0 | HRTIM_FLTINR2_FLT6SRC_0));
+  temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT4SRC_0));
+
+  /* this for SouRCe bit 0 */
+  Src0 = (uint64_t)temp1 << 32U;
+  Src0 |= (uint64_t)temp2;
+  Src0 = (Src0 >> REG_SHIFT_TAB_FLTxF[iFault]) ;
+
+  return ((uint32_t)(Src0 | Src1));
+}
+
+/**
+  * @brief  Set the polarity of a fault signal.
+  * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_SetPolarity\n
+  *         FLTINR1     FLT2P        LL_HRTIM_FLT_SetPolarity\n
+  *         FLTINR1     FLT3P        LL_HRTIM_FLT_SetPolarity\n
+  *         FLTINR1     FLT4P        LL_HRTIM_FLT_SetPolarity\n
+  *         FLTINR2     FLT5P        LL_HRTIM_FLT_SetPolarity\n
+  *         FLTINR2     FLT6P        LL_HRTIM_FLT_SetPolarity
+  * @note This function must not be called when the fault channel is enabled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW
+  *         @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
+  __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
+
+  uint64_t cfg = (uint64_t)((uint64_t)Polarity & (uint64_t)(HRTIM_FLTINR1_FLT1P)) << REG_SHIFT_TAB_FLTxF[iFault] ;  /* this for Polarity bit */
+  uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1P) << REG_SHIFT_TAB_FLTxF[iFault] ;  /* this for Polarity bit */
+
+  /* for Polarity bit */
+  MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(cfg));
+  MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(cfg  >> 32U));
+}
+
+/**
+  * @brief  Get actual polarity of a fault signal.
+  * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_GetPolarity\n
+  *         FLTINR1     FLT2P        LL_HRTIM_FLT_GetPolarity\n
+  *         FLTINR1     FLT3P        LL_HRTIM_FLT_GetPolarity\n
+  *         FLTINR1     FLT4P        LL_HRTIM_FLT_GetPolarity\n
+  *         FLTINR2     FLT5P        LL_HRTIM_FLT_GetPolarity\n
+  *         FLTINR2     FLT6P        LL_HRTIM_FLT_GetPolarity
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW
+  *         @arg @ref LL_HRTIM_FLT_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
+  __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
+  uint32_t temp1, temp2; /* temp variables used for MISRA-C  */
+  uint64_t cfg;
+
+  temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT6P));
+  temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT4P));
+
+  cfg = (uint64_t)temp1 << 32 ;
+  cfg |= (uint64_t)temp2;
+  cfg = (cfg >> REG_SHIFT_TAB_FLTxF[iFault]) ;
+
+  return (uint32_t)(cfg);
+
+}
+
+/**
+  * @brief  Set the digital noise filter of a fault signal.
+  * @rmtoll FLTINR1     FLT1F      LL_HRTIM_FLT_SetFilter\n
+  *         FLTINR1     FLT2F      LL_HRTIM_FLT_SetFilter\n
+  *         FLTINR1     FLT3F      LL_HRTIM_FLT_SetFilter\n
+  *         FLTINR1     FLT4F      LL_HRTIM_FLT_SetFilter\n
+  *         FLTINR2     FLT5F      LL_HRTIM_FLT_SetFilter\n
+  *         FLTINR2     FLT6F      LL_HRTIM_FLT_SetFilter
+  * @note This function must not be called when the fault channel is enabled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @param  Filter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FLT_FILTER_NONE
+  *         @arg @ref LL_HRTIM_FLT_FILTER_1
+  *         @arg @ref LL_HRTIM_FLT_FILTER_2
+  *         @arg @ref LL_HRTIM_FLT_FILTER_3
+  *         @arg @ref LL_HRTIM_FLT_FILTER_4
+  *         @arg @ref LL_HRTIM_FLT_FILTER_5
+  *         @arg @ref LL_HRTIM_FLT_FILTER_6
+  *         @arg @ref LL_HRTIM_FLT_FILTER_7
+  *         @arg @ref LL_HRTIM_FLT_FILTER_8
+  *         @arg @ref LL_HRTIM_FLT_FILTER_9
+  *         @arg @ref LL_HRTIM_FLT_FILTER_10
+  *         @arg @ref LL_HRTIM_FLT_FILTER_11
+  *         @arg @ref LL_HRTIM_FLT_FILTER_12
+  *         @arg @ref LL_HRTIM_FLT_FILTER_13
+  *         @arg @ref LL_HRTIM_FLT_FILTER_14
+  *         @arg @ref LL_HRTIM_FLT_FILTER_15
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
+  __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
+
+  uint64_t flt = (uint64_t)((uint64_t)Filter & (uint64_t)HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ;  /* this for filter bits */
+  uint64_t mask = (uint64_t)(HRTIM_FLTINR1_FLT1F) << REG_SHIFT_TAB_FLTxF[iFault] ;  /* this for Polarity bit */
+
+  MODIFY_REG(*pReg1, (uint32_t)(mask), (uint32_t)(flt));
+  MODIFY_REG(*pReg2, (uint32_t)(mask >> 32U), (uint32_t)(flt  >> 32U));
+}
+
+/**
+  * @brief  Get actual digital noise filter setting of a fault signal.
+  * @rmtoll FLTINR1     FLT1F      LL_HRTIM_FLT_GetFilter\n
+  *         FLTINR1     FLT2F      LL_HRTIM_FLT_GetFilter\n
+  *         FLTINR1     FLT3F      LL_HRTIM_FLT_GetFilter\n
+  *         FLTINR1     FLT4F      LL_HRTIM_FLT_GetFilter\n
+  *         FLTINR2     FLT5F      LL_HRTIM_FLT_GetFilter\n
+  *         FLTINR2     FLT6F      LL_HRTIM_FLT_GetFilter
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval Filter This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FLT_FILTER_NONE
+  *         @arg @ref LL_HRTIM_FLT_FILTER_1
+  *         @arg @ref LL_HRTIM_FLT_FILTER_2
+  *         @arg @ref LL_HRTIM_FLT_FILTER_3
+  *         @arg @ref LL_HRTIM_FLT_FILTER_4
+  *         @arg @ref LL_HRTIM_FLT_FILTER_5
+  *         @arg @ref LL_HRTIM_FLT_FILTER_6
+  *         @arg @ref LL_HRTIM_FLT_FILTER_7
+  *         @arg @ref LL_HRTIM_FLT_FILTER_8
+  *         @arg @ref LL_HRTIM_FLT_FILTER_9
+  *         @arg @ref LL_HRTIM_FLT_FILTER_10
+  *         @arg @ref LL_HRTIM_FLT_FILTER_11
+  *         @arg @ref LL_HRTIM_FLT_FILTER_12
+  *         @arg @ref LL_HRTIM_FLT_FILTER_13
+  *         @arg @ref LL_HRTIM_FLT_FILTER_14
+  *         @arg @ref LL_HRTIM_FLT_FILTER_15
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg1 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1)));
+  __IO uint32_t *pReg2 = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR2)));
+  uint32_t temp1, temp2; /* temp variables used for MISRA-C  */
+  uint64_t flt;
+  temp1 = READ_BIT(*pReg2, (uint32_t)(HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT6F));
+  temp2 = READ_BIT(*pReg1, (uint32_t)(HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT4F));
+
+  flt = (uint64_t)temp1 << 32U;
+  flt |= (uint64_t)temp2;
+  flt = (flt >> REG_SHIFT_TAB_FLTxF[iFault]) ;
+
+  return (uint32_t)(flt);
+
+}
+
+/**
+  * @brief  Set the fault circuitry prescaler.
+  * @rmtoll FLTINR2     FLTSD      LL_HRTIM_FLT_SetPrescaler
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
+{
+  MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);
+}
+
+/**
+  * @brief  Get actual fault circuitry prescaler setting.
+  * @rmtoll FLTINR2     FLTSD      LL_HRTIM_FLT_GetPrescaler
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1
+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2
+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4
+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
+{
+  return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));
+}
+
+/**
+  * @brief  Lock the fault signal conditioning settings.
+  * @rmtoll FLTINR1     FLT1LCK      LL_HRTIM_FLT_Lock\n
+  *         FLTINR1     FLT2LCK      LL_HRTIM_FLT_Lock\n
+  *         FLTINR1     FLT3LCK      LL_HRTIM_FLT_Lock\n
+  *         FLTINR1     FLT4LCK      LL_HRTIM_FLT_Lock\n
+  *         FLTINR2     FLT5LCK      LL_HRTIM_FLT_Lock\n
+  *         FLTINR2     FLT6LCK      LL_HRTIM_FLT_Lock
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+                                                     REG_OFFSET_TAB_FLTINR[iFault]));
+  SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+  * @brief  Enable the fault circuitry for the designated fault input.
+  * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_Enable\n
+  *         FLTINR1     FLT2E      LL_HRTIM_FLT_Enable\n
+  *         FLTINR1     FLT3E      LL_HRTIM_FLT_Enable\n
+  *         FLTINR1     FLT4E      LL_HRTIM_FLT_Enable\n
+  *         FLTINR2     FLT5E      LL_HRTIM_FLT_Enable\n
+  *         FLTINR2     FLT6E      LL_HRTIM_FLT_Enable
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+                                                     REG_OFFSET_TAB_FLTINR[iFault]));
+  SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+  * @brief  Disable the fault circuitry for for the designated fault input.
+  * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_Disable\n
+  *         FLTINR1     FLT2E      LL_HRTIM_FLT_Disable\n
+  *         FLTINR1     FLT3E      LL_HRTIM_FLT_Disable\n
+  *         FLTINR1     FLT4E      LL_HRTIM_FLT_Disable\n
+  *         FLTINR2     FLT5E      LL_HRTIM_FLT_Disable\n
+  *         FLTINR2     FLT6E      LL_HRTIM_FLT_Disable
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+                                                     REG_OFFSET_TAB_FLTINR[iFault]));
+  CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));
+
+}
+
+/**
+  * @brief  Indicate whether the fault circuitry is enabled for a given fault input.
+  * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_IsEnabled\n
+  *         FLTINR1     FLT2E      LL_HRTIM_FLT_IsEnabled\n
+  *         FLTINR1     FLT3E      LL_HRTIM_FLT_IsEnabled\n
+  *         FLTINR1     FLT4E      LL_HRTIM_FLT_IsEnabled\n
+  *         FLTINR2     FLT5E      LL_HRTIM_FLT_IsEnabled\n
+  *         FLTINR2     FLT6E      LL_HRTIM_FLT_IsEnabled
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +
+                                                           REG_OFFSET_TAB_FLTINR[iFault]));
+  return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==
+           (HRTIM_FLTINR1_FLT1E)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the Blanking of the fault circuitry for the designated fault input.
+  * @rmtoll FLTINR1     FLT1BLKE      LL_HRTIM_FLT_EnableBlanking\n
+  *         FLTINR1     FLT2BLKE      LL_HRTIM_FLT_EnableBlanking\n
+  *         FLTINR1     FLT3BLKE      LL_HRTIM_FLT_EnableBlanking\n
+  *         FLTINR1     FLT4BLKE      LL_HRTIM_FLT_EnableBlanking\n
+  *         FLTINR2     FLT5BLKE      LL_HRTIM_FLT_EnableBlanking\n
+  *         FLTINR2     FLT6BLKE      LL_HRTIM_FLT_EnableBlanking
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_EnableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
+                                                     REG_OFFSET_TAB_FLTINR[iFault]));
+  SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]);
+}
+
+/**
+  * @brief  Disable the Blanking of the fault circuitry for the designated fault input.
+  * @rmtoll FLTINR1     FLT1BLKE      LL_HRTIM_FLT_DisableBlanking\n
+  *         FLTINR1     FLT2BLKE      LL_HRTIM_FLT_DisableBlanking\n
+  *         FLTINR1     FLT3BLKE      LL_HRTIM_FLT_DisableBlanking\n
+  *         FLTINR1     FLT4BLKE      LL_HRTIM_FLT_DisableBlanking\n
+  *         FLTINR2     FLT5BLKE      LL_HRTIM_FLT_DisableBlanking\n
+  *         FLTINR2     FLT6BLKE      LL_HRTIM_FLT_DisableBlanking
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_DisableBlanking(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
+                                                     REG_OFFSET_TAB_FLTINR[iFault]));
+  CLEAR_BIT(*pReg, (HRTIM_FLTINR3_FLT1BLKE << REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+  * @brief  Indicate whether the Blanking of the fault circuitry is enabled for a given fault input.
+  * @rmtoll FLTINR1     FLT1BLKE      LL_HRTIM_FLT_IsEnabledBlanking\n
+  *         FLTINR1     FLT2BLKE      LL_HRTIM_FLT_IsEnabledBlanking\n
+  *         FLTINR1     FLT3BLKE      LL_HRTIM_FLT_IsEnabledBlanking\n
+  *         FLTINR1     FLT4BLKE      LL_HRTIM_FLT_IsEnabledBlanking\n
+  *         FLTINR2     FLT5BLKE      LL_HRTIM_FLT_IsEnabledBlanking\n
+  *         FLTINR2     FLT6BLKE      LL_HRTIM_FLT_IsEnabledBlanking
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval State of FLTxBLKE bit in HRTIM_FLTINRx register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabledBlanking(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
+                                                     REG_OFFSET_TAB_FLTINR[iFault]));
+  uint32_t temp; /* MISRAC-2012 compliance */
+  temp = READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKE) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault];
+
+  return ((temp == (HRTIM_FLTINR3_FLT1BLKE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the Blanking Source of the fault circuitry  for a given fault input.
+  * @note Fault inputs can be temporary disabled to blank spurious fault events.
+  * @note This function allows for selection amongst 2 possible blanking sources.
+  * @note Events triggering blanking window start and blanking window end depend
+  *       on both the selected blanking source and the fault input.
+  * @rmtoll FLTINR3     FLT1BLKS      LL_HRTIM_FLT_SetBlankingSrc\n
+  *         FLTINR3     FLT2BLKS      LL_HRTIM_FLT_SetBlankingSrc\n
+  *         FLTINR3     FLT3BLKS      LL_HRTIM_FLT_SetBlankingSrc\n
+  *         FLTINR3     FLT4BLKS      LL_HRTIM_FLT_SetBlankingSrc\n
+  *         FLTINR4     FLT5BLKS      LL_HRTIM_FLT_SetBlankingSrc\n
+  *         FLTINR4     FLT6BLKS      LL_HRTIM_FLT_SetBlankingSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @param  Source parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FLT_BLANKING_RSTALIGNED
+  *         @arg @ref LL_HRTIM_FLT_BLANKING_MOVING
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_SetBlankingSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Source)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
+                                                     REG_OFFSET_TAB_FLTINR[iFault]));
+  MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1BLKS << REG_SHIFT_TAB_FLTxE[iFault]), (Source << REG_SHIFT_TAB_FLTxE[iFault]));
+
+}
+
+/**
+  * @brief  Get the Blanking Source of the fault circuitry is enabled for a given fault input.
+  * @rmtoll FLTINR3     FLT1BLKS      LL_HRTIM_FLT_GetBlankingSrc\n
+  *         FLTINR3     FLT2BLKS      LL_HRTIM_FLT_GetBlankingSrc\n
+  *         FLTINR3     FLT3BLKS      LL_HRTIM_FLT_GetBlankingSrc\n
+  *         FLTINR3     FLT4BLKS      LL_HRTIM_FLT_GetBlankingSrc\n
+  *         FLTINR4     FLT5BLKS      LL_HRTIM_FLT_GetBlankingSrc\n
+  *         FLTINR4     FLT6BLKS      LL_HRTIM_FLT_GetBlankingSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetBlankingSrc(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
+                                                           REG_OFFSET_TAB_FLTINR[iFault]));
+  return ((READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1BLKS) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]));
+}
+
+/**
+  * @brief  Set the Counter threshold value of a fault counter.
+  * @rmtoll FLTINR3     FLT1CNT      LL_HRTIM_FLT_SetCounterThreshold\n
+  *         FLTINR3     FLT2CNT      LL_HRTIM_FLT_SetCounterThreshold\n
+  *         FLTINR3     FLT3CNT      LL_HRTIM_FLT_SetCounterThreshold\n
+  *         FLTINR3     FLT4CNT      LL_HRTIM_FLT_SetCounterThreshold\n
+  *         FLTINR4     FLT5CNT      LL_HRTIM_FLT_SetCounterThreshold\n
+  *         FLTINR4     FLT6CNT      LL_HRTIM_FLT_SetCounterThreshold
+  * @note This function must not be called when the fault channel is enabled.
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @param  Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_SetCounterThreshold(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Threshold)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
+                                                     REG_OFFSET_TAB_FLTINR[iFault]));
+  MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1CNT << REG_SHIFT_TAB_FLTxE[iFault]), (Threshold << REG_SHIFT_TAB_FLTxCNT[iFault]));
+}
+
+/**
+  * @brief  Get actual the Counter threshold value of a fault counter.
+  * @rmtoll FLTINR3     FLT1CNT      LL_HRTIM_FLT_GetCounterThreshold\n
+  *         FLTINR3     FLT2CNT      LL_HRTIM_FLT_GetCounterThreshold\n
+  *         FLTINR3     FLT3CNT      LL_HRTIM_FLT_GetCounterThreshold\n
+  *         FLTINR3     FLT4CNT      LL_HRTIM_FLT_GetCounterThreshold\n
+  *         FLTINR4     FLT5CNT      LL_HRTIM_FLT_GetCounterThreshold\n
+  *         FLTINR4     FLT6CNT      LL_HRTIM_FLT_GetCounterThreshold
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval Threshold This parameter can be a number between Min_Data=0 and Max_Data=15
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetCounterThreshold(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
+                                                           REG_OFFSET_TAB_FLTINR[iFault]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CNT) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxCNT[iFault]);
+}
+
+/**
+  * @brief  Set the mode of reset of a fault counter to 'always reset'.
+  * @rmtoll FLTINR3     FLT1RSTM      LL_HRTIM_FLT_SetResetMode\n
+  *         FLTINR3     FLT2RSTM      LL_HRTIM_FLT_SetResetMode\n
+  *         FLTINR3     FLT3RSTM      LL_HRTIM_FLT_SetResetMode\n
+  *         FLTINR3     FLT4RSTM      LL_HRTIM_FLT_SetResetMode\n
+  *         FLTINR4     FLT5RSTM      LL_HRTIM_FLT_SetResetMode\n
+  *         FLTINR4     FLT6RSTM      LL_HRTIM_FLT_SetResetMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
+  *         @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_SetResetMode(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Mode)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
+                                                     REG_OFFSET_TAB_FLTINR[iFault]));
+  MODIFY_REG(*pReg, (HRTIM_FLTINR3_FLT1RSTM << REG_SHIFT_TAB_FLTxE[iFault]), Mode << REG_SHIFT_TAB_FLTxE[iFault]);
+
+}
+
+/**
+  * @brief  Get the mode of reset of a fault counter to 'reset on event'.
+  * @rmtoll FLTINR3     FLT1RSTM      LL_HRTIM_FLT_GetResetMode\n
+  *         FLTINR3     FLT2RSTM      LL_HRTIM_FLT_GetResetMode\n
+  *         FLTINR3     FLT3RSTM      LL_HRTIM_FLT_GetResetMode\n
+  *         FLTINR3     FLT4RSTM      LL_HRTIM_FLT_GetResetMode\n
+  *         FLTINR4     FLT5RSTM      LL_HRTIM_FLT_GetResetMode\n
+  *         FLTINR4     FLT6RSTM      LL_HRTIM_FLT_GetResetMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FLT_COUNTERRST_UNCONDITIONAL
+  *         @arg @ref LL_HRTIM_FLT_COUNTERRST_CONDITIONAL
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetResetMode(const HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
+                                                           REG_OFFSET_TAB_FLTINR[iFault]));
+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1RSTM) << REG_SHIFT_TAB_FLTxE[iFault]) >> REG_SHIFT_TAB_FLTxE[iFault]);
+}
+
+/**
+  * @brief  Reset the fault counter for a fault circuitry
+  * @rmtoll FLTINR3     FLT1CRES      LL_HRTIM_FLT_ResetCounter\n
+  *         FLTINR3     FLT2CRES      LL_HRTIM_FLT_ResetCounter\n
+  *         FLTINR3     FLT3CRES      LL_HRTIM_FLT_ResetCounter\n
+  *         FLTINR3     FLT4CRES      LL_HRTIM_FLT_ResetCounter\n
+  *         FLTINR4     FLT5CRES      LL_HRTIM_FLT_ResetCounter\n
+  *         FLTINR4     FLT6CRES      LL_HRTIM_FLT_ResetCounter
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Fault This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_FAULT_1
+  *         @arg @ref LL_HRTIM_FAULT_2
+  *         @arg @ref LL_HRTIM_FAULT_3
+  *         @arg @ref LL_HRTIM_FAULT_4
+  *         @arg @ref LL_HRTIM_FAULT_5
+  *         @arg @ref LL_HRTIM_FAULT_6
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_FLT_ResetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)
+{
+  uint32_t iFault = (uint8_t)POSITION_VAL(Fault);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR3) +
+                                                     REG_OFFSET_TAB_FLTINR[iFault]));
+  SET_BIT(*pReg, (uint32_t)(HRTIM_FLTINR3_FLT1CRES) << REG_SHIFT_TAB_FLTxE[iFault]);
+
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management
+  * @{
+  */
+
+/**
+  * @brief  Configure the burst mode controller.
+  * @rmtoll BMCR     BMOM        LL_HRTIM_BM_Config\n
+  *         BMCR     BMCLK       LL_HRTIM_BM_Config\n
+  *         BMCR     BMPRSC      LL_HRTIM_BM_Config
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Configuration This parameter must be a combination of all the following values:
+  *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)
+{
+  MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);
+}
+
+/**
+  * @brief  Set the burst mode controller operating mode.
+  * @rmtoll BMCR     BMOM        LL_HRTIM_BM_SetMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
+  *         @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)
+{
+  MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);
+}
+
+/**
+  * @brief  Get actual burst mode controller operating mode.
+  * @rmtoll BMCR     BMOM        LL_HRTIM_BM_GetMode
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval Mode This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT
+  *         @arg @ref LL_HRTIM_BM_MODE_CONTINOUS
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(const HRTIM_TypeDef *HRTIMx)
+{
+  return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);
+}
+
+/**
+  * @brief  Set the burst mode controller clock source.
+  * @rmtoll BMCR     BMCLK       LL_HRTIM_BM_SetClockSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  ClockSrc This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)
+{
+  MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);
+}
+
+/**
+  * @brief  Get actual burst mode controller clock source.
+  * @rmtoll BMCR     BMCLK       LL_HRTIM_BM_GetClockSrc
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval ClockSrc This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_F
+  * @retval ClockSrc This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO
+  *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(const HRTIM_TypeDef *HRTIMx)
+{
+  return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);
+}
+
+/**
+  * @brief  Set the burst mode controller prescaler.
+  * @rmtoll BMCR     BMPRSC      LL_HRTIM_BM_SetPrescaler
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)
+{
+  MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);
+}
+
+/**
+  * @brief  Get actual burst mode controller prescaler setting.
+  * @rmtoll BMCR     BMPRSC      LL_HRTIM_BM_GetPrescaler
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval Prescaler This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV64
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV128
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV256
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV512
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384
+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(const HRTIM_TypeDef *HRTIMx)
+{
+  return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);
+}
+
+/**
+  * @brief  Enable burst mode compare and period registers preload.
+  * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_EnablePreload
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
+}
+
+/**
+  * @brief  Disable burst mode compare and period registers preload.
+  * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_DisablePreload
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
+}
+
+/**
+  * @brief  Indicate whether burst mode compare and period registers are preloaded.
+  * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_IsEnabledPreload
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(const HRTIM_TypeDef *HRTIMx)
+{
+  uint32_t temp; /* MISRAC-2012 compliance */
+  temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);
+
+  return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the burst mode controller trigger
+  * @rmtoll BMTRGR     SW           LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     MSTRST       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     MSTREP       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     MSTCMP1      LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     MSTCMP2      LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     MSTCMP3      LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     MSTCMP4      LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TARST        LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TAREP        LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TACMP1       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TACMP2       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TBRST        LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TBREP        LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TBCMP1       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TBCMP2       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TCRST        LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TCREP        LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TCCMP1       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TDRST        LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TDREP        LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TDCMP2       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TEREP        LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TECMP1       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TECMP2       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TFREP        LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TFRST        LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TFCMP1       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TAEEV7       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     TAEEV8       LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     EEV7         LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     EEV8         LL_HRTIM_BM_SetTrig\n
+  *         BMTRGR     OCHIPEV      LL_HRTIM_BM_SetTrig
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Trig This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_BM_TRIG_NONE
+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
+  *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
+  *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
+  *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
+    * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)
+{
+  WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);
+}
+
+/**
+  * @brief  Get actual burst mode controller trigger.
+  * @rmtoll BMTRGR     SW           LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     MSTRST       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     MSTREP       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     MSTCMP1      LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     MSTCMP2      LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     MSTCMP3      LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     MSTCMP4      LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TARST        LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TAREP        LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TACMP1       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TACMP2       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TBRST        LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TBREP        LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TBCMP1       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TBCMP2       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TCRST        LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TCREP        LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TCCMP1       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TDRST        LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TDREP        LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TDCMP2       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TEREP        LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TECMP1       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TECMP2       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TFREP        LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TFRST        LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TFCMP1       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TAEEV7       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     TAEEV8       LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     EEV7         LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     EEV8         LL_HRTIM_BM_GetTrig\n
+  *         BMTRGR     OCHIPEV      LL_HRTIM_BM_GetTrig
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval Trig This parameter can be a combination of the following values:
+  *         @arg @ref LL_HRTIM_BM_TRIG_NONE
+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET
+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1
+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2
+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3
+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMF_RESET
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMF_REPETITION
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMF_CMP1
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7
+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8
+  *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_7
+  *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_8
+  *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(const HRTIM_TypeDef *HRTIMx)
+{
+  return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);
+}
+
+/**
+  * @brief  Set the burst mode controller compare value.
+  * @rmtoll BMCMPR     BMCMP      LL_HRTIM_BM_SetCompare
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  CompareValue Compare value must be above or equal to 3
+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)
+{
+  WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);
+}
+
+/**
+  * @brief  Get actual burst mode controller compare value.
+  * @rmtoll BMCMPR     BMCMP      LL_HRTIM_BM_GetCompare
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval CompareValue Compare value must be above or equal to 3
+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,
+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(const HRTIM_TypeDef *HRTIMx)
+{
+  return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);
+}
+
+/**
+  * @brief  Set the burst mode controller period.
+  * @rmtoll BMPER     BMPER      LL_HRTIM_BM_SetPeriod
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Period The period value must be above or equal to 3 periods of the fHRTIM clock,
+  *         that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+  *         The maximum value is 0x0000 FFDF.
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)
+{
+  WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);
+}
+
+/**
+  * @brief  Get actual burst mode controller period.
+  * @rmtoll BMPER     BMPER      LL_HRTIM_BM_GetPeriod
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,
+  *         that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...
+  *         The maximum value is 0x0000 FFDF.
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(const HRTIM_TypeDef *HRTIMx)
+{
+  return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);
+}
+
+/**
+  * @brief  Enable the burst mode controller
+  * @rmtoll BMCR     BME      LL_HRTIM_BM_Enable
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
+}
+
+/**
+  * @brief  Disable the burst mode controller
+  * @rmtoll BMCR     BME      LL_HRTIM_BM_Disable
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);
+}
+
+/**
+  * @brief  Indicate whether the burst mode controller is enabled.
+  * @rmtoll BMCR     BME      LL_HRTIM_BM_IsEnabled
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of BME bit in HRTIM_BMCR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Trigger the burst operation (software trigger)
+  * @rmtoll BMTRGR     SW           LL_HRTIM_BM_Start
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
+}
+
+/**
+  * @brief  Stop the burst mode operation.
+  * @rmtoll BMCR     BMSTAT           LL_HRTIM_BM_Stop
+  * @note Causes a burst mode early termination.
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);
+}
+
+/**
+  * @brief  Get actual burst mode status
+  * @rmtoll BMCR     BMSTAT           LL_HRTIM_BM_GetStatus
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval Status This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_BM_STATUS_NORMAL
+  *         @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(const HRTIM_TypeDef *HRTIMx)
+{
+  return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Clear the Fault 1 interrupt flag.
+  * @rmtoll ICR     FLT1C           LL_HRTIM_ClearFlag_FLT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);
+}
+
+/**
+  * @brief  Indicate whether Fault 1 interrupt occurred.
+  * @rmtoll ICR     FLT1           LL_HRTIM_IsActiveFlag_FLT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Fault 2 interrupt flag.
+  * @rmtoll ICR     FLT2C           LL_HRTIM_ClearFlag_FLT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);
+}
+
+/**
+  * @brief  Indicate whether Fault 2 interrupt occurred.
+  * @rmtoll ICR     FLT2           LL_HRTIM_IsActiveFlag_FLT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Fault 3 interrupt flag.
+  * @rmtoll ICR     FLT3C           LL_HRTIM_ClearFlag_FLT3
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);
+}
+
+/**
+  * @brief  Indicate whether Fault 3 interrupt occurred.
+  * @rmtoll ICR     FLT3           LL_HRTIM_IsActiveFlag_FLT3
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Fault 4 interrupt flag.
+  * @rmtoll ICR     FLT4C           LL_HRTIM_ClearFlag_FLT4
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);
+}
+
+/**
+  * @brief  Indicate whether Fault 4 interrupt occurred.
+  * @rmtoll ICR     FLT4           LL_HRTIM_IsActiveFlag_FLT4
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Fault 5 interrupt flag.
+  * @rmtoll ICR     FLT5C           LL_HRTIM_ClearFlag_FLT5
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);
+}
+
+/**
+  * @brief  Indicate whether Fault 5 interrupt occurred.
+  * @rmtoll ICR     FLT5           LL_HRTIM_IsActiveFlag_FLT5
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Fault 6 interrupt flag.
+  * @rmtoll ICR     FLT6C           LL_HRTIM_ClearFlag_FLT6
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT6(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT6C);
+}
+
+/**
+  * @brief  Indicate whether Fault 6 interrupt occurred.
+  * @rmtoll ICR     FLT6           LL_HRTIM_IsActiveFlag_FLT6
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of FLT6 bit in HRTIM_ISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT6(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT6) == (HRTIM_ISR_FLT6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the System Fault interrupt flag.
+  * @rmtoll ICR     SYSFLTC           LL_HRTIM_ClearFlag_SYSFLT
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);
+}
+
+/**
+  * @brief  Indicate whether System Fault interrupt occurred.
+  * @rmtoll ISR     SYSFLT           LL_HRTIM_IsActiveFlag_SYSFLT
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the DLL ready interrupt flag.
+  * @rmtoll ICR     DLLRDYC           LL_HRTIM_ClearFlag_DLLRDY
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_DLLRDYC);
+}
+
+/**
+  * @brief  Indicate whether DLL ready  interrupt occurred.
+  * @rmtoll ISR     DLLRDY           LL_HRTIM_IsActiveFlag_DLLRDY
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of DLLRDY bit in HRTIM_ISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLLRDY(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_DLLRDY) == (HRTIM_ISR_DLLRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Burst Mode period interrupt flag.
+  * @rmtoll ICR     BMPERC           LL_HRTIM_ClearFlag_BMPER
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);
+}
+
+/**
+  * @brief  Indicate whether Burst Mode period interrupt occurred.
+  * @rmtoll ISR     BMPER           LL_HRTIM_IsActiveFlag_BMPER
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the Synchronization Input interrupt flag.
+  * @rmtoll MICR     SYNCC           LL_HRTIM_ClearFlag_SYNC
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);
+}
+
+/**
+  * @brief  Indicate whether the Synchronization Input interrupt occurred.
+  * @rmtoll MISR     SYNC           LL_HRTIM_IsActiveFlag_SYNC
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of SYNC bit in HRTIM_MISR register  (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the update interrupt flag for a given timer (including the master timer) .
+  * @rmtoll MICR        MUPDC          LL_HRTIM_ClearFlag_UPDATE\n
+  *         TIMxICR     UPDC           LL_HRTIM_ClearFlag_UPDATE
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MICR_MUPD);
+}
+
+/**
+  * @brief  Indicate whether the update interrupt has occurred for a given timer (including the master timer) .
+  * @rmtoll MISR        MUPD          LL_HRTIM_IsActiveFlag_UPDATE\n
+  *         TIMxISR     UPD           LL_HRTIM_IsActiveFlag_UPDATE
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the repetition interrupt flag for a given timer (including the master timer) .
+  * @rmtoll MICR        MREPC          LL_HRTIM_ClearFlag_REP\n
+  *         TIMxICR     REPC           LL_HRTIM_ClearFlag_REP
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MICR_MREP);
+
+}
+
+/**
+  * @brief  Indicate whether the repetition  interrupt has occurred for a given timer (including the master timer) .
+  * @rmtoll MISR        MREP          LL_HRTIM_IsActiveFlag_REP\n
+  *         TIMxISR     REP           LL_HRTIM_IsActiveFlag_REP
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the compare 1 match interrupt for a given timer (including the master timer).
+  * @rmtoll MICR        MCMP1C          LL_HRTIM_ClearFlag_CMP1\n
+  *         TIMxICR     CMP1C           LL_HRTIM_ClearFlag_CMP1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MICR_MCMP1);
+}
+
+/**
+  * @brief  Indicate whether the compare match 1  interrupt has occurred for a given timer (including the master timer) .
+  * @rmtoll MISR        MCMP1          LL_HRTIM_IsActiveFlag_CMP1\n
+  *         TIMxISR     CMP1           LL_HRTIM_IsActiveFlag_CMP1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the compare 2 match interrupt for a given timer (including the master timer).
+  * @rmtoll MICR        MCMP2C          LL_HRTIM_ClearFlag_CMP2\n
+  *         TIMxICR     CMP2C           LL_HRTIM_ClearFlag_CMP2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MICR_MCMP2);
+}
+
+/**
+  * @brief  Indicate whether the compare match 2  interrupt has occurred for a given timer (including the master timer) .
+  * @rmtoll MISR        MCMP2          LL_HRTIM_IsActiveFlag_CMP2\n
+  *         TIMxISR     CMP2           LL_HRTIM_IsActiveFlag_CMP2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the compare 3 match interrupt for a given timer (including the master timer).
+  * @rmtoll MICR        MCMP3C          LL_HRTIM_ClearFlag_CMP3\n
+  *         TIMxICR     CMP3C           LL_HRTIM_ClearFlag_CMP3
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MICR_MCMP3);
+}
+
+/**
+  * @brief  Indicate whether the compare match 3  interrupt has occurred for a given timer (including the master timer) .
+  * @rmtoll MISR        MCMP3          LL_HRTIM_IsActiveFlag_CMP3\n
+  *         TIMxISR     CMP3           LL_HRTIM_IsActiveFlag_CMP3
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the compare 4 match interrupt for a given timer (including the master timer).
+  * @rmtoll MICR        MCMP4C          LL_HRTIM_ClearFlag_CMP4\n
+  *         TIMxICR     CMP4C           LL_HRTIM_ClearFlag_CMP4
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MICR_MCMP4);
+}
+
+/**
+  * @brief  Indicate whether the compare match 4  interrupt has occurred for a given timer (including the master timer) .
+  * @rmtoll MISR        MCMP4          LL_HRTIM_IsActiveFlag_CMP4\n
+  *         TIMxISR     CMP4           LL_HRTIM_IsActiveFlag_CMP4
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the capture 1 interrupt flag for a given timer.
+  * @rmtoll TIMxICR     CPT1C           LL_HRTIM_ClearFlag_CPT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);
+}
+
+/**
+  * @brief  Indicate whether the capture 1 interrupt occurred for a given timer.
+  * @rmtoll TIMxISR     CPT1           LL_HRTIM_IsActiveFlag_CPT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the capture 2 interrupt flag for a given timer.
+  * @rmtoll TIMxICR     CPT2C           LL_HRTIM_ClearFlag_CPT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);
+}
+
+/**
+  * @brief  Indicate whether the capture 2 interrupt occurred for a given timer.
+  * @rmtoll TIMxISR     CPT2           LL_HRTIM_IsActiveFlag_CPT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the output 1 set interrupt flag for a given timer.
+  * @rmtoll TIMxICR     SET1C           LL_HRTIM_ClearFlag_SET1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMICR_SET1C);
+}
+
+/**
+  * @brief  Indicate whether the output 1 set interrupt occurred for a given timer.
+  * @rmtoll TIMxISR     SET1           LL_HRTIM_IsActiveFlag_SET1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the output 1 reset interrupt flag for a given timer.
+  * @rmtoll TIMxICR     RST1C           LL_HRTIM_ClearFlag_RST1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMICR_RST1C);
+}
+
+/**
+  * @brief  Indicate whether the output 1 reset interrupt occurred for a given timer.
+  * @rmtoll TIMxISR     RST1           LL_HRTIM_IsActiveFlag_RST1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the output 2 set interrupt flag for a given timer.
+  * @rmtoll TIMxICR     SET2C           LL_HRTIM_ClearFlag_SET2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMICR_SET2C);
+}
+
+/**
+  * @brief  Indicate whether the output 2 set interrupt occurred for a given timer.
+  * @rmtoll TIMxISR     SET2           LL_HRTIM_IsActiveFlag_SET2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the output 2reset interrupt flag for a given timer.
+  * @rmtoll TIMxICR     RST2C           LL_HRTIM_ClearFlag_RST2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMICR_RST2C);
+}
+
+/**
+  * @brief  Indicate whether the output 2 reset interrupt occurred for a given timer.
+  * @rmtoll TIMxISR     RST2           LL_HRTIM_IsActiveFlag_RST2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the reset and/or roll-over interrupt flag for a given timer.
+  * @rmtoll TIMxICR     RSTC           LL_HRTIM_ClearFlag_RST
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMICR_RSTC);
+}
+
+/**
+  * @brief  Indicate whether the  reset and/or roll-over interrupt occurred for a given timer.
+  * @rmtoll TIMxISR     RST           LL_HRTIM_IsActiveFlag_RST
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear the delayed protection interrupt flag for a given timer.
+  * @rmtoll TIMxICR     DLYPRTC           LL_HRTIM_ClearFlag_DLYPRT
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC);
+}
+
+/**
+  * @brief  Indicate whether the  delayed protection interrupt occurred for a given timer.
+  * @rmtoll TIMxISR     DLYPRT           LL_HRTIM_IsActiveFlag_DLYPRT
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable the fault 1 interrupt.
+  * @rmtoll IER     FLT1IE           LL_HRTIM_EnableIT_FLT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
+}
+
+/**
+  * @brief  Disable the fault 1 interrupt.
+  * @rmtoll IER     FLT1IE           LL_HRTIM_DisableIT_FLT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);
+}
+
+/**
+  * @brief  Indicate whether the fault 1 interrupt is enabled.
+  * @rmtoll IER     FLT1IE           LL_HRTIM_IsEnabledIT_FLT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the fault 2 interrupt.
+  * @rmtoll IER     FLT2IE           LL_HRTIM_EnableIT_FLT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
+}
+
+/**
+  * @brief  Disable the fault 2 interrupt.
+  * @rmtoll IER     FLT2IE           LL_HRTIM_DisableIT_FLT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);
+}
+
+/**
+  * @brief  Indicate whether the fault 2 interrupt is enabled.
+  * @rmtoll IER     FLT2IE           LL_HRTIM_IsEnabledIT_FLT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the fault 3 interrupt.
+  * @rmtoll IER     FLT3IE           LL_HRTIM_EnableIT_FLT3
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
+}
+
+/**
+  * @brief  Disable the fault 3 interrupt.
+  * @rmtoll IER     FLT3IE           LL_HRTIM_DisableIT_FLT3
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);
+}
+
+/**
+  * @brief  Indicate whether the fault 3 interrupt is enabled.
+  * @rmtoll IER     FLT3IE           LL_HRTIM_IsEnabledIT_FLT3
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the fault 4 interrupt.
+  * @rmtoll IER     FLT4IE           LL_HRTIM_EnableIT_FLT4
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
+}
+
+/**
+  * @brief  Disable the fault 4 interrupt.
+  * @rmtoll IER     FLT4IE           LL_HRTIM_DisableIT_FLT4
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);
+}
+
+/**
+  * @brief  Indicate whether the fault 4 interrupt is enabled.
+  * @rmtoll IER     FLT4IE           LL_HRTIM_IsEnabledIT_FLT4
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the fault 5 interrupt.
+  * @rmtoll IER     FLT5IE           LL_HRTIM_EnableIT_FLT5
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
+}
+
+/**
+  * @brief  Disable the fault 5 interrupt.
+  * @rmtoll IER     FLT5IE           LL_HRTIM_DisableIT_FLT5
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);
+}
+
+/**
+  * @brief  Indicate whether the fault 5 interrupt is enabled.
+  * @rmtoll IER     FLT5IE           LL_HRTIM_IsEnabledIT_FLT5
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the fault 6 interrupt.
+  * @rmtoll IER     FLT6IE           LL_HRTIM_EnableIT_FLT6
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT6(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6);
+}
+
+/**
+  * @brief  Disable the fault 6 interrupt.
+  * @rmtoll IER     FLT6IE           LL_HRTIM_DisableIT_FLT6
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT6(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6);
+}
+
+/**
+  * @brief  Indicate whether the fault 6 interrupt is enabled.
+  * @rmtoll IER     FLT6IE           LL_HRTIM_IsEnabledIT_FLT6
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of FLT6IE bit in HRTIM_IER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT6(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT6) == (HRTIM_IER_FLT6)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the system fault interrupt.
+  * @rmtoll IER     SYSFLTIE           LL_HRTIM_EnableIT_SYSFLT
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
+}
+
+/**
+  * @brief  Disable the system fault interrupt.
+  * @rmtoll IER     SYSFLTIE           LL_HRTIM_DisableIT_SYSFLT
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);
+}
+
+/**
+  * @brief  Indicate whether the system fault interrupt is enabled.
+  * @rmtoll IER     SYSFLTIE           LL_HRTIM_IsEnabledIT_SYSFLT
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the DLL ready interrupt.
+  * @rmtoll IER     DLLRDYIE           LL_HRTIM_EnableIT_DLLRDY
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
+}
+
+/**
+  * @brief  Disable the DLL ready interrupt.
+  * @rmtoll IER     DLLRDYIE           LL_HRTIM_DisableIT_DLLRDY
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_DLLRDY(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY);
+}
+
+/**
+  * @brief  Indicate whether the DLL ready interrupt is enabled.
+  * @rmtoll IER     DLLRDYIE           LL_HRTIM_IsEnabledIT_DLLRDY
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of DLLRDYIE bit in HRTIM_IER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLLRDY(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_DLLRDY) == (HRTIM_IER_DLLRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the burst mode period interrupt.
+  * @rmtoll IER     BMPERIE           LL_HRTIM_EnableIT_BMPER
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
+}
+
+/**
+  * @brief  Disable the burst mode period interrupt.
+  * @rmtoll IER     BMPERIE           LL_HRTIM_DisableIT_BMPER
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);
+}
+
+/**
+  * @brief  Indicate whether the burst mode period interrupt is enabled.
+  * @rmtoll IER     BMPERIE           LL_HRTIM_IsEnabledIT_BMPER
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the synchronization input interrupt.
+  * @rmtoll MDIER     SYNCIE           LL_HRTIM_EnableIT_SYNC
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
+}
+
+/**
+  * @brief  Disable the synchronization input interrupt.
+  * @rmtoll MDIER     SYNCIE           LL_HRTIM_DisableIT_SYNC
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);
+}
+
+/**
+  * @brief  Indicate whether the synchronization input interrupt is enabled.
+  * @rmtoll MDIER     SYNCIE           LL_HRTIM_IsEnabledIT_SYNC
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the update interrupt for a given timer.
+  * @rmtoll MDIER        MUPDIE           LL_HRTIM_EnableIT_UPDATE\n
+  *         TIMxDIER     UPDIE            LL_HRTIM_EnableIT_UPDATE
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);
+}
+
+/**
+  * @brief  Disable the update interrupt for a given timer.
+  * @rmtoll MDIER        MUPDIE           LL_HRTIM_DisableIT_UPDATE\n
+  *         TIMxDIER     UPDIE            LL_HRTIM_DisableIT_UPDATE
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);
+}
+
+/**
+  * @brief  Indicate whether the update interrupt is enabled for a given timer.
+  * @rmtoll MDIER        MUPDIE           LL_HRTIM_IsEnabledIT_UPDATE\n
+  *         TIMxDIER     UPDIE            LL_HRTIM_IsEnabledIT_UPDATE
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the repetition interrupt for a given timer.
+  * @rmtoll MDIER        MREPIE           LL_HRTIM_EnableIT_REP\n
+  *         TIMxDIER     REPIE            LL_HRTIM_EnableIT_REP
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MDIER_MREPIE);
+}
+
+/**
+  * @brief  Disable the repetition interrupt for a given timer.
+  * @rmtoll MDIER        MREPIE           LL_HRTIM_DisableIT_REP\n
+  *         TIMxDIER     REPIE            LL_HRTIM_DisableIT_REP
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);
+}
+
+/**
+  * @brief  Indicate whether the repetition interrupt is enabled for a given timer.
+  * @rmtoll MDIER        MREPIE           LL_HRTIM_IsEnabledIT_REP\n
+  *         TIMxDIER     REPIE            LL_HRTIM_IsEnabledIT_REP
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the compare 1 interrupt for a given timer.
+  * @rmtoll MDIER        MCMP1IE           LL_HRTIM_EnableIT_CMP1\n
+  *         TIMxDIER     CMP1IE            LL_HRTIM_EnableIT_CMP1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
+}
+
+/**
+  * @brief  Disable the compare 1 interrupt for a given timer.
+  * @rmtoll MDIER        MCMP1IE           LL_HRTIM_DisableIT_CMP1\n
+  *         TIMxDIER     CMP1IE            LL_HRTIM_DisableIT_CMP1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);
+}
+
+/**
+  * @brief  Indicate whether the compare 1 interrupt is enabled for a given timer.
+  * @rmtoll MDIER        MCMP1IE           LL_HRTIM_IsEnabledIT_CMP1\n
+  *         TIMxDIER     CMP1IE            LL_HRTIM_IsEnabledIT_CMP1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the compare 2 interrupt for a given timer.
+  * @rmtoll MDIER        MCMP2IE           LL_HRTIM_EnableIT_CMP2\n
+  *         TIMxDIER     CMP2IE            LL_HRTIM_EnableIT_CMP2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
+}
+
+/**
+  * @brief  Disable the compare 2 interrupt for a given timer.
+  * @rmtoll MDIER        MCMP2IE           LL_HRTIM_DisableIT_CMP2\n
+  *         TIMxDIER     CMP2IE            LL_HRTIM_DisableIT_CMP2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);
+}
+
+/**
+  * @brief  Indicate whether the compare 2 interrupt is enabled for a given timer.
+  * @rmtoll MDIER        MCMP2IE           LL_HRTIM_IsEnabledIT_CMP2\n
+  *         TIMxDIER     CMP2IE            LL_HRTIM_IsEnabledIT_CMP2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the compare 3 interrupt for a given timer.
+  * @rmtoll MDIER        MCMP3IE           LL_HRTIM_EnableIT_CMP3\n
+  *         TIMxDIER     CMP3IE            LL_HRTIM_EnableIT_CMP3
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
+}
+
+/**
+  * @brief  Disable the compare 3 interrupt for a given timer.
+  * @rmtoll MDIER        MCMP3IE           LL_HRTIM_DisableIT_CMP3\n
+  *         TIMxDIER     CMP3IE            LL_HRTIM_DisableIT_CMP3
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);
+}
+
+/**
+  * @brief  Indicate whether the compare 3 interrupt is enabled for a given timer.
+  * @rmtoll MDIER        MCMP3IE           LL_HRTIM_IsEnabledIT_CMP3\n
+  *         TIMxDIER     CMP3IE            LL_HRTIM_IsEnabledIT_CMP3
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the compare 4 interrupt for a given timer.
+  * @rmtoll MDIER        MCMP4IE           LL_HRTIM_EnableIT_CMP4\n
+  *         TIMxDIER     CMP4IE            LL_HRTIM_EnableIT_CMP4
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
+}
+
+/**
+  * @brief  Disable the compare 4 interrupt for a given timer.
+  * @rmtoll MDIER        MCMP4IE           LL_HRTIM_DisableIT_CMP4\n
+  *         TIMxDIER     CMP4IE            LL_HRTIM_DisableIT_CMP4
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);
+}
+
+/**
+  * @brief  Indicate whether the compare 4 interrupt is enabled for a given timer.
+  * @rmtoll MDIER        MCMP4IE           LL_HRTIM_IsEnabledIT_CMP4\n
+  *         TIMxDIER     CMP4IE            LL_HRTIM_IsEnabledIT_CMP4
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the capture 1 interrupt for a given timer.
+  * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_EnableIT_CPT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
+}
+
+/**
+  * @brief  Enable the capture 1 interrupt for a given timer.
+  * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_DisableIT_CPT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);
+}
+
+/**
+  * @brief  Indicate whether the capture 1 interrupt is enabled for a given timer.
+  * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_IsEnabledIT_CPT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the capture 2 interrupt for a given timer.
+  * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_EnableIT_CPT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
+}
+
+/**
+  * @brief  Enable the capture 2 interrupt for a given timer.
+  * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_DisableIT_CPT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);
+}
+
+/**
+  * @brief  Indicate whether the capture 2 interrupt is enabled for a given timer.
+  * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_IsEnabledIT_CPT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the output 1 set interrupt for a given timer.
+  * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_EnableIT_SET1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
+}
+
+/**
+  * @brief  Disable the output 1 set interrupt for a given timer.
+  * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_DisableIT_SET1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);
+}
+
+/**
+  * @brief  Indicate whether the output 1 set interrupt is enabled for a given timer.
+  * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_IsEnabledIT_SET1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the output 1 reset interrupt for a given timer.
+  * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_EnableIT_RST1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
+}
+
+/**
+  * @brief  Disable the output 1 reset interrupt for a given timer.
+  * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_DisableIT_RST1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);
+}
+
+/**
+  * @brief  Indicate whether the output 1 reset interrupt is enabled for a given timer.
+  * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_IsEnabledIT_RST1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the output 2 set interrupt for a given timer.
+  * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_EnableIT_SET2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
+}
+
+/**
+  * @brief  Disable the output 2 set interrupt for a given timer.
+  * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_DisableIT_SET2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);
+}
+
+/**
+  * @brief  Indicate whether the output 2 set interrupt is enabled for a given timer.
+  * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_IsEnabledIT_SET2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the output 2 reset interrupt for a given timer.
+  * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_EnableIT_RST2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
+}
+
+/**
+  * @brief  Disable the output 2 reset interrupt for a given timer.
+  * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_DisableIT_RST2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);
+}
+
+/**
+  * @brief  Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.
+  * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_DisableIT_RST2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the reset/roll-over interrupt for a given timer.
+  * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_EnableIT_RST
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
+}
+
+/**
+  * @brief  Disable the reset/roll-over interrupt for a given timer.
+  * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_DisableIT_RST
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);
+}
+
+/**
+  * @brief  Indicate whether the reset/roll-over interrupt is enabled for a given timer.
+  * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_IsEnabledIT_RST
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the delayed protection interrupt for a given timer.
+  * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_EnableIT_DLYPRT
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
+}
+
+/**
+  * @brief  Disable the delayed protection interrupt for a given timer.
+  * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_DisableIT_DLYPRT
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);
+}
+
+/**
+  * @brief  Indicate whether the delayed protection interrupt is enabled for a given timer.
+  * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_IsEnabledIT_DLYPRT
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable the synchronization input DMA request.
+  * @rmtoll MDIER     SYNCDE            LL_HRTIM_EnableDMAReq_SYNC
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+  SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
+}
+
+/**
+  * @brief  Disable the synchronization input DMA request
+  * @rmtoll MDIER     SYNCDE            LL_HRTIM_DisableDMAReq_SYNC
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)
+{
+  CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);
+}
+
+/**
+  * @brief  Indicate whether the synchronization input DMA request is enabled.
+  * @rmtoll MDIER     SYNCDE            LL_HRTIM_IsEnabledDMAReq_SYNC
+  * @param  HRTIMx High Resolution Timer instance
+  * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(const HRTIM_TypeDef *HRTIMx)
+{
+  return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the update DMA request for a given timer.
+  * @rmtoll MDIER        MUPDDE            LL_HRTIM_EnableDMAReq_UPDATE\n
+  *         TIMxDIER     UPDDE             LL_HRTIM_EnableDMAReq_UPDATE
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);
+}
+
+/**
+  * @brief  Disable the update DMA request for a given timer.
+  * @rmtoll MDIER        MUPDDE            LL_HRTIM_DisableDMAReq_UPDATE\n
+  *         TIMxDIER     UPDDE             LL_HRTIM_DisableDMAReq_UPDATE
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);
+}
+
+/**
+  * @brief  Indicate whether the update DMA request is enabled for a given timer.
+  * @rmtoll MDIER        MUPDDE            LL_HRTIM_IsEnabledDMAReq_UPDATE\n
+  *         TIMxDIER     UPDDE             LL_HRTIM_IsEnabledDMAReq_UPDATE
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the repetition DMA request for a given timer.
+  * @rmtoll MDIER        MREPDE            LL_HRTIM_EnableDMAReq_REP\n
+  *         TIMxDIER     REPDE             LL_HRTIM_EnableDMAReq_REP
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MDIER_MREPDE);
+}
+
+/**
+  * @brief  Disable the repetition DMA request for a given timer.
+  * @rmtoll MDIER        MREPDE            LL_HRTIM_DisableDMAReq_REP\n
+  *         TIMxDIER     REPDE             LL_HRTIM_DisableDMAReq_REP
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);
+}
+
+/**
+  * @brief  Indicate whether the repetition DMA request is enabled for a given timer.
+  * @rmtoll MDIER        MREPDE            LL_HRTIM_IsEnabledDMAReq_REP\n
+  *         TIMxDIER     REPDE             LL_HRTIM_IsEnabledDMAReq_REP
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the compare 1 DMA request for a given timer.
+  * @rmtoll MDIER        MCMP1DE            LL_HRTIM_EnableDMAReq_CMP1\n
+  *         TIMxDIER     CMP1DE             LL_HRTIM_EnableDMAReq_CMP1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
+}
+
+/**
+  * @brief  Disable the compare 1 DMA request for a given timer.
+  * @rmtoll MDIER        MCMP1DE            LL_HRTIM_DisableDMAReq_CMP1\n
+  *         TIMxDIER     CMP1DE             LL_HRTIM_DisableDMAReq_CMP1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);
+}
+
+/**
+  * @brief  Indicate whether the compare 1 DMA request is enabled for a given timer.
+  * @rmtoll MDIER        MCMP1DE            LL_HRTIM_IsEnabledDMAReq_CMP1\n
+  *         TIMxDIER     CMP1DE             LL_HRTIM_IsEnabledDMAReq_CMP1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the compare 2 DMA request for a given timer.
+  * @rmtoll MDIER        MCMP2DE            LL_HRTIM_EnableDMAReq_CMP2\n
+  *         TIMxDIER     CMP2DE             LL_HRTIM_EnableDMAReq_CMP2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
+}
+
+/**
+  * @brief  Disable the compare 2 DMA request for a given timer.
+  * @rmtoll MDIER        MCMP2DE            LL_HRTIM_DisableDMAReq_CMP2\n
+  *         TIMxDIER     CMP2DE             LL_HRTIM_DisableDMAReq_CMP2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);
+}
+
+/**
+  * @brief  Indicate whether the compare 2 DMA request is enabled for a given timer.
+  * @rmtoll MDIER        MCMP2DE            LL_HRTIM_IsEnabledDMAReq_CMP2\n
+  *         TIMxDIER     CMP2DE             LL_HRTIM_IsEnabledDMAReq_CMP2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the compare 3 DMA request for a given timer.
+  * @rmtoll MDIER        MCMP3DE            LL_HRTIM_EnableDMAReq_CMP3\n
+  *         TIMxDIER     CMP3DE             LL_HRTIM_EnableDMAReq_CMP3
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
+}
+
+/**
+  * @brief  Disable the compare 3 DMA request for a given timer.
+  * @rmtoll MDIER        MCMP3DE            LL_HRTIM_DisableDMAReq_CMP3\n
+  *         TIMxDIER     CMP3DE             LL_HRTIM_DisableDMAReq_CMP3
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);
+}
+
+/**
+  * @brief  Indicate whether the compare 3 DMA request is enabled for a given timer.
+  * @rmtoll MDIER        MCMP3DE            LL_HRTIM_IsEnabledDMAReq_CMP3\n
+  *         TIMxDIER     CMP3DE             LL_HRTIM_IsEnabledDMAReq_CMP3
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the compare 4 DMA request for a given timer.
+  * @rmtoll MDIER        MCMP4DE            LL_HRTIM_EnableDMAReq_CMP4\n
+  *         TIMxDIER     CMP4DE             LL_HRTIM_EnableDMAReq_CMP4
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
+}
+
+/**
+  * @brief  Disable the compare 4 DMA request for a given timer.
+  * @rmtoll MDIER        MCMP4DE            LL_HRTIM_DisableDMAReq_CMP4\n
+  *         TIMxDIER     CMP4DE             LL_HRTIM_DisableDMAReq_CMP4
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);
+}
+
+/**
+  * @brief  Indicate whether the compare 4 DMA request is enabled for a given timer.
+  * @rmtoll MDIER        MCMP4DE            LL_HRTIM_IsEnabledDMAReq_CMP4\n
+  *         TIMxDIER     CMP4DE             LL_HRTIM_IsEnabledDMAReq_CMP4
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_MASTER
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the capture 1 DMA request for a given timer.
+  * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_EnableDMAReq_CPT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
+}
+
+/**
+  * @brief  Disable the capture 1 DMA request for a given timer.
+  * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_DisableDMAReq_CPT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);
+}
+
+/**
+  * @brief  Indicate whether the capture 1 DMA request is enabled for a given timer.
+  * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_IsEnabledDMAReq_CPT1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the capture 2 DMA request for a given timer.
+  * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_EnableDMAReq_CPT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
+}
+
+/**
+  * @brief  Disable the capture 2 DMA request for a given timer.
+  * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_DisableDMAReq_CPT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);
+}
+
+/**
+  * @brief  Indicate whether the capture 2 DMA request is enabled for a given timer.
+  * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_IsEnabledDMAReq_CPT2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the output 1 set  DMA request for a given timer.
+  * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_EnableDMAReq_SET1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
+}
+
+/**
+  * @brief  Disable the output 1 set  DMA request for a given timer.
+  * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_DisableDMAReq_SET1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);
+}
+
+/**
+  * @brief  Indicate whether the output 1 set  DMA request is enabled for a given timer.
+  * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_IsEnabledDMAReq_SET1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the output 1 reset  DMA request for a given timer.
+  * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_EnableDMAReq_RST1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
+}
+
+/**
+  * @brief  Disable the output 1 reset  DMA request for a given timer.
+  * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_DisableDMAReq_RST1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);
+}
+
+/**
+  * @brief  Indicate whether the output 1 reset interrupt is enabled for a given timer.
+  * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_IsEnabledDMAReq_RST1
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the output 2 set  DMA request for a given timer.
+  * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_EnableDMAReq_SET2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
+}
+
+/**
+  * @brief  Disable the output 2 set  DMA request for a given timer.
+  * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_DisableDMAReq_SET2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);
+}
+
+/**
+  * @brief  Indicate whether the output 2 set  DMA request is enabled for a given timer.
+  * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_IsEnabledDMAReq_SET2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the output 2 reset  DMA request for a given timer.
+  * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_EnableDMAReq_RST2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
+}
+
+/**
+  * @brief  Disable the output 2 reset  DMA request for a given timer.
+  * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_DisableDMAReq_RST2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);
+}
+
+/**
+  * @brief  Indicate whether the output 2 reset  DMA request is enabled for a given timer.
+  * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_IsEnabledDMAReq_RST2
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the reset/roll-over DMA request for a given timer.
+  * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_EnableDMAReq_RST
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
+}
+
+/**
+  * @brief  Disable the reset/roll-over DMA request for a given timer.
+  * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_DisableDMAReq_RST
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);
+}
+
+/**
+  * @brief  Indicate whether the reset/roll-over DMA request is enabled for a given timer.
+  * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_IsEnabledDMAReq_RST
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the delayed protection DMA request for a given timer.
+  * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_EnableDMAReq_DLYPRT
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
+}
+
+/**
+  * @brief  Disable the delayed protection DMA request for a given timer.
+  * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_DisableDMAReq_DLYPRT
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval None
+  */
+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                     REG_OFFSET_TAB_TIMER[iTimer]));
+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);
+}
+
+/**
+  * @brief  Indicate whether the delayed protection DMA request is enabled for a given timer.
+  * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_IsEnabledDMAReq_DLYPRT
+  * @param  HRTIMx High Resolution Timer instance
+  * @param  Timer This parameter can be one of the following values:
+  *         @arg @ref LL_HRTIM_TIMER_A
+  *         @arg @ref LL_HRTIM_TIMER_B
+  *         @arg @ref LL_HRTIM_TIMER_C
+  *         @arg @ref LL_HRTIM_TIMER_D
+  *         @arg @ref LL_HRTIM_TIMER_E
+  *         @arg @ref LL_HRTIM_TIMER_F
+  * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(const HRTIM_TypeDef *HRTIMx, uint32_t Timer)
+{
+  uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);
+  const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +
+                                                           REG_OFFSET_TAB_TIMER[iTimer]));
+
+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef *HRTIMx);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HRTIM1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_HRTIM_H */
+
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h
new file mode 100644
index 0000000..0c9a894
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_lpuart.h
@@ -0,0 +1,2658 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_lpuart.h
+  * @author  MCD Application Team
+  * @brief   Header file of LPUART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_LPUART_H
+#define STM32G4xx_LL_LPUART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (LPUART1)
+
+/** @defgroup LPUART_LL LPUART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables
+  * @{
+  */
+/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */
+static const uint16_t LPUART_PRESCALER_TAB[] =
+{
+  (uint16_t)1,
+  (uint16_t)2,
+  (uint16_t)4,
+  (uint16_t)6,
+  (uint16_t)8,
+  (uint16_t)10,
+  (uint16_t)12,
+  (uint16_t)16,
+  (uint16_t)32,
+  (uint16_t)64,
+  (uint16_t)128,
+  (uint16_t)256
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants
+  * @{
+  */
+/* Defines used in Baud Rate related macros and corresponding register setting computation */
+#define LPUART_LPUARTDIV_FREQ_MUL     256U
+#define LPUART_BRR_MASK               0x000FFFFFU
+#define LPUART_BRR_MIN_VALUE          0x00000300U
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL LPUART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
+                                           This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetPrescaler().*/
+
+  uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref LPUART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_LPUART_SetHWFlowCtrl().*/
+
+} LL_LPUART_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_WriteReg function
+  * @{
+  */
+#define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error clear flag */
+#define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error clear flag */
+#define LL_LPUART_ICR_NCF                  USART_ICR_NECF                /*!< Noise error detected clear flag */
+#define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error clear flag */
+#define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected clear flag */
+#define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete clear flag */
+#define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS clear flag */
+#define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match clear flag */
+#define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_LPUART_ReadReg function
+  * @{
+  */
+#define LL_LPUART_ISR_PE               USART_ISR_PE         /*!< Parity error flag */
+#define LL_LPUART_ISR_FE               USART_ISR_FE         /*!< Framing error flag */
+#define LL_LPUART_ISR_NE               USART_ISR_NE         /*!< Noise detected flag */
+#define LL_LPUART_ISR_ORE              USART_ISR_ORE        /*!< Overrun error flag */
+#define LL_LPUART_ISR_IDLE             USART_ISR_IDLE       /*!< Idle line detected flag */
+#define LL_LPUART_ISR_RXNE_RXFNE       USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */
+#define LL_LPUART_ISR_TC               USART_ISR_TC         /*!< Transmission complete flag */
+#define LL_LPUART_ISR_TXE_TXFNF        USART_ISR_TXE_TXFNF  /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_LPUART_ISR_CTSIF            USART_ISR_CTSIF      /*!< CTS interrupt flag */
+#define LL_LPUART_ISR_CTS              USART_ISR_CTS        /*!< CTS flag */
+#define LL_LPUART_ISR_BUSY             USART_ISR_BUSY       /*!< Busy flag */
+#define LL_LPUART_ISR_CMF              USART_ISR_CMF        /*!< Character match flag */
+#define LL_LPUART_ISR_SBKF             USART_ISR_SBKF       /*!< Send break flag */
+#define LL_LPUART_ISR_RWU              USART_ISR_RWU        /*!< Receiver wakeup from Mute mode flag */
+#define LL_LPUART_ISR_WUF              USART_ISR_WUF        /*!< Wakeup from Stop mode flag */
+#define LL_LPUART_ISR_TEACK            USART_ISR_TEACK      /*!< Transmit enable acknowledge flag */
+#define LL_LPUART_ISR_REACK            USART_ISR_REACK      /*!< Receive enable acknowledge flag */
+#define LL_LPUART_ISR_TXFE             USART_ISR_TXFE       /*!< TX FIFO empty flag */
+#define LL_LPUART_ISR_RXFF             USART_ISR_RXFF       /*!< RX FIFO full flag */
+#define LL_LPUART_ISR_RXFT             USART_ISR_RXFT       /*!< RX FIFO threshold flag */
+#define LL_LPUART_ISR_TXFT             USART_ISR_TXFT       /*!< TX FIFO threshold flag */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions
+  * @{
+  */
+#define LL_LPUART_CR1_IDLEIE         USART_CR1_IDLEIE         /*!< IDLE interrupt enable */
+#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty
+                                                                   interrupt enable */
+#define LL_LPUART_CR1_TCIE           USART_CR1_TCIE           /*!< Transmission complete interrupt enable */
+#define LL_LPUART_CR1_TXEIE_TXFNFIE  USART_CR1_TXEIE_TXFNFIE  /*!< Transmit data register empty and TX FIFO
+                                                                   not full interrupt enable */
+#define LL_LPUART_CR1_PEIE           USART_CR1_PEIE           /*!< Parity error */
+#define LL_LPUART_CR1_CMIE           USART_CR1_CMIE           /*!< Character match interrupt enable */
+#define LL_LPUART_CR1_TXFEIE         USART_CR1_TXFEIE         /*!< TX FIFO empty interrupt enable */
+#define LL_LPUART_CR1_RXFFIE         USART_CR1_RXFFIE         /*!< RX FIFO full interrupt enable */
+#define LL_LPUART_CR3_EIE            USART_CR3_EIE            /*!< Error interrupt enable */
+#define LL_LPUART_CR3_CTSIE          USART_CR3_CTSIE          /*!< CTS interrupt enable */
+#define LL_LPUART_CR3_WUFIE          USART_CR3_WUFIE          /*!< Wakeup from Stop mode interrupt enable */
+#define LL_LPUART_CR3_TXFTIE         USART_CR3_TXFTIE         /*!< TX FIFO threshold interrupt enable */
+#define LL_LPUART_CR3_RXFTIE         USART_CR3_RXFTIE         /*!< RX FIFO threshold interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+  * @{
+  */
+#define LL_LPUART_FIFOTHRESHOLD_1_8        0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_4        0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_1_2        0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_3_4        0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_7_8        0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_LPUART_FIFOTHRESHOLD_8_8        0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DIRECTION Direction
+  * @{
+  */
+#define LL_LPUART_DIRECTION_NONE  0x00000000U                  /*!< Transmitter and Receiver are disabled           */
+#define LL_LPUART_DIRECTION_RX    USART_CR1_RE                 /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_LPUART_DIRECTION_TX    USART_CR1_TE                 /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled            */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_LPUART_PARITY_NONE 0x00000000U                    /*!< Parity control disabled                            */
+#define LL_LPUART_PARITY_EVEN USART_CR1_PCE                  /*!< Parity control enabled and Even Parity is selected */
+#define LL_LPUART_PARITY_ODD  (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_LPUART_WAKEUP_IDLELINE    0x00000000U    /*!<  LPUART wake up from Mute mode on Idle Line    */
+#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!<  LPUART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_8B 0x00000000U  /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler
+  * @{
+  */
+#define LL_LPUART_PRESCALER_DIV1   0x00000000U                    /*!< Input clock not divided   */
+#define LL_LPUART_PRESCALER_DIV2   (USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 2  */
+#define LL_LPUART_PRESCALER_DIV4   (USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 4  */
+#define LL_LPUART_PRESCALER_DIV6   (USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 6  */
+#define LL_LPUART_PRESCALER_DIV8   (USART_PRESC_PRESCALER_2)      /*!< Input clock divided by 8  */
+#define LL_LPUART_PRESCALER_DIV10  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 10 */
+#define LL_LPUART_PRESCALER_DIV12  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 12 */
+#define LL_LPUART_PRESCALER_DIV16  (USART_PRESC_PRESCALER_2 |\
+                                    USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 16 */
+#define LL_LPUART_PRESCALER_DIV32  (USART_PRESC_PRESCALER_3)      /*!< Input clock divided by 32 */
+#define LL_LPUART_PRESCALER_DIV64  (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 64 */
+#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_1)      /*!< Input clock divided by 128 */
+#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\
+                                    USART_PRESC_PRESCALER_1 |\
+                                    USART_PRESC_PRESCALER_0)      /*!< Input clock divided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_LPUART_STOPBITS_1         0x00000000U             /*!< 1 stop bit */
+#define LL_LPUART_STOPBITS_2         USART_CR2_STOP_1        /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_LPUART_TXRX_STANDARD      0x00000000U        /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_LPUART_TXRX_SWAPPED       (USART_CR2_SWAP)   /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_RXPIN_LEVEL_STANDARD   0x00000000U       /*!< RX pin signal works using the standard logic levels */
+#define LL_LPUART_RXPIN_LEVEL_INVERTED   (USART_CR2_RXINV) /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_LPUART_TXPIN_LEVEL_STANDARD  0x00000000U       /*!< TX pin signal works using the standard logic levels */
+#define LL_LPUART_TXPIN_LEVEL_INVERTED  (USART_CR2_TXINV) /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U       /*!< Logical data from the data register are send/received
+                                                               in positive/direct logic. (1=H, 0=L)                  */
+#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received
+                                                               in negative/inverse logic. (1=L, 0=H).
+                                                               The parity bit is also inverted.                      */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U        /*!< data is transmitted/received with data bit 0 first,
+                                                            following the start bit */
+#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first,
+                                                            following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U     /*!< 4-bit address detection method selected */
+#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_LPUART_HWCONTROL_NONE    0x00000000U                       /*!< CTS and RTS hardware flow control disabled */
+#define LL_LPUART_HWCONTROL_RTS     USART_CR3_RTSE                    /*!< RTS output enabled, data is only requested
+                                                                           when there is space in the receive buffer  */
+#define LL_LPUART_HWCONTROL_CTS     USART_CR3_CTSE                    /*!< CTS mode enabled, data is only transmitted
+                                                                           when the nCTS input is asserted (tied to 0)*/
+#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled  */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_LPUART_WAKEUP_ON_ADDRESS   0x00000000U                          /*!< Wake up active on address match */
+#define LL_LPUART_WAKEUP_ON_STARTBIT  USART_CR3_WUS_1                      /*!< Wake up active on Start bit detection */
+#define LL_LPUART_WAKEUP_ON_RXNE      (USART_CR3_WUS_0 | USART_CR3_WUS_1)  /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_LPUART_DE_POLARITY_HIGH         0x00000000U    /*!< DE signal is active high */
+#define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP  /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U    /*!< Get address of data register used for transmission */
+#define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U    /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in LPUART register
+  * @param  __INSTANCE__ LPUART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros
+  * @{
+  */
+
+/**
+  * @brief  Compute LPUARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate (20-bit value of LPUARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud Rate value to achieve
+  * @retval LPUARTDIV value to be used for BRR register filling
+  */
+#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\
+  ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\
+      * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions
+  * @{
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  LPUART Enable
+  * @rmtoll CR1          UE            LL_LPUART_Enable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  LPUART Disable
+  * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the LPUART is kept, but all the status
+  *         flags, in the LPUARTx_ISR are set to their default values.
+  * @note   In order to go into low-power mode without generating errors on the line,
+  *         the TE bit must be reset before and the software must wait
+  *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.
+  *         The DMA requests are also reset when UE = 0 so the DMA channel must
+  *         be disabled before resetting the UE bit.
+  * @rmtoll CR1          UE            LL_LPUART_Disable
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled
+  * @rmtoll CR1          UE            LL_LPUART_IsEnabled
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  FIFO Mode Enable
+  * @rmtoll CR1          FIFOEN        LL_LPUART_EnableFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  FIFO Mode Disable
+  * @rmtoll CR1          FIFOEN        LL_LPUART_DisableFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  Indicate if FIFO Mode is enabled
+  * @rmtoll CR1          FIFOEN        LL_LPUART_IsEnabledFIFO
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure TX FIFO Threshold
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_SetTXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return TX FIFO Threshold Configuration
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_GetTXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure RX FIFO Threshold
+  * @rmtoll CR3          RXFTCFG       LL_LPUART_SetRXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return RX FIFO Threshold Configuration
+  * @rmtoll CR3          RXFTCFG       LL_LPUART_GetRXFIFOThreshold
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure TX and RX FIFOs Threshold
+  * @rmtoll CR3          TXFTCFG       LL_LPUART_ConfigFIFOsThreshold\n
+  *         CR3          RXFTCFG       LL_LPUART_ConfigFIFOsThreshold
+  * @param  LPUARTx LPUART Instance
+  * @param  TXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @param  RXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \
+                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+  * @brief  LPUART enabled in STOP Mode
+  * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that
+  *         LPUART clock selection is HSI or LSE in RCC.
+  * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  LPUART disabled in STOP Mode
+  * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode
+  * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if LPUART is enabled in STOP Mode
+  *         (able to wake up MCU from Stop mode or not)
+  * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n
+  *         CR1          TE            LL_LPUART_SetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n
+  *         CR1          TE            LL_LPUART_GetTransferDirection
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DIRECTION_NONE
+  *         @arg @ref LL_LPUART_DIRECTION_RX
+  *         @arg @ref LL_LPUART_DIRECTION_TX
+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled)
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_LPUART_SetParity\n
+  *         CR1          PCE           LL_LPUART_SetParity
+  * @param  LPUARTx LPUART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_LPUART_GetParity\n
+  *         CR1          PCE           LL_LPUART_GetParity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE
+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_SetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M             LL_LPUART_GetDataWidth
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
+  * @rmtoll PRESC        PRESCALER     LL_LPUART_SetPrescaler
+  * @param  LPUARTx LPUART Instance
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
+  * @rmtoll PRESC        PRESCALER     LL_LPUART_GetPrescaler
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function
+  *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n
+  *         CR1          PCE           LL_LPUART_ConfigCharacter\n
+  *         CR1          M             LL_LPUART_ConfigCharacter\n
+  *         CR2          STOP          LL_LPUART_ConfigCharacter
+  * @param  LPUARTx LPUART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DATAWIDTH_7B
+  *         @arg @ref LL_LPUART_DATAWIDTH_8B
+  *         @arg @ref LL_LPUART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PARITY_NONE
+  *         @arg @ref LL_LPUART_PARITY_EVEN
+  *         @arg @ref LL_LPUART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_STOPBITS_1
+  *         @arg @ref LL_LPUART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,
+                                               uint32_t StopBits)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXRX_STANDARD
+  *         @arg @ref LL_LPUART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  *
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST
+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Set Address of the LPUART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the LPUART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress
+  * @param  LPUARTx LPUART Instance
+  * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_HWCONTROL_NONE
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS
+  *         @arg @ref LL_LPUART_HWCONTROL_CTS
+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.
+  *
+  * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock and expected Baud Rate values
+  * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid
+  *         (Baud rate value != 0).
+  * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,
+  *         a care should be taken when generating high baud rates using high PeriphClk
+  *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].
+  * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                           uint32_t BaudRate)
+{
+  if (BaudRate != 0U)
+  {
+    LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate
+  * @param  LPUARTx LPUART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_PRESCALER_DIV1
+  *         @arg @ref LL_LPUART_PRESCALER_DIV2
+  *         @arg @ref LL_LPUART_PRESCALER_DIV4
+  *         @arg @ref LL_LPUART_PRESCALER_DIV6
+  *         @arg @ref LL_LPUART_PRESCALER_DIV8
+  *         @arg @ref LL_LPUART_PRESCALER_DIV10
+  *         @arg @ref LL_LPUART_PRESCALER_DIV12
+  *         @arg @ref LL_LPUART_PRESCALER_DIV16
+  *         @arg @ref LL_LPUART_PRESCALER_DIV32
+  *         @arg @ref LL_LPUART_PRESCALER_DIV64
+  *         @arg @ref LL_LPUART_PRESCALER_DIV128
+  *         @arg @ref LL_LPUART_PRESCALER_DIV256
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk,
+                                               uint32_t PrescalerValue)
+{
+  uint32_t lpuartdiv;
+  uint32_t brrresult;
+  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));
+
+  lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;
+
+  if (lpuartdiv >= LPUART_BRR_MIN_VALUE)
+  {
+    brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);
+  }
+  else
+  {
+    brrresult = 0x0UL;
+  }
+
+  return (brrresult);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : c
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)
+{
+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime
+  * @param  LPUARTx LPUART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)
+{
+  MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity
+  * @param  LPUARTx LPUART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH
+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx)
+{
+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the LPUART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not
+  * @rmtoll ISR          RXNE_RXFNE    LL_LPUART_IsActiveFlag_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not
+  * @rmtoll ISR          TXE_TXFNF     LL_LPUART_IsActiveFlag_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS interrupt Flag is set or not
+  * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS Flag is set or not
+  * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not
+  * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Empty Flag is set or not
+  * @rmtoll ISR          TXFE          LL_LPUART_IsActiveFlag_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Full Flag is set or not
+  * @rmtoll ISR          RXFF          LL_LPUART_IsActiveFlag_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Threshold Flag is set or not
+  * @rmtoll ISR          TXFT          LL_LPUART_IsActiveFlag_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Threshold Flag is set or not
+  * @rmtoll ISR          RXFT          LL_LPUART_IsActiveFlag_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise detected Flag
+  * @rmtoll ICR          NECF          LL_LPUART_ClearFlag_NE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)
+{
+  WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_EnableIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_EnableIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Empty Interrupt
+  * @rmtoll CR1          TXFEIE        LL_LPUART_EnableIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_LPUART_EnableIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Threshold Interrupt
+  * @rmtoll CR3          TXFTIE        LL_LPUART_EnableIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Threshold Interrupt
+  * @rmtoll CR3          RXFTIE        LL_LPUART_EnableIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_DisableIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_LPUART_DisableIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Empty Interrupt
+  * @rmtoll CR1          TXFEIE        LL_LPUART_DisableIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_LPUART_DisableIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).
+  *         - 0: Interrupt is inhibited
+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Threshold Interrupt
+  * @rmtoll CR3          TXFTIE        LL_LPUART_DisableIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Threshold Interrupt
+  * @rmtoll CR3          RXFTIE        LL_LPUART_DisableIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_IsEnabledIT_RXNE_RXFNE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+#define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_IsEnabledIT_TXE_TXFNF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled
+  * @rmtoll CR1          TXFEIE        LL_LPUART_IsEnabledIT_TXFE
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART RX FIFO Full Interrupt is enabled or disabled
+  * @rmtoll CR1          RXFFIE        LL_LPUART_IsEnabledIT_RXFF
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.
+  * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled
+  * @rmtoll CR3          TXFTIE        LL_LPUART_IsEnabledIT_TXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled
+  * @rmtoll CR3          RXFTIE        LL_LPUART_IsEnabledIT_RXFT
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)
+{
+  ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)
+{
+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr
+  * @param  LPUARTx LPUART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx)
+{
+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the LPUART data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr
+  * @param  LPUARTx LPUART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(LPUARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx)
+{
+  return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9
+  * @param  LPUARTx LPUART Instance
+  * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx)
+{
+  return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData8
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)
+{
+  LPUARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData9
+  * @param  LPUARTx LPUART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)
+{
+  LPUARTx->TDR = Value & 0x1FFUL;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup LPUART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put LPUART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data and FIFO flush
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @brief  Request a Transmit data FIFO flush
+  * @note   TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This
+  *         also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register).
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll RQR          TXFRQ         LL_LPUART_RequestTxDataFlush
+  * @param  LPUARTx LPUART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx)
+{
+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx);
+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct);
+void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* LPUART1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_LPUART_H */
+
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h
new file mode 100644
index 0000000..51058c8
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Inc/stm32g4xx_ll_usart.h
@@ -0,0 +1,4399 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_usart.h
+  * @author  MCD Application Team
+  * @brief   Header file of USART LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32G4xx_LL_USART_H
+#define STM32G4xx_LL_USART_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx.h"
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5)
+
+/** @defgroup USART_LL USART
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Variables USART Private Variables
+  * @{
+  */
+/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */
+static const uint32_t USART_PRESCALER_TAB[] =
+{
+  1UL,
+  2UL,
+  4UL,
+  6UL,
+  8UL,
+  10UL,
+  12UL,
+  16UL,
+  32UL,
+  64UL,
+  128UL,
+  256UL
+};
+/**
+  * @}
+  */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup USART_LL_Private_Constants USART Private Constants
+  * @{
+  */
+/**
+  * @}
+  */
+/* Private macros ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_Private_Macros USART Private Macros
+  * @{
+  */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_ES_INIT USART Exported Init structures
+  * @{
+  */
+
+/**
+  * @brief LL USART Init Structure definition
+  */
+typedef struct
+{
+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.
+                                           This parameter can be a value of @ref USART_LL_EC_PRESCALER.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetPrescaler().*/
+
+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetBaudRate().*/
+
+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetDataWidth().*/
+
+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetStopBitsLength().*/
+
+  uint32_t Parity;                    /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetParity().*/
+
+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetTransferDirection().*/
+
+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetHWFlowCtrl().*/
+
+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.
+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.
+
+                                           This feature can be modified afterwards using unitary
+                                           function @ref LL_USART_SetOverSampling().*/
+
+} LL_USART_InitTypeDef;
+
+/**
+  * @brief LL USART Clock Init Structure definition
+  */
+typedef struct
+{
+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.
+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.
+
+                                           USART HW configuration can be modified afterwards using unitary functions
+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.
+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetClockPolarity().
+                                           For more details, refer to description of this function. */
+
+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetClockPhase().
+                                           For more details, refer to description of this function. */
+
+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.
+
+                                           USART HW configuration can be modified afterwards using unitary
+                                           functions @ref LL_USART_SetLastClkPulseOutput().
+                                           For more details, refer to description of this function. */
+
+} LL_USART_ClockInitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Constants USART Exported Constants
+  * @{
+  */
+
+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_WriteReg function
+  * @{
+  */
+#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error clear flag */
+#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error clear flag */
+#define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected clear flag */
+#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error clear flag */
+#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected clear flag */
+#define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty clear flag */
+#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete clear flag */
+#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time clear flag */
+#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection clear flag */
+#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS clear flag */
+#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout clear flag */
+#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block clear flag */
+#define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun clear flag */
+#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match clear flag */
+#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode clear flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines
+  * @brief    Flags defines which can be used with LL_USART_ReadReg function
+  * @{
+  */
+#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */
+#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */
+#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */
+#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */
+#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */
+#define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */
+#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */
+#define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/
+#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */
+#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */
+#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */
+#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */
+#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */
+#define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */
+#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */
+#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */
+#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */
+#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */
+#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */
+#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */
+#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */
+#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */
+#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */
+#define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */
+#define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */
+#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */
+#define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */
+#define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IT IT Defines
+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions
+  * @{
+  */
+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */
+#define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */
+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */
+#define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */
+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */
+#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */
+#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */
+#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */
+#define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */
+#define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */
+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */
+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */
+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */
+#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */
+#define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */
+#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */
+#define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold
+  * @{
+  */
+#define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */
+#define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */
+#define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */
+#define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DIRECTION Communication Direction
+  * @{
+  */
+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */
+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */
+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */
+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PARITY Parity Control
+  * @{
+  */
+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */
+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */
+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP Wakeup
+  * @{
+  */
+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */
+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth
+  * @{
+  */
+#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */
+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling
+  * @{
+  */
+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */
+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EC_CLOCK Clock Signal
+  * @{
+  */
+
+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */
+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */
+/**
+  * @}
+  */
+#endif /*USE_FULL_LL_DRIVER*/
+
+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse
+  * @{
+  */
+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */
+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PHASE Clock Phase
+  * @{
+  */
+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */
+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_POLARITY Clock Polarity
+  * @{
+  */
+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/
+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler
+  * @{
+  */
+#define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not divided   */
+#define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock divided by 2  */
+#define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock divided by 4  */
+#define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 6  */
+#define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock divided by 8  */
+#define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 10 */
+#define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 12 */
+#define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */
+#define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock divided by 32 */
+#define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock divided by 64 */
+#define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock divided by 128 */
+#define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_STOPBITS Stop Bits
+  * @{
+  */
+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */
+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */
+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */
+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap
+  * @{
+  */
+#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */
+#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */
+#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion
+  * @{
+  */
+#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */
+#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion
+  * @{
+  */
+#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */
+#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_BITORDER Bit Order
+  * @{
+  */
+#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */
+#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection
+  * @{
+  */
+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */
+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */
+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */
+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection
+  * @{
+  */
+#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */
+#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control
+  * @{
+  */
+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */
+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */
+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */
+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation
+  * @{
+  */
+#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */
+#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */
+#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power
+  * @{
+  */
+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */
+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length
+  * @{
+  */
+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */
+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity
+  * @{
+  */
+#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */
+#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data
+  * @{
+  */
+#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */
+#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup USART_LL_Exported_Macros USART Exported Macros
+  * @{
+  */
+
+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in USART register
+  * @param  __INSTANCE__ USART Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper
+  * @{
+  */
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case
+  */
+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+  (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\
+    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @brief  Compute USARTDIV value according to Peripheral Clock and
+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)
+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance
+  * @param  __PRESCALER__ This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  __BAUDRATE__ Baud rate value to achieve
+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case
+  */
+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \
+  ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\
+    + ((__BAUDRATE__)/2U))/(__BAUDRATE__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup USART_LL_Exported_Functions USART Exported Functions
+  * @{
+  */
+
+/** @defgroup USART_LL_EF_Configuration Configuration functions
+  * @{
+  */
+
+/**
+  * @brief  USART Enable
+  * @rmtoll CR1          UE            LL_USART_Enable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  USART Disable (all USART prescalers and outputs are disabled)
+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,
+  *         and current operations are discarded. The configuration of the USART is kept, but all the status
+  *         flags, in the USARTx_ISR are set to their default values.
+  * @rmtoll CR1          UE            LL_USART_Disable
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);
+}
+
+/**
+  * @brief  Indicate if USART is enabled
+  * @rmtoll CR1          UE            LL_USART_IsEnabled
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  FIFO Mode Enable
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  FIFO Mode Disable
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);
+}
+
+/**
+  * @brief  Indicate if FIFO Mode is enabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure TX FIFO Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return TX FIFO Threshold Configuration
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure RX FIFO Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @param  Threshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Return RX FIFO Threshold Configuration
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+}
+
+/**
+  * @brief  Configure TX and RX FIFOs Threshold
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n
+  *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold
+  * @param  USARTx USART Instance
+  * @param  TXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @param  RXThreshold This parameter can be one of the following values:
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8
+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) |
+                    (RXThreshold << USART_CR3_RXFTCFG_Pos));
+}
+
+/**
+  * @brief  USART enabled in STOP Mode.
+  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that
+  *         USART clock selection is HSI or LSE in RCC.
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  USART disabled in STOP Mode.
+  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);
+}
+
+/**
+  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)
+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Receiver Disable
+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE);
+}
+
+/**
+  * @brief  Transmitter Enable
+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Transmitter Disable
+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE);
+}
+
+/**
+  * @brief  Configure simultaneously enabled/disabled states
+  *         of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n
+  *         CR1          TE            LL_USART_SetTransferDirection
+  * @param  USARTx USART Instance
+  * @param  TransferDirection This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)
+{
+  ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);
+}
+
+/**
+  * @brief  Return enabled/disabled states of Transmitter and Receiver
+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n
+  *         CR1          TE            LL_USART_GetTransferDirection
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DIRECTION_NONE
+  *         @arg @ref LL_USART_DIRECTION_RX
+  *         @arg @ref LL_USART_DIRECTION_TX
+  *         @arg @ref LL_USART_DIRECTION_TX_RX
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));
+}
+
+/**
+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).
+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.
+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position
+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.
+  * @rmtoll CR1          PS            LL_USART_SetParity\n
+  *         CR1          PCE           LL_USART_SetParity
+  * @param  USARTx USART Instance
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);
+}
+
+/**
+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)
+  * @rmtoll CR1          PS            LL_USART_GetParity\n
+  *         CR1          PCE           LL_USART_GetParity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  */
+__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));
+}
+
+/**
+  * @brief  Set Receiver Wake Up method from Mute mode.
+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @param  Method This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);
+}
+
+/**
+  * @brief  Return Receiver Wake Up method from Mute mode
+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_IDLELINE
+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));
+}
+
+/**
+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n
+  *         CR1          M1            LL_USART_SetDataWidth
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);
+}
+
+/**
+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)
+  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n
+  *         CR1          M1            LL_USART_GetDataWidth
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));
+}
+
+/**
+  * @brief  Allow switch between Mute Mode and Active mode
+  * @rmtoll CR1          MME           LL_USART_EnableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.
+  * @rmtoll CR1          MME           LL_USART_DisableMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME);
+}
+
+/**
+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed
+  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Oversampling to 8-bit or 16-bit mode
+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling
+  * @param  USARTx USART Instance
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);
+}
+
+/**
+  * @brief  Return Oversampling mode
+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  */
+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));
+}
+
+/**
+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @param  LastBitClockPulse This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);
+}
+
+/**
+  * @brief  Retrieve Clock pulse of the last data bit output configuration
+  *         (Last bit Clock pulse output to the SCLK pin or not)
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));
+}
+
+/**
+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase
+  * @param  USARTx USART Instance
+  * @param  ClockPhase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);
+}
+
+/**
+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));
+}
+
+/**
+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity
+  * @param  USARTx USART Instance
+  * @param  ClockPolarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);
+}
+
+/**
+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  */
+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));
+}
+
+/**
+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function
+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function
+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function
+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n
+  *         CR2          CPOL          LL_USART_ConfigClock\n
+  *         CR2          LBCL          LL_USART_ConfigClock
+  * @param  USARTx USART Instance
+  * @param  Phase This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PHASE_1EDGE
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_POLARITY_LOW
+  *         @arg @ref LL_USART_POLARITY_HIGH
+  * @param  LBCPOutput This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT
+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);
+}
+
+/**
+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  */
+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));
+}
+
+/**
+  * @brief  Enable Clock output on SCLK pin
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Disable Clock output on SCLK pin
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Indicate if Clock output on SCLK pin is enabled
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength
+  * @param  USARTx USART Instance
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Retrieve the length of the stop bits
+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  */
+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));
+}
+
+/**
+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function
+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function
+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function
+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n
+  *         CR1          PCE           LL_USART_ConfigCharacter\n
+  *         CR1          M0            LL_USART_ConfigCharacter\n
+  *         CR1          M1            LL_USART_ConfigCharacter\n
+  *         CR2          STOP          LL_USART_ConfigCharacter
+  * @param  USARTx USART Instance
+  * @param  DataWidth This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DATAWIDTH_7B
+  *         @arg @ref LL_USART_DATAWIDTH_8B
+  *         @arg @ref LL_USART_DATAWIDTH_9B
+  * @param  Parity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PARITY_NONE
+  *         @arg @ref LL_USART_PARITY_EVEN
+  *         @arg @ref LL_USART_PARITY_ODD
+  * @param  StopBits This parameter can be one of the following values:
+  *         @arg @ref LL_USART_STOPBITS_0_5
+  *         @arg @ref LL_USART_STOPBITS_1
+  *         @arg @ref LL_USART_STOPBITS_1_5
+  *         @arg @ref LL_USART_STOPBITS_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,
+                                              uint32_t StopBits)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);
+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);
+}
+
+/**
+  * @brief  Configure TX/RX pins swapping setting.
+  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap
+  * @param  USARTx USART Instance
+  * @param  SwapConfig This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);
+}
+
+/**
+  * @brief  Retrieve TX/RX pins swapping configuration.
+  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXRX_STANDARD
+  *         @arg @ref LL_USART_TXRX_SWAPPED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));
+}
+
+/**
+  * @brief  Configure RX pin active level logic
+  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve RX pin active level logic configuration
+  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));
+}
+
+/**
+  * @brief  Configure TX pin active level logic
+  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel
+  * @param  USARTx USART Instance
+  * @param  PinInvMethod This parameter can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);
+}
+
+/**
+  * @brief  Retrieve TX pin active level logic configuration
+  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD
+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));
+}
+
+/**
+  * @brief  Configure Binary data logic.
+  * @note   Allow to define how Logical data from the data register are send/received :
+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)
+  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @param  DataLogic This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);
+}
+
+/**
+  * @brief  Retrieve Binary data configuration
+  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE
+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));
+}
+
+/**
+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @param  BitOrder This parameter can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);
+}
+
+/**
+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)
+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.
+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.
+  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_BITORDER_LSBFIRST
+  *         @arg @ref LL_USART_BITORDER_MSBFIRST
+  */
+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));
+}
+
+/**
+  * @brief  Enable Auto Baud-Rate Detection
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Disable Auto Baud-Rate Detection
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);
+}
+
+/**
+  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Auto Baud-Rate mode bits
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @param  AutoBaudRateMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);
+}
+
+/**
+  * @brief  Return Auto Baud-Rate mode
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
+  */
+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
+}
+
+/**
+  * @brief  Enable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Disable Receiver Timeout
+  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);
+}
+
+/**
+  * @brief  Indicate if Receiver Timeout feature is enabled
+  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Address of the USART node.
+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with address mark detection.
+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.
+  *         (b7-b4 should be set to 0)
+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.
+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,
+  *         for wake up with 7-bit address mark detection.
+  *         The MSB of the character sent by the transmitter should be equal to 1.
+  *         It may also be used for character detection during normal reception,
+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).
+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]
+  *         value and CMF flag is set on match)
+  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n
+  *         CR2          ADDM7         LL_USART_ConfigNodeAddress
+  * @param  USARTx USART Instance
+  * @param  AddressLen This parameter can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  * @param  NodeAddress 4 or 7 bit Address of the USART node.
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,
+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));
+}
+
+/**
+  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.
+  * @note   If 4-bit Address Detection is selected in ADDM7,
+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)
+  *         If 7-bit Address Detection is selected in ADDM7,
+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)
+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress
+  * @param  USARTx USART Instance
+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);
+}
+
+/**
+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)
+  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B
+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));
+}
+
+/**
+  * @brief  Enable RTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Disable RTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);
+}
+
+/**
+  * @brief  Enable CTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Disable CTS HW Flow Control
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);
+}
+
+/**
+  * @brief  Configure HW Flow Control mode (both CTS and RTS)
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @param  HardwareFlowControl This parameter can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);
+}
+
+/**
+  * @brief  Return HW Flow Control configuration (both CTS and RTS)
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n
+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_HWCONTROL_NONE
+  *         @arg @ref LL_USART_HWCONTROL_RTS
+  *         @arg @ref LL_USART_HWCONTROL_CTS
+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS
+  */
+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));
+}
+
+/**
+  * @brief  Enable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Disable One bit sampling method
+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);
+}
+
+/**
+  * @brief  Indicate if One bit sampling method is enabled
+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Disable Overrun detection
+  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);
+}
+
+/**
+  * @brief  Indicate if Overrun detection is enabled
+  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_SetWKUPType
+  * @param  USARTx USART Instance
+  * @param  Type This parameter can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);
+}
+
+/**
+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUS           LL_USART_GetWKUPType
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS
+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT
+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));
+}
+
+/**
+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.
+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)
+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values
+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid
+  *         (Baud rate value != 0)
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @param  BaudRate Baud Rate
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                          uint32_t OverSampling,
+                                          uint32_t BaudRate)
+{
+  uint32_t usartdiv;
+  uint32_t brrtemp;
+
+  if (PrescalerValue > LL_USART_PRESCALER_DIV256)
+  {
+    /* Do not overstep the size of USART_PRESCALER_TAB */
+  }
+  else if (BaudRate == 0U)
+  {
+    /* Can Not divide per 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+    brrtemp = usartdiv & 0xFFF0U;
+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+    USARTx->BRR = brrtemp;
+  }
+  else
+  {
+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));
+  }
+}
+
+/**
+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register
+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values
+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.
+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.
+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate
+  * @param  USARTx USART Instance
+  * @param  PeriphClk Peripheral Clock
+  * @param  PrescalerValue This parameter can be one of the following values:
+  *         @arg @ref LL_USART_PRESCALER_DIV1
+  *         @arg @ref LL_USART_PRESCALER_DIV2
+  *         @arg @ref LL_USART_PRESCALER_DIV4
+  *         @arg @ref LL_USART_PRESCALER_DIV6
+  *         @arg @ref LL_USART_PRESCALER_DIV8
+  *         @arg @ref LL_USART_PRESCALER_DIV10
+  *         @arg @ref LL_USART_PRESCALER_DIV12
+  *         @arg @ref LL_USART_PRESCALER_DIV16
+  *         @arg @ref LL_USART_PRESCALER_DIV32
+  *         @arg @ref LL_USART_PRESCALER_DIV64
+  *         @arg @ref LL_USART_PRESCALER_DIV128
+  *         @arg @ref LL_USART_PRESCALER_DIV256
+  * @param  OverSampling This parameter can be one of the following values:
+  *         @arg @ref LL_USART_OVERSAMPLING_16
+  *         @arg @ref LL_USART_OVERSAMPLING_8
+  * @retval Baud Rate
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,
+                                              uint32_t OverSampling)
+{
+  uint32_t usartdiv;
+  uint32_t brrresult = 0x0U;
+  uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));
+
+  usartdiv = USARTx->BRR;
+
+  if (usartdiv == 0U)
+  {
+    /* Do not perform a division by 0 */
+  }
+  else if (OverSampling == LL_USART_OVERSAMPLING_8)
+  {
+    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;
+    if (usartdiv != 0U)
+    {
+      brrresult = (periphclkpresc * 2U) / usartdiv;
+    }
+  }
+  else
+  {
+    if ((usartdiv & 0xFFFFU) != 0U)
+    {
+      brrresult = periphclkpresc / usartdiv;
+    }
+  }
+  return (brrresult);
+}
+
+/**
+  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout
+  * @param  USARTx USART Instance
+  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);
+}
+
+/**
+  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)
+  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));
+}
+
+/**
+  * @brief  Set Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength
+  * @param  USARTx USART Instance
+  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)
+{
+  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @brief  Get Block Length value in reception
+  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature
+  * @{
+  */
+
+/**
+  * @brief  Enable IrDA mode
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_EnableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Disable IrDA mode
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_DisableIrda
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Indicate if IrDA mode is enabled
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Configure IrDA Power Mode (Normal or Low Power)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @param  PowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_IRDA_POWER_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);
+}
+
+/**
+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL
+  *         @arg @ref LL_USART_PHASE_2EDGE
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));
+}
+
+/**
+  * @brief  Set Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Irda prescaler value, used for dividing the USART clock source
+  *         to achieve the Irda Low Power frequency (8 bits value)
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler
+  * @param  USARTx USART Instance
+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Smartcard NACK transmission
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Disable Smartcard NACK transmission
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);
+}
+
+/**
+  * @brief  Indicate if Smartcard NACK transmission is enabled
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable Smartcard mode
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Disable Smartcard mode
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Indicate if Smartcard mode is enabled
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.
+  *         In transmission mode, it specifies the number of automatic retransmission retries, before
+  *         generating a transmission error (FE bit set).
+  *         In reception mode, it specifies the number or erroneous reception trials, before generating a
+  *         reception error (RXNE and PE bits set)
+  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount
+  * @param  USARTx USART Instance
+  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);
+}
+
+/**
+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue);
+}
+
+/**
+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock
+  *         source to provide the SMARTCARD Clock (5 bits value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler
+  * @param  USARTx USART Instance
+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));
+}
+
+/**
+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)
+{
+  MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));
+}
+
+/**
+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods
+  *         (GT[7:0] bits : Guard time value)
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime
+  * @param  USARTx USART Instance
+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)
+  */
+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature
+  * @{
+  */
+
+/**
+  * @brief  Enable Single Wire Half-Duplex mode
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Disable Single Wire Half-Duplex mode
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature
+  * @{
+  */
+/**
+  * @brief  Enable SPI Synchronous Slave mode
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Disable SPI Synchronous Slave mode
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);
+}
+
+/**
+  * @brief  Indicate if  SPI Synchronous Slave mode is enabled
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable SPI Slave Selection using NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave Selection depends on NSS input pin
+  *         (The slave is selected when NSS is low and deselected when NSS is high).
+  * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Disable SPI Slave Selection using NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @note   SPI Slave will be always selected and NSS input pin will be ignored.
+  * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);
+}
+
+/**
+  * @brief  Indicate if  SPI Slave Selection depends on NSS input pin
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature
+  * @{
+  */
+
+/**
+  * @brief  Set LIN Break Detection Length
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @param  LINBDLength This parameter can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)
+{
+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);
+}
+
+/**
+  * @brief  Return LIN Break Detection Length
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B
+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B
+  */
+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));
+}
+
+/**
+  * @brief  Enable LIN mode
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Disable LIN mode
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Indicate if LIN mode is enabled
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature
+  * @{
+  */
+
+/**
+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Return DEDT (Driver Enable De-Assertion Time)
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);
+}
+
+/**
+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @param  Time Value between Min_Data=0 and Max_Data=31
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)
+{
+  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Return DEAT (Driver Enable Assertion Time)
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime
+  * @param  USARTx USART Instance
+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);
+}
+
+/**
+  * @brief  Enable Driver Enable (DE) Mode
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_EnableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Disable Driver Enable (DE) Mode
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_DisableDEMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);
+}
+
+/**
+  * @brief  Indicate if Driver Enable (DE) Mode is enabled
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Select Driver Enable Polarity
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @param  Polarity This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)
+{
+  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);
+}
+
+/**
+  * @brief  Return Driver Enable Polarity
+  * @note   Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not
+  *         Driver Enable feature is supported by the USARTx instance.
+  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity
+  * @param  USARTx USART Instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_USART_DE_POLARITY_HIGH
+  *         @arg @ref LL_USART_DE_POLARITY_LOW
+  */
+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx)
+{
+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services
+  * @{
+  */
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)
+  * @note   In UART mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Asynchronous Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n
+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)
+{
+  /* In Asynchronous mode, the following bits must be kept cleared:
+  - LINEN, CLKEN bits in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode
+  * @note   In Synchronous mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the USART in Synchronous mode.
+  * @note   Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not
+  *         Synchronous mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  * @note   Other remaining configurations items related to Synchronous Mode
+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n
+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n
+  *         CR3          IREN          LL_USART_ConfigSyncMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSyncMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)
+{
+  /* In Synchronous mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));
+  /* set the UART/USART in Synchronous mode */
+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode
+  * @note   In LIN mode, the following bits must be kept cleared:
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also set the UART/USART in LIN mode.
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function
+  * @note   Other remaining configurations items related to LIN Mode
+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n
+  *         CR2          STOP          LL_USART_ConfigLINMode\n
+  *         CR2          LINEN         LL_USART_ConfigLINMode\n
+  *         CR3          IREN          LL_USART_ConfigLINMode\n
+  *         CR3          SCEN          LL_USART_ConfigLINMode\n
+  *         CR3          HDSEL         LL_USART_ConfigLINMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)
+{
+  /* In LIN mode, the following bits must be kept cleared:
+  - STOP and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* Set the UART/USART in LIN mode */
+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode
+  * @note   In Half Duplex mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *         This function also sets the UART/USART in Half Duplex mode.
+  * @note   Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not
+  *         Half-Duplex mode is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function
+  * @note   Other remaining configurations items related to Half Duplex Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n
+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)
+{
+  /* In Half Duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));
+  /* set the UART/USART in Half Duplex mode */
+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode
+  * @note   In Smartcard mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also configures Stop bits to 1.5 bits and
+  *         sets the USART in Smartcard mode (SCEN bit).
+  *         Clock Output is also enabled (CLKEN).
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function
+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function
+  * @note   Other remaining configurations items related to Smartcard Mode
+  *         (as Baud Rate, Word length, Parity, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n
+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n
+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n
+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n
+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)
+{
+  /* In Smartcard mode, the following bits must be kept cleared:
+  - LINEN bit in the USART_CR2 register,
+  - IREN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
+  /* Configure Stop bits to 1.5 bits */
+  /* Synchronous mode is activated by default */
+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));
+  /* set the UART/USART in Smartcard mode */
+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode
+  * @note   In IRDA mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - STOP and CLKEN bits in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  *         This function also sets the UART/USART in IRDA mode (IREN bit).
+  * @note   Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not
+  *         IrDA feature is supported by the USARTx instance.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function
+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function
+  * @note   Other remaining configurations items related to Irda Mode
+  *         (as Baud Rate, Word length, Power mode, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n
+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n
+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n
+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n
+  *         CR3          IREN          LL_USART_ConfigIrdaMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)
+{
+  /* In IRDA mode, the following bits must be kept cleared:
+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,
+  - SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
+  /* set the UART/USART in IRDA mode */
+  SET_BIT(USARTx->CR3, USART_CR3_IREN);
+}
+
+/**
+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode
+  *         (several USARTs connected in a network, one of the USARTs can be the master,
+  *         its TX output connected to the RX inputs of the other slaves USARTs).
+  * @note   In MultiProcessor mode, the following bits must be kept cleared:
+  *           - LINEN bit in the USART_CR2 register,
+  *           - CLKEN bit in the USART_CR2 register,
+  *           - SCEN bit in the USART_CR3 register,
+  *           - IREN bit in the USART_CR3 register,
+  *           - HDSEL bit in the USART_CR3 register.
+  * @note   Call of this function is equivalent to following function call sequence :
+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function
+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function
+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function
+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function
+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function
+  * @note   Other remaining configurations items related to Multi processor Mode
+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using
+  *         dedicated functions
+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n
+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n
+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)
+{
+  /* In Multi Processor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.
+  */
+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management
+  * @{
+  */
+
+/**
+  * @brief  Check if the USART Parity Error Flag is set or not
+  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Framing Error Flag is set or not
+  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Noise error detected Flag is set or not
+  * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART OverRun Error Flag is set or not
+  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART IDLE line detected Flag is set or not
+  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Flag is set or not
+  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Flag is set or not
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS interrupt Flag is set or not
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Flag is set or not
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Time Out Flag is set or not
+  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Flag is set or not
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the SPI Slave Underrun error flag is set or not
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Auto-Baud Rate Flag is set or not
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Busy Flag is set or not
+  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Flag is set or not
+  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Send Break Flag is set or not
+  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not
+  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from stop mode Flag is set or not
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not
+  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not
+  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Threshold Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Threshold Flag is set or not
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear Parity Error Flag
+  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_PECF);
+}
+
+/**
+  * @brief  Clear Framing Error Flag
+  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_FECF);
+}
+
+/**
+  * @brief  Clear Noise Error detected Flag
+  * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_NECF);
+}
+
+/**
+  * @brief  Clear OverRun Error Flag
+  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);
+}
+
+/**
+  * @brief  Clear IDLE line detected Flag
+  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);
+}
+
+/**
+  * @brief  Clear TX FIFO Empty Flag
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);
+}
+
+/**
+  * @brief  Clear Transmission Complete Flag
+  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);
+}
+
+/**
+  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag
+  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);
+}
+
+/**
+  * @brief  Clear LIN Break Detection Flag
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);
+}
+
+/**
+  * @brief  Clear CTS Interrupt Flag
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);
+}
+
+/**
+  * @brief  Clear Receiver Time Out Flag
+  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);
+}
+
+/**
+  * @brief  Clear End Of Block Flag
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);
+}
+
+/**
+  * @brief  Clear SPI Slave Underrun Flag
+  * @note   Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not
+  *         SPI Slave mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);
+}
+
+/**
+  * @brief  Clear Character Match Flag
+  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);
+}
+
+/**
+  * @brief  Clear Wake Up from stop mode Flag
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)
+{
+  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_IT_Management IT_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Enable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Enable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Enable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Enable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Enable End Of Block Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Full Interrupt
+  * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Enable LIN Break Detection Interrupt
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Enable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Enable CTS Interrupt
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Enable Wake Up from Stop Mode Interrupt
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Enable TX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Enable RX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Disable IDLE Interrupt
+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);
+}
+
+#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);
+}
+
+/**
+  * @brief  Disable Transmission Complete Interrupt
+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);
+}
+
+#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);
+}
+
+/**
+  * @brief  Disable Parity Error Interrupt
+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);
+}
+
+/**
+  * @brief  Disable Character Match Interrupt
+  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);
+}
+
+/**
+  * @brief  Disable Receiver Timeout Interrupt
+  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);
+}
+
+/**
+  * @brief  Disable End Of Block Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Empty Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Full Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);
+}
+
+/**
+  * @brief  Disable LIN Break Detection Interrupt
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);
+}
+
+/**
+  * @brief  Disable Error Interrupt
+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing
+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).
+  *           0: Interrupt is inhibited
+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.
+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);
+}
+
+/**
+  * @brief  Disable CTS Interrupt
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);
+}
+
+/**
+  * @brief  Disable Wake Up from Stop Mode Interrupt
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);
+}
+
+/**
+  * @brief  Disable TX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);
+}
+
+/**
+  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);
+}
+
+/**
+  * @brief  Disable RX FIFO Threshold Interrupt
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);
+}
+
+/**
+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.
+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.
+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);
+}
+
+#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */
+
+/**
+  * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.
+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.
+  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.
+  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not
+  *         LIN feature is supported by the USARTx instance.
+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Error Interrupt is enabled or disabled.
+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not
+  *         Hardware Flow control feature is supported by the USARTx instance.
+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.
+  * @note   Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not
+  *         Wake-up from Stop mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.
+  * @note   Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not
+  *         Smartcard feature is supported by the USARTx instance.
+  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_DMA_Management DMA_Management
+  * @{
+  */
+
+/**
+  * @brief  Enable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Disable DMA Mode for reception
+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for reception
+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Disable DMA Mode for transmission
+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)
+{
+  ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);
+}
+
+/**
+  * @brief  Check if DMA Mode is enabled for transmission
+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Disable DMA Disabling on Reception Error
+  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)
+{
+  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);
+}
+
+/**
+  * @brief  Indicate if DMA Disabling on Reception Error is disabled
+  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr
+  * @param  USARTx USART Instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx)
+{
+  return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the data register address used for DMA transfer
+  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n
+  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr
+  * @param  USARTx USART Instance
+  * @param  Direction This parameter can be one of the following values:
+  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT
+  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE
+  * @retval Address of data register
+  */
+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction)
+{
+  uint32_t data_reg_addr;
+
+  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)
+  {
+    /* return address of TDR register */
+    data_reg_addr = (uint32_t) &(USARTx->TDR);
+  }
+  else
+  {
+    /* return address of RDR register */
+    data_reg_addr = (uint32_t) &(USARTx->RDR);
+  }
+
+  return data_reg_addr;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Data_Management Data_Management
+  * @{
+  */
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData8
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx)
+{
+  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);
+}
+
+/**
+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)
+  * @rmtoll RDR          RDR           LL_USART_ReceiveData9
+  * @param  USARTx USART Instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF
+  */
+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx)
+{
+  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData8
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)
+{
+  USARTx->TDR = Value;
+}
+
+/**
+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)
+  * @rmtoll TDR          TDR           LL_USART_TransmitData9
+  * @param  USARTx USART Instance
+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)
+{
+  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_LL_EF_Execution Execution
+  * @{
+  */
+
+/**
+  * @brief  Request an Automatic Baud Rate measurement on next received data frame
+  * @note   Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not
+  *         Auto Baud Rate detection feature is supported by the USARTx instance.
+  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);
+}
+
+/**
+  * @brief  Request Break sending
+  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);
+}
+
+/**
+  * @brief  Put USART in mute mode and set the RWU flag
+  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);
+}
+
+/**
+  * @brief  Request a Receive Data and FIFO flush
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @note   Allows to discard the received data without reading them, and avoid an overrun
+  *         condition.
+  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);
+}
+
+/**
+  * @brief  Request a Transmit data and FIFO flush
+  * @note   Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not
+  *         FIFO mode feature is supported by the USARTx instance.
+  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush
+  * @param  USARTx USART Instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)
+{
+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx);
+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct);
+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);
+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32G4xx_LL_USART_H */
+
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c
new file mode 100644
index 0000000..8930f28
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc.c
@@ -0,0 +1,3716 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_adc.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Analog to Digital Converter (ADC)
+  *          peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *           + Peripheral State functions
+  *          Other functions (extended functions) are available in file
+  *          "stm32g4xx_hal_adc_ex.c".
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### ADC peripheral features #####
+  ==============================================================================
+  [..]
+  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+
+  (+) Interrupt generation at the end of regular conversion and in case of
+      analog watchdog or overrun events.
+
+  (+) Single and continuous conversion modes.
+
+  (+) Scan mode for conversion of several channels sequentially.
+
+  (+) Data alignment with in-built data coherency.
+
+  (+) Programmable sampling time (channel wise)
+
+  (+) External trigger (timer or EXTI) with configurable polarity
+
+  (+) DMA request generation for transfer of conversions data of regular group.
+
+  (+) Configurable delay between conversions in Dual interleaved mode.
+
+  (+) ADC channels selectable single/differential input.
+
+  (+) ADC offset shared on 4 offset instances.
+  (+) ADC gain compensation
+
+  (+) ADC calibration
+
+  (+) ADC conversion of regular group.
+
+  (+) ADC supply requirements: 1.62 V to 3.6 V.
+
+  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+      Vdda or to an external voltage reference).
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+
+     *** Configuration of top level parameters related to ADC ***
+     ============================================================
+     [..]
+
+    (#) Enable the ADC interface
+        (++) As prerequisite, ADC clock must be configured at RCC top level.
+
+        (++) Two clock settings are mandatory:
+             (+++) ADC clock (core clock, also possibly conversion clock).
+
+             (+++) ADC clock (conversions clock).
+                   Two possible clock sources: synchronous clock derived from AHB clock
+                   or asynchronous clock derived from system clock or PLL (output divider P)
+                   running up to 75MHz.
+
+             (+++) Example:
+                   Into HAL_ADC_MspInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory)
+
+               RCC_ADCCLKSOURCE_PLL enable:                       (optional: if asynchronous clock selected)
+               (+++) RCC_PeriphClkInitTypeDef   RCC_PeriphClkInit;
+               (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+               (+++) PeriphClkInit.AdcClockSelection    = RCC_ADCCLKSOURCE_PLL;
+               (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
+
+        (++) ADC clock source and clock prescaler are configured at ADC level with
+             parameter "ClockPrescaler" using function HAL_ADC_Init().
+
+    (#) ADC pins configuration
+         (++) Enable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+         (++) Configure these ADC pins in analog mode
+              using function HAL_GPIO_Init()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Configure the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+              into the function of corresponding ADC interruption vector
+              ADCx_IRQHandler().
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+              using function HAL_DMA_Init().
+         (++) Configure the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+              into the function of corresponding DMA interruption vector
+              DMAx_Channelx_IRQHandler().
+
+     *** Configuration of ADC, group regular, channels parameters ***
+     ================================================================
+     [..]
+
+    (#) Configure the ADC parameters (resolution, data alignment, ...)
+        and regular group parameters (conversion trigger, sequencer, ...)
+        using function HAL_ADC_Init().
+
+    (#) Configure the channels for regular group parameters (channel number,
+        channel rank into sequencer, ..., into regular group)
+        using function HAL_ADC_ConfigChannel().
+
+    (#) Optionally, configure the analog watchdog parameters (channels
+        monitored, thresholds, ...)
+        using function HAL_ADC_AnalogWDGConfig().
+
+     *** Execution of ADC conversions ***
+     ====================================
+     [..]
+
+    (#) Optionally, perform an automatic ADC calibration to improve the
+        conversion accuracy
+        using function HAL_ADCEx_Calibration_Start().
+
+    (#) ADC driver can be used among three modes: polling, interruption,
+        transfer by DMA.
+
+        (++) ADC conversion by polling:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start()
+          (+++) Wait for ADC conversion completion
+                using function HAL_ADC_PollForConversion()
+          (+++) Retrieve conversion results
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral
+                using function HAL_ADC_Stop()
+
+        (++) ADC conversion by interruption:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_IT()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback()
+                (this function must be implemented in user program)
+          (+++) Retrieve conversion results
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral
+                using function HAL_ADC_Stop_IT()
+
+        (++) ADC conversion with transfer by DMA:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_DMA()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+                (these functions must be implemented in user program)
+          (+++) Conversion results are automatically transferred by DMA into
+                destination variable address.
+          (+++) Stop conversion and disable the ADC peripheral
+                using function HAL_ADC_Stop_DMA()
+
+     [..]
+
+    (@) Callback functions must be implemented in user program:
+      (+@) HAL_ADC_ErrorCallback()
+      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+      (+@) HAL_ADC_ConvCpltCallback()
+      (+@) HAL_ADC_ConvHalfCpltCallback
+
+     *** Deinitialization of ADC ***
+     ============================================================
+     [..]
+
+    (#) Disable the ADC interface
+      (++) ADC clock can be hard reset and disabled at RCC top level.
+        (++) Hard reset of ADC peripherals
+             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+        (++) ADC clock disable
+             using the equivalent macro/functions as configuration step.
+             (+++) Example:
+                   Into HAL_ADC_MspDeInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+               (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
+               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+    (#) ADC pins configuration
+         (++) Disable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Disable the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Deinitialize the DMA
+              using function HAL_DMA_Init().
+         (++) Disable the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+    [..]
+
+    *** Callback registration ***
+    =============================================
+    [..]
+
+     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions @ref HAL_ADC_RegisterCallback()
+     to register an interrupt callback.
+    [..]
+
+     Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
+       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+       (+) EndOfSamplingCallback          : ADC end of sampling callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+
+     Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+     weak function.
+    [..]
+
+     @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) InjectedConvCpltCallback       : ADC group injected conversion complete callback
+       (+) InjectedQueueOverflowCallback  : ADC group injected context queue overflow callback
+       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+       (+) EndOfSamplingCallback          : ADC end of sampling callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     [..]
+
+     By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+     these callbacks are null (not registered beforehand).
+    [..]
+
+     If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+     [..]
+
+     Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+    [..]
+
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
+     or @ref HAL_ADC_Init() function.
+     [..]
+
+     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADC ADC
+  * @brief ADC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+#define ADC_CFGR_FIELDS_1 (ADC_CFGR_RES    | ADC_CFGR_ALIGN   |\
+                           ADC_CFGR_CONT   | ADC_CFGR_OVRMOD  |\
+                           ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
+                           ADC_CFGR_EXTEN  | ADC_CFGR_EXTSEL)              /*!< ADC_CFGR fields of parameters that can
+                          be updated when no regular conversion is on-going */
+
+/* Timeout values for ADC operations (enable settling time,                   */
+/*   disable settling time, ...).                                             */
+/*   Values defined to be higher than worst cases: low clock frequency,       */
+/*   maximum prescalers.                                                      */
+#define ADC_ENABLE_TIMEOUT              (2UL)    /*!< ADC enable time-out value  */
+#define ADC_DISABLE_TIMEOUT             (2UL)    /*!< ADC disable time-out value */
+
+/* Timeout to wait for current conversion on going to be completed.           */
+/* Timeout fixed to longest ADC conversion possible, for 1 channel:           */
+/*   - maximum sampling time (640.5 adc_clk)                                  */
+/*   - ADC resolution (Tsar 12 bits= 12.5 adc_clk)                            */
+/*   - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio)   */
+/*   - ADC oversampling ratio 256                                             */
+/*   Calculation: 653 * 4096 * 256 CPU clock cycles max                       */
+/* Unit: cycles of CPU clock.                                                 */
+#define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL)  /*!< ADC conversion completion time-out value */
+
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    ADC Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the ADC.
+      (+) De-initialize the ADC.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the ADC peripheral and regular group according to
+  *         parameters specified in structure "ADC_InitTypeDef".
+  * @note   As prerequisite, ADC clock must be configured at RCC top level
+  *         (refer to description of RCC configuration for ADC
+  *         in header of this file).
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+  *         coming from ADC state reset. Following calls to this function can
+  *         be used to reconfigure some parameters of ADC_InitTypeDef
+  *         structure on the fly, without modifying MSP configuration. If ADC
+  *         MSP has to be modified again, HAL_ADC_DeInit() must be called
+  *         before HAL_ADC_Init().
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure
+  *         "ADC_InitTypeDef".
+  * @note   This function configures the ADC within 2 scopes: scope of entire
+  *         ADC and scope of regular group. For parameters details, see comments
+  *         of structure "ADC_InitTypeDef".
+  * @note   Parameters related to common ADC registers (ADC clock mode) are set
+  *         only if all ADCs are disabled.
+  *         If this is not the case, these common parameters setting are
+  *         bypassed without error reporting: it can be the intended behaviour in
+  *         case of update of a parameter of ADC_InitTypeDef on the fly,
+  *         without  disabling the other ADCs.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmp_cfgr;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+  __IO uint32_t wait_loop_index = 0UL;
+
+  /* Check ADC handle */
+  if (hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+  assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation));
+  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv));
+  assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+  assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+
+  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+  {
+    assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+    assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+    if (hadc->Init.DiscontinuousConvMode == ENABLE)
+    {
+      assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
+    }
+  }
+
+  /* DISCEN and CONT bits cannot be set at the same time */
+  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+
+  /* Actions performed only if ADC is coming from state reset:                */
+  /* - Initialization of ADC MSP                                              */
+  if (hadc->State == HAL_ADC_STATE_RESET)
+  {
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    /* Init the ADC Callback settings */
+    hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
+    hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
+    hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
+    hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
+    hadc->InjectedConvCpltCallback      = HAL_ADCEx_InjectedConvCpltCallback;       /* Legacy weak callback */
+    hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;  /* Legacy weak callback */
+    hadc->LevelOutOfWindow2Callback     = HAL_ADCEx_LevelOutOfWindow2Callback;      /* Legacy weak callback */
+    hadc->LevelOutOfWindow3Callback     = HAL_ADCEx_LevelOutOfWindow3Callback;      /* Legacy weak callback */
+    hadc->EndOfSamplingCallback         = HAL_ADCEx_EndOfSamplingCallback;          /* Legacy weak callback */
+
+    if (hadc->MspInitCallback == NULL)
+    {
+      hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hadc->MspInitCallback(hadc);
+#else
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+
+    /* Initialize Lock */
+    hadc->Lock = HAL_UNLOCKED;
+  }
+
+  /* - Exit from deep-power-down mode and ADC voltage regulator enable        */
+  if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
+  {
+    /* Disable ADC deep power down mode */
+    LL_ADC_DisableDeepPowerDown(hadc->Instance);
+
+    /* System was in deep power down mode, calibration must
+     be relaunched or a previously saved calibration factor
+     re-applied once the ADC voltage regulator is enabled */
+  }
+
+  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+  {
+    /* Enable ADC internal voltage regulator */
+    LL_ADC_EnableInternalRegulator(hadc->Instance);
+
+    /* Note: Variable divided by 2 to compensate partially              */
+    /*       CPU processing cycles, scaling in us split to not          */
+    /*       exceed 32 bits register capacity and handle low frequency. */
+    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+    while (wait_loop_index != 0UL)
+    {
+      wait_loop_index--;
+    }
+  }
+
+  /* Verification that ADC voltage regulator is correctly enabled, whether    */
+  /* or not ADC is coming from state reset (if any potential problem of       */
+  /* clocking, voltage regulator would not be enabled).                       */
+  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    /* Set ADC error code to ADC peripheral internal error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Configuration of ADC parameters if previous preliminary actions are      */
+  /* correctly completed and if there is no conversion on going on regular    */
+  /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
+  /* called to update a parameter on the fly).                                */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+
+  if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+      && (tmp_adc_is_conversion_on_going_regular == 0UL)
+     )
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+
+    /* Configuration of common ADC parameters                                 */
+
+    /* Parameters update conditioned to ADC state:                            */
+    /* Parameters that can be updated only when ADC is disabled:              */
+    /*  - clock configuration                                                 */
+    if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+    {
+      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+      {
+        /* Reset configuration of ADC common register CCR:                      */
+        /*                                                                      */
+        /*   - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set  */
+        /*     according to adc->Init.ClockPrescaler. It selects the clock      */
+        /*    source and sets the clock division factor.                        */
+        /*                                                                      */
+        /* Some parameters of this register are not reset, since they are set   */
+        /* by other functions and must be kept in case of usage of this         */
+        /* function on the fly (update of a parameter of ADC_InitTypeDef        */
+        /* without needing to reconfigure all other ADC groups/channels         */
+        /* parameters):                                                         */
+        /*   - when multimode feature is available, multimode-related           */
+        /*     parameters: MDMA, DMACFG, DELAY, DUAL (set by API                */
+        /*     HAL_ADCEx_MultiModeConfigChannel() )                             */
+        /*   - internal measurement paths: Vbat, temperature sensor, Vref       */
+        /*     (set into HAL_ADC_ConfigChannel() or                             */
+        /*     HAL_ADCEx_InjectedConfigChannel() )                              */
+        LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
+      }
+    }
+
+    /* Configuration of ADC:                                                  */
+    /*  - resolution                               Init.Resolution            */
+    /*  - data alignment                           Init.DataAlign             */
+    /*  - external trigger to start conversion     Init.ExternalTrigConv      */
+    /*  - external trigger polarity                Init.ExternalTrigConvEdge  */
+    /*  - continuous conversion mode               Init.ContinuousConvMode    */
+    /*  - overrun                                  Init.Overrun               */
+    /*  - discontinuous mode                       Init.DiscontinuousConvMode */
+    /*  - discontinuous mode channel count         Init.NbrOfDiscConversion   */
+    tmp_cfgr  = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)           |
+                 hadc->Init.Overrun                                                     |
+                 hadc->Init.DataAlign                                                   |
+                 hadc->Init.Resolution                                                  |
+                 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
+
+    if (hadc->Init.DiscontinuousConvMode == ENABLE)
+    {
+      tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
+    }
+
+    /* Enable external trigger if trigger selection is different of software  */
+    /* start.                                                                 */
+    /* Note: This configuration keeps the hardware feature of parameter       */
+    /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+    /*       software start.                                                  */
+    if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+    {
+      tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
+                   | hadc->Init.ExternalTrigConvEdge
+                  );
+    }
+
+    /* Update Configuration Register CFGR */
+    MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr);
+
+    /* Configuration of sampling mode */
+    MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
+
+    /* Parameters update conditioned to ADC state:                            */
+    /* Parameters that can be updated when ADC is disabled or enabled without */
+    /* conversion on going on regular and injected groups:                    */
+    /*  - Gain Compensation               Init.GainCompensation               */
+    /*  - DMA continuous request          Init.DMAContinuousRequests          */
+    /*  - LowPowerAutoWait feature        Init.LowPowerAutoWait               */
+    /*  - Oversampling parameters         Init.Oversampling                   */
+    tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+    if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+        && (tmp_adc_is_conversion_on_going_injected == 0UL)
+       )
+    {
+      tmp_cfgr = (ADC_CFGR_DFSDM(hadc)                                            |
+                   ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)        |
+                   ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+
+      MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr);
+
+      if (hadc->Init.GainCompensation != 0UL)
+      {
+        SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
+        MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
+      }
+      else
+      {
+        CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
+        MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
+      }
+
+      if (hadc->Init.OversamplingMode == ENABLE)
+      {
+        assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
+        assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
+        assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
+        assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
+
+        /* Configuration of Oversampler:                                      */
+        /*  - Oversampling Ratio                                              */
+        /*  - Right bit shift                                                 */
+        /*  - Triggered mode                                                  */
+        /*  - Oversampling mode (continued/resumed)                           */
+        MODIFY_REG(hadc->Instance->CFGR2,
+                   ADC_CFGR2_OVSR  |
+                   ADC_CFGR2_OVSS  |
+                   ADC_CFGR2_TROVS |
+                   ADC_CFGR2_ROVSM,
+                   ADC_CFGR2_ROVSE                       |
+                   hadc->Init.Oversampling.Ratio         |
+                   hadc->Init.Oversampling.RightBitShift |
+                   hadc->Init.Oversampling.TriggeredMode |
+                   hadc->Init.Oversampling.OversamplingStopReset
+                  );
+      }
+      else
+      {
+        /* Disable ADC oversampling scope on ADC group regular */
+        CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
+      }
+
+    }
+
+    /* Configuration of regular group sequencer:                              */
+    /* - if scan mode is disabled, regular channels sequence length is set to */
+    /*   0x00: 1 channel converted (channel on regular rank 1)                */
+    /*   Parameter "NbrOfConversion" is discarded.                            */
+    /*   Note: Scan mode is not present by hardware on this device, but       */
+    /*   emulated by software for alignment over all STM32 devices.           */
+    /* - if scan mode is enabled, regular channels sequence length is set to  */
+    /*   parameter "NbrOfConversion".                                         */
+
+    if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+    {
+      /* Set number of ranks in regular group sequencer */
+      MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
+    }
+    else
+    {
+      CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
+    }
+
+    /* Initialize the ADC state */
+    /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
+    ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Deinitialize the ADC peripheral registers to their default reset
+  *         values, with deinitialization of the ADC MSP.
+  * @note   For devices with several ADCs: reset of ADC common registers is done
+  *         only if all ADCs sharing the same common group are disabled.
+  *         (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
+  *         all ADC instances use the same core clock at RCC level, disabling
+  *         the core clock reset all ADC instances).
+  *         If this is not the case, reset of these common parameters reset is
+  *         bypassed without error reporting: it can be the intended behavior in
+  *         case of reset of a single ADC while the other ADCs sharing the same
+  *         common group is still running.
+  * @note   By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
+  *         this saves more power by reducing leakage currents
+  *         and is particularly interesting before entering MCU low-power modes.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check ADC handle */
+  if (hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+  /* Stop potential conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped            */
+  /* Flush register JSQR: reset the queue sequencer when injected             */
+  /* queue sequencer is enabled and ADC disabled.                             */
+  /* The software and hardware triggers of the injected sequence are both     */
+  /* internally disabled just after the completion of the last valid          */
+  /* injected sequence.                                                       */
+  SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Change ADC state */
+      hadc->State = HAL_ADC_STATE_READY;
+    }
+  }
+
+  /* Note: HAL ADC deInit is done independently of ADC conversion stop        */
+  /*       and disable return status. In case of status fail, attempt to      */
+  /*       perform deinitialization anyway and it is up user code in          */
+  /*       in HAL_ADC_MspDeInit() to reset the ADC peripheral using           */
+  /*       system RCC hard reset.                                             */
+
+  /* ========== Reset ADC registers ========== */
+  /* Reset register IER */
+  __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 | ADC_IT_AWD1 |
+                              ADC_IT_JQOVF | ADC_IT_OVR  |
+                              ADC_IT_JEOS  | ADC_IT_JEOC |
+                              ADC_IT_EOS   | ADC_IT_EOC  |
+                              ADC_IT_EOSMP | ADC_IT_RDY));
+
+  /* Reset register ISR */
+  __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
+                              ADC_FLAG_JQOVF | ADC_FLAG_OVR  |
+                              ADC_FLAG_JEOS  | ADC_FLAG_JEOC |
+                              ADC_FLAG_EOS   | ADC_FLAG_EOC  |
+                              ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+
+  /* Reset register CR */
+  /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
+     ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
+     no direct reset applicable.
+     Update CR register to reset value where doable by software */
+  CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
+  SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
+
+  /* Reset register CFGR */
+  CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
+  SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+  /* Reset register CFGR2 */
+  CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS   | ADC_CFGR2_OVSS |
+            ADC_CFGR2_OVSR  | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
+
+  /* Reset register SMPR1 */
+  CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
+
+  /* Reset register SMPR2 */
+  CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
+            ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
+            ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
+
+  /* Reset register TR1 */
+  CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
+
+  /* Reset register TR2 */
+  CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
+
+  /* Reset register TR3 */
+  CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
+
+  /* Reset register SQR1 */
+  CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
+            ADC_SQR1_SQ1 | ADC_SQR1_L);
+
+  /* Reset register SQR2 */
+  CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
+            ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
+
+  /* Reset register SQR3 */
+  CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
+            ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
+
+  /* Reset register SQR4 */
+  CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+  /* Register JSQR was reset when the ADC was disabled */
+
+  /* Reset register DR */
+  /* bits in access mode read only, no direct reset applicable*/
+
+  /* Reset register OFR1 */
+  CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
+  /* Reset register OFR2 */
+  CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
+  /* Reset register OFR3 */
+  CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
+  /* Reset register OFR4 */
+  CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
+
+  /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+  /* bits in access mode read only, no direct reset applicable*/
+
+  /* Reset register AWD2CR */
+  CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+  /* Reset register AWD3CR */
+  CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+  /* Reset register DIFSEL */
+  CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+  /* Reset register CALFACT */
+  CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+
+
+  /* ========== Reset common ADC registers ========== */
+
+  /* Software is allowed to change common parameters only when all the other
+     ADCs are disabled.   */
+  if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+  {
+    /* Reset configuration of ADC common register CCR:
+      - clock mode: CKMODE, PRESCEN
+      - multimode related parameters (when this feature is available): MDMA,
+        DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
+      - internal measurement paths: Vbat, temperature sensor, Vref (set into
+        HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
+    */
+    ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
+
+    /* ========== Hard reset ADC peripheral ========== */
+    /* Performs a global reset of the entire ADC peripherals instances        */
+    /* sharing the same common ADC instance: ADC state is forced to           */
+    /* a similar state as after device power-on.                              */
+    /* Note: A possible implementation is to add RCC bus reset of ADC         */
+    /* (for example, using macro                                              */
+    /*  __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
+    /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)":         */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    if (hadc->MspDeInitCallback == NULL)
+    {
+      hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
+    }
+
+    /* DeInit the low level hardware */
+    hadc->MspDeInitCallback(hadc);
+#else
+    /* DeInit the low level hardware */
+    HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  }
+
+  /* Set ADC error code to none */
+  ADC_CLEAR_ERRORCODE(hadc);
+
+  /* Reset injected channel configuration parameters */
+  hadc->InjectionConfig.ContextQueue = 0;
+  hadc->InjectionConfig.ChannelCount = 0;
+
+  /* Set ADC state */
+  hadc->State = HAL_ADC_STATE_RESET;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Initialize the ADC MSP.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspInit must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitialize the ADC MSP.
+  * @param hadc ADC handle
+  * @note   All ADC instances use the same core clock at RCC level, disabling
+  *         the core clock reset all ADC instances).
+  * @retval None
+  */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspDeInit must be implemented in the user file.
+   */
+}
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User ADC Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
+  *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
+  *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+                                           pADC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = pCallback;
+        break;
+
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = pCallback;
+        break;
+
+      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+        hadc->InjectedConvCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
+        hadc->InjectedQueueOverflowCallback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+        hadc->LevelOutOfWindow2Callback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+        hadc->LevelOutOfWindow3Callback = pCallback;
+        break;
+
+      case HAL_ADC_END_OF_SAMPLING_CB_ID :
+        hadc->EndOfSamplingCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a ADC Callback
+  *         ADC callback is redirected to the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID  ADC group injected conversion complete callback ID
+  *          @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID        ADC group injected context queue overflow callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
+  *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+        break;
+
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+        break;
+
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+        break;
+
+      case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
+        hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
+        break;
+
+      case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
+        hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+        hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+        hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
+        break;
+
+      case HAL_ADC_END_OF_SAMPLING_CB_ID :
+        hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
+        break;
+
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
+  * @brief    ADC IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of regular group.
+      (+) Stop conversion of regular group.
+      (+) Poll for conversion complete on regular group.
+      (+) Poll for conversion event.
+      (+) Get result of regular channel conversion.
+      (+) Start conversion of regular group and enable interruptions.
+      (+) Stop conversion of regular group and disable interruptions.
+      (+) Handle ADC interrupt request
+      (+) Start conversion of regular group and enable DMA transfer.
+      (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC, start conversion of regular group.
+  * @note   Interruptions enabled in this function: None.
+  * @note   Case of multimode enabled (when multimode feature is available):
+  *           if ADC is Slave, ADC is enabled but conversion is not started,
+  *           if ADC is master, ADC is enabled and multimode conversion is started.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - if ADC instance is master or if multimode feature is not available
+        - if multimode setting is disabled (ADC instance slave in independent mode) */
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+         )
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+      /* Set ADC error code */
+      /* Check if a conversion is on going on ADC group injected */
+      if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
+      {
+        /* Reset ADC error code fields related to regular conversions only */
+        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+      }
+      else
+      {
+        /* Reset all ADC error code fields */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+
+      /* Clear ADC group regular conversion flag and overrun flag               */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      /* Case of multimode enabled (when multimode feature is available):     */
+      /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
+      /*    enabled only (conversion is not started),                         */
+      /*  - if ADC is master, ADC is enabled and conversion is started.       */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+         )
+      {
+        /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+        {
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+        }
+
+        /* Start ADC group regular conversion */
+        LL_ADC_REG_StartConversion(hadc->Instance);
+      }
+      else
+      {
+        /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        /* if Master ADC JAUTO bit is set, update Slave State in setting
+           HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
+        tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+        if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
+        {
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+        }
+
+      }
+#else
+      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+      {
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+      }
+
+      /* Start ADC group regular conversion */
+      LL_ADC_REG_StartConversion(hadc->Instance);
+#endif /* ADC_MULTIMODE_SUPPORT */
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected channels in
+  *         case of auto_injection mode), disable ADC peripheral.
+  * @note:  ADC peripheral disable is forcing stop of potential
+  *         conversion on injected group. If injected group is under use, it
+  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Wait for regular group conversion to be completed.
+  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
+  *         conversion) are cleared by this function, with an exception:
+  *         if low power feature "LowPowerAutoWait" is enabled, flags are
+  *         not cleared to not interfere with this feature until data register
+  *         is read using function HAL_ADC_GetValue().
+  * @note   This function cannot be used in a particular setup: ADC configured
+  *         in DMA mode and polling for end of each conversion (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+  *         In this case, DMA resets the flag EOC and polling cannot be
+  *         performed on each conversion. Nevertheless, polling can still
+  *         be performed on the complete sequence (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+  * @param hadc ADC handle
+  * @param Timeout Timeout value in millisecond.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t tmp_Flag_End;
+  uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* If end of conversion selected to end of sequence conversions */
+  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+  {
+    tmp_Flag_End = ADC_FLAG_EOS;
+  }
+  /* If end of conversion selected to end of unitary conversion */
+  else /* ADC_EOC_SINGLE_CONV */
+  {
+    /* Verification that ADC configuration is compliant with polling for      */
+    /* each conversion:                                                       */
+    /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
+    /* several ranks and polling for end of each conversion.                  */
+    /* For code simplicity sake, this particular case is generalized to       */
+    /* ADC configured in DMA mode and and polling for end of each conversion. */
+#if defined(ADC_MULTIMODE_SUPPORT)
+    if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+       )
+    {
+      /* Check ADC DMA mode in independent mode on ADC group regular */
+      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        return HAL_ERROR;
+      }
+      else
+      {
+        tmp_Flag_End = (ADC_FLAG_EOC);
+      }
+    }
+    else
+    {
+      /* Check ADC DMA mode in multimode on ADC group regular */
+      if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+        return HAL_ERROR;
+      }
+      else
+      {
+        tmp_Flag_End = (ADC_FLAG_EOC);
+      }
+    }
+#else
+    /* Check ADC DMA mode */
+    if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      return HAL_ERROR;
+    }
+    else
+    {
+      tmp_Flag_End = (ADC_FLAG_EOC);
+    }
+#endif /* ADC_MULTIMODE_SUPPORT */
+  }
+
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+
+  /* Wait until End of unitary conversion or sequence conversions flag is raised */
+  while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+  /* Determine whether any further conversion upcoming on group regular       */
+  /* by external trigger, continuous mode or scan sequence on going.          */
+  if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+      && (hadc->Init.ContinuousConvMode == DISABLE)
+     )
+  {
+    /* Check whether end of sequence is reached */
+    if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+    {
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+      if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+      {
+        SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+      }
+    }
+  }
+
+  /* Get relevant register CFGR in ADC instance of ADC master or slave        */
+  /* in function of multimode state (for devices with multimode               */
+  /* available).                                                              */
+#if defined(ADC_MULTIMODE_SUPPORT)
+  if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+      || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+      || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+      || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+     )
+  {
+    /* Retrieve handle ADC CFGR register */
+    tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+  }
+  else
+  {
+    /* Retrieve Master ADC CFGR register */
+    tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+    tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+  }
+#else
+  /* Retrieve handle ADC CFGR register */
+  tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Clear polled flag */
+  if (tmp_Flag_End == ADC_FLAG_EOS)
+  {
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
+  }
+  else
+  {
+    /* Clear end of conversion EOC flag of regular group if low power feature */
+    /* "LowPowerAutoWait " is disabled, to not interfere with this feature    */
+    /* until data register is read using function HAL_ADC_GetValue().         */
+    if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
+    {
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+    }
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll for ADC event.
+  * @param hadc ADC handle
+  * @param EventType the ADC event type.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event
+  *            @arg @ref ADC_AWD1_EVENT   ADC Analog watchdog 1 event (main analog watchdog, present on
+  *                                       all STM32 series)
+  *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event (additional analog watchdog, not present on
+  *                                       all STM32 series)
+  *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event (additional analog watchdog, not present on
+  *                                       all STM32 series)
+  *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
+  *            @arg @ref ADC_JQOVF_EVENT  ADC Injected context queue overflow event
+  * @param Timeout Timeout value in millisecond.
+  * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
+  *         Indeed, the latter is reset only if hadc->Init.Overrun field is set
+  *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
+  *         by a new converted data as soon as OVR is cleared.
+  *         To reset OVR flag once the preserved data is retrieved, the user can resort
+  *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+
+  /* Check selected event flag */
+  while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  switch (EventType)
+  {
+    /* End Of Sampling event */
+    case ADC_EOSMP_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+
+      /* Clear the End Of Sampling flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+
+      break;
+
+    /* Analog watchdog (level out of window) event */
+    /* Note: In case of several analog watchdog enabled, if needed to know      */
+    /* which one triggered and on which ADCx, test ADC state of analog watchdog */
+    /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()".        */
+    /* For example:                                                             */
+    /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "          */
+    /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) "          */
+    /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) "          */
+
+    /* Check analog watchdog 1 flag */
+    case ADC_AWD_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+      /* Clear ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+
+      break;
+
+    /* Check analog watchdog 2 flag */
+    case ADC_AWD2_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+      /* Clear ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+
+      break;
+
+    /* Check analog watchdog 3 flag */
+    case ADC_AWD3_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+      /* Clear ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+
+      break;
+
+    /* Injected context queue overflow event */
+    case ADC_JQOVF_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+      /* Set ADC error code to Injected context queue overflow */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+      /* Clear ADC Injected context queue overflow flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+      break;
+
+    /* Overrun event */
+    default: /* Case ADC_OVR_EVENT */
+      /* If overrun is set to overwrite previous data, overrun event is not     */
+      /* considered as an error.                                                */
+      /* (cf ref manual "Managing conversions without using the DMA and without */
+      /* overrun ")                                                             */
+      if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+      {
+        /* Set ADC state */
+        SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+        /* Set ADC error code to overrun */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+      }
+      else
+      {
+        /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
+           otherwise, data register is potentially overwritten by new converted data as soon
+           as OVR is cleared. */
+        __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+      }
+      break;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of regular group with interruption.
+  * @note   Interruptions enabled in this function according to initialization
+  *         setting : EOC (end of conversion), EOS (end of sequence),
+  *         OVR overrun.
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   Case of multimode enabled (when multimode feature is available):
+  *         HAL_ADC_Start_IT() must be called for ADC Slave first, then for
+  *         ADC Master.
+  *         For ADC Slave, ADC is enabled only (conversion is not started).
+  *         For ADC Master, ADC is enabled and multimode conversion is started.
+  * @note   To guarantee a proper reset of all interruptions once all the needed
+  *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
+  *         a correct stop of the IT-based conversions.
+  * @note   By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
+  *         interruption. If required (e.g. in case of oversampling with trigger
+  *         mode), the user must:
+  *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
+  *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
+  *          before calling HAL_ADC_Start_IT().
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - if ADC instance is master or if multimode feature is not available
+        - if multimode setting is disabled (ADC instance slave in independent mode) */
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+         )
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+      /* Set ADC error code */
+      /* Check if a conversion is on going on ADC group injected */
+      if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+      {
+        /* Reset ADC error code fields related to regular conversions only */
+        CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+      }
+      else
+      {
+        /* Reset all ADC error code fields */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+
+      /* Clear ADC group regular conversion flag and overrun flag               */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Disable all interruptions before enabling the desired ones */
+      __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+      /* Enable ADC end of conversion interrupt */
+      switch (hadc->Init.EOCSelection)
+      {
+        case ADC_EOC_SEQ_CONV:
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
+          break;
+        /* case ADC_EOC_SINGLE_CONV */
+        default:
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+          break;
+      }
+
+      /* Enable ADC overrun interrupt */
+      /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
+         ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
+         behavior and no CPU time is lost for a non-processed interruption */
+      if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+      {
+        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+      }
+
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      /* Case of multimode enabled (when multimode feature is available):     */
+      /*  - if ADC is slave and dual regular conversions are enabled, ADC is  */
+      /*    enabled only (conversion is not started),                         */
+      /*  - if ADC is master, ADC is enabled and conversion is started.       */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+         )
+      {
+        /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+        {
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+
+          /* Enable as well injected interruptions in case
+           HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+           allows to start regular and injected conversions when JAUTO is
+           set with a single call to HAL_ADC_Start_IT() */
+          switch (hadc->Init.EOCSelection)
+          {
+            case ADC_EOC_SEQ_CONV:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+              break;
+            /* case ADC_EOC_SINGLE_CONV */
+            default:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+              break;
+          }
+        }
+
+        /* Start ADC group regular conversion */
+        LL_ADC_REG_StartConversion(hadc->Instance);
+      }
+      else
+      {
+        /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        /* if Master ADC JAUTO bit is set, Slave injected interruptions
+           are enabled nevertheless (for same reason as above) */
+        tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+        if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
+        {
+          /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
+             and in resetting HAL_ADC_STATE_INJ_EOC bit */
+          ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+          /* Next, set Slave injected interruptions */
+          switch (hadc->Init.EOCSelection)
+          {
+            case ADC_EOC_SEQ_CONV:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+              break;
+            /* case ADC_EOC_SINGLE_CONV */
+            default:
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+              __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+              break;
+          }
+        }
+      }
+#else
+      /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
+      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
+      {
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
+
+        /* Enable as well injected interruptions in case
+         HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
+         allows to start regular and injected conversions when JAUTO is
+         set with a single call to HAL_ADC_Start_IT() */
+        switch (hadc->Init.EOCSelection)
+        {
+          case ADC_EOC_SEQ_CONV:
+            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+            __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+            break;
+          /* case ADC_EOC_SINGLE_CONV */
+          default:
+            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+            __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+            break;
+        }
+      }
+
+      /* Start ADC group regular conversion */
+      LL_ADC_REG_StartConversion(hadc->Instance);
+#endif /* ADC_MULTIMODE_SUPPORT */
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable interrution of
+  *         end-of-conversion, disable ADC peripheral.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going, on ADC groups regular and injected */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC end of conversion interrupt for regular group */
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
+  * @note   Interruptions enabled in this function:
+  *         overrun (if applicable), DMA half transfer, DMA transfer complete.
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
+  *         is designed for single-ADC mode only. For multimode, the dedicated
+  *         HAL_ADCEx_MultiModeStart_DMA() function must be used.
+  * @param hadc ADC handle
+  * @param pData Destination Buffer address.
+  * @param Length Number of data to be transferred from ADC peripheral to memory
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+    /* Ensure that multimode regular conversions are not enabled.   */
+    /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used.  */
+    if ((ADC_IS_INDEPENDENT(hadc) != RESET)
+        || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+       )
+#endif /* ADC_MULTIMODE_SUPPORT */
+    {
+      /* Enable the ADC peripheral */
+      tmp_hal_status = ADC_Enable(hadc);
+
+      /* Start conversion if ADC is effectively enabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state                                                        */
+        /* - Clear state bitfield related to regular group conversion results   */
+        /* - Set state bitfield related to regular operation                    */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                          HAL_ADC_STATE_REG_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+        /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+          - if ADC instance is master or if multimode feature is not available
+          - if multimode setting is disabled (ADC instance slave in independent mode) */
+        if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+            || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+           )
+        {
+          CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+        }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+        /* Check if a conversion is on going on ADC group injected */
+        if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
+        {
+          /* Reset ADC error code fields related to regular conversions only */
+          CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
+        }
+        else
+        {
+          /* Reset all ADC error code fields */
+          ADC_CLEAR_ERRORCODE(hadc);
+        }
+
+        /* Set the DMA transfer complete callback */
+        hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+        /* Set the DMA half transfer complete callback */
+        hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+        /* Set the DMA error callback */
+        hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+        /* Manage ADC and DMA start: ADC overrun interruption, DMA start,     */
+        /* ADC start (in case of SW start):                                   */
+
+        /* Clear regular group conversion flag and overrun flag               */
+        /* (To ensure of no unknown state from potential previous ADC         */
+        /* operations)                                                        */
+        __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+        /* Process unlocked */
+        /* Unlock before starting ADC conversions: in case of potential         */
+        /* interruption, to let the process to ADC IRQ Handler.                 */
+        __HAL_UNLOCK(hadc);
+
+        /* With DMA, overrun event is always considered as an error even if
+           hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
+           ADC_IT_OVR is enabled. */
+        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+        /* Enable ADC DMA mode */
+        SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+        /* Start the DMA channel */
+        tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+        /* Enable conversion of regular group.                                  */
+        /* If software start has been selected, conversion starts immediately.  */
+        /* If external trigger has been selected, conversion will start at next */
+        /* trigger event.                                                       */
+        /* Start ADC group regular conversion */
+        LL_ADC_REG_StartConversion(hadc->Instance);
+      }
+      else
+      {
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+      }
+
+    }
+#if defined(ADC_MULTIMODE_SUPPORT)
+    else
+    {
+      tmp_hal_status = HAL_ERROR;
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+#endif /* ADC_MULTIMODE_SUPPORT */
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable ADC DMA transfer, disable
+  *         ADC peripheral.
+  * @note:  ADC peripheral disable is forcing stop of potential
+  *         conversion on ADC group injected. If ADC group injected is under use, it
+  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+  * @note   Case of multimode enabled (when multimode feature is available):
+  *         HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
+  *         For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential ADC group regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
+    CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+    {
+      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+      /* Check if DMA channel effectively disabled */
+      if (tmp_hal_status != HAL_OK)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+      }
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripheral */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
+    /* to keep in memory a potential failing status.                          */
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmp_hal_status = ADC_Disable(hadc);
+    }
+    else
+    {
+      (void)ADC_Disable(hadc);
+    }
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get ADC regular group conversion result.
+  * @note   Reading register DR automatically clears ADC flag EOC
+  *         (ADC group regular end of unitary conversion).
+  * @note   This function does not clear ADC flag EOS
+  *         (ADC group regular end of sequence conversion).
+  *         Occurrence of flag EOS rising:
+  *          - If sequencer is composed of 1 rank, flag EOS is equivalent
+  *            to flag EOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag EOC only is raised, at the end of the scan sequence
+  *            both flags EOC and EOS are raised.
+  *         To clear this flag, either use function:
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADC_PollForConversion()
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+  * @param hadc ADC handle
+  * @retval ADC group regular conversion data
+  */
+uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Note: EOC flag is not cleared here by software because automatically     */
+  /*       cleared by hardware when reading register DR.                      */
+
+  /* Return ADC converted value */
+  return hadc->Instance->DR;
+}
+
+/**
+  * @brief  Start ADC conversion sampling phase of regular group
+  * @note:  This function should only be called to start sampling when
+  *         - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
+  *         mode has been selected
+  *         - @ref ADC_SOFTWARE_START has been selected as trigger source
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Start sampling */
+  SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop ADC conversion sampling phase of regular group and start conversion
+  * @note:  This function should only be called to stop sampling when
+  *         - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
+  *         mode has been selected
+  *         - @ref ADC_SOFTWARE_START has been selected as trigger source
+  *         - after sampling has been started using @ref HAL_ADC_StartSampling.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Start sampling */
+  CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handle ADC interrupt request.
+  * @param hadc ADC handle
+  * @retval None
+  */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
+{
+  uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
+  uint32_t tmp_isr = hadc->Instance->ISR;
+  uint32_t tmp_ier = hadc->Instance->IER;
+  uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+  uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+  uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+
+  /* ========== Check End of Sampling flag for ADC group regular ========== */
+  if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
+  {
+    /* Update state machine on end of sampling status if not in error state */
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+    }
+
+    /* End Of Sampling callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->EndOfSamplingCallback(hadc);
+#else
+    HAL_ADCEx_EndOfSamplingCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear regular group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+  }
+
+  /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
+  if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
+      (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+  {
+    /* Update state machine on conversion status if not in error state */
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+    }
+
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going         */
+    /* to disable interruption.                                               */
+    if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+    {
+      /* Get relevant register CFGR in ADC instance of ADC master or slave    */
+      /* in function of multimode state (for devices with multimode           */
+      /* available).                                                          */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
+         )
+      {
+        /* check CONT bit directly in handle ADC CFGR register */
+        tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+      }
+      else
+      {
+        /* else need to check Master ADC CONT bit */
+        tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+        tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+      }
+#else
+      tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+      /* Carry on if continuous mode is disabled */
+      if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
+      {
+        /* If End of Sequence is reached, disable interrupts */
+        if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+        {
+          /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit         */
+          /* ADSTART==0 (no conversion on going)                              */
+          if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+          {
+            /* Disable ADC end of sequence conversion interrupt */
+            /* Note: Overrun interrupt was enabled with EOC interrupt in      */
+            /* HAL_Start_IT(), but is not disabled here because can be used   */
+            /* by overrun IRQ process below.                                  */
+            __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+            /* Set ADC state */
+            CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+            if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+            {
+              SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+            }
+          }
+          else
+          {
+            /* Change ADC state to error state */
+            SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+            /* Set ADC error code to ADC peripheral internal error */
+            SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+          }
+        }
+      }
+    }
+
+    /* Conversion complete callback */
+    /* Note: Into callback function "HAL_ADC_ConvCpltCallback()",             */
+    /*       to determine if conversion has been triggered from EOC or EOS,   */
+    /*       possibility to use:                                              */
+    /*        " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "               */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear regular group conversion flag */
+    /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
+    /*       conversion flags clear induces the release of the preserved data.*/
+    /*       Therefore, if the preserved data value is needed, it must be     */
+    /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+  }
+
+  /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
+  if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
+      (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
+  {
+    /* Update state machine on conversion status if not in error state */
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+    }
+
+    /* Retrieve ADC configuration */
+    tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+    tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+    /* Get relevant register CFGR in ADC instance of ADC master or slave  */
+    /* in function of multimode state (for devices with multimode         */
+    /* available).                                                        */
+#if defined(ADC_MULTIMODE_SUPPORT)
+    if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+        || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+        || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+       )
+    {
+      tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+    }
+    else
+    {
+      tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+      tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+    }
+#else
+    tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+    /* Disable interruption if no further conversion upcoming by injected     */
+    /* external trigger or by automatic injected conversion with regular      */
+    /* group having no further conversion upcoming (same conditions as        */
+    /* regular group interruption disabling above),                           */
+    /* and if injected scan sequence is completed.                            */
+    if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
+    {
+      if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
+          ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
+           (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
+      {
+        /* If End of Sequence is reached, disable interrupts */
+        if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+        {
+          /* Particular case if injected contexts queue is enabled:             */
+          /* when the last context has been fully processed, JSQR is reset      */
+          /* by the hardware. Even if no injected conversion is planned to come */
+          /* (queue empty, triggers are ignored), it can start again            */
+          /* immediately after setting a new context (JADSTART is still set).   */
+          /* Therefore, state of HAL ADC injected group is kept to busy.        */
+          if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+          {
+            /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit       */
+            /* JADSTART==0 (no conversion on going)                             */
+            if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+            {
+              /* Disable ADC end of sequence conversion interrupt  */
+              __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
+
+              /* Set ADC state */
+              CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+              if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+              {
+                SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+              }
+            }
+            else
+            {
+              /* Update ADC state machine to error */
+              SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+              /* Set ADC error code to ADC peripheral internal error */
+              SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+            }
+          }
+        }
+      }
+    }
+
+    /* Injected Conversion complete callback */
+    /* Note:  HAL_ADCEx_InjectedConvCpltCallback can resort to
+              if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
+              if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
+              interruption has been triggered by end of conversion or end of
+              sequence.    */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->InjectedConvCpltCallback(hadc);
+#else
+    HAL_ADCEx_InjectedConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear injected group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
+  }
+
+  /* ========== Check Analog watchdog 1 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+    /* Level out of window 1 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->LevelOutOfWindowCallback(hadc);
+#else
+    HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+  }
+
+  /* ========== Check analog watchdog 2 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+    /* Level out of window 2 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->LevelOutOfWindow2Callback(hadc);
+#else
+    HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+  }
+
+  /* ========== Check analog watchdog 3 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+    /* Level out of window 3 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->LevelOutOfWindow3Callback(hadc);
+#else
+    HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+  }
+
+  /* ========== Check Overrun flag ========== */
+  if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
+  {
+    /* If overrun is set to overwrite previous data (default setting),        */
+    /* overrun event is not considered as an error.                           */
+    /* (cf ref manual "Managing conversions without using the DMA and without */
+    /* overrun ")                                                             */
+    /* Exception for usage with DMA overrun event always considered as an     */
+    /* error.                                                                 */
+    if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+    {
+      overrun_error = 1UL;
+    }
+    else
+    {
+      /* Check DMA configuration */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
+      {
+        /* Multimode (when feature is available) is enabled,
+           Common Control Register MDMA bits must be checked. */
+        if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
+        {
+          overrun_error = 1UL;
+        }
+      }
+      else
+#endif /* ADC_MULTIMODE_SUPPORT */
+      {
+        /* Multimode not set or feature not available or ADC independent */
+        if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL)
+        {
+          overrun_error = 1UL;
+        }
+      }
+    }
+
+    if (overrun_error == 1UL)
+    {
+      /* Change ADC state to error state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+      /* Set ADC error code to overrun */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+      /* Error callback */
+      /* Note: In case of overrun, ADC conversion data is preserved until     */
+      /*       flag OVR is reset.                                             */
+      /*       Therefore, old ADC conversion data can be retrieved in         */
+      /*       function "HAL_ADC_ErrorCallback()".                            */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    }
+
+    /* Clear ADC overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  }
+
+  /* ========== Check Injected context queue overflow flag ========== */
+  if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
+  {
+    /* Change ADC state to overrun state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+    /* Set ADC error code to Injected context queue overflow */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+
+    /* Clear the Injected context queue overflow flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
+
+    /* Injected context queue overflow callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->InjectedQueueOverflowCallback(hadc);
+#else
+    HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  }
+
+}
+
+/**
+  * @brief  Conversion complete callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Conversion DMA half-transfer callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 1 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  ADC error callback in non-blocking mode
+  *         (ADC conversion with interruption or transfer by DMA).
+  * @note   In case of error due to overrun when using ADC with DMA transfer
+  *         (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+  *         - If needed, restart a new ADC conversion using function
+  *           "HAL_ADC_Start_DMA()"
+  *           (this function is also clearing overrun flag)
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ErrorCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure channels on regular group
+      (+) Configure the analog watchdog
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure a channel to be assigned to ADC group regular.
+  * @note   In case of usage of internal measurement channels:
+  *         Vbat/VrefInt/TempSensor.
+  *         These internal paths can be disabled using function
+  *         HAL_ADC_DeInit().
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes channel into ADC group regular,
+  *         following calls to this function can be used to reconfigure
+  *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
+  *         without resetting the ADC.
+  *         The setting of these parameters is conditioned to ADC state:
+  *         Refer to comments of structure "ADC_ChannelConfTypeDef".
+  * @param hadc ADC handle
+  * @param pConfig Structure of ADC channel assigned to ADC group regular.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmpOffsetShifted;
+  uint32_t tmp_config_internal_channel;
+  __IO uint32_t wait_loop_index = 0UL;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff));
+  assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber));
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset));
+
+  /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+     ignored (considered as reset) */
+  assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
+
+  /* Verification of channel number */
+  if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
+  {
+    assert_param(IS_ADC_CHANNEL(hadc, pConfig->Channel));
+  }
+  else
+  {
+    assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Channel number                                                        */
+  /*  - Channel rank                                                          */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Set ADC group regular sequence: channel on the selected scan sequence rank */
+    LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
+
+    /* Parameters update conditioned to ADC state:                              */
+    /* Parameters that can be updated when ADC is disabled or enabled without   */
+    /* conversion on going on regular group:                                    */
+    /*  - Channel sampling time                                                 */
+    /*  - Channel offset                                                        */
+    tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+    tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+    if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+        && (tmp_adc_is_conversion_on_going_injected == 0UL)
+       )
+    {
+      /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
+      if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
+      {
+        /* Set sampling time of the selected ADC channel */
+        LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
+
+        /* Set ADC sampling time common configuration */
+        LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
+      }
+      else
+      {
+        /* Set sampling time of the selected ADC channel */
+        LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
+
+        /* Set ADC sampling time common configuration */
+        LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
+      }
+
+      /* Configure the offset: offset enable/disable, channel, offset value */
+
+      /* Shift the offset with respect to the selected ADC resolution. */
+      /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+      tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
+
+      if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
+      {
+        /* Set ADC selected offset number */
+        LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted);
+
+        assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign));
+        assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation));
+        /* Set ADC selected offset sign & saturation */
+        LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign);
+        LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
+                                   (pConfig->OffsetSaturation == ENABLE) ?
+                                   LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
+      }
+      else
+      {
+        /* Scan each offset register to check if the selected channel is targeted. */
+        /* If this is the case, the corresponding offset number is disabled.       */
+        if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+            == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
+        {
+          LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
+        }
+        if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+            == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
+        {
+          LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
+        }
+        if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+            == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
+        {
+          LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
+        }
+        if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+            == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
+        {
+          LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
+        }
+      }
+    }
+
+    /* Parameters update conditioned to ADC state:                              */
+    /* Parameters that can be updated only when ADC is disabled:                */
+    /*  - Single or differential mode                                           */
+    if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+    {
+      /* Set mode single-ended or differential input of the selected ADC channel */
+      LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
+
+      /* Configuration of differential mode */
+      if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
+      {
+        /* Set sampling time of the selected ADC channel */
+        /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
+        LL_ADC_SetChannelSamplingTime(hadc->Instance,
+                                      (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
+                                                   (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel)
+                                                    + 1UL) & 0x1FUL)),
+                                      pConfig->SamplingTime);
+      }
+
+    }
+
+    /* Management of internal measurement channels: Vbat/VrefInt/TempSensor.  */
+    /* If internal channel selected, enable dedicated internal buffers and    */
+    /* paths.                                                                 */
+    /* Note: these internal measurement paths can be disabled using           */
+    /* HAL_ADC_DeInit().                                                      */
+
+    if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
+    {
+      tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+      /* If the requested internal measurement path has already been enabled, */
+      /* bypass the configuration processing.                                 */
+      if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5))
+          && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+      {
+        if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                         LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+          /* Delay for temperature sensor stabilization time */
+          /* Wait loop initialization and execution */
+          /* Note: Variable divided by 2 to compensate partially              */
+          /*       CPU processing cycles, scaling in us split to not          */
+          /*       exceed 32 bits register capacity and handle low frequency. */
+          wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+          while (wait_loop_index != 0UL)
+          {
+            wait_loop_index--;
+          }
+        }
+      }
+      else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
+               && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+      {
+        if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                         LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+        }
+      }
+      else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
+               && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+      {
+        if (ADC_VREFINT_INSTANCE(hadc))
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                         LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+        }
+      }
+      else
+      {
+        /* nothing to do */
+      }
+    }
+  }
+
+  /* If a conversion is on going on regular group, no update on regular       */
+  /* channel could be done on neither of the channel configuration structure  */
+  /* parameters.                                                              */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Configure the analog watchdog.
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the selected analog watchdog, successive
+  *         calls to this function can be used to reconfigure some parameters
+  *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
+  *         the ADC.
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure
+  *         "ADC_AnalogWDGConfTypeDef".
+  * @note   On this STM32 series, analog watchdog thresholds can be modified
+  *         while ADC conversion is on going.
+  *         In this case, some constraints must be taken into account:
+  *         the programmed threshold values are effective from the next
+  *         ADC EOC (end of unitary conversion).
+  *         Considering that registers write delay may happen due to
+  *         bus activity, this might cause an uncertainty on the
+  *         effective timing of the new programmed threshold values.
+  * @param hadc ADC handle
+  * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmp_awd_high_threshold_shifted;
+  uint32_t tmp_awd_low_threshold_shifted;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(pAnalogWDGConfig->FilteringConfig));
+  assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
+
+  if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
+      (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
+      (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
+  {
+    assert_param(IS_ADC_CHANNEL(hadc, pAnalogWDGConfig->Channel));
+  }
+
+  /* Verify thresholds range */
+  if (hadc->Init.OversamplingMode == ENABLE)
+  {
+    /* Case of oversampling enabled: depending on ratio and shift configuration,
+       analog watchdog thresholds can be higher than ADC resolution.
+       Verify if thresholds are within maximum thresholds range. */
+    assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->HighThreshold));
+    assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, pAnalogWDGConfig->LowThreshold));
+  }
+  else
+  {
+    /* Verify if thresholds are within the selected ADC resolution */
+    assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
+    assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on ADC groups regular and injected:                  */
+  /*  - Analog watchdog channels                                              */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+  if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    /* Analog watchdog configuration */
+    if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+    {
+      /* Configuration of analog watchdog:                                    */
+      /*  - Set the analog watchdog enable mode: one or overall group of      */
+      /*    channels, on groups regular and-or injected.                      */
+      switch (pAnalogWDGConfig->WatchdogMode)
+      {
+        case ADC_ANALOGWATCHDOG_SINGLE_REG:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+                                          __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+                                                                          LL_ADC_GROUP_REGULAR));
+          break;
+
+        case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+                                          __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+                                                                          LL_ADC_GROUP_INJECTED));
+          break;
+
+        case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+                                          __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
+                                                                          LL_ADC_GROUP_REGULAR_INJECTED));
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_REG:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_INJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+          break;
+
+        default: /* ADC_ANALOGWATCHDOG_NONE */
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
+          break;
+      }
+
+      /* Set the filtering configuration */
+      MODIFY_REG(hadc->Instance->TR1,
+                 ADC_TR1_AWDFILT,
+                 pAnalogWDGConfig->FilteringConfig);
+
+      /* Update state, clear previous result related to AWD1 */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+      /* Clear flag ADC analog watchdog */
+      /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+      /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+      /* (in case left enabled by previous ADC operations).                 */
+      LL_ADC_ClearFlag_AWD1(hadc->Instance);
+
+      /* Configure ADC analog watchdog interrupt */
+      if (pAnalogWDGConfig->ITMode == ENABLE)
+      {
+        LL_ADC_EnableIT_AWD1(hadc->Instance);
+      }
+      else
+      {
+        LL_ADC_DisableIT_AWD1(hadc->Instance);
+      }
+    }
+    /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
+    else
+    {
+      switch (pAnalogWDGConfig->WatchdogMode)
+      {
+        case ADC_ANALOGWATCHDOG_SINGLE_REG:
+        case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
+        case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
+          /* Update AWD by bitfield to keep the possibility to monitor        */
+          /* several channels by successive calls of this function.           */
+          if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+          {
+            SET_BIT(hadc->Instance->AWD2CR,
+                    (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
+          }
+          else
+          {
+            SET_BIT(hadc->Instance->AWD3CR,
+                    (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
+          }
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_REG:
+        case ADC_ANALOGWATCHDOG_ALL_INJEC:
+        case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance,
+                                          pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
+          break;
+
+        default: /* ADC_ANALOGWATCHDOG_NONE */
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
+          break;
+      }
+
+      if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+      {
+        /* Update state, clear previous result related to AWD2 */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+        /* Clear flag ADC analog watchdog */
+        /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+        /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+        /* (in case left enabled by previous ADC operations).                 */
+        LL_ADC_ClearFlag_AWD2(hadc->Instance);
+
+        /* Configure ADC analog watchdog interrupt */
+        if (pAnalogWDGConfig->ITMode == ENABLE)
+        {
+          LL_ADC_EnableIT_AWD2(hadc->Instance);
+        }
+        else
+        {
+          LL_ADC_DisableIT_AWD2(hadc->Instance);
+        }
+      }
+      /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+      else
+      {
+        /* Update state, clear previous result related to AWD3 */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+        /* Clear flag ADC analog watchdog */
+        /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+        /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+        /* (in case left enabled by previous ADC operations).                 */
+        LL_ADC_ClearFlag_AWD3(hadc->Instance);
+
+        /* Configure ADC analog watchdog interrupt */
+        if (pAnalogWDGConfig->ITMode == ENABLE)
+        {
+          LL_ADC_EnableIT_AWD3(hadc->Instance);
+        }
+        else
+        {
+          LL_ADC_DisableIT_AWD3(hadc->Instance);
+        }
+      }
+    }
+
+  }
+
+  /* Analog watchdog thresholds configuration */
+  if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+  {
+    /* Shift the offset with respect to the selected ADC resolution:        */
+    /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
+    /* are set to 0.                                                        */
+    tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
+    tmp_awd_low_threshold_shifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
+  }
+  /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
+  else
+  {
+    /* Shift the offset with respect to the selected ADC resolution:        */
+    /* Thresholds have to be left-aligned on bit 7, the LSB (right bits)    */
+    /* are set to 0.                                                        */
+    tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
+    tmp_awd_low_threshold_shifted  = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
+  }
+
+  /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+  LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, tmp_awd_high_threshold_shifted,
+                                  tmp_awd_low_threshold_shifted);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+  *  @brief    ADC Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral state and errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions to get in run-time the status of the
+    peripheral.
+      (+) Check the ADC state
+      (+) Check the ADC error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the ADC handle state.
+  * @note   ADC state machine is managed by bitfields, ADC status must be
+  *         compared with states bits.
+  *         For example:
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+  * @param hadc ADC handle
+  * @retval ADC handle state (bitfield on 32 bits)
+  */
+uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Return ADC handle state */
+  return hadc->State;
+}
+
+/**
+  * @brief  Return the ADC error code.
+  * @param hadc ADC handle
+  * @retval ADC error code (bitfield on 32 bits)
+  */
+uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  return hadc->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Stop ADC conversion.
+  * @param hadc ADC handle
+  * @param ConversionGroup ADC group regular and/or injected.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_REGULAR_GROUP           ADC regular conversion type.
+  *            @arg @ref ADC_INJECTED_GROUP          ADC injected conversion type.
+  *            @arg @ref ADC_REGULAR_INJECTED_GROUP  ADC regular and injected conversion type.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
+{
+  uint32_t tickstart;
+  uint32_t Conversion_Timeout_CPU_cycles = 0UL;
+  uint32_t conversion_group_reassigned = ConversionGroup;
+  uint32_t tmp_ADC_CR_ADSTART_JADSTART;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
+
+  /* Verification if ADC is not already stopped (on regular and injected      */
+  /* groups) to bypass this function if not needed.                           */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+  if ((tmp_adc_is_conversion_on_going_regular != 0UL)
+      || (tmp_adc_is_conversion_on_going_injected != 0UL)
+     )
+  {
+    /* Particular case of continuous auto-injection mode combined with        */
+    /* auto-delay mode.                                                       */
+    /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not   */
+    /* injected group stop ADC_CR_JADSTP).                                    */
+    /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1   */
+    /* (see reference manual).                                                */
+    if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
+        && (hadc->Init.ContinuousConvMode == ENABLE)
+        && (hadc->Init.LowPowerAutoWait == ENABLE)
+       )
+    {
+      /* Use stop of regular group */
+      conversion_group_reassigned = ADC_REGULAR_GROUP;
+
+      /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
+      while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
+      {
+        if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+        Conversion_Timeout_CPU_cycles ++;
+      }
+
+      /* Clear JEOS */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
+    }
+
+    /* Stop potential conversion on going on ADC group regular */
+    if (conversion_group_reassigned != ADC_INJECTED_GROUP)
+    {
+      /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+      if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+      {
+        if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+        {
+          /* Stop ADC group regular conversion */
+          LL_ADC_REG_StopConversion(hadc->Instance);
+        }
+      }
+    }
+
+    /* Stop potential conversion on going on ADC group injected */
+    if (conversion_group_reassigned != ADC_REGULAR_GROUP)
+    {
+      /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
+      if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+      {
+        if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+        {
+          /* Stop ADC group injected conversion */
+          LL_ADC_INJ_StopConversion(hadc->Instance);
+        }
+      }
+    }
+
+    /* Selection of start and stop bits with respect to the regular or injected group */
+    switch (conversion_group_reassigned)
+    {
+      case ADC_REGULAR_INJECTED_GROUP:
+        tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
+        break;
+      case ADC_INJECTED_GROUP:
+        tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
+        break;
+      /* Case ADC_REGULAR_GROUP only*/
+      default:
+        tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
+        break;
+    }
+
+    /* Wait for conversion effectively stopped */
+    tickstart = HAL_GetTick();
+
+    while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+  }
+
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC must be disabled
+  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
+{
+  uint32_t tickstart;
+  __IO uint32_t wait_loop_index = 0UL;
+
+  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
+  /* enabling phase not yet completed: flag ADC ready not yet set).           */
+  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
+  /* causes: ADC clock not running, ...).                                     */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    /* Check if conditions to enable the ADC are fulfilled */
+    if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+                               | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+      /* Set ADC error code to ADC peripheral internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+      return HAL_ERROR;
+    }
+
+    /* Enable the ADC peripheral */
+    LL_ADC_Enable(hadc->Instance);
+
+    if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
+         & LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
+    {
+      /* Delay for temperature sensor buffer stabilization time */
+      /* Note: Value LL_ADC_DELAY_TEMPSENSOR_STAB_US used instead of      */
+      /*       LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US because needed      */
+      /*       in case of ADC enable after a system wake up               */
+      /*       from low power mode.                                       */
+
+      /* Wait loop initialization and execution */
+      /* Note: Variable divided by 2 to compensate partially              */
+      /*       CPU processing cycles, scaling in us split to not          */
+      /*       exceed 32 bits register capacity and handle low frequency. */
+      wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+      while (wait_loop_index != 0UL)
+      {
+        wait_loop_index--;
+      }
+    }
+
+    /* Wait for ADC effectively enabled */
+    tickstart = HAL_GetTick();
+
+    while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+    {
+      /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
+          has been cleared (after a calibration), ADEN bit is reset by the
+          calibration logic.
+          The workaround is to continue setting ADEN until ADRDY is becomes 1.
+          Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+          4 ADC clock cycle duration */
+      /* Note: Test of ADC enabled required due to hardware constraint to     */
+      /*       not enable ADC if already enabled.                             */
+      if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+      {
+        LL_ADC_Enable(hadc->Instance);
+      }
+
+      if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC conversions must be
+  *         stopped.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
+{
+  uint32_t tickstart;
+  const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
+
+  /* Verification if ADC is not already disabled:                             */
+  /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
+  /*       disabled.                                                          */
+  if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+      && (tmp_adc_is_disable_on_going == 0UL)
+     )
+  {
+    /* Check if conditions to disable the ADC are fulfilled */
+    if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+    {
+      /* Disable the ADC peripheral */
+      LL_ADC_Disable(hadc->Instance);
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+    }
+    else
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+      /* Set ADC error code to ADC peripheral internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+      return HAL_ERROR;
+    }
+
+    /* Wait for ADC effectively disabled */
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+
+    while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DMA transfer complete callback.
+  * @param hdma pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Update state machine on conversion status if not in error state */
+  if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going         */
+    /* to disable interruption.                                               */
+    /* Is it the end of the regular sequence ? */
+    if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
+    {
+      /* Are conversions software-triggered ? */
+      if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+      {
+        /* Is CONT bit set ? */
+        if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
+        {
+          /* CONT bit is not set, no more conversions expected */
+          CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+          if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+          {
+            SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+          }
+        }
+      }
+    }
+    else
+    {
+      /* DMA End of Transfer interrupt was triggered but conversions sequence
+         is not over. If DMACFG is set to 0, conversions are stopped. */
+      if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL)
+      {
+        /* DMACFG bit is not set, conversions are stopped. */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+        if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
+        {
+          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+        }
+      }
+    }
+
+    /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  }
+  else /* DMA and-or internal error occurred */
+  {
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+    {
+      /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Call ADC DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback(hdma);
+    }
+  }
+}
+
+/**
+  * @brief  DMA half transfer complete callback.
+  * @param hdma pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ConvHalfCpltCallback(hadc);
+#else
+  HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA error callback.
+  * @param hdma pointer to DMA handle.
+  * @retval None
+  */
+void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+  /* Set ADC error code to DMA error */
+  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+  /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ErrorCallback(hadc);
+#else
+  HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c
new file mode 100644
index 0000000..06c5ece
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_adc_ex.c
@@ -0,0 +1,2384 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_adc_ex.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Analog to Digital Converter (ADC)
+  *          peripheral:
+  *           + Peripheral Control functions
+  *          Other functions (generic functions) are available in file
+  *          "stm32g4xx_hal_adc.c".
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  [..]
+  (@) Sections "ADC peripheral features" and "How to use this driver" are
+      available in file of generic functions "stm32g4xx_hal_adc.c".
+  [..]
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADCEx ADCEx
+  * @brief ADC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+  * @{
+  */
+
+#define ADC_JSQR_FIELDS      ((ADC_JSQR_JL | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN |\
+                               ADC_JSQR_JSQ1  | ADC_JSQR_JSQ2 |\
+                               ADC_JSQR_JSQ3 | ADC_JSQR_JSQ4 ))           /*!< ADC_JSQR fields of parameters that can
+                             be updated anytime once the ADC is enabled */
+
+/* Fixed timeout value for ADC calibration.                                   */
+/* Values defined to be higher than worst cases: low clock frequency,         */
+/* maximum prescalers.                                                        */
+/* Ex of profile low frequency : f_ADC at f_CPU/3968 (minimum value           */
+/* considering both possible ADC clocking scheme:                             */
+/*        - ADC clock from synchronous clock with AHB prescaler 512,          */
+/*          ADC prescaler 4.                                                  */
+/*           Ratio max = 512 *4 = 2048                                        */
+/*        - ADC clock from asynchronous clock (PLLP) with prescaler 256.      */
+/*          Highest CPU clock PLL (PLLR).                                     */
+/*           Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256    */
+/*                     = 3968 )                                               */
+/* Calibration_time MAX = 81 / f_ADC                                          */
+/*                      = 81 / (f_CPU/3938) = 318978 CPU cycles               */
+#define ADC_CALIBRATION_TIMEOUT         (318978UL)   /*!< ADC calibration time-out value (unit: CPU cycles) */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
+  * @brief    Extended IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+      (+) Perform the ADC self-calibration for single or differential ending.
+      (+) Get calibration factors for single or differential ending.
+      (+) Set calibration factors for single or differential ending.
+
+      (+) Start conversion of ADC group injected.
+      (+) Stop conversion of ADC group injected.
+      (+) Poll for conversion complete on ADC group injected.
+      (+) Get result of ADC group injected channel conversion.
+      (+) Start conversion of ADC group injected and enable interruptions.
+      (+) Stop conversion of ADC group injected and disable interruptions.
+
+      (+) When multimode feature is available, start multimode and enable DMA transfer.
+      (+) Stop multimode and disable ADC DMA transfer.
+      (+) Get result of multimode conversion.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Perform an ADC automatic self-calibration
+  *         Calibration prerequisite: ADC must be disabled (execute this
+  *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+  * @param  hadc       ADC handle
+  * @param  SingleDiff Selection of single-ended or differential input
+  *         This parameter can be one of the following values:
+  *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
+  *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  __IO uint32_t wait_loop_index = 0UL;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Calibration prerequisite: ADC must be disabled. */
+
+  /* Disable the ADC (if not already disabled) */
+  tmp_hal_status = ADC_Disable(hadc);
+
+  /* Check if ADC is effectively disabled */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+
+    /* Start ADC calibration in mode single-ended or differential */
+    LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
+
+    /* Wait for calibration completion */
+    while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
+    {
+      wait_loop_index++;
+      if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_BUSY_INTERNAL,
+                          HAL_ADC_STATE_ERROR_INTERNAL);
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+
+        return HAL_ERROR;
+      }
+    }
+
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_BUSY_INTERNAL,
+                      HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    /* Note: No need to update variable "tmp_hal_status" here: already set    */
+    /*       to state "HAL_ERROR" by function disabling the ADC.              */
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get the calibration factor.
+  * @param hadc ADC handle.
+  * @param SingleDiff This parameter can be only:
+  *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
+  *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+  * @retval Calibration value.
+  */
+uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+
+  /* Return the selected ADC calibration value */
+  return LL_ADC_GetCalibrationFactor(hadc->Instance, SingleDiff);
+}
+
+/**
+  * @brief  Set the calibration factor to overwrite automatic conversion result.
+  *         ADC must be enabled and no conversion is ongoing.
+  * @param hadc ADC handle
+  * @param SingleDiff This parameter can be only:
+  *           @arg @ref ADC_SINGLE_ENDED       Channel in mode input single ended
+  *           @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
+  * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+  * @retval HAL state
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
+                                                 uint32_t CalibrationFactor)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
+  assert_param(IS_ADC_CALFACT(CalibrationFactor));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Verification of hardware constraints before modifying the calibration    */
+  /* factors register: ADC must be enabled, no conversion on going.           */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+  if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+      && (tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    /* Set the selected ADC calibration value */
+    LL_ADC_SetCalibrationFactor(hadc->Instance, SingleDiff, CalibrationFactor);
+  }
+  else
+  {
+    /* Update ADC state machine */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    /* Update ADC error code */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+    /* Update ADC state machine to error */
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of injected group.
+  * @note   Interruptions enabled in this function: None.
+  * @note   Case of multimode enabled when multimode feature is available:
+  *         HAL_ADCEx_InjectedStart() API must be called for ADC slave first,
+  *         then for ADC master.
+  *         For ADC slave, ADC is enabled only (conversion is not started).
+  *         For ADC master, ADC is enabled and multimode conversion is started.
+  * @param hadc ADC handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tmp_config_injected_queue;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+  {
+    return HAL_BUSY;
+  }
+  else
+  {
+    /* In case of software trigger detection enabled, JQDIS must be set
+      (which can be done only if ADSTART and JADSTART are both cleared).
+       If JQDIS is not set at that point, returns an error
+       - since software trigger detection is disabled. User needs to
+       resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+       - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+         the queue is empty */
+    tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+    if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
+        && (tmp_config_injected_queue == 0UL)
+       )
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      return HAL_ERROR;
+    }
+
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Check if a regular conversion is ongoing */
+      if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
+      {
+        /* Reset ADC error code field related to injected conversions only */
+        CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+      }
+      else
+      {
+        /* Set ADC error code to none */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to injected group conversion results  */
+      /* - Set state bitfield related to injected operation                   */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+                        HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - if ADC instance is master or if multimode feature is not available
+        - if multimode setting is disabled (ADC instance slave in independent mode) */
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+         )
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+      /* Clear ADC group injected group conversion flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable conversion of injected group, if automatic injected conversion  */
+      /* is disabled.                                                           */
+      /* If software start has been selected, conversion starts immediately.    */
+      /* If external trigger has been selected, conversion will start at next   */
+      /* trigger event.                                                         */
+      /* Case of multimode enabled (when multimode feature is available):       */
+      /* if ADC is slave,                                                       */
+      /*    - ADC is enabled only (conversion is not started),                  */
+      /*    - if multimode only concerns regular conversion, ADC is enabled     */
+      /*     and conversion is started.                                         */
+      /* If ADC is master or independent,                                       */
+      /*    - ADC is enabled and conversion is started.                         */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+         )
+      {
+        /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+        if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+        {
+          LL_ADC_INJ_StartConversion(hadc->Instance);
+        }
+      }
+      else
+      {
+        /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#else
+      if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+      {
+        /* Start ADC group injected conversion */
+        LL_ADC_INJ_StartConversion(hadc->Instance);
+      }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+
+    /* Return function status */
+    return tmp_hal_status;
+  }
+}
+
+/**
+  * @brief  Stop conversion of injected channels. Disable ADC peripheral if
+  *         no regular conversion is on going.
+  * @note   If ADC must be disabled and if conversion is on going on
+  *         regular group, function HAL_ADC_Stop must be used to stop both
+  *         injected and regular groups, and disable the ADC.
+  * @note   If injected group mode auto-injection is enabled,
+  *         function HAL_ADC_Stop must be used.
+  * @note   In case of multimode enabled (when multimode feature is available),
+  *         HAL_ADCEx_InjectedStop() must be called for ADC master first, then for ADC slave.
+  *         For ADC master, conversion is stopped and ADC is disabled.
+  *         For ADC slave, ADC is disabled only (conversion stop of ADC master
+  *         has already stopped conversion of ADC slave).
+  * @param hadc ADC handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going on injected group only. */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if injected conversions are effectively stopped   */
+  /* and if no conversion on regular group is on-going                       */
+  if (tmp_hal_status == HAL_OK)
+  {
+    if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      /* 2. Disable the ADC peripheral */
+      tmp_hal_status = ADC_Disable(hadc);
+
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    /* Conversion on injected group is stopped, but ADC not disabled since    */
+    /* conversion on regular group is still running.                          */
+    else
+    {
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Wait for injected group conversion to be completed.
+  * @param hadc ADC handle
+  * @param Timeout Timeout value in millisecond.
+  * @note   Depending on hadc->Init.EOCSelection, JEOS or JEOC is
+  *         checked and cleared depending on AUTDLY bit status.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t tmp_flag_end;
+  uint32_t tmp_adc_inj_is_trigger_source_sw_start;
+  uint32_t tmp_adc_reg_is_trigger_source_sw_start;
+  uint32_t tmp_cfgr;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  const ADC_TypeDef *tmpADC_Master;
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* If end of sequence selected */
+  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+  {
+    tmp_flag_end = ADC_FLAG_JEOS;
+  }
+  else /* end of conversion selected */
+  {
+    tmp_flag_end = ADC_FLAG_JEOC;
+  }
+
+  /* Get timeout */
+  tickstart = HAL_GetTick();
+
+  /* Wait until End of Conversion or Sequence flag is raised */
+  while ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if ((hadc->Instance->ISR & tmp_flag_end) == 0UL)
+        {
+          /* Update ADC state machine to timeout */
+          SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Retrieve ADC configuration */
+  tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
+  tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
+  /* Get relevant register CFGR in ADC instance of ADC master or slave  */
+  /* in function of multimode state (for devices with multimode         */
+  /* available).                                                        */
+#if defined(ADC_MULTIMODE_SUPPORT)
+  if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+      || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+      || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+      || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+     )
+  {
+    tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+  }
+  else
+  {
+    tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
+    tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
+  }
+#else
+  tmp_cfgr = READ_REG(hadc->Instance->CFGR);
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
+
+  /* Determine whether any further conversion upcoming on group injected      */
+  /* by external trigger or by automatic injected conversion                  */
+  /* from group regular.                                                      */
+  if ((tmp_adc_inj_is_trigger_source_sw_start != 0UL)            ||
+      ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL)      &&
+       ((tmp_adc_reg_is_trigger_source_sw_start != 0UL)  &&
+        (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL))))
+  {
+    /* Check whether end of sequence is reached */
+    if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
+    {
+      /* Particular case if injected contexts queue is enabled:             */
+      /* when the last context has been fully processed, JSQR is reset      */
+      /* by the hardware. Even if no injected conversion is planned to come */
+      /* (queue empty, triggers are ignored), it can start again            */
+      /* immediately after setting a new context (JADSTART is still set).   */
+      /* Therefore, state of HAL ADC injected group is kept to busy.        */
+      if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
+      {
+        /* Set ADC state */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+
+        if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
+        {
+          SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+        }
+      }
+    }
+  }
+
+  /* Clear polled flag */
+  if (tmp_flag_end == ADC_FLAG_JEOS)
+  {
+    /* Clear end of sequence JEOS flag of injected group if low power feature */
+    /* "LowPowerAutoWait " is disabled, to not interfere with this feature.   */
+    /* For injected groups, no new conversion will start before JEOS is       */
+    /* cleared.                                                               */
+    if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
+    {
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+    }
+  }
+  else
+  {
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
+  }
+
+  /* Return API HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of injected group with interruption.
+  * @note   Interruptions enabled in this function according to initialization
+  *         setting : JEOC (end of conversion) or JEOS (end of sequence)
+  * @note   Case of multimode enabled (when multimode feature is enabled):
+  *         HAL_ADCEx_InjectedStart_IT() API must be called for ADC slave first,
+  *         then for ADC master.
+  *         For ADC slave, ADC is enabled only (conversion is not started).
+  *         For ADC master, ADC is enabled and multimode conversion is started.
+  * @param hadc ADC handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tmp_config_injected_queue;
+#if defined(ADC_MULTIMODE_SUPPORT)
+  uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
+  {
+    return HAL_BUSY;
+  }
+  else
+  {
+    /* In case of software trigger detection enabled, JQDIS must be set
+      (which can be done only if ADSTART and JADSTART are both cleared).
+       If JQDIS is not set at that point, returns an error
+       - since software trigger detection is disabled. User needs to
+       resort to HAL_ADCEx_DisableInjectedQueue() API to set JQDIS.
+       - or (if JQDIS is intentionally reset) since JEXTEN = 0 which means
+         the queue is empty */
+    tmp_config_injected_queue = READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+    if ((READ_BIT(hadc->Instance->JSQR, ADC_JSQR_JEXTEN) == 0UL)
+        && (tmp_config_injected_queue == 0UL)
+       )
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+      return HAL_ERROR;
+    }
+
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Check if a regular conversion is ongoing */
+      if ((hadc->State & HAL_ADC_STATE_REG_BUSY) != 0UL)
+      {
+        /* Reset ADC error code field related to injected conversions only */
+        CLEAR_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
+      }
+      else
+      {
+        /* Set ADC error code to none */
+        ADC_CLEAR_ERRORCODE(hadc);
+      }
+
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to injected group conversion results  */
+      /* - Set state bitfield related to injected operation                   */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC,
+                        HAL_ADC_STATE_INJ_BUSY);
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+      /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
+        - if ADC instance is master or if multimode feature is not available
+        - if multimode setting is disabled (ADC instance slave in independent mode) */
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+         )
+      {
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+      /* Clear ADC group injected group conversion flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JEOC | ADC_FLAG_JEOS));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable ADC Injected context queue overflow interrupt if this feature   */
+      /* is enabled.                                                            */
+      if ((hadc->Instance->CFGR & ADC_CFGR_JQM) != 0UL)
+      {
+        __HAL_ADC_ENABLE_IT(hadc, ADC_FLAG_JQOVF);
+      }
+
+      /* Enable ADC end of conversion interrupt */
+      switch (hadc->Init.EOCSelection)
+      {
+        case ADC_EOC_SEQ_CONV:
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
+          break;
+        /* case ADC_EOC_SINGLE_CONV */
+        default:
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
+          break;
+      }
+
+      /* Enable conversion of injected group, if automatic injected conversion  */
+      /* is disabled.                                                           */
+      /* If software start has been selected, conversion starts immediately.    */
+      /* If external trigger has been selected, conversion will start at next   */
+      /* trigger event.                                                         */
+      /* Case of multimode enabled (when multimode feature is available):       */
+      /* if ADC is slave,                                                       */
+      /*    - ADC is enabled only (conversion is not started),                  */
+      /*    - if multimode only concerns regular conversion, ADC is enabled     */
+      /*     and conversion is started.                                         */
+      /* If ADC is master or independent,                                       */
+      /*    - ADC is enabled and conversion is started.                         */
+#if defined(ADC_MULTIMODE_SUPPORT)
+      if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
+          || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
+          || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
+         )
+      {
+        /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+        if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+        {
+          LL_ADC_INJ_StartConversion(hadc->Instance);
+        }
+      }
+      else
+      {
+        /* ADC instance is not a multimode slave instance with multimode injected conversions enabled */
+        SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
+      }
+#else
+      if (LL_ADC_INJ_GetTrigAuto(hadc->Instance) == LL_ADC_INJ_TRIG_INDEPENDENT)
+      {
+        /* Start ADC group injected conversion */
+        LL_ADC_INJ_StartConversion(hadc->Instance);
+      }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+
+    /* Return function status */
+    return tmp_hal_status;
+  }
+}
+
+/**
+  * @brief  Stop conversion of injected channels, disable interruption of
+  *         end-of-conversion. Disable ADC peripheral if no regular conversion
+  *         is on going.
+  * @note   If ADC must be disabled and if conversion is on going on
+  *         regular group, function HAL_ADC_Stop must be used to stop both
+  *         injected and regular groups, and disable the ADC.
+  * @note   If injected group mode auto-injection is enabled,
+  *         function HAL_ADC_Stop must be used.
+  * @note   Case of multimode enabled (when multimode feature is available):
+  *         HAL_ADCEx_InjectedStop_IT() API must be called for ADC master first,
+  *         then for ADC slave.
+  *         For ADC master, conversion is stopped and ADC is disabled.
+  *         For ADC slave, ADC is disabled only (conversion stop of ADC master
+  *         has already stopped conversion of ADC slave).
+  * @note   In case of auto-injection mode, HAL_ADC_Stop() must be used.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going on injected group only. */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if injected conversions are effectively stopped   */
+  /* and if no conversion on the other group (regular group) is intended to   */
+  /* continue.                                                                */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC end of conversion interrupt for injected channels */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_JEOC | ADC_IT_JEOS | ADC_FLAG_JQOVF));
+
+    if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      /* 2. Disable the ADC peripheral */
+      tmp_hal_status = ADC_Disable(hadc);
+
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    /* Conversion on injected group is stopped, but ADC not disabled since    */
+    /* conversion on regular group is still running.                          */
+    else
+    {
+      /* Set ADC state */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Enable ADC, start MultiMode conversion and transfer regular results through DMA.
+  * @note   Multimode must have been previously configured using
+  *         HAL_ADCEx_MultiModeConfigChannel() function.
+  *         Interruptions enabled in this function:
+  *          overrun, DMA half transfer, DMA transfer complete.
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   State field of Slave ADC handle is not updated in this configuration:
+  *          user should not rely on it for information related to Slave regular
+  *         conversions.
+  * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+  * @param pData Destination Buffer address.
+  * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  ADC_HandleTypeDef tmp_hadc_slave;
+  ADC_Common_TypeDef *tmpADC_Common;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+  {
+    return HAL_BUSY;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Temporary handle minimum initialization */
+    __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
+    ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
+
+    /* Set a temporary handle of the ADC slave associated to the ADC master   */
+    ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
+
+    if (tmp_hadc_slave.Instance == NULL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+
+      return HAL_ERROR;
+    }
+
+    /* Enable the ADC peripherals: master and slave (in case if not already   */
+    /* enabled previously)                                                    */
+    tmp_hal_status = ADC_Enable(hadc);
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmp_hal_status = ADC_Enable(&tmp_hadc_slave);
+    }
+
+    /* Start multimode conversion of ADCs pair */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        (HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP),
+                        HAL_ADC_STATE_REG_BUSY);
+
+      /* Set ADC error code to none */
+      ADC_CLEAR_ERRORCODE(hadc);
+
+      /* Set the DMA transfer complete callback */
+      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+      /* Set the DMA half transfer complete callback */
+      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+      /* Set the DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ;
+
+      /* Pointer to the common control register  */
+      tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+      /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
+      /* start (in case of SW start):                                           */
+
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable ADC overrun interrupt */
+      __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+      /* Start the DMA channel */
+      tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length);
+
+      /* Enable conversion of regular group.                                    */
+      /* If software start has been selected, conversion starts immediately.    */
+      /* If external trigger has been selected, conversion will start at next   */
+      /* trigger event.                                                         */
+      /* Start ADC group regular conversion */
+      LL_ADC_REG_StartConversion(hadc->Instance);
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+
+    /* Return function status */
+    return tmp_hal_status;
+  }
+}
+
+/**
+  * @brief  Stop multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral.
+  * @note   Multimode is kept enabled after this function. MultiMode DMA bits
+  *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+  *         Multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+  *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+  *         resort to HAL_ADCEx_DisableMultiMode() API.
+  * @note   In case of DMA configured in circular mode, function
+  *         HAL_ADC_Stop_DMA() must be called after this function with handle of
+  *         ADC slave, to properly disable the DMA channel.
+  * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tickstart;
+  ADC_HandleTypeDef tmp_hadc_slave;
+  uint32_t tmp_hadc_slave_conversion_on_going;
+  HAL_StatusTypeDef tmp_hadc_slave_disable_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential multimode conversion on going, on regular and injected groups */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Temporary handle minimum initialization */
+    __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
+    ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
+
+    /* Set a temporary handle of the ADC slave associated to the ADC master   */
+    ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
+
+    if (tmp_hadc_slave.Instance == NULL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+
+      return HAL_ERROR;
+    }
+
+    /* Procedure to disable the ADC peripheral: wait for conversions          */
+    /* effectively stopped (ADC master and ADC slave), then disable ADC       */
+
+    /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+    tickstart = HAL_GetTick();
+
+    tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+    while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+           || (tmp_hadc_slave_conversion_on_going == 1UL)
+          )
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+        if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+            || (tmp_hadc_slave_conversion_on_going == 1UL)
+           )
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_ERROR;
+        }
+      }
+
+      tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+    }
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    /* Note: DMA channel of ADC slave should be stopped after this function   */
+    /*       with HAL_ADC_Stop_DMA() API.                                     */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status == HAL_ERROR)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripherals: master and slave */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+    /* memory a potential failing status.                                     */
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmp_hadc_slave_disable_status = ADC_Disable(&tmp_hadc_slave);
+      if ((ADC_Disable(hadc) == HAL_OK)           &&
+          (tmp_hadc_slave_disable_status == HAL_OK))
+      {
+        tmp_hal_status = HAL_OK;
+      }
+    }
+    else
+    {
+      /* In case of error, attempt to disable ADC master and slave without status assert */
+      (void) ADC_Disable(hadc);
+      (void) ADC_Disable(&tmp_hadc_slave);
+    }
+
+    /* Set ADC state (ADC master) */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
+                      HAL_ADC_STATE_READY);
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Return the last ADC Master and Slave regular conversions results when in multimode configuration.
+  * @param hadc ADC handle of ADC Master (handle of ADC Slave must not be used)
+  * @retval The converted data values.
+  */
+uint32_t HAL_ADCEx_MultiModeGetValue(const ADC_HandleTypeDef *hadc)
+{
+  const ADC_Common_TypeDef *tmpADC_Common;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+  /* Prevent unused argument(s) compilation warning if no assert_param check */
+  /* and possible no usage in __LL_ADC_COMMON_INSTANCE() below               */
+  UNUSED(hadc);
+
+  /* Pointer to the common control register  */
+  tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+  /* Return the multi mode conversion value */
+  return tmpADC_Common->CDR;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Get ADC injected group conversion result.
+  * @note   Reading register JDRx automatically clears ADC flag JEOC
+  *         (ADC group injected end of unitary conversion).
+  * @note   This function does not clear ADC flag JEOS
+  *         (ADC group injected end of sequence conversion)
+  *         Occurrence of flag JEOS rising:
+  *          - If sequencer is composed of 1 rank, flag JEOS is equivalent
+  *            to flag JEOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag JEOC only is raised, at the end of the scan sequence
+  *            both flags JEOC and EOS are raised.
+  *         Flag JEOS must not be cleared by this function because
+  *         it would not be compliant with low power features
+  *         (feature low power auto-wait, not available on all STM32 series).
+  *         To clear this flag, either use function:
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADCEx_InjectedPollForConversion()
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
+  * @param hadc ADC handle
+  * @param InjectedRank the converted ADC injected rank.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_INJECTED_RANK_1 ADC group injected rank 1
+  *            @arg @ref ADC_INJECTED_RANK_2 ADC group injected rank 2
+  *            @arg @ref ADC_INJECTED_RANK_3 ADC group injected rank 3
+  *            @arg @ref ADC_INJECTED_RANK_4 ADC group injected rank 4
+  * @retval ADC group injected conversion data
+  */
+uint32_t HAL_ADCEx_InjectedGetValue(const ADC_HandleTypeDef *hadc, uint32_t InjectedRank)
+{
+  uint32_t tmp_jdr;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
+
+  /* Get ADC converted value */
+  switch (InjectedRank)
+  {
+    case ADC_INJECTED_RANK_4:
+      tmp_jdr = hadc->Instance->JDR4;
+      break;
+    case ADC_INJECTED_RANK_3:
+      tmp_jdr = hadc->Instance->JDR3;
+      break;
+    case ADC_INJECTED_RANK_2:
+      tmp_jdr = hadc->Instance->JDR2;
+      break;
+    case ADC_INJECTED_RANK_1:
+    default:
+      tmp_jdr = hadc->Instance->JDR1;
+      break;
+  }
+
+  /* Return ADC converted value */
+  return tmp_jdr;
+}
+
+/**
+  * @brief  Injected conversion complete callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_InjectedConvCpltCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Injected context queue overflow callback.
+  * @note   This callback is called if injected context queue is enabled
+            (parameter "QueueInjectedContext" in injected channel configuration)
+            and if a new injected context is set when queue is full (maximum 2
+            contexts).
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_InjectedQueueOverflowCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 2 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 3 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
+  */
+}
+
+
+/**
+  * @brief  End Of Sampling callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected channels in
+  *         case of auto_injection mode), disable ADC peripheral if no
+  *         conversion is on going on injected group.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+  /* Disable ADC peripheral if regular conversions are effectively stopped
+     and if no injected conversions are on-going */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+    if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      /* 2. Disable the ADC peripheral */
+      tmp_hal_status = ADC_Disable(hadc);
+
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    /* Conversion on injected group is stopped, but ADC not disabled since    */
+    /* conversion on regular group is still running.                          */
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+/**
+  * @brief  Stop ADC conversion of ADC groups regular and injected,
+  *         disable interrution of end-of-conversion,
+  *         disable ADC peripheral if no conversion is on going
+  *         on injected group.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped
+    and if no injected conversion is on-going */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+    /* Disable all regular-related interrupts */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+    /* 2. Disable ADC peripheral if no injected conversions are on-going */
+    if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      tmp_hal_status = ADC_Disable(hadc);
+      /* if no issue reported */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable ADC DMA transfer, disable
+  *         ADC peripheral if no conversion is on going
+  *         on injected group.
+  * @note   HAL_ADCEx_RegularStop_DMA() function is dedicated to single-ADC mode only.
+  *         For multimode (when multimode feature is available),
+  *         HAL_ADCEx_RegularMultiModeStop_DMA() API must be used.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped
+     and if no injected conversion is on-going */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+    /* Disable ADC DMA (ADC DMA configuration ADC_CFGR_DMACFG is kept) */
+    CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
+    /* while DMA transfer is on going)                                        */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status != HAL_OK)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripheral */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
+    /* to keep in memory a potential failing status.                          */
+    if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+    {
+      if (tmp_hal_status == HAL_OK)
+      {
+        tmp_hal_status = ADC_Disable(hadc);
+      }
+      else
+      {
+        (void)ADC_Disable(hadc);
+      }
+
+      /* Check if ADC is effectively disabled */
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_INJ_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+    }
+    else
+    {
+      SET_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Stop DMA-based multimode ADC conversion, disable ADC DMA transfer, disable ADC peripheral if no injected
+  *         conversion is on-going.
+  * @note   Multimode is kept enabled after this function. Multimode DMA bits
+  *         (MDMA and DMACFG bits of common CCR register) are maintained. To disable
+  *         multimode (set with HAL_ADCEx_MultiModeConfigChannel()), ADC must be
+  *         reinitialized using HAL_ADC_Init() or HAL_ADC_DeInit(), or the user can
+  *         resort to HAL_ADCEx_DisableMultiMode() API.
+  * @note   In case of DMA configured in circular mode, function
+  *         HAL_ADCEx_RegularStop_DMA() must be called after this function with handle of
+  *         ADC slave, to properly disable the DMA channel.
+  * @param hadc ADC handle of ADC master (handle of ADC slave must not be used)
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tickstart;
+  ADC_HandleTypeDef tmp_hadc_slave;
+  uint32_t tmp_hadc_slave_conversion_on_going;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+
+  /* 1. Stop potential multimode conversion on going, on regular groups */
+  tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_GROUP);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Clear HAL_ADC_STATE_REG_BUSY bit */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
+
+    /* Temporary handle minimum initialization */
+    __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
+    ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
+
+    /* Set a temporary handle of the ADC slave associated to the ADC master   */
+    ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
+
+    if (tmp_hadc_slave.Instance == NULL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+
+      return HAL_ERROR;
+    }
+
+    /* Procedure to disable the ADC peripheral: wait for conversions          */
+    /* effectively stopped (ADC master and ADC slave), then disable ADC       */
+
+    /* 1. Wait for ADC conversion completion for ADC master and ADC slave */
+    tickstart = HAL_GetTick();
+
+    tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+    while ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+           || (tmp_hadc_slave_conversion_on_going == 1UL)
+          )
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+        if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 1UL)
+            || (tmp_hadc_slave_conversion_on_going == 1UL)
+           )
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Process unlocked */
+          __HAL_UNLOCK(hadc);
+
+          return HAL_ERROR;
+        }
+      }
+
+      tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+    }
+
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    /* Note: DMA channel of ADC slave should be stopped after this function   */
+    /* with HAL_ADCEx_RegularStop_DMA() API.                                  */
+    tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+    /* Check if DMA channel effectively disabled */
+    if (tmp_hal_status != HAL_OK)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripherals: master and slave if no injected        */
+    /*   conversion is on-going.                                              */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep in */
+    /* memory a potential failing status.                                     */
+    if (tmp_hal_status == HAL_OK)
+    {
+      if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+      {
+        tmp_hal_status =  ADC_Disable(hadc);
+        if (tmp_hal_status == HAL_OK)
+        {
+          if (LL_ADC_INJ_IsConversionOngoing((&tmp_hadc_slave)->Instance) == 0UL)
+          {
+            tmp_hal_status =  ADC_Disable(&tmp_hadc_slave);
+          }
+        }
+      }
+
+      if (tmp_hal_status == HAL_OK)
+      {
+        /* Both Master and Slave ADC's could be disabled. Update Master State */
+        /* Clear HAL_ADC_STATE_INJ_BUSY bit, set HAL_ADC_STATE_READY bit */
+        ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY, HAL_ADC_STATE_READY);
+      }
+      else
+      {
+        /* injected (Master or Slave) conversions are still on-going,
+           no Master State change */
+      }
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group2 ADC Extended Peripheral Control functions
+  * @brief    ADC Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure channels on injected group
+      (+) Configure multimode when multimode feature is available
+      (+) Enable or Disable Injected Queue
+      (+) Disable ADC voltage regulator
+      (+) Enter ADC deep-power-down mode
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure a channel to be assigned to ADC group injected.
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes injected group, following calls to this
+  *         function can be used to reconfigure some parameters of structure
+  *         "ADC_InjectionConfTypeDef" on the fly, without resetting the ADC.
+  *         The setting of these parameters is conditioned to ADC state:
+  *         Refer to comments of structure "ADC_InjectionConfTypeDef".
+  * @note   In case of usage of internal measurement channels:
+  *         Vbat/VrefInt/TempSensor.
+  *         These internal paths can be disabled using function
+  *         HAL_ADC_DeInit().
+  * @note   Caution: For Injected Context Queue use, a context must be fully
+  *         defined before start of injected conversion. All channels are configured
+  *         consecutively for the same ADC instance. Therefore, the number of calls to
+  *         HAL_ADCEx_InjectedConfigChannel() must be equal to the value of parameter
+  *         InjectedNbrOfConversion for each context.
+  *  - Example 1: If 1 context is intended to be used (or if there is no use of the
+  *    Injected Queue Context feature) and if the context contains 3 injected ranks
+  *    (InjectedNbrOfConversion = 3), HAL_ADCEx_InjectedConfigChannel() must be
+  *    called once for each channel (i.e. 3 times) before starting a conversion.
+  *    This function must not be called to configure a 4th injected channel:
+  *    it would start a new context into context queue.
+  *  - Example 2: If 2 contexts are intended to be used and each of them contains
+  *    3 injected ranks (InjectedNbrOfConversion = 3),
+  *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and
+  *    for each context (3 channels x 2 contexts = 6 calls). Conversion can
+  *    start once the 1st context is set, that is after the first three
+  *    HAL_ADCEx_InjectedConfigChannel() calls. The 2nd context can be set on the fly.
+  * @param hadc ADC handle
+  * @param pConfigInjected Structure of ADC injected group and ADC channel for
+  *         injected group.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,
+                                                  const ADC_InjectionConfTypeDef *pConfigInjected)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmp_offset_shifted;
+  uint32_t tmp_config_internal_channel;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+  __IO uint32_t wait_loop_index = 0;
+
+  uint32_t tmp_jsqr_context_queue_being_built = 0U;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_SAMPLE_TIME(pConfigInjected->InjectedSamplingTime));
+  assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfigInjected->InjectedSingleDiff));
+  assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->AutoInjectedConv));
+  assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->QueueInjectedContext));
+  assert_param(IS_ADC_EXTTRIGINJEC_EDGE(pConfigInjected->ExternalTrigInjecConvEdge));
+  assert_param(IS_ADC_EXTTRIGINJEC(hadc, pConfigInjected->ExternalTrigInjecConv));
+  assert_param(IS_ADC_OFFSET_NUMBER(pConfigInjected->InjectedOffsetNumber));
+  assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfigInjected->InjectedOffset));
+  assert_param(IS_ADC_OFFSET_SIGN(pConfigInjected->InjectedOffsetSign));
+  assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedOffsetSaturation));
+  assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjecOversamplingMode));
+
+  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+  {
+    assert_param(IS_ADC_INJECTED_RANK(pConfigInjected->InjectedRank));
+    assert_param(IS_ADC_INJECTED_NB_CONV(pConfigInjected->InjectedNbrOfConversion));
+    assert_param(IS_FUNCTIONAL_STATE(pConfigInjected->InjectedDiscontinuousConvMode));
+  }
+
+
+  /* if JOVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
+     ignored (considered as reset) */
+  assert_param(!((pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
+                 && (pConfigInjected->InjecOversamplingMode == ENABLE)));
+
+  /* JDISCEN and JAUTO bits can't be set at the same time  */
+  assert_param(!((pConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
+                 && (pConfigInjected->AutoInjectedConv == ENABLE)));
+
+  /*  DISCEN and JAUTO bits can't be set at the same time */
+  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (pConfigInjected->AutoInjectedConv == ENABLE)));
+
+  /* Verification of channel number */
+  if (pConfigInjected->InjectedSingleDiff != ADC_DIFFERENTIAL_ENDED)
+  {
+    assert_param(IS_ADC_CHANNEL(hadc, pConfigInjected->InjectedChannel));
+  }
+  else
+  {
+    assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfigInjected->InjectedChannel));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Configuration of injected group sequencer:                               */
+  /* Hardware constraint: Must fully define injected context register JSQR    */
+  /* before make it entering into injected sequencer queue.                   */
+  /*                                                                          */
+  /* - if scan mode is disabled:                                              */
+  /*    * Injected channels sequence length is set to 0x00: 1 channel         */
+  /*      converted (channel on injected rank 1)                              */
+  /*      Parameter "InjectedNbrOfConversion" is discarded.                   */
+  /*    * Injected context register JSQR setting is simple: register is fully */
+  /*      defined on one call of this function (for injected rank 1) and can  */
+  /*      be entered into queue directly.                                     */
+  /* - if scan mode is enabled:                                               */
+  /*    * Injected channels sequence length is set to parameter               */
+  /*      "InjectedNbrOfConversion".                                          */
+  /*    * Injected context register JSQR setting more complex: register is    */
+  /*      fully defined over successive calls of this function, for each      */
+  /*      injected channel rank. It is entered into queue only when all       */
+  /*      injected ranks have been set.                                       */
+  /*   Note: Scan mode is not present by hardware on this device, but used    */
+  /*   by software for alignment over all STM32 devices.                      */
+
+  if ((hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)  ||
+      (pConfigInjected->InjectedNbrOfConversion == 1U))
+  {
+    /* Configuration of context register JSQR:                                */
+    /*  - number of ranks in injected group sequencer: fixed to 1st rank      */
+    /*    (scan mode disabled, only rank 1 used)                              */
+    /*  - external trigger to start conversion                                */
+    /*  - external trigger polarity                                           */
+    /*  - channel set to rank 1 (scan mode disabled, only rank 1 can be used) */
+
+    if (pConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
+    {
+      /* Enable external trigger if trigger selection is different of         */
+      /* software start.                                                      */
+      /* Note: This configuration keeps the hardware feature of parameter     */
+      /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
+      /*       software start.                                                */
+      if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+      {
+        tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1)
+                                              | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
+                                              | pConfigInjected->ExternalTrigInjecConvEdge
+                                             );
+      }
+      else
+      {
+        tmp_jsqr_context_queue_being_built = (ADC_JSQR_RK(pConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1));
+      }
+
+      MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, tmp_jsqr_context_queue_being_built);
+      /* For debug and informative reasons, hadc handle saves JSQR setting */
+      hadc->InjectionConfig.ContextQueue = tmp_jsqr_context_queue_being_built;
+
+    }
+  }
+  else
+  {
+    /* Case of scan mode enabled, several channels to set into injected group */
+    /* sequencer.                                                             */
+    /*                                                                        */
+    /* Procedure to define injected context register JSQR over successive     */
+    /* calls of this function, for each injected channel rank:                */
+    /* 1. Start new context and set parameters related to all injected        */
+    /*    channels: injected sequence length and trigger.                     */
+
+    /* if hadc->InjectionConfig.ChannelCount is equal to 0, this is the first */
+    /*   call of the context under setting                                    */
+    if (hadc->InjectionConfig.ChannelCount == 0U)
+    {
+      /* Initialize number of channels that will be configured on the context */
+      /*  being built                                                         */
+      hadc->InjectionConfig.ChannelCount = pConfigInjected->InjectedNbrOfConversion;
+      /* Handle hadc saves the context under build up over each HAL_ADCEx_InjectedConfigChannel()
+         call, this context will be written in JSQR register at the last call.
+         At this point, the context is merely reset  */
+      hadc->InjectionConfig.ContextQueue = 0x00000000U;
+
+      /* Configuration of context register JSQR:                              */
+      /*  - number of ranks in injected group sequencer                       */
+      /*  - external trigger to start conversion                              */
+      /*  - external trigger polarity                                         */
+
+      /* Enable external trigger if trigger selection is different of         */
+      /* software start.                                                      */
+      /* Note: This configuration keeps the hardware feature of parameter     */
+      /*       ExternalTrigInjecConvEdge "trigger edge none" equivalent to    */
+      /*       software start.                                                */
+      if (pConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
+      {
+        tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U)
+                                              | (pConfigInjected->ExternalTrigInjecConv & ADC_JSQR_JEXTSEL)
+                                              | pConfigInjected->ExternalTrigInjecConvEdge
+                                             );
+      }
+      else
+      {
+        tmp_jsqr_context_queue_being_built = ((pConfigInjected->InjectedNbrOfConversion - 1U));
+      }
+
+    }
+
+    /* 2. Continue setting of context under definition with parameter       */
+    /*    related to each channel: channel rank sequence                    */
+    /* Clear the old JSQx bits for the selected rank */
+    tmp_jsqr_context_queue_being_built &= ~ADC_JSQR_RK(ADC_SQR3_SQ10, pConfigInjected->InjectedRank);
+
+    /* Set the JSQx bits for the selected rank */
+    tmp_jsqr_context_queue_being_built |= ADC_JSQR_RK(pConfigInjected->InjectedChannel, pConfigInjected->InjectedRank);
+
+    /* Decrease channel count  */
+    hadc->InjectionConfig.ChannelCount--;
+
+    /* 3. tmp_jsqr_context_queue_being_built is fully built for this HAL_ADCEx_InjectedConfigChannel()
+          call, aggregate the setting to those already built during the previous
+          HAL_ADCEx_InjectedConfigChannel() calls (for the same context of course)  */
+    hadc->InjectionConfig.ContextQueue |= tmp_jsqr_context_queue_being_built;
+
+    /* 4. End of context setting: if this is the last channel set, then write context
+        into register JSQR and make it enter into queue                   */
+    if (hadc->InjectionConfig.ChannelCount == 0U)
+    {
+      MODIFY_REG(hadc->Instance->JSQR, ADC_JSQR_FIELDS, hadc->InjectionConfig.ContextQueue);
+    }
+  }
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on injected group:                                   */
+  /*  - Injected context queue: Queue disable (active context is kept) or     */
+  /*    enable (context decremented, up to 2 contexts queued)                 */
+  /*  - Injected discontinuous mode: can be enabled only if auto-injected     */
+  /*    mode is disabled.                                                     */
+  if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* If auto-injected mode is disabled: no constraint                       */
+    if (pConfigInjected->AutoInjectedConv == DISABLE)
+    {
+      MODIFY_REG(hadc->Instance->CFGR,
+                 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
+                 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext)           |
+                 ADC_CFGR_INJECT_DISCCONTINUOUS((uint32_t)pConfigInjected->InjectedDiscontinuousConvMode));
+    }
+    /* If auto-injected mode is enabled: Injected discontinuous setting is    */
+    /* discarded.                                                             */
+    else
+    {
+      MODIFY_REG(hadc->Instance->CFGR,
+                 ADC_CFGR_JQM | ADC_CFGR_JDISCEN,
+                 ADC_CFGR_INJECT_CONTEXT_QUEUE((uint32_t)pConfigInjected->QueueInjectedContext));
+    }
+
+  }
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular and injected groups:                      */
+  /*  - Automatic injected conversion: can be enabled if injected group       */
+  /*    external triggers are disabled.                                       */
+  /*  - Channel sampling time                                                 */
+  /*  - Channel offset                                                        */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+  if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    /* If injected group external triggers are disabled (set to injected      */
+    /* software start): no constraint                                         */
+    if ((pConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
+        || (pConfigInjected->ExternalTrigInjecConvEdge == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE))
+    {
+      if (pConfigInjected->AutoInjectedConv == ENABLE)
+      {
+        SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+      }
+      else
+      {
+        CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+      }
+    }
+    /* If Automatic injected conversion was intended to be set and could not  */
+    /* due to injected group external triggers enabled, error is reported.    */
+    else
+    {
+      if (pConfigInjected->AutoInjectedConv == ENABLE)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+        tmp_hal_status = HAL_ERROR;
+      }
+      else
+      {
+        CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO);
+      }
+    }
+
+    if (pConfigInjected->InjecOversamplingMode == ENABLE)
+    {
+      assert_param(IS_ADC_OVERSAMPLING_RATIO(pConfigInjected->InjecOversampling.Ratio));
+      assert_param(IS_ADC_RIGHT_BIT_SHIFT(pConfigInjected->InjecOversampling.RightBitShift));
+
+      /*  JOVSE must be reset in case of triggered regular mode  */
+      assert_param(!(READ_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)
+                     == (ADC_CFGR2_ROVSE | ADC_CFGR2_TROVS)));
+
+      /* Configuration of Injected Oversampler:                                 */
+      /*  - Oversampling Ratio                                                  */
+      /*  - Right bit shift                                                     */
+
+      /* Enable OverSampling mode */
+      MODIFY_REG(hadc->Instance->CFGR2,
+                 ADC_CFGR2_JOVSE |
+                 ADC_CFGR2_OVSR  |
+                 ADC_CFGR2_OVSS,
+                 ADC_CFGR2_JOVSE                                  |
+                 pConfigInjected->InjecOversampling.Ratio         |
+                 pConfigInjected->InjecOversampling.RightBitShift
+                );
+    }
+    else
+    {
+      /* Disable Regular OverSampling */
+      CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_JOVSE);
+    }
+
+    /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
+    if (pConfigInjected->InjectedSamplingTime == ADC_SAMPLETIME_3CYCLES_5)
+    {
+      /* Set sampling time of the selected ADC channel */
+      LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
+
+      /* Set ADC sampling time common configuration */
+      LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
+    }
+    else
+    {
+      /* Set sampling time of the selected ADC channel */
+      LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfigInjected->InjectedChannel,
+                                    pConfigInjected->InjectedSamplingTime);
+
+      /* Set ADC sampling time common configuration */
+      LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
+    }
+
+    /* Configure the offset: offset enable/disable, channel, offset value */
+
+    /* Shift the offset with respect to the selected ADC resolution. */
+    /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
+    tmp_offset_shifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, pConfigInjected->InjectedOffset);
+
+    if (pConfigInjected->InjectedOffsetNumber != ADC_OFFSET_NONE)
+    {
+      /* Set ADC selected offset number */
+      LL_ADC_SetOffset(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedChannel,
+                       tmp_offset_shifted);
+
+      /* Set ADC selected offset sign & saturation */
+      LL_ADC_SetOffsetSign(hadc->Instance, pConfigInjected->InjectedOffsetNumber, pConfigInjected->InjectedOffsetSign);
+      LL_ADC_SetOffsetSaturation(hadc->Instance, pConfigInjected->InjectedOffsetNumber,
+                                 (pConfigInjected->InjectedOffsetSaturation == ENABLE) ?
+                                 LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
+    }
+    else
+    {
+      /* Scan each offset register to check if the selected channel is targeted. */
+      /* If this is the case, the corresponding offset number is disabled.       */
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
+          == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+      {
+        LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
+      }
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
+          == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+      {
+        LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
+      }
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
+          == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+      {
+        LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
+      }
+      if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
+          == __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfigInjected->InjectedChannel))
+      {
+        LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
+      }
+    }
+
+  }
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated only when ADC is disabled:                */
+  /*  - Single or differential mode                                           */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    /* Set mode single-ended or differential input of the selected ADC channel */
+    LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfigInjected->InjectedChannel, pConfigInjected->InjectedSingleDiff);
+
+    /* Configuration of differential mode */
+    /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
+    if (pConfigInjected->InjectedSingleDiff == ADC_DIFFERENTIAL_ENDED)
+    {
+      /* Set sampling time of the selected ADC channel */
+      LL_ADC_SetChannelSamplingTime(hadc->Instance,
+                                    (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
+                                                 (__LL_ADC_CHANNEL_TO_DECIMAL_NB(
+                                                    (uint32_t)pConfigInjected->InjectedChannel)
+                                                  + 1UL) & 0x1FUL)),
+                                    pConfigInjected->InjectedSamplingTime);
+    }
+
+  }
+
+  /* Management of internal measurement channels: Vbat/VrefInt/TempSensor   */
+  /* internal measurement paths enable: If internal channel selected,       */
+  /* enable dedicated internal buffers and path.                            */
+  /* Note: these internal measurement paths can be disabled using           */
+  /* HAL_ADC_DeInit().                                                      */
+
+  if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfigInjected->InjectedChannel))
+  {
+    tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+    /* If the requested internal measurement path has already been enabled,   */
+    /* bypass the configuration processing.                                   */
+    if (((pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC1)
+         || (pConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR_ADC5))
+        && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+    {
+      if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
+      {
+        LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                       LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+        /* Delay for temperature sensor stabilization time */
+        /* Wait loop initialization and execution */
+        /* Note: Variable divided by 2 to compensate partially              */
+        /*       CPU processing cycles, scaling in us split to not          */
+        /*       exceed 32 bits register capacity and handle low frequency. */
+        wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL)
+                           * (((SystemCoreClock / (100000UL * 2UL)) + 1UL) + 1UL));
+        while (wait_loop_index != 0UL)
+        {
+          wait_loop_index--;
+        }
+      }
+    }
+    else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)
+             && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
+    {
+      if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
+      {
+        LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                       LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
+      }
+    }
+    else if ((pConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)
+             && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+    {
+      if (ADC_VREFINT_INSTANCE(hadc))
+      {
+        LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                       LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+      }
+    }
+    else
+    {
+      /* nothing to do */
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/**
+  * @brief  Enable ADC multimode and configure multimode parameters
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes multimode parameters, following
+  *         calls to this function can be used to reconfigure some parameters
+  *         of structure "ADC_MultiModeTypeDef" on the fly, without resetting
+  *         the ADCs.
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure
+  *         "ADC_MultiModeTypeDef".
+  * @note   To move back configuration from multimode to single mode, ADC must
+  *         be reset (using function HAL_ADC_Init() ).
+  * @param hadc Master ADC handle
+  * @param pMultimode Structure of ADC multimode configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  ADC_Common_TypeDef *tmpADC_Common;
+  ADC_HandleTypeDef tmp_hadc_slave;
+  uint32_t tmp_hadc_slave_conversion_on_going;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_MULTIMODE(pMultimode->Mode));
+  if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
+  {
+    assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
+    assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Temporary handle minimum initialization */
+  __HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
+  ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
+
+  ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
+
+  if (tmp_hadc_slave.Instance == NULL)
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hadc);
+
+    return HAL_ERROR;
+  }
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Multimode DMA configuration                                           */
+  /*  - Multimode DMA mode                                                    */
+  tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
+  if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+      && (tmp_hadc_slave_conversion_on_going == 0UL))
+  {
+    /* Pointer to the common control register */
+    tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
+
+    /* If multimode is selected, configure all multimode parameters.          */
+    /* Otherwise, reset multimode parameters (can be used in case of          */
+    /* transition from multimode to independent mode).                        */
+    if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
+    {
+      MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
+                 pMultimode->DMAAccessMode |
+                 ADC_CCR_MULTI_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+
+      /* Parameters that can be updated only when ADC is disabled:                */
+      /*  - Multimode mode selection                                              */
+      /*  - Multimode delay                                                       */
+      /*    Note: Delay range depends on selected resolution:                     */
+      /*      from 1 to 12 clock cycles for 12 bits                               */
+      /*      from 1 to 10 clock cycles for 10 bits,                              */
+      /*      from 1 to 8 clock cycles for 8 bits                                 */
+      /*      from 1 to 6 clock cycles for 6 bits                                 */
+      /*    If a higher delay is selected, it will be clipped to maximum delay    */
+      /*    range                                                                 */
+      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+      {
+        MODIFY_REG(tmpADC_Common->CCR,
+                   ADC_CCR_DUAL |
+                   ADC_CCR_DELAY,
+                   pMultimode->Mode |
+                   pMultimode->TwoSamplingDelay
+                  );
+      }
+    }
+    else /* ADC_MODE_INDEPENDENT */
+    {
+      CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
+
+      /* Parameters that can be updated only when ADC is disabled:                */
+      /*  - Multimode mode selection                                              */
+      /*  - Multimode delay                                                       */
+      if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
+      {
+        CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
+      }
+    }
+  }
+  /* If one of the ADC sharing the same common group is enabled, no update    */
+  /* could be done on neither of the multimode structure parameters.          */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+/**
+  * @brief  Enable Injected Queue
+  * @note   This function resets CFGR register JQDIS bit in order to enable the
+  *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+  *         are both equal to 0 to ensure that no regular nor injected
+  *         conversion is ongoing.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+  /* Parameter can be set only if no conversion is on-going */
+  if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
+
+    /* Update state, clear previous result related to injected queue overflow */
+    CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
+
+    tmp_hal_status = HAL_OK;
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Disable Injected Queue
+  * @note   This function sets CFGR register JQDIS bit in order to disable the
+  *         Injected Queue. JQDIS can be written only when ADSTART and JDSTART
+  *         are both equal to 0 to ensure that no regular nor injected
+  *         conversion is ongoing.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+  uint32_t tmp_adc_is_conversion_on_going_injected;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+  tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
+
+  /* Parameter can be set only if no conversion is on-going */
+  if ((tmp_adc_is_conversion_on_going_regular == 0UL)
+      && (tmp_adc_is_conversion_on_going_injected == 0UL)
+     )
+  {
+    LL_ADC_INJ_SetQueueMode(hadc->Instance, LL_ADC_INJ_QUEUE_DISABLE);
+    tmp_hal_status = HAL_OK;
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Disable ADC voltage regulator.
+  * @note   Disabling voltage regulator allows to save power. This operation can
+  *         be carried out only when ADC is disabled.
+  * @note   To enable again the voltage regulator, the user is expected to
+  *         resort to HAL_ADC_Init() API.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    LL_ADC_DisableInternalRegulator(hadc->Instance);
+    tmp_hal_status = HAL_OK;
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enter ADC deep-power-down mode
+  * @note   This mode is achieved in setting DEEPPWD bit and allows to save power
+  *         in reducing leakage currents. It is particularly interesting before
+  *         entering stop modes.
+  * @note   Setting DEEPPWD automatically clears ADVREGEN bit and disables the
+  *         ADC voltage regulator. This means that this API encompasses
+  *         HAL_ADCEx_DisableVoltageRegulator(). Additionally, the internal
+  *         calibration is lost.
+  * @note   To exit the ADC deep-power-down mode, the user is expected to
+  *         resort to HAL_ADC_Init() API as well as to relaunch a calibration
+  *         with HAL_ADCEx_Calibration_Start() API or to re-apply a previously
+  *         saved calibration factor.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    LL_ADC_EnableDeepPowerDown(hadc->Instance);
+    tmp_hal_status = HAL_OK;
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_comp.c b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_comp.c
new file mode 100644
index 0000000..1dc7f91
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_comp.c
@@ -0,0 +1,1099 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_comp.c
+  * @author  MCD Application Team
+  * @brief   COMP HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the COMP peripheral:
+  *           + Initialization and de-initialization functions
+  *           + Peripheral control functions
+  *           + Peripheral state functions
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+          ##### COMP Peripheral features #####
+  ==============================================================================
+
+  [..]
+      The STM32G4xx device family integrates seven analog comparators instances:
+      COMP1, COMP2, COMP3, COMP4, COMP5, COMP6 and COMP7.
+      (#) Comparators input minus (inverting input) and input plus (non inverting input)
+          can be set to internal references or to GPIO pins
+          (refer to GPIO list in reference manual).
+
+      (#) Comparators output level is available using HAL_COMP_GetOutputLevel()
+          and can be redirected to other peripherals: GPIO pins (in mode
+          alternate functions for comparator), timers.
+          (refer to GPIO list in reference manual).
+
+      (#) The comparators have interrupt capability through the EXTI controller
+          with wake-up from sleep and stop modes.
+
+          From the corresponding IRQ handler, the right interrupt source can be retrieved
+          using macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
+
+            ##### How to use this driver #####
+  ==============================================================================
+  [..]
+      This driver provides functions to configure and program the comparator instances
+      of STM32G4xx devices.
+
+      To use the comparator, perform the following steps:
+
+      (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
+      (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
+           using HAL_GPIO_Init().
+      (++) If needed, configure the GPIO connected to comparator output in alternate function mode
+           using HAL_GPIO_Init().
+      (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
+           selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
+           interrupt vector using HAL_NVIC_EnableIRQ() function.
+
+      (#) Configure the comparator using HAL_COMP_Init() function:
+      (++) Select the input minus (inverting input)
+      (++) Select the input plus (non-inverting input)
+      (++) Select the hysteresis
+      (++) Select the blanking source
+      (++) Select the output polarity
+
+      -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
+          to enable internal control clock of the comparators.
+          However, this is a legacy strategy. In future STM32 families,
+          COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
+          Therefore, for compatibility anticipation, it is recommended to
+          implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
+
+      (#) Reconfiguration on-the-fly of comparator can be done by calling again
+          function HAL_COMP_Init() with new input structure parameters values.
+
+      (#) Enable the comparator using HAL_COMP_Start() function.
+
+      (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
+          to manage comparator outputs (events and output level).
+
+      (#) Disable the comparator using HAL_COMP_Stop() function.
+
+      (#) De-initialize the comparator using HAL_COMP_DeInit() function.
+
+      (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
+          The only way to unlock the comparator is a device hardware reset.
+
+    *** Callback registration ***
+    =============================================
+    [..]
+
+     The compilation flag USE_HAL_COMP_REGISTER_CALLBACKS, when set to 1,
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions HAL_COMP_RegisterCallback()
+     to register an interrupt callback.
+    [..]
+
+     Function HAL_COMP_RegisterCallback() allows to register following callbacks:
+       (+) TriggerCallback       : callback for COMP trigger.
+       (+) MspInitCallback       : callback for Msp Init.
+       (+) MspDeInitCallback     : callback for Msp DeInit.
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+
+     Use function HAL_COMP_UnRegisterCallback to reset a callback to the default
+     weak function.
+    [..]
+
+     HAL_COMP_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) TriggerCallback       : callback for COMP trigger.
+       (+) MspInitCallback       : callback for Msp Init.
+       (+) MspDeInitCallback     : callback for Msp DeInit.
+     [..]
+
+     By default, after the HAL_COMP_Init() and when the state is HAL_COMP_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     example HAL_COMP_TriggerCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the HAL_COMP_Init()/ HAL_COMP_DeInit() only when
+     these callbacks are null (not registered beforehand).
+    [..]
+
+     If MspInit or MspDeInit are not null, the HAL_COMP_Init()/ HAL_COMP_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+     [..]
+
+     Callbacks can be registered/unregistered in HAL_COMP_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in HAL_COMP_STATE_READY or HAL_COMP_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+    [..]
+
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using HAL_COMP_RegisterCallback() before calling HAL_COMP_DeInit()
+     or HAL_COMP_Init() function.
+     [..]
+
+     When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_COMP_MODULE_ENABLED
+
+
+
+/** @defgroup COMP COMP
+  * @brief COMP HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup COMP_Private_Constants
+  * @{
+  */
+
+/* Delay for COMP startup time.                                               */
+/* Note: Delay required to reach propagation delay specification.             */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define COMP_DELAY_STARTUP_US           (5UL)      /*!< Delay for COMP startup time */
+
+/* Delay for COMP voltage scaler stabilization time.                          */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART_SCALER").                                                */
+/* Unit: us                                                                   */
+#define COMP_DELAY_VOLTAGE_SCALER_STAB_US (200UL)  /*!< Delay for COMP voltage scaler stabilization time */
+
+#define COMP_OUTPUT_LEVEL_BITOFFSET_POS    (30UL)
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup COMP_Exported_Functions COMP Exported Functions
+  * @{
+  */
+
+/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
+  *  @brief    Initialization and de-initialization functions.
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions to initialize and de-initialize comparators
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the COMP according to the specified
+  *         parameters in the COMP_InitTypeDef and initialize the associated handle.
+  * @note   If the selected comparator is locked, initialization can't be performed.
+  *         To unlock the configuration, perform a system reset.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
+{
+  uint32_t tmp_csr;
+  uint32_t exti_line;
+  uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */
+  __IO uint32_t wait_loop_index = 0UL;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the COMP handle allocation and lock status */
+  if (hcomp == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (__HAL_COMP_IS_LOCKED(hcomp))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+    assert_param(IS_COMP_INPUT_PLUS(hcomp->Instance, hcomp->Init.InputPlus));
+    assert_param(IS_COMP_INPUT_MINUS(hcomp->Instance, hcomp->Init.InputMinus));
+    assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
+    assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
+    assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
+    assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
+
+    if (hcomp->State == HAL_COMP_STATE_RESET)
+    {
+      /* Allocate lock resource and initialize it */
+      hcomp->Lock = HAL_UNLOCKED;
+
+      /* Set COMP error code to none */
+      COMP_CLEAR_ERRORCODE(hcomp);
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+      /* Init the COMP Callback settings */
+      hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
+
+      if (hcomp->MspInitCallback == NULL)
+      {
+        hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit  */
+      }
+
+      /* Init the low level hardware */
+      /* Note: Internal control clock of the comparators must                 */
+      /*       be enabled in "HAL_COMP_MspInit()"                             */
+      /*       using "__HAL_RCC_SYSCFG_CLK_ENABLE()".                         */
+      hcomp->MspInitCallback(hcomp);
+#else
+      /* Init the low level hardware */
+      /* Note: Internal control clock of the comparators must                 */
+      /*       be enabled in "HAL_COMP_MspInit()"                             */
+      /*       using "__HAL_RCC_SYSCFG_CLK_ENABLE()".                         */
+      HAL_COMP_MspInit(hcomp);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+    }
+
+    /* Memorize voltage scaler state before initialization */
+    comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN);
+
+    /* Set COMP parameters */
+    tmp_csr = (hcomp->Init.InputMinus
+               | hcomp->Init.InputPlus
+               | hcomp->Init.BlankingSrce
+               | hcomp->Init.Hysteresis
+               | hcomp->Init.OutputPol
+              );
+
+    /* Set parameters in COMP register */
+    /* Note: Update all bits except read-only, lock and enable bits */
+    MODIFY_REG(hcomp->Instance->CSR,
+               COMP_CSR_INMSEL   | COMP_CSR_INPSEL |
+               COMP_CSR_POLARITY | COMP_CSR_HYST   |
+               COMP_CSR_BLANKING | COMP_CSR_BRGEN  | COMP_CSR_SCALEN,
+               tmp_csr
+              );
+
+    /* Delay for COMP scaler bridge voltage stabilization */
+    /* Apply the delay if voltage scaler bridge is required and not already enabled */
+    if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) &&
+        (comp_voltage_scaler_initialized == 0UL))
+    {
+      /* Wait loop initialization and execution */
+      /* Note: Variable divided by 2 to compensate partially              */
+      /*       CPU processing cycles, scaling in us split to not          */
+      /*       exceed 32 bits register capacity and handle low frequency. */
+      wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+      while (wait_loop_index != 0UL)
+      {
+        wait_loop_index--;
+      }
+    }
+
+    /* Get the EXTI line corresponding to the selected COMP instance */
+    exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
+
+    /* Manage EXTI settings */
+    if ((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
+    {
+      /* Configure EXTI rising edge */
+      if ((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
+      {
+#if defined(COMP7)
+        if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
+        {
+          LL_EXTI_EnableRisingTrig_32_63(exti_line);
+        }
+        else
+        {
+          LL_EXTI_EnableRisingTrig_0_31(exti_line);
+        }
+#else
+        LL_EXTI_EnableRisingTrig_0_31(exti_line);
+#endif /* COMP7 */
+      }
+      else
+      {
+#if defined(COMP7)
+        if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
+        {
+          LL_EXTI_DisableRisingTrig_32_63(exti_line);
+        }
+        else
+        {
+          LL_EXTI_DisableRisingTrig_0_31(exti_line);
+        }
+#else
+        LL_EXTI_DisableRisingTrig_0_31(exti_line);
+#endif /* COMP7 */
+      }
+
+      /* Configure EXTI falling edge */
+      if ((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
+      {
+#if defined(COMP7)
+        if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
+        {
+          LL_EXTI_EnableFallingTrig_32_63(exti_line);
+        }
+        else
+        {
+          LL_EXTI_EnableFallingTrig_0_31(exti_line);
+        }
+#else
+        LL_EXTI_EnableFallingTrig_0_31(exti_line);
+#endif /* COMP7 */
+      }
+      else
+      {
+#if defined(COMP7)
+        if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
+        {
+          LL_EXTI_DisableFallingTrig_32_63(exti_line);
+        }
+        else
+        {
+          LL_EXTI_DisableFallingTrig_0_31(exti_line);
+        }
+#else
+        LL_EXTI_DisableFallingTrig_0_31(exti_line);
+#endif /* COMP7 */
+      }
+
+      /* Clear COMP EXTI pending bit (if any) */
+#if defined(COMP7)
+      if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
+      {
+        LL_EXTI_ClearFlag_32_63(exti_line);
+      }
+      else
+      {
+        LL_EXTI_ClearFlag_0_31(exti_line);
+      }
+#else
+      LL_EXTI_ClearFlag_0_31(exti_line);
+#endif /* COMP7 */
+
+      /* Configure EXTI event mode */
+      if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
+      {
+#if defined(COMP7)
+        if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
+        {
+          LL_EXTI_EnableEvent_32_63(exti_line);
+        }
+        else
+        {
+          LL_EXTI_EnableEvent_0_31(exti_line);
+        }
+#else
+        LL_EXTI_EnableEvent_0_31(exti_line);
+#endif /* COMP7 */
+      }
+      else
+      {
+#if defined(COMP7)
+        if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
+        {
+          LL_EXTI_DisableEvent_32_63(exti_line);
+        }
+        else
+        {
+          LL_EXTI_DisableEvent_0_31(exti_line);
+        }
+#else
+        LL_EXTI_DisableEvent_0_31(exti_line);
+#endif /* COMP7 */
+      }
+
+      /* Configure EXTI interrupt mode */
+      if ((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
+      {
+#if defined(COMP7)
+        if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
+        {
+          LL_EXTI_EnableIT_32_63(exti_line);
+        }
+        else
+        {
+          LL_EXTI_EnableIT_0_31(exti_line);
+        }
+#else
+        LL_EXTI_EnableIT_0_31(exti_line);
+#endif /* COMP7 */
+      }
+      else
+      {
+#if defined(COMP7)
+        if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
+        {
+          LL_EXTI_DisableIT_32_63(exti_line);
+        }
+        else
+        {
+          LL_EXTI_DisableIT_0_31(exti_line);
+        }
+#else
+        LL_EXTI_DisableIT_0_31(exti_line);
+#endif /* COMP7 */
+      }
+    }
+    else
+    {
+      /* Disable EXTI event mode */
+#if defined(COMP7)
+      if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
+      {
+        LL_EXTI_DisableEvent_32_63(exti_line);
+      }
+      else
+      {
+        LL_EXTI_DisableEvent_0_31(exti_line);
+      }
+#else
+      LL_EXTI_DisableEvent_0_31(exti_line);
+#endif /* COMP7 */
+
+      /* Disable EXTI interrupt mode */
+#if defined(COMP7)
+      if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
+      {
+        LL_EXTI_DisableIT_32_63(exti_line);
+      }
+      else
+      {
+        LL_EXTI_DisableIT_0_31(exti_line);
+      }
+#else
+      LL_EXTI_DisableIT_0_31(exti_line);
+#endif /* COMP7 */
+    }
+
+    /* Set HAL COMP handle state */
+    /* Note: Transition from state reset to state ready,                      */
+    /*       otherwise (coming from state ready or busy) no state update.     */
+    if (hcomp->State == HAL_COMP_STATE_RESET)
+    {
+      hcomp->State = HAL_COMP_STATE_READY;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  DeInitialize the COMP peripheral.
+  * @note   Deinitialization cannot be performed if the COMP configuration is locked.
+  *         To unlock the configuration, perform a system reset.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the COMP handle allocation and lock status */
+  if (hcomp == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (__HAL_COMP_IS_LOCKED(hcomp))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+    /* Set COMP_CSR register to reset value */
+    WRITE_REG(hcomp->Instance->CSR, 0x00000000UL);
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+    if (hcomp->MspDeInitCallback == NULL)
+    {
+      hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit  */
+    }
+
+    /* DeInit the low level hardware: GPIO, RCC clock, NVIC */
+    hcomp->MspDeInitCallback(hcomp);
+#else
+    /* DeInit the low level hardware: GPIO, RCC clock, NVIC */
+    HAL_COMP_MspDeInit(hcomp);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+
+    /* Set HAL COMP handle state */
+    hcomp->State = HAL_COMP_STATE_RESET;
+
+    /* Release Lock */
+    __HAL_UNLOCK(hcomp);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize the COMP MSP.
+  * @param  hcomp  COMP handle
+  * @retval None
+  */
+__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcomp);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_COMP_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the COMP MSP.
+  * @param  hcomp  COMP handle
+  * @retval None
+  */
+__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcomp);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_COMP_MspDeInit could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User COMP Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
+  *                the configuration information for the specified COMP.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
+  *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
+                                            pCOMP_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (HAL_COMP_STATE_READY == hcomp->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_COMP_TRIGGER_CB_ID :
+        hcomp->TriggerCallback = pCallback;
+        break;
+
+      case HAL_COMP_MSPINIT_CB_ID :
+        hcomp->MspInitCallback = pCallback;
+        break;
+
+      case HAL_COMP_MSPDEINIT_CB_ID :
+        hcomp->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_COMP_STATE_RESET == hcomp->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_COMP_MSPINIT_CB_ID :
+        hcomp->MspInitCallback = pCallback;
+        break;
+
+      case HAL_COMP_MSPDEINIT_CB_ID :
+        hcomp->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a COMP Callback
+  *         COMP callback is redirected to the weak predefined callback
+  * @param  hcomp Pointer to a COMP_HandleTypeDef structure that contains
+  *                the configuration information for the specified COMP.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_COMP_TRIGGER_CB_ID Trigger callback ID
+  *          @arg @ref HAL_COMP_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_COMP_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_COMP_STATE_READY == hcomp->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_COMP_TRIGGER_CB_ID :
+        hcomp->TriggerCallback = HAL_COMP_TriggerCallback;         /* Legacy weak callback */
+        break;
+
+      case HAL_COMP_MSPINIT_CB_ID :
+        hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
+        break;
+
+      case HAL_COMP_MSPDEINIT_CB_ID :
+        hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
+        break;
+
+      default :
+        /* Update the error code */
+        hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_COMP_STATE_RESET == hcomp->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_COMP_MSPINIT_CB_ID :
+        hcomp->MspInitCallback = HAL_COMP_MspInit;                 /* Legacy weak MspInit */
+        break;
+
+      case HAL_COMP_MSPDEINIT_CB_ID :
+        hcomp->MspDeInitCallback = HAL_COMP_MspDeInit;             /* Legacy weak MspDeInit */
+        break;
+
+      default :
+        /* Update the error code */
+        hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
+  *  @brief   Start-Stop operation functions.
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start a comparator instance.
+      (+) Stop a comparator instance.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the comparator.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
+{
+  __IO uint32_t wait_loop_index = 0UL;
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the COMP handle allocation and lock status */
+  if (hcomp == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (__HAL_COMP_IS_LOCKED(hcomp))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+    if (hcomp->State == HAL_COMP_STATE_READY)
+    {
+      /* Enable the selected comparator */
+      SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
+
+      /* Set HAL COMP handle state */
+      hcomp->State = HAL_COMP_STATE_BUSY;
+
+      /* Delay for COMP startup time */
+      /* Wait loop initialization and execution */
+      /* Note: Variable divided by 2 to compensate partially                  */
+      /*       CPU processing cycles.                                         */
+      /* Note: In case of system low frequency (below 1Mhz), short delay      */
+      /*       of startup time (few us) is within CPU processing cycles       */
+      /*       of following instructions.                                     */
+      wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL)));
+      while (wait_loop_index != 0UL)
+      {
+        wait_loop_index--;
+      }
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Stop the comparator.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the COMP handle allocation and lock status */
+  if (hcomp == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (__HAL_COMP_IS_LOCKED(hcomp))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+    /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY    */
+    /* (all states except HAL_COMP_STATE_RESET and except locked status.      */
+    if (hcomp->State != HAL_COMP_STATE_RESET)
+    {
+      /* Disable the selected comparator */
+      CLEAR_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
+
+      /* Set HAL COMP handle state */
+      hcomp->State = HAL_COMP_STATE_READY;
+    }
+    else
+    {
+      status = HAL_ERROR;
+    }
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Comparator IRQ handler.
+  * @param  hcomp  COMP handle
+  * @retval None
+  */
+void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
+{
+  /* Get the EXTI line corresponding to the selected COMP instance */
+  uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
+  uint32_t tmp_comp_exti_flag_set = 0UL;
+
+  /* Check COMP EXTI flag */
+#if defined(COMP7)
+  if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
+  {
+    if (LL_EXTI_IsActiveFlag_32_63(exti_line) != 0UL)
+    {
+      tmp_comp_exti_flag_set = 2UL;
+    }
+  }
+  else
+  {
+    if (LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL)
+    {
+      tmp_comp_exti_flag_set = 1UL;
+    }
+  }
+#else
+  if (LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL)
+  {
+    tmp_comp_exti_flag_set = 1UL;
+  }
+#endif /* COMP7 */
+
+  if (tmp_comp_exti_flag_set != 0UL)
+  {
+    /* Clear COMP EXTI line pending bit */
+#if defined(COMP7)
+    if (tmp_comp_exti_flag_set == 2UL)
+    {
+      LL_EXTI_ClearFlag_32_63(exti_line);
+    }
+    else
+    {
+      LL_EXTI_ClearFlag_0_31(exti_line);
+    }
+#else
+    LL_EXTI_ClearFlag_0_31(exti_line);
+#endif /* COMP7 */
+
+    /* COMP trigger user callback */
+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
+    hcomp->TriggerCallback(hcomp);
+#else
+    HAL_COMP_TriggerCallback(hcomp);
+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   Management functions.
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the comparators.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Lock the selected comparator configuration.
+  * @note   A system reset is required to unlock the comparator configuration.
+  * @note   Locking the comparator from reset state is possible
+  *         if __HAL_RCC_SYSCFG_CLK_ENABLE() is being called before.
+  * @param  hcomp  COMP handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the COMP handle allocation and lock status */
+  if (hcomp == NULL)
+  {
+    status = HAL_ERROR;
+  }
+  else if (__HAL_COMP_IS_LOCKED(hcomp))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Check the parameter */
+    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+    /* Set HAL COMP handle state */
+    switch (hcomp->State)
+    {
+      case HAL_COMP_STATE_RESET:
+        hcomp->State = HAL_COMP_STATE_RESET_LOCKED;
+        break;
+      case HAL_COMP_STATE_READY:
+        hcomp->State = HAL_COMP_STATE_READY_LOCKED;
+        break;
+      default: /* HAL_COMP_STATE_BUSY */
+        hcomp->State = HAL_COMP_STATE_BUSY_LOCKED;
+        break;
+    }
+
+    /* Set the lock bit corresponding to selected comparator */
+    __HAL_COMP_LOCK(hcomp);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Return the output level (high or low) of the selected comparator.
+  *         On this STM32 series, comparator 'value' is taken before
+  *         polarity and blanking are applied, thus:
+  *           - Comparator output is low when the input plus is at a lower
+  *             voltage than the input minus
+  *           - Comparator output is high when the input plus is at a higher
+  *             voltage than the input minus
+  * @param  hcomp  COMP handle
+  * @retval Returns the selected comparator output level:
+  *         @arg COMP_OUTPUT_LEVEL_LOW
+  *         @arg COMP_OUTPUT_LEVEL_HIGH
+  *
+  */
+uint32_t HAL_COMP_GetOutputLevel(const COMP_HandleTypeDef *hcomp)
+{
+  /* Check the parameter */
+  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+  return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE)
+                    >> COMP_OUTPUT_LEVEL_BITOFFSET_POS);
+}
+
+/**
+  * @brief  Comparator trigger callback.
+  * @param  hcomp  COMP handle
+  * @retval None
+  */
+__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hcomp);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_COMP_TriggerCallback should be implemented in the user file
+   */
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
+  *  @brief   Peripheral State functions.
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral State functions #####
+ ===============================================================================
+    [..]
+    This subsection permit to get in run-time the status of the peripheral.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the COMP handle state.
+  * @param  hcomp  COMP handle
+  * @retval HAL state
+  */
+HAL_COMP_StateTypeDef HAL_COMP_GetState(const COMP_HandleTypeDef *hcomp)
+{
+  /* Check the COMP handle allocation */
+  if (hcomp == NULL)
+  {
+    return HAL_COMP_STATE_RESET;
+  }
+
+  /* Check the parameter */
+  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+  /* Return HAL COMP handle state */
+  return hcomp->State;
+}
+
+/**
+  * @brief  Return the COMP error code.
+  * @param hcomp COMP handle
+  * @retval COMP error code
+  */
+uint32_t HAL_COMP_GetError(const COMP_HandleTypeDef *hcomp)
+{
+  /* Check the parameters */
+  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
+
+  return hcomp->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+
+#endif /* HAL_COMP_MODULE_ENABLED */
+
+/**
+  * @}
+  */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c
new file mode 100644
index 0000000..662e3bb
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac.c
@@ -0,0 +1,1749 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_dac.c
+  * @author  MCD Application Team
+  * @brief   DAC HAL module driver.
+  *         This file provides firmware functions to manage the following
+  *         functionalities of the Digital to Analog Converter (DAC) peripheral:
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *           + Peripheral State and Errors functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### DAC Peripheral features #####
+  ==============================================================================
+    [..]
+      *** DAC Channels ***
+      ====================
+    [..]
+    STM32G4 devices integrate up to seven 12-bit Digital Analog Converters,
+    up to six of them grouped by pair forming a DAC instance.
+
+    The 2 converters of an single instance (i.e. channel1 & channel2)
+    can be used independently or simultaneously (dual mode):
+      (#) DAC channel1 with DAC_OUT1 as output (not for all) or connected to on-chip
+          peripherals (ex. comparators, operational amplifier).
+      (#) DAC channel2 with DAC_OUT2 as output (not for all) or connected to on-chip
+          peripherals (ex. comparators, operational amplifier).
+    Note: when an instance only includes one converter, only independent mode is
+        supported by this converter.
+
+    STM32G4 instances & converters availability and output PIO mapping (DAC_OUTx):
+    ----------------------------------------------------------------------------
+                           |    DAC1    |    DAC2    |    DAC3    |    DAC4    |
+    ----------------------------------------------------------------------------
+    Channel 1  |           |    YES     |    YES     |    YES     |    YES
+               | DAC_OUT1  |    PA4     |    PA6     |     -      |     -
+    ----------------------------------------------------------------------------
+    Channel 2  |           |    YES     |    NO      |    YES     |    YES
+               | DAC_OUT2  |    PA5     |     -      |     -      |     -
+    ----------------------------------------------------------------------------
+    Note: On this STM32 series, all devices do not include each DAC instances listed
+          above. Refer to device datasheet for DACx instance availability.
+
+      *** DAC Triggers ***
+      ====================
+    [..]
+    Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE
+    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register.
+    [..]
+    Digital to Analog conversion can be triggered by:
+      (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9.
+          The used pin (GPIOx_PIN_9) must be configured in input mode.
+
+      (#) Timers TRGO: TIM1, TIM2, TIM3, TIM4, TIM6, TIM7, TIM8 and TIM15
+          (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...)
+
+      (#) Software using DAC_TRIGGER_SOFTWARE
+
+      (#) HRTimer TRGO: HRTIM1 (1)
+          (DAC_TRIGGER_HRTIM_TRG01, DAC_TRIGGER_HRTIM_TRG02...)
+
+    [..]
+    Specific triggers for sawtooth generation:
+      (#) External event: EXTI Line 10 (any GPIOx_PIN_10) using DAC_TRIGGER_EXT_IT10.
+          The used pin (GPIOx_PIN_10) must be configured in input mode.
+
+      (#) HRTimer Step & Reset: HRTIM1 (1)
+          (DAC_TRIGGER_HRTIM_RST_TRG1, DAC_TRIGGER_HRTIM_STEP_TRG1...)
+
+      Note: On this STM32 series, parameter only available if HRTIM feature is
+            supported (refer to device datasheet for supported features list)
+
+      *** DAC Buffer mode feature ***
+      ===============================
+      [..]
+      Each DAC channel integrates an output buffer that can be used to
+      reduce the output impedance, and to drive external loads directly
+      without having to add an external operational amplifier.
+      To enable, the output buffer use
+      sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE;
+      [..]
+      (@) Refer to the device datasheet for more details about output
+          impedance value with and without output buffer.
+
+      *** DAC connect feature ***
+      ===============================
+      [..]
+      Each DAC channel can be connected internally.
+      To connect, use
+      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
+      or
+      sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_BOTH; (caution: dependence to other parameters,
+      refer to literal description).
+
+      *** GPIO configurations guidelines ***
+      =====================
+      [..]
+      When a DAC channel is used (ex channel1 on PA4) and the other is not
+      (ex channel2 on PA5 is configured in Analog and disabled).
+      Channel1 may disturb channel2 as coupling effect.
+      Note that there is no coupling on channel2 as soon as channel2 is turned on.
+      Coupling on adjacent channel could be avoided as follows:
+      when unused PA5 is configured as INPUT PULL-UP or DOWN.
+      PA5 is configured in ANALOG just before it is turned on.
+
+      *** DAC Sample and Hold feature ***
+      ========================
+      [..]
+      For each converter, 2 modes are supported: normal mode and
+      "sample and hold" mode (i.e. low power mode).
+      In the sample and hold mode, the DAC core converts data, then holds the
+      converted voltage on a capacitor. When not converting, the DAC cores and
+      buffer are completely turned off between samples and the DAC output is
+      tri-stated, therefore  reducing the overall power consumption. A new
+      stabilization period is needed before each new conversion.
+
+      The sample and hold allow setting internal or external voltage @
+      low power consumption cost (output value can be at any given rate either
+      by CPU or DMA).
+
+      The Sample and hold block and registers uses either LSI & run in
+      several power modes: run mode, sleep mode, low power run, low power sleep
+      mode & stop1 mode.
+
+      Low power stop1 mode allows only static conversion.
+
+      To enable Sample and Hold mode
+      Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI &
+      RCC_LSI_ON parameters.
+
+      Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE;
+         & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime,
+           DAC_HoldTime & DAC_RefreshTime;
+
+       *** DAC calibration feature ***
+       ===================================
+      [..]
+       (#)  The 2 converters (channel1 & channel2) provide calibration capabilities.
+       (++) Calibration aims at correcting some offset of output buffer.
+       (++) The DAC uses either factory calibration settings OR user defined
+           calibration (trimming) settings (i.e. trimming mode).
+       (++) The user defined settings can be figured out using self calibration
+           handled by HAL_DACEx_SelfCalibrate.
+       (++) HAL_DACEx_SelfCalibrate:
+       (+++) Runs automatically the calibration.
+       (+++) Enables the user trimming mode
+       (+++) Updates a structure with trimming values with fresh calibration
+            results.
+            The user may store the calibration results for larger
+            (ex monitoring the trimming as a function of temperature
+            for instance)
+
+       *** DAC wave generation feature ***
+       ===================================
+       [..]
+       Both DAC channels can be used to generate
+         (#) Noise wave
+         (#) Triangle wave
+         (#) Sawtooth wave
+
+       *** DAC data format ***
+       =======================
+       [..]
+       The DAC data format can be:
+         (#) 8-bit right alignment using DAC_ALIGN_8B_R
+         (#) 12-bit left alignment using DAC_ALIGN_12B_L
+         (#) 12-bit right alignment using DAC_ALIGN_12B_R
+
+       *** DAC data value to voltage correspondence ***
+       ================================================
+       [..]
+       The analog output voltage on each DAC channel pin is determined
+       by the following equation:
+       [..]
+       DAC_OUTx = VREF+ * DOR / 4095
+       (+) with  DOR is the Data Output Register
+       [..]
+          VREF+ is the input voltage reference (refer to the device datasheet)
+       [..]
+        e.g. To set DAC_OUT1 to 0.7V, use
+       (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+
+       *** DMA requests ***
+       =====================
+       [..]
+       A DMAMUX request can be generated when an external trigger (but not a software trigger)
+       occurs if DMAMUX requests are enabled using HAL_DAC_Start_DMA().
+       DMAMUX requests are mapped as following:
+        ----------------------------------------------------------------------------
+                               |    DAC1    |    DAC2    |    DAC3    |    DAC4    |
+        ----------------------------------------------------------------------------
+        Channel 1  |           |     6      |     41     |    102     |    104
+        ----------------------------------------------------------------------------
+        Channel 2  |           |     7      |     -      |    103     |    105
+        ----------------------------------------------------------------------------
+        Note: On this STM32 series, all devices do not include each DAC instances listed
+              above. Refer to device datasheet for DACx instance availability.
+
+       *** High frequency interface mode ***
+       =====================================
+       [..]
+       The high frequency interface informs DAC instance about the bus frequency in use.
+       It is mandatory information for DAC (as internal timing of DAC is bus frequency dependent)
+       provided thanks to parameter DAC_HighFrequency handled in HAL_DAC_ConfigChannel () function.
+       Use of DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC value of DAC_HighFrequency is recommended
+       function figured out the correct setting.
+       The high frequency mode is same for all converters of a same DAC instance. Either same
+       parameter DAC_HighFrequency is used for all DAC converters or again self
+       DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC detection parameter.
+
+     [..]
+    (@) For Dual mode and specific signal (Sawtooth, triangle and noise) generation
+        please refer to Extended Features Driver description
+
+                      ##### How to use this driver #####
+  ==============================================================================
+    [..]
+      (+) DAC APB clock must be enabled to get write access to DAC
+          registers using HAL_DAC_Init()
+      (+) If available & needed, configure DAC_OUTx (DAC_OUT1, DAC_OUT2) in analog mode.
+      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
+      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions.
+
+     *** Calibration mode IO operation ***
+     ======================================
+     [..]
+       (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset()
+       (+) Run the calibration using HAL_DACEx_SelfCalibrate()
+       (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming()
+
+     *** Polling mode IO operation ***
+     =================================
+     [..]
+       (+) Start the DAC peripheral using HAL_DAC_Start()
+       (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function.
+       (+) Stop the DAC peripheral using HAL_DAC_Stop()
+
+     *** DMA mode IO operation ***
+     ==============================
+     [..]
+       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length
+           of data to be transferred at each end of conversion
+           First issued trigger will start the conversion of the value previously set by HAL_DAC_SetValue().
+       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+           function is executed and user can add his own code by customization of function pointer
+           HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+           function is executed and user can add his own code by customization of function pointer
+           HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2()
+       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can
+            add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
+       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
+           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2()
+           function is executed and user can add his own code by customization of function pointer
+           HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and
+           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1()
+       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
+
+    *** Callback registration ***
+    =============================================
+    [..]
+      The compilation define  USE_HAL_DAC_REGISTER_CALLBACKS when set to 1
+      allows the user to configure dynamically the driver callbacks.
+
+    Use Functions HAL_DAC_RegisterCallback() to register a user callback,
+      it allows to register following callbacks:
+      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
+      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
+      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
+      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
+      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
+      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
+      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
+      (+) MspInitCallback         : DAC MspInit.
+      (+) MspDeInitCallback       : DAC MspdeInit.
+      This function takes as parameters the HAL peripheral handle, the Callback ID
+      and a pointer to the user callback function.
+
+    Use function HAL_DAC_UnRegisterCallback() to reset a callback to the default
+      weak (overridden) function. It allows to reset following callbacks:
+      (+) ConvCpltCallbackCh1     : callback when a half transfer is completed on Ch1.
+      (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1.
+      (+) ErrorCallbackCh1        : callback when an error occurs on Ch1.
+      (+) DMAUnderrunCallbackCh1  : callback when an underrun error occurs on Ch1.
+      (+) ConvCpltCallbackCh2     : callback when a half transfer is completed on Ch2.
+      (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2.
+      (+) ErrorCallbackCh2        : callback when an error occurs on Ch2.
+      (+) DMAUnderrunCallbackCh2  : callback when an underrun error occurs on Ch2.
+      (+) MspInitCallback         : DAC MspInit.
+      (+) MspDeInitCallback       : DAC MspdeInit.
+      (+) All Callbacks
+      This function) takes as parameters the HAL peripheral handle and the Callback ID.
+
+      By default, after the HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET
+      all callbacks are reset to the corresponding legacy weak (overridden) functions.
+      Exception done for MspInit and MspDeInit callbacks that are respectively
+      reset to the legacy weak (overridden) functions in the HAL_DAC_Init
+      and  HAL_DAC_DeInit only when these callbacks are null (not registered beforehand).
+      If not, MspInit or MspDeInit are not null, the HAL_DAC_Init and HAL_DAC_DeInit
+      keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+      Callbacks can be registered/unregistered in READY state only.
+      Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
+      in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
+      during the Init/DeInit.
+      In that case first register the MspInit/MspDeInit user callbacks
+      using HAL_DAC_RegisterCallback before calling HAL_DAC_DeInit
+      or HAL_DAC_Init function.
+
+      When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or
+      not defined, the callback registering feature is not available
+      and weak (overridden) callbacks are used.
+
+     *** DAC HAL driver macros list ***
+     =============================================
+     [..]
+       Below the list of most used macros in DAC HAL driver.
+
+      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
+      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
+      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
+      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
+
+     [..]
+      (@) You can refer to the DAC HAL driver header file for more useful macros
+
+@endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+#if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
+
+/** @defgroup DAC DAC
+  * @brief DAC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup DAC_Private_Constants DAC Private Constants
+  * @{
+  */
+#define TIMEOUT_DAC_CALIBCONFIG        1U         /* 1   ms        */
+#define HFSEL_ENABLE_THRESHOLD_80MHZ   80000000U  /* 80 MHz        */
+#define HFSEL_ENABLE_THRESHOLD_160MHZ  160000000U /* 160 MHz       */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions -------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Functions DAC Exported Functions
+  * @{
+  */
+
+/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+  ==============================================================================
+              ##### Initialization and de-initialization functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the DAC.
+      (+) De-initialize the DAC.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the DAC peripheral according to the specified parameters
+  *         in the DAC_InitStruct and initialize the associated handle.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
+{
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+  if (hdac->State == HAL_DAC_STATE_RESET)
+  {
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+    /* Init the DAC Callback settings */
+    hdac->ConvCpltCallbackCh1           = HAL_DAC_ConvCpltCallbackCh1;
+    hdac->ConvHalfCpltCallbackCh1       = HAL_DAC_ConvHalfCpltCallbackCh1;
+    hdac->ErrorCallbackCh1              = HAL_DAC_ErrorCallbackCh1;
+    hdac->DMAUnderrunCallbackCh1        = HAL_DAC_DMAUnderrunCallbackCh1;
+
+    hdac->ConvCpltCallbackCh2           = HAL_DACEx_ConvCpltCallbackCh2;
+    hdac->ConvHalfCpltCallbackCh2       = HAL_DACEx_ConvHalfCpltCallbackCh2;
+    hdac->ErrorCallbackCh2              = HAL_DACEx_ErrorCallbackCh2;
+    hdac->DMAUnderrunCallbackCh2        = HAL_DACEx_DMAUnderrunCallbackCh2;
+
+    if (hdac->MspInitCallback == NULL)
+    {
+      hdac->MspInitCallback             = HAL_DAC_MspInit;
+    }
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+    /* Allocate lock resource and initialize it */
+    hdac->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+    /* Init the low level hardware */
+    hdac->MspInitCallback(hdac);
+#else
+    /* Init the low level hardware */
+    HAL_DAC_MspInit(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+  }
+
+  /* Initialize the DAC state*/
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Set DAC error code to none */
+  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+  /* Initialize the DAC state*/
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Deinitialize the DAC peripheral registers to their default reset values.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac)
+{
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  if (hdac->MspDeInitCallback == NULL)
+  {
+    hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  hdac->MspDeInitCallback(hdac);
+#else
+  /* DeInit the low level hardware */
+  HAL_DAC_MspDeInit(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+  /* Set DAC error code to none */
+  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_RESET;
+
+  /* Release Lock */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Initialize the DAC MSP.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DeInitialize the DAC MSP.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
+  *  @brief    IO operation functions
+  *
+@verbatim
+  ==============================================================================
+             ##### IO operation functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start conversion.
+      (+) Stop conversion.
+      (+) Start conversion and enable DMA transfer.
+      (+) Stop conversion and disable DMA transfer.
+      (+) Get result of conversion.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables DAC and starts conversion of channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+  __IO uint32_t wait_loop_index;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Enable the Peripheral */
+  __HAL_DAC_ENABLE(hdac, Channel);
+  /* Ensure minimum wait before using peripheral after enabling it */
+  /* Wait loop initialization and execution */
+  /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed 32 */
+  /*       bits register capacity and handle low frequency. */
+  wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+  while (wait_loop_index != 0UL)
+  {
+    wait_loop_index--;
+  }
+
+  if (Channel == DAC_CHANNEL_1)
+  {
+    /* Check if software trigger enabled */
+    if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
+    {
+      /* Enable the selected DAC software conversion */
+      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
+    }
+  }
+
+  else
+  {
+    /* Check if software trigger enabled */
+    if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
+    {
+      /* Enable the selected DAC software conversion*/
+      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
+    }
+  }
+
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables DAC and stop conversion of channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+
+  /* Disable the Peripheral */
+  __HAL_DAC_DISABLE(hdac, Channel);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables DAC and starts conversion of channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  pData The source Buffer address.
+  * @param  Length The length of data to be transferred from memory to DAC peripheral
+  * @param  Alignment Specifies the data alignment for DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, const uint32_t *pData, uint32_t Length,
+                                    uint32_t Alignment)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tmpreg;
+  __IO uint32_t wait_loop_index;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+  assert_param(IS_DAC_ALIGN(Alignment));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  if (Channel == DAC_CHANNEL_1)
+  {
+    /* Set the DMA transfer complete callback for channel1 */
+    hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+    /* Set the DMA half transfer complete callback for channel1 */
+    hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+    /* Set the DMA error callback for channel1 */
+    hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+    /* Enable the selected DAC channel1 DMA request */
+    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+
+    /* Case of use of channel 1 */
+    switch (Alignment)
+    {
+      case DAC_ALIGN_12B_R:
+        /* Get DHR12R1 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
+        break;
+      case DAC_ALIGN_12B_L:
+        /* Get DHR12L1 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
+        break;
+      default: /* case DAC_ALIGN_8B_R */
+        /* Get DHR8R1 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
+        break;
+    }
+  }
+
+  else
+  {
+    /* Set the DMA transfer complete callback for channel2 */
+    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+    /* Set the DMA half transfer complete callback for channel2 */
+    hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+    /* Set the DMA error callback for channel2 */
+    hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
+    /* Enable the selected DAC channel2 DMA request */
+    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+
+    /* Case of use of channel 2 */
+    switch (Alignment)
+    {
+      case DAC_ALIGN_12B_R:
+        /* Get DHR12R2 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
+        break;
+      case DAC_ALIGN_12B_L:
+        /* Get DHR12L2 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
+        break;
+      default: /* case DAC_ALIGN_8B_R */
+        /* Get DHR8R2 address */
+        tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
+        break;
+    }
+  }
+
+  if (Channel == DAC_CHANNEL_1)
+  {
+    /* Enable the DAC DMA underrun interrupt */
+    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+    /* Enable the DMA channel */
+    status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+  }
+
+  else
+  {
+    /* Enable the DAC DMA underrun interrupt */
+    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
+
+    /* Enable the DMA channel */
+    status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
+  }
+
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdac);
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Peripheral */
+    __HAL_DAC_ENABLE(hdac, Channel);
+    /* Ensure minimum wait before using peripheral after enabling it */
+    /* Wait loop initialization and execution */
+    /* Note: Variable divided by 2 to compensate partially              */
+    /*       CPU processing cycles, scaling in us split to not          */
+    /*       exceed 32 bits register capacity and handle low frequency. */
+    wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+    while (wait_loop_index != 0UL)
+    {
+      wait_loop_index--;
+    }
+  }
+  else
+  {
+    hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Disables DAC and stop conversion of channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+
+  /* Disable the selected DAC channel DMA request */
+  hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << (Channel & 0x10UL));
+
+  /* Disable the Peripheral */
+  __HAL_DAC_DISABLE(hdac, Channel);
+
+  /* Disable the DMA channel */
+
+  /* Channel1 is used */
+  if (Channel == DAC_CHANNEL_1)
+  {
+    /* Disable the DMA channel */
+    (void)HAL_DMA_Abort(hdac->DMA_Handle1);
+
+    /* Disable the DAC DMA underrun interrupt */
+    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
+  }
+
+  else /* Channel2 is used for */
+  {
+    /* Disable the DMA channel */
+    (void)HAL_DMA_Abort(hdac->DMA_Handle2);
+
+    /* Disable the DAC DMA underrun interrupt */
+    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
+  }
+
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Handles DAC interrupt request
+  *         This function uses the interruption of DMA
+  *         underrun.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac)
+{
+  uint32_t itsource = hdac->Instance->CR;
+  uint32_t itflag   = hdac->Instance->SR;
+
+  if ((itsource & DAC_IT_DMAUDR1) == DAC_IT_DMAUDR1)
+  {
+    /* Check underrun flag of DAC channel 1 */
+    if ((itflag & DAC_FLAG_DMAUDR1) == DAC_FLAG_DMAUDR1)
+    {
+      /* Change DAC state to error state */
+      hdac->State = HAL_DAC_STATE_ERROR;
+
+      /* Set DAC error code to channel1 DMA underrun error */
+      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1);
+
+      /* Clear the underrun flag */
+      __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR1);
+
+      /* Disable the selected DAC channel1 DMA request */
+      __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN1);
+
+      /* Error callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+      hdac->DMAUnderrunCallbackCh1(hdac);
+#else
+      HAL_DAC_DMAUnderrunCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+    }
+  }
+
+
+  if ((itsource & DAC_IT_DMAUDR2) == DAC_IT_DMAUDR2)
+  {
+    /* Check underrun flag of DAC channel 2 */
+    if ((itflag & DAC_FLAG_DMAUDR2) == DAC_FLAG_DMAUDR2)
+    {
+      /* Change DAC state to error state */
+      hdac->State = HAL_DAC_STATE_ERROR;
+
+      /* Set DAC error code to channel2 DMA underrun error */
+      SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2);
+
+      /* Clear the underrun flag */
+      __HAL_DAC_CLEAR_FLAG(hdac, DAC_FLAG_DMAUDR2);
+
+      /* Disable the selected DAC channel2 DMA request */
+      __HAL_DAC_DISABLE_IT(hdac, DAC_CR_DMAEN2);
+
+      /* Error callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+      hdac->DMAUnderrunCallbackCh2(hdac);
+#else
+      HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+    }
+  }
+
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  Alignment Specifies the data alignment.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data Data to be loaded in the selected data holding register.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
+{
+  __IO uint32_t tmp = 0UL;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+  assert_param(IS_DAC_ALIGN(Alignment));
+  /* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */
+  if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL)
+  {
+    assert_param(IS_DAC_DATA(Data));
+  }
+
+  tmp = (uint32_t)hdac->Instance;
+  if (Channel == DAC_CHANNEL_1)
+  {
+    tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
+  }
+
+  else
+  {
+    tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
+  }
+
+
+  /* Set the DAC channel selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Conversion complete callback in non-blocking mode for Channel1
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel1
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error DAC callback for Channel1.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA underrun DAC callback for channel1.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+             ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure channels.
+      (+) Set the specified data holding register value for DAC channel.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DAC_GetValue(const DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+  uint32_t result;
+
+  /* Check the DAC peripheral handle */
+  assert_param(hdac != NULL);
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+
+  if (Channel == DAC_CHANNEL_1)
+  {
+    result = hdac->Instance->DOR1;
+  }
+
+  else
+  {
+    result = hdac->Instance->DOR2;
+  }
+
+  /* Returns the DAC channel data output register value */
+  return result;
+}
+
+/**
+  * @brief  Configures the selected DAC channel.
+  * @note   By calling this function, the high frequency interface mode (HFSEL bits)
+  *         will be set. This parameter scope is the DAC instance. As the function
+  *         is called for each channel, the @ref DAC_HighFrequency of @arg sConfig
+  *         must be the same at each call.
+  *         (or DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC self detect).
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  sConfig DAC configuration structure.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
+                                        const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tmpreg1;
+  uint32_t tmpreg2;
+  uint32_t tickstart;
+  uint32_t hclkfreq;
+  uint32_t connectOnChip;
+
+  /* Check the DAC peripheral handle and channel configuration struct */
+  if ((hdac == NULL) || (sConfig == NULL))
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency));
+  assert_param(IS_DAC_TRIGGER(hdac->Instance, sConfig->DAC_Trigger));
+  assert_param(IS_DAC_TRIGGER2(hdac->Instance, sConfig->DAC_Trigger2));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
+  assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral));
+  assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming));
+  if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
+  {
+    assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
+  }
+  assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
+  if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
+  {
+    assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime));
+    assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime));
+    assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime));
+  }
+  else
+  {
+    /* In case of mode normal and buffer disabled, connection to both on chip periph and external pin is not possible */
+    if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_DISABLE)
+    {
+      assert_param(sConfig->DAC_ConnectOnChipPeripheral != DAC_CHIPCONNECT_BOTH);
+    }
+  }
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+  assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode));
+  assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Sample and hold configuration */
+  if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
+  {
+    /* Get timeout */
+    tickstart = HAL_GetTick();
+
+    if (Channel == DAC_CHANNEL_1)
+    {
+      /* SHSR1 can be written when BWST1 is cleared */
+      while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
+      {
+        /* Check for the Timeout */
+        if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
+        {
+          /* New check to avoid false timeout detection in case of preemption */
+          if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
+          {
+            /* Update error code */
+            SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
+
+            /* Change the DMA state */
+            hdac->State = HAL_DAC_STATE_TIMEOUT;
+
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
+    }
+
+    else /* Channel 2 */
+    {
+      /* SHSR2 can be written when BWST2 is cleared */
+      while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
+      {
+        /* Check for the Timeout */
+        if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
+        {
+          /* New check to avoid false timeout detection in case of preemption */
+          if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
+          {
+            /* Update error code */
+            SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
+
+            /* Change the DMA state */
+            hdac->State = HAL_DAC_STATE_TIMEOUT;
+
+            return HAL_TIMEOUT;
+          }
+        }
+      }
+      hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
+    }
+
+
+    /* HoldTime */
+    MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
+               (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
+    /* RefreshTime */
+    MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
+               (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
+  }
+
+  if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
+    /* USER TRIMMING */
+  {
+    /* Get the DAC CCR value */
+    tmpreg1 = hdac->Instance->CCR;
+    /* Clear trimming value */
+    tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
+    /* Configure for the selected trimming offset */
+    tmpreg2 = sConfig->DAC_TrimmingValue;
+    /* Calculate CCR register value depending on DAC_Channel */
+    tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
+    /* Write to DAC CCR */
+    hdac->Instance->CCR = tmpreg1;
+  }
+  /* else factory trimming is used (factory setting are available at reset)*/
+  /* SW Nothing has nothing to do */
+
+  /* Get the DAC MCR value */
+  tmpreg1 = hdac->Instance->MCR;
+  /* Clear DAC_MCR_MODEx bits */
+  tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
+  /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
+
+
+  if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
+  {
+    connectOnChip = 0x00000000UL;
+  }
+  else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
+  {
+    connectOnChip = DAC_MCR_MODE1_0;
+  }
+  else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
+  {
+    if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
+    {
+      connectOnChip = DAC_MCR_MODE1_0;
+    }
+    else
+    {
+      connectOnChip = 0x00000000UL;
+    }
+  }
+  tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
+  /* Clear DAC_MCR_DMADOUBLEx */
+  tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL));
+  /* Configure for the selected DAC channel: DMA double data mode */
+  tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL;
+  /* Clear DAC_MCR_SINFORMATx */
+  tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL));
+  /* Configure for the selected DAC channel: Signed format */
+  tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL;
+  /* Clear DAC_MCR_HFSEL bits */
+  tmpreg1 &= ~(DAC_MCR_HFSEL);
+  /* Configure for both DAC channels: high frequency mode */
+  if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency)
+  {
+    hclkfreq = HAL_RCC_GetHCLKFreq();
+    if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ)
+    {
+      tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ;
+    }
+    else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ)
+    {
+      tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ;
+    }
+    else
+    {
+      tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE;
+    }
+  }
+  else
+  {
+    tmpreg1 |= sConfig->DAC_HighFrequency;
+  }
+  /* Calculate MCR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
+  /* Write to DAC MCR */
+  hdac->Instance->MCR = tmpreg1;
+
+  /* DAC in normal operating mode hence clear DAC_CR_CENx bit */
+  CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
+
+  /* Get the DAC CR value */
+  tmpreg1 = hdac->Instance->CR;
+  /* Clear TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
+  /* Configure for the selected DAC channel: trigger */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  tmpreg2 = sConfig->DAC_Trigger;
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
+  /* Write to DAC CR */
+  hdac->Instance->CR = tmpreg1;
+  /* Disable wave generation */
+  CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
+
+  /* Set STRSTTRIGSELx and STINCTRIGSELx bits according to DAC_Trigger & DAC_Trigger2 values */
+  tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos;
+  tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos;
+  /* Modify STMODR register value depending on DAC_Channel */
+  MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1)
+             << (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL));
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
+  *  @brief   Peripheral State and Errors functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Errors functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to
+      (+) Check the DAC state.
+      (+) Check the DAC Errors.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  return the DAC handle state
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL state
+  */
+HAL_DAC_StateTypeDef HAL_DAC_GetState(const DAC_HandleTypeDef *hdac)
+{
+  /* Return DAC handle state */
+  return hdac->State;
+}
+
+
+/**
+  * @brief  Return the DAC error code
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval DAC Error Code
+  */
+uint32_t HAL_DAC_GetError(const DAC_HandleTypeDef *hdac)
+{
+  return hdac->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup DAC_Exported_Functions_Group1
+  * @{
+  */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User DAC Callback
+  *         To be used instead of the weak (overridden) predefined callback
+  * @note   The HAL_DAC_RegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to register
+  *         callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
+  * @param  hdac DAC handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK   DAC Error Callback ID
+  *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID       DAC CH1 Complete Callback ID
+  *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID  DAC CH1 Half Complete Callback ID
+  *          @arg @ref HAL_DAC_CH1_ERROR_ID             DAC CH1 Error Callback ID
+  *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID       DAC CH1 UnderRun Callback ID
+  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID       DAC CH2 Complete Callback ID
+  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID  DAC CH2 Half Complete Callback ID
+  *          @arg @ref HAL_DAC_CH2_ERROR_ID             DAC CH2 Error Callback ID
+  *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID       DAC CH2 UnderRun Callback ID
+  *          @arg @ref HAL_DAC_MSPINIT_CB_ID            DAC MSP Init Callback ID
+  *          @arg @ref HAL_DAC_MSPDEINIT_CB_ID          DAC MSP DeInit Callback ID
+  *
+  * @param  pCallback pointer to the Callback function
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,
+                                           pDAC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+    return HAL_ERROR;
+  }
+
+  if (hdac->State == HAL_DAC_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DAC_CH1_COMPLETE_CB_ID :
+        hdac->ConvCpltCallbackCh1 = pCallback;
+        break;
+      case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
+        hdac->ConvHalfCpltCallbackCh1 = pCallback;
+        break;
+      case HAL_DAC_CH1_ERROR_ID :
+        hdac->ErrorCallbackCh1 = pCallback;
+        break;
+      case HAL_DAC_CH1_UNDERRUN_CB_ID :
+        hdac->DMAUnderrunCallbackCh1 = pCallback;
+        break;
+
+      case HAL_DAC_CH2_COMPLETE_CB_ID :
+        hdac->ConvCpltCallbackCh2 = pCallback;
+        break;
+      case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
+        hdac->ConvHalfCpltCallbackCh2 = pCallback;
+        break;
+      case HAL_DAC_CH2_ERROR_ID :
+        hdac->ErrorCallbackCh2 = pCallback;
+        break;
+      case HAL_DAC_CH2_UNDERRUN_CB_ID :
+        hdac->DMAUnderrunCallbackCh2 = pCallback;
+        break;
+
+      case HAL_DAC_MSPINIT_CB_ID :
+        hdac->MspInitCallback = pCallback;
+        break;
+      case HAL_DAC_MSPDEINIT_CB_ID :
+        hdac->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hdac->State == HAL_DAC_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DAC_MSPINIT_CB_ID :
+        hdac->MspInitCallback = pCallback;
+        break;
+      case HAL_DAC_MSPDEINIT_CB_ID :
+        hdac->MspDeInitCallback = pCallback;
+        break;
+      default :
+        /* Update the error code */
+        hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a User DAC Callback
+  *         DAC Callback is redirected to the weak (overridden) predefined callback
+  * @note   The HAL_DAC_UnRegisterCallback() may be called before HAL_DAC_Init() in HAL_DAC_STATE_RESET to un-register
+  *         callbacks for HAL_DAC_MSPINIT_CB_ID and HAL_DAC_MSPDEINIT_CB_ID
+  * @param  hdac DAC handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID          DAC CH1 transfer Complete Callback ID
+  *          @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID     DAC CH1 Half Complete Callback ID
+  *          @arg @ref HAL_DAC_CH1_ERROR_ID                DAC CH1 Error Callback ID
+  *          @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID          DAC CH1 UnderRun Callback ID
+  *          @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID          DAC CH2 Complete Callback ID
+  *          @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID     DAC CH2 Half Complete Callback ID
+  *          @arg @ref HAL_DAC_CH2_ERROR_ID                DAC CH2 Error Callback ID
+  *          @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID          DAC CH2 UnderRun Callback ID
+  *          @arg @ref HAL_DAC_MSPINIT_CB_ID               DAC MSP Init Callback ID
+  *          @arg @ref HAL_DAC_MSPDEINIT_CB_ID             DAC MSP DeInit Callback ID
+  *          @arg @ref HAL_DAC_ALL_CB_ID                   DAC All callbacks
+  * @retval status
+  */
+HAL_StatusTypeDef HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (hdac->State == HAL_DAC_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DAC_CH1_COMPLETE_CB_ID :
+        hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+        break;
+      case HAL_DAC_CH1_HALF_COMPLETE_CB_ID :
+        hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+        break;
+      case HAL_DAC_CH1_ERROR_ID :
+        hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+        break;
+      case HAL_DAC_CH1_UNDERRUN_CB_ID :
+        hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+        break;
+
+      case HAL_DAC_CH2_COMPLETE_CB_ID :
+        hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+        break;
+      case HAL_DAC_CH2_HALF_COMPLETE_CB_ID :
+        hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+        break;
+      case HAL_DAC_CH2_ERROR_ID :
+        hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+        break;
+      case HAL_DAC_CH2_UNDERRUN_CB_ID :
+        hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+        break;
+
+      case HAL_DAC_MSPINIT_CB_ID :
+        hdac->MspInitCallback = HAL_DAC_MspInit;
+        break;
+      case HAL_DAC_MSPDEINIT_CB_ID :
+        hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+        break;
+      case HAL_DAC_ALL_CB_ID :
+        hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1;
+        hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1;
+        hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1;
+        hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1;
+
+        hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2;
+        hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2;
+        hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2;
+        hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2;
+
+        hdac->MspInitCallback = HAL_DAC_MspInit;
+        hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (hdac->State == HAL_DAC_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_DAC_MSPINIT_CB_ID :
+        hdac->MspInitCallback = HAL_DAC_MspInit;
+        break;
+      case HAL_DAC_MSPDEINIT_CB_ID :
+        hdac->MspDeInitCallback = HAL_DAC_MspDeInit;
+        break;
+      default :
+        /* Update the error code */
+        hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+        /* update return status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK;
+    /* update return status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup DAC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  DMA conversion complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ConvCpltCallbackCh1(hdac);
+#else
+  HAL_DAC_ConvCpltCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+  hdac->State = HAL_DAC_STATE_READY;
+}
+
+/**
+  * @brief  DMA half transfer complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
+{
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  /* Conversion complete callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ConvHalfCpltCallbackCh1(hdac);
+#else
+  HAL_DAC_ConvHalfCpltCallbackCh1(hdac);
+#endif  /* USE_HAL_DAC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA error callback
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
+{
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Set DAC error code to DMA error */
+  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ErrorCallbackCh1(hdac);
+#else
+  HAL_DAC_ErrorCallbackCh1(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+  hdac->State = HAL_DAC_STATE_READY;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 || DAC2 || DAC3 || DAC4 */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+/**
+  * @}
+  */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c
new file mode 100644
index 0000000..e1d1e39
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_dac_ex.c
@@ -0,0 +1,1184 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_dac_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended DAC HAL module driver.
+  *          This file provides firmware functions to manage the extended
+  *          functionalities of the DAC peripheral.
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                      ##### How to use this driver #####
+  ==============================================================================
+    [..]
+     *** Dual mode IO operation ***
+     ==============================
+     [..]
+      (+) Use HAL_DACEx_DualStart() to enable both channel and start conversion
+          for dual mode operation.
+          If software trigger is selected, using HAL_DACEx_DualStart() will start
+          the conversion of the value previously set by HAL_DACEx_DualSetValue().
+      (+) Use HAL_DACEx_DualStop() to disable both channel and stop conversion
+          for dual mode operation.
+      (+) Use HAL_DACEx_DualStart_DMA() to enable both channel and start conversion
+          for dual mode operation using DMA to feed DAC converters.
+          First issued trigger will start the conversion of the value previously
+          set by HAL_DACEx_DualSetValue().
+          The same callbacks that are used in single mode are called in dual mode to notify
+          transfer completion (half complete or complete), errors or underrun.
+      (+) Use HAL_DACEx_DualStop_DMA() to disable both channel and stop conversion
+          for dual mode operation using DMA to feed DAC converters.
+      (+) When Dual mode is enabled (i.e. DAC Channel1 and Channel2 are used simultaneously) :
+          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
+          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in
+          Channel 1 and Channel 2.
+     *** Signal generation operation ***
+     ===================================
+     [..]
+      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
+      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
+
+      (+) Use HAL_DACEx_SawtoothWaveGenerate() to generate sawtooth signal.
+      (+) Use HAL_DACEx_SawtoothWaveDataReset() to reset sawtooth wave.
+      (+) Use HAL_DACEx_SawtoothWaveDataStep() to step sawtooth wave.
+
+      (+) HAL_DACEx_SelfCalibrate to calibrate one DAC channel.
+      (+) HAL_DACEx_SetUserTrimming to set user trimming value.
+      (+) HAL_DACEx_GetTrimOffset to retrieve trimming value (factory setting
+          after reset, user setting if HAL_DACEx_SetUserTrimming have been used
+          at least one time after reset).
+
+ @endverbatim
+  ******************************************************************************
+  */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_DAC_MODULE_ENABLED
+
+#if defined(DAC1) || defined(DAC2) || defined(DAC3) ||defined (DAC4)
+
+/** @defgroup DACEx DACEx
+  * @brief DAC Extended HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Delay for DAC minimum trimming time.                                       */
+/* Note: minimum time needed between two calibration steps                    */
+/*       The delay below is specified under conditions:                       */
+/*        - DAC channel output buffer enabled                                 */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* electrical characteristics, parameter "tTRIM").                            */
+/* Unit: us                                                                   */
+#define DAC_DELAY_TRIM_US          (50UL)     /*!< Delay for DAC minimum trimming time */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
+  * @{
+  */
+
+/** @defgroup DACEx_Exported_Functions_Group2 IO operation functions
+  *  @brief    Extended IO operation functions
+  *
+@verbatim
+  ==============================================================================
+                 ##### Extended features functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start conversion.
+      (+) Stop conversion.
+      (+) Start conversion and enable DMA transfer.
+      (+) Stop conversion and disable DMA transfer.
+      (+) Get result of conversion.
+      (+) Get result of dual mode conversion.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Enables DAC and starts conversion of both channels.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac)
+{
+  uint32_t tmp_swtrig = 0UL;
+  __IO uint32_t wait_loop_index;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Enable the Peripheral */
+  __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
+  __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
+  /* Ensure minimum wait before using peripheral after enabling it */
+  /* Wait loop initialization and execution */
+  /* Note: Variable divided by 2 to compensate partially              */
+  /*       CPU processing cycles, scaling in us split to not          */
+  /*       exceed 32 bits register capacity and handle low frequency. */
+  wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+  while (wait_loop_index != 0UL)
+  {
+    wait_loop_index--;
+  }
+
+  /* Check if software trigger enabled */
+  if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
+  {
+    tmp_swtrig |= DAC_SWTRIGR_SWTRIG1;
+  }
+  if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (DAC_CHANNEL_2 & 0x10UL)))
+  {
+    tmp_swtrig |= DAC_SWTRIGR_SWTRIG2;
+  }
+  /* Enable the selected DAC software conversion*/
+  SET_BIT(hdac->Instance->SWTRIGR, tmp_swtrig);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disables DAC and stop conversion of both channels.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac)
+{
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2));
+
+  /* Disable the Peripheral */
+  __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
+  __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enables DAC and starts conversion of both channel 1 and 2 of the same DAC.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The DAC channel that will request data from DMA.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @param  pData The destination peripheral Buffer address.
+  * @param  Length The length of data to be transferred from memory to DAC peripheral
+  * @param  Alignment Specifies the data alignment for DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel,
+                                          const uint32_t *pData, uint32_t Length, uint32_t Alignment)
+{
+  HAL_StatusTypeDef status;
+  uint32_t tmpreg = 0UL;
+  __IO uint32_t wait_loop_index;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+  /* Ensure Channel 2 exists for this particular DAC instance */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2));
+  assert_param(IS_DAC_ALIGN(Alignment));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  if (Channel == DAC_CHANNEL_1)
+  {
+    /* Set the DMA transfer complete callback for channel1 */
+    hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
+
+    /* Set the DMA half transfer complete callback for channel1 */
+    hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
+
+    /* Set the DMA error callback for channel1 */
+    hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
+
+    /* Enable the selected DAC channel1 DMA request */
+    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
+  }
+  else
+  {
+    /* Set the DMA transfer complete callback for channel2 */
+    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
+
+    /* Set the DMA half transfer complete callback for channel2 */
+    hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
+
+    /* Set the DMA error callback for channel2 */
+    hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
+
+    /* Enable the selected DAC channel2 DMA request */
+    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
+  }
+
+  switch (Alignment)
+  {
+    case DAC_ALIGN_12B_R:
+      /* Get DHR12R1 address */
+      tmpreg = (uint32_t)&hdac->Instance->DHR12RD;
+      break;
+    case DAC_ALIGN_12B_L:
+      /* Get DHR12L1 address */
+      tmpreg = (uint32_t)&hdac->Instance->DHR12LD;
+      break;
+    case DAC_ALIGN_8B_R:
+      /* Get DHR8R1 address */
+      tmpreg = (uint32_t)&hdac->Instance->DHR8RD;
+      break;
+    default:
+      break;
+  }
+
+  /* Enable the DMA channel */
+  if (Channel == DAC_CHANNEL_1)
+  {
+    /* Enable the DAC DMA underrun interrupt */
+    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
+
+    /* Enable the DMA channel */
+    status = HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
+  }
+  else
+  {
+    /* Enable the DAC DMA underrun interrupt */
+    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
+
+    /* Enable the DMA channel */
+    status = HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hdac);
+
+  if (status == HAL_OK)
+  {
+    /* Enable the Peripheral */
+    __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_1);
+    __HAL_DAC_ENABLE(hdac, DAC_CHANNEL_2);
+    /* Ensure minimum wait before using peripheral after enabling it */
+    /* Wait loop initialization and execution */
+    /* Note: Variable divided by 2 to compensate partially              */
+    /*       CPU processing cycles, scaling in us split to not          */
+    /*       exceed 32 bits register capacity and handle low frequency. */
+    wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+    while (wait_loop_index != 0UL)
+    {
+      wait_loop_index--;
+    }
+  }
+  else
+  {
+    hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Disables DAC and stop conversion both channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The DAC channel that requests data from DMA.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Ensure Channel 2 exists for this particular DAC instance */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, DAC_CHANNEL_2));
+
+  /* Disable the selected DAC channel DMA request */
+  CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2 | DAC_CR_DMAEN1);
+
+  /* Disable the Peripheral */
+  __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_1);
+  __HAL_DAC_DISABLE(hdac, DAC_CHANNEL_2);
+
+  /* Disable the DMA channel */
+
+  /* Channel1 is used */
+  if (Channel == DAC_CHANNEL_1)
+  {
+    /* Disable the DMA channel */
+    status = HAL_DMA_Abort(hdac->DMA_Handle1);
+
+    /* Disable the DAC DMA underrun interrupt */
+    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1);
+  }
+  else
+  {
+    /* Disable the DMA channel */
+    status = HAL_DMA_Abort(hdac->DMA_Handle2);
+
+    /* Disable the DAC DMA underrun interrupt */
+    __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2);
+  }
+
+  /* Check if DMA Channel effectively disabled */
+  if (status != HAL_OK)
+  {
+    /* Update DAC state machine to error */
+    hdac->State = HAL_DAC_STATE_ERROR;
+  }
+  else
+  {
+    /* Change DAC state */
+    hdac->State = HAL_DAC_STATE_READY;
+  }
+
+  /* Return function status */
+  return status;
+}
+
+
+/**
+  * @brief  Enable or disable the selected DAC channel wave generation.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  Amplitude Select max triangle amplitude.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
+  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
+  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
+  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
+  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
+  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
+  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
+  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
+  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
+  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
+  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
+  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
+{
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Enable the triangle wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
+             (DAC_CR_WAVE1_1 | Amplitude) << (Channel & 0x10UL));
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable or disable the selected DAC channel wave generation.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  Amplitude Unmask DAC channel LFSR for noise wave generation.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation
+  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude)
+{
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  /* Enable the noise wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR, ((DAC_CR_WAVE1) | (DAC_CR_MAMP1)) << (Channel & 0x10UL),
+             (DAC_CR_WAVE1_0 | Amplitude) << (Channel & 0x10UL));
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable or disable the selected DAC channel sawtooth wave generation.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  Polarity polarity to be used for wave generation.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_SAWTOOTH_POLARITY_DECREMENT
+  *            @arg DAC_SAWTOOTH_POLARITY_INCREMENT
+  * @param  ResetData Sawtooth wave reset value.
+  *          Range is from 0 to DAC full range 4095 (0xFFF)
+  * @param  StepData Sawtooth wave step value.
+  *          12.4 bit format, unsigned: 12 bits exponent / 4 bits mantissa
+  *          Step value step is 1/16 = 0.0625
+  *          Step value range is 0.0000 to 4095.9375 (0xFFF.F)
+  * @note    Sawtooth reset and step triggers are configured by calling @ref HAL_DAC_ConfigChannel
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_SawtoothWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Polarity,
+                                                 uint32_t ResetData, uint32_t StepData)
+{
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+  assert_param(IS_DAC_SAWTOOTH_POLARITY(Polarity));
+  assert_param(IS_DAC_RESET_DATA(ResetData));
+  assert_param(IS_DAC_STEP_DATA(StepData));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_BUSY;
+
+  if (Channel == DAC_CHANNEL_1)
+  {
+    /* Configure the sawtooth wave generation data parameters */
+    MODIFY_REG(hdac->Instance->STR1,
+               DAC_STR1_STINCDATA1 | DAC_STR1_STDIR1 | DAC_STR1_STRSTDATA1,
+               (StepData << DAC_STR1_STINCDATA1_Pos)
+               | Polarity
+               | (ResetData << DAC_STR1_STRSTDATA1_Pos));
+  }
+  else
+  {
+    /* Configure the sawtooth wave generation data parameters */
+    MODIFY_REG(hdac->Instance->STR2,
+               DAC_STR2_STINCDATA2 | DAC_STR2_STDIR2 | DAC_STR2_STRSTDATA2,
+               (StepData << DAC_STR2_STINCDATA2_Pos)
+               | Polarity
+               | (ResetData << DAC_STR2_STRSTDATA2_Pos));
+  }
+
+  /* Enable the sawtooth wave generation for the selected DAC channel */
+  MODIFY_REG(hdac->Instance->CR,
+             (DAC_CR_WAVE1) << (Channel & 0x10UL),
+             (uint32_t)(DAC_CR_WAVE1_1 | DAC_CR_WAVE1_0) << (Channel & 0x10UL));
+
+  /* Change DAC state */
+  hdac->State = HAL_DAC_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Trig sawtooth wave reset
+  * @note   This function allows to reset sawtooth wave in case of SW trigger
+  *         has been configured for this usage.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataReset(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STRSTTRIGSEL1) == 0UL /* SW TRIGGER */)
+  {
+    /* Change DAC state */
+    hdac->State = HAL_DAC_STATE_BUSY;
+
+    if (Channel == DAC_CHANNEL_1)
+    {
+      /* Enable the selected DAC software conversion */
+      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
+    }
+    else
+    {
+      /* Enable the selected DAC software conversion */
+      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
+    }
+
+    /* Change DAC state */
+    hdac->State = HAL_DAC_STATE_READY;
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return status;
+}
+
+/**
+  * @brief  Trig sawtooth wave step
+  * @note   This function allows to generate step  in sawtooth wave in case of
+  *         SW trigger has been configured for this usage.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_SawtoothWaveDataStep(DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+
+  /* Process locked */
+  __HAL_LOCK(hdac);
+
+  if (((hdac->Instance->STMODR >> (Channel & 0x10UL)) & DAC_STMODR_STINCTRIGSEL1) == 0UL /* SW TRIGGER */)
+  {
+    /* Change DAC state */
+    hdac->State = HAL_DAC_STATE_BUSY;
+
+    if (Channel == DAC_CHANNEL_1)
+    {
+      /* Enable the selected DAC software conversion */
+      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIGB1);
+    }
+    else
+    {
+      /* Enable the selected DAC software conversion */
+      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIGB2);
+    }
+
+    /* Change DAC state */
+    hdac->State = HAL_DAC_STATE_READY;
+  }
+  else
+  {
+    status = HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hdac);
+
+  /* Return function status */
+  return status;
+}
+
+
+/**
+  * @brief  Set the specified data holding register value for dual DAC channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *               the configuration information for the specified DAC.
+  * @param  Alignment Specifies the data alignment for dual channel DAC.
+  *          This parameter can be one of the following values:
+  *            DAC_ALIGN_8B_R: 8bit right data alignment selected
+  *            DAC_ALIGN_12B_L: 12bit left data alignment selected
+  *            DAC_ALIGN_12B_R: 12bit right data alignment selected
+  * @param  Data1 Data for DAC Channel1 to be loaded in the selected data holding register.
+  * @param  Data2 Data for DAC Channel2 to be loaded in the selected data  holding register.
+  * @note   In dual mode, a unique register access is required to write in both
+  *          DAC channels at the same time.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
+{
+  uint32_t data;
+  uint32_t tmp;
+
+  /* Check the DAC peripheral handle */
+  if (hdac == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(Alignment));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+
+  /* Calculate and set dual DAC data holding register value */
+  if (Alignment == DAC_ALIGN_8B_R)
+  {
+    data = ((uint32_t)Data2 << 8U) | Data1;
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16U) | Data1;
+  }
+
+  tmp = (uint32_t)hdac->Instance;
+  tmp += DAC_DHR12RD_ALIGNMENT(Alignment);
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Conversion complete callback in non-blocking mode for Channel2.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Conversion half DMA transfer callback in non-blocking mode for Channel2.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Error DAC callback for Channel2.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  DMA underrun DAC callback for Channel2.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval None
+  */
+__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hdac);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_DACEx_DMAUnderrunCallbackCh2 could be implemented in the user file
+   */
+}
+
+
+/**
+  * @brief  Run the self calibration of one DAC channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  sConfig DAC channel configuration structure.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval Updates DAC_TrimmingValue. , DAC_UserTrimming set to DAC_UserTrimming
+  * @retval HAL status
+  * @note   Calibration runs about 7 ms.
+  */
+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  uint32_t trimmingvalue;
+  uint32_t delta;
+  __IO uint32_t wait_loop_index;
+
+  /* store/restore channel configuration structure purpose */
+  uint32_t oldmodeconfiguration;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+
+  /* Check the DAC handle allocation */
+  /* Check if DAC running */
+  if ((hdac == NULL) || (sConfig == NULL))
+  {
+    status = HAL_ERROR;
+  }
+  else if (hdac->State == HAL_DAC_STATE_BUSY)
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hdac);
+
+    /* Store configuration */
+    oldmodeconfiguration = (hdac->Instance->MCR & (DAC_MCR_MODE1 << (Channel & 0x10UL)));
+
+    /* Disable the selected DAC channel */
+    CLEAR_BIT((hdac->Instance->CR), (DAC_CR_EN1 << (Channel & 0x10UL)));
+    /* Wait for ready bit to be de-asserted */
+    HAL_Delay(1);
+
+    /* Set mode in MCR  for calibration */
+    MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), 0U);
+
+    /* Enable the selected DAC channel calibration */
+    /* i.e. set DAC_CR_CENx bit */
+    SET_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
+
+    /* Init trimming counter */
+    /* Medium value */
+    trimmingvalue = 0x10UL;
+    delta = 0x08UL;
+    while (delta != 0UL)
+    {
+      /* Set candidate trimming */
+      MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
+
+      /* Wait minimum time needed between two calibration steps (OTRIM) */
+      /* Wait loop initialization and execution */
+      /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
+      /*       32 bits register capacity and handle low frequency. */
+      wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+      while (wait_loop_index != 0UL)
+      {
+        wait_loop_index--;
+      }
+
+      if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL)))
+      {
+        /* DAC_SR_CAL_FLAGx is HIGH try higher trimming */
+        trimmingvalue -= delta;
+      }
+      else
+      {
+        /* DAC_SR_CAL_FLAGx is LOW try lower trimming */
+        trimmingvalue += delta;
+      }
+      delta >>= 1UL;
+    }
+
+    /* Still need to check if right calibration is current value or one step below */
+    /* Indeed the first value that causes the DAC_SR_CAL_FLAGx bit to change from 0 to 1  */
+    /* Set candidate trimming */
+    MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
+
+    /* Wait minimum time needed between two calibration steps (OTRIM) */
+    /* Wait loop initialization and execution */
+    /* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed */
+    /*       32 bits register capacity and handle low frequency. */
+    wait_loop_index = ((DAC_DELAY_TRIM_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+    while (wait_loop_index != 0UL)
+    {
+      wait_loop_index--;
+    }
+
+    if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL)
+    {
+      /* Check trimming value below maximum */
+      if (trimmingvalue < 0x1FU)
+      {
+        /* Trimming is actually one value more */
+        trimmingvalue++;
+      }
+      /* Set right trimming */
+      MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL)));
+    }
+
+    /* Disable the selected DAC channel calibration */
+    /* i.e. clear DAC_CR_CENx bit */
+    CLEAR_BIT((hdac->Instance->CR), (DAC_CR_CEN1 << (Channel & 0x10UL)));
+
+    sConfig->DAC_TrimmingValue = trimmingvalue;
+    sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
+
+    /* Restore configuration */
+    MODIFY_REG(hdac->Instance->MCR, (DAC_MCR_MODE1 << (Channel & 0x10UL)), oldmodeconfiguration);
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdac);
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set the trimming mode and trimming value (user trimming mode applied).
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @param  sConfig DAC configuration structure updated with new DAC trimming value.
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @param  NewTrimmingValue DAC new trimming value
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,
+                                            uint32_t NewTrimmingValue)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+  assert_param(IS_DAC_NEWTRIMMINGVALUE(NewTrimmingValue));
+
+  /* Check the DAC handle and channel configuration struct allocation */
+  if ((hdac == NULL) || (sConfig == NULL))
+  {
+    status = HAL_ERROR;
+  }
+  else
+  {
+    /* Process locked */
+    __HAL_LOCK(hdac);
+
+    /* Set new trimming */
+    MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (NewTrimmingValue << (Channel & 0x10UL)));
+
+    /* Update trimming mode */
+    sConfig->DAC_UserTrimming = DAC_TRIMMING_USER;
+    sConfig->DAC_TrimmingValue = NewTrimmingValue;
+
+    /* Process unlocked */
+    __HAL_UNLOCK(hdac);
+  }
+  return status;
+}
+
+/**
+  * @brief  Return the DAC trimming value.
+  * @param  hdac DAC handle
+  * @param  Channel The selected DAC channel.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
+  *            @arg DAC_CHANNEL_2: DAC Channel2 selected (1)
+  *
+  *         (1) On this STM32 series, parameter not available on all instances.
+  *             Refer to device datasheet for channels availability.
+  * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F
+ */
+uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel)
+{
+  /* Check the parameter */
+  assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
+
+  /* Retrieve trimming */
+  return ((hdac->Instance->CCR & (DAC_CCR_OTRIM1 << (Channel & 0x10UL))) >> (Channel & 0x10UL));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup DACEx_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Extended Peripheral Control functions
+  *
+@verbatim
+  ==============================================================================
+             ##### Peripheral Control functions #####
+  ==============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Set the specified data holding register value for DAC channel.
+
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Return the last data output value of the selected DAC channel.
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
+  *         the configuration information for the specified DAC.
+  * @retval The selected DAC channel data output value.
+  */
+uint32_t HAL_DACEx_DualGetValue(const DAC_HandleTypeDef *hdac)
+{
+  uint32_t tmp = 0UL;
+
+  tmp |= hdac->Instance->DOR1;
+
+  tmp |= hdac->Instance->DOR2 << 16UL;
+
+  /* Returns the DAC channel data output register value */
+  return tmp;
+}
+
+
+/**
+  * @}
+  */
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup DACEx_Private_Functions DACEx private functions
+  *  @brief    Extended private functions
+  * @{
+  */
+
+
+/**
+  * @brief  DMA conversion complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ConvCpltCallbackCh2(hdac);
+#else
+  HAL_DACEx_ConvCpltCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+  hdac->State = HAL_DAC_STATE_READY;
+}
+
+/**
+  * @brief  DMA half transfer complete callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
+{
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+  /* Conversion complete callback */
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ConvHalfCpltCallbackCh2(hdac);
+#else
+  HAL_DACEx_ConvHalfCpltCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA error callback.
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
+  *                the configuration information for the specified DMA module.
+  * @retval None
+  */
+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)
+{
+  DAC_HandleTypeDef *hdac = (DAC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Set DAC error code to DMA error */
+  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
+
+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
+  hdac->ErrorCallbackCh2(hdac);
+#else
+  HAL_DACEx_ErrorCallbackCh2(hdac);
+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
+
+  hdac->State = HAL_DAC_STATE_READY;
+}
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* DAC1 || DAC2 || DAC3 || DAC4 */
+
+#endif /* HAL_DAC_MODULE_ENABLED */
+
+/**
+  * @}
+  */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_hrtim.c b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_hrtim.c
new file mode 100644
index 0000000..cf99f6f
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_hrtim.c
@@ -0,0 +1,11077 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_hrtim.c
+  * @author  MCD Application Team
+  * @brief   TIM HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the High Resolution Timer (HRTIM) peripheral:
+  *           + HRTIM Initialization
+  *           + DLL Calibration Start
+  *           + Timer Time Base Unit Configuration
+  *           + Simple Time Base Start/Stop
+  *           + Simple Time Base Start/Stop Interrupt
+  *           + Simple Time Base Start/Stop DMA Request
+  *           + Simple Output Compare/PWM Channel Configuration
+  *           + Simple Output Compare/PWM Channel Start/Stop Interrupt
+  *           + Simple Output Compare/PWM Channel Start/Stop DMA Request
+  *           + Simple Input Capture Channel Configuration
+  *           + Simple Input Capture Channel Start/Stop Interrupt
+  *           + Simple Input Capture Channel Start/Stop DMA Request
+  *           + Simple One Pulse Channel Configuration
+  *           + Simple One Pulse Channel Start/Stop Interrupt
+  *           + HRTIM External Synchronization Configuration
+  *           + HRTIM Burst Mode Controller Configuration
+  *           + HRTIM Burst Mode Controller Enabling
+  *           + HRTIM External Events Conditioning Configuration
+  *           + HRTIM Faults Conditioning Configuration
+  *           + HRTIM Faults Enabling
+  *           + HRTIM ADC trigger Configuration
+  *           + Waveform Timer Configuration
+  *           + Waveform Event Filtering Configuration
+  *           + Waveform Dead Time Insertion Configuration
+  *           + Waveform Chopper Mode Configuration
+  *           + Waveform Compare Unit Configuration
+  *           + Waveform Capture Unit Configuration
+  *           + Waveform Output Configuration
+  *           + Waveform Counter Start/Stop
+  *           + Waveform Counter Start/Stop Interrupt
+  *           + Waveform Counter Start/Stop DMA Request
+  *           + Waveform Output Enabling
+  *           + Waveform Output Level Set/Get
+  *           + Waveform Output State Get
+  *           + Waveform Burst DMA Operation Configuration
+  *           + Waveform Burst DMA Operation Start
+  *           + Waveform Timer Counter Software Reset
+  *           + Waveform Capture Software Trigger
+  *           + Waveform Burst Mode Controller Software Trigger
+  *           + Waveform Timer Pre-loadable Registers Update Enabling
+  *           + Waveform Timer Pre-loadable Registers Software Update
+  *           + Waveform Timer Delayed Protection Status Get
+  *           + Waveform Timer Burst Status Get
+  *           + Waveform Timer Push-Pull Status Get
+  *           + Peripheral State Get
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+==============================================================================
+                      ##### Simple mode v.s. waveform mode #####
+==============================================================================
+  [..] The HRTIM HAL API is split into 2 categories:
+    (#)Simple functions: these functions allow for using a HRTIM timer as a
+       general purpose timer with high resolution capabilities.
+       HRTIM simple modes are managed through the set of functions named
+       HAL_HRTIM_Simple<Function>. These functions are similar in name and usage
+       to the one defined for the TIM peripheral. When a HRTIM timer operates in
+       simple mode, only a very limited set of HRTIM features are used.
+       Following simple modes are proposed:
+         (++)Output compare mode,
+         (++)PWM output mode,
+         (++)Input capture mode,
+         (++)One pulse mode.
+    (#)Waveform functions: These functions allow taking advantage of the HRTIM
+       flexibility to produce numerous types of control signal. When a HRTIM timer
+       operates in waveform mode, all the HRTIM features are accessible without
+       any restriction. HRTIM waveform modes are managed through the set of
+       functions named HAL_HRTIM_Waveform<Function>
+
+                      ##### How to use this driver #####
+==============================================================================
+    [..]
+     (#)Initialize the HRTIM low level resources by implementing the
+        HAL_HRTIM_MspInit() function:
+        (##)Enable the HRTIM clock source using __HRTIMx_CLK_ENABLE()
+        (##)Connect HRTIM pins to MCU I/Os
+            (+++) Enable the clock for the HRTIM GPIOs using the following
+                  function: __HAL_RCC_GPIOx_CLK_ENABLE()
+            (+++) Configure these GPIO pins in Alternate Function mode using
+                  HAL_GPIO_Init()
+        (##)When using DMA to control data transfer (e.g HAL_HRTIM_SimpleBaseStart_DMA())
+            (+++)Enable the DMAx interface clock using __DMAx_CLK_ENABLE()
+            (+++)Initialize the DMA handle
+            (+++)Associate the initialized DMA handle to the appropriate DMA
+                 handle of the HRTIM handle using __HAL_LINKDMA()
+            (+++)Initialize the DMA channel using HAL_DMA_Init()
+            (+++)Configure the priority and enable the NVIC for the transfer
+                 complete interrupt on the DMA channel using HAL_NVIC_SetPriority()
+                 and HAL_NVIC_EnableIRQ()
+        (##)In case of using interrupt mode (e.g HAL_HRTIM_SimpleBaseStart_IT())
+            (+++)Configure the priority and enable the NVIC for the concerned
+                 HRTIM interrupt using HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
+
+    (#)Initialize the HRTIM HAL using HAL_HRTIM_Init(). The HRTIM configuration
+       structure (field of the HRTIM handle) specifies which global interrupt of
+       whole HRTIM must be enabled (Burst mode period, System fault, Faults).
+       It also contains the HRTIM external synchronization configuration. HRTIM
+       can act as a master (generating a synchronization signal) or as a slave
+       (waiting for a trigger to be synchronized).
+
+    (#)Start the high resolution unit using HAL_HRTIM_DLLCalibrationStart(). DLL
+       calibration is executed periodically and compensate for potential voltage
+       and temperature drifts. DLL calibration period is specified by the
+       CalibrationRate argument.
+
+    (#)HRTIM timers cannot be used until the high resolution unit is ready. This
+       can be checked using HAL_HRTIM_PollForDLLCalibration(): this function returns
+       HAL_OK if DLL calibration is completed or HAL_TIMEOUT if the DLL calibration
+       is still going on when timeout given as argument expires. DLL calibration
+       can also be started in interrupt mode using HAL_HRTIM_DLLCalibrationStart_IT().
+       In that case an interrupt is generated when the DLL calibration is completed.
+       Note that as DLL calibration is executed on a periodic basis an interrupt
+       will be generated at the end of every DLL calibration operation
+      (worst case: one interrupt every 14 micro seconds !).
+
+     (#) Configure HRTIM resources shared by all HRTIM timers
+        (##)Burst Mode Controller:
+                (+++)HAL_HRTIM_BurstModeConfig(): configures the HRTIM burst mode
+                     controller: operating mode (continuous or one-shot mode), clock
+                     (source, prescaler) , trigger(s), period, idle duration.
+        (##)External Events Conditioning:
+                (+++)HAL_HRTIM_EventConfig(): configures the conditioning of an
+                     external event channel: source, polarity, edge-sensitivity.
+                     External event can be used as triggers (timer reset, input
+                     capture, burst mode, ADC triggers, delayed protection)
+                     They can also be used to set or reset timer outputs. Up to
+                     10 event channels are available.
+                (+++)HAL_HRTIM_EventPrescalerConfig(): configures the external
+                     event sampling clock (used for digital filtering).
+        (##)Fault Conditioning:
+                (+++)HAL_HRTIM_FaultConfig(): configures the conditioning of a
+                     fault channel: source, polarity, edge-sensitivity. Fault
+                     channels are used to disable the outputs in case of an
+                     abnormal operation. Up to 6 fault channels are available.
+                (+++)HAL_HRTIM_FaultPrescalerConfig(): configures the fault
+                     sampling clock (used for digital filtering).
+                (+++)HAL_HRTIM_FaultModeCtl(): Enables or disables fault input(s)
+                     circuitry. By default all fault inputs are disabled.
+        (##)ADC trigger:
+                (+++)HAL_HRTIM_ADCTriggerConfig(): configures the source triggering
+                     the update of the ADC trigger register and the ADC trigger.
+                     4 independent triggers are available to start both the regular
+                     and the injected sequencers of the 2 ADCs
+
+     (#) Configure HRTIM timer time base using HAL_HRTIM_TimeBaseConfig(). This
+         function must be called whatever the HRTIM timer operating mode is
+         (simple v.s. waveform). It configures mainly:
+        (##)The HRTIM  timer counter operating mode (continuous v.s. one shot)
+        (##)The HRTIM  timer clock prescaler
+        (##)The HRTIM  timer period
+        (##)The HRTIM  timer repetition counter
+
+     *** If the HRTIM timer operates in simple mode ***
+     ===================================================
+     [..]
+     (#) Start or Stop simple timers
+              (++)Simple time base: HAL_HRTIM_SimpleBaseStart(),HAL_HRTIM_SimpleBaseStop(),
+                  HAL_HRTIM_SimpleBaseStart_IT(),HAL_HRTIM_SimpleBaseStop_IT(),
+                  HAL_HRTIM_SimpleBaseStart_DMA(),HAL_HRTIM_SimpleBaseStop_DMA().
+              (++)Simple output compare: HAL_HRTIM_SimpleOCChannelConfig(),
+                  HAL_HRTIM_SimpleOCStart(),HAL_HRTIM_SimpleOCStop(),
+                  HAL_HRTIM_SimpleOCStart_IT(),HAL_HRTIM_SimpleOCStop_IT(),
+                  HAL_HRTIM_SimpleOCStart_DMA(),HAL_HRTIM_SimpleOCStop_DMA(),
+              (++)Simple PWM output: HAL_HRTIM_SimplePWMChannelConfig(),
+                  HAL_HRTIM_SimplePWMStart(),HAL_HRTIM_SimplePWMStop(),
+                  HAL_HRTIM_SimplePWMStart_IT(),HAL_HRTIM_SimplePWMStop_IT(),
+                  HAL_HRTIM_SimplePWMStart_DMA(),HAL_HRTIM_SimplePWMStop_DMA(),
+              (++)Simple input capture: HAL_HRTIM_SimpleCaptureChannelConfig(),
+                  HAL_HRTIM_SimpleCaptureStart(),HAL_HRTIM_SimpleCaptureStop(),
+                  HAL_HRTIM_SimpleCaptureStart_IT(),HAL_HRTIM_SimpleCaptureStop_IT(),
+                  HAL_HRTIM_SimpleCaptureStart_DMA(),HAL_HRTIM_SimpleCaptureStop_DMA().
+              (++)Simple one pulse: HAL_HRTIM_SimpleOnePulseChannelConfig(),
+                  HAL_HRTIM_SimpleOnePulseStart(),HAL_HRTIM_SimpleOnePulseStop(),
+                  HAL_HRTIM_SimpleOnePulseStart_IT(),HAL_HRTIM_SimpleOnePulseStop_It().
+
+     *** If the HRTIM timer operates in waveform mode ***
+     ====================================================
+     [..]
+     (#) Completes waveform timer configuration
+              (++)HAL_HRTIM_WaveformTimerConfig(): configuration of a HRTIM timer
+                  operating in wave form mode mainly consists in:
+                (+++)Enabling the HRTIM timer interrupts and DMA requests.
+                (+++)Enabling the half mode for the HRTIM timer.
+                (+++)Defining how the HRTIM timer reacts to external synchronization input.
+                (+++)Enabling the push-pull mode for the HRTIM timer.
+                (+++)Enabling the fault channels for the HRTIM timer.
+                (+++)Enabling the dead-time insertion for the HRTIM timer.
+                (+++)Setting the delayed protection mode for the HRTIM timer (source and outputs
+                     on which the delayed protection are applied).
+                (+++)Specifying the HRTIM timer update and reset triggers.
+                (+++)Specifying the HRTIM timer registers update policy (e.g. pre-load enabling).
+              (++)HAL_HRTIM_TimerEventFilteringConfig(): configures external
+                  event blanking and windowing circuitry of a HRTIM timer:
+                (+++)Blanking:  to mask external events during a defined  time period a defined time period
+                (+++)Windowing, to enable external events only during a defined time period
+              (++)HAL_HRTIM_DeadTimeConfig(): configures the dead-time insertion
+                  unit for a HRTIM timer. Allows to generate a couple of
+                  complementary signals from a single reference waveform,
+                  with programmable delays between active state.
+              (++)HAL_HRTIM_ChopperModeConfig(): configures the parameters of
+                  the high-frequency carrier signal added on top of the timing
+                  unit output. Chopper mode can be enabled or disabled for each
+                   timer output separately (see  HAL_HRTIM_WaveformOutputConfig()).
+              (++)HAL_HRTIM_BurstDMAConfig(): configures the burst DMA burst
+                  controller. Allows having multiple HRTIM registers updated
+                  with a single DMA request. The burst DMA operation is started
+                  by calling HAL_HRTIM_BurstDMATransfer().
+              (++)HAL_HRTIM_WaveformCompareConfig():configures the compare unit
+                  of a HRTIM timer. This operation consists in setting the
+                  compare value and possibly specifying the auto delayed mode
+                  for compare units 2 and 4 (allows to have compare events
+                  generated relatively to capture events). Note that when auto
+                  delayed mode is needed, the capture unit associated to the
+                  compare unit must be configured separately.
+              (++)HAL_HRTIM_WaveformCaptureConfig(): configures the capture unit
+                  of a HRTIM timer. This operation consists in specifying the
+                  source(s)  triggering the capture (timer register update event,
+                  external event, timer output set/reset event, other HRTIM
+                  timer related events).
+              (++)HAL_HRTIM_WaveformOutputConfig(): configuration of a HRTIM timer
+                  output mainly consists in:
+                (+++)Setting the output polarity (active high or active low),
+                (+++)Defining the set/reset crossbar for the output,
+                (+++)Specifying the fault level (active or inactive) in IDLE and FAULT states.,
+
+     (#) Set waveform timer output(s) level
+              (++)HAL_HRTIM_WaveformSetOutputLevel(): forces the output to its
+                  active or inactive level. For example, when deadtime insertion
+                  is enabled it is necessary to force the output level by software
+                  to have the outputs in a complementary state as soon as the RUN mode is entered.
+
+     (#) Enable or Disable waveform timer output(s)
+              (++)HAL_HRTIM_WaveformOutputStart(),HAL_HRTIM_WaveformOutputStop().
+
+     (#) Start or Stop waveform HRTIM timer(s).
+              (++)HAL_HRTIM_WaveformCountStart(),HAL_HRTIM_WaveformCountStop(),
+              (++)HAL_HRTIM_WaveformCountStart_IT(),HAL_HRTIM_WaveformCountStop_IT(),
+              (++)HAL_HRTIM_WaveformCountStart_DMA(),HAL_HRTIM_WaveformCountStop_DMA(),
+     (#) Burst mode controller enabling:
+              (++)HAL_HRTIM_BurstModeCtl(): activates or de-activates the
+                  burst mode controller.
+
+     (#) Some HRTIM operations can be triggered by software:
+              (++)HAL_HRTIM_BurstModeSoftwareTrigger(): calling this function
+                  trigs the burst operation.
+              (++)HAL_HRTIM_SoftwareCapture(): calling this function trigs the
+                  capture of the HRTIM timer counter.
+              (++)HAL_HRTIM_SoftwareUpdate(): calling this function trigs the
+                  update of the pre-loadable registers of the HRTIM timer
+              (++)HAL_HRTIM_SoftwareReset():calling this function resets the
+                  HRTIM timer counter.
+
+     (#) Some functions can be used any time to retrieve HRTIM timer related
+            information
+              (++)HAL_HRTIM_GetCapturedValue(): returns actual value of the
+                  capture register of the designated capture unit.
+              (++)HAL_HRTIM_WaveformGetOutputLevel(): returns actual level
+                 (ACTIVE/INACTIVE) of the designated timer output.
+              (++)HAL_HRTIM_WaveformGetOutputState():returns actual state
+                 (IDLE/RUN/FAULT) of the designated timer output.
+              (++)HAL_HRTIM_GetDelayedProtectionStatus():returns actual level
+                 (ACTIVE/INACTIVE) of the designated output when the delayed
+                  protection was triggered.
+              (++)HAL_HRTIM_GetBurstStatus(): returns the actual status
+                 (ACTIVE/INACTIVE) of the burst mode controller.
+              (++)HAL_HRTIM_GetCurrentPushPullStatus(): when the push-pull mode
+                 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
+                 the push-pull status indicates on which output the signal is currently
+                 active (e.g signal applied on output 1 and output 2 forced
+                 inactive or vice versa).
+             (++)HAL_HRTIM_GetIdlePushPullStatus(): when the push-pull mode
+                 is enabled for the HRTIM timer (see HAL_HRTIM_WaveformTimerConfig()),
+                 the idle push-pull status indicates during which period the
+                 delayed protection request occurred (e.g. protection occurred
+                 when the output 1 was active and output 2 forced inactive or
+                 vice versa).
+
+     (#) Some functions can be used any time to retrieve actual HRTIM status
+             (++)HAL_HRTIM_GetState(): returns actual HRTIM instance HAL state.
+
+     *** Callback registration ***
+     =============================
+     [..]
+     The compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS when set to 1
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions HAL_HRTIM_RegisterCallback() or HAL_HRTIM_TIMxRegisterCallback()
+     to register an interrupt callback.
+
+     [..]
+     Function HAL_HRTIM_RegisterCallback() allows to register following callbacks:
+       (+) Fault1Callback               : Fault 1 interrupt callback function
+       (+) Fault2Callback               : Fault 2 interrupt callback function
+       (+) Fault3Callback               : Fault 3 interrupt callback function
+       (+) Fault4Callback               : Fault 4 interrupt callback function
+       (+) Fault5Callback               : Fault 5 interrupt callback function
+       (+) Fault6Callback               : Fault 6 interrupt callback function
+       (+) SystemFaultCallback          : System fault interrupt callback function
+       (+) DLLCalibrationReadyCallback  : DLL Ready interrupt callback function
+       (+) BurstModePeriodCallback      : Burst mode period interrupt callback function
+       (+) SynchronizationEventCallback : Sync Input interrupt callback function
+       (+) ErrorCallback                : DMA error callback function
+       (+) MspInitCallback              : HRTIM MspInit callback function
+       (+) MspDeInitCallback            : HRTIM MspInit callback function
+
+     [..]
+     Function HAL_HRTIM_TIMxRegisterCallback() allows to register following callbacks:
+       (+) RegistersUpdateCallback   : Timer x Update interrupt callback function
+       (+) RepetitionEventCallback   : Timer x Repetition interrupt callback function
+       (+) Compare1EventCallback     : Timer x Compare 1 match interrupt callback function
+       (+) Compare2EventCallback     : Timer x Compare 2 match interrupt callback function
+       (+) Compare3EventCallback     : Timer x Compare 3 match interrupt callback function
+       (+) Compare4EventCallback     : Timer x Compare 4 match interrupt callback function
+       (+) Capture1EventCallback     : Timer x Capture 1 interrupts callback function
+       (+) Capture2EventCallback     : Timer x Capture 2 interrupts callback function
+       (+) DelayedProtectionCallback : Timer x Delayed protection interrupt callback function
+       (+) CounterResetCallback      : Timer x counter reset/roll-over interrupt callback function
+       (+) Output1SetCallback        : Timer x output 1 set interrupt callback function
+       (+) Output1ResetCallback      : Timer x output 1 reset interrupt callback function
+       (+) Output2SetCallback        : Timer x output 2 set interrupt callback function
+       (+) Output2ResetCallback      : Timer x output 2 reset interrupt callback function
+       (+) BurstDMATransferCallback  : Timer x Burst DMA completed interrupt callback function
+
+     [..]
+     Both functions take as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+
+     [..]
+     Use function HAL_HRTIM_UnRegisterCallback or HAL_HRTIM_TIMxUnRegisterCallback
+     to reset a callback to the default weak function. Both functions take  as parameters
+     the HAL peripheral handle and the Callback ID.
+
+     [..]
+     By default, after the HAL_HRTIM_Init() and when the state is HAL_HRTIM_STATE_RESET
+     all callbacks are set to the corresponding weak functions (e.g HAL_HRTIM_Fault1Callback)
+     Exception done for MspInit and MspDeInit functions that are reset to the legacy
+     weak functions in the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() only when these
+     callbacks are null (not registered beforehand). If MspInit or MspDeInit are
+     not null, the HAL_HRTIM_Init()/ HAL_HRTIM_DeInit() keep and use the user
+     MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+
+     [..]
+     Callbacks can be registered/unregistered in HAL_HRTIM_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in HAL_HRTIM_STATE_READY or HAL_HRTIM_STATE_RESET states, thus registered
+     (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using HAL_HRTIM_RegisterCallback() before calling HAL_HRTIM_DeInit()
+     or HAL_HRTIM_Init() function.
+
+     [..]
+     When the compilation flag USE_HAL_HRTIM_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all
+     callbacks are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+#ifdef HAL_HRTIM_MODULE_ENABLED
+
+#if defined(HRTIM1)
+
+/** @defgroup HRTIM HRTIM
+  * @brief HRTIM HAL module driver
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup HRTIM_Private_Defines HRTIM Private Define
+  * @{
+  */
+#define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
+                           HRTIM_FLTR_FLT2EN |\
+                           HRTIM_FLTR_FLT3EN |\
+                           HRTIM_FLTR_FLT4EN | \
+                           HRTIM_FLTR_FLT5EN | \
+                           HRTIM_FLTR_FLT6EN)
+
+#define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER  |\
+                                      HRTIM_TIMUPDATETRIGGER_TIMER_A |\
+                                      HRTIM_TIMUPDATETRIGGER_TIMER_B |\
+                                      HRTIM_TIMUPDATETRIGGER_TIMER_C |\
+                                      HRTIM_TIMUPDATETRIGGER_TIMER_D |\
+                                      HRTIM_TIMUPDATETRIGGER_TIMER_E |\
+                                      HRTIM_TIMUPDATETRIGGER_TIMER_F)
+
+#define HRTIM_FLTINR1_FLTxLCK ((HRTIM_FAULTLOCK_READONLY)        | \
+                               (HRTIM_FAULTLOCK_READONLY << 8U)  | \
+                               (HRTIM_FAULTLOCK_READONLY << 16U) | \
+                               (HRTIM_FAULTLOCK_READONLY << 24U))
+
+#define HRTIM_FLTINR2_FLTxLCK ((HRTIM_FAULTLOCK_READONLY)        | \
+                               (HRTIM_FAULTLOCK_READONLY << 8U))
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup HRTIM_Private_Variables HRTIM Private Variables
+  * @{
+  */
+static uint32_t TimerIdxToTimerId[] =
+{
+  HRTIM_TIMERID_TIMER_A,
+  HRTIM_TIMERID_TIMER_B,
+  HRTIM_TIMERID_TIMER_C,
+  HRTIM_TIMERID_TIMER_D,
+  HRTIM_TIMERID_TIMER_E,
+  HRTIM_TIMERID_TIMER_F,
+  HRTIM_TIMERID_MASTER,
+};
+/**
+  * @}
+  */
+
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup HRTIM_Private_Functions HRTIM Private Functions
+  * @{
+  */
+static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim,
+                                    const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg);
+
+static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim,
+                                        uint32_t TimerIdx,
+                                        const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg);
+
+static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
+                                        const HRTIM_TimerCfgTypeDef *pTimerCfg);
+
+static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx,
+                                            const HRTIM_TimerCfgTypeDef *pTimerCfg);
+
+static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             const HRTIM_TimerCtlTypeDef *pTimerCtl);
+
+static void  HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             uint32_t pRollOverMode);
+
+
+static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim,
+                                    uint32_t TimerIdx,
+                                    uint32_t CaptureUnit,
+                                    uint32_t Event);
+
+static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim,
+                               uint32_t TimerIdx,
+                               uint32_t Output,
+                               const HRTIM_OutputCfgTypeDef *pOutputCfg);
+
+static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
+                              uint32_t Event,
+                              const HRTIM_EventCfgTypeDef *pEventCfg);
+
+static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim,
+                                  uint32_t TimerIdx,
+                                  uint32_t Event);
+
+static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim,
+                                      uint32_t TimerIdx,
+                                      uint32_t OCChannel);
+
+static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim,
+                                       uint32_t TimerIdx,
+                                       uint32_t OCChannel);
+
+static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim,
+                                                         uint32_t TimerIdx);
+
+static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim,
+                                         const DMA_HandleTypeDef *hdma);
+
+static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim,
+                                       uint32_t TimerIdx);
+
+static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim);
+
+static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim);
+
+static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim,
+                            uint32_t TimerIdx);
+
+static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma);
+
+static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma);
+
+static void HRTIM_DMAError(DMA_HandleTypeDef *hdma);
+
+static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+/** @defgroup HRTIM_Exported_Functions HRTIM Exported Functions
+  * @{
+  */
+
+/** @defgroup HRTIM_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+@verbatim
+ ===============================================================================
+              ##### Initialization and Time Base Configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize a HRTIM instance
+      (+) De-initialize a HRTIM instance
+      (+) Initialize the HRTIM MSP
+      (+) De-initialize the HRTIM MSP
+      (+) Start the high-resolution unit (start DLL calibration)
+      (+) Check that the high resolution unit is ready (DLL calibration done)
+      (+) Configure the time base unit of a HRTIM timer
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize a HRTIM instance
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim)
+{
+  uint8_t timer_idx;
+  uint32_t hrtim_mcr;
+
+  /* Check the HRTIM handle allocation */
+  if (hhrtim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
+  assert_param(IS_HRTIM_IT(hhrtim->Init.HRTIMInterruptRequests));
+
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+  if (hhrtim->State == HAL_HRTIM_STATE_RESET)
+  {
+    /* Initialize callback function pointers to their default values */
+    hhrtim->Fault1Callback               = HAL_HRTIM_Fault1Callback;
+    hhrtim->Fault2Callback               = HAL_HRTIM_Fault2Callback;
+    hhrtim->Fault3Callback               = HAL_HRTIM_Fault3Callback;
+    hhrtim->Fault4Callback               = HAL_HRTIM_Fault4Callback;
+    hhrtim->Fault5Callback               = HAL_HRTIM_Fault5Callback;
+    hhrtim->Fault6Callback               = HAL_HRTIM_Fault6Callback;
+    hhrtim->SystemFaultCallback          = HAL_HRTIM_SystemFaultCallback;
+    hhrtim->DLLCalibrationReadyCallback  = HAL_HRTIM_DLLCalibrationReadyCallback;
+    hhrtim->BurstModePeriodCallback      = HAL_HRTIM_BurstModePeriodCallback;
+    hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
+    hhrtim->ErrorCallback                = HAL_HRTIM_ErrorCallback;
+    hhrtim->RegistersUpdateCallback      = HAL_HRTIM_RegistersUpdateCallback;
+    hhrtim->RepetitionEventCallback      = HAL_HRTIM_RepetitionEventCallback;
+    hhrtim->Compare1EventCallback        = HAL_HRTIM_Compare1EventCallback;
+    hhrtim->Compare2EventCallback        = HAL_HRTIM_Compare2EventCallback;
+    hhrtim->Compare3EventCallback        = HAL_HRTIM_Compare3EventCallback;
+    hhrtim->Compare4EventCallback        = HAL_HRTIM_Compare4EventCallback;
+    hhrtim->Capture1EventCallback        = HAL_HRTIM_Capture1EventCallback;
+    hhrtim->Capture2EventCallback        = HAL_HRTIM_Capture2EventCallback;
+    hhrtim->DelayedProtectionCallback    = HAL_HRTIM_DelayedProtectionCallback;
+    hhrtim->CounterResetCallback         = HAL_HRTIM_CounterResetCallback;
+    hhrtim->Output1SetCallback           = HAL_HRTIM_Output1SetCallback;
+    hhrtim->Output1ResetCallback         = HAL_HRTIM_Output1ResetCallback;
+    hhrtim->Output2SetCallback           = HAL_HRTIM_Output2SetCallback;
+    hhrtim->Output2ResetCallback         = HAL_HRTIM_Output2ResetCallback;
+    hhrtim->BurstDMATransferCallback     = HAL_HRTIM_BurstDMATransferCallback;
+
+    if (hhrtim->MspInitCallback == NULL)
+    {
+      hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
+    }
+  }
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+
+  /* Set the HRTIM state */
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Initialize the DMA handles */
+  hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
+  hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
+  hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
+  hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
+  hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
+  hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
+  hhrtim->hdmaTimerF = (DMA_HandleTypeDef *)NULL;
+
+  /* HRTIM output synchronization configuration (if required) */
+  if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
+  {
+    /* Check parameters */
+    assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(hhrtim->Init.SyncOutputSource));
+    assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
+
+    /* The synchronization output initialization procedure must be done prior
+       to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
+    */
+    if (hhrtim->Instance == HRTIM1)
+    {
+      /* Enable the HRTIM peripheral clock */
+      __HAL_RCC_HRTIM1_CLK_ENABLE();
+    }
+
+    hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
+
+    /* Set the event to be sent on the synchronization output */
+    hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
+    hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
+
+    /* Set the polarity of the synchronization output */
+    hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
+    hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
+
+    /* Update the HRTIM registers */
+    hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
+  }
+
+  /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+  hhrtim->MspInitCallback(hhrtim);
+#else
+  HAL_HRTIM_MspInit(hhrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+
+  /* HRTIM input synchronization configuration (if required) */
+  if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
+  {
+    /* Check parameters */
+    assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
+
+    hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
+
+    /* Set the synchronization input source */
+    hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
+    hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
+
+    /* Update the HRTIM registers */
+    hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
+  }
+
+  /* Initialize the HRTIM state*/
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Initialize the lock status of the HRTIM HAL API */
+  __HAL_UNLOCK(hhrtim);
+
+  /* Initialize timer related parameters */
+  for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+       timer_idx <= HRTIM_TIMERINDEX_MASTER ;
+       timer_idx++)
+  {
+    hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
+    hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
+    hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
+    hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
+    hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
+    hhrtim->TimerParam[timer_idx].DMASize = 0U;
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  De-initialize a HRTIM instance
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_DeInit(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Check the HRTIM handle allocation */
+  if (hhrtim == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_ALL_INSTANCE(hhrtim->Instance));
+
+  /* Set the HRTIM state */
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* DeInit the low level hardware */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+  if (hhrtim->MspDeInitCallback == NULL)
+  {
+    hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
+  }
+
+  hhrtim->MspDeInitCallback(hhrtim);
+#else
+  HAL_HRTIM_MspDeInit(hhrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  MSP initialization for a HRTIM instance
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+__weak void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_HRTIM_MspInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  MSP de-initialization of a HRTIM instance
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+__weak void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_HRTIM_MspDeInit could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Start the DLL calibration
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  CalibrationRate DLL calibration period
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
+  *                    @arg HRTIM_CALIBRATIONRATE_0: Periodic DLL calibration. T=6.168 ms
+  *                    @arg HRTIM_CALIBRATIONRATE_1: Periodic DLL calibration. T=0.771 ms
+  *                    @arg HRTIM_CALIBRATIONRATE_2: Periodic DLL calibration. T=0.096 ms
+  *                    @arg HRTIM_CALIBRATIONRATE_3: Periodic DLL calibration. T=0.012 ms
+  * @retval HAL status
+  * @note This function locks the HRTIM instance. HRTIM instance is unlocked
+  *       within the HAL_HRTIM_PollForDLLCalibration function, just before
+  *       exiting the function.
+  */
+HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t CalibrationRate)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
+  {
+    /* One shot DLL calibration */
+    CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
+    SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
+  }
+  else
+  {
+    /* Periodic DLL calibration */
+    SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
+    MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
+    SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
+  }
+
+  /* Set HRTIM state */
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the DLL calibration.
+  *         DLL ready interrupt is enabled
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  CalibrationRate DLL calibration period
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_SINGLE_CALIBRATION: One shot DLL calibration
+  *                    @arg HRTIM_CALIBRATIONRATE_0: Periodic DLL calibration. T=6.168 ms
+  *                    @arg HRTIM_CALIBRATIONRATE_1: Periodic DLL calibration. T=0.771 ms
+  *                    @arg HRTIM_CALIBRATIONRATE_2: Periodic DLL calibration. T=0.096 ms
+  *                    @arg HRTIM_CALIBRATIONRATE_3: Periodic DLL calibration. T=0.012 ms
+  * @retval HAL status
+  * @note This function locks the HRTIM instance. HRTIM instance is unlocked
+  *       within the IRQ processing function when processing the DLL ready
+  *       interrupt.
+  * @note If this function is called for periodic calibration, the DLLRDY
+  *       interrupt is generated every time the calibration completes which
+  *       will significantly increases the overall interrupt rate.
+  */
+HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t CalibrationRate)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable DLL Ready interrupt flag */
+  __HAL_HRTIM_ENABLE_IT(hhrtim, HRTIM_IT_DLLRDY);
+
+  if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
+  {
+    /* One shot DLL calibration */
+    CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
+    SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
+  }
+  else
+  {
+    /* Periodic DLL calibration */
+    SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
+    MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
+    SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
+  }
+
+  /* Set HRTIM state */
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll the DLL calibration ready flag and returns when the flag is
+  *         set (DLL calibration completed) or upon timeout expiration.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Timeout Timeout duration in millisecond
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  tickstart = HAL_GetTick();
+
+  /* Check End of conversion flag */
+  while (__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET)
+  {
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+      {
+        hhrtim->State = HAL_HRTIM_STATE_ERROR;
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Set HRTIM State */
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the time base unit of a timer
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  pTimeBaseCfg pointer to the time base configuration structure
+  * @note This function must be called prior starting the timer
+  * @note   The time-base unit initialization parameters specify:
+  *           The timer counter operating mode (continuous, one shot),
+  *           The timer clock prescaler,
+  *           The timer period,
+  *           The timer repetition counter.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx,
+                                           const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+  assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
+  assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Set the HRTIM state */
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+  {
+    /* Configure master timer time base unit */
+    HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
+  }
+  else
+  {
+    /* Configure timing unit time base unit */
+    HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
+  }
+
+  /* Set HRTIM state */
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Exported_Functions_Group2 Simple time base mode functions
+  *  @brief    Simple time base mode functions.
+@verbatim
+ ===============================================================================
+              ##### Simple time base mode functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start simple time base
+      (+) Stop simple time base
+      (+) Start simple time base and enable interrupt
+      (+) Stop simple time base and disable interrupt
+      (+) Start simple time base and enable DMA transfer
+      (+) Stop simple time base and disable DMA transfer
+      -@-  When a HRTIM timer operates in simple time base mode, the timer
+           counter counts from 0 to the period value.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Start the counter of a timer operating in simple time base mode.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index.
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the counter of a timer operating in simple time base mode.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index.
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Disable the timer counter */
+  __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the counter of a timer operating in simple time base mode
+  *         (Timer repetition interrupt is enabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index.
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable the repetition interrupt */
+  if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+  {
+    __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
+  }
+  else
+  {
+    __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
+  }
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the counter of a timer operating in simple time base mode
+  *         (Timer repetition interrupt is disabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index.
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Disable the repetition interrupt */
+  if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+  {
+    __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, HRTIM_MASTER_IT_MREP);
+  }
+  else
+  {
+    __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
+  }
+
+  /* Disable the timer counter */
+  __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the counter of a timer operating in simple time base mode
+  *         (Timer repetition DMA request is enabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index.
+  *                   This parameter can be one of the following values:
+  *                    @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                    @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                    @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                    @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                    @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                    @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  SrcAddr DMA transfer source address
+  * @param  DestAddr DMA transfer destination address
+  * @param  Length The length of data items (data size) to be transferred
+  *                     from source to destination
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t TimerIdx,
+                                                uint32_t SrcAddr,
+                                                uint32_t DestAddr,
+                                                uint32_t Length)
+{
+  DMA_HandleTypeDef *hdma;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  if (hhrtim->State == HAL_HRTIM_STATE_READY)
+  {
+    if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      hhrtim->State = HAL_HRTIM_STATE_BUSY;
+    }
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  /* Get the timer DMA handler */
+  hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+  if (hdma == NULL)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  /* Set the DMA transfer completed callback */
+  if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+  {
+    hdma->XferCpltCallback = HRTIM_DMAMasterCplt;
+  }
+  else
+  {
+    hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+  }
+
+  /* Set the DMA error callback */
+  hdma->XferErrorCallback = HRTIM_DMAError ;
+
+  /* Enable the DMA channel */
+  if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  /* Enable the timer repetition DMA request */
+  if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+  {
+    __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
+  }
+  else
+  {
+    __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
+  }
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the counter of a timer operating in simple time base mode
+  *         (Timer repetition DMA request is disabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index.
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx)
+{
+  DMA_HandleTypeDef *hdma;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_READY;
+
+    /* Disable the DMA */
+    if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+    }
+    /* Disable the timer repetition DMA request */
+    __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim, HRTIM_MASTER_DMA_MREP);
+  }
+  else
+  {
+    /* Get the timer DMA handler */
+    hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+    if (hdma == NULL)
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+    }
+    else
+    {
+      hhrtim->State = HAL_HRTIM_STATE_READY;
+
+      /* Disable the DMA */
+      if (HAL_DMA_Abort(hdma) != HAL_OK)
+      {
+        hhrtim->State = HAL_HRTIM_STATE_ERROR;
+      }
+
+      /* Disable the timer repetition DMA request */
+      __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_REP);
+    }
+  }
+
+  /* Disable the timer counter */
+  __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Exported_Functions_Group3 Simple output compare mode functions
+  *  @brief    Simple output compare functions
+@verbatim
+ ===============================================================================
+              ##### Simple output compare functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure simple output channel
+      (+) Start simple output compare
+      (+) Stop simple output compare
+      (+) Start simple output compare and enable interrupt
+      (+) Stop simple output compare and disable interrupt
+      (+) Start simple output compare and enable DMA transfer
+      (+) Stop simple output compare and disable DMA transfer
+       -@- When a HRTIM timer operates in simple output compare mode
+           the output level is set to a programmable value when a match
+           is found between the compare register and the counter.
+           Compare unit 1 is automatically associated to output 1
+           Compare unit 2 is automatically associated to output 2
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure an output in simple output compare mode
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  OCChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @param  pSimpleOCChannelCfg pointer to the simple output compare output configuration structure
+  * @note When the timer operates in simple output compare mode:
+  *         Output 1 is implicitly controlled by the compare unit 1
+  *         Output 2 is implicitly controlled by the compare unit 2
+  *       Output Set/Reset crossbar is set according to the selected output compare mode:
+  *         Toggle: SETxyR = RSTxyR = CMPy
+  *         Active: SETxyR = CMPy, RSTxyR = 0
+  *         Inactive: SETxy =0, RSTxy = CMPy
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t OCChannel,
+                                                  const HRTIM_SimpleOCChannelCfgTypeDef *pSimpleOCChannelCfg)
+{
+  uint32_t CompareUnit = (uint32_t)RESET;
+  HRTIM_OutputCfgTypeDef OutputCfg;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+  assert_param(IS_HRTIM_BASICOCMODE(pSimpleOCChannelCfg->Mode));
+  assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOCChannelCfg->Pulse));
+  assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOCChannelCfg->Polarity));
+  assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOCChannelCfg->IdleLevel));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  /* Set HRTIM state */
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Configure timer compare unit */
+  switch (OCChannel)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      CompareUnit = HRTIM_COMPAREUNIT_1;
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOCChannelCfg->Pulse;
+      break;
+    }
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      CompareUnit = HRTIM_COMPAREUNIT_2;
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOCChannelCfg->Pulse;
+      break;
+    }
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure timer output */
+  OutputCfg.Polarity = (pSimpleOCChannelCfg->Polarity & HRTIM_OUTR_POL1);
+  OutputCfg.IdleLevel = (pSimpleOCChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
+  OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
+  OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+  OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+  OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+  switch (pSimpleOCChannelCfg->Mode)
+  {
+    case HRTIM_BASICOCMODE_TOGGLE:
+    {
+      if (CompareUnit == HRTIM_COMPAREUNIT_1)
+      {
+        OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+      }
+      else
+      {
+        OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+      }
+      OutputCfg.ResetSource = OutputCfg.SetSource;
+      break;
+    }
+
+    case HRTIM_BASICOCMODE_ACTIVE:
+    {
+      if (CompareUnit == HRTIM_COMPAREUNIT_1)
+      {
+        OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+      }
+      else
+      {
+        OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+      }
+      OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
+      break;
+    }
+
+    case HRTIM_BASICOCMODE_INACTIVE:
+    {
+      if (CompareUnit == HRTIM_COMPAREUNIT_1)
+      {
+        OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
+      }
+      else
+      {
+        OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
+      }
+      OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
+      break;
+    }
+
+    default:
+    {
+      OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
+      OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
+
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  HRTIM_OutputConfig(hhrtim,
+                     TimerIdx,
+                     OCChannel,
+                     &OutputCfg);
+
+  /* Set HRTIM state */
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the output compare signal generation on the designed timer output
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  OCChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,
+                                          uint32_t TimerIdx,
+                                          uint32_t OCChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable the timer output */
+  hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the output compare signal generation on the designed timer output
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  OCChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,
+                                         uint32_t TimerIdx,
+                                         uint32_t OCChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Disable the timer output */
+  hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
+
+  /* Disable the timer counter */
+  __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the output compare signal generation on the designed timer output
+  *         (Interrupt is enabled (see note note below)).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  OCChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @note Interrupt enabling depends on the chosen output compare mode
+  *          Output toggle: compare match interrupt is enabled
+  *          Output set active:  output set interrupt is enabled
+  *          Output set inactive:  output reset interrupt is enabled
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             uint32_t OCChannel)
+{
+  uint32_t interrupt;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Get the interrupt to enable (depends on the output compare mode) */
+  interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
+
+  /* Enable the timer output */
+  hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
+
+  /* Enable the timer interrupt (depends on the output compare mode) */
+  __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, interrupt);
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the output compare signal generation on the designed timer output
+  *         (Interrupt is disabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  OCChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx,
+                                            uint32_t OCChannel)
+{
+  uint32_t interrupt;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Disable the timer output */
+  hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
+
+  /* Get the interrupt to disable (depends on the output compare mode) */
+  interrupt = HRTIM_GetITFromOCMode(hhrtim, TimerIdx, OCChannel);
+
+  /* Disable the timer interrupt */
+  __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, interrupt);
+
+  /* Disable the timer counter */
+  __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the output compare signal generation on the designed timer output
+  *         (DMA request is enabled (see note below)).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  OCChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @param  SrcAddr DMA transfer source address
+  * @param  DestAddr DMA transfer destination address
+  * @param  Length The length of data items (data size) to be transferred
+  *                     from source to destination
+  * @note  DMA request enabling depends on the chosen output compare mode
+  *          Output toggle: compare match DMA request is enabled
+  *          Output set active:  output set DMA request is enabled
+  *          Output set inactive:  output reset DMA request is enabled
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx,
+                                              uint32_t OCChannel,
+                                              uint32_t SrcAddr,
+                                              uint32_t DestAddr,
+                                              uint32_t Length)
+{
+  DMA_HandleTypeDef *hdma;
+  uint32_t dma_request;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  if (hhrtim->State == HAL_HRTIM_STATE_READY)
+  {
+    if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      hhrtim->State = HAL_HRTIM_STATE_BUSY;
+    }
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  /* Enable the timer output */
+  hhrtim->Instance->sCommonRegs.OENR |= OCChannel;
+
+  /* Get the DMA request to enable */
+  dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
+
+  /* Get the timer DMA handler */
+  hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+  if (hdma == NULL)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  /* Set the DMA error callback */
+  hdma->XferErrorCallback = HRTIM_DMAError ;
+
+  /* Set the DMA transfer completed callback */
+  hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+
+  /* Enable the DMA channel */
+  if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  /* Enable the timer DMA request */
+  __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, dma_request);
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the output compare signal generation on the designed timer output
+  *         (DMA request is disabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  OCChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             uint32_t OCChannel)
+{
+  uint32_t dma_request;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Disable the timer output */
+  hhrtim->Instance->sCommonRegs.ODISR |= OCChannel;
+
+  /* Get the timer DMA handler */
+  /* Disable the DMA */
+  if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  /* Get the DMA request to disable */
+  dma_request = HRTIM_GetDMAFromOCMode(hhrtim, TimerIdx, OCChannel);
+
+  /* Disable the timer DMA request */
+  __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, dma_request);
+
+  /* Disable the timer counter */
+  __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Exported_Functions_Group4 Simple PWM output mode functions
+  *  @brief    Simple PWM output functions
+@verbatim
+ ===============================================================================
+              ##### Simple PWM output functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure simple PWM output channel
+      (+) Start simple PWM output
+      (+) Stop simple PWM output
+      (+) Start simple PWM output and enable interrupt
+      (+) Stop simple PWM output and disable interrupt
+      (+) Start simple PWM output and enable DMA transfer
+      (+) Stop simple PWM output and disable DMA transfer
+      -@- When a HRTIM timer operates in simple PWM output mode
+          the output level is set to a programmable value when a match is
+          found between the compare register and the counter and reset when
+          the timer period is reached. Duty cycle is determined by the
+          comparison value.
+          Compare unit 1 is automatically associated to output 1
+          Compare unit 2 is automatically associated to output 2
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure an output in simple PWM mode
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  PWMChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @param  pSimplePWMChannelCfg pointer to the simple PWM output configuration structure
+  * @note When the timer operates in simple PWM output mode:
+  *         Output 1 is implicitly controlled by the compare unit 1
+  *         Output 2 is implicitly controlled by the compare unit 2
+  *       Output Set/Reset crossbar is set as follows:
+  *         Output 1: SETx1R = CMP1, RSTx1R = PER
+  *         Output 2: SETx2R = CMP2, RST2R = PER
+  * @note When Simple PWM mode is used the registers preload mechanism is
+  *       enabled (otherwise the behavior is not guaranteed).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t TimerIdx,
+                                                   uint32_t PWMChannel,
+                                                   const HRTIM_SimplePWMChannelCfgTypeDef *pSimplePWMChannelCfg)
+{
+  HRTIM_OutputCfgTypeDef OutputCfg;
+  uint32_t hrtim_timcr;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+  assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimplePWMChannelCfg->Polarity));
+  assert_param(IS_HRTIM_OUTPUTPULSE(pSimplePWMChannelCfg->Pulse));
+  assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimplePWMChannelCfg->IdleLevel));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Configure timer compare unit */
+  switch (PWMChannel)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimplePWMChannelCfg->Pulse;
+      OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimplePWMChannelCfg->Pulse;
+      OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+      break;
+    }
+    default:
+    {
+      OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
+      OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
+
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure timer output */
+  OutputCfg.Polarity = (pSimplePWMChannelCfg->Polarity & HRTIM_OUTR_POL1);
+  OutputCfg.IdleLevel = (pSimplePWMChannelCfg->IdleLevel & HRTIM_OUTR_IDLES1);
+  OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
+  OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+  OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+  OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+  OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
+
+  HRTIM_OutputConfig(hhrtim,
+                     TimerIdx,
+                     PWMChannel,
+                     &OutputCfg);
+
+  /* Enable the registers preload mechanism */
+  hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
+  hrtim_timcr |= HRTIM_TIMCR_PREEN;
+  hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the PWM output signal generation on the designed timer output
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  PWMChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx,
+                                           uint32_t PWMChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable the timer output */
+  hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the PWM output signal generation on the designed timer output
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  PWMChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,
+                                          uint32_t TimerIdx,
+                                          uint32_t PWMChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Disable the timer output */
+  hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
+
+  /* Disable the timer counter */
+  __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the PWM output signal generation on the designed timer output
+  *         (The compare interrupt is enabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  PWMChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx,
+                                              uint32_t PWMChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable the timer output */
+  hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
+
+  /* Enable the timer interrupt (depends on the PWM output) */
+  switch (PWMChannel)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the PWM output signal generation on the designed timer output
+  *         (The compare interrupt is disabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  PWMChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             uint32_t PWMChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Disable the timer output */
+  hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
+
+  /* Disable the timer interrupt (depends on the PWM output) */
+  switch (PWMChannel)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the timer counter */
+  __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the PWM output signal generation on the designed timer output
+  *         (The compare DMA request is enabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  PWMChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @param  SrcAddr DMA transfer source address
+  * @param  DestAddr DMA transfer destination address
+  * @param  Length The length of data items (data size) to be transferred
+  *                     from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx,
+                                               uint32_t PWMChannel,
+                                               uint32_t SrcAddr,
+                                               uint32_t DestAddr,
+                                               uint32_t Length)
+{
+  DMA_HandleTypeDef *hdma;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  if (hhrtim->State == HAL_HRTIM_STATE_READY)
+  {
+    if ((SrcAddr == 0U) || (DestAddr == 0U) || (Length == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      hhrtim->State = HAL_HRTIM_STATE_BUSY;
+    }
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  /* Enable the timer output */
+  hhrtim->Instance->sCommonRegs.OENR |= PWMChannel;
+
+  /* Get the timer DMA handler */
+  hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+  if (hdma == NULL)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  /* Set the DMA error callback */
+  hdma->XferErrorCallback = HRTIM_DMAError ;
+
+  /* Set the DMA transfer completed callback */
+  hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+
+  /* Enable the DMA channel */
+  if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  /* Enable the timer DMA request */
+  switch (PWMChannel)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the PWM output signal generation on the designed timer output
+  *         (The compare DMA request is disabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  PWMChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx,
+                                              uint32_t PWMChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Disable the timer output */
+  hhrtim->Instance->sCommonRegs.ODISR |= PWMChannel;
+
+  /* Get the timer DMA handler */
+  /* Disable the DMA */
+  if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  /* Disable the timer DMA request */
+  switch (PWMChannel)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP1);
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CMP2);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the timer counter */
+  __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Exported_Functions_Group5 Simple input capture functions
+  *  @brief    Simple input capture functions
+@verbatim
+ ===============================================================================
+              ##### Simple input capture functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure simple input capture channel
+      (+) Start simple input capture
+      (+) Stop simple input capture
+      (+) Start simple input capture and enable interrupt
+      (+) Stop simple input capture and disable interrupt
+      (+) Start simple input capture and enable DMA transfer
+      (+) Stop simple input capture and disable DMA transfer
+      -@- When a HRTIM timer operates in simple input capture mode
+          the Capture Register (HRTIM_CPT1/2xR) is used to latch the
+         value of the timer counter counter after a transition detected
+         on a given external event input.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure a simple capture
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CaptureChannel Capture unit
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+  *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+  * @param  pSimpleCaptureChannelCfg pointer to the simple capture configuration structure
+  * @note When the timer operates in simple capture mode the capture is triggered
+  *       by the designated external event and GPIO input is implicitly used as event source.
+  *       The cature can be triggered by a rising edge, a falling edge or both
+  *       edges on event channel.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                       uint32_t TimerIdx,
+                                                       uint32_t CaptureChannel,
+                                                       const HRTIM_SimpleCaptureChannelCfgTypeDef *pSimpleCaptureChannelCfg)
+{
+  HRTIM_EventCfgTypeDef EventCfg;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+  assert_param(IS_HRTIM_EVENT(pSimpleCaptureChannelCfg->Event));
+  assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleCaptureChannelCfg->EventSensitivity,
+                                      pSimpleCaptureChannelCfg->EventPolarity));
+  assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleCaptureChannelCfg->EventSensitivity));
+  assert_param(IS_HRTIM_EVENTFILTER(pSimpleCaptureChannelCfg->Event,
+                                    pSimpleCaptureChannelCfg->EventFilter));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Configure external event channel */
+  EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
+  EventCfg.Filter = (pSimpleCaptureChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
+  EventCfg.Polarity = (pSimpleCaptureChannelCfg->EventPolarity & HRTIM_EECR1_EE1POL);
+  EventCfg.Sensitivity = (pSimpleCaptureChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
+  EventCfg.Source = HRTIM_EEV1SRC_GPIO; /* source 1 for External Event */
+
+  HRTIM_EventConfig(hhrtim,
+                    pSimpleCaptureChannelCfg->Event,
+                    &EventCfg);
+
+  /* Memorize capture trigger (will be configured when the capture is started */
+  HRTIM_CaptureUnitConfig(hhrtim,
+                          TimerIdx,
+                          CaptureChannel,
+                          pSimpleCaptureChannelCfg->Event);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable a simple capture on the designed capture unit
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CaptureChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+  *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+  * @retval HAL status
+  * @note  The external event triggering the capture is available for all timing
+  *        units. It can be used directly and is active as soon as the timing
+  *        unit counter is enabled.
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx,
+                                               uint32_t CaptureChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Set the capture unit trigger */
+  switch (CaptureChannel)
+  {
+    case HRTIM_CAPTUREUNIT_1:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
+      break;
+    }
+
+    case HRTIM_CAPTUREUNIT_2:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable a simple capture on the designed capture unit
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CaptureChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+  *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx,
+                                              uint32_t CaptureChannel)
+{
+  uint32_t hrtim_cpt1cr;
+  uint32_t hrtim_cpt2cr;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Set the capture unit trigger */
+  switch (CaptureChannel)
+  {
+    case HRTIM_CAPTUREUNIT_1:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
+      break;
+    }
+
+    case HRTIM_CAPTUREUNIT_2:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
+  hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
+
+  /* Disable the timer counter */
+  if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
+      (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
+  {
+    __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable a simple capture on the designed capture unit
+  *         (Capture interrupt is enabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CaptureChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+  *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t CaptureChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Set the capture unit trigger */
+  switch (CaptureChannel)
+  {
+    case HRTIM_CAPTUREUNIT_1:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
+
+      /* Enable the capture unit 1 interrupt */
+      __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
+      break;
+    }
+
+    case HRTIM_CAPTUREUNIT_2:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
+
+      /* Enable the capture unit 2 interrupt */
+      __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable a simple capture on the designed capture unit
+  *         (Capture interrupt is disabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CaptureChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+  *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t TimerIdx,
+                                                 uint32_t CaptureChannel)
+{
+
+  uint32_t hrtim_cpt1cr;
+  uint32_t hrtim_cpt2cr;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Set the capture unit trigger */
+  switch (CaptureChannel)
+  {
+    case HRTIM_CAPTUREUNIT_1:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
+
+      /* Disable the capture unit 1 interrupt */
+      __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
+      break;
+    }
+
+    case HRTIM_CAPTUREUNIT_2:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
+
+      /* Disable the capture unit 2 interrupt */
+      __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
+  hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
+
+  /* Disable the timer counter */
+  if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
+      (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
+  {
+    __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable a simple capture on the designed capture unit
+  *         (Capture DMA request is enabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CaptureChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+  *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+  * @param  SrcAddr DMA transfer source address
+  * @param  DestAddr DMA transfer destination address
+  * @param  Length The length of data items (data size) to be transferred
+  *                     from source to destination
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t TimerIdx,
+                                                   uint32_t CaptureChannel,
+                                                   uint32_t SrcAddr,
+                                                   uint32_t DestAddr,
+                                                   uint32_t Length)
+{
+  DMA_HandleTypeDef *hdma;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Get the timer DMA handler */
+  hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+  if (hdma == NULL)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  /* Set the DMA error callback */
+  hdma->XferErrorCallback = HRTIM_DMAError ;
+
+  /* Set the DMA transfer completed callback */
+  hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+
+  /* Enable the DMA channel */
+  if (HAL_DMA_Start_IT(hdma, SrcAddr, DestAddr, Length) != HAL_OK)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  switch (CaptureChannel)
+  {
+    case HRTIM_CAPTUREUNIT_1:
+    {
+      /* Set the capture unit trigger */
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger1;
+
+      __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
+      break;
+    }
+
+    case HRTIM_CAPTUREUNIT_2:
+    {
+      /* Set the capture unit trigger */
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = hhrtim->TimerParam[TimerIdx].CaptureTrigger2;
+
+      /* Enable the timer DMA request */
+      __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable a simple capture on the designed capture unit
+  *         (Capture DMA request is disabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CaptureChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+  *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t CaptureChannel)
+{
+
+  uint32_t hrtim_cpt1cr;
+  uint32_t hrtim_cpt2cr;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Get the timer DMA handler */
+  /* Disable the DMA */
+  if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx)) != HAL_OK)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  switch (CaptureChannel)
+  {
+    case HRTIM_CAPTUREUNIT_1:
+    {
+      /* Reset the capture unit trigger */
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
+
+      /* Disable the capture unit 1 DMA request */
+      __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT1);
+      break;
+    }
+
+    case HRTIM_CAPTUREUNIT_2:
+    {
+      /* Reset the capture unit trigger */
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
+
+      /* Disable the capture unit 2 DMA request */
+      __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim, TimerIdx, HRTIM_TIM_DMA_CPT2);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  hrtim_cpt1cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR;
+  hrtim_cpt2cr = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR;
+
+  /* Disable the timer counter */
+  if ((hrtim_cpt1cr == HRTIM_CAPTURETRIGGER_NONE) &&
+      (hrtim_cpt2cr == HRTIM_CAPTURETRIGGER_NONE))
+  {
+    __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Exported_Functions_Group6 Simple one pulse functions
+  *  @brief    Simple one pulse functions
+@verbatim
+ ===============================================================================
+              ##### Simple one pulse functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure one pulse channel
+      (+) Start one pulse generation
+      (+) Stop one pulse generation
+      (+) Start one pulse generation and enable interrupt
+      (+) Stop one pulse generation and disable interrupt
+      -@- When a HRTIM timer operates in simple one pulse mode
+          the timer counter is started in response to transition detected
+          on a given external event input to generate a pulse with a
+          programmable length after a programmable delay.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure an output simple one pulse mode
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  OnePulseChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @param  pSimpleOnePulseChannelCfg pointer to the simple one pulse output configuration structure
+  * @note When the timer operates in simple one pulse mode:
+  *         the timer counter is implicitly started by the reset event,
+  *         the reset of the timer counter is triggered by the designated external event
+  *         GPIO input is implicitly used as event source,
+  *         Output 1 is implicitly controlled by the compare unit 1,
+  *         Output 2 is implicitly controlled by the compare unit 2.
+  *       Output Set/Reset crossbar is set as follows:
+  *         Output 1: SETx1R = CMP1, RSTx1R = PER
+  *         Output 2: SETx2R = CMP2, RST2R = PER
+  * @retval HAL status
+  * @note If HAL_HRTIM_SimpleOnePulseChannelConfig is called for both timer
+  *       outputs, the reset event related configuration data provided in the
+  *       second call will override the reset event related configuration data
+  *       provided in the first call.
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                        uint32_t TimerIdx,
+                                                        uint32_t OnePulseChannel,
+                                                        const HRTIM_SimpleOnePulseChannelCfgTypeDef *pSimpleOnePulseChannelCfg)
+{
+  HRTIM_OutputCfgTypeDef OutputCfg;
+  HRTIM_EventCfgTypeDef EventCfg;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+  assert_param(IS_HRTIM_OUTPUTPULSE(pSimpleOnePulseChannelCfg->Pulse));
+  assert_param(IS_HRTIM_OUTPUTPOLARITY(pSimpleOnePulseChannelCfg->OutputPolarity));
+  assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pSimpleOnePulseChannelCfg->OutputIdleLevel));
+  assert_param(IS_HRTIM_EVENT(pSimpleOnePulseChannelCfg->Event));
+  assert_param(IS_HRTIM_EVENTPOLARITY(pSimpleOnePulseChannelCfg->EventSensitivity,
+                                      pSimpleOnePulseChannelCfg->EventPolarity));
+  assert_param(IS_HRTIM_EVENTSENSITIVITY(pSimpleOnePulseChannelCfg->EventSensitivity));
+  assert_param(IS_HRTIM_EVENTFILTER(pSimpleOnePulseChannelCfg->Event,
+                                    pSimpleOnePulseChannelCfg->EventFilter));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Configure timer compare unit */
+  switch (OnePulseChannel)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pSimpleOnePulseChannelCfg->Pulse;
+      OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pSimpleOnePulseChannelCfg->Pulse;
+      OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+      break;
+    }
+
+    default:
+    {
+      OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
+      OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
+
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Configure timer output */
+  OutputCfg.Polarity = (pSimpleOnePulseChannelCfg->OutputPolarity & HRTIM_OUTR_POL1);
+  OutputCfg.IdleLevel = (pSimpleOnePulseChannelCfg->OutputIdleLevel & HRTIM_OUTR_IDLES1);
+  OutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
+  OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+  OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+  OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+  OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMPER;
+
+  HRTIM_OutputConfig(hhrtim,
+                     TimerIdx,
+                     OnePulseChannel,
+                     &OutputCfg);
+
+  /* Configure external event channel */
+  EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
+  EventCfg.Filter = (pSimpleOnePulseChannelCfg->EventFilter & HRTIM_EECR3_EE6F);
+  EventCfg.Polarity = (pSimpleOnePulseChannelCfg->EventPolarity & HRTIM_OUTR_POL1);
+  EventCfg.Sensitivity = (pSimpleOnePulseChannelCfg->EventSensitivity & HRTIM_EECR1_EE1SNS);
+  EventCfg.Source = HRTIM_EEV1SRC_GPIO; /* source 1 for External Event */
+
+  HRTIM_EventConfig(hhrtim,
+                    pSimpleOnePulseChannelCfg->Event,
+                    &EventCfg);
+
+  /* Configure the timer reset register */
+  HRTIM_TIM_ResetConfig(hhrtim,
+                        TimerIdx,
+                        pSimpleOnePulseChannelCfg->Event);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the simple one pulse signal generation on the designed output
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  OnePulseChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t TimerIdx,
+                                                uint32_t OnePulseChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable the timer output */
+  hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the simple one pulse signal generation on the designed output
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  OnePulseChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx,
+                                               uint32_t OnePulseChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Disable the timer output */
+  hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
+
+  /* Disable the timer counter */
+  __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the simple one pulse signal generation on the designed output
+  *         (The compare interrupt is enabled (pulse start)).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer E
+  * @param  OnePulseChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t TimerIdx,
+                                                   uint32_t OnePulseChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable the timer output */
+  hhrtim->Instance->sCommonRegs.OENR |= OnePulseChannel;
+
+  /* Enable the timer interrupt (depends on the OnePulse output) */
+  switch (OnePulseChannel)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the simple one pulse signal generation on the designed output
+  *         (The compare interrupt is disabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  OnePulseChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t OnePulseChannel)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Disable the timer output */
+  hhrtim->Instance->sCommonRegs.ODISR |= OnePulseChannel;
+
+  /* Disable the timer interrupt (depends on the OnePulse output) */
+  switch (OnePulseChannel)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Disable the timer counter */
+  __HAL_HRTIM_DISABLE(hhrtim, TimerIdxToTimerId[TimerIdx]);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Exported_Functions_Group7 Configuration functions
+  *  @brief    HRTIM configuration functions
+@verbatim
+ ===============================================================================
+              ##### HRTIM configuration functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to configure the HRTIM
+          resources shared by all the HRTIM timers operating in waveform mode:
+      (+) Configure the burst mode controller
+      (+) Configure an external event conditioning
+      (+) Configure the external events sampling clock
+      (+) Configure a fault conditioning
+      (+) Enable or disable fault inputs
+      (+) Configure the faults sampling clock
+      (+) Configure an ADC trigger
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the burst mode feature of the HRTIM
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  pBurstModeCfg pointer to the burst mode configuration structure
+  * @retval HAL status
+  * @note This function must be called before starting the burst mode
+  *       controller
+  */
+HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,
+                                            const HRTIM_BurstModeCfgTypeDef *pBurstModeCfg)
+{
+  uint32_t hrtim_bmcr;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
+  assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
+  assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
+  assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
+  assert_param(IS_HRTIM_BURSTMODETRIGGER(pBurstModeCfg->Trigger));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
+
+  /* Set the burst mode operating mode */
+  hrtim_bmcr &= ~(HRTIM_BMCR_BMOM);
+  hrtim_bmcr |= (pBurstModeCfg->Mode & HRTIM_BMCR_BMOM);
+
+  /* Set the burst mode clock source */
+  hrtim_bmcr &= ~(HRTIM_BMCR_BMCLK);
+  hrtim_bmcr |= (pBurstModeCfg->ClockSource & HRTIM_BMCR_BMCLK);
+
+  /* Set the burst mode prescaler */
+  hrtim_bmcr &= ~(HRTIM_BMCR_BMPRSC);
+  hrtim_bmcr |= pBurstModeCfg->Prescaler;
+
+  /* Enable/disable burst mode registers preload */
+  hrtim_bmcr &= ~(HRTIM_BMCR_BMPREN);
+  hrtim_bmcr |= (pBurstModeCfg->PreloadEnable & HRTIM_BMCR_BMPREN);
+
+  /* Set the burst mode trigger */
+  hhrtim->Instance->sCommonRegs.BMTRGR = pBurstModeCfg->Trigger;
+
+  /* Set the burst mode compare value */
+  hhrtim->Instance->sCommonRegs.BMCMPR = pBurstModeCfg->IdleDuration;
+
+  /* Set the burst mode period */
+  hhrtim->Instance->sCommonRegs.BMPER = pBurstModeCfg->Period;
+
+  /* Update the HRTIM registers */
+  hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the conditioning of an external event
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Event external event to configure
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_EVENT_NONE: no external Event
+  *                    @arg HRTIM_EVENT_1: External event 1
+  *                    @arg HRTIM_EVENT_2: External event 2
+  *                    @arg HRTIM_EVENT_3: External event 3
+  *                    @arg HRTIM_EVENT_4: External event 4
+  *                    @arg HRTIM_EVENT_5: External event 5
+  *                    @arg HRTIM_EVENT_6: External event 6
+  *                    @arg HRTIM_EVENT_7: External event 7
+  *                    @arg HRTIM_EVENT_8: External event 8
+  *                    @arg HRTIM_EVENT_9: External event 9
+  *                    @arg HRTIM_EVENT_10: External event 10
+  * @param  pEventCfg pointer to the event conditioning configuration structure
+  * @note This function must be called before starting the timer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
+                                        uint32_t Event,
+                                        const HRTIM_EventCfgTypeDef *pEventCfg)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_EVENT(Event));
+  assert_param(IS_HRTIM_EVENTSRC(Event, pEventCfg->Source));
+  assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
+  assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
+  assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
+  assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Configure the event channel */
+  HRTIM_EventConfig(hhrtim, Event, pEventCfg);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the external event conditioning block prescaler
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Prescaler Prescaler value
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIM
+  *                    @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIM / 2
+  *                    @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIM / 4
+  *                    @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIM / 8
+  * @note This function must be called before starting the timer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t Prescaler)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Set the external event prescaler */
+  MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the conditioning of fault input
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Fault fault input to configure
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_FAULT_1: Fault input 1
+  *                    @arg HRTIM_FAULT_2: Fault input 2
+  *                    @arg HRTIM_FAULT_3: Fault input 3
+  *                    @arg HRTIM_FAULT_4: Fault input 4
+  *                    @arg HRTIM_FAULT_5: Fault input 5
+  *                    @arg HRTIM_FAULT_6: Fault input 6
+  * @param  pFaultCfg pointer to the fault conditioning configuration structure
+  * @note This function must be called before starting the timer and before
+  *       enabling faults inputs
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,
+                                        uint32_t Fault,
+                                        const HRTIM_FaultCfgTypeDef *pFaultCfg)
+{
+  uint32_t hrtim_fltinr1;
+  uint32_t hrtim_fltinr2;
+  uint32_t source0, source1;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_FAULT(Fault));
+  assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
+  assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
+  assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
+  assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Configure fault channel */
+  hrtim_fltinr1 = hhrtim->Instance->sCommonRegs.FLTINR1;
+  hrtim_fltinr2 = hhrtim->Instance->sCommonRegs.FLTINR2;
+
+  source0 = (pFaultCfg->Source & 1U);
+  source1 = ((pFaultCfg->Source & 2U) >> 1);
+
+  switch (Fault)
+  {
+    case HRTIM_FAULT_1:
+    {
+      hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC_0 | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
+      hrtim_fltinr1 |= (pFaultCfg->Polarity & HRTIM_FLTINR1_FLT1P);
+      hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT1SRC_0_Pos);
+      hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT1SRC_1);
+      hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT1SRC_1_Pos);
+      hrtim_fltinr1 |= (pFaultCfg->Filter & HRTIM_FLTINR1_FLT1F);
+      hrtim_fltinr1 |= (pFaultCfg->Lock & HRTIM_FLTINR1_FLT1LCK);
+      break;
+    }
+
+    case HRTIM_FAULT_2:
+    {
+      hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC_0 | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
+      hrtim_fltinr1 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR1_FLT2P);
+      hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT2SRC_0_Pos);
+      hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT2SRC_1);
+      hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT2SRC_1_Pos);
+      hrtim_fltinr1 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR1_FLT2F);
+      hrtim_fltinr1 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR1_FLT2LCK);
+      break;
+    }
+
+    case HRTIM_FAULT_3:
+    {
+      hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC_0 | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
+      hrtim_fltinr1 |= ((pFaultCfg->Polarity << 16U) & HRTIM_FLTINR1_FLT3P);
+      hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT3SRC_0_Pos);
+      hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT3SRC_1);
+      hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT3SRC_1_Pos);
+      hrtim_fltinr1 |= ((pFaultCfg->Filter << 16U) & HRTIM_FLTINR1_FLT3F);
+      hrtim_fltinr1 |= ((pFaultCfg->Lock << 16U) & HRTIM_FLTINR1_FLT3LCK);
+      break;
+    }
+
+    case HRTIM_FAULT_4:
+    {
+      hrtim_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC_0 | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
+      hrtim_fltinr1 |= ((pFaultCfg->Polarity << 24U) & HRTIM_FLTINR1_FLT4P);
+      hrtim_fltinr1 |= (source0 << HRTIM_FLTINR1_FLT4SRC_0_Pos);
+      hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT4SRC_1);
+      hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT4SRC_1_Pos);
+      hrtim_fltinr1 |= ((pFaultCfg->Filter << 24U) & HRTIM_FLTINR1_FLT4F);
+      hrtim_fltinr1 |= ((pFaultCfg->Lock << 24U) & HRTIM_FLTINR1_FLT4LCK);
+      break;
+    }
+
+    case HRTIM_FAULT_5:
+    {
+      hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC_0 | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
+      hrtim_fltinr2 |= (pFaultCfg->Polarity & HRTIM_FLTINR2_FLT5P);
+      hrtim_fltinr2 |= (source0 << HRTIM_FLTINR2_FLT5SRC_0_Pos);
+      hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT5SRC_1);
+      hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT5SRC_1_Pos);
+      hrtim_fltinr2 |= (pFaultCfg->Filter & HRTIM_FLTINR2_FLT5F);
+      hrtim_fltinr2 |= (pFaultCfg->Lock & HRTIM_FLTINR2_FLT5LCK);
+      break;
+    }
+
+    case HRTIM_FAULT_6:
+    {
+      hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6P | HRTIM_FLTINR2_FLT6SRC_0 | HRTIM_FLTINR2_FLT6F | HRTIM_FLTINR2_FLT6LCK);
+      hrtim_fltinr2 |= ((pFaultCfg->Polarity << 8U) & HRTIM_FLTINR2_FLT6P);
+      hrtim_fltinr2 |= (source0 << HRTIM_FLTINR2_FLT6SRC_0_Pos);
+      hrtim_fltinr2 &= ~(HRTIM_FLTINR2_FLT6SRC_1);
+      hrtim_fltinr2 |= (source1 << HRTIM_FLTINR2_FLT6SRC_1_Pos);
+      hrtim_fltinr2 |= ((pFaultCfg->Filter << 8U) & HRTIM_FLTINR2_FLT6F);
+      hrtim_fltinr2 |= ((pFaultCfg->Lock << 8U) & HRTIM_FLTINR2_FLT6LCK);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Update the HRTIM registers except LOCK bit */
+  hhrtim->Instance->sCommonRegs.FLTINR1 = (hrtim_fltinr1 & (~(HRTIM_FLTINR1_FLTxLCK)));
+  hhrtim->Instance->sCommonRegs.FLTINR2 = (hrtim_fltinr2 & (~(HRTIM_FLTINR2_FLTxLCK)));
+
+  /* Update the HRTIM registers LOCK bit */
+  SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR1, (hrtim_fltinr1 & HRTIM_FLTINR1_FLTxLCK));
+  SET_BIT(hhrtim->Instance->sCommonRegs.FLTINR2, (hrtim_fltinr2 & HRTIM_FLTINR2_FLTxLCK));
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the fault conditioning block prescaler
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Prescaler Prescaler value
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIM
+  *                    @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIM / 2
+  *                    @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIM / 4
+  *                    @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIM / 8
+  * @retval HAL status
+  * @note This function must be called before starting the timer and before
+  *       enabling faults inputs
+  */
+HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t Prescaler)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Set the external event prescaler */
+  MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, (Prescaler & HRTIM_FLTINR2_FLTSD));
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure and Enable the blanking source of a Fault input
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Fault fault input to configure
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_FAULT_1: Fault input 1
+  *                    @arg HRTIM_FAULT_2: Fault input 2
+  *                    @arg HRTIM_FAULT_3: Fault input 3
+  *                    @arg HRTIM_FAULT_4: Fault input 4
+  *                    @arg HRTIM_FAULT_5: Fault input 5
+  *                    @arg HRTIM_FAULT_6: Fault input 6
+  * @param  pFaultBlkCfg: pointer to the fault conditioning configuration structure
+  * @note This function automatically enables the Blanking on Fault
+  * @note This function must be called when fault is not enabled
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_FaultBlankingConfigAndEnable(HRTIM_HandleTypeDef *hhrtim,
+                                                         uint32_t Fault,
+                                                         const HRTIM_FaultBlankingCfgTypeDef *pFaultBlkCfg)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_FAULT(Fault));
+  assert_param(IS_HRTIM_FAULTBLANKNGMODE(pFaultBlkCfg->BlankingSource));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  switch (Fault)
+  {
+    case HRTIM_FAULT_1:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
+                 (HRTIM_FLTINR3_FLT1BLKS | HRTIM_FLTINR3_FLT1BLKE),
+                 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT1BLKS_Pos) |
+                  HRTIM_FLTINR3_FLT1BLKE));
+      break;
+    }
+    case HRTIM_FAULT_2:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
+                 (HRTIM_FLTINR3_FLT2BLKS | HRTIM_FLTINR3_FLT2BLKE),
+                 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT2BLKS_Pos) |
+                  HRTIM_FLTINR3_FLT2BLKE));
+      break;
+    }
+    case HRTIM_FAULT_3:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
+                 (HRTIM_FLTINR3_FLT3BLKS | HRTIM_FLTINR3_FLT3BLKE),
+                 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT3BLKS_Pos) |
+                  HRTIM_FLTINR3_FLT3BLKE));
+      break;
+    }
+    case HRTIM_FAULT_4:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
+                 (HRTIM_FLTINR3_FLT4BLKS | HRTIM_FLTINR3_FLT4BLKE),
+                 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR3_FLT4BLKS_Pos) |
+                  HRTIM_FLTINR3_FLT4BLKE));
+      break;
+    }
+    case HRTIM_FAULT_5:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
+                 (HRTIM_FLTINR4_FLT5BLKS | HRTIM_FLTINR4_FLT5BLKE),
+                 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT5BLKS_Pos) |
+                  HRTIM_FLTINR4_FLT5BLKE));
+      break;
+    }
+    case HRTIM_FAULT_6:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
+                 (HRTIM_FLTINR4_FLT6BLKS | HRTIM_FLTINR4_FLT6BLKE),
+                 ((pFaultBlkCfg->BlankingSource << HRTIM_FLTINR4_FLT6BLKS_Pos) |
+                  HRTIM_FLTINR4_FLT6BLKE));
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the Fault Counter (Threshold and Reset Mode)
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Fault fault input to configure
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_FAULT_1: Fault input 1
+  *                    @arg HRTIM_FAULT_2: Fault input 2
+  *                    @arg HRTIM_FAULT_3: Fault input 3
+  *                    @arg HRTIM_FAULT_4: Fault input 4
+  *                    @arg HRTIM_FAULT_5: Fault input 5
+  *                    @arg HRTIM_FAULT_6: Fault input 6
+  * @param  pFaultBlkCfg: pointer to the fault conditioning configuration structure
+  * @retval HAL status
+  * @note  A fault is considered valid when the number of
+  *        events is equal to the (FLTxCNT[3:0]+1) value
+  *
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_FaultCounterConfig(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t Fault,
+                                               const HRTIM_FaultBlankingCfgTypeDef *pFaultBlkCfg)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_FAULT(Fault));
+  assert_param(IS_HRTIM_FAULTCOUNTER(pFaultBlkCfg->Threshold));
+  assert_param(IS_HRTIM_FAULTCOUNTERRST(pFaultBlkCfg->ResetMode));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  switch (Fault)
+  {
+    case HRTIM_FAULT_1:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
+                 (HRTIM_FLTINR3_FLT1RSTM | HRTIM_FLTINR3_FLT1CNT),
+                 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT1CNT_Pos) |
+                 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT1RSTM_Pos));
+      break;
+    }
+    case HRTIM_FAULT_2:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
+                 (HRTIM_FLTINR3_FLT2RSTM | HRTIM_FLTINR3_FLT2CNT),
+                 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT2CNT_Pos) |
+                 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT2RSTM_Pos));
+      break;
+    }
+    case HRTIM_FAULT_3:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
+                 (HRTIM_FLTINR3_FLT3RSTM | HRTIM_FLTINR3_FLT3CNT),
+                 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT3CNT_Pos) |
+                 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT3RSTM_Pos));
+      break;
+    }
+    case HRTIM_FAULT_4:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3,
+                 (HRTIM_FLTINR3_FLT4RSTM | HRTIM_FLTINR3_FLT4CNT),
+                 (pFaultBlkCfg->Threshold << HRTIM_FLTINR3_FLT4CNT_Pos) |
+                 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR3_FLT4RSTM_Pos));
+      break;
+    }
+    case HRTIM_FAULT_5:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
+                 (HRTIM_FLTINR4_FLT5RSTM | HRTIM_FLTINR4_FLT5CNT),
+                 (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT5CNT_Pos) |
+                 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT5RSTM_Pos));
+      break;
+    }
+    case HRTIM_FAULT_6:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4,
+                 (HRTIM_FLTINR4_FLT6RSTM | HRTIM_FLTINR4_FLT6CNT),
+                 (pFaultBlkCfg->Threshold << HRTIM_FLTINR4_FLT6CNT_Pos) |
+                 (pFaultBlkCfg->ResetMode << HRTIM_FLTINR4_FLT6RSTM_Pos));
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the fault Counter Reset
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Fault fault input to reset
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_FAULT_1: Fault input 1
+  *                    @arg HRTIM_FAULT_2: Fault input 2
+  *                    @arg HRTIM_FAULT_3: Fault input 3
+  *                    @arg HRTIM_FAULT_4: Fault input 4
+  *                    @arg HRTIM_FAULT_5: Fault input 5
+  *                    @arg HRTIM_FAULT_6: Fault input 6
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_FaultCounterReset(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t Fault)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_FAULT(Fault));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  switch (Fault)
+  {
+    case HRTIM_FAULT_1:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT1CRES, HRTIM_FLTINR3_FLT1CRES) ;
+      break;
+    }
+    case HRTIM_FAULT_2:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT2CRES, HRTIM_FLTINR3_FLT2CRES) ;
+      break;
+    }
+    case HRTIM_FAULT_3:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT3CRES, HRTIM_FLTINR3_FLT3CRES) ;
+      break;
+    }
+    case HRTIM_FAULT_4:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR3, HRTIM_FLTINR3_FLT4CRES, HRTIM_FLTINR3_FLT4CRES) ;
+      break;
+    }
+    case HRTIM_FAULT_5:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, HRTIM_FLTINR4_FLT5CRES, HRTIM_FLTINR4_FLT5CRES) ;
+      break;
+    }
+    case HRTIM_FAULT_6:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR4, HRTIM_FLTINR4_FLT6CRES, HRTIM_FLTINR4_FLT6CRES) ;
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable or disables the HRTIMx Fault mode.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Faults fault input(s) to enable or disable
+  *                   This parameter can be any combination of the following values:
+  *                    @arg HRTIM_FAULT_1: Fault input 1
+  *                    @arg HRTIM_FAULT_2: Fault input 2
+  *                    @arg HRTIM_FAULT_3: Fault input 3
+  *                    @arg HRTIM_FAULT_4: Fault input 4
+  *                    @arg HRTIM_FAULT_5: Fault input 5
+  *                    @arg HRTIM_FAULT_6: Fault input 6
+  * @param  Enable Fault(s) enabling
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_FAULTMODECTL_ENABLED: Fault(s) enabled
+  *                    @arg HRTIM_FAULTMODECTL_DISABLED: Fault(s) disabled
+  * @retval None
+  */
+void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef *hhrtim,
+                            uint32_t Faults,
+                            uint32_t Enable)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_FAULT(Faults));
+  assert_param(IS_HRTIM_FAULTMODECTL(Enable));
+
+  if ((Faults & HRTIM_FAULT_1) != (uint32_t)RESET)
+  {
+    MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT1E, (Enable & HRTIM_FLTINR1_FLT1E));
+  }
+  if ((Faults & HRTIM_FAULT_2) != (uint32_t)RESET)
+  {
+    MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT2E, ((Enable << 8U) & HRTIM_FLTINR1_FLT2E));
+  }
+  if ((Faults & HRTIM_FAULT_3) != (uint32_t)RESET)
+  {
+    MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT3E, ((Enable << 16U) & HRTIM_FLTINR1_FLT3E));
+  }
+  if ((Faults & HRTIM_FAULT_4) != (uint32_t)RESET)
+  {
+    MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR1, HRTIM_FLTINR1_FLT4E, ((Enable << 24U) & HRTIM_FLTINR1_FLT4E));
+  }
+  if ((Faults & HRTIM_FAULT_5) != (uint32_t)RESET)
+  {
+    MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT5E, ((Enable) & HRTIM_FLTINR2_FLT5E));
+  }
+  if ((Faults & HRTIM_FAULT_6) != (uint32_t)RESET)
+  {
+    MODIFY_REG(hhrtim->Instance->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLT6E, ((Enable << 8U) & HRTIM_FLTINR2_FLT6E));
+  }
+}
+
+/**
+  * @brief  Configure both the ADC trigger register update source and the ADC
+  *         trigger source.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  ADCTrigger ADC trigger to configure
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
+  *                    @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
+  *                    @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
+  *                    @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
+  *                    @arg HRTIM_ADCTRIGGER_5: ADC trigger 5
+  *                    @arg HRTIM_ADCTRIGGER_6: ADC trigger 6
+  *                    @arg HRTIM_ADCTRIGGER_7: ADC trigger 7
+  *                    @arg HRTIM_ADCTRIGGER_8: ADC trigger 8
+  *                    @arg HRTIM_ADCTRIGGER_9: ADC trigger 9
+  *                    @arg HRTIM_ADCTRIGGER_10: ADC trigger 10
+  * @param  pADCTriggerCfg pointer to the ADC trigger configuration structure
+  *                    for Trigger nb (1..4): pADCTriggerCfg->Trigger parameter
+  *                    can be a combination of the following values
+  *                    @arg HRTIM_ADCTRIGGEREVENT13_...
+  *                    @arg HRTIM_ADCTRIGGEREVENT24_...
+  *                    for Trigger nb (5..10): pADCTriggerCfg->Trigger parameter
+  *                    can be one of the following values
+  *                    @arg HRTIM_ADCTRIGGEREVENT579_...
+  *                    @arg HRTIM_ADCTRIGGEREVENT6810_...
+  * @retval HAL status
+  * @note This function must be called before starting the timer
+  */
+HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t ADCTrigger,
+                                             const HRTIM_ADCTriggerCfgTypeDef *pADCTriggerCfg)
+{
+  uint32_t hrtim_cr1;
+  uint32_t hrtim_adcur;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
+  assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Set the ADC trigger update source */
+  hrtim_cr1 = hhrtim->Instance->sCommonRegs.CR1;
+  hrtim_adcur = hhrtim->Instance->sCommonRegs.ADCUR;
+
+  switch (ADCTrigger)
+  {
+    case HRTIM_ADCTRIGGER_1:
+    {
+      hrtim_cr1 &= ~(HRTIM_CR1_ADC1USRC);
+      hrtim_cr1 |= (pADCTriggerCfg->UpdateSource & HRTIM_CR1_ADC1USRC);
+
+      /* Set the ADC trigger 1 source */
+      hhrtim->Instance->sCommonRegs.ADC1R = pADCTriggerCfg->Trigger;
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_2:
+    {
+      hrtim_cr1 &= ~(HRTIM_CR1_ADC2USRC);
+      hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 3U) & HRTIM_CR1_ADC2USRC);
+
+      /* Set the ADC trigger 2 source */
+      hhrtim->Instance->sCommonRegs.ADC2R = pADCTriggerCfg->Trigger;
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_3:
+    {
+      hrtim_cr1 &= ~(HRTIM_CR1_ADC3USRC);
+      hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 6U) & HRTIM_CR1_ADC3USRC);
+
+      /* Set the ADC trigger 3 source */
+      hhrtim->Instance->sCommonRegs.ADC3R = pADCTriggerCfg->Trigger;
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_4:
+    {
+      hrtim_cr1 &= ~(HRTIM_CR1_ADC4USRC);
+      hrtim_cr1 |= ((pADCTriggerCfg->UpdateSource << 9U) & HRTIM_CR1_ADC4USRC);
+
+      /* Set the ADC trigger 4 source */
+      hhrtim->Instance->sCommonRegs.ADC4R = pADCTriggerCfg->Trigger;
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_5:
+    {
+      hrtim_adcur &= ~(HRTIM_ADCUR_AD5USRC);
+      hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 16U) & HRTIM_ADCUR_AD5USRC);
+
+      /* Set the ADC trigger 5 source */
+      hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD5TRG);
+      hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD5TRG_Pos) & HRTIM_ADCER_AD5TRG);
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_6:
+    {
+      hrtim_adcur &= ~(HRTIM_ADCUR_AD6USRC);
+      hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 12U) & HRTIM_ADCUR_AD6USRC);
+
+      /* Set the ADC trigger 6 source */
+      hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD6TRG);
+      hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD6TRG_Pos) & HRTIM_ADCER_AD6TRG);
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_7:
+    {
+      hrtim_adcur &= ~(HRTIM_ADCUR_AD7USRC);
+      hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 8U) & HRTIM_ADCUR_AD7USRC);
+
+      /* Set the ADC trigger 7 source */
+      hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD7TRG);
+      hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD7TRG_Pos) & HRTIM_ADCER_AD7TRG);
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_8:
+    {
+      hrtim_adcur &= ~(HRTIM_ADCUR_AD8USRC);
+      hrtim_adcur |= ((pADCTriggerCfg->UpdateSource >> 4U) & HRTIM_ADCUR_AD8USRC);
+
+      /* Set the ADC trigger 8 source */
+      hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD8TRG);
+      hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD8TRG_Pos) & HRTIM_ADCER_AD8TRG);
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_9:
+    {
+      hrtim_adcur &= ~(HRTIM_ADCUR_AD9USRC);
+      hrtim_adcur |= ((pADCTriggerCfg->UpdateSource) & HRTIM_ADCUR_AD9USRC);
+
+      /* Set the ADC trigger 9 source */
+      hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD9TRG);
+      hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD9TRG_Pos) & HRTIM_ADCER_AD9TRG);
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_10:
+    {
+      hrtim_adcur &= ~(HRTIM_ADCUR_AD10USRC);
+      hrtim_adcur |= ((pADCTriggerCfg->UpdateSource << 4U) & HRTIM_ADCUR_AD10USRC);
+
+      /* Set the ADC trigger 10 source */
+      hhrtim->Instance->sCommonRegs.ADCER &= ~(HRTIM_ADCER_AD10TRG);
+      hhrtim->Instance->sCommonRegs.ADCER |= ((pADCTriggerCfg->Trigger << HRTIM_ADCER_AD10TRG_Pos) & HRTIM_ADCER_AD10TRG);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Update the HRTIM registers */
+  if (ADCTrigger < HRTIM_ADCTRIGGER_5)
+  {
+    hhrtim->Instance->sCommonRegs.CR1 = hrtim_cr1;
+  }
+  else
+  {
+    hhrtim->Instance->sCommonRegs.ADCUR = hrtim_adcur;
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the ADC trigger postscaler register of the ADC
+  *         trigger source.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  ADCTrigger ADC trigger to configure
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
+  *                    @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
+  *                    @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
+  *                    @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
+  *                    @arg HRTIM_ADCTRIGGER_5: ADC trigger 5
+  *                    @arg HRTIM_ADCTRIGGER_6: ADC trigger 6
+  *                    @arg HRTIM_ADCTRIGGER_7: ADC trigger 7
+  *                    @arg HRTIM_ADCTRIGGER_8: ADC trigger 8
+  *                    @arg HRTIM_ADCTRIGGER_9: ADC trigger 9
+  *                    @arg HRTIM_ADCTRIGGER_10: ADC trigger 10
+  * @param  Postscaler  value 0..1F
+  * @retval HAL status
+  * @note This function must be called before starting the timer
+  */
+HAL_StatusTypeDef HAL_HRTIM_ADCPostScalerConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t ADCTrigger,
+                                                uint32_t Postscaler)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  switch (ADCTrigger)
+  {
+    case HRTIM_ADCTRIGGER_1:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD1PSC, (Postscaler & HRTIM_ADCPS1_AD1PSC));
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_2:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD2PSC, ((Postscaler << HRTIM_ADCPS1_AD2PSC_Pos) & HRTIM_ADCPS1_AD2PSC));
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_3:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD3PSC, ((Postscaler << HRTIM_ADCPS1_AD3PSC_Pos) & HRTIM_ADCPS1_AD3PSC));
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_4:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD4PSC, ((Postscaler << HRTIM_ADCPS1_AD4PSC_Pos) & HRTIM_ADCPS1_AD4PSC));
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_5:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS1, HRTIM_ADCPS1_AD5PSC, ((Postscaler << HRTIM_ADCPS1_AD5PSC_Pos) & HRTIM_ADCPS1_AD5PSC));
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_6:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD6PSC, ((Postscaler << HRTIM_ADCPS2_AD6PSC_Pos) & HRTIM_ADCPS2_AD6PSC));
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_7:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD7PSC, ((Postscaler << HRTIM_ADCPS2_AD7PSC_Pos) & HRTIM_ADCPS2_AD7PSC));
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_8:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD8PSC, ((Postscaler << HRTIM_ADCPS2_AD8PSC_Pos) & HRTIM_ADCPS2_AD8PSC));
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_9:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD9PSC, ((Postscaler << HRTIM_ADCPS2_AD9PSC_Pos) & HRTIM_ADCPS2_AD9PSC));
+      break;
+    }
+
+    case HRTIM_ADCTRIGGER_10:
+    {
+      MODIFY_REG(hhrtim->Instance->sCommonRegs.ADCPS2, HRTIM_ADCPS2_AD10PSC, ((Postscaler << HRTIM_ADCPS2_AD10PSC_Pos) & HRTIM_ADCPS2_AD10PSC));
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the ADC Roll-Over mode of the ADC
+  *         trigger source.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  RollOverCfg This parameter can be a combination of all the following values:
+  *                   @arg HRTIM_TIM_FEROM_BOTH  or HRTIM_TIM_FEROM_CREST  or HRTIM_TIM_FEROM_VALLEY
+  *                   @arg HRTIM_TIM_BMROM_BOTH  or HRTIM_TIM_BMROM_CREST  or HRTIM_TIM_BMROM_VALLEY
+  *                   @arg HRTIM_TIM_ADROM_BOTH  or HRTIM_TIM_ADROM_CREST  or HRTIM_TIM_ADROM_VALLEY
+  *                   @arg HRTIM_TIM_OUTROM_BOTH or HRTIM_TIM_OUTROM_CREST or HRTIM_TIM_OUTROM_VALLEY
+  *                   @arg HRTIM_TIM_ROM_BOTH    or HRTIM_TIM_ROM_CREST    or HRTIM_TIM_ROM_VALLEY
+  * @note This function must be called before starting the timer
+  */
+HAL_StatusTypeDef HAL_HRTIM_RollOverModeConfig(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx,
+                                               uint32_t RollOverCfg)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_ROLLOVERMODE(RollOverCfg));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  HRTIM_TimingUnitRollOver_Config(hhrtim, TimerIdx, RollOverCfg);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Exported_Functions_Group8 Timer waveform configuration and functions
+  *  @brief    HRTIM timer configuration and control functions
+@verbatim
+ ===============================================================================
+              ##### HRTIM timer configuration and control functions #####
+ ===============================================================================
+    [..]  This section provides functions used to configure and control a
+          HRTIM timer operating in waveform mode:
+      (+) Configure HRTIM timer general behavior
+      (+) Configure HRTIM timer event filtering
+      (+) Configure HRTIM timer deadtime insertion
+      (+) Configure HRTIM timer chopper mode
+      (+) Configure HRTIM timer burst DMA
+      (+) Configure HRTIM timer compare unit
+      (+) Configure HRTIM timer capture unit
+      (+) Configure HRTIM timer output
+      (+) Set HRTIM timer output level
+      (+) Enable HRTIM timer output
+      (+) Disable HRTIM timer output
+      (+) Start HRTIM timer
+      (+) Stop HRTIM timer
+      (+) Start HRTIM timer and enable interrupt
+      (+) Stop HRTIM timer and disable interrupt
+      (+) Start HRTIM timer and enable DMA transfer
+      (+) Stop HRTIM timer and disable DMA transfer
+      (+) Enable or disable the burst mode controller
+      (+) Start the burst mode controller (by software)
+      (+) Trigger a Capture (by software)
+      (+) Update the HRTIM timer preloadable registers (by software)
+      (+) Reset the HRTIM timer counter (by software)
+      (+) Start a burst DMA transfer
+      (+) Enable timer register update
+      (+) Disable timer register update
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure the general behavior of a timer operating in waveform mode
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  pTimerCfg pointer to the timer configuration structure
+  * @note When the timer operates in waveform mode, all the features supported by
+  *       the HRTIM are available without any limitation.
+  * @retval HAL status
+  * @note This function must be called before starting the timer
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t TimerIdx,
+                                                const HRTIM_TimerCfgTypeDef *pTimerCfg)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+  /* Relevant for all HRTIM timers, including the master */
+  assert_param(IS_HRTIM_HALFMODE(pTimerCfg->HalfModeEnable));
+  assert_param(IS_HRTIM_INTERLEAVEDMODE(pTimerCfg->InterleavedMode));
+  assert_param(IS_HRTIM_SYNCSTART(pTimerCfg->StartOnSync));
+  assert_param(IS_HRTIM_SYNCRESET(pTimerCfg->ResetOnSync));
+  assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
+  assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
+  assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
+  assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+  {
+    /* Check parameters */
+    assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
+    assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
+    assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
+
+    /* Configure master timer */
+    HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
+  }
+  else
+  {
+    /* Check parameters */
+    assert_param(IS_HRTIM_UPDATEGATING_TIM(pTimerCfg->UpdateGating));
+    assert_param(IS_HRTIM_TIM_IT(pTimerCfg->InterruptRequests));
+    assert_param(IS_HRTIM_TIM_DMA(pTimerCfg->DMARequests));
+    assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
+    assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
+    assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
+    assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->PushPull,
+                                               pTimerCfg->DeadTimeInsertion));
+    assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->PushPull,
+                                               pTimerCfg->DelayedProtectionMode));
+    assert_param(IS_HRTIM_OUTPUTBALANCEDIDLE(pTimerCfg->BalancedIdleAutomaticResume));
+    assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
+    assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
+    assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
+    assert_param(IS_HRTIM_TIMSYNCUPDATE(pTimerCfg->ReSyncUpdate));
+
+    /* Configure timing unit */
+    HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
+  }
+
+  /* Update timer parameters */
+  hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
+  hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
+  hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
+  hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
+  hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
+
+  /* Force a software update */
+  HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
+
+  /* Configure slave timer update re-synchronization */
+  if ((TimerIdx != HRTIM_TIMERINDEX_MASTER)
+      && (pTimerCfg->UpdateGating == HRTIM_UPDATEGATING_INDEPENDENT))
+  {
+    MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR,
+               HRTIM_TIMCR_RSYNCU_Msk,
+               pTimerCfg->ReSyncUpdate << HRTIM_TIMCR_RSYNCU_Pos);
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the general behavior of a timer operating in waveform mode
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  pTimerCtl pointer to the timer configuration structure
+  * @note When the timer operates in waveform mode, all the features supported by
+  *       the HRTIM are available without any limitation.
+  * @retval HAL status
+  * @note This function must be called before starting the timer
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t TimerIdx,
+                                                 const HRTIM_TimerCtlTypeDef *pTimerCtl)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+  /* Relevant for all A..F HRTIM timers */
+  assert_param(IS_HRTIM_TIMERUPDOWNMODE(pTimerCtl->UpDownMode));
+  assert_param(IS_HRTIM_TIMERTRGHLFMODE(pTimerCtl->TrigHalf));
+  assert_param(IS_HRTIM_TIMERGTCMP3(pTimerCtl->GreaterCMP3));
+  assert_param(IS_HRTIM_TIMERGTCMP1(pTimerCtl->GreaterCMP1));
+  assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset));
+  assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep));
+  assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Configure timing unit */
+  HRTIM_TimingUnitWaveform_Control(hhrtim, TimerIdx, pTimerCtl);
+
+  /* Force a software update */
+  HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the Dual Channel Dac behavior of a timer operating in waveform mode
+  * @param  hhrtim: pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  pTimerCtl pointer to the timer DualChannel Dac configuration structure
+  * @note When the timer operates in waveform mode, all the features supported by
+  *       the HRTIM are available without any limitation.
+  * @retval HAL status
+  * @note This function must be called before starting the timer
+  */
+HAL_StatusTypeDef HAL_HRTIM_TimerDualChannelDacConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                      uint32_t TimerIdx,
+                                                      const HRTIM_TimerCtlTypeDef *pTimerCtl)
+{
+  assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset));
+  assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep));
+  assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+  /* clear DCDS,DCDR,DCDE bits */
+  CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2,
+            (HRTIM_TIMER_DCDE_ENABLED |
+             HRTIM_TIMER_DCDS_OUT1RST |
+             HRTIM_TIMER_DCDR_OUT1SET));
+
+  MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2,
+             (HRTIM_TIMER_DCDE_ENABLED |
+              HRTIM_TIMER_DCDS_OUT1RST |
+              HRTIM_TIMER_DCDR_OUT1SET),
+             (pTimerCtl->DualChannelDacReset |
+              pTimerCtl->DualChannelDacStep |
+              pTimerCtl->DualChannelDacEnable));
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the event filtering capabilities of a timer (blanking, windowing)
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  Event external event for which timer event filtering must be configured
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_EVENT_1: External event 1
+  *                    @arg HRTIM_EVENT_2: External event 2
+  *                    @arg HRTIM_EVENT_3: External event 3
+  *                    @arg HRTIM_EVENT_4: External event 4
+  *                    @arg HRTIM_EVENT_5: External event 5
+  *                    @arg HRTIM_EVENT_6: External event 6
+  *                    @arg HRTIM_EVENT_7: External event 7
+  *                    @arg HRTIM_EVENT_8: External event 8
+  *                    @arg HRTIM_EVENT_9: External event 9
+  *                    @arg HRTIM_EVENT_10: External event 10
+  * @param  pTimerEventFilteringCfg pointer to the timer event filtering configuration structure
+  * @note This function must be called before starting the timer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                      uint32_t TimerIdx,
+                                                      uint32_t Event,
+                                                      const HRTIM_TimerEventFilteringCfgTypeDef *pTimerEventFilteringCfg)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_EVENT(Event));
+  assert_param(IS_HRTIM_TIMEVENTFILTER(TimerIdx, pTimerEventFilteringCfg->Filter));
+
+  assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Configure timer event filtering capabilities */
+  switch (Event)
+  {
+    case HRTIM_EVENT_NONE:
+    {
+      CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1);
+      CLEAR_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2);
+      break;
+    }
+
+    case HRTIM_EVENT_1:
+    {
+      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH),
+                 (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
+      break;
+    }
+
+    case HRTIM_EVENT_2:
+    {
+      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH),
+                 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U));
+      break;
+    }
+
+    case HRTIM_EVENT_3:
+    {
+      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH),
+                 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U));
+      break;
+    }
+
+    case HRTIM_EVENT_4:
+    {
+      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH),
+                 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U));
+      break;
+    }
+
+    case HRTIM_EVENT_5:
+    {
+      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR1, (HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH),
+                 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U));
+      break;
+    }
+
+    case HRTIM_EVENT_6:
+    {
+      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH),
+                 (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch));
+      break;
+    }
+
+    case HRTIM_EVENT_7:
+    {
+      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH),
+                 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6U));
+      break;
+    }
+
+    case HRTIM_EVENT_8:
+    {
+      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH),
+                 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12U));
+      break;
+    }
+
+    case HRTIM_EVENT_9:
+    {
+      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH),
+                 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18U));
+      break;
+    }
+
+    case HRTIM_EVENT_10:
+    {
+      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR2, (HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH),
+                 ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24U));
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the external Event Counter A or B of a timer (source, threshold, reset mode)
+  *         but does not enable : call HAL_HRTIM_ExternalEventCounterEnable afterwards
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  EventCounter external event Counter A or B for which timer event must be configured
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_EVENTCOUNTER_A
+  *                    @arg HRTIM_EVENTCOUNTER_B
+  * @param  pTimerExternalEventCfg: pointer to the timer external event configuration structure
+  * @note This function must be called before starting the timer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t EventCounter,
+                                                  const HRTIM_ExternalEventCfgTypeDef *pTimerExternalEventCfg)
+{
+  uint32_t hrtim_eefr3;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
+  assert_param(IS_HRTIM_TIMEEVENT_RESETMODE(pTimerExternalEventCfg->ResetMode));
+  assert_param(IS_HRTIM_TIMEEVENT_COUNTER(pTimerExternalEventCfg->Counter));
+  assert_param(IS_HRTIM_EVENT(pTimerExternalEventCfg->Source));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
+  {
+    if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE)
+    {
+      /* reset External EventCounter A */
+      WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0xFFFF0000U);
+    }
+    else
+    {
+      /* Set timer External EventCounter A configuration */
+      hrtim_eefr3  = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVARSTM_Pos;
+      hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVASEL_Pos;
+      hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVACNT_Pos;
+      /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */
+
+      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3,
+                 (HRTIM_EEFR3_EEVARSTM | HRTIM_EEFR3_EEVASEL | HRTIM_EEFR3_EEVACNT), hrtim_eefr3);
+    }
+  }
+
+  if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
+  {
+    if (pTimerExternalEventCfg->Source == HRTIM_EVENT_NONE)
+    {
+      /* reset External EventCounter B */
+      WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, 0x0000FFFFU);
+    }
+    else
+    {
+      /* Set timer External EventCounter B configuration */
+      hrtim_eefr3  = (pTimerExternalEventCfg->ResetMode) << HRTIM_EEFR3_EEVBRSTM_Pos;
+      hrtim_eefr3 |= ((pTimerExternalEventCfg->Source - 1U)) << HRTIM_EEFR3_EEVBSEL_Pos;
+      hrtim_eefr3 |= (pTimerExternalEventCfg->Counter) << HRTIM_EEFR3_EEVBCNT_Pos;
+      /* do not enable, use HAL_HRTIM_TimerExternalEventEnable function */
+
+      MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3,
+                 (HRTIM_EEFR3_EEVBRSTM | HRTIM_EEFR3_EEVBSEL | HRTIM_EEFR3_EEVBCNT), hrtim_eefr3);
+    }
+  }
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the external event Counter A or B of a timer
+  * @param  hhrtim: pointer to HAL HRTIM handle
+  * @param  TimerIdx: Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  EventCounter external Event Counter A or B for which timer event must be configured
+  *                    This parameter can be a one of the following values:
+  *                    @arg HRTIM_EVENTCOUNTER_A
+  *                    @arg HRTIM_EVENTCOUNTER_B
+  * @note This function must be called before starting the timer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterEnable(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t EventCounter)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
+  {
+    SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACE);
+  }
+  if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
+  {
+    SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE);
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the external event Counter A or B of a timer
+  * @param  hhrtim: pointer to HAL HRTIM handle
+  * @param  TimerIdx: Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  EventCounter external event Counter A or B for which timer event must be configured
+  *                    This parameter can be a one of the following values:
+  *                    @arg HRTIM_EVENTCOUNTER_A
+  *                    @arg HRTIM_EVENTCOUNTER_B
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterDisable(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t TimerIdx,
+                                                   uint32_t EventCounter)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
+  {
+    CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACE);
+  }
+
+  if ((EventCounter & HRTIM_EVENTCOUNTER_B) != 0U)
+  {
+    CLEAR_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCE);
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Reset the external event Counter A or B of a timer
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  EventCounter external event Counter A or B for which timer event must be configured
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_EVENTCOUNTER_A
+  *                    @arg HRTIM_EVENTCOUNTER_B
+  * @note This function must be called before starting the timer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_ExtEventCounterReset(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t TimerIdx,
+                                                 uint32_t EventCounter)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_TIMEEVENT(EventCounter));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  if ((EventCounter & HRTIM_EVENTCOUNTER_A) != 0U)
+  {
+    SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVACRES);
+  }
+  if ((EventCounter & HRTIM_EVENTCOUNTER_B)  != 0U)
+  {
+    SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].EEFxR3, HRTIM_EEFR3_EEVBCRES);
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the dead-time insertion feature for a timer
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  pDeadTimeCfg pointer to the deadtime insertion configuration structure
+  * @retval HAL status
+  * @note This function must be called before starting the timer
+  */
+HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx,
+                                           const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg)
+{
+  uint32_t hrtim_dtr;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(pDeadTimeCfg->Prescaler));
+  assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
+  assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
+  assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
+  assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
+  assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
+  assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Set timer deadtime configuration */
+  hrtim_dtr  = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
+  hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
+  hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
+  hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
+  hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
+  hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
+  hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
+  hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
+  hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
+
+  /* Update the HRTIM registers */
+  MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
+               HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
+               HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
+               HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the chopper mode feature for a timer
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  pChopperModeCfg pointer to the chopper mode configuration structure
+  * @retval HAL status
+  * @note This function must be called before configuring the timer output(s)
+  */
+HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx,
+                                              const HRTIM_ChopperModeCfgTypeDef *pChopperModeCfg)
+{
+  uint32_t hrtim_chpr;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_CHOPPER_PRESCALERRATIO(pChopperModeCfg->CarrierFreq));
+  assert_param(IS_HRTIM_CHOPPER_DUTYCYCLE(pChopperModeCfg->DutyCycle));
+  assert_param(IS_HRTIM_CHOPPER_PULSEWIDTH(pChopperModeCfg->StartPulse));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Set timer choppe mode configuration */
+  hrtim_chpr  = (pChopperModeCfg->CarrierFreq & HRTIM_CHPR_CARFRQ);
+  hrtim_chpr |= (pChopperModeCfg->DutyCycle & HRTIM_CHPR_CARDTY);
+  hrtim_chpr |= (pChopperModeCfg->StartPulse & HRTIM_CHPR_STRPW);
+
+  /* Update the HRTIM registers */
+  MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CHPxR,
+             (HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW),
+             hrtim_chpr);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the burst DMA controller for a timer
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                  This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  RegistersToUpdate registers to be written by DMA
+  *                    This parameter can be any combination of the following values:
+  *                    @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
+  *                    @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
+  *                    @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
+  *                    @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
+  *                    @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
+  *                    @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
+  *                    @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
+  *                    @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
+  *                    @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
+  *                    @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
+  *                    @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
+  *                    @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
+  *                    @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
+  *                    @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
+  *                    @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
+  *                    @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
+  *                    @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
+  *                    @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
+  *                    @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
+  *                    @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
+  *                    @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
+  * @retval HAL status
+  * @note This function must be called before starting the timer
+  */
+HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx,
+                                           uint32_t RegistersToUpdate)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Set the burst DMA timer update register */
+  switch (TimerIdx)
+  {
+    case HRTIM_TIMERINDEX_TIMER_A:
+    {
+      hhrtim->Instance->sCommonRegs.BDTAUPR = RegistersToUpdate;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_B:
+    {
+      hhrtim->Instance->sCommonRegs.BDTBUPR = RegistersToUpdate;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_C:
+    {
+      hhrtim->Instance->sCommonRegs.BDTCUPR = RegistersToUpdate;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_D:
+    {
+      hhrtim->Instance->sCommonRegs.BDTDUPR = RegistersToUpdate;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_E:
+    {
+      hhrtim->Instance->sCommonRegs.BDTEUPR = RegistersToUpdate;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_F:
+    {
+      hhrtim->Instance->sCommonRegs.BDTFUPR = RegistersToUpdate;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_MASTER:
+    {
+      hhrtim->Instance->sCommonRegs.BDMUPR = RegistersToUpdate;
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the compare unit of a timer operating in waveform mode
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CompareUnit Compare unit to configure
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+  *                    @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+  *                    @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+  *                    @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+  * @param  pCompareCfg pointer to the compare unit configuration structure
+  * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
+  *       application has to configure separately the capture unit. Capture unit
+  *       to configure in that case depends on the compare unit auto delayed mode
+  *       is applied to (see below):
+  *         Auto delayed on output compare 2: capture unit 1 must be configured
+  *         Auto delayed on output compare 4: capture unit 2 must be configured
+  * @retval HAL status
+  * @note This function must be called before starting the timer
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t CompareUnit,
+                                                  const HRTIM_CompareCfgTypeDef *pCompareCfg)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Configure the compare unit */
+  if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+  {
+    switch (CompareUnit)
+    {
+      case HRTIM_COMPAREUNIT_1:
+      {
+        hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
+        break;
+      }
+
+      case HRTIM_COMPAREUNIT_2:
+      {
+        hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
+        break;
+      }
+
+      case HRTIM_COMPAREUNIT_3:
+      {
+        hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
+        break;
+      }
+
+      case HRTIM_COMPAREUNIT_4:
+      {
+        hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
+        break;
+      }
+
+      default:
+      {
+        hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhrtim);
+
+        break;
+      }
+    }
+
+    if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+    {
+      return HAL_ERROR;
+    }
+
+  }
+  else
+  {
+    switch (CompareUnit)
+    {
+      case HRTIM_COMPAREUNIT_1:
+      {
+        /* Set the compare value */
+        hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
+        break;
+      }
+
+      case HRTIM_COMPAREUNIT_2:
+      {
+        /* Check parameters */
+        assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
+
+        /* Set the compare value */
+        hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
+
+        if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
+        {
+          /* Configure auto-delayed mode */
+          /* DELCMP2 bitfield must be reset when reprogrammed from one value */
+          /* to the other to reinitialize properly the auto-delayed mechanism */
+          hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
+          hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
+
+          /* Set the compare value for timeout compare unit (if any) */
+          if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
+          {
+            hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
+          }
+          else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
+          {
+            hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
+          }
+          else
+          {
+            /* nothing to do */
+          }
+        }
+        else
+        {
+          /* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
+          MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
+        }
+        break;
+      }
+
+      case HRTIM_COMPAREUNIT_3:
+      {
+        /* Set the compare value */
+        hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
+        break;
+      }
+
+      case HRTIM_COMPAREUNIT_4:
+      {
+        /* Check parameters */
+        assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
+
+        /* Set the compare value */
+        hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
+
+        if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
+        {
+          /* Configure auto-delayed mode */
+          /* DELCMP4 bitfield must be reset when reprogrammed from one value */
+          /* to the other to reinitialize properly the auto-delayed mechanism */
+          hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
+          hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
+
+          /* Set the compare value for timeout compare unit (if any) */
+          if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
+          {
+            hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
+          }
+          else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
+          {
+            hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
+          }
+          else
+          {
+            /* nothing to do */
+          }
+        }
+        else
+        {
+          /* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
+          MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
+        }
+        break;
+      }
+
+      default:
+      {
+        hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhrtim);
+
+        break;
+      }
+    }
+
+    if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+    {
+      return HAL_ERROR;
+    }
+
+  }
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the capture unit of a timer operating in waveform mode
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CaptureUnit Capture unit to configure
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+  *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+  * @param  pCaptureCfg pointer to the compare unit configuration structure
+  * @retval HAL status
+  * @note This function must be called before starting the timer
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t TimerIdx,
+                                                  uint32_t CaptureUnit,
+                                                  const HRTIM_CaptureCfgTypeDef *pCaptureCfg)
+{
+  uint32_t Trigger;
+  uint32_t TimerF_Trigger = (uint32_t)(pCaptureCfg->Trigger >> 32);
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMER_CAPTURETRIGGER(TimerIdx, (uint32_t)(pCaptureCfg->Trigger)));
+  assert_param(IS_HRTIM_TIMER_CAPTUREFTRIGGER(TimerIdx, TimerF_Trigger));
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* TimerF_Trigger is valid for setting other Timers than Timer F */
+  if (TimerIdx == HRTIM_TIMERINDEX_TIMER_A)
+  { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFF0FFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TA1SET_Pos); }
+  else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_B)
+  { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFF0FFFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TB1SET_Pos); }
+  else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_C)
+  { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFF0FFFFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TC1SET_Pos); }
+  else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_D)
+  { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xF0FFFFFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TD1SET_Pos); }
+  else if (TimerIdx == HRTIM_TIMERINDEX_TIMER_E)
+  { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0x0FFFFFFFU) | ((TimerF_Trigger) << HRTIM_CPT1CR_TE1SET_Pos); }
+  else
+  { Trigger = ((uint32_t)(pCaptureCfg->Trigger) & 0xFFFFFFFFU); }
+  /* for setting source capture on Timer F, use Trigger only (all bits are valid then) */
+
+  /* Configure the capture unit */
+
+  switch (CaptureUnit)
+  {
+    case HRTIM_CAPTUREUNIT_1:
+    {
+      WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, Trigger);
+      break;
+    }
+
+    case HRTIM_CAPTUREUNIT_2:
+    {
+      WRITE_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, Trigger);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Configure the output of a timer operating in waveform mode
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  Output Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @param  pOutputCfg pointer to the timer output configuration structure
+  * @retval HAL status
+  * @note This function must be called before configuring the timer and after
+  *       configuring the deadtime insertion feature (if required).
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t TimerIdx,
+                                                 uint32_t Output,
+                                                 const HRTIM_OutputCfgTypeDef *pOutputCfg)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+  assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
+  assert_param(IS_HRTIM_OUTPUTIDLELEVEL(pOutputCfg->IdleLevel));
+  assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
+  assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
+  assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
+  assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Configure the timer output */
+  HRTIM_OutputConfig(hhrtim,
+                     TimerIdx,
+                     Output,
+                     pOutputCfg);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Force the timer output to its active or inactive state
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  Output Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @param OutputLevel indicates whether the output is forced to its active or inactive level
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active level
+  *                    @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive level
+  * @retval HAL status
+  * @note The 'software set/reset trigger' bit in the output set/reset registers
+  *       is automatically reset by hardware
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t TimerIdx,
+                                                   uint32_t Output,
+                                                   uint32_t OutputLevel)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+  assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Force timer output level */
+  switch (Output)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
+      {
+        /* Force output to its active state */
+        SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R, HRTIM_SET1R_SST);
+      }
+      else
+      {
+        /* Force output to its inactive state */
+        SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R, HRTIM_RST1R_SRT);
+      }
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
+      {
+        /* Force output to its active state */
+        SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R, HRTIM_SET2R_SST);
+      }
+      else
+      {
+        /* Force output to its inactive state */
+        SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R, HRTIM_RST2R_SRT);
+      }
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the generation of the waveform signal on the designated output(s)
+  *         Outputs can be combined (ORed) to allow for simultaneous output enabling.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  OutputsToStart Timer output(s) to enable
+  *                    This parameter can be any combination of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t OutputsToStart)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable the HRTIM outputs */
+  hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the generation of the waveform signal on the designated output(s)
+  *         Outputs can be combined (ORed) to allow for simultaneous output disabling.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  OutputsToStop Timer output(s) to disable
+  *                    This parameter can be any combination of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t OutputsToStop)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable the HRTIM outputs */
+  hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the counter of the designated timer(s) operating in waveform mode
+  *         Timers can be combined (ORed) to allow for simultaneous counter start.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Timers Timer counter(s) to start
+  *                   This parameter can be any combination of the following values:
+  *                   @arg HRTIM_TIMERID_MASTER
+  *                   @arg HRTIM_TIMERID_TIMER_A
+  *                   @arg HRTIM_TIMERID_TIMER_B
+  *                   @arg HRTIM_TIMERID_TIMER_C
+  *                   @arg HRTIM_TIMERID_TIMER_D
+  *                   @arg HRTIM_TIMERID_TIMER_E
+  *                   @arg HRTIM_TIMERID_TIMER_F
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t Timers)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERID(Timers));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable timer(s) counter */
+  hhrtim->Instance->sMasterRegs.MCR |= (Timers);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the counter of the designated timer(s) operating in waveform mode
+  *         Timers can be combined (ORed) to allow for simultaneous counter stop.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Timers Timer counter(s) to stop
+  *                   This parameter can be any combination of the following values:
+  *                   @arg HRTIM_TIMERID_MASTER
+  *                   @arg HRTIM_TIMERID_TIMER_A
+  *                   @arg HRTIM_TIMERID_TIMER_B
+  *                   @arg HRTIM_TIMERID_TIMER_C
+  *                   @arg HRTIM_TIMERID_TIMER_D
+  *                   @arg HRTIM_TIMERID_TIMER_E
+  *                   @arg HRTIM_TIMERID_TIMER_F
+  * @retval HAL status
+  * @note The counter of a timer is stopped only if all timer outputs are disabled
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t Timers)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERID(Timers));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Disable timer(s) counter */
+  hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the counter of the designated timer(s) operating in waveform mode
+  *         Timers can be combined (ORed) to allow for simultaneous counter start.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Timers Timer counter(s) to start
+  *                   This parameter can be any combination of the following values:
+  *                   @arg HRTIM_TIMERID_MASTER
+  *                   @arg HRTIM_TIMERID_TIMER_A
+  *                   @arg HRTIM_TIMERID_TIMER_B
+  *                   @arg HRTIM_TIMERID_TIMER_C
+  *                   @arg HRTIM_TIMERID_TIMER_D
+  *                   @arg HRTIM_TIMERID_TIMER_E
+  *                   @arg HRTIM_TIMERID_TIMER_F
+  * @note HRTIM interrupts (e.g. faults interrupts) and interrupts related
+  *       to the timers to start are enabled within this function.
+  *       Interrupts to enable are selected through HAL_HRTIM_WaveformTimerConfig
+  *       function.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t Timers)
+{
+  uint8_t timer_idx;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERID(Timers));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable HRTIM interrupts (if required) */
+  __HAL_HRTIM_ENABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests);
+
+  /* Enable master timer related interrupts (if required) */
+  if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
+  {
+    __HAL_HRTIM_MASTER_ENABLE_IT(hhrtim,
+                                 hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
+  }
+
+  /* Enable timing unit related interrupts (if required) */
+  for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+       timer_idx < HRTIM_TIMERINDEX_MASTER ;
+       timer_idx++)
+  {
+    if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
+    {
+      __HAL_HRTIM_TIMER_ENABLE_IT(hhrtim,
+                                  timer_idx,
+                                  hhrtim->TimerParam[timer_idx].InterruptRequests);
+    }
+  }
+
+  /* Enable timer(s) counter */
+  hhrtim->Instance->sMasterRegs.MCR |= (Timers);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the counter of the designated timer(s) operating in waveform mode
+  *         Timers can be combined (ORed) to allow for simultaneous counter stop.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Timers Timer counter(s) to stop
+  *                   This parameter can be any combination of the following values:
+  *                   @arg HRTIM_TIMERID_MASTER
+  *                   @arg HRTIM_TIMERID_TIMER_A
+  *                   @arg HRTIM_TIMERID_TIMER_B
+  *                   @arg HRTIM_TIMERID_TIMER_C
+  *                   @arg HRTIM_TIMERID_TIMER_D
+  *                   @arg HRTIM_TIMERID_TIMER_E
+  *                   @arg HRTIM_TIMERID_TIMER_F
+  * @retval HAL status
+  * @note The counter of a timer is stopped only if all timer outputs are disabled
+  * @note All enabled timer related interrupts are disabled.
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim,
+                                                 uint32_t Timers)
+{
+  /* ++ WA */
+  __IO uint32_t delai = (uint32_t)(0x17FU);
+  /* -- WA */
+
+  uint8_t timer_idx;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERID(Timers));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Disable HRTIM interrupts (if required) */
+  __HAL_HRTIM_DISABLE_IT(hhrtim, hhrtim->Init.HRTIMInterruptRequests);
+
+  /* Disable master timer related interrupts (if required) */
+  if ((Timers & HRTIM_TIMERID_MASTER) != 0U)
+  {
+    /* Interrupts enable flag must be cleared one by one */
+    __HAL_HRTIM_MASTER_DISABLE_IT(hhrtim, hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].InterruptRequests);
+  }
+
+  /* Disable timing unit related interrupts (if required) */
+  for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+       timer_idx < HRTIM_TIMERINDEX_MASTER ;
+       timer_idx++)
+  {
+    if ((Timers & TimerIdxToTimerId[timer_idx]) != 0U)
+    {
+      __HAL_HRTIM_TIMER_DISABLE_IT(hhrtim, timer_idx, hhrtim->TimerParam[timer_idx].InterruptRequests);
+    }
+  }
+
+  /* ++ WA */
+  do { delai--; } while (delai != 0U);
+  /* -- WA */
+
+  /* Disable timer(s) counter */
+  hhrtim->Instance->sMasterRegs.MCR &= ~(Timers);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start the counter of the designated timer(s) operating in waveform mode
+  *         Timers can be combined (ORed) to allow for simultaneous counter start.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Timers Timer counter(s) to start
+  *                   This parameter can be any combination of the following values:
+  *                   @arg HRTIM_TIMERID_MASTER
+  *                   @arg HRTIM_TIMERID_TIMER_A
+  *                   @arg HRTIM_TIMERID_TIMER_B
+  *                   @arg HRTIM_TIMERID_TIMER_C
+  *                   @arg HRTIM_TIMERID_TIMER_D
+  *                   @arg HRTIM_TIMERID_TIMER_E
+  *                   @arg HRTIM_TIMERID_TIMER_F
+  * @retval HAL status
+  * @note This function enables the dma request(s) mentioned in the timer
+  *       configuration data structure for every timers to start.
+  * @note The source memory address, the destination memory address and the
+  *       size of each DMA transfer are specified at timer configuration time
+  *       (see HAL_HRTIM_WaveformTimerConfig)
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                                   uint32_t Timers)
+{
+  uint8_t timer_idx;
+  DMA_HandleTypeDef *hdma;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERID(Timers));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  if (((Timers & HRTIM_TIMERID_MASTER) != (uint32_t)RESET) &&
+      (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
+  {
+    /* Set the DMA error callback */
+    hhrtim->hdmaMaster->XferErrorCallback = HRTIM_DMAError ;
+
+    /* Set the DMA transfer completed callback */
+    hhrtim->hdmaMaster->XferCpltCallback = HRTIM_DMAMasterCplt;
+
+    /* Enable the DMA channel */
+    if (HAL_DMA_Start_IT(hhrtim->hdmaMaster,
+                         hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASrcAddress,
+                         hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMADstAddress,
+                         hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMASize) != HAL_OK)
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      return HAL_ERROR;
+    }
+
+    /* Enable the timer DMA request */
+    __HAL_HRTIM_MASTER_ENABLE_DMA(hhrtim,
+                                  hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
+  }
+
+  for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+       timer_idx < HRTIM_TIMERINDEX_MASTER ;
+       timer_idx++)
+  {
+    if (((Timers & TimerIdxToTimerId[timer_idx]) != (uint32_t)RESET) &&
+        (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
+    {
+      /* Get the timer DMA handler */
+      hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx);
+
+      if (hdma == NULL)
+      {
+        hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhrtim);
+
+        return HAL_ERROR;
+      }
+
+      /* Set the DMA error callback */
+      hdma->XferErrorCallback = HRTIM_DMAError ;
+
+      /* Set the DMA transfer completed callback */
+      hdma->XferCpltCallback = HRTIM_DMATimerxCplt;
+
+      /* Enable the DMA channel */
+      if (HAL_DMA_Start_IT(hdma,
+                           hhrtim->TimerParam[timer_idx].DMASrcAddress,
+                           hhrtim->TimerParam[timer_idx].DMADstAddress,
+                           hhrtim->TimerParam[timer_idx].DMASize) != HAL_OK)
+      {
+        hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+        /* Process Unlocked */
+        __HAL_UNLOCK(hhrtim);
+
+        return HAL_ERROR;
+      }
+
+      /* Enable the timer DMA request */
+      __HAL_HRTIM_TIMER_ENABLE_DMA(hhrtim,
+                                   timer_idx,
+                                   hhrtim->TimerParam[timer_idx].DMARequests);
+    }
+  }
+
+  /* Enable the timer counter */
+  __HAL_HRTIM_ENABLE(hhrtim, Timers);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Stop the counter of the designated timer(s) operating in waveform mode
+  *         Timers can be combined (ORed) to allow for simultaneous counter stop.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Timers Timer counter(s) to stop
+  *                   This parameter can be any combination of the following values:
+  *                   @arg HRTIM_TIMERID_MASTER
+  *                   @arg HRTIM_TIMERID_TIMER_A
+  *                   @arg HRTIM_TIMERID_TIMER_B
+  *                   @arg HRTIM_TIMERID_TIMER_C
+  *                   @arg HRTIM_TIMERID_TIMER_D
+  *                   @arg HRTIM_TIMERID_TIMER_E
+  *                   @arg HRTIM_TIMERID_TIMER_F
+  * @retval HAL status
+  * @note  The counter of a timer is stopped only if all timer outputs are disabled
+  * @note  All enabled timer related DMA requests are disabled.
+  */
+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim,
+                                                  uint32_t Timers)
+{
+  uint8_t timer_idx;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERID(Timers));
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  if (((Timers & HRTIM_TIMERID_MASTER) != 0U) &&
+      (hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests != 0U))
+  {
+    /* Disable the DMA */
+    if (HAL_DMA_Abort(hhrtim->hdmaMaster) != HAL_OK)
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+    }
+    else
+    {
+      hhrtim->State = HAL_HRTIM_STATE_READY;
+      /* Disable the DMA request(s) */
+      __HAL_HRTIM_MASTER_DISABLE_DMA(hhrtim,
+                                     hhrtim->TimerParam[HRTIM_TIMERINDEX_MASTER].DMARequests);
+    }
+  }
+
+  for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
+       timer_idx < HRTIM_TIMERINDEX_MASTER ;
+       timer_idx++)
+  {
+    if (((Timers & TimerIdxToTimerId[timer_idx]) != 0U) &&
+        (hhrtim->TimerParam[timer_idx].DMARequests != 0U))
+    {
+      /* Get the timer DMA handler */
+      /* Disable the DMA */
+      if (HAL_DMA_Abort(HRTIM_GetDMAHandleFromTimerIdx(hhrtim, timer_idx)) != HAL_OK)
+      {
+        hhrtim->State = HAL_HRTIM_STATE_ERROR;
+      }
+      else
+      {
+        hhrtim->State = HAL_HRTIM_STATE_READY;
+
+        /* Disable the DMA request(s) */
+        __HAL_HRTIM_TIMER_DISABLE_DMA(hhrtim,
+                                      timer_idx,
+                                      hhrtim->TimerParam[timer_idx].DMARequests);
+      }
+    }
+  }
+
+  /* Disable the timer counter */
+  __HAL_HRTIM_DISABLE(hhrtim, Timers);
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+  else
+  {
+    return HAL_OK;
+  }
+}
+
+/**
+  * @brief  Enable or disables the HRTIM burst mode controller.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Enable Burst mode controller enabling
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
+  *                    @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
+  * @retval HAL status
+  * @note This function must be called after starting the timer(s)
+  */
+HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,
+                                         uint32_t Enable)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_BURSTMODECTL(Enable));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable/Disable the burst mode controller */
+  MODIFY_REG(hhrtim->Instance->sCommonRegs.BMCR, HRTIM_BMCR_BME, Enable);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Trig the burst mode operation.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim)
+{
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Software trigger of the burst mode controller */
+  SET_BIT(hhrtim->Instance->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Trig a software capture on the designed capture unit
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CaptureUnit Capture unit to trig
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+  *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+  * @retval HAL status
+  * @note The 'software capture' bit in the capure configuration register is
+  *       automatically reset by hardware
+  */
+HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx,
+                                            uint32_t CaptureUnit)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Force a software capture on concerned capture unit */
+  switch (CaptureUnit)
+  {
+    case HRTIM_CAPTUREUNIT_1:
+    {
+      SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xCR, HRTIM_CPT1CR_SWCPT);
+      break;
+    }
+
+    case HRTIM_CAPTUREUNIT_2:
+    {
+      SET_BIT(hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xCR, HRTIM_CPT2CR_SWCPT);
+      break;
+    }
+
+    default:
+    {
+      hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      break;
+    }
+  }
+
+  if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Trig the update of the registers of one or several timers
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Timers timers concerned with the software register update
+  *                   This parameter can be any combination of the following values:
+  *                   @arg HRTIM_TIMERUPDATE_MASTER
+  *                   @arg HRTIM_TIMERUPDATE_A
+  *                   @arg HRTIM_TIMERUPDATE_B
+  *                   @arg HRTIM_TIMERUPDATE_C
+  *                   @arg HRTIM_TIMERUPDATE_D
+  *                   @arg HRTIM_TIMERUPDATE_E
+  *                   @arg HRTIM_TIMERUPDATE_F
+  * @retval HAL status
+  * @note The 'software update' bits in the HRTIM control register 2 register are
+  *       automatically reset by hardware
+  */
+HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t Timers)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMERUPDATE(Timers));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Force timer(s) registers update */
+  hhrtim->Instance->sCommonRegs.CR2 |= Timers;
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Swap the Timer  outputs
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Timers timers concerned with the software register update
+  *                   This parameter can be any combination of the following values:
+  *                   @arg HRTIM_TIMERSWAP_A
+  *                   @arg HRTIM_TIMERSWAP_B
+  *                   @arg HRTIM_TIMERSWAP_C
+  *                   @arg HRTIM_TIMERSWAP_D
+  *                   @arg HRTIM_TIMERSWAP_E
+  *                   @arg HRTIM_TIMERSWAP_F
+  * @retval HAL status
+  * @note The function is not significant when the Push-pull mode is enabled (PSHPLL = 1)
+  */
+HAL_StatusTypeDef HAL_HRTIM_SwapTimerOutput(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t Timers)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMERSWAP(Timers));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Force timer(s) registers update */
+  hhrtim->Instance->sCommonRegs.CR2 |= Timers;
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Trig the reset of one or several timers
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Timers timers concerned with the software counter reset
+  *                   This parameter can be any combination of the following values:
+  *                   @arg HRTIM_TIMERRESET_MASTER
+  *                   @arg HRTIM_TIMERRESET_TIMER_A
+  *                   @arg HRTIM_TIMERRESET_TIMER_B
+  *                   @arg HRTIM_TIMERRESET_TIMER_C
+  *                   @arg HRTIM_TIMERRESET_TIMER_D
+  *                   @arg HRTIM_TIMERRESET_TIMER_E
+  *                   @arg HRTIM_TIMERRESET_TIMER_F
+  * @retval HAL status
+  * @note The 'software reset' bits in the HRTIM control register 2  are
+  *       automatically reset by hardware
+  */
+HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,
+                                          uint32_t Timers)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMERRESET(Timers));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Force timer(s) registers reset */
+  hhrtim->Instance->sCommonRegs.CR2 = Timers;
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Swap the output of one or several timers
+  * @param hhrtim: pointer to HAL HRTIM handle
+  * @param Timers: timers concerned with the software register update
+  * This parameter can be any combination of the following values:
+  * @arg HRTIM_TIMERSWAP_A
+  * @arg HRTIM_TIMERSWAP_B
+  * @arg HRTIM_TIMERSWAP_C
+  * @arg HRTIM_TIMERSWAP_D
+  * @arg HRTIM_TIMERSWAP_E
+  * @arg HRTIM_TIMERSWAP_F
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_OutputSwapEnable(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t Timers)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMERSWAP(Timers));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Force timer(s) registers update */
+  hhrtim->Instance->sCommonRegs.CR2 |= Timers;
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Un-swap the output of one or several timers
+  * @param hhrtim: pointer to HAL HRTIM handle
+  * @param Timers: timers concerned with the software register update
+  * This parameter can be any combination of the following values:
+  * @arg HRTIM_TIMERSWAP_A
+  * @arg HRTIM_TIMERSWAP_B
+  * @arg HRTIM_TIMERSWAP_C
+  * @arg HRTIM_TIMERSWAP_D
+  * @arg HRTIM_TIMERSWAP_E
+  * @arg HRTIM_TIMERSWAP_F
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_OutputSwapDisable(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t Timers)
+{
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMERSWAP(Timers));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Force timer(s) registers update */
+  hhrtim->Instance->sCommonRegs.CR2 &= ~(Timers);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start a burst DMA operation to update HRTIM control registers content
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  BurstBufferAddress address of the buffer the HRTIM control registers
+  *                             content will be updated from.
+  * @param  BurstBufferLength size (in WORDS) of the burst buffer.
+  * @retval HAL status
+  * @note The TimerIdx parameter determines the dma channel to be used by the
+  *       DMA burst controller (see below)
+  *       HRTIM_TIMERINDEX_MASTER: DMA channel 2 is used by the DMA burst controller
+  *       HRTIM_TIMERINDEX_TIMER_A: DMA channel 3 is used by the DMA burst controller
+  *       HRTIM_TIMERINDEX_TIMER_B: DMA channel 4 is used by the DMA burst controller
+  *       HRTIM_TIMERINDEX_TIMER_C: DMA channel 5 is used by the DMA burst controller
+  *       HRTIM_TIMERINDEX_TIMER_D: DMA channel 6 is used by the DMA burst controller
+  *       HRTIM_TIMERINDEX_TIMER_E: DMA channel 7 is used by the DMA burst controller
+  *       HRTIM_TIMERINDEX_TIMER_F: DMA channel 8 is used by the DMA burst controller
+  */
+HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             uint32_t BurstBufferAddress,
+                                             uint32_t BurstBufferLength)
+{
+  DMA_HandleTypeDef *hdma;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+  if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
+  {
+    return HAL_BUSY;
+  }
+  if (hhrtim->State == HAL_HRTIM_STATE_READY)
+  {
+    if ((BurstBufferAddress == 0U) || (BurstBufferLength == 0U))
+    {
+      return HAL_ERROR;
+    }
+    else
+    {
+      hhrtim->State = HAL_HRTIM_STATE_BUSY;
+    }
+  }
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  /* Get the timer DMA handler */
+  hdma = HRTIM_GetDMAHandleFromTimerIdx(hhrtim, TimerIdx);
+
+  if (hdma == NULL)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  /* Set the DMA transfer completed callback */
+  hdma->XferCpltCallback = HRTIM_BurstDMACplt;
+
+  /* Set the DMA error callback */
+  hdma->XferErrorCallback = HRTIM_DMAError ;
+
+  /* Enable the DMA channel */
+  if (HAL_DMA_Start_IT(hdma,
+                       BurstBufferAddress,
+                       (uint32_t) &(hhrtim->Instance->sCommonRegs.BDMADR),
+                       BurstBufferLength) != HAL_OK)
+  {
+    hhrtim->State = HAL_HRTIM_STATE_ERROR;
+
+    /* Process Unlocked */
+    __HAL_UNLOCK(hhrtim);
+
+    return HAL_ERROR;
+  }
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the transfer from preload to active registers for one
+  *         or several timing units (including master timer).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Timers Timer(s) concerned by the register preload enabling command
+  *                   This parameter can be any combination of the following values:
+  *                   @arg HRTIM_TIMERUPDATE_MASTER
+  *                   @arg HRTIM_TIMERUPDATE_A
+  *                   @arg HRTIM_TIMERUPDATE_B
+  *                   @arg HRTIM_TIMERUPDATE_C
+  *                   @arg HRTIM_TIMERUPDATE_D
+  *                   @arg HRTIM_TIMERUPDATE_E
+  *                   @arg HRTIM_TIMERUPDATE_E
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,
+                                         uint32_t Timers)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERUPDATE(Timers));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable timer(s) registers update */
+  hhrtim->Instance->sCommonRegs.CR1 &= ~(Timers);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the transfer from preload to active registers for one
+  *         or several timing units (including master timer).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Timers Timer(s) concerned by the register preload disabling command
+  *                   This parameter can be any combination of the following values:
+  *                   @arg HRTIM_TIMERUPDATE_MASTER
+  *                   @arg HRTIM_TIMERUPDATE_A
+  *                   @arg HRTIM_TIMERUPDATE_B
+  *                   @arg HRTIM_TIMERUPDATE_C
+  *                   @arg HRTIM_TIMERUPDATE_D
+  *                   @arg HRTIM_TIMERUPDATE_E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,
+                                          uint32_t Timers)
+{
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMERUPDATE(Timers));
+
+  /* Process Locked */
+  __HAL_LOCK(hhrtim);
+
+  hhrtim->State = HAL_HRTIM_STATE_BUSY;
+
+  /* Enable timer(s) registers update */
+  hhrtim->Instance->sCommonRegs.CR1 |= (Timers);
+
+  hhrtim->State = HAL_HRTIM_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(hhrtim);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Exported_Functions_Group9 Peripheral state functions
+  *  @brief    Peripheral State functions
+@verbatim
+ ===============================================================================
+              ##### Peripheral State functions #####
+ ===============================================================================
+    [..]  This section provides functions used to get HRTIM or HRTIM timer
+          specific information:
+      (+) Get HRTIM HAL state
+      (+) Get captured value
+      (+) Get HRTIM timer output level
+      (+) Get HRTIM timer output state
+      (+) Get delayed protection status
+      (+) Get burst status
+      (+) Get current push-pull status
+      (+) Get idle push-pull status
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the HRTIM HAL state
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval HAL state
+  */
+HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(const HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Return HRTIM state */
+  return hhrtim->State;
+}
+
+/**
+  * @brief  Return actual value of the capture register of the designated capture unit
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CaptureUnit Capture unit to trig
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+  *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+  * @retval Captured value
+  */
+uint32_t HAL_HRTIM_GetCapturedValue(const HRTIM_HandleTypeDef *hhrtim,
+                                    uint32_t TimerIdx,
+                                    uint32_t CaptureUnit)
+{
+  uint32_t captured_value;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
+
+  /* Read captured value */
+  switch (CaptureUnit)
+  {
+    case HRTIM_CAPTUREUNIT_1:
+    {
+      captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & 0x0000FFFFU;
+      break;
+    }
+
+    case HRTIM_CAPTUREUNIT_2:
+    {
+      captured_value = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & 0x0000FFFFU;
+      break;
+    }
+
+    default:
+    {
+      captured_value = 0xFFFFFFFFUL;
+      break;
+    }
+
+  }
+
+  return captured_value;
+}
+
+/**
+  * @brief  Return actual value and direction of the capture register of the designated capture unit
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CaptureUnit Capture unit to trig
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+  *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+  * @retval captured value and direction structure
+  */
+HRTIM_CaptureValueTypeDef HAL_HRTIM_GetCaptured(const HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t TimerIdx,
+                                                uint32_t CaptureUnit)
+{
+  uint32_t tmp;
+  HRTIM_CaptureValueTypeDef captured;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
+
+  /* Read captured value */
+  switch (CaptureUnit)
+  {
+    case HRTIM_CAPTUREUNIT_1:
+      tmp = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR;
+      captured.Value = tmp & HRTIM_CPT1R_CPT1R & 0x0000FFFFU;
+      captured.Dir = (((tmp & HRTIM_CPT1R_DIR) == HRTIM_CPT1R_DIR) ? 1U : 0U);
+      break;
+    case HRTIM_CAPTUREUNIT_2:
+      tmp = hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR;
+      captured.Value = tmp & HRTIM_CPT2R_CPT2R & 0x0000FFFFU;
+      captured.Dir = (((tmp & HRTIM_CPT2R_DIR) == HRTIM_CPT2R_DIR) ? 1U : 0U);
+      break;
+    default:
+      captured.Value = 0xFFFFFFFFUL;
+      captured.Dir = 0xFFFFFFFFUL;
+      break;
+  }
+
+  return captured;
+}
+
+/**
+  * @brief  Return actual direction of the capture register of the designated capture unit
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  CaptureUnit Capture unit to trig
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+  *                    @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+  * @retval captured direction
+  *                    @arg This parameter is one HRTIM_Timer_UpDown_Mode :
+  *                    @arg HRTIM_TIMERUPDOWNMODE_UP
+  *                    @arg HRTIM_TIMERUPDOWNMODE_UPDOWN
+  */
+uint32_t HAL_HRTIM_GetCapturedDir(const HRTIM_HandleTypeDef *hhrtim,
+                                  uint32_t TimerIdx,
+                                  uint32_t CaptureUnit)
+{
+  uint32_t tmp;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+  assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
+
+  /* Read captured value */
+  switch (CaptureUnit)
+  {
+    case HRTIM_CAPTUREUNIT_1:
+      tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT1xR & HRTIM_CPT1R_DIR) >> HRTIM_CPT1R_DIR_Pos);
+      break;
+    case HRTIM_CAPTUREUNIT_2:
+      tmp = ((hhrtim->Instance->sTimerxRegs[TimerIdx].CPT2xR & HRTIM_CPT2R_DIR) >> HRTIM_CPT2R_DIR_Pos);
+      break;
+    default:
+      tmp = 0xFFFFFFFFU;
+      break;
+  }
+
+  return tmp;
+}
+
+
+/**
+  * @brief  Return actual level (active or inactive) of the designated output
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  Output Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval Output level
+  * @note Returned output level is taken before the output stage (chopper,
+  *        polarity).
+  */
+uint32_t HAL_HRTIM_WaveformGetOutputLevel(const HRTIM_HandleTypeDef *hhrtim,
+                                          uint32_t TimerIdx,
+                                          uint32_t Output)
+{
+  uint32_t output_level;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+  /* Read the output level */
+  switch (Output)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != (uint32_t)RESET)
+      {
+        output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
+      }
+      else
+      {
+        output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+      }
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != (uint32_t)RESET)
+      {
+        output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
+      }
+      else
+      {
+        output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+      }
+      break;
+    }
+
+    default:
+    {
+      output_level = 0xFFFFFFFFUL;
+      break;
+    }
+  }
+
+  return output_level;
+}
+
+/**
+  * @brief  Return actual state (RUN, IDLE, FAULT) of the designated output
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  Output Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval Output state
+  */
+uint32_t HAL_HRTIM_WaveformGetOutputState(const HRTIM_HandleTypeDef *hhrtim,
+                                          uint32_t TimerIdx,
+                                          uint32_t Output)
+{
+  uint32_t output_bit;
+  uint32_t output_state;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(TimerIdx);
+
+  /* Set output state according to output control status and output disable status */
+  switch (Output)
+  {
+    case HRTIM_OUTPUT_TA1:
+    {
+      output_bit = HRTIM_OENR_TA1OEN;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    {
+      output_bit = HRTIM_OENR_TA2OEN;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TB1:
+    {
+      output_bit = HRTIM_OENR_TB1OEN;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TB2:
+    {
+      output_bit = HRTIM_OENR_TB2OEN;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TC1:
+    {
+      output_bit = HRTIM_OENR_TC1OEN;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TC2:
+    {
+      output_bit = HRTIM_OENR_TC2OEN;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TD1:
+    {
+      output_bit = HRTIM_OENR_TD1OEN;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TD2:
+    {
+      output_bit = HRTIM_OENR_TD2OEN;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TE1:
+    {
+      output_bit = HRTIM_OENR_TE1OEN;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TE2:
+    {
+      output_bit = HRTIM_OENR_TE2OEN;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TF1:
+    {
+      output_bit = HRTIM_OENR_TF1OEN;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TF2:
+    {
+      output_bit = HRTIM_OENR_TF2OEN;
+      break;
+    }
+
+    default:
+    {
+      output_bit = 0UL;
+      break;
+    }
+  }
+
+  if ((hhrtim->Instance->sCommonRegs.OENR & output_bit) != (uint32_t)RESET)
+  {
+    /* Output is enabled: output in RUN state (whatever output disable status is)*/
+    output_state = HRTIM_OUTPUTSTATE_RUN;
+  }
+  else
+  {
+    if ((hhrtim->Instance->sCommonRegs.ODSR & output_bit) != (uint32_t)RESET)
+    {
+      /* Output is disabled: output in FAULT state */
+      output_state = HRTIM_OUTPUTSTATE_FAULT;
+    }
+    else
+    {
+      /* Output is disabled: output in IDLE state */
+      output_state = HRTIM_OUTPUTSTATE_IDLE;
+    }
+  }
+
+  return (output_state);
+}
+
+/**
+  * @brief  Return the level (active or inactive) of the designated output
+  *         when the delayed protection was triggered.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @param  Output Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval Delayed protection status
+  */
+uint32_t HAL_HRTIM_GetDelayedProtectionStatus(const HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx,
+                                              uint32_t Output)
+{
+  uint32_t delayed_protection_status;
+
+  /* Check parameters */
+  assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+  /* Read the delayed protection status */
+  switch (Output)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != (uint32_t)RESET)
+      {
+        /* Output 1 was active when the delayed idle protection was triggered */
+        delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
+      }
+      else
+      {
+        /* Output 1 was inactive when the delayed idle protection was triggered */
+        delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+      }
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      if ((hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != (uint32_t)RESET)
+      {
+        /* Output 2 was active when the delayed idle protection was triggered */
+        delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
+      }
+      else
+      {
+        /* Output 2 was inactive when the delayed idle protection was triggered */
+        delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+      }
+      break;
+    }
+
+    default:
+    {
+      delayed_protection_status = 0xFFFFFFFFUL;
+      break;
+    }
+  }
+
+  return delayed_protection_status;
+}
+
+/**
+  * @brief  Return the actual status (active or inactive) of the burst mode controller
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval Burst mode controller status
+  */
+uint32_t HAL_HRTIM_GetBurstStatus(const HRTIM_HandleTypeDef *hhrtim)
+{
+  uint32_t burst_mode_status;
+
+  /* Read burst mode status */
+  burst_mode_status = (hhrtim->Instance->sCommonRegs.BMCR & HRTIM_BMCR_BMSTAT);
+
+  return burst_mode_status;
+}
+
+/**
+  * @brief  Indicate on which output the signal is currently active (when the
+  *         push pull mode is enabled).
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval Burst mode controller status
+  */
+uint32_t HAL_HRTIM_GetCurrentPushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx)
+{
+  uint32_t current_pushpull_status;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+  /* Read current push pull status */
+  current_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
+
+  return current_pushpull_status;
+}
+
+
+/**
+  * @brief  Indicate on which output the signal was applied, in push-pull mode,
+            balanced fault mode or delayed idle mode, when the protection was triggered.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval Idle Push Pull Status
+  */
+uint32_t HAL_HRTIM_GetIdlePushPullStatus(const HRTIM_HandleTypeDef *hhrtim,
+                                         uint32_t TimerIdx)
+{
+  uint32_t idle_pushpull_status;
+
+  /* Check the parameters */
+  assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+  /* Read current push pull status */
+  idle_pushpull_status = (hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
+
+  return idle_pushpull_status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup HRTIM_Exported_Functions_Group10 Interrupts handling
+  *  @brief  Functions called when HRTIM generates an interrupt
+  *          7 interrupts can be generated by the master timer:
+  *            - Master timer registers update
+  *            - Synchronization event received
+  *            - Master timer repetition event
+  *            - Master Compare 1 to 4 event
+  *          14 interrupts can be generated by each timing unit:
+  *            - Delayed protection triggered
+  *            - Counter reset or roll-over event
+  *            - Output 1 and output 2 reset (transition active to inactive)
+  *            - Output 1 and output 2 set (transition inactive to active)
+  *            - Capture 1 and 2 events
+  *            - Timing unit registers update
+  *            - Repetition event
+  *            - Compare 1 to 4 event
+  *          8 global interrupts are generated for the whole HRTIM:
+  *            - System fault and Fault 1 to 5 (regardless of the timing unit attribution)
+  *            - DLL calibration done
+  *            - Burst mode period completed
+@verbatim
+ ===============================================================================
+                      ##### HRTIM interrupts handling #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to manage the HRTIM
+    interrupts:
+      (+)  HRTIM interrupt handler
+      (+)  Callback function called when Fault1 interrupt occurs
+      (+)  Callback function called when Fault2 interrupt occurs
+      (+)  Callback function called when Fault3 interrupt occurs
+      (+)  Callback function called when Fault4 interrupt occurs
+      (+)  Callback function called when Fault5 interrupt occurs
+      (+)  Callback function called when Fault6 interrupt occurs
+      (+)  Callback function called when system Fault interrupt occurs
+      (+)  Callback function called when DLL ready interrupt occurs
+      (+)  Callback function called when burst mode period interrupt occurs
+      (+)  Callback function called when synchronization input interrupt occurs
+      (+)  Callback function called when a timer register update interrupt occurs
+      (+)  Callback function called when a timer repetition interrupt occurs
+      (+)  Callback function called when a compare 1 match interrupt occurs
+      (+)  Callback function called when a compare 2 match interrupt occurs
+      (+)  Callback function called when a compare 3 match interrupt occurs
+      (+)  Callback function called when a compare 4 match interrupt occurs
+      (+)  Callback function called when a capture 1 interrupt occurs
+      (+)  Callback function called when a capture 2 interrupt occurs
+      (+)  Callback function called when a delayed protection interrupt occurs
+      (+)  Callback function called when a timer counter reset interrupt occurs
+      (+)  Callback function called when a timer output 1 set interrupt occurs
+      (+)  Callback function called when a timer output 1 reset interrupt occurs
+      (+)  Callback function called when a timer output 2 set interrupt occurs
+      (+)  Callback function called when a timer output 2 reset interrupt occurs
+      (+)  Callback function called when a timer output 2 reset interrupt occurs
+      (+)  Callback function called upon completion of a burst DMA transfer
+      (+)  HRTIM callback function registration
+      (+)  HRTIM callback function unregistration
+      (+)  HRTIM Timer x callback function registration
+      (+)  HRTIM Timer x callback function unregistration
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  This function handles HRTIM interrupt request.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be any value of HRTIM_Timer_Index
+  * @retval None
+  */
+void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,
+                          uint32_t TimerIdx)
+{
+  /* HRTIM interrupts handling */
+  if (TimerIdx == HRTIM_TIMERINDEX_COMMON)
+  {
+    HRTIM_HRTIM_ISR(hhrtim);
+  }
+  else if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+  {
+    /* Master related interrupts handling */
+    HRTIM_Master_ISR(hhrtim);
+  }
+  else
+  {
+    /* Timing unit related interrupts handling */
+    HRTIM_Timer_ISR(hhrtim, TimerIdx);
+  }
+
+}
+
+/**
+  * @brief  Callback function invoked when a fault 1 interrupt occurred
+  * @param  hhrtim pointer to HAL HRTIM handle  * @retval None
+  * @retval None
+  */
+__weak void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Fault1Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when a fault 2 interrupt occurred
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+__weak void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Fault2Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when a fault 3 interrupt occurred
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+__weak void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Fault3Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when a fault 4 interrupt occurred
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+__weak void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Fault4Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when a fault 5 interrupt occurred
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+__weak void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Fault5Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when a fault 6 interrupt occurred
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+__weak void HAL_HRTIM_Fault6Callback(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Fault6Callback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when a system fault interrupt occurred
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+__weak void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_SystemFaultCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the DLL calibration is completed
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+__weak void HAL_HRTIM_DLLCalibrationReadyCallback(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_DLLCalibrationCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the end of the burst mode period is reached
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+__weak void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_BurstModeCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when a synchronization input event is received
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+__weak void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_SynchronizationEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when timer registers are updated
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Master_RegistersUpdateCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when timer repetition period has elapsed
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                              uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Master_RepetitionEventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the timer counter matches the value
+  *         programmed in the compare 1 register
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Master_Compare1EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the timer counter matches the value
+  *         programmed in the compare 2 register
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  */
+__weak void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Master_Compare2EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the timer counter matches the value
+  *         programmed in the compare 3 register
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Master_Compare3EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the timer counter matches the value
+  *         programmed in the compare 4 register.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Master_Compare4EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the timer x capture 1 event occurs
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Timer_Capture1EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the timer x capture 2 event occurs
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,
+                                            uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Timer_Capture2EventCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the delayed idle or balanced idle mode is
+  *         entered.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,
+                                                uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Timer_DelayedProtectionCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the timer x counter reset/roll-over
+  *         event occurs.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Timer_CounterResetCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the timer x output 1 is set
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,
+                                         uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Timer_Output1SetCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the timer x output 1 is reset
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Timer_Output1ResetCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the timer x output 2 is set
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,
+                                         uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Timer_Output2SetCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when the timer x output 2 is reset
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,
+                                           uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_Timer_Output2ResetCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when a DMA burst transfer is completed
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_MASTER  for master timer
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+__weak void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,
+                                               uint32_t TimerIdx)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+  UNUSED(TimerIdx);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_BurstDMATransferCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief  Callback function invoked when a DMA error occurs
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+__weak void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hhrtim);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_HRTIM_ErrorCallback could be implemented in the user file
+   */
+}
+
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HRTIM callback function registration
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  CallbackID ID of the HRTIM callback function to register
+  *                   This parameter can be one of the following values:
+  *                   @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_FAULT6CALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_MSPINIT_CB_ID
+  *                   @arg HAL_HRTIM_MSPDEINIT_CB_ID
+  * @param  pCallback Callback function pointer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef        *hhrtim,
+                                             HAL_HRTIM_CallbackIDTypeDef CallbackID,
+                                             pHRTIM_CallbackTypeDef      pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the state */
+    hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hhrtim);
+
+  if (HAL_HRTIM_STATE_READY == hhrtim->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
+        hhrtim->Fault1Callback = pCallback;
+        break;
+
+      case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
+        hhrtim->Fault2Callback = pCallback;
+        break;
+
+      case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
+        hhrtim->Fault3Callback = pCallback;
+        break;
+
+      case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
+        hhrtim->Fault4Callback = pCallback;
+        break;
+
+      case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
+        hhrtim->Fault5Callback = pCallback;
+        break;
+
+      case HAL_HRTIM_FAULT6CALLBACK_CB_ID :
+        hhrtim->Fault6Callback = pCallback;
+        break;
+
+      case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
+        hhrtim->SystemFaultCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
+        hhrtim->DLLCalibrationReadyCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
+        hhrtim->BurstModePeriodCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
+        hhrtim->SynchronizationEventCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_ERRORCALLBACK_CB_ID :
+        hhrtim->ErrorCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_MSPINIT_CB_ID :
+        hhrtim->MspInitCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_MSPDEINIT_CB_ID :
+        hhrtim->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the state */
+        hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HRTIM_MSPINIT_CB_ID :
+        hhrtim->MspInitCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_MSPDEINIT_CB_ID :
+        hhrtim->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the state */
+        hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the state */
+    hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhrtim);
+
+  return status;
+}
+
+/**
+  * @brief  HRTIM callback function un-registration
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  CallbackID ID of the HRTIM callback function to unregister
+  *                   This parameter can be one of the following values:
+  *                   @arg HAL_HRTIM_FAULT1CALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_FAULT2CALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_FAULT3CALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_FAULT4CALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_FAULT5CALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_FAULT6CALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_ERRORCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_MSPINIT_CB_ID
+  *                   @arg HAL_HRTIM_MSPDEINIT_CB_ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *hhrtim,
+                                               HAL_HRTIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hhrtim);
+
+  if (HAL_HRTIM_STATE_READY == hhrtim->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HRTIM_FAULT1CALLBACK_CB_ID :
+        hhrtim->Fault1Callback = HAL_HRTIM_Fault1Callback;
+        break;
+
+      case HAL_HRTIM_FAULT2CALLBACK_CB_ID :
+        hhrtim->Fault2Callback = HAL_HRTIM_Fault2Callback;
+        break;
+
+      case HAL_HRTIM_FAULT3CALLBACK_CB_ID :
+        hhrtim->Fault3Callback = HAL_HRTIM_Fault3Callback;
+        break;
+
+      case HAL_HRTIM_FAULT4CALLBACK_CB_ID :
+        hhrtim->Fault4Callback = HAL_HRTIM_Fault4Callback;
+        break;
+
+      case HAL_HRTIM_FAULT5CALLBACK_CB_ID :
+        hhrtim->Fault5Callback = HAL_HRTIM_Fault5Callback;
+        break;
+
+      case HAL_HRTIM_FAULT6CALLBACK_CB_ID :
+        hhrtim->Fault6Callback = HAL_HRTIM_Fault6Callback;
+        break;
+
+      case HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID :
+        hhrtim->SystemFaultCallback = HAL_HRTIM_SystemFaultCallback;
+        break;
+
+      case HAL_HRTIM_DLLCALBRATIONREADYCALLBACK_CB_ID :
+        hhrtim->DLLCalibrationReadyCallback = HAL_HRTIM_DLLCalibrationReadyCallback;
+        break;
+
+      case HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID :
+        hhrtim->BurstModePeriodCallback = HAL_HRTIM_BurstModePeriodCallback;
+        break;
+
+      case HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID :
+        hhrtim->SynchronizationEventCallback = HAL_HRTIM_SynchronizationEventCallback;
+        break;
+
+      case HAL_HRTIM_ERRORCALLBACK_CB_ID :
+        hhrtim->ErrorCallback = HAL_HRTIM_ErrorCallback;
+        break;
+
+      case HAL_HRTIM_MSPINIT_CB_ID :
+        hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
+        break;
+
+      case HAL_HRTIM_MSPDEINIT_CB_ID :
+        hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
+        break;
+
+      default :
+        /* Update the state */
+        hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_HRTIM_STATE_RESET == hhrtim->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HRTIM_MSPINIT_CB_ID :
+        hhrtim->MspInitCallback = HAL_HRTIM_MspInit;
+        break;
+
+      case HAL_HRTIM_MSPDEINIT_CB_ID :
+        hhrtim->MspDeInitCallback = HAL_HRTIM_MspDeInit;
+        break;
+
+      default :
+        /* Update the state */
+        hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the state */
+    hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhrtim);
+
+  return status;
+}
+
+/**
+  * @brief  HRTIM Timer x callback function registration
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  CallbackID ID of the HRTIM Timer x callback function to register
+  *                   This parameter can be one of the following values:
+  *                   @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
+  * @param  pCallback Callback function pointer
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *hhrtim,
+                                                 HAL_HRTIM_CallbackIDTypeDef CallbackID,
+                                                 pHRTIM_TIMxCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the state */
+    hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hhrtim);
+
+  if (HAL_HRTIM_STATE_READY == hhrtim->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
+        hhrtim->RegistersUpdateCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
+        hhrtim->RepetitionEventCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
+        hhrtim->Compare1EventCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
+        hhrtim->Compare2EventCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
+        hhrtim->Compare3EventCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
+        hhrtim->Compare4EventCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
+        hhrtim->Capture1EventCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
+        hhrtim->Capture2EventCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
+        hhrtim->DelayedProtectionCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
+        hhrtim->CounterResetCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
+        hhrtim->Output1SetCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
+        hhrtim->Output1ResetCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
+        hhrtim->Output2SetCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
+        hhrtim->Output2ResetCallback = pCallback;
+        break;
+
+      case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
+        hhrtim->BurstDMATransferCallback = pCallback;
+        break;
+
+      default :
+        /* Update the state */
+        hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the state */
+    hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhrtim);
+
+  return status;
+}
+
+/**
+  * @brief  HRTIM Timer x callback function un-registration
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  CallbackID ID of the HRTIM callback Timer x function to unregister
+  *                   This parameter can be one of the following values:
+  *                   @arg HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID
+  *                   @arg HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *hhrtim,
+                                                   HAL_HRTIM_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Process locked */
+  __HAL_LOCK(hhrtim);
+
+  if (HAL_HRTIM_STATE_READY == hhrtim->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID :
+        hhrtim->RegistersUpdateCallback = HAL_HRTIM_RegistersUpdateCallback;
+        break;
+
+      case HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID :
+        hhrtim->RepetitionEventCallback = HAL_HRTIM_RepetitionEventCallback;
+        break;
+
+      case HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID :
+        hhrtim->Compare1EventCallback = HAL_HRTIM_Compare1EventCallback;
+        break;
+
+      case HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID :
+        hhrtim->Compare2EventCallback = HAL_HRTIM_Compare2EventCallback;
+        break;
+
+      case HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID :
+        hhrtim->Compare3EventCallback = HAL_HRTIM_Compare3EventCallback;
+        break;
+
+      case HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID :
+        hhrtim->Compare4EventCallback = HAL_HRTIM_Compare4EventCallback;
+        break;
+
+      case HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID :
+        hhrtim->Capture1EventCallback = HAL_HRTIM_Capture1EventCallback;
+        break;
+
+      case HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID :
+        hhrtim->Capture2EventCallback = HAL_HRTIM_Capture2EventCallback;
+        break;
+
+      case HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID :
+        hhrtim->DelayedProtectionCallback = HAL_HRTIM_DelayedProtectionCallback;
+        break;
+
+      case HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID :
+        hhrtim->CounterResetCallback = HAL_HRTIM_CounterResetCallback;
+        break;
+
+      case HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID :
+        hhrtim->Output1SetCallback = HAL_HRTIM_Output1SetCallback;
+        break;
+
+      case HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID :
+        hhrtim->Output1ResetCallback = HAL_HRTIM_Output1ResetCallback;
+        break;
+
+      case HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID :
+        hhrtim->Output2SetCallback = HAL_HRTIM_Output2SetCallback;
+        break;
+
+      case HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID :
+        hhrtim->Output2ResetCallback = HAL_HRTIM_Output2ResetCallback;
+        break;
+
+      case HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID :
+        hhrtim->BurstDMATransferCallback = HAL_HRTIM_BurstDMATransferCallback;
+        break;
+
+      default :
+        /* Update the state */
+        hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the state */
+    hhrtim->State = HAL_HRTIM_STATE_INVALID_CALLBACK;
+
+    /* Return error status */
+    status = HAL_ERROR;
+  }
+
+  /* Release Lock */
+  __HAL_UNLOCK(hhrtim);
+
+  return status;
+}
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup HRTIM_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Configure the master timer time base
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  pTimeBaseCfg pointer to the time base configuration structure
+  * @retval None
+  */
+static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim,
+                                    const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
+{
+  uint32_t hrtim_mcr;
+
+  /* Configure master timer */
+  hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
+
+  /* Set the prescaler ratio */
+  hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
+  hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
+
+  /* Set the operating mode */
+  hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
+  hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
+
+  /* Update the HRTIM registers */
+  hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
+  hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
+  hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
+}
+
+/**
+  * @brief  Configure timing unit (Timer A to Timer F) time base
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  * @param  pTimeBaseCfg pointer to the time base configuration structure
+  * @retval None
+  */
+static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim,
+                                        uint32_t TimerIdx,
+                                        const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
+{
+  uint32_t hrtim_timcr;
+
+  /* Configure master timing unit */
+  hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
+
+  /* Set the prescaler ratio */
+  hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
+  hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
+
+  /* Set the operating mode */
+  hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
+  hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
+
+  /* Update the HRTIM registers */
+  hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
+  hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
+  hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
+}
+
+/**
+  * @brief  Configure the master timer in waveform mode
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  pTimerCfg pointer to the timer configuration data structure
+  * @retval None
+  */
+static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
+                                        const HRTIM_TimerCfgTypeDef *pTimerCfg)
+{
+  uint32_t hrtim_mcr;
+  uint32_t hrtim_bmcr;
+
+  /* Configure master timer */
+  hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
+  hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
+
+  /* Enable/Disable the half mode */
+  hrtim_mcr &= ~(HRTIM_MCR_HALF);
+  hrtim_mcr |= pTimerCfg->HalfModeEnable;
+
+  /* INTLVD bits are set to 00 */
+  hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
+  if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED)
+      || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL))
+  {
+    /* INTLVD bits set to 00 */
+    hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
+    hrtim_mcr |= (HRTIM_MCR_HALF);
+  }
+  else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE)
+  {
+    hrtim_mcr |= (HRTIM_MCR_INTLVD_0);
+    hrtim_mcr &= ~(HRTIM_MCR_INTLVD_1);
+  }
+  else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD)
+  {
+    hrtim_mcr |= (HRTIM_MCR_INTLVD_1);
+    hrtim_mcr &= ~(HRTIM_MCR_INTLVD_0);
+  }
+  else
+  {
+    hrtim_mcr &= ~(HRTIM_MCR_HALF);
+    hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
+  }
+
+  /* Enable/Disable the timer start upon synchronization event reception */
+  hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
+  hrtim_mcr |= pTimerCfg->StartOnSync;
+
+  /* Enable/Disable the timer reset upon synchronization event reception */
+  hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
+  hrtim_mcr |= pTimerCfg->ResetOnSync;
+
+  /* Enable/Disable the DAC synchronization event generation */
+  hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
+  hrtim_mcr |= pTimerCfg->DACSynchro;
+
+  /* Enable/Disable preload mechanism for timer registers */
+  hrtim_mcr &= ~(HRTIM_MCR_PREEN);
+  hrtim_mcr |= pTimerCfg->PreloadEnable;
+
+  /* Master timer registers update handling */
+  hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
+  hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
+
+  /* Enable/Disable registers update on repetition */
+  hrtim_mcr &= ~(HRTIM_MCR_MREPU);
+  hrtim_mcr |= pTimerCfg->RepetitionUpdate;
+
+  /* Set the timer burst mode */
+  hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
+  hrtim_bmcr |= pTimerCfg->BurstMode;
+
+  /* Update the HRTIM registers */
+  hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
+  hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
+}
+
+/**
+  * @brief  Configure timing unit (Timer A to Timer F) in waveform mode
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  * @param  pTimerCfg pointer to the timer configuration data structure
+  * @retval None
+  */
+static void  HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             const HRTIM_TimerCfgTypeDef *pTimerCfg)
+{
+  uint32_t hrtim_timcr;
+  uint32_t hrtim_timfltr;
+  uint32_t hrtim_timoutr;
+  uint32_t hrtim_timrstr;
+  uint32_t hrtim_bmcr;
+
+  /* UPDGAT bitfield must be reset before programming a new value */
+  hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
+
+  /* Configure timing unit (Timer A to Timer F) */
+  hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
+  hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
+  hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
+  hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
+
+  /* Enable/Disable the half mode */
+  hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
+  hrtim_timcr |= pTimerCfg->HalfModeEnable;
+
+  if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED)
+      || (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL))
+  {
+    /* INTLVD bits set to 00 */
+    hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD);
+    hrtim_timcr |= (HRTIM_TIMCR_HALF);
+  }
+  else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE)
+  {
+    hrtim_timcr |= (HRTIM_TIMCR_INTLVD_0);
+    hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_1);
+  }
+  else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD)
+  {
+    hrtim_timcr |= (HRTIM_TIMCR_INTLVD_1);
+    hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_0);
+  }
+  else
+  {
+    hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
+    hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD);
+  }
+
+  /* Enable/Disable the timer start upon synchronization event reception */
+  hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
+  hrtim_timcr |= pTimerCfg->StartOnSync;
+
+  /* Enable/Disable the timer reset upon synchronization event reception */
+  hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
+  hrtim_timcr |= pTimerCfg->ResetOnSync;
+
+  /* Enable/Disable the DAC synchronization event generation */
+  hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
+  hrtim_timcr |= pTimerCfg->DACSynchro;
+
+  /* Enable/Disable preload mechanism for timer registers */
+  hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
+  hrtim_timcr |= pTimerCfg->PreloadEnable;
+
+  /* Timing unit registers update handling */
+  hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
+  hrtim_timcr |= pTimerCfg->UpdateGating;
+
+  /* Enable/Disable registers update on repetition */
+  hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
+  if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
+  {
+    hrtim_timcr |= HRTIM_TIMCR_TREPU;
+  }
+
+  /* Set the push-pull mode */
+  hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
+  hrtim_timcr |= pTimerCfg->PushPull;
+
+  /* Enable/Disable registers update on timer counter reset */
+  hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
+  hrtim_timcr |= pTimerCfg->ResetUpdate;
+
+  /* Set the timer update trigger */
+  hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
+  hrtim_timcr |= pTimerCfg->UpdateTrigger;
+
+  /* Enable/Disable the fault channel at timer level */
+  hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
+  hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
+
+  /* Lock/Unlock fault sources at timer level */
+  hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
+  hrtim_timfltr |= pTimerCfg->FaultLock;
+
+  /* Enable/Disable dead time insertion at timer level */
+  hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
+  hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
+
+  /* Enable/Disable delayed protection at timer level
+     Delayed Idle is available whatever the timer operating mode (regular, push-pull)
+     Balanced Idle is only available in push-pull mode
+  */
+  if (((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
+       && (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
+      || (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
+  {
+    hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT | HRTIM_OUTR_DLYPRTEN);
+    hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
+  }
+
+  /* Set the BIAR mode : one bit for both outputs */
+  hrtim_timoutr &= ~(HRTIM_OUTR_BIAR);
+  hrtim_timoutr |= (pTimerCfg->BalancedIdleAutomaticResume);
+
+  /* Set the timer counter reset trigger */
+  hrtim_timrstr = pTimerCfg->ResetTrigger;
+
+  /* Set the timer burst mode */
+  switch (TimerIdx)
+  {
+    case HRTIM_TIMERINDEX_TIMER_A:
+    {
+      hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
+      hrtim_bmcr |= (pTimerCfg->BurstMode << 1U);
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_B:
+    {
+      hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
+      hrtim_bmcr |= (pTimerCfg->BurstMode << 2U);
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_C:
+    {
+      hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
+      hrtim_bmcr |= (pTimerCfg->BurstMode << 3U);
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_D:
+    {
+      hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
+      hrtim_bmcr |= (pTimerCfg->BurstMode << 4U);
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_E:
+    {
+      hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
+      hrtim_bmcr |= (pTimerCfg->BurstMode << 5U);
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_F:
+    {
+      hrtim_bmcr &= ~(HRTIM_BMCR_TFBM);
+      hrtim_bmcr |= (pTimerCfg->BurstMode << 6U);
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Update the HRTIM registers */
+  hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
+  hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
+  hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
+  hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
+  hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
+}
+
+/**
+  * @brief  Control timing unit (timer A to timer F) in waveform mode
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  * @param  pTimerCtl pointer to the timer configuration data structure
+  * @retval None
+  */
+static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             const HRTIM_TimerCtlTypeDef *pTimerCtl)
+{
+  uint32_t hrtim_timcr2;
+
+  /* Configure timing unit (Timer A to Timer F) */
+  hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2;
+
+  /* Set the UpDown counting Mode */
+  hrtim_timcr2 &= ~(HRTIM_TIMCR2_UDM);
+  hrtim_timcr2 |= (pTimerCtl->UpDownMode << HRTIM_TIMCR2_UDM_Pos) ;
+
+  /* Set the TrigHalf Mode : requires the counter to be disabled */
+  hrtim_timcr2 &= ~(HRTIM_TIMCR2_TRGHLF);
+  hrtim_timcr2 |= pTimerCtl->TrigHalf;
+
+  /* define the compare event operating mode */
+  hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP1);
+  hrtim_timcr2 |= pTimerCtl->GreaterCMP1;
+
+  /* define the compare event operating mode */
+  hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP3);
+  hrtim_timcr2 |= pTimerCtl->GreaterCMP3;
+
+  if (pTimerCtl->DualChannelDacEnable == HRTIM_TIMER_DCDE_ENABLED)
+  {
+    /* Set the DualChannel DAC Reset trigger : requires DCDE enabled */
+    hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDR);
+    hrtim_timcr2 |= pTimerCtl->DualChannelDacReset;
+
+    /* Set the DualChannel DAC Step trigger : requires DCDE enabled */
+    hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDS);
+    hrtim_timcr2 |= pTimerCtl->DualChannelDacStep;
+
+    /* Enable the DualChannel DAC trigger */
+    hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDE);
+    hrtim_timcr2 |= pTimerCtl->DualChannelDacEnable;
+  }
+  /* Update the HRTIM registers */
+  hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2  = hrtim_timcr2;
+
+}
+
+/**
+  * @brief  Configure timing RollOver Mode (Timer A to Timer F)
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  * @param  pRollOverMode: a combination of the timer RollOver Mode configuration
+  * @retval None
+  */
+static void  HRTIM_TimingUnitRollOver_Config(HRTIM_HandleTypeDef *hhrtim,
+                                             uint32_t TimerIdx,
+                                             uint32_t pRollOverMode)
+{
+  uint32_t hrtim_timcr2;
+
+  /* Configure timing unit (Timer A to Timer F) */
+  hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2;
+
+  if ((hrtim_timcr2 & HRTIM_TIMCR2_UDM) != 0U)
+  {
+    /* xxROM bitfield must be reset before programming a new value */
+    hrtim_timcr2 &= ~(HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM |
+                      HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM);
+
+    /* Update the HRTIM TIMxCR2 register */
+    hrtim_timcr2 |= pRollOverMode & (HRTIM_TIMCR2_ROM | HRTIM_TIMCR2_OUTROM |
+                                     HRTIM_TIMCR2_ADROM | HRTIM_TIMCR2_BMROM | HRTIM_TIMCR2_FEROM);
+
+    hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2;
+  }
+}
+
+/**
+  * @brief  Configure a capture unit
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  * @param  CaptureUnit Capture unit identifier
+  * @param  Event Event reference
+  * @retval None
+  */
+static void HRTIM_CaptureUnitConfig(HRTIM_HandleTypeDef *hhrtim,
+                                    uint32_t TimerIdx,
+                                    uint32_t CaptureUnit,
+                                    uint32_t Event)
+{
+  uint32_t CaptureTrigger = 0xFFFFFFFFU;
+
+  switch (Event)
+  {
+    case HRTIM_EVENT_1:
+    {
+      CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
+      break;
+    }
+
+    case HRTIM_EVENT_2:
+    {
+      CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
+      break;
+    }
+
+    case HRTIM_EVENT_3:
+    {
+      CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
+      break;
+    }
+
+    case HRTIM_EVENT_4:
+    {
+      CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
+      break;
+    }
+
+    case HRTIM_EVENT_5:
+    {
+      CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
+      break;
+    }
+
+    case HRTIM_EVENT_6:
+    {
+      CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
+      break;
+    }
+
+    case HRTIM_EVENT_7:
+    {
+      CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
+      break;
+    }
+
+    case HRTIM_EVENT_8:
+    {
+      CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
+      break;
+    }
+
+    case HRTIM_EVENT_9:
+    {
+      CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
+      break;
+    }
+
+    case HRTIM_EVENT_10:
+    {
+      CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  switch (CaptureUnit)
+  {
+    case HRTIM_CAPTUREUNIT_1:
+    {
+      hhrtim->TimerParam[TimerIdx].CaptureTrigger1 = CaptureTrigger;
+      break;
+    }
+
+    case HRTIM_CAPTUREUNIT_2:
+    {
+      hhrtim->TimerParam[TimerIdx].CaptureTrigger2 = CaptureTrigger;
+      break;
+    }
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  Configure the output of a timing unit
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  * @param  Output timing unit output identifier
+  * @param  pOutputCfg pointer to the output configuration data structure
+  * @retval None
+  */
+static void  HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim,
+                                uint32_t TimerIdx,
+                                uint32_t Output,
+                                const HRTIM_OutputCfgTypeDef *pOutputCfg)
+{
+  uint32_t hrtim_outr;
+  uint32_t hrtim_dtr;
+
+  uint32_t shift = 0U;
+
+  hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
+  hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
+
+  switch (Output)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      /* Set the output set/reset crossbar */
+      hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
+      hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      /* Set the output set/reset crossbar */
+      hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
+      hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
+      shift = 16U;
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  /* Clear output config */
+  hrtim_outr &= ~((HRTIM_OUTR_POL1 |
+                   HRTIM_OUTR_IDLM1 |
+                   HRTIM_OUTR_IDLES1 |
+                   HRTIM_OUTR_FAULT1 |
+                   HRTIM_OUTR_CHP1 |
+                   HRTIM_OUTR_DIDL1) << shift);
+
+  /* Set the polarity */
+  hrtim_outr |= (pOutputCfg->Polarity << shift);
+
+  /* Set the IDLE mode */
+  hrtim_outr |= (pOutputCfg->IdleMode << shift);
+
+  /* Set the IDLE state */
+  hrtim_outr |= (pOutputCfg->IdleLevel << shift);
+
+  /* Set the FAULT state */
+  hrtim_outr |= (pOutputCfg->FaultLevel << shift);
+
+  /* Set the chopper mode */
+  hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
+
+  /* Set the burst mode entry mode : deadtime insertion when entering the idle
+     state during a burst mode operation is allowed only under the following
+     conditions:
+     - the outputs is active during the burst mode (IDLES=1U)
+     - positive deadtimes (SDTR/SDTF set to 0U)
+  */
+  if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
+      ((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
+      ((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
+  {
+    hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
+  }
+
+  /* Update HRTIM register */
+  hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
+}
+
+/**
+  * @brief  Configure an external event channel
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  Event Event channel identifier
+  * @param  pEventCfg pointer to the event channel configuration data structure
+  * @retval None
+  */
+static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
+                              uint32_t Event,
+                              const HRTIM_EventCfgTypeDef *pEventCfg)
+{
+  uint32_t hrtim_eecr1;
+  uint32_t hrtim_eecr2;
+  uint32_t hrtim_eecr3;
+
+  /* Configure external event channel */
+  hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
+  hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
+  hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
+
+  switch (Event)
+  {
+    case HRTIM_EVENT_NONE:
+    {
+      /* Update the HRTIM registers */
+      hhrtim->Instance->sCommonRegs.EECR1 = 0U;
+      hhrtim->Instance->sCommonRegs.EECR2 = 0U;
+      hhrtim->Instance->sCommonRegs.EECR3 = 0U;
+      break;
+    }
+
+    case HRTIM_EVENT_1:
+    {
+      hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
+      hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
+      hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
+      hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
+      /* Update the HRTIM registers (all bitfields but EE1FAST bit) */
+      hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+      /* Update the HRTIM registers (EE1FAST bit) */
+      hrtim_eecr1 |= (pEventCfg->FastMode  & HRTIM_EECR1_EE1FAST);
+      hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+      break;
+    }
+
+    case HRTIM_EVENT_2:
+    {
+      hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
+      hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
+      hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
+      hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
+      /* Update the HRTIM registers (all bitfields but EE2FAST bit) */
+      hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+      /* Update the HRTIM registers (EE2FAST bit) */
+      hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
+      hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+      break;
+    }
+
+    case HRTIM_EVENT_3:
+    {
+      hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
+      hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
+      hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
+      hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
+      /* Update the HRTIM registers (all bitfields but EE3FAST bit) */
+      hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+      /* Update the HRTIM registers (EE3FAST bit) */
+      hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
+      hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+      break;
+    }
+
+    case HRTIM_EVENT_4:
+    {
+      hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
+      hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
+      hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
+      hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
+      /* Update the HRTIM registers (all bitfields but EE4FAST bit) */
+      hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+      /* Update the HRTIM registers (EE4FAST bit) */
+      hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
+      hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+      break;
+    }
+
+    case HRTIM_EVENT_5:
+    {
+      hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
+      hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
+      hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
+      hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
+      /* Update the HRTIM registers (all bitfields but EE5FAST bit) */
+      hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+      /* Update the HRTIM registers (EE5FAST bit) */
+      hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
+      hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
+      break;
+    }
+
+    case HRTIM_EVENT_6:
+    {
+      hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
+      hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
+      hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
+      hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
+      hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
+      hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
+      /* Update the HRTIM registers */
+      hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+      hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+      break;
+    }
+
+    case HRTIM_EVENT_7:
+    {
+      hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
+      hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
+      hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
+      hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
+      hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
+      hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
+      /* Update the HRTIM registers */
+      hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+      hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+      break;
+    }
+
+    case HRTIM_EVENT_8:
+    {
+      hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
+      hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
+      hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
+      hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
+      hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
+      hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F);
+      /* Update the HRTIM registers */
+      hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+      hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+      break;
+    }
+
+    case HRTIM_EVENT_9:
+    {
+      hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
+      hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
+      hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
+      hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
+      hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
+      hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
+      /* Update the HRTIM registers */
+      hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+      hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+      break;
+    }
+
+    case HRTIM_EVENT_10:
+    {
+      hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
+      hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
+      hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
+      hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
+      hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
+      hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
+      /* Update the HRTIM registers */
+      hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
+      hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
+      break;
+    }
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  Configure the timer counter reset
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  * @param  Event Event channel identifier
+  * @retval None
+  */
+static void HRTIM_TIM_ResetConfig(HRTIM_HandleTypeDef *hhrtim,
+                                  uint32_t TimerIdx,
+                                  uint32_t Event)
+{
+  switch (Event)
+  {
+    case HRTIM_EVENT_1:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
+      break;
+    }
+
+    case HRTIM_EVENT_2:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
+      break;
+    }
+
+    case HRTIM_EVENT_3:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
+      break;
+    }
+
+    case HRTIM_EVENT_4:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
+      break;
+    }
+
+    case HRTIM_EVENT_5:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
+      break;
+    }
+
+    case HRTIM_EVENT_6:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
+      break;
+    }
+
+    case HRTIM_EVENT_7:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
+      break;
+    }
+
+    case HRTIM_EVENT_8:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
+      break;
+    }
+
+    case HRTIM_EVENT_9:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
+      break;
+    }
+
+    case HRTIM_EVENT_10:
+    {
+      hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
+      break;
+    }
+
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  Return the interrupt to enable or disable according to the
+  *         OC mode.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  * @param  OCChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval Interrupt to enable or disable
+  */
+static uint32_t HRTIM_GetITFromOCMode(const HRTIM_HandleTypeDef *hhrtim,
+                                      uint32_t TimerIdx,
+                                      uint32_t OCChannel)
+{
+  uint32_t hrtim_set;
+  uint32_t hrtim_reset;
+  uint32_t interrupt = 0U;
+
+  switch (OCChannel)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      /* Retrieves actual OC mode and set interrupt accordingly */
+      hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
+      hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
+
+      if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
+          ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
+      {
+        /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
+        interrupt = HRTIM_TIM_IT_CMP1;
+      }
+      else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
+               (hrtim_reset == 0U))
+      {
+        /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
+        interrupt = HRTIM_TIM_IT_SET1;
+      }
+      else if ((hrtim_set == 0U) &&
+               ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
+      {
+        /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
+        interrupt = HRTIM_TIM_IT_RST1;
+      }
+      else
+      {
+        /* nothing to do */
+      }
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      /* Retrieves actual OC mode and set interrupt accordingly */
+      hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
+      hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
+
+      if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
+          ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
+      {
+        /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
+        interrupt = HRTIM_TIM_IT_CMP2;
+      }
+      else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
+               (hrtim_reset == 0U))
+      {
+        /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
+        interrupt = HRTIM_TIM_IT_SET2;
+      }
+      else if ((hrtim_set == 0U) &&
+               ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
+      {
+        /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
+        interrupt = HRTIM_TIM_IT_RST2;
+      }
+      else
+      {
+        /* nothing to do */
+      }
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return interrupt;
+}
+
+/**
+  * @brief  Return the DMA request to enable or disable according to the
+  *         OC mode.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  * @param  OCChannel Timer output
+  *                    This parameter can be one of the following values:
+  *                    @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+  *                    @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+  *                    @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+  *                    @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+  *                    @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+  *                    @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+  *                    @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+  *                    @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+  *                    @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+  *                    @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+  *                    @arg HRTIM_OUTPUT_TF1: Timer F - Output 1
+  *                    @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
+  * @retval DMA request to enable or disable
+  */
+static uint32_t HRTIM_GetDMAFromOCMode(const HRTIM_HandleTypeDef *hhrtim,
+                                       uint32_t TimerIdx,
+                                       uint32_t OCChannel)
+{
+  uint32_t hrtim_set;
+  uint32_t hrtim_reset;
+  uint32_t dma_request = 0U;
+
+  switch (OCChannel)
+  {
+    case HRTIM_OUTPUT_TA1:
+    case HRTIM_OUTPUT_TB1:
+    case HRTIM_OUTPUT_TC1:
+    case HRTIM_OUTPUT_TD1:
+    case HRTIM_OUTPUT_TE1:
+    case HRTIM_OUTPUT_TF1:
+    {
+      /* Retrieves actual OC mode and set dma_request accordingly */
+      hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R;
+      hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R;
+
+      if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
+          ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
+      {
+        /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
+        dma_request = HRTIM_TIM_DMA_CMP1;
+      }
+      else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP1) == HRTIM_OUTPUTSET_TIMCMP1) &&
+               (hrtim_reset == 0U))
+      {
+        /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
+        dma_request = HRTIM_TIM_DMA_SET1;
+      }
+      else if ((hrtim_set == 0U) &&
+               ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP1) == HRTIM_OUTPUTRESET_TIMCMP1))
+      {
+        /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
+        dma_request = HRTIM_TIM_DMA_RST1;
+      }
+      else
+      {
+        /* nothing to do */
+      }
+      break;
+    }
+
+    case HRTIM_OUTPUT_TA2:
+    case HRTIM_OUTPUT_TB2:
+    case HRTIM_OUTPUT_TC2:
+    case HRTIM_OUTPUT_TD2:
+    case HRTIM_OUTPUT_TE2:
+    case HRTIM_OUTPUT_TF2:
+    {
+      /* Retrieves actual OC mode and set dma_request accordingly */
+      hrtim_set = hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R;
+      hrtim_reset = hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R;
+
+      if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
+          ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
+      {
+        /* OC mode: HRTIM_BASICOCMODE_TOGGLE */
+        dma_request = HRTIM_TIM_DMA_CMP2;
+      }
+      else if (((hrtim_set & HRTIM_OUTPUTSET_TIMCMP2) == HRTIM_OUTPUTSET_TIMCMP2) &&
+               (hrtim_reset == 0U))
+      {
+        /* OC mode: HRTIM_BASICOCMODE_ACTIVE */
+        dma_request = HRTIM_TIM_DMA_SET2;
+      }
+      else if ((hrtim_set == 0U) &&
+               ((hrtim_reset & HRTIM_OUTPUTRESET_TIMCMP2) == HRTIM_OUTPUTRESET_TIMCMP2))
+      {
+        /* OC mode: HRTIM_BASICOCMODE_INACTIVE */
+        dma_request = HRTIM_TIM_DMA_RST2;
+      }
+      else
+      {
+        /* nothing to do */
+      }
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return dma_request;
+}
+
+static DMA_HandleTypeDef *HRTIM_GetDMAHandleFromTimerIdx(const HRTIM_HandleTypeDef *hhrtim,
+                                                         uint32_t TimerIdx)
+{
+  DMA_HandleTypeDef *hdma = (DMA_HandleTypeDef *)NULL;
+
+  switch (TimerIdx)
+  {
+    case HRTIM_TIMERINDEX_MASTER:
+    {
+      hdma = hhrtim->hdmaMaster;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_A:
+    {
+      hdma = hhrtim->hdmaTimerA;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_B:
+    {
+      hdma = hhrtim->hdmaTimerB;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_C:
+    {
+      hdma = hhrtim->hdmaTimerC;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_D:
+    {
+      hdma = hhrtim->hdmaTimerD;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_E:
+    {
+      hdma = hhrtim->hdmaTimerE;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_F:
+    {
+      hdma = hhrtim->hdmaTimerF;
+      break;
+    }
+
+    default:
+      break;
+  }
+
+  return hdma;
+}
+
+static uint32_t GetTimerIdxFromDMAHandle(const HRTIM_HandleTypeDef *hhrtim,
+                                         const DMA_HandleTypeDef *hdma)
+{
+  uint32_t timed_idx = 0xFFFFFFFFU;
+
+  if (hdma == hhrtim->hdmaMaster)
+  {
+    timed_idx = HRTIM_TIMERINDEX_MASTER;
+  }
+  else if (hdma == hhrtim->hdmaTimerA)
+  {
+    timed_idx = HRTIM_TIMERINDEX_TIMER_A;
+  }
+  else if (hdma == hhrtim->hdmaTimerB)
+  {
+    timed_idx = HRTIM_TIMERINDEX_TIMER_B;
+  }
+  else if (hdma == hhrtim->hdmaTimerC)
+  {
+    timed_idx = HRTIM_TIMERINDEX_TIMER_C;
+  }
+  else if (hdma == hhrtim->hdmaTimerD)
+  {
+    timed_idx = HRTIM_TIMERINDEX_TIMER_D;
+  }
+  else if (hdma == hhrtim->hdmaTimerE)
+  {
+    timed_idx = HRTIM_TIMERINDEX_TIMER_E;
+  }
+  else if (hdma == hhrtim->hdmaTimerF)
+  {
+    timed_idx = HRTIM_TIMERINDEX_TIMER_F;
+  }
+  else
+  {
+    /* nothing to do */
+  }
+  return timed_idx;
+}
+
+/**
+  * @brief  Force an immediate transfer from the preload to the active
+  *         registers.
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  * @retval None
+  */
+static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim,
+                                       uint32_t TimerIdx)
+{
+  switch (TimerIdx)
+  {
+    case HRTIM_TIMERINDEX_MASTER:
+    {
+      hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_A:
+    {
+      hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_B:
+    {
+      hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_C:
+    {
+      hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_D:
+    {
+      hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_E:
+    {
+      hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
+      break;
+    }
+
+    case HRTIM_TIMERINDEX_TIMER_F:
+    {
+      hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TFSWU;
+      break;
+    }
+
+    default:
+      break;
+  }
+}
+
+
+/**
+  * @brief  HRTIM interrupts service routine
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+static void HRTIM_HRTIM_ISR(HRTIM_HandleTypeDef *hhrtim)
+{
+  uint32_t isrflags = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
+  uint32_t ierits   = READ_REG(hhrtim->Instance->sCommonRegs.IER);
+
+  /* Fault 1 event */
+  if ((uint32_t)(isrflags & HRTIM_FLAG_FLT1) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(ierits & HRTIM_IT_FLT1) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT1);
+
+      /* Invoke Fault 1 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Fault1Callback(hhrtim);
+#else
+      HAL_HRTIM_Fault1Callback(hhrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Fault 2 event */
+  if ((uint32_t)(isrflags & HRTIM_FLAG_FLT2) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(ierits & HRTIM_IT_FLT2) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT2);
+
+      /* Invoke Fault 2 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Fault2Callback(hhrtim);
+#else
+      HAL_HRTIM_Fault2Callback(hhrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Fault 3 event */
+  if ((uint32_t)(isrflags & HRTIM_FLAG_FLT3) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(ierits & HRTIM_IT_FLT3) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT3);
+
+      /* Invoke Fault 3 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Fault3Callback(hhrtim);
+#else
+      HAL_HRTIM_Fault3Callback(hhrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Fault 4 event */
+  if ((uint32_t)(isrflags & HRTIM_FLAG_FLT4) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(ierits & HRTIM_IT_FLT4) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT4);
+
+      /* Invoke Fault 4 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Fault4Callback(hhrtim);
+#else
+      HAL_HRTIM_Fault4Callback(hhrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Fault 5 event */
+  if ((uint32_t)(isrflags & HRTIM_FLAG_FLT5) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(ierits & HRTIM_IT_FLT5) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT5);
+
+      /* Invoke Fault 5 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Fault5Callback(hhrtim);
+#else
+      HAL_HRTIM_Fault5Callback(hhrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Fault 6 event */
+  if ((uint32_t)(isrflags & HRTIM_FLAG_FLT6) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(ierits & HRTIM_IT_FLT6) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_FLT6);
+
+      /* Invoke Fault 6 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Fault6Callback(hhrtim);
+#else
+      HAL_HRTIM_Fault6Callback(hhrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* System fault event */
+  if ((uint32_t)(isrflags & HRTIM_FLAG_SYSFLT) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(ierits & HRTIM_IT_SYSFLT) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_SYSFLT);
+
+      /* Invoke System fault event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->SystemFaultCallback(hhrtim);
+#else
+      HAL_HRTIM_SystemFaultCallback(hhrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  Master timer interrupts service routine
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @retval None
+  */
+static void HRTIM_Master_ISR(HRTIM_HandleTypeDef *hhrtim)
+{
+  uint32_t isrflags  = READ_REG(hhrtim->Instance->sCommonRegs.ISR);
+  uint32_t ierits    = READ_REG(hhrtim->Instance->sCommonRegs.IER);
+  uint32_t misrflags = READ_REG(hhrtim->Instance->sMasterRegs.MISR);
+  uint32_t mdierits  = READ_REG(hhrtim->Instance->sMasterRegs.MDIER);
+
+  /* DLL calibration ready event */
+  if ((uint32_t)(isrflags & HRTIM_FLAG_DLLRDY) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(ierits & HRTIM_IT_DLLRDY) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_DLLRDY);
+
+      /* Set HRTIM State */
+      hhrtim->State = HAL_HRTIM_STATE_READY;
+
+      /* Process unlocked */
+      __HAL_UNLOCK(hhrtim);
+
+      /* Invoke System fault event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->DLLCalibrationReadyCallback(hhrtim);
+#else
+      HAL_HRTIM_DLLCalibrationReadyCallback(hhrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Burst mode period event */
+  if ((uint32_t)(isrflags & HRTIM_FLAG_BMPER) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(ierits & HRTIM_IT_BMPER) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_CLEAR_IT(hhrtim, HRTIM_IT_BMPER);
+
+      /* Invoke Burst mode period event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->BurstModePeriodCallback(hhrtim);
+#else
+      HAL_HRTIM_BurstModePeriodCallback(hhrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Master timer compare 1 event */
+  if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP1) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP1) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP1);
+
+      /* Invoke compare 1 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+#else
+      HAL_HRTIM_Compare1EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Master timer compare 2 event */
+  if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP2) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP2) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP2);
+
+      /* Invoke compare 2 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+#else
+      HAL_HRTIM_Compare2EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Master timer compare 3 event */
+  if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP3) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP3) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP3);
+
+      /* Invoke compare 3 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+#else
+      HAL_HRTIM_Compare3EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Master timer compare 4 event */
+  if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MCMP4) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MCMP4) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MCMP4);
+
+      /* Invoke compare 4 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+#else
+      HAL_HRTIM_Compare4EventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Master timer repetition event */
+  if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MREP) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MREP) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MREP);
+
+      /* Invoke repetition event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+#else
+      HAL_HRTIM_RepetitionEventCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Synchronization input event */
+  if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_SYNC) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(mdierits & HRTIM_MASTER_IT_SYNC) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_SYNC);
+
+      /* Invoke synchronization event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->SynchronizationEventCallback(hhrtim);
+#else
+      HAL_HRTIM_SynchronizationEventCallback(hhrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Master timer registers update event */
+  if ((uint32_t)(misrflags & HRTIM_MASTER_FLAG_MUPD) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(mdierits & HRTIM_MASTER_IT_MUPD) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_MASTER_CLEAR_IT(hhrtim, HRTIM_MASTER_IT_MUPD);
+
+      /* Invoke registers update event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+#else
+      HAL_HRTIM_RegistersUpdateCallback(hhrtim, HRTIM_TIMERINDEX_MASTER);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  Timer interrupts service routine
+  * @param  hhrtim pointer to HAL HRTIM handle
+  * @param  TimerIdx Timer index
+  *                   This parameter can be one of the following values:
+  *                   @arg HRTIM_TIMERINDEX_TIMER_A for timer A
+  *                   @arg HRTIM_TIMERINDEX_TIMER_B for timer B
+  *                   @arg HRTIM_TIMERINDEX_TIMER_C for timer C
+  *                   @arg HRTIM_TIMERINDEX_TIMER_D for timer D
+  *                   @arg HRTIM_TIMERINDEX_TIMER_E for timer E
+  *                   @arg HRTIM_TIMERINDEX_TIMER_F for timer F
+  * @retval None
+  */
+static void HRTIM_Timer_ISR(HRTIM_HandleTypeDef *hhrtim,
+                            uint32_t TimerIdx)
+{
+  uint32_t tisrflags = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxISR);
+  uint32_t tdierits  = READ_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxDIER);
+
+  /* Timer compare 1 event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP1) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP1) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP1);
+
+      /* Invoke compare 1 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Compare1EventCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_Compare1EventCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timer compare 2 event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP2) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP2) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP2);
+
+      /* Invoke compare 2 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Compare2EventCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_Compare2EventCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timer compare 3 event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP3) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP3) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP3);
+
+      /* Invoke compare 3 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Compare3EventCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_Compare3EventCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timer compare 4 event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CMP4) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_CMP4) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CMP4);
+
+      /* Invoke compare 4 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Compare4EventCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_Compare4EventCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timer repetition event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_REP) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_REP) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_REP);
+
+      /* Invoke repetition event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->RepetitionEventCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_RepetitionEventCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timer registers update event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_UPD) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_UPD) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_UPD);
+
+      /* Invoke registers update event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->RegistersUpdateCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_RegistersUpdateCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timer capture 1 event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT1) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT1) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT1);
+
+      /* Invoke capture 1 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Capture1EventCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_Capture1EventCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timer capture 2 event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_CPT2) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_CPT2) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_CPT2);
+
+      /* Invoke capture 2 event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Capture2EventCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_Capture2EventCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timer output 1 set event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET1) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET1) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET1);
+
+      /* Invoke output 1 set event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Output1SetCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_Output1SetCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timer output 1 reset event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST1) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST1) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST1);
+
+      /* Invoke output 1 reset event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Output1ResetCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_Output1ResetCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timer output 2 set event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_SET2) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_SET2) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_SET2);
+
+      /* Invoke output 2 set event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Output2SetCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_Output2SetCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timer output 2 reset event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST2) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST2) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST2);
+
+      /* Invoke output 2 reset event callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->Output2ResetCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_Output2ResetCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Timer reset event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_RST) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_RST) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_RST);
+
+      /* Invoke timer reset callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->CounterResetCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_CounterResetCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+
+  /* Delayed protection event */
+  if ((uint32_t)(tisrflags & HRTIM_TIM_FLAG_DLYPRT) != (uint32_t)RESET)
+  {
+    if ((uint32_t)(tdierits & HRTIM_TIM_IT_DLYPRT) != (uint32_t)RESET)
+    {
+      __HAL_HRTIM_TIMER_CLEAR_IT(hhrtim, TimerIdx, HRTIM_TIM_IT_DLYPRT);
+
+      /* Invoke delayed protection callback */
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+      hhrtim->DelayedProtectionCallback(hhrtim, TimerIdx);
+#else
+      HAL_HRTIM_DelayedProtectionCallback(hhrtim, TimerIdx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+    }
+  }
+}
+
+/**
+  * @brief  DMA callback invoked upon master timer related DMA request completion
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void HRTIM_DMAMasterCplt(DMA_HandleTypeDef *hdma)
+{
+  HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP1) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+#else
+    HAL_HRTIM_Compare1EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP2) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+#else
+    HAL_HRTIM_Compare2EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP3) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+#else
+    HAL_HRTIM_Compare3EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MCMP4) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+#else
+    HAL_HRTIM_Compare4EventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_SYNC) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->SynchronizationEventCallback(hrtim);
+#else
+    HAL_HRTIM_SynchronizationEventCallback(hrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MUPD) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+#else
+    HAL_HRTIM_RegistersUpdateCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sMasterRegs.MDIER & HRTIM_MASTER_DMA_MREP) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+#else
+    HAL_HRTIM_RepetitionEventCallback(hrtim, HRTIM_TIMERINDEX_MASTER);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* nothing to do */
+  }
+}
+
+/**
+  * @brief  DMA callback invoked upon timer A..F related DMA request completion
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void HRTIM_DMATimerxCplt(DMA_HandleTypeDef *hdma)
+{
+  uint8_t timer_idx;
+
+  HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  timer_idx = (uint8_t)GetTimerIdxFromDMAHandle(hrtim, hdma);
+
+  if (!IS_HRTIM_TIMING_UNIT(timer_idx)) {return;}
+
+  if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP1) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Compare1EventCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_Compare1EventCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP2) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Compare2EventCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_Compare2EventCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP3) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Compare3EventCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_Compare3EventCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CMP4) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Compare4EventCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_Compare4EventCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_UPD) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->RegistersUpdateCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_RegistersUpdateCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT1) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Capture1EventCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_Capture1EventCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_CPT2) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Capture2EventCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_Capture2EventCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET1) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Output1SetCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_Output1SetCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST1) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Output1ResetCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_Output1ResetCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_SET2) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Output2SetCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_Output2SetCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST2) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->Output2ResetCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_Output2ResetCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_RST) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->CounterResetCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_CounterResetCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_DLYPRT) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->DelayedProtectionCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_DelayedProtectionCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else if ((hrtim->Instance->sTimerxRegs[timer_idx].TIMxDIER & HRTIM_TIM_DMA_REP) != (uint32_t)RESET)
+  {
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+    hrtim->RepetitionEventCallback(hrtim, timer_idx);
+#else
+    HAL_HRTIM_RepetitionEventCallback(hrtim, timer_idx);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* nothing to do */
+  }
+}
+
+/**
+  * @brief  DMA error callback
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void HRTIM_DMAError(DMA_HandleTypeDef *hdma)
+{
+  HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+  hrtim->ErrorCallback(hrtim);
+#else
+  HAL_HRTIM_ErrorCallback(hrtim);
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA callback invoked upon burst DMA transfer completion
+  * @param  hdma pointer to DMA handle.
+  * @retval None
+  */
+static void HRTIM_BurstDMACplt(DMA_HandleTypeDef *hdma)
+{
+  HRTIM_HandleTypeDef *hrtim = (HRTIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
+  hrtim->BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
+#else
+  HAL_HRTIM_BurstDMATransferCallback(hrtim, GetTimerIdxFromDMAHandle(hrtim, hdma));
+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HRTIM1 */
+
+#endif /* HAL_HRTIM_MODULE_ENABLED */
+
+/**
+  * @}
+  */
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c
new file mode 100644
index 0000000..edb4900
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart.c
@@ -0,0 +1,4695 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_uart.c
+  * @author  MCD Application Team
+  * @brief   UART HAL module driver.
+  *          This file provides firmware functions to manage the following
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + IO operation functions
+  *           + Peripheral Control functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+ ===============================================================================
+                        ##### How to use this driver #####
+ ===============================================================================
+  [..]
+    The UART HAL driver can be used as follows:
+
+    (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart).
+    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
+        (++) Enable the USARTx interface clock.
+        (++) UART pins configuration:
+            (+++) Enable the clock for the UART GPIOs.
+            (+++) Configure these UART pins as alternate function pull-up.
+        (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
+             and HAL_UART_Receive_IT() APIs):
+            (+++) Configure the USARTx interrupt priority.
+            (+++) Enable the NVIC USART IRQ handle.
+        (++) UART interrupts handling:
+              -@@-  The specific UART interrupts (Transmission complete interrupt,
+                RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts)
+                are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT()
+                inside the transmit and receive processes.
+        (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
+             and HAL_UART_Receive_DMA() APIs):
+            (+++) Declare a DMA handle structure for the Tx/Rx channel.
+            (+++) Enable the DMAx interface clock.
+            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
+            (+++) Configure the DMA Tx/Rx channel.
+            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
+            (+++) Configure the priority and enable the NVIC for the transfer complete
+                  interrupt on the DMA Tx/Rx channel.
+
+    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware
+        flow control and Mode (Receiver/Transmitter) in the huart handle Init structure.
+
+    (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...)
+        in the huart handle AdvancedInit structure.
+
+    (#) For the UART asynchronous mode, initialize the UART registers by calling
+        the HAL_UART_Init() API.
+
+    (#) For the UART Half duplex mode, initialize the UART registers by calling
+        the HAL_HalfDuplex_Init() API.
+
+    (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers
+        by calling the HAL_LIN_Init() API.
+
+    (#) For the UART Multiprocessor mode, initialize the UART registers
+        by calling the HAL_MultiProcessor_Init() API.
+
+    (#) For the UART RS485 Driver Enabled mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    [..]
+    (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(),
+        also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by
+        calling the customized HAL_UART_MspInit() API.
+
+    ##### Callback registration #####
+    ==================================
+
+    [..]
+    The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1
+    allows the user to configure dynamically the driver callbacks.
+
+    [..]
+    Use Function HAL_UART_RegisterCallback() to register a user callback.
+    Function HAL_UART_RegisterCallback() allows to register following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) WakeupCallback            : Wakeup Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+    This function takes as parameters the HAL peripheral handle, the Callback ID
+    and a pointer to the user callback function.
+
+    [..]
+    Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
+    weak function.
+    HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
+    and the Callback ID.
+    This function allows to reset following callbacks:
+    (+) TxHalfCpltCallback        : Tx Half Complete Callback.
+    (+) TxCpltCallback            : Tx Complete Callback.
+    (+) RxHalfCpltCallback        : Rx Half Complete Callback.
+    (+) RxCpltCallback            : Rx Complete Callback.
+    (+) ErrorCallback             : Error Callback.
+    (+) AbortCpltCallback         : Abort Complete Callback.
+    (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback.
+    (+) AbortReceiveCpltCallback  : Abort Receive Complete Callback.
+    (+) WakeupCallback            : Wakeup Callback.
+    (+) RxFifoFullCallback        : Rx Fifo Full Callback.
+    (+) TxFifoEmptyCallback       : Tx Fifo Empty Callback.
+    (+) MspInitCallback           : UART MspInit.
+    (+) MspDeInitCallback         : UART MspDeInit.
+
+    [..]
+    For specific callback RxEventCallback, use dedicated registration/reset functions:
+    respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback().
+
+    [..]
+    By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
+    all callbacks are set to the corresponding weak functions:
+    examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
+    Exception done for MspInit and MspDeInit functions that are respectively
+    reset to the legacy weak functions in the HAL_UART_Init()
+    and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
+    If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
+    keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
+
+    [..]
+    Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only.
+    Exception done MspInit/MspDeInit that can be registered/unregistered
+    in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user)
+    MspInit/DeInit callbacks can be used during the Init/DeInit.
+    In that case first register the MspInit/MspDeInit user callbacks
+    using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit()
+    or HAL_UART_Init() function.
+
+    [..]
+    When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
+    not defined, the callback registration feature is not available
+    and weak callbacks are used.
+
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UART UART
+  * @brief HAL UART module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UART_Private_Constants UART Private Constants
+  * @{
+  */
+#define USART_CR1_FIELDS  ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \
+                                      USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */
+
+#define USART_CR3_FIELDS  ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \
+                                      USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */
+
+#define LPUART_BRR_MIN  0x00000300U  /* LPUART BRR minimum authorized value */
+#define LPUART_BRR_MAX  0x000FFFFFU  /* LPUART BRR maximum authorized value */
+
+#define UART_BRR_MIN    0x10U        /* UART BRR minimum authorized value */
+#define UART_BRR_MAX    0x0000FFFFU  /* UART BRR maximum authorized value */
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup UART_Private_Functions
+  * @{
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
+static void UART_DMAError(DMA_HandleTypeDef *hdma);
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma);
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma);
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart);
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart);
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Private variables ---------------------------------------------------------*/
+/** @addtogroup UART_Private_variables
+  * @{
+  */
+const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
+/**
+  * @}
+  */
+
+/* Exported Constants --------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UART_Exported_Functions UART Exported Functions
+  * @{
+  */
+
+/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions
+  *  @brief    Initialization and Configuration functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API
+    follow respectively the UART asynchronous, UART Half duplex, UART LIN mode
+    and UART multiprocessor mode configuration procedures (details for the procedures
+    are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible UART formats are listed in the
+  following table.
+
+  Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
+  {
+    /* Check the parameters */
+    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
+  }
+  else
+  {
+    /* Check the parameters */
+    assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In asynchronous mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Initialize the half-duplex mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check UART instance */
+  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In half-duplex mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the LIN mode according to the specified
+  *        parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart             UART handle.
+  * @param BreakDetectLength Specifies the LIN break detection length.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection
+  *          @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the LIN UART instance */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+  /* Check the Break detection length parameter */
+  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
+
+  /* LIN mode limited to 16-bit oversampling only */
+  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    return HAL_ERROR;
+  }
+  /* LIN mode limited to 8-bit data length */
+  if (huart->Init.WordLength != UART_WORDLENGTH_8B)
+  {
+    return HAL_ERROR;
+  }
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In LIN mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN and IREN bits in the USART_CR3 register.*/
+  CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN);
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN));
+
+  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+  SET_BIT(huart->Instance->CR2, USART_CR2_LINEN);
+
+  /* Set the USART LIN Break detection length. */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief Initialize the multiprocessor mode according to the specified
+  *        parameters in the UART_InitTypeDef and initialize the associated handle.
+  * @param huart        UART handle.
+  * @param Address      UART node address (4-, 6-, 7- or 8-bit long).
+  * @param WakeUpMethod Specifies the UART wakeup method.
+  *        This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection
+  *          @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark
+  * @note  If the user resorts to idle line detection wake up, the Address parameter
+  *        is useless and ignored by the initialization function.
+  * @note  If the user resorts to address mark wake up, the address length detection
+  *        is configured by default to 4 bits only. For the UART to be able to
+  *        manage 6-, 7- or 8-bit long addresses detection, the API
+  *        HAL_MultiProcessorEx_AddressLength_Set() must be called after
+  *        HAL_MultiProcessor_Init().
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the wake up method parameter */
+  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* In multiprocessor mode, the following bits must be kept cleared:
+  - LINEN and CLKEN bits in the USART_CR2 register,
+  - SCEN, HDSEL and IREN  bits in the USART_CR3 register. */
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+
+  if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK)
+  {
+    /* If address mark wake up method is chosen, set the USART address node */
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS));
+  }
+
+  /* Set the wake up method by setting the WAKE bit in the CR1 register */
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
+
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+
+/**
+  * @brief DeInitialize the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  __HAL_UART_DISABLE(huart);
+
+  huart->Instance->CR1 = 0x0U;
+  huart->Instance->CR2 = 0x0U;
+  huart->Instance->CR3 = 0x0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  if (huart->MspDeInitCallback == NULL)
+  {
+    huart->MspDeInitCallback = HAL_UART_MspDeInit;
+  }
+  /* DeInit the low level hardware */
+  huart->MspDeInitCallback(huart);
+#else
+  /* DeInit the low level hardware */
+  HAL_UART_MspDeInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->gState = HAL_UART_STATE_RESET;
+  huart->RxState = HAL_UART_STATE_RESET;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Initialize the UART MSP.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspInit can be implemented in the user file
+   */
+}
+
+/**
+  * @brief DeInitialize the UART MSP.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_MspDeInit can be implemented in the user file
+   */
+}
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User UART Callback
+  *         To be used to override the weak predefined callback
+  * @note   The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+  *         HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
+  *         callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,
+                                            pUART_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = pCallback;
+        break;
+
+      case HAL_UART_WAKEUP_CB_ID :
+        huart->WakeupCallback = pCallback;
+        break;
+
+      case HAL_UART_RX_FIFO_FULL_CB_ID :
+        huart->RxFifoFullCallback = pCallback;
+        break;
+
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+        huart->TxFifoEmptyCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = pCallback;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister an UART Callback
+  *         UART callaback is redirected to the weak predefined callback
+  * @note   The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
+  *         HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register
+  *         callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
+  * @param  huart uart handle
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *           @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID
+  *           @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID
+  *           @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID
+  *           @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID
+  *           @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID
+  *           @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID
+  *           @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID
+  *           @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID
+  *           @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID
+  *           @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID
+  *           @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID
+  *           @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (HAL_UART_STATE_READY == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_TX_HALFCOMPLETE_CB_ID :
+        huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback;               /* Legacy weak  TxHalfCpltCallback    */
+        break;
+
+      case HAL_UART_TX_COMPLETE_CB_ID :
+        huart->TxCpltCallback = HAL_UART_TxCpltCallback;                       /* Legacy weak TxCpltCallback         */
+        break;
+
+      case HAL_UART_RX_HALFCOMPLETE_CB_ID :
+        huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback;               /* Legacy weak RxHalfCpltCallback     */
+        break;
+
+      case HAL_UART_RX_COMPLETE_CB_ID :
+        huart->RxCpltCallback = HAL_UART_RxCpltCallback;                       /* Legacy weak RxCpltCallback         */
+        break;
+
+      case HAL_UART_ERROR_CB_ID :
+        huart->ErrorCallback = HAL_UART_ErrorCallback;                         /* Legacy weak ErrorCallback          */
+        break;
+
+      case HAL_UART_ABORT_COMPLETE_CB_ID :
+        huart->AbortCpltCallback = HAL_UART_AbortCpltCallback;                 /* Legacy weak AbortCpltCallback      */
+        break;
+
+      case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID :
+        huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak
+                                                                                  AbortTransmitCpltCallback          */
+        break;
+
+      case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID :
+        huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback;   /* Legacy weak
+                                                                                  AbortReceiveCpltCallback           */
+        break;
+
+      case HAL_UART_WAKEUP_CB_ID :
+        huart->WakeupCallback = HAL_UARTEx_WakeupCallback;                     /* Legacy weak WakeupCallback         */
+        break;
+
+      case HAL_UART_RX_FIFO_FULL_CB_ID :
+        huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback;             /* Legacy weak RxFifoFullCallback     */
+        break;
+
+      case HAL_UART_TX_FIFO_EMPTY_CB_ID :
+        huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback;           /* Legacy weak TxFifoEmptyCallback    */
+        break;
+
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;                             /* Legacy weak MspInitCallback        */
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;                         /* Legacy weak MspDeInitCallback      */
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_UART_STATE_RESET == huart->gState)
+  {
+    switch (CallbackID)
+    {
+      case HAL_UART_MSPINIT_CB_ID :
+        huart->MspInitCallback = HAL_UART_MspInit;
+        break;
+
+      case HAL_UART_MSPDEINIT_CB_ID :
+        huart->MspDeInitCallback = HAL_UART_MspDeInit;
+        break;
+
+      default :
+        huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Register a User UART Rx Event Callback
+  *         To be used instead of the weak predefined callback
+  * @param  huart     Uart handle
+  * @param  pCallback Pointer to the Rx Event Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    huart->RxEventCallback = pCallback;
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  UnRegister the UART Rx Event Callback
+  *         UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback
+  * @param  huart     Uart handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback  */
+  }
+  else
+  {
+    huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK;
+
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group2 IO operation functions
+  * @brief UART Transmit/Receive functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of functions allowing to manage the UART asynchronous
+    and Half duplex data transfers.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The communication is performed in polling mode.
+           The HAL status of all data processing is returned by the same function
+           after finishing transfer.
+       (+) Non-Blocking mode: The communication is performed using Interrupts
+           or DMA, These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when
+           using DMA mode.
+           The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks
+           will be executed respectively at the end of the transmit or Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected
+
+    (#) Blocking mode API's are :
+        (+) HAL_UART_Transmit()
+        (+) HAL_UART_Receive()
+
+    (#) Non-Blocking mode API's with Interrupt are :
+        (+) HAL_UART_Transmit_IT()
+        (+) HAL_UART_Receive_IT()
+        (+) HAL_UART_IRQHandler()
+
+    (#) Non-Blocking mode API's with DMA are :
+        (+) HAL_UART_Transmit_DMA()
+        (+) HAL_UART_Receive_DMA()
+        (+) HAL_UART_DMAPause()
+        (+) HAL_UART_DMAResume()
+        (+) HAL_UART_DMAStop()
+
+    (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode:
+        (+) HAL_UART_TxHalfCpltCallback()
+        (+) HAL_UART_TxCpltCallback()
+        (+) HAL_UART_RxHalfCpltCallback()
+        (+) HAL_UART_RxCpltCallback()
+        (+) HAL_UART_ErrorCallback()
+
+    (#) Non-Blocking mode transfers could be aborted using Abort API's :
+        (+) HAL_UART_Abort()
+        (+) HAL_UART_AbortTransmit()
+        (+) HAL_UART_AbortReceive()
+        (+) HAL_UART_Abort_IT()
+        (+) HAL_UART_AbortTransmit_IT()
+        (+) HAL_UART_AbortReceive_IT()
+
+    (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided:
+        (+) HAL_UART_AbortCpltCallback()
+        (+) HAL_UART_AbortTransmitCpltCallback()
+        (+) HAL_UART_AbortReceiveCpltCallback()
+
+    (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced
+        reception services:
+        (+) HAL_UARTEx_RxEventCallback()
+
+    (#) In Non-Blocking mode transfers, possible errors are split into 2 categories.
+        Errors are handled as follows :
+       (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is
+           to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error
+           in Interrupt mode reception .
+           Received character is then retrieved and stored in Rx buffer, Error code is set to allow user
+           to identify error type, and HAL_UART_ErrorCallback() user callback is executed.
+           Transfer is kept ongoing on UART side.
+           If user wants to abort it, Abort services should be called by user.
+       (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted.
+           This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode.
+           Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback()
+           user callback is executed.
+
+    -@- In the Half duplex communication, it is forbidden to run the transmit
+        and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Send an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @note When FIFO mode is enabled, writing a data in the TDR register adds one
+  *       data to the TXFIFO. Write operations to the TDR register are performed
+  *       when TXFNF flag is set. From hardware perspective, TXFNF flag and
+  *       TXE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (u8 or u16 data elements).
+  * @param Size    Amount of data elements (u8 or u16) to be sent.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  const uint8_t  *pdata8bits;
+  const uint16_t *pdata16bits;
+  uint32_t tickstart;
+
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+
+    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (const uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    while (huart->TxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+
+        huart->gState = HAL_UART_STATE_READY;
+
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+        pdata16bits++;
+      }
+      else
+      {
+        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+        pdata8bits++;
+      }
+      huart->TxXferCount--;
+    }
+
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+    {
+      huart->gState = HAL_UART_STATE_READY;
+
+      return HAL_TIMEOUT;
+    }
+
+    /* At end of Tx process, restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+  *       is not empty. Read operations from the RDR register are performed when
+  *       RXFNE flag is set. From hardware perspective, RXFNE flag and
+  *       RXNE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (u8 or u16 data elements).
+  * @param Size    Amount of data elements (u8 or u16) to be received.
+  * @param Timeout Timeout duration.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint16_t uhMask;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+    uhMask = huart->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* as long as data have to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK)
+      {
+        huart->RxState = HAL_UART_STATE_READY;
+
+        return HAL_TIMEOUT;
+      }
+      if (pdata8bits == NULL)
+      {
+        *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+        pdata16bits++;
+      }
+      else
+      {
+        *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+        pdata8bits++;
+      }
+      huart->RxXferCount--;
+    }
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in interrupt mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    huart->pTxBuffPtr  = pData;
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+    huart->TxISR       = NULL;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    /* Configure Tx interrupt processing */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->TxISR = UART_TxISR_16BIT_FIFOEN;
+      }
+      else
+      {
+        huart->TxISR = UART_TxISR_8BIT_FIFOEN;
+      }
+
+      /* Enable the TX FIFO threshold interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+    }
+    else
+    {
+      /* Set the Tx ISR function pointer according to the data word length */
+      if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+      {
+        huart->TxISR = UART_TxISR_16BIT;
+      }
+      else
+      {
+        huart->TxISR = UART_TxISR_8BIT;
+      }
+
+      /* Enable the Transmit Data Register Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+    }
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    if (!(IS_LPUART_INSTANCE(huart->Instance)))
+    {
+      /* Check that USART RTOEN bit is set */
+      if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+      {
+        /* Enable the UART Receiver Timeout Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+      }
+    }
+
+    return (UART_Start_Receive_IT(huart, pData, Size));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Send an amount of data in DMA mode.
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the sent data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 provided through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be sent.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Tx process is not already ongoing */
+  if (huart->gState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    huart->pTxBuffPtr  = pData;
+    huart->TxXferSize  = Size;
+    huart->TxXferCount = Size;
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA transfer complete callback */
+      huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
+
+      /* Set the UART DMA Half transfer complete callback */
+      huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
+
+      /* Set the DMA error callback */
+      huart->hdmatx->XferErrorCallback = UART_DMAError;
+
+      /* Set the DMA abort callback */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      /* Enable the UART transmit DMA channel */
+      if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK)
+      {
+        /* Set error code to DMA */
+        huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+        /* Restore huart->gState to ready */
+        huart->gState = HAL_UART_STATE_READY;
+
+        return HAL_ERROR;
+      }
+    }
+    /* Clear the TC flag in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF);
+
+    /* Enable the DMA transfer for transmit request by setting the DMAT bit
+    in the UART CR3 register */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode.
+  * @note   When the UART parity is enabled (PCE = 1), the received data contain
+  *         the parity bit (MSB position).
+  * @note   When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *         the received data is handled as a set of u16. In this case, Size must indicate the number
+  *         of u16 available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (u8 or u16 data elements).
+  * @param Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Reception type to Standard reception */
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    if (!(IS_LPUART_INSTANCE(huart->Instance)))
+    {
+      /* Check that USART RTOEN bit is set */
+      if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+      {
+        /* Enable the UART Receiver Timeout Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+      }
+    }
+
+    return (UART_Start_Receive_DMA(huart, pData, Size));
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Pause the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
+{
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    /* Disable the UART DMA Tx request */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the UART DMA Rx request */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Resume the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
+{
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    /* Enable the UART DMA Tx request */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+  }
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    /* Clear the Overrun flag before resuming the Rx transfer */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+    /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Enable the UART DMA Rx request */
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Stop the DMA Transfer.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
+{
+  /* The Lock is not implemented on this API to allow the user application
+     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() /
+     HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback:
+     indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete
+     interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of
+     the stream and the corresponding call back is executed. */
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel */
+    if (huart->hdmatx != NULL)
+    {
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel */
+    if (huart->hdmarx != NULL)
+    {
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    UART_EndRxTransfer(huart);
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart)
+{
+  /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE |
+                                          USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx and Rx transfer counters */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart)
+{
+  /* Disable TCIE, TXEIE and TXFTIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Tx transfer counter */
+  huart->TxXferCount = 0U;
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (blocking mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  * @note   This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart)
+{
+  /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback to Null.
+         No call back execution at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = NULL;
+
+      if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
+      {
+        if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
+        {
+          /* Set error code to DMA */
+          huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+
+  /* Reset Rx transfer counter */
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing transfers (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx and Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart)
+{
+  uint32_t abortcplt = 1U;
+
+  /* Disable interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE |
+                                          USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE));
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised
+     before any call to DMA Abort functions */
+  /* DMA Tx Handle is valid */
+  if (huart->hdmatx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Tx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+    {
+      huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback;
+    }
+    else
+    {
+      huart->hdmatx->XferAbortCallback = NULL;
+    }
+  }
+  /* DMA Rx Handle is valid */
+  if (huart->hdmarx != NULL)
+  {
+    /* Set DMA Abort Complete callback if UART DMA Rx request if enabled.
+       Otherwise, set it to NULL */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback;
+    }
+    else
+    {
+      huart->hdmarx->XferAbortCallback = NULL;
+    }
+  }
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable DMA Tx at UART level */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* UART Tx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        huart->hdmatx->XferAbortCallback = NULL;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* UART Rx DMA Abort callback has already been initialised :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        huart->hdmarx->XferAbortCallback = NULL;
+        abortcplt = 1U;
+      }
+      else
+      {
+        abortcplt = 0U;
+      }
+    }
+  }
+
+  /* if no DMA abort complete callback execution is required => call user Abort Complete callback */
+  if (abortcplt == 1U)
+  {
+    /* Reset Tx and Rx transfer counters */
+    huart->TxXferCount = 0U;
+    huart->RxXferCount = 0U;
+
+    /* Clear ISR function pointers */
+    huart->RxISR = NULL;
+    huart->TxISR = NULL;
+
+    /* Reset errorCode */
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Discard the received data */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+    /* Restore huart->gState and huart->RxState to Ready */
+    huart->gState  = HAL_UART_STATE_READY;
+    huart->RxState = HAL_UART_STATE_READY;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort complete callback */
+    huart->AbortCpltCallback(huart);
+#else
+    /* Call legacy weak Abort complete callback */
+    HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Transmit transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Tx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+  /* Abort the UART DMA Tx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT))
+  {
+    /* Disable the UART DMA Tx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmatx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback;
+
+      /* Abort DMA TX */
+      if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */
+        huart->hdmatx->XferAbortCallback(huart->hdmatx);
+      }
+    }
+    else
+    {
+      /* Reset Tx transfer counter */
+      huart->TxXferCount = 0U;
+
+      /* Clear TxISR function pointers */
+      huart->TxISR = NULL;
+
+      /* Restore huart->gState to Ready */
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Transmit Complete Callback */
+      huart->AbortTransmitCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Transmit Complete Callback */
+      HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Tx transfer counter */
+    huart->TxXferCount = 0U;
+
+    /* Clear TxISR function pointers */
+    huart->TxISR = NULL;
+
+    /* Flush the whole TX FIFO (if needed) */
+    if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+    {
+      __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+    }
+
+    /* Restore huart->gState to Ready */
+    huart->gState = HAL_UART_STATE_READY;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Transmit Complete Callback */
+    huart->AbortTransmitCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Transmit Complete Callback */
+    HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Abort ongoing Receive transfer (Interrupt mode).
+  * @param  huart UART handle.
+  * @note   This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode.
+  *         This procedure performs following operations :
+  *           - Disable UART Interrupts (Rx)
+  *           - Disable the DMA transfer in the peripheral register (if enabled)
+  *           - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode)
+  *           - Set handle State to READY
+  *           - At abort completion, call user abort complete callback
+  * @note   This procedure is executed in Interrupt mode, meaning that abort procedure could be
+  *         considered as completed only when user abort complete callback is executed (not when exiting function).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
+  }
+
+  /* Abort the UART DMA Rx channel if enabled */
+  if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+  {
+    /* Disable the UART DMA Rx request if enabled */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */
+    if (huart->hdmarx != NULL)
+    {
+      /* Set the UART DMA Abort callback :
+         will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */
+      huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback;
+
+      /* Abort DMA RX */
+      if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+      {
+        /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+        huart->hdmarx->XferAbortCallback(huart->hdmarx);
+      }
+    }
+    else
+    {
+      /* Reset Rx transfer counter */
+      huart->RxXferCount = 0U;
+
+      /* Clear RxISR function pointer */
+      huart->pRxBuffPtr = NULL;
+
+      /* Clear the Error flags in the ICR register */
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+      /* Discard the received data */
+      __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+      /* Restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+      huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+      /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+      /* Call registered Abort Receive Complete Callback */
+      huart->AbortReceiveCpltCallback(huart);
+#else
+      /* Call legacy weak Abort Receive Complete Callback */
+      HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    }
+  }
+  else
+  {
+    /* Reset Rx transfer counter */
+    huart->RxXferCount = 0U;
+
+    /* Clear RxISR function pointer */
+    huart->pRxBuffPtr = NULL;
+
+    /* Clear the Error flags in the ICR register */
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+    /* Restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+    huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+    /* As no DMA to be aborted, call directly user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Abort Receive Complete Callback */
+    huart->AbortReceiveCpltCallback(huart);
+#else
+    /* Call legacy weak Abort Receive Complete Callback */
+    HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Handle UART interrupt request.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
+{
+  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+
+  uint32_t errorflags;
+  uint32_t errorcode;
+
+  /* If no error occurs */
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+  if (errorflags == 0U)
+  {
+    /* UART in mode Receiver ---------------------------------------------------*/
+    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+    {
+      if (huart->RxISR != NULL)
+      {
+        huart->RxISR(huart);
+      }
+      return;
+    }
+  }
+
+  /* If some errors occur */
+  if ((errorflags != 0U)
+      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+  {
+    /* UART parity error interrupt occurred -------------------------------------*/
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+    }
+
+    /* UART frame error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+    }
+
+    /* UART noise error interrupt occurred --------------------------------------*/
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+    }
+
+    /* UART Over-Run interrupt occurred -----------------------------------------*/
+    if (((isrflags & USART_ISR_ORE) != 0U)
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+            ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+    }
+
+    /* UART Receiver Timeout interrupt occurred ---------------------------------*/
+    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+      huart->ErrorCode |= HAL_UART_ERROR_RTO;
+    }
+
+    /* Call UART Error Call back function if need be ----------------------------*/
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+    {
+      /* UART in mode Receiver --------------------------------------------------*/
+      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+      {
+        if (huart->RxISR != NULL)
+        {
+          huart->RxISR(huart);
+        }
+      }
+
+      /* If Error is to be considered as blocking :
+          - Receiver Timeout error in Reception
+          - Overrun error in Reception
+          - any error occurs in DMA mode reception
+      */
+      errorcode = huart->ErrorCode;
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+      {
+        /* Blocking error : transfer is aborted
+           Set the UART state ready to be able to start again the process,
+           Disable Rx Interrupts, and disable Rx DMA request, if ongoing */
+        UART_EndRxTransfer(huart);
+
+        /* Abort the UART DMA Rx channel if enabled */
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+        {
+          /* Disable the UART DMA Rx request if enabled */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* Abort the UART DMA Rx channel */
+          if (huart->hdmarx != NULL)
+          {
+            /* Set the UART DMA Abort callback :
+               will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+
+            /* Abort DMA RX */
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+            {
+              /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+            }
+          }
+          else
+          {
+            /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered error callback*/
+            huart->ErrorCallback(huart);
+#else
+            /*Call legacy weak error callback*/
+            HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+          }
+        }
+        else
+        {
+          /* Call user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+      }
+      else
+      {
+        /* Non Blocking error : transfer could go on.
+           Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered error callback*/
+        huart->ErrorCallback(huart);
+#else
+        /*Call legacy weak error callback*/
+        HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+      }
+    }
+    return;
+
+  } /* End if some error occurs */
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : */
+  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      && ((isrflags & USART_ISR_IDLE) != 0U)
+      && ((cr1its & USART_ISR_IDLE) != 0U))
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+    /* Check if DMA mode is enabled in UART */
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+    {
+      /* DMA mode enabled */
+      /* Check received length : If all expected data are received, do nothing,
+         (DMA cplt callback will be called).
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+      if ((nb_remaining_rx_data > 0U)
+          && (nb_remaining_rx_data < huart->RxXferSize))
+      {
+        /* Reception is not complete */
+        huart->RxXferCount = nb_remaining_rx_data;
+
+        /* In Normal mode, end DMA xfer and HAL UART Rx process*/
+        if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
+        {
+          /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+          /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+             in the UART CR3 register */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+          /* At end of Rx process, restore huart->RxState to Ready */
+          huart->RxState = HAL_UART_STATE_READY;
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          /* Last bytes received, so no need as the abort is immediate */
+          (void)HAL_DMA_Abort(huart->hdmarx);
+        }
+
+        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+           In this case, Rx Event type is Idle Event */
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      else
+      {
+        /* If DMA is in Circular mode, Idle event is to be reported to user
+           even if occurring after a Transfer Complete event from DMA */
+        if (nb_remaining_rx_data == huart->RxXferSize)
+        {
+          if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
+          {
+            /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+               In this case, Rx Event type is Idle Event */
+            huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+            /*Call registered Rx Event callback*/
+            huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+            /*Call legacy weak Rx Event callback*/
+            HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+          }
+        }
+      }
+      return;
+    }
+    else
+    {
+      /* DMA mode not enabled */
+      /* Check received length : If all expected data are received, do nothing.
+         Otherwise, if at least one data has already been received, IDLE event is to be notified to user */
+      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+      if ((huart->RxXferCount > 0U)
+          && (nb_rx_data > 0U))
+      {
+        /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+        /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+           In this case, Rx Event type is Idle Event */
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxEventCallback(huart, nb_rx_data);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, nb_rx_data);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      return;
+    }
+  }
+
+  /* UART wakeup from Stop mode interrupt occurred ---------------------------*/
+  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+  {
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+
+    /* UART Rx state is not reset as a reception process might be ongoing.
+       If UART handle state fields need to be reset to READY, this could be done in Wakeup callback */
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Wakeup Callback */
+    huart->WakeupCallback(huart);
+#else
+    /* Call legacy weak Wakeup Callback */
+    HAL_UARTEx_WakeupCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* UART in mode Transmitter ------------------------------------------------*/
+  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+  {
+    if (huart->TxISR != NULL)
+    {
+      huart->TxISR(huart);
+    }
+    return;
+  }
+
+  /* UART in mode Transmitter (transmission end) -----------------------------*/
+  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+  {
+    UART_EndTransmit_IT(huart);
+    return;
+  }
+
+  /* UART TX Fifo Empty occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Tx Fifo Empty Callback */
+    huart->TxFifoEmptyCallback(huart);
+#else
+    /* Call legacy weak Tx Fifo Empty Callback */
+    HAL_UARTEx_TxFifoEmptyCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+
+  /* UART RX Fifo Full occurred ----------------------------------------------*/
+  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /* Call registered Rx Fifo Full Callback */
+    huart->RxFifoFullCallback(huart);
+#else
+    /* Call legacy weak Rx Fifo Full Callback */
+    HAL_UARTEx_RxFifoFullCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+    return;
+  }
+}
+
+/**
+  * @brief Tx Transfer completed callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_TxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Tx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_TxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_RxCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Rx Half Transfer completed callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE: This function should not be modified, when the callback is needed,
+           the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART error callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_ErrorCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART Abort Receive Complete callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Reception Event Callback (Rx event notification called after use of advanced reception service).
+  * @param  huart UART handle
+  * @param  Size  Number of data available in application reception buffer (indicates a position in
+  *               reception buffer until which, data are available)
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+  UNUSED(Size);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxEventCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief   UART control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to control the UART.
+     (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly
+     (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature
+     (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature
+     (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode
+     (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode
+     (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode
+     (+) UART_SetConfig() API configures the UART peripheral
+     (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features
+     (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization
+     (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter
+     (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver
+     (+) HAL_LIN_SendBreak() API transmits the break characters
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Update on the fly the receiver timeout value in RTOR register.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @param  TimeoutValue receiver timeout value in number of baud blocks. The timeout
+  *                     value must be less or equal to 0x0FFFFFFFF.
+  * @retval None
+  */
+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue));
+    MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue);
+  }
+}
+
+/**
+  * @brief  Enable the UART receiver timeout feature.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    if (huart->gState == HAL_UART_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(huart);
+
+      huart->gState = HAL_UART_STATE_BUSY;
+
+      /* Set the USART RTOEN bit */
+      SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(huart);
+
+      return HAL_OK;
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Disable the UART receiver timeout feature.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *                    the configuration information for the specified UART module.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart)
+{
+  if (!(IS_LPUART_INSTANCE(huart->Instance)))
+  {
+    if (huart->gState == HAL_UART_STATE_READY)
+    {
+      /* Process Locked */
+      __HAL_LOCK(huart);
+
+      huart->gState = HAL_UART_STATE_BUSY;
+
+      /* Clear the USART RTOEN bit */
+      CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN);
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      /* Process Unlocked */
+      __HAL_UNLOCK(huart);
+
+      return HAL_OK;
+    }
+    else
+    {
+      return HAL_BUSY;
+    }
+  }
+  else
+  {
+    return HAL_ERROR;
+  }
+}
+
+/**
+  * @brief  Enable UART in mute mode (does not mean UART enters mute mode;
+  *         to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called).
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Enable USART mute mode by setting the MME bit in the CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief  Disable UART mute mode (does not mean the UART actually exits mute mode
+  *         as it may not have been in mute mode at this very moment).
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable USART mute mode by clearing the MME bit in the CR1 register */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Enter UART mute mode (means UART actually enters mute mode).
+  * @note  To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called.
+  * @param huart UART handle.
+  * @retval None
+  */
+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
+{
+  __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST);
+}
+
+/**
+  * @brief  Enable the UART transmitter and disable the UART receiver.
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the UART receiver and disable the UART transmitter.
+  * @param  huart UART handle.
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
+{
+  __HAL_LOCK(huart);
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Clear TE and RE bits */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE));
+
+  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  Transmit break characters.
+  * @param  huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
+{
+  /* Check the parameters */
+  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
+
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Send break characters */
+  __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions
+  *  @brief   UART Peripheral State functions
+  *
+@verbatim
+  ==============================================================================
+            ##### Peripheral State and Error functions #####
+  ==============================================================================
+    [..]
+    This subsection provides functions allowing to :
+      (+) Return the UART handle state.
+      (+) Return the UART handle error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief Return the UART handle state.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval HAL state
+  */
+HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart)
+{
+  uint32_t temp1;
+  uint32_t temp2;
+  temp1 = huart->gState;
+  temp2 = huart->RxState;
+
+  return (HAL_UART_StateTypeDef)(temp1 | temp2);
+}
+
+/**
+  * @brief  Return the UART handle error code.
+  * @param  huart Pointer to a UART_HandleTypeDef structure that contains
+  *               the configuration information for the specified UART.
+  * @retval UART Error Code
+  */
+uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart)
+{
+  return huart->ErrorCode;
+}
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup UART_Private_Functions UART Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Initialize the callbacks to their default values.
+  * @param  huart UART handle.
+  * @retval none
+  */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart)
+{
+  /* Init the UART Callback settings */
+  huart->TxHalfCpltCallback        = HAL_UART_TxHalfCpltCallback;        /* Legacy weak TxHalfCpltCallback        */
+  huart->TxCpltCallback            = HAL_UART_TxCpltCallback;            /* Legacy weak TxCpltCallback            */
+  huart->RxHalfCpltCallback        = HAL_UART_RxHalfCpltCallback;        /* Legacy weak RxHalfCpltCallback        */
+  huart->RxCpltCallback            = HAL_UART_RxCpltCallback;            /* Legacy weak RxCpltCallback            */
+  huart->ErrorCallback             = HAL_UART_ErrorCallback;             /* Legacy weak ErrorCallback             */
+  huart->AbortCpltCallback         = HAL_UART_AbortCpltCallback;         /* Legacy weak AbortCpltCallback         */
+  huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */
+  huart->AbortReceiveCpltCallback  = HAL_UART_AbortReceiveCpltCallback;  /* Legacy weak AbortReceiveCpltCallback  */
+  huart->WakeupCallback            = HAL_UARTEx_WakeupCallback;          /* Legacy weak WakeupCallback            */
+  huart->RxFifoFullCallback        = HAL_UARTEx_RxFifoFullCallback;      /* Legacy weak RxFifoFullCallback        */
+  huart->TxFifoEmptyCallback       = HAL_UARTEx_TxFifoEmptyCallback;     /* Legacy weak TxFifoEmptyCallback       */
+  huart->RxEventCallback           = HAL_UARTEx_RxEventCallback;         /* Legacy weak RxEventCallback           */
+
+}
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+
+/**
+  * @brief Configure the UART peripheral.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpreg;
+  uint16_t brrtemp;
+  UART_ClockSourceTypeDef clocksource;
+  uint32_t usartdiv;
+  HAL_StatusTypeDef ret               = HAL_OK;
+  uint32_t lpuart_ker_ck_pres;
+  uint32_t pclk;
+
+  /* Check the parameters */
+  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));
+  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
+  if (UART_INSTANCE_LOWPOWER(huart))
+  {
+    assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits));
+  }
+  else
+  {
+    assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
+    assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling));
+  }
+
+  assert_param(IS_UART_PARITY(huart->Init.Parity));
+  assert_param(IS_UART_MODE(huart->Init.Mode));
+  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
+  assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling));
+  assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler));
+
+  /*-------------------------- USART CR1 Configuration -----------------------*/
+  /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure
+  *  the UART Word Length, Parity, Mode and oversampling:
+  *  set the M bits according to huart->Init.WordLength value
+  *  set PCE and PS bits according to huart->Init.Parity value
+  *  set TE and RE bits according to huart->Init.Mode value
+  *  set OVER8 bit according to huart->Init.OverSampling value */
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+
+  /*-------------------------- USART CR2 Configuration -----------------------*/
+  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
+  * to huart->Init.StopBits value */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+
+  /*-------------------------- USART CR3 Configuration -----------------------*/
+  /* Configure
+  * - UART HardWare Flow Control: set CTSE and RTSE bits according
+  *   to huart->Init.HwFlowCtl value
+  * - one-bit sampling method versus three samples' majority rule according
+  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
+  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+
+  if (!(UART_INSTANCE_LOWPOWER(huart)))
+  {
+    tmpreg |= huart->Init.OneBitSampling;
+  }
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+
+  /*-------------------------- USART PRESC Configuration -----------------------*/
+  /* Configure
+  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
+  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+
+  /*-------------------------- USART BRR Configuration -----------------------*/
+  UART_GETCLOCKSOURCE(huart, clocksource);
+
+  /* Check LPUART instance */
+  if (UART_INSTANCE_LOWPOWER(huart))
+  {
+    /* Retrieve frequency clock */
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        pclk = (uint32_t) HSI_VALUE;
+        break;
+      case UART_CLOCKSOURCE_SYSCLK:
+        pclk = HAL_RCC_GetSysClockFreq();
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+        break;
+      default:
+        pclk = 0U;
+        ret = HAL_ERROR;
+        break;
+    }
+
+    /* If proper clock source reported */
+    if (pclk != 0U)
+    {
+      /* Compute clock after Prescaler */
+      lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
+
+      /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
+      if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
+          (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
+      {
+        ret = HAL_ERROR;
+      }
+      else
+      {
+        /* Check computed UsartDiv value is in allocated range
+           (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
+        usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+        if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
+        {
+          huart->Instance->BRR = usartdiv;
+        }
+        else
+        {
+          ret = HAL_ERROR;
+        }
+      } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
+                (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
+    } /* if (pclk != 0) */
+  }
+  /* Check UART Over Sampling to set Baud Rate Register */
+  else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+  {
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+        break;
+      case UART_CLOCKSOURCE_PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        pclk = (uint32_t) HSI_VALUE;
+        break;
+      case UART_CLOCKSOURCE_SYSCLK:
+        pclk = HAL_RCC_GetSysClockFreq();
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+        break;
+      default:
+        pclk = 0U;
+        ret = HAL_ERROR;
+        break;
+    }
+
+    /* USARTDIV must be greater than or equal to 0d16 */
+    if (pclk != 0U)
+    {
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+      {
+        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+        huart->Instance->BRR = brrtemp;
+      }
+      else
+      {
+        ret = HAL_ERROR;
+      }
+    }
+  }
+  else
+  {
+    switch (clocksource)
+    {
+      case UART_CLOCKSOURCE_PCLK1:
+        pclk = HAL_RCC_GetPCLK1Freq();
+        break;
+      case UART_CLOCKSOURCE_PCLK2:
+        pclk = HAL_RCC_GetPCLK2Freq();
+        break;
+      case UART_CLOCKSOURCE_HSI:
+        pclk = (uint32_t) HSI_VALUE;
+        break;
+      case UART_CLOCKSOURCE_SYSCLK:
+        pclk = HAL_RCC_GetSysClockFreq();
+        break;
+      case UART_CLOCKSOURCE_LSE:
+        pclk = (uint32_t) LSE_VALUE;
+        break;
+      default:
+        pclk = 0U;
+        ret = HAL_ERROR;
+        break;
+    }
+
+    if (pclk != 0U)
+    {
+      /* USARTDIV must be greater than or equal to 0d16 */
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+      {
+        huart->Instance->BRR = (uint16_t)usartdiv;
+      }
+      else
+      {
+        ret = HAL_ERROR;
+      }
+    }
+  }
+
+  /* Initialize the number of data to process during RX/TX ISR execution */
+  huart->NbTxDataToProcess = 1;
+  huart->NbRxDataToProcess = 1;
+
+  /* Clear ISR function pointers */
+  huart->RxISR = NULL;
+  huart->TxISR = NULL;
+
+  return ret;
+}
+
+/**
+  * @brief Configure the UART peripheral advanced features.
+  * @param huart UART handle.
+  * @retval None
+  */
+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
+{
+  /* Check whether the set of advanced features to configure is properly set */
+  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
+
+  /* if required, configure RX/TX pins swap */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+  }
+
+  /* if required, configure TX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+  }
+
+  /* if required, configure RX pin active level inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+  }
+
+  /* if required, configure data inversion */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+  }
+
+  /* if required, configure RX overrun detection disabling */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+  {
+    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+  }
+
+  /* if required, configure DMA disabling on reception error */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+  }
+
+  /* if required, configure auto Baud rate detection scheme */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+  {
+    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
+    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+    /* set auto Baudrate detection parameters if detection is enabled */
+    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+    {
+      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
+      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+    }
+  }
+
+  /* if required, configure MSB first on communication line */
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+  {
+    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+  }
+}
+
+/**
+  * @brief Check the UART Idle State.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
+{
+  uint32_t tickstart;
+
+  /* Initialize the UART ErrorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+
+  /* Check if the Transmitter is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+  {
+    /* Wait until TEACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Disable TXE interrupt for the interrupt process */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
+
+      huart->gState = HAL_UART_STATE_READY;
+
+      __HAL_UNLOCK(huart);
+
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Check if the Receiver is enabled */
+  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+  {
+    /* Wait until REACK flag is set */
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+    {
+      /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
+      interrupts for the interrupt process */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      huart->RxState = HAL_UART_STATE_READY;
+
+      __HAL_UNLOCK(huart);
+
+      /* Timeout occurred */
+      return HAL_TIMEOUT;
+    }
+  }
+
+  /* Initialize the UART State */
+  huart->gState = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  This function handles UART Communication Timeout. It waits
+  *                  until a flag is no longer in the specified status.
+  * @param huart     UART handle.
+  * @param Flag      Specifies the UART flag to check
+  * @param Status    The actual Flag status (SET or RESET)
+  * @param Tickstart Tick start value
+  * @param Timeout   Timeout duration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
+                                              uint32_t Tickstart, uint32_t Timeout)
+{
+  /* Wait until flag is set */
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+  {
+    /* Check for the Timeout */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+      {
+
+        return HAL_TIMEOUT;
+      }
+
+      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
+      {
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
+        {
+          /* Clear Overrun Error flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+
+          /* Blocking error : transfer is aborted
+          Set the UART state ready to be able to start again the process,
+          Disable Rx Interrupts if ongoing */
+          UART_EndRxTransfer(huart);
+
+          huart->ErrorCode = HAL_UART_ERROR_ORE;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+
+          return HAL_ERROR;
+        }
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+        {
+          /* Clear Receiver Timeout flag*/
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+
+          /* Blocking error : transfer is aborted
+          Set the UART state ready to be able to start again the process,
+          Disable Rx Interrupts if ongoing */
+          UART_EndRxTransfer(huart);
+
+          huart->ErrorCode = HAL_UART_ERROR_RTO;
+
+          /* Process Unlocked */
+          __HAL_UNLOCK(huart);
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start Receive operation in interrupt mode.
+  * @note   This function could be called by all HAL UART API providing reception in Interrupt mode.
+  * @note   When calling this function, parameters validity is considered as already checked,
+  *         i.e. Rx State, buffer address, ...
+  *         UART Handle is assumed as Locked.
+  * @param  huart UART handle.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  huart->pRxBuffPtr  = pData;
+  huart->RxXferSize  = Size;
+  huart->RxXferCount = Size;
+  huart->RxISR       = NULL;
+
+  /* Computation of UART mask to apply to RDR register */
+  UART_MASK_COMPUTATION(huart);
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Configure Rx interrupt processing */
+  if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess))
+  {
+    /* Set the Rx ISR function pointer according to the data word length */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      huart->RxISR = UART_RxISR_16BIT_FIFOEN;
+    }
+    else
+    {
+      huart->RxISR = UART_RxISR_8BIT_FIFOEN;
+    }
+
+    /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    }
+    ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+  }
+  else
+  {
+    /* Set the Rx ISR function pointer according to the data word length */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      huart->RxISR = UART_RxISR_16BIT;
+    }
+    else
+    {
+      huart->RxISR = UART_RxISR_8BIT;
+    }
+
+    /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */
+    if (huart->Init.Parity != UART_PARITY_NONE)
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE);
+    }
+    else
+    {
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  return HAL_OK;
+}
+
+/**
+  * @brief  Start Receive operation in DMA mode.
+  * @note   This function could be called by all HAL UART API providing reception in DMA mode.
+  * @note   When calling this function, parameters validity is considered as already checked,
+  *         i.e. Rx State, buffer address, ...
+  *         UART Handle is assumed as Locked.
+  * @param  huart UART handle.
+  * @param  pData Pointer to data buffer (u8 or u16 data elements).
+  * @param  Size  Amount of data elements (u8 or u16) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  huart->pRxBuffPtr = pData;
+  huart->RxXferSize = Size;
+
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+
+  if (huart->hdmarx != NULL)
+  {
+    /* Set the UART DMA transfer complete callback */
+    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+
+    /* Set the UART DMA Half transfer complete callback */
+    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+
+    /* Set the DMA error callback */
+    huart->hdmarx->XferErrorCallback = UART_DMAError;
+
+    /* Set the DMA abort callback */
+    huart->hdmarx->XferAbortCallback = NULL;
+
+    /* Enable the DMA channel */
+    if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+    {
+      /* Set error code to DMA */
+      huart->ErrorCode = HAL_UART_ERROR_DMA;
+
+      /* Restore huart->RxState to ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      return HAL_ERROR;
+    }
+  }
+
+  /* Enable the UART Parity Error Interrupt */
+  if (huart->Init.Parity != UART_PARITY_NONE)
+  {
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+  }
+
+  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+  /* Enable the DMA transfer for the receiver request by setting the DMAR bit
+  in the UART CR3 register */
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+  return HAL_OK;
+}
+
+
+/**
+  * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable TXEIE, TCIE, TXFT interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
+
+  /* At end of Tx process, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+}
+
+
+/**
+  * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
+  * @param  huart UART handle.
+  * @retval None
+  */
+static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
+{
+  /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+  ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+  /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+  }
+
+  /* At end of Rx process, restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Reset RxIsr function pointer */
+  huart->RxISR = NULL;
+}
+
+
+/**
+  * @brief DMA UART transmit process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+  {
+    huart->TxXferCount = 0U;
+
+    /* Disable the DMA transfer for transmit request by resetting the DMAT bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT);
+
+    /* Enable the UART Transmit Complete Interrupt */
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+  }
+  /* DMA Circular mode */
+  else
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Tx complete callback*/
+    huart->TxCpltCallback(huart);
+#else
+    /*Call legacy weak Tx complete callback*/
+    HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART transmit process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx Half complete callback*/
+  huart->TxHalfCpltCallback(huart);
+#else
+  /*Call legacy weak Tx Half complete callback*/
+  HAL_UART_TxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief DMA UART receive process complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* DMA Normal mode */
+  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+  {
+    huart->RxXferCount = 0U;
+
+    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
+       in the UART CR3 register */
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
+    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+    {
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+    }
+  }
+
+  /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+     In this case, Rx Event type is Transfer Complete */
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : use Rx Event callback */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Event callback*/
+    huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+    /*Call legacy weak Rx Event callback*/
+    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* In other cases : use Rx Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx complete callback*/
+    huart->RxCpltCallback(huart);
+#else
+    /*Call legacy weak Rx complete callback*/
+    HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART receive process half complete callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  /* Initialize type of RxEvent that correspond to RxEvent callback execution;
+     In this case, Rx Event type is Half Transfer */
+  huart->RxEventType = HAL_UART_RXEVENT_HT;
+
+  /* Check current reception Mode :
+     If Reception till IDLE event has been selected : use Rx Event callback */
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+  {
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Event callback*/
+    huart->RxEventCallback(huart, huart->RxXferSize / 2U);
+#else
+    /*Call legacy weak Rx Event callback*/
+    HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+  else
+  {
+    /* In other cases : use Rx Half Complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    /*Call registered Rx Half complete callback*/
+    huart->RxHalfCpltCallback(huart);
+#else
+    /*Call legacy weak Rx Half complete callback*/
+    HAL_UART_RxHalfCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+  }
+}
+
+/**
+  * @brief DMA UART communication error callback.
+  * @param hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  const HAL_UART_StateTypeDef gstate = huart->gState;
+  const HAL_UART_StateTypeDef rxstate = huart->RxState;
+
+  /* Stop UART DMA Tx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
+      (gstate == HAL_UART_STATE_BUSY_TX))
+  {
+    huart->TxXferCount = 0U;
+    UART_EndTxTransfer(huart);
+  }
+
+  /* Stop UART DMA Rx request if ongoing */
+  if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
+      (rxstate == HAL_UART_STATE_BUSY_RX))
+  {
+    huart->RxXferCount = 0U;
+    UART_EndRxTransfer(huart);
+  }
+
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART communication abort callback, when initiated by HAL services on Error
+  *         (To be called at end of DMA Abort procedure following error occurrence).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+  huart->RxXferCount = 0U;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
+#else
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Tx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Rx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->hdmatx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmarx != NULL)
+  {
+    if (huart->hdmarx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user
+  *         (To be called at end of DMA Rx Abort procedure following user abort request).
+  * @note   When this callback is executed, User Abort complete call back is called only if no
+  *         Abort still ongoing for Tx DMA Handle.
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->hdmarx->XferAbortCallback = NULL;
+
+  /* Check if an Abort process is still ongoing */
+  if (huart->hdmatx != NULL)
+  {
+    if (huart->hdmatx->XferAbortCallback != NULL)
+    {
+      return;
+    }
+  }
+
+  /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */
+  huart->TxXferCount = 0U;
+  huart->RxXferCount = 0U;
+
+  /* Reset errorCode */
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->gState and huart->RxState to Ready */
+  huart->gState  = HAL_UART_STATE_READY;
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort complete callback */
+  huart->AbortCpltCallback(huart);
+#else
+  /* Call legacy weak Abort complete callback */
+  HAL_UART_AbortCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+
+/**
+  * @brief  DMA UART Tx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortTransmit_IT API (Abort only Tx transfer)
+  *         (This callback is executed at end of DMA Tx Abort procedure following user abort request,
+  *         and leads to user Tx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+
+  huart->TxXferCount = 0U;
+
+  /* Flush the whole TX FIFO (if needed) */
+  if (huart->FifoMode == UART_FIFOMODE_ENABLE)
+  {
+    __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST);
+  }
+
+  /* Restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Transmit Complete Callback */
+  huart->AbortTransmitCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Transmit Complete Callback */
+  HAL_UART_AbortTransmitCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA UART Rx communication abort callback, when initiated by user by a call to
+  *         HAL_UART_AbortReceive_IT API (Abort only Rx transfer)
+  *         (This callback is executed at end of DMA Rx Abort procedure following user abort request,
+  *         and leads to user Rx Abort Complete callback execution).
+  * @param  hdma DMA handle.
+  * @retval None
+  */
+static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma)
+{
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  huart->RxXferCount = 0U;
+
+  /* Clear the Error flags in the ICR register */
+  __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
+
+  /* Discard the received data */
+  __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+
+  /* Restore huart->RxState to Ready */
+  huart->RxState = HAL_UART_STATE_READY;
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+  /* Call user Abort complete callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /* Call registered Abort Receive Complete Callback */
+  huart->AbortReceiveCpltCallback(huart);
+#else
+  /* Call legacy weak Abort Receive Complete Callback */
+  HAL_UART_AbortReceiveCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief TX interrupt handler for 7 or 8 bits data word length .
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_8BIT(UART_HandleTypeDef *huart)
+{
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if (huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+      huart->pTxBuffPtr++;
+      huart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief TX interrupt handler for 9 bits data word length.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_16BIT(UART_HandleTypeDef *huart)
+{
+  const uint16_t *tmp;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    if (huart->TxXferCount == 0U)
+    {
+      /* Disable the UART Transmit Data Register Empty Interrupt */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE);
+
+      /* Enable the UART Transmit Complete Interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+    }
+    else
+    {
+      tmp = (const uint16_t *) huart->pTxBuffPtr;
+      huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+      huart->pTxBuffPtr += 2U;
+      huart->TxXferCount--;
+    }
+  }
+}
+
+/**
+  * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (huart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+        /* Enable the UART Transmit Complete Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+        break; /* force exit loop */
+      }
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF);
+        huart->pTxBuffPtr++;
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Transmit_IT().
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  const uint16_t *tmp;
+  uint16_t  nb_tx_data;
+
+  /* Check that a Tx process is ongoing */
+  if (huart->gState == HAL_UART_STATE_BUSY_TX)
+  {
+    for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--)
+    {
+      if (huart->TxXferCount == 0U)
+      {
+        /* Disable the TX FIFO threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE);
+
+        /* Enable the UART Transmit Complete Interrupt */
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+        break; /* force exit loop */
+      }
+      else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U)
+      {
+        tmp = (const uint16_t *) huart->pTxBuffPtr;
+        huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL);
+        huart->pTxBuffPtr += 2U;
+        huart->TxXferCount--;
+      }
+      else
+      {
+        /* Nothing to do */
+      }
+    }
+  }
+}
+
+/**
+  * @brief  Wrap up transmission in non-blocking mode.
+  * @param  huart pointer to a UART_HandleTypeDef structure that contains
+  *                the configuration information for the specified UART module.
+  * @retval None
+  */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable the UART Transmit Complete Interrupt */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Cleat TxISR function pointer */
+  huart->TxISR = NULL;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief RX interrupt handler for 7 or 8 bits data word length .
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+    huart->pRxBuffPtr++;
+    huart->RxXferCount--;
+
+    if (huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupts */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+
+      /* Initialize type of RxEvent to Transfer Complete */
+      huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+      if (!(IS_LPUART_INSTANCE(huart->Instance)))
+      {
+        /* Check that USART RTOEN bit is set */
+        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+        {
+          /* Enable the UART Receiver Timeout Interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+        }
+      }
+
+      /* Check current reception Mode :
+         If Reception till IDLE event has been selected : */
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Disable IDLE interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+        {
+          /* Clear IDLE Flag */
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      else
+      {
+        /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrupt handler for 9 bits data word length .
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t uhMask = huart->Mask;
+  uint16_t  uhdata;
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+    tmp = (uint16_t *) huart->pRxBuffPtr ;
+    *tmp = (uint16_t)(uhdata & uhMask);
+    huart->pRxBuffPtr += 2U;
+    huart->RxXferCount--;
+
+    if (huart->RxXferCount == 0U)
+    {
+      /* Disable the UART Parity Error Interrupt and RXNE interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+
+      /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+
+      /* Rx process is completed, restore huart->RxState to Ready */
+      huart->RxState = HAL_UART_STATE_READY;
+
+      /* Clear RxISR function pointer */
+      huart->RxISR = NULL;
+
+      /* Initialize type of RxEvent to Transfer Complete */
+      huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+      if (!(IS_LPUART_INSTANCE(huart->Instance)))
+      {
+        /* Check that USART RTOEN bit is set */
+        if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+        {
+          /* Enable the UART Receiver Timeout Interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+        }
+      }
+
+      /* Check current reception Mode :
+         If Reception till IDLE event has been selected : */
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        /* Set reception type to Standard */
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+        /* Disable IDLE interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+        {
+          /* Clear IDLE Flag */
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx Event callback*/
+        huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+        /*Call legacy weak Rx Event callback*/
+        HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+      }
+      else
+      {
+        /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+        /*Call registered Rx complete callback*/
+        huart->RxCpltCallback(huart);
+#else
+        /*Call legacy weak Rx complete callback*/
+        HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+      }
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrupt handler for 7 or 8  bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+  uint16_t  nb_rx_data;
+  uint16_t  rxdatacount;
+  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
+  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
+  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    nb_rx_data = huart->NbRxDataToProcess;
+    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+      *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask);
+      huart->pRxBuffPtr++;
+      huart->RxXferCount--;
+      isrflags = READ_REG(huart->Instance->ISR);
+
+      /* If some non blocking errors occurred */
+      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+      {
+        /* UART parity error interrupt occurred -------------------------------------*/
+        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_PE;
+        }
+
+        /* UART frame error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_FE;
+        }
+
+        /* UART noise error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_NE;
+        }
+
+        /* Call UART Error Call back function if need be ----------------------------*/
+        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+        {
+          /* Non Blocking error : transfer could go on.
+          Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          huart->ErrorCode = HAL_UART_ERROR_NONE;
+        }
+      }
+
+      if (huart->RxXferCount == 0U)
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+           and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+        /* Initialize type of RxEvent to Transfer Complete */
+        huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+        if (!(IS_LPUART_INSTANCE(huart->Instance)))
+        {
+          /* Check that USART RTOEN bit is set */
+          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+          {
+            /* Enable the UART Receiver Timeout Interrupt */
+            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+          }
+        }
+
+        /* Check current reception Mode :
+           If Reception till IDLE event has been selected : */
+        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+        {
+          /* Set reception type to Standard */
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          /* Disable IDLE interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+          {
+            /* Clear IDLE Flag */
+            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+          }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx Event callback*/
+          huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+          /*Call legacy weak Rx Event callback*/
+          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+        }
+        else
+        {
+          /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx complete callback*/
+          huart->RxCpltCallback(huart);
+#else
+          /*Call legacy weak Rx complete callback*/
+          HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+        break;
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_8BIT;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled.
+  * @note   Function is called under interruption only, once
+  *         interruptions have been enabled by HAL_UART_Receive_IT()
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart)
+{
+  uint16_t *tmp;
+  uint16_t  uhMask = huart->Mask;
+  uint16_t  uhdata;
+  uint16_t  nb_rx_data;
+  uint16_t  rxdatacount;
+  uint32_t  isrflags = READ_REG(huart->Instance->ISR);
+  uint32_t  cr1its   = READ_REG(huart->Instance->CR1);
+  uint32_t  cr3its   = READ_REG(huart->Instance->CR3);
+
+  /* Check that a Rx process is ongoing */
+  if (huart->RxState == HAL_UART_STATE_BUSY_RX)
+  {
+    nb_rx_data = huart->NbRxDataToProcess;
+    while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U))
+    {
+      uhdata = (uint16_t) READ_REG(huart->Instance->RDR);
+      tmp = (uint16_t *) huart->pRxBuffPtr ;
+      *tmp = (uint16_t)(uhdata & uhMask);
+      huart->pRxBuffPtr += 2U;
+      huart->RxXferCount--;
+      isrflags = READ_REG(huart->Instance->ISR);
+
+      /* If some non blocking errors occurred */
+      if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U)
+      {
+        /* UART parity error interrupt occurred -------------------------------------*/
+        if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_PE;
+        }
+
+        /* UART frame error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_FE;
+        }
+
+        /* UART noise error interrupt occurred --------------------------------------*/
+        if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+        {
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+
+          huart->ErrorCode |= HAL_UART_ERROR_NE;
+        }
+
+        /* Call UART Error Call back function if need be ----------------------------*/
+        if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+        {
+          /* Non Blocking error : transfer could go on.
+          Error is notified to user through user error callback */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered error callback*/
+          huart->ErrorCallback(huart);
+#else
+          /*Call legacy weak error callback*/
+          HAL_UART_ErrorCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+          huart->ErrorCode = HAL_UART_ERROR_NONE;
+        }
+      }
+
+      if (huart->RxXferCount == 0U)
+      {
+        /* Disable the UART Parity Error Interrupt and RXFT interrupt*/
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+
+        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error)
+           and RX FIFO Threshold interrupt */
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+
+        /* Rx process is completed, restore huart->RxState to Ready */
+        huart->RxState = HAL_UART_STATE_READY;
+
+        /* Clear RxISR function pointer */
+        huart->RxISR = NULL;
+
+        /* Initialize type of RxEvent to Transfer Complete */
+        huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+        if (!(IS_LPUART_INSTANCE(huart->Instance)))
+        {
+          /* Check that USART RTOEN bit is set */
+          if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U)
+          {
+            /* Enable the UART Receiver Timeout Interrupt */
+            ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE);
+          }
+        }
+
+        /* Check current reception Mode :
+           If Reception till IDLE event has been selected : */
+        if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+        {
+          /* Set reception type to Standard */
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+
+          /* Disable IDLE interrupt */
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+
+          if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET)
+          {
+            /* Clear IDLE Flag */
+            __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+          }
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx Event callback*/
+          huart->RxEventCallback(huart, huart->RxXferSize);
+#else
+          /*Call legacy weak Rx Event callback*/
+          HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+        }
+        else
+        {
+          /* Standard reception API called */
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+          /*Call registered Rx complete callback*/
+          huart->RxCpltCallback(huart);
+#else
+          /*Call legacy weak Rx complete callback*/
+          HAL_UART_RxCpltCallback(huart);
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+        }
+        break;
+      }
+    }
+
+    /* When remaining number of bytes to receive is less than the RX FIFO
+    threshold, next incoming frames are processed as if FIFO mode was
+    disabled (i.e. one interrupt per received frame).
+    */
+    rxdatacount = huart->RxXferCount;
+    if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess))
+    {
+      /* Disable the UART RXFT interrupt*/
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE);
+
+      /* Update the RxISR function pointer */
+      huart->RxISR = UART_RxISR_16BIT;
+
+      /* Enable the UART Data Register Not Empty interrupt */
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE);
+    }
+  }
+  else
+  {
+    /* Clear RXNE interrupt flag */
+    __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
+  }
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c
new file mode 100644
index 0000000..cdb0c95
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_hal_uart_ex.c
@@ -0,0 +1,1042 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_hal_uart_ex.c
+  * @author  MCD Application Team
+  * @brief   Extended UART HAL module driver.
+  *          This file provides firmware functions to manage the following extended
+  *          functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART).
+  *           + Initialization and de-initialization functions
+  *           + Peripheral Control functions
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+               ##### UART peripheral extended features  #####
+  ==============================================================================
+
+    (#) Declare a UART_HandleTypeDef handle structure.
+
+    (#) For the UART RS485 Driver Enable mode, initialize the UART registers
+        by calling the HAL_RS485Ex_Init() API.
+
+    (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming.
+
+        -@- When UART operates in FIFO mode, FIFO mode must be enabled prior
+            starting RX/TX transfers. Also RX/TX FIFO thresholds must be
+            configured prior starting RX/TX transfers.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_hal.h"
+
+/** @addtogroup STM32G4xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup UARTEx UARTEx
+  * @brief UART Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_UART_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @defgroup UARTEX_Private_Constants UARTEx Private Constants
+  * @{
+  */
+/* UART RX FIFO depth */
+#define RX_FIFO_DEPTH 8U
+
+/* UART TX FIFO depth */
+#define TX_FIFO_DEPTH 8U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup UARTEx_Private_Functions UARTEx Private Functions
+  * @{
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart);
+/**
+  * @}
+  */
+
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup UARTEx_Exported_Functions  UARTEx Exported Functions
+  * @{
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    Extended Initialization and Configuration Functions
+  *
+@verbatim
+===============================================================================
+            ##### Initialization and Configuration functions #####
+ ===============================================================================
+    [..]
+    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy
+    in asynchronous mode.
+      (+) For the asynchronous mode the parameters below can be configured:
+        (++) Baud Rate
+        (++) Word Length
+        (++) Stop Bit
+        (++) Parity: If the parity is enabled, then the MSB bit of the data written
+             in the data register is transmitted but is changed by the parity bit.
+        (++) Hardware flow control
+        (++) Receiver/transmitter modes
+        (++) Over Sampling Method
+        (++) One-Bit Sampling Method
+      (+) For the asynchronous mode, the following advanced features can be configured as well:
+        (++) TX and/or RX pin level inversion
+        (++) data logical level inversion
+        (++) RX and TX pins swap
+        (++) RX overrun detection disabling
+        (++) DMA disabling on RX error
+        (++) MSB first on communication line
+        (++) auto Baud rate detection
+    [..]
+    The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration
+     procedures (details for the procedures are available in reference manual).
+
+@endverbatim
+
+  Depending on the frame length defined by the M1 and M0 bits (7-bit,
+  8-bit or 9-bit), the possible UART formats are listed in the
+  following table.
+
+    Table 1. UART frame format.
+    +-----------------------------------------------------------------------+
+    |  M1 bit |  M0 bit |  PCE bit  |             UART frame                |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    0      |    | SB |    8 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    0      |    | SB |    9 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    0    |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    0      |    | SB |    7 bit data   | STB |     |
+    |---------|---------|-----------|---------------------------------------|
+    |    1    |    0    |    1      |    | SB | 6 bit data | PB | STB |     |
+    +-----------------------------------------------------------------------+
+
+  * @{
+  */
+
+/**
+  * @brief Initialize the RS485 Driver enable feature according to the specified
+  *         parameters in the UART_InitTypeDef and creates the associated handle.
+  * @param huart            UART handle.
+  * @param Polarity         Select the driver enable polarity.
+  *          This parameter can be one of the following values:
+  *          @arg @ref UART_DE_POLARITY_HIGH DE signal is active high
+  *          @arg @ref UART_DE_POLARITY_LOW  DE signal is active low
+  * @param AssertionTime    Driver Enable assertion time:
+  *       5-bit value defining the time between the activation of the DE (Driver Enable)
+  *       signal and the beginning of the start bit. It is expressed in sample time
+  *       units (1/8 or 1/16 bit time, depending on the oversampling rate)
+  * @param DeassertionTime  Driver Enable deassertion time:
+  *       5-bit value defining the time between the end of the last stop bit, in a
+  *       transmitted message, and the de-activation of the DE (Driver Enable) signal.
+  *       It is expressed in sample time units (1/8 or 1/16 bit time, depending on the
+  *       oversampling rate).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
+                                   uint32_t DeassertionTime)
+{
+  uint32_t temp;
+
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+  /* Check the Driver Enable UART instance */
+  assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance));
+
+  /* Check the Driver Enable polarity */
+  assert_param(IS_UART_DE_POLARITY(Polarity));
+
+  /* Check the Driver Enable assertion time */
+  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
+
+  /* Check the Driver Enable deassertion time */
+  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
+
+  if (huart->gState == HAL_UART_STATE_RESET)
+  {
+    /* Allocate lock resource and initialize it */
+    huart->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+    UART_InitCallbacksToDefault(huart);
+
+    if (huart->MspInitCallback == NULL)
+    {
+      huart->MspInitCallback = HAL_UART_MspInit;
+    }
+
+    /* Init the low level hardware */
+    huart->MspInitCallback(huart);
+#else
+    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
+    HAL_UART_MspInit(huart);
+#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
+  }
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Perform advanced settings configuration */
+  /* For some items, configuration requires to be done prior TE and RE bits are set */
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+  {
+    UART_AdvFeatureConfig(huart);
+  }
+
+  /* Set the UART Communication parameters */
+  if (UART_SetConfig(huart) == HAL_ERROR)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
+  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+
+  /* Set the Driver Enable polarity */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+
+  /* Set the Driver Enable assertion and deassertion times */
+  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions
+  *  @brief Extended functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    This subsection provides a set of Wakeup and FIFO mode related callback functions.
+
+    (#) Wakeup from Stop mode Callback:
+        (+) HAL_UARTEx_WakeupCallback()
+
+    (#) TX/RX Fifos Callbacks:
+        (+) HAL_UARTEx_RxFifoFullCallback()
+        (+) HAL_UARTEx_TxFifoEmptyCallback()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief UART wakeup from Stop mode callback.
+  * @param huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_WakeupCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART RX Fifo full callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  UART TX Fifo empty callback.
+  * @param  huart UART handle.
+  * @retval None
+  */
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(huart);
+
+  /* NOTE : This function should not be modified, when the callback is needed,
+            the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions
+  * @brief    Extended Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### Peripheral Control functions #####
+ ===============================================================================
+    [..] This section provides the following functions:
+     (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address
+         detection length to more than 4 bits for multiprocessor address mark wake up.
+     (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode
+         trigger: address match, Start Bit detection or RXNE bit status.
+     (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode
+     (+) HAL_UARTEx_DisableStopMode() API disables the above functionality
+     (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode
+     (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode
+     (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold
+     (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold
+
+    [..] This subsection also provides a set of additional functions providing enhanced reception
+    services to user. (For example, these functions allow application to handle use cases
+    where number of data to be received is unknown).
+
+    (#) Compared to standard reception services which only consider number of received
+        data elements as reception completion criteria, these functions also consider additional events
+        as triggers for updating reception status to caller :
+       (+) Detection of inactivity period (RX line has not been active for a given period).
+          (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state)
+               for 1 frame time, after last received byte.
+          (++) RX inactivity detected by RTO, i.e. line has been in idle state
+               for a programmable time, after last received byte.
+       (+) Detection that a specific character has been received.
+
+    (#) There are two mode of transfer:
+       (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received,
+           or till IDLE event occurs. Reception is handled only during function execution.
+           When function exits, no data reception could occur. HAL status and number of actually received data elements,
+           are returned by function after finishing transfer.
+       (+) Non-Blocking mode: The reception is performed using Interrupts or DMA.
+           These API's return the HAL status.
+           The end of the data processing will be indicated through the
+           dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode.
+           The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process
+           The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected.
+
+    (#) Blocking mode API:
+        (+) HAL_UARTEx_ReceiveToIdle()
+
+    (#) Non-Blocking mode API with Interrupt:
+        (+) HAL_UARTEx_ReceiveToIdle_IT()
+
+    (#) Non-Blocking mode API with DMA:
+        (+) HAL_UARTEx_ReceiveToIdle_DMA()
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief By default in multiprocessor mode, when the wake up method is set
+  *        to address mark, the UART handles only 4-bit long addresses detection;
+  *        this API allows to enable longer addresses detection (6-, 7- or 8-bit
+  *        long).
+  * @note  Addresses detection lengths are: 6-bit address detection in 7-bit data mode,
+  *        7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode.
+  * @param huart         UART handle.
+  * @param AddressLength This parameter can be one of the following values:
+  *          @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address
+  *          @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength)
+{
+  /* Check the UART handle allocation */
+  if (huart == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the address length parameter */
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength));
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength);
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* TEACK and/or REACK to check before moving huart->gState to Ready */
+  return (UART_CheckIdleState(huart));
+}
+
+/**
+  * @brief Set Wakeup from Stop mode interrupt flag selection.
+  * @note It is the application responsibility to enable the interrupt used as
+  *       usart_wkup interrupt source before entering low-power mode.
+  * @param huart           UART handle.
+  * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status.
+  *          This parameter can be one of the following values:
+  *          @arg @ref UART_WAKEUP_ON_ADDRESS
+  *          @arg @ref UART_WAKEUP_ON_STARTBIT
+  *          @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+  uint32_t tickstart;
+
+  /* check the wake-up from stop mode UART instance */
+  assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance));
+  /* check the wake-up selection parameter */
+  assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Disable the Peripheral */
+  __HAL_UART_DISABLE(huart);
+
+  /* Set the wake-up selection scheme */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent);
+
+  if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS)
+  {
+    UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection);
+  }
+
+  /* Enable the Peripheral */
+  __HAL_UART_ENABLE(huart);
+
+  /* Init tickstart for timeout management */
+  tickstart = HAL_GetTick();
+
+  /* Wait until REACK flag is set */
+  if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+  {
+    status = HAL_TIMEOUT;
+  }
+  else
+  {
+    /* Initialize the UART State */
+    huart->gState = HAL_UART_STATE_READY;
+  }
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return status;
+}
+
+/**
+  * @brief Enable UART Stop Mode.
+  * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  /* Set UESM bit */
+  ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Disable UART Stop Mode.
+  * @param huart UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart)
+{
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  /* Clear UESM bit */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM);
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Enable FIFO mode */
+  SET_BIT(tmpcr1, USART_CR1_FIFOEN);
+  huart->FifoMode = UART_FIFOMODE_ENABLE;
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the FIFO mode.
+  * @param huart      UART handle.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Disable FIFO mode */
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+  huart->FifoMode = UART_FIFOMODE_DISABLE;
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the TXFIFO threshold.
+  * @param huart      UART handle.
+  * @param Threshold  TX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_4
+  *            @arg @ref UART_TXFIFO_THRESHOLD_1_2
+  *            @arg @ref UART_TXFIFO_THRESHOLD_3_4
+  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Update TX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief  Set the RXFIFO threshold.
+  * @param huart      UART handle.
+  * @param Threshold  RX FIFO threshold value
+  *          This parameter can be one of the following values:
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_4
+  *            @arg @ref UART_RXFIFO_THRESHOLD_1_2
+  *            @arg @ref UART_RXFIFO_THRESHOLD_3_4
+  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
+  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+{
+  uint32_t tmpcr1;
+
+  /* Check the parameters */
+  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
+  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
+
+  /* Process Locked */
+  __HAL_LOCK(huart);
+
+  huart->gState = HAL_UART_STATE_BUSY;
+
+  /* Save actual UART configuration */
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+
+  /* Disable UART */
+  __HAL_UART_DISABLE(huart);
+
+  /* Update RX threshold configuration */
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+
+  /* Determine the number of data to process during RX/TX ISR execution */
+  UARTEx_SetNbDataToProcess(huart);
+
+  /* Restore UART configuration */
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+
+  huart->gState = HAL_UART_STATE_READY;
+
+  /* Process Unlocked */
+  __HAL_UNLOCK(huart);
+
+  return HAL_OK;
+}
+
+/**
+  * @brief Receive an amount of data in blocking mode till either the expected number of data
+  *        is received or an IDLE event occurs.
+  * @note  HAL_OK is returned if reception is completed (expected number of data has been received)
+  *        or if reception is stopped after IDLE event (less than the expected number of data has been received)
+  *        In this case, RxLen output parameter indicates number of data available in reception buffer.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *        of uint16_t available through pData.
+  * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO
+  *       is not empty. Read operations from the RDR register are performed when
+  *       RXFNE flag is set. From hardware perspective, RXFNE flag and
+  *       RXNE are mapped on the same bit-field.
+  * @param huart   UART handle.
+  * @param pData   Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size    Amount of data elements (uint8_t or uint16_t) to be received.
+  * @param RxLen   Number of data elements finally received
+  *                (could be lower than Size, in case reception ends on IDLE event)
+  * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence).
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen,
+                                           uint32_t Timeout)
+{
+  uint8_t  *pdata8bits;
+  uint16_t *pdata16bits;
+  uint16_t uhMask;
+  uint32_t tickstart;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return  HAL_ERROR;
+    }
+
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+    huart->RxState = HAL_UART_STATE_BUSY_RX;
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+    /* Init tickstart for timeout management */
+    tickstart = HAL_GetTick();
+
+    huart->RxXferSize  = Size;
+    huart->RxXferCount = Size;
+
+    /* Computation of UART mask to apply to RDR register */
+    UART_MASK_COMPUTATION(huart);
+    uhMask = huart->Mask;
+
+    /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+    {
+      pdata8bits  = NULL;
+      pdata16bits = (uint16_t *) pData;
+    }
+    else
+    {
+      pdata8bits  = pData;
+      pdata16bits = NULL;
+    }
+
+    /* Initialize output number of received elements */
+    *RxLen = 0U;
+
+    /* as long as data have to be received */
+    while (huart->RxXferCount > 0U)
+    {
+      /* Check if IDLE flag is set */
+      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE))
+      {
+        /* Clear IDLE flag in ISR */
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+
+        /* If Set, but no data ever received, clear flag without exiting loop */
+        /* If Set, and data has already been received, this means Idle Event is valid : End reception */
+        if (*RxLen > 0U)
+        {
+          huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+          huart->RxState = HAL_UART_STATE_READY;
+
+          return HAL_OK;
+        }
+      }
+
+      /* Check if RXNE flag is set */
+      if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE))
+      {
+        if (pdata8bits == NULL)
+        {
+          *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask);
+          pdata16bits++;
+        }
+        else
+        {
+          *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask);
+          pdata8bits++;
+        }
+        /* Increment number of received elements */
+        *RxLen += 1U;
+        huart->RxXferCount--;
+      }
+
+      /* Check for the Timeout */
+      if (Timeout != HAL_MAX_DELAY)
+      {
+        if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
+        {
+          huart->RxState = HAL_UART_STATE_READY;
+
+          return HAL_TIMEOUT;
+        }
+      }
+    }
+
+    /* Set number of received elements in output parameter : RxLen */
+    *RxLen = huart->RxXferSize - huart->RxXferCount;
+    /* At end of Rx process, restore huart->RxState to Ready */
+    huart->RxState = HAL_UART_STATE_READY;
+
+    return HAL_OK;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in interrupt mode till either the expected number of data
+  *        is received or an IDLE event occurs.
+  * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
+  *        to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating
+  *        number of received data elements.
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *        of uint16_t available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Reception type to reception till IDLE Event*/
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+    (void)UART_Start_Receive_IT(huart, pData, Size);
+
+    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+    {
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+      ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+    }
+    else
+    {
+      /* In case of errors already pending when reception is started,
+         Interrupts may have already been raised and lead to reception abortion.
+         (Overrun error for instance).
+         In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+      status = HAL_ERROR;
+    }
+
+    return status;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Receive an amount of data in DMA mode till either the expected number
+  *        of data is received or an IDLE event occurs.
+  * @note  Reception is initiated by this function call. Further progress of reception is achieved thanks
+  *        to DMA services, transferring automatically received data elements in user reception buffer and
+  *        calling registered callbacks at half/end of reception. UART IDLE events are also used to consider
+  *        reception phase as ended. In all cases, callback execution will indicate number of received data elements.
+  * @note  When the UART parity is enabled (PCE = 1), the received data contain
+  *        the parity bit (MSB position).
+  * @note  When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
+  *        the received data is handled as a set of uint16_t. In this case, Size must indicate the number
+  *        of uint16_t available through pData.
+  * @param huart UART handle.
+  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
+  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
+{
+  HAL_StatusTypeDef status;
+
+  /* Check that a Rx process is not already ongoing */
+  if (huart->RxState == HAL_UART_STATE_READY)
+  {
+    if ((pData == NULL) || (Size == 0U))
+    {
+      return HAL_ERROR;
+    }
+
+    /* Set Reception type to reception till IDLE Event*/
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
+
+    status =  UART_Start_Receive_DMA(huart, pData, Size);
+
+    /* Check Rx process has been successfully started */
+    if (status == HAL_OK)
+    {
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+      {
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+      }
+      else
+      {
+        /* In case of errors already pending when reception is started,
+           Interrupts may have already been raised and lead to reception abortion.
+           (Overrun error for instance).
+           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
+        status = HAL_ERROR;
+      }
+    }
+
+    return status;
+  }
+  else
+  {
+    return HAL_BUSY;
+  }
+}
+
+/**
+  * @brief Provide Rx Event type that has lead to RxEvent callback execution.
+  * @note  When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress
+  *        of reception process is provided to application through calls of Rx Event callback (either default one
+  *        HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event,
+  *        Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead
+  *        to Rx Event callback execution.
+  * @note  This function is expected to be called within the user implementation of Rx Event Callback,
+  *        in order to provide the accurate value :
+  *        In Interrupt Mode :
+  *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+  *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+  *             received data is lower than expected one)
+  *        In DMA Mode :
+  *           - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received)
+  *           - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received
+  *           - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of
+  *             received data is lower than expected one).
+  *        In DMA mode, RxEvent callback could be called several times;
+  *        When DMA is configured in Normal Mode, HT event does not stop Reception process;
+  *        When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process;
+  * @param  huart UART handle.
+  * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
+  */
+HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
+{
+  /* Return Rx Event type value, as stored in UART handle */
+  return (huart->RxEventType);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup UARTEx_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection.
+  * @param huart           UART handle.
+  * @param WakeUpSelection UART wake up from stop mode parameters.
+  * @retval None
+  */
+static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection)
+{
+  assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength));
+
+  /* Set the USART address length */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength);
+
+  /* Set the USART address node */
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS));
+}
+
+/**
+  * @brief Calculate the number of data to process in RX/TX ISR.
+  * @note The RX FIFO depth and the TX FIFO depth is extracted from
+  *       the UART configuration registers.
+  * @param huart UART handle.
+  * @retval None
+  */
+static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
+{
+  uint8_t rx_fifo_depth;
+  uint8_t tx_fifo_depth;
+  uint8_t rx_fifo_threshold;
+  uint8_t tx_fifo_threshold;
+  static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
+  static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
+
+  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+  {
+    huart->NbTxDataToProcess = 1U;
+    huart->NbRxDataToProcess = 1U;
+  }
+  else
+  {
+    rx_fifo_depth = RX_FIFO_DEPTH;
+    tx_fifo_depth = TX_FIFO_DEPTH;
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+                               (uint16_t)denominator[tx_fifo_threshold];
+    huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
+                               (uint16_t)denominator[rx_fifo_threshold];
+  }
+}
+/**
+  * @}
+  */
+
+#endif /* HAL_UART_MODULE_ENABLED */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c
new file mode 100644
index 0000000..092a253
--- /dev/null
+++ b/code/Drivers/STM32G4xx_HAL_Driver/Src/stm32g4xx_ll_adc.c
@@ -0,0 +1,1419 @@
+/**
+  ******************************************************************************
+  * @file    stm32g4xx_ll_adc.c
+  * @author  MCD Application Team
+  * @brief   ADC LL module driver
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2019 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+#if defined(USE_FULL_LL_DRIVER)
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32g4xx_ll_adc.h"
+#include "stm32g4xx_ll_bus.h"
+
+#ifdef  USE_FULL_ASSERT
+#include "stm32_assert.h"
+#else
+#define assert_param(expr) ((void)0U)
+#endif /* USE_FULL_ASSERT */
+
+/** @addtogroup STM32G4xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4) || defined (ADC5)
+
+/** @addtogroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @addtogroup ADC_LL_Private_Constants
+  * @{
+  */
+
+/* Definitions of ADC hardware constraints delays */
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
+/*       not timeout values:                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout     */
+/*       values definition.                                                   */
+/* Note: ADC timeout values are defined here in CPU cycles to be independent  */
+/*       of device clock setting.                                             */
+/*       In user application, ADC timeout values should be defined with       */
+/*       temporal values, in function of device clock settings.               */
+/*       Highest ratio CPU clock frequency vs ADC clock frequency:            */
+/*        - ADC clock from synchronous clock with AHB prescaler 512,          */
+/*          ADC prescaler 4.                                                  */
+/*           Ratio max = 512 *4 = 2048                                        */
+/*        - ADC clock from asynchronous clock (PLLP) with prescaler 256.      */
+/*          Highest CPU clock PLL (PLLR).                                     */
+/*           Ratio max = PLLRmax /PPLPmin * 256 = (VCO/2) / (VCO/31) * 256    */
+/*                     = 3968                                                 */
+/* Unit: CPU cycles.                                                          */
+#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST          (3968UL)
+#define ADC_TIMEOUT_DISABLE_CPU_CYCLES          (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES  (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1UL)
+
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @addtogroup ADC_LL_Private_Macros
+  * @{
+  */
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* common to several ADC instances.                                           */
+#define IS_LL_ADC_COMMON_CLOCK(__CLOCK__)                                      \
+  (((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2)                             \
+   || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4)                             \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV2)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV4)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV6)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV8)                                 \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV10)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV12)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV16)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV32)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV64)                                \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV128)                               \
+   || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV256)                               \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC instance.                                                              */
+#define IS_LL_ADC_RESOLUTION(__RESOLUTION__)                                   \
+  (((__RESOLUTION__) == LL_ADC_RESOLUTION_12B)                                 \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B)                              \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B)                               \
+   || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B)                               \
+  )
+
+#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__)                                   \
+  (((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT)                               \
+   || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT)                             \
+  )
+
+#define IS_LL_ADC_LOW_POWER(__LOW_POWER__)                                     \
+  (((__LOW_POWER__) == LL_ADC_LP_MODE_NONE)                                    \
+   || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT)                                  \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC group regular                                                          */
+#if defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)               \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG5)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG6)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG7)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG8)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG9)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG10)               \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2)           \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3)           \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         \
+          )                                                                    \
+      )                                                                        \
+   || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2)          \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG2)          \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG4)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)               \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2)           \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3)           \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         \
+          )                                                                    \
+      )                                                                        \
+   || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#elif defined(STM32G471xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         \
+          )                                                                    \
+      )                                                                        \
+   || (((__ADC_INSTANCE__) == ADC3) \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)               \
+  )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__)       \
+  (((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE)                         \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3)                  \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO)                \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRGO2)               \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1)                 \
+   || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2)           \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3)           \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11)         \
+          )                                                                    \
+      )                                                                        \
+   || (((__ADC_INSTANCE__) == ADC3)                                            \
+       && (                                                                    \
+            ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1)            \
+         || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#endif /* STM32G4xx */
+
+#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__)                 \
+  (((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE)                       \
+   || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS)                \
+  )
+
+#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__)                       \
+  (((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE)                    \
+   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED)              \
+   || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED)            \
+  )
+
+#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__)             \
+  (((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED)              \
+   || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN)         \
+  )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__)                 \
+  (((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE)                  \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS)         \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS)        \
+   || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS)        \
+  )
+
+#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__)          \
+  (((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE)              \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK)             \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS)            \
+   || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS)            \
+  )
+
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* ADC group injected                                                         */
+#if defined(STM32G474xx) || defined(STM32G484xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
+  (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)               \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG5)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG6)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG7)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG8)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG9)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG10)               \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)         \
+          )                                                                    \
+      )                                                                        \
+   || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG1)          \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG3)          \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#elif defined(STM32G473xx) || defined(STM32G483xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
+  (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)               \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)         \
+          )                                                                    \
+      )                                                                        \
+   || ((((__ADC_INSTANCE__) == ADC3) || ((__ADC_INSTANCE__) == ADC4) || ((__ADC_INSTANCE__) == ADC5)) \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#elif defined(STM32G471xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
+  (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)         \
+          )                                                                    \
+      )                                                                        \
+   || ((((__ADC_INSTANCE__) == ADC3)) \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#elif defined(STM32G411xB) || defined(STM32G411xC) || defined(STM32G414xx) || defined(STM32GBK1CB) || defined(STM32G431xx) || defined(STM32G441xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
+  (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)               \
+  )
+#elif defined(STM32G491xx) || defined(STM32G4A1xx)
+#define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__)       \
+  (((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE)                         \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)                 \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4)                  \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO)                \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2)               \
+   || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_LPTIM_OUT)                 \
+   || ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2))          \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM16_CH1)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)         \
+          )                                                                    \
+      )                                                                        \
+   || ((((__ADC_INSTANCE__) == ADC3))                                          \
+       && (                                                                    \
+            ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2)            \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2)           \
+         || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE3)          \
+          )                                                                    \
+      )                                                                        \
+  )
+#endif /* STM32G4xx */
+
+#define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__)                     \
+  (((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING)                     \
+   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING)                 \
+   || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING)           \
+  )
+
+#define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__)                             \
+  (((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT)                        \
+   || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR)                \
+  )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__)                 \
+  (((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE)                  \
+   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS)         \
+   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS)         \
+   || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS)         \
+  )
+
+#define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__)          \
+  (((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE)              \
+   || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK)             \
+  )
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+/* Check of parameters for configuration of ADC hierarchical scope:           */
+/* multimode.                                                                 */
+#define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__)                                   \
+  (((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT)                              \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN)                       \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM)                  \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT)                  \
+   || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM)                  \
+  )
+
+#define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__)                   \
+  (((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC)                 \
+   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B)       \
+   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B)         \
+   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B)       \
+   || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B)         \
+  )
+
+#define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__)                   \
+  (((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE)              \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)          \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES)         \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES)         \
+   || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES)         \
+  )
+
+#define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__)                   \
+  (((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER)                           \
+   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE)                         \
+   || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE)                  \
+  )
+
+#endif /* ADC_MULTIMODE_SUPPORT */
+/**
+  * @}
+  */
+
+
+/* Private function prototypes -----------------------------------------------*/
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_LL_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_LL_EF_Init
+  * @{
+  */
+
+/**
+  * @brief  De-initialize registers of all ADC instances belonging to
+  *         the same ADC common instance to their default reset values.
+  * @note   This function is performing a hard reset, using high level
+  *         clock source RCC ADC reset.
+  *         Caution: On this STM32 series, if several ADC instances are available
+  *         on the selected device, RCC ADC reset will reset
+  *         all ADC instances belonging to the common ADC instance.
+  *         To de-initialize only 1 ADC instance, use
+  *         function @ref LL_ADC_DeInit().
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC common registers are de-initialized
+  *          - ERROR: not applicable
+  */
+ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+
+  if (ADCxy_COMMON == ADC12_COMMON)
+  {
+    /* Force reset of ADC clock (core clock) */
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC12);
+
+    /* Release reset of ADC clock (core clock) */
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC12);
+  }
+#if defined(ADC345_COMMON)
+  else
+  {
+    /* Force reset of ADC clock (core clock) */
+    LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_ADC345);
+
+    /* Release reset of ADC clock (core clock) */
+    LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_ADC345);
+  }
+#endif /* ADC345_COMMON */
+
+  return SUCCESS;
+}
+
+/**
+  * @brief  Initialize some features of ADC common parameters
+  *         (all ADC instances belonging to the same ADC common instance)
+  *         and multimode (for devices with several ADC instances available).
+  * @note   The setting of ADC common parameters is conditioned to
+  *         ADC instances state:
+  *         All ADC instances belonging to the same ADC common instance
+  *         must be disabled.
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC common registers are initialized
+  *          - ERROR: ADC common registers are not initialized
+  */
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
+  assert_param(IS_LL_ADC_COMMON_CLOCK(pADC_CommonInitStruct->CommonClock));
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+  assert_param(IS_LL_ADC_MULTI_MODE(pADC_CommonInitStruct->Multimode));
+  if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+  {
+    assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(pADC_CommonInitStruct->MultiDMATransfer));
+    assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(pADC_CommonInitStruct->MultiTwoSamplingDelay));
+  }
+#endif /* ADC_MULTIMODE_SUPPORT */
+
+  /* Note: Hardware constraint (refer to description of functions             */
+  /*       "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"):               */
+  /*       On this STM32 series, setting of these features is conditioned to  */
+  /*       ADC state:                                                         */
+  /*       All ADC instances of the ADC common group must be disabled.        */
+  if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - common to several ADC                                               */
+    /*    (all ADC instances belonging to the same ADC common instance)       */
+    /*    - Set ADC clock (conversion clock)                                  */
+    /*  - multimode (if several ADC instances available on the                */
+    /*    selected device)                                                    */
+    /*    - Set ADC multimode configuration                                   */
+    /*    - Set ADC multimode DMA transfer                                    */
+    /*    - Set ADC multimode: delay between 2 sampling phases                */
+#if defined(ADC_MULTIMODE_SUPPORT)
+    if (pADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
+    {
+      MODIFY_REG(ADCxy_COMMON->CCR,
+                 ADC_CCR_CKMODE
+                 | ADC_CCR_PRESC
+                 | ADC_CCR_DUAL
+                 | ADC_CCR_MDMA
+                 | ADC_CCR_DELAY
+                 ,
+                 pADC_CommonInitStruct->CommonClock
+                 | pADC_CommonInitStruct->Multimode
+                 | pADC_CommonInitStruct->MultiDMATransfer
+                 | pADC_CommonInitStruct->MultiTwoSamplingDelay
+                );
+    }
+    else
+    {
+      MODIFY_REG(ADCxy_COMMON->CCR,
+                 ADC_CCR_CKMODE
+                 | ADC_CCR_PRESC
+                 | ADC_CCR_DUAL
+                 | ADC_CCR_MDMA
+                 | ADC_CCR_DELAY
+                 ,
+                 pADC_CommonInitStruct->CommonClock
+                 | LL_ADC_MULTI_INDEPENDENT
+                );
+    }
+#else
+    LL_ADC_SetCommonClock(ADCxy_COMMON, pADC_CommonInitStruct->CommonClock);
+#endif /* ADC_MULTIMODE_SUPPORT */
+  }
+  else
+  {
+    /* Initialization error: One or several ADC instances belonging to        */
+    /* the same ADC common instance are not disabled.                         */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_CommonInitTypeDef field to default value.
+  * @param  pADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
+  *                              whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct)
+{
+  /* Set pADC_CommonInitStruct fields to default values */
+  /* Set fields of ADC common */
+  /* (all ADC instances belonging to the same ADC common instance) */
+  pADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
+
+#if defined(ADC_MULTIMODE_SUPPORT)
+  /* Set fields of ADC multimode */
+  pADC_CommonInitStruct->Multimode             = LL_ADC_MULTI_INDEPENDENT;
+  pADC_CommonInitStruct->MultiDMATransfer      = LL_ADC_MULTI_REG_DMA_EACH_ADC;
+  pADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
+#endif /* ADC_MULTIMODE_SUPPORT */
+}
+
+/**
+  * @brief  De-initialize registers of the selected ADC instance
+  *         to their default reset values.
+  * @note   To reset all ADC instances quickly (perform a hard reset),
+  *         use function @ref LL_ADC_CommonDeInit().
+  * @note   If this functions returns error status, it means that ADC instance
+  *         is in an unknown state.
+  *         In this case, perform a hard reset using high level
+  *         clock source RCC ADC reset.
+  *         Caution: On this STM32 series, if several ADC instances are available
+  *         on the selected device, RCC ADC reset will reset
+  *         all ADC instances belonging to the common ADC instance.
+  *         Refer to function @ref LL_ADC_CommonDeInit().
+  * @param  ADCx ADC instance
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are de-initialized
+  *          - ERROR: ADC registers are not de-initialized
+  */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
+{
+  ErrorStatus status = SUCCESS;
+
+  __IO uint32_t timeout_cpu_cycles = 0UL;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+  /* Disable ADC instance if not already disabled.                            */
+  if (LL_ADC_IsEnabled(ADCx) == 1UL)
+  {
+    /* Stop potential ADC conversion on going on ADC group regular.           */
+    if (LL_ADC_REG_IsConversionOngoing(ADCx) != 0UL)
+    {
+      if (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0UL)
+      {
+        LL_ADC_REG_StopConversion(ADCx);
+      }
+    }
+
+    /* Stop potential ADC conversion on going on ADC group injected.          */
+    if (LL_ADC_INJ_IsConversionOngoing(ADCx) != 0UL)
+    {
+      if (LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0UL)
+      {
+        LL_ADC_INJ_StopConversion(ADCx);
+      }
+    }
+
+    /* Wait for ADC conversions are effectively stopped                       */
+    timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
+    while ((LL_ADC_REG_IsStopConversionOngoing(ADCx)
+            | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1UL)
+    {
+      timeout_cpu_cycles--;
+      if (timeout_cpu_cycles == 0UL)
+      {
+        /* Time-out error */
+        status = ERROR;
+        break;
+      }
+    }
+
+    /* Flush group injected contexts queue (register JSQR):                   */
+    /* Note: Bit JQM must be set to empty the contexts queue (otherwise       */
+    /*       contexts queue is maintained with the last active context).      */
+    LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
+
+    /* Disable the ADC instance */
+    LL_ADC_Disable(ADCx);
+
+    /* Wait for ADC instance is effectively disabled */
+    timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
+    while (LL_ADC_IsDisableOngoing(ADCx) == 1UL)
+    {
+      timeout_cpu_cycles--;
+      if (timeout_cpu_cycles == 0UL)
+      {
+        /* Time-out error */
+        status = ERROR;
+        break;
+      }
+    }
+  }
+
+  /* Check whether ADC state is compliant with expected state */
+  if (READ_BIT(ADCx->CR,
+               (ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
+                | ADC_CR_ADDIS | ADC_CR_ADEN)
+              )
+      == 0UL)
+  {
+    /* ========== Reset ADC registers ========== */
+    /* Reset register IER */
+    CLEAR_BIT(ADCx->IER,
+              (LL_ADC_IT_ADRDY
+               | LL_ADC_IT_EOC
+               | LL_ADC_IT_EOS
+               | LL_ADC_IT_OVR
+               | LL_ADC_IT_EOSMP
+               | LL_ADC_IT_JEOC
+               | LL_ADC_IT_JEOS
+               | LL_ADC_IT_JQOVF
+               | LL_ADC_IT_AWD1
+               | LL_ADC_IT_AWD2
+               | LL_ADC_IT_AWD3
+              )
+             );
+
+    /* Reset register ISR */
+    SET_BIT(ADCx->ISR,
+            (LL_ADC_FLAG_ADRDY
+             | LL_ADC_FLAG_EOC
+             | LL_ADC_FLAG_EOS
+             | LL_ADC_FLAG_OVR
+             | LL_ADC_FLAG_EOSMP
+             | LL_ADC_FLAG_JEOC
+             | LL_ADC_FLAG_JEOS
+             | LL_ADC_FLAG_JQOVF
+             | LL_ADC_FLAG_AWD1
+             | LL_ADC_FLAG_AWD2
+             | LL_ADC_FLAG_AWD3
+            )
+           );
+
+    /* Reset register CR */
+    /*  - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,  */
+    /*    ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in                      */
+    /*    access mode "read-set": no direct reset applicable.                 */
+    /*  - Reset Calibration mode to default setting (single ended).           */
+    /*  - Disable ADC internal voltage regulator.                             */
+    /*  - Enable ADC deep power down.                                         */
+    /*    Note: ADC internal voltage regulator disable and ADC deep power     */
+    /*          down enable are conditioned to ADC state disabled:            */
+    /*          already done above.                                           */
+    CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
+    SET_BIT(ADCx->CR, ADC_CR_DEEPPWD);
+
+    /* Reset register CFGR */
+    MODIFY_REG(ADCx->CFGR,
+               (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN
+                | ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
+                | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
+                | ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD
+                | ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN
+                | ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN),
+               ADC_CFGR_JQDIS
+              );
+
+    /* Reset register CFGR2 */
+    CLEAR_BIT(ADCx->CFGR2,
+              (ADC_CFGR2_ROVSM  | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS
+               | ADC_CFGR2_SWTRIG | ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG
+               | ADC_CFGR2_GCOMP
+               | ADC_CFGR2_OVSR   | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE)
+             );
+
+    /* Reset register SMPR1 */
+    CLEAR_BIT(ADCx->SMPR1,
+              (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
+               | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
+               | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
+             );
+
+    /* Reset register SMPR2 */
+    CLEAR_BIT(ADCx->SMPR2,
+              (ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
+               | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
+               | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
+             );
+
+    /* Reset register TR1 */
+    MODIFY_REG(ADCx->TR1, ADC_TR1_AWDFILT | ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
+
+    /* Reset register TR2 */
+    MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
+
+    /* Reset register TR3 */
+    MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
+
+    /* Reset register SQR1 */
+    CLEAR_BIT(ADCx->SQR1,
+              (ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
+               | ADC_SQR1_SQ1 | ADC_SQR1_L)
+             );
+
+    /* Reset register SQR2 */
+    CLEAR_BIT(ADCx->SQR2,
+              (ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
+               | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
+             );
+
+    /* Reset register SQR3 */
+    CLEAR_BIT(ADCx->SQR3,
+              (ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
+               | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
+             );
+
+    /* Reset register SQR4 */
+    CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
+
+    /* Reset register JSQR */
+    CLEAR_BIT(ADCx->JSQR,
+              (ADC_JSQR_JL
+               | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
+               | ADC_JSQR_JSQ4    | ADC_JSQR_JSQ3
+               | ADC_JSQR_JSQ2    | ADC_JSQR_JSQ1)
+             );
+
+    /* Reset register DR */
+    /* Note: bits in access mode read only, no direct reset applicable */
+
+    /* Reset register OFR1 */
+    CLEAR_BIT(ADCx->OFR1,
+              ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1 | ADC_OFR1_SATEN | ADC_OFR1_OFFSETPOS);
+    /* Reset register OFR2 */
+    CLEAR_BIT(ADCx->OFR2,
+              ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2 | ADC_OFR2_SATEN | ADC_OFR2_OFFSETPOS);
+    /* Reset register OFR3 */
+    CLEAR_BIT(ADCx->OFR3,
+              ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3 | ADC_OFR3_SATEN | ADC_OFR3_OFFSETPOS);
+    /* Reset register OFR4 */
+    CLEAR_BIT(ADCx->OFR4,
+              ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4 | ADC_OFR4_SATEN | ADC_OFR4_OFFSETPOS);
+
+    /* Reset registers JDR1, JDR2, JDR3, JDR4 */
+    /* Note: bits in access mode read only, no direct reset applicable */
+
+    /* Reset register AWD2CR */
+    CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
+
+    /* Reset register AWD3CR */
+    CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
+
+    /* Reset register DIFSEL */
+    CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
+
+    /* Reset register CALFACT */
+    CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
+
+    /* Reset register GCOMP */
+    CLEAR_BIT(ADCx->GCOMP, ADC_GCOMP_GCOMPCOEFF);
+  }
+  else
+  {
+    /* ADC instance is in an unknown state */
+    /* Need to performing a hard reset of ADC instance, using high level      */
+    /* clock source RCC ADC reset.                                            */
+    /* Caution: On this STM32 series, if several ADC instances are available  */
+    /*          on the selected device, RCC ADC reset will reset              */
+    /*          all ADC instances belonging to the common ADC instance.       */
+    /* Caution: On this STM32 series, if several ADC instances are available  */
+    /*          on the selected device, RCC ADC reset will reset              */
+    /*          all ADC instances belonging to the common ADC instance.       */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Initialize some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Affects both group regular and group injected (availability
+  *         of ADC group injected depends on STM32 series).
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 series. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, some other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group regular or group injected sequencer:
+  *            map channel on the selected sequencer rank.
+  *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  pADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+
+  assert_param(IS_LL_ADC_RESOLUTION(pADC_InitStruct->Resolution));
+  assert_param(IS_LL_ADC_DATA_ALIGN(pADC_InitStruct->DataAlignment));
+  assert_param(IS_LL_ADC_LOW_POWER(pADC_InitStruct->LowPowerMode));
+
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if (LL_ADC_IsEnabled(ADCx) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC instance                                                        */
+    /*    - Set ADC data resolution                                           */
+    /*    - Set ADC conversion data alignment                                 */
+    /*    - Set ADC low power mode                                            */
+    MODIFY_REG(ADCx->CFGR,
+               ADC_CFGR_RES
+               | ADC_CFGR_ALIGN
+               | ADC_CFGR_AUTDLY
+               ,
+               pADC_InitStruct->Resolution
+               | pADC_InitStruct->DataAlignment
+               | pADC_InitStruct->LowPowerMode
+              );
+
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_InitTypeDef field to default value.
+  * @param  pADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
+  *                        whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct)
+{
+  /* Set pADC_InitStruct fields to default values */
+  /* Set fields of ADC instance */
+  pADC_InitStruct->Resolution    = LL_ADC_RESOLUTION_12B;
+  pADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
+  pADC_InitStruct->LowPowerMode  = LL_ADC_LP_MODE_NONE;
+
+}
+
+/**
+  * @brief  Initialize some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 series. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group regular or group injected sequencer:
+  *            map channel on the selected sequencer rank.
+  *            Refer to function @ref LL_ADC_REG_SetSequencerRanks().
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @param  ADCx ADC instance
+  * @param  pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, pADC_RegInitStruct->TriggerSource));
+  assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(pADC_RegInitStruct->SequencerLength));
+  if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+  {
+    assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(pADC_RegInitStruct->SequencerDiscont));
+
+    /* ADC group regular continuous mode and discontinuous mode                 */
+    /* can not be enabled simultenaeously                                       */
+    assert_param((pADC_RegInitStruct->ContinuousMode == LL_ADC_REG_CONV_SINGLE)
+                 || (pADC_RegInitStruct->SequencerDiscont == LL_ADC_REG_SEQ_DISCONT_DISABLE));
+  }
+  assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(pADC_RegInitStruct->ContinuousMode));
+  assert_param(IS_LL_ADC_REG_DMA_TRANSFER(pADC_RegInitStruct->DMATransfer));
+  assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(pADC_RegInitStruct->Overrun));
+
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if (LL_ADC_IsEnabled(ADCx) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC group regular                                                   */
+    /*    - Set ADC group regular trigger source                              */
+    /*    - Set ADC group regular sequencer length                            */
+    /*    - Set ADC group regular sequencer discontinuous mode                */
+    /*    - Set ADC group regular continuous mode                             */
+    /*    - Set ADC group regular conversion data transfer: no transfer or    */
+    /*      transfer by DMA, and DMA requests mode                            */
+    /*    - Set ADC group regular overrun behavior                            */
+    /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by    */
+    /*       setting of trigger source to SW start.                           */
+    if (pADC_RegInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+    {
+      MODIFY_REG(ADCx->CFGR,
+                 ADC_CFGR_EXTSEL
+                 | ADC_CFGR_EXTEN
+                 | ADC_CFGR_DISCEN
+                 | ADC_CFGR_DISCNUM
+                 | ADC_CFGR_CONT
+                 | ADC_CFGR_DMAEN
+                 | ADC_CFGR_DMACFG
+                 | ADC_CFGR_OVRMOD
+                 ,
+                 pADC_RegInitStruct->TriggerSource
+                 | pADC_RegInitStruct->SequencerDiscont
+                 | pADC_RegInitStruct->ContinuousMode
+                 | pADC_RegInitStruct->DMATransfer
+                 | pADC_RegInitStruct->Overrun
+                );
+    }
+    else
+    {
+      MODIFY_REG(ADCx->CFGR,
+                 ADC_CFGR_EXTSEL
+                 | ADC_CFGR_EXTEN
+                 | ADC_CFGR_DISCEN
+                 | ADC_CFGR_DISCNUM
+                 | ADC_CFGR_CONT
+                 | ADC_CFGR_DMAEN
+                 | ADC_CFGR_DMACFG
+                 | ADC_CFGR_OVRMOD
+                 ,
+                 pADC_RegInitStruct->TriggerSource
+                 | LL_ADC_REG_SEQ_DISCONT_DISABLE
+                 | pADC_RegInitStruct->ContinuousMode
+                 | pADC_RegInitStruct->DMATransfer
+                 | pADC_RegInitStruct->Overrun
+                );
+    }
+
+    /* Set ADC group regular sequencer length and scan direction */
+    LL_ADC_REG_SetSequencerLength(ADCx, pADC_RegInitStruct->SequencerLength);
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_REG_InitTypeDef field to default value.
+  * @param  pADC_RegInitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
+  *                            whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct)
+{
+  /* Set pADC_RegInitStruct fields to default values */
+  /* Set fields of ADC group regular */
+  /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by      */
+  /*       setting of trigger source to SW start.                             */
+  pADC_RegInitStruct->TriggerSource    = LL_ADC_REG_TRIG_SOFTWARE;
+  pADC_RegInitStruct->SequencerLength  = LL_ADC_REG_SEQ_SCAN_DISABLE;
+  pADC_RegInitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
+  pADC_RegInitStruct->ContinuousMode   = LL_ADC_REG_CONV_SINGLE;
+  pADC_RegInitStruct->DMATransfer      = LL_ADC_REG_DMA_TRANSFER_NONE;
+  pADC_RegInitStruct->Overrun          = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
+}
+
+/**
+  * @brief  Initialize some features of ADC group injected.
+  * @note   These parameters have an impact on ADC scope: ADC group injected.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "INJ").
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 series. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  * @note   After using this function, other features must be configured
+  *         using LL unitary functions.
+  *         The minimum configuration remaining to be done is:
+  *          - Set ADC group injected sequencer:
+  *            map channel on the selected sequencer rank.
+  *            Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
+  *          - Set ADC channel sampling time
+  *            Refer to function LL_ADC_SetChannelSamplingTime();
+  * @note   Caution if feature ADC group injected contexts queue is enabled
+  *         (refer to with function @ref LL_ADC_INJ_SetQueueMode() ):
+  *         using successively several times this function will appear as
+  *         having no effect.
+  *         To set several features of ADC group injected, use
+  *         function @ref LL_ADC_INJ_ConfigQueueContext().
+  * @param  ADCx ADC instance
+  * @param  pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: ADC registers are initialized
+  *          - ERROR: ADC registers are not initialized
+  */
+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, const LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
+{
+  ErrorStatus status = SUCCESS;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(ADCx));
+  assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, pADC_InjInitStruct->TriggerSource));
+  assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(pADC_InjInitStruct->SequencerLength));
+  if (pADC_InjInitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
+  {
+    assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(pADC_InjInitStruct->SequencerDiscont));
+  }
+  assert_param(IS_LL_ADC_INJ_TRIG_AUTO(pADC_InjInitStruct->TrigAuto));
+
+  /* Note: Hardware constraint (refer to description of this function):       */
+  /*       ADC instance must be disabled.                                     */
+  if (LL_ADC_IsEnabled(ADCx) == 0UL)
+  {
+    /* Configuration of ADC hierarchical scope:                               */
+    /*  - ADC group injected                                                  */
+    /*    - Set ADC group injected trigger source                             */
+    /*    - Set ADC group injected sequencer length                           */
+    /*    - Set ADC group injected sequencer discontinuous mode               */
+    /*    - Set ADC group injected conversion trigger: independent or         */
+    /*      from ADC group regular                                            */
+    /* Note: On this STM32 series, ADC trigger edge is set to value 0x0 by    */
+    /*       setting of trigger source to SW start.                           */
+    if (pADC_InjInitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
+    {
+      MODIFY_REG(ADCx->CFGR,
+                 ADC_CFGR_JDISCEN
+                 | ADC_CFGR_JAUTO
+                 ,
+                 pADC_InjInitStruct->SequencerDiscont
+                 | pADC_InjInitStruct->TrigAuto
+                );
+    }
+    else
+    {
+      MODIFY_REG(ADCx->CFGR,
+                 ADC_CFGR_JDISCEN
+                 | ADC_CFGR_JAUTO
+                 ,
+                 LL_ADC_REG_SEQ_DISCONT_DISABLE
+                 | pADC_InjInitStruct->TrigAuto
+                );
+    }
+
+    MODIFY_REG(ADCx->JSQR,
+               ADC_JSQR_JEXTSEL
+               | ADC_JSQR_JEXTEN
+               | ADC_JSQR_JL
+               ,
+               pADC_InjInitStruct->TriggerSource
+               | pADC_InjInitStruct->SequencerLength
+              );
+  }
+  else
+  {
+    /* Initialization error: ADC instance is not disabled. */
+    status = ERROR;
+  }
+  return status;
+}
+
+/**
+  * @brief  Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
+  * @param  pADC_InjInitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
+  *                            whose fields will be set to default values.
+  * @retval None
+  */
+void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *pADC_InjInitStruct)
+{
+  /* Set pADC_InjInitStruct fields to default values */
+  /* Set fields of ADC group injected */
+  pADC_InjInitStruct->TriggerSource    = LL_ADC_INJ_TRIG_SOFTWARE;
+  pADC_InjInitStruct->SequencerLength  = LL_ADC_INJ_SEQ_SCAN_DISABLE;
+  pADC_InjInitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
+  pADC_InjInitStruct->TrigAuto         = LL_ADC_INJ_TRIG_INDEPENDENT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 || ADC2 || ADC3 || ADC4 || ADC5 */
+
+/**
+  * @}
+  */
+
+#endif /* USE_FULL_LL_DRIVER */
diff --git a/kicad/c64psu/#auto_saved_files# b/kicad/c64psu/#auto_saved_files#
new file mode 100644
index 0000000..1ab9e60
--- /dev/null
+++ b/kicad/c64psu/#auto_saved_files#
@@ -0,0 +1 @@
+C:\Users\janik\C64PSU\kicad\c64psu\_autosave-c64psu.kicad_sch
diff --git a/kicad/c64psu/c64psu-backups/c64psu-2025-08-11_151728.zip b/kicad/c64psu/c64psu-backups/c64psu-2025-08-11_151728.zip
deleted file mode 100644
index 868ce68e2a42dd6eb7b0e948209b1ec8f0a7a437..0000000000000000000000000000000000000000
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new file mode 100644
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literal 0
HcmV?d00001

diff --git a/kicad/c64psu/c64psu.kicad_pcb b/kicad/c64psu/c64psu.kicad_pcb
index 248a1c0..3bfdc29 100644
--- a/kicad/c64psu/c64psu.kicad_pcb
+++ b/kicad/c64psu/c64psu.kicad_pcb
@@ -145,111 +145,94 @@
 	(net 2 "V_USB")
 	(net 3 "15V")
 	(net 4 "5V")
-	(net 5 "SW")
-	(net 6 "Net-(U1-BST)")
-	(net 7 "Net-(U1-EN{slash}UVLO)")
-	(net 8 "Net-(U1-ILIM)")
-	(net 9 "Net-(U1-FB)")
-	(net 10 "Net-(C15-Pad2)")
-	(net 11 "Net-(C16-Pad2)")
-	(net 12 "Net-(U1-COMP)")
-	(net 13 "Net-(U1-RT)")
-	(net 14 "Net-(U1-SS{slash}TRK)")
-	(net 15 "9VAC2")
-	(net 16 "9VAC1")
-	(net 17 "V_REF = 2.048 | 2.5 | 2.9")
-	(net 18 "9VAC_OUT2")
-	(net 19 "9VAC_OUT1")
-	(net 20 "3.3V")
-	(net 21 "VDDA")
-	(net 22 "LV_VCC")
-	(net 23 "Net-(IC1-V5V)")
-	(net 24 "Net-(D1-A)")
-	(net 25 "Net-(IC1-VOUT)")
-	(net 26 "Net-(IC1-VSEL)")
-	(net 27 "unconnected-(IC1-FLIP-Pad6)")
-	(net 28 "DN")
-	(net 29 "Net-(IC1-PWR_EN)")
-	(net 30 "Net-(IC1-LED)")
-	(net 31 "Net-(IC1-VCC)")
-	(net 32 "Net-(IC1-ISEL)")
-	(net 33 "DP")
-	(net 34 "CC1")
-	(net 35 "CC2")
-	(net 36 "unconnected-(J1-SBU1-PadA8)")
-	(net 37 "unconnected-(J1-SBU2-PadB8)")
-	(net 38 "NRST")
-	(net 39 "JTDI")
-	(net 40 "VCP_TX")
-	(net 41 "unconnected-(J3-NC-Pad2)")
-	(net 42 "JTMS")
-	(net 43 "unconnected-(J3-NC-Pad1)")
-	(net 44 "unconnected-(J3-JRCLK{slash}NC-Pad9)")
-	(net 45 "VCP_RX")
-	(net 46 "JTDO")
-	(net 47 "Net-(Q1-Pad4)")
-	(net 48 "Net-(Q1-Pad5_8)")
-	(net 49 "Net-(Q6-Pad4)")
-	(net 50 "Net-(Q7-Pad4)")
-	(net 51 "G3")
-	(net 52 "G4")
-	(net 53 "G1")
-	(net 54 "G2")
-	(net 55 "Net-(U1-HO)")
-	(net 56 "Net-(U1-LO)")
-	(net 57 "Net-(U1-PGOOD)")
-	(net 58 "Net-(U1-SYNCIN)")
-	(net 59 "Net-(U3-+)")
-	(net 60 "Net-(U3--)")
-	(net 61 "1.225V")
-	(net 62 "OSC_OUT")
-	(net 63 "PWM_G1")
-	(net 64 "PWM_G2")
-	(net 65 "PWM_G4")
-	(net 66 "PWM_G3")
-	(net 67 "unconnected-(U1-SYNCOUT-Pad7)")
-	(net 68 "unconnected-(U1-NC-Pad9)")
-	(net 69 "unconnected-(U1-NC-Pad16)")
-	(net 70 "unconnected-(U2-PA1-Pad9)")
-	(net 71 "unconnected-(U2-PB9-Pad46)")
-	(net 72 "unconnected-(U2-PC15-Pad4)")
-	(net 73 "OSC_IN")
-	(net 74 "unconnected-(U2-PA3-Pad11)")
-	(net 75 "unconnected-(U2-PB4-Pad41)")
-	(net 76 "unconnected-(U2-PB15-Pad29)")
-	(net 77 "unconnected-(U2-PB0-Pad16)")
-	(net 78 "unconnected-(U2-PB2-Pad18)")
-	(net 79 "unconnected-(U2-PB5-Pad42)")
-	(net 80 "9VAC_COMP_ADC")
-	(net 81 "unconnected-(U2-PA2-Pad10)")
-	(net 82 "unconnected-(U2-PA7-Pad15)")
-	(net 83 "JTCLK")
-	(net 84 "unconnected-(U2-PG10-Pad7)")
-	(net 85 "unconnected-(U2-PA0-Pad8)")
-	(net 86 "unconnected-(U2-PA6-Pad14)")
-	(net 87 "unconnected-(U2-PC13-Pad2)")
-	(net 88 "unconnected-(U2-PA12-Pad34)")
-	(net 89 "unconnected-(U2-PB8-Pad45)")
-	(net 90 "unconnected-(U2-PA5-Pad13)")
-	(net 91 "unconnected-(U2-PB1-Pad17)")
-	(net 92 "unconnected-(U2-PB10-Pad22)")
-	(net 93 "unconnected-(U2-PC14-Pad3)")
-	(net 94 "unconnected-(U2-PA4-Pad12)")
-	(net 95 "ENABLE_DRVA")
-	(net 96 "ENABLE_DRVB")
-	(net 97 "unconnected-(U6-NC-Pad4)")
-	(net 98 "CURRENT_COMP_ADC")
-	(net 99 "unconnected-(U7-NC-Pad3)")
-	(net 100 "unconnected-(U8-NC-Pad4)")
-	(net 101 "Net-(L2-Pad1)")
-	(net 102 "Net-(L3-Pad1)")
-	(net 103 "Net-(U6-+IN)")
+	(net 5 "9VAC2")
+	(net 6 "9VAC1")
+	(net 7 "V_REF = 2.048 | 2.5 | 2.9")
+	(net 8 "9VAC_OUT2")
+	(net 9 "9VAC_OUT1")
+	(net 10 "3.3V")
+	(net 11 "VDDA")
+	(net 12 "Net-(IC1-V5V)")
+	(net 13 "Net-(D1-A)")
+	(net 14 "Net-(IC1-VOUT)")
+	(net 15 "Net-(IC1-VSEL)")
+	(net 16 "unconnected-(IC1-FLIP-Pad6)")
+	(net 17 "DN")
+	(net 18 "Net-(IC1-PWR_EN)")
+	(net 19 "Net-(IC1-LED)")
+	(net 20 "Net-(IC1-VCC)")
+	(net 21 "Net-(IC1-ISEL)")
+	(net 22 "DP")
+	(net 23 "CC1")
+	(net 24 "CC2")
+	(net 25 "unconnected-(J1-SBU1-PadA8)")
+	(net 26 "unconnected-(J1-SBU2-PadB8)")
+	(net 27 "NRST")
+	(net 28 "JTDI")
+	(net 29 "VCP_TX")
+	(net 30 "unconnected-(J3-NC-Pad2)")
+	(net 31 "JTMS")
+	(net 32 "unconnected-(J3-NC-Pad1)")
+	(net 33 "unconnected-(J3-JRCLK{slash}NC-Pad9)")
+	(net 34 "VCP_RX")
+	(net 35 "JTDO")
+	(net 36 "Net-(Q1-Pad4)")
+	(net 37 "Net-(Q1-Pad5_8)")
+	(net 38 "G3")
+	(net 39 "G4")
+	(net 40 "G1")
+	(net 41 "G2")
+	(net 42 "Net-(U3-+)")
+	(net 43 "Net-(U3--)")
+	(net 44 "1.225V")
+	(net 45 "OSC_OUT")
+	(net 46 "PWM_G1")
+	(net 47 "PWM_G2")
+	(net 48 "PWM_G4")
+	(net 49 "PWM_G3")
+	(net 50 "unconnected-(U2-PA1-Pad9)")
+	(net 51 "unconnected-(U2-PB9-Pad46)")
+	(net 52 "unconnected-(U2-PC15-Pad4)")
+	(net 53 "OSC_IN")
+	(net 54 "unconnected-(U2-PA3-Pad11)")
+	(net 55 "unconnected-(U2-PB4-Pad41)")
+	(net 56 "unconnected-(U2-PB15-Pad29)")
+	(net 57 "unconnected-(U2-PB0-Pad16)")
+	(net 58 "unconnected-(U2-PB2-Pad18)")
+	(net 59 "unconnected-(U2-PB5-Pad42)")
+	(net 60 "9VAC_COMP_ADC")
+	(net 61 "unconnected-(U2-PA2-Pad10)")
+	(net 62 "unconnected-(U2-PA7-Pad15)")
+	(net 63 "JTCLK")
+	(net 64 "unconnected-(U2-PG10-Pad7)")
+	(net 65 "unconnected-(U2-PA0-Pad8)")
+	(net 66 "unconnected-(U2-PA6-Pad14)")
+	(net 67 "unconnected-(U2-PC13-Pad2)")
+	(net 68 "unconnected-(U2-PA12-Pad34)")
+	(net 69 "unconnected-(U2-PB8-Pad45)")
+	(net 70 "unconnected-(U2-PA5-Pad13)")
+	(net 71 "unconnected-(U2-PB1-Pad17)")
+	(net 72 "unconnected-(U2-PB10-Pad22)")
+	(net 73 "unconnected-(U2-PC14-Pad3)")
+	(net 74 "unconnected-(U2-PA4-Pad12)")
+	(net 75 "ENABLE_DRVA")
+	(net 76 "ENABLE_DRVB")
+	(net 77 "CURRENT_COMP_ADC")
+	(net 78 "unconnected-(U7-NC-Pad3)")
+	(net 79 "unconnected-(U8-NC-Pad4)")
+	(net 80 "Net-(L2-Pad1)")
+	(net 81 "Net-(L3-Pad1)")
+	(net 82 "Net-(IC2-SW)")
+	(net 83 "Net-(IC2-VBST)")
+	(net 84 "Net-(IC2-EN)")
+	(net 85 "Net-(IC2-VFB)")
+	(net 86 "Net-(U1-+)")
 	(footprint "custom:9VAC_TRANSF"
 		(layer "F.Cu")
 		(uuid "006dbad8-f4c8-4a6d-8aec-949e81edd5dc")
 		(at 198.37 84.11)
 		(property "Reference" "T1"
-			(at 9.1318 0.1096 0)
+			(at -21.595 23.465 0)
 			(unlocked yes)
 			(layer "F.SilkS")
 			(uuid "f5283d8b-1845-429f-889a-54e1b010b9ac")
@@ -353,7 +336,7 @@
 			(drill 1.5)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 16 "9VAC1")
+			(net 6 "9VAC1")
 			(pinfunction "AA")
 			(pintype "passive")
 			(uuid "71e93540-20ea-4c73-9b13-05b86a0c45db")
@@ -388,7 +371,7 @@
 			(drill 1.5)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 15 "9VAC2")
+			(net 5 "9VAC2")
 			(pinfunction "AB")
 			(pintype "passive")
 			(uuid "c1aa306d-e9c6-4147-8081-85015bebcd89")
@@ -399,7 +382,7 @@
 			(drill 1.5)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 18 "9VAC_OUT2")
+			(net 8 "9VAC_OUT2")
 			(pinfunction "SA")
 			(pintype "passive")
 			(uuid "c1f1faac-ee30-40a2-b88e-b2242f02f41b")
@@ -434,7 +417,7 @@
 			(drill 1.5)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 19 "9VAC_OUT1")
+			(net 9 "9VAC_OUT1")
 			(pinfunction "SB")
 			(pintype "passive")
 			(uuid "6488b803-dbdb-47c3-bc5a-4c067391ece2")
@@ -444,7 +427,7 @@
 	(footprint "DI006H03SQ:SOIC127P600X175-8N"
 		(layer "F.Cu")
 		(uuid "01ed6020-81e7-489c-8b29-1359b733da1d")
-		(at 158.0896 83.1088 180)
+		(at 164.9984 84.9884 180)
 		(property "Reference" "Q2"
 			(at -0.075 -3.635 0)
 			(layer "F.SilkS")
@@ -686,7 +669,7 @@
 			(at -2.475 -1.905 180)
 			(size 1.97 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 52 "G4")
+			(net 39 "G4")
 			(pintype "passive")
 			(solder_mask_margin 0.102)
 			(uuid "6ccb4029-3f83-48ce-b114-a7c37fa735f8")
@@ -695,7 +678,7 @@
 			(at -2.475 -0.635 180)
 			(size 1.97 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 102 "Net-(L3-Pad1)")
+			(net 81 "Net-(L3-Pad1)")
 			(pintype "passive")
 			(solder_mask_margin 0.102)
 			(uuid "f3350dda-91a7-4316-9799-e8fb2794f12b")
@@ -704,7 +687,7 @@
 			(at -2.475 0.635 180)
 			(size 1.97 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 103 "Net-(U6-+IN)")
+			(net 86 "Net-(U1-+)")
 			(pintype "passive")
 			(solder_mask_margin 0.102)
 			(uuid "fd17541d-b3f6-4db8-8a48-f5d067581369")
@@ -713,7 +696,7 @@
 			(at -2.475 1.905 180)
 			(size 1.97 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 54 "G2")
+			(net 41 "G2")
 			(pintype "passive")
 			(solder_mask_margin 0.102)
 			(uuid "74aeeb06-cf0c-41ee-90e7-2c0c65ace0be")
@@ -722,7 +705,7 @@
 			(at 2.475 1.905 180)
 			(size 1.97 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 53 "G1")
+			(net 40 "G1")
 			(pintype "passive")
 			(solder_mask_margin 0.102)
 			(uuid "a00a1215-6ef8-4555-be21-0fdd559f080b")
@@ -731,7 +714,7 @@
 			(at 2.475 0.635 180)
 			(size 1.97 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 101 "Net-(L2-Pad1)")
+			(net 80 "Net-(L2-Pad1)")
 			(pintype "passive")
 			(solder_mask_margin 0.102)
 			(uuid "0f64a673-120d-48a1-bc9b-891eceea8ccb")
@@ -749,447 +732,23 @@
 			(at 2.475 -1.905 180)
 			(size 1.97 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 51 "G3")
+			(net 38 "G3")
 			(pintype "passive")
 			(solder_mask_margin 0.102)
 			(uuid "bc53311a-802b-41e1-8fd1-5b64de705766")
 		)
 		(embedded_fonts no)
 	)
-	(footprint "Capacitor_SMD:C_0402_1005Metric"
-		(layer "F.Cu")
-		(uuid "0436a71a-38cf-41ea-ba46-baf2f9d04eed")
-		(at 179.2504 27.0988)
-		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "capacitor")
-		(property "Reference" "C14"
-			(at 0 -1.16 0)
-			(layer "F.SilkS")
-			(uuid "18ece100-e136-4a85-8500-a1b903c01f18")
-			(effects
-				(font
-					(size 1 1)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property "Value" "56pF"
-			(at 0 1.16 0)
-			(layer "F.Fab")
-			(uuid "e906e3c4-2952-4001-9994-1ad53977acce")
-			(effects
-				(font
-					(size 1 1)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property "Datasheet" "~"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "d304b63e-dfc7-4657-8c5a-63e82e177ec0")
-			(effects
-				(font
-					(size 1.27 1.27)
-					(thickness 0.15)
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-			)
-		)
-		(property "Description" "Unpolarized capacitor"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "bbc37807-9834-438c-9efc-277b5bf980c3")
-			(effects
-				(font
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-		)
-		(property "MPN" "CC0402JRNPO9BN560"
-			(at 0 0 0)
-			(unlocked yes)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "17d013d0-e5f5-45d2-a21e-fcf5eb300004")
-			(effects
-				(font
-					(size 1 1)
-					(thickness 0.15)
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-			)
-		)
-		(property ki_fp_filters "C_*")
-		(path "/90331e1d-4638-4e36-879e-c9f4d236e03d")
-		(sheetname "/")
-		(sheetfile "c64psu.kicad_sch")
-		(attr smd)
-		(fp_line
-			(start -0.107836 -0.36)
-			(end 0.107836 -0.36)
-			(stroke
-				(width 0.12)
-				(type solid)
-			)
-			(layer "F.SilkS")
-			(uuid "93e6834a-a203-4955-b5f2-e9948f29028b")
-		)
-		(fp_line
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-			(end 0.107836 0.36)
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-			(layer "F.SilkS")
-			(uuid "13af0403-9273-458a-998c-48a24ff56449")
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-		(fp_line
-			(start -0.91 -0.46)
-			(end 0.91 -0.46)
-			(stroke
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-			(layer "F.CrtYd")
-			(uuid "c6d3359b-a69d-4caf-82e5-91823ab439fc")
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-		(fp_line
-			(start -0.91 0.46)
-			(end -0.91 -0.46)
-			(stroke
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-			(layer "F.CrtYd")
-			(uuid "c78cbd42-6068-4737-af54-5d4e46d3a7c9")
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-		(fp_line
-			(start 0.91 -0.46)
-			(end 0.91 0.46)
-			(stroke
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-			(layer "F.CrtYd")
-			(uuid "3f2f8985-c888-4c0e-bd43-773165743e8b")
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-		(fp_line
-			(start 0.91 0.46)
-			(end -0.91 0.46)
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-			(layer "F.CrtYd")
-			(uuid "d20c52f0-3c67-45af-b149-35cec3965abc")
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-		(fp_line
-			(start -0.5 -0.25)
-			(end 0.5 -0.25)
-			(stroke
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-			(layer "F.Fab")
-			(uuid "7fc43b06-319d-460b-a4f5-e9522c4622a1")
-		)
-		(fp_line
-			(start -0.5 0.25)
-			(end -0.5 -0.25)
-			(stroke
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-			(layer "F.Fab")
-			(uuid "da5906c9-233c-47aa-9fad-7b49b2e6f71c")
-		)
-		(fp_line
-			(start 0.5 -0.25)
-			(end 0.5 0.25)
-			(stroke
-				(width 0.1)
-				(type solid)
-			)
-			(layer "F.Fab")
-			(uuid "4a4935ff-23aa-495a-bc16-db75706bb0a0")
-		)
-		(fp_line
-			(start 0.5 0.25)
-			(end -0.5 0.25)
-			(stroke
-				(width 0.1)
-				(type solid)
-			)
-			(layer "F.Fab")
-			(uuid "d180efcb-f23c-42c0-9740-e3d40558fa94")
-		)
-		(fp_text user "${REFERENCE}"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(uuid "f6b86d80-6c02-40f9-b9bb-1037d2c5a614")
-			(effects
-				(font
-					(size 0.25 0.25)
-					(thickness 0.04)
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-			)
-		)
-		(pad "1" smd roundrect
-			(at -0.48 0)
-			(size 0.56 0.62)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 1 "GND")
-			(pintype "passive")
-			(uuid "750b640a-8e72-4c67-bbe8-4a5a8a924345")
-		)
-		(pad "2" smd roundrect
-			(at 0.48 0)
-			(size 0.56 0.62)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 8 "Net-(U1-ILIM)")
-			(pintype "passive")
-			(uuid "e9f3f6c3-9dd0-43da-972f-57868eb2518c")
-		)
-		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0402_1005Metric.step"
-			(offset
-				(xyz 0 0 0)
-			)
-			(scale
-				(xyz 1 1 1)
-			)
-			(rotate
-				(xyz 0 0 0)
-			)
-		)
-	)
-	(footprint "Resistor_SMD:R_0603_1608Metric"
-		(layer "F.Cu")
-		(uuid "052dabe5-d46a-4247-b117-8231f56edc11")
-		(at 153.9504 15.0588)
-		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "resistor")
-		(property "Reference" "R9"
-			(at 0 -1.43 0)
-			(layer "F.SilkS")
-			(uuid "a0c23368-a6eb-47eb-a4ef-23d06e34acaf")
-			(effects
-				(font
-					(size 1 1)
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-		)
-		(property "Value" "49.9k"
-			(at 0 1.43 0)
-			(layer "F.Fab")
-			(uuid "5607bf08-7bf8-41ad-b164-92b229abe97b")
-			(effects
-				(font
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-			)
-		)
-		(property "Datasheet" "~"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "3fee4452-0e69-4793-9114-c424f55952f1")
-			(effects
-				(font
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-		)
-		(property "Description" "Resistor"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "b1d25bd2-9db9-48a0-9963-9ce7428c59fc")
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-		(property "MPN" "RC0603FR-0749K9L"
-			(at 0 0 0)
-			(unlocked yes)
-			(layer "F.Fab")
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-			(uuid "d00621dc-abdb-4685-87fd-f49433f28a0f")
-			(effects
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-		(property ki_fp_filters "R_*")
-		(path "/8d013909-6459-493e-b919-a6599ee359f5")
-		(sheetname "/")
-		(sheetfile "c64psu.kicad_sch")
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-		(fp_text user "${REFERENCE}"
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-		(pad "1" smd roundrect
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-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 3 "15V")
-			(pintype "passive")
-			(uuid "fa752f60-82df-4834-bfaa-95ffe9ecf20b")
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-		(pad "2" smd roundrect
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-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 7 "Net-(U1-EN{slash}UVLO)")
-			(pintype "passive")
-			(uuid "b1291c66-a6ac-4a10-a638-0b6637e105fa")
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-		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.step"
-			(offset
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-			(scale
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-			(rotate
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-	)
 	(footprint "Capacitor_SMD:C_0805_2012Metric"
 		(layer "F.Cu")
-		(uuid "12f2dcf0-8cf2-4d3c-bdf5-7c35c017748a")
-		(at 141.6812 21.9964 90)
+		(uuid "0b7e03ac-c656-4476-8afc-127cfca6bb83")
+		(at 176.1823 54.18075)
 		(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
 		(tags "capacitor")
-		(property "Reference" "C7"
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 			(net 4 "5V")
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 			(net 1 "GND")
 			(pintype "passive")
-			(uuid "b3db6ca8-fdce-4768-8762-d3315486c300")
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-		(tags "resistor")
-		(property "Reference" "R12"
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+		(uuid "12a741cb-a9c4-4f13-a1d0-8104f1bf6bc2")
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-			(net 57 "Net-(U1-PGOOD)")
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 		(layer "F.Cu")
 		(uuid "1b2d7034-4791-4d1f-885e-3e7b209639d7")
-		(at 126.1376 47.2616)
+		(at 145.9575 57.90675)
 		(descr "LED SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
 		(tags "LED")
 		(property "Reference" "D1"
 			(at 0 -1.43 0)
 			(layer "F.SilkS")
-			(uuid "d53ddc19-b5d4-4e5f-872a-5790a8170886")
+			(uuid "f2f01e1b-1a69-4105-9a9e-b0468a3d3de0")
 			(effects
 				(font
 					(size 1 1)
@@ -1650,7 +1235,7 @@
 		(property "Value" "LED"
 			(at 0 1.43 0)
 			(layer "F.Fab")
-			(uuid "92497cec-540e-4a7d-873a-bfb125686d3f")
+			(uuid "6a1f4f1b-a285-41a9-9eaf-e9159ccf4ffd")
 			(effects
 				(font
 					(size 1 1)
@@ -1662,7 +1247,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "cf68e829-03fc-419f-92fa-a66ecbc74b7f")
+			(uuid "57501f70-b3cb-4358-a5ba-39703120265b")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -1674,7 +1259,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "7ba19d11-b98e-40df-b7d4-f9be940347ec")
+			(uuid "56e846b4-e848-4612-9153-42dfe7a68e1a")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -1859,7 +1444,7 @@
 			(size 0.875 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 24 "Net-(D1-A)")
+			(net 13 "Net-(D1-A)")
 			(pinfunction "A")
 			(pintype "passive")
 			(uuid "34597deb-9e04-4723-82d4-55e00e519d84")
@@ -1880,7 +1465,7 @@
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "F.Cu")
 		(uuid "1c76de96-23cf-402d-8a22-5553764380ef")
-		(at 134.5692 73.9648 180)
+		(at 150.694499 80.3977 180)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C46"
@@ -2129,7 +1714,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pintype "passive")
 			(uuid "d874159a-fac5-498b-9035-08fa29bddfb6")
 		)
@@ -2158,13 +1743,13 @@
 	(footprint "ap33771c:SON40P300X300X80-15N-D"
 		(layer "F.Cu")
 		(uuid "1fdf5e56-8911-40e7-9e05-bfe8bda1dfe7")
-		(at 126.9976 51.5916 180)
+		(at 146.8175 62.23675 180)
 		(descr "W-DFN3030-14")
 		(tags "Integrated Circuit")
 		(property "Reference" "IC1"
-			(at 0 0 0)
+			(at 0.8175 2.61175 0)
 			(layer "F.SilkS")
-			(uuid "ede8da4e-dfb1-45b8-921d-77f4d7b7f0e4")
+			(uuid "30afa27d-976c-4c92-8194-ebea7f5f0148")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -2176,7 +1761,7 @@
 			(at 0 0 0)
 			(layer "F.SilkS")
 			(hide yes)
-			(uuid "3552d069-97a2-47d6-a875-d94f11f3c8d1")
+			(uuid "2f9d1fce-7fd7-410a-82c4-a9b342e739c3")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -2188,7 +1773,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "9203cc36-484c-47f1-bfae-85873286be95")
+			(uuid "c2499ca4-b813-4354-9a1d-1de86e87c59b")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -2200,7 +1785,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "445deac8-9e6b-430d-84db-418acb39faf8")
+			(uuid "ad130272-3b6c-4052-8ab1-209cae5494ea")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -2408,7 +1993,7 @@
 			(at -1.5 -1.2 270)
 			(size 0.2 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 25 "Net-(IC1-VOUT)")
+			(net 14 "Net-(IC1-VOUT)")
 			(pinfunction "VOUT")
 			(pintype "passive")
 			(thermal_bridge_angle 45)
@@ -2418,7 +2003,7 @@
 			(at -1.5 -0.8 270)
 			(size 0.2 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 29 "Net-(IC1-PWR_EN)")
+			(net 18 "Net-(IC1-PWR_EN)")
 			(pinfunction "PWR_EN")
 			(pintype "passive")
 			(thermal_bridge_angle 45)
@@ -2428,7 +2013,7 @@
 			(at -1.5 -0.4 270)
 			(size 0.2 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 31 "Net-(IC1-VCC)")
+			(net 20 "Net-(IC1-VCC)")
 			(pinfunction "VCC")
 			(pintype "passive")
 			(thermal_bridge_angle 45)
@@ -2458,7 +2043,7 @@
 			(at -1.5 0.8 270)
 			(size 0.2 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 27 "unconnected-(IC1-FLIP-Pad6)")
+			(net 16 "unconnected-(IC1-FLIP-Pad6)")
 			(pinfunction "FLIP")
 			(pintype "passive+no_connect")
 			(thermal_bridge_angle 45)
@@ -2468,7 +2053,7 @@
 			(at -1.5 1.2 270)
 			(size 0.2 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 30 "Net-(IC1-LED)")
+			(net 19 "Net-(IC1-LED)")
 			(pinfunction "LED")
 			(pintype "passive")
 			(thermal_bridge_angle 45)
@@ -2478,7 +2063,7 @@
 			(at 1.5 1.2 270)
 			(size 0.2 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 26 "Net-(IC1-VSEL)")
+			(net 15 "Net-(IC1-VSEL)")
 			(pinfunction "VSEL")
 			(pintype "passive")
 			(thermal_bridge_angle 45)
@@ -2488,7 +2073,7 @@
 			(at 1.5 0.8 270)
 			(size 0.2 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 32 "Net-(IC1-ISEL)")
+			(net 21 "Net-(IC1-ISEL)")
 			(pinfunction "ISEL")
 			(pintype "passive")
 			(thermal_bridge_angle 45)
@@ -2498,7 +2083,7 @@
 			(at 1.5 0.4 270)
 			(size 0.2 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 35 "CC2")
+			(net 24 "CC2")
 			(pinfunction "CC2")
 			(pintype "passive")
 			(thermal_bridge_angle 45)
@@ -2508,7 +2093,7 @@
 			(at 1.5 0 270)
 			(size 0.2 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 34 "CC1")
+			(net 23 "CC1")
 			(pinfunction "CC1")
 			(pintype "passive")
 			(thermal_bridge_angle 45)
@@ -2518,7 +2103,7 @@
 			(at 1.5 -0.4 270)
 			(size 0.2 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 28 "DN")
+			(net 17 "DN")
 			(pinfunction "DN")
 			(pintype "passive")
 			(thermal_bridge_angle 45)
@@ -2528,7 +2113,7 @@
 			(at 1.5 -0.8 270)
 			(size 0.2 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 33 "DP")
+			(net 22 "DP")
 			(pinfunction "DP")
 			(pintype "passive")
 			(thermal_bridge_angle 45)
@@ -2538,7 +2123,7 @@
 			(at 1.5 -1.2 270)
 			(size 0.2 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 23 "Net-(IC1-V5V)")
+			(net 12 "Net-(IC1-V5V)")
 			(pinfunction "V5V")
 			(pintype "passive")
 			(thermal_bridge_angle 45)
@@ -2556,16 +2141,16 @@
 		)
 		(embedded_fonts no)
 	)
-	(footprint "Resistor_SMD:R_0603_1608Metric"
+	(footprint "MountingHole:MountingHole_3.2mm_M3_DIN965_Pad_TopBottom"
 		(layer "F.Cu")
-		(uuid "23ffb52f-ba9a-48e2-949e-90e8c4a20f86")
-		(at 119.5324 50.3936 180)
-		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "resistor")
-		(property "Reference" "R5"
-			(at 0 -1.43 0)
+		(uuid "20cf8bed-80d6-4924-afe5-629663f97e2b")
+		(at 190 42)
+		(descr "Mounting Hole 3.2mm, M3, generated by kicad-footprint-generator mountinghole.py")
+		(tags "mountinghole M3 DIN965")
+		(property "Reference" "H1"
+			(at 0 -3.75 0)
 			(layer "F.SilkS")
-			(uuid "2b6b4ade-0192-4b61-acd8-f5daa42e00c6")
+			(uuid "85585049-abfa-4c88-ac5f-c460874ef52c")
 			(effects
 				(font
 					(size 1 1)
@@ -2573,10 +2158,10 @@
 				)
 			)
 		)
-		(property "Value" "52k 1%"
-			(at 0 1.43 0)
+		(property "Value" "MountingHole_Pad"
+			(at 0 3.75 0)
 			(layer "F.Fab")
-			(uuid "73689641-e035-4b2f-b409-b7cdc88858fa")
+			(uuid "8f040a46-df87-4153-aa54-9d475240a544")
 			(effects
 				(font
 					(size 1 1)
@@ -2588,7 +2173,131 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "e50c63b4-c706-4f59-a619-a2c85eb2183d")
+			(uuid "55a9b75c-4f35-4846-bdad-746744858626")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Description" "Mounting Hole with connection"
+			(at 0 0 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "bcc965d3-3c8b-4bc0-b24d-54021f8cd429")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property ki_fp_filters "MountingHole*Pad*")
+		(path "/f604aa64-ced0-4f56-8986-0cee27aa8f45")
+		(sheetname "/")
+		(sheetfile "c64psu.kicad_sch")
+		(attr exclude_from_pos_files exclude_from_bom)
+		(fp_circle
+			(center 0 0)
+			(end 2.8 0)
+			(stroke
+				(width 0.15)
+				(type solid)
+			)
+			(fill no)
+			(layer "Cmts.User")
+			(uuid "bd1b4627-b7ac-4704-98b7-96127ba3d021")
+		)
+		(fp_circle
+			(center 0 0)
+			(end 3.05 0)
+			(stroke
+				(width 0.05)
+				(type solid)
+			)
+			(fill no)
+			(layer "F.CrtYd")
+			(uuid "a7d41f78-d205-4c12-a0cf-5423a4077f29")
+		)
+		(fp_text user "${REFERENCE}"
+			(at 0 0 0)
+			(layer "F.Fab")
+			(uuid "1c24d9d8-81a3-41d7-80f4-89028fdb536b")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(pad "1" thru_hole circle
+			(at 0 0)
+			(size 3.6 3.6)
+			(drill 3.2)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
+			(net 1 "GND")
+			(pinfunction "1")
+			(pintype "input")
+			(zone_connect 2)
+			(uuid "b9ed226f-7deb-4cc6-a353-9ced950a5504")
+		)
+		(pad "1" connect circle
+			(at 0 0)
+			(size 5.6 5.6)
+			(layers "F.Cu" "F.Mask")
+			(net 1 "GND")
+			(pinfunction "1")
+			(pintype "input")
+			(zone_connect 2)
+			(uuid "ae5f9d10-45aa-49fc-9083-00ac698f6fd9")
+		)
+		(pad "1" connect circle
+			(at 0 0)
+			(size 5.6 5.6)
+			(layers "B.Cu" "B.Mask")
+			(net 1 "GND")
+			(pinfunction "1")
+			(pintype "input")
+			(zone_connect 2)
+			(uuid "b5b05692-6339-4d12-a699-540948060932")
+		)
+		(embedded_fonts no)
+	)
+	(footprint "Resistor_SMD:R_0603_1608Metric"
+		(layer "F.Cu")
+		(uuid "23ffb52f-ba9a-48e2-949e-90e8c4a20f86")
+		(at 139.3523 61.03875 180)
+		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+		(tags "resistor")
+		(property "Reference" "R5"
+			(at 2.5273 -0.06125 0)
+			(layer "F.SilkS")
+			(uuid "c5a4abe1-3e4c-483e-872b-eed43d943259")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" "52k 1%"
+			(at 0 1.43 0)
+			(layer "F.Fab")
+			(uuid "2abd92f0-8b76-4a78-90d1-362c39c7c224")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Datasheet" "~"
+			(at 0 0 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "8272ba37-81cb-4cb0-b93e-907af9f87502")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -2600,7 +2309,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "a50d79be-cd21-4eb2-b916-71e89dfd3471")
+			(uuid "6998faa0-7cbe-4c8f-8b71-22f8a5aca97a")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -2742,7 +2451,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 26 "Net-(IC1-VSEL)")
+			(net 15 "Net-(IC1-VSEL)")
 			(pintype "passive")
 			(uuid "6108d8a4-0631-4ba7-8a24-0300a512fb60")
 		)
@@ -2771,11 +2480,11 @@
 	(footprint "TestPoint:TestPoint_2Pads_Pitch2.54mm_Drill0.8mm"
 		(layer "F.Cu")
 		(uuid "24612743-3eff-4696-afc0-c14a1a96a719")
-		(at 143.5184 74.7648)
+		(at 166.5 72.525 180)
 		(descr "Test point with 2 pins, pitch 2.54mm, drill diameter 0.8mm")
 		(tags "CONN DEV")
 		(property "Reference" "TP2"
-			(at 1.3 -2 0)
+			(at 12.2344 1.6384 0)
 			(layer "F.SilkS")
 			(uuid "ae3ad5db-cda1-4740-a2c6-16c0b67cd6b1")
 			(effects
@@ -2797,7 +2506,7 @@
 			)
 		)
 		(property "Datasheet" "~"
-			(at 0 0 0)
+			(at 0 0 180)
 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
@@ -2810,7 +2519,7 @@
 			)
 		)
 		(property "Description" "2-polar test point"
-			(at 0 0 0)
+			(at 0 0 180)
 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
@@ -2828,64 +2537,14 @@
 		(sheetfile "c64psu.kicad_sch")
 		(attr exclude_from_pos_files exclude_from_bom dnp)
 		(fp_line
-			(start -1.03 -0.4)
-			(end -0.53 -0.9)
+			(start 3.57 0.4)
+			(end 3.07 0.9)
 			(stroke
 				(width 0.15)
 				(type solid)
 			)
 			(layer "F.SilkS")
-			(uuid "6eef0ced-939f-4a32-b522-b8c100c33afa")
-		)
-		(fp_line
-			(start -1.03 0.4)
-			(end -1.03 -0.4)
-			(stroke
-				(width 0.15)
-				(type solid)
-			)
-			(layer "F.SilkS")
-			(uuid "63ec0f7e-1c97-40ce-8ad5-0b46d700fd91")
-		)
-		(fp_line
-			(start -0.53 -0.9)
-			(end 3.07 -0.9)
-			(stroke
-				(width 0.15)
-				(type solid)
-			)
-			(layer "F.SilkS")
-			(uuid "20dc7457-69c0-40ea-a400-20b082181fcd")
-		)
-		(fp_line
-			(start -0.53 0.9)
-			(end -1.03 0.4)
-			(stroke
-				(width 0.15)
-				(type solid)
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-			(layer "F.SilkS")
-			(uuid "13f98e9f-c681-4810-b38a-add8362ae511")
-		)
-		(fp_line
-			(start 3.07 -0.9)
-			(end 3.57 -0.4)
-			(stroke
-				(width 0.15)
-				(type solid)
-			)
-			(layer "F.SilkS")
-			(uuid "a51a68d5-ea52-4e06-ab30-ba1e9789db4c")
-		)
-		(fp_line
-			(start 3.07 0.9)
-			(end -0.53 0.9)
-			(stroke
-				(width 0.15)
-				(type solid)
-			)
-			(layer "F.SilkS")
-			(uuid "57922be1-0ce8-4c02-8cbe-f578c955dfcf")
+			(uuid "3e0bd3e9-04fb-4b98-a83c-a22e2f1cdf5c")
 		)
 		(fp_line
 			(start 3.57 -0.4)
@@ -2898,74 +2557,74 @@
 			(uuid "14279f3d-78e8-4ca1-a474-5365c419be75")
 		)
 		(fp_line
-			(start 3.57 0.4)
-			(end 3.07 0.9)
+			(start 3.07 0.9)
+			(end -0.53 0.900001)
 			(stroke
 				(width 0.15)
 				(type solid)
 			)
 			(layer "F.SilkS")
-			(uuid "3e0bd3e9-04fb-4b98-a83c-a22e2f1cdf5c")
+			(uuid "57922be1-0ce8-4c02-8cbe-f578c955dfcf")
 		)
 		(fp_line
-			(start -1.3 -0.5)
-			(end -1.3 0.5)
+			(start 3.07 -0.9)
+			(end 3.57 -0.4)
+			(stroke
+				(width 0.15)
+				(type solid)
+			)
+			(layer "F.SilkS")
+			(uuid "a51a68d5-ea52-4e06-ab30-ba1e9789db4c")
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 			(layer "F.CrtYd")
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+			(uuid "f909030d-4141-44ed-aec8-9ce0358bdf71")
 		)
 		(fp_text user "${REFERENCE}"
 			(at 1.3 -2 0)
@@ -2999,18 +2708,18 @@
 			)
 		)
 		(pad "1" thru_hole circle
-			(at 0 0)
+			(at 0 0 180)
 			(size 1.4 1.4)
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 64 "PWM_G2")
+			(net 47 "PWM_G2")
 			(pinfunction "1")
 			(pintype "passive")
 			(uuid "36c729ed-6b1a-46ff-9abb-e27fe76af4e9")
 		)
 		(pad "2" thru_hole circle
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+			(at 2.54 0 180)
 			(size 1.4 1.4)
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
@@ -3022,16 +2731,254 @@
 		)
 		(embedded_fonts no)
 	)
+	(footprint "Capacitor_SMD:C_0805_2012Metric"
+		(layer "F.Cu")
+		(uuid "262a0bad-513e-488d-bc61-d1a5908e6fb5")
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+		(tags "capacitor")
+		(property "Reference" "C5"
+			(at 2.951501 0.05905 0)
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+			(uuid "73a50b10-9003-40fc-9e6b-cd97a3f56fac")
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+		(property ki_fp_filters "C_*")
+		(path "/80fb66d1-ee38-4b3d-ba55-da4ef1522f00")
+		(sheetname "/")
+		(sheetfile "c64psu.kicad_sch")
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+			(uuid "532dcf4e-4912-4e7a-ba42-3e9a89f98f15")
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+		(fp_text user "${REFERENCE}"
+			(at 0 0 0)
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+			(uuid "559ed09a-6329-411e-86d5-13acd0a210d0")
+			(effects
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+					(thickness 0.08)
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+		(pad "1" smd roundrect
+			(at -0.949999 0)
+			(size 1 1.45)
+			(layers "F.Cu" "F.Mask" "F.Paste")
+			(roundrect_rratio 0.25)
+			(net 4 "5V")
+			(pintype "passive")
+			(uuid "d2f8f1ca-ecbb-4b48-8f80-cb4bd65742e6")
+		)
+		(pad "2" smd roundrect
+			(at 0.949999 0)
+			(size 1 1.45)
+			(layers "F.Cu" "F.Mask" "F.Paste")
+			(roundrect_rratio 0.25)
+			(net 1 "GND")
+			(pintype "passive")
+			(uuid "75f1be47-ad4d-4c86-8d63-e221d3fd2070")
+		)
+		(embedded_fonts no)
+		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.step"
+			(offset
+				(xyz 0 0 0)
+			)
+			(scale
+				(xyz 1 1 1)
+			)
+			(rotate
+				(xyz 0 0 0)
+			)
+		)
+	)
 	(footprint "Resistor_SMD:R_0402_1005Metric"
 		(layer "F.Cu")
 		(uuid "28e3e672-59bd-40d9-a954-05de88109e69")
-		(at 131.7752 47.093599 -90)
+		(at 151.5951 57.738749 -90)
 		(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "resistor")
 		(property "Reference" "R3"
-			(at 0 -1.17 90)
+			(at 2.011251 -0.0799 90)
 			(layer "F.SilkS")
-			(uuid "5204eed7-3a2f-4c94-a202-466fb1ee97df")
+			(uuid "cec93abb-3489-48eb-819a-8b6d620ad905")
 			(effects
 				(font
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 		(property "Value" "10"
 			(at 0 1.17 90)
 			(layer "F.Fab")
-			(uuid "0335a794-f788-4413-a0b4-ef168ae47b75")
+			(uuid "1494772d-043c-4098-ade6-43d9310ad9c4")
 			(effects
 				(font
 					(size 1 1)
@@ -3054,7 +3001,7 @@
 			(at 0 0 90)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "c738104a-beb3-455e-8641-1c035d18d73d")
+			(uuid "353651e4-7a97-4bfb-b533-bdd552428c8e")
 			(effects
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@@ -3066,7 +3013,7 @@
 			(at 0 0 90)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "8f00d9cd-081c-4ae8-abbc-c3a26a19657f")
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 			(effects
 				(font
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@@ -3208,7 +3155,7 @@
 			(size 0.54 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 47 "Net-(Q1-Pad4)")
+			(net 36 "Net-(Q1-Pad4)")
 			(pintype "passive")
 			(uuid "255683db-4ab0-41dd-9935-4767bf19d38f")
 		)
@@ -3217,7 +3164,7 @@
 			(size 0.54 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 29 "Net-(IC1-PWR_EN)")
+			(net 18 "Net-(IC1-PWR_EN)")
 			(pintype "passive")
 			(uuid "357d67a6-c192-4e8c-8f99-20fd28e01e6b")
 		)
@@ -3237,11 +3184,11 @@
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "F.Cu")
 		(uuid "2afad1ae-e3ec-4293-9090-84084e8fbffc")
-		(at 130.2512 92.71)
+		(at 149.0422 98.027)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C48"
-			(at 0 -1.16 0)
+			(at 2.8578 0.248 0)
 			(layer "F.SilkS")
 			(uuid "4aa89930-15c1-449f-b1ff-337ba4fd5dde")
 			(effects
@@ -3485,7 +3432,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 21 "VDDA")
+			(net 11 "VDDA")
 			(pintype "passive")
 			(uuid "43272b65-bc06-4c92-8e06-27816cf94edd")
 		)
@@ -3511,16 +3458,16 @@
 			)
 		)
 	)
-	(footprint "Capacitor_SMD:C_1206_3216Metric"
+	(footprint "Resistor_SMD:R_0402_1005Metric"
 		(layer "F.Cu")
-		(uuid "2b45c6d0-8640-4f7f-8115-48a0c7771686")
-		(at 173.02 84.3 -90)
-		(descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "capacitor")
-		(property "Reference" "C25"
-			(at -3.9852 0.046 90)
+		(uuid "2cfb2d15-65f8-4e0d-b0a0-ea9e45e95818")
+		(at 171.5595 54.284349 -90)
+		(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+		(tags "resistor")
+		(property "Reference" "R29"
+			(at 4.290651 0.0345 90)
 			(layer "F.SilkS")
-			(uuid "2fda5f05-f311-437c-ad04-3959428d42e1")
+			(uuid "23dbcf81-6adc-4807-96ff-8cac176c5178")
 			(effects
 				(font
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@@ -3528,10 +3475,10 @@
 				)
 			)
 		)
-		(property "Value" "10uF"
-			(at 0 1.850001 90)
+		(property "Value" "10.2k"
+			(at 0 1.17 90)
 			(layer "F.Fab")
-			(uuid "7b288585-653a-48a0-b0bf-f2a593301a69")
+			(uuid "8f922fed-30ad-42a1-b347-a007fa4d3853")
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 				(font
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@@ -3543,7 +3490,7 @@
 			(at 0 0 90)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "2d274075-d807-48f4-91c1-4d748a3445f0")
+			(uuid "a020a6b8-2d6e-4e24-9f85-aab612e0c2c6")
 			(effects
 				(font
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@@ -3551,11 +3498,11 @@
 				)
 			)
 		)
-		(property "Description" "Unpolarized capacitor"
+		(property "Description" "Resistor"
 			(at 0 0 90)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "eba60058-9a30-45b3-99ff-6ceb42efcd41")
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@@ -3563,12 +3510,12 @@
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 			)
 		)
-		(property "MPN" "CC1206KKX5R9BB106 "
+		(property "MPN" ""
 			(at 0 0 270)
 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "4e2e6785-89c9-4782-8eea-29e71115760c")
+			(uuid "5a87a6f7-72e5-4f31-9bc9-30384f2d80cc")
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 				(font
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@@ -3576,142 +3523,142 @@
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 		)
-		(property ki_fp_filters "C_*")
-		(path "/d4839fd2-827a-489c-ac06-e357ed71f7ac")
+		(property ki_fp_filters "R_*")
+		(path "/07e4bb78-6f75-43ba-bcbd-9c97942f3e3c")
 		(sheetname "/")
 		(sheetfile "c64psu.kicad_sch")
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+		(attr smd)
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+			(start -0.153641 0.38)
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 			(layer "F.SilkS")
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 			(layer "F.Fab")
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 			(layer "F.Fab")
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 		(fp_text user "${REFERENCE}"
 			(at 0 0 90)
 			(layer "F.Fab")
-			(uuid "4fff44d2-64be-4197-b431-fd691e9db1e7")
+			(uuid "f53f3ef6-6936-4c1f-8ba1-fb7d9377b165")
 			(effects
 				(font
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 		)
 		(pad "1" smd roundrect
-			(at -1.475001 0 270)
-			(size 1.15 1.8)
+			(at -0.509999 0 270)
+			(size 0.54 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.217391)
-			(net 16 "9VAC1")
+			(roundrect_rratio 0.25)
+			(net 4 "5V")
 			(pintype "passive")
-			(uuid "df29526b-3aee-46c7-acca-aa9f465b9262")
+			(uuid "c024a6cb-8f26-43b6-b917-a9c9ba8cdfbd")
 		)
 		(pad "2" smd roundrect
-			(at 1.475001 0 270)
-			(size 1.15 1.8)
+			(at 0.509999 0 270)
+			(size 0.54 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.217391)
-			(net 15 "9VAC2")
+			(roundrect_rratio 0.25)
+			(net 85 "Net-(IC2-VFB)")
 			(pintype "passive")
-			(uuid "940107c1-9b2f-4177-bcd1-6d329b3a2700")
+			(uuid "b8f7cb39-6cfa-42ce-8548-26f4c565b8f0")
 		)
 		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_1206_3216Metric.step"
+		(model "${KICAD9_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.step"
 			(offset
 				(xyz 0 0 0)
 			)
@@ -3726,11 +3673,11 @@
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "F.Cu")
 		(uuid "2f9b5e56-521e-45a4-9fb5-fb73218d7162")
-		(at 119.5832 84.0232 45)
+		(at 138.3742 89.3402 45)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C97"
-			(at 0 -1.16 45)
+			(at -0.006364 -1.583495 45)
 			(layer "F.SilkS")
 			(uuid "80caa4d6-6e3a-42a1-87cf-4ca13d3e4283")
 			(effects
@@ -3983,7 +3930,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 73 "OSC_IN")
+			(net 53 "OSC_IN")
 			(pintype "passive")
 			(uuid "09ff1eee-2022-47a9-a475-cdaf0e03ace1")
 		)
@@ -4003,13 +3950,13 @@
 	(footprint "Resistor_SMD:R_0603_1608Metric"
 		(layer "F.Cu")
 		(uuid "335e2041-5877-48a2-ba07-f512b5a53a68")
-		(at 127.0508 42.672)
+		(at 146.8707 53.31715)
 		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "resistor")
 		(property "Reference" "R1"
 			(at 0 -1.43 0)
 			(layer "F.SilkS")
-			(uuid "2d555527-f8de-4a8b-a651-b713531f612f")
+			(uuid "0662fd99-aa30-46d6-894a-60c6dc09440a")
 			(effects
 				(font
 					(size 1 1)
@@ -4020,7 +3967,7 @@
 		(property "Value" "5m"
 			(at 0 1.43 0)
 			(layer "F.Fab")
-			(uuid "a3d7aa3c-4fd6-43f6-ab76-42beb19ad8ce")
+			(uuid "2257658a-5a7d-40ea-b1c4-f4e100ac4ce6")
 			(effects
 				(font
 					(size 1 1)
@@ -4032,7 +3979,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "f7437994-89b8-4bce-9b28-61733f3b0f1b")
+			(uuid "cd7dd96c-4a48-450e-b584-b274ed7b7ac1")
 			(effects
 				(font
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@@ -4044,7 +3991,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "168782e5-4ced-4124-acd1-d062145bd264")
+			(uuid "6fb72ea5-cde0-414c-992d-130304203008")
 			(effects
 				(font
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@@ -4195,7 +4142,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 31 "Net-(IC1-VCC)")
+			(net 20 "Net-(IC1-VCC)")
 			(pintype "passive")
 			(uuid "43f21025-ebc6-4572-b746-06847a7d4824")
 		)
@@ -4212,16 +4159,228 @@
 			)
 		)
 	)
+	(footprint "Resistor_SMD:R_0402_1005Metric"
+		(layer "F.Cu")
+		(uuid "359d6276-c9e8-48c2-929a-04bbe2317332")
+		(at 171.5595 56.21275 -90)
+		(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+		(tags "resistor")
+		(property "Reference" "R30"
+			(at 5.18725 0.1345 90)
+			(layer "F.SilkS")
+			(uuid "faec4c1b-334a-485a-a6e8-ce4b95e20e70")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" "1.37k"
+			(at 0 1.17 90)
+			(layer "F.Fab")
+			(uuid "1c8e00a2-2146-4a73-9577-52303ff9db12")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
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+		(property "Datasheet" "~"
+			(at 0 0 90)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "3ba14cce-d99f-4cf0-879b-c2ba76158174")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
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+		)
+		(property "Description" "Resistor"
+			(at 0 0 90)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "4dff730c-306a-4056-83d1-9d9e9c65528b")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
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+		)
+		(property "MPN" ""
+			(at 0 0 270)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "63fa69bf-a400-475d-bacf-83663d8bcdf9")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property ki_fp_filters "R_*")
+		(path "/4712aa1d-0cc2-4b01-bd83-51dd73d2f15c")
+		(sheetname "/")
+		(sheetfile "c64psu.kicad_sch")
+		(attr smd)
+		(fp_line
+			(start -0.153641 0.38)
+			(end 0.153641 0.38)
+			(stroke
+				(width 0.12)
+				(type solid)
+			)
+			(layer "F.SilkS")
+			(uuid "fa6f67c2-a437-4863-900b-e522a0262b05")
+		)
+		(fp_line
+			(start -0.153641 -0.38)
+			(end 0.153641 -0.38)
+			(stroke
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+				(type solid)
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+			(layer "F.SilkS")
+			(uuid "c37c74a2-f609-4dac-96d7-a586d7f463cc")
+		)
+		(fp_line
+			(start -0.93 0.47)
+			(end -0.93 -0.47)
+			(stroke
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+				(type solid)
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+			(layer "F.CrtYd")
+			(uuid "1bea176e-35d8-4507-831a-63a46f827b7b")
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+		(fp_line
+			(start 0.93 0.47)
+			(end -0.93 0.47)
+			(stroke
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+			(layer "F.CrtYd")
+			(uuid "c525622d-417d-4cf4-b1d9-498d1b7ed70c")
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+			(end 0.93 -0.47)
+			(stroke
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+			(layer "F.CrtYd")
+			(uuid "0648bec1-13f2-4c19-941d-170496a1f2bc")
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+			(start 0.93 -0.47)
+			(end 0.93 0.47)
+			(stroke
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+			(layer "F.CrtYd")
+			(uuid "98399b84-0e12-4c32-b803-fc9169b21b6f")
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+		(fp_line
+			(start -0.525 0.27)
+			(end -0.525 -0.27)
+			(stroke
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+			(layer "F.Fab")
+			(uuid "50fae929-9aa7-4d05-9fc6-e15394a8c489")
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+		(fp_line
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+			(end -0.525 0.27)
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+			(uuid "eb685ae5-af20-4575-9d38-36d93f636215")
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+			(start -0.525 -0.27)
+			(end 0.525 -0.27)
+			(stroke
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+			(layer "F.Fab")
+			(uuid "c80c3eef-0b2c-4d46-9bd1-3efc58b3c32f")
+		)
+		(fp_line
+			(start 0.525 -0.27)
+			(end 0.525 0.27)
+			(stroke
+				(width 0.1)
+				(type solid)
+			)
+			(layer "F.Fab")
+			(uuid "cfdd3ce7-6609-48e0-9537-43fd0beef668")
+		)
+		(fp_text user "${REFERENCE}"
+			(at 0 0 90)
+			(layer "F.Fab")
+			(uuid "7c9a90a6-f96d-4395-be9d-ddc029068973")
+			(effects
+				(font
+					(size 0.26 0.26)
+					(thickness 0.04)
+				)
+			)
+		)
+		(pad "1" smd roundrect
+			(at -0.509999 0 270)
+			(size 0.54 0.64)
+			(layers "F.Cu" "F.Mask" "F.Paste")
+			(roundrect_rratio 0.25)
+			(net 85 "Net-(IC2-VFB)")
+			(pintype "passive")
+			(uuid "67cfa6c3-1acf-41da-9f08-dc288d4f68be")
+		)
+		(pad "2" smd roundrect
+			(at 0.509999 0 270)
+			(size 0.54 0.64)
+			(layers "F.Cu" "F.Mask" "F.Paste")
+			(roundrect_rratio 0.25)
+			(net 1 "GND")
+			(pintype "passive")
+			(uuid "abe7bd12-ce4a-4542-9d08-0d9c1b062091")
+		)
+		(embedded_fonts no)
+		(model "${KICAD9_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.step"
+			(offset
+				(xyz 0 0 0)
+			)
+			(scale
+				(xyz 1 1 1)
+			)
+			(rotate
+				(xyz 0 0 0)
+			)
+		)
+	)
 	(footprint "Diode_SMD:D_SMA"
 		(layer "F.Cu")
 		(uuid "3a3d80c8-53ad-40cc-8267-ba7011c6d6f8")
-		(at 125.711199 38.608)
+		(at 145.531099 49.25315)
 		(descr "Diode SMA (DO-214AC)")
 		(tags "Diode SMA (DO-214AC)")
 		(property "Reference" "D3"
 			(at 0 -2.5 0)
 			(layer "F.SilkS")
-			(uuid "e1713030-cb11-4b69-9a3e-2d203a1cba47")
+			(uuid "c3e0a0c7-2625-4a6b-af69-5e7466051c34")
 			(effects
 				(font
 					(size 1 1)
@@ -4232,7 +4391,7 @@
 		(property "Value" "SMAJ15A"
 			(at 0 2.600001 0)
 			(layer "F.Fab")
-			(uuid "e634a29e-376e-432e-8a92-7bd8b0ce3947")
+			(uuid "a80d993c-8ccf-434a-980b-3acfb6e4dec2")
 			(effects
 				(font
 					(size 1 1)
@@ -4245,7 +4404,7 @@
 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "c515ba12-388f-421e-b658-9e8c3527499e")
+			(uuid "b293d663-bdd8-4910-bff7-a267a2b85f70")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -4258,7 +4417,7 @@
 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "4dfddef1-b587-4bb7-af50-f0bc7578ac8a")
+			(uuid "cc4755cd-eec2-42ed-84b9-da3ca2e5ce42")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -4485,248 +4644,10 @@
 			)
 		)
 	)
-	(footprint "Capacitor_SMD:C_1210_3225Metric"
-		(layer "F.Cu")
-		(uuid "3aa976aa-b024-4312-87f2-cf66bce5c7b0")
-		(at 125.476 14.0716)
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-		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_1210_3225Metric.step"
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 		(layer "F.Cu")
 		(uuid "3d6b282a-b7af-4361-9a5e-a9e67b86c369")
-		(at 133.9596 68.4276 90)
+		(at 150.084899 74.8605 90)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C62"
@@ -5003,7 +4924,7 @@
 	(footprint "TestPoint:TestPoint_2Pads_Pitch2.54mm_Drill0.8mm"
 		(layer "F.Cu")
 		(uuid "3eb7d7da-e07e-4807-803e-47f73a473ab2")
-		(at 142.9596 100.9776)
+		(at 158.975 97.1)
 		(descr "Test point with 2 pins, pitch 2.54mm, drill diameter 0.8mm")
 		(tags "CONN DEV")
 		(property "Reference" "TP4"
@@ -5061,7 +4982,7 @@
 		(attr exclude_from_pos_files exclude_from_bom dnp)
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@@ -5080,7 +5001,7 @@
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@@ -5236,7 +5157,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 66 "PWM_G3")
+			(net 49 "PWM_G3")
 			(pinfunction "1")
 			(pintype "passive")
 			(uuid "6d0b6575-f71d-485d-bfd8-600034c73828")
@@ -5257,11 +5178,11 @@
 	(footprint "Capacitor_SMD:C_1210_3225Metric"
 		(layer "F.Cu")
 		(uuid "3f798f33-80de-4953-9ee8-461967873cff")
-		(at 152.7048 85.3948 90)
+		(at 159.6136 87.2744 90)
 		(descr "Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C31"
-			(at 0 -2.300001 90)
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 			(layer "F.SilkS")
 			(uuid "d887d9a1-60bb-430a-b5d1-31f696e7ae58")
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 		(layer "F.Cu")
 		(uuid "4089365a-2a9f-4c5c-8e56-f7b17c5cbd66")
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 		(property "Reference" "Q1"
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 			(layer "F.SilkS")
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@@ -5510,7 +5431,7 @@
 		(property "Value" "DI025N06PT-AQ"
 			(at 9.864999 3.015 0)
 			(layer "F.Fab")
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@@ -5522,7 +5443,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "08de8669-1af9-4ead-8dbc-790d0e527cb7")
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@@ -5534,7 +5455,7 @@
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@@ -5851,7 +5772,7 @@
 			(at -1.5 0.975 180)
 			(size 0.7 0.42)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 47 "Net-(Q1-Pad4)")
+			(net 36 "Net-(Q1-Pad4)")
 			(pintype "passive")
 			(solder_mask_margin 0.102)
 			(uuid "114abb6f-59f9-4a07-a71f-71401c4a4d35")
@@ -5860,7 +5781,7 @@
 			(at 0 0 180)
 			(size 0.7 0.42)
 			(layers "F.Cu")
-			(net 48 "Net-(Q1-Pad5_8)")
+			(net 37 "Net-(Q1-Pad5_8)")
 			(pintype "passive")
 			(options
 				(clearance outline)
@@ -5885,14 +5806,14 @@
 	)
 	(footprint "Capacitor_SMD:C_0805_2012Metric"
 		(layer "F.Cu")
-		(uuid "4d8b3570-544d-4b42-83f9-e47f84da8ea6")
-		(at 139.6492 21.9964 90)
+		(uuid "4b8b1835-cb18-4ae4-82f8-c319a6e14342")
+		(at 172.7279 52.14875 180)
 		(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
 		(tags "capacitor")
-		(property "Reference" "C6"
-			(at 0 -1.679999 90)
+		(property "Reference" "C39"
+			(at 0.2779 2.02375 0)
 			(layer "F.SilkS")
-			(uuid "2725ba51-9ea4-45b4-aa78-c8f87a48af07")
+			(uuid "2bcb3983-6f32-4ce5-b59a-1a13819d982b")
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@@ -5901,9 +5822,9 @@
 			)
 		)
 		(property "Value" "10uF"
-			(at 0 1.679999 90)
+			(at 0 1.679999 0)
 			(layer "F.Fab")
-			(uuid "310080fe-b0e5-4f2d-872c-9ecc4915ff2f")
+			(uuid "47f4618c-60a8-4c0f-9468-c19361c879da")
 			(effects
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@@ -5912,10 +5833,10 @@
 			)
 		)
 		(property "Datasheet" "~"
-			(at 0 0 90)
+			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "f1a2dd3e-5858-4de1-a637-7557bc83acee")
+			(uuid "f63249f4-5484-4fe3-9c8d-c54d99556acf")
 			(effects
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@@ -5924,10 +5845,10 @@
 			)
 		)
 		(property "Description" "Unpolarized capacitor"
-			(at 0 0 90)
+			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "e59f7e24-dda1-4b8a-964d-66b43a564776")
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@@ -5936,11 +5857,11 @@
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 		(property "MPN" "GRM21BR61C106KE15K"
-			(at 0 0 90)
+			(at 0 0 180)
 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "94741316-50d5-4c30-ac38-c603dc340b90")
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@@ -5949,11 +5870,11 @@
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 		(property "Part Number" ""
-			(at 0 0 90)
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 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "5967b9ae-4633-4348-b999-c31bb699e7ba")
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@@ -5962,11 +5883,11 @@
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 		(property "Specifications" ""
-			(at 0 0 90)
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 			(layer "F.Fab")
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@@ -5975,20 +5896,10 @@
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 		(property ki_fp_filters "C_*")
-		(path "/38e610d0-1481-4d6c-9241-dd93292a129d")
+		(path "/03445493-0a3f-4d3d-8743-454e66a3e553")
 		(sheetname "/")
 		(sheetfile "c64psu.kicad_sch")
 		(attr smd)
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@@ -5997,27 +5908,17 @@
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 			(stroke
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-			(layer "F.CrtYd")
-			(uuid "78fcad64-8c2c-4e96-a39c-6f7ffb684ae6")
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@@ -6027,7 +5928,17 @@
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-			(uuid "7eb8d040-3602-4aca-97f0-f75dde9473b6")
+			(uuid "7d1a5891-cc10-4ca2-b728-fadcb1d9c7ec")
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@@ -6037,27 +5948,17 @@
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 			(layer "F.CrtYd")
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+			(layer "F.CrtYd")
+			(uuid "17b819cc-eac3-4f12-8265-78571ff55978")
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@@ -6067,7 +5968,17 @@
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+			(uuid "34fa6825-252d-4ee4-bb00-ce35a2aa29b7")
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+			(uuid "55e1f1b1-38e1-4261-aa2b-de343854e134")
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+			(layer "F.Fab")
+			(uuid "83ef65be-7d1a-4d6e-b67c-2e1e73162389")
 		)
 		(fp_text user "${REFERENCE}"
-			(at 0 0 90)
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 			(layer "F.Fab")
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@@ -6091,22 +6012,22 @@
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 		(pad "1" smd roundrect
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+			(at -0.949999 0 180)
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
 			(net 4 "5V")
 			(pintype "passive")
-			(uuid "47179d89-0df9-4713-9531-808323732de4")
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 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
 			(net 1 "GND")
 			(pintype "passive")
-			(uuid "d324f0ac-0787-4cda-b73f-14a235fb6b1b")
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 		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.step"
@@ -6124,11 +6045,11 @@
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 		(tags "capacitor")
 		(property "Reference" "C35"
-			(at 0 -1.16 90)
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@@ -6401,7 +6322,7 @@
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@@ -6649,7 +6570,7 @@
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-			(net 17 "V_REF = 2.048 | 2.5 | 2.9")
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@@ -6675,226 +6596,14 @@
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-		(embedded_fonts no)
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-			(rotate
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 		(layer "F.Cu")
 		(uuid "5031087b-a783-48bb-a833-625c16446537")
-		(at 130.2512 93.6752 180)
+		(at 149.0422 98.9922 180)
 		(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "resistor")
 		(property "Reference" "R23"
-			(at 0 -1.17 0)
+			(at -2.9328 -0.6578 0)
 			(layer "F.SilkS")
 			(uuid "26df543a-d1e2-4eef-bf22-820865ee5be7")
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@@ -7138,7 +6847,7 @@
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 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pintype "passive")
 			(uuid "8bff2528-fa45-41d0-a56e-e2bdbe6458cd")
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@@ -7147,7 +6856,7 @@
 			(size 0.54 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 21 "VDDA")
+			(net 11 "VDDA")
 			(pintype "passive")
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@@ -7164,1085 +6873,34 @@
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-		(layer "F.Cu")
-		(uuid "51c9840a-9fb0-4fc5-a228-b982cf52f051")
-		(at 133.604 7.4676 180)
-		(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "resistor")
-		(property "Reference" "R10"
-			(at 0 -1.17 0)
-			(layer "F.SilkS")
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-			(at 0 0 180)
-			(layer "F.Fab")
-			(uuid "fa7cb96a-0a7a-4b5d-a831-00ff87d31b3d")
-			(effects
-				(font
-					(size 0.5 0.5)
-					(thickness 0.08)
-				)
-			)
-		)
-		(pad "1" smd roundrect
-			(at -0.95 0 180)
-			(size 1 1.45)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 5 "SW")
-			(pintype "passive")
-			(uuid "93c04874-edbf-4edb-9911-5f7ee2a31635")
-		)
-		(pad "2" smd roundrect
-			(at 0.95 0 180)
-			(size 1 1.45)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 6 "Net-(U1-BST)")
-			(pintype "passive")
-			(uuid "0e8b5097-d424-4582-abe6-51ceef1d7928")
-		)
-		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.step"
-			(offset
-				(xyz 0 0 0)
-			)
-			(scale
-				(xyz 1 1 1)
-			)
-			(rotate
-				(xyz 0 0 0)
-			)
-		)
-	)
-	(footprint "Resistor_SMD:R_0603_1608Metric"
-		(layer "F.Cu")
-		(uuid "564d090b-448d-4878-9e7f-a0dc72424ce4")
-		(at 153.9504 25.0988)
-		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "resistor")
-		(property "Reference" "R19"
-			(at 0 -1.43 0)
-			(layer "F.SilkS")
-			(uuid "16d74e42-8817-4c05-b115-c07464b7fc33")
-			(effects
-				(font
-					(size 1 1)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property "Value" "20k"
-			(at 0 1.43 0)
-			(layer "F.Fab")
-			(uuid "f60d00d6-14ff-4a44-a206-4beab231db6e")
-			(effects
-				(font
-					(size 1 1)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property "Datasheet" "~"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "11079306-522f-4705-aeb4-95c38ceddd37")
-			(effects
-				(font
-					(size 1.27 1.27)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property "Description" "Resistor"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "8b1298c7-d093-4a6f-8557-2afa8729925f")
-			(effects
-				(font
-					(size 1.27 1.27)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property "MPN" "RC0603FR-1320KL"
-			(at 0 0 0)
-			(unlocked yes)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "ad3b8d74-db6f-46a2-9ba4-5399e0f6ee1f")
-			(effects
-				(font
-					(size 1 1)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property ki_fp_filters "R_*")
-		(path "/cff61884-1f0a-4ed2-9b88-049540059b97")
-		(sheetname "/")
-		(sheetfile "c64psu.kicad_sch")
-		(attr smd)
-		(fp_line
-			(start -0.237258 -0.5225)
-			(end 0.237258 -0.5225)
-			(stroke
-				(width 0.12)
-				(type solid)
-			)
-			(layer "F.SilkS")
-			(uuid "7a87d8dd-309f-4c7a-b142-a315179c0d25")
-		)
-		(fp_line
-			(start -0.237258 0.5225)
-			(end 0.237258 0.5225)
-			(stroke
-				(width 0.12)
-				(type solid)
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-			(layer "F.SilkS")
-			(uuid "5ae83ab3-b0a1-4a94-a9c0-7a977ea66cad")
-		)
-		(fp_line
-			(start -1.48 -0.73)
-			(end 1.48 -0.73)
-			(stroke
-				(width 0.05)
-				(type solid)
-			)
-			(layer "F.CrtYd")
-			(uuid "c97e03b6-2ae5-47b0-bd77-d1fbb0cd6fdf")
-		)
-		(fp_line
-			(start -1.48 0.73)
-			(end -1.48 -0.73)
-			(stroke
-				(width 0.05)
-				(type solid)
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-			(layer "F.CrtYd")
-			(uuid "cfdcde66-5775-4569-83da-34c8342412ed")
-		)
-		(fp_line
-			(start 1.48 -0.73)
-			(end 1.48 0.73)
-			(stroke
-				(width 0.05)
-				(type solid)
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-			(layer "F.CrtYd")
-			(uuid "4b03b1e9-1905-4c08-a406-9a706179818c")
-		)
-		(fp_line
-			(start 1.48 0.73)
-			(end -1.48 0.73)
-			(stroke
-				(width 0.05)
-				(type solid)
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-			(layer "F.CrtYd")
-			(uuid "b91cce6e-f84c-4268-a0f1-1b30b40b47a7")
-		)
-		(fp_line
-			(start -0.8 -0.4125)
-			(end 0.8 -0.4125)
-			(stroke
-				(width 0.1)
-				(type solid)
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-			(layer "F.Fab")
-			(uuid "bf7e10bd-ca02-4d5a-b7b2-8b28a4456a9f")
-		)
-		(fp_line
-			(start -0.8 0.4125)
-			(end -0.8 -0.4125)
-			(stroke
-				(width 0.1)
-				(type solid)
-			)
-			(layer "F.Fab")
-			(uuid "bb46dfa8-734f-4479-9c5a-a75f8df841c1")
-		)
-		(fp_line
-			(start 0.8 -0.4125)
-			(end 0.8 0.4125)
-			(stroke
-				(width 0.1)
-				(type solid)
-			)
-			(layer "F.Fab")
-			(uuid "ca76c46c-c724-4fe1-842e-f4a272f80c9b")
-		)
-		(fp_line
-			(start 0.8 0.4125)
-			(end -0.8 0.4125)
-			(stroke
-				(width 0.1)
-				(type solid)
-			)
-			(layer "F.Fab")
-			(uuid "eae43540-31e9-4c48-8fdb-5f7793a4709d")
-		)
-		(fp_text user "${REFERENCE}"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(uuid "5b3226a4-2afe-4c20-a6d8-e8093eb1b207")
-			(effects
-				(font
-					(size 0.4 0.4)
-					(thickness 0.06)
-				)
-			)
-		)
-		(pad "1" smd roundrect
-			(at -0.825 0)
-			(size 0.8 0.95)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 13 "Net-(U1-RT)")
-			(pintype "passive")
-			(uuid "fa41c760-6a75-47fb-b630-8a2d85141de3")
-		)
-		(pad "2" smd roundrect
-			(at 0.825 0)
-			(size 0.8 0.95)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 1 "GND")
-			(pintype "passive")
-			(uuid "dcc0f2a4-bd00-47c2-a11e-1a47c148b536")
-		)
-		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.step"
-			(offset
-				(xyz 0 0 0)
-			)
-			(scale
-				(xyz 1 1 1)
-			)
-			(rotate
-				(xyz 0 0 0)
-			)
-		)
-	)
 	(footprint "TestPoint:TestPoint_2Pads_Pitch2.54mm_Drill0.8mm"
 		(layer "F.Cu")
 		(uuid "576ce062-6b6e-497c-b256-542c26ea5456")
-		(at 167.64 85.6288 90)
+		(at 172.2628 85.7812 90)
 		(descr "Test point with 2 pins, pitch 2.54mm, drill diameter 0.8mm")
 		(tags "CONN DEV")
 		(property "Reference" "TP5"
-			(at 1.3 -2 90)
-			(layer "F.SilkS")
+			(at -2.7188 0.1122 -90)
+			(layer "B.SilkS")
 			(uuid "9119bb27-e52f-4538-ba42-e78db47eff63")
 			(effects
 				(font
 					(size 1 1)
 					(thickness 0.15)
 				)
+				(justify mirror)
 			)
 		)
 		(property "Value" "TestPoint_2Pole"
-			(at 1.27 2 90)
-			(layer "F.Fab")
+			(at 1.2072 11.47 -90)
+			(layer "B.Fab")
 			(uuid "51637fc4-dcb4-4ed8-805c-c5ba5b4ca0d0")
 			(effects
 				(font
 					(size 1 1)
 					(thickness 0.15)
 				)
+				(justify mirror)
 			)
 		)
 		(property "Datasheet" "~"
@@ -8437,14 +7095,15 @@
 			(uuid "1622f049-a3d3-48ff-8546-227b74634af4")
 		)
 		(fp_text user "${REFERENCE}"
-			(at 1.3 -2 90)
-			(layer "F.Fab")
+			(at 1.736 12.676 -90)
+			(layer "B.Fab")
 			(uuid "6fa9d81b-ea93-4f89-9e69-2920c4c883cf")
 			(effects
 				(font
 					(size 1 1)
 					(thickness 0.15)
 				)
+				(justify mirror)
 			)
 		)
 		(pad "1" thru_hole circle
@@ -8453,7 +7112,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 15 "9VAC2")
+			(net 5 "9VAC2")
 			(pinfunction "1")
 			(pintype "passive")
 			(uuid "d6fd6e2d-7461-4098-a88f-a42fd5e93b8b")
@@ -8464,7 +7123,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 16 "9VAC1")
+			(net 6 "9VAC1")
 			(pinfunction "2")
 			(pintype "passive")
 			(uuid "2fc535ce-e2d8-406d-8eca-63890b127748")
@@ -8474,7 +7133,7 @@
 	(footprint "Package_QFP:LQFP-48_7x7mm_P0.5mm"
 		(layer "F.Cu")
 		(uuid "591eea2c-7002-439b-99dd-a27b48041182")
-		(at 128.2192 86.0552)
+		(at 147.0102 91.3722)
 		(descr "LQFP, 48 Pin (JEDEC MS-026 variation BBC, 1.40mm body thickness, https://www.jedec.org/document_search?search_api_views_fulltext=MS-026, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/ltc-legacy-lqfp/05081760_a_lx48.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
 		(tags "LQFP QFP CASE-932AA CASE-932-03 C48-1 C48-2 C48-3 C48-5 C48-6 C48-6C PT0048A")
 		(property "Reference" "U2"
@@ -8899,7 +7558,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pinfunction "VBAT")
 			(pintype "power_in")
 			(uuid "1c2bf669-1595-442d-9f1f-7e9c7985fe0c")
@@ -8909,7 +7568,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 87 "unconnected-(U2-PC13-Pad2)")
+			(net 67 "unconnected-(U2-PC13-Pad2)")
 			(pinfunction "PC13")
 			(pintype "bidirectional")
 			(uuid "94804157-0a92-4011-ac75-a7cee12ea891")
@@ -8919,7 +7578,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 93 "unconnected-(U2-PC14-Pad3)")
+			(net 73 "unconnected-(U2-PC14-Pad3)")
 			(pinfunction "PC14")
 			(pintype "bidirectional")
 			(uuid "df8a0512-6af9-4064-8213-cf5b561da99d")
@@ -8929,7 +7588,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 72 "unconnected-(U2-PC15-Pad4)")
+			(net 52 "unconnected-(U2-PC15-Pad4)")
 			(pinfunction "PC15")
 			(pintype "bidirectional")
 			(uuid "13fd4b72-5818-4862-8f27-c37070faa54a")
@@ -8939,7 +7598,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 73 "OSC_IN")
+			(net 53 "OSC_IN")
 			(pinfunction "PF0")
 			(pintype "bidirectional")
 			(uuid "71557305-28fd-4576-9ebc-9713c1b9ba8e")
@@ -8949,7 +7608,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 62 "OSC_OUT")
+			(net 45 "OSC_OUT")
 			(pinfunction "PF1")
 			(pintype "bidirectional")
 			(uuid "d6de06d0-0be0-4e99-b12d-f89a7bf9cfad")
@@ -8959,7 +7618,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 84 "unconnected-(U2-PG10-Pad7)")
+			(net 64 "unconnected-(U2-PG10-Pad7)")
 			(pinfunction "PG10")
 			(pintype "bidirectional")
 			(uuid "720d593a-0c8a-49c2-9122-89a0c5cfd4fd")
@@ -8969,7 +7628,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 85 "unconnected-(U2-PA0-Pad8)")
+			(net 65 "unconnected-(U2-PA0-Pad8)")
 			(pinfunction "PA0")
 			(pintype "bidirectional")
 			(uuid "8008a418-846d-4a28-9ba7-86cfa364d902")
@@ -8979,7 +7638,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 70 "unconnected-(U2-PA1-Pad9)")
+			(net 50 "unconnected-(U2-PA1-Pad9)")
 			(pinfunction "PA1")
 			(pintype "bidirectional")
 			(uuid "04bf18ec-9971-4402-9121-aeb1747c6571")
@@ -8989,7 +7648,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "unconnected-(U2-PA2-Pad10)")
+			(net 61 "unconnected-(U2-PA2-Pad10)")
 			(pinfunction "PA2")
 			(pintype "bidirectional")
 			(uuid "6dd2833c-aabc-47e8-9ea5-70a40ee82591")
@@ -8999,7 +7658,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 74 "unconnected-(U2-PA3-Pad11)")
+			(net 54 "unconnected-(U2-PA3-Pad11)")
 			(pinfunction "PA3")
 			(pintype "bidirectional")
 			(uuid "31d20303-cbae-430e-986a-df7a07540b99")
@@ -9009,7 +7668,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 94 "unconnected-(U2-PA4-Pad12)")
+			(net 74 "unconnected-(U2-PA4-Pad12)")
 			(pinfunction "PA4")
 			(pintype "bidirectional")
 			(uuid "faf0be4f-bd5e-4444-b4dc-faef7d1c049c")
@@ -9019,7 +7678,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 90 "unconnected-(U2-PA5-Pad13)")
+			(net 70 "unconnected-(U2-PA5-Pad13)")
 			(pinfunction "PA5")
 			(pintype "bidirectional")
 			(uuid "af67d401-6592-4c54-be18-593c692e6ae0")
@@ -9029,7 +7688,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 86 "unconnected-(U2-PA6-Pad14)")
+			(net 66 "unconnected-(U2-PA6-Pad14)")
 			(pinfunction "PA6")
 			(pintype "bidirectional")
 			(uuid "85f243ae-71b3-4391-ae9f-6fb982ac6b6b")
@@ -9039,7 +7698,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 82 "unconnected-(U2-PA7-Pad15)")
+			(net 62 "unconnected-(U2-PA7-Pad15)")
 			(pinfunction "PA7")
 			(pintype "bidirectional")
 			(uuid "6f520a2c-9cc2-4dca-8965-1b5785783209")
@@ -9049,7 +7708,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 77 "unconnected-(U2-PB0-Pad16)")
+			(net 57 "unconnected-(U2-PB0-Pad16)")
 			(pinfunction "PB0")
 			(pintype "bidirectional")
 			(uuid "465f2d85-b8dd-4475-acce-b17d5d2d68e0")
@@ -9059,7 +7718,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 91 "unconnected-(U2-PB1-Pad17)")
+			(net 71 "unconnected-(U2-PB1-Pad17)")
 			(pinfunction "PB1")
 			(pintype "bidirectional")
 			(uuid "d2d06395-6a9e-448c-a11d-00f69269b1fd")
@@ -9069,7 +7728,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 78 "unconnected-(U2-PB2-Pad18)")
+			(net 58 "unconnected-(U2-PB2-Pad18)")
 			(pinfunction "PB2")
 			(pintype "bidirectional")
 			(uuid "5d14ac40-c5d7-4f28-8ddb-483afc496b36")
@@ -9089,7 +7748,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 17 "V_REF = 2.048 | 2.5 | 2.9")
+			(net 7 "V_REF = 2.048 | 2.5 | 2.9")
 			(pinfunction "VREF+")
 			(pintype "input")
 			(uuid "766e7fa4-5c4b-40d8-8b8c-1a4dcdfe3c8f")
@@ -9099,7 +7758,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 21 "VDDA")
+			(net 11 "VDDA")
 			(pinfunction "VDDA")
 			(pintype "power_in")
 			(uuid "0c317437-78ff-46eb-8cfa-f8f4080436d1")
@@ -9109,7 +7768,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 92 "unconnected-(U2-PB10-Pad22)")
+			(net 72 "unconnected-(U2-PB10-Pad22)")
 			(pinfunction "PB10")
 			(pintype "bidirectional")
 			(uuid "d7664fda-5617-486e-a5db-ab365751451a")
@@ -9129,7 +7788,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pinfunction "VDD")
 			(pintype "power_in")
 			(uuid "b5c205ad-f277-478b-94f8-e117a7abeca6")
@@ -9139,7 +7798,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 96 "ENABLE_DRVB")
+			(net 76 "ENABLE_DRVB")
 			(pinfunction "PB11")
 			(pintype "bidirectional")
 			(uuid "7c0e85df-f658-4618-a454-30d6ff0275b2")
@@ -9149,7 +7808,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 95 "ENABLE_DRVA")
+			(net 75 "ENABLE_DRVA")
 			(pinfunction "PB12")
 			(pintype "bidirectional")
 			(uuid "40e92b78-0b60-442e-8035-5a6d194c465d")
@@ -9159,7 +7818,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 80 "9VAC_COMP_ADC")
+			(net 60 "9VAC_COMP_ADC")
 			(pinfunction "PB13")
 			(pintype "bidirectional")
 			(uuid "c8f72e33-0e6a-4e70-bedc-228925145539")
@@ -9169,7 +7828,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 98 "CURRENT_COMP_ADC")
+			(net 77 "CURRENT_COMP_ADC")
 			(pinfunction "PB14")
 			(pintype "bidirectional")
 			(uuid "8b8d8d2d-f035-4ac4-84ee-b0fedb46116f")
@@ -9179,7 +7838,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 76 "unconnected-(U2-PB15-Pad29)")
+			(net 56 "unconnected-(U2-PB15-Pad29)")
 			(pinfunction "PB15")
 			(pintype "bidirectional")
 			(uuid "3eb967cd-1160-4325-b179-7364235e9acd")
@@ -9189,7 +7848,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 66 "PWM_G3")
+			(net 49 "PWM_G3")
 			(pinfunction "PA8")
 			(pintype "bidirectional")
 			(uuid "a21266fb-74d1-453e-b5e9-c8f36efff162")
@@ -9199,7 +7858,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 65 "PWM_G4")
+			(net 48 "PWM_G4")
 			(pinfunction "PA9")
 			(pintype "bidirectional")
 			(uuid "33b67f4e-8cc1-495c-ab03-4c5c3ea67f01")
@@ -9209,7 +7868,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 63 "PWM_G1")
+			(net 46 "PWM_G1")
 			(pinfunction "PA10")
 			(pintype "bidirectional")
 			(uuid "957a97ee-3f41-47b1-aae0-2ac73ec9836f")
@@ -9219,7 +7878,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 64 "PWM_G2")
+			(net 47 "PWM_G2")
 			(pinfunction "PA11")
 			(pintype "bidirectional")
 			(uuid "2a3f75b2-aa30-4fbd-bb42-034c5bce7faf")
@@ -9229,7 +7888,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 88 "unconnected-(U2-PA12-Pad34)")
+			(net 68 "unconnected-(U2-PA12-Pad34)")
 			(pinfunction "PA12")
 			(pintype "bidirectional")
 			(uuid "9ed2dc5a-b088-4103-afad-55083e70d5d7")
@@ -9249,7 +7908,7 @@
 			(size 1.475 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pinfunction "VDD")
 			(pintype "power_in")
 			(uuid "44a97cd3-eaf9-474e-ba68-ab7867095197")
@@ -9259,7 +7918,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 42 "JTMS")
+			(net 31 "JTMS")
 			(pinfunction "PA13")
 			(pintype "bidirectional")
 			(uuid "6abff41c-5432-45c5-a390-cce4b3274e86")
@@ -9269,7 +7928,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 83 "JTCLK")
+			(net 63 "JTCLK")
 			(pinfunction "PA14")
 			(pintype "bidirectional")
 			(uuid "afa7151d-6db3-48f6-a796-10e52e024b27")
@@ -9279,7 +7938,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 39 "JTDI")
+			(net 28 "JTDI")
 			(pinfunction "PA15")
 			(pintype "bidirectional")
 			(uuid "c818907c-ff96-4d6d-b339-f40e0dc3062a")
@@ -9289,7 +7948,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 46 "JTDO")
+			(net 35 "JTDO")
 			(pinfunction "PB3")
 			(pintype "bidirectional")
 			(uuid "282dbcdd-2184-428c-94cb-dccc37001ec4")
@@ -9299,7 +7958,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 75 "unconnected-(U2-PB4-Pad41)")
+			(net 55 "unconnected-(U2-PB4-Pad41)")
 			(pinfunction "PB4")
 			(pintype "bidirectional")
 			(uuid "3330c734-a453-429a-ae8c-147e8754bee9")
@@ -9309,7 +7968,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 79 "unconnected-(U2-PB5-Pad42)")
+			(net 59 "unconnected-(U2-PB5-Pad42)")
 			(pinfunction "PB5")
 			(pintype "bidirectional")
 			(uuid "5f165444-7ccf-4cfb-aebe-74ae20d4d037")
@@ -9319,7 +7978,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 40 "VCP_TX")
+			(net 29 "VCP_TX")
 			(pinfunction "PB6")
 			(pintype "bidirectional")
 			(uuid "3c07af1e-4f31-4cb6-baea-f16710cbd26e")
@@ -9329,7 +7988,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 45 "VCP_RX")
+			(net 34 "VCP_RX")
 			(pinfunction "PB7")
 			(pintype "bidirectional")
 			(uuid "ad4f5455-917e-4582-b6de-4fd56116ed08")
@@ -9339,7 +7998,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 89 "unconnected-(U2-PB8-Pad45)")
+			(net 69 "unconnected-(U2-PB8-Pad45)")
 			(pinfunction "PB8")
 			(pintype "bidirectional")
 			(uuid "a9d6c2c1-4aa6-478a-9d4b-bda785e3ee70")
@@ -9349,7 +8008,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 71 "unconnected-(U2-PB9-Pad46)")
+			(net 51 "unconnected-(U2-PB9-Pad46)")
 			(pinfunction "PB9")
 			(pintype "bidirectional")
 			(uuid "0714f710-17f4-4566-9bdb-5879177f7c88")
@@ -9369,7 +8028,7 @@
 			(size 0.3 1.475)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pinfunction "VDD")
 			(pintype "power_in")
 			(uuid "d93c9f60-4ff6-43f0-8aa5-c3c49db203b9")
@@ -9387,39 +8046,40 @@
 			)
 		)
 	)
-	(footprint "Capacitor_SMD:C_0402_1005Metric"
+	(footprint "KiCad:SOT95P280X95-6N"
 		(layer "F.Cu")
-		(uuid "5d31bc09-da41-4349-83ad-34e56513ed1a")
-		(at 149.2784 70.7248)
-		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "capacitor")
-		(property "Reference" "C27"
-			(at 0 -1.16 0)
+		(uuid "5a502ee0-e8a8-4e95-93b8-4c1514a99e91")
+		(at 168.6131 54.28235)
+		(descr "TSOT23-6-2")
+		(tags "Integrated Circuit")
+		(property "Reference" "IC2"
+			(at 0 0 0)
 			(layer "F.SilkS")
-			(uuid "d1ff4c70-3fa0-413f-869f-85b855e7ed0d")
+			(uuid "e789dfb7-c066-427e-84e2-9e52abcf65ec")
 			(effects
 				(font
-					(size 1 1)
-					(thickness 0.15)
+					(size 1.27 1.27)
+					(thickness 0.254)
 				)
 			)
 		)
-		(property "Value" "1uF"
-			(at 0 1.16 0)
-			(layer "F.Fab")
-			(uuid "2f0e1bdd-99e0-47c5-a9fd-bd0dbd2ec6c2")
+		(property "Value" "TPP363082-T6TR"
+			(at 0 0 0)
+			(layer "F.SilkS")
+			(hide yes)
+			(uuid "b573e556-d3f3-4924-ad8c-ac9147c8c935")
 			(effects
 				(font
-					(size 1 1)
-					(thickness 0.15)
+					(size 1.27 1.27)
+					(thickness 0.254)
 				)
 			)
 		)
-		(property "Datasheet" "~"
+		(property "Datasheet" "http://file.3peakic.com.cn:8080/product/Datasheet_TPP36308.pdf"
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "aa309eb1-2ea0-4f44-bc01-134b431b9ff3")
+			(uuid "1b9a8c3d-0d12-4a5d-b0b7-2c53cabbb1ac")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -9427,11 +8087,11 @@
 				)
 			)
 		)
-		(property "Description" "Unpolarized capacitor"
+		(property "Description" "Step-Down DC-DC Voltage Converter IC TSOT23-6"
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "407dc619-5b67-4066-b0f7-155d35dcb962")
+			(uuid "aee434bb-2574-46ec-9e59-db8cb3713142")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -9439,12 +8099,12 @@
 				)
 			)
 		)
-		(property "MPN" "CC0402KPX5R8BB105"
+		(property "Height" "0.95"
 			(at 0 0 0)
 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "e260501b-c129-438b-bf6f-08247d76a39d")
+			(uuid "678b75b8-36d0-4d90-ab05-e15c197ae096")
 			(effects
 				(font
 					(size 1 1)
@@ -9452,380 +8112,295 @@
 				)
 			)
 		)
-		(property ki_fp_filters "C_*")
-		(path "/1bbdeedc-df9f-4536-822e-32e2191fe233")
+		(property "Manufacturer_Name" "3Peak Incorporated"
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "ff0ab67f-b3b3-4006-89a6-755d6f66e0b6")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Manufacturer_Part_Number" "TPP363082-T6TR"
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "101bdb25-3e75-4c7a-bd2c-734ad877d9d0")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Mouser Part Number" ""
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "1487c1d0-cef0-43d0-9f2c-05926f694e7c")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Mouser Price/Stock" ""
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "06d0c683-d663-4d92-b0db-fab463301099")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Arrow Part Number" ""
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "3ca38625-5b76-40a6-a117-bd6d94597629")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Arrow Price/Stock" ""
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "7bec39f0-f3bc-4913-8fdc-6e76dcfcc7b3")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(path "/89fc8042-990b-4c7d-a564-d50737d3d3c2")
 		(sheetname "/")
 		(sheetfile "c64psu.kicad_sch")
 		(attr smd)
 		(fp_line
-			(start -0.107836 -0.36)
-			(end 0.107836 -0.36)
+			(start -1.85 -1.6)
+			(end -0.65 -1.6)
 			(stroke
-				(width 0.12)
+				(width 0.2)
 				(type solid)
 			)
 			(layer "F.SilkS")
-			(uuid "11df3d06-2a3d-4303-bf9b-7cb112bedceb")
+			(uuid "5945a067-14c1-48ea-903f-11153300a7d4")
 		)
 		(fp_line
-			(start -0.107836 0.36)
-			(end 0.107836 0.36)
+			(start -0.3 -1.468)
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 			(stroke
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 				(type solid)
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 			(layer "F.SilkS")
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+			(uuid "d1c51826-256a-4d7e-90ca-fbe3f0f9620e")
 		)
 		(fp_line
-			(start -0.91 -0.46)
-			(end 0.91 -0.46)
+			(start -0.3 1.468)
+			(end -0.3 -1.468)
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+				(width 0.2)
+				(type solid)
+			)
+			(layer "F.SilkS")
+			(uuid "5eb2a84a-75bc-4684-b98a-86724ef434f9")
+		)
+		(fp_line
+			(start 0.3 -1.468)
+			(end 0.3 1.468)
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+				(width 0.2)
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+			(uuid "099322a1-4dfe-4024-81b3-42f1b494c6c7")
+		)
+		(fp_line
+			(start 0.3 1.468)
+			(end -0.3 1.468)
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+				(width 0.2)
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+			)
+			(layer "F.SilkS")
+			(uuid "ecc784a9-e5ba-4d2e-9947-80eaee2c34af")
+		)
+		(fp_line
+			(start -2.1 -1.775)
+			(end 2.1 -1.775)
 			(stroke
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 			)
 			(layer "F.CrtYd")
-			(uuid "54b2e32e-9f7b-4598-9dd0-1a36c976be30")
+			(uuid "46dbf39e-5973-4d17-b858-d0c5dba53017")
 		)
 		(fp_line
-			(start -0.91 0.46)
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+			(start -2.1 1.775)
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+			(uuid "6c6c4d9e-601a-4b0a-b2c6-a92aa1522ede")
 		)
 		(fp_line
-			(start 0.91 -0.46)
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 			(layer "F.CrtYd")
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+			(uuid "edb100ce-96a8-4d7a-93e5-2a460a36bc8a")
 		)
 		(fp_line
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 			(layer "F.CrtYd")
-			(uuid "983ca59c-18aa-4f95-844b-cbb4b2a24a4e")
+			(uuid "a9ed2233-508b-4464-ac1d-52910f5e20e8")
 		)
 		(fp_line
-			(start -0.5 -0.25)
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+			(start -0.8 -1.468)
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 			(stroke
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 			(layer "F.Fab")
-			(uuid "b1361fe5-e803-4eac-bc61-d3ccab588a7e")
+			(uuid "f5918d40-9c2f-469e-be6f-a19e7705895a")
 		)
 		(fp_line
-			(start -0.5 0.25)
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 			(stroke
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-			(uuid "85db29c7-6731-4724-84a1-33164ad450e7")
+			(uuid "09537ed2-2e0c-414d-9790-2f6b544c43ee")
 		)
 		(fp_line
-			(start 0.5 -0.25)
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 			)
 			(layer "F.Fab")
-			(uuid "92436016-26f5-4aff-8a27-c67dbb2ece54")
+			(uuid "0cdb7291-d302-4d4f-bca9-88dc04d5d746")
 		)
 		(fp_line
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+			(net 82 "Net-(IC2-SW)")
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+			(uuid "49f9222b-9c57-47db-924a-f05f092af87d")
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+			(layers "F.Cu" "F.Mask" "F.Paste")
+			(net 84 "Net-(IC2-EN)")
+			(pinfunction "EN")
+			(pintype "passive")
+			(uuid "bd05ea04-e280-4077-9fb8-6ed6fc278371")
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+			(size 0.6 1.2)
+			(layers "F.Cu" "F.Mask" "F.Paste")
+			(net 83 "Net-(IC2-VBST)")
+			(pinfunction "VBST")
+			(pintype "passive")
+			(uuid "32c09055-d462-4f67-b622-96149ad90e6c")
 		)
 		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_1210_3225Metric.step"
+		(model "TPP363082-T6TR.stp"
 			(offset
 				(xyz 0 0 0)
 			)
@@ -9840,7 +8415,7 @@
 	(footprint "GSB1C4621DS1HR:AMPHENOL_GSB1C4621DS1HR"
 		(layer "F.Cu")
 		(uuid "5f2f0b99-bdb4-44f5-9350-d1ea18bc2d7f")
-		(at 115.0301 43.12985 -90)
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 		(property "Reference" "J1"
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 			(layer "F.SilkS")
@@ -10257,17 +8832,6 @@
 			(layer "F.Fab")
 			(uuid "faeb5790-2a5c-4e84-9c0a-f93dd1a207ea")
 		)
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@@ -10290,7 +8854,7 @@
 			(at -1.25 -5.149999 270)
 			(size 0.3 1.1)
 			(layers "F.Cu" "F.Mask")
-			(net 34 "CC1")
+			(net 23 "CC1")
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 			(pintype "bidirectional")
 			(uuid "694e61bc-a83a-499d-8d8a-1ca16347a89b")
@@ -10299,7 +8863,7 @@
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 			(size 0.3 1.1)
 			(layers "F.Cu" "F.Mask")
-			(net 33 "DP")
+			(net 22 "DP")
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 			(uuid "106ae5b1-e396-4630-ad91-664fa1c2f851")
@@ -10308,7 +8872,7 @@
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 			(size 0.3 1.1)
 			(layers "F.Cu" "F.Mask")
-			(net 28 "DN")
+			(net 17 "DN")
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 			(uuid "ed50b056-1f7c-4cb8-b38b-1bcca0b8a0c8")
@@ -10317,7 +8881,7 @@
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 			(size 0.3 1.1)
 			(layers "F.Cu" "F.Mask")
-			(net 36 "unconnected-(J1-SBU1-PadA8)")
+			(net 25 "unconnected-(J1-SBU1-PadA8)")
 			(pinfunction "SBU1")
 			(pintype "bidirectional+no_connect")
 			(uuid "07248a5f-965b-420e-ac49-11b587588fa8")
@@ -10344,7 +8908,7 @@
 			(at 1.75 -5.15 270)
 			(size 0.3 1.1)
 			(layers "F.Cu" "F.Mask")
-			(net 35 "CC2")
+			(net 24 "CC2")
 			(pinfunction "CC2")
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 			(uuid "326a6132-b2ef-4a8c-bcbe-3b884dcb6206")
@@ -10353,7 +8917,7 @@
 			(at 0.75 -5.15 270)
 			(size 0.3 1.1)
 			(layers "F.Cu" "F.Mask")
-			(net 33 "DP")
+			(net 22 "DP")
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 			(pintype "bidirectional")
 			(uuid "ea3b85cc-aae8-4264-87cb-04844ce86139")
@@ -10362,7 +8926,7 @@
 			(at -0.75 -5.15 270)
 			(size 0.3 1.1)
 			(layers "F.Cu" "F.Mask")
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@@ -10371,7 +8935,7 @@
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 			(size 0.3 1.1)
 			(layers "F.Cu" "F.Mask")
-			(net 37 "unconnected-(J1-SBU2-PadB8)")
+			(net 26 "unconnected-(J1-SBU2-PadB8)")
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 			(pintype "bidirectional+no_connect")
 			(uuid "af9f9b2f-77e0-4aaa-869b-3543c0b01641")
@@ -10440,7 +9004,7 @@
 	(footprint "Capacitor_SMD:C_1210_3225Metric"
 		(layer "F.Cu")
 		(uuid "5f8ce8fe-7c0a-4d19-91a1-8625cfbac55f")
-		(at 149.461059 85.355444 -90)
+		(at 156.369859 87.235044 -90)
 		(descr "Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C33"
@@ -10675,16 +9239,16 @@
 			)
 		)
 	)
-	(footprint "Resistor_SMD:R_0603_1608Metric"
+	(footprint "Capacitor_SMD:C_1210_3225Metric"
 		(layer "F.Cu")
-		(uuid "6575ec81-a5d5-4529-b9d4-a9b081230211")
-		(at 153.9504 22.5888)
-		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "resistor")
-		(property "Reference" "R18"
-			(at 0 -1.43 0)
+		(uuid "6357c846-c523-45c9-84bd-ba6091756580")
+		(at 155.95 58.375)
+		(descr "Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+		(tags "capacitor")
+		(property "Reference" "C8"
+			(at -0.082895 2.24725 0)
 			(layer "F.SilkS")
-			(uuid "7444646f-bf21-4d5f-8a09-4cb7e503754b")
+			(uuid "aebfadae-81d7-4523-b1c1-7f0927dc745f")
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@@ -10692,10 +9256,10 @@
 				)
 			)
 		)
-		(property "Value" "3.83k 0.1%"
-			(at 0 1.43 0)
+		(property "Value" "10uF"
+			(at 0 2.300001 0)
 			(layer "F.Fab")
-			(uuid "a6a3d23f-9e2f-45b9-ad94-5954e02a0039")
+			(uuid "7829b928-c8ba-49d2-838f-e934da2868f6")
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@@ -10703,11 +9267,11 @@
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+		(property "Datasheet" "https://ds.yuden.co.jp/TYCOMPAS/ut/detail?pn=MSASU32MSB5106KPNA01&u=M"
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "663f5619-a894-4966-835c-694b63f9bb72")
+			(uuid "10cdc4df-eff8-4671-90e3-ba567bf1b9b5")
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@@ -10715,11 +9279,11 @@
 				)
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 		)
-		(property "Description" "Resistor"
+		(property "Description" "Unpolarized capacitor"
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 			(layer "F.Fab")
 			(hide yes)
-			(uuid "2ea5003b-93a5-4b09-a09f-2cc7259c77e1")
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@@ -10727,12 +9291,12 @@
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@@ -10766,142 +9330,142 @@
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 		(fp_text user "${REFERENCE}"
 			(at 0 0 0)
 			(layer "F.Fab")
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+			(uuid "a020221c-fefa-4dcf-bd49-51735515c2e0")
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 		(pad "1" smd roundrect
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+			(at -1.475001 0)
+			(size 1.15 2.7)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 11 "Net-(C16-Pad2)")
+			(roundrect_rratio 0.217391)
+			(net 1 "GND")
 			(pintype "passive")
-			(uuid "6b00109f-8595-47c1-83d2-154991e66fa2")
+			(uuid "9276266c-1b9c-4b9c-9cc2-28be31e8bb76")
 		)
 		(pad "2" smd roundrect
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+			(at 1.475001 0)
+			(size 1.15 2.7)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 9 "Net-(U1-FB)")
+			(roundrect_rratio 0.217391)
+			(net 3 "15V")
 			(pintype "passive")
-			(uuid "728a627a-22bd-4b17-aed3-fe81be7ed202")
+			(uuid "dcc54079-9622-4ad9-ad94-adc718280130")
 		)
 		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.step"
+		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_1210_3225Metric.step"
 			(offset
 				(xyz 0 0 0)
 			)
@@ -10916,7 +9480,7 @@
 	(footprint "TestPoint:TestPoint_2Pads_Pitch2.54mm_Drill0.8mm"
 		(layer "F.Cu")
 		(uuid "67e91030-4ce7-4a4b-b954-d94406f2e826")
-		(at 142.9596 97.6276)
+		(at 166.574999 97.1 180)
 		(descr "Test point with 2 pins, pitch 2.54mm, drill diameter 0.8mm")
 		(tags "CONN DEV")
 		(property "Reference" "TP3"
@@ -10942,7 +9506,7 @@
 			)
 		)
 		(property "Datasheet" "~"
-			(at 0 0 0)
+			(at 0 0 180)
 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
@@ -10955,7 +9519,7 @@
 			)
 		)
 		(property "Description" "2-polar test point"
-			(at 0 0 0)
+			(at 0 0 180)
 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
@@ -10973,64 +9537,14 @@
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 			(layer "F.CrtYd")
-			(uuid "4c227f02-c8a6-4da7-ab9c-abccaf6fdb5b")
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+			(uuid "191564b8-9839-4026-9bd6-9acf916c2ab7")
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+			(uuid "58c93149-20d0-4c6e-af3a-ec3a22931ec4")
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+			(stroke
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+			(layer "F.CrtYd")
+			(uuid "367e391f-9eff-4f80-b3e5-7d6b58bf81e8")
+		)
+		(fp_line
+			(start -1.3 -0.5)
+			(end -1.3 0.5)
+			(stroke
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+			(layer "F.CrtYd")
+			(uuid "5c7a61b8-8541-4c52-9660-8ce25ed4b564")
 		)
 		(fp_text user "${REFERENCE}"
 			(at 1.3 -2 0)
@@ -11144,18 +9708,18 @@
 			)
 		)
 		(pad "1" thru_hole circle
-			(at 0 0)
+			(at 0 0 180)
 			(size 1.4 1.4)
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 65 "PWM_G4")
+			(net 48 "PWM_G4")
 			(pinfunction "1")
 			(pintype "passive")
 			(uuid "ff6a7b0c-6b42-4863-a089-1d2da5837235")
 		)
 		(pad "2" thru_hole circle
-			(at 2.54 0)
+			(at 2.54 0 180)
 			(size 1.4 1.4)
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
@@ -11170,11 +9734,11 @@
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "F.Cu")
 		(uuid "68a43063-33b6-48c5-b50f-cc6723842832")
-		(at 157.8356 79.9084 180)
+		(at 164.7444 81.788 180)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C28"
-			(at 0 -1.16 0)
+			(at -2.5556 -0.062 0)
 			(layer "F.SilkS")
 			(uuid "5141aba2-cd29-436d-be16-3b69f97b3714")
 			(effects
@@ -11382,11 +9946,11 @@
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "F.Cu")
 		(uuid "6aed9c8a-278c-4eff-b7c4-beb476cf2a93")
-		(at 122.5296 82.804 90)
+		(at 141.3206 88.121 90)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C61"
-			(at 0 -1.16 90)
+			(at 1.096 -1.1956 90)
 			(layer "F.SilkS")
 			(uuid "f9fbf24d-c856-4659-aecc-9123bc0f4937")
 			(effects
@@ -11630,7 +10194,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pintype "passive")
 			(uuid "713b0775-08e0-4665-8f3e-55c89a80b7a4")
 		)
@@ -11656,254 +10220,16 @@
 			)
 		)
 	)
-	(footprint "Resistor_SMD:R_0402_1005Metric"
-		(layer "F.Cu")
-		(uuid "6c0ab79e-1348-48c3-aeb5-ce9a0a661d56")
-		(at 138.176 7.0104 -90)
-		(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "resistor")
-		(property "Reference" "R11"
-			(at 0 -1.17 90)
-			(layer "F.SilkS")
-			(uuid "0afe9dd3-fe94-4cc3-b086-0f7d974aa1d6")
-			(effects
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-					(thickness 0.15)
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-		)
-		(property "Value" "1"
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-		(pad "1" smd roundrect
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-			(size 0.54 0.64)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 56 "Net-(U1-LO)")
-			(pintype "passive")
-			(uuid "cfb61711-788f-4713-aa60-fe01e03f0641")
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-		(pad "2" smd roundrect
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-			(size 0.54 0.64)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 50 "Net-(Q7-Pad4)")
-			(pintype "passive")
-			(uuid "eacd30ec-24d3-454d-9244-d8573cbac9d9")
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-		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.step"
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-			(scale
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-			(rotate
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 	(footprint "Capacitor_SMD:C_0603_1608Metric"
 		(layer "F.Cu")
 		(uuid "7bf51e9f-8823-4ef4-8151-14b0304534b5")
-		(at 124.7648 44.0436 -90)
+		(at 144.5847 54.68875 -90)
 		(descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C1"
 			(at 0 -1.43 90)
 			(layer "F.SilkS")
-			(uuid "3cab7309-9097-4dd4-8a2d-c71ef55ba1ab")
+			(uuid "2e52876a-ff35-44fa-89b1-71d1181e1fb0")
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 		(property "Value" "10uF"
 			(at 0 1.43 90)
 			(layer "F.Fab")
-			(uuid "f1b83e28-5144-4fb0-85d7-8bba30ac272d")
+			(uuid "cd96480a-11f5-46a0-b72f-35870ad190f6")
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@@ -11926,7 +10252,7 @@
 			(at 0 0 90)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "8d8b7e0e-d64e-493d-9d26-aba7e02c6bda")
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@@ -11938,7 +10264,7 @@
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 			(layer "F.Fab")
 			(hide yes)
-			(uuid "59cbc33e-6fe1-4e9c-a422-92a37263e5e1")
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 			(effects
 				(font
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@@ -12106,14 +10432,212 @@
 			)
 		)
 	)
+	(footprint "custom:CSBX1060"
+		(layer "F.Cu")
+		(uuid "7cd867d2-49dc-4834-b0c1-70193583d7cf")
+		(at 169.0195 45.54475 90)
+		(property "Reference" "L1"
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+			(unlocked yes)
+			(layer "F.SilkS")
+			(uuid "57c07912-9d22-4b5f-a616-ae9a687df033")
+			(effects
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+		(property "Value" "15uH"
+			(at 0 1 90)
+			(unlocked yes)
+			(layer "F.Fab")
+			(uuid "9fbd5f2b-bad6-4239-9426-266c6bbe9de0")
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+		(property "Datasheet" "~"
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+			(unlocked yes)
+			(layer "F.Fab")
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+			(uuid "023e6b33-0f7b-41d1-ae70-67dc53d86052")
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+		(property "Description" "Inductor"
+			(at 0 0 90)
+			(unlocked yes)
+			(layer "F.Fab")
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+			(uuid "48b03e5f-8e92-4914-8f5c-ac7fe712551d")
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+		(property "MPN" "CSBX1060-150M"
+			(at 0 0 90)
+			(unlocked yes)
+			(layer "F.Fab")
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+			(uuid "a55af99f-0899-4a58-ac8b-e613b05196a3")
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+		(property ki_fp_filters "Choke_* *Coil* Inductor_* L_*")
+		(path "/9101fc58-c1a6-494e-b931-fa93c5707ee2")
+		(sheetname "/")
+		(sheetfile "c64psu.kicad_sch")
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+			(pts
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+			)
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+				(width 0.05)
+				(type solid)
+			)
+			(fill no)
+			(layer "F.CrtYd")
+			(uuid "461cf6e2-9649-40ad-86d5-1a9cd13c9bd8")
+		)
+		(fp_text user "${REFERENCE}"
+			(at 0 2.5 90)
+			(unlocked yes)
+			(layer "F.Fab")
+			(uuid "4652d8f9-bac0-4054-a9fb-2faf5be3a6a5")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
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+		)
+		(pad "1" smd roundrect
+			(at 0 -3.824999 90)
+			(size 3.85 3.85)
+			(layers "F.Cu" "F.Mask" "F.Paste")
+			(roundrect_rratio 0.15)
+			(net 82 "Net-(IC2-SW)")
+			(pinfunction "1")
+			(pintype "passive")
+			(uuid "ec1f89eb-cf9a-4dbc-93c1-f562671418e5")
+		)
+		(pad "2" smd roundrect
+			(at 0 3.824999 90)
+			(size 3.85 3.85)
+			(layers "F.Cu" "F.Mask" "F.Paste")
+			(roundrect_rratio 0.15)
+			(net 4 "5V")
+			(pinfunction "2")
+			(pintype "passive")
+			(uuid "888751a4-6add-4665-af42-b518529c509e")
+		)
+		(embedded_fonts no)
+	)
 	(footprint "DI025N06PT:TRANS_DI025N06PT-AQ"
 		(layer "F.Cu")
 		(uuid "80d848ab-818c-4c6f-b791-edfe63fd79d5")
-		(at 133.0452 43.0276)
+		(at 152.8651 53.67275)
 		(property "Reference" "Q5"
 			(at 1.125 -3.075 0)
 			(layer "F.SilkS")
-			(uuid "79d209ca-53d7-485b-b0a1-97ea725b3c5a")
+			(uuid "c66c2fea-7595-4a42-a7bd-d938f9a10516")
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@@ -12122,9 +10646,9 @@
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 		)
 		(property "Value" "DI025N06PT-AQ"
-			(at 9.915799 3.1674 0)
+			(at 9.971099 3.694249 0)
 			(layer "F.Fab")
-			(uuid "dc6d0034-d241-4ead-babd-21b42480bd4d")
+			(uuid "ddcc228e-8c34-49a8-b200-ca345cecfe51")
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@@ -12136,7 +10660,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "0df75f4a-1d99-4c78-9588-a806765f9e68")
+			(uuid "f5d20826-0952-48e0-be8f-87943a9e3824")
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@@ -12148,7 +10672,7 @@
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 			(layer "F.Fab")
 			(hide yes)
-			(uuid "9afb7c18-a5d5-4ec6-9bfe-93db4cb8d838")
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@@ -12438,7 +10962,7 @@
 			(at -1.5 -0.975)
 			(size 0.7 0.42)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 31 "Net-(IC1-VCC)")
+			(net 20 "Net-(IC1-VCC)")
 			(pintype "passive")
 			(solder_mask_margin 0.102)
 			(uuid "fc652a3f-7c28-436a-aaa0-3a1e0825138a")
@@ -12447,7 +10971,7 @@
 			(at -1.5 -0.325)
 			(size 0.7 0.42)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 31 "Net-(IC1-VCC)")
+			(net 20 "Net-(IC1-VCC)")
 			(pintype "passive")
 			(solder_mask_margin 0.102)
 			(uuid "1ad6b809-b0d1-4121-9d48-1d1074cb1a1b")
@@ -12456,7 +10980,7 @@
 			(at -1.5 0.325)
 			(size 0.7 0.42)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 31 "Net-(IC1-VCC)")
+			(net 20 "Net-(IC1-VCC)")
 			(pintype "passive")
 			(solder_mask_margin 0.102)
 			(uuid "5e7633e7-327a-4ac1-90b0-97856e611e38")
@@ -12465,7 +10989,7 @@
 			(at -1.5 0.975)
 			(size 0.7 0.42)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 47 "Net-(Q1-Pad4)")
+			(net 36 "Net-(Q1-Pad4)")
 			(pintype "passive")
 			(solder_mask_margin 0.102)
 			(uuid "0344b5aa-042e-4a72-802d-cdc60a9e8227")
@@ -12474,7 +10998,7 @@
 			(at 0 0)
 			(size 0.7 0.42)
 			(layers "F.Cu")
-			(net 48 "Net-(Q1-Pad5_8)")
+			(net 37 "Net-(Q1-Pad5_8)")
 			(pintype "passive")
 			(options
 				(clearance outline)
@@ -12497,16 +11021,16 @@
 		)
 		(embedded_fonts no)
 	)
-	(footprint "LV5144:VQFN20_RGY_TEX"
+	(footprint "MountingHole:MountingHole_3.2mm_M3_DIN965_Pad_TopBottom"
 		(layer "F.Cu")
-		(uuid "822ded8b-36ad-4b67-9825-e0dbb3a03f81")
-		(at 135.435301 -0.265999 -90)
-		(tags "LV5144RGYR ")
-		(property "Reference" "U1"
-			(at 0 0 270)
-			(unlocked yes)
+		(uuid "84802582-c7a3-4c62-bce2-e59a380c3a68")
+		(at 140 105)
+		(descr "Mounting Hole 3.2mm, M3, generated by kicad-footprint-generator mountinghole.py")
+		(tags "mountinghole M3 DIN965")
+		(property "Reference" "H3"
+			(at 0 -3.75 0)
 			(layer "F.SilkS")
-			(uuid "fb9da3f9-d014-4fbd-8930-936b2611dd6c")
+			(uuid "17fd8473-31be-4555-b5f5-47d8517c740a")
 			(effects
 				(font
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@@ -12514,739 +11038,10 @@
 				)
 			)
 		)
-		(property "Value" "LV5144RGYR"
-			(at 0 0 270)
-			(unlocked yes)
+		(property "Value" "MountingHole_Pad"
+			(at 0 3.75 0)
 			(layer "F.Fab")
-			(uuid "5a0aeb68-bc0c-43f7-a9c8-4a4318ff2864")
-			(effects
-				(font
-					(size 1 1)
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 		(layer "F.Cu")
 		(uuid "8956c995-5caf-4690-8c1d-d09927afbc8b")
-		(at 122.0724 71.5772 -90)
+		(at 140.8634 76.8942 -90)
 		(descr "surface-mounted straight pin header, 2x07, 1.27mm pitch, double rows")
 		(tags "Surface mounted pin header SMD 2x07 1.27mm double row")
 		(property "Reference" "J3"
@@ -14365,7 +11849,7 @@
 			(at -1.95 -3.81 270)
 			(size 2.4 0.74)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 43 "unconnected-(J3-NC-Pad1)")
+			(net 32 "unconnected-(J3-NC-Pad1)")
 			(pinfunction "NC")
 			(pintype "no_connect")
 			(uuid "8f73fc7f-e4b4-4fb1-ad73-e3f48f2ee174")
@@ -14374,7 +11858,7 @@
 			(at 1.95 -3.81 270)
 			(size 2.4 0.74)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 41 "unconnected-(J3-NC-Pad2)")
+			(net 30 "unconnected-(J3-NC-Pad2)")
 			(pinfunction "NC")
 			(pintype "no_connect")
 			(uuid "72936e08-0b20-4062-bfe6-adb9b3a5373f")
@@ -14383,7 +11867,7 @@
 			(at -1.95 -2.54 270)
 			(size 2.4 0.74)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pinfunction "VCC")
 			(pintype "power_in")
 			(uuid "ed748e6c-41bd-4ee4-8777-9d6504edd61e")
@@ -14392,7 +11876,7 @@
 			(at 1.95 -2.54 270)
 			(size 2.4 0.74)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 42 "JTMS")
+			(net 31 "JTMS")
 			(pinfunction "JTMS/SWDIO")
 			(pintype "bidirectional")
 			(uuid "740b2a82-3e11-44d2-8a0b-8d0bcd8de181")
@@ -14410,7 +11894,7 @@
 			(at 1.95 -1.27 270)
 			(size 2.4 0.74)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 83 "JTCLK")
+			(net 63 "JTCLK")
 			(pinfunction "JCLK/SWCLK")
 			(pintype "output")
 			(uuid "f24b3960-e048-4843-849d-068f589619bc")
@@ -14428,7 +11912,7 @@
 			(at 1.95 0 270)
 			(size 2.4 0.74)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 46 "JTDO")
+			(net 35 "JTDO")
 			(pinfunction "JTDO/SWO")
 			(pintype "input")
 			(uuid "d2d464cd-c79f-4e5b-8829-c93a63e44b5b")
@@ -14437,7 +11921,7 @@
 			(at -1.95 1.27 270)
 			(size 2.4 0.74)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 44 "unconnected-(J3-JRCLK{slash}NC-Pad9)")
+			(net 33 "unconnected-(J3-JRCLK{slash}NC-Pad9)")
 			(pinfunction "JRCLK/NC")
 			(pintype "input+no_connect")
 			(uuid "96703882-6eb4-4e5f-a1dc-f6432a5d3461")
@@ -14446,7 +11930,7 @@
 			(at 1.95 1.27 270)
 			(size 2.4 0.74)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 39 "JTDI")
+			(net 28 "JTDI")
 			(pinfunction "JTDI/NC")
 			(pintype "output")
 			(uuid "25906879-095a-4333-806c-4bbc5699937c")
@@ -14464,7 +11948,7 @@
 			(at 1.95 2.54 270)
 			(size 2.4 0.74)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 38 "NRST")
+			(net 27 "NRST")
 			(pinfunction "~{RST}")
 			(pintype "open_collector")
 			(uuid "24b44b0c-48e0-4310-88b9-a4dfdd447efe")
@@ -14473,7 +11957,7 @@
 			(at -1.95 3.81 270)
 			(size 2.4 0.74)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 45 "VCP_RX")
+			(net 34 "VCP_RX")
 			(pinfunction "VCP_RX")
 			(pintype "output")
 			(uuid "b59ec308-d097-44e8-99d6-b46eb981bc40")
@@ -14482,7 +11966,7 @@
 			(at 1.95 3.81 270)
 			(size 2.4 0.74)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 40 "VCP_TX")
+			(net 29 "VCP_TX")
 			(pinfunction "VCP_TX")
 			(pintype "input")
 			(uuid "5cb0f59c-7352-41dd-ab8a-84d53813534d")
@@ -14500,646 +11984,10 @@
 			)
 		)
 	)
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-		(uuid "8b20212d-eb16-47ce-a5dc-e62ab7610115")
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-		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "resistor")
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-			(layers "F.Cu" "F.Mask" "F.Paste")
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-			(net 3 "15V")
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-			(net 25 "Net-(IC1-VOUT)")
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-		(embedded_fonts no)
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-		(tags "resistor")
-		(property "Reference" "R13"
-			(at 0 -1.43 0)
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-			(net 7 "Net-(U1-EN{slash}UVLO)")
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-			(net 1 "GND")
-			(pintype "passive")
-			(uuid "97c279e0-4fd2-408a-ac67-dd4072ea374e")
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-		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.step"
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 		(layer "F.Cu")
 		(uuid "9028e3f3-03ea-4c29-bf13-e7b1872741e3")
-		(at 124.9172 80.4164)
+		(at 143.7082 85.7334)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C47"
@@ -15396,7 +12244,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pintype "passive")
 			(uuid "25938617-0250-4514-ba40-78d3bc4bbbc0")
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@@ -15413,16 +12261,16 @@
 			)
 		)
 	)
-	(footprint "Resistor_SMD:R_0603_1608Metric"
+	(footprint "Capacitor_SMD:C_0805_2012Metric"
 		(layer "F.Cu")
-		(uuid "97c3592f-bf7f-472d-8d9e-dc6b4318c153")
-		(at 119.5274 51.9036 180)
-		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "resistor")
-		(property "Reference" "R6"
-			(at 0 -1.43 0)
+		(uuid "96add98a-ac11-4d71-8277-3a1df8d307d6")
+		(at 176.5887 45.84955)
+		(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+		(tags "capacitor")
+		(property "Reference" "C6"
+			(at 2.8613 0.05045 0)
 			(layer "F.SilkS")
-			(uuid "9a89e7aa-1344-4a13-a451-7b5e1f1a785e")
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@@ -15430,10 +12278,10 @@
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-		(property "Value" "52k 1%"
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+		(property "Value" "10uF"
+			(at 0 1.679999 0)
 			(layer "F.Fab")
-			(uuid "3758963a-1338-493c-9709-4c22b42ae255")
+			(uuid "32a3abe6-a77c-4fc0-b828-b318d7767ec8")
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@@ -15445,7 +12293,245 @@
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+			(uuid "8b74afb5-3bc4-4667-8056-1031586e01e1")
+		)
+		(fp_text user "${REFERENCE}"
+			(at 0 0 0)
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+			(uuid "349e595f-245a-4adc-b315-8901d08b6826")
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+		(pad "1" smd roundrect
+			(at -0.949999 0)
+			(size 1 1.45)
+			(layers "F.Cu" "F.Mask" "F.Paste")
+			(roundrect_rratio 0.25)
+			(net 4 "5V")
+			(pintype "passive")
+			(uuid "3e95f861-6d0b-4adb-97a3-4391b894b235")
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+		(pad "2" smd roundrect
+			(at 0.949999 0)
+			(size 1 1.45)
+			(layers "F.Cu" "F.Mask" "F.Paste")
+			(roundrect_rratio 0.25)
+			(net 1 "GND")
+			(pintype "passive")
+			(uuid "09c5d706-9469-48b8-97c0-6f81a4e6e0b2")
+		)
+		(embedded_fonts no)
+		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.step"
+			(offset
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+			(scale
+				(xyz 1 1 1)
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+			(rotate
+				(xyz 0 0 0)
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+		)
+	)
+	(footprint "Resistor_SMD:R_0603_1608Metric"
+		(layer "F.Cu")
+		(uuid "97c3592f-bf7f-472d-8d9e-dc6b4318c153")
+		(at 139.3473 62.54875 180)
+		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+		(tags "resistor")
+		(property "Reference" "R6"
+			(at 2.4973 -0.00125 0)
+			(layer "F.SilkS")
+			(uuid "643f7caf-5e84-42fa-b28b-3e19ea3da806")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
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+		(property "Value" "52k 1%"
+			(at 0 1.43 0)
+			(layer "F.Fab")
+			(uuid "17adc4ab-b880-4564-b84b-357876f41e09")
+			(effects
+				(font
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+					(thickness 0.15)
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+		(property "Datasheet" "~"
+			(at 0 0 0)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "eab56339-e1aa-4894-8932-5bf4027ac3a3")
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@@ -15457,7 +12543,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "44b51510-98f1-44b6-9963-ea424c470a6f")
+			(uuid "5ead34c9-9d53-46a8-8dc6-2aae6b57f8c0")
 			(effects
 				(font
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@@ -15599,7 +12685,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 32 "Net-(IC1-ISEL)")
+			(net 21 "Net-(IC1-ISEL)")
 			(pintype "passive")
 			(uuid "fea0b12d-5859-4a0f-ba7c-e9dbf9239a95")
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@@ -15628,11 +12714,11 @@
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "F.Cu")
 		(uuid "9931c949-e338-4c49-a48f-5e97af0ea0c7")
-		(at 132.334 90.424)
+		(at 151.125 95.741)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C59"
-			(at 0 -1.16 0)
+			(at 2.475 0.034 0)
 			(layer "F.SilkS")
 			(uuid "13afe22a-0658-4102-bb26-4285086b5551")
 			(effects
@@ -15876,7 +12962,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pintype "passive")
 			(uuid "94c55e9b-e816-4566-99e4-0fd6bdba84d4")
 		)
@@ -15905,10 +12991,10 @@
 	(footprint "Crystal:Crystal_SMD_2520-4Pin_2.5x2.0mm"
 		(layer "F.Cu")
 		(uuid "996191b7-5354-4fea-ad28-a72d82f13720")
-		(at 120.5992 85.8012 45)
+		(at 139.3902 91.1182 45)
 		(descr "SMD2520/4, Crystal, 2.5x2.0mm package, SMD, generated with kicad-footprint-generator make_crystal.py, http://www.newxtal.com/UploadFiles/Images/2012-11-12-09-29-09-776.pdf")
 		(property "Reference" "Y2"
-			(at 0 -2.2 45)
+			(at -3.286864 0.116865 45)
 			(layer "F.SilkS")
 			(uuid "ab52a3f4-36ca-4ff7-8cf1-532c4458ee94")
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@@ -16096,7 +13182,7 @@
 			(size 1.15 1)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 62 "OSC_OUT")
+			(net 45 "OSC_OUT")
 			(pinfunction "1")
 			(pintype "passive")
 			(uuid "abbe4187-339d-48f1-bf5b-3963c5b3000b")
@@ -16116,7 +13202,7 @@
 			(size 1.15 1)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 73 "OSC_IN")
+			(net 53 "OSC_IN")
 			(pinfunction "3")
 			(pintype "passive")
 			(uuid "b0720097-6a15-4677-bcf1-fea8f952ff77")
@@ -16144,252 +13230,14 @@
 			)
 		)
 	)
-	(footprint "Resistor_SMD:R_0402_1005Metric"
-		(layer "F.Cu")
-		(uuid "99673c43-861d-4a20-bfdf-b16a8962bfe5")
-		(at 167.5104 15.2288)
-		(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "resistor")
-		(property "Reference" "R15"
-			(at 0 -1.17 0)
-			(layer "F.SilkS")
-			(uuid "c66a12de-79fd-41a5-a079-9724e71b45c1")
-			(effects
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+			(net 1 "GND")
+			(pintype "passive")
+			(uuid "be530fa1-4c85-4762-ae79-766c3d68d152")
+		)
+		(embedded_fonts no)
+		(model "${KICAD9_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.step"
+			(offset
+				(xyz 0 0 0)
+			)
+			(scale
+				(xyz 1 1 1)
+			)
+			(rotate
+				(xyz 0 0 0)
+			)
+		)
+	)
 	(footprint "Package_TO_SOT_SMD:SOT-23-5"
 		(layer "F.Cu")
 		(uuid "a2a8f815-24b1-4e38-87c7-936b04fbf5c7")
-		(at 134.9389 71.4248 -90)
+		(at 151.064199 77.8577 -90)
 		(descr "SOT, 5 Pin (JEDEC MO-178 Var AA https://www.jedec.org/document_search?search_api_views_fulltext=MO-178), generated with kicad-footprint-generator ipc_gullwing_generator.py")
 		(tags "SOT TO_SOT_SMD")
 		(property "Reference" "U8"
@@ -17275,7 +14322,7 @@
 			(size 1.325 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 100 "unconnected-(U8-NC-Pad4)")
+			(net 79 "unconnected-(U8-NC-Pad4)")
 			(pinfunction "NC")
 			(pintype "no_connect")
 			(uuid "6f2f149d-2ef1-4075-953c-09176871e2b1")
@@ -17285,7 +14332,7 @@
 			(size 1.325 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pinfunction "OUT")
 			(pintype "power_out")
 			(uuid "945ec520-b944-4f59-8b09-4ca3e90101e1")
@@ -17303,16 +14350,16 @@
 			)
 		)
 	)
-	(footprint "Capacitor_SMD:C_0805_2012Metric"
+	(footprint "Capacitor_SMD:C_1210_3225Metric"
 		(layer "F.Cu")
-		(uuid "ac4179d2-894b-4905-b19a-7d28e5225432")
-		(at 126.8476 21.9964 90)
-		(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
+		(uuid "aba49755-471f-423a-a656-5555d8b57440")
+		(at 161.0947 52.19955 -90)
+		(descr "Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
-		(property "Reference" "C4"
-			(at 0 -1.679999 90)
+		(property "Reference" "C10"
+			(at -2.99955 -0.0553 180)
 			(layer "F.SilkS")
-			(uuid "fc549cec-55f4-4de3-a9af-343fba6ce4d0")
+			(uuid "885386da-6f6c-4b03-8d3e-65679f556bdd")
 			(effects
 				(font
 					(size 1 1)
@@ -17321,9 +14368,9 @@
 			)
 		)
 		(property "Value" "10uF"
-			(at 0 1.679999 90)
+			(at 0 2.300001 90)
 			(layer "F.Fab")
-			(uuid "062882f0-941f-4326-8a5a-91aeecef30c3")
+			(uuid "f20ddebb-e766-443a-9cc4-052e9d333670")
 			(effects
 				(font
 					(size 1 1)
@@ -17331,11 +14378,11 @@
 				)
 			)
 		)
-		(property "Datasheet" "~"
+		(property "Datasheet" "https://ds.yuden.co.jp/TYCOMPAS/ut/detail?pn=MSASU32MSB5106KPNA01&u=M"
 			(at 0 0 90)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "78f33072-c059-4f1c-bdc2-2f91401860bb")
+			(uuid "52cd8591-278e-43f6-a748-62db2e056cff")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -17347,7 +14394,7 @@
 			(at 0 0 90)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "a547d358-9d35-4bd1-9165-11a52247946c")
+			(uuid "c5c18e62-004f-4a4a-8872-fa63529c113e")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -17355,12 +14402,12 @@
 				)
 			)
 		)
-		(property "MPN" "GRM21BR61C106KE15K"
-			(at 0 0 90)
+		(property "MPN" "UMK325BJ106KM-P"
+			(at 0 0 270)
 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "56870283-bb4b-4817-8363-48655b131ffe")
+			(uuid "1293292e-453e-49b0-9f13-2e46cce24f24")
 			(effects
 				(font
 					(size 1 1)
@@ -17369,11 +14416,11 @@
 			)
 		)
 		(property "Part Number" ""
-			(at 0 0 90)
+			(at 0 0 270)
 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "a4c76d4c-512d-4909-b0e9-ec3c58943bca")
+			(uuid "0ae36dd7-d4a4-4d7d-899c-8783563743bb")
 			(effects
 				(font
 					(size 1 1)
@@ -17382,11 +14429,11 @@
 			)
 		)
 		(property "Specifications" ""
-			(at 0 0 90)
+			(at 0 0 270)
 			(unlocked yes)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "2646b475-7fe5-491d-b066-e5ce105b6906")
+			(uuid "73941fa3-1b1b-4f2f-839d-740957b4b1e5")
 			(effects
 				(font
 					(size 1 1)
@@ -17395,141 +14442,141 @@
 			)
 		)
 		(property ki_fp_filters "C_*")
-		(path "/13733f7c-0281-4309-b20f-1ae935527f44")
+		(path "/2fd42189-ede2-4b50-a44d-da6f190fa22d")
 		(sheetname "/")
 		(sheetfile "c64psu.kicad_sch")
 		(attr smd)
 		(fp_line
-			(start -0.261253 -0.735)
-			(end 0.261253 -0.735)
+			(start -0.711252 1.36)
+			(end 0.711252 1.36)
 			(stroke
 				(width 0.12)
 				(type solid)
 			)
 			(layer "F.SilkS")
-			(uuid "8d72a2dd-5bf7-42e0-80eb-6695635de658")
+			(uuid "56989541-e76b-4958-85d3-5c63379f287b")
 		)
 		(fp_line
-			(start -0.261253 0.735)
-			(end 0.261253 0.735)
+			(start -0.711252 -1.36)
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 			(stroke
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 			(layer "F.SilkS")
-			(uuid "fa0c4ec7-43f2-42fa-b39f-d925d74ed0dd")
+			(uuid "5657889f-fd18-4338-b6c5-947aac8f3214")
 		)
 		(fp_line
-			(start 1.7 -0.98)
-			(end 1.7 0.98)
+			(start -2.3 1.6)
+			(end -2.3 -1.6)
 			(stroke
 				(width 0.05)
 				(type solid)
 			)
 			(layer "F.CrtYd")
-			(uuid "c0de2a41-2aa6-4bee-9afb-2ef2df9666d4")
+			(uuid "5bc748b4-2b47-46d1-9853-2696623acaa3")
 		)
 		(fp_line
-			(start -1.7 -0.98)
-			(end 1.7 -0.98)
+			(start 2.3 1.6)
+			(end -2.3 1.6)
 			(stroke
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 			)
 			(layer "F.CrtYd")
-			(uuid "85fb3e76-5934-4d46-9e3a-517f3d569b8c")
+			(uuid "a8d2577a-0c99-4633-8f3d-4aafc1816c86")
 		)
 		(fp_line
-			(start 1.7 0.98)
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+			(start -2.3 -1.6)
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 			(layer "F.CrtYd")
-			(uuid "7fdfd3ca-0b6e-4daa-b5e8-212f9fc82ef8")
+			(uuid "33a3dc8e-3578-4a49-97d2-241c4e785da0")
 		)
 		(fp_line
-			(start -1.7 0.98)
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+			(start 2.3 -1.6)
+			(end 2.3 1.6)
 			(stroke
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 				(type solid)
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 			(layer "F.CrtYd")
-			(uuid "8bc797bb-a31c-45a2-9690-badf46100b97")
+			(uuid "e71350aa-ae67-45b3-91dc-faa15bde0b3e")
 		)
 		(fp_line
-			(start 1 -0.625)
-			(end 1 0.625)
+			(start -1.6 1.25)
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 			(stroke
 				(width 0.1)
 				(type solid)
 			)
 			(layer "F.Fab")
-			(uuid "7dfeb04f-0a74-49ad-a47b-d8f2d9de1545")
+			(uuid "49683a33-901f-49dd-b539-a8d2f342c846")
 		)
 		(fp_line
-			(start -1 -0.625)
-			(end 1 -0.625)
+			(start 1.6 1.25)
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 			(stroke
 				(width 0.1)
 				(type solid)
 			)
 			(layer "F.Fab")
-			(uuid "0b3630e1-9cf4-44e0-9025-ad5d8674b726")
+			(uuid "b89a8734-d679-4f08-945a-a05675711d14")
 		)
 		(fp_line
-			(start 1 0.625)
-			(end -1 0.625)
+			(start -1.6 -1.25)
+			(end 1.6 -1.25)
 			(stroke
 				(width 0.1)
 				(type solid)
 			)
 			(layer "F.Fab")
-			(uuid "aac96951-1371-4573-b080-2a29e14fdfb6")
+			(uuid "2dc72aad-8458-45f8-afa2-e996d4fa518c")
 		)
 		(fp_line
-			(start -1 0.625)
-			(end -1 -0.625)
+			(start 1.6 -1.25)
+			(end 1.6 1.25)
 			(stroke
 				(width 0.1)
 				(type solid)
 			)
 			(layer "F.Fab")
-			(uuid "7e907e48-098c-4b5c-9bde-8a5003be7ceb")
+			(uuid "045a1ce8-cbe9-4f11-95fe-bd8f153ff2f8")
 		)
 		(fp_text user "${REFERENCE}"
 			(at 0 0 90)
 			(layer "F.Fab")
-			(uuid "a298ae5e-208d-48d7-a1df-8ada0cdaf200")
+			(uuid "45f08f5c-d9a2-4b08-b918-1b822a9a01fd")
 			(effects
 				(font
-					(size 0.5 0.5)
-					(thickness 0.08)
+					(size 0.8 0.8)
+					(thickness 0.12)
 				)
 			)
 		)
 		(pad "1" smd roundrect
-			(at -0.949999 0 90)
-			(size 1 1.45)
+			(at -1.475001 0 270)
+			(size 1.15 2.7)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 4 "5V")
-			(pintype "passive")
-			(uuid "758178a0-1c36-4938-b738-744f151c2f0f")
-		)
-		(pad "2" smd roundrect
-			(at 0.949999 0 90)
-			(size 1 1.45)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
+			(roundrect_rratio 0.217391)
 			(net 1 "GND")
 			(pintype "passive")
-			(uuid "04a11db0-a475-4e64-8c42-e32820b62896")
+			(uuid "47257b6d-913a-4615-a99f-af183c1cd352")
+		)
+		(pad "2" smd roundrect
+			(at 1.475001 0 270)
+			(size 1.15 2.7)
+			(layers "F.Cu" "F.Mask" "F.Paste")
+			(roundrect_rratio 0.217391)
+			(net 3 "15V")
+			(pintype "passive")
+			(uuid "a6906862-8eee-41cf-8c1e-b6cf7bee067e")
 		)
 		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0805_2012Metric.step"
+		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_1210_3225Metric.step"
 			(offset
 				(xyz 0 0 0)
 			)
@@ -17544,11 +14591,11 @@
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "F.Cu")
 		(uuid "ad981a70-3a56-4b96-af60-86cc9d37a4c7")
-		(at 132.8928 81.9404 90)
+		(at 151.6838 87.2574 90)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C60"
-			(at 0 -1.16 90)
+			(at 0.107836 1.1162 90)
 			(layer "F.SilkS")
 			(uuid "1a819a5e-fc3f-46d5-9eb5-529131c6c406")
 			(effects
@@ -17792,7 +14839,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pintype "passive")
 			(uuid "8e08722c-c70f-4919-b8ef-1b609b00bdf0")
 		)
@@ -17821,13 +14868,13 @@
 	(footprint "Resistor_SMD:R_0402_1005Metric"
 		(layer "F.Cu")
 		(uuid "b2299b88-bea9-4bf2-9103-10966baaeb4c")
-		(at 132.230401 45.6184)
+		(at 152.050301 56.26355)
 		(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "resistor")
 		(property "Reference" "R37"
-			(at 0 -1.17 0)
+			(at -2.525301 0.16145 0)
 			(layer "F.SilkS")
-			(uuid "5b66a4ff-32ec-4e90-9b0c-2005f05873b3")
+			(uuid "683102ab-0774-479f-a63c-a1541198308a")
 			(effects
 				(font
 					(size 1 1)
@@ -17838,7 +14885,7 @@
 		(property "Value" "10k"
 			(at 0 1.17 0)
 			(layer "F.Fab")
-			(uuid "7035ed89-66d9-417e-8db4-69502c500b57")
+			(uuid "536e75ee-7f14-46c8-91f9-af0d5b2c011a")
 			(effects
 				(font
 					(size 1 1)
@@ -17850,7 +14897,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "1bfdb8f3-9cf4-4608-b805-b8dbb073a1f4")
+			(uuid "f5bdcdca-7bf1-490a-a6b2-7063fd65fc01")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -17862,7 +14909,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "9fa63853-67e3-4523-a08e-6d24ef67edcb")
+			(uuid "31c7ab81-e6ce-4b4d-afbf-dbe5bff25870")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -18030,7 +15077,7 @@
 			(size 0.54 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 47 "Net-(Q1-Pad4)")
+			(net 36 "Net-(Q1-Pad4)")
 			(pintype "passive")
 			(uuid "b3898ff3-01d4-4b4f-9022-e4add62d3b07")
 		)
@@ -18039,7 +15086,7 @@
 			(size 0.54 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 48 "Net-(Q1-Pad5_8)")
+			(net 37 "Net-(Q1-Pad5_8)")
 			(pintype "passive")
 			(uuid "3d24f6a6-ad9a-44ea-bc8f-a94224a03922")
 		)
@@ -18056,16 +15103,270 @@
 			)
 		)
 	)
+	(footprint "TestPoint:TestPoint_2Pads_Pitch2.54mm_Drill0.8mm"
+		(layer "F.Cu")
+		(uuid "b9d3bee8-5c98-4f75-aa7e-4781d08da46f")
+		(at 174.1703 56.36515)
+		(descr "Test point with 2 pins, pitch 2.54mm, drill diameter 0.8mm")
+		(tags "CONN DEV")
+		(property "Reference" "TP7"
+			(at 1.27 1.95985 0)
+			(layer "F.SilkS")
+			(uuid "eced6573-c63f-4a2c-bd32-67e58cbc4a55")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Value" "TestPoint_2Pole"
+			(at 1.27 2 0)
+			(layer "F.Fab")
+			(uuid "705c3908-4a16-41f5-b798-8931ec407823")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Datasheet" "~"
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "820867b2-34d3-483b-a9ee-579e3c33c6e8")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property "Description" "2-polar test point"
+			(at 0 0 0)
+			(unlocked yes)
+			(layer "F.Fab")
+			(hide yes)
+			(uuid "fe8b3758-0626-463a-a276-650417191cfa")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
+				)
+			)
+		)
+		(property ki_fp_filters "Pin* Test*")
+		(path "/385b0f4f-257a-4a21-8636-fa7e8256f99c")
+		(sheetname "/")
+		(sheetfile "c64psu.kicad_sch")
+		(attr exclude_from_pos_files exclude_from_bom dnp)
+		(fp_line
+			(start -1.03 -0.4)
+			(end -0.53 -0.9)
+			(stroke
+				(width 0.15)
+				(type solid)
+			)
+			(layer "F.SilkS")
+			(uuid "0aec9fb0-77af-4ecd-8909-9f06baee2460")
+		)
+		(fp_line
+			(start -1.03 0.4)
+			(end -1.03 -0.4)
+			(stroke
+				(width 0.15)
+				(type solid)
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+			(layer "F.SilkS")
+			(uuid "0448e548-316c-4d99-8124-456759b721d6")
+		)
+		(fp_line
+			(start -0.53 -0.9)
+			(end 3.07 -0.9)
+			(stroke
+				(width 0.15)
+				(type solid)
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+			(layer "F.SilkS")
+			(uuid "6738d485-71ab-4639-988e-1ccd728a417b")
+		)
+		(fp_line
+			(start -0.53 0.9)
+			(end -1.03 0.4)
+			(stroke
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+			(layer "F.SilkS")
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+			(net 4 "5V")
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 		(layer "F.Cu")
 		(uuid "ba3b0d91-4356-444f-8a6d-e8019c91af99")
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 		(tags "resistor")
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-			(net 30 "Net-(IC1-LED)")
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-			(net 24 "Net-(D1-A)")
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-		(at 128.3436 91.7448 180)
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-			(net 17 "V_REF = 2.048 | 2.5 | 2.9")
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+		(uuid "bdc8bf32-7273-4885-8448-4e44b881f4c2")
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 			(remove_unused_layers no)
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+			(net 9 "9VAC_OUT1")
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-		(model "${KICAD9_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0603_1608Metric.step"
+		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0402_1005Metric.step"
 			(offset
 				(xyz 0 0 0)
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@@ -21205,13 +17166,13 @@
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 		(layer "F.Cu")
 		(uuid "d55dcea3-7bf1-4626-99ab-8b9ca346b527")
-		(at 137.1092 46.8376 180)
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 		(descr "Capacitor SMD 1210 (3225 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C3"
-			(at 0 -2.300001 0)
+			(at 3.00185 0.0697 180)
 			(layer "F.SilkS")
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+			(uuid "ab9c5234-67fa-4683-8c41-4d96e688eedf")
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 		(property "Description" "Unpolarized capacitor"
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 		(property "MPN" "UMK325BJ106KM-P"
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@@ -21292,26 +17253,6 @@
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 			(layer "F.CrtYd")
 			(uuid "0047d975-593b-4690-b864-391d9b44ef66")
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 		(fp_text user "${REFERENCE}"
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+			(at -1.475001 0 270)
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 			(layers "F.Cu" "F.Mask" "F.Paste")
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@@ -21393,7 +17354,7 @@
 			(uuid "270ed01f-a297-4cb1-990c-6f11ac49f086")
 		)
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 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.217391)
@@ -21417,7 +17378,7 @@
 	(footprint "Diode_SMD:D_SOD-323"
 		(layer "F.Cu")
 		(uuid "d7f01e67-97ad-44c0-90ae-1ef2397dd1e6")
-		(at 129.9972 95.1484 180)
+		(at 148.7882 100.4654 180)
 		(descr "SOD-323")
 		(tags "SOD-323")
 		(property "Reference" "D27"
@@ -21737,7 +17698,7 @@
 			(size 0.6 0.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pinfunction "K")
 			(pintype "passive")
 			(uuid "144501be-d5db-4005-92b4-9e34f7875de3")
@@ -21747,7 +17708,7 @@
 			(size 0.6 0.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 17 "V_REF = 2.048 | 2.5 | 2.9")
+			(net 7 "V_REF = 2.048 | 2.5 | 2.9")
 			(pinfunction "A")
 			(pintype "passive")
 			(uuid "c2213357-b09e-4098-b583-d8cb71858211")
@@ -21765,464 +17726,14 @@
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-	(footprint "Capacitor_SMD:C_0402_1005Metric"
-		(layer "F.Cu")
-		(uuid "d84cb35f-65d9-43ab-85eb-95f45f462ed6")
-		(at 179.2504 31.0388)
-		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "capacitor")
-		(property "Reference" "C18"
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 		(fp_line
 			(start 3.8 0.5)
 			(end 3.8 -0.5)
@@ -22434,8 +17915,38 @@
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+			(uuid "6e1f2664-36ba-473c-9894-a81a555d352a")
+		)
 		(fp_text user "${REFERENCE}"
-			(at 1.3 -2 0)
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 			(layer "F.Fab")
 			(uuid "db4311e5-6964-4212-8f15-b4eea7b534e1")
 			(effects
@@ -22446,18 +17957,18 @@
 			)
 		)
 		(pad "1" thru_hole circle
-			(at 0 0)
+			(at 0 0 90)
 			(size 1.4 1.4)
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 63 "PWM_G1")
+			(net 46 "PWM_G1")
 			(pinfunction "1")
 			(pintype "passive")
 			(uuid "1ae7bfd6-b640-4f0d-8ee4-434c7f4be6ac")
 		)
 		(pad "2" thru_hole circle
-			(at 2.54 0)
+			(at 2.54 0 90)
 			(size 1.4 1.4)
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
@@ -22469,482 +17980,6 @@
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 		(embedded_fonts no)
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-		(layer "F.Cu")
-		(uuid "df9ff22f-bd09-44c6-8d5a-f4d046ce0db7")
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-		(tags "resistor")
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-		(property "Description" "Resistor"
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-		(pad "1" smd roundrect
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-			(size 0.54 0.64)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 9 "Net-(U1-FB)")
-			(pintype "passive")
-			(uuid "0ae05d26-fd1d-41ad-b733-90ec4759b2eb")
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-		(pad "2" smd roundrect
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-			(net 4 "5V")
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-			(uuid "40908145-12a4-4780-8191-e9cf0ffacc8a")
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-		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.step"
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-		(layer "F.Cu")
-		(uuid "e04ebfe1-fc6f-4bb1-b171-659c91dc031d")
-		(at 167.5104 19.2088)
-		(descr "Resistor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "resistor")
-		(property "Reference" "R17"
-			(at 0 -1.17 0)
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-			(size 0.54 0.64)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 10 "Net-(C15-Pad2)")
-			(pintype "passive")
-			(uuid "bc43e393-2092-4eb8-97e0-2d9ae3f76375")
-		)
-		(pad "2" smd roundrect
-			(at 0.51 0)
-			(size 0.54 0.64)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 4 "5V")
-			(pintype "passive")
-			(uuid "fe488dcc-5d8b-47b6-b424-cd575745a37d")
-		)
-		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Resistor_SMD.3dshapes/R_0402_1005Metric.step"
-			(offset
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-			(scale
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-			)
-			(rotate
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-			)
-		)
-	)
 	(footprint "TestPoint:TestPoint_2Pads_Pitch2.54mm_Drill0.8mm"
 		(layer "F.Cu")
 		(uuid "e20c6d70-ca25-4b4b-b942-da573dc77771")
@@ -22952,7 +17987,7 @@
 		(descr "Test point with 2 pins, pitch 2.54mm, drill diameter 0.8mm")
 		(tags "CONN DEV")
 		(property "Reference" "TP6"
-			(at 1.2412 -0.7764 90)
+			(at 1.27 -2.1738 90)
 			(layer "F.SilkS")
 			(uuid "c07fdeda-98ae-4e92-a5e8-c16f9a9fac44")
 			(effects
@@ -23181,7 +18216,7 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 18 "9VAC_OUT2")
+			(net 8 "9VAC_OUT2")
 			(pinfunction "1")
 			(pintype "passive")
 			(uuid "f4776e0e-c04d-4721-b62e-85eee8514480")
@@ -23192,23 +18227,23 @@
 			(drill 0.8)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 19 "9VAC_OUT1")
+			(net 9 "9VAC_OUT1")
 			(pinfunction "2")
 			(pintype "passive")
 			(uuid "361ecc1b-b5db-4a60-b7ef-c857350b423e")
 		)
 		(embedded_fonts no)
 	)
-	(footprint "Capacitor_SMD:C_0805_2012Metric"
+	(footprint "Resistor_SMD:R_0603_1608Metric"
 		(layer "F.Cu")
-		(uuid "ec89cb2d-2d07-4388-8921-a1ba2afb8c1c")
-		(at 163.8304 19.8188)
-		(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
-		(tags "capacitor")
-		(property "Reference" "C16"
-			(at 0 -1.68 0)
+		(uuid "e39b71e2-39c6-45e2-8741-323e0f71a4e1")
+		(at 150.925 64.25 180)
+		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+		(tags "resistor")
+		(property "Reference" "R7"
+			(at 0 -1.43 0)
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+		(tags "capacitor")
+		(property "Reference" "C38"
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+		(property "MPN" "GRM21BR61C106KE15K"
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 			(layer "F.Fab")
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 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 12 "Net-(U1-COMP)")
+			(net 4 "5V")
 			(pintype "passive")
-			(uuid "5578a91d-606a-4bbc-8ee4-d07c33f8cadd")
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 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 11 "Net-(C16-Pad2)")
+			(net 1 "GND")
 			(pintype "passive")
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-	(footprint "Capacitor_SMD:C_0402_1005Metric"
+	(footprint "MountingHole:MountingHole_3.2mm_M3_DIN965_Pad_TopBottom"
 		(layer "F.Cu")
-		(uuid "ece0c51a-5610-49a6-ad54-66b49a8da697")
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-		(tags "capacitor")
-		(property "Reference" "C13"
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+		(uuid "f1926ad4-7fd5-42de-85bc-6017e2938872")
+		(at 140 42)
+		(descr "Mounting Hole 3.2mm, M3, generated by kicad-footprint-generator mountinghole.py")
+		(tags "mountinghole M3 DIN965")
+		(property "Reference" "H2"
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 			(layer "F.SilkS")
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+		(property "Value" "MountingHole_Pad"
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+		(pad "1" thru_hole circle
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+			(size 3.6 3.6)
+			(drill 3.2)
+			(layers "*.Cu" "*.Mask")
+			(remove_unused_layers no)
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-			(pintype "passive")
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+			(pintype "input")
+			(zone_connect 2)
+			(uuid "7592f726-26a4-482b-8c61-b729cb80f44f")
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+			(layers "B.Cu" "B.Mask")
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+			(uuid "dd7b0473-b150-4d40-ab7b-884c5a77adf8")
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-		(tags "capacitor")
-		(property "Reference" "C34"
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+		(uuid "f1dd4fa7-a455-47c6-94dc-d5ebd4f8cc02")
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+		(property ki_fp_filters "R_*")
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 			(net 3 "15V")
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-			(roundrect_rratio 0.217391)
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+			(roundrect_rratio 0.25)
+			(net 84 "Net-(IC2-EN)")
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+			(uuid "ddc43098-0172-4d70-89a8-552b76c2004f")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -24837,7 +19328,7 @@
 			(at 0 0 0)
 			(layer "F.Fab")
 			(hide yes)
-			(uuid "fdfd58a5-9b8f-47ee-be29-07f445d3af4a")
+			(uuid "2bfbc7cf-f34f-4c48-a4fe-889a1c315733")
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -25079,7 +19570,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 23 "Net-(IC1-V5V)")
+			(net 12 "Net-(IC1-V5V)")
 			(pintype "passive")
 			(uuid "6ae803d7-6e32-43d4-8b4f-59234b136d03")
 		)
@@ -25099,11 +19590,11 @@
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "F.Cu")
 		(uuid "fbe54208-ccb5-4f4e-86e0-1a91426d15cd")
-		(at 121.1072 88.0872 45)
+		(at 139.8982 93.4042 45)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C94"
-			(at 0 -1.16 45)
+			(at -2.576697 0.17508 45)
 			(layer "F.SilkS")
 			(uuid "e9a9e55b-9739-4e6a-a13d-aba99ffb0484")
 			(effects
@@ -25356,7 +19847,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 62 "OSC_OUT")
+			(net 45 "OSC_OUT")
 			(pintype "passive")
 			(uuid "a674556e-60ee-4104-8d6a-cadbd070e756")
 		)
@@ -25376,11 +19867,11 @@
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "F.Cu")
 		(uuid "fd069f6c-1f85-4727-87cf-a95939fe84e4")
-		(at 130.2512 91.7448 180)
+		(at 149.0422 97.0618 180)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C49"
-			(at 0 -1.16 0)
+			(at -2.8578 0.0118 0)
 			(layer "F.SilkS")
 			(uuid "ae3484f3-add3-44de-8a17-526f595e2f7e")
 			(effects
@@ -25633,7 +20124,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 21 "VDDA")
+			(net 11 "VDDA")
 			(pintype "passive")
 			(uuid "a9629e81-5b10-4815-abb4-db24e1ec1183")
 		)
@@ -25650,264 +20141,10 @@
 			)
 		)
 	)
-	(footprint "Inductor_SMD:L_Changjiang_FXL1040"
-		(layer "F.Cu")
-		(uuid "fe196612-287b-4e45-ac21-3a149b0ae018")
-		(at 170.64 69.09)
-		(descr "Inductor, Changjiang, FXL1040, 10.95x10.0x3.8mm, (https://www.lcsc.com/datasheet/lcsc_datasheet_2404260921_cjiang--Changjiang-Microelectronics-Tech-FXL0420-2R2-M_C167206.pdf), generated with kicad-footprint-generator gen_inductor.py")
-		(tags "Inductor power shielded cjiang fxl")
-		(property "Reference" "L2"
-			(at 0 -6 0)
-			(layer "F.SilkS")
-			(uuid "72b783be-5794-438c-9917-dc51076689d9")
-			(effects
-				(font
-					(size 1 1)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property "Value" "47uH"
-			(at 0 6 0)
-			(layer "F.Fab")
-			(uuid "091839f2-e545-4ba0-962f-4362da164826")
-			(effects
-				(font
-					(size 1 1)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property "Datasheet" "~"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "74074933-9300-482f-8ce8-502c78685123")
-			(effects
-				(font
-					(size 1.27 1.27)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property "Description" "Inductor"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "928cb4c4-2783-47d6-9e6e-ee170a549116")
-			(effects
-				(font
-					(size 1.27 1.27)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property "MPN" "TMPC 1004H-470MG-D"
-			(at 0 0 0)
-			(unlocked yes)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "e7d5d344-9019-4103-ae67-ee37fc816fa3")
-			(effects
-				(font
-					(size 1 1)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property ki_fp_filters "Choke_* *Coil* Inductor_* L_*")
-		(path "/39d55365-97c5-4bda-b5df-7d42c7bccdf4")
-		(sheetname "/")
-		(sheetfile "c64psu.kicad_sch")
-		(attr smd)
-		(fp_line
-			(start -5.735 -5.26)
-			(end -5.735 -2.31)
-			(stroke
-				(width 0.12)
-				(type solid)
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-			(layer "F.SilkS")
-			(uuid "4b3031f2-cc04-449e-ba8d-5567266652e4")
-		)
-		(fp_line
-			(start -5.735 -5.26)
-			(end 5.735 -5.26)
-			(stroke
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-				(type solid)
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-			(layer "F.SilkS")
-			(uuid "c149c6df-fb2e-4dc1-a34c-ab01c9e5956d")
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-		(fp_line
-			(start -5.735 5.26)
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-			(stroke
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-			(uuid "17b9b6bf-3017-42e6-b5ec-ea6def645f96")
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-		(fp_line
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-			(stroke
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-			(layer "F.SilkS")
-			(uuid "b3e41507-2010-463d-a356-7e797dd2ff17")
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-		(fp_line
-			(start 5.735 -5.26)
-			(end 5.735 -2.31)
-			(stroke
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-				(type solid)
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-			(layer "F.SilkS")
-			(uuid "7ccf72bb-89eb-4304-9010-dbc362f2392a")
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-		(fp_line
-			(start 5.735 5.26)
-			(end 5.735 2.31)
-			(stroke
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-				(type solid)
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-			(layer "F.SilkS")
-			(uuid "5f5676db-a0c9-4ef6-95c3-d14565dd7ca8")
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-		(fp_line
-			(start -7.05 -5.25)
-			(end -7.05 5.25)
-			(stroke
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-				(type solid)
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-			(layer "F.CrtYd")
-			(uuid "2ce0c0cb-a9f8-46fd-9427-5bb8ae4849bd")
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-		(fp_line
-			(start -7.05 5.25)
-			(end 7.05 5.25)
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-			(layer "F.CrtYd")
-			(uuid "47710aa9-0eff-4ad7-86b7-75509e79eb61")
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-		(fp_line
-			(start 7.05 -5.25)
-			(end -7.05 -5.25)
-			(stroke
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-			(layer "F.CrtYd")
-			(uuid "a96d0805-1d94-47f6-863f-c74fdfc44481")
-		)
-		(fp_line
-			(start 7.05 5.25)
-			(end 7.05 -5.25)
-			(stroke
-				(width 0.05)
-				(type solid)
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-			(layer "F.CrtYd")
-			(uuid "3d87b502-682d-4801-86f3-6932c5da950c")
-		)
-		(fp_line
-			(start -5.475 -5)
-			(end -5.475 5)
-			(stroke
-				(width 0.1)
-				(type solid)
-			)
-			(layer "F.Fab")
-			(uuid "bacadc4e-db4c-4683-a9f5-eba04ab7b4f1")
-		)
-		(fp_line
-			(start -5.475 5)
-			(end 5.475 5)
-			(stroke
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-				(type solid)
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-			(layer "F.Fab")
-			(uuid "bb4bddac-409c-44b0-af55-6ceedae2e65e")
-		)
-		(fp_line
-			(start 5.475 -5)
-			(end -5.475 -5)
-			(stroke
-				(width 0.1)
-				(type solid)
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-			(layer "F.Fab")
-			(uuid "80951df7-5c6b-4156-9309-3c9250b352a4")
-		)
-		(fp_line
-			(start 5.475 5)
-			(end 5.475 -5)
-			(stroke
-				(width 0.1)
-				(type solid)
-			)
-			(layer "F.Fab")
-			(uuid "8199288a-c8b4-4fc3-935d-d3e84aaa2efc")
-		)
-		(fp_text user "${REFERENCE}"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(uuid "56a2a12f-8bd5-4d5d-b861-73f02aab057d")
-			(effects
-				(font
-					(size 1 1)
-					(thickness 0.15)
-				)
-			)
-		)
-		(pad "1" smd roundrect
-			(at -4.75 0)
-			(size 4.1 4.1)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.060976)
-			(net 101 "Net-(L2-Pad1)")
-			(pinfunction "1")
-			(pintype "passive")
-			(uuid "96e0b52d-f73e-4b47-9e09-5b588c265720")
-		)
-		(pad "2" smd roundrect
-			(at 4.75 0)
-			(size 4.1 4.1)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.060976)
-			(net 16 "9VAC1")
-			(pinfunction "2")
-			(pintype "passive")
-			(uuid "72fc9e44-09fa-49c0-bec1-be48c3aa8093")
-		)
-		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Inductor_SMD.3dshapes/L_Changjiang_FXL1040.step"
-			(offset
-				(xyz 0 0 0)
-			)
-			(scale
-				(xyz 1 1 1)
-			)
-			(rotate
-				(xyz 0 0 0)
-			)
-		)
-	)
 	(footprint "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"
 		(layer "F.Cu")
 		(uuid "ffaaa5ce-33e3-4c61-857e-0019cf77aee1")
-		(at 158.0896 75.7428 -90)
+		(at 164.9984 77.6224 -90)
 		(descr "SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
 		(tags "SOIC SO")
 		(property "Reference" "U4"
@@ -26212,7 +20449,7 @@
 			(size 1.95 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 95 "ENABLE_DRVA")
+			(net 75 "ENABLE_DRVA")
 			(pinfunction "ENA")
 			(pintype "input")
 			(uuid "687762fb-8265-4a16-896c-eea432dd628d")
@@ -26222,7 +20459,7 @@
 			(size 1.95 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 64 "PWM_G2")
+			(net 47 "PWM_G2")
 			(pinfunction "INA")
 			(pintype "input")
 			(uuid "619f062d-a9a5-4eef-bed0-9472daa71434")
@@ -26242,7 +20479,7 @@
 			(size 1.95 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 63 "PWM_G1")
+			(net 46 "PWM_G1")
 			(pinfunction "INB")
 			(pintype "input")
 			(uuid "8c5a24bd-732d-4d35-8807-a6581ebce28e")
@@ -26252,7 +20489,7 @@
 			(size 1.95 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 53 "G1")
+			(net 40 "G1")
 			(pinfunction "~{OUTB}")
 			(pintype "output")
 			(uuid "f5642e03-d161-4e14-bd01-76a23dce8a94")
@@ -26272,7 +20509,7 @@
 			(size 1.95 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 54 "G2")
+			(net 41 "G2")
 			(pinfunction "OUTA")
 			(pintype "output")
 			(uuid "8f725c18-6b8c-41ca-aa8b-085202f14805")
@@ -26282,7 +20519,7 @@
 			(size 1.95 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 96 "ENABLE_DRVB")
+			(net 76 "ENABLE_DRVB")
 			(pinfunction "ENB")
 			(pintype "input")
 			(uuid "9c46872c-7e46-4cca-842e-7ca1eb65319c")
@@ -26307,7 +20544,7 @@
 		(descr "Diode SMA (DO-214AC)")
 		(tags "Diode SMA (DO-214AC)")
 		(property "Reference" "D2"
-			(at 0 2.5 90)
+			(at 4.561801 -0.0968 90)
 			(layer "B.SilkS")
 			(uuid "7f75bed3-e5c4-4736-a167-2cdc055e7cda")
 			(effects
@@ -26550,7 +20787,7 @@
 			(size 2.5 1.8)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.1388888889)
-			(net 18 "9VAC_OUT2")
+			(net 8 "9VAC_OUT2")
 			(pinfunction "A1")
 			(pintype "passive")
 			(uuid "da816482-71d6-4a2b-a7a0-121631a153fd")
@@ -26560,7 +20797,7 @@
 			(size 2.5 1.8)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.1388888889)
-			(net 19 "9VAC_OUT1")
+			(net 9 "9VAC_OUT1")
 			(pinfunction "A2")
 			(pintype "passive")
 			(uuid "acc454bb-2325-4ff2-8951-7efab0d58fac")
@@ -26585,7 +20822,7 @@
 		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "resistor")
 		(property "Reference" "R24"
-			(at 0 1.43 90)
+			(at 3.0448 -0.1714 90)
 			(layer "B.SilkS")
 			(uuid "2b672fdc-7f20-4396-84c2-6f991a0dd343")
 			(effects
@@ -26770,7 +21007,7 @@
 			(size 0.8 0.95)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 60 "Net-(U3--)")
+			(net 43 "Net-(U3--)")
 			(pintype "passive")
 			(uuid "0455e07a-4fd0-45bb-a350-69b4d586b26f")
 		)
@@ -26779,7 +21016,7 @@
 			(size 0.8 0.95)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 15 "9VAC2")
+			(net 5 "9VAC2")
 			(pintype "passive")
 			(uuid "c3d4e5a7-cea9-4d02-a9e4-cc1cd8112546")
 		)
@@ -26803,7 +21040,7 @@
 		(descr "SOT, 5 Pin (JEDEC MO-178 Var AA https://www.jedec.org/document_search?search_api_views_fulltext=MO-178), generated with kicad-footprint-generator ipc_gullwing_generator.py")
 		(tags "SOT TO_SOT_SMD")
 		(property "Reference" "U3"
-			(at 0 2.4 0)
+			(at 3.0064 -0.0438 0)
 			(layer "B.SilkS")
 			(uuid "69f0bf77-0d28-41c1-908f-6c101f62700b")
 			(effects
@@ -27110,7 +21347,7 @@
 			(size 1.325 0.6)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 59 "Net-(U3-+)")
+			(net 42 "Net-(U3-+)")
 			(pinfunction "+")
 			(pintype "input")
 			(uuid "a97a1e1a-77dd-46a5-9844-3c424ba7235d")
@@ -27130,7 +21367,7 @@
 			(size 1.325 0.6)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 60 "Net-(U3--)")
+			(net 43 "Net-(U3--)")
 			(pinfunction "-")
 			(pintype "input")
 			(uuid "f01e6daf-96bb-4390-aefb-68f5b2c37745")
@@ -27140,7 +21377,7 @@
 			(size 1.325 0.6)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 80 "9VAC_COMP_ADC")
+			(net 60 "9VAC_COMP_ADC")
 			(pintype "output")
 			(uuid "c6a176da-377e-469a-af82-44f32acbc7b8")
 		)
@@ -27170,11 +21407,11 @@
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "B.Cu")
 		(uuid "25ca8da9-49de-4a3d-89f2-bb84af8a1676")
-		(at 160.6804 76.1888 90)
+		(at 161.7 77.45)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C2"
-			(at 0 1.16 90)
+			(at -2.22 0.16 0)
 			(layer "B.SilkS")
 			(uuid "dfe3e656-a60e-479e-9392-aaf1b3dc344b")
 			(effects
@@ -27186,7 +21423,7 @@
 			)
 		)
 		(property "Value" "10uF"
-			(at 0 -2.6332 90)
+			(at 0 -2.633201 0)
 			(layer "B.Fab")
 			(uuid "f4b73c8d-a581-463e-b0fc-828b5c1e7fc1")
 			(effects
@@ -27198,7 +21435,7 @@
 			)
 		)
 		(property "Datasheet" "~"
-			(at 0 0 90)
+			(at 0 0 0)
 			(layer "B.Fab")
 			(hide yes)
 			(uuid "b99b1875-95ef-44e6-ad6e-d9d688d0bbf1")
@@ -27211,7 +21448,7 @@
 			)
 		)
 		(property "Description" "Unpolarized capacitor"
-			(at 0 0 90)
+			(at 0 0 0)
 			(layer "B.Fab")
 			(hide yes)
 			(uuid "6641d181-7b14-4242-8827-2df50630bb26")
@@ -27224,7 +21461,7 @@
 			)
 		)
 		(property "MPN" "CC0402MPX5R5BB106"
-			(at 0 0 270)
+			(at 0 0 180)
 			(unlocked yes)
 			(layer "B.Fab")
 			(hide yes)
@@ -27262,16 +21499,6 @@
 			(layer "B.SilkS")
 			(uuid "f3d54ed3-2d58-47e9-977a-0f228385a175")
 		)
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-			(stroke
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-			(layer "B.CrtYd")
-			(uuid "8116e7a1-9ee1-4536-9889-50e48535dfbe")
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 		(fp_line
 			(start -0.91 -0.46)
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@@ -27282,16 +21509,6 @@
 			(layer "B.CrtYd")
 			(uuid "2518b333-eb3d-407d-81cc-be74acef36f1")
 		)
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-			(uuid "30c469fe-3524-40d9-b22f-73baaaa4b0f9")
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 		(fp_line
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@@ -27303,14 +21520,24 @@
 			(uuid "8c575289-af7b-4218-b5c3-7eaefce7bc87")
 		)
 		(fp_line
-			(start 0.5 -0.25)
-			(end -0.5 -0.25)
+			(start 0.91 -0.46)
+			(end -0.91 -0.46)
 			(stroke
-				(width 0.1)
+				(width 0.05)
 				(type solid)
 			)
-			(layer "B.Fab")
-			(uuid "dadc0dfb-5448-43ab-b218-0fcb77109aca")
+			(layer "B.CrtYd")
+			(uuid "8116e7a1-9ee1-4536-9889-50e48535dfbe")
+		)
+		(fp_line
+			(start 0.91 0.46)
+			(end 0.91 -0.46)
+			(stroke
+				(width 0.05)
+				(type solid)
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+			(layer "B.CrtYd")
+			(uuid "30c469fe-3524-40d9-b22f-73baaaa4b0f9")
 		)
 		(fp_line
 			(start -0.5 -0.25)
@@ -27322,16 +21549,6 @@
 			(layer "B.Fab")
 			(uuid "c80d853c-e269-4651-a481-f254ef682979")
 		)
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 		(fp_line
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@@ -27342,8 +21559,28 @@
 			(layer "B.Fab")
 			(uuid "ffe40356-043a-46ae-acdc-55cddca9b0ed")
 		)
+		(fp_line
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+			(stroke
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+				(type solid)
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+			(layer "B.Fab")
+			(uuid "dadc0dfb-5448-43ab-b218-0fcb77109aca")
+		)
+		(fp_line
+			(start 0.5 0.25)
+			(end 0.5 -0.25)
+			(stroke
+				(width 0.1)
+				(type solid)
+			)
+			(layer "B.Fab")
+			(uuid "f3e80ed3-4c16-40a1-a7d7-fd1b507b0ae6")
+		)
 		(fp_text user "${REFERENCE}"
-			(at 0 -1.4732 90)
+			(at 0 -1.4732 0)
 			(layer "B.Fab")
 			(uuid "f9d75309-b8fe-451f-be28-94e229033ded")
 			(effects
@@ -27355,7 +21592,7 @@
 			)
 		)
 		(pad "1" smd roundrect
-			(at -0.48 0 90)
+			(at -0.48 0)
 			(size 0.56 0.62)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
@@ -27364,11 +21601,11 @@
 			(uuid "94b55881-a757-4efb-a866-9a5bfc161362")
 		)
 		(pad "2" smd roundrect
-			(at 0.48 0 90)
+			(at 0.48 0)
 			(size 0.56 0.62)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pintype "passive")
 			(uuid "293cbc87-14c0-4217-ade6-a7c87b4249c3")
 		)
@@ -27385,6 +21622,224 @@
 			)
 		)
 	)
+	(footprint "Capacitor_SMD:C_1206_3216Metric"
+		(layer "B.Cu")
+		(uuid "2b45c6d0-8640-4f7f-8115-48a0c7771686")
+		(at 177.3936 84.4804 -90)
+		(descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+		(tags "capacitor")
+		(property "Reference" "C25"
+			(at -3.9852 -0.046 90)
+			(layer "B.SilkS")
+			(uuid "2fda5f05-f311-437c-ad04-3959428d42e1")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
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+				(justify mirror)
+			)
+		)
+		(property "Value" "10uF"
+			(at 0 -1.850001 90)
+			(layer "B.Fab")
+			(uuid "7b288585-653a-48a0-b0bf-f2a593301a69")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
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+				(justify mirror)
+			)
+		)
+		(property "Datasheet" "~"
+			(at 0 0 90)
+			(layer "B.Fab")
+			(hide yes)
+			(uuid "2d274075-d807-48f4-91c1-4d748a3445f0")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
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+				(justify mirror)
+			)
+		)
+		(property "Description" "Unpolarized capacitor"
+			(at 0 0 90)
+			(layer "B.Fab")
+			(hide yes)
+			(uuid "eba60058-9a30-45b3-99ff-6ceb42efcd41")
+			(effects
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+				(justify mirror)
+			)
+		)
+		(property "MPN" "CC1206KKX5R9BB106 "
+			(at 0 0 90)
+			(unlocked yes)
+			(layer "B.Fab")
+			(hide yes)
+			(uuid "4e2e6785-89c9-4782-8eea-29e71115760c")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
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+				(justify mirror)
+			)
+		)
+		(property ki_fp_filters "C_*")
+		(path "/d4839fd2-827a-489c-ac06-e357ed71f7ac")
+		(sheetname "/")
+		(sheetfile "c64psu.kicad_sch")
+		(attr smd dnp)
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+			(start -0.711252 0.91)
+			(end 0.711252 0.91)
+			(stroke
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+			(layer "B.SilkS")
+			(uuid "c1a0a0f2-9c6c-4a65-b721-bf7da1101f76")
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+			(uuid "3f9d8253-8734-4973-97b5-5cb75e98062c")
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+			(start -2.3 1.15)
+			(end 2.3 1.15)
+			(stroke
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+			(layer "B.CrtYd")
+			(uuid "b871052f-6ee0-4074-bdbe-05b76dc2b07d")
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+		(fp_line
+			(start 2.3 1.15)
+			(end 2.3 -1.15)
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+			(layer "B.CrtYd")
+			(uuid "6b80daca-95ef-4af5-bbf5-23ab7ec310f1")
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+			(uuid "87c4b5c0-d833-4df9-8ae5-659b0716ddaa")
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+			(uuid "7705d40d-4e4c-4f3d-baf0-919c5b71cb3e")
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+			(uuid "fbc5a496-0d94-4464-98ce-5f682c5b4187")
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+			(end 1.6 -0.8)
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+			(uuid "fcd4f0f8-7eb5-4260-b0f3-c2947ecc9cc7")
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+			(end -1.6 0.8)
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+			(layer "B.Fab")
+			(uuid "99af9345-6f3c-47ca-aafb-d1c5d0b46172")
+		)
+		(fp_line
+			(start 1.6 -0.8)
+			(end -1.6 -0.8)
+			(stroke
+				(width 0.1)
+				(type solid)
+			)
+			(layer "B.Fab")
+			(uuid "270f441f-e7a1-4a85-ad22-f8fd68c2d8f8")
+		)
+		(fp_text user "${REFERENCE}"
+			(at 0 0 90)
+			(layer "B.Fab")
+			(uuid "4fff44d2-64be-4197-b431-fd691e9db1e7")
+			(effects
+				(font
+					(size 0.8 0.8)
+					(thickness 0.12)
+				)
+				(justify mirror)
+			)
+		)
+		(pad "1" smd roundrect
+			(at -1.475001 0 270)
+			(size 1.15 1.8)
+			(layers "B.Cu" "B.Mask" "B.Paste")
+			(roundrect_rratio 0.217391)
+			(net 6 "9VAC1")
+			(pintype "passive")
+			(uuid "df29526b-3aee-46c7-acca-aa9f465b9262")
+		)
+		(pad "2" smd roundrect
+			(at 1.475001 0 270)
+			(size 1.15 1.8)
+			(layers "B.Cu" "B.Mask" "B.Paste")
+			(roundrect_rratio 0.217391)
+			(net 5 "9VAC2")
+			(pintype "passive")
+			(uuid "940107c1-9b2f-4177-bcd1-6d329b3a2700")
+		)
+		(embedded_fonts no)
+		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_1206_3216Metric.step"
+			(offset
+				(xyz 0 0 0)
+			)
+			(scale
+				(xyz 1 1 1)
+			)
+			(rotate
+				(xyz 0 0 0)
+			)
+		)
+	)
 	(footprint "Resistor_SMD:R_0603_1608Metric"
 		(layer "B.Cu")
 		(uuid "3395c573-6c02-4cbe-b572-ae7079026224")
@@ -27392,7 +21847,7 @@
 		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "resistor")
 		(property "Reference" "R27"
-			(at 0 1.43 0)
+			(at 0.0588 -1.5796 0)
 			(layer "B.SilkS")
 			(uuid "1363a8ea-c826-4c32-ac1e-70958857189c")
 			(effects
@@ -27577,7 +22032,7 @@
 			(size 0.8 0.95)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 60 "Net-(U3--)")
+			(net 43 "Net-(U3--)")
 			(pintype "passive")
 			(uuid "efd4b4a7-7e4e-4c97-b21b-42fe9ac06876")
 		)
@@ -27586,7 +22041,7 @@
 			(size 0.8 0.95)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 80 "9VAC_COMP_ADC")
+			(net 60 "9VAC_COMP_ADC")
 			(pintype "passive")
 			(uuid "99641e67-8927-4cfd-a400-34c255083f0a")
 		)
@@ -27610,7 +22065,7 @@
 		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "resistor")
 		(property "Reference" "R26"
-			(at 0 1.43 90)
+			(at 3.096 -0.0016 90)
 			(layer "B.SilkS")
 			(uuid "79a20688-20f6-49cf-b9dc-a8874a0d03a8")
 			(effects
@@ -27795,7 +22250,7 @@
 			(size 0.8 0.95)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 61 "1.225V")
+			(net 44 "1.225V")
 			(pintype "passive")
 			(uuid "0b86d479-a92f-4ed6-bebf-1338fb44b428")
 		)
@@ -27804,7 +22259,7 @@
 			(size 0.8 0.95)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pintype "passive")
 			(uuid "9691092c-254c-4aa1-b72f-dd7e998dc1a2")
 		)
@@ -27824,7 +22279,7 @@
 	(footprint "Package_SO:SOIC-8_3.9x4.9mm_P1.27mm"
 		(layer "B.Cu")
 		(uuid "4cf42998-2ce7-4300-957c-40d807f36117")
-		(at 158.0388 90.1192 90)
+		(at 164.9476 91.9988 90)
 		(descr "SOIC, 8 Pin (JEDEC MS-012AA, https://www.analog.com/media/en/package-pcb-resources/package/pkg_pdf/soic_narrow-r/r_8.pdf), generated with kicad-footprint-generator ipc_gullwing_generator.py")
 		(tags "SOIC SO")
 		(property "Reference" "U5"
@@ -28135,7 +22590,7 @@
 			(size 1.95 0.6)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 95 "ENABLE_DRVA")
+			(net 75 "ENABLE_DRVA")
 			(pinfunction "ENA")
 			(pintype "input")
 			(uuid "e00dc386-d5db-4c6b-bdb5-3fff189d966d")
@@ -28145,7 +22600,7 @@
 			(size 1.95 0.6)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 65 "PWM_G4")
+			(net 48 "PWM_G4")
 			(pinfunction "INA")
 			(pintype "input")
 			(uuid "eb1adf75-3553-4aa3-977a-c5f94f38faee")
@@ -28165,7 +22620,7 @@
 			(size 1.95 0.6)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 66 "PWM_G3")
+			(net 49 "PWM_G3")
 			(pinfunction "INB")
 			(pintype "input")
 			(uuid "eb22d562-eb07-495d-a678-acbac722e0a8")
@@ -28175,7 +22630,7 @@
 			(size 1.95 0.6)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 51 "G3")
+			(net 38 "G3")
 			(pinfunction "~{OUTB}")
 			(pintype "output")
 			(uuid "ab20db6d-2b56-4166-8ab0-7dc6e694c959")
@@ -28195,7 +22650,7 @@
 			(size 1.95 0.6)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 52 "G4")
+			(net 39 "G4")
 			(pinfunction "OUTA")
 			(pintype "output")
 			(uuid "a0bde9bc-a71b-4a96-9b90-a2d6d8714b17")
@@ -28205,7 +22660,7 @@
 			(size 1.95 0.6)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 96 "ENABLE_DRVB")
+			(net 76 "ENABLE_DRVB")
 			(pinfunction "ENB")
 			(pintype "input")
 			(uuid "712db1e0-0a0c-4191-a13c-025d327266fa")
@@ -28223,6 +22678,224 @@
 			)
 		)
 	)
+	(footprint "Capacitor_SMD:C_0402_1005Metric"
+		(layer "B.Cu")
+		(uuid "5d31bc09-da41-4349-83ad-34e56513ed1a")
+		(at 161.675 91.92 90)
+		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+		(tags "capacitor")
+		(property "Reference" "C27"
+			(at 0.107836 -1.25 90)
+			(layer "B.SilkS")
+			(uuid "d1ff4c70-3fa0-413f-869f-85b855e7ed0d")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+				(justify mirror)
+			)
+		)
+		(property "Value" "1uF"
+			(at 0 -1.16 90)
+			(layer "B.Fab")
+			(uuid "2f0e1bdd-99e0-47c5-a9fd-bd0dbd2ec6c2")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+				(justify mirror)
+			)
+		)
+		(property "Datasheet" "~"
+			(at 0 0 90)
+			(layer "B.Fab")
+			(hide yes)
+			(uuid "aa309eb1-2ea0-4f44-bc01-134b431b9ff3")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
+				)
+				(justify mirror)
+			)
+		)
+		(property "Description" "Unpolarized capacitor"
+			(at 0 0 90)
+			(layer "B.Fab")
+			(hide yes)
+			(uuid "407dc619-5b67-4066-b0f7-155d35dcb962")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
+				)
+				(justify mirror)
+			)
+		)
+		(property "MPN" "CC0402KPX5R8BB105"
+			(at 0 0 270)
+			(unlocked yes)
+			(layer "B.Fab")
+			(hide yes)
+			(uuid "e260501b-c129-438b-bf6f-08247d76a39d")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+				(justify mirror)
+			)
+		)
+		(property ki_fp_filters "C_*")
+		(path "/1bbdeedc-df9f-4536-822e-32e2191fe233")
+		(sheetname "/")
+		(sheetfile "c64psu.kicad_sch")
+		(attr smd)
+		(fp_line
+			(start -0.107836 -0.36)
+			(end 0.107836 -0.36)
+			(stroke
+				(width 0.12)
+				(type solid)
+			)
+			(layer "B.SilkS")
+			(uuid "e5831f80-0de1-4134-80ed-2e9313928e6e")
+		)
+		(fp_line
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 		(layer "B.Cu")
 		(uuid "adc4077a-124d-4ea7-be22-c23dd66f1f5f")
-		(at 156.21 80.8228 180)
+		(at 165.21 82.86 180)
 		(descr "Resistor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "resistor")
 		(property "Reference" "R21"
-			(at 0 1.65 0)
+			(at -2.9312 -0.1476 0)
 			(layer "B.SilkS")
 			(uuid "d17a6c45-0dfc-4491-a72f-3cc7dc5f9941")
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@@ -29804,7 +23742,7 @@
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 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.243902)
-			(net 103 "Net-(U6-+IN)")
+			(net 86 "Net-(U1-+)")
 			(pintype "passive")
 			(uuid "f99bec4b-9adc-41b9-be32-af22616169bb")
 		)
@@ -29837,7 +23775,7 @@
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C21"
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 			(uuid "6d1f0cd0-0a3d-4cd1-b921-6742654152c4")
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@@ -30055,7 +23993,7 @@
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 		(tags "SOT TO_SOT_SMD")
 		(property "Reference" "U7"
-			(at 0 2.4 0)
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 			(uuid "53e095a3-3ff1-4b3d-883c-8ed00dba2afb")
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@@ -30362,7 +24300,7 @@
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 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 61 "1.225V")
+			(net 44 "1.225V")
 			(pinfunction "K")
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 			(uuid "5ed51892-1975-4cfd-ae9d-26bce9d68afe")
@@ -30382,7 +24320,7 @@
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 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 99 "unconnected-(U7-NC-Pad3)")
+			(net 78 "unconnected-(U7-NC-Pad3)")
 			(pinfunction "NC")
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 			(uuid "9803ae09-5c37-4732-be51-5646fd88bc14")
@@ -30400,6 +24338,1035 @@
 			)
 		)
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+		(layer "B.Cu")
+		(uuid "b6a5d7c3-440b-4628-a7bf-7265f691c709")
+		(at 164.68 78.42 180)
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+		(tags "SOT TO_SOT_SMD")
+		(property "Reference" "U1"
+			(at 0 2.4 0)
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+		(property "Datasheet" "http://www.ti.com/lit/ds/symlink/ina180.pdf"
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+		(property "Description" "Current Sense Amplifier, 1 Circuit, Rail-to-Rail, 26V, Gain 50 V/V, SOT-23-5"
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+		(property ki_fp_filters "SOT?23*")
+		(path "/6dc6d238-1cbf-46a0-97a0-db9b1bc57c2f")
+		(sheetname "/")
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+		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_1206_3216Metric.step"
+			(offset
+				(xyz 0 0 0)
+			)
+			(scale
+				(xyz 1 1 1)
+			)
+			(rotate
+				(xyz 0 0 0)
+			)
+		)
+	)
+	(footprint "Capacitor_SMD:C_1206_3216Metric"
+		(layer "B.Cu")
+		(uuid "c762acb6-ab60-4c45-8066-eb5cf5ba3d6f")
+		(at 174.9636 84.4704 -90)
+		(descr "Capacitor SMD 1206 (3216 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
+		(tags "capacitor")
+		(property "Reference" "C19"
+			(at -3.772 -0.0376 90)
+			(layer "B.SilkS")
+			(uuid "67dca98b-f00e-4b83-944c-3a1c424d8099")
+			(effects
+				(font
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+					(thickness 0.15)
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+				(justify mirror)
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+		)
+		(property "Value" "10uF"
+			(at 0 -1.850001 90)
+			(layer "B.Fab")
+			(uuid "e22e5619-6f4c-4147-b927-617849e6b70c")
+			(effects
+				(font
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+					(thickness 0.15)
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+				(justify mirror)
+			)
+		)
+		(property "Datasheet" "~"
+			(at 0 0 90)
+			(layer "B.Fab")
+			(hide yes)
+			(uuid "5a44b35f-f09e-49de-898a-e06bb14781db")
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+					(size 1.27 1.27)
+					(thickness 0.15)
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+				(justify mirror)
+			)
+		)
+		(property "Description" "Unpolarized capacitor"
+			(at 0 0 90)
+			(layer "B.Fab")
+			(hide yes)
+			(uuid "fa7c7bab-21e7-445e-8bb8-4ca55d050855")
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+				(justify mirror)
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+		)
+		(property "MPN" "CC1206KKX5R9BB106 "
+			(at 0 0 90)
+			(unlocked yes)
+			(layer "B.Fab")
+			(hide yes)
+			(uuid "b1838e8e-951e-4bba-8643-7b6356cf2bb9")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+				(justify mirror)
+			)
+		)
+		(property ki_fp_filters "C_*")
+		(path "/491dd2d9-9758-49e6-bf42-f2b1033479b8")
+		(sheetname "/")
+		(sheetfile "c64psu.kicad_sch")
+		(attr smd)
+		(fp_line
+			(start -0.711252 0.91)
+			(end 0.711252 0.91)
+			(stroke
+				(width 0.12)
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+			(layer "B.SilkS")
+			(uuid "ba956c9e-11a6-425c-acff-d82aa5c36166")
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+			(uuid "4162db85-30e9-4afa-9299-6246d0b1f71e")
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+		(fp_line
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+			(stroke
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+			(layer "B.CrtYd")
+			(uuid "070eec90-d97f-40a8-9283-f4f6901f81b4")
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+			(stroke
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+			(uuid "caff1b0c-7223-4149-9605-b4c1b3069533")
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+			(uuid "84abd33f-dba0-4bf1-82c6-d8526d36d2cd")
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+			(layer "B.Fab")
+			(uuid "25084c36-e581-48bc-8815-43c34e8f951a")
+		)
+		(fp_line
+			(start 1.6 -0.8)
+			(end -1.6 -0.8)
+			(stroke
+				(width 0.1)
+				(type solid)
+			)
+			(layer "B.Fab")
+			(uuid "3eec7264-ccf1-4953-9335-1bc29cd11a02")
+		)
+		(fp_text user "${REFERENCE}"
+			(at 0 0 90)
+			(layer "B.Fab")
+			(uuid "94d91640-33ba-4f74-8657-67b4e9fcfb8f")
+			(effects
+				(font
+					(size 0.8 0.8)
+					(thickness 0.12)
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+				(justify mirror)
+			)
+		)
+		(pad "1" smd roundrect
+			(at -1.475001 0 270)
+			(size 1.15 1.8)
+			(layers "B.Cu" "B.Mask" "B.Paste")
+			(roundrect_rratio 0.217391)
+			(net 6 "9VAC1")
+			(pintype "passive")
+			(uuid "9a8279e6-49bc-4f5a-9da1-373915866bf2")
+		)
+		(pad "2" smd roundrect
+			(at 1.475001 0 270)
+			(size 1.15 1.8)
+			(layers "B.Cu" "B.Mask" "B.Paste")
+			(roundrect_rratio 0.217391)
+			(net 5 "9VAC2")
+			(pintype "passive")
+			(uuid "29a8d733-4aa9-4d00-87a2-d0f34a01c00a")
+		)
+		(embedded_fonts no)
+		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_1206_3216Metric.step"
+			(offset
+				(xyz 0 0 0)
+			)
+			(scale
+				(xyz 1 1 1)
+			)
+			(rotate
+				(xyz 0 0 0)
+			)
+		)
+	)
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "B.Cu")
 		(uuid "cad19558-e675-4261-be5a-4c70a7830ec8")
@@ -30407,7 +25374,7 @@
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C22"
-			(at 0 1.16 90)
+			(at 2.538 0.3774 90)
 			(layer "B.SilkS")
 			(uuid "b41adbb7-8404-4b63-83c9-bfe2cd42f0b6")
 			(effects
@@ -30819,7 +25786,7 @@
 			(size 0.8 0.95)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 19 "9VAC_OUT1")
+			(net 9 "9VAC_OUT1")
 			(pintype "passive")
 			(uuid "1f0ccad0-2588-47a3-9e60-722f29abd0f8")
 		)
@@ -30839,11 +25806,11 @@
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "B.Cu")
 		(uuid "e0588254-780b-4e04-83e0-8573eb9a4cdf")
-		(at 157.988 85.9028)
+		(at 164.8968 87.7824)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C29"
-			(at 0 1.16 0)
+			(at 3.9782 0.6426 0)
 			(layer "B.SilkS")
 			(uuid "80271ec3-0bfc-4eb1-aa40-80cac40f8b23")
 			(effects
@@ -31057,11 +26024,11 @@
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "B.Cu")
 		(uuid "e5306bf2-56ad-4738-aa93-e954311ca332")
-		(at 160.6804 74.3204 90)
+		(at 161.67 76.47 180)
 		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C24"
-			(at 0 1.16 90)
+			(at 2.57 0.12 0)
 			(layer "B.SilkS")
 			(uuid "b9795b94-64fc-4573-abab-14a697a6394f")
 			(effects
@@ -31073,7 +26040,7 @@
 			)
 		)
 		(property "Value" "100nF"
-			(at 0 -1.16 90)
+			(at 0 -1.16 0)
 			(layer "B.Fab")
 			(uuid "e57761b9-bf4b-4436-a293-84db4506d43a")
 			(effects
@@ -31085,7 +26052,7 @@
 			)
 		)
 		(property "Datasheet" "~"
-			(at 0 0 90)
+			(at 0 0 0)
 			(layer "B.Fab")
 			(hide yes)
 			(uuid "4d7e2f4c-a75e-4c79-a8c3-b2c4edee9f61")
@@ -31098,7 +26065,7 @@
 			)
 		)
 		(property "Description" "Unpolarized capacitor"
-			(at 0 0 90)
+			(at 0 0 0)
 			(layer "B.Fab")
 			(hide yes)
 			(uuid "94de3933-31d7-4702-b063-9cad667ff63c")
@@ -31111,7 +26078,7 @@
 			)
 		)
 		(property "MPN" "CL05B104KO5NNNC"
-			(at 0 0 270)
+			(at 0 0 0)
 			(unlocked yes)
 			(layer "B.Fab")
 			(hide yes)
@@ -31129,16 +26096,6 @@
 		(sheetname "/")
 		(sheetfile "c64psu.kicad_sch")
 		(attr smd)
-		(fp_line
-			(start -0.107836 -0.36)
-			(end 0.107836 -0.36)
-			(stroke
-				(width 0.12)
-				(type solid)
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-			(layer "B.SilkS")
-			(uuid "80999e14-5e98-41b6-8e57-df3fdf0f22e9")
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 		(fp_line
 			(start -0.107836 0.36)
 			(end 0.107836 0.36)
@@ -31150,24 +26107,14 @@
 			(uuid "300c6476-8bc1-4c6b-83ec-85e87f253906")
 		)
 		(fp_line
-			(start 0.91 -0.46)
-			(end -0.91 -0.46)
+			(start -0.107836 -0.36)
+			(end 0.107836 -0.36)
 			(stroke
-				(width 0.05)
+				(width 0.12)
 				(type solid)
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-			(layer "B.CrtYd")
-			(uuid "9362af38-f528-4ee9-837a-742c185d777b")
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-			)
-			(layer "B.CrtYd")
-			(uuid "28d5df88-9b34-4faa-94a3-f26737bcfd9e")
+			(layer "B.SilkS")
+			(uuid "80999e14-5e98-41b6-8e57-df3fdf0f22e9")
 		)
 		(fp_line
 			(start 0.91 0.46)
@@ -31179,6 +26126,16 @@
 			(layer "B.CrtYd")
 			(uuid "d4111c5e-3aef-400b-946b-59aaf1f35886")
 		)
+		(fp_line
+			(start 0.91 -0.46)
+			(end -0.91 -0.46)
+			(stroke
+				(width 0.05)
+				(type solid)
+			)
+			(layer "B.CrtYd")
+			(uuid "9362af38-f528-4ee9-837a-742c185d777b")
+		)
 		(fp_line
 			(start -0.91 0.46)
 			(end 0.91 0.46)
@@ -31190,24 +26147,14 @@
 			(uuid "bb37f855-0bd2-4413-91b1-07cb70616ddc")
 		)
 		(fp_line
-			(start 0.5 -0.25)
-			(end -0.5 -0.25)
+			(start -0.91 -0.46)
+			(end -0.91 0.46)
 			(stroke
-				(width 0.1)
+				(width 0.05)
 				(type solid)
 			)
-			(layer "B.Fab")
-			(uuid "7a9550d4-74f7-4b0f-94a2-6145075e496a")
-		)
-		(fp_line
-			(start -0.5 -0.25)
-			(end -0.5 0.25)
-			(stroke
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-				(type solid)
-			)
-			(layer "B.Fab")
-			(uuid "5dedb194-f6a5-49ff-b078-378ac45a7605")
+			(layer "B.CrtYd")
+			(uuid "28d5df88-9b34-4faa-94a3-f26737bcfd9e")
 		)
 		(fp_line
 			(start 0.5 0.25)
@@ -31219,6 +26166,16 @@
 			(layer "B.Fab")
 			(uuid "7beb17a5-e7bb-4841-acc5-b60b4481a74d")
 		)
+		(fp_line
+			(start 0.5 -0.25)
+			(end -0.5 -0.25)
+			(stroke
+				(width 0.1)
+				(type solid)
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+			(layer "B.Fab")
+			(uuid "7a9550d4-74f7-4b0f-94a2-6145075e496a")
+		)
 		(fp_line
 			(start -0.5 0.25)
 			(end 0.5 0.25)
@@ -31229,8 +26186,18 @@
 			(layer "B.Fab")
 			(uuid "f8e0a94b-6d16-45c0-b21f-f57a0d8277bd")
 		)
+		(fp_line
+			(start -0.5 -0.25)
+			(end -0.5 0.25)
+			(stroke
+				(width 0.1)
+				(type solid)
+			)
+			(layer "B.Fab")
+			(uuid "5dedb194-f6a5-49ff-b078-378ac45a7605")
+		)
 		(fp_text user "${REFERENCE}"
-			(at 0 -1.4732 90)
+			(at 0 -1.4732 0)
 			(layer "B.Fab")
 			(uuid "62751c43-1173-47fc-a5e5-642a1859d7af")
 			(effects
@@ -31242,16 +26209,16 @@
 			)
 		)
 		(pad "1" smd roundrect
-			(at -0.48 0 90)
+			(at -0.48 0 180)
 			(size 0.56 0.62)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 20 "3.3V")
+			(net 10 "3.3V")
 			(pintype "passive")
 			(uuid "cf90a6d3-3af5-482d-881e-aa11d855e68f")
 		)
 		(pad "2" smd roundrect
-			(at 0.48 0 90)
+			(at 0.48 0 180)
 			(size 0.56 0.62)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
@@ -31279,7 +26246,7 @@
 		(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 72, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
 		(tags "resistor")
 		(property "Reference" "R22"
-			(at -0.6096 10.5618 90)
+			(at 3.1572 -0.0286 90)
 			(layer "B.SilkS")
 			(uuid "4b5ac968-14b4-48bf-93d6-d68dd195c220")
 			(effects
@@ -31464,7 +26431,7 @@
 			(size 0.8 0.95)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 59 "Net-(U3-+)")
+			(net 42 "Net-(U3-+)")
 			(pintype "passive")
 			(uuid "6a51c43d-67f7-4fc1-91f7-64940bb5c1c8")
 		)
@@ -31473,7 +26440,7 @@
 			(size 0.8 0.95)
 			(layers "B.Cu" "B.Mask" "B.Paste")
 			(roundrect_rratio 0.25)
-			(net 16 "9VAC1")
+			(net 6 "9VAC1")
 			(pintype "passive")
 			(uuid "c8a1d780-b7cb-492a-992a-134071b2b8ce")
 		)
@@ -31490,259 +26457,522 @@
 			)
 		)
 	)
-	(gr_rect
-		(start 111.8076 -9.618)
-		(end 219.54 108.9564)
+	(footprint "Inductor_SMD:L_Changjiang_FXL1040"
+		(layer "B.Cu")
+		(uuid "fe196612-287b-4e45-ac21-3a149b0ae018")
+		(at 175.1076 69.1388)
+		(descr "Inductor, Changjiang, FXL1040, 10.95x10.0x3.8mm, (https://www.lcsc.com/datasheet/lcsc_datasheet_2404260921_cjiang--Changjiang-Microelectronics-Tech-FXL0420-2R2-M_C167206.pdf), generated with kicad-footprint-generator gen_inductor.py")
+		(tags "Inductor power shielded cjiang fxl")
+		(property "Reference" "L2"
+			(at 0 6 0)
+			(layer "B.SilkS")
+			(uuid "bd7c43c1-a424-4a47-aa2e-75e44b14e3b0")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+				(justify mirror)
+			)
+		)
+		(property "Value" "47uH"
+			(at -12.592105 -4.39725 0)
+			(layer "B.Fab")
+			(uuid "2dce4f39-2c75-4f58-a858-f541f2456401")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+				(justify mirror)
+			)
+		)
+		(property "Datasheet" "~"
+			(at 0 0 0)
+			(layer "B.Fab")
+			(hide yes)
+			(uuid "e6f6575c-48d7-45bb-9053-91d81b86b217")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
+				)
+				(justify mirror)
+			)
+		)
+		(property "Description" "Inductor"
+			(at 0 0 0)
+			(layer "B.Fab")
+			(hide yes)
+			(uuid "c97b22ad-eb29-411c-8d9f-4ee1c1224f48")
+			(effects
+				(font
+					(size 1.27 1.27)
+					(thickness 0.15)
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+				(justify mirror)
+			)
+		)
+		(property "MPN" "TMPC 1004H-470MG-D"
+			(at 0 0 180)
+			(unlocked yes)
+			(layer "B.Fab")
+			(hide yes)
+			(uuid "e7d5d344-9019-4103-ae67-ee37fc816fa3")
+			(effects
+				(font
+					(size 1 1)
+					(thickness 0.15)
+				)
+				(justify mirror)
+			)
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 	(zone
-		(net 47)
+		(net 36)
 		(net_name "Net-(Q1-Pad4)")
 		(layer "In2.Cu")
 		(uuid "b30dfd68-2df7-430c-8313-841b27854228")
@@ -38998,19 +34609,19 @@
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diff --git a/kicad/c64psu/c64psu.kicad_prl b/kicad/c64psu/c64psu.kicad_prl
index b924590..d8e1fb7 100644
--- a/kicad/c64psu/c64psu.kicad_prl
+++ b/kicad/c64psu/c64psu.kicad_prl
@@ -1,7 +1,7 @@
 {
   "board": {
     "active_layer": 0,
-    "active_layer_preset": "All Layers",
+    "active_layer_preset": "",
     "auto_track_width": true,
     "hidden_netclasses": [],
     "hidden_nets": [],
diff --git a/kicad/c64psu/c64psu.kicad_pro b/kicad/c64psu/c64psu.kicad_pro
index 6b110cb..837027d 100644
--- a/kicad/c64psu/c64psu.kicad_pro
+++ b/kicad/c64psu/c64psu.kicad_pro
@@ -48,7 +48,7 @@
         "silk_text_thickness": 0.1,
         "silk_text_upright": false,
         "zones": {
-          "min_clearance": 0.2
+          "min_clearance": 0.5
         }
       },
       "diff_pair_dimensions": [
@@ -58,7 +58,76 @@
           "width": 0.0
         }
       ],
-      "drc_exclusions": [],
+      "drc_exclusions": [
+        [
+          "footprint_symbol_mismatch|168613100|54282350|5a502ee0-e8a8-4e95-93b8-4c1514a99e91|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|136887500|57596750|5f2f0b99-bdb4-44f5-9350-d1ea18bc2d7f|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|140863400|76894200|8956c995-5caf-4690-8c1d-d09927afbc8b|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|147010200|91372200|591eea2c-7002-439b-99dd-a27b48041182|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|151151699|77857700|a2a8f815-24b1-4e38-87c7-936b04fbf5c7|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|152627600|53672750|80d848ab-818c-4c6f-b791-edfe63fd79d5|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|157343000|53682550|4089365a-2a9f-4c5c-8e56-f7b17c5cbd66|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|161075000|73125000|dd7c36ec-083d-459a-a327-f8f096aa3376|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|164680000|78332500|b6a5d7c3-440b-4628-a7bf-7265f691c709|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|165012600|91998800|4cf42998-2ce7-4300-957c-40d807f36117|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|165063400|77622400|ffaaa5ce-33e3-4c61-857e-0019cf77aee1|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|172262800|84531200|576ce062-6b6e-497c-b256-542c26ea5456|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|174929600|99212400|c0509443-0a46-414a-95a3-6ccf7e93e714|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|175107600|69138800|fe196612-287b-4e45-ac21-3a149b0ae018|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|190906400|84443700|163e8590-a204-43e9-9339-a4161faa7720|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
+          "lib_footprint_mismatch|193598800|48920399|e20c6d70-ca25-4b4b-b942-da573dc77771|00000000-0000-0000-0000-000000000000",
+          ""
+        ],
+        [
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+          ""
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+      ],
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diff --git a/kicad/c64psu/c64psu.kicad_sch b/kicad/c64psu/c64psu.kicad_sch
index c6613f4..9070113 100644
--- a/kicad/c64psu/c64psu.kicad_sch
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 			)
 			(embedded_fonts no)
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 				)
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@@ -20157,6 +18324,72 @@
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@@ -20408,6 +18641,72 @@
 			)
 		)
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 		(lib_id "power:GND")
 		(at 175.26 177.8 0)
@@ -20550,6 +18849,91 @@
 			)
 		)
 	)
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@@ -20682,197 +19066,6 @@
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@@ -20940,32 +19133,32 @@
 		)
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+		(lib_id "Device:C")
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-		(property "Footprint" "Resistor_SMD:R_0402_1005Metric"
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+		(property "Footprint" "Capacitor_SMD:C_1210_3225Metric"
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@@ -20973,8 +19166,8 @@
 				(hide yes)
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-		(property "Datasheet" "~"
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+		(property "Datasheet" "https://ds.yuden.co.jp/TYCOMPAS/ut/detail?pn=MSASU32MSB5106KPNA01&u=M"
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@@ -20982,8 +19175,8 @@
 				(hide yes)
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 				(hide yes)
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 			)
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 		(property "Part Number" ""
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 		)
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-		(property "Footprint" "Capacitor_SMD:C_0805_2012Metric"
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+		(property "Footprint" "MountingHole:MountingHole_3.2mm_M3_DIN965_Pad_TopBottom"
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+		(property "Description" "Mounting Hole with connection"
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 		(property "Value" "GND"
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+			(at 273.05 191.7699 0)
 			(effects
 				(font
 					(size 1.27 1.27)
 				)
+				(justify left)
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 		)
 		(property "Footprint" ""
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+			(at 270.51 190.5 0)
 			(effects
 				(font
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@@ -27244,7 +24651,7 @@
 			)
 		)
 		(property "Datasheet" ""
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+			(at 270.51 190.5 0)
 			(effects
 				(font
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@@ -27253,7 +24660,7 @@
 			)
 		)
 		(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
-			(at 248.92 219.71 0)
+			(at 270.51 190.5 0)
 			(effects
 				(font
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@@ -27339,83 +24746,6 @@
 			)
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-				(font
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 	(symbol
 		(lib_id "Device:C")
 		(at 55.88 165.1 0)
@@ -27533,6 +24863,73 @@
 			)
 		)
 	)
+	(symbol
+		(lib_id "Mechanical:MountingHole_Pad")
+		(at 298.45 100.33 0)
+		(unit 1)
+		(exclude_from_sim no)
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+		(dnp no)
+		(fields_autoplaced yes)
+		(uuid "e513a14a-576d-4c0f-ac0d-0b2c725dd566")
+		(property "Reference" "H2"
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+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left)
+			)
+		)
+		(property "Value" "MountingHole_Pad"
+			(at 300.99 100.3299 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left)
+			)
+		)
+		(property "Footprint" "MountingHole:MountingHole_3.2mm_M3_DIN965_Pad_TopBottom"
+			(at 298.45 100.33 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(hide yes)
+			)
+		)
+		(property "Datasheet" "~"
+			(at 298.45 100.33 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(hide yes)
+			)
+		)
+		(property "Description" "Mounting Hole with connection"
+			(at 298.45 100.33 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(hide yes)
+			)
+		)
+		(pin "1"
+			(uuid "0ccc0a53-ed49-4efd-ba10-bd3a07d687a9")
+		)
+		(instances
+			(project "c64psu"
+				(path "/3c972f41-0cf6-4df5-8102-00aa652b6726"
+					(reference "H2")
+					(unit 1)
+				)
+			)
+		)
+	)
 	(symbol
 		(lib_id "Device:R")
 		(at 238.76 201.93 0)
@@ -27612,103 +25009,6 @@
 			)
 		)
 	)
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-		(lib_id "Device:R")
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-				(font
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-		(property "Value" "10k"
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-				(font
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-		(property "Footprint" "Resistor_SMD:R_0402_1005Metric"
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-				(font
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-				(hide yes)
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-		(property "Description" "Resistor"
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-			(effects
-				(font
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-				(hide yes)
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-		(property "MPN" "RC0402JR-0710KL"
-			(at 191.77 43.18 0)
-			(effects
-				(font
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-				(hide yes)
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-		(property "Part Number" ""
-			(at 191.77 43.18 0)
-			(effects
-				(font
-					(size 1.27 1.27)
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-				(hide yes)
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-		(property "Specifications" ""
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-				(font
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-		(pin "1"
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-		(pin "2"
-			(uuid "90ffba11-b618-47f1-9acc-961ebccde614")
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-		(instances
-			(project "c64psu"
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-	)
 	(symbol
 		(lib_id "Device:R")
 		(at 72.39 165.1 0)
@@ -28056,83 +25356,6 @@
 			)
 		)
 	)
-	(symbol
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-		(at 228.6 24.13 90)
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-		(uuid "f14215a0-6bf5-4907-9705-b5e104674115")
-		(property "Reference" "R8"
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-		(property "Value" "3.24k"
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-				(font
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-		(property "Footprint" "Resistor_SMD:R_0402_1005Metric"
-			(at 228.6 25.908 90)
-			(effects
-				(font
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-				(hide yes)
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-		(property "Datasheet" "~"
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-			(effects
-				(font
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-				(hide yes)
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-		)
-		(property "Description" "Resistor"
-			(at 228.6 24.13 0)
-			(effects
-				(font
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-				)
-				(hide yes)
-			)
-		)
-		(property "MPN" "RC0402FR-073K24L"
-			(at 228.6 24.13 90)
-			(effects
-				(font
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-				(hide yes)
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-		(pin "2"
-			(uuid "45df55bf-a249-4247-9a44-01e8d7d06228")
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-		(pin "1"
-			(uuid "60b2114b-55b9-4213-b59d-6a69a5c8fc37")
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-		(instances
-			(project ""
-				(path "/3c972f41-0cf6-4df5-8102-00aa652b6726"
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-	)
 	(symbol
 		(lib_id "Device:C")
 		(at 59.69 93.98 180)
@@ -28326,17 +25549,35 @@
 		)
 	)
 	(symbol
-		(lib_id "power:GND")
-		(at 241.3 90.17 0)
+		(lib_id "Mechanical:MountingHole_Pad")
+		(at 274.32 100.33 0)
 		(unit 1)
 		(exclude_from_sim no)
-		(in_bom yes)
+		(in_bom no)
 		(on_board yes)
 		(dnp no)
 		(fields_autoplaced yes)
-		(uuid "f663f3cc-a05d-4c0c-8b6c-712ff025a268")
-		(property "Reference" "#PWR018"
-			(at 241.3 96.52 0)
+		(uuid "f604aa64-ced0-4f56-8986-0cee27aa8f45")
+		(property "Reference" "H1"
+			(at 276.86 97.7899 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left)
+			)
+		)
+		(property "Value" "MountingHole_Pad"
+			(at 276.86 100.3299 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left)
+			)
+		)
+		(property "Footprint" "MountingHole:MountingHole_3.2mm_M3_DIN965_Pad_TopBottom"
+			(at 274.32 100.33 0)
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -28344,16 +25585,8 @@
 				(hide yes)
 			)
 		)
-		(property "Value" "GND"
-			(at 241.3 95.25 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-			)
-		)
-		(property "Footprint" ""
-			(at 241.3 90.17 0)
+		(property "Datasheet" "~"
+			(at 274.32 100.33 0)
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -28361,17 +25594,8 @@
 				(hide yes)
 			)
 		)
-		(property "Datasheet" ""
-			(at 241.3 90.17 0)
-			(effects
-				(font
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-				)
-				(hide yes)
-			)
-		)
-		(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
-			(at 241.3 90.17 0)
+		(property "Description" "Mounting Hole with connection"
+			(at 274.32 100.33 0)
 			(effects
 				(font
 					(size 1.27 1.27)
@@ -28380,78 +25604,12 @@
 			)
 		)
 		(pin "1"
-			(uuid "4254832b-c8cd-4c1f-9b67-38cda8eb0c38")
+			(uuid "30f70cff-aca1-4163-84cc-989831c4ec3c")
 		)
 		(instances
-			(project "c64psu"
+			(project ""
 				(path "/3c972f41-0cf6-4df5-8102-00aa652b6726"
-					(reference "#PWR018")
-					(unit 1)
-				)
-			)
-		)
-	)
-	(symbol
-		(lib_id "power:GND")
-		(at 251.46 81.28 0)
-		(unit 1)
-		(exclude_from_sim no)
-		(in_bom yes)
-		(on_board yes)
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-		(fields_autoplaced yes)
-		(uuid "f687fc2a-5f1f-4b50-aef2-5f4c4f593153")
-		(property "Reference" "#PWR017"
-			(at 251.46 87.63 0)
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-				(hide yes)
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-		(property "Value" "GND"
-			(at 251.46 86.36 0)
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-		(property "Footprint" ""
-			(at 251.46 81.28 0)
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-		(property "Datasheet" ""
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-			(effects
-				(font
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-				(hide yes)
-			)
-		)
-		(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
-			(at 251.46 81.28 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(hide yes)
-			)
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-		(pin "1"
-			(uuid "51088575-f091-494c-ba14-1ef43b69d7ec")
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-		(instances
-			(project "c64psu"
-				(path "/3c972f41-0cf6-4df5-8102-00aa652b6726"
-					(reference "#PWR017")
+					(reference "H1")
 					(unit 1)
 				)
 			)
@@ -28613,71 +25771,6 @@
 			)
 		)
 	)
-	(symbol
-		(lib_id "power:GND")
-		(at 182.88 48.26 0)
-		(unit 1)
-		(exclude_from_sim no)
-		(in_bom yes)
-		(on_board yes)
-		(dnp no)
-		(uuid "f82f0fff-1ba3-44ac-bb49-fa098e381856")
-		(property "Reference" "#PWR020"
-			(at 182.88 54.61 0)
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-				(hide yes)
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-		(property "Value" "GND"
-			(at 180.594 47.244 0)
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-		(property "Footprint" ""
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-		(property "Datasheet" ""
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-				(font
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-				(hide yes)
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-		(property "Description" "Power symbol creates a global label with name \"GND\" , ground"
-			(at 182.88 48.26 0)
-			(effects
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-		(pin "1"
-			(uuid "a7629642-01be-451c-8eab-41ee6067e19b")
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-		(instances
-			(project "c64psu"
-				(path "/3c972f41-0cf6-4df5-8102-00aa652b6726"
-					(reference "#PWR020")
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-			)
-		)
-	)
 	(symbol
 		(lib_id "power:GND")
 		(at 34.29 125.73 270)
diff --git a/kicad/c64psu/lib/LIB_TPP363082-T6TR/TPP363082-T6TR/KiCad/TPP363082-T6TR.bak b/kicad/c64psu/lib/LIB_TPP363082-T6TR/TPP363082-T6TR/KiCad/TPP363082-T6TR.bak
new file mode 100644
index 0000000..75f5f81
--- /dev/null
+++ b/kicad/c64psu/lib/LIB_TPP363082-T6TR/TPP363082-T6TR/KiCad/TPP363082-T6TR.bak
@@ -0,0 +1,249 @@
+(kicad_symbol_lib
+	(version 20241209)
+	(generator "kicad_symbol_editor")
+	(generator_version "9.0")
+	(symbol "TPP363082-T6TR"
+		(exclude_from_sim no)
+		(in_bom yes)
+		(on_board yes)
+		(property "Reference" "IC"
+			(at 24.13 7.62 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+			)
+		)
+		(property "Value" "TPP363082-T6TR"
+			(at 24.13 5.08 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+			)
+		)
+		(property "Footprint" "SOT95P280X95-6N"
+			(at 24.13 -94.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Datasheet" "http://file.3peakic.com.cn:8080/product/Datasheet_TPP36308.pdf"
+			(at 24.13 -194.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Description" "Step-Down DC-DC Voltage Converter IC TSOT23-6"
+			(at 14.732 -9.398 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(hide yes)
+			)
+		)
+		(property "Height" "0.95"
+			(at 24.13 -394.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Manufacturer_Name" "3Peak Incorporated"
+			(at 24.13 -494.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Manufacturer_Part_Number" "TPP363082-T6TR"
+			(at 24.13 -594.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Mouser Part Number" ""
+			(at 24.13 -694.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Mouser Price/Stock" ""
+			(at 24.13 -794.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Arrow Part Number" ""
+			(at 24.13 -894.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Arrow Price/Stock" ""
+			(at 24.13 -994.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(symbol "TPP363082-T6TR_1_1"
+			(rectangle
+				(start 5.08 2.54)
+				(end 22.86 -20.955)
+				(stroke
+					(width 0.254)
+					(type default)
+				)
+				(fill
+					(type background)
+				)
+			)
+			(pin passive line
+				(at 0 0 0)
+				(length 5.08)
+				(name "VIN"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+				(number "3"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+			)
+			(pin passive line
+				(at 0 -8.89 0)
+				(length 5.08)
+				(name "EN"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+				(number "5"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+			)
+			(pin passive line
+				(at 0 -19.05 0)
+				(length 5.08)
+				(name "GND"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+				(number "1"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+			)
+			(pin passive line
+				(at 27.94 0 180)
+				(length 5.08)
+				(name "SW"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+				(number "2"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+			)
+			(pin passive line
+				(at 27.94 -8.89 180)
+				(length 5.08)
+				(name "VBST"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+				(number "6"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+			)
+			(pin passive line
+				(at 27.94 -19.05 180)
+				(length 5.08)
+				(name "VFB"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+				(number "4"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+			)
+		)
+		(embedded_fonts no)
+	)
+)
diff --git a/kicad/c64psu/lib/LIB_TPP363082-T6TR/TPP363082-T6TR/KiCad/TPP363082-T6TR.kicad_sym b/kicad/c64psu/lib/LIB_TPP363082-T6TR/TPP363082-T6TR/KiCad/TPP363082-T6TR.kicad_sym
index 82b1ee8..75f5f81 100644
--- a/kicad/c64psu/lib/LIB_TPP363082-T6TR/TPP363082-T6TR/KiCad/TPP363082-T6TR.kicad_sym
+++ b/kicad/c64psu/lib/LIB_TPP363082-T6TR/TPP363082-T6TR/KiCad/TPP363082-T6TR.kicad_sym
@@ -1,70 +1,249 @@
-(kicad_symbol_lib (version 20211014) (generator SamacSys_ECAD_Model)
-  (symbol "TPP363082-T6TR" (in_bom yes) (on_board yes)
-    (property "Reference" "IC" (at 24.13 7.62 0)
-      (effects (font (size 1.27 1.27)) (justify left top))
-    )
-    (property "Value" "TPP363082-T6TR" (at 24.13 5.08 0)
-      (effects (font (size 1.27 1.27)) (justify left top))
-    )
-    (property "Footprint" "SOT95P280X95-6N" (at 24.13 -94.92 0)
-      (effects (font (size 1.27 1.27)) (justify left top) hide)
-    )
-    (property "Datasheet" "http://file.3peakic.com.cn:8080/product/Datasheet_TPP36308.pdf" (at 24.13 -194.92 0)
-      (effects (font (size 1.27 1.27)) (justify left top) hide)
-    )
-    (property "ki_description" "Step-Down DC-DC Voltage Converter IC TSOT23-6" (at 24.13 -294.92 0)
-      (effects (font (size 1.27 1.27)) (justify left top) hide)
-    )
-    (property "Height" "0.95" (at 24.13 -394.92 0)
-      (effects (font (size 1.27 1.27)) (justify left top) hide)
-    )
-    (property "Manufacturer_Name" "3Peak Incorporated" (at 24.13 -494.92 0)
-      (effects (font (size 1.27 1.27)) (justify left top) hide)
-    )
-    (property "Manufacturer_Part_Number" "TPP363082-T6TR" (at 24.13 -594.92 0)
-      (effects (font (size 1.27 1.27)) (justify left top) hide)
-    )
-    (property "Mouser Part Number" "" (at 24.13 -694.92 0)
-      (effects (font (size 1.27 1.27)) (justify left top) hide)
-    )
-    (property "Mouser Price/Stock" "" (at 24.13 -794.92 0)
-      (effects (font (size 1.27 1.27)) (justify left top) hide)
-    )
-    (property "Arrow Part Number" "" (at 24.13 -894.92 0)
-      (effects (font (size 1.27 1.27)) (justify left top) hide)
-    )
-    (property "Arrow Price/Stock" "" (at 24.13 -994.92 0)
-      (effects (font (size 1.27 1.27)) (justify left top) hide)
-    )
-    (rectangle
-      (start 5.08 2.54)
-      (end 22.86 -7.62)
-      (stroke (width 0.254) (type default))
-      (fill (type background))
-    )
-    (pin passive line (at 0 0 0) (length 5.08)
-      (name "GND" (effects (font (size 1.27 1.27))))
-      (number "1" (effects (font (size 1.27 1.27))))
-    )
-    (pin passive line (at 0 -2.54 0) (length 5.08)
-      (name "SW" (effects (font (size 1.27 1.27))))
-      (number "2" (effects (font (size 1.27 1.27))))
-    )
-    (pin passive line (at 0 -5.08 0) (length 5.08)
-      (name "VIN" (effects (font (size 1.27 1.27))))
-      (number "3" (effects (font (size 1.27 1.27))))
-    )
-    (pin passive line (at 27.94 0 180) (length 5.08)
-      (name "VBST" (effects (font (size 1.27 1.27))))
-      (number "6" (effects (font (size 1.27 1.27))))
-    )
-    (pin passive line (at 27.94 -2.54 180) (length 5.08)
-      (name "EN" (effects (font (size 1.27 1.27))))
-      (number "5" (effects (font (size 1.27 1.27))))
-    )
-    (pin passive line (at 27.94 -5.08 180) (length 5.08)
-      (name "VFB" (effects (font (size 1.27 1.27))))
-      (number "4" (effects (font (size 1.27 1.27))))
-    )
-  )
+(kicad_symbol_lib
+	(version 20241209)
+	(generator "kicad_symbol_editor")
+	(generator_version "9.0")
+	(symbol "TPP363082-T6TR"
+		(exclude_from_sim no)
+		(in_bom yes)
+		(on_board yes)
+		(property "Reference" "IC"
+			(at 24.13 7.62 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+			)
+		)
+		(property "Value" "TPP363082-T6TR"
+			(at 24.13 5.08 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+			)
+		)
+		(property "Footprint" "SOT95P280X95-6N"
+			(at 24.13 -94.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Datasheet" "http://file.3peakic.com.cn:8080/product/Datasheet_TPP36308.pdf"
+			(at 24.13 -194.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Description" "Step-Down DC-DC Voltage Converter IC TSOT23-6"
+			(at 14.732 -9.398 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(hide yes)
+			)
+		)
+		(property "Height" "0.95"
+			(at 24.13 -394.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Manufacturer_Name" "3Peak Incorporated"
+			(at 24.13 -494.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Manufacturer_Part_Number" "TPP363082-T6TR"
+			(at 24.13 -594.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Mouser Part Number" ""
+			(at 24.13 -694.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Mouser Price/Stock" ""
+			(at 24.13 -794.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Arrow Part Number" ""
+			(at 24.13 -894.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(property "Arrow Price/Stock" ""
+			(at 24.13 -994.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left top)
+				(hide yes)
+			)
+		)
+		(symbol "TPP363082-T6TR_1_1"
+			(rectangle
+				(start 5.08 2.54)
+				(end 22.86 -20.955)
+				(stroke
+					(width 0.254)
+					(type default)
+				)
+				(fill
+					(type background)
+				)
+			)
+			(pin passive line
+				(at 0 0 0)
+				(length 5.08)
+				(name "VIN"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+				(number "3"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+			)
+			(pin passive line
+				(at 0 -8.89 0)
+				(length 5.08)
+				(name "EN"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+				(number "5"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+			)
+			(pin passive line
+				(at 0 -19.05 0)
+				(length 5.08)
+				(name "GND"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+				(number "1"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+			)
+			(pin passive line
+				(at 27.94 0 180)
+				(length 5.08)
+				(name "SW"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+				(number "2"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+			)
+			(pin passive line
+				(at 27.94 -8.89 180)
+				(length 5.08)
+				(name "VBST"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+				(number "6"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+			)
+			(pin passive line
+				(at 27.94 -19.05 180)
+				(length 5.08)
+				(name "VFB"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+				(number "4"
+					(effects
+						(font
+							(size 1.27 1.27)
+						)
+					)
+				)
+			)
+		)
+		(embedded_fonts no)
+	)
 )
diff --git a/kicad/c64psu/~_autosave-c64psu.kicad_pcb.lck b/kicad/c64psu/~c64psu.kicad_sch.lck
similarity index 100%
rename from kicad/c64psu/~_autosave-c64psu.kicad_pcb.lck
rename to kicad/c64psu/~c64psu.kicad_sch.lck