release/: JLCPCB order files when the repository makes them

A repository with .gitea/scripts/jlcpcb-files.py (harNES) gets
<board>-<tag>-jlcpcb-bom.csv and -jlcpcb-cpl.csv (rotations corrected per
LCSC part) in release/: the script runs with --force on a copy of hardware/
without the committed jlcpcb/ folders, so nothing stale is taken. When it
refuses a board (DRC, missing correction), release/README.md and a workflow
warning say why; the generic -cpl.csv then is the only placement file.

TEMPLATE.md

@@ -121,6 +121,7 @@ stage tag is pushed; nobody edits it.
 | `release/hardware/<board>/<board>-<tag>-cpl.csv` | pick and place (KiCad position file, mm, both sides, DNP left out) |
 | `release/hardware/<board>/<board>-<tag>-schematic.pdf`, `-pcb.pdf` | the schematic; the PCB with one page per copper, silkscreen and fab layer |
 | `release/hardware/<board>/<board>-<tag>-top.png`, `-bottom.png` | 3D renders |
+| `release/hardware/<board>/<board>-<tag>-jlcpcb-bom.csv`, `-jlcpcb-cpl.csv` | only in a repository with `.gitea/scripts/jlcpcb-files.py` (harNES): JLCPCB's BOM and a CPL with rotations corrected per LCSC part, made only from a clean DRC; use these, not `-cpl.csv`, for JLCPCB assembly |
 | `release/docs/<name>-<tag>.pdf` | every `docs/*.md` except `README.md` and `input.md` (pandoc), and every `docs/tex/*.tex` with a `\documentclass` (pdflatex); the footer carries product, tag, commit and date |
 
 - Boards are the `[[boards]]` of `proplan.toml` (or `hardware/*/*.kicad_pro`
@@ -146,8 +147,9 @@ stage tag is pushed; nobody edits it.
   writes the same files to `build/` (ignored by git).
 
 Not in it (yet): firmware binaries (firmware has its own tags), STEP models
-(`mech/`), JLCPCB-specific BOM/CPL with rotation corrections (harNES's
-`jlcpcb-files.py` does that per push).
+(`mech/`). JLCPCB order files need `jlcpcb-files.py` and a
+`jlcpcb-corrections.csv` per board (harNES has both); without them the generic
+`-cpl.csv` carries KiCad's rotations, which JLCPCB's footprints may not share.
 
 ## proplan.toml