janikandClaude Fable 5
26b1cfaa45
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Multiple Thevenin supplies and prescribed-current loads on one net, solved in absolute volts with the Tellegen power balance verified per run; a source-sink pair table (effective copper resistance per supply x load pair plus an exactly-summing proportional-sharing loss attribution), in summary.txt and as its own figure. Bonded terminals short a package's contacts into one lug so the per-pin split becomes a solve outcome. Geometry dumps carry the terminal set (schema v8). The dialog gained a Classic/PDN mode selector and a full PDN editor: per-role supply/load tables built from the marker rectangles (or a config's terminal set, which never pins mode or net), with Component hints, per-terminal Layer scopes, Active checkboxes, comments, a per-net row filter, resizable tables and a scrolling, screen-sized dialog. Numbers accept SI suffixes (50m, 4.7k) everywhere. fill_res_config.json fully specifies a run (classic or PDN) with validation, comments, named side-by-side configs (the one called default auto-loads), Load/Save buttons with an editable file name, and saves that never drop anything drawn on the board. 347 tests, green on Python 3.13 and on the 3.9 macOS wheel stack. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
202 lines
12 KiB
Python
202 lines
12 KiB
Python
"""All tunable constants; the dialog exposes the common ones per run.
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A <board dir>/fill_res_config.json (see configfile.py) can override the
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run parameters, select physics constants and the marker layers, and in
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PDN mode defines the supply/load terminals. Values here remain the
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defaults when no config file is present.
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"""
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from __future__ import annotations # KiCad's macOS Python is 3.9: without
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# this, `float | None` annotations are
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# evaluated at import and crash there
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# --- Grid sizing ---
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# Benchmarked on the VOUT+ plane (147x59 mm): R changes < 0.3% from
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# 150 um cells down to 50 um. Accuracy is feature-limited (slots/necks
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# narrower than one cell), not plane-limited - override CELL_UM_OVERRIDE
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# for boards with sub-cell slots.
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TARGET_CELLS = 2_000_000 # auto cell size aims for roughly this many cells
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HARD_MAX_CELLS = 16_000_000 # abort above this (see GridSizeError message)
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MIN_CELL_UM = 25.0 # clamp for auto cell size
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MAX_CELL_UM = 500.0
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CELL_UM_OVERRIDE: float | None = None # force a cell size, bypasses auto (not HARD_MAX)
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MARGIN_CELLS = 2 # empty guard cells around the copper bbox
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# --- Physics ---
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RHO_CU_OHM_M = 1.68e-8 # copper resistivity at 20 degC
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COPPER_THICKNESS_UM: float | None = None # None -> stackup, fallback 35.0 with warning
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FALLBACK_THICKNESS_UM = 35.0
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TEST_CURRENT_A = 1.0 # default injected current (dialog/CLI-selectable)
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VIA_PLATING_UM = 18.0 # barrel plating thickness (always plated)
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VIAS_CAPPED = True # filled + capped vias (dialog checkbox):
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# outer-layer mouths carry a CAP_PLATING_UM
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# thin copper cap, inner-layer mouths are
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# holes. False = open mouths on all layers.
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# Ring/pad copper of vias is modeled either
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# way; THT-pad copper/drills are not.
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CAP_PLATING_UM = 15.0 # cap plating thickness (fab spec)
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CAP_MAX_DRILL_MM = 0.5 # fab caps only small vias: drills above this
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# stay open even with VIAS_CAPPED
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# (dialog-settable)
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INCLUDE_SMD_PADS = True # the net's SMD pad copper conducts too (exact
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# shapes on the pad's layer): pads are the
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# junctions where traces/spokes meet, and
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# selected pad contacts get their real copper.
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# Dead-end pads are dropped as floating islands
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INCLUDE_TH_PADS = True # plated through-hole pads stitch layers too;
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# their holes are modeled solder-filled (a
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# soldered component lead), so the solder core
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# conducts in parallel with the plating
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THT_LEAD_PROTRUSION_MM = 1.5 # clipped THT lead protrusion on the side
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# opposite the component: a solder cone of
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# this height at the drill wall (tapering to
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# zero at the pad edge) wraps the lead of
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# every populated THT pad. 0 = no cones
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THT_LEAD_CLEARANCE_MM = 0.25 # hole diameter minus lead diameter (fab
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# rule): a lead cylinder of drill - this
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# conducts inside every solder-filled hole
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THT_LEAD_RHO_OHM_M = 1.68e-8 # lead material resistivity: copper leads/
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# wires; brass ~6.4e-8, phosphor bronze
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# ~1.1e-7, copper-clad steel higher - raise
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# this if your components use such leads
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SKIN_SIDES = 1 # skin-effect field config: 1 = plane facing a
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# return plane (conservative), 2 = isolated foil
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# --- Solder / mask-opening buildup ---
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INCLUDE_MASK_BUILDUP = False # OFF by default; dialog-toggleable. Zones on
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# F.Mask/B.Mask = mask openings that collect
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# solder on the pour underneath
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SOLDER_THICKNESS_UM = 50.0 # solder height over opened copper
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SOLDER_RHO_OHM_M = 1.32e-7 # SAC305, ~7.9x copper
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BUILDUP_EXTRA_CU_UM = 0.0 # optional user-added copper (busbar/wire
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# soldered into the opening); dialog-settable
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# --- Zone / layer selection ---
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INCLUDE_TRACKS = True # the net's traces (straight + arc tracks)
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# conduct together with the zone fills;
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# dialog-toggleable
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TRACK_1D_FACTOR = 3.0 # traces narrower than this many grid cells
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# become exact 1D resistor chains along their
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# centerline instead of rasterized outlines
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# (no discretization error in the trace R;
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# 0 = always rasterize)
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LAYER_HINT: str | None = None # e.g. "F.Cu" to disambiguate candidate fills
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ELECTRODE_POS_LAYER = "User.1" # rectangles on this layer mark V+ contact parts
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ELECTRODE_NEG_LAYER = "User.2" # rectangles on this layer mark V- contact parts
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ELECTRODE_PDN_LAYER = "User.3" # PDN mode: rectangles referenced from the
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# config file as "rect:NAME" live here, named
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# by a text item placed inside them (role
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# comes from the config entry, so one layer
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# serves supplies and loads alike)
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ALWAYS_REFILL = False # refill zones even if KiCad says they are filled
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# --- Configuration file ---
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CONFIG_FILENAME = "fill_res_config.json"
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# searched next to the board file, after the
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# board-specific "<stem>.fill_res_config.json"
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# (several boards can share a directory)
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# --- In-KiCad result overlays (EXPERIMENTAL) ---
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PUSH_OVERLAYS = False # after solving, push the per-layer |J|
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# heatmaps into the open board as unlocked
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# reference images (editor-only, never
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# plotted); dialog-toggleable
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OVERLAY_LAYERS = ("User.9", "User.10", "User.11", "User.12")
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# copper layers map here in stackup order
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# (top first); existing reference images on
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# these layers are REPLACED on every push;
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# each must be enabled in Board Setup
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OVERLAY_ALPHA = 255 # overlay opacity over copper (0-255);
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# translucency washes out over bright
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# copper - toggle the User layer instead
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# --- Low-current copper marking (EXPERIMENTAL) ---
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TRIM_ENABLED = False # dialog default: mark the copper below
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# TRIM_THRESHOLD_PCT as polygons on
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# TRIM_LAYERS. A suggestion, not a safe
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# cut list: copper carries little current
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# BECAUSE the rest carries it - removal
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# redistributes |J|, re-run after changes
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TRIM_MODE = "pct" # dialog default for the threshold unit:
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# "pct" (% of the mean |J|) or "abs"
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# (A/mm2)
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TRIM_THRESHOLD_PCT = 10.0 # relative threshold: % of the mean |J|
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# over all solved copper cells (mean, not
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# max: contact-corner spikes would dwarf
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# a max-relative threshold)
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TRIM_THRESHOLD_A_MM2 = 1.0 # absolute threshold [A/mm2]. |J| scales
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# with the test current, so this is only
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# meaningful with the real operating
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# current entered as test current
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TRIM_LAYERS = ("User.5", "User.6", "User.7", "User.8")
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# copper layers map here in stackup order
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# (top first); existing polygons on these
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# layers are REPLACED on every push; each
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# must be enabled in Board Setup
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TRIM_MIN_AREA_MM2 = 0.5 # marked specks smaller than this are
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# dropped (nothing useful to reclaim)
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# --- Adaptive grid ---
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ADAPTIVE_CELLS = True # solve on a 2:1-balanced quadtree: fine at
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# copper boundaries/electrodes/features,
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# coarse plane interiors (dialog-toggleable).
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# With the deferred-correction pass the
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# deviation from the uniform grid is <0.03%
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# measured; untick for the reference grid
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TARGET_CELLS_ADAPTIVE = 8_000_000 # auto cell-size budget with the adaptive
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# grid: unknowns no longer scale with the
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# fine cell count, so the auto sizer picks
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# a ~2x finer h (memory-bound: masks/fields)
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ADAPTIVE_MAX_CELL_UM = 1000.0 # coarsest leaf edge length (also the
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# granularity of the potential/field maps
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# on plane interiors). The MINIMUM element
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# size is the grid cell size itself (auto /
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# dialog / CELL_UM_OVERRIDE). The guard
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# distance caps leaf growth near features
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ADAPTIVE_GUARD = 4 # a leaf of size s needs >= GUARD*s cells of
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# clearance to the nearest feature
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ADAPTIVE_CORRECTION_PASSES = 1 # deferred-correction re-solves fixing the
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# coarse-fine interface flux bias (same
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# matrix, reused factorization/AMG). 1 pass
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# cuts the raw ~0.5-2% low bias to <0.03%
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# measured; 0 disables
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# --- PDN mode ---
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PDN_V_NOMINAL = 3.3 # default supply open-circuit voltage [V];
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# per-supply v_oc and the config file's
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# run.v_nominal override it. Only shifts the
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# absolute-volt reporting reference - drops
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# and currents are independent of it
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PDN_R_OUT_EPS = 1e-12 # supplies with r_out_ohm at or below this
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# become ideal (Dirichlet) contacts: the
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# exact R_out -> 0 limit, avoiding a huge
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# attachment conductance in the matrix
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# --- Solver ---
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CONTACT_MODEL = "uniform" # "uniform": conductor pressed on top injects
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# orthogonally with uniform surface density
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# (J ramps across the contact); "equipotential":
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# ideal bonded lug (Dirichlet). The two bracket
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# a real contact: R_equi <= R_real <= R_uniform.
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SPSOLVE_MAX_UNKNOWNS = 500_000 # above this, AMG-preconditioned CG (pyamg;
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# Jacobi-CG if pyamg is missing). Direct is
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# exact and fastest for small grids; measured
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# at 1.4M unknowns: spsolve 13 s / ~3 GB,
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# AMG-CG 6 s at a fraction of the memory
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AMG_TOL = 1e-10 # relative residual of the AMG-CG solve
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CG_TOL = 1e-8 # Jacobi-CG fallback (no pyamg)
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CG_MAXITER = 50_000 # CG iterations are cheap; large grids need many
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# --- Geometry ---
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ARC_TOL_FRACTION = 0.5 # arc sagitta tolerance as a fraction of cell size
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# --- Plots / output ---
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CMAP_POTENTIAL = "viridis"
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CMAP_CURRENT = "inferno"
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CMAP_POWER = "magma"
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POWER_DYNAMIC_RANGE = 1e4 # LogNorm span for the power map (power ~ J^2)
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LOG_CURRENT_SCALE = True
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CURRENT_DYNAMIC_RANGE = 1e3 # LogNorm vmin = vmax / this
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DPI = 150
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INTERACTIVE = True # False -> save PNGs only, never open windows
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OUTPUT_DIRNAME = "fill_res_results"
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