README usage: mixed rect+pads selection example, solve-time warning
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Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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@@ -58,8 +58,14 @@ SWIG API. Requires KiCad **10.0.1+**.
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`ELECTRODE_NEG_LAYER`), any number per side, axis-aligned;
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- **pads and vias** (SMD pad: real copper shape on its own layer;
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through-hole pads and vias become **barrel contacts**: the current
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enters at the drill wall on every spanned layer, see below);
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selected pads/vias fill a side that has no rectangles;
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enters at the drill wall on every spanned layer, see below).
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Selected pads/vias fill the side that has **no rectangles**, so
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mixing both kinds is the everyday workflow: e.g. select **one
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rectangle on `User.1`** (V+) **plus any number of pads / THT
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holes** (Ctrl-click) — the pads together form the V− terminal
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(a connector's pin group, a via cluster, …). All selected
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pads/vias go to that one side; if both marker layers already
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provide rectangles, selecting pads on top is an error;
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- legacy: exactly 2 selected contacts with no marker rectangles still
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works; empty selection scans the whole board's marker layers.
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2. **Select the contacts**, click the **Fill Resistance** Ω button.
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@@ -68,7 +74,11 @@ SWIG API. Requires KiCad **10.0.1+**.
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("All selected layers" = bolted-lug/through contact), the **test
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current**, and optionally a grid cell size. Multiple layers are coupled
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through the net's via/pad barrels automatically.
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4. Read R / voltage drop / total power in the figure titles and status
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4. Wait for the solve. Depending on board size, included layers, cell
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size and your hardware it can take **considerable time** — large
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multi-layer pours at fine cell sizes may run for minutes (on our
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test setup a typical real-board run finishes in ≈ 8 s). Then read
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R / voltage drop / total power in the figure titles and status
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bar. Outputs land in `<board dir>\fill_res_results\<timestamp>\`:
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per-layer `1_raster_map` / `2_potential` / `3_current_density` /
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`4_power_density` PNGs, `summary.txt` (incl. the busiest vias with
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