Full solder joint at every populated THT pad, read from KiCad
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Build PCM package / build (push) Successful in 8s
No size-threshold guessing: whether a hole is a via or a THT pad already comes from KiCad (board.get_vias vs drilled board.get_pads). Every populated THT pad of the net now carries the complete joint the contacts got: solder-filled barrel, average-thickness coat over a pad-diameter disc on the outer layers, and the protruding-lead cone on the side opposite its owning footprint. The footprint side and the Do-not-populate flag are read from KiCad (footprint pads store absolute positions, so owner lookup is an exact (x, y, number) map); DNP pads stay plating-only with no joint. Contact pads are deduplicated by barrel center so their cone/coat is never applied twice. Barrels are now gathered in single-layer runs too: via rings and drill mouths perforate a lone plane, THT joints stiffen it locally. ViaLink gains solder_filled + protrusion_side (legacy dumps load with the old every-THT-pad-filled semantics). Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
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@@ -178,12 +178,13 @@ def _barrel_links(stack: RasterStack, problem: Problem
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length = problem.layers[lb].z_nm - problem.layers[la].z_nm
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if length <= 0:
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continue
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# THT pads carry a soldered component lead: the hole is
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# solder-filled, the core conducts in parallel with the plating
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# populated THT pads carry a soldered component lead: the hole
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# is solder-filled, the core conducts in parallel with the
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# plating (DNP pads and vias stay plating-only)
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r_dc = via.barrel_resistance(
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length, problem.rho_ohm_m, problem.plating_nm,
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solder_rho_ohm_m=(problem.solder_rho_ohm_m
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if via.kind == "pad" else None))
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if via.solder_filled else None))
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links.append((vi, la, ia, ja, lb, ib, jb, r_dc))
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return links, dead
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