janik
14610 lines
587 KiB
Plaintext
14610 lines
587 KiB
Plaintext
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feeder_mk2.elf: file format elf32-littlearm
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Sections:
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Idx Name Size VMA LMA File off Algn
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0 .isr_vector 000000c0 08000000 08000000 00001000 2**0
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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1 .text 00005244 080000c0 080000c0 000010c0 2**2
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CONTENTS, ALLOC, LOAD, READONLY, CODE
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2 .rodata 000000a8 08005304 08005304 00006304 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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3 .ARM.extab 00000000 080053ac 080053ac 00007034 2**0
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CONTENTS, READONLY
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4 .ARM 00000008 080053ac 080053ac 000063ac 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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5 .preinit_array 00000000 080053b4 080053b4 00007034 2**0
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CONTENTS, ALLOC, LOAD, DATA
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6 .init_array 00000004 080053b4 080053b4 000063b4 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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7 .fini_array 00000004 080053b8 080053b8 000063b8 2**2
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CONTENTS, ALLOC, LOAD, READONLY, DATA
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8 .data 00000034 20000000 080053bc 00007000 2**2
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CONTENTS, ALLOC, LOAD, DATA
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9 .bss 00001334 20000034 080053f0 00007034 2**2
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ALLOC
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10 ._user_heap_stack 00000600 20001368 080053f0 00007368 2**0
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ALLOC
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11 .ARM.attributes 00000028 00000000 00000000 00007034 2**0
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CONTENTS, READONLY
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12 .debug_info 0001b071 00000000 00000000 0000705c 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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13 .debug_abbrev 00002ea9 00000000 00000000 000220cd 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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14 .debug_loclists 0000bf8f 00000000 00000000 00024f76 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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15 .debug_aranges 00000f48 00000000 00000000 00030f08 2**3
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CONTENTS, READONLY, DEBUGGING, OCTETS
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16 .debug_rnglists 000013c2 00000000 00000000 00031e50 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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17 .debug_macro 00015b92 00000000 00000000 00033212 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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18 .debug_line 0001a342 00000000 00000000 00048da4 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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19 .debug_str 0008ec08 00000000 00000000 000630e6 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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20 .comment 00000043 00000000 00000000 000f1cee 2**0
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CONTENTS, READONLY
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21 .debug_frame 00002bb0 00000000 00000000 000f1d34 2**2
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CONTENTS, READONLY, DEBUGGING, OCTETS
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22 .debug_line_str 0000004d 00000000 00000000 000f48e4 2**0
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CONTENTS, READONLY, DEBUGGING, OCTETS
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Disassembly of section .text:
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080000c0 <__do_global_dtors_aux>:
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80000c0: b510 push {r4, lr}
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80000c2: 4c06 ldr r4, [pc, #24] @ (80000dc <__do_global_dtors_aux+0x1c>)
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80000c4: 7823 ldrb r3, [r4, #0]
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80000c6: 2b00 cmp r3, #0
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80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
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80000ca: 4b05 ldr r3, [pc, #20] @ (80000e0 <__do_global_dtors_aux+0x20>)
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80000cc: 2b00 cmp r3, #0
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80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
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80000d0: 4804 ldr r0, [pc, #16] @ (80000e4 <__do_global_dtors_aux+0x24>)
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80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
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80000d4: bf00 nop
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80000d6: 2301 movs r3, #1
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80000d8: 7023 strb r3, [r4, #0]
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80000da: bd10 pop {r4, pc}
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80000dc: 20000034 .word 0x20000034
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80000e0: 00000000 .word 0x00000000
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80000e4: 080052ec .word 0x080052ec
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080000e8 <frame_dummy>:
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80000e8: 4b04 ldr r3, [pc, #16] @ (80000fc <frame_dummy+0x14>)
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80000ea: b510 push {r4, lr}
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80000ec: 2b00 cmp r3, #0
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80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
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80000f0: 4903 ldr r1, [pc, #12] @ (8000100 <frame_dummy+0x18>)
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80000f2: 4804 ldr r0, [pc, #16] @ (8000104 <frame_dummy+0x1c>)
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80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
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80000f6: bf00 nop
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80000f8: bd10 pop {r4, pc}
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80000fa: 46c0 nop @ (mov r8, r8)
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80000fc: 00000000 .word 0x00000000
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8000100: 20000038 .word 0x20000038
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8000104: 080052ec .word 0x080052ec
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08000108 <__gnu_thumb1_case_uqi>:
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8000108: b402 push {r1}
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800010a: 4671 mov r1, lr
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800010c: 0849 lsrs r1, r1, #1
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800010e: 0049 lsls r1, r1, #1
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8000110: 5c09 ldrb r1, [r1, r0]
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8000112: 0049 lsls r1, r1, #1
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8000114: 448e add lr, r1
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8000116: bc02 pop {r1}
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8000118: 4770 bx lr
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800011a: 46c0 nop @ (mov r8, r8)
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0800011c <__gnu_thumb1_case_uhi>:
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800011c: b403 push {r0, r1}
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800011e: 4671 mov r1, lr
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8000120: 0849 lsrs r1, r1, #1
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8000122: 0040 lsls r0, r0, #1
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8000124: 0049 lsls r1, r1, #1
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8000126: 5a09 ldrh r1, [r1, r0]
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8000128: 0049 lsls r1, r1, #1
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800012a: 448e add lr, r1
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800012c: bc03 pop {r0, r1}
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800012e: 4770 bx lr
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08000130 <__udivsi3>:
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8000130: 2200 movs r2, #0
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8000132: 0843 lsrs r3, r0, #1
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8000134: 428b cmp r3, r1
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8000136: d374 bcc.n 8000222 <__udivsi3+0xf2>
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8000138: 0903 lsrs r3, r0, #4
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800013a: 428b cmp r3, r1
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800013c: d35f bcc.n 80001fe <__udivsi3+0xce>
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800013e: 0a03 lsrs r3, r0, #8
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8000140: 428b cmp r3, r1
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8000142: d344 bcc.n 80001ce <__udivsi3+0x9e>
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8000144: 0b03 lsrs r3, r0, #12
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8000146: 428b cmp r3, r1
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8000148: d328 bcc.n 800019c <__udivsi3+0x6c>
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800014a: 0c03 lsrs r3, r0, #16
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800014c: 428b cmp r3, r1
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800014e: d30d bcc.n 800016c <__udivsi3+0x3c>
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8000150: 22ff movs r2, #255 @ 0xff
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8000152: 0209 lsls r1, r1, #8
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8000154: ba12 rev r2, r2
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8000156: 0c03 lsrs r3, r0, #16
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8000158: 428b cmp r3, r1
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800015a: d302 bcc.n 8000162 <__udivsi3+0x32>
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800015c: 1212 asrs r2, r2, #8
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800015e: 0209 lsls r1, r1, #8
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8000160: d065 beq.n 800022e <__udivsi3+0xfe>
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8000162: 0b03 lsrs r3, r0, #12
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8000164: 428b cmp r3, r1
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8000166: d319 bcc.n 800019c <__udivsi3+0x6c>
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8000168: e000 b.n 800016c <__udivsi3+0x3c>
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800016a: 0a09 lsrs r1, r1, #8
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800016c: 0bc3 lsrs r3, r0, #15
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800016e: 428b cmp r3, r1
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8000170: d301 bcc.n 8000176 <__udivsi3+0x46>
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8000172: 03cb lsls r3, r1, #15
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8000174: 1ac0 subs r0, r0, r3
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8000176: 4152 adcs r2, r2
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8000178: 0b83 lsrs r3, r0, #14
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800017a: 428b cmp r3, r1
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800017c: d301 bcc.n 8000182 <__udivsi3+0x52>
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800017e: 038b lsls r3, r1, #14
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8000180: 1ac0 subs r0, r0, r3
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8000182: 4152 adcs r2, r2
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8000184: 0b43 lsrs r3, r0, #13
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8000186: 428b cmp r3, r1
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8000188: d301 bcc.n 800018e <__udivsi3+0x5e>
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800018a: 034b lsls r3, r1, #13
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800018c: 1ac0 subs r0, r0, r3
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800018e: 4152 adcs r2, r2
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8000190: 0b03 lsrs r3, r0, #12
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8000192: 428b cmp r3, r1
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8000194: d301 bcc.n 800019a <__udivsi3+0x6a>
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8000196: 030b lsls r3, r1, #12
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8000198: 1ac0 subs r0, r0, r3
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800019a: 4152 adcs r2, r2
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800019c: 0ac3 lsrs r3, r0, #11
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800019e: 428b cmp r3, r1
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80001a0: d301 bcc.n 80001a6 <__udivsi3+0x76>
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80001a2: 02cb lsls r3, r1, #11
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80001a4: 1ac0 subs r0, r0, r3
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80001a6: 4152 adcs r2, r2
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80001a8: 0a83 lsrs r3, r0, #10
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80001aa: 428b cmp r3, r1
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80001ac: d301 bcc.n 80001b2 <__udivsi3+0x82>
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80001ae: 028b lsls r3, r1, #10
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80001b0: 1ac0 subs r0, r0, r3
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80001b2: 4152 adcs r2, r2
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80001b4: 0a43 lsrs r3, r0, #9
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80001b6: 428b cmp r3, r1
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80001b8: d301 bcc.n 80001be <__udivsi3+0x8e>
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80001ba: 024b lsls r3, r1, #9
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80001bc: 1ac0 subs r0, r0, r3
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80001be: 4152 adcs r2, r2
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80001c0: 0a03 lsrs r3, r0, #8
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80001c2: 428b cmp r3, r1
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80001c4: d301 bcc.n 80001ca <__udivsi3+0x9a>
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80001c6: 020b lsls r3, r1, #8
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80001c8: 1ac0 subs r0, r0, r3
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80001ca: 4152 adcs r2, r2
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80001cc: d2cd bcs.n 800016a <__udivsi3+0x3a>
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80001ce: 09c3 lsrs r3, r0, #7
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80001d0: 428b cmp r3, r1
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80001d2: d301 bcc.n 80001d8 <__udivsi3+0xa8>
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80001d4: 01cb lsls r3, r1, #7
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80001d6: 1ac0 subs r0, r0, r3
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80001d8: 4152 adcs r2, r2
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80001da: 0983 lsrs r3, r0, #6
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80001dc: 428b cmp r3, r1
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80001de: d301 bcc.n 80001e4 <__udivsi3+0xb4>
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80001e0: 018b lsls r3, r1, #6
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80001e2: 1ac0 subs r0, r0, r3
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80001e4: 4152 adcs r2, r2
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80001e6: 0943 lsrs r3, r0, #5
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80001e8: 428b cmp r3, r1
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80001ea: d301 bcc.n 80001f0 <__udivsi3+0xc0>
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80001ec: 014b lsls r3, r1, #5
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80001ee: 1ac0 subs r0, r0, r3
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80001f0: 4152 adcs r2, r2
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80001f2: 0903 lsrs r3, r0, #4
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80001f4: 428b cmp r3, r1
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80001f6: d301 bcc.n 80001fc <__udivsi3+0xcc>
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80001f8: 010b lsls r3, r1, #4
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80001fa: 1ac0 subs r0, r0, r3
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80001fc: 4152 adcs r2, r2
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80001fe: 08c3 lsrs r3, r0, #3
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8000200: 428b cmp r3, r1
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8000202: d301 bcc.n 8000208 <__udivsi3+0xd8>
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8000204: 00cb lsls r3, r1, #3
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8000206: 1ac0 subs r0, r0, r3
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8000208: 4152 adcs r2, r2
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800020a: 0883 lsrs r3, r0, #2
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800020c: 428b cmp r3, r1
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800020e: d301 bcc.n 8000214 <__udivsi3+0xe4>
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8000210: 008b lsls r3, r1, #2
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8000212: 1ac0 subs r0, r0, r3
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8000214: 4152 adcs r2, r2
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8000216: 0843 lsrs r3, r0, #1
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8000218: 428b cmp r3, r1
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800021a: d301 bcc.n 8000220 <__udivsi3+0xf0>
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800021c: 004b lsls r3, r1, #1
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800021e: 1ac0 subs r0, r0, r3
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8000220: 4152 adcs r2, r2
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8000222: 1a41 subs r1, r0, r1
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8000224: d200 bcs.n 8000228 <__udivsi3+0xf8>
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8000226: 4601 mov r1, r0
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8000228: 4152 adcs r2, r2
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800022a: 4610 mov r0, r2
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800022c: 4770 bx lr
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800022e: e7ff b.n 8000230 <__udivsi3+0x100>
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8000230: b501 push {r0, lr}
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8000232: 2000 movs r0, #0
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8000234: f000 f8f0 bl 8000418 <__aeabi_idiv0>
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8000238: bd02 pop {r1, pc}
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800023a: 46c0 nop @ (mov r8, r8)
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0800023c <__aeabi_uidivmod>:
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800023c: 2900 cmp r1, #0
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800023e: d0f7 beq.n 8000230 <__udivsi3+0x100>
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8000240: e776 b.n 8000130 <__udivsi3>
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8000242: 4770 bx lr
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08000244 <__divsi3>:
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8000244: 4603 mov r3, r0
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8000246: 430b orrs r3, r1
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8000248: d47f bmi.n 800034a <__divsi3+0x106>
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800024a: 2200 movs r2, #0
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800024c: 0843 lsrs r3, r0, #1
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800024e: 428b cmp r3, r1
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8000250: d374 bcc.n 800033c <__divsi3+0xf8>
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8000252: 0903 lsrs r3, r0, #4
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8000254: 428b cmp r3, r1
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8000256: d35f bcc.n 8000318 <__divsi3+0xd4>
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8000258: 0a03 lsrs r3, r0, #8
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800025a: 428b cmp r3, r1
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800025c: d344 bcc.n 80002e8 <__divsi3+0xa4>
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800025e: 0b03 lsrs r3, r0, #12
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8000260: 428b cmp r3, r1
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8000262: d328 bcc.n 80002b6 <__divsi3+0x72>
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8000264: 0c03 lsrs r3, r0, #16
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8000266: 428b cmp r3, r1
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8000268: d30d bcc.n 8000286 <__divsi3+0x42>
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800026a: 22ff movs r2, #255 @ 0xff
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800026c: 0209 lsls r1, r1, #8
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800026e: ba12 rev r2, r2
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8000270: 0c03 lsrs r3, r0, #16
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8000272: 428b cmp r3, r1
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8000274: d302 bcc.n 800027c <__divsi3+0x38>
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8000276: 1212 asrs r2, r2, #8
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8000278: 0209 lsls r1, r1, #8
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800027a: d065 beq.n 8000348 <__divsi3+0x104>
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800027c: 0b03 lsrs r3, r0, #12
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800027e: 428b cmp r3, r1
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8000280: d319 bcc.n 80002b6 <__divsi3+0x72>
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8000282: e000 b.n 8000286 <__divsi3+0x42>
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8000284: 0a09 lsrs r1, r1, #8
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8000286: 0bc3 lsrs r3, r0, #15
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8000288: 428b cmp r3, r1
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800028a: d301 bcc.n 8000290 <__divsi3+0x4c>
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800028c: 03cb lsls r3, r1, #15
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800028e: 1ac0 subs r0, r0, r3
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8000290: 4152 adcs r2, r2
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8000292: 0b83 lsrs r3, r0, #14
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8000294: 428b cmp r3, r1
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8000296: d301 bcc.n 800029c <__divsi3+0x58>
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8000298: 038b lsls r3, r1, #14
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800029a: 1ac0 subs r0, r0, r3
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800029c: 4152 adcs r2, r2
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800029e: 0b43 lsrs r3, r0, #13
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80002a0: 428b cmp r3, r1
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80002a2: d301 bcc.n 80002a8 <__divsi3+0x64>
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80002a4: 034b lsls r3, r1, #13
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80002a6: 1ac0 subs r0, r0, r3
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80002a8: 4152 adcs r2, r2
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80002aa: 0b03 lsrs r3, r0, #12
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80002ac: 428b cmp r3, r1
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80002ae: d301 bcc.n 80002b4 <__divsi3+0x70>
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80002b0: 030b lsls r3, r1, #12
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80002b2: 1ac0 subs r0, r0, r3
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80002b4: 4152 adcs r2, r2
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80002b6: 0ac3 lsrs r3, r0, #11
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80002b8: 428b cmp r3, r1
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80002ba: d301 bcc.n 80002c0 <__divsi3+0x7c>
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80002bc: 02cb lsls r3, r1, #11
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80002be: 1ac0 subs r0, r0, r3
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80002c0: 4152 adcs r2, r2
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80002c2: 0a83 lsrs r3, r0, #10
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80002c4: 428b cmp r3, r1
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80002c6: d301 bcc.n 80002cc <__divsi3+0x88>
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80002c8: 028b lsls r3, r1, #10
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80002ca: 1ac0 subs r0, r0, r3
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80002cc: 4152 adcs r2, r2
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80002ce: 0a43 lsrs r3, r0, #9
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80002d0: 428b cmp r3, r1
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80002d2: d301 bcc.n 80002d8 <__divsi3+0x94>
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80002d4: 024b lsls r3, r1, #9
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80002d6: 1ac0 subs r0, r0, r3
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80002d8: 4152 adcs r2, r2
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80002da: 0a03 lsrs r3, r0, #8
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80002dc: 428b cmp r3, r1
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80002de: d301 bcc.n 80002e4 <__divsi3+0xa0>
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80002e0: 020b lsls r3, r1, #8
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80002e2: 1ac0 subs r0, r0, r3
|
|
80002e4: 4152 adcs r2, r2
|
|
80002e6: d2cd bcs.n 8000284 <__divsi3+0x40>
|
|
80002e8: 09c3 lsrs r3, r0, #7
|
|
80002ea: 428b cmp r3, r1
|
|
80002ec: d301 bcc.n 80002f2 <__divsi3+0xae>
|
|
80002ee: 01cb lsls r3, r1, #7
|
|
80002f0: 1ac0 subs r0, r0, r3
|
|
80002f2: 4152 adcs r2, r2
|
|
80002f4: 0983 lsrs r3, r0, #6
|
|
80002f6: 428b cmp r3, r1
|
|
80002f8: d301 bcc.n 80002fe <__divsi3+0xba>
|
|
80002fa: 018b lsls r3, r1, #6
|
|
80002fc: 1ac0 subs r0, r0, r3
|
|
80002fe: 4152 adcs r2, r2
|
|
8000300: 0943 lsrs r3, r0, #5
|
|
8000302: 428b cmp r3, r1
|
|
8000304: d301 bcc.n 800030a <__divsi3+0xc6>
|
|
8000306: 014b lsls r3, r1, #5
|
|
8000308: 1ac0 subs r0, r0, r3
|
|
800030a: 4152 adcs r2, r2
|
|
800030c: 0903 lsrs r3, r0, #4
|
|
800030e: 428b cmp r3, r1
|
|
8000310: d301 bcc.n 8000316 <__divsi3+0xd2>
|
|
8000312: 010b lsls r3, r1, #4
|
|
8000314: 1ac0 subs r0, r0, r3
|
|
8000316: 4152 adcs r2, r2
|
|
8000318: 08c3 lsrs r3, r0, #3
|
|
800031a: 428b cmp r3, r1
|
|
800031c: d301 bcc.n 8000322 <__divsi3+0xde>
|
|
800031e: 00cb lsls r3, r1, #3
|
|
8000320: 1ac0 subs r0, r0, r3
|
|
8000322: 4152 adcs r2, r2
|
|
8000324: 0883 lsrs r3, r0, #2
|
|
8000326: 428b cmp r3, r1
|
|
8000328: d301 bcc.n 800032e <__divsi3+0xea>
|
|
800032a: 008b lsls r3, r1, #2
|
|
800032c: 1ac0 subs r0, r0, r3
|
|
800032e: 4152 adcs r2, r2
|
|
8000330: 0843 lsrs r3, r0, #1
|
|
8000332: 428b cmp r3, r1
|
|
8000334: d301 bcc.n 800033a <__divsi3+0xf6>
|
|
8000336: 004b lsls r3, r1, #1
|
|
8000338: 1ac0 subs r0, r0, r3
|
|
800033a: 4152 adcs r2, r2
|
|
800033c: 1a41 subs r1, r0, r1
|
|
800033e: d200 bcs.n 8000342 <__divsi3+0xfe>
|
|
8000340: 4601 mov r1, r0
|
|
8000342: 4152 adcs r2, r2
|
|
8000344: 4610 mov r0, r2
|
|
8000346: 4770 bx lr
|
|
8000348: e05d b.n 8000406 <__divsi3+0x1c2>
|
|
800034a: 0fca lsrs r2, r1, #31
|
|
800034c: d000 beq.n 8000350 <__divsi3+0x10c>
|
|
800034e: 4249 negs r1, r1
|
|
8000350: 1003 asrs r3, r0, #32
|
|
8000352: d300 bcc.n 8000356 <__divsi3+0x112>
|
|
8000354: 4240 negs r0, r0
|
|
8000356: 4053 eors r3, r2
|
|
8000358: 2200 movs r2, #0
|
|
800035a: 469c mov ip, r3
|
|
800035c: 0903 lsrs r3, r0, #4
|
|
800035e: 428b cmp r3, r1
|
|
8000360: d32d bcc.n 80003be <__divsi3+0x17a>
|
|
8000362: 0a03 lsrs r3, r0, #8
|
|
8000364: 428b cmp r3, r1
|
|
8000366: d312 bcc.n 800038e <__divsi3+0x14a>
|
|
8000368: 22fc movs r2, #252 @ 0xfc
|
|
800036a: 0189 lsls r1, r1, #6
|
|
800036c: ba12 rev r2, r2
|
|
800036e: 0a03 lsrs r3, r0, #8
|
|
8000370: 428b cmp r3, r1
|
|
8000372: d30c bcc.n 800038e <__divsi3+0x14a>
|
|
8000374: 0189 lsls r1, r1, #6
|
|
8000376: 1192 asrs r2, r2, #6
|
|
8000378: 428b cmp r3, r1
|
|
800037a: d308 bcc.n 800038e <__divsi3+0x14a>
|
|
800037c: 0189 lsls r1, r1, #6
|
|
800037e: 1192 asrs r2, r2, #6
|
|
8000380: 428b cmp r3, r1
|
|
8000382: d304 bcc.n 800038e <__divsi3+0x14a>
|
|
8000384: 0189 lsls r1, r1, #6
|
|
8000386: d03a beq.n 80003fe <__divsi3+0x1ba>
|
|
8000388: 1192 asrs r2, r2, #6
|
|
800038a: e000 b.n 800038e <__divsi3+0x14a>
|
|
800038c: 0989 lsrs r1, r1, #6
|
|
800038e: 09c3 lsrs r3, r0, #7
|
|
8000390: 428b cmp r3, r1
|
|
8000392: d301 bcc.n 8000398 <__divsi3+0x154>
|
|
8000394: 01cb lsls r3, r1, #7
|
|
8000396: 1ac0 subs r0, r0, r3
|
|
8000398: 4152 adcs r2, r2
|
|
800039a: 0983 lsrs r3, r0, #6
|
|
800039c: 428b cmp r3, r1
|
|
800039e: d301 bcc.n 80003a4 <__divsi3+0x160>
|
|
80003a0: 018b lsls r3, r1, #6
|
|
80003a2: 1ac0 subs r0, r0, r3
|
|
80003a4: 4152 adcs r2, r2
|
|
80003a6: 0943 lsrs r3, r0, #5
|
|
80003a8: 428b cmp r3, r1
|
|
80003aa: d301 bcc.n 80003b0 <__divsi3+0x16c>
|
|
80003ac: 014b lsls r3, r1, #5
|
|
80003ae: 1ac0 subs r0, r0, r3
|
|
80003b0: 4152 adcs r2, r2
|
|
80003b2: 0903 lsrs r3, r0, #4
|
|
80003b4: 428b cmp r3, r1
|
|
80003b6: d301 bcc.n 80003bc <__divsi3+0x178>
|
|
80003b8: 010b lsls r3, r1, #4
|
|
80003ba: 1ac0 subs r0, r0, r3
|
|
80003bc: 4152 adcs r2, r2
|
|
80003be: 08c3 lsrs r3, r0, #3
|
|
80003c0: 428b cmp r3, r1
|
|
80003c2: d301 bcc.n 80003c8 <__divsi3+0x184>
|
|
80003c4: 00cb lsls r3, r1, #3
|
|
80003c6: 1ac0 subs r0, r0, r3
|
|
80003c8: 4152 adcs r2, r2
|
|
80003ca: 0883 lsrs r3, r0, #2
|
|
80003cc: 428b cmp r3, r1
|
|
80003ce: d301 bcc.n 80003d4 <__divsi3+0x190>
|
|
80003d0: 008b lsls r3, r1, #2
|
|
80003d2: 1ac0 subs r0, r0, r3
|
|
80003d4: 4152 adcs r2, r2
|
|
80003d6: d2d9 bcs.n 800038c <__divsi3+0x148>
|
|
80003d8: 0843 lsrs r3, r0, #1
|
|
80003da: 428b cmp r3, r1
|
|
80003dc: d301 bcc.n 80003e2 <__divsi3+0x19e>
|
|
80003de: 004b lsls r3, r1, #1
|
|
80003e0: 1ac0 subs r0, r0, r3
|
|
80003e2: 4152 adcs r2, r2
|
|
80003e4: 1a41 subs r1, r0, r1
|
|
80003e6: d200 bcs.n 80003ea <__divsi3+0x1a6>
|
|
80003e8: 4601 mov r1, r0
|
|
80003ea: 4663 mov r3, ip
|
|
80003ec: 4152 adcs r2, r2
|
|
80003ee: 105b asrs r3, r3, #1
|
|
80003f0: 4610 mov r0, r2
|
|
80003f2: d301 bcc.n 80003f8 <__divsi3+0x1b4>
|
|
80003f4: 4240 negs r0, r0
|
|
80003f6: 2b00 cmp r3, #0
|
|
80003f8: d500 bpl.n 80003fc <__divsi3+0x1b8>
|
|
80003fa: 4249 negs r1, r1
|
|
80003fc: 4770 bx lr
|
|
80003fe: 4663 mov r3, ip
|
|
8000400: 105b asrs r3, r3, #1
|
|
8000402: d300 bcc.n 8000406 <__divsi3+0x1c2>
|
|
8000404: 4240 negs r0, r0
|
|
8000406: b501 push {r0, lr}
|
|
8000408: 2000 movs r0, #0
|
|
800040a: f000 f805 bl 8000418 <__aeabi_idiv0>
|
|
800040e: bd02 pop {r1, pc}
|
|
|
|
08000410 <__aeabi_idivmod>:
|
|
8000410: 2900 cmp r1, #0
|
|
8000412: d0f8 beq.n 8000406 <__divsi3+0x1c2>
|
|
8000414: e716 b.n 8000244 <__divsi3>
|
|
8000416: 4770 bx lr
|
|
|
|
08000418 <__aeabi_idiv0>:
|
|
8000418: 4770 bx lr
|
|
800041a: 46c0 nop @ (mov r8, r8)
|
|
|
|
0800041c <__aeabi_ldivmod>:
|
|
800041c: 2b00 cmp r3, #0
|
|
800041e: d115 bne.n 800044c <__aeabi_ldivmod+0x30>
|
|
8000420: 2a00 cmp r2, #0
|
|
8000422: d113 bne.n 800044c <__aeabi_ldivmod+0x30>
|
|
8000424: 2900 cmp r1, #0
|
|
8000426: db06 blt.n 8000436 <__aeabi_ldivmod+0x1a>
|
|
8000428: dc01 bgt.n 800042e <__aeabi_ldivmod+0x12>
|
|
800042a: 2800 cmp r0, #0
|
|
800042c: d006 beq.n 800043c <__aeabi_ldivmod+0x20>
|
|
800042e: 2000 movs r0, #0
|
|
8000430: 43c0 mvns r0, r0
|
|
8000432: 0841 lsrs r1, r0, #1
|
|
8000434: e002 b.n 800043c <__aeabi_ldivmod+0x20>
|
|
8000436: 2180 movs r1, #128 @ 0x80
|
|
8000438: 0609 lsls r1, r1, #24
|
|
800043a: 2000 movs r0, #0
|
|
800043c: b407 push {r0, r1, r2}
|
|
800043e: 4802 ldr r0, [pc, #8] @ (8000448 <__aeabi_ldivmod+0x2c>)
|
|
8000440: a101 add r1, pc, #4 @ (adr r1, 8000448 <__aeabi_ldivmod+0x2c>)
|
|
8000442: 1840 adds r0, r0, r1
|
|
8000444: 9002 str r0, [sp, #8]
|
|
8000446: bd03 pop {r0, r1, pc}
|
|
8000448: ffffffd1 .word 0xffffffd1
|
|
800044c: b403 push {r0, r1}
|
|
800044e: 4668 mov r0, sp
|
|
8000450: b501 push {r0, lr}
|
|
8000452: 9802 ldr r0, [sp, #8]
|
|
8000454: f000 f834 bl 80004c0 <__gnu_ldivmod_helper>
|
|
8000458: 9b01 ldr r3, [sp, #4]
|
|
800045a: 469e mov lr, r3
|
|
800045c: b002 add sp, #8
|
|
800045e: bc0c pop {r2, r3}
|
|
8000460: 4770 bx lr
|
|
8000462: 46c0 nop @ (mov r8, r8)
|
|
|
|
08000464 <__aeabi_lmul>:
|
|
8000464: b5f0 push {r4, r5, r6, r7, lr}
|
|
8000466: 46ce mov lr, r9
|
|
8000468: 4699 mov r9, r3
|
|
800046a: 0c03 lsrs r3, r0, #16
|
|
800046c: 469c mov ip, r3
|
|
800046e: 0413 lsls r3, r2, #16
|
|
8000470: 4647 mov r7, r8
|
|
8000472: 0c1b lsrs r3, r3, #16
|
|
8000474: 001d movs r5, r3
|
|
8000476: 000e movs r6, r1
|
|
8000478: 4661 mov r1, ip
|
|
800047a: 0404 lsls r4, r0, #16
|
|
800047c: 0c24 lsrs r4, r4, #16
|
|
800047e: b580 push {r7, lr}
|
|
8000480: 0007 movs r7, r0
|
|
8000482: 0c10 lsrs r0, r2, #16
|
|
8000484: 434b muls r3, r1
|
|
8000486: 4365 muls r5, r4
|
|
8000488: 4341 muls r1, r0
|
|
800048a: 4360 muls r0, r4
|
|
800048c: 0c2c lsrs r4, r5, #16
|
|
800048e: 18c0 adds r0, r0, r3
|
|
8000490: 1824 adds r4, r4, r0
|
|
8000492: 468c mov ip, r1
|
|
8000494: 42a3 cmp r3, r4
|
|
8000496: d903 bls.n 80004a0 <__aeabi_lmul+0x3c>
|
|
8000498: 2380 movs r3, #128 @ 0x80
|
|
800049a: 025b lsls r3, r3, #9
|
|
800049c: 4698 mov r8, r3
|
|
800049e: 44c4 add ip, r8
|
|
80004a0: 4649 mov r1, r9
|
|
80004a2: 4379 muls r1, r7
|
|
80004a4: 4356 muls r6, r2
|
|
80004a6: 0c23 lsrs r3, r4, #16
|
|
80004a8: 042d lsls r5, r5, #16
|
|
80004aa: 0c2d lsrs r5, r5, #16
|
|
80004ac: 1989 adds r1, r1, r6
|
|
80004ae: 4463 add r3, ip
|
|
80004b0: 0424 lsls r4, r4, #16
|
|
80004b2: 1960 adds r0, r4, r5
|
|
80004b4: 18c9 adds r1, r1, r3
|
|
80004b6: bcc0 pop {r6, r7}
|
|
80004b8: 46b9 mov r9, r7
|
|
80004ba: 46b0 mov r8, r6
|
|
80004bc: bdf0 pop {r4, r5, r6, r7, pc}
|
|
80004be: 46c0 nop @ (mov r8, r8)
|
|
|
|
080004c0 <__gnu_ldivmod_helper>:
|
|
80004c0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80004c2: 46ce mov lr, r9
|
|
80004c4: 4647 mov r7, r8
|
|
80004c6: b580 push {r7, lr}
|
|
80004c8: 4691 mov r9, r2
|
|
80004ca: 4698 mov r8, r3
|
|
80004cc: 0004 movs r4, r0
|
|
80004ce: 000d movs r5, r1
|
|
80004d0: f000 f814 bl 80004fc <__divdi3>
|
|
80004d4: 0007 movs r7, r0
|
|
80004d6: 000e movs r6, r1
|
|
80004d8: 0002 movs r2, r0
|
|
80004da: 000b movs r3, r1
|
|
80004dc: 4648 mov r0, r9
|
|
80004de: 4641 mov r1, r8
|
|
80004e0: f7ff ffc0 bl 8000464 <__aeabi_lmul>
|
|
80004e4: 1a24 subs r4, r4, r0
|
|
80004e6: 418d sbcs r5, r1
|
|
80004e8: 9b08 ldr r3, [sp, #32]
|
|
80004ea: 0038 movs r0, r7
|
|
80004ec: 0031 movs r1, r6
|
|
80004ee: 601c str r4, [r3, #0]
|
|
80004f0: 605d str r5, [r3, #4]
|
|
80004f2: bcc0 pop {r6, r7}
|
|
80004f4: 46b9 mov r9, r7
|
|
80004f6: 46b0 mov r8, r6
|
|
80004f8: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
80004fa: 46c0 nop @ (mov r8, r8)
|
|
|
|
080004fc <__divdi3>:
|
|
80004fc: b5f0 push {r4, r5, r6, r7, lr}
|
|
80004fe: 4645 mov r5, r8
|
|
8000500: 46de mov lr, fp
|
|
8000502: 4657 mov r7, sl
|
|
8000504: 464e mov r6, r9
|
|
8000506: b5e0 push {r5, r6, r7, lr}
|
|
8000508: b083 sub sp, #12
|
|
800050a: 9200 str r2, [sp, #0]
|
|
800050c: 9301 str r3, [sp, #4]
|
|
800050e: 000d movs r5, r1
|
|
8000510: 9900 ldr r1, [sp, #0]
|
|
8000512: 9a01 ldr r2, [sp, #4]
|
|
8000514: 0004 movs r4, r0
|
|
8000516: 2d00 cmp r5, #0
|
|
8000518: db61 blt.n 80005de <__divdi3+0xe2>
|
|
800051a: 0006 movs r6, r0
|
|
800051c: 002f movs r7, r5
|
|
800051e: 2a00 cmp r2, #0
|
|
8000520: db0c blt.n 800053c <__divdi3+0x40>
|
|
8000522: 9c00 ldr r4, [sp, #0]
|
|
8000524: 9d01 ldr r5, [sp, #4]
|
|
8000526: 42bd cmp r5, r7
|
|
8000528: d91a bls.n 8000560 <__divdi3+0x64>
|
|
800052a: 2000 movs r0, #0
|
|
800052c: 2100 movs r1, #0
|
|
800052e: b003 add sp, #12
|
|
8000530: bcf0 pop {r4, r5, r6, r7}
|
|
8000532: 46bb mov fp, r7
|
|
8000534: 46b2 mov sl, r6
|
|
8000536: 46a9 mov r9, r5
|
|
8000538: 46a0 mov r8, r4
|
|
800053a: bdf0 pop {r4, r5, r6, r7, pc}
|
|
800053c: 2500 movs r5, #0
|
|
800053e: 424c negs r4, r1
|
|
8000540: 4195 sbcs r5, r2
|
|
8000542: 42bd cmp r5, r7
|
|
8000544: d8f1 bhi.n 800052a <__divdi3+0x2e>
|
|
8000546: d100 bne.n 800054a <__divdi3+0x4e>
|
|
8000548: e0ae b.n 80006a8 <__divdi3+0x1ac>
|
|
800054a: 2301 movs r3, #1
|
|
800054c: 425b negs r3, r3
|
|
800054e: 4699 mov r9, r3
|
|
8000550: e00b b.n 800056a <__divdi3+0x6e>
|
|
8000552: 9a00 ldr r2, [sp, #0]
|
|
8000554: 9b01 ldr r3, [sp, #4]
|
|
8000556: 2500 movs r5, #0
|
|
8000558: 4254 negs r4, r2
|
|
800055a: 419d sbcs r5, r3
|
|
800055c: 42bd cmp r5, r7
|
|
800055e: d8e4 bhi.n 800052a <__divdi3+0x2e>
|
|
8000560: 42bd cmp r5, r7
|
|
8000562: d100 bne.n 8000566 <__divdi3+0x6a>
|
|
8000564: e09c b.n 80006a0 <__divdi3+0x1a4>
|
|
8000566: 2300 movs r3, #0
|
|
8000568: 4699 mov r9, r3
|
|
800056a: 0029 movs r1, r5
|
|
800056c: 0020 movs r0, r4
|
|
800056e: f000 f8c3 bl 80006f8 <__clzdi2>
|
|
8000572: 4680 mov r8, r0
|
|
8000574: 0039 movs r1, r7
|
|
8000576: 0030 movs r0, r6
|
|
8000578: f000 f8be bl 80006f8 <__clzdi2>
|
|
800057c: 4643 mov r3, r8
|
|
800057e: 1a1b subs r3, r3, r0
|
|
8000580: 4698 mov r8, r3
|
|
8000582: 3b20 subs r3, #32
|
|
8000584: d500 bpl.n 8000588 <__divdi3+0x8c>
|
|
8000586: e080 b.n 800068a <__divdi3+0x18e>
|
|
8000588: 0021 movs r1, r4
|
|
800058a: 4099 lsls r1, r3
|
|
800058c: 469a mov sl, r3
|
|
800058e: 000b movs r3, r1
|
|
8000590: 0021 movs r1, r4
|
|
8000592: 4640 mov r0, r8
|
|
8000594: 4081 lsls r1, r0
|
|
8000596: 000a movs r2, r1
|
|
8000598: 42bb cmp r3, r7
|
|
800059a: d82d bhi.n 80005f8 <__divdi3+0xfc>
|
|
800059c: d02a beq.n 80005f4 <__divdi3+0xf8>
|
|
800059e: 4651 mov r1, sl
|
|
80005a0: 1ab6 subs r6, r6, r2
|
|
80005a2: 419f sbcs r7, r3
|
|
80005a4: 2900 cmp r1, #0
|
|
80005a6: da00 bge.n 80005aa <__divdi3+0xae>
|
|
80005a8: e09b b.n 80006e2 <__divdi3+0x1e6>
|
|
80005aa: 2100 movs r1, #0
|
|
80005ac: 2000 movs r0, #0
|
|
80005ae: 2401 movs r4, #1
|
|
80005b0: 9000 str r0, [sp, #0]
|
|
80005b2: 9101 str r1, [sp, #4]
|
|
80005b4: 4651 mov r1, sl
|
|
80005b6: 408c lsls r4, r1
|
|
80005b8: 9401 str r4, [sp, #4]
|
|
80005ba: 2401 movs r4, #1
|
|
80005bc: 4645 mov r5, r8
|
|
80005be: 40ac lsls r4, r5
|
|
80005c0: 9400 str r4, [sp, #0]
|
|
80005c2: 4644 mov r4, r8
|
|
80005c4: 2c00 cmp r4, #0
|
|
80005c6: d11e bne.n 8000606 <__divdi3+0x10a>
|
|
80005c8: 9800 ldr r0, [sp, #0]
|
|
80005ca: 9901 ldr r1, [sp, #4]
|
|
80005cc: 464b mov r3, r9
|
|
80005ce: 2b00 cmp r3, #0
|
|
80005d0: d0ad beq.n 800052e <__divdi3+0x32>
|
|
80005d2: 0003 movs r3, r0
|
|
80005d4: 000c movs r4, r1
|
|
80005d6: 2100 movs r1, #0
|
|
80005d8: 4258 negs r0, r3
|
|
80005da: 41a1 sbcs r1, r4
|
|
80005dc: e7a7 b.n 800052e <__divdi3+0x32>
|
|
80005de: 2700 movs r7, #0
|
|
80005e0: 4266 negs r6, r4
|
|
80005e2: 41af sbcs r7, r5
|
|
80005e4: 2a00 cmp r2, #0
|
|
80005e6: dbb4 blt.n 8000552 <__divdi3+0x56>
|
|
80005e8: 9c00 ldr r4, [sp, #0]
|
|
80005ea: 9d01 ldr r5, [sp, #4]
|
|
80005ec: 42bd cmp r5, r7
|
|
80005ee: d89c bhi.n 800052a <__divdi3+0x2e>
|
|
80005f0: d1ab bne.n 800054a <__divdi3+0x4e>
|
|
80005f2: e059 b.n 80006a8 <__divdi3+0x1ac>
|
|
80005f4: 42b1 cmp r1, r6
|
|
80005f6: d9d2 bls.n 800059e <__divdi3+0xa2>
|
|
80005f8: 2000 movs r0, #0
|
|
80005fa: 2100 movs r1, #0
|
|
80005fc: 4644 mov r4, r8
|
|
80005fe: 9000 str r0, [sp, #0]
|
|
8000600: 9101 str r1, [sp, #4]
|
|
8000602: 2c00 cmp r4, #0
|
|
8000604: d0e0 beq.n 80005c8 <__divdi3+0xcc>
|
|
8000606: 07dc lsls r4, r3, #31
|
|
8000608: 46a4 mov ip, r4
|
|
800060a: 4661 mov r1, ip
|
|
800060c: 0854 lsrs r4, r2, #1
|
|
800060e: 46c4 mov ip, r8
|
|
8000610: 430c orrs r4, r1
|
|
8000612: 085d lsrs r5, r3, #1
|
|
8000614: e014 b.n 8000640 <__divdi3+0x144>
|
|
8000616: 42bd cmp r5, r7
|
|
8000618: d101 bne.n 800061e <__divdi3+0x122>
|
|
800061a: 42b4 cmp r4, r6
|
|
800061c: d812 bhi.n 8000644 <__divdi3+0x148>
|
|
800061e: 0032 movs r2, r6
|
|
8000620: 003b movs r3, r7
|
|
8000622: 1b12 subs r2, r2, r4
|
|
8000624: 41ab sbcs r3, r5
|
|
8000626: 2601 movs r6, #1
|
|
8000628: 1892 adds r2, r2, r2
|
|
800062a: 415b adcs r3, r3
|
|
800062c: 2700 movs r7, #0
|
|
800062e: 18b6 adds r6, r6, r2
|
|
8000630: 415f adcs r7, r3
|
|
8000632: 2301 movs r3, #1
|
|
8000634: 425b negs r3, r3
|
|
8000636: 469b mov fp, r3
|
|
8000638: 44dc add ip, fp
|
|
800063a: 4663 mov r3, ip
|
|
800063c: 2b00 cmp r3, #0
|
|
800063e: d00a beq.n 8000656 <__divdi3+0x15a>
|
|
8000640: 42bd cmp r5, r7
|
|
8000642: d9e8 bls.n 8000616 <__divdi3+0x11a>
|
|
8000644: 2301 movs r3, #1
|
|
8000646: 425b negs r3, r3
|
|
8000648: 469b mov fp, r3
|
|
800064a: 44dc add ip, fp
|
|
800064c: 4663 mov r3, ip
|
|
800064e: 19b6 adds r6, r6, r6
|
|
8000650: 417f adcs r7, r7
|
|
8000652: 2b00 cmp r3, #0
|
|
8000654: d1f4 bne.n 8000640 <__divdi3+0x144>
|
|
8000656: 9a00 ldr r2, [sp, #0]
|
|
8000658: 9b01 ldr r3, [sp, #4]
|
|
800065a: 4651 mov r1, sl
|
|
800065c: 1992 adds r2, r2, r6
|
|
800065e: 417b adcs r3, r7
|
|
8000660: 2900 cmp r1, #0
|
|
8000662: db25 blt.n 80006b0 <__divdi3+0x1b4>
|
|
8000664: 003c movs r4, r7
|
|
8000666: 003d movs r5, r7
|
|
8000668: 40cc lsrs r4, r1
|
|
800066a: 4641 mov r1, r8
|
|
800066c: 40cd lsrs r5, r1
|
|
800066e: 4651 mov r1, sl
|
|
8000670: 2900 cmp r1, #0
|
|
8000672: db2d blt.n 80006d0 <__divdi3+0x1d4>
|
|
8000674: 0025 movs r5, r4
|
|
8000676: 408d lsls r5, r1
|
|
8000678: 0029 movs r1, r5
|
|
800067a: 4645 mov r5, r8
|
|
800067c: 40ac lsls r4, r5
|
|
800067e: 0020 movs r0, r4
|
|
8000680: 1a12 subs r2, r2, r0
|
|
8000682: 418b sbcs r3, r1
|
|
8000684: 9200 str r2, [sp, #0]
|
|
8000686: 9301 str r3, [sp, #4]
|
|
8000688: e79e b.n 80005c8 <__divdi3+0xcc>
|
|
800068a: 4642 mov r2, r8
|
|
800068c: 0028 movs r0, r5
|
|
800068e: 469a mov sl, r3
|
|
8000690: 2320 movs r3, #32
|
|
8000692: 0021 movs r1, r4
|
|
8000694: 4090 lsls r0, r2
|
|
8000696: 1a9b subs r3, r3, r2
|
|
8000698: 40d9 lsrs r1, r3
|
|
800069a: 0003 movs r3, r0
|
|
800069c: 430b orrs r3, r1
|
|
800069e: e777 b.n 8000590 <__divdi3+0x94>
|
|
80006a0: 42b4 cmp r4, r6
|
|
80006a2: d900 bls.n 80006a6 <__divdi3+0x1aa>
|
|
80006a4: e741 b.n 800052a <__divdi3+0x2e>
|
|
80006a6: e75e b.n 8000566 <__divdi3+0x6a>
|
|
80006a8: 42b4 cmp r4, r6
|
|
80006aa: d800 bhi.n 80006ae <__divdi3+0x1b2>
|
|
80006ac: e74d b.n 800054a <__divdi3+0x4e>
|
|
80006ae: e73c b.n 800052a <__divdi3+0x2e>
|
|
80006b0: 4640 mov r0, r8
|
|
80006b2: 2120 movs r1, #32
|
|
80006b4: 1a09 subs r1, r1, r0
|
|
80006b6: 0038 movs r0, r7
|
|
80006b8: 4088 lsls r0, r1
|
|
80006ba: 0034 movs r4, r6
|
|
80006bc: 0001 movs r1, r0
|
|
80006be: 4640 mov r0, r8
|
|
80006c0: 40c4 lsrs r4, r0
|
|
80006c2: 003d movs r5, r7
|
|
80006c4: 430c orrs r4, r1
|
|
80006c6: 4641 mov r1, r8
|
|
80006c8: 40cd lsrs r5, r1
|
|
80006ca: 4651 mov r1, sl
|
|
80006cc: 2900 cmp r1, #0
|
|
80006ce: dad1 bge.n 8000674 <__divdi3+0x178>
|
|
80006d0: 4640 mov r0, r8
|
|
80006d2: 2120 movs r1, #32
|
|
80006d4: 0026 movs r6, r4
|
|
80006d6: 4085 lsls r5, r0
|
|
80006d8: 1a09 subs r1, r1, r0
|
|
80006da: 40ce lsrs r6, r1
|
|
80006dc: 0029 movs r1, r5
|
|
80006de: 4331 orrs r1, r6
|
|
80006e0: e7cb b.n 800067a <__divdi3+0x17e>
|
|
80006e2: 4641 mov r1, r8
|
|
80006e4: 2420 movs r4, #32
|
|
80006e6: 2501 movs r5, #1
|
|
80006e8: 1a64 subs r4, r4, r1
|
|
80006ea: 2000 movs r0, #0
|
|
80006ec: 2100 movs r1, #0
|
|
80006ee: 40e5 lsrs r5, r4
|
|
80006f0: 9000 str r0, [sp, #0]
|
|
80006f2: 9101 str r1, [sp, #4]
|
|
80006f4: 9501 str r5, [sp, #4]
|
|
80006f6: e760 b.n 80005ba <__divdi3+0xbe>
|
|
|
|
080006f8 <__clzdi2>:
|
|
80006f8: b510 push {r4, lr}
|
|
80006fa: 2900 cmp r1, #0
|
|
80006fc: d103 bne.n 8000706 <__clzdi2+0xe>
|
|
80006fe: f000 f807 bl 8000710 <__clzsi2>
|
|
8000702: 3020 adds r0, #32
|
|
8000704: e002 b.n 800070c <__clzdi2+0x14>
|
|
8000706: 0008 movs r0, r1
|
|
8000708: f000 f802 bl 8000710 <__clzsi2>
|
|
800070c: bd10 pop {r4, pc}
|
|
800070e: 46c0 nop @ (mov r8, r8)
|
|
|
|
08000710 <__clzsi2>:
|
|
8000710: 211c movs r1, #28
|
|
8000712: 2301 movs r3, #1
|
|
8000714: 041b lsls r3, r3, #16
|
|
8000716: 4298 cmp r0, r3
|
|
8000718: d301 bcc.n 800071e <__clzsi2+0xe>
|
|
800071a: 0c00 lsrs r0, r0, #16
|
|
800071c: 3910 subs r1, #16
|
|
800071e: 0a1b lsrs r3, r3, #8
|
|
8000720: 4298 cmp r0, r3
|
|
8000722: d301 bcc.n 8000728 <__clzsi2+0x18>
|
|
8000724: 0a00 lsrs r0, r0, #8
|
|
8000726: 3908 subs r1, #8
|
|
8000728: 091b lsrs r3, r3, #4
|
|
800072a: 4298 cmp r0, r3
|
|
800072c: d301 bcc.n 8000732 <__clzsi2+0x22>
|
|
800072e: 0900 lsrs r0, r0, #4
|
|
8000730: 3904 subs r1, #4
|
|
8000732: a202 add r2, pc, #8 @ (adr r2, 800073c <__clzsi2+0x2c>)
|
|
8000734: 5c10 ldrb r0, [r2, r0]
|
|
8000736: 1840 adds r0, r0, r1
|
|
8000738: 4770 bx lr
|
|
800073a: 46c0 nop @ (mov r8, r8)
|
|
800073c: 02020304 .word 0x02020304
|
|
8000740: 01010101 .word 0x01010101
|
|
...
|
|
|
|
0800074c <CRC8_107_add>:
|
|
|
|
#include "crc.h"
|
|
|
|
void CRC8_107_add(CRC8_107 *ctx, uint8_t data)
|
|
{
|
|
ctx->crc ^= ((uint32_t)data << 8);
|
|
800074c: 6803 ldr r3, [r0, #0]
|
|
for (size_t bit_n = 0; bit_n < 8; bit_n++) {
|
|
if (ctx->crc & 0x8000u) {
|
|
800074e: 2280 movs r2, #128 @ 0x80
|
|
ctx->crc ^= ((uint32_t)data << 8);
|
|
8000750: 0209 lsls r1, r1, #8
|
|
8000752: 4059 eors r1, r3
|
|
8000754: 2308 movs r3, #8
|
|
{
|
|
8000756: b510 push {r4, lr}
|
|
ctx->crc ^= ((uint32_t)0x1070u << 3); // same as 0x8380
|
|
8000758: 4c05 ldr r4, [pc, #20] @ (8000770 <CRC8_107_add+0x24>)
|
|
if (ctx->crc & 0x8000u) {
|
|
800075a: 0212 lsls r2, r2, #8
|
|
800075c: 4211 tst r1, r2
|
|
800075e: d000 beq.n 8000762 <CRC8_107_add+0x16>
|
|
ctx->crc ^= ((uint32_t)0x1070u << 3); // same as 0x8380
|
|
8000760: 4061 eors r1, r4
|
|
for (size_t bit_n = 0; bit_n < 8; bit_n++) {
|
|
8000762: 3b01 subs r3, #1
|
|
}
|
|
ctx->crc <<= 1;
|
|
8000764: 0049 lsls r1, r1, #1
|
|
for (size_t bit_n = 0; bit_n < 8; bit_n++) {
|
|
8000766: 2b00 cmp r3, #0
|
|
8000768: d1f8 bne.n 800075c <CRC8_107_add+0x10>
|
|
}
|
|
}
|
|
800076a: 6001 str r1, [r0, #0]
|
|
800076c: bd10 pop {r4, pc}
|
|
800076e: 46c0 nop @ (mov r8, r8)
|
|
8000770: 00008380 .word 0x00008380
|
|
|
|
08000774 <CRC8_107_getChecksum>:
|
|
|
|
uint8_t CRC8_107_getChecksum(const CRC8_107 *ctx)
|
|
{
|
|
return (uint8_t)(ctx->crc >> 8);
|
|
8000774: 6800 ldr r0, [r0, #0]
|
|
8000776: 0a00 lsrs r0, r0, #8
|
|
8000778: b2c0 uxtb r0, r0
|
|
}
|
|
800077a: 4770 bx lr
|
|
|
|
0800077c <SystemClock_Config>:
|
|
/**
|
|
* @brief System Clock Configuration
|
|
* @retval None
|
|
*/
|
|
void SystemClock_Config(void)
|
|
{
|
|
800077c: b570 push {r4, r5, r6, lr}
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
|
|
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1);
|
|
800077e: 2607 movs r6, #7
|
|
8000780: 2501 movs r5, #1
|
|
{
|
|
8000782: b08c sub sp, #48 @ 0x30
|
|
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
|
|
8000784: 2218 movs r2, #24
|
|
8000786: 2100 movs r1, #0
|
|
8000788: a806 add r0, sp, #24
|
|
800078a: f004 fd79 bl 8005280 <memset>
|
|
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
|
|
800078e: 2214 movs r2, #20
|
|
8000790: 2100 movs r1, #0
|
|
8000792: 4668 mov r0, sp
|
|
8000794: f004 fd74 bl 8005280 <memset>
|
|
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1);
|
|
8000798: 4a11 ldr r2, [pc, #68] @ (80007e0 <SystemClock_Config+0x64>)
|
|
*/
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
|
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
800079a: a805 add r0, sp, #20
|
|
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1);
|
|
800079c: 6813 ldr r3, [r2, #0]
|
|
800079e: 43b3 bics r3, r6
|
|
80007a0: 432b orrs r3, r5
|
|
80007a2: 6013 str r3, [r2, #0]
|
|
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
|
|
80007a4: 2302 movs r3, #2
|
|
80007a6: 9305 str r3, [sp, #20]
|
|
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
|
|
80007a8: 33fe adds r3, #254 @ 0xfe
|
|
80007aa: 9308 str r3, [sp, #32]
|
|
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
|
|
80007ac: 2300 movs r3, #0
|
|
80007ae: 9309 str r3, [sp, #36] @ 0x24
|
|
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
|
|
80007b0: 3340 adds r3, #64 @ 0x40
|
|
80007b2: 930a str r3, [sp, #40] @ 0x28
|
|
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
|
|
80007b4: f002 fde4 bl 8003380 <HAL_RCC_OscConfig>
|
|
80007b8: 2800 cmp r0, #0
|
|
80007ba: d001 beq.n 80007c0 <SystemClock_Config+0x44>
|
|
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
|
|
Can only be executed in Privileged modes.
|
|
*/
|
|
__STATIC_FORCEINLINE void __disable_irq(void)
|
|
{
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
80007bc: b672 cpsid i
|
|
void Error_Handler(void)
|
|
{
|
|
/* USER CODE BEGIN Error_Handler_Debug */
|
|
/* User can add his own implementation to report the HAL error return state */
|
|
__disable_irq();
|
|
while (1)
|
|
80007be: e7fe b.n 80007be <SystemClock_Config+0x42>
|
|
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
|
|
80007c0: 9001 str r0, [sp, #4]
|
|
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
|
|
80007c2: 9002 str r0, [sp, #8]
|
|
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
|
|
80007c4: 9003 str r0, [sp, #12]
|
|
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
|
|
80007c6: 9004 str r0, [sp, #16]
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
|
|
80007c8: 0029 movs r1, r5
|
|
80007ca: 4668 mov r0, sp
|
|
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
|
|
80007cc: 9600 str r6, [sp, #0]
|
|
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
|
|
80007ce: f002 ff3b bl 8003648 <HAL_RCC_ClockConfig>
|
|
80007d2: 2800 cmp r0, #0
|
|
80007d4: d001 beq.n 80007da <SystemClock_Config+0x5e>
|
|
80007d6: b672 cpsid i
|
|
while (1)
|
|
80007d8: e7fe b.n 80007d8 <SystemClock_Config+0x5c>
|
|
}
|
|
80007da: b00c add sp, #48 @ 0x30
|
|
80007dc: bd70 pop {r4, r5, r6, pc}
|
|
80007de: 46c0 nop @ (mov r8, r8)
|
|
80007e0: 40022000 .word 0x40022000
|
|
|
|
080007e4 <HAL_TIM_PeriodElapsedCallback>:
|
|
{
|
|
80007e4: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
if (htim == &htim14) // encoder check timer (runs at 20khz)
|
|
80007e6: 4b53 ldr r3, [pc, #332] @ (8000934 <HAL_TIM_PeriodElapsedCallback+0x150>)
|
|
80007e8: 4c53 ldr r4, [pc, #332] @ (8000938 <HAL_TIM_PeriodElapsedCallback+0x154>)
|
|
80007ea: 4298 cmp r0, r3
|
|
80007ec: d000 beq.n 80007f0 <HAL_TIM_PeriodElapsedCallback+0xc>
|
|
80007ee: e093 b.n 8000918 <HAL_TIM_PeriodElapsedCallback+0x134>
|
|
uint16_t count = htim3.Instance->CNT;
|
|
80007f0: 4b52 ldr r3, [pc, #328] @ (800093c <HAL_TIM_PeriodElapsedCallback+0x158>)
|
|
if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
|
|
80007f2: 4d53 ldr r5, [pc, #332] @ (8000940 <HAL_TIM_PeriodElapsedCallback+0x15c>)
|
|
uint16_t count = htim3.Instance->CNT;
|
|
80007f4: 681b ldr r3, [r3, #0]
|
|
80007f6: 27fa movs r7, #250 @ 0xfa
|
|
80007f8: 6a59 ldr r1, [r3, #36] @ 0x24
|
|
if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
|
|
80007fa: 882b ldrh r3, [r5, #0]
|
|
encoder_count_extra ++;
|
|
80007fc: 4851 ldr r0, [pc, #324] @ (8000944 <HAL_TIM_PeriodElapsedCallback+0x160>)
|
|
if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
|
|
80007fe: 469c mov ip, r3
|
|
8000800: 4e51 ldr r6, [pc, #324] @ (8000948 <HAL_TIM_PeriodElapsedCallback+0x164>)
|
|
encoder_count_extra ++;
|
|
8000802: 6803 ldr r3, [r0, #0]
|
|
uint16_t count = htim3.Instance->CNT;
|
|
8000804: b28a uxth r2, r1
|
|
if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
|
|
8000806: 00bf lsls r7, r7, #2
|
|
8000808: 45b4 cmp ip, r6
|
|
800080a: d958 bls.n 80008be <HAL_TIM_PeriodElapsedCallback+0xda>
|
|
encoder_count_extra ++;
|
|
800080c: 3301 adds r3, #1
|
|
if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
|
|
800080e: 42ba cmp r2, r7
|
|
8000810: d35a bcc.n 80008c8 <HAL_TIM_PeriodElapsedCallback+0xe4>
|
|
if (total_count > POSITION_OVERFLOW_THRESHOLD)
|
|
8000812: 2780 movs r7, #128 @ 0x80
|
|
encoder_previous = count; // update previous for next cycle
|
|
8000814: 802a strh r2, [r5, #0]
|
|
total_count = (encoder_count_extra * 65536) + count;
|
|
8000816: 4d4b ldr r5, [pc, #300] @ (8000944 <HAL_TIM_PeriodElapsedCallback+0x160>)
|
|
8000818: b289 uxth r1, r1
|
|
800081a: 682a ldr r2, [r5, #0]
|
|
800081c: 4e4b ldr r6, [pc, #300] @ (800094c <HAL_TIM_PeriodElapsedCallback+0x168>)
|
|
800081e: 0413 lsls r3, r2, #16
|
|
8000820: 185b adds r3, r3, r1
|
|
target_count -= adjustment;
|
|
8000822: 494b ldr r1, [pc, #300] @ (8000950 <HAL_TIM_PeriodElapsedCallback+0x16c>)
|
|
total_count = (encoder_count_extra * 65536) + count;
|
|
8000824: 6033 str r3, [r6, #0]
|
|
target_count -= adjustment;
|
|
8000826: 6808 ldr r0, [r1, #0]
|
|
if (total_count > POSITION_OVERFLOW_THRESHOLD)
|
|
8000828: 05ff lsls r7, r7, #23
|
|
800082a: 42bb cmp r3, r7
|
|
800082c: db4e blt.n 80008cc <HAL_TIM_PeriodElapsedCallback+0xe8>
|
|
total_count -= adjustment;
|
|
800082e: 4f49 ldr r7, [pc, #292] @ (8000954 <HAL_TIM_PeriodElapsedCallback+0x170>)
|
|
8000830: 19db adds r3, r3, r7
|
|
8000832: 6033 str r3, [r6, #0]
|
|
feed_target_position -= adjustment;
|
|
8000834: 4e48 ldr r6, [pc, #288] @ (8000958 <HAL_TIM_PeriodElapsedCallback+0x174>)
|
|
target_count -= adjustment;
|
|
8000836: 19c0 adds r0, r0, r7
|
|
8000838: 6008 str r0, [r1, #0]
|
|
feed_target_position -= adjustment;
|
|
800083a: 6830 ldr r0, [r6, #0]
|
|
800083c: 19c0 adds r0, r0, r7
|
|
800083e: 6030 str r0, [r6, #0]
|
|
encoder_count_extra -= (adjustment / 65536);
|
|
8000840: 4846 ldr r0, [pc, #280] @ (800095c <HAL_TIM_PeriodElapsedCallback+0x178>)
|
|
encoder_count_extra += (adjustment / 65536);
|
|
8000842: 1812 adds r2, r2, r0
|
|
mm_position = 0;
|
|
8000844: 2000 movs r0, #0
|
|
encoder_count_extra += (adjustment / 65536);
|
|
8000846: 602a str r2, [r5, #0]
|
|
mm_position = 0;
|
|
8000848: 4a45 ldr r2, [pc, #276] @ (8000960 <HAL_TIM_PeriodElapsedCallback+0x17c>)
|
|
800084a: 6010 str r0, [r2, #0]
|
|
if (pid_add!=0)
|
|
800084c: 4845 ldr r0, [pc, #276] @ (8000964 <HAL_TIM_PeriodElapsedCallback+0x180>)
|
|
800084e: 6802 ldr r2, [r0, #0]
|
|
8000850: 2a00 cmp r2, #0
|
|
8000852: d004 beq.n 800085e <HAL_TIM_PeriodElapsedCallback+0x7a>
|
|
int64_t temp = target_count + pid_add;
|
|
8000854: 680d ldr r5, [r1, #0]
|
|
8000856: 1952 adds r2, r2, r5
|
|
pid_add = 0;
|
|
8000858: 2500 movs r5, #0
|
|
target_count = temp;
|
|
800085a: 600a str r2, [r1, #0]
|
|
pid_add = 0;
|
|
800085c: 6005 str r5, [r0, #0]
|
|
vel_counter++;
|
|
800085e: 4842 ldr r0, [pc, #264] @ (8000968 <HAL_TIM_PeriodElapsedCallback+0x184>)
|
|
8000860: 7802 ldrb r2, [r0, #0]
|
|
8000862: 3201 adds r2, #1
|
|
8000864: b2d2 uxtb r2, r2
|
|
8000866: 7002 strb r2, [r0, #0]
|
|
if (vel_counter >= 20)
|
|
8000868: 2a13 cmp r2, #19
|
|
800086a: d907 bls.n 800087c <HAL_TIM_PeriodElapsedCallback+0x98>
|
|
velocity = total_count - vel_prev_pos;
|
|
800086c: 4d3f ldr r5, [pc, #252] @ (800096c <HAL_TIM_PeriodElapsedCallback+0x188>)
|
|
800086e: 4e40 ldr r6, [pc, #256] @ (8000970 <HAL_TIM_PeriodElapsedCallback+0x18c>)
|
|
8000870: 682a ldr r2, [r5, #0]
|
|
vel_prev_pos = total_count;
|
|
8000872: 602b str r3, [r5, #0]
|
|
velocity = total_count - vel_prev_pos;
|
|
8000874: 1a9a subs r2, r3, r2
|
|
8000876: 6032 str r2, [r6, #0]
|
|
vel_counter = 0;
|
|
8000878: 2200 movs r2, #0
|
|
800087a: 7002 strb r2, [r0, #0]
|
|
if (total_count != last_moved_pos)
|
|
800087c: 4a3d ldr r2, [pc, #244] @ (8000974 <HAL_TIM_PeriodElapsedCallback+0x190>)
|
|
800087e: 483e ldr r0, [pc, #248] @ (8000978 <HAL_TIM_PeriodElapsedCallback+0x194>)
|
|
8000880: 6815 ldr r5, [r2, #0]
|
|
8000882: 429d cmp r5, r3
|
|
8000884: d031 beq.n 80008ea <HAL_TIM_PeriodElapsedCallback+0x106>
|
|
last_moved_pos = total_count;
|
|
8000886: 6013 str r3, [r2, #0]
|
|
still_counter = 0;
|
|
8000888: 2200 movs r2, #0
|
|
still_counter++;
|
|
800088a: 8002 strh r2, [r0, #0]
|
|
int32_t error = target_count - total_count;
|
|
800088c: 680d ldr r5, [r1, #0]
|
|
htim1.Instance->CCR1 = PWM;
|
|
800088e: 6824 ldr r4, [r4, #0]
|
|
int32_t error = target_count - total_count;
|
|
8000890: 1aed subs r5, r5, r3
|
|
int32_t brake_distance = velocity * brake_time_tenths / 10;
|
|
8000892: 4b3a ldr r3, [pc, #232] @ (800097c <HAL_TIM_PeriodElapsedCallback+0x198>)
|
|
8000894: 4e3a ldr r6, [pc, #232] @ (8000980 <HAL_TIM_PeriodElapsedCallback+0x19c>)
|
|
8000896: 681b ldr r3, [r3, #0]
|
|
if (error >= FEED_POSITION_TOLERANCE && (is_stopped || error > brake_distance))
|
|
8000898: 2d0e cmp r5, #14
|
|
800089a: dd2e ble.n 80008fa <HAL_TIM_PeriodElapsedCallback+0x116>
|
|
800089c: 2a28 cmp r2, #40 @ 0x28
|
|
800089e: d807 bhi.n 80008b0 <HAL_TIM_PeriodElapsedCallback+0xcc>
|
|
int32_t brake_distance = velocity * brake_time_tenths / 10;
|
|
80008a0: 4a33 ldr r2, [pc, #204] @ (8000970 <HAL_TIM_PeriodElapsedCallback+0x18c>)
|
|
80008a2: 210a movs r1, #10
|
|
80008a4: 6810 ldr r0, [r2, #0]
|
|
80008a6: 4358 muls r0, r3
|
|
80008a8: f7ff fccc bl 8000244 <__divsi3>
|
|
if (error >= FEED_POSITION_TOLERANCE && (is_stopped || error > brake_distance))
|
|
80008ac: 4285 cmp r5, r0
|
|
80008ae: dd2d ble.n 800090c <HAL_TIM_PeriodElapsedCallback+0x128>
|
|
htim1.Instance->CCR1 = PWM;
|
|
80008b0: 2396 movs r3, #150 @ 0x96
|
|
htim1.Instance->CCR2 = 0;
|
|
80008b2: 2200 movs r2, #0
|
|
htim1.Instance->CCR1 = PWM;
|
|
80008b4: 011b lsls r3, r3, #4
|
|
80008b6: 6363 str r3, [r4, #52] @ 0x34
|
|
htim1.Instance->CCR2 = 0;
|
|
80008b8: 63a2 str r2, [r4, #56] @ 0x38
|
|
debug_pid_output = -PWM_MAX;
|
|
80008ba: 8033 strh r3, [r6, #0]
|
|
}
|
|
80008bc: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
else if ((encoder_previous < CNT_LIMIT_ZONE) && (count > CNT_MAX-CNT_LIMIT_ZONE)) // negative turnaround
|
|
80008be: 45bc cmp ip, r7
|
|
80008c0: d2a7 bcs.n 8000812 <HAL_TIM_PeriodElapsedCallback+0x2e>
|
|
80008c2: 42b2 cmp r2, r6
|
|
80008c4: d9a5 bls.n 8000812 <HAL_TIM_PeriodElapsedCallback+0x2e>
|
|
encoder_count_extra --;
|
|
80008c6: 3b01 subs r3, #1
|
|
80008c8: 6003 str r3, [r0, #0]
|
|
80008ca: e7a2 b.n 8000812 <HAL_TIM_PeriodElapsedCallback+0x2e>
|
|
else if (total_count < -POSITION_OVERFLOW_THRESHOLD)
|
|
80008cc: 27c0 movs r7, #192 @ 0xc0
|
|
80008ce: 063f lsls r7, r7, #24
|
|
80008d0: 42bb cmp r3, r7
|
|
80008d2: dcbb bgt.n 800084c <HAL_TIM_PeriodElapsedCallback+0x68>
|
|
total_count += adjustment;
|
|
80008d4: 4f2b ldr r7, [pc, #172] @ (8000984 <HAL_TIM_PeriodElapsedCallback+0x1a0>)
|
|
80008d6: 19db adds r3, r3, r7
|
|
80008d8: 6033 str r3, [r6, #0]
|
|
feed_target_position += adjustment;
|
|
80008da: 4e1f ldr r6, [pc, #124] @ (8000958 <HAL_TIM_PeriodElapsedCallback+0x174>)
|
|
target_count += adjustment;
|
|
80008dc: 19c0 adds r0, r0, r7
|
|
80008de: 6008 str r0, [r1, #0]
|
|
feed_target_position += adjustment;
|
|
80008e0: 6830 ldr r0, [r6, #0]
|
|
80008e2: 19c0 adds r0, r0, r7
|
|
80008e4: 6030 str r0, [r6, #0]
|
|
encoder_count_extra += (adjustment / 65536);
|
|
80008e6: 4828 ldr r0, [pc, #160] @ (8000988 <HAL_TIM_PeriodElapsedCallback+0x1a4>)
|
|
80008e8: e7ab b.n 8000842 <HAL_TIM_PeriodElapsedCallback+0x5e>
|
|
else if (still_counter < 1000)
|
|
80008ea: 25fa movs r5, #250 @ 0xfa
|
|
80008ec: 8802 ldrh r2, [r0, #0]
|
|
80008ee: 00ad lsls r5, r5, #2
|
|
80008f0: 42aa cmp r2, r5
|
|
80008f2: d2cb bcs.n 800088c <HAL_TIM_PeriodElapsedCallback+0xa8>
|
|
still_counter++;
|
|
80008f4: 3201 adds r2, #1
|
|
80008f6: b292 uxth r2, r2
|
|
80008f8: e7c7 b.n 800088a <HAL_TIM_PeriodElapsedCallback+0xa6>
|
|
else if (error < -FEED_POSITION_TOLERANCE)
|
|
80008fa: 350f adds r5, #15
|
|
80008fc: da06 bge.n 800090c <HAL_TIM_PeriodElapsedCallback+0x128>
|
|
htim1.Instance->CCR1 = 0;
|
|
80008fe: 2300 movs r3, #0
|
|
8000900: 6363 str r3, [r4, #52] @ 0x34
|
|
htim1.Instance->CCR2 = PWM;
|
|
8000902: 2396 movs r3, #150 @ 0x96
|
|
8000904: 011b lsls r3, r3, #4
|
|
8000906: 63a3 str r3, [r4, #56] @ 0x38
|
|
debug_pid_output = -PWM_MAX;
|
|
8000908: 4b20 ldr r3, [pc, #128] @ (800098c <HAL_TIM_PeriodElapsedCallback+0x1a8>)
|
|
800090a: e7d6 b.n 80008ba <HAL_TIM_PeriodElapsedCallback+0xd6>
|
|
htim1.Instance->CCR1 = PWM_MAX;
|
|
800090c: 2396 movs r3, #150 @ 0x96
|
|
800090e: 011b lsls r3, r3, #4
|
|
8000910: 6363 str r3, [r4, #52] @ 0x34
|
|
htim1.Instance->CCR2 = PWM_MAX;
|
|
8000912: 63a3 str r3, [r4, #56] @ 0x38
|
|
debug_pid_output = 0;
|
|
8000914: 2300 movs r3, #0
|
|
8000916: e7d0 b.n 80008ba <HAL_TIM_PeriodElapsedCallback+0xd6>
|
|
if (htim == &htim1) return; // PWM timer
|
|
8000918: 42a0 cmp r0, r4
|
|
800091a: d0cf beq.n 80008bc <HAL_TIM_PeriodElapsedCallback+0xd8>
|
|
if (htim == &htim16) //SW1 timer
|
|
800091c: 4b1c ldr r3, [pc, #112] @ (8000990 <HAL_TIM_PeriodElapsedCallback+0x1ac>)
|
|
800091e: 4298 cmp r0, r3
|
|
8000920: d103 bne.n 800092a <HAL_TIM_PeriodElapsedCallback+0x146>
|
|
sw1_pressed = 0;
|
|
8000922: 4b1c ldr r3, [pc, #112] @ (8000994 <HAL_TIM_PeriodElapsedCallback+0x1b0>)
|
|
sw2_pressed = 0;
|
|
8000924: 2200 movs r2, #0
|
|
8000926: 701a strb r2, [r3, #0]
|
|
8000928: e7c8 b.n 80008bc <HAL_TIM_PeriodElapsedCallback+0xd8>
|
|
else if (htim == &htim17) //SW2 timer
|
|
800092a: 4b1b ldr r3, [pc, #108] @ (8000998 <HAL_TIM_PeriodElapsedCallback+0x1b4>)
|
|
800092c: 4298 cmp r0, r3
|
|
800092e: d1c5 bne.n 80008bc <HAL_TIM_PeriodElapsedCallback+0xd8>
|
|
sw2_pressed = 0;
|
|
8000930: 4b1a ldr r3, [pc, #104] @ (800099c <HAL_TIM_PeriodElapsedCallback+0x1b8>)
|
|
8000932: e7f7 b.n 8000924 <HAL_TIM_PeriodElapsedCallback+0x140>
|
|
8000934: 2000121c .word 0x2000121c
|
|
8000938: 200012b4 .word 0x200012b4
|
|
800093c: 20001268 .word 0x20001268
|
|
8000940: 20000f98 .word 0x20000f98
|
|
8000944: 20000f9c .word 0x20000f9c
|
|
8000948: 0000fc17 .word 0x0000fc17
|
|
800094c: 20000158 .word 0x20000158
|
|
8000950: 20000154 .word 0x20000154
|
|
8000954: e0000001 .word 0xe0000001
|
|
8000958: 20000108 .word 0x20000108
|
|
800095c: ffffe001 .word 0xffffe001
|
|
8000960: 200000e8 .word 0x200000e8
|
|
8000964: 20000128 .word 0x20000128
|
|
8000968: 20000060 .word 0x20000060
|
|
800096c: 2000005c .word 0x2000005c
|
|
8000970: 20000058 .word 0x20000058
|
|
8000974: 20000054 .word 0x20000054
|
|
8000978: 20000050 .word 0x20000050
|
|
800097c: 20000008 .word 0x20000008
|
|
8000980: 20000080 .word 0x20000080
|
|
8000984: 1fffffff .word 0x1fffffff
|
|
8000988: 00001fff .word 0x00001fff
|
|
800098c: fffff6a0 .word 0xfffff6a0
|
|
8000990: 200011d0 .word 0x200011d0
|
|
8000994: 20000fa1 .word 0x20000fa1
|
|
8000998: 20001184 .word 0x20001184
|
|
800099c: 20000fa0 .word 0x20000fa0
|
|
|
|
080009a0 <HAL_GPIO_EXTI_Falling_Callback>:
|
|
if(GPIO_Pin == SW1_Pin) // SW1 (lower button)
|
|
80009a0: 2380 movs r3, #128 @ 0x80
|
|
{
|
|
80009a2: b510 push {r4, lr}
|
|
if(GPIO_Pin == SW1_Pin) // SW1 (lower button)
|
|
80009a4: 009b lsls r3, r3, #2
|
|
80009a6: 4298 cmp r0, r3
|
|
80009a8: d105 bne.n 80009b6 <HAL_GPIO_EXTI_Falling_Callback+0x16>
|
|
if (!sw1_pressed)
|
|
80009aa: 4c0b ldr r4, [pc, #44] @ (80009d8 <HAL_GPIO_EXTI_Falling_Callback+0x38>)
|
|
htim16.Instance->CNT = 0;
|
|
80009ac: 480b ldr r0, [pc, #44] @ (80009dc <HAL_GPIO_EXTI_Falling_Callback+0x3c>)
|
|
if (!sw1_pressed)
|
|
80009ae: 7823 ldrb r3, [r4, #0]
|
|
80009b0: 2b00 cmp r3, #0
|
|
80009b2: d009 beq.n 80009c8 <HAL_GPIO_EXTI_Falling_Callback+0x28>
|
|
}
|
|
80009b4: bd10 pop {r4, pc}
|
|
else if (GPIO_Pin == SW2_Pin) // SW2 (upper button)
|
|
80009b6: 2380 movs r3, #128 @ 0x80
|
|
80009b8: 005b lsls r3, r3, #1
|
|
80009ba: 4298 cmp r0, r3
|
|
80009bc: d1fa bne.n 80009b4 <HAL_GPIO_EXTI_Falling_Callback+0x14>
|
|
if (!sw2_pressed)
|
|
80009be: 4c08 ldr r4, [pc, #32] @ (80009e0 <HAL_GPIO_EXTI_Falling_Callback+0x40>)
|
|
80009c0: 7823 ldrb r3, [r4, #0]
|
|
80009c2: 2b00 cmp r3, #0
|
|
80009c4: d1f6 bne.n 80009b4 <HAL_GPIO_EXTI_Falling_Callback+0x14>
|
|
htim17.Instance->CNT = 0;
|
|
80009c6: 4807 ldr r0, [pc, #28] @ (80009e4 <HAL_GPIO_EXTI_Falling_Callback+0x44>)
|
|
80009c8: 6802 ldr r2, [r0, #0]
|
|
80009ca: 6253 str r3, [r2, #36] @ 0x24
|
|
HAL_TIM_Base_Start_IT(&htim17);
|
|
80009cc: f003 f8c6 bl 8003b5c <HAL_TIM_Base_Start_IT>
|
|
sw2_pressed = 1;
|
|
80009d0: 2301 movs r3, #1
|
|
80009d2: 7023 strb r3, [r4, #0]
|
|
}
|
|
80009d4: e7ee b.n 80009b4 <HAL_GPIO_EXTI_Falling_Callback+0x14>
|
|
80009d6: 46c0 nop @ (mov r8, r8)
|
|
80009d8: 20000fa1 .word 0x20000fa1
|
|
80009dc: 200011d0 .word 0x200011d0
|
|
80009e0: 20000fa0 .word 0x20000fa0
|
|
80009e4: 20001184 .word 0x20001184
|
|
|
|
080009e8 <HAL_UARTEx_RxEventCallback>:
|
|
{
|
|
80009e8: b570 push {r4, r5, r6, lr}
|
|
80009ea: 000d movs r5, r1
|
|
if (Size > 64) return; // todo error handling
|
|
80009ec: 2940 cmp r1, #64 @ 0x40
|
|
80009ee: d822 bhi.n 8000a36 <HAL_UARTEx_RxEventCallback+0x4e>
|
|
rx_msg_count++;
|
|
80009f0: 2400 movs r4, #0
|
|
80009f2: 4a13 ldr r2, [pc, #76] @ (8000a40 <HAL_UARTEx_RxEventCallback+0x58>)
|
|
if (msg_buf_empty[i])
|
|
80009f4: 4e13 ldr r6, [pc, #76] @ (8000a44 <HAL_UARTEx_RxEventCallback+0x5c>)
|
|
rx_msg_count++;
|
|
80009f6: 8813 ldrh r3, [r2, #0]
|
|
80009f8: 3301 adds r3, #1
|
|
80009fa: b29b uxth r3, r3
|
|
80009fc: 8013 strh r3, [r2, #0]
|
|
if (msg_buf_empty[i])
|
|
80009fe: 5d33 ldrb r3, [r6, r4]
|
|
8000a00: 2b00 cmp r3, #0
|
|
8000a02: d019 beq.n 8000a38 <HAL_UARTEx_RxEventCallback+0x50>
|
|
memcpy(msg_buf[i], DMA_buffer, Size);
|
|
8000a04: 4b10 ldr r3, [pc, #64] @ (8000a48 <HAL_UARTEx_RxEventCallback+0x60>)
|
|
8000a06: 01a0 lsls r0, r4, #6
|
|
8000a08: 002a movs r2, r5
|
|
8000a0a: 18c0 adds r0, r0, r3
|
|
8000a0c: 490f ldr r1, [pc, #60] @ (8000a4c <HAL_UARTEx_RxEventCallback+0x64>)
|
|
8000a0e: f004 fc63 bl 80052d8 <memcpy>
|
|
msg_buf_size[i] = Size;
|
|
8000a12: 4b0f ldr r3, [pc, #60] @ (8000a50 <HAL_UARTEx_RxEventCallback+0x68>)
|
|
8000a14: b2ed uxtb r5, r5
|
|
8000a16: 551d strb r5, [r3, r4]
|
|
msg_buf_empty[i] = 0;
|
|
8000a18: 2300 movs r3, #0
|
|
8000a1a: 5533 strb r3, [r6, r4]
|
|
HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
|
|
8000a1c: 4c0d ldr r4, [pc, #52] @ (8000a54 <HAL_UARTEx_RxEventCallback+0x6c>)
|
|
8000a1e: 2240 movs r2, #64 @ 0x40
|
|
8000a20: 0020 movs r0, r4
|
|
8000a22: 490a ldr r1, [pc, #40] @ (8000a4c <HAL_UARTEx_RxEventCallback+0x64>)
|
|
8000a24: f004 fbec bl 8005200 <HAL_UARTEx_ReceiveToIdle_DMA>
|
|
__HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT);
|
|
8000a28: 2104 movs r1, #4
|
|
8000a2a: 3404 adds r4, #4
|
|
8000a2c: 6fe3 ldr r3, [r4, #124] @ 0x7c
|
|
8000a2e: 681a ldr r2, [r3, #0]
|
|
8000a30: 6813 ldr r3, [r2, #0]
|
|
8000a32: 438b bics r3, r1
|
|
8000a34: 6013 str r3, [r2, #0]
|
|
}
|
|
8000a36: bd70 pop {r4, r5, r6, pc}
|
|
for (uint8_t i = 0; i < MSG_BUF_COUNT; i++)
|
|
8000a38: 3401 adds r4, #1
|
|
8000a3a: 2c36 cmp r4, #54 @ 0x36
|
|
8000a3c: d1df bne.n 80009fe <HAL_UARTEx_RxEventCallback+0x16>
|
|
8000a3e: e7ed b.n 8000a1c <HAL_UARTEx_RxEventCallback+0x34>
|
|
8000a40: 2000015c .word 0x2000015c
|
|
8000a44: 20000f54 .word 0x20000f54
|
|
8000a48: 2000019e .word 0x2000019e
|
|
8000a4c: 2000015e .word 0x2000015e
|
|
8000a50: 20000f1e .word 0x20000f1e
|
|
8000a54: 2000105c .word 0x2000105c
|
|
|
|
08000a58 <HAL_UART_ErrorCallback>:
|
|
if (huart->Instance == USART2)
|
|
8000a58: 4b0c ldr r3, [pc, #48] @ (8000a8c <HAL_UART_ErrorCallback+0x34>)
|
|
8000a5a: 6802 ldr r2, [r0, #0]
|
|
{
|
|
8000a5c: b510 push {r4, lr}
|
|
if (huart->Instance == USART2)
|
|
8000a5e: 429a cmp r2, r3
|
|
8000a60: d113 bne.n 8000a8a <HAL_UART_ErrorCallback+0x32>
|
|
uart_error_count++;
|
|
8000a62: 490b ldr r1, [pc, #44] @ (8000a90 <HAL_UART_ErrorCallback+0x38>)
|
|
HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
|
|
8000a64: 4c0b ldr r4, [pc, #44] @ (8000a94 <HAL_UART_ErrorCallback+0x3c>)
|
|
uart_error_count++;
|
|
8000a66: 880b ldrh r3, [r1, #0]
|
|
HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
|
|
8000a68: 0020 movs r0, r4
|
|
uart_error_count++;
|
|
8000a6a: 3301 adds r3, #1
|
|
8000a6c: b29b uxth r3, r3
|
|
8000a6e: 800b strh r3, [r1, #0]
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_FEF | UART_CLEAR_NEF | UART_CLEAR_PEF);
|
|
8000a70: 230f movs r3, #15
|
|
HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
|
|
8000a72: 4909 ldr r1, [pc, #36] @ (8000a98 <HAL_UART_ErrorCallback+0x40>)
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_FEF | UART_CLEAR_NEF | UART_CLEAR_PEF);
|
|
8000a74: 6213 str r3, [r2, #32]
|
|
HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
|
|
8000a76: 2240 movs r2, #64 @ 0x40
|
|
8000a78: f004 fbc2 bl 8005200 <HAL_UARTEx_ReceiveToIdle_DMA>
|
|
__HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT);
|
|
8000a7c: 2104 movs r1, #4
|
|
8000a7e: 3404 adds r4, #4
|
|
8000a80: 6fe3 ldr r3, [r4, #124] @ 0x7c
|
|
8000a82: 681a ldr r2, [r3, #0]
|
|
8000a84: 6813 ldr r3, [r2, #0]
|
|
8000a86: 438b bics r3, r1
|
|
8000a88: 6013 str r3, [r2, #0]
|
|
}
|
|
8000a8a: bd10 pop {r4, pc}
|
|
8000a8c: 40004400 .word 0x40004400
|
|
8000a90: 2000007e .word 0x2000007e
|
|
8000a94: 2000105c .word 0x2000105c
|
|
8000a98: 2000015e .word 0x2000015e
|
|
|
|
08000a9c <set_LED>:
|
|
{
|
|
8000a9c: b570 push {r4, r5, r6, lr}
|
|
8000a9e: 000d movs r5, r1
|
|
8000aa0: 0014 movs r4, r2
|
|
if (R) R = GPIO_PIN_SET;
|
|
8000aa2: 1e43 subs r3, r0, #1
|
|
8000aa4: 4198 sbcs r0, r3
|
|
if (G) G = GPIO_PIN_SET;
|
|
8000aa6: 1e6b subs r3, r5, #1
|
|
8000aa8: 419d sbcs r5, r3
|
|
if (B) B = GPIO_PIN_SET;
|
|
8000aaa: 1e63 subs r3, r4, #1
|
|
8000aac: 419c sbcs r4, r3
|
|
HAL_GPIO_WritePin(LED_R_GPIO_Port,LED_R_Pin,R);
|
|
8000aae: b2c2 uxtb r2, r0
|
|
8000ab0: 2108 movs r1, #8
|
|
8000ab2: 4807 ldr r0, [pc, #28] @ (8000ad0 <set_LED+0x34>)
|
|
8000ab4: f002 fc48 bl 8003348 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LED_G_GPIO_Port,LED_G_Pin,G);
|
|
8000ab8: b2ea uxtb r2, r5
|
|
8000aba: 2120 movs r1, #32
|
|
8000abc: 4804 ldr r0, [pc, #16] @ (8000ad0 <set_LED+0x34>)
|
|
8000abe: f002 fc43 bl 8003348 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(LED_B_GPIO_Port,LED_B_Pin,B);
|
|
8000ac2: 2110 movs r1, #16
|
|
8000ac4: 4802 ldr r0, [pc, #8] @ (8000ad0 <set_LED+0x34>)
|
|
8000ac6: b2e2 uxtb r2, r4
|
|
8000ac8: f002 fc3e bl 8003348 <HAL_GPIO_WritePin>
|
|
}
|
|
8000acc: bd70 pop {r4, r5, r6, pc}
|
|
8000ace: 46c0 nop @ (mov r8, r8)
|
|
8000ad0: 50000400 .word 0x50000400
|
|
|
|
08000ad4 <rs485_transmit>:
|
|
{
|
|
8000ad4: b570 push {r4, r5, r6, lr}
|
|
8000ad6: 0005 movs r5, r0
|
|
HAL_Delay(1);
|
|
8000ad8: 2001 movs r0, #1
|
|
{
|
|
8000ada: 000e movs r6, r1
|
|
HAL_Delay(1);
|
|
8000adc: f001 ff1e bl 800291c <HAL_Delay>
|
|
HAL_UART_AbortReceive(&huart2);
|
|
8000ae0: 4c11 ldr r4, [pc, #68] @ (8000b28 <rs485_transmit+0x54>)
|
|
8000ae2: 0020 movs r0, r4
|
|
8000ae4: f003 fd3c bl 8004560 <HAL_UART_AbortReceive>
|
|
HAL_GPIO_WritePin(USART2_NRE_GPIO_Port, USART2_NRE_Pin, GPIO_PIN_SET); // NRE high = receiver off
|
|
8000ae8: 2201 movs r2, #1
|
|
8000aea: 20a0 movs r0, #160 @ 0xa0
|
|
8000aec: 0011 movs r1, r2
|
|
8000aee: 05c0 lsls r0, r0, #23
|
|
8000af0: f002 fc2a bl 8003348 <HAL_GPIO_WritePin>
|
|
HAL_UART_Transmit(&huart2, data, len, 100);
|
|
8000af4: 2364 movs r3, #100 @ 0x64
|
|
8000af6: 0032 movs r2, r6
|
|
8000af8: 0029 movs r1, r5
|
|
8000afa: 0020 movs r0, r4
|
|
8000afc: f004 f955 bl 8004daa <HAL_UART_Transmit>
|
|
HAL_GPIO_WritePin(USART2_NRE_GPIO_Port, USART2_NRE_Pin, GPIO_PIN_RESET); // NRE low = receiver on
|
|
8000b00: 20a0 movs r0, #160 @ 0xa0
|
|
8000b02: 2200 movs r2, #0
|
|
8000b04: 2101 movs r1, #1
|
|
8000b06: 05c0 lsls r0, r0, #23
|
|
8000b08: f002 fc1e bl 8003348 <HAL_GPIO_WritePin>
|
|
HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
|
|
8000b0c: 2240 movs r2, #64 @ 0x40
|
|
8000b0e: 0020 movs r0, r4
|
|
8000b10: 4906 ldr r1, [pc, #24] @ (8000b2c <rs485_transmit+0x58>)
|
|
8000b12: f004 fb75 bl 8005200 <HAL_UARTEx_ReceiveToIdle_DMA>
|
|
__HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT);
|
|
8000b16: 2104 movs r1, #4
|
|
8000b18: 3404 adds r4, #4
|
|
8000b1a: 6fe3 ldr r3, [r4, #124] @ 0x7c
|
|
8000b1c: 681a ldr r2, [r3, #0]
|
|
8000b1e: 6813 ldr r3, [r2, #0]
|
|
8000b20: 438b bics r3, r1
|
|
8000b22: 6013 str r3, [r2, #0]
|
|
}
|
|
8000b24: bd70 pop {r4, r5, r6, pc}
|
|
8000b26: 46c0 nop @ (mov r8, r8)
|
|
8000b28: 2000105c .word 0x2000105c
|
|
8000b2c: 2000015e .word 0x2000015e
|
|
|
|
08000b30 <comp_crc_header>:
|
|
{
|
|
8000b30: b570 push {r4, r5, r6, lr}
|
|
8000b32: 000d movs r5, r1
|
|
8000b34: 0004 movs r4, r0
|
|
CRC8_107_add(lcrc,lresponse->header.toAddress);
|
|
8000b36: 7809 ldrb r1, [r1, #0]
|
|
8000b38: f7ff fe08 bl 800074c <CRC8_107_add>
|
|
CRC8_107_add(lcrc,lresponse->header.fromAddress);
|
|
8000b3c: 7869 ldrb r1, [r5, #1]
|
|
8000b3e: 0020 movs r0, r4
|
|
8000b40: f7ff fe04 bl 800074c <CRC8_107_add>
|
|
CRC8_107_add(lcrc,lresponse->header.packetId);
|
|
8000b44: 78a9 ldrb r1, [r5, #2]
|
|
8000b46: 0020 movs r0, r4
|
|
8000b48: f7ff fe00 bl 800074c <CRC8_107_add>
|
|
CRC8_107_add(lcrc,lresponse->header.payloadLength);
|
|
8000b4c: 78e9 ldrb r1, [r5, #3]
|
|
8000b4e: 0020 movs r0, r4
|
|
8000b50: f7ff fdfc bl 800074c <CRC8_107_add>
|
|
}
|
|
8000b54: bd70 pop {r4, r5, r6, pc}
|
|
...
|
|
|
|
08000b58 <peel_ramp_update>:
|
|
{
|
|
8000b58: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
uint32_t now = HAL_GetTick();
|
|
8000b5a: f001 fed9 bl 8002910 <HAL_GetTick>
|
|
uint32_t dt = now - peel_last_ramp_time;
|
|
8000b5e: 4b1d ldr r3, [pc, #116] @ (8000bd4 <peel_ramp_update+0x7c>)
|
|
8000b60: 681a ldr r2, [r3, #0]
|
|
8000b62: 1a81 subs r1, r0, r2
|
|
if (dt == 0) return;
|
|
8000b64: 4290 cmp r0, r2
|
|
8000b66: d024 beq.n 8000bb2 <peel_ramp_update+0x5a>
|
|
if (peel_current_pwm == peel_target_pwm) return;
|
|
8000b68: 4e1b ldr r6, [pc, #108] @ (8000bd8 <peel_ramp_update+0x80>)
|
|
peel_last_ramp_time = now;
|
|
8000b6a: 6018 str r0, [r3, #0]
|
|
if (peel_current_pwm == peel_target_pwm) return;
|
|
8000b6c: 2300 movs r3, #0
|
|
8000b6e: 5ef7 ldrsh r7, [r6, r3]
|
|
8000b70: 4b1a ldr r3, [pc, #104] @ (8000bdc <peel_ramp_update+0x84>)
|
|
8000b72: 2400 movs r4, #0
|
|
8000b74: 5f1c ldrsh r4, [r3, r4]
|
|
8000b76: 42a7 cmp r7, r4
|
|
8000b78: d01b beq.n 8000bb2 <peel_ramp_update+0x5a>
|
|
int16_t step = (int16_t)((int32_t)PWM_MAX * dt / PEEL_RAMP_TIME_MS);
|
|
8000b7a: 2096 movs r0, #150 @ 0x96
|
|
8000b7c: 0100 lsls r0, r0, #4
|
|
8000b7e: 4348 muls r0, r1
|
|
8000b80: 2164 movs r1, #100 @ 0x64
|
|
8000b82: f7ff fad5 bl 8000130 <__udivsi3>
|
|
8000b86: 1c03 adds r3, r0, #0
|
|
if (step < 1) step = 1;
|
|
8000b88: b200 sxth r0, r0
|
|
peel_current_pwm += step;
|
|
8000b8a: b2bd uxth r5, r7
|
|
if (step < 1) step = 1;
|
|
8000b8c: 2800 cmp r0, #0
|
|
8000b8e: dc00 bgt.n 8000b92 <peel_ramp_update+0x3a>
|
|
8000b90: 2301 movs r3, #1
|
|
peel_current_pwm += step;
|
|
8000b92: b29b uxth r3, r3
|
|
if (peel_target_pwm > peel_current_pwm)
|
|
8000b94: 42a7 cmp r7, r4
|
|
8000b96: da0d bge.n 8000bb4 <peel_ramp_update+0x5c>
|
|
peel_current_pwm += step;
|
|
8000b98: 18eb adds r3, r5, r3
|
|
8000b9a: b21b sxth r3, r3
|
|
if (peel_current_pwm > peel_target_pwm)
|
|
8000b9c: 429c cmp r4, r3
|
|
8000b9e: db0d blt.n 8000bbc <peel_ramp_update+0x64>
|
|
if (peel_current_pwm < peel_target_pwm)
|
|
8000ba0: 001c movs r4, r3
|
|
peel_current_pwm = peel_target_pwm;
|
|
8000ba2: 8033 strh r3, [r6, #0]
|
|
htim1.Instance->CCR3 = peel_current_pwm;
|
|
8000ba4: 4b0e ldr r3, [pc, #56] @ (8000be0 <peel_ramp_update+0x88>)
|
|
8000ba6: 681b ldr r3, [r3, #0]
|
|
if (peel_current_pwm > 0)
|
|
8000ba8: 2c00 cmp r4, #0
|
|
8000baa: dd09 ble.n 8000bc0 <peel_ramp_update+0x68>
|
|
htim1.Instance->CCR4 = 0;
|
|
8000bac: 2200 movs r2, #0
|
|
htim1.Instance->CCR3 = peel_current_pwm;
|
|
8000bae: 63dc str r4, [r3, #60] @ 0x3c
|
|
htim1.Instance->CCR4 = 0;
|
|
8000bb0: 641a str r2, [r3, #64] @ 0x40
|
|
}
|
|
8000bb2: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
peel_current_pwm -= step;
|
|
8000bb4: 1aeb subs r3, r5, r3
|
|
8000bb6: b21b sxth r3, r3
|
|
if (peel_current_pwm < peel_target_pwm)
|
|
8000bb8: 429c cmp r4, r3
|
|
8000bba: ddf1 ble.n 8000ba0 <peel_ramp_update+0x48>
|
|
8000bbc: 0023 movs r3, r4
|
|
8000bbe: e7f0 b.n 8000ba2 <peel_ramp_update+0x4a>
|
|
else if (peel_current_pwm < 0)
|
|
8000bc0: 2c00 cmp r4, #0
|
|
8000bc2: d004 beq.n 8000bce <peel_ramp_update+0x76>
|
|
htim1.Instance->CCR3 = 0;
|
|
8000bc4: 2200 movs r2, #0
|
|
htim1.Instance->CCR4 = -peel_current_pwm;
|
|
8000bc6: 4264 negs r4, r4
|
|
htim1.Instance->CCR3 = 0;
|
|
8000bc8: 63da str r2, [r3, #60] @ 0x3c
|
|
htim1.Instance->CCR4 = 0;
|
|
8000bca: 641c str r4, [r3, #64] @ 0x40
|
|
8000bcc: e7f1 b.n 8000bb2 <peel_ramp_update+0x5a>
|
|
htim1.Instance->CCR3 = 0;
|
|
8000bce: 63dc str r4, [r3, #60] @ 0x3c
|
|
8000bd0: e7fb b.n 8000bca <peel_ramp_update+0x72>
|
|
8000bd2: 46c0 nop @ (mov r8, r8)
|
|
8000bd4: 200000fc .word 0x200000fc
|
|
8000bd8: 20000100 .word 0x20000100
|
|
8000bdc: 20000102 .word 0x20000102
|
|
8000be0: 200012b4 .word 0x200012b4
|
|
|
|
08000be4 <drive_continuous>:
|
|
target_count = total_count + 10000;
|
|
8000be4: 4b05 ldr r3, [pc, #20] @ (8000bfc <drive_continuous+0x18>)
|
|
8000be6: 681a ldr r2, [r3, #0]
|
|
target_count = total_count - 10000;
|
|
8000be8: 4b05 ldr r3, [pc, #20] @ (8000c00 <drive_continuous+0x1c>)
|
|
8000bea: 18d3 adds r3, r2, r3
|
|
if (forward)
|
|
8000bec: 2800 cmp r0, #0
|
|
8000bee: d001 beq.n 8000bf4 <drive_continuous+0x10>
|
|
target_count = total_count + 10000;
|
|
8000bf0: 4b04 ldr r3, [pc, #16] @ (8000c04 <drive_continuous+0x20>)
|
|
8000bf2: 18d3 adds r3, r2, r3
|
|
8000bf4: 4a04 ldr r2, [pc, #16] @ (8000c08 <drive_continuous+0x24>)
|
|
}
|
|
8000bf6: 6013 str r3, [r2, #0]
|
|
8000bf8: 4770 bx lr
|
|
8000bfa: 46c0 nop @ (mov r8, r8)
|
|
8000bfc: 20000158 .word 0x20000158
|
|
8000c00: ffffd8f0 .word 0xffffd8f0
|
|
8000c04: 00002710 .word 0x00002710
|
|
8000c08: 20000154 .word 0x20000154
|
|
|
|
08000c0c <halt_all>:
|
|
htim1.Instance->CCR1 = PWM_MAX;
|
|
8000c0c: 4b09 ldr r3, [pc, #36] @ (8000c34 <halt_all+0x28>)
|
|
peel_target_pwm = 0;
|
|
8000c0e: 490a ldr r1, [pc, #40] @ (8000c38 <halt_all+0x2c>)
|
|
htim1.Instance->CCR1 = PWM_MAX;
|
|
8000c10: 681a ldr r2, [r3, #0]
|
|
8000c12: 2396 movs r3, #150 @ 0x96
|
|
8000c14: 011b lsls r3, r3, #4
|
|
8000c16: 6353 str r3, [r2, #52] @ 0x34
|
|
htim1.Instance->CCR2 = PWM_MAX;
|
|
8000c18: 6393 str r3, [r2, #56] @ 0x38
|
|
peel_target_pwm = 0;
|
|
8000c1a: 2300 movs r3, #0
|
|
8000c1c: 800b strh r3, [r1, #0]
|
|
peel_current_pwm = 0;
|
|
8000c1e: 4907 ldr r1, [pc, #28] @ (8000c3c <halt_all+0x30>)
|
|
htim1.Instance->CCR3 = 0;
|
|
8000c20: 63d3 str r3, [r2, #60] @ 0x3c
|
|
peel_current_pwm = 0;
|
|
8000c22: 800b strh r3, [r1, #0]
|
|
target_count = total_count;
|
|
8000c24: 4906 ldr r1, [pc, #24] @ (8000c40 <halt_all+0x34>)
|
|
htim1.Instance->CCR4 = 0;
|
|
8000c26: 6413 str r3, [r2, #64] @ 0x40
|
|
target_count = total_count;
|
|
8000c28: 6809 ldr r1, [r1, #0]
|
|
8000c2a: 4a06 ldr r2, [pc, #24] @ (8000c44 <halt_all+0x38>)
|
|
8000c2c: 6011 str r1, [r2, #0]
|
|
pid_add = 0;
|
|
8000c2e: 4a06 ldr r2, [pc, #24] @ (8000c48 <halt_all+0x3c>)
|
|
8000c30: 6013 str r3, [r2, #0]
|
|
}
|
|
8000c32: 4770 bx lr
|
|
8000c34: 200012b4 .word 0x200012b4
|
|
8000c38: 20000102 .word 0x20000102
|
|
8000c3c: 20000100 .word 0x20000100
|
|
8000c40: 20000158 .word 0x20000158
|
|
8000c44: 20000154 .word 0x20000154
|
|
8000c48: 20000128 .word 0x20000128
|
|
|
|
08000c4c <identify_feeder>:
|
|
{
|
|
8000c4c: b510 push {r4, lr}
|
|
8000c4e: 2403 movs r4, #3
|
|
set_LED(1, 1, 1);
|
|
8000c50: 2201 movs r2, #1
|
|
8000c52: 0011 movs r1, r2
|
|
8000c54: 0010 movs r0, r2
|
|
8000c56: f7ff ff21 bl 8000a9c <set_LED>
|
|
HAL_Delay(300);
|
|
8000c5a: 2096 movs r0, #150 @ 0x96
|
|
8000c5c: 0040 lsls r0, r0, #1
|
|
8000c5e: f001 fe5d bl 800291c <HAL_Delay>
|
|
set_LED(0, 0, 0);
|
|
8000c62: 2200 movs r2, #0
|
|
8000c64: 0010 movs r0, r2
|
|
8000c66: 0011 movs r1, r2
|
|
8000c68: f7ff ff18 bl 8000a9c <set_LED>
|
|
HAL_Delay(300);
|
|
8000c6c: 2096 movs r0, #150 @ 0x96
|
|
for (int i = 0; i < 3; i++)
|
|
8000c6e: 3c01 subs r4, #1
|
|
HAL_Delay(300);
|
|
8000c70: 0040 lsls r0, r0, #1
|
|
8000c72: f001 fe53 bl 800291c <HAL_Delay>
|
|
for (int i = 0; i < 3; i++)
|
|
8000c76: 2c00 cmp r4, #0
|
|
8000c78: d1ea bne.n 8000c50 <identify_feeder+0x4>
|
|
}
|
|
8000c7a: bd10 pop {r4, pc}
|
|
|
|
08000c7c <show_version>:
|
|
set_LED(0, 1, 0);
|
|
8000c7c: 2200 movs r2, #0
|
|
{
|
|
8000c7e: b510 push {r4, lr}
|
|
set_LED(0, 1, 0);
|
|
8000c80: 0010 movs r0, r2
|
|
8000c82: 2101 movs r1, #1
|
|
8000c84: f7ff ff0a bl 8000a9c <set_LED>
|
|
HAL_Delay(250);
|
|
8000c88: 20fa movs r0, #250 @ 0xfa
|
|
8000c8a: f001 fe47 bl 800291c <HAL_Delay>
|
|
set_LED(0, 0, 0);
|
|
8000c8e: 2200 movs r2, #0
|
|
8000c90: 0010 movs r0, r2
|
|
8000c92: 0011 movs r1, r2
|
|
8000c94: f7ff ff02 bl 8000a9c <set_LED>
|
|
HAL_Delay(250);
|
|
8000c98: 20fa movs r0, #250 @ 0xfa
|
|
8000c9a: f001 fe3f bl 800291c <HAL_Delay>
|
|
}
|
|
8000c9e: bd10 pop {r4, pc}
|
|
|
|
08000ca0 <start_feed>:
|
|
{
|
|
8000ca0: b5f0 push {r4, r5, r6, r7, lr}
|
|
if (feed_state != FEED_STATE_IDLE)
|
|
8000ca2: 4b2c ldr r3, [pc, #176] @ (8000d54 <start_feed+0xb4>)
|
|
{
|
|
8000ca4: b085 sub sp, #20
|
|
if (feed_state != FEED_STATE_IDLE)
|
|
8000ca6: 9301 str r3, [sp, #4]
|
|
8000ca8: 781b ldrb r3, [r3, #0]
|
|
{
|
|
8000caa: 0004 movs r4, r0
|
|
8000cac: 9102 str r1, [sp, #8]
|
|
if (feed_state != FEED_STATE_IDLE)
|
|
8000cae: b2dd uxtb r5, r3
|
|
8000cb0: 2b00 cmp r3, #0
|
|
8000cb2: d140 bne.n 8000d36 <start_feed+0x96>
|
|
feed_distance_tenths = distance_tenths;
|
|
8000cb4: 4b28 ldr r3, [pc, #160] @ (8000d58 <start_feed+0xb8>)
|
|
8000cb6: 8018 strh r0, [r3, #0]
|
|
feed_in_progress = 1;
|
|
8000cb8: 2001 movs r0, #1
|
|
feed_direction = forward;
|
|
8000cba: 4b28 ldr r3, [pc, #160] @ (8000d5c <start_feed+0xbc>)
|
|
set_LED(1, 1, 1); // White during feed
|
|
8000cbc: 0002 movs r2, r0
|
|
feed_direction = forward;
|
|
8000cbe: 7019 strb r1, [r3, #0]
|
|
feed_retry_count = 0;
|
|
8000cc0: 4b27 ldr r3, [pc, #156] @ (8000d60 <start_feed+0xc0>)
|
|
set_LED(1, 1, 1); // White during feed
|
|
8000cc2: 0001 movs r1, r0
|
|
feed_retry_count = 0;
|
|
8000cc4: 701d strb r5, [r3, #0]
|
|
feed_in_progress = 1;
|
|
8000cc6: 4b27 ldr r3, [pc, #156] @ (8000d64 <start_feed+0xc4>)
|
|
8000cc8: 7018 strb r0, [r3, #0]
|
|
last_feed_status = STATUS_OK;
|
|
8000cca: 4b27 ldr r3, [pc, #156] @ (8000d68 <start_feed+0xc8>)
|
|
8000ccc: 701d strb r5, [r3, #0]
|
|
set_LED(1, 1, 1); // White during feed
|
|
8000cce: f7ff fee5 bl 8000a9c <set_LED>
|
|
if (forward)
|
|
8000cd2: 4b26 ldr r3, [pc, #152] @ (8000d6c <start_feed+0xcc>)
|
|
8000cd4: 4f26 ldr r7, [pc, #152] @ (8000d70 <start_feed+0xd0>)
|
|
8000cd6: 9303 str r3, [sp, #12]
|
|
8000cd8: 9b02 ldr r3, [sp, #8]
|
|
8000cda: 4e26 ldr r6, [pc, #152] @ (8000d74 <start_feed+0xd4>)
|
|
8000cdc: 2b00 cmp r3, #0
|
|
8000cde: d02c beq.n 8000d3a <start_feed+0x9a>
|
|
feed_state = FEED_STATE_DRIVING;
|
|
8000ce0: 2304 movs r3, #4
|
|
8000ce2: 9a01 ldr r2, [sp, #4]
|
|
8000ce4: 7013 strb r3, [r2, #0]
|
|
feed_state_start_time = HAL_GetTick();
|
|
8000ce6: f001 fe13 bl 8002910 <HAL_GetTick>
|
|
peel_done = 0;
|
|
8000cea: 4b23 ldr r3, [pc, #140] @ (8000d78 <start_feed+0xd8>)
|
|
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
|
|
8000cec: 9a03 ldr r2, [sp, #12]
|
|
peel_done = 0;
|
|
8000cee: 701d strb r5, [r3, #0]
|
|
feed_state_duration = distance_tenths * PEEL_TIME_PER_TENTH_MM;
|
|
8000cf0: 2312 movs r3, #18
|
|
8000cf2: 4363 muls r3, r4
|
|
8000cf4: 6033 str r3, [r6, #0]
|
|
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
|
|
8000cf6: 2396 movs r3, #150 @ 0x96
|
|
8000cf8: 011b lsls r3, r3, #4
|
|
8000cfa: 8013 strh r3, [r2, #0]
|
|
drive_done = 0;
|
|
8000cfc: 4b1f ldr r3, [pc, #124] @ (8000d7c <start_feed+0xdc>)
|
|
feed_state_start_time = HAL_GetTick();
|
|
8000cfe: 6038 str r0, [r7, #0]
|
|
drive_done = 0;
|
|
8000d00: 701d strb r5, [r3, #0]
|
|
feed_timeout_time = HAL_GetTick() + (distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
|
|
8000d02: f001 fe05 bl 8002910 <HAL_GetTick>
|
|
8000d06: 2364 movs r3, #100 @ 0x64
|
|
8000d08: 4363 muls r3, r4
|
|
8000d0a: 33f5 adds r3, #245 @ 0xf5
|
|
8000d0c: 4a1c ldr r2, [pc, #112] @ (8000d80 <start_feed+0xe0>)
|
|
8000d0e: 33ff adds r3, #255 @ 0xff
|
|
8000d10: 181b adds r3, r3, r0
|
|
8000d12: 6013 str r3, [r2, #0]
|
|
int64_t temp = ((int64_t)tenths * 100 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV;
|
|
8000d14: 0020 movs r0, r4
|
|
8000d16: 2300 movs r3, #0
|
|
8000d18: 4a1a ldr r2, [pc, #104] @ (8000d84 <start_feed+0xe4>)
|
|
8000d1a: 17e1 asrs r1, r4, #31
|
|
8000d1c: f7ff fba2 bl 8000464 <__aeabi_lmul>
|
|
8000d20: 2300 movs r3, #0
|
|
8000d22: 4a19 ldr r2, [pc, #100] @ (8000d88 <start_feed+0xe8>)
|
|
8000d24: f7ff fb7a bl 800041c <__aeabi_ldivmod>
|
|
feed_target_position = total_count + tenths_to_counts(distance_tenths);
|
|
8000d28: 4b18 ldr r3, [pc, #96] @ (8000d8c <start_feed+0xec>)
|
|
8000d2a: 681b ldr r3, [r3, #0]
|
|
8000d2c: 1818 adds r0, r3, r0
|
|
8000d2e: 4b18 ldr r3, [pc, #96] @ (8000d90 <start_feed+0xf0>)
|
|
8000d30: 6018 str r0, [r3, #0]
|
|
target_count = feed_target_position;
|
|
8000d32: 4b18 ldr r3, [pc, #96] @ (8000d94 <start_feed+0xf4>)
|
|
8000d34: 6018 str r0, [r3, #0]
|
|
}
|
|
8000d36: b005 add sp, #20
|
|
8000d38: bdf0 pop {r4, r5, r6, r7, pc}
|
|
feed_state = FEED_STATE_UNPEEL;
|
|
8000d3a: 2303 movs r3, #3
|
|
8000d3c: 9a01 ldr r2, [sp, #4]
|
|
8000d3e: 7013 strb r3, [r2, #0]
|
|
feed_state_start_time = HAL_GetTick();
|
|
8000d40: f001 fde6 bl 8002910 <HAL_GetTick>
|
|
feed_state_duration = distance_tenths * BACKWARDS_PEEL_TIME_PER_TENTH_MM;
|
|
8000d44: 231e movs r3, #30
|
|
8000d46: 4363 muls r3, r4
|
|
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
|
|
8000d48: 9a03 ldr r2, [sp, #12]
|
|
feed_state_duration = distance_tenths * BACKWARDS_PEEL_TIME_PER_TENTH_MM;
|
|
8000d4a: 6033 str r3, [r6, #0]
|
|
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
|
|
8000d4c: 4b12 ldr r3, [pc, #72] @ (8000d98 <start_feed+0xf8>)
|
|
feed_state_start_time = HAL_GetTick();
|
|
8000d4e: 6038 str r0, [r7, #0]
|
|
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
|
|
8000d50: 8013 strh r3, [r2, #0]
|
|
}
|
|
8000d52: e7f0 b.n 8000d36 <start_feed+0x96>
|
|
8000d54: 2000011c .word 0x2000011c
|
|
8000d58: 2000010c .word 0x2000010c
|
|
8000d5c: 20000004 .word 0x20000004
|
|
8000d60: 20000104 .word 0x20000104
|
|
8000d64: 20000125 .word 0x20000125
|
|
8000d68: 20000126 .word 0x20000126
|
|
8000d6c: 20000102 .word 0x20000102
|
|
8000d70: 20000118 .word 0x20000118
|
|
8000d74: 20000114 .word 0x20000114
|
|
8000d78: 20000003 .word 0x20000003
|
|
8000d7c: 20000002 .word 0x20000002
|
|
8000d80: 20000110 .word 0x20000110
|
|
8000d84: 002c01a0 .word 0x002c01a0
|
|
8000d88: 0001f377 .word 0x0001f377
|
|
8000d8c: 20000158 .word 0x20000158
|
|
8000d90: 20000108 .word 0x20000108
|
|
8000d94: 20000154 .word 0x20000154
|
|
8000d98: fffff6a0 .word 0xfffff6a0
|
|
|
|
08000d9c <feed_state_machine_update>:
|
|
{
|
|
8000d9c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
if (feed_state == FEED_STATE_IDLE)
|
|
8000d9e: 4eaa ldr r6, [pc, #680] @ (8001048 <feed_state_machine_update+0x2ac>)
|
|
8000da0: 7833 ldrb r3, [r6, #0]
|
|
8000da2: 2b00 cmp r3, #0
|
|
8000da4: d03a beq.n 8000e1c <feed_state_machine_update+0x80>
|
|
uint32_t now = HAL_GetTick();
|
|
8000da6: f001 fdb3 bl 8002910 <HAL_GetTick>
|
|
uint32_t elapsed = now - feed_state_start_time;
|
|
8000daa: 4da8 ldr r5, [pc, #672] @ (800104c <feed_state_machine_update+0x2b0>)
|
|
uint32_t now = HAL_GetTick();
|
|
8000dac: 0004 movs r4, r0
|
|
uint32_t elapsed = now - feed_state_start_time;
|
|
8000dae: 682b ldr r3, [r5, #0]
|
|
8000db0: 1ac3 subs r3, r0, r3
|
|
switch (feed_state)
|
|
8000db2: 7830 ldrb r0, [r6, #0]
|
|
8000db4: 3801 subs r0, #1
|
|
8000db6: 2808 cmp r0, #8
|
|
8000db8: d900 bls.n 8000dbc <feed_state_machine_update+0x20>
|
|
8000dba: e142 b.n 8001042 <feed_state_machine_update+0x2a6>
|
|
8000dbc: f7ff f9ae bl 800011c <__gnu_thumb1_case_uhi>
|
|
8000dc0: 0141002e .word 0x0141002e
|
|
8000dc4: 002f0009 .word 0x002f0009
|
|
8000dc8: 00d400bc .word 0x00d400bc
|
|
8000dcc: 00f200eb .word 0x00f200eb
|
|
8000dd0: 0101 .short 0x0101
|
|
if (elapsed >= feed_state_duration)
|
|
8000dd2: 4a9f ldr r2, [pc, #636] @ (8001050 <feed_state_machine_update+0x2b4>)
|
|
8000dd4: 6812 ldr r2, [r2, #0]
|
|
8000dd6: 4293 cmp r3, r2
|
|
8000dd8: d320 bcc.n 8000e1c <feed_state_machine_update+0x80>
|
|
peel_target_pwm = 0;
|
|
8000dda: 2200 movs r2, #0
|
|
8000ddc: 4b9d ldr r3, [pc, #628] @ (8001054 <feed_state_machine_update+0x2b8>)
|
|
feed_state_start_time = now;
|
|
8000dde: 602c str r4, [r5, #0]
|
|
peel_target_pwm = 0;
|
|
8000de0: 801a strh r2, [r3, #0]
|
|
feed_state = FEED_STATE_DRIVING;
|
|
8000de2: 2304 movs r3, #4
|
|
8000de4: 7033 strb r3, [r6, #0]
|
|
int16_t total_backward = feed_distance_tenths + BACKLASH_COMP_TENTH_MM;
|
|
8000de6: 4b9c ldr r3, [pc, #624] @ (8001058 <feed_state_machine_update+0x2bc>)
|
|
feed_timeout_time = now + (total_backward * TIMEOUT_TIME_PER_TENTH_MM) + 500;
|
|
8000de8: 4a9c ldr r2, [pc, #624] @ (800105c <feed_state_machine_update+0x2c0>)
|
|
int16_t total_backward = feed_distance_tenths + BACKLASH_COMP_TENTH_MM;
|
|
8000dea: 8818 ldrh r0, [r3, #0]
|
|
feed_timeout_time = now + (total_backward * TIMEOUT_TIME_PER_TENTH_MM) + 500;
|
|
8000dec: 2364 movs r3, #100 @ 0x64
|
|
int16_t total_backward = feed_distance_tenths + BACKLASH_COMP_TENTH_MM;
|
|
8000dee: 300a adds r0, #10
|
|
8000df0: b200 sxth r0, r0
|
|
feed_timeout_time = now + (total_backward * TIMEOUT_TIME_PER_TENTH_MM) + 500;
|
|
8000df2: 4343 muls r3, r0
|
|
8000df4: 33f5 adds r3, #245 @ 0xf5
|
|
8000df6: 33ff adds r3, #255 @ 0xff
|
|
8000df8: 191b adds r3, r3, r4
|
|
8000dfa: 6013 str r3, [r2, #0]
|
|
int64_t temp = ((int64_t)tenths * 100 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV;
|
|
8000dfc: 17c1 asrs r1, r0, #31
|
|
8000dfe: 2300 movs r3, #0
|
|
8000e00: 4a97 ldr r2, [pc, #604] @ (8001060 <feed_state_machine_update+0x2c4>)
|
|
8000e02: f7ff fb2f bl 8000464 <__aeabi_lmul>
|
|
8000e06: 2300 movs r3, #0
|
|
8000e08: 4a96 ldr r2, [pc, #600] @ (8001064 <feed_state_machine_update+0x2c8>)
|
|
8000e0a: f7ff fb07 bl 800041c <__aeabi_ldivmod>
|
|
feed_target_position = total_count - tenths_to_counts(total_backward);
|
|
8000e0e: 4c96 ldr r4, [pc, #600] @ (8001068 <feed_state_machine_update+0x2cc>)
|
|
8000e10: 6823 ldr r3, [r4, #0]
|
|
8000e12: 1a18 subs r0, r3, r0
|
|
8000e14: 4b95 ldr r3, [pc, #596] @ (800106c <feed_state_machine_update+0x2d0>)
|
|
8000e16: 6018 str r0, [r3, #0]
|
|
target_count = feed_target_position;
|
|
8000e18: 4b95 ldr r3, [pc, #596] @ (8001070 <feed_state_machine_update+0x2d4>)
|
|
8000e1a: 6018 str r0, [r3, #0]
|
|
}
|
|
8000e1c: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
|
|
if (!peel_done && elapsed >= feed_state_duration)
|
|
8000e1e: 4995 ldr r1, [pc, #596] @ (8001074 <feed_state_machine_update+0x2d8>)
|
|
8000e20: 780a ldrb r2, [r1, #0]
|
|
8000e22: 2a00 cmp r2, #0
|
|
8000e24: d107 bne.n 8000e36 <feed_state_machine_update+0x9a>
|
|
8000e26: 488a ldr r0, [pc, #552] @ (8001050 <feed_state_machine_update+0x2b4>)
|
|
8000e28: 6800 ldr r0, [r0, #0]
|
|
8000e2a: 4283 cmp r3, r0
|
|
8000e2c: d303 bcc.n 8000e36 <feed_state_machine_update+0x9a>
|
|
peel_target_pwm = 0;
|
|
8000e2e: 4b89 ldr r3, [pc, #548] @ (8001054 <feed_state_machine_update+0x2b8>)
|
|
8000e30: 801a strh r2, [r3, #0]
|
|
peel_done = 1;
|
|
8000e32: 3201 adds r2, #1
|
|
8000e34: 700a strb r2, [r1, #0]
|
|
int32_t error = feed_target_position - total_count;
|
|
8000e36: 4b8c ldr r3, [pc, #560] @ (8001068 <feed_state_machine_update+0x2cc>)
|
|
8000e38: 681b ldr r3, [r3, #0]
|
|
8000e3a: 469c mov ip, r3
|
|
8000e3c: 4b8b ldr r3, [pc, #556] @ (800106c <feed_state_machine_update+0x2d0>)
|
|
8000e3e: 6819 ldr r1, [r3, #0]
|
|
8000e40: 9301 str r3, [sp, #4]
|
|
8000e42: 4663 mov r3, ip
|
|
8000e44: 1ac9 subs r1, r1, r3
|
|
int32_t abs_error = error < 0 ? -error : error;
|
|
8000e46: 17cb asrs r3, r1, #31
|
|
8000e48: 18c8 adds r0, r1, r3
|
|
8000e4a: 4058 eors r0, r3
|
|
int32_t brake_adj = abs_error >= 20 ? 20 : abs_error >= 10 ? 10 : abs_error >= 5 ? 5 : 0;
|
|
8000e4c: 2314 movs r3, #20
|
|
8000e4e: 2813 cmp r0, #19
|
|
8000e50: dc06 bgt.n 8000e60 <feed_state_machine_update+0xc4>
|
|
8000e52: 3b0a subs r3, #10
|
|
8000e54: 2809 cmp r0, #9
|
|
8000e56: dc03 bgt.n 8000e60 <feed_state_machine_update+0xc4>
|
|
8000e58: 2300 movs r3, #0
|
|
8000e5a: 2804 cmp r0, #4
|
|
8000e5c: dd00 ble.n 8000e60 <feed_state_machine_update+0xc4>
|
|
8000e5e: 3305 adds r3, #5
|
|
if (!drive_done && abs_error < FEED_POSITION_TOLERANCE)
|
|
8000e60: 4f85 ldr r7, [pc, #532] @ (8001078 <feed_state_machine_update+0x2dc>)
|
|
8000e62: 783f ldrb r7, [r7, #0]
|
|
8000e64: 2f00 cmp r7, #0
|
|
8000e66: d10a bne.n 8000e7e <feed_state_machine_update+0xe2>
|
|
8000e68: 280e cmp r0, #14
|
|
8000e6a: dc2c bgt.n 8000ec6 <feed_state_machine_update+0x12a>
|
|
if (error < 0)
|
|
8000e6c: 2900 cmp r1, #0
|
|
8000e6e: da13 bge.n 8000e98 <feed_state_machine_update+0xfc>
|
|
brake_time_tenths += brake_adj;
|
|
8000e70: 4f82 ldr r7, [pc, #520] @ (800107c <feed_state_machine_update+0x2e0>)
|
|
8000e72: 6838 ldr r0, [r7, #0]
|
|
8000e74: 18c0 adds r0, r0, r3
|
|
8000e76: 6038 str r0, [r7, #0]
|
|
drive_done = 1;
|
|
8000e78: 2701 movs r7, #1
|
|
8000e7a: 487f ldr r0, [pc, #508] @ (8001078 <feed_state_machine_update+0x2dc>)
|
|
8000e7c: 7007 strb r7, [r0, #0]
|
|
if (peel_done && drive_done)
|
|
8000e7e: 2a00 cmp r2, #0
|
|
8000e80: d021 beq.n 8000ec6 <feed_state_machine_update+0x12a>
|
|
if (!feed_direction)
|
|
8000e82: 4b7f ldr r3, [pc, #508] @ (8001080 <feed_state_machine_update+0x2e4>)
|
|
8000e84: 781a ldrb r2, [r3, #0]
|
|
8000e86: 4b72 ldr r3, [pc, #456] @ (8001050 <feed_state_machine_update+0x2b4>)
|
|
8000e88: 2a00 cmp r2, #0
|
|
8000e8a: d011 beq.n 8000eb0 <feed_state_machine_update+0x114>
|
|
feed_state = FEED_STATE_SETTLING;
|
|
8000e8c: 2207 movs r2, #7
|
|
feed_state_start_time = now;
|
|
8000e8e: 602c str r4, [r5, #0]
|
|
feed_state = FEED_STATE_SETTLING;
|
|
8000e90: 7032 strb r2, [r6, #0]
|
|
feed_state_duration = FEED_SETTLE_TIME;
|
|
8000e92: 2232 movs r2, #50 @ 0x32
|
|
8000e94: 601a str r2, [r3, #0]
|
|
8000e96: e7c1 b.n 8000e1c <feed_state_machine_update+0x80>
|
|
else if (error > 0 && brake_time_tenths > brake_adj)
|
|
8000e98: 2900 cmp r1, #0
|
|
8000e9a: d0ed beq.n 8000e78 <feed_state_machine_update+0xdc>
|
|
8000e9c: 4877 ldr r0, [pc, #476] @ (800107c <feed_state_machine_update+0x2e0>)
|
|
8000e9e: 6807 ldr r7, [r0, #0]
|
|
8000ea0: 42bb cmp r3, r7
|
|
8000ea2: da03 bge.n 8000eac <feed_state_machine_update+0x110>
|
|
brake_time_tenths -= brake_adj;
|
|
8000ea4: 6807 ldr r7, [r0, #0]
|
|
8000ea6: 1aff subs r7, r7, r3
|
|
brake_time_tenths = 1;
|
|
8000ea8: 6007 str r7, [r0, #0]
|
|
8000eaa: e7e5 b.n 8000e78 <feed_state_machine_update+0xdc>
|
|
8000eac: 2701 movs r7, #1
|
|
8000eae: e7fb b.n 8000ea8 <feed_state_machine_update+0x10c>
|
|
feed_state = FEED_STATE_SLACK_REMOVAL;
|
|
8000eb0: 2205 movs r2, #5
|
|
8000eb2: 7032 strb r2, [r6, #0]
|
|
feed_state_duration = BACKWARDS_FEED_FILM_SLACK_REMOVAL_TIME;
|
|
8000eb4: 325a adds r2, #90 @ 0x5a
|
|
8000eb6: 32ff adds r2, #255 @ 0xff
|
|
8000eb8: 601a str r2, [r3, #0]
|
|
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
|
|
8000eba: 2296 movs r2, #150 @ 0x96
|
|
8000ebc: 4b65 ldr r3, [pc, #404] @ (8001054 <feed_state_machine_update+0x2b8>)
|
|
8000ebe: 0112 lsls r2, r2, #4
|
|
feed_state_start_time = now;
|
|
8000ec0: 602c str r4, [r5, #0]
|
|
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
|
|
8000ec2: 801a strh r2, [r3, #0]
|
|
}
|
|
8000ec4: e7aa b.n 8000e1c <feed_state_machine_update+0x80>
|
|
else if (error < -FEED_POSITION_TOLERANCE)
|
|
8000ec6: 4e65 ldr r6, [pc, #404] @ (800105c <feed_state_machine_update+0x2c0>)
|
|
8000ec8: 310f adds r1, #15
|
|
8000eca: da28 bge.n 8000f1e <feed_state_machine_update+0x182>
|
|
brake_time_tenths += brake_adj;
|
|
8000ecc: 496b ldr r1, [pc, #428] @ (800107c <feed_state_machine_update+0x2e0>)
|
|
8000ece: 680a ldr r2, [r1, #0]
|
|
8000ed0: 189b adds r3, r3, r2
|
|
feed_retry_total++;
|
|
8000ed2: 4a6c ldr r2, [pc, #432] @ (8001084 <feed_state_machine_update+0x2e8>)
|
|
else brake_time_tenths = 1;
|
|
8000ed4: 600b str r3, [r1, #0]
|
|
feed_retry_total++;
|
|
8000ed6: 8813 ldrh r3, [r2, #0]
|
|
target_count = total_count - tenths_to_counts(10);
|
|
8000ed8: 4f65 ldr r7, [pc, #404] @ (8001070 <feed_state_machine_update+0x2d4>)
|
|
feed_retry_total++;
|
|
8000eda: 3301 adds r3, #1
|
|
8000edc: b29b uxth r3, r3
|
|
8000ede: 8013 strh r3, [r2, #0]
|
|
target_count = total_count - tenths_to_counts(10);
|
|
8000ee0: 4663 mov r3, ip
|
|
HAL_Delay(200);
|
|
8000ee2: 20c8 movs r0, #200 @ 0xc8
|
|
target_count = total_count - tenths_to_counts(10);
|
|
8000ee4: 3be1 subs r3, #225 @ 0xe1
|
|
8000ee6: 603b str r3, [r7, #0]
|
|
HAL_Delay(200);
|
|
8000ee8: f001 fd18 bl 800291c <HAL_Delay>
|
|
htim1.Instance->CCR1 = PWM_MAX;
|
|
8000eec: 2296 movs r2, #150 @ 0x96
|
|
8000eee: 4b66 ldr r3, [pc, #408] @ (8001088 <feed_state_machine_update+0x2ec>)
|
|
8000ef0: 0112 lsls r2, r2, #4
|
|
8000ef2: 681b ldr r3, [r3, #0]
|
|
HAL_Delay(50);
|
|
8000ef4: 2032 movs r0, #50 @ 0x32
|
|
htim1.Instance->CCR1 = PWM_MAX;
|
|
8000ef6: 635a str r2, [r3, #52] @ 0x34
|
|
htim1.Instance->CCR2 = PWM_MAX;
|
|
8000ef8: 639a str r2, [r3, #56] @ 0x38
|
|
HAL_Delay(50);
|
|
8000efa: f001 fd0f bl 800291c <HAL_Delay>
|
|
target_count = feed_target_position;
|
|
8000efe: 9b01 ldr r3, [sp, #4]
|
|
feed_state_start_time = now;
|
|
8000f00: 602c str r4, [r5, #0]
|
|
target_count = feed_target_position;
|
|
8000f02: 681b ldr r3, [r3, #0]
|
|
8000f04: 603b str r3, [r7, #0]
|
|
feed_timeout_time = HAL_GetTick() + (feed_distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
|
|
8000f06: f001 fd03 bl 8002910 <HAL_GetTick>
|
|
8000f0a: 4b53 ldr r3, [pc, #332] @ (8001058 <feed_state_machine_update+0x2bc>)
|
|
8000f0c: 2200 movs r2, #0
|
|
8000f0e: 5e9a ldrsh r2, [r3, r2]
|
|
8000f10: 2364 movs r3, #100 @ 0x64
|
|
8000f12: 4353 muls r3, r2
|
|
8000f14: 33f5 adds r3, #245 @ 0xf5
|
|
8000f16: 33ff adds r3, #255 @ 0xff
|
|
8000f18: 181b adds r3, r3, r0
|
|
8000f1a: 6033 str r3, [r6, #0]
|
|
8000f1c: e77e b.n 8000e1c <feed_state_machine_update+0x80>
|
|
else if (now > feed_timeout_time)
|
|
8000f1e: 6832 ldr r2, [r6, #0]
|
|
8000f20: 4294 cmp r4, r2
|
|
8000f22: d800 bhi.n 8000f26 <feed_state_machine_update+0x18a>
|
|
8000f24: e77a b.n 8000e1c <feed_state_machine_update+0x80>
|
|
if (brake_time_tenths > brake_adj) brake_time_tenths -= brake_adj;
|
|
8000f26: 4955 ldr r1, [pc, #340] @ (800107c <feed_state_machine_update+0x2e0>)
|
|
8000f28: 680a ldr r2, [r1, #0]
|
|
8000f2a: 4293 cmp r3, r2
|
|
8000f2c: da02 bge.n 8000f34 <feed_state_machine_update+0x198>
|
|
8000f2e: 680a ldr r2, [r1, #0]
|
|
8000f30: 1ad3 subs r3, r2, r3
|
|
8000f32: e7ce b.n 8000ed2 <feed_state_machine_update+0x136>
|
|
else brake_time_tenths = 1;
|
|
8000f34: 2301 movs r3, #1
|
|
8000f36: e7cc b.n 8000ed2 <feed_state_machine_update+0x136>
|
|
if (elapsed >= feed_state_duration)
|
|
8000f38: 4a45 ldr r2, [pc, #276] @ (8001050 <feed_state_machine_update+0x2b4>)
|
|
8000f3a: 6812 ldr r2, [r2, #0]
|
|
8000f3c: 4293 cmp r3, r2
|
|
8000f3e: d200 bcs.n 8000f42 <feed_state_machine_update+0x1a6>
|
|
8000f40: e76c b.n 8000e1c <feed_state_machine_update+0x80>
|
|
peel_target_pwm = 0;
|
|
8000f42: 2200 movs r2, #0
|
|
8000f44: 4b43 ldr r3, [pc, #268] @ (8001054 <feed_state_machine_update+0x2b8>)
|
|
feed_state_start_time = now;
|
|
8000f46: 602c str r4, [r5, #0]
|
|
peel_target_pwm = 0;
|
|
8000f48: 801a strh r2, [r3, #0]
|
|
feed_state = FEED_STATE_DRIVING_BACKLASH;
|
|
8000f4a: 2306 movs r3, #6
|
|
feed_timeout_time = now + (BACKLASH_COMP_TENTH_MM * TIMEOUT_TIME_PER_TENTH_MM) + 200;
|
|
8000f4c: 2296 movs r2, #150 @ 0x96
|
|
feed_state = FEED_STATE_DRIVING_BACKLASH;
|
|
8000f4e: 7033 strb r3, [r6, #0]
|
|
feed_timeout_time = now + (BACKLASH_COMP_TENTH_MM * TIMEOUT_TIME_PER_TENTH_MM) + 200;
|
|
8000f50: 00d2 lsls r2, r2, #3
|
|
8000f52: 4b42 ldr r3, [pc, #264] @ (800105c <feed_state_machine_update+0x2c0>)
|
|
8000f54: 18a4 adds r4, r4, r2
|
|
8000f56: 601c str r4, [r3, #0]
|
|
feed_target_position = total_count + tenths_to_counts(BACKLASH_COMP_TENTH_MM);
|
|
8000f58: 4b43 ldr r3, [pc, #268] @ (8001068 <feed_state_machine_update+0x2cc>)
|
|
8000f5a: 4a44 ldr r2, [pc, #272] @ (800106c <feed_state_machine_update+0x2d0>)
|
|
8000f5c: 681b ldr r3, [r3, #0]
|
|
8000f5e: 33e1 adds r3, #225 @ 0xe1
|
|
8000f60: 6013 str r3, [r2, #0]
|
|
target_count = feed_target_position;
|
|
8000f62: 4a43 ldr r2, [pc, #268] @ (8001070 <feed_state_machine_update+0x2d4>)
|
|
feed_timeout_time = HAL_GetTick() + (feed_distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
|
|
8000f64: 6013 str r3, [r2, #0]
|
|
8000f66: e759 b.n 8000e1c <feed_state_machine_update+0x80>
|
|
int32_t error = feed_target_position - total_count;
|
|
8000f68: 4b40 ldr r3, [pc, #256] @ (800106c <feed_state_machine_update+0x2d0>)
|
|
8000f6a: 4a3f ldr r2, [pc, #252] @ (8001068 <feed_state_machine_update+0x2cc>)
|
|
8000f6c: 681b ldr r3, [r3, #0]
|
|
8000f6e: 6812 ldr r2, [r2, #0]
|
|
8000f70: 1a9b subs r3, r3, r2
|
|
if (error < 0) error = -error;
|
|
8000f72: 17da asrs r2, r3, #31
|
|
8000f74: 189b adds r3, r3, r2
|
|
8000f76: 4053 eors r3, r2
|
|
if (error < FEED_POSITION_TOLERANCE)
|
|
8000f78: 2b0e cmp r3, #14
|
|
8000f7a: dc04 bgt.n 8000f86 <feed_state_machine_update+0x1ea>
|
|
feed_state = FEED_STATE_SETTLING;
|
|
8000f7c: 2307 movs r3, #7
|
|
feed_state_start_time = now;
|
|
8000f7e: 602c str r4, [r5, #0]
|
|
feed_state = FEED_STATE_SETTLING;
|
|
8000f80: 7033 strb r3, [r6, #0]
|
|
feed_state_duration = FEED_SETTLE_TIME;
|
|
8000f82: 4b33 ldr r3, [pc, #204] @ (8001050 <feed_state_machine_update+0x2b4>)
|
|
8000f84: e785 b.n 8000e92 <feed_state_machine_update+0xf6>
|
|
else if (now > feed_timeout_time)
|
|
8000f86: 4b35 ldr r3, [pc, #212] @ (800105c <feed_state_machine_update+0x2c0>)
|
|
8000f88: 681b ldr r3, [r3, #0]
|
|
8000f8a: 429c cmp r4, r3
|
|
8000f8c: d800 bhi.n 8000f90 <feed_state_machine_update+0x1f4>
|
|
8000f8e: e745 b.n 8000e1c <feed_state_machine_update+0x80>
|
|
feed_state = FEED_STATE_TIMEOUT;
|
|
8000f90: 2309 movs r3, #9
|
|
feed_state = FEED_STATE_IDLE;
|
|
8000f92: 7033 strb r3, [r6, #0]
|
|
break;
|
|
8000f94: e742 b.n 8000e1c <feed_state_machine_update+0x80>
|
|
if (elapsed >= feed_state_duration)
|
|
8000f96: 4a2e ldr r2, [pc, #184] @ (8001050 <feed_state_machine_update+0x2b4>)
|
|
8000f98: 6812 ldr r2, [r2, #0]
|
|
8000f9a: 4293 cmp r3, r2
|
|
8000f9c: d200 bcs.n 8000fa0 <feed_state_machine_update+0x204>
|
|
8000f9e: e73d b.n 8000e1c <feed_state_machine_update+0x80>
|
|
feed_state = FEED_STATE_COMPLETE;
|
|
8000fa0: 2308 movs r3, #8
|
|
8000fa2: e7f6 b.n 8000f92 <feed_state_machine_update+0x1f6>
|
|
feed_state = FEED_STATE_IDLE;
|
|
8000fa4: 2300 movs r3, #0
|
|
feed_in_progress = 0;
|
|
8000fa6: 4a39 ldr r2, [pc, #228] @ (800108c <feed_state_machine_update+0x2f0>)
|
|
feed_state = FEED_STATE_IDLE;
|
|
8000fa8: 7033 strb r3, [r6, #0]
|
|
feed_in_progress = 0;
|
|
8000faa: 7013 strb r3, [r2, #0]
|
|
last_feed_status = STATUS_OK;
|
|
8000fac: 4a38 ldr r2, [pc, #224] @ (8001090 <feed_state_machine_update+0x2f4>)
|
|
8000fae: 7013 strb r3, [r2, #0]
|
|
feed_just_completed = 1;
|
|
8000fb0: 2201 movs r2, #1
|
|
8000fb2: 4b38 ldr r3, [pc, #224] @ (8001094 <feed_state_machine_update+0x2f8>)
|
|
8000fb4: 701a strb r2, [r3, #0]
|
|
feed_ok_count++;
|
|
8000fb6: 4a38 ldr r2, [pc, #224] @ (8001098 <feed_state_machine_update+0x2fc>)
|
|
8000fb8: 8813 ldrh r3, [r2, #0]
|
|
8000fba: 3301 adds r3, #1
|
|
8000fbc: b29b uxth r3, r3
|
|
8000fbe: 8013 strh r3, [r2, #0]
|
|
break;
|
|
8000fc0: e72c b.n 8000e1c <feed_state_machine_update+0x80>
|
|
if (feed_retry_count < FEED_RETRY_LIMIT)
|
|
8000fc2: 4a36 ldr r2, [pc, #216] @ (800109c <feed_state_machine_update+0x300>)
|
|
8000fc4: 7813 ldrb r3, [r2, #0]
|
|
8000fc6: 2b02 cmp r3, #2
|
|
8000fc8: d829 bhi.n 800101e <feed_state_machine_update+0x282>
|
|
feed_retry_count++;
|
|
8000fca: 3301 adds r3, #1
|
|
8000fcc: 7013 strb r3, [r2, #0]
|
|
feed_retry_total++;
|
|
8000fce: 4a2d ldr r2, [pc, #180] @ (8001084 <feed_state_machine_update+0x2e8>)
|
|
target_count = total_count - tenths_to_counts(10);
|
|
8000fd0: 4f27 ldr r7, [pc, #156] @ (8001070 <feed_state_machine_update+0x2d4>)
|
|
feed_retry_total++;
|
|
8000fd2: 8813 ldrh r3, [r2, #0]
|
|
HAL_Delay(200); // Let motor reverse past backlash
|
|
8000fd4: 20c8 movs r0, #200 @ 0xc8
|
|
feed_retry_total++;
|
|
8000fd6: 3301 adds r3, #1
|
|
8000fd8: b29b uxth r3, r3
|
|
8000fda: 8013 strh r3, [r2, #0]
|
|
target_count = total_count - tenths_to_counts(10);
|
|
8000fdc: 4b22 ldr r3, [pc, #136] @ (8001068 <feed_state_machine_update+0x2cc>)
|
|
8000fde: 681b ldr r3, [r3, #0]
|
|
8000fe0: 3be1 subs r3, #225 @ 0xe1
|
|
8000fe2: 603b str r3, [r7, #0]
|
|
HAL_Delay(200); // Let motor reverse past backlash
|
|
8000fe4: f001 fc9a bl 800291c <HAL_Delay>
|
|
htim1.Instance->CCR1 = PWM_MAX;
|
|
8000fe8: 2296 movs r2, #150 @ 0x96
|
|
8000fea: 4b27 ldr r3, [pc, #156] @ (8001088 <feed_state_machine_update+0x2ec>)
|
|
8000fec: 0112 lsls r2, r2, #4
|
|
8000fee: 681b ldr r3, [r3, #0]
|
|
HAL_Delay(50); // Settle
|
|
8000ff0: 2032 movs r0, #50 @ 0x32
|
|
htim1.Instance->CCR1 = PWM_MAX;
|
|
8000ff2: 635a str r2, [r3, #52] @ 0x34
|
|
htim1.Instance->CCR2 = PWM_MAX;
|
|
8000ff4: 639a str r2, [r3, #56] @ 0x38
|
|
HAL_Delay(50); // Settle
|
|
8000ff6: f001 fc91 bl 800291c <HAL_Delay>
|
|
target_count = feed_target_position;
|
|
8000ffa: 4b1c ldr r3, [pc, #112] @ (800106c <feed_state_machine_update+0x2d0>)
|
|
feed_state_start_time = now;
|
|
8000ffc: 602c str r4, [r5, #0]
|
|
target_count = feed_target_position;
|
|
8000ffe: 681b ldr r3, [r3, #0]
|
|
8001000: 603b str r3, [r7, #0]
|
|
feed_state = FEED_STATE_DRIVING;
|
|
8001002: 2304 movs r3, #4
|
|
8001004: 7033 strb r3, [r6, #0]
|
|
feed_timeout_time = HAL_GetTick() + (feed_distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
|
|
8001006: f001 fc83 bl 8002910 <HAL_GetTick>
|
|
800100a: 4b13 ldr r3, [pc, #76] @ (8001058 <feed_state_machine_update+0x2bc>)
|
|
800100c: 4a13 ldr r2, [pc, #76] @ (800105c <feed_state_machine_update+0x2c0>)
|
|
800100e: 2100 movs r1, #0
|
|
8001010: 5e59 ldrsh r1, [r3, r1]
|
|
8001012: 2364 movs r3, #100 @ 0x64
|
|
8001014: 434b muls r3, r1
|
|
8001016: 33f5 adds r3, #245 @ 0xf5
|
|
8001018: 33ff adds r3, #255 @ 0xff
|
|
800101a: 181b adds r3, r3, r0
|
|
800101c: e7a2 b.n 8000f64 <feed_state_machine_update+0x1c8>
|
|
feed_state = FEED_STATE_IDLE;
|
|
800101e: 2300 movs r3, #0
|
|
feed_in_progress = 0;
|
|
8001020: 4a1a ldr r2, [pc, #104] @ (800108c <feed_state_machine_update+0x2f0>)
|
|
feed_state = FEED_STATE_IDLE;
|
|
8001022: 7033 strb r3, [r6, #0]
|
|
feed_in_progress = 0;
|
|
8001024: 7013 strb r3, [r2, #0]
|
|
last_feed_status = STATUS_COULDNT_REACH;
|
|
8001026: 2202 movs r2, #2
|
|
8001028: 4b19 ldr r3, [pc, #100] @ (8001090 <feed_state_machine_update+0x2f4>)
|
|
800102a: 701a strb r2, [r3, #0]
|
|
feed_just_completed = 1;
|
|
800102c: 4b19 ldr r3, [pc, #100] @ (8001094 <feed_state_machine_update+0x2f8>)
|
|
800102e: 3a01 subs r2, #1
|
|
8001030: 701a strb r2, [r3, #0]
|
|
feed_fail_count++;
|
|
8001032: 4a1b ldr r2, [pc, #108] @ (80010a0 <feed_state_machine_update+0x304>)
|
|
8001034: 8813 ldrh r3, [r2, #0]
|
|
8001036: 3301 adds r3, #1
|
|
8001038: b29b uxth r3, r3
|
|
800103a: 8013 strh r3, [r2, #0]
|
|
halt_all();
|
|
800103c: f7ff fde6 bl 8000c0c <halt_all>
|
|
8001040: e6ec b.n 8000e1c <feed_state_machine_update+0x80>
|
|
feed_state = FEED_STATE_IDLE;
|
|
8001042: 2300 movs r3, #0
|
|
8001044: e7a5 b.n 8000f92 <feed_state_machine_update+0x1f6>
|
|
8001046: 46c0 nop @ (mov r8, r8)
|
|
8001048: 2000011c .word 0x2000011c
|
|
800104c: 20000118 .word 0x20000118
|
|
8001050: 20000114 .word 0x20000114
|
|
8001054: 20000102 .word 0x20000102
|
|
8001058: 2000010c .word 0x2000010c
|
|
800105c: 20000110 .word 0x20000110
|
|
8001060: 002c01a0 .word 0x002c01a0
|
|
8001064: 0001f377 .word 0x0001f377
|
|
8001068: 20000158 .word 0x20000158
|
|
800106c: 20000108 .word 0x20000108
|
|
8001070: 20000154 .word 0x20000154
|
|
8001074: 20000003 .word 0x20000003
|
|
8001078: 20000002 .word 0x20000002
|
|
800107c: 20000008 .word 0x20000008
|
|
8001080: 20000004 .word 0x20000004
|
|
8001084: 2000011e .word 0x2000011e
|
|
8001088: 200012b4 .word 0x200012b4
|
|
800108c: 20000125 .word 0x20000125
|
|
8001090: 20000126 .word 0x20000126
|
|
8001094: 20000124 .word 0x20000124
|
|
8001098: 20000122 .word 0x20000122
|
|
800109c: 20000104 .word 0x20000104
|
|
80010a0: 20000120 .word 0x20000120
|
|
|
|
080010a4 <handle_vendor_options>:
|
|
{
|
|
80010a4: b570 push {r4, r5, r6, lr}
|
|
uint8_t command = options[0];
|
|
80010a6: 7803 ldrb r3, [r0, #0]
|
|
{
|
|
80010a8: 000c movs r4, r1
|
|
if (command <= 0x0F)
|
|
80010aa: 2b0f cmp r3, #15
|
|
80010ac: d80e bhi.n 80010cc <handle_vendor_options+0x28>
|
|
size_t start_index = command * VENDOR_SPECIFIC_OPTIONS_LENGTH;
|
|
80010ae: 2214 movs r2, #20
|
|
80010b0: 4353 muls r3, r2
|
|
if (start_index < version_len)
|
|
80010b2: 2b08 cmp r3, #8
|
|
80010b4: dc1a bgt.n 80010ec <handle_vendor_options+0x48>
|
|
size_t remaining = version_len - start_index;
|
|
80010b6: 2509 movs r5, #9
|
|
memcpy(response, VERSION_STRING + start_index, copy_len);
|
|
80010b8: 490f ldr r1, [pc, #60] @ (80010f8 <handle_vendor_options+0x54>)
|
|
size_t remaining = version_len - start_index;
|
|
80010ba: 1aed subs r5, r5, r3
|
|
memcpy(response, VERSION_STRING + start_index, copy_len);
|
|
80010bc: 1859 adds r1, r3, r1
|
|
80010be: 002a movs r2, r5
|
|
80010c0: 0020 movs r0, r4
|
|
80010c2: f004 f909 bl 80052d8 <memcpy>
|
|
response[copy_len] = '\0';
|
|
80010c6: 2300 movs r3, #0
|
|
80010c8: 5563 strb r3, [r4, r5]
|
|
}
|
|
80010ca: bd70 pop {r4, r5, r6, pc}
|
|
switch (command)
|
|
80010cc: 2b10 cmp r3, #16
|
|
80010ce: d10c bne.n 80010ea <handle_vendor_options+0x46>
|
|
uint8_t led_mask = options[1];
|
|
80010d0: 7840 ldrb r0, [r0, #1]
|
|
if (set)
|
|
80010d2: 0702 lsls r2, r0, #28
|
|
80010d4: d5f9 bpl.n 80010ca <handle_vendor_options+0x26>
|
|
set_LED(red, green, blue);
|
|
80010d6: 2401 movs r4, #1
|
|
80010d8: 0002 movs r2, r0
|
|
int green = (led_mask >> 1) & 1;
|
|
80010da: 0841 lsrs r1, r0, #1
|
|
int red = (led_mask >> 2) & 1;
|
|
80010dc: 0880 lsrs r0, r0, #2
|
|
set_LED(red, green, blue);
|
|
80010de: 4022 ands r2, r4
|
|
80010e0: 4021 ands r1, r4
|
|
80010e2: 4020 ands r0, r4
|
|
80010e4: f7ff fcda bl 8000a9c <set_LED>
|
|
80010e8: e7ef b.n 80010ca <handle_vendor_options+0x26>
|
|
memset(response, 0, VENDOR_SPECIFIC_OPTIONS_LENGTH);
|
|
80010ea: 2214 movs r2, #20
|
|
80010ec: 2100 movs r1, #0
|
|
80010ee: 0020 movs r0, r4
|
|
80010f0: f004 f8c6 bl 8005280 <memset>
|
|
break;
|
|
80010f4: e7e9 b.n 80010ca <handle_vendor_options+0x26>
|
|
80010f6: 46c0 nop @ (mov r8, r8)
|
|
80010f8: 08005315 .word 0x08005315
|
|
|
|
080010fc <onewire_delay_us>:
|
|
uint32_t cycles = us * 48;
|
|
80010fc: 2330 movs r3, #48 @ 0x30
|
|
80010fe: 4358 muls r0, r3
|
|
uint32_t elapsed = 0;
|
|
8001100: 2300 movs r3, #0
|
|
{
|
|
8001102: b570 push {r4, r5, r6, lr}
|
|
uint32_t reload = SysTick->LOAD;
|
|
8001104: 4c08 ldr r4, [pc, #32] @ (8001128 <onewire_delay_us+0x2c>)
|
|
8001106: 6865 ldr r5, [r4, #4]
|
|
uint32_t prev = SysTick->VAL;
|
|
8001108: 68a2 ldr r2, [r4, #8]
|
|
elapsed += prev + reload + 1 - now;
|
|
800110a: 3501 adds r5, #1
|
|
while (elapsed < cycles)
|
|
800110c: 4283 cmp r3, r0
|
|
800110e: d300 bcc.n 8001112 <onewire_delay_us+0x16>
|
|
}
|
|
8001110: bd70 pop {r4, r5, r6, pc}
|
|
uint32_t now = SysTick->VAL;
|
|
8001112: 68a1 ldr r1, [r4, #8]
|
|
if (now <= prev)
|
|
8001114: 428a cmp r2, r1
|
|
8001116: d303 bcc.n 8001120 <onewire_delay_us+0x24>
|
|
elapsed += prev - now;
|
|
8001118: 18d3 adds r3, r2, r3
|
|
800111a: 1a5b subs r3, r3, r1
|
|
{
|
|
800111c: 000a movs r2, r1
|
|
800111e: e7f5 b.n 800110c <onewire_delay_us+0x10>
|
|
elapsed += prev + reload + 1 - now;
|
|
8001120: 1a6e subs r6, r5, r1
|
|
8001122: 18b2 adds r2, r6, r2
|
|
8001124: 189b adds r3, r3, r2
|
|
8001126: e7f9 b.n 800111c <onewire_delay_us+0x20>
|
|
8001128: e000e010 .word 0xe000e010
|
|
|
|
0800112c <onewire_read_bit>:
|
|
return (ONEWIRE_GPIO_Port->IDR & ONEWIRE_Pin) ? 1 : 0;
|
|
800112c: 23a0 movs r3, #160 @ 0xa0
|
|
800112e: 05db lsls r3, r3, #23
|
|
8001130: 6918 ldr r0, [r3, #16]
|
|
8001132: 0640 lsls r0, r0, #25
|
|
8001134: 0fc0 lsrs r0, r0, #31
|
|
}
|
|
8001136: 4770 bx lr
|
|
|
|
08001138 <onewire_reset>:
|
|
{
|
|
8001138: b570 push {r4, r5, r6, lr}
|
|
ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
|
|
800113a: 24a0 movs r4, #160 @ 0xa0
|
|
800113c: 2540 movs r5, #64 @ 0x40
|
|
onewire_delay_us(ONEWIRE_DELAY_H); // 480us
|
|
800113e: 20f0 movs r0, #240 @ 0xf0
|
|
ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
|
|
8001140: 05e4 lsls r4, r4, #23
|
|
8001142: 62a5 str r5, [r4, #40] @ 0x28
|
|
onewire_delay_us(ONEWIRE_DELAY_H); // 480us
|
|
8001144: 0040 lsls r0, r0, #1
|
|
8001146: f7ff ffd9 bl 80010fc <onewire_delay_us>
|
|
ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
|
|
800114a: 61a5 str r5, [r4, #24]
|
|
onewire_delay_us(ONEWIRE_DELAY_I); // 70us
|
|
800114c: 2046 movs r0, #70 @ 0x46
|
|
800114e: f7ff ffd5 bl 80010fc <onewire_delay_us>
|
|
presence = !onewire_read_bit(); // Device pulls low if present
|
|
8001152: f7ff ffeb bl 800112c <onewire_read_bit>
|
|
8001156: 0004 movs r4, r0
|
|
onewire_delay_us(ONEWIRE_DELAY_J); // 410us
|
|
8001158: 20cd movs r0, #205 @ 0xcd
|
|
800115a: 0040 lsls r0, r0, #1
|
|
800115c: f7ff ffce bl 80010fc <onewire_delay_us>
|
|
return presence;
|
|
8001160: 2001 movs r0, #1
|
|
8001162: 4060 eors r0, r4
|
|
8001164: b2c0 uxtb r0, r0
|
|
}
|
|
8001166: bd70 pop {r4, r5, r6, pc}
|
|
|
|
08001168 <onewire_write_bit>:
|
|
{
|
|
8001168: b570 push {r4, r5, r6, lr}
|
|
800116a: 25a0 movs r5, #160 @ 0xa0
|
|
800116c: 2440 movs r4, #64 @ 0x40
|
|
800116e: 05ed lsls r5, r5, #23
|
|
ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
|
|
8001170: 62ac str r4, [r5, #40] @ 0x28
|
|
if (bit)
|
|
8001172: 2800 cmp r0, #0
|
|
8001174: d007 beq.n 8001186 <onewire_write_bit+0x1e>
|
|
onewire_delay_us(ONEWIRE_DELAY_A); // 6us
|
|
8001176: 2006 movs r0, #6
|
|
8001178: f7ff ffc0 bl 80010fc <onewire_delay_us>
|
|
onewire_delay_us(ONEWIRE_DELAY_B); // 64us
|
|
800117c: 0020 movs r0, r4
|
|
ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
|
|
800117e: 61ac str r4, [r5, #24]
|
|
onewire_delay_us(ONEWIRE_DELAY_D); // 10us
|
|
8001180: f7ff ffbc bl 80010fc <onewire_delay_us>
|
|
}
|
|
8001184: bd70 pop {r4, r5, r6, pc}
|
|
onewire_delay_us(ONEWIRE_DELAY_C); // 60us
|
|
8001186: 203c movs r0, #60 @ 0x3c
|
|
8001188: f7ff ffb8 bl 80010fc <onewire_delay_us>
|
|
onewire_delay_us(ONEWIRE_DELAY_D); // 10us
|
|
800118c: 200a movs r0, #10
|
|
ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
|
|
800118e: 61ac str r4, [r5, #24]
|
|
onewire_delay_us(ONEWIRE_DELAY_D); // 10us
|
|
8001190: e7f6 b.n 8001180 <onewire_write_bit+0x18>
|
|
|
|
08001192 <onewire_read_bit_slot>:
|
|
{
|
|
8001192: b570 push {r4, r5, r6, lr}
|
|
ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
|
|
8001194: 24a0 movs r4, #160 @ 0xa0
|
|
8001196: 2540 movs r5, #64 @ 0x40
|
|
8001198: 05e4 lsls r4, r4, #23
|
|
800119a: 62a5 str r5, [r4, #40] @ 0x28
|
|
onewire_delay_us(ONEWIRE_DELAY_A); // 6us
|
|
800119c: 2006 movs r0, #6
|
|
800119e: f7ff ffad bl 80010fc <onewire_delay_us>
|
|
ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
|
|
80011a2: 61a5 str r5, [r4, #24]
|
|
onewire_delay_us(ONEWIRE_DELAY_E); // 9us
|
|
80011a4: 2009 movs r0, #9
|
|
80011a6: f7ff ffa9 bl 80010fc <onewire_delay_us>
|
|
bit = onewire_read_bit();
|
|
80011aa: f7ff ffbf bl 800112c <onewire_read_bit>
|
|
80011ae: 0004 movs r4, r0
|
|
onewire_delay_us(ONEWIRE_DELAY_F); // 55us
|
|
80011b0: 2037 movs r0, #55 @ 0x37
|
|
80011b2: f7ff ffa3 bl 80010fc <onewire_delay_us>
|
|
}
|
|
80011b6: 0020 movs r0, r4
|
|
80011b8: bd70 pop {r4, r5, r6, pc}
|
|
|
|
080011ba <onewire_write_byte>:
|
|
{
|
|
80011ba: b570 push {r4, r5, r6, lr}
|
|
80011bc: 0004 movs r4, r0
|
|
80011be: 2508 movs r5, #8
|
|
onewire_write_bit(byte & 0x01);
|
|
80011c0: 2601 movs r6, #1
|
|
80011c2: 0020 movs r0, r4
|
|
for (int i = 0; i < 8; i++)
|
|
80011c4: 3d01 subs r5, #1
|
|
onewire_write_bit(byte & 0x01);
|
|
80011c6: 4030 ands r0, r6
|
|
80011c8: f7ff ffce bl 8001168 <onewire_write_bit>
|
|
byte >>= 1;
|
|
80011cc: 0864 lsrs r4, r4, #1
|
|
for (int i = 0; i < 8; i++)
|
|
80011ce: 2d00 cmp r5, #0
|
|
80011d0: d1f7 bne.n 80011c2 <onewire_write_byte+0x8>
|
|
}
|
|
80011d2: bd70 pop {r4, r5, r6, pc}
|
|
|
|
080011d4 <onewire_read_byte>:
|
|
{
|
|
80011d4: b570 push {r4, r5, r6, lr}
|
|
80011d6: 2508 movs r5, #8
|
|
uint8_t byte = 0;
|
|
80011d8: 2400 movs r4, #0
|
|
if (onewire_read_bit_slot())
|
|
80011da: 267f movs r6, #127 @ 0x7f
|
|
80011dc: f7ff ffd9 bl 8001192 <onewire_read_bit_slot>
|
|
80011e0: 4240 negs r0, r0
|
|
byte >>= 1;
|
|
80011e2: 0864 lsrs r4, r4, #1
|
|
if (onewire_read_bit_slot())
|
|
80011e4: 43b0 bics r0, r6
|
|
80011e6: 4304 orrs r4, r0
|
|
for (int i = 0; i < 8; i++)
|
|
80011e8: 3d01 subs r5, #1
|
|
if (onewire_read_bit_slot())
|
|
80011ea: b2e4 uxtb r4, r4
|
|
for (int i = 0; i < 8; i++)
|
|
80011ec: 2d00 cmp r5, #0
|
|
80011ee: d1f5 bne.n 80011dc <onewire_read_byte+0x8>
|
|
}
|
|
80011f0: 0020 movs r0, r4
|
|
80011f2: bd70 pop {r4, r5, r6, pc}
|
|
|
|
080011f4 <read_floor_address>:
|
|
{
|
|
80011f4: b510 push {r4, lr}
|
|
80011f6: b672 cpsid i
|
|
if (!onewire_reset())
|
|
80011f8: f7ff ff9e bl 8001138 <onewire_reset>
|
|
80011fc: 2800 cmp r0, #0
|
|
80011fe: d102 bne.n 8001206 <read_floor_address+0x12>
|
|
__ASM volatile ("cpsie i" : : : "memory");
|
|
8001200: b662 cpsie i
|
|
return FLOOR_ADDRESS_NOT_DETECTED;
|
|
8001202: 30ff adds r0, #255 @ 0xff
|
|
}
|
|
8001204: bd10 pop {r4, pc}
|
|
onewire_write_byte(DS2431_SKIP_ROM);
|
|
8001206: 20cc movs r0, #204 @ 0xcc
|
|
8001208: f7ff ffd7 bl 80011ba <onewire_write_byte>
|
|
onewire_write_byte(DS2431_READ_MEMORY);
|
|
800120c: 20f0 movs r0, #240 @ 0xf0
|
|
800120e: f7ff ffd4 bl 80011ba <onewire_write_byte>
|
|
onewire_write_byte(FLOOR_ADDRESS_LOCATION & 0xFF);
|
|
8001212: 2000 movs r0, #0
|
|
8001214: f7ff ffd1 bl 80011ba <onewire_write_byte>
|
|
onewire_write_byte((FLOOR_ADDRESS_LOCATION >> 8) & 0xFF);
|
|
8001218: 2000 movs r0, #0
|
|
800121a: f7ff ffce bl 80011ba <onewire_write_byte>
|
|
uint8_t address = onewire_read_byte();
|
|
800121e: f7ff ffd9 bl 80011d4 <onewire_read_byte>
|
|
8001222: b662 cpsie i
|
|
return address;
|
|
8001224: e7ee b.n 8001204 <read_floor_address+0x10>
|
|
|
|
08001226 <write_floor_address>:
|
|
{
|
|
8001226: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8001228: 0004 movs r4, r0
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
800122a: b672 cpsid i
|
|
if (!onewire_reset())
|
|
800122c: f7ff ff84 bl 8001138 <onewire_reset>
|
|
8001230: 2800 cmp r0, #0
|
|
8001232: d102 bne.n 800123a <write_floor_address+0x14>
|
|
__ASM volatile ("cpsie i" : : : "memory");
|
|
8001234: b662 cpsie i
|
|
return 0; // Device not present
|
|
8001236: 2000 movs r0, #0
|
|
}
|
|
8001238: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
onewire_write_byte(DS2431_SKIP_ROM);
|
|
800123a: 20cc movs r0, #204 @ 0xcc
|
|
800123c: f7ff ffbd bl 80011ba <onewire_write_byte>
|
|
onewire_write_byte(DS2431_WRITE_SCRATCHPAD);
|
|
8001240: 200f movs r0, #15
|
|
8001242: f7ff ffba bl 80011ba <onewire_write_byte>
|
|
onewire_write_byte(FLOOR_ADDRESS_LOCATION & 0xFF);
|
|
8001246: 2000 movs r0, #0
|
|
8001248: f7ff ffb7 bl 80011ba <onewire_write_byte>
|
|
onewire_write_byte((FLOOR_ADDRESS_LOCATION >> 8) & 0xFF);
|
|
800124c: 2000 movs r0, #0
|
|
800124e: f7ff ffb4 bl 80011ba <onewire_write_byte>
|
|
onewire_write_byte(address);
|
|
8001252: 0020 movs r0, r4
|
|
8001254: f7ff ffb1 bl 80011ba <onewire_write_byte>
|
|
8001258: 2507 movs r5, #7
|
|
onewire_write_byte(0xFF); // Pad with 0xFF
|
|
800125a: 20ff movs r0, #255 @ 0xff
|
|
for (int i = 1; i < 8; i++)
|
|
800125c: 3d01 subs r5, #1
|
|
onewire_write_byte(0xFF); // Pad with 0xFF
|
|
800125e: f7ff ffac bl 80011ba <onewire_write_byte>
|
|
for (int i = 1; i < 8; i++)
|
|
8001262: 2d00 cmp r5, #0
|
|
8001264: d1f9 bne.n 800125a <write_floor_address+0x34>
|
|
onewire_delay_us(100);
|
|
8001266: 2064 movs r0, #100 @ 0x64
|
|
8001268: f7ff ff48 bl 80010fc <onewire_delay_us>
|
|
if (!onewire_reset())
|
|
800126c: f7ff ff64 bl 8001138 <onewire_reset>
|
|
8001270: 2800 cmp r0, #0
|
|
8001272: d0df beq.n 8001234 <write_floor_address+0xe>
|
|
onewire_write_byte(DS2431_SKIP_ROM);
|
|
8001274: 20cc movs r0, #204 @ 0xcc
|
|
8001276: f7ff ffa0 bl 80011ba <onewire_write_byte>
|
|
onewire_write_byte(DS2431_READ_SCRATCHPAD);
|
|
800127a: 20aa movs r0, #170 @ 0xaa
|
|
800127c: f7ff ff9d bl 80011ba <onewire_write_byte>
|
|
uint8_t ta1 = onewire_read_byte(); // Target address 1
|
|
8001280: f7ff ffa8 bl 80011d4 <onewire_read_byte>
|
|
8001284: 0007 movs r7, r0
|
|
uint8_t ta2 = onewire_read_byte(); // Target address 2
|
|
8001286: f7ff ffa5 bl 80011d4 <onewire_read_byte>
|
|
800128a: 0006 movs r6, r0
|
|
uint8_t es = onewire_read_byte(); // E/S register
|
|
800128c: f7ff ffa2 bl 80011d4 <onewire_read_byte>
|
|
8001290: 0005 movs r5, r0
|
|
uint8_t verify = onewire_read_byte();
|
|
8001292: f7ff ff9f bl 80011d4 <onewire_read_byte>
|
|
if (verify != address)
|
|
8001296: 4284 cmp r4, r0
|
|
8001298: d1cc bne.n 8001234 <write_floor_address+0xe>
|
|
onewire_read_byte();
|
|
800129a: f7ff ff9b bl 80011d4 <onewire_read_byte>
|
|
800129e: f7ff ff99 bl 80011d4 <onewire_read_byte>
|
|
80012a2: f7ff ff97 bl 80011d4 <onewire_read_byte>
|
|
80012a6: f7ff ff95 bl 80011d4 <onewire_read_byte>
|
|
80012aa: f7ff ff93 bl 80011d4 <onewire_read_byte>
|
|
80012ae: f7ff ff91 bl 80011d4 <onewire_read_byte>
|
|
80012b2: f7ff ff8f bl 80011d4 <onewire_read_byte>
|
|
if (!onewire_reset())
|
|
80012b6: f7ff ff3f bl 8001138 <onewire_reset>
|
|
80012ba: 2800 cmp r0, #0
|
|
80012bc: d0ba beq.n 8001234 <write_floor_address+0xe>
|
|
onewire_write_byte(DS2431_SKIP_ROM);
|
|
80012be: 20cc movs r0, #204 @ 0xcc
|
|
80012c0: f7ff ff7b bl 80011ba <onewire_write_byte>
|
|
onewire_write_byte(DS2431_COPY_SCRATCHPAD);
|
|
80012c4: 2055 movs r0, #85 @ 0x55
|
|
80012c6: f7ff ff78 bl 80011ba <onewire_write_byte>
|
|
onewire_write_byte(ta1);
|
|
80012ca: 0038 movs r0, r7
|
|
80012cc: f7ff ff75 bl 80011ba <onewire_write_byte>
|
|
onewire_write_byte(ta2);
|
|
80012d0: 0030 movs r0, r6
|
|
80012d2: f7ff ff72 bl 80011ba <onewire_write_byte>
|
|
onewire_write_byte(es);
|
|
80012d6: 0028 movs r0, r5
|
|
80012d8: f7ff ff6f bl 80011ba <onewire_write_byte>
|
|
80012dc: b662 cpsie i
|
|
HAL_Delay(15);
|
|
80012de: 200f movs r0, #15
|
|
80012e0: f001 fb1c bl 800291c <HAL_Delay>
|
|
uint8_t read_back = read_floor_address();
|
|
80012e4: f7ff ff86 bl 80011f4 <read_floor_address>
|
|
return (read_back == address) ? 1 : 0;
|
|
80012e8: 1a20 subs r0, r4, r0
|
|
80012ea: 4243 negs r3, r0
|
|
80012ec: 4158 adcs r0, r3
|
|
80012ee: b2c0 uxtb r0, r0
|
|
80012f0: e7a2 b.n 8001238 <write_floor_address+0x12>
|
|
...
|
|
|
|
080012f4 <handleRS485Message>:
|
|
{
|
|
80012f4: b5f0 push {r4, r5, r6, r7, lr}
|
|
last_rx_size = size;
|
|
80012f6: 4bbb ldr r3, [pc, #748] @ (80015e4 <handleRS485Message+0x2f0>)
|
|
{
|
|
80012f8: b08b sub sp, #44 @ 0x2c
|
|
last_rx_size = size;
|
|
80012fa: 7019 strb r1, [r3, #0]
|
|
80012fc: 2300 movs r3, #0
|
|
{
|
|
80012fe: 0005 movs r5, r0
|
|
for (uint8_t i = 0; i < 8 && i < size; i++) last_rx_bytes[i] = buffer[i];
|
|
8001300: 48b9 ldr r0, [pc, #740] @ (80015e8 <handleRS485Message+0x2f4>)
|
|
8001302: b2da uxtb r2, r3
|
|
8001304: 4291 cmp r1, r2
|
|
8001306: d807 bhi.n 8001318 <handleRS485Message+0x24>
|
|
if (size >= 1 && buffer[0] == my_address)
|
|
8001308: 2900 cmp r1, #0
|
|
800130a: d10a bne.n 8001322 <handleRS485Message+0x2e>
|
|
drop_size++;
|
|
800130c: 4ab7 ldr r2, [pc, #732] @ (80015ec <handleRS485Message+0x2f8>)
|
|
drop_addr++;
|
|
800130e: 8813 ldrh r3, [r2, #0]
|
|
8001310: 3301 adds r3, #1
|
|
8001312: b29b uxth r3, r3
|
|
8001314: 8013 strh r3, [r2, #0]
|
|
return; // message not for us
|
|
8001316: e036 b.n 8001386 <handleRS485Message+0x92>
|
|
for (uint8_t i = 0; i < 8 && i < size; i++) last_rx_bytes[i] = buffer[i];
|
|
8001318: 5cea ldrb r2, [r5, r3]
|
|
800131a: 54c2 strb r2, [r0, r3]
|
|
800131c: 3301 adds r3, #1
|
|
800131e: 2b08 cmp r3, #8
|
|
8001320: d1ef bne.n 8001302 <handleRS485Message+0xe>
|
|
if (size >= 1 && buffer[0] == my_address)
|
|
8001322: 4fb3 ldr r7, [pc, #716] @ (80015f0 <handleRS485Message+0x2fc>)
|
|
8001324: 782a ldrb r2, [r5, #0]
|
|
8001326: 783b ldrb r3, [r7, #0]
|
|
8001328: 429a cmp r2, r3
|
|
800132a: d02e beq.n 800138a <handleRS485Message+0x96>
|
|
if (size < sizeof(PhotonPacketHeader) + 1) // header + at least commandId
|
|
800132c: 2905 cmp r1, #5
|
|
800132e: d9ed bls.n 800130c <handleRS485Message+0x18>
|
|
uint32_t crc;
|
|
} CRC8_107;
|
|
|
|
static inline void CRC8_107_init(CRC8_107 *ctx)
|
|
{
|
|
ctx->crc = 0x0u;
|
|
8001330: 2400 movs r4, #0
|
|
last_rx_to = header->toAddress;
|
|
8001332: 4bb0 ldr r3, [pc, #704] @ (80015f4 <handleRS485Message+0x300>)
|
|
8001334: 7829 ldrb r1, [r5, #0]
|
|
CRC8_107_add(&rx_crc, header->toAddress);
|
|
8001336: a801 add r0, sp, #4
|
|
last_rx_to = header->toAddress;
|
|
8001338: 7019 strb r1, [r3, #0]
|
|
800133a: 9401 str r4, [sp, #4]
|
|
CRC8_107_add(&rx_crc, header->toAddress);
|
|
800133c: f7ff fa06 bl 800074c <CRC8_107_add>
|
|
CRC8_107_add(&rx_crc, header->fromAddress);
|
|
8001340: 7869 ldrb r1, [r5, #1]
|
|
8001342: a801 add r0, sp, #4
|
|
8001344: f7ff fa02 bl 800074c <CRC8_107_add>
|
|
CRC8_107_add(&rx_crc, header->packetId);
|
|
8001348: 78a9 ldrb r1, [r5, #2]
|
|
800134a: a801 add r0, sp, #4
|
|
800134c: f7ff f9fe bl 800074c <CRC8_107_add>
|
|
CRC8_107_add(&rx_crc, header->payloadLength);
|
|
8001350: 78e9 ldrb r1, [r5, #3]
|
|
8001352: a801 add r0, sp, #4
|
|
8001354: f7ff f9fa bl 800074c <CRC8_107_add>
|
|
for (uint8_t i = 0; i < header->payloadLength; i++)
|
|
8001358: 78eb ldrb r3, [r5, #3]
|
|
800135a: 42a3 cmp r3, r4
|
|
800135c: d822 bhi.n 80013a4 <handleRS485Message+0xb0>
|
|
if (CRC8_107_getChecksum(&rx_crc) != header->crc)
|
|
800135e: a801 add r0, sp, #4
|
|
8001360: f7ff fa08 bl 8000774 <CRC8_107_getChecksum>
|
|
8001364: 792b ldrb r3, [r5, #4]
|
|
if (header->toAddress == my_address)
|
|
8001366: 782c ldrb r4, [r5, #0]
|
|
8001368: 783a ldrb r2, [r7, #0]
|
|
if (CRC8_107_getChecksum(&rx_crc) != header->crc)
|
|
800136a: 4283 cmp r3, r0
|
|
800136c: d022 beq.n 80013b4 <handleRS485Message+0xc0>
|
|
drop_crc++;
|
|
800136e: 49a2 ldr r1, [pc, #648] @ (80015f8 <handleRS485Message+0x304>)
|
|
8001370: 880b ldrh r3, [r1, #0]
|
|
8001372: 3301 adds r3, #1
|
|
8001374: b29b uxth r3, r3
|
|
8001376: 800b strh r3, [r1, #0]
|
|
if (header->toAddress == my_address)
|
|
8001378: 4294 cmp r4, r2
|
|
800137a: d104 bne.n 8001386 <handleRS485Message+0x92>
|
|
my_addr_crc_exp = CRC8_107_getChecksum(&rx_crc);
|
|
800137c: a801 add r0, sp, #4
|
|
800137e: f7ff f9f9 bl 8000774 <CRC8_107_getChecksum>
|
|
8001382: 4b9e ldr r3, [pc, #632] @ (80015fc <handleRS485Message+0x308>)
|
|
8001384: 7018 strb r0, [r3, #0]
|
|
}
|
|
8001386: b00b add sp, #44 @ 0x2c
|
|
8001388: bdf0 pop {r4, r5, r6, r7, pc}
|
|
my_addr_size = size;
|
|
800138a: 4b9d ldr r3, [pc, #628] @ (8001600 <handleRS485Message+0x30c>)
|
|
for (uint8_t i = 0; i < 8 && i < size; i++) my_addr_bytes[i] = buffer[i];
|
|
800138c: 489d ldr r0, [pc, #628] @ (8001604 <handleRS485Message+0x310>)
|
|
my_addr_size = size;
|
|
800138e: 7019 strb r1, [r3, #0]
|
|
8001390: 2300 movs r3, #0
|
|
for (uint8_t i = 0; i < 8 && i < size; i++) my_addr_bytes[i] = buffer[i];
|
|
8001392: 5cea ldrb r2, [r5, r3]
|
|
8001394: 54c2 strb r2, [r0, r3]
|
|
8001396: 2b07 cmp r3, #7
|
|
8001398: d0c8 beq.n 800132c <handleRS485Message+0x38>
|
|
800139a: 3301 adds r3, #1
|
|
800139c: b2da uxtb r2, r3
|
|
800139e: 428a cmp r2, r1
|
|
80013a0: d3f7 bcc.n 8001392 <handleRS485Message+0x9e>
|
|
80013a2: e7c3 b.n 800132c <handleRS485Message+0x38>
|
|
CRC8_107_add(&rx_crc, buffer[sizeof(PhotonPacketHeader) + i]);
|
|
80013a4: 192b adds r3, r5, r4
|
|
80013a6: 7959 ldrb r1, [r3, #5]
|
|
80013a8: a801 add r0, sp, #4
|
|
for (uint8_t i = 0; i < header->payloadLength; i++)
|
|
80013aa: 3401 adds r4, #1
|
|
CRC8_107_add(&rx_crc, buffer[sizeof(PhotonPacketHeader) + i]);
|
|
80013ac: f7ff f9ce bl 800074c <CRC8_107_add>
|
|
for (uint8_t i = 0; i < header->payloadLength; i++)
|
|
80013b0: b2e4 uxtb r4, r4
|
|
80013b2: e7d1 b.n 8001358 <handleRS485Message+0x64>
|
|
if ((header->toAddress != PHOTON_NETWORK_BROADCAST_ADDRESS) &&
|
|
80013b4: 2cff cmp r4, #255 @ 0xff
|
|
80013b6: d003 beq.n 80013c0 <handleRS485Message+0xcc>
|
|
80013b8: 4294 cmp r4, r2
|
|
80013ba: d001 beq.n 80013c0 <handleRS485Message+0xcc>
|
|
drop_addr++;
|
|
80013bc: 4a92 ldr r2, [pc, #584] @ (8001608 <handleRS485Message+0x314>)
|
|
80013be: e7a6 b.n 800130e <handleRS485Message+0x1a>
|
|
80013c0: 2600 movs r6, #0
|
|
msg_handled++;
|
|
80013c2: 4992 ldr r1, [pc, #584] @ (800160c <handleRS485Message+0x318>)
|
|
last_rx_cmd = buffer[sizeof(PhotonPacketHeader)]; // commandId
|
|
80013c4: 7968 ldrb r0, [r5, #5]
|
|
msg_handled++;
|
|
80013c6: 880b ldrh r3, [r1, #0]
|
|
response.header.fromAddress = my_address;
|
|
80013c8: ac03 add r4, sp, #12
|
|
msg_handled++;
|
|
80013ca: 3301 adds r3, #1
|
|
80013cc: b29b uxth r3, r3
|
|
80013ce: 800b strh r3, [r1, #0]
|
|
last_rx_cmd = buffer[sizeof(PhotonPacketHeader)]; // commandId
|
|
80013d0: 4b8f ldr r3, [pc, #572] @ (8001610 <handleRS485Message+0x31c>)
|
|
80013d2: 9602 str r6, [sp, #8]
|
|
80013d4: 7018 strb r0, [r3, #0]
|
|
response.header.fromAddress = my_address;
|
|
80013d6: 7062 strb r2, [r4, #1]
|
|
response.header.packetId = command->header.packetId;
|
|
80013d8: 78ab ldrb r3, [r5, #2]
|
|
80013da: 70a3 strb r3, [r4, #2]
|
|
response.header.toAddress = command->header.fromAddress;
|
|
80013dc: 786b ldrb r3, [r5, #1]
|
|
80013de: 7023 strb r3, [r4, #0]
|
|
switch (command->commandId)
|
|
80013e0: 2806 cmp r0, #6
|
|
80013e2: d809 bhi.n 80013f8 <handleRS485Message+0x104>
|
|
80013e4: 42b0 cmp r0, r6
|
|
80013e6: d0ce beq.n 8001386 <handleRS485Message+0x92>
|
|
80013e8: 3802 subs r0, #2
|
|
80013ea: 2804 cmp r0, #4
|
|
80013ec: d813 bhi.n 8001416 <handleRS485Message+0x122>
|
|
80013ee: f7fe fe8b bl 8000108 <__gnu_thumb1_case_uqi>
|
|
80013f2: 5430 .short 0x5430
|
|
80013f4: aa68 .short 0xaa68
|
|
80013f6: f0 .byte 0xf0
|
|
80013f7: 00 .byte 0x00
|
|
80013f8: 0003 movs r3, r0
|
|
80013fa: 3341 adds r3, #65 @ 0x41
|
|
80013fc: b2db uxtb r3, r3
|
|
80013fe: 2b04 cmp r3, #4
|
|
8001400: d8c1 bhi.n 8001386 <handleRS485Message+0x92>
|
|
8001402: 38c0 subs r0, #192 @ 0xc0
|
|
8001404: 2803 cmp r0, #3
|
|
8001406: d900 bls.n 800140a <handleRS485Message+0x116>
|
|
8001408: e10c b.n 8001624 <handleRS485Message+0x330>
|
|
800140a: f7fe fe87 bl 800011c <__gnu_thumb1_case_uhi>
|
|
800140e: 0146 .short 0x0146
|
|
8001410: 0179015a .word 0x0179015a
|
|
8001414: 0189 .short 0x0189
|
|
memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH);
|
|
8001416: 2012 movs r0, #18
|
|
8001418: 497e ldr r1, [pc, #504] @ (8001614 <handleRS485Message+0x320>)
|
|
800141a: 220c movs r2, #12
|
|
800141c: 4468 add r0, sp
|
|
800141e: f003 ff5b bl 80052d8 <memcpy>
|
|
response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for status byte
|
|
8001422: 230d movs r3, #13
|
|
comp_crc_header(&crc,&response);
|
|
8001424: 0021 movs r1, r4
|
|
8001426: a802 add r0, sp, #8
|
|
response.status = STATUS_OK;
|
|
8001428: 7166 strb r6, [r4, #5]
|
|
response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for status byte
|
|
800142a: 70e3 strb r3, [r4, #3]
|
|
comp_crc_header(&crc,&response);
|
|
800142c: f7ff fb80 bl 8000b30 <comp_crc_header>
|
|
for (uint32_t i = 0; i<response.header.payloadLength; i++)
|
|
8001430: 78e3 ldrb r3, [r4, #3]
|
|
8001432: 42b3 cmp r3, r6
|
|
8001434: d806 bhi.n 8001444 <handleRS485Message+0x150>
|
|
response.header.crc = CRC8_107_getChecksum(&crc);
|
|
8001436: a802 add r0, sp, #8
|
|
8001438: f7ff f99c bl 8000774 <CRC8_107_getChecksum>
|
|
packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
|
|
800143c: 78e1 ldrb r1, [r4, #3]
|
|
response.header.crc = CRC8_107_getChecksum(&crc);
|
|
800143e: 7120 strb r0, [r4, #4]
|
|
rs485_transmit((uint8_t *)&response, packet_len);
|
|
8001440: 3105 adds r1, #5
|
|
8001442: e126 b.n 8001692 <handleRS485Message+0x39e>
|
|
CRC8_107_add(&crc,*(payload_ptr+i));
|
|
8001444: 19a3 adds r3, r4, r6
|
|
8001446: 7959 ldrb r1, [r3, #5]
|
|
8001448: a802 add r0, sp, #8
|
|
800144a: f7ff f97f bl 800074c <CRC8_107_add>
|
|
for (uint32_t i = 0; i<response.header.payloadLength; i++)
|
|
800144e: 3601 adds r6, #1
|
|
8001450: e7ee b.n 8001430 <handleRS485Message+0x13c>
|
|
memcpy(response.payload.initializeFeeder.uuid,UUID,UUID_LENGTH);
|
|
8001452: 2012 movs r0, #18
|
|
8001454: 4e6f ldr r6, [pc, #444] @ (8001614 <handleRS485Message+0x320>)
|
|
8001456: 220c movs r2, #12
|
|
8001458: 0031 movs r1, r6
|
|
800145a: 4468 add r0, sp
|
|
800145c: f003 ff3c bl 80052d8 <memcpy>
|
|
if(memcmp(UUID,command->payload.initializeFeeder.uuid,UUID_LENGTH) == 0)
|
|
8001460: 220c movs r2, #12
|
|
8001462: 0030 movs r0, r6
|
|
8001464: 1da9 adds r1, r5, #6
|
|
8001466: f003 fefd bl 8005264 <memcmp>
|
|
800146a: 2301 movs r3, #1
|
|
800146c: 2800 cmp r0, #0
|
|
800146e: d102 bne.n 8001476 <handleRS485Message+0x182>
|
|
is_initialized = 1;
|
|
8001470: 4a69 ldr r2, [pc, #420] @ (8001618 <handleRS485Message+0x324>)
|
|
8001472: 7013 strb r3, [r2, #0]
|
|
response.status = STATUS_OK;
|
|
8001474: 0003 movs r3, r0
|
|
8001476: 7163 strb r3, [r4, #5]
|
|
response.header.payloadLength = sizeof(response.payload.initializeFeeder)+1;
|
|
8001478: 230d movs r3, #13
|
|
comp_crc_header(&crc,&response);
|
|
800147a: 0021 movs r1, r4
|
|
800147c: a802 add r0, sp, #8
|
|
response.header.payloadLength = sizeof(response.payload.initializeFeeder)+1;
|
|
800147e: 70e3 strb r3, [r4, #3]
|
|
for (uint32_t i = 0; i<response.header.payloadLength; i++)
|
|
8001480: 2500 movs r5, #0
|
|
comp_crc_header(&crc,&response);
|
|
8001482: f7ff fb55 bl 8000b30 <comp_crc_header>
|
|
for (uint32_t i = 0; i<response.header.payloadLength; i++)
|
|
8001486: 78e3 ldrb r3, [r4, #3]
|
|
8001488: 42ab cmp r3, r5
|
|
800148a: d9d4 bls.n 8001436 <handleRS485Message+0x142>
|
|
CRC8_107_add(&crc,*(payload_ptr+i));
|
|
800148c: 1963 adds r3, r4, r5
|
|
800148e: 7959 ldrb r1, [r3, #5]
|
|
8001490: a802 add r0, sp, #8
|
|
8001492: f7ff f95b bl 800074c <CRC8_107_add>
|
|
for (uint32_t i = 0; i<response.header.payloadLength; i++)
|
|
8001496: 3501 adds r5, #1
|
|
8001498: e7f5 b.n 8001486 <handleRS485Message+0x192>
|
|
response.payload.protocolVersion.version = PROTOCOL_VERSION;
|
|
800149a: 2301 movs r3, #1
|
|
response.status = STATUS_OK;
|
|
800149c: 2500 movs r5, #0
|
|
response.payload.protocolVersion.version = PROTOCOL_VERSION;
|
|
800149e: 71a3 strb r3, [r4, #6]
|
|
comp_crc_header(&crc,&response);
|
|
80014a0: 0021 movs r1, r4
|
|
response.header.payloadLength = sizeof(response.payload.protocolVersion)+1;
|
|
80014a2: 18db adds r3, r3, r3
|
|
comp_crc_header(&crc,&response);
|
|
80014a4: a802 add r0, sp, #8
|
|
response.status = STATUS_OK;
|
|
80014a6: 7165 strb r5, [r4, #5]
|
|
response.header.payloadLength = sizeof(response.payload.protocolVersion)+1;
|
|
80014a8: 70e3 strb r3, [r4, #3]
|
|
comp_crc_header(&crc,&response);
|
|
80014aa: f7ff fb41 bl 8000b30 <comp_crc_header>
|
|
for (uint32_t i = 0; i<response.header.payloadLength; i++)
|
|
80014ae: 78e3 ldrb r3, [r4, #3]
|
|
80014b0: 42ab cmp r3, r5
|
|
80014b2: d9c0 bls.n 8001436 <handleRS485Message+0x142>
|
|
CRC8_107_add(&crc,*(payload_ptr+i));
|
|
80014b4: 1963 adds r3, r4, r5
|
|
80014b6: 7959 ldrb r1, [r3, #5]
|
|
80014b8: a802 add r0, sp, #8
|
|
80014ba: f7ff f947 bl 800074c <CRC8_107_add>
|
|
for (uint32_t i = 0; i<response.header.payloadLength; i++)
|
|
80014be: 3501 adds r5, #1
|
|
80014c0: e7f5 b.n 80014ae <handleRS485Message+0x1ba>
|
|
if (!is_initialized)
|
|
80014c2: 4b55 ldr r3, [pc, #340] @ (8001618 <handleRS485Message+0x324>)
|
|
80014c4: 781e ldrb r6, [r3, #0]
|
|
80014c6: 2e00 cmp r6, #0
|
|
80014c8: d117 bne.n 80014fa <handleRS485Message+0x206>
|
|
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
|
|
80014ca: 2012 movs r0, #18
|
|
response.status = STATUS_UNINITIALIZED_FEEDER;
|
|
80014cc: 2303 movs r3, #3
|
|
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
|
|
80014ce: 4951 ldr r1, [pc, #324] @ (8001614 <handleRS485Message+0x320>)
|
|
80014d0: 220c movs r2, #12
|
|
80014d2: 4468 add r0, sp
|
|
response.status = STATUS_UNINITIALIZED_FEEDER;
|
|
80014d4: 7163 strb r3, [r4, #5]
|
|
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
|
|
80014d6: f003 feff bl 80052d8 <memcpy>
|
|
response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
|
|
80014da: 230d movs r3, #13
|
|
comp_crc_header(&crc, &response);
|
|
80014dc: 0021 movs r1, r4
|
|
80014de: a802 add r0, sp, #8
|
|
response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
|
|
80014e0: 70e3 strb r3, [r4, #3]
|
|
comp_crc_header(&crc, &response);
|
|
80014e2: f7ff fb25 bl 8000b30 <comp_crc_header>
|
|
for (uint32_t i = 0; i < response.header.payloadLength; i++)
|
|
80014e6: 78e3 ldrb r3, [r4, #3]
|
|
80014e8: 42b3 cmp r3, r6
|
|
80014ea: d9a4 bls.n 8001436 <handleRS485Message+0x142>
|
|
CRC8_107_add(&crc, *(payload_ptr + i));
|
|
80014ec: 19a3 adds r3, r4, r6
|
|
80014ee: 7959 ldrb r1, [r3, #5]
|
|
80014f0: a802 add r0, sp, #8
|
|
80014f2: f7ff f92b bl 800074c <CRC8_107_add>
|
|
for (uint32_t i = 0; i < response.header.payloadLength; i++)
|
|
80014f6: 3601 adds r6, #1
|
|
80014f8: e7f5 b.n 80014e6 <handleRS485Message+0x1f2>
|
|
PEEL_BACKOFF_TIME +
|
|
80014fa: 221c movs r2, #28
|
|
80014fc: 79ab ldrb r3, [r5, #6]
|
|
response.status = STATUS_OK;
|
|
80014fe: 2600 movs r6, #0
|
|
PEEL_BACKOFF_TIME +
|
|
8001500: 4353 muls r3, r2
|
|
uint16_t time = (distance * PEEL_TIME_PER_TENTH_MM) +
|
|
8001502: 33e6 adds r3, #230 @ 0xe6
|
|
uint16_t exp_time_be = (exp_time >> 8) | (exp_time << 8); // byte swap for network order
|
|
8001504: ba5b rev16 r3, r3
|
|
response.payload.expectedTimeToFeed.expectedFeedTime = exp_time_be;
|
|
8001506: 80e3 strh r3, [r4, #6]
|
|
response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
|
|
8001508: 2303 movs r3, #3
|
|
comp_crc_header(&crc, &response);
|
|
800150a: 0021 movs r1, r4
|
|
800150c: a802 add r0, sp, #8
|
|
response.status = STATUS_OK;
|
|
800150e: 7166 strb r6, [r4, #5]
|
|
response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
|
|
8001510: 70e3 strb r3, [r4, #3]
|
|
comp_crc_header(&crc, &response);
|
|
8001512: f7ff fb0d bl 8000b30 <comp_crc_header>
|
|
for (uint32_t i = 0; i < response.header.payloadLength; i++)
|
|
8001516: 78e3 ldrb r3, [r4, #3]
|
|
8001518: 42b3 cmp r3, r6
|
|
800151a: d80d bhi.n 8001538 <handleRS485Message+0x244>
|
|
response.header.crc = CRC8_107_getChecksum(&crc);
|
|
800151c: a802 add r0, sp, #8
|
|
800151e: f7ff f929 bl 8000774 <CRC8_107_getChecksum>
|
|
packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
|
|
8001522: 78e1 ldrb r1, [r4, #3]
|
|
response.header.crc = CRC8_107_getChecksum(&crc);
|
|
8001524: 7120 strb r0, [r4, #4]
|
|
rs485_transmit((uint8_t *)&response, packet_len);
|
|
8001526: 3105 adds r1, #5
|
|
8001528: 0020 movs r0, r4
|
|
800152a: f7ff fad3 bl 8000ad4 <rs485_transmit>
|
|
start_feed(command->payload.move.distance, 1);
|
|
800152e: 2101 movs r1, #1
|
|
8001530: 79a8 ldrb r0, [r5, #6]
|
|
start_feed(command->payload.move.distance, 0);
|
|
8001532: f7ff fbb5 bl 8000ca0 <start_feed>
|
|
break;
|
|
8001536: e726 b.n 8001386 <handleRS485Message+0x92>
|
|
CRC8_107_add(&crc, *(payload_ptr + i));
|
|
8001538: 19a3 adds r3, r4, r6
|
|
800153a: 7959 ldrb r1, [r3, #5]
|
|
800153c: a802 add r0, sp, #8
|
|
800153e: f7ff f905 bl 800074c <CRC8_107_add>
|
|
for (uint32_t i = 0; i < response.header.payloadLength; i++)
|
|
8001542: 3601 adds r6, #1
|
|
8001544: e7e7 b.n 8001516 <handleRS485Message+0x222>
|
|
if (!is_initialized)
|
|
8001546: 4b34 ldr r3, [pc, #208] @ (8001618 <handleRS485Message+0x324>)
|
|
8001548: 781e ldrb r6, [r3, #0]
|
|
800154a: 2e00 cmp r6, #0
|
|
800154c: d118 bne.n 8001580 <handleRS485Message+0x28c>
|
|
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
|
|
800154e: 2012 movs r0, #18
|
|
response.status = STATUS_UNINITIALIZED_FEEDER;
|
|
8001550: 2303 movs r3, #3
|
|
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
|
|
8001552: 4930 ldr r1, [pc, #192] @ (8001614 <handleRS485Message+0x320>)
|
|
8001554: 220c movs r2, #12
|
|
8001556: 4468 add r0, sp
|
|
response.status = STATUS_UNINITIALIZED_FEEDER;
|
|
8001558: 7163 strb r3, [r4, #5]
|
|
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
|
|
800155a: f003 febd bl 80052d8 <memcpy>
|
|
response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
|
|
800155e: 230d movs r3, #13
|
|
comp_crc_header(&crc, &response);
|
|
8001560: 0021 movs r1, r4
|
|
8001562: a802 add r0, sp, #8
|
|
response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
|
|
8001564: 70e3 strb r3, [r4, #3]
|
|
comp_crc_header(&crc, &response);
|
|
8001566: f7ff fae3 bl 8000b30 <comp_crc_header>
|
|
for (uint32_t i = 0; i < response.header.payloadLength; i++)
|
|
800156a: 78e3 ldrb r3, [r4, #3]
|
|
800156c: 42b3 cmp r3, r6
|
|
800156e: d800 bhi.n 8001572 <handleRS485Message+0x27e>
|
|
8001570: e761 b.n 8001436 <handleRS485Message+0x142>
|
|
CRC8_107_add(&crc, *(payload_ptr + i));
|
|
8001572: 19a3 adds r3, r4, r6
|
|
8001574: 7959 ldrb r1, [r3, #5]
|
|
8001576: a802 add r0, sp, #8
|
|
8001578: f7ff f8e8 bl 800074c <CRC8_107_add>
|
|
for (uint32_t i = 0; i < response.header.payloadLength; i++)
|
|
800157c: 3601 adds r6, #1
|
|
800157e: e7f4 b.n 800156a <handleRS485Message+0x276>
|
|
return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) +
|
|
8001580: 231e movs r3, #30
|
|
8001582: 2164 movs r1, #100 @ 0x64
|
|
uint16_t exp_time = calculate_expected_feed_time(command->payload.move.distance, 0);
|
|
8001584: 79aa ldrb r2, [r5, #6]
|
|
response.status = STATUS_OK;
|
|
8001586: 2600 movs r6, #0
|
|
return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) +
|
|
8001588: 4353 muls r3, r2
|
|
((distance + (BACKLASH_COMP_TENTH_MM * 2)) * TIMEOUT_TIME_PER_TENTH_MM) +
|
|
800158a: 3214 adds r2, #20
|
|
return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) +
|
|
800158c: 434a muls r2, r1
|
|
BACKWARDS_FEED_FILM_SLACK_REMOVAL_TIME + 50;
|
|
800158e: 3391 adds r3, #145 @ 0x91
|
|
8001590: 33ff adds r3, #255 @ 0xff
|
|
8001592: 189b adds r3, r3, r2
|
|
uint16_t exp_time_be = (exp_time >> 8) | (exp_time << 8); // byte swap for network order
|
|
8001594: ba5b rev16 r3, r3
|
|
response.payload.expectedTimeToFeed.expectedFeedTime = exp_time_be;
|
|
8001596: 80e3 strh r3, [r4, #6]
|
|
response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
|
|
8001598: 2303 movs r3, #3
|
|
comp_crc_header(&crc, &response);
|
|
800159a: 0021 movs r1, r4
|
|
800159c: a802 add r0, sp, #8
|
|
response.status = STATUS_OK;
|
|
800159e: 7166 strb r6, [r4, #5]
|
|
response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
|
|
80015a0: 70e3 strb r3, [r4, #3]
|
|
comp_crc_header(&crc, &response);
|
|
80015a2: f7ff fac5 bl 8000b30 <comp_crc_header>
|
|
for (uint32_t i = 0; i < response.header.payloadLength; i++)
|
|
80015a6: 78e3 ldrb r3, [r4, #3]
|
|
80015a8: 42b3 cmp r3, r6
|
|
80015aa: d80b bhi.n 80015c4 <handleRS485Message+0x2d0>
|
|
response.header.crc = CRC8_107_getChecksum(&crc);
|
|
80015ac: a802 add r0, sp, #8
|
|
80015ae: f7ff f8e1 bl 8000774 <CRC8_107_getChecksum>
|
|
packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
|
|
80015b2: 78e1 ldrb r1, [r4, #3]
|
|
response.header.crc = CRC8_107_getChecksum(&crc);
|
|
80015b4: 7120 strb r0, [r4, #4]
|
|
rs485_transmit((uint8_t *)&response, packet_len);
|
|
80015b6: 3105 adds r1, #5
|
|
80015b8: 0020 movs r0, r4
|
|
80015ba: f7ff fa8b bl 8000ad4 <rs485_transmit>
|
|
start_feed(command->payload.move.distance, 0);
|
|
80015be: 2100 movs r1, #0
|
|
80015c0: 79a8 ldrb r0, [r5, #6]
|
|
80015c2: e7b6 b.n 8001532 <handleRS485Message+0x23e>
|
|
CRC8_107_add(&crc, *(payload_ptr + i));
|
|
80015c4: 19a3 adds r3, r4, r6
|
|
80015c6: 7959 ldrb r1, [r3, #5]
|
|
80015c8: a802 add r0, sp, #8
|
|
80015ca: f7ff f8bf bl 800074c <CRC8_107_add>
|
|
for (uint32_t i = 0; i < response.header.payloadLength; i++)
|
|
80015ce: 3601 adds r6, #1
|
|
80015d0: e7e9 b.n 80015a6 <handleRS485Message+0x2b2>
|
|
if (feed_in_progress)
|
|
80015d2: 4b12 ldr r3, [pc, #72] @ (800161c <handleRS485Message+0x328>)
|
|
80015d4: 781a ldrb r2, [r3, #0]
|
|
response.status = STATUS_FEEDING_IN_PROGRESS;
|
|
80015d6: 2304 movs r3, #4
|
|
if (feed_in_progress)
|
|
80015d8: 2a00 cmp r2, #0
|
|
80015da: d101 bne.n 80015e0 <handleRS485Message+0x2ec>
|
|
response.status = last_feed_status;
|
|
80015dc: 4b10 ldr r3, [pc, #64] @ (8001620 <handleRS485Message+0x32c>)
|
|
80015de: 781b ldrb r3, [r3, #0]
|
|
response.status = STATUS_OK;
|
|
80015e0: 7163 strb r3, [r4, #5]
|
|
80015e2: e063 b.n 80016ac <handleRS485Message+0x3b8>
|
|
80015e4: 20000075 .word 0x20000075
|
|
80015e8: 2000006b .word 0x2000006b
|
|
80015ec: 2000007c .word 0x2000007c
|
|
80015f0: 20000024 .word 0x20000024
|
|
80015f4: 20000074 .word 0x20000074
|
|
80015f8: 2000007a .word 0x2000007a
|
|
80015fc: 20000061 .word 0x20000061
|
|
8001600: 20000062 .word 0x20000062
|
|
8001604: 20000063 .word 0x20000063
|
|
8001608: 20000078 .word 0x20000078
|
|
800160c: 20000076 .word 0x20000076
|
|
8001610: 20000073 .word 0x20000073
|
|
8001614: 20000f8b .word 0x20000f8b
|
|
8001618: 20000f8a .word 0x20000f8a
|
|
800161c: 20000125 .word 0x20000125
|
|
8001620: 20000126 .word 0x20000126
|
|
if (!is_initialized)
|
|
8001624: 4b4d ldr r3, [pc, #308] @ (800175c <handleRS485Message+0x468>)
|
|
8001626: 781f ldrb r7, [r3, #0]
|
|
8001628: 2f00 cmp r7, #0
|
|
800162a: d119 bne.n 8001660 <handleRS485Message+0x36c>
|
|
response.status = STATUS_UNINITIALIZED_FEEDER;
|
|
800162c: 2303 movs r3, #3
|
|
800162e: 7163 strb r3, [r4, #5]
|
|
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
|
|
8001630: 330f adds r3, #15
|
|
8001632: 446b add r3, sp
|
|
8001634: 0018 movs r0, r3
|
|
8001636: 494a ldr r1, [pc, #296] @ (8001760 <handleRS485Message+0x46c>)
|
|
8001638: 220c movs r2, #12
|
|
800163a: f003 fe4d bl 80052d8 <memcpy>
|
|
response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
|
|
800163e: 230d movs r3, #13
|
|
comp_crc_header(&crc, &response);
|
|
8001640: 0021 movs r1, r4
|
|
8001642: a802 add r0, sp, #8
|
|
response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
|
|
8001644: 70e3 strb r3, [r4, #3]
|
|
comp_crc_header(&crc, &response);
|
|
8001646: f7ff fa73 bl 8000b30 <comp_crc_header>
|
|
for (uint32_t i = 0; i < response.header.payloadLength; i++)
|
|
800164a: 78e3 ldrb r3, [r4, #3]
|
|
800164c: 42bb cmp r3, r7
|
|
800164e: d800 bhi.n 8001652 <handleRS485Message+0x35e>
|
|
8001650: e6f1 b.n 8001436 <handleRS485Message+0x142>
|
|
CRC8_107_add(&crc, *(payload_ptr + i));
|
|
8001652: 19e3 adds r3, r4, r7
|
|
8001654: 7959 ldrb r1, [r3, #5]
|
|
8001656: a802 add r0, sp, #8
|
|
8001658: f7ff f878 bl 800074c <CRC8_107_add>
|
|
for (uint32_t i = 0; i < response.header.payloadLength; i++)
|
|
800165c: 3701 adds r7, #1
|
|
800165e: e7f4 b.n 800164a <handleRS485Message+0x356>
|
|
handle_vendor_options(command->payload.vendorOptions.options, response.payload.vendorOptions.options);
|
|
8001660: 2312 movs r3, #18
|
|
8001662: 446b add r3, sp
|
|
8001664: 0019 movs r1, r3
|
|
8001666: 1da8 adds r0, r5, #6
|
|
8001668: f7ff fd1c bl 80010a4 <handle_vendor_options>
|
|
comp_crc_header(&crc,&response);
|
|
800166c: 0021 movs r1, r4
|
|
800166e: a802 add r0, sp, #8
|
|
response.status = STATUS_OK;
|
|
8001670: 7166 strb r6, [r4, #5]
|
|
comp_crc_header(&crc,&response);
|
|
8001672: f7ff fa5d bl 8000b30 <comp_crc_header>
|
|
CRC8_107_add(&crc,*(payload_ptr+i));
|
|
8001676: 19a3 adds r3, r4, r6
|
|
8001678: 7959 ldrb r1, [r3, #5]
|
|
800167a: a802 add r0, sp, #8
|
|
for (uint32_t i = 0; i<sizeof(response.payload.vendorOptions)+1; i++)
|
|
800167c: 3601 adds r6, #1
|
|
CRC8_107_add(&crc,*(payload_ptr+i));
|
|
800167e: f7ff f865 bl 800074c <CRC8_107_add>
|
|
for (uint32_t i = 0; i<sizeof(response.payload.vendorOptions)+1; i++)
|
|
8001682: 2e15 cmp r6, #21
|
|
8001684: d1f7 bne.n 8001676 <handleRS485Message+0x382>
|
|
response.header.crc = CRC8_107_getChecksum(&crc);
|
|
8001686: a802 add r0, sp, #8
|
|
8001688: f7ff f874 bl 8000774 <CRC8_107_getChecksum>
|
|
rs485_transmit((uint8_t *)&response, packet_len);
|
|
800168c: 211a movs r1, #26
|
|
response.header.crc = CRC8_107_getChecksum(&crc);
|
|
800168e: 7120 strb r0, [r4, #4]
|
|
response.header.payloadLength = sizeof(response.payload.vendorOptions)+1; // +1 for the status byte
|
|
8001690: 70e6 strb r6, [r4, #3]
|
|
rs485_transmit((uint8_t *)&response, packet_len);
|
|
8001692: 0020 movs r0, r4
|
|
8001694: f7ff fa1e bl 8000ad4 <rs485_transmit>
|
|
break;
|
|
8001698: e675 b.n 8001386 <handleRS485Message+0x92>
|
|
if(memcmp(UUID,command->payload.getFeederAddress.uuid,UUID_LENGTH) == 0)
|
|
800169a: 220c movs r2, #12
|
|
800169c: 4830 ldr r0, [pc, #192] @ (8001760 <handleRS485Message+0x46c>)
|
|
800169e: 1da9 adds r1, r5, #6
|
|
80016a0: f003 fde0 bl 8005264 <memcmp>
|
|
80016a4: 2800 cmp r0, #0
|
|
80016a6: d000 beq.n 80016aa <handleRS485Message+0x3b6>
|
|
80016a8: e66d b.n 8001386 <handleRS485Message+0x92>
|
|
response.status = STATUS_OK;
|
|
80016aa: 7160 strb r0, [r4, #5]
|
|
response.header.payloadLength = 1; // only status byte
|
|
80016ac: 2301 movs r3, #1
|
|
comp_crc_header(&crc, &response);
|
|
80016ae: 0021 movs r1, r4
|
|
80016b0: a802 add r0, sp, #8
|
|
response.header.payloadLength = 1; // only status byte
|
|
80016b2: 70e3 strb r3, [r4, #3]
|
|
comp_crc_header(&crc, &response);
|
|
80016b4: f7ff fa3c bl 8000b30 <comp_crc_header>
|
|
CRC8_107_add(&crc, response.status);
|
|
80016b8: 7961 ldrb r1, [r4, #5]
|
|
80016ba: a802 add r0, sp, #8
|
|
80016bc: f7ff f846 bl 800074c <CRC8_107_add>
|
|
response.header.crc = CRC8_107_getChecksum(&crc);
|
|
80016c0: e6b9 b.n 8001436 <handleRS485Message+0x142>
|
|
if(memcmp(UUID,command->payload.identifyFeeder.uuid,UUID_LENGTH) == 0)
|
|
80016c2: 220c movs r2, #12
|
|
80016c4: 4826 ldr r0, [pc, #152] @ (8001760 <handleRS485Message+0x46c>)
|
|
80016c6: 1da9 adds r1, r5, #6
|
|
80016c8: f003 fdcc bl 8005264 <memcmp>
|
|
80016cc: 2800 cmp r0, #0
|
|
80016ce: d000 beq.n 80016d2 <handleRS485Message+0x3de>
|
|
80016d0: e659 b.n 8001386 <handleRS485Message+0x92>
|
|
response.header.payloadLength = 1; // only status byte
|
|
80016d2: 2301 movs r3, #1
|
|
comp_crc_header(&crc,&response);
|
|
80016d4: 0021 movs r1, r4
|
|
response.status = STATUS_OK;
|
|
80016d6: 7160 strb r0, [r4, #5]
|
|
comp_crc_header(&crc,&response);
|
|
80016d8: a802 add r0, sp, #8
|
|
response.header.payloadLength = 1; // only status byte
|
|
80016da: 70e3 strb r3, [r4, #3]
|
|
comp_crc_header(&crc,&response);
|
|
80016dc: f7ff fa28 bl 8000b30 <comp_crc_header>
|
|
CRC8_107_add(&crc,response.status);
|
|
80016e0: 7961 ldrb r1, [r4, #5]
|
|
80016e2: a802 add r0, sp, #8
|
|
80016e4: f7ff f832 bl 800074c <CRC8_107_add>
|
|
response.header.crc = CRC8_107_getChecksum(&crc);
|
|
80016e8: a802 add r0, sp, #8
|
|
80016ea: f7ff f843 bl 8000774 <CRC8_107_getChecksum>
|
|
packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
|
|
80016ee: 78e1 ldrb r1, [r4, #3]
|
|
response.header.crc = CRC8_107_getChecksum(&crc);
|
|
80016f0: 7120 strb r0, [r4, #4]
|
|
rs485_transmit((uint8_t *)&response, packet_len);
|
|
80016f2: 3105 adds r1, #5
|
|
80016f4: 0020 movs r0, r4
|
|
80016f6: f7ff f9ed bl 8000ad4 <rs485_transmit>
|
|
identify_feeder();
|
|
80016fa: f7ff faa7 bl 8000c4c <identify_feeder>
|
|
break;
|
|
80016fe: e642 b.n 8001386 <handleRS485Message+0x92>
|
|
uint8_t new_address = command->payload.programFeederFloorAddress.address;
|
|
8001700: 7cad ldrb r5, [r5, #18]
|
|
uint8_t write_success = write_floor_address(new_address);
|
|
8001702: 0028 movs r0, r5
|
|
8001704: f7ff fd8f bl 8001226 <write_floor_address>
|
|
if (write_success)
|
|
8001708: 2305 movs r3, #5
|
|
800170a: 2800 cmp r0, #0
|
|
800170c: d100 bne.n 8001710 <handleRS485Message+0x41c>
|
|
800170e: e767 b.n 80015e0 <handleRS485Message+0x2ec>
|
|
floor_address_status = 2;
|
|
8001710: 2202 movs r2, #2
|
|
floor_address = new_address;
|
|
8001712: 4b14 ldr r3, [pc, #80] @ (8001764 <handleRS485Message+0x470>)
|
|
my_address = new_address;
|
|
8001714: 703d strb r5, [r7, #0]
|
|
floor_address = new_address;
|
|
8001716: 701d strb r5, [r3, #0]
|
|
floor_address_status = 2;
|
|
8001718: 4b13 ldr r3, [pc, #76] @ (8001768 <handleRS485Message+0x474>)
|
|
800171a: 701a strb r2, [r3, #0]
|
|
response.status = STATUS_OK;
|
|
800171c: 2300 movs r3, #0
|
|
800171e: e75f b.n 80015e0 <handleRS485Message+0x2ec>
|
|
if (is_initialized) return;
|
|
8001720: 4b0e ldr r3, [pc, #56] @ (800175c <handleRS485Message+0x468>)
|
|
8001722: 781d ldrb r5, [r3, #0]
|
|
8001724: 2d00 cmp r5, #0
|
|
8001726: d000 beq.n 800172a <handleRS485Message+0x436>
|
|
8001728: e62d b.n 8001386 <handleRS485Message+0x92>
|
|
memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH);
|
|
800172a: 2012 movs r0, #18
|
|
800172c: 490c ldr r1, [pc, #48] @ (8001760 <handleRS485Message+0x46c>)
|
|
800172e: 220c movs r2, #12
|
|
8001730: 4468 add r0, sp
|
|
8001732: f003 fdd1 bl 80052d8 <memcpy>
|
|
response.header.payloadLength = sizeof(response.payload.getFeederId)+1;
|
|
8001736: 230d movs r3, #13
|
|
comp_crc_header(&crc,&response);
|
|
8001738: 0021 movs r1, r4
|
|
800173a: a802 add r0, sp, #8
|
|
response.status=STATUS_OK;
|
|
800173c: 7165 strb r5, [r4, #5]
|
|
response.header.payloadLength = sizeof(response.payload.getFeederId)+1;
|
|
800173e: 70e3 strb r3, [r4, #3]
|
|
comp_crc_header(&crc,&response);
|
|
8001740: f7ff f9f6 bl 8000b30 <comp_crc_header>
|
|
for (uint32_t i = 0; i<response.header.payloadLength; i++)
|
|
8001744: 78e3 ldrb r3, [r4, #3]
|
|
8001746: 42ab cmp r3, r5
|
|
8001748: d800 bhi.n 800174c <handleRS485Message+0x458>
|
|
800174a: e674 b.n 8001436 <handleRS485Message+0x142>
|
|
CRC8_107_add(&crc,*(payload_ptr+i));
|
|
800174c: 1963 adds r3, r4, r5
|
|
800174e: 7959 ldrb r1, [r3, #5]
|
|
8001750: a802 add r0, sp, #8
|
|
8001752: f7fe fffb bl 800074c <CRC8_107_add>
|
|
for (uint32_t i = 0; i<response.header.payloadLength; i++)
|
|
8001756: 3501 adds r5, #1
|
|
8001758: e7f4 b.n 8001744 <handleRS485Message+0x450>
|
|
800175a: 46c0 nop @ (mov r8, r8)
|
|
800175c: 20000f8a .word 0x20000f8a
|
|
8001760: 20000f8b .word 0x20000f8b
|
|
8001764: 20000001 .word 0x20000001
|
|
8001768: 200000ec .word 0x200000ec
|
|
|
|
0800176c <debug_itoa>:
|
|
{
|
|
800176c: b5f0 push {r4, r5, r6, r7, lr}
|
|
800176e: 0004 movs r4, r0
|
|
8001770: 000d movs r5, r1
|
|
8001772: b087 sub sp, #28
|
|
if (val < 0) { neg = 1; val = -val; }
|
|
8001774: 2800 cmp r0, #0
|
|
8001776: da1a bge.n 80017ae <debug_itoa+0x42>
|
|
8001778: 2601 movs r6, #1
|
|
800177a: 4244 negs r4, r0
|
|
uint8_t i = 0, len = 0;
|
|
800177c: 2700 movs r7, #0
|
|
else { while (val > 0) { tmp[i++] = '0' + (val % 10); val /= 10; } }
|
|
800177e: 0020 movs r0, r4
|
|
8001780: 210a movs r1, #10
|
|
8001782: 9701 str r7, [sp, #4]
|
|
8001784: f7fe fe44 bl 8000410 <__aeabi_idivmod>
|
|
8001788: 9a01 ldr r2, [sp, #4]
|
|
800178a: 3130 adds r1, #48 @ 0x30
|
|
800178c: ab03 add r3, sp, #12
|
|
800178e: 0020 movs r0, r4
|
|
8001790: 5499 strb r1, [r3, r2]
|
|
8001792: 210a movs r1, #10
|
|
8001794: f7fe fd56 bl 8000244 <__divsi3>
|
|
8001798: 3701 adds r7, #1
|
|
800179a: 0004 movs r4, r0
|
|
800179c: b2ff uxtb r7, r7
|
|
800179e: 2800 cmp r0, #0
|
|
80017a0: d1ed bne.n 800177e <debug_itoa+0x12>
|
|
if (neg) { *buf++ = '-'; len++; }
|
|
80017a2: 2e00 cmp r6, #0
|
|
80017a4: d00c beq.n 80017c0 <debug_itoa+0x54>
|
|
80017a6: 232d movs r3, #45 @ 0x2d
|
|
80017a8: 702b strb r3, [r5, #0]
|
|
80017aa: 3501 adds r5, #1
|
|
80017ac: e008 b.n 80017c0 <debug_itoa+0x54>
|
|
if (val == 0) { tmp[i++] = '0'; }
|
|
80017ae: 2800 cmp r0, #0
|
|
80017b0: d001 beq.n 80017b6 <debug_itoa+0x4a>
|
|
80017b2: 2600 movs r6, #0
|
|
80017b4: e7e2 b.n 800177c <debug_itoa+0x10>
|
|
80017b6: 2330 movs r3, #48 @ 0x30
|
|
uint8_t i = 0, len = 0;
|
|
80017b8: 0006 movs r6, r0
|
|
if (val == 0) { tmp[i++] = '0'; }
|
|
80017ba: 2701 movs r7, #1
|
|
80017bc: aa02 add r2, sp, #8
|
|
80017be: 7113 strb r3, [r2, #4]
|
|
80017c0: 003b movs r3, r7
|
|
while (i > 0) { *buf++ = tmp[--i]; len++; }
|
|
80017c2: 2b00 cmp r3, #0
|
|
80017c4: d103 bne.n 80017ce <debug_itoa+0x62>
|
|
return len;
|
|
80017c6: 19f0 adds r0, r6, r7
|
|
80017c8: b2c0 uxtb r0, r0
|
|
}
|
|
80017ca: b007 add sp, #28
|
|
80017cc: bdf0 pop {r4, r5, r6, r7, pc}
|
|
while (i > 0) { *buf++ = tmp[--i]; len++; }
|
|
80017ce: 3b01 subs r3, #1
|
|
80017d0: b2db uxtb r3, r3
|
|
80017d2: aa03 add r2, sp, #12
|
|
80017d4: 5cd2 ldrb r2, [r2, r3]
|
|
80017d6: 702a strb r2, [r5, #0]
|
|
80017d8: 3501 adds r5, #1
|
|
80017da: e7f2 b.n 80017c2 <debug_itoa+0x56>
|
|
|
|
080017dc <debug_hex8>:
|
|
{
|
|
80017dc: b570 push {r4, r5, r6, lr}
|
|
80017de: 0004 movs r4, r0
|
|
80017e0: 000d movs r5, r1
|
|
80017e2: b086 sub sp, #24
|
|
const char hex[] = "0123456789ABCDEF";
|
|
80017e4: ae01 add r6, sp, #4
|
|
80017e6: 2211 movs r2, #17
|
|
80017e8: 0030 movs r0, r6
|
|
80017ea: 4906 ldr r1, [pc, #24] @ (8001804 <debug_hex8+0x28>)
|
|
80017ec: f003 fd74 bl 80052d8 <memcpy>
|
|
buf[0] = hex[(val >> 4) & 0x0F];
|
|
80017f0: 0923 lsrs r3, r4, #4
|
|
80017f2: 5cf3 ldrb r3, [r6, r3]
|
|
}
|
|
80017f4: 2002 movs r0, #2
|
|
buf[0] = hex[(val >> 4) & 0x0F];
|
|
80017f6: 702b strb r3, [r5, #0]
|
|
buf[1] = hex[val & 0x0F];
|
|
80017f8: 230f movs r3, #15
|
|
80017fa: 401c ands r4, r3
|
|
80017fc: 5d33 ldrb r3, [r6, r4]
|
|
80017fe: 706b strb r3, [r5, #1]
|
|
}
|
|
8001800: b006 add sp, #24
|
|
8001802: bd70 pop {r4, r5, r6, pc}
|
|
8001804: 08005304 .word 0x08005304
|
|
|
|
08001808 <debug_output>:
|
|
{
|
|
8001808: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
if (!debug_enabled) return;
|
|
800180a: 4b6b ldr r3, [pc, #428] @ (80019b8 <debug_output+0x1b0>)
|
|
800180c: 781b ldrb r3, [r3, #0]
|
|
800180e: 2b00 cmp r3, #0
|
|
8001810: d100 bne.n 8001814 <debug_output+0xc>
|
|
8001812: e0cf b.n 80019b4 <debug_output+0x1ac>
|
|
uint32_t now = HAL_GetTick();
|
|
8001814: f001 f87c bl 8002910 <HAL_GetTick>
|
|
if ((now - last_debug_output_time) < DEBUG_OUTPUT_INTERVAL_MS) return;
|
|
8001818: 4a68 ldr r2, [pc, #416] @ (80019bc <debug_output+0x1b4>)
|
|
800181a: 6813 ldr r3, [r2, #0]
|
|
800181c: 1ac3 subs r3, r0, r3
|
|
800181e: 2b63 cmp r3, #99 @ 0x63
|
|
8001820: d800 bhi.n 8001824 <debug_output+0x1c>
|
|
8001822: e0c7 b.n 80019b4 <debug_output+0x1ac>
|
|
*p++ = '$'; *p++ = 'P'; *p++ = ':';
|
|
8001824: 2324 movs r3, #36 @ 0x24
|
|
8001826: 243a movs r4, #58 @ 0x3a
|
|
8001828: 4d65 ldr r5, [pc, #404] @ (80019c0 <debug_output+0x1b8>)
|
|
p += debug_itoa(total_count, p);
|
|
800182a: 4e66 ldr r6, [pc, #408] @ (80019c4 <debug_output+0x1bc>)
|
|
800182c: 4f66 ldr r7, [pc, #408] @ (80019c8 <debug_output+0x1c0>)
|
|
last_debug_output_time = now;
|
|
800182e: 6010 str r0, [r2, #0]
|
|
p += debug_itoa(total_count, p);
|
|
8001830: 0039 movs r1, r7
|
|
8001832: 6830 ldr r0, [r6, #0]
|
|
*p++ = '$'; *p++ = 'P'; *p++ = ':';
|
|
8001834: 702b strb r3, [r5, #0]
|
|
8001836: 332c adds r3, #44 @ 0x2c
|
|
8001838: 706b strb r3, [r5, #1]
|
|
800183a: 70ac strb r4, [r5, #2]
|
|
p += debug_itoa(total_count, p);
|
|
800183c: f7ff ff96 bl 800176c <debug_itoa>
|
|
8001840: 183f adds r7, r7, r0
|
|
*p++ = ':';
|
|
8001842: 1c7b adds r3, r7, #1
|
|
8001844: 703c strb r4, [r7, #0]
|
|
p += debug_itoa(target_count, p);
|
|
8001846: 4f61 ldr r7, [pc, #388] @ (80019cc <debug_output+0x1c4>)
|
|
8001848: 0019 movs r1, r3
|
|
800184a: 6838 ldr r0, [r7, #0]
|
|
*p++ = ':';
|
|
800184c: 9301 str r3, [sp, #4]
|
|
p += debug_itoa(target_count, p);
|
|
800184e: f7ff ff8d bl 800176c <debug_itoa>
|
|
8001852: 9b01 ldr r3, [sp, #4]
|
|
8001854: 1818 adds r0, r3, r0
|
|
*p++ = ':';
|
|
8001856: 1c43 adds r3, r0, #1
|
|
8001858: 9301 str r3, [sp, #4]
|
|
800185a: 7004 strb r4, [r0, #0]
|
|
p += debug_itoa(target_count - total_count, p);
|
|
800185c: 6833 ldr r3, [r6, #0]
|
|
800185e: 6838 ldr r0, [r7, #0]
|
|
8001860: 9901 ldr r1, [sp, #4]
|
|
8001862: 1ac0 subs r0, r0, r3
|
|
8001864: f7ff ff82 bl 800176c <debug_itoa>
|
|
8001868: 9b01 ldr r3, [sp, #4]
|
|
*p++ = ','; *p++ = 'I'; *p++ = ':';
|
|
800186a: 272c movs r7, #44 @ 0x2c
|
|
p += debug_itoa(target_count - total_count, p);
|
|
800186c: 1818 adds r0, r3, r0
|
|
*p++ = ','; *p++ = 'I'; *p++ = ':';
|
|
800186e: 2349 movs r3, #73 @ 0x49
|
|
8001870: 7043 strb r3, [r0, #1]
|
|
p += debug_itoa(debug_pid_output, p);
|
|
8001872: 4b57 ldr r3, [pc, #348] @ (80019d0 <debug_output+0x1c8>)
|
|
*p++ = ','; *p++ = 'I'; *p++ = ':';
|
|
8001874: 1cc6 adds r6, r0, #3
|
|
8001876: 7007 strb r7, [r0, #0]
|
|
8001878: 7084 strb r4, [r0, #2]
|
|
p += debug_itoa(debug_pid_output, p);
|
|
800187a: 8818 ldrh r0, [r3, #0]
|
|
800187c: 0031 movs r1, r6
|
|
800187e: b200 sxth r0, r0
|
|
8001880: f7ff ff74 bl 800176c <debug_itoa>
|
|
*p++ = ','; *p++ = 'S'; *p++ = ':';
|
|
8001884: 2353 movs r3, #83 @ 0x53
|
|
p += debug_itoa(debug_pid_output, p);
|
|
8001886: 1830 adds r0, r6, r0
|
|
*p++ = ','; *p++ = 'S'; *p++ = ':';
|
|
8001888: 7043 strb r3, [r0, #1]
|
|
*p++ = '0' + feed_state; // State as single digit 0-9
|
|
800188a: 4b52 ldr r3, [pc, #328] @ (80019d4 <debug_output+0x1cc>)
|
|
*p++ = ','; *p++ = 'C'; *p++ = ':';
|
|
800188c: 0006 movs r6, r0
|
|
*p++ = '0' + feed_state; // State as single digit 0-9
|
|
800188e: 781b ldrb r3, [r3, #0]
|
|
*p++ = ','; *p++ = 'S'; *p++ = ':';
|
|
8001890: 7007 strb r7, [r0, #0]
|
|
*p++ = '0' + feed_state; // State as single digit 0-9
|
|
8001892: 3330 adds r3, #48 @ 0x30
|
|
8001894: 70c3 strb r3, [r0, #3]
|
|
*p++ = ','; *p++ = 'F'; *p++ = ':';
|
|
8001896: 2346 movs r3, #70 @ 0x46
|
|
8001898: 7143 strb r3, [r0, #5]
|
|
*p++ = '0' + is_initialized;
|
|
800189a: 4b4f ldr r3, [pc, #316] @ (80019d8 <debug_output+0x1d0>)
|
|
*p++ = ','; *p++ = 'S'; *p++ = ':';
|
|
800189c: 7084 strb r4, [r0, #2]
|
|
*p++ = '0' + is_initialized;
|
|
800189e: 781b ldrb r3, [r3, #0]
|
|
*p++ = ','; *p++ = 'F'; *p++ = ':';
|
|
80018a0: 7107 strb r7, [r0, #4]
|
|
*p++ = '0' + is_initialized;
|
|
80018a2: 3330 adds r3, #48 @ 0x30
|
|
80018a4: 71c3 strb r3, [r0, #7]
|
|
*p++ = '0' + feed_in_progress;
|
|
80018a6: 4b4d ldr r3, [pc, #308] @ (80019dc <debug_output+0x1d4>)
|
|
*p++ = ','; *p++ = 'F'; *p++ = ':';
|
|
80018a8: 7184 strb r4, [r0, #6]
|
|
*p++ = '0' + feed_in_progress;
|
|
80018aa: 781b ldrb r3, [r3, #0]
|
|
*p++ = ','; *p++ = 'C'; *p++ = ':';
|
|
80018ac: 7247 strb r7, [r0, #9]
|
|
*p++ = '0' + feed_in_progress;
|
|
80018ae: 3330 adds r3, #48 @ 0x30
|
|
80018b0: 7203 strb r3, [r0, #8]
|
|
*p++ = ','; *p++ = 'C'; *p++ = ':';
|
|
80018b2: 2343 movs r3, #67 @ 0x43
|
|
80018b4: 7283 strb r3, [r0, #10]
|
|
p += debug_itoa(feed_ok_count, p);
|
|
80018b6: 4b4a ldr r3, [pc, #296] @ (80019e0 <debug_output+0x1d8>)
|
|
*p++ = ','; *p++ = 'C'; *p++ = ':';
|
|
80018b8: 72c4 strb r4, [r0, #11]
|
|
p += debug_itoa(feed_ok_count, p);
|
|
80018ba: 8818 ldrh r0, [r3, #0]
|
|
*p++ = ','; *p++ = 'C'; *p++ = ':';
|
|
80018bc: 360c adds r6, #12
|
|
p += debug_itoa(feed_ok_count, p);
|
|
80018be: 0031 movs r1, r6
|
|
80018c0: b280 uxth r0, r0
|
|
80018c2: f7ff ff53 bl 800176c <debug_itoa>
|
|
p += debug_itoa(feed_fail_count, p);
|
|
80018c6: 4b47 ldr r3, [pc, #284] @ (80019e4 <debug_output+0x1dc>)
|
|
p += debug_itoa(feed_ok_count, p);
|
|
80018c8: 1830 adds r0, r6, r0
|
|
*p++ = ':';
|
|
80018ca: 1c46 adds r6, r0, #1
|
|
80018cc: 7004 strb r4, [r0, #0]
|
|
p += debug_itoa(feed_fail_count, p);
|
|
80018ce: 8818 ldrh r0, [r3, #0]
|
|
80018d0: 0031 movs r1, r6
|
|
80018d2: b280 uxth r0, r0
|
|
80018d4: f7ff ff4a bl 800176c <debug_itoa>
|
|
p += debug_itoa(brake_time_tenths, p);
|
|
80018d8: 4b43 ldr r3, [pc, #268] @ (80019e8 <debug_output+0x1e0>)
|
|
p += debug_itoa(feed_fail_count, p);
|
|
80018da: 1830 adds r0, r6, r0
|
|
*p++ = ':';
|
|
80018dc: 1c46 adds r6, r0, #1
|
|
p += debug_itoa(brake_time_tenths, p);
|
|
80018de: 0031 movs r1, r6
|
|
*p++ = ':';
|
|
80018e0: 7004 strb r4, [r0, #0]
|
|
p += debug_itoa(brake_time_tenths, p);
|
|
80018e2: 6818 ldr r0, [r3, #0]
|
|
80018e4: f7ff ff42 bl 800176c <debug_itoa>
|
|
p += debug_itoa(feed_retry_total, p);
|
|
80018e8: 4b40 ldr r3, [pc, #256] @ (80019ec <debug_output+0x1e4>)
|
|
p += debug_itoa(brake_time_tenths, p);
|
|
80018ea: 1830 adds r0, r6, r0
|
|
*p++ = ':';
|
|
80018ec: 1c46 adds r6, r0, #1
|
|
80018ee: 7004 strb r4, [r0, #0]
|
|
p += debug_itoa(feed_retry_total, p);
|
|
80018f0: 8818 ldrh r0, [r3, #0]
|
|
80018f2: 0031 movs r1, r6
|
|
80018f4: b280 uxth r0, r0
|
|
80018f6: f7ff ff39 bl 800176c <debug_itoa>
|
|
*p++ = ','; *p++ = 'A'; *p++ = ':';
|
|
80018fa: 2341 movs r3, #65 @ 0x41
|
|
p += debug_itoa(feed_retry_total, p);
|
|
80018fc: 1836 adds r6, r6, r0
|
|
*p++ = ','; *p++ = 'A'; *p++ = ':';
|
|
80018fe: 7073 strb r3, [r6, #1]
|
|
p += debug_hex8(my_address, p);
|
|
8001900: 4b3b ldr r3, [pc, #236] @ (80019f0 <debug_output+0x1e8>)
|
|
*p++ = ','; *p++ = 'A'; *p++ = ':';
|
|
8001902: 7037 strb r7, [r6, #0]
|
|
8001904: 70b4 strb r4, [r6, #2]
|
|
8001906: 1cf1 adds r1, r6, #3
|
|
p += debug_hex8(my_address, p);
|
|
8001908: 7818 ldrb r0, [r3, #0]
|
|
800190a: f7ff ff67 bl 80017dc <debug_hex8>
|
|
*p++ = ','; *p++ = 'R'; *p++ = ':';
|
|
800190e: 2352 movs r3, #82 @ 0x52
|
|
8001910: 71b3 strb r3, [r6, #6]
|
|
8001912: 0033 movs r3, r6
|
|
8001914: 3308 adds r3, #8
|
|
8001916: 9301 str r3, [sp, #4]
|
|
p += debug_itoa(drop_crc, p);
|
|
8001918: 4b36 ldr r3, [pc, #216] @ (80019f4 <debug_output+0x1ec>)
|
|
*p++ = ','; *p++ = 'R'; *p++ = ':';
|
|
800191a: 7177 strb r7, [r6, #5]
|
|
p += debug_itoa(drop_crc, p);
|
|
800191c: 8818 ldrh r0, [r3, #0]
|
|
*p++ = ','; *p++ = 'R'; *p++ = ':';
|
|
800191e: 71f4 strb r4, [r6, #7]
|
|
p += debug_itoa(drop_crc, p);
|
|
8001920: 9901 ldr r1, [sp, #4]
|
|
8001922: b280 uxth r0, r0
|
|
8001924: f7ff ff22 bl 800176c <debug_itoa>
|
|
8001928: 9b01 ldr r3, [sp, #4]
|
|
800192a: 1818 adds r0, r3, r0
|
|
p += debug_itoa(msg_handled, p);
|
|
800192c: 4b32 ldr r3, [pc, #200] @ (80019f8 <debug_output+0x1f0>)
|
|
*p++ = ':';
|
|
800192e: 1c46 adds r6, r0, #1
|
|
8001930: 7004 strb r4, [r0, #0]
|
|
p += debug_itoa(msg_handled, p);
|
|
8001932: 8818 ldrh r0, [r3, #0]
|
|
8001934: 0031 movs r1, r6
|
|
8001936: b280 uxth r0, r0
|
|
8001938: f7ff ff18 bl 800176c <debug_itoa>
|
|
p += debug_itoa(uart_error_count, p);
|
|
800193c: 4b2f ldr r3, [pc, #188] @ (80019fc <debug_output+0x1f4>)
|
|
p += debug_itoa(msg_handled, p);
|
|
800193e: 1830 adds r0, r6, r0
|
|
*p++ = ':';
|
|
8001940: 1c46 adds r6, r0, #1
|
|
8001942: 7004 strb r4, [r0, #0]
|
|
p += debug_itoa(uart_error_count, p);
|
|
8001944: 8818 ldrh r0, [r3, #0]
|
|
8001946: 0031 movs r1, r6
|
|
8001948: b280 uxth r0, r0
|
|
800194a: f7ff ff0f bl 800176c <debug_itoa>
|
|
*p++ = ','; *p++ = 'T'; *p++ = ':';
|
|
800194e: 2354 movs r3, #84 @ 0x54
|
|
p += debug_itoa(uart_error_count, p);
|
|
8001950: 1830 adds r0, r6, r0
|
|
*p++ = ','; *p++ = 'T'; *p++ = ':';
|
|
8001952: 7007 strb r7, [r0, #0]
|
|
p += debug_itoa(my_addr_size, p);
|
|
8001954: 4f2a ldr r7, [pc, #168] @ (8001a00 <debug_output+0x1f8>)
|
|
*p++ = ','; *p++ = 'T'; *p++ = ':';
|
|
8001956: 1cc6 adds r6, r0, #3
|
|
8001958: 7084 strb r4, [r0, #2]
|
|
800195a: 7043 strb r3, [r0, #1]
|
|
p += debug_itoa(my_addr_size, p);
|
|
800195c: 7838 ldrb r0, [r7, #0]
|
|
800195e: 0031 movs r1, r6
|
|
8001960: b2c0 uxtb r0, r0
|
|
8001962: f7ff ff03 bl 800176c <debug_itoa>
|
|
8001966: 1830 adds r0, r6, r0
|
|
*p++ = ':';
|
|
8001968: 7004 strb r4, [r0, #0]
|
|
800196a: 2400 movs r4, #0
|
|
800196c: 1c46 adds r6, r0, #1
|
|
for (uint8_t i = 0; i < 8 && i < my_addr_size; i++)
|
|
800196e: 783a ldrb r2, [r7, #0]
|
|
8001970: b2e3 uxtb r3, r4
|
|
8001972: 429a cmp r2, r3
|
|
8001974: d909 bls.n 800198a <debug_output+0x182>
|
|
p += debug_hex8(my_addr_bytes[i], p);
|
|
8001976: 4b23 ldr r3, [pc, #140] @ (8001a04 <debug_output+0x1fc>)
|
|
8001978: 0031 movs r1, r6
|
|
800197a: 5d18 ldrb r0, [r3, r4]
|
|
for (uint8_t i = 0; i < 8 && i < my_addr_size; i++)
|
|
800197c: 3401 adds r4, #1
|
|
p += debug_hex8(my_addr_bytes[i], p);
|
|
800197e: b2c0 uxtb r0, r0
|
|
8001980: f7ff ff2c bl 80017dc <debug_hex8>
|
|
8001984: 3602 adds r6, #2
|
|
for (uint8_t i = 0; i < 8 && i < my_addr_size; i++)
|
|
8001986: 2c08 cmp r4, #8
|
|
8001988: d1f1 bne.n 800196e <debug_output+0x166>
|
|
*p++ = ':';
|
|
800198a: 233a movs r3, #58 @ 0x3a
|
|
800198c: 7033 strb r3, [r6, #0]
|
|
p += debug_hex8(my_addr_crc_exp, p);
|
|
800198e: 4b1e ldr r3, [pc, #120] @ (8001a08 <debug_output+0x200>)
|
|
*p++ = ':';
|
|
8001990: 1c71 adds r1, r6, #1
|
|
p += debug_hex8(my_addr_crc_exp, p);
|
|
8001992: 7818 ldrb r0, [r3, #0]
|
|
8001994: b2c0 uxtb r0, r0
|
|
8001996: f7ff ff21 bl 80017dc <debug_hex8>
|
|
*p++ = '*'; *p++ = '\r'; *p++ = '\n';
|
|
800199a: 232a movs r3, #42 @ 0x2a
|
|
800199c: 70f3 strb r3, [r6, #3]
|
|
800199e: 3b1d subs r3, #29
|
|
80019a0: 7133 strb r3, [r6, #4]
|
|
80019a2: 3b03 subs r3, #3
|
|
80019a4: 7173 strb r3, [r6, #5]
|
|
80019a6: 3606 adds r6, #6
|
|
HAL_UART_Transmit(&huart1, (uint8_t*)debug_tx_buffer, p - debug_tx_buffer, 10);
|
|
80019a8: 1b72 subs r2, r6, r5
|
|
80019aa: 0029 movs r1, r5
|
|
80019ac: 4817 ldr r0, [pc, #92] @ (8001a0c <debug_output+0x204>)
|
|
80019ae: b292 uxth r2, r2
|
|
80019b0: f003 f9fb bl 8004daa <HAL_UART_Transmit>
|
|
}
|
|
80019b4: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
|
|
80019b6: 46c0 nop @ (mov r8, r8)
|
|
80019b8: 20000000 .word 0x20000000
|
|
80019bc: 200000e4 .word 0x200000e4
|
|
80019c0: 20000082 .word 0x20000082
|
|
80019c4: 20000158 .word 0x20000158
|
|
80019c8: 20000085 .word 0x20000085
|
|
80019cc: 20000154 .word 0x20000154
|
|
80019d0: 20000080 .word 0x20000080
|
|
80019d4: 2000011c .word 0x2000011c
|
|
80019d8: 20000f8a .word 0x20000f8a
|
|
80019dc: 20000125 .word 0x20000125
|
|
80019e0: 20000122 .word 0x20000122
|
|
80019e4: 20000120 .word 0x20000120
|
|
80019e8: 20000008 .word 0x20000008
|
|
80019ec: 2000011e .word 0x2000011e
|
|
80019f0: 20000024 .word 0x20000024
|
|
80019f4: 2000007a .word 0x2000007a
|
|
80019f8: 20000076 .word 0x20000076
|
|
80019fc: 2000007e .word 0x2000007e
|
|
8001a00: 20000062 .word 0x20000062
|
|
8001a04: 20000063 .word 0x20000063
|
|
8001a08: 20000061 .word 0x20000061
|
|
8001a0c: 200010f0 .word 0x200010f0
|
|
|
|
08001a10 <reset_position_if_needed>:
|
|
{
|
|
8001a10: b570 push {r4, r5, r6, lr}
|
|
if ((total_count % counts_per_mm) == 0 && feed_state == FEED_STATE_IDLE)
|
|
8001a12: 4d12 ldr r5, [pc, #72] @ (8001a5c <reset_position_if_needed+0x4c>)
|
|
8001a14: 4b12 ldr r3, [pc, #72] @ (8001a60 <reset_position_if_needed+0x50>)
|
|
8001a16: 6828 ldr r0, [r5, #0]
|
|
8001a18: 4a12 ldr r2, [pc, #72] @ (8001a64 <reset_position_if_needed+0x54>)
|
|
8001a1a: 4343 muls r3, r0
|
|
8001a1c: 189b adds r3, r3, r2
|
|
8001a1e: 4a12 ldr r2, [pc, #72] @ (8001a68 <reset_position_if_needed+0x58>)
|
|
8001a20: 4293 cmp r3, r2
|
|
8001a22: d819 bhi.n 8001a58 <reset_position_if_needed+0x48>
|
|
8001a24: 4b11 ldr r3, [pc, #68] @ (8001a6c <reset_position_if_needed+0x5c>)
|
|
8001a26: 781b ldrb r3, [r3, #0]
|
|
8001a28: b2dc uxtb r4, r3
|
|
8001a2a: 2b00 cmp r3, #0
|
|
8001a2c: d114 bne.n 8001a58 <reset_position_if_needed+0x48>
|
|
int32_t mm_moved = total_count / counts_per_mm;
|
|
8001a2e: 21e1 movs r1, #225 @ 0xe1
|
|
8001a30: f7fe fc08 bl 8000244 <__divsi3>
|
|
mm_position += mm_moved;
|
|
8001a34: 4e0e ldr r6, [pc, #56] @ (8001a70 <reset_position_if_needed+0x60>)
|
|
8001a36: 6833 ldr r3, [r6, #0]
|
|
8001a38: 181b adds r3, r3, r0
|
|
8001a3a: 6033 str r3, [r6, #0]
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8001a3c: b672 cpsid i
|
|
encoder_count_extra = 0;
|
|
8001a3e: 4b0d ldr r3, [pc, #52] @ (8001a74 <reset_position_if_needed+0x64>)
|
|
total_count = 0;
|
|
8001a40: 602c str r4, [r5, #0]
|
|
encoder_count_extra = 0;
|
|
8001a42: 601c str r4, [r3, #0]
|
|
htim3.Instance->CNT = 0;
|
|
8001a44: 4b0c ldr r3, [pc, #48] @ (8001a78 <reset_position_if_needed+0x68>)
|
|
8001a46: 681b ldr r3, [r3, #0]
|
|
8001a48: 625c str r4, [r3, #36] @ 0x24
|
|
encoder_previous = 0;
|
|
8001a4a: 4b0c ldr r3, [pc, #48] @ (8001a7c <reset_position_if_needed+0x6c>)
|
|
8001a4c: 801c strh r4, [r3, #0]
|
|
target_count = 0;
|
|
8001a4e: 4b0c ldr r3, [pc, #48] @ (8001a80 <reset_position_if_needed+0x70>)
|
|
8001a50: 601c str r4, [r3, #0]
|
|
feed_target_position = 0;
|
|
8001a52: 4b0c ldr r3, [pc, #48] @ (8001a84 <reset_position_if_needed+0x74>)
|
|
8001a54: 601c str r4, [r3, #0]
|
|
__ASM volatile ("cpsie i" : : : "memory");
|
|
8001a56: b662 cpsie i
|
|
}
|
|
8001a58: bd70 pop {r4, r5, r6, pc}
|
|
8001a5a: 46c0 nop @ (mov r8, r8)
|
|
8001a5c: 20000158 .word 0x20000158
|
|
8001a60: 87654321 .word 0x87654321
|
|
8001a64: 0091a2b3 .word 0x0091a2b3
|
|
8001a68: 01234566 .word 0x01234566
|
|
8001a6c: 2000011c .word 0x2000011c
|
|
8001a70: 200000e8 .word 0x200000e8
|
|
8001a74: 20000f9c .word 0x20000f9c
|
|
8001a78: 20001268 .word 0x20001268
|
|
8001a7c: 20000f98 .word 0x20000f98
|
|
8001a80: 20000154 .word 0x20000154
|
|
8001a84: 20000108 .word 0x20000108
|
|
|
|
08001a88 <main>:
|
|
{
|
|
8001a88: b5f0 push {r4, r5, r6, r7, lr}
|
|
8001a8a: b0a3 sub sp, #140 @ 0x8c
|
|
HAL_Init();
|
|
8001a8c: f000 ff28 bl 80028e0 <HAL_Init>
|
|
pid_init(&motor_pid,kp,ki,kd,i_min,i_max,PWM_MAX,pid_max_step);
|
|
8001a90: 4bd4 ldr r3, [pc, #848] @ (8001de4 <main+0x35c>)
|
|
8001a92: 4ed5 ldr r6, [pc, #852] @ (8001de8 <main+0x360>)
|
|
8001a94: 681d ldr r5, [r3, #0]
|
|
8001a96: 4bd5 ldr r3, [pc, #852] @ (8001dec <main+0x364>)
|
|
int32_t integrator_min,
|
|
int32_t integrator_max,
|
|
int32_t out_max,
|
|
int32_t max_output_step)
|
|
{
|
|
pid->kp = kp;
|
|
8001a98: 6836 ldr r6, [r6, #0]
|
|
8001a9a: 681c ldr r4, [r3, #0]
|
|
8001a9c: 4bd4 ldr r3, [pc, #848] @ (8001df0 <main+0x368>)
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001a9e: af15 add r7, sp, #84 @ 0x54
|
|
pid_init(&motor_pid,kp,ki,kd,i_min,i_max,PWM_MAX,pid_max_step);
|
|
8001aa0: 6818 ldr r0, [r3, #0]
|
|
8001aa2: 4bd4 ldr r3, [pc, #848] @ (8001df4 <main+0x36c>)
|
|
8001aa4: 6819 ldr r1, [r3, #0]
|
|
8001aa6: 4bd4 ldr r3, [pc, #848] @ (8001df8 <main+0x370>)
|
|
8001aa8: 681a ldr r2, [r3, #0]
|
|
8001aaa: 4bd4 ldr r3, [pc, #848] @ (8001dfc <main+0x374>)
|
|
|
|
pid->integrator = 0;
|
|
pid->prev_error = 0;
|
|
|
|
pid->integrator_min = integrator_min;
|
|
pid->integrator_max = integrator_max;
|
|
8001aac: 6199 str r1, [r3, #24]
|
|
pid->out_max = out_max;
|
|
8001aae: 2196 movs r1, #150 @ 0x96
|
|
pid->ki = ki;
|
|
8001ab0: 605d str r5, [r3, #4]
|
|
pid->integrator = 0;
|
|
8001ab2: 2500 movs r5, #0
|
|
pid->out_max = out_max;
|
|
8001ab4: 0109 lsls r1, r1, #4
|
|
pid->kp = kp;
|
|
8001ab6: 601e str r6, [r3, #0]
|
|
pid->kd = kd;
|
|
8001ab8: 609c str r4, [r3, #8]
|
|
pid->integrator_min = integrator_min;
|
|
8001aba: 6158 str r0, [r3, #20]
|
|
pid->out_max = out_max;
|
|
8001abc: 61d9 str r1, [r3, #28]
|
|
|
|
pid->max_output_step = max_output_step;
|
|
8001abe: 621a str r2, [r3, #32]
|
|
pid->integrator = 0;
|
|
8001ac0: 60dd str r5, [r3, #12]
|
|
pid->prev_error = 0;
|
|
8001ac2: 611d str r5, [r3, #16]
|
|
pid->last_output = 0;
|
|
8001ac4: 625d str r5, [r3, #36] @ 0x24
|
|
SystemClock_Config();
|
|
8001ac6: f7fe fe59 bl 800077c <SystemClock_Config>
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8001aca: 2214 movs r2, #20
|
|
8001acc: 0029 movs r1, r5
|
|
8001ace: 0038 movs r0, r7
|
|
8001ad0: f003 fbd6 bl 8005280 <memset>
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8001ad4: 2220 movs r2, #32
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001ad6: 2601 movs r6, #1
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8001ad8: 4cc9 ldr r4, [pc, #804] @ (8001e00 <main+0x378>)
|
|
HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
|
|
8001ada: 20a0 movs r0, #160 @ 0xa0
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8001adc: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
|
|
8001ade: 2141 movs r1, #65 @ 0x41
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8001ae0: 4313 orrs r3, r2
|
|
8001ae2: 6363 str r3, [r4, #52] @ 0x34
|
|
8001ae4: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
|
|
8001ae6: 05c0 lsls r0, r0, #23
|
|
__HAL_RCC_GPIOF_CLK_ENABLE();
|
|
8001ae8: 4013 ands r3, r2
|
|
8001aea: 9303 str r3, [sp, #12]
|
|
8001aec: 9b03 ldr r3, [sp, #12]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001aee: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8001af0: 3a1e subs r2, #30
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8001af2: 4333 orrs r3, r6
|
|
8001af4: 6363 str r3, [r4, #52] @ 0x34
|
|
8001af6: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
8001af8: 4033 ands r3, r6
|
|
8001afa: 9304 str r3, [sp, #16]
|
|
8001afc: 9b04 ldr r3, [sp, #16]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
8001afe: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
8001b00: 4313 orrs r3, r2
|
|
8001b02: 6363 str r3, [r4, #52] @ 0x34
|
|
8001b04: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
8001b06: 4013 ands r3, r2
|
|
8001b08: 9305 str r3, [sp, #20]
|
|
8001b0a: 9b05 ldr r3, [sp, #20]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8001b0c: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
8001b0e: 3202 adds r2, #2
|
|
8001b10: 4313 orrs r3, r2
|
|
8001b12: 6363 str r3, [r4, #52] @ 0x34
|
|
8001b14: 6b63 ldr r3, [r4, #52] @ 0x34
|
|
8001b16: 4013 ands r3, r2
|
|
8001b18: 9306 str r3, [sp, #24]
|
|
HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
|
|
8001b1a: 002a movs r2, r5
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
8001b1c: 9b06 ldr r3, [sp, #24]
|
|
HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
|
|
8001b1e: f001 fc13 bl 8003348 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_WritePin(GPIOB, LED_R_Pin|LED_B_Pin|LED_G_Pin, GPIO_PIN_RESET);
|
|
8001b22: 002a movs r2, r5
|
|
8001b24: 2138 movs r1, #56 @ 0x38
|
|
8001b26: 48b7 ldr r0, [pc, #732] @ (8001e04 <main+0x37c>)
|
|
8001b28: f001 fc0e bl 8003348 <HAL_GPIO_WritePin>
|
|
HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
|
|
8001b2c: 20a0 movs r0, #160 @ 0xa0
|
|
GPIO_InitStruct.Pin = USART2_NRE_Pin;
|
|
8001b2e: 9615 str r6, [sp, #84] @ 0x54
|
|
HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
|
|
8001b30: 0039 movs r1, r7
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001b32: 607e str r6, [r7, #4]
|
|
HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
|
|
8001b34: 05c0 lsls r0, r0, #23
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001b36: 60bd str r5, [r7, #8]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001b38: 60fd str r5, [r7, #12]
|
|
HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
|
|
8001b3a: f001 fb45 bl 80031c8 <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = ONEWIRE_Pin;
|
|
8001b3e: 2340 movs r3, #64 @ 0x40
|
|
HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
|
|
8001b40: 20a0 movs r0, #160 @ 0xa0
|
|
GPIO_InitStruct.Pin = ONEWIRE_Pin;
|
|
8001b42: 9315 str r3, [sp, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
|
|
8001b44: 3b2f subs r3, #47 @ 0x2f
|
|
HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
|
|
8001b46: 0039 movs r1, r7
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
|
|
8001b48: 607b str r3, [r7, #4]
|
|
HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
|
|
8001b4a: 05c0 lsls r0, r0, #23
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001b4c: 60bd str r5, [r7, #8]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001b4e: 60fd str r5, [r7, #12]
|
|
HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
|
|
8001b50: f001 fb3a bl 80031c8 <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = LED_R_Pin|LED_B_Pin|LED_G_Pin;
|
|
8001b54: 2338 movs r3, #56 @ 0x38
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001b56: 0039 movs r1, r7
|
|
GPIO_InitStruct.Pin = LED_R_Pin|LED_B_Pin|LED_G_Pin;
|
|
8001b58: 9315 str r3, [sp, #84] @ 0x54
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001b5a: 48aa ldr r0, [pc, #680] @ (8001e04 <main+0x37c>)
|
|
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
|
|
8001b5c: 607e str r6, [r7, #4]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001b5e: 60bd str r5, [r7, #8]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8001b60: 60fd str r5, [r7, #12]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001b62: f001 fb31 bl 80031c8 <HAL_GPIO_Init>
|
|
GPIO_InitStruct.Pin = SW2_Pin|SW1_Pin;
|
|
8001b66: 23c0 movs r3, #192 @ 0xc0
|
|
8001b68: 009b lsls r3, r3, #2
|
|
8001b6a: 9315 str r3, [sp, #84] @ 0x54
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
|
|
8001b6c: 4ba6 ldr r3, [pc, #664] @ (8001e08 <main+0x380>)
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001b6e: 0039 movs r1, r7
|
|
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
|
|
8001b70: 607b str r3, [r7, #4]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001b72: 48a4 ldr r0, [pc, #656] @ (8001e04 <main+0x37c>)
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8001b74: 60bd str r5, [r7, #8]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8001b76: f001 fb27 bl 80031c8 <HAL_GPIO_Init>
|
|
HAL_NVIC_SetPriority(EXTI4_15_IRQn, 0, 0);
|
|
8001b7a: 002a movs r2, r5
|
|
8001b7c: 0029 movs r1, r5
|
|
8001b7e: 2007 movs r0, #7
|
|
8001b80: f001 f928 bl 8002dd4 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(EXTI4_15_IRQn);
|
|
8001b84: 2007 movs r0, #7
|
|
8001b86: f001 f94f bl 8002e28 <HAL_NVIC_EnableIRQ>
|
|
__HAL_RCC_DMA1_CLK_ENABLE();
|
|
8001b8a: 6ba3 ldr r3, [r4, #56] @ 0x38
|
|
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
|
|
8001b8c: 002a movs r2, r5
|
|
__HAL_RCC_DMA1_CLK_ENABLE();
|
|
8001b8e: 4333 orrs r3, r6
|
|
8001b90: 63a3 str r3, [r4, #56] @ 0x38
|
|
8001b92: 6ba3 ldr r3, [r4, #56] @ 0x38
|
|
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
|
|
8001b94: 0029 movs r1, r5
|
|
__HAL_RCC_DMA1_CLK_ENABLE();
|
|
8001b96: 4033 ands r3, r6
|
|
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
|
|
8001b98: 2009 movs r0, #9
|
|
__HAL_RCC_DMA1_CLK_ENABLE();
|
|
8001b9a: 9302 str r3, [sp, #8]
|
|
8001b9c: 9b02 ldr r3, [sp, #8]
|
|
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
|
|
8001b9e: f001 f919 bl 8002dd4 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
|
|
8001ba2: 2009 movs r0, #9
|
|
8001ba4: f001 f940 bl 8002e28 <HAL_NVIC_EnableIRQ>
|
|
HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0);
|
|
8001ba8: 002a movs r2, r5
|
|
8001baa: 0029 movs r1, r5
|
|
8001bac: 200a movs r0, #10
|
|
8001bae: f001 f911 bl 8002dd4 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
|
|
8001bb2: 200a movs r0, #10
|
|
8001bb4: f001 f938 bl 8002e28 <HAL_NVIC_EnableIRQ>
|
|
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
|
|
8001bb8: 2210 movs r2, #16
|
|
8001bba: 0029 movs r1, r5
|
|
8001bbc: a80a add r0, sp, #40 @ 0x28
|
|
8001bbe: f003 fb5f bl 8005280 <memset>
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
8001bc2: ae0e add r6, sp, #56 @ 0x38
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8001bc4: 220c movs r2, #12
|
|
8001bc6: 0029 movs r1, r5
|
|
8001bc8: a807 add r0, sp, #28
|
|
8001bca: f003 fb59 bl 8005280 <memset>
|
|
TIM_OC_InitTypeDef sConfigOC = {0};
|
|
8001bce: 221c movs r2, #28
|
|
8001bd0: 0029 movs r1, r5
|
|
8001bd2: 0030 movs r0, r6
|
|
8001bd4: f003 fb54 bl 8005280 <memset>
|
|
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
|
|
8001bd8: 0029 movs r1, r5
|
|
8001bda: 2234 movs r2, #52 @ 0x34
|
|
8001bdc: 0038 movs r0, r7
|
|
8001bde: f003 fb4f bl 8005280 <memset>
|
|
htim1.Init.Period = 2400;
|
|
8001be2: 2196 movs r1, #150 @ 0x96
|
|
htim1.Instance = TIM1;
|
|
8001be4: 4c89 ldr r4, [pc, #548] @ (8001e0c <main+0x384>)
|
|
8001be6: 4b8a ldr r3, [pc, #552] @ (8001e10 <main+0x388>)
|
|
htim1.Init.Period = 2400;
|
|
8001be8: 0109 lsls r1, r1, #4
|
|
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
|
|
8001bea: 0020 movs r0, r4
|
|
htim1.Instance = TIM1;
|
|
8001bec: 6023 str r3, [r4, #0]
|
|
htim1.Init.Prescaler = 0;
|
|
8001bee: 6065 str r5, [r4, #4]
|
|
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8001bf0: 60a5 str r5, [r4, #8]
|
|
htim1.Init.Period = 2400;
|
|
8001bf2: 60e1 str r1, [r4, #12]
|
|
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8001bf4: 6125 str r5, [r4, #16]
|
|
htim1.Init.RepetitionCounter = 0;
|
|
8001bf6: 6165 str r5, [r4, #20]
|
|
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8001bf8: 61a5 str r5, [r4, #24]
|
|
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
|
|
8001bfa: f002 f92d bl 8003e58 <HAL_TIM_Base_Init>
|
|
8001bfe: 42a8 cmp r0, r5
|
|
8001c00: d001 beq.n 8001c06 <main+0x17e>
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8001c02: b672 cpsid i
|
|
while (1)
|
|
8001c04: e7fe b.n 8001c04 <main+0x17c>
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
8001c06: 2380 movs r3, #128 @ 0x80
|
|
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
|
|
8001c08: 0020 movs r0, r4
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
8001c0a: 015b lsls r3, r3, #5
|
|
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
|
|
8001c0c: a90a add r1, sp, #40 @ 0x28
|
|
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
|
|
8001c0e: 930a str r3, [sp, #40] @ 0x28
|
|
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
|
|
8001c10: f002 fa9a bl 8004148 <HAL_TIM_ConfigClockSource>
|
|
8001c14: 2800 cmp r0, #0
|
|
8001c16: d001 beq.n 8001c1c <main+0x194>
|
|
8001c18: b672 cpsid i
|
|
while (1)
|
|
8001c1a: e7fe b.n 8001c1a <main+0x192>
|
|
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
|
|
8001c1c: 0020 movs r0, r4
|
|
8001c1e: f002 f945 bl 8003eac <HAL_TIM_PWM_Init>
|
|
8001c22: 2800 cmp r0, #0
|
|
8001c24: d001 beq.n 8001c2a <main+0x1a2>
|
|
8001c26: b672 cpsid i
|
|
while (1)
|
|
8001c28: e7fe b.n 8001c28 <main+0x1a0>
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8001c2a: 9007 str r0, [sp, #28]
|
|
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
|
|
8001c2c: 9008 str r0, [sp, #32]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8001c2e: 9009 str r0, [sp, #36] @ 0x24
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
|
|
8001c30: a907 add r1, sp, #28
|
|
8001c32: 0020 movs r0, r4
|
|
8001c34: f002 fbae bl 8004394 <HAL_TIMEx_MasterConfigSynchronization>
|
|
8001c38: 1e02 subs r2, r0, #0
|
|
8001c3a: d001 beq.n 8001c40 <main+0x1b8>
|
|
8001c3c: b672 cpsid i
|
|
while (1)
|
|
8001c3e: e7fe b.n 8001c3e <main+0x1b6>
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
|
8001c40: 2360 movs r3, #96 @ 0x60
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
8001c42: 0031 movs r1, r6
|
|
sConfigOC.OCMode = TIM_OCMODE_PWM1;
|
|
8001c44: 930e str r3, [sp, #56] @ 0x38
|
|
sConfigOC.Pulse = 0;
|
|
8001c46: 6070 str r0, [r6, #4]
|
|
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
|
|
8001c48: 60b0 str r0, [r6, #8]
|
|
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
|
|
8001c4a: 60f0 str r0, [r6, #12]
|
|
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
|
|
8001c4c: 6130 str r0, [r6, #16]
|
|
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
|
|
8001c4e: 6170 str r0, [r6, #20]
|
|
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
|
|
8001c50: 61b0 str r0, [r6, #24]
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
|
|
8001c52: 0020 movs r0, r4
|
|
8001c54: f002 f9e6 bl 8004024 <HAL_TIM_PWM_ConfigChannel>
|
|
8001c58: 2800 cmp r0, #0
|
|
8001c5a: d001 beq.n 8001c60 <main+0x1d8>
|
|
8001c5c: b672 cpsid i
|
|
while (1)
|
|
8001c5e: e7fe b.n 8001c5e <main+0x1d6>
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
|
|
8001c60: 2204 movs r2, #4
|
|
8001c62: 0031 movs r1, r6
|
|
8001c64: 0020 movs r0, r4
|
|
8001c66: f002 f9dd bl 8004024 <HAL_TIM_PWM_ConfigChannel>
|
|
8001c6a: 2800 cmp r0, #0
|
|
8001c6c: d001 beq.n 8001c72 <main+0x1ea>
|
|
8001c6e: b672 cpsid i
|
|
while (1)
|
|
8001c70: e7fe b.n 8001c70 <main+0x1e8>
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
|
|
8001c72: 2208 movs r2, #8
|
|
8001c74: 0031 movs r1, r6
|
|
8001c76: 0020 movs r0, r4
|
|
8001c78: f002 f9d4 bl 8004024 <HAL_TIM_PWM_ConfigChannel>
|
|
8001c7c: 2800 cmp r0, #0
|
|
8001c7e: d001 beq.n 8001c84 <main+0x1fc>
|
|
8001c80: b672 cpsid i
|
|
while (1)
|
|
8001c82: e7fe b.n 8001c82 <main+0x1fa>
|
|
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
|
|
8001c84: 220c movs r2, #12
|
|
8001c86: 0031 movs r1, r6
|
|
8001c88: 0020 movs r0, r4
|
|
8001c8a: f002 f9cb bl 8004024 <HAL_TIM_PWM_ConfigChannel>
|
|
8001c8e: 2800 cmp r0, #0
|
|
8001c90: d001 beq.n 8001c96 <main+0x20e>
|
|
8001c92: b672 cpsid i
|
|
while (1)
|
|
8001c94: e7fe b.n 8001c94 <main+0x20c>
|
|
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
|
|
8001c96: 2380 movs r3, #128 @ 0x80
|
|
8001c98: 019b lsls r3, r3, #6
|
|
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
|
|
8001c9a: 9015 str r0, [sp, #84] @ 0x54
|
|
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
|
|
8001c9c: 617b str r3, [r7, #20]
|
|
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
|
|
8001c9e: 2380 movs r3, #128 @ 0x80
|
|
8001ca0: 049b lsls r3, r3, #18
|
|
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
|
|
8001ca2: 6078 str r0, [r7, #4]
|
|
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
|
|
8001ca4: 60b8 str r0, [r7, #8]
|
|
sBreakDeadTimeConfig.DeadTime = 0;
|
|
8001ca6: 60f8 str r0, [r7, #12]
|
|
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
|
|
8001ca8: 6138 str r0, [r7, #16]
|
|
sBreakDeadTimeConfig.BreakFilter = 0;
|
|
8001caa: 61b8 str r0, [r7, #24]
|
|
sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT;
|
|
8001cac: 61f8 str r0, [r7, #28]
|
|
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
|
|
8001cae: 6238 str r0, [r7, #32]
|
|
sBreakDeadTimeConfig.Break2Filter = 0;
|
|
8001cb0: 62b8 str r0, [r7, #40] @ 0x28
|
|
sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT;
|
|
8001cb2: 62f8 str r0, [r7, #44] @ 0x2c
|
|
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
|
|
8001cb4: 6338 str r0, [r7, #48] @ 0x30
|
|
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
|
|
8001cb6: 0039 movs r1, r7
|
|
8001cb8: 0020 movs r0, r4
|
|
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
|
|
8001cba: 627b str r3, [r7, #36] @ 0x24
|
|
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
|
|
8001cbc: f002 fb9e bl 80043fc <HAL_TIMEx_ConfigBreakDeadTime>
|
|
8001cc0: 1e05 subs r5, r0, #0
|
|
8001cc2: d001 beq.n 8001cc8 <main+0x240>
|
|
8001cc4: b672 cpsid i
|
|
while (1)
|
|
8001cc6: e7fe b.n 8001cc6 <main+0x23e>
|
|
HAL_TIM_MspPostInit(&htim1);
|
|
8001cc8: 0020 movs r0, r4
|
|
8001cca: f000 fc93 bl 80025f4 <HAL_TIM_MspPostInit>
|
|
TIM_Encoder_InitTypeDef sConfig = {0};
|
|
8001cce: 2220 movs r2, #32
|
|
8001cd0: 0029 movs r1, r5
|
|
8001cd2: a816 add r0, sp, #88 @ 0x58
|
|
8001cd4: f003 fad4 bl 8005280 <memset>
|
|
TIM_MasterConfigTypeDef sMasterConfig = {0};
|
|
8001cd8: 220c movs r2, #12
|
|
8001cda: 0029 movs r1, r5
|
|
8001cdc: 0030 movs r0, r6
|
|
8001cde: f003 facf bl 8005280 <memset>
|
|
htim3.Instance = TIM3;
|
|
8001ce2: 4b4c ldr r3, [pc, #304] @ (8001e14 <main+0x38c>)
|
|
htim3.Init.Period = 65535;
|
|
8001ce4: 4c4c ldr r4, [pc, #304] @ (8001e18 <main+0x390>)
|
|
htim3.Instance = TIM3;
|
|
8001ce6: 9300 str r3, [sp, #0]
|
|
8001ce8: 9a00 ldr r2, [sp, #0]
|
|
8001cea: 4b4c ldr r3, [pc, #304] @ (8001e1c <main+0x394>)
|
|
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
|
|
8001cec: 0039 movs r1, r7
|
|
htim3.Instance = TIM3;
|
|
8001cee: 6013 str r3, [r2, #0]
|
|
sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
|
|
8001cf0: 2303 movs r3, #3
|
|
8001cf2: 9315 str r3, [sp, #84] @ 0x54
|
|
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
|
|
8001cf4: 3b02 subs r3, #2
|
|
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
|
|
8001cf6: 0010 movs r0, r2
|
|
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
|
|
8001cf8: 60bb str r3, [r7, #8]
|
|
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
|
|
8001cfa: 61bb str r3, [r7, #24]
|
|
htim3.Init.Prescaler = 0;
|
|
8001cfc: 6055 str r5, [r2, #4]
|
|
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8001cfe: 6095 str r5, [r2, #8]
|
|
htim3.Init.Period = 65535;
|
|
8001d00: 60d4 str r4, [r2, #12]
|
|
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8001d02: 6115 str r5, [r2, #16]
|
|
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8001d04: 6195 str r5, [r2, #24]
|
|
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
|
|
8001d06: f002 f8fb bl 8003f00 <HAL_TIM_Encoder_Init>
|
|
8001d0a: 2800 cmp r0, #0
|
|
8001d0c: d001 beq.n 8001d12 <main+0x28a>
|
|
8001d0e: b672 cpsid i
|
|
while (1)
|
|
8001d10: e7fe b.n 8001d10 <main+0x288>
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8001d12: 2300 movs r3, #0
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
|
8001d14: 0031 movs r1, r6
|
|
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
|
|
8001d16: 930e str r3, [sp, #56] @ 0x38
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
|
8001d18: 9800 ldr r0, [sp, #0]
|
|
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
|
|
8001d1a: 60b3 str r3, [r6, #8]
|
|
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
|
|
8001d1c: f002 fb3a bl 8004394 <HAL_TIMEx_MasterConfigSynchronization>
|
|
8001d20: 2800 cmp r0, #0
|
|
8001d22: d001 beq.n 8001d28 <main+0x2a0>
|
|
8001d24: b672 cpsid i
|
|
while (1)
|
|
8001d26: e7fe b.n 8001d26 <main+0x29e>
|
|
huart1.Instance = USART1;
|
|
8001d28: 4d3d ldr r5, [pc, #244] @ (8001e20 <main+0x398>)
|
|
8001d2a: 4b3e ldr r3, [pc, #248] @ (8001e24 <main+0x39c>)
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8001d2c: 260c movs r6, #12
|
|
huart1.Instance = USART1;
|
|
8001d2e: 602b str r3, [r5, #0]
|
|
huart1.Init.BaudRate = 115200;
|
|
8001d30: 23e1 movs r3, #225 @ 0xe1
|
|
huart1.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8001d32: 60a8 str r0, [r5, #8]
|
|
huart1.Init.BaudRate = 115200;
|
|
8001d34: 025b lsls r3, r3, #9
|
|
huart1.Init.StopBits = UART_STOPBITS_1;
|
|
8001d36: 60e8 str r0, [r5, #12]
|
|
huart1.Init.Parity = UART_PARITY_NONE;
|
|
8001d38: 6128 str r0, [r5, #16]
|
|
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8001d3a: 61a8 str r0, [r5, #24]
|
|
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8001d3c: 61e8 str r0, [r5, #28]
|
|
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8001d3e: 6228 str r0, [r5, #32]
|
|
huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
|
8001d40: 6268 str r0, [r5, #36] @ 0x24
|
|
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8001d42: 62a8 str r0, [r5, #40] @ 0x28
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
8001d44: 0028 movs r0, r5
|
|
huart1.Init.BaudRate = 115200;
|
|
8001d46: 606b str r3, [r5, #4]
|
|
huart1.Init.Mode = UART_MODE_TX_RX;
|
|
8001d48: 616e str r6, [r5, #20]
|
|
if (HAL_UART_Init(&huart1) != HAL_OK)
|
|
8001d4a: f003 f8fd bl 8004f48 <HAL_UART_Init>
|
|
8001d4e: 1e01 subs r1, r0, #0
|
|
8001d50: d001 beq.n 8001d56 <main+0x2ce>
|
|
8001d52: b672 cpsid i
|
|
while (1)
|
|
8001d54: e7fe b.n 8001d54 <main+0x2cc>
|
|
if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
|
|
8001d56: 0028 movs r0, r5
|
|
8001d58: f003 fa10 bl 800517c <HAL_UARTEx_SetTxFifoThreshold>
|
|
8001d5c: 1e01 subs r1, r0, #0
|
|
8001d5e: d001 beq.n 8001d64 <main+0x2dc>
|
|
8001d60: b672 cpsid i
|
|
while (1)
|
|
8001d62: e7fe b.n 8001d62 <main+0x2da>
|
|
if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
|
|
8001d64: 0028 movs r0, r5
|
|
8001d66: f003 fa29 bl 80051bc <HAL_UARTEx_SetRxFifoThreshold>
|
|
8001d6a: 2800 cmp r0, #0
|
|
8001d6c: d001 beq.n 8001d72 <main+0x2ea>
|
|
8001d6e: b672 cpsid i
|
|
while (1)
|
|
8001d70: e7fe b.n 8001d70 <main+0x2e8>
|
|
if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
|
|
8001d72: 0028 movs r0, r5
|
|
8001d74: f003 f9e4 bl 8005140 <HAL_UARTEx_DisableFifoMode>
|
|
8001d78: 1e01 subs r1, r0, #0
|
|
8001d7a: d001 beq.n 8001d80 <main+0x2f8>
|
|
8001d7c: b672 cpsid i
|
|
while (1)
|
|
8001d7e: e7fe b.n 8001d7e <main+0x2f6>
|
|
huart2.Instance = USART2;
|
|
8001d80: 4d29 ldr r5, [pc, #164] @ (8001e28 <main+0x3a0>)
|
|
8001d82: 4b2a ldr r3, [pc, #168] @ (8001e2c <main+0x3a4>)
|
|
huart2.Init.WordLength = UART_WORDLENGTH_8B;
|
|
8001d84: 60a8 str r0, [r5, #8]
|
|
huart2.Instance = USART2;
|
|
8001d86: 602b str r3, [r5, #0]
|
|
huart2.Init.BaudRate = 57600;
|
|
8001d88: 23e1 movs r3, #225 @ 0xe1
|
|
8001d8a: 021b lsls r3, r3, #8
|
|
8001d8c: 606b str r3, [r5, #4]
|
|
if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 31, 31) != HAL_OK)
|
|
8001d8e: 231f movs r3, #31
|
|
huart2.Init.StopBits = UART_STOPBITS_1;
|
|
8001d90: 60e8 str r0, [r5, #12]
|
|
huart2.Init.Parity = UART_PARITY_NONE;
|
|
8001d92: 6128 str r0, [r5, #16]
|
|
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
|
|
8001d94: 61a8 str r0, [r5, #24]
|
|
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
|
|
8001d96: 61e8 str r0, [r5, #28]
|
|
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
|
|
8001d98: 6228 str r0, [r5, #32]
|
|
huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
|
|
8001d9a: 6268 str r0, [r5, #36] @ 0x24
|
|
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
|
|
8001d9c: 62a8 str r0, [r5, #40] @ 0x28
|
|
if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 31, 31) != HAL_OK)
|
|
8001d9e: 001a movs r2, r3
|
|
8001da0: 0028 movs r0, r5
|
|
huart2.Init.Mode = UART_MODE_TX_RX;
|
|
8001da2: 616e str r6, [r5, #20]
|
|
if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 31, 31) != HAL_OK)
|
|
8001da4: f003 f982 bl 80050ac <HAL_RS485Ex_Init>
|
|
8001da8: 2800 cmp r0, #0
|
|
8001daa: d001 beq.n 8001db0 <main+0x328>
|
|
8001dac: b672 cpsid i
|
|
while (1)
|
|
8001dae: e7fe b.n 8001dae <main+0x326>
|
|
if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_2) != HAL_OK)
|
|
8001db0: 2180 movs r1, #128 @ 0x80
|
|
8001db2: 0028 movs r0, r5
|
|
8001db4: 05c9 lsls r1, r1, #23
|
|
8001db6: f003 f9e1 bl 800517c <HAL_UARTEx_SetTxFifoThreshold>
|
|
8001dba: 2800 cmp r0, #0
|
|
8001dbc: d001 beq.n 8001dc2 <main+0x33a>
|
|
8001dbe: b672 cpsid i
|
|
while (1)
|
|
8001dc0: e7fe b.n 8001dc0 <main+0x338>
|
|
if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_2) != HAL_OK)
|
|
8001dc2: 2180 movs r1, #128 @ 0x80
|
|
8001dc4: 0028 movs r0, r5
|
|
8001dc6: 04c9 lsls r1, r1, #19
|
|
8001dc8: f003 f9f8 bl 80051bc <HAL_UARTEx_SetRxFifoThreshold>
|
|
8001dcc: 2800 cmp r0, #0
|
|
8001dce: d001 beq.n 8001dd4 <main+0x34c>
|
|
8001dd0: b672 cpsid i
|
|
while (1)
|
|
8001dd2: e7fe b.n 8001dd2 <main+0x34a>
|
|
if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK)
|
|
8001dd4: 0028 movs r0, r5
|
|
8001dd6: f003 f9b3 bl 8005140 <HAL_UARTEx_DisableFifoMode>
|
|
8001dda: 1e03 subs r3, r0, #0
|
|
8001ddc: d028 beq.n 8001e30 <main+0x3a8>
|
|
8001dde: b672 cpsid i
|
|
while (1)
|
|
8001de0: e7fe b.n 8001de0 <main+0x358>
|
|
8001de2: 46c0 nop @ (mov r8, r8)
|
|
8001de4: 2000001c .word 0x2000001c
|
|
8001de8: 20000020 .word 0x20000020
|
|
8001dec: 20000018 .word 0x20000018
|
|
8001df0: 20000014 .word 0x20000014
|
|
8001df4: 20000010 .word 0x20000010
|
|
8001df8: 2000000c .word 0x2000000c
|
|
8001dfc: 2000012c .word 0x2000012c
|
|
8001e00: 40021000 .word 0x40021000
|
|
8001e04: 50000400 .word 0x50000400
|
|
8001e08: 10210000 .word 0x10210000
|
|
8001e0c: 200012b4 .word 0x200012b4
|
|
8001e10: 40012c00 .word 0x40012c00
|
|
8001e14: 20001268 .word 0x20001268
|
|
8001e18: 0000ffff .word 0x0000ffff
|
|
8001e1c: 40000400 .word 0x40000400
|
|
8001e20: 200010f0 .word 0x200010f0
|
|
8001e24: 40013800 .word 0x40013800
|
|
8001e28: 2000105c .word 0x2000105c
|
|
8001e2c: 40004400 .word 0x40004400
|
|
htim16.Instance = TIM16;
|
|
8001e30: 48d3 ldr r0, [pc, #844] @ (8002180 <main+0x6f8>)
|
|
8001e32: 4ad4 ldr r2, [pc, #848] @ (8002184 <main+0x6fc>)
|
|
htim16.Init.Prescaler = 48000-1;
|
|
8001e34: 4ed4 ldr r6, [pc, #848] @ (8002188 <main+0x700>)
|
|
htim16.Instance = TIM16;
|
|
8001e36: 6002 str r2, [r0, #0]
|
|
htim16.Init.Prescaler = 48000-1;
|
|
8001e38: 6046 str r6, [r0, #4]
|
|
htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8001e3a: 6083 str r3, [r0, #8]
|
|
htim16.Init.Period = 65535;
|
|
8001e3c: 60c4 str r4, [r0, #12]
|
|
htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8001e3e: 6103 str r3, [r0, #16]
|
|
htim16.Init.RepetitionCounter = 0;
|
|
8001e40: 6143 str r3, [r0, #20]
|
|
htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8001e42: 6183 str r3, [r0, #24]
|
|
if (HAL_TIM_Base_Init(&htim16) != HAL_OK)
|
|
8001e44: f002 f808 bl 8003e58 <HAL_TIM_Base_Init>
|
|
8001e48: 2800 cmp r0, #0
|
|
8001e4a: d001 beq.n 8001e50 <main+0x3c8>
|
|
8001e4c: b672 cpsid i
|
|
while (1)
|
|
8001e4e: e7fe b.n 8001e4e <main+0x3c6>
|
|
htim17.Instance = TIM17;
|
|
8001e50: 48ce ldr r0, [pc, #824] @ (800218c <main+0x704>)
|
|
8001e52: 4bcf ldr r3, [pc, #828] @ (8002190 <main+0x708>)
|
|
htim17.Init.Prescaler = 48000-1;
|
|
8001e54: 6046 str r6, [r0, #4]
|
|
htim17.Instance = TIM17;
|
|
8001e56: 6003 str r3, [r0, #0]
|
|
htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8001e58: 2300 movs r3, #0
|
|
htim17.Init.Period = 65535;
|
|
8001e5a: 60c4 str r4, [r0, #12]
|
|
htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8001e5c: 6083 str r3, [r0, #8]
|
|
htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8001e5e: 6103 str r3, [r0, #16]
|
|
htim17.Init.RepetitionCounter = 0;
|
|
8001e60: 6143 str r3, [r0, #20]
|
|
htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8001e62: 6183 str r3, [r0, #24]
|
|
if (HAL_TIM_Base_Init(&htim17) != HAL_OK)
|
|
8001e64: f001 fff8 bl 8003e58 <HAL_TIM_Base_Init>
|
|
8001e68: 2800 cmp r0, #0
|
|
8001e6a: d001 beq.n 8001e70 <main+0x3e8>
|
|
8001e6c: b672 cpsid i
|
|
while (1)
|
|
8001e6e: e7fe b.n 8001e6e <main+0x3e6>
|
|
htim14.Instance = TIM14;
|
|
8001e70: 4bc8 ldr r3, [pc, #800] @ (8002194 <main+0x70c>)
|
|
8001e72: 9301 str r3, [sp, #4]
|
|
8001e74: 9a01 ldr r2, [sp, #4]
|
|
8001e76: 4bc8 ldr r3, [pc, #800] @ (8002198 <main+0x710>)
|
|
htim14.Init.CounterMode = TIM_COUNTERMODE_UP;
|
|
8001e78: 6090 str r0, [r2, #8]
|
|
htim14.Instance = TIM14;
|
|
8001e7a: 6013 str r3, [r2, #0]
|
|
htim14.Init.Prescaler = 480-1;
|
|
8001e7c: 23e0 movs r3, #224 @ 0xe0
|
|
8001e7e: 33ff adds r3, #255 @ 0xff
|
|
8001e80: 6053 str r3, [r2, #4]
|
|
htim14.Init.Period = 50;
|
|
8001e82: 2332 movs r3, #50 @ 0x32
|
|
htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
|
|
8001e84: 6110 str r0, [r2, #16]
|
|
htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
|
|
8001e86: 6190 str r0, [r2, #24]
|
|
if (HAL_TIM_Base_Init(&htim14) != HAL_OK)
|
|
8001e88: 0010 movs r0, r2
|
|
htim14.Init.Period = 50;
|
|
8001e8a: 60d3 str r3, [r2, #12]
|
|
if (HAL_TIM_Base_Init(&htim14) != HAL_OK)
|
|
8001e8c: f001 ffe4 bl 8003e58 <HAL_TIM_Base_Init>
|
|
8001e90: 1e06 subs r6, r0, #0
|
|
8001e92: d001 beq.n 8001e98 <main+0x410>
|
|
8001e94: b672 cpsid i
|
|
while (1)
|
|
8001e96: e7fe b.n 8001e96 <main+0x40e>
|
|
ADC_ChannelConfTypeDef sConfig = {0};
|
|
8001e98: 0001 movs r1, r0
|
|
8001e9a: 220c movs r2, #12
|
|
8001e9c: 0038 movs r0, r7
|
|
8001e9e: f003 f9ef bl 8005280 <memset>
|
|
hadc1.Instance = ADC1;
|
|
8001ea2: 4cbe ldr r4, [pc, #760] @ (800219c <main+0x714>)
|
|
8001ea4: 4bbe ldr r3, [pc, #760] @ (80021a0 <main+0x718>)
|
|
if (HAL_ADC_Init(&hadc1) != HAL_OK)
|
|
8001ea6: 0020 movs r0, r4
|
|
hadc1.Instance = ADC1;
|
|
8001ea8: 6023 str r3, [r4, #0]
|
|
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
|
|
8001eaa: 2380 movs r3, #128 @ 0x80
|
|
8001eac: 05db lsls r3, r3, #23
|
|
8001eae: 6063 str r3, [r4, #4]
|
|
hadc1.Init.ScanConvMode = ADC_SCAN_SEQ_FIXED;
|
|
8001eb0: 2380 movs r3, #128 @ 0x80
|
|
8001eb2: 061b lsls r3, r3, #24
|
|
8001eb4: 6123 str r3, [r4, #16]
|
|
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
|
|
8001eb6: 2304 movs r3, #4
|
|
8001eb8: 6163 str r3, [r4, #20]
|
|
hadc1.Init.NbrOfConversion = 1;
|
|
8001eba: 3b03 subs r3, #3
|
|
8001ebc: 61e3 str r3, [r4, #28]
|
|
hadc1.Init.DiscontinuousConvMode = DISABLE;
|
|
8001ebe: 18e3 adds r3, r4, r3
|
|
8001ec0: 77de strb r6, [r3, #31]
|
|
hadc1.Init.DMAContinuousRequests = DISABLE;
|
|
8001ec2: 0023 movs r3, r4
|
|
8001ec4: 332c adds r3, #44 @ 0x2c
|
|
8001ec6: 701e strb r6, [r3, #0]
|
|
hadc1.Init.OversamplingMode = DISABLE;
|
|
8001ec8: 0023 movs r3, r4
|
|
8001eca: 333c adds r3, #60 @ 0x3c
|
|
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
|
|
8001ecc: 60a6 str r6, [r4, #8]
|
|
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
|
|
8001ece: 60e6 str r6, [r4, #12]
|
|
hadc1.Init.LowPowerAutoWait = DISABLE;
|
|
8001ed0: 8326 strh r6, [r4, #24]
|
|
hadc1.Init.ContinuousConvMode = DISABLE;
|
|
8001ed2: 76a6 strb r6, [r4, #26]
|
|
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
|
|
8001ed4: 6266 str r6, [r4, #36] @ 0x24
|
|
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
|
|
8001ed6: 62a6 str r6, [r4, #40] @ 0x28
|
|
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
|
|
8001ed8: 6326 str r6, [r4, #48] @ 0x30
|
|
hadc1.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_1CYCLE_5;
|
|
8001eda: 6366 str r6, [r4, #52] @ 0x34
|
|
hadc1.Init.OversamplingMode = DISABLE;
|
|
8001edc: 701e strb r6, [r3, #0]
|
|
hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
|
|
8001ede: 64e6 str r6, [r4, #76] @ 0x4c
|
|
if (HAL_ADC_Init(&hadc1) != HAL_OK)
|
|
8001ee0: f000 fd44 bl 800296c <HAL_ADC_Init>
|
|
8001ee4: 2800 cmp r0, #0
|
|
8001ee6: d001 beq.n 8001eec <main+0x464>
|
|
8001ee8: b672 cpsid i
|
|
while (1)
|
|
8001eea: e7fe b.n 8001eea <main+0x462>
|
|
sConfig.Channel = ADC_CHANNEL_7;
|
|
8001eec: 4bad ldr r3, [pc, #692] @ (80021a4 <main+0x71c>)
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
8001eee: 0039 movs r1, r7
|
|
sConfig.Channel = ADC_CHANNEL_7;
|
|
8001ef0: 9315 str r3, [sp, #84] @ 0x54
|
|
sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
|
|
8001ef2: 2301 movs r3, #1
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
8001ef4: 0020 movs r0, r4
|
|
sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
|
|
8001ef6: 607b str r3, [r7, #4]
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
8001ef8: f000 fe48 bl 8002b8c <HAL_ADC_ConfigChannel>
|
|
8001efc: 2800 cmp r0, #0
|
|
8001efe: d001 beq.n 8001f04 <main+0x47c>
|
|
8001f00: b672 cpsid i
|
|
while (1)
|
|
8001f02: e7fe b.n 8001f02 <main+0x47a>
|
|
sConfig.Channel = ADC_CHANNEL_22;
|
|
8001f04: 4ba8 ldr r3, [pc, #672] @ (80021a8 <main+0x720>)
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
8001f06: 0020 movs r0, r4
|
|
8001f08: 0039 movs r1, r7
|
|
sConfig.Channel = ADC_CHANNEL_22;
|
|
8001f0a: 9315 str r3, [sp, #84] @ 0x54
|
|
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
|
|
8001f0c: f000 fe3e bl 8002b8c <HAL_ADC_ConfigChannel>
|
|
8001f10: 1e04 subs r4, r0, #0
|
|
8001f12: d001 beq.n 8001f18 <main+0x490>
|
|
8001f14: b672 cpsid i
|
|
while (1)
|
|
8001f16: e7fe b.n 8001f16 <main+0x48e>
|
|
*puuid = HAL_GetUIDw0();
|
|
8001f18: f000 fd12 bl 8002940 <HAL_GetUIDw0>
|
|
8001f1c: 4ea3 ldr r6, [pc, #652] @ (80021ac <main+0x724>)
|
|
8001f1e: 0a03 lsrs r3, r0, #8
|
|
8001f20: 7030 strb r0, [r6, #0]
|
|
8001f22: 7073 strb r3, [r6, #1]
|
|
8001f24: 0c03 lsrs r3, r0, #16
|
|
8001f26: 0e00 lsrs r0, r0, #24
|
|
8001f28: 70b3 strb r3, [r6, #2]
|
|
8001f2a: 70f0 strb r0, [r6, #3]
|
|
*(puuid+1) = HAL_GetUIDw1();
|
|
8001f2c: f000 fd0e bl 800294c <HAL_GetUIDw1>
|
|
8001f30: 0a03 lsrs r3, r0, #8
|
|
8001f32: 7130 strb r0, [r6, #4]
|
|
8001f34: 7173 strb r3, [r6, #5]
|
|
8001f36: 0c03 lsrs r3, r0, #16
|
|
8001f38: 0e00 lsrs r0, r0, #24
|
|
8001f3a: 71b3 strb r3, [r6, #6]
|
|
8001f3c: 71f0 strb r0, [r6, #7]
|
|
*(puuid+2) = HAL_GetUIDw2();
|
|
8001f3e: f000 fd0b bl 8002958 <HAL_GetUIDw2>
|
|
8001f42: 0a03 lsrs r3, r0, #8
|
|
8001f44: 7230 strb r0, [r6, #8]
|
|
8001f46: 7273 strb r3, [r6, #9]
|
|
8001f48: 0c03 lsrs r3, r0, #16
|
|
8001f4a: 0e00 lsrs r0, r0, #24
|
|
8001f4c: 72f0 strb r0, [r6, #11]
|
|
HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL);
|
|
8001f4e: 213c movs r1, #60 @ 0x3c
|
|
8001f50: 9800 ldr r0, [sp, #0]
|
|
*(puuid+2) = HAL_GetUIDw2();
|
|
8001f52: 72b3 strb r3, [r6, #10]
|
|
HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL);
|
|
8001f54: f001 fe33 bl 8003bbe <HAL_TIM_Encoder_Start>
|
|
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1); // Feed motor
|
|
8001f58: 4e95 ldr r6, [pc, #596] @ (80021b0 <main+0x728>)
|
|
8001f5a: 0021 movs r1, r4
|
|
8001f5c: 0030 movs r0, r6
|
|
8001f5e: f002 fa15 bl 800438c <HAL_TIM_PWM_Start>
|
|
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_2); // Feed motor
|
|
8001f62: 2104 movs r1, #4
|
|
8001f64: 0030 movs r0, r6
|
|
8001f66: f002 fa11 bl 800438c <HAL_TIM_PWM_Start>
|
|
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_3); // Peel motor
|
|
8001f6a: 2108 movs r1, #8
|
|
8001f6c: 0030 movs r0, r6
|
|
8001f6e: f002 fa0d bl 800438c <HAL_TIM_PWM_Start>
|
|
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_4); // Peel motor
|
|
8001f72: 210c movs r1, #12
|
|
8001f74: 0030 movs r0, r6
|
|
8001f76: f002 fa09 bl 800438c <HAL_TIM_PWM_Start>
|
|
HAL_TIM_Base_Start_IT(&htim14);
|
|
8001f7a: 9801 ldr r0, [sp, #4]
|
|
8001f7c: f001 fdee bl 8003b5c <HAL_TIM_Base_Start_IT>
|
|
floor_address = read_floor_address();
|
|
8001f80: f7ff f938 bl 80011f4 <read_floor_address>
|
|
8001f84: 4b8b ldr r3, [pc, #556] @ (80021b4 <main+0x72c>)
|
|
8001f86: 7018 strb r0, [r3, #0]
|
|
if (floor_address == FLOOR_ADDRESS_NOT_DETECTED)
|
|
8001f88: 4b8b ldr r3, [pc, #556] @ (80021b8 <main+0x730>)
|
|
8001f8a: 28ff cmp r0, #255 @ 0xff
|
|
8001f8c: d16c bne.n 8002068 <main+0x5e0>
|
|
set_LED(1, 0, 0); // Red = EEPROM not detected
|
|
8001f8e: 0022 movs r2, r4
|
|
8001f90: 0021 movs r1, r4
|
|
floor_address_status = 0;
|
|
8001f92: 701c strb r4, [r3, #0]
|
|
set_LED(1, 0, 0); // Red = EEPROM not detected
|
|
8001f94: 38fe subs r0, #254 @ 0xfe
|
|
set_LED(0, 0, 1); // Blue = not programmed
|
|
8001f96: f7fe fd81 bl 8000a9c <set_LED>
|
|
for (uint8_t i = 0; i < MSG_BUF_COUNT; i++) msg_buf_empty[i] = 1;
|
|
8001f9a: 2401 movs r4, #1
|
|
{
|
|
8001f9c: 2300 movs r3, #0
|
|
for (uint8_t i = 0; i < MSG_BUF_COUNT; i++) msg_buf_empty[i] = 1;
|
|
8001f9e: 4a87 ldr r2, [pc, #540] @ (80021bc <main+0x734>)
|
|
8001fa0: 9200 str r2, [sp, #0]
|
|
8001fa2: 9a00 ldr r2, [sp, #0]
|
|
8001fa4: 54d4 strb r4, [r2, r3]
|
|
8001fa6: 3301 adds r3, #1
|
|
8001fa8: 2b36 cmp r3, #54 @ 0x36
|
|
8001faa: d1fa bne.n 8001fa2 <main+0x51a>
|
|
HAL_UARTEx_ReceiveToIdle_DMA (&huart2,DMA_buffer,64);
|
|
8001fac: 2240 movs r2, #64 @ 0x40
|
|
8001fae: 4984 ldr r1, [pc, #528] @ (80021c0 <main+0x738>)
|
|
8001fb0: 0028 movs r0, r5
|
|
8001fb2: f003 f925 bl 8005200 <HAL_UARTEx_ReceiveToIdle_DMA>
|
|
__HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT); // Disable half-transfer interrupt
|
|
8001fb6: 2104 movs r1, #4
|
|
8001fb8: 1d2b adds r3, r5, #4
|
|
8001fba: 6fdb ldr r3, [r3, #124] @ 0x7c
|
|
8001fbc: 681a ldr r2, [r3, #0]
|
|
8001fbe: 6813 ldr r3, [r2, #0]
|
|
8001fc0: 438b bics r3, r1
|
|
8001fc2: 6013 str r3, [r2, #0]
|
|
__HAL_UART_ENABLE_IT(&huart2, UART_IT_ERR); // Enable error interrupt for overrun recovery
|
|
8001fc4: 682b ldr r3, [r5, #0]
|
|
8001fc6: 689a ldr r2, [r3, #8]
|
|
8001fc8: 4314 orrs r4, r2
|
|
8001fca: 609c str r4, [r3, #8]
|
|
uint8_t sw1_state = HAL_GPIO_ReadPin(SW1_GPIO_Port, SW1_Pin); // 1 = released, 0 = pressed
|
|
8001fcc: 2180 movs r1, #128 @ 0x80
|
|
8001fce: 487d ldr r0, [pc, #500] @ (80021c4 <main+0x73c>)
|
|
8001fd0: 0089 lsls r1, r1, #2
|
|
8001fd2: f001 f9b3 bl 800333c <HAL_GPIO_ReadPin>
|
|
uint8_t sw2_state = HAL_GPIO_ReadPin(SW2_GPIO_Port, SW2_Pin);
|
|
8001fd6: 2180 movs r1, #128 @ 0x80
|
|
uint8_t sw1_state = HAL_GPIO_ReadPin(SW1_GPIO_Port, SW1_Pin); // 1 = released, 0 = pressed
|
|
8001fd8: 0006 movs r6, r0
|
|
uint8_t sw2_state = HAL_GPIO_ReadPin(SW2_GPIO_Port, SW2_Pin);
|
|
8001fda: 0049 lsls r1, r1, #1
|
|
8001fdc: 4879 ldr r0, [pc, #484] @ (80021c4 <main+0x73c>)
|
|
8001fde: f001 f9ad bl 800333c <HAL_GPIO_ReadPin>
|
|
if (driving)
|
|
8001fe2: 4f79 ldr r7, [pc, #484] @ (80021c8 <main+0x740>)
|
|
8001fe4: 783c ldrb r4, [r7, #0]
|
|
8001fe6: 2c00 cmp r4, #0
|
|
8001fe8: d06e beq.n 80020c8 <main+0x640>
|
|
if ((driving_direction && sw2_state) || (!driving_direction && sw1_state))
|
|
8001fea: 4b78 ldr r3, [pc, #480] @ (80021cc <main+0x744>)
|
|
8001fec: 7819 ldrb r1, [r3, #0]
|
|
8001fee: 2900 cmp r1, #0
|
|
8001ff0: d050 beq.n 8002094 <main+0x60c>
|
|
8001ff2: 2800 cmp r0, #0
|
|
8001ff4: d150 bne.n 8002098 <main+0x610>
|
|
else if (!drive_mode)
|
|
8001ff6: 4b76 ldr r3, [pc, #472] @ (80021d0 <main+0x748>)
|
|
8001ff8: 781b ldrb r3, [r3, #0]
|
|
8001ffa: 2b00 cmp r3, #0
|
|
8001ffc: d107 bne.n 800200e <main+0x586>
|
|
target_count = total_count + 10000;
|
|
8001ffe: 4b75 ldr r3, [pc, #468] @ (80021d4 <main+0x74c>)
|
|
8002000: 4a75 ldr r2, [pc, #468] @ (80021d8 <main+0x750>)
|
|
8002002: 681b ldr r3, [r3, #0]
|
|
if (driving_direction)
|
|
8002004: 2900 cmp r1, #0
|
|
8002006: d05d beq.n 80020c4 <main+0x63c>
|
|
target_count = total_count + 10000;
|
|
8002008: 4974 ldr r1, [pc, #464] @ (80021dc <main+0x754>)
|
|
target_count = total_count - 10000;
|
|
800200a: 185b adds r3, r3, r1
|
|
800200c: 6013 str r3, [r2, #0]
|
|
feed_state_machine_update();
|
|
800200e: f7fe fec5 bl 8000d9c <feed_state_machine_update>
|
|
peel_ramp_update();
|
|
8002012: f7fe fda1 bl 8000b58 <peel_ramp_update>
|
|
debug_output();
|
|
8002016: f7ff fbf7 bl 8001808 <debug_output>
|
|
if (feed_just_completed)
|
|
800201a: 4b71 ldr r3, [pc, #452] @ (80021e0 <main+0x758>)
|
|
800201c: 781a ldrb r2, [r3, #0]
|
|
800201e: 2a00 cmp r2, #0
|
|
8002020: d00c beq.n 800203c <main+0x5b4>
|
|
feed_just_completed = 0;
|
|
8002022: 2100 movs r1, #0
|
|
8002024: 7019 strb r1, [r3, #0]
|
|
if (last_feed_status == STATUS_OK)
|
|
8002026: 4b6f ldr r3, [pc, #444] @ (80021e4 <main+0x75c>)
|
|
8002028: 7818 ldrb r0, [r3, #0]
|
|
800202a: 4288 cmp r0, r1
|
|
800202c: d000 beq.n 8002030 <main+0x5a8>
|
|
800202e: e1cc b.n 80023ca <main+0x942>
|
|
set_LED(0, 0, 0); // Success - LED off
|
|
8002030: 0002 movs r2, r0
|
|
8002032: 0001 movs r1, r0
|
|
8002034: f7fe fd32 bl 8000a9c <set_LED>
|
|
reset_position_if_needed();
|
|
8002038: f7ff fcea bl 8001a10 <reset_position_if_needed>
|
|
uint16_t time2 = sw2_pressed ? htim17.Instance->CNT : 0;
|
|
800203c: 2400 movs r4, #0
|
|
msg_buf_empty[bi] = 1;
|
|
800203e: 2601 movs r6, #1
|
|
if (!msg_buf_empty[bi])
|
|
8002040: 9b00 ldr r3, [sp, #0]
|
|
8002042: 5d1b ldrb r3, [r3, r4]
|
|
8002044: b2df uxtb r7, r3
|
|
8002046: 2b00 cmp r3, #0
|
|
8002048: d10a bne.n 8002060 <main+0x5d8>
|
|
handleRS485Message(msg_buf[bi], msg_buf_size[bi]);
|
|
800204a: 4d67 ldr r5, [pc, #412] @ (80021e8 <main+0x760>)
|
|
800204c: 4b67 ldr r3, [pc, #412] @ (80021ec <main+0x764>)
|
|
800204e: 5d29 ldrb r1, [r5, r4]
|
|
8002050: 01a0 lsls r0, r4, #6
|
|
8002052: 18c0 adds r0, r0, r3
|
|
8002054: b2c9 uxtb r1, r1
|
|
8002056: f7ff f94d bl 80012f4 <handleRS485Message>
|
|
msg_buf_empty[bi] = 1;
|
|
800205a: 9b00 ldr r3, [sp, #0]
|
|
msg_buf_size[bi] = 0;
|
|
800205c: 552f strb r7, [r5, r4]
|
|
msg_buf_empty[bi] = 1;
|
|
800205e: 551e strb r6, [r3, r4]
|
|
for (uint8_t bi = 0; bi < MSG_BUF_COUNT; bi++)
|
|
8002060: 3401 adds r4, #1
|
|
8002062: 2c36 cmp r4, #54 @ 0x36
|
|
8002064: d1ec bne.n 8002040 <main+0x5b8>
|
|
8002066: e7b1 b.n 8001fcc <main+0x544>
|
|
else if (floor_address == FLOOR_ADDRESS_NOT_PROGRAMMED)
|
|
8002068: 2800 cmp r0, #0
|
|
800206a: d103 bne.n 8002074 <main+0x5ec>
|
|
floor_address_status = 1;
|
|
800206c: 2201 movs r2, #1
|
|
set_LED(0, 0, 1); // Blue = not programmed
|
|
800206e: 0001 movs r1, r0
|
|
floor_address_status = 1;
|
|
8002070: 701a strb r2, [r3, #0]
|
|
set_LED(0, 0, 1); // Blue = not programmed
|
|
8002072: e790 b.n 8001f96 <main+0x50e>
|
|
floor_address_status = 2;
|
|
8002074: 2202 movs r2, #2
|
|
8002076: 701a strb r2, [r3, #0]
|
|
my_address = floor_address;
|
|
8002078: 4b5d ldr r3, [pc, #372] @ (80021f0 <main+0x768>)
|
|
set_LED(0, 1, 0); // Green briefly = valid address
|
|
800207a: 0022 movs r2, r4
|
|
800207c: 2101 movs r1, #1
|
|
my_address = floor_address;
|
|
800207e: 7018 strb r0, [r3, #0]
|
|
set_LED(0, 1, 0); // Green briefly = valid address
|
|
8002080: 0020 movs r0, r4
|
|
8002082: f7fe fd0b bl 8000a9c <set_LED>
|
|
HAL_Delay(200);
|
|
8002086: 20c8 movs r0, #200 @ 0xc8
|
|
8002088: f000 fc48 bl 800291c <HAL_Delay>
|
|
set_LED(0, 0, 0);
|
|
800208c: 0022 movs r2, r4
|
|
800208e: 0021 movs r1, r4
|
|
8002090: 0020 movs r0, r4
|
|
8002092: e780 b.n 8001f96 <main+0x50e>
|
|
if ((driving_direction && sw2_state) || (!driving_direction && sw1_state))
|
|
8002094: 2e00 cmp r6, #0
|
|
8002096: d0ae beq.n 8001ff6 <main+0x56e>
|
|
driving = 0;
|
|
8002098: 2400 movs r4, #0
|
|
halt_all();
|
|
800209a: f7fe fdb7 bl 8000c0c <halt_all>
|
|
HAL_TIM_Base_Stop(&htim16);
|
|
800209e: 4838 ldr r0, [pc, #224] @ (8002180 <main+0x6f8>)
|
|
driving = 0;
|
|
80020a0: 703c strb r4, [r7, #0]
|
|
HAL_TIM_Base_Stop(&htim16);
|
|
80020a2: f001 fd45 bl 8003b30 <HAL_TIM_Base_Stop>
|
|
HAL_TIM_Base_Stop(&htim17);
|
|
80020a6: 4839 ldr r0, [pc, #228] @ (800218c <main+0x704>)
|
|
80020a8: f001 fd42 bl 8003b30 <HAL_TIM_Base_Stop>
|
|
sw1_pressed = 0;
|
|
80020ac: 4b51 ldr r3, [pc, #324] @ (80021f4 <main+0x76c>)
|
|
80020ae: 701c strb r4, [r3, #0]
|
|
sw2_pressed = 0;
|
|
80020b0: 4b51 ldr r3, [pc, #324] @ (80021f8 <main+0x770>)
|
|
80020b2: 701c strb r4, [r3, #0]
|
|
sw1_long_handled = 0;
|
|
80020b4: 4b51 ldr r3, [pc, #324] @ (80021fc <main+0x774>)
|
|
80020b6: 701c strb r4, [r3, #0]
|
|
sw2_long_handled = 0;
|
|
80020b8: 4b51 ldr r3, [pc, #324] @ (8002200 <main+0x778>)
|
|
80020ba: 701c strb r4, [r3, #0]
|
|
set_LED(0, 0, 0);
|
|
80020bc: 0022 movs r2, r4
|
|
set_LED(0, 0, 1); // Blue = tape mode
|
|
80020be: 0021 movs r1, r4
|
|
80020c0: 0020 movs r0, r4
|
|
80020c2: e038 b.n 8002136 <main+0x6ae>
|
|
target_count = total_count - 10000;
|
|
80020c4: 494f ldr r1, [pc, #316] @ (8002204 <main+0x77c>)
|
|
80020c6: e7a0 b.n 800200a <main+0x582>
|
|
else if (both_pressed_handled)
|
|
80020c8: 4b4f ldr r3, [pc, #316] @ (8002208 <main+0x780>)
|
|
80020ca: 469c mov ip, r3
|
|
80020cc: 781b ldrb r3, [r3, #0]
|
|
80020ce: 2b00 cmp r3, #0
|
|
80020d0: d049 beq.n 8002166 <main+0x6de>
|
|
if (sw1_state && sw2_state)
|
|
80020d2: 2e00 cmp r6, #0
|
|
80020d4: d016 beq.n 8002104 <main+0x67c>
|
|
80020d6: 2800 cmp r0, #0
|
|
80020d8: d014 beq.n 8002104 <main+0x67c>
|
|
both_pressed_handled = 0;
|
|
80020da: 4663 mov r3, ip
|
|
HAL_TIM_Base_Stop(&htim16);
|
|
80020dc: 4828 ldr r0, [pc, #160] @ (8002180 <main+0x6f8>)
|
|
both_pressed_handled = 0;
|
|
80020de: 701c strb r4, [r3, #0]
|
|
HAL_TIM_Base_Stop(&htim16);
|
|
80020e0: f001 fd26 bl 8003b30 <HAL_TIM_Base_Stop>
|
|
HAL_TIM_Base_Stop(&htim17);
|
|
80020e4: 4829 ldr r0, [pc, #164] @ (800218c <main+0x704>)
|
|
80020e6: f001 fd23 bl 8003b30 <HAL_TIM_Base_Stop>
|
|
HAL_Delay(400);
|
|
80020ea: 20c8 movs r0, #200 @ 0xc8
|
|
sw1_pressed = 0;
|
|
80020ec: 4b41 ldr r3, [pc, #260] @ (80021f4 <main+0x76c>)
|
|
HAL_Delay(400);
|
|
80020ee: 0040 lsls r0, r0, #1
|
|
sw1_pressed = 0;
|
|
80020f0: 701c strb r4, [r3, #0]
|
|
sw2_pressed = 0;
|
|
80020f2: 4b41 ldr r3, [pc, #260] @ (80021f8 <main+0x770>)
|
|
80020f4: 701c strb r4, [r3, #0]
|
|
sw1_long_handled = 0;
|
|
80020f6: 4b41 ldr r3, [pc, #260] @ (80021fc <main+0x774>)
|
|
80020f8: 701c strb r4, [r3, #0]
|
|
sw2_long_handled = 0;
|
|
80020fa: 4b41 ldr r3, [pc, #260] @ (8002200 <main+0x778>)
|
|
80020fc: 701c strb r4, [r3, #0]
|
|
HAL_Delay(400);
|
|
80020fe: f000 fc0d bl 800291c <HAL_Delay>
|
|
8002102: e7db b.n 80020bc <main+0x634>
|
|
uint32_t hold_time = HAL_GetTick() - both_pressed_start;
|
|
8002104: f000 fc04 bl 8002910 <HAL_GetTick>
|
|
8002108: 4b40 ldr r3, [pc, #256] @ (800220c <main+0x784>)
|
|
800210a: 681b ldr r3, [r3, #0]
|
|
800210c: 1ac0 subs r0, r0, r3
|
|
if (hold_time > 2000 && hold_time < 2100)
|
|
800210e: 4b40 ldr r3, [pc, #256] @ (8002210 <main+0x788>)
|
|
8002110: 18c3 adds r3, r0, r3
|
|
8002112: 2b62 cmp r3, #98 @ 0x62
|
|
8002114: d802 bhi.n 800211c <main+0x694>
|
|
show_version();
|
|
8002116: f7fe fdb1 bl 8000c7c <show_version>
|
|
800211a: e778 b.n 800200e <main+0x586>
|
|
else if (hold_time > 4000 && hold_time < 6000)
|
|
800211c: 4b3d ldr r3, [pc, #244] @ (8002214 <main+0x78c>)
|
|
800211e: 4a3e ldr r2, [pc, #248] @ (8002218 <main+0x790>)
|
|
8002120: 18c3 adds r3, r0, r3
|
|
8002122: 4293 cmp r3, r2
|
|
8002124: d80a bhi.n 800213c <main+0x6b4>
|
|
set_LED((hold_time / 100) % 2, 0, !((hold_time / 100) % 2));
|
|
8002126: 2164 movs r1, #100 @ 0x64
|
|
8002128: f7fe f802 bl 8000130 <__udivsi3>
|
|
800212c: 2301 movs r3, #1
|
|
800212e: 001a movs r2, r3
|
|
8002130: 2100 movs r1, #0
|
|
8002132: 4382 bics r2, r0
|
|
8002134: 4018 ands r0, r3
|
|
if (!driving) set_LED(0, 0, 0);
|
|
8002136: f7fe fcb1 bl 8000a9c <set_LED>
|
|
800213a: e768 b.n 800200e <main+0x586>
|
|
else if (hold_time >= 6000)
|
|
800213c: 4b37 ldr r3, [pc, #220] @ (800221c <main+0x794>)
|
|
800213e: 4298 cmp r0, r3
|
|
8002140: d800 bhi.n 8002144 <main+0x6bc>
|
|
8002142: e764 b.n 800200e <main+0x586>
|
|
set_LED(1, 0, 1);
|
|
8002144: 2201 movs r2, #1
|
|
8002146: 2100 movs r1, #0
|
|
8002148: 0010 movs r0, r2
|
|
800214a: f7fe fca7 bl 8000a9c <set_LED>
|
|
HAL_Delay(100);
|
|
800214e: 2064 movs r0, #100 @ 0x64
|
|
8002150: f000 fbe4 bl 800291c <HAL_Delay>
|
|
__ASM volatile ("dsb 0xF":::"memory");
|
|
8002154: f3bf 8f4f dsb sy
|
|
*/
|
|
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
|
{
|
|
__DSB(); /* Ensure all outstanding memory accesses included
|
|
buffered write are completed before reset */
|
|
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
|
8002158: 4b31 ldr r3, [pc, #196] @ (8002220 <main+0x798>)
|
|
800215a: 4a32 ldr r2, [pc, #200] @ (8002224 <main+0x79c>)
|
|
800215c: 60da str r2, [r3, #12]
|
|
800215e: f3bf 8f4f dsb sy
|
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
|
__DSB(); /* Ensure completion of memory access */
|
|
|
|
for(;;) /* wait until reset */
|
|
{
|
|
__NOP();
|
|
8002162: 46c0 nop @ (mov r8, r8)
|
|
for(;;) /* wait until reset */
|
|
8002164: e7fd b.n 8002162 <main+0x6da>
|
|
else if (sw1_pressed || sw2_pressed)
|
|
8002166: 4a23 ldr r2, [pc, #140] @ (80021f4 <main+0x76c>)
|
|
8002168: 7814 ldrb r4, [r2, #0]
|
|
800216a: 9201 str r2, [sp, #4]
|
|
800216c: 4a22 ldr r2, [pc, #136] @ (80021f8 <main+0x770>)
|
|
800216e: 7815 ldrb r5, [r2, #0]
|
|
8002170: 2c00 cmp r4, #0
|
|
8002172: d159 bne.n 8002228 <main+0x7a0>
|
|
8002174: 2d00 cmp r5, #0
|
|
8002176: d100 bne.n 800217a <main+0x6f2>
|
|
8002178: e749 b.n 800200e <main+0x586>
|
|
uint16_t time1 = sw1_pressed ? htim16.Instance->CNT : 0;
|
|
800217a: 0022 movs r2, r4
|
|
800217c: e05a b.n 8002234 <main+0x7ac>
|
|
800217e: 46c0 nop @ (mov r8, r8)
|
|
8002180: 200011d0 .word 0x200011d0
|
|
8002184: 40014400 .word 0x40014400
|
|
8002188: 0000bb7f .word 0x0000bb7f
|
|
800218c: 20001184 .word 0x20001184
|
|
8002190: 40014800 .word 0x40014800
|
|
8002194: 2000121c .word 0x2000121c
|
|
8002198: 40002000 .word 0x40002000
|
|
800219c: 20001300 .word 0x20001300
|
|
80021a0: 40012400 .word 0x40012400
|
|
80021a4: 1c000080 .word 0x1c000080
|
|
80021a8: 58400000 .word 0x58400000
|
|
80021ac: 20000f8b .word 0x20000f8b
|
|
80021b0: 200012b4 .word 0x200012b4
|
|
80021b4: 20000001 .word 0x20000001
|
|
80021b8: 200000ec .word 0x200000ec
|
|
80021bc: 20000f54 .word 0x20000f54
|
|
80021c0: 2000015e .word 0x2000015e
|
|
80021c4: 50000400 .word 0x50000400
|
|
80021c8: 200000f8 .word 0x200000f8
|
|
80021cc: 200000f7 .word 0x200000f7
|
|
80021d0: 200000f9 .word 0x200000f9
|
|
80021d4: 20000158 .word 0x20000158
|
|
80021d8: 20000154 .word 0x20000154
|
|
80021dc: 00002710 .word 0x00002710
|
|
80021e0: 20000124 .word 0x20000124
|
|
80021e4: 20000126 .word 0x20000126
|
|
80021e8: 20000f1e .word 0x20000f1e
|
|
80021ec: 2000019e .word 0x2000019e
|
|
80021f0: 20000024 .word 0x20000024
|
|
80021f4: 20000fa1 .word 0x20000fa1
|
|
80021f8: 20000fa0 .word 0x20000fa0
|
|
80021fc: 200000f6 .word 0x200000f6
|
|
8002200: 200000f5 .word 0x200000f5
|
|
8002204: ffffd8f0 .word 0xffffd8f0
|
|
8002208: 200000f4 .word 0x200000f4
|
|
800220c: 200000f0 .word 0x200000f0
|
|
8002210: fffff82f .word 0xfffff82f
|
|
8002214: fffff05f .word 0xfffff05f
|
|
8002218: 000007ce .word 0x000007ce
|
|
800221c: 0000176f .word 0x0000176f
|
|
8002220: e000ed00 .word 0xe000ed00
|
|
8002224: 05fa0004 .word 0x05fa0004
|
|
8002228: 4a6a ldr r2, [pc, #424] @ (80023d4 <main+0x94c>)
|
|
800222a: 6812 ldr r2, [r2, #0]
|
|
800222c: 6a52 ldr r2, [r2, #36] @ 0x24
|
|
800222e: b292 uxth r2, r2
|
|
uint16_t time2 = sw2_pressed ? htim17.Instance->CNT : 0;
|
|
8002230: 2d00 cmp r5, #0
|
|
8002232: d003 beq.n 800223c <main+0x7b4>
|
|
8002234: 4b68 ldr r3, [pc, #416] @ (80023d8 <main+0x950>)
|
|
8002236: 681b ldr r3, [r3, #0]
|
|
8002238: 6a5b ldr r3, [r3, #36] @ 0x24
|
|
800223a: b29b uxth r3, r3
|
|
uint16_t max_time = (time1 > time2) ? time1 : time2;
|
|
800223c: 1c11 adds r1, r2, #0
|
|
800223e: 429a cmp r2, r3
|
|
8002240: d200 bcs.n 8002244 <main+0x7bc>
|
|
8002242: 1c19 adds r1, r3, #0
|
|
if (max_time < 100)
|
|
8002244: b289 uxth r1, r1
|
|
8002246: 2963 cmp r1, #99 @ 0x63
|
|
8002248: d800 bhi.n 800224c <main+0x7c4>
|
|
800224a: e6e0 b.n 800200e <main+0x586>
|
|
else if (sw1_pressed && sw2_pressed && !sw1_state && !sw2_state)
|
|
800224c: 2c00 cmp r4, #0
|
|
800224e: d061 beq.n 8002314 <main+0x88c>
|
|
8002250: 2d00 cmp r5, #0
|
|
8002252: d017 beq.n 8002284 <main+0x7fc>
|
|
8002254: 0034 movs r4, r6
|
|
8002256: 4304 orrs r4, r0
|
|
8002258: b2e4 uxtb r4, r4
|
|
800225a: 2c00 cmp r4, #0
|
|
800225c: d000 beq.n 8002260 <main+0x7d8>
|
|
800225e: e09f b.n 80023a0 <main+0x918>
|
|
both_pressed_handled = 1;
|
|
8002260: 4663 mov r3, ip
|
|
8002262: 2501 movs r5, #1
|
|
8002264: 701d strb r5, [r3, #0]
|
|
both_pressed_start = HAL_GetTick();
|
|
8002266: f000 fb53 bl 8002910 <HAL_GetTick>
|
|
800226a: 4b5c ldr r3, [pc, #368] @ (80023dc <main+0x954>)
|
|
800226c: 6018 str r0, [r3, #0]
|
|
if (drive_mode)
|
|
800226e: 4b5c ldr r3, [pc, #368] @ (80023e0 <main+0x958>)
|
|
8002270: 781a ldrb r2, [r3, #0]
|
|
8002272: 2a00 cmp r2, #0
|
|
8002274: d002 beq.n 800227c <main+0x7f4>
|
|
set_LED(0, 0, 1); // Blue = tape mode
|
|
8002276: 002a movs r2, r5
|
|
drive_mode = 0;
|
|
8002278: 701c strb r4, [r3, #0]
|
|
set_LED(0, 0, 1); // Blue = tape mode
|
|
800227a: e720 b.n 80020be <main+0x636>
|
|
set_LED(1, 1, 0); // Yellow = peel mode
|
|
800227c: 0029 movs r1, r5
|
|
800227e: 0028 movs r0, r5
|
|
drive_mode = 1;
|
|
8002280: 701d strb r5, [r3, #0]
|
|
set_LED(1, 1, 0); // Yellow = peel mode
|
|
8002282: e758 b.n 8002136 <main+0x6ae>
|
|
if (!sw1_state && time1 > 2000 && !sw1_long_handled)
|
|
8002284: 2e00 cmp r6, #0
|
|
8002286: d120 bne.n 80022ca <main+0x842>
|
|
8002288: 23fa movs r3, #250 @ 0xfa
|
|
800228a: 00db lsls r3, r3, #3
|
|
800228c: 429a cmp r2, r3
|
|
800228e: d800 bhi.n 8002292 <main+0x80a>
|
|
8002290: e6bd b.n 800200e <main+0x586>
|
|
8002292: 4b54 ldr r3, [pc, #336] @ (80023e4 <main+0x95c>)
|
|
8002294: 781a ldrb r2, [r3, #0]
|
|
8002296: 2a00 cmp r2, #0
|
|
8002298: d000 beq.n 800229c <main+0x814>
|
|
800229a: e6b8 b.n 800200e <main+0x586>
|
|
sw1_long_handled = 1;
|
|
800229c: 2001 movs r0, #1
|
|
set_LED(1, 1, 1);
|
|
800229e: 0002 movs r2, r0
|
|
80022a0: 0001 movs r1, r0
|
|
sw1_long_handled = 1;
|
|
80022a2: 7018 strb r0, [r3, #0]
|
|
set_LED(1, 1, 1);
|
|
80022a4: f7fe fbfa bl 8000a9c <set_LED>
|
|
if (drive_mode)
|
|
80022a8: 4b4d ldr r3, [pc, #308] @ (80023e0 <main+0x958>)
|
|
80022aa: 781b ldrb r3, [r3, #0]
|
|
80022ac: 2b00 cmp r3, #0
|
|
80022ae: d008 beq.n 80022c2 <main+0x83a>
|
|
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
|
|
80022b0: 4b4d ldr r3, [pc, #308] @ (80023e8 <main+0x960>)
|
|
80022b2: 4a4e ldr r2, [pc, #312] @ (80023ec <main+0x964>)
|
|
80022b4: 801a strh r2, [r3, #0]
|
|
driving = 1;
|
|
80022b6: 2301 movs r3, #1
|
|
driving_direction = 0;
|
|
80022b8: 2200 movs r2, #0
|
|
driving = 1;
|
|
80022ba: 703b strb r3, [r7, #0]
|
|
driving_direction = 0;
|
|
80022bc: 4b4c ldr r3, [pc, #304] @ (80023f0 <main+0x968>)
|
|
80022be: 701a strb r2, [r3, #0]
|
|
80022c0: e6a5 b.n 800200e <main+0x586>
|
|
drive_continuous(0);
|
|
80022c2: 0028 movs r0, r5
|
|
80022c4: f7fe fc8e bl 8000be4 <drive_continuous>
|
|
80022c8: e7f5 b.n 80022b6 <main+0x82e>
|
|
else if (sw1_state && time1 <= 2000 && time1 > 100)
|
|
80022ca: 3a65 subs r2, #101 @ 0x65
|
|
80022cc: 4b49 ldr r3, [pc, #292] @ (80023f4 <main+0x96c>)
|
|
80022ce: b292 uxth r2, r2
|
|
80022d0: 4e40 ldr r6, [pc, #256] @ (80023d4 <main+0x94c>)
|
|
80022d2: 4c44 ldr r4, [pc, #272] @ (80023e4 <main+0x95c>)
|
|
80022d4: 429a cmp r2, r3
|
|
80022d6: d80f bhi.n 80022f8 <main+0x870>
|
|
set_LED(1, 1, 1);
|
|
80022d8: 2201 movs r2, #1
|
|
80022da: 0011 movs r1, r2
|
|
80022dc: 0010 movs r0, r2
|
|
80022de: f7fe fbdd bl 8000a9c <set_LED>
|
|
start_feed(20, 0);
|
|
80022e2: 0029 movs r1, r5
|
|
80022e4: 2014 movs r0, #20
|
|
80022e6: f7fe fcdb bl 8000ca0 <start_feed>
|
|
HAL_TIM_Base_Stop(&htim16);
|
|
80022ea: 0030 movs r0, r6
|
|
80022ec: f001 fc20 bl 8003b30 <HAL_TIM_Base_Stop>
|
|
sw1_pressed = 0;
|
|
80022f0: 4b41 ldr r3, [pc, #260] @ (80023f8 <main+0x970>)
|
|
sw1_long_handled = 0;
|
|
80022f2: 7025 strb r5, [r4, #0]
|
|
sw1_pressed = 0;
|
|
80022f4: 701d strb r5, [r3, #0]
|
|
sw1_long_handled = 0;
|
|
80022f6: e68a b.n 800200e <main+0x586>
|
|
HAL_TIM_Base_Stop(&htim16);
|
|
80022f8: 0030 movs r0, r6
|
|
80022fa: f001 fc19 bl 8003b30 <HAL_TIM_Base_Stop>
|
|
sw1_pressed = 0;
|
|
80022fe: 9b01 ldr r3, [sp, #4]
|
|
sw1_long_handled = 0;
|
|
8002300: 7025 strb r5, [r4, #0]
|
|
sw1_pressed = 0;
|
|
8002302: 701d strb r5, [r3, #0]
|
|
if (!driving) set_LED(0, 0, 0);
|
|
8002304: 783b ldrb r3, [r7, #0]
|
|
8002306: 2b00 cmp r3, #0
|
|
8002308: d000 beq.n 800230c <main+0x884>
|
|
800230a: e680 b.n 800200e <main+0x586>
|
|
800230c: 2200 movs r2, #0
|
|
800230e: 0011 movs r1, r2
|
|
8002310: 0010 movs r0, r2
|
|
8002312: e710 b.n 8002136 <main+0x6ae>
|
|
else if (sw2_pressed && !sw1_pressed)
|
|
8002314: 2d00 cmp r5, #0
|
|
8002316: d043 beq.n 80023a0 <main+0x918>
|
|
if (!sw2_state && time2 > 2000 && !sw2_long_handled)
|
|
8002318: 2800 cmp r0, #0
|
|
800231a: d123 bne.n 8002364 <main+0x8dc>
|
|
800231c: 22fa movs r2, #250 @ 0xfa
|
|
800231e: 00d2 lsls r2, r2, #3
|
|
8002320: 4293 cmp r3, r2
|
|
8002322: d800 bhi.n 8002326 <main+0x89e>
|
|
8002324: e673 b.n 800200e <main+0x586>
|
|
8002326: 4b35 ldr r3, [pc, #212] @ (80023fc <main+0x974>)
|
|
8002328: 781a ldrb r2, [r3, #0]
|
|
800232a: 2a00 cmp r2, #0
|
|
800232c: d000 beq.n 8002330 <main+0x8a8>
|
|
800232e: e66e b.n 800200e <main+0x586>
|
|
sw2_long_handled = 1;
|
|
8002330: 3001 adds r0, #1
|
|
set_LED(1, 1, 1);
|
|
8002332: 0002 movs r2, r0
|
|
8002334: 0001 movs r1, r0
|
|
sw2_long_handled = 1;
|
|
8002336: 7018 strb r0, [r3, #0]
|
|
set_LED(1, 1, 1);
|
|
8002338: f7fe fbb0 bl 8000a9c <set_LED>
|
|
if (drive_mode)
|
|
800233c: 4b28 ldr r3, [pc, #160] @ (80023e0 <main+0x958>)
|
|
800233e: 781b ldrb r3, [r3, #0]
|
|
8002340: 2b00 cmp r3, #0
|
|
8002342: d008 beq.n 8002356 <main+0x8ce>
|
|
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
|
|
8002344: 2296 movs r2, #150 @ 0x96
|
|
8002346: 4b28 ldr r3, [pc, #160] @ (80023e8 <main+0x960>)
|
|
8002348: 0112 lsls r2, r2, #4
|
|
800234a: 801a strh r2, [r3, #0]
|
|
driving = 1;
|
|
800234c: 2301 movs r3, #1
|
|
driving_direction = 1;
|
|
800234e: 4a28 ldr r2, [pc, #160] @ (80023f0 <main+0x968>)
|
|
driving = 1;
|
|
8002350: 703b strb r3, [r7, #0]
|
|
sw2_long_handled = 0;
|
|
8002352: 7013 strb r3, [r2, #0]
|
|
8002354: e65b b.n 800200e <main+0x586>
|
|
target_count = total_count + 10000;
|
|
8002356: 4b2a ldr r3, [pc, #168] @ (8002400 <main+0x978>)
|
|
8002358: 492a ldr r1, [pc, #168] @ (8002404 <main+0x97c>)
|
|
800235a: 681b ldr r3, [r3, #0]
|
|
800235c: 4a2a ldr r2, [pc, #168] @ (8002408 <main+0x980>)
|
|
800235e: 185b adds r3, r3, r1
|
|
8002360: 6013 str r3, [r2, #0]
|
|
}
|
|
8002362: e7f3 b.n 800234c <main+0x8c4>
|
|
8002364: 491c ldr r1, [pc, #112] @ (80023d8 <main+0x950>)
|
|
else if (sw2_state && time2 <= 2000 && time2 > 100)
|
|
8002366: 3b65 subs r3, #101 @ 0x65
|
|
8002368: 4a22 ldr r2, [pc, #136] @ (80023f4 <main+0x96c>)
|
|
800236a: b29b uxth r3, r3
|
|
800236c: 4e27 ldr r6, [pc, #156] @ (800240c <main+0x984>)
|
|
800236e: 4d23 ldr r5, [pc, #140] @ (80023fc <main+0x974>)
|
|
8002370: 9101 str r1, [sp, #4]
|
|
8002372: 4293 cmp r3, r2
|
|
8002374: d80e bhi.n 8002394 <main+0x90c>
|
|
set_LED(1, 1, 1);
|
|
8002376: 2201 movs r2, #1
|
|
8002378: 0011 movs r1, r2
|
|
800237a: 0010 movs r0, r2
|
|
800237c: f7fe fb8e bl 8000a9c <set_LED>
|
|
start_feed(20, 1);
|
|
8002380: 2101 movs r1, #1
|
|
8002382: 2014 movs r0, #20
|
|
8002384: f7fe fc8c bl 8000ca0 <start_feed>
|
|
HAL_TIM_Base_Stop(&htim17);
|
|
8002388: 9801 ldr r0, [sp, #4]
|
|
800238a: f001 fbd1 bl 8003b30 <HAL_TIM_Base_Stop>
|
|
sw2_pressed = 0;
|
|
800238e: 7034 strb r4, [r6, #0]
|
|
sw2_long_handled = 0;
|
|
8002390: 702c strb r4, [r5, #0]
|
|
8002392: e63c b.n 800200e <main+0x586>
|
|
HAL_TIM_Base_Stop(&htim17);
|
|
8002394: 9801 ldr r0, [sp, #4]
|
|
8002396: f001 fbcb bl 8003b30 <HAL_TIM_Base_Stop>
|
|
sw2_pressed = 0;
|
|
800239a: 7034 strb r4, [r6, #0]
|
|
sw2_long_handled = 0;
|
|
800239c: 702c strb r4, [r5, #0]
|
|
if (!driving) set_LED(0, 0, 0);
|
|
800239e: e7b1 b.n 8002304 <main+0x87c>
|
|
else if (sw1_state && sw2_state)
|
|
80023a0: 2e00 cmp r6, #0
|
|
80023a2: d100 bne.n 80023a6 <main+0x91e>
|
|
80023a4: e633 b.n 800200e <main+0x586>
|
|
80023a6: 2800 cmp r0, #0
|
|
80023a8: d100 bne.n 80023ac <main+0x924>
|
|
80023aa: e630 b.n 800200e <main+0x586>
|
|
HAL_TIM_Base_Stop(&htim16);
|
|
80023ac: 4809 ldr r0, [pc, #36] @ (80023d4 <main+0x94c>)
|
|
80023ae: f001 fbbf bl 8003b30 <HAL_TIM_Base_Stop>
|
|
HAL_TIM_Base_Stop(&htim17);
|
|
80023b2: 4809 ldr r0, [pc, #36] @ (80023d8 <main+0x950>)
|
|
80023b4: f001 fbbc bl 8003b30 <HAL_TIM_Base_Stop>
|
|
sw1_pressed = 0;
|
|
80023b8: 2300 movs r3, #0
|
|
80023ba: 9a01 ldr r2, [sp, #4]
|
|
80023bc: 7013 strb r3, [r2, #0]
|
|
sw2_pressed = 0;
|
|
80023be: 4a13 ldr r2, [pc, #76] @ (800240c <main+0x984>)
|
|
80023c0: 7013 strb r3, [r2, #0]
|
|
sw1_long_handled = 0;
|
|
80023c2: 4a08 ldr r2, [pc, #32] @ (80023e4 <main+0x95c>)
|
|
80023c4: 7013 strb r3, [r2, #0]
|
|
sw2_long_handled = 0;
|
|
80023c6: 4a0d ldr r2, [pc, #52] @ (80023fc <main+0x974>)
|
|
80023c8: e7c3 b.n 8002352 <main+0x8ca>
|
|
set_LED(1, 0, 0); // Error - LED red
|
|
80023ca: 000a movs r2, r1
|
|
80023cc: 2001 movs r0, #1
|
|
80023ce: f7fe fb65 bl 8000a9c <set_LED>
|
|
80023d2: e633 b.n 800203c <main+0x5b4>
|
|
80023d4: 200011d0 .word 0x200011d0
|
|
80023d8: 20001184 .word 0x20001184
|
|
80023dc: 200000f0 .word 0x200000f0
|
|
80023e0: 200000f9 .word 0x200000f9
|
|
80023e4: 200000f6 .word 0x200000f6
|
|
80023e8: 20000102 .word 0x20000102
|
|
80023ec: fffff6a0 .word 0xfffff6a0
|
|
80023f0: 200000f7 .word 0x200000f7
|
|
80023f4: 0000076b .word 0x0000076b
|
|
80023f8: 20000fa1 .word 0x20000fa1
|
|
80023fc: 200000f5 .word 0x200000f5
|
|
8002400: 20000158 .word 0x20000158
|
|
8002404: 00002710 .word 0x00002710
|
|
8002408: 20000154 .word 0x20000154
|
|
800240c: 20000fa0 .word 0x20000fa0
|
|
|
|
08002410 <Error_Handler>:
|
|
__ASM volatile ("cpsid i" : : : "memory");
|
|
8002410: b672 cpsid i
|
|
while (1)
|
|
8002412: e7fe b.n 8002412 <Error_Handler+0x2>
|
|
|
|
08002414 <HAL_MspInit>:
|
|
|
|
/* USER CODE BEGIN MspInit 0 */
|
|
|
|
/* USER CODE END MspInit 0 */
|
|
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8002414: 2101 movs r1, #1
|
|
8002416: 4b0a ldr r3, [pc, #40] @ (8002440 <HAL_MspInit+0x2c>)
|
|
{
|
|
8002418: b082 sub sp, #8
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
800241a: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
800241c: 430a orrs r2, r1
|
|
800241e: 641a str r2, [r3, #64] @ 0x40
|
|
8002420: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
8002422: 400a ands r2, r1
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8002424: 2180 movs r1, #128 @ 0x80
|
|
__HAL_RCC_SYSCFG_CLK_ENABLE();
|
|
8002426: 9200 str r2, [sp, #0]
|
|
8002428: 9a00 ldr r2, [sp, #0]
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800242a: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
800242c: 0549 lsls r1, r1, #21
|
|
800242e: 430a orrs r2, r1
|
|
8002430: 63da str r2, [r3, #60] @ 0x3c
|
|
8002432: 6bdb ldr r3, [r3, #60] @ 0x3c
|
|
8002434: 400b ands r3, r1
|
|
8002436: 9301 str r3, [sp, #4]
|
|
8002438: 9b01 ldr r3, [sp, #4]
|
|
/* System interrupt init*/
|
|
|
|
/* USER CODE BEGIN MspInit 1 */
|
|
|
|
/* USER CODE END MspInit 1 */
|
|
}
|
|
800243a: b002 add sp, #8
|
|
800243c: 4770 bx lr
|
|
800243e: 46c0 nop @ (mov r8, r8)
|
|
8002440: 40021000 .word 0x40021000
|
|
|
|
08002444 <HAL_ADC_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param hadc: ADC handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
|
|
{
|
|
8002444: b530 push {r4, r5, lr}
|
|
8002446: 0004 movs r4, r0
|
|
8002448: b091 sub sp, #68 @ 0x44
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800244a: 2214 movs r2, #20
|
|
800244c: 2100 movs r1, #0
|
|
800244e: a804 add r0, sp, #16
|
|
8002450: f002 ff16 bl 8005280 <memset>
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
8002454: 221c movs r2, #28
|
|
8002456: 2100 movs r1, #0
|
|
8002458: a809 add r0, sp, #36 @ 0x24
|
|
800245a: f002 ff11 bl 8005280 <memset>
|
|
if(hadc->Instance==ADC1)
|
|
800245e: 4b1e ldr r3, [pc, #120] @ (80024d8 <HAL_ADC_MspInit+0x94>)
|
|
8002460: 6822 ldr r2, [r4, #0]
|
|
8002462: 429a cmp r2, r3
|
|
8002464: d136 bne.n 80024d4 <HAL_ADC_MspInit+0x90>
|
|
|
|
/* USER CODE END ADC1_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clocks
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
|
|
8002466: 2320 movs r3, #32
|
|
PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002468: a809 add r0, sp, #36 @ 0x24
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
|
|
800246a: 9309 str r3, [sp, #36] @ 0x24
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
800246c: f001 f9c6 bl 80037fc <HAL_RCCEx_PeriphCLKConfig>
|
|
8002470: 2800 cmp r0, #0
|
|
8002472: d001 beq.n 8002478 <HAL_ADC_MspInit+0x34>
|
|
{
|
|
Error_Handler();
|
|
8002474: f7ff ffcc bl 8002410 <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_ADC_CLK_ENABLE();
|
|
8002478: 2180 movs r1, #128 @ 0x80
|
|
800247a: 4b18 ldr r3, [pc, #96] @ (80024dc <HAL_ADC_MspInit+0x98>)
|
|
800247c: 0349 lsls r1, r1, #13
|
|
800247e: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
PB12 ------> ADC1_IN22
|
|
*/
|
|
GPIO_InitStruct.Pin = IPROP_PEEL_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
|
|
8002480: 20a0 movs r0, #160 @ 0xa0
|
|
__HAL_RCC_ADC_CLK_ENABLE();
|
|
8002482: 430a orrs r2, r1
|
|
8002484: 641a str r2, [r3, #64] @ 0x40
|
|
8002486: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
8002488: 2503 movs r5, #3
|
|
__HAL_RCC_ADC_CLK_ENABLE();
|
|
800248a: 400a ands r2, r1
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800248c: 2101 movs r1, #1
|
|
__HAL_RCC_ADC_CLK_ENABLE();
|
|
800248e: 9201 str r2, [sp, #4]
|
|
8002490: 9a01 ldr r2, [sp, #4]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8002492: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002494: 2400 movs r4, #0
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8002496: 430a orrs r2, r1
|
|
8002498: 635a str r2, [r3, #52] @ 0x34
|
|
800249a: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
|
|
800249c: 05c0 lsls r0, r0, #23
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800249e: 400a ands r2, r1
|
|
80024a0: 9202 str r2, [sp, #8]
|
|
80024a2: 9a02 ldr r2, [sp, #8]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80024a4: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
80024a6: 1849 adds r1, r1, r1
|
|
80024a8: 430a orrs r2, r1
|
|
80024aa: 635a str r2, [r3, #52] @ 0x34
|
|
80024ac: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
80024ae: 9505 str r5, [sp, #20]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80024b0: 400b ands r3, r1
|
|
80024b2: 9303 str r3, [sp, #12]
|
|
80024b4: 9b03 ldr r3, [sp, #12]
|
|
GPIO_InitStruct.Pin = IPROP_PEEL_Pin;
|
|
80024b6: 2380 movs r3, #128 @ 0x80
|
|
HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
|
|
80024b8: a904 add r1, sp, #16
|
|
GPIO_InitStruct.Pin = IPROP_PEEL_Pin;
|
|
80024ba: 9304 str r3, [sp, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80024bc: 9406 str r4, [sp, #24]
|
|
HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
|
|
80024be: f000 fe83 bl 80031c8 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = IPROP_DRIVE_Pin;
|
|
80024c2: 2380 movs r3, #128 @ 0x80
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
HAL_GPIO_Init(IPROP_DRIVE_GPIO_Port, &GPIO_InitStruct);
|
|
80024c4: 4806 ldr r0, [pc, #24] @ (80024e0 <HAL_ADC_MspInit+0x9c>)
|
|
GPIO_InitStruct.Pin = IPROP_DRIVE_Pin;
|
|
80024c6: 015b lsls r3, r3, #5
|
|
HAL_GPIO_Init(IPROP_DRIVE_GPIO_Port, &GPIO_InitStruct);
|
|
80024c8: a904 add r1, sp, #16
|
|
GPIO_InitStruct.Pin = IPROP_DRIVE_Pin;
|
|
80024ca: 9304 str r3, [sp, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
|
|
80024cc: 9505 str r5, [sp, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80024ce: 9406 str r4, [sp, #24]
|
|
HAL_GPIO_Init(IPROP_DRIVE_GPIO_Port, &GPIO_InitStruct);
|
|
80024d0: f000 fe7a bl 80031c8 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END ADC1_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80024d4: b011 add sp, #68 @ 0x44
|
|
80024d6: bd30 pop {r4, r5, pc}
|
|
80024d8: 40012400 .word 0x40012400
|
|
80024dc: 40021000 .word 0x40021000
|
|
80024e0: 50000400 .word 0x50000400
|
|
|
|
080024e4 <HAL_TIM_Base_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_base: TIM_Base handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
|
|
{
|
|
80024e4: b51f push {r0, r1, r2, r3, r4, lr}
|
|
if(htim_base->Instance==TIM1)
|
|
80024e6: 6803 ldr r3, [r0, #0]
|
|
80024e8: 4a26 ldr r2, [pc, #152] @ (8002584 <HAL_TIM_Base_MspInit+0xa0>)
|
|
80024ea: 4293 cmp r3, r2
|
|
80024ec: d10b bne.n 8002506 <HAL_TIM_Base_MspInit+0x22>
|
|
{
|
|
/* USER CODE BEGIN TIM1_MspInit 0 */
|
|
|
|
/* USER CODE END TIM1_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM1_CLK_ENABLE();
|
|
80024ee: 2180 movs r1, #128 @ 0x80
|
|
80024f0: 4b25 ldr r3, [pc, #148] @ (8002588 <HAL_TIM_Base_MspInit+0xa4>)
|
|
80024f2: 0109 lsls r1, r1, #4
|
|
80024f4: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
80024f6: 430a orrs r2, r1
|
|
80024f8: 641a str r2, [r3, #64] @ 0x40
|
|
80024fa: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
80024fc: 400b ands r3, r1
|
|
80024fe: 9300 str r3, [sp, #0]
|
|
8002500: 9b00 ldr r3, [sp, #0]
|
|
/* USER CODE BEGIN TIM17_MspInit 1 */
|
|
|
|
/* USER CODE END TIM17_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
8002502: b005 add sp, #20
|
|
8002504: bd00 pop {pc}
|
|
else if(htim_base->Instance==TIM14)
|
|
8002506: 4a21 ldr r2, [pc, #132] @ (800258c <HAL_TIM_Base_MspInit+0xa8>)
|
|
8002508: 4293 cmp r3, r2
|
|
800250a: d112 bne.n 8002532 <HAL_TIM_Base_MspInit+0x4e>
|
|
__HAL_RCC_TIM14_CLK_ENABLE();
|
|
800250c: 2180 movs r1, #128 @ 0x80
|
|
800250e: 4b1e ldr r3, [pc, #120] @ (8002588 <HAL_TIM_Base_MspInit+0xa4>)
|
|
8002510: 0209 lsls r1, r1, #8
|
|
8002512: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
|
|
8002514: 2013 movs r0, #19
|
|
__HAL_RCC_TIM14_CLK_ENABLE();
|
|
8002516: 430a orrs r2, r1
|
|
8002518: 641a str r2, [r3, #64] @ 0x40
|
|
HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
|
|
800251a: 2200 movs r2, #0
|
|
__HAL_RCC_TIM14_CLK_ENABLE();
|
|
800251c: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800251e: 400b ands r3, r1
|
|
8002520: 9301 str r3, [sp, #4]
|
|
HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
|
|
8002522: 0011 movs r1, r2
|
|
__HAL_RCC_TIM14_CLK_ENABLE();
|
|
8002524: 9b01 ldr r3, [sp, #4]
|
|
HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
|
|
8002526: f000 fc55 bl 8002dd4 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(TIM14_IRQn);
|
|
800252a: 2013 movs r0, #19
|
|
HAL_NVIC_EnableIRQ(TIM17_IRQn);
|
|
800252c: f000 fc7c bl 8002e28 <HAL_NVIC_EnableIRQ>
|
|
}
|
|
8002530: e7e7 b.n 8002502 <HAL_TIM_Base_MspInit+0x1e>
|
|
else if(htim_base->Instance==TIM16)
|
|
8002532: 4a17 ldr r2, [pc, #92] @ (8002590 <HAL_TIM_Base_MspInit+0xac>)
|
|
8002534: 4293 cmp r3, r2
|
|
8002536: d110 bne.n 800255a <HAL_TIM_Base_MspInit+0x76>
|
|
__HAL_RCC_TIM16_CLK_ENABLE();
|
|
8002538: 2180 movs r1, #128 @ 0x80
|
|
800253a: 4b13 ldr r3, [pc, #76] @ (8002588 <HAL_TIM_Base_MspInit+0xa4>)
|
|
800253c: 0289 lsls r1, r1, #10
|
|
800253e: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
|
|
8002540: 2015 movs r0, #21
|
|
__HAL_RCC_TIM16_CLK_ENABLE();
|
|
8002542: 430a orrs r2, r1
|
|
8002544: 641a str r2, [r3, #64] @ 0x40
|
|
HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
|
|
8002546: 2200 movs r2, #0
|
|
__HAL_RCC_TIM16_CLK_ENABLE();
|
|
8002548: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
800254a: 400b ands r3, r1
|
|
800254c: 9302 str r3, [sp, #8]
|
|
HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
|
|
800254e: 0011 movs r1, r2
|
|
__HAL_RCC_TIM16_CLK_ENABLE();
|
|
8002550: 9b02 ldr r3, [sp, #8]
|
|
HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
|
|
8002552: f000 fc3f bl 8002dd4 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(TIM16_IRQn);
|
|
8002556: 2015 movs r0, #21
|
|
8002558: e7e8 b.n 800252c <HAL_TIM_Base_MspInit+0x48>
|
|
else if(htim_base->Instance==TIM17)
|
|
800255a: 4a0e ldr r2, [pc, #56] @ (8002594 <HAL_TIM_Base_MspInit+0xb0>)
|
|
800255c: 4293 cmp r3, r2
|
|
800255e: d1d0 bne.n 8002502 <HAL_TIM_Base_MspInit+0x1e>
|
|
__HAL_RCC_TIM17_CLK_ENABLE();
|
|
8002560: 2180 movs r1, #128 @ 0x80
|
|
8002562: 4b09 ldr r3, [pc, #36] @ (8002588 <HAL_TIM_Base_MspInit+0xa4>)
|
|
8002564: 02c9 lsls r1, r1, #11
|
|
8002566: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
|
|
8002568: 2016 movs r0, #22
|
|
__HAL_RCC_TIM17_CLK_ENABLE();
|
|
800256a: 430a orrs r2, r1
|
|
800256c: 641a str r2, [r3, #64] @ 0x40
|
|
HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
|
|
800256e: 2200 movs r2, #0
|
|
__HAL_RCC_TIM17_CLK_ENABLE();
|
|
8002570: 6c1b ldr r3, [r3, #64] @ 0x40
|
|
8002572: 400b ands r3, r1
|
|
8002574: 9303 str r3, [sp, #12]
|
|
HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
|
|
8002576: 0011 movs r1, r2
|
|
__HAL_RCC_TIM17_CLK_ENABLE();
|
|
8002578: 9b03 ldr r3, [sp, #12]
|
|
HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
|
|
800257a: f000 fc2b bl 8002dd4 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(TIM17_IRQn);
|
|
800257e: 2016 movs r0, #22
|
|
8002580: e7d4 b.n 800252c <HAL_TIM_Base_MspInit+0x48>
|
|
8002582: 46c0 nop @ (mov r8, r8)
|
|
8002584: 40012c00 .word 0x40012c00
|
|
8002588: 40021000 .word 0x40021000
|
|
800258c: 40002000 .word 0x40002000
|
|
8002590: 40014400 .word 0x40014400
|
|
8002594: 40014800 .word 0x40014800
|
|
|
|
08002598 <HAL_TIM_Encoder_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param htim_encoder: TIM_Encoder handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
|
|
{
|
|
8002598: b510 push {r4, lr}
|
|
800259a: 0004 movs r4, r0
|
|
800259c: b088 sub sp, #32
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
800259e: 2214 movs r2, #20
|
|
80025a0: 2100 movs r1, #0
|
|
80025a2: a803 add r0, sp, #12
|
|
80025a4: f002 fe6c bl 8005280 <memset>
|
|
if(htim_encoder->Instance==TIM3)
|
|
80025a8: 4b0f ldr r3, [pc, #60] @ (80025e8 <HAL_TIM_Encoder_MspInit+0x50>)
|
|
80025aa: 6822 ldr r2, [r4, #0]
|
|
80025ac: 429a cmp r2, r3
|
|
80025ae: d119 bne.n 80025e4 <HAL_TIM_Encoder_MspInit+0x4c>
|
|
{
|
|
/* USER CODE BEGIN TIM3_MspInit 0 */
|
|
|
|
/* USER CODE END TIM3_MspInit 0 */
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
80025b0: 2202 movs r2, #2
|
|
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
80025b2: 2004 movs r0, #4
|
|
__HAL_RCC_TIM3_CLK_ENABLE();
|
|
80025b4: 4b0d ldr r3, [pc, #52] @ (80025ec <HAL_TIM_Encoder_MspInit+0x54>)
|
|
80025b6: 6bd9 ldr r1, [r3, #60] @ 0x3c
|
|
80025b8: 4311 orrs r1, r2
|
|
80025ba: 63d9 str r1, [r3, #60] @ 0x3c
|
|
80025bc: 6bd9 ldr r1, [r3, #60] @ 0x3c
|
|
80025be: 4011 ands r1, r2
|
|
80025c0: 9101 str r1, [sp, #4]
|
|
80025c2: 9901 ldr r1, [sp, #4]
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
80025c4: 6b59 ldr r1, [r3, #52] @ 0x34
|
|
80025c6: 4301 orrs r1, r0
|
|
80025c8: 6359 str r1, [r3, #52] @ 0x34
|
|
80025ca: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
GPIO_InitStruct.Pin = QUAD_A_Pin|QUAD_B_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80025cc: a903 add r1, sp, #12
|
|
__HAL_RCC_GPIOC_CLK_ENABLE();
|
|
80025ce: 4003 ands r3, r0
|
|
80025d0: 9302 str r3, [sp, #8]
|
|
80025d2: 9b02 ldr r3, [sp, #8]
|
|
GPIO_InitStruct.Pin = QUAD_A_Pin|QUAD_B_Pin;
|
|
80025d4: 23c0 movs r3, #192 @ 0xc0
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80025d6: 4806 ldr r0, [pc, #24] @ (80025f0 <HAL_TIM_Encoder_MspInit+0x58>)
|
|
GPIO_InitStruct.Pin = QUAD_A_Pin|QUAD_B_Pin;
|
|
80025d8: 9303 str r3, [sp, #12]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
|
|
80025da: 3bbf subs r3, #191 @ 0xbf
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80025dc: 9204 str r2, [sp, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
|
|
80025de: 9307 str r3, [sp, #28]
|
|
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
|
|
80025e0: f000 fdf2 bl 80031c8 <HAL_GPIO_Init>
|
|
|
|
/* USER CODE END TIM3_MspInit 1 */
|
|
|
|
}
|
|
|
|
}
|
|
80025e4: b008 add sp, #32
|
|
80025e6: bd10 pop {r4, pc}
|
|
80025e8: 40000400 .word 0x40000400
|
|
80025ec: 40021000 .word 0x40021000
|
|
80025f0: 50000800 .word 0x50000800
|
|
|
|
080025f4 <HAL_TIM_MspPostInit>:
|
|
|
|
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
|
|
{
|
|
80025f4: b510 push {r4, lr}
|
|
80025f6: 0004 movs r4, r0
|
|
80025f8: b086 sub sp, #24
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
80025fa: 2214 movs r2, #20
|
|
80025fc: 2100 movs r1, #0
|
|
80025fe: a801 add r0, sp, #4
|
|
8002600: f002 fe3e bl 8005280 <memset>
|
|
if(htim->Instance==TIM1)
|
|
8002604: 4b13 ldr r3, [pc, #76] @ (8002654 <HAL_TIM_MspPostInit+0x60>)
|
|
8002606: 6822 ldr r2, [r4, #0]
|
|
8002608: 429a cmp r2, r3
|
|
800260a: d120 bne.n 800264e <HAL_TIM_MspPostInit+0x5a>
|
|
{
|
|
/* USER CODE BEGIN TIM1_MspPostInit 0 */
|
|
|
|
/* USER CODE END TIM1_MspPostInit 0 */
|
|
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800260c: 2101 movs r1, #1
|
|
800260e: 4b12 ldr r3, [pc, #72] @ (8002658 <HAL_TIM_MspPostInit+0x64>)
|
|
GPIO_InitStruct.Pin = PEEL1_Pin|PEEL2_Pin;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_TIM1;
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8002610: 20a0 movs r0, #160 @ 0xa0
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8002612: 6b5a ldr r2, [r3, #52] @ 0x34
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002614: 2402 movs r4, #2
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
8002616: 430a orrs r2, r1
|
|
8002618: 635a str r2, [r3, #52] @ 0x34
|
|
800261a: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800261c: 05c0 lsls r0, r0, #23
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
800261e: 400b ands r3, r1
|
|
8002620: 9300 str r3, [sp, #0]
|
|
8002622: 9b00 ldr r3, [sp, #0]
|
|
GPIO_InitStruct.Pin = PEEL1_Pin|PEEL2_Pin;
|
|
8002624: 230c movs r3, #12
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8002626: a901 add r1, sp, #4
|
|
GPIO_InitStruct.Pin = PEEL1_Pin|PEEL2_Pin;
|
|
8002628: 9301 str r3, [sp, #4]
|
|
GPIO_InitStruct.Alternate = GPIO_AF5_TIM1;
|
|
800262a: 3b07 subs r3, #7
|
|
800262c: 9305 str r3, [sp, #20]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
800262e: 9402 str r4, [sp, #8]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8002630: f000 fdca bl 80031c8 <HAL_GPIO_Init>
|
|
|
|
GPIO_InitStruct.Pin = DRIVE1_Pin|DRIVE2_Pin;
|
|
8002634: 23c0 movs r3, #192 @ 0xc0
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
GPIO_InitStruct.Alternate = GPIO_AF2_TIM1;
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8002636: 20a0 movs r0, #160 @ 0xa0
|
|
GPIO_InitStruct.Pin = DRIVE1_Pin|DRIVE2_Pin;
|
|
8002638: 009b lsls r3, r3, #2
|
|
800263a: 9301 str r3, [sp, #4]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
800263c: 2300 movs r3, #0
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800263e: a901 add r1, sp, #4
|
|
8002640: 05c0 lsls r0, r0, #23
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002642: 9402 str r4, [sp, #8]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
8002644: 9303 str r3, [sp, #12]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
8002646: 9304 str r3, [sp, #16]
|
|
GPIO_InitStruct.Alternate = GPIO_AF2_TIM1;
|
|
8002648: 9405 str r4, [sp, #20]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
800264a: f000 fdbd bl 80031c8 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN TIM1_MspPostInit 1 */
|
|
|
|
/* USER CODE END TIM1_MspPostInit 1 */
|
|
}
|
|
|
|
}
|
|
800264e: b006 add sp, #24
|
|
8002650: bd10 pop {r4, pc}
|
|
8002652: 46c0 nop @ (mov r8, r8)
|
|
8002654: 40012c00 .word 0x40012c00
|
|
8002658: 40021000 .word 0x40021000
|
|
|
|
0800265c <HAL_UART_MspInit>:
|
|
* This function configures the hardware resources used in this example
|
|
* @param huart: UART handle pointer
|
|
* @retval None
|
|
*/
|
|
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
|
|
{
|
|
800265c: b530 push {r4, r5, lr}
|
|
800265e: 0005 movs r5, r0
|
|
8002660: b091 sub sp, #68 @ 0x44
|
|
GPIO_InitTypeDef GPIO_InitStruct = {0};
|
|
8002662: 2214 movs r2, #20
|
|
8002664: 2100 movs r1, #0
|
|
8002666: a804 add r0, sp, #16
|
|
8002668: f002 fe0a bl 8005280 <memset>
|
|
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
|
|
800266c: 221c movs r2, #28
|
|
800266e: 2100 movs r1, #0
|
|
8002670: a809 add r0, sp, #36 @ 0x24
|
|
8002672: f002 fe05 bl 8005280 <memset>
|
|
if(huart->Instance==USART1)
|
|
8002676: 682b ldr r3, [r5, #0]
|
|
8002678: 4a43 ldr r2, [pc, #268] @ (8002788 <HAL_UART_MspInit+0x12c>)
|
|
800267a: 4293 cmp r3, r2
|
|
800267c: d127 bne.n 80026ce <HAL_UART_MspInit+0x72>
|
|
|
|
/* USER CODE END USART1_MspInit 0 */
|
|
|
|
/** Initializes the peripherals clocks
|
|
*/
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
|
800267e: 2301 movs r3, #1
|
|
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1;
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002680: a809 add r0, sp, #36 @ 0x24
|
|
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
|
|
8002682: 9309 str r3, [sp, #36] @ 0x24
|
|
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
|
|
8002684: f001 f8ba bl 80037fc <HAL_RCCEx_PeriphCLKConfig>
|
|
8002688: 2800 cmp r0, #0
|
|
800268a: d001 beq.n 8002690 <HAL_UART_MspInit+0x34>
|
|
{
|
|
Error_Handler();
|
|
800268c: f7ff fec0 bl 8002410 <Error_Handler>
|
|
}
|
|
|
|
/* Peripheral clock enable */
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
8002690: 2180 movs r1, #128 @ 0x80
|
|
8002692: 4b3e ldr r3, [pc, #248] @ (800278c <HAL_UART_MspInit+0x130>)
|
|
8002694: 01c9 lsls r1, r1, #7
|
|
8002696: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
GPIO_InitStruct.Alternate = GPIO_AF0_USART1;
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
8002698: 483d ldr r0, [pc, #244] @ (8002790 <HAL_UART_MspInit+0x134>)
|
|
__HAL_RCC_USART1_CLK_ENABLE();
|
|
800269a: 430a orrs r2, r1
|
|
800269c: 641a str r2, [r3, #64] @ 0x40
|
|
800269e: 6c1a ldr r2, [r3, #64] @ 0x40
|
|
80026a0: 400a ands r2, r1
|
|
80026a2: 9200 str r2, [sp, #0]
|
|
80026a4: 9a00 ldr r2, [sp, #0]
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80026a6: 2202 movs r2, #2
|
|
80026a8: 6b59 ldr r1, [r3, #52] @ 0x34
|
|
80026aa: 4311 orrs r1, r2
|
|
80026ac: 6359 str r1, [r3, #52] @ 0x34
|
|
80026ae: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80026b0: a904 add r1, sp, #16
|
|
__HAL_RCC_GPIOB_CLK_ENABLE();
|
|
80026b2: 4013 ands r3, r2
|
|
80026b4: 9301 str r3, [sp, #4]
|
|
80026b6: 9b01 ldr r3, [sp, #4]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
|
|
80026b8: 23c0 movs r3, #192 @ 0xc0
|
|
80026ba: 9304 str r3, [sp, #16]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80026bc: 2300 movs r3, #0
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
80026be: 9205 str r2, [sp, #20]
|
|
GPIO_InitStruct.Pull = GPIO_NOPULL;
|
|
80026c0: 9306 str r3, [sp, #24]
|
|
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
|
|
80026c2: 9307 str r3, [sp, #28]
|
|
GPIO_InitStruct.Alternate = GPIO_AF0_USART1;
|
|
80026c4: 9308 str r3, [sp, #32]
|
|
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
|
|
80026c6: f000 fd7f bl 80031c8 <HAL_GPIO_Init>
|
|
/* USER CODE BEGIN USART2_MspInit 1 */
|
|
|
|
/* USER CODE END USART2_MspInit 1 */
|
|
}
|
|
|
|
}
|
|
80026ca: b011 add sp, #68 @ 0x44
|
|
80026cc: bd30 pop {r4, r5, pc}
|
|
else if(huart->Instance==USART2)
|
|
80026ce: 4a31 ldr r2, [pc, #196] @ (8002794 <HAL_UART_MspInit+0x138>)
|
|
80026d0: 4293 cmp r3, r2
|
|
80026d2: d1fa bne.n 80026ca <HAL_UART_MspInit+0x6e>
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
80026d4: 2180 movs r1, #128 @ 0x80
|
|
80026d6: 4b2d ldr r3, [pc, #180] @ (800278c <HAL_UART_MspInit+0x130>)
|
|
80026d8: 0289 lsls r1, r1, #10
|
|
80026da: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80026dc: 20a0 movs r0, #160 @ 0xa0
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
80026de: 430a orrs r2, r1
|
|
80026e0: 63da str r2, [r3, #60] @ 0x3c
|
|
80026e2: 6bda ldr r2, [r3, #60] @ 0x3c
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80026e4: 05c0 lsls r0, r0, #23
|
|
__HAL_RCC_USART2_CLK_ENABLE();
|
|
80026e6: 400a ands r2, r1
|
|
80026e8: 9202 str r2, [sp, #8]
|
|
80026ea: 9a02 ldr r2, [sp, #8]
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80026ec: 2201 movs r2, #1
|
|
80026ee: 6b59 ldr r1, [r3, #52] @ 0x34
|
|
80026f0: 4311 orrs r1, r2
|
|
80026f2: 6359 str r1, [r3, #52] @ 0x34
|
|
80026f4: 6b5b ldr r3, [r3, #52] @ 0x34
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
80026f6: a904 add r1, sp, #16
|
|
__HAL_RCC_GPIOA_CLK_ENABLE();
|
|
80026f8: 4013 ands r3, r2
|
|
80026fa: 9303 str r3, [sp, #12]
|
|
80026fc: 9b03 ldr r3, [sp, #12]
|
|
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
|
|
80026fe: 2332 movs r3, #50 @ 0x32
|
|
8002700: 9304 str r3, [sp, #16]
|
|
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
|
|
8002702: 3b30 subs r3, #48 @ 0x30
|
|
8002704: 9305 str r3, [sp, #20]
|
|
GPIO_InitStruct.Alternate = GPIO_AF1_USART2;
|
|
8002706: 9208 str r2, [sp, #32]
|
|
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
|
|
8002708: f000 fd5e bl 80031c8 <HAL_GPIO_Init>
|
|
hdma_usart2_rx.Instance = DMA1_Channel2;
|
|
800270c: 4c22 ldr r4, [pc, #136] @ (8002798 <HAL_UART_MspInit+0x13c>)
|
|
800270e: 4b23 ldr r3, [pc, #140] @ (800279c <HAL_UART_MspInit+0x140>)
|
|
hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8002710: 2280 movs r2, #128 @ 0x80
|
|
hdma_usart2_rx.Instance = DMA1_Channel2;
|
|
8002712: 6023 str r3, [r4, #0]
|
|
hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX;
|
|
8002714: 2334 movs r3, #52 @ 0x34
|
|
8002716: 6063 str r3, [r4, #4]
|
|
hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
|
|
8002718: 2300 movs r3, #0
|
|
800271a: 60a3 str r3, [r4, #8]
|
|
hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
800271c: 60e3 str r3, [r4, #12]
|
|
hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
800271e: 6163 str r3, [r4, #20]
|
|
hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
8002720: 61a3 str r3, [r4, #24]
|
|
hdma_usart2_rx.Init.Mode = DMA_NORMAL;
|
|
8002722: 61e3 str r3, [r4, #28]
|
|
hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
|
|
8002724: 2380 movs r3, #128 @ 0x80
|
|
if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
|
|
8002726: 0020 movs r0, r4
|
|
hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
|
|
8002728: 015b lsls r3, r3, #5
|
|
hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
|
|
800272a: 6122 str r2, [r4, #16]
|
|
hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
|
|
800272c: 6223 str r3, [r4, #32]
|
|
if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
|
|
800272e: f000 fbdb bl 8002ee8 <HAL_DMA_Init>
|
|
8002732: 2800 cmp r0, #0
|
|
8002734: d001 beq.n 800273a <HAL_UART_MspInit+0xde>
|
|
Error_Handler();
|
|
8002736: f7ff fe6b bl 8002410 <Error_Handler>
|
|
__HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx);
|
|
800273a: 1d2b adds r3, r5, #4
|
|
800273c: 67dc str r4, [r3, #124] @ 0x7c
|
|
800273e: 62a5 str r5, [r4, #40] @ 0x28
|
|
hdma_usart2_tx.Instance = DMA1_Channel1;
|
|
8002740: 4b17 ldr r3, [pc, #92] @ (80027a0 <HAL_UART_MspInit+0x144>)
|
|
8002742: 4c18 ldr r4, [pc, #96] @ (80027a4 <HAL_UART_MspInit+0x148>)
|
|
hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8002744: 2280 movs r2, #128 @ 0x80
|
|
hdma_usart2_tx.Instance = DMA1_Channel1;
|
|
8002746: 6023 str r3, [r4, #0]
|
|
hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX;
|
|
8002748: 2335 movs r3, #53 @ 0x35
|
|
800274a: 6063 str r3, [r4, #4]
|
|
hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
|
|
800274c: 3b25 subs r3, #37 @ 0x25
|
|
800274e: 60a3 str r3, [r4, #8]
|
|
hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
|
|
8002750: 2300 movs r3, #0
|
|
8002752: 60e3 str r3, [r4, #12]
|
|
hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
|
|
8002754: 6163 str r3, [r4, #20]
|
|
hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
|
|
8002756: 61a3 str r3, [r4, #24]
|
|
hdma_usart2_tx.Init.Mode = DMA_NORMAL;
|
|
8002758: 61e3 str r3, [r4, #28]
|
|
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH;
|
|
800275a: 2380 movs r3, #128 @ 0x80
|
|
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
|
|
800275c: 0020 movs r0, r4
|
|
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH;
|
|
800275e: 019b lsls r3, r3, #6
|
|
hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
|
|
8002760: 6122 str r2, [r4, #16]
|
|
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH;
|
|
8002762: 6223 str r3, [r4, #32]
|
|
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
|
|
8002764: f000 fbc0 bl 8002ee8 <HAL_DMA_Init>
|
|
8002768: 2800 cmp r0, #0
|
|
800276a: d001 beq.n 8002770 <HAL_UART_MspInit+0x114>
|
|
Error_Handler();
|
|
800276c: f7ff fe50 bl 8002410 <Error_Handler>
|
|
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
|
|
8002770: 2200 movs r2, #0
|
|
8002772: 201c movs r0, #28
|
|
8002774: 0011 movs r1, r2
|
|
__HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx);
|
|
8002776: 67ec str r4, [r5, #124] @ 0x7c
|
|
8002778: 62a5 str r5, [r4, #40] @ 0x28
|
|
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
|
|
800277a: f000 fb2b bl 8002dd4 <HAL_NVIC_SetPriority>
|
|
HAL_NVIC_EnableIRQ(USART2_IRQn);
|
|
800277e: 201c movs r0, #28
|
|
8002780: f000 fb52 bl 8002e28 <HAL_NVIC_EnableIRQ>
|
|
}
|
|
8002784: e7a1 b.n 80026ca <HAL_UART_MspInit+0x6e>
|
|
8002786: 46c0 nop @ (mov r8, r8)
|
|
8002788: 40013800 .word 0x40013800
|
|
800278c: 40021000 .word 0x40021000
|
|
8002790: 50000400 .word 0x50000400
|
|
8002794: 40004400 .word 0x40004400
|
|
8002798: 20001000 .word 0x20001000
|
|
800279c: 4002001c .word 0x4002001c
|
|
80027a0: 40020008 .word 0x40020008
|
|
80027a4: 20000fa4 .word 0x20000fa4
|
|
|
|
080027a8 <NMI_Handler>:
|
|
{
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
|
|
|
|
/* USER CODE END NonMaskableInt_IRQn 0 */
|
|
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
|
|
while (1)
|
|
80027a8: e7fe b.n 80027a8 <NMI_Handler>
|
|
|
|
080027aa <HardFault_Handler>:
|
|
void HardFault_Handler(void)
|
|
{
|
|
/* USER CODE BEGIN HardFault_IRQn 0 */
|
|
|
|
/* USER CODE END HardFault_IRQn 0 */
|
|
while (1)
|
|
80027aa: e7fe b.n 80027aa <HardFault_Handler>
|
|
|
|
080027ac <SVC_Handler>:
|
|
|
|
/* USER CODE END SVCall_IRQn 0 */
|
|
/* USER CODE BEGIN SVCall_IRQn 1 */
|
|
|
|
/* USER CODE END SVCall_IRQn 1 */
|
|
}
|
|
80027ac: 4770 bx lr
|
|
|
|
080027ae <PendSV_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles Pendable request for system service.
|
|
*/
|
|
void PendSV_Handler(void)
|
|
80027ae: 4770 bx lr
|
|
|
|
080027b0 <SysTick_Handler>:
|
|
|
|
/**
|
|
* @brief This function handles System tick timer.
|
|
*/
|
|
void SysTick_Handler(void)
|
|
{
|
|
80027b0: b510 push {r4, lr}
|
|
/* USER CODE BEGIN SysTick_IRQn 0 */
|
|
|
|
/* USER CODE END SysTick_IRQn 0 */
|
|
HAL_IncTick();
|
|
80027b2: f000 f8a1 bl 80028f8 <HAL_IncTick>
|
|
/* USER CODE BEGIN SysTick_IRQn 1 */
|
|
|
|
/* USER CODE END SysTick_IRQn 1 */
|
|
}
|
|
80027b6: bd10 pop {r4, pc}
|
|
|
|
080027b8 <EXTI4_15_IRQHandler>:
|
|
void EXTI4_15_IRQHandler(void)
|
|
{
|
|
/* USER CODE BEGIN EXTI4_15_IRQn 0 */
|
|
|
|
/* USER CODE END EXTI4_15_IRQn 0 */
|
|
HAL_GPIO_EXTI_IRQHandler(SW2_Pin);
|
|
80027b8: 2080 movs r0, #128 @ 0x80
|
|
{
|
|
80027ba: b510 push {r4, lr}
|
|
HAL_GPIO_EXTI_IRQHandler(SW2_Pin);
|
|
80027bc: 0040 lsls r0, r0, #1
|
|
80027be: f000 fdcb bl 8003358 <HAL_GPIO_EXTI_IRQHandler>
|
|
HAL_GPIO_EXTI_IRQHandler(SW1_Pin);
|
|
80027c2: 2080 movs r0, #128 @ 0x80
|
|
80027c4: 0080 lsls r0, r0, #2
|
|
80027c6: f000 fdc7 bl 8003358 <HAL_GPIO_EXTI_IRQHandler>
|
|
/* USER CODE BEGIN EXTI4_15_IRQn 1 */
|
|
|
|
/* USER CODE END EXTI4_15_IRQn 1 */
|
|
}
|
|
80027ca: bd10 pop {r4, pc}
|
|
|
|
080027cc <DMA1_Channel1_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 channel 1 interrupt.
|
|
*/
|
|
void DMA1_Channel1_IRQHandler(void)
|
|
{
|
|
80027cc: b510 push {r4, lr}
|
|
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Channel1_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_usart2_tx);
|
|
80027ce: 4802 ldr r0, [pc, #8] @ (80027d8 <DMA1_Channel1_IRQHandler+0xc>)
|
|
80027d0: f000 fca4 bl 800311c <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Channel1_IRQn 1 */
|
|
}
|
|
80027d4: bd10 pop {r4, pc}
|
|
80027d6: 46c0 nop @ (mov r8, r8)
|
|
80027d8: 20000fa4 .word 0x20000fa4
|
|
|
|
080027dc <DMA1_Channel2_3_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles DMA1 channel 2 and channel 3 interrupts.
|
|
*/
|
|
void DMA1_Channel2_3_IRQHandler(void)
|
|
{
|
|
80027dc: b510 push {r4, lr}
|
|
/* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */
|
|
|
|
/* USER CODE END DMA1_Channel2_3_IRQn 0 */
|
|
HAL_DMA_IRQHandler(&hdma_usart2_rx);
|
|
80027de: 4802 ldr r0, [pc, #8] @ (80027e8 <DMA1_Channel2_3_IRQHandler+0xc>)
|
|
80027e0: f000 fc9c bl 800311c <HAL_DMA_IRQHandler>
|
|
/* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */
|
|
|
|
/* USER CODE END DMA1_Channel2_3_IRQn 1 */
|
|
}
|
|
80027e4: bd10 pop {r4, pc}
|
|
80027e6: 46c0 nop @ (mov r8, r8)
|
|
80027e8: 20001000 .word 0x20001000
|
|
|
|
080027ec <TIM14_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles TIM14 global interrupt.
|
|
*/
|
|
void TIM14_IRQHandler(void)
|
|
{
|
|
80027ec: b510 push {r4, lr}
|
|
/* USER CODE BEGIN TIM14_IRQn 0 */
|
|
|
|
/* USER CODE END TIM14_IRQn 0 */
|
|
HAL_TIM_IRQHandler(&htim14);
|
|
80027ee: 4802 ldr r0, [pc, #8] @ (80027f8 <TIM14_IRQHandler+0xc>)
|
|
80027f0: f001 fa42 bl 8003c78 <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM14_IRQn 1 */
|
|
|
|
/* USER CODE END TIM14_IRQn 1 */
|
|
}
|
|
80027f4: bd10 pop {r4, pc}
|
|
80027f6: 46c0 nop @ (mov r8, r8)
|
|
80027f8: 2000121c .word 0x2000121c
|
|
|
|
080027fc <TIM16_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles TIM16 global interrupt.
|
|
*/
|
|
void TIM16_IRQHandler(void)
|
|
{
|
|
80027fc: b510 push {r4, lr}
|
|
/* USER CODE BEGIN TIM16_IRQn 0 */
|
|
|
|
/* USER CODE END TIM16_IRQn 0 */
|
|
HAL_TIM_IRQHandler(&htim16);
|
|
80027fe: 4802 ldr r0, [pc, #8] @ (8002808 <TIM16_IRQHandler+0xc>)
|
|
8002800: f001 fa3a bl 8003c78 <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM16_IRQn 1 */
|
|
|
|
/* USER CODE END TIM16_IRQn 1 */
|
|
}
|
|
8002804: bd10 pop {r4, pc}
|
|
8002806: 46c0 nop @ (mov r8, r8)
|
|
8002808: 200011d0 .word 0x200011d0
|
|
|
|
0800280c <TIM17_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles TIM17 global interrupt.
|
|
*/
|
|
void TIM17_IRQHandler(void)
|
|
{
|
|
800280c: b510 push {r4, lr}
|
|
/* USER CODE BEGIN TIM17_IRQn 0 */
|
|
|
|
/* USER CODE END TIM17_IRQn 0 */
|
|
HAL_TIM_IRQHandler(&htim17);
|
|
800280e: 4802 ldr r0, [pc, #8] @ (8002818 <TIM17_IRQHandler+0xc>)
|
|
8002810: f001 fa32 bl 8003c78 <HAL_TIM_IRQHandler>
|
|
/* USER CODE BEGIN TIM17_IRQn 1 */
|
|
|
|
/* USER CODE END TIM17_IRQn 1 */
|
|
}
|
|
8002814: bd10 pop {r4, pc}
|
|
8002816: 46c0 nop @ (mov r8, r8)
|
|
8002818: 20001184 .word 0x20001184
|
|
|
|
0800281c <USART2_IRQHandler>:
|
|
|
|
/**
|
|
* @brief This function handles USART2 interrupt.
|
|
*/
|
|
void USART2_IRQHandler(void)
|
|
{
|
|
800281c: b510 push {r4, lr}
|
|
/* USER CODE BEGIN USART2_IRQn 0 */
|
|
|
|
/* USER CODE END USART2_IRQn 0 */
|
|
HAL_UART_IRQHandler(&huart2);
|
|
800281e: 4802 ldr r0, [pc, #8] @ (8002828 <USART2_IRQHandler+0xc>)
|
|
8002820: f001 ff34 bl 800468c <HAL_UART_IRQHandler>
|
|
/* USER CODE BEGIN USART2_IRQn 1 */
|
|
|
|
/* USER CODE END USART2_IRQn 1 */
|
|
}
|
|
8002824: bd10 pop {r4, pc}
|
|
8002826: 46c0 nop @ (mov r8, r8)
|
|
8002828: 2000105c .word 0x2000105c
|
|
|
|
0800282c <SystemInit>:
|
|
|
|
/* Configure the Vector Table location add offset address ------------------*/
|
|
#ifdef VECT_TAB_SRAM
|
|
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
|
|
#else
|
|
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
|
|
800282c: 2280 movs r2, #128 @ 0x80
|
|
800282e: 4b02 ldr r3, [pc, #8] @ (8002838 <SystemInit+0xc>)
|
|
8002830: 0512 lsls r2, r2, #20
|
|
8002832: 609a str r2, [r3, #8]
|
|
#endif
|
|
}
|
|
8002834: 4770 bx lr
|
|
8002836: 46c0 nop @ (mov r8, r8)
|
|
8002838: e000ed00 .word 0xe000ed00
|
|
|
|
0800283c <Reset_Handler>:
|
|
|
|
.section .text.Reset_Handler
|
|
.weak Reset_Handler
|
|
.type Reset_Handler, %function
|
|
Reset_Handler:
|
|
ldr r0, =_estack
|
|
800283c: 480d ldr r0, [pc, #52] @ (8002874 <LoopForever+0x2>)
|
|
mov sp, r0 /* set stack pointer */
|
|
800283e: 4685 mov sp, r0
|
|
/* Call the clock system initialization function.*/
|
|
bl SystemInit
|
|
8002840: f7ff fff4 bl 800282c <SystemInit>
|
|
|
|
/* Copy the data segment initializers from flash to SRAM */
|
|
movs r1, #0
|
|
8002844: 2100 movs r1, #0
|
|
b LoopCopyDataInit
|
|
8002846: e003 b.n 8002850 <LoopCopyDataInit>
|
|
|
|
08002848 <CopyDataInit>:
|
|
|
|
CopyDataInit:
|
|
ldr r3, =_sidata
|
|
8002848: 4b0b ldr r3, [pc, #44] @ (8002878 <LoopForever+0x6>)
|
|
ldr r3, [r3, r1]
|
|
800284a: 585b ldr r3, [r3, r1]
|
|
str r3, [r0, r1]
|
|
800284c: 5043 str r3, [r0, r1]
|
|
adds r1, r1, #4
|
|
800284e: 3104 adds r1, #4
|
|
|
|
08002850 <LoopCopyDataInit>:
|
|
|
|
LoopCopyDataInit:
|
|
ldr r0, =_sdata
|
|
8002850: 480a ldr r0, [pc, #40] @ (800287c <LoopForever+0xa>)
|
|
ldr r3, =_edata
|
|
8002852: 4b0b ldr r3, [pc, #44] @ (8002880 <LoopForever+0xe>)
|
|
adds r2, r0, r1
|
|
8002854: 1842 adds r2, r0, r1
|
|
cmp r2, r3
|
|
8002856: 429a cmp r2, r3
|
|
bcc CopyDataInit
|
|
8002858: d3f6 bcc.n 8002848 <CopyDataInit>
|
|
ldr r2, =_sbss
|
|
800285a: 4a0a ldr r2, [pc, #40] @ (8002884 <LoopForever+0x12>)
|
|
b LoopFillZerobss
|
|
800285c: e002 b.n 8002864 <LoopFillZerobss>
|
|
|
|
0800285e <FillZerobss>:
|
|
/* Zero fill the bss segment. */
|
|
FillZerobss:
|
|
movs r3, #0
|
|
800285e: 2300 movs r3, #0
|
|
str r3, [r2]
|
|
8002860: 6013 str r3, [r2, #0]
|
|
adds r2, r2, #4
|
|
8002862: 3204 adds r2, #4
|
|
|
|
08002864 <LoopFillZerobss>:
|
|
|
|
|
|
LoopFillZerobss:
|
|
ldr r3, = _ebss
|
|
8002864: 4b08 ldr r3, [pc, #32] @ (8002888 <LoopForever+0x16>)
|
|
cmp r2, r3
|
|
8002866: 429a cmp r2, r3
|
|
bcc FillZerobss
|
|
8002868: d3f9 bcc.n 800285e <FillZerobss>
|
|
|
|
|
|
/* Call static constructors */
|
|
bl __libc_init_array
|
|
800286a: f002 fd11 bl 8005290 <__libc_init_array>
|
|
/* Call the application's entry point.*/
|
|
bl main
|
|
800286e: f7ff f90b bl 8001a88 <main>
|
|
|
|
08002872 <LoopForever>:
|
|
|
|
LoopForever:
|
|
b LoopForever
|
|
8002872: e7fe b.n 8002872 <LoopForever>
|
|
ldr r0, =_estack
|
|
8002874: 20003000 .word 0x20003000
|
|
ldr r3, =_sidata
|
|
8002878: 080053bc .word 0x080053bc
|
|
ldr r0, =_sdata
|
|
800287c: 20000000 .word 0x20000000
|
|
ldr r3, =_edata
|
|
8002880: 20000034 .word 0x20000034
|
|
ldr r2, =_sbss
|
|
8002884: 20000034 .word 0x20000034
|
|
ldr r3, = _ebss
|
|
8002888: 20001368 .word 0x20001368
|
|
|
|
0800288c <ADC1_IRQHandler>:
|
|
* @retval : None
|
|
*/
|
|
.section .text.Default_Handler,"ax",%progbits
|
|
Default_Handler:
|
|
Infinite_Loop:
|
|
b Infinite_Loop
|
|
800288c: e7fe b.n 800288c <ADC1_IRQHandler>
|
|
...
|
|
|
|
08002890 <HAL_InitTick>:
|
|
* implementation in user file.
|
|
* @param TickPriority Tick interrupt priority.
|
|
* @retval HAL status
|
|
*/
|
|
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
|
|
{
|
|
8002890: b570 push {r4, r5, r6, lr}
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
|
|
if ((uint32_t)uwTickFreq != 0UL)
|
|
8002892: 4b10 ldr r3, [pc, #64] @ (80028d4 <HAL_InitTick+0x44>)
|
|
{
|
|
8002894: 0005 movs r5, r0
|
|
if ((uint32_t)uwTickFreq != 0UL)
|
|
8002896: 7819 ldrb r1, [r3, #0]
|
|
8002898: 2900 cmp r1, #0
|
|
800289a: d101 bne.n 80028a0 <HAL_InitTick+0x10>
|
|
status = HAL_ERROR;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
status = HAL_ERROR;
|
|
800289c: 2001 movs r0, #1
|
|
status = HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return status;
|
|
}
|
|
800289e: bd70 pop {r4, r5, r6, pc}
|
|
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) == 0U)
|
|
80028a0: 20fa movs r0, #250 @ 0xfa
|
|
80028a2: 0080 lsls r0, r0, #2
|
|
80028a4: f7fd fc44 bl 8000130 <__udivsi3>
|
|
80028a8: 4c0b ldr r4, [pc, #44] @ (80028d8 <HAL_InitTick+0x48>)
|
|
80028aa: 0001 movs r1, r0
|
|
80028ac: 6820 ldr r0, [r4, #0]
|
|
80028ae: f7fd fc3f bl 8000130 <__udivsi3>
|
|
80028b2: f000 fac5 bl 8002e40 <HAL_SYSTICK_Config>
|
|
80028b6: 1e04 subs r4, r0, #0
|
|
80028b8: d1f0 bne.n 800289c <HAL_InitTick+0xc>
|
|
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
|
|
80028ba: 2d03 cmp r5, #3
|
|
80028bc: d8ee bhi.n 800289c <HAL_InitTick+0xc>
|
|
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
|
|
80028be: 0002 movs r2, r0
|
|
80028c0: 2001 movs r0, #1
|
|
80028c2: 0029 movs r1, r5
|
|
80028c4: 4240 negs r0, r0
|
|
80028c6: f000 fa85 bl 8002dd4 <HAL_NVIC_SetPriority>
|
|
uwTickPrio = TickPriority;
|
|
80028ca: 4b04 ldr r3, [pc, #16] @ (80028dc <HAL_InitTick+0x4c>)
|
|
80028cc: 0020 movs r0, r4
|
|
80028ce: 601d str r5, [r3, #0]
|
|
return status;
|
|
80028d0: e7e5 b.n 800289e <HAL_InitTick+0xe>
|
|
80028d2: 46c0 nop @ (mov r8, r8)
|
|
80028d4: 2000002c .word 0x2000002c
|
|
80028d8: 20000028 .word 0x20000028
|
|
80028dc: 20000030 .word 0x20000030
|
|
|
|
080028e0 <HAL_Init>:
|
|
{
|
|
80028e0: b510 push {r4, lr}
|
|
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
|
|
80028e2: 2003 movs r0, #3
|
|
80028e4: f7ff ffd4 bl 8002890 <HAL_InitTick>
|
|
80028e8: 1e04 subs r4, r0, #0
|
|
80028ea: d103 bne.n 80028f4 <HAL_Init+0x14>
|
|
HAL_MspInit();
|
|
80028ec: f7ff fd92 bl 8002414 <HAL_MspInit>
|
|
}
|
|
80028f0: 0020 movs r0, r4
|
|
80028f2: bd10 pop {r4, pc}
|
|
status = HAL_ERROR;
|
|
80028f4: 2401 movs r4, #1
|
|
80028f6: e7fb b.n 80028f0 <HAL_Init+0x10>
|
|
|
|
080028f8 <HAL_IncTick>:
|
|
* implementations in user file.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_IncTick(void)
|
|
{
|
|
uwTick += (uint32_t)uwTickFreq;
|
|
80028f8: 4a03 ldr r2, [pc, #12] @ (8002908 <HAL_IncTick+0x10>)
|
|
80028fa: 4b04 ldr r3, [pc, #16] @ (800290c <HAL_IncTick+0x14>)
|
|
80028fc: 6811 ldr r1, [r2, #0]
|
|
80028fe: 781b ldrb r3, [r3, #0]
|
|
8002900: 185b adds r3, r3, r1
|
|
8002902: 6013 str r3, [r2, #0]
|
|
}
|
|
8002904: 4770 bx lr
|
|
8002906: 46c0 nop @ (mov r8, r8)
|
|
8002908: 20001364 .word 0x20001364
|
|
800290c: 2000002c .word 0x2000002c
|
|
|
|
08002910 <HAL_GetTick>:
|
|
* implementations in user file.
|
|
* @retval tick value
|
|
*/
|
|
__weak uint32_t HAL_GetTick(void)
|
|
{
|
|
return uwTick;
|
|
8002910: 4b01 ldr r3, [pc, #4] @ (8002918 <HAL_GetTick+0x8>)
|
|
8002912: 6818 ldr r0, [r3, #0]
|
|
}
|
|
8002914: 4770 bx lr
|
|
8002916: 46c0 nop @ (mov r8, r8)
|
|
8002918: 20001364 .word 0x20001364
|
|
|
|
0800291c <HAL_Delay>:
|
|
* implementations in user file.
|
|
* @param Delay specifies the delay time length, in milliseconds.
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_Delay(uint32_t Delay)
|
|
{
|
|
800291c: b570 push {r4, r5, r6, lr}
|
|
800291e: 0004 movs r4, r0
|
|
uint32_t tickstart = HAL_GetTick();
|
|
8002920: f7ff fff6 bl 8002910 <HAL_GetTick>
|
|
8002924: 0005 movs r5, r0
|
|
uint32_t wait = Delay;
|
|
|
|
/* Add a freq to guarantee minimum wait */
|
|
if (wait < HAL_MAX_DELAY)
|
|
8002926: 1c63 adds r3, r4, #1
|
|
8002928: d002 beq.n 8002930 <HAL_Delay+0x14>
|
|
{
|
|
wait += (uint32_t)(uwTickFreq);
|
|
800292a: 4b04 ldr r3, [pc, #16] @ (800293c <HAL_Delay+0x20>)
|
|
800292c: 781b ldrb r3, [r3, #0]
|
|
800292e: 18e4 adds r4, r4, r3
|
|
}
|
|
|
|
while ((HAL_GetTick() - tickstart) < wait)
|
|
8002930: f7ff ffee bl 8002910 <HAL_GetTick>
|
|
8002934: 1b40 subs r0, r0, r5
|
|
8002936: 42a0 cmp r0, r4
|
|
8002938: d3fa bcc.n 8002930 <HAL_Delay+0x14>
|
|
{
|
|
}
|
|
}
|
|
800293a: bd70 pop {r4, r5, r6, pc}
|
|
800293c: 2000002c .word 0x2000002c
|
|
|
|
08002940 <HAL_GetUIDw0>:
|
|
* @brief Returns first word of the unique device identifier (UID based on 96 bits)
|
|
* @retval Device identifier
|
|
*/
|
|
uint32_t HAL_GetUIDw0(void)
|
|
{
|
|
return (READ_REG(*((uint32_t *)UID_BASE)));
|
|
8002940: 4b01 ldr r3, [pc, #4] @ (8002948 <HAL_GetUIDw0+0x8>)
|
|
8002942: 6818 ldr r0, [r3, #0]
|
|
}
|
|
8002944: 4770 bx lr
|
|
8002946: 46c0 nop @ (mov r8, r8)
|
|
8002948: 1fff7550 .word 0x1fff7550
|
|
|
|
0800294c <HAL_GetUIDw1>:
|
|
* @brief Returns second word of the unique device identifier (UID based on 96 bits)
|
|
* @retval Device identifier
|
|
*/
|
|
uint32_t HAL_GetUIDw1(void)
|
|
{
|
|
return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
|
|
800294c: 4b01 ldr r3, [pc, #4] @ (8002954 <HAL_GetUIDw1+0x8>)
|
|
800294e: 6818 ldr r0, [r3, #0]
|
|
}
|
|
8002950: 4770 bx lr
|
|
8002952: 46c0 nop @ (mov r8, r8)
|
|
8002954: 1fff7554 .word 0x1fff7554
|
|
|
|
08002958 <HAL_GetUIDw2>:
|
|
* @brief Returns third word of the unique device identifier (UID based on 96 bits)
|
|
* @retval Device identifier
|
|
*/
|
|
uint32_t HAL_GetUIDw2(void)
|
|
{
|
|
return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
|
|
8002958: 4b01 ldr r3, [pc, #4] @ (8002960 <HAL_GetUIDw2+0x8>)
|
|
800295a: 6818 ldr r0, [r3, #0]
|
|
}
|
|
800295c: 4770 bx lr
|
|
800295e: 46c0 nop @ (mov r8, r8)
|
|
8002960: 1fff7558 .word 0x1fff7558
|
|
|
|
08002964 <LL_ADC_REG_IsConversionOngoing>:
|
|
* @param ADCx ADC instance
|
|
* @retval 0: no conversion is on going on ADC group regular.
|
|
*/
|
|
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
|
|
{
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
|
|
8002964: 6880 ldr r0, [r0, #8]
|
|
8002966: 0740 lsls r0, r0, #29
|
|
8002968: 0fc0 lsrs r0, r0, #31
|
|
}
|
|
800296a: 4770 bx lr
|
|
|
|
0800296c <HAL_ADC_Init>:
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
uint32_t tmpCFGR1 = 0UL;
|
|
uint32_t tmpCFGR2 = 0UL;
|
|
uint32_t tmp_adc_reg_is_conversion_on_going;
|
|
__IO uint32_t wait_loop_index = 0UL;
|
|
800296c: 2300 movs r3, #0
|
|
{
|
|
800296e: b5f0 push {r4, r5, r6, r7, lr}
|
|
8002970: b085 sub sp, #20
|
|
8002972: 0004 movs r4, r0
|
|
__IO uint32_t wait_loop_index = 0UL;
|
|
8002974: 9303 str r3, [sp, #12]
|
|
|
|
/* Check ADC handle */
|
|
if (hadc == NULL)
|
|
8002976: 4298 cmp r0, r3
|
|
8002978: d100 bne.n 800297c <HAL_ADC_Init+0x10>
|
|
800297a: e0ef b.n 8002b5c <HAL_ADC_Init+0x1f0>
|
|
/* continuous mode is disabled. */
|
|
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
|
|
|
|
/* Actions performed only if ADC is coming from state reset: */
|
|
/* - Initialization of ADC MSP */
|
|
if (hadc->State == HAL_ADC_STATE_RESET)
|
|
800297c: 6d85 ldr r5, [r0, #88] @ 0x58
|
|
800297e: 429d cmp r5, r3
|
|
8002980: d105 bne.n 800298e <HAL_ADC_Init+0x22>
|
|
|
|
/* Init the low level hardware */
|
|
hadc->MspInitCallback(hadc);
|
|
#else
|
|
/* Init the low level hardware */
|
|
HAL_ADC_MspInit(hadc);
|
|
8002982: f7ff fd5f bl 8002444 <HAL_ADC_MspInit>
|
|
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
|
|
/* Initialize Lock */
|
|
hadc->Lock = HAL_UNLOCKED;
|
|
8002986: 0023 movs r3, r4
|
|
8002988: 3354 adds r3, #84 @ 0x54
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
800298a: 65e5 str r5, [r4, #92] @ 0x5c
|
|
hadc->Lock = HAL_UNLOCKED;
|
|
800298c: 701d strb r5, [r3, #0]
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
|
|
800298e: 2380 movs r3, #128 @ 0x80
|
|
}
|
|
|
|
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
|
|
8002990: 6825 ldr r5, [r4, #0]
|
|
8002992: 055b lsls r3, r3, #21
|
|
8002994: 68aa ldr r2, [r5, #8]
|
|
8002996: 421a tst r2, r3
|
|
8002998: d100 bne.n 800299c <HAL_ADC_Init+0x30>
|
|
800299a: e0a7 b.n 8002aec <HAL_ADC_Init+0x180>
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
800299c: 2200 movs r2, #0
|
|
800299e: 68ab ldr r3, [r5, #8]
|
|
80029a0: 9201 str r2, [sp, #4]
|
|
80029a2: 00db lsls r3, r3, #3
|
|
80029a4: d408 bmi.n 80029b8 <HAL_ADC_Init+0x4c>
|
|
/* or not ADC is coming from state reset (if any potential problem of */
|
|
/* clocking, voltage regulator would not be enabled). */
|
|
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
|
|
{
|
|
/* Update ADC state machine to error */
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
80029a6: 2310 movs r3, #16
|
|
|
|
/* Set ADC error code to ADC peripheral internal error */
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
80029a8: 2601 movs r6, #1
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
80029aa: 6da2 ldr r2, [r4, #88] @ 0x58
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
80029ac: 9601 str r6, [sp, #4]
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
80029ae: 4313 orrs r3, r2
|
|
80029b0: 65a3 str r3, [r4, #88] @ 0x58
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
80029b2: 6de3 ldr r3, [r4, #92] @ 0x5c
|
|
80029b4: 4333 orrs r3, r6
|
|
80029b6: 65e3 str r3, [r4, #92] @ 0x5c
|
|
|
|
/* Configuration of ADC parameters if previous preliminary actions are */
|
|
/* correctly completed and if there is no conversion on going on regular */
|
|
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
|
|
/* called to update a parameter on the fly). */
|
|
tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
|
|
80029b8: 0028 movs r0, r5
|
|
80029ba: f7ff ffd3 bl 8002964 <LL_ADC_REG_IsConversionOngoing>
|
|
|
|
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
|
|
80029be: 2210 movs r2, #16
|
|
80029c0: 6da3 ldr r3, [r4, #88] @ 0x58
|
|
80029c2: 4013 ands r3, r2
|
|
80029c4: 4303 orrs r3, r0
|
|
80029c6: d000 beq.n 80029ca <HAL_ADC_Init+0x5e>
|
|
80029c8: e0cb b.n 8002b62 <HAL_ADC_Init+0x1f6>
|
|
&& (tmp_adc_reg_is_conversion_on_going == 0UL)
|
|
)
|
|
{
|
|
/* Set ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
80029ca: 6da2 ldr r2, [r4, #88] @ 0x58
|
|
80029cc: 4b67 ldr r3, [pc, #412] @ (8002b6c <HAL_ADC_Init+0x200>)
|
|
ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
|
|
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
|
|
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
|
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
|
|
hadc->Init.DataAlign |
|
|
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
|
|
80029ce: 6920 ldr r0, [r4, #16]
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
80029d0: 401a ands r2, r3
|
|
80029d2: 3306 adds r3, #6
|
|
80029d4: 33ff adds r3, #255 @ 0xff
|
|
80029d6: 4313 orrs r3, r2
|
|
80029d8: 65a3 str r3, [r4, #88] @ 0x58
|
|
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
|
|
80029da: 68ab ldr r3, [r5, #8]
|
|
80029dc: 07db lsls r3, r3, #31
|
|
80029de: d461 bmi.n 8002aa4 <HAL_ADC_Init+0x138>
|
|
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
|
|
80029e0: 6b27 ldr r7, [r4, #48] @ 0x30
|
|
80029e2: 68e1 ldr r1, [r4, #12]
|
|
80029e4: 1e7b subs r3, r7, #1
|
|
80029e6: 419f sbcs r7, r3
|
|
80029e8: 68a3 ldr r3, [r4, #8]
|
|
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
|
80029ea: 7ea2 ldrb r2, [r4, #26]
|
|
80029ec: 430b orrs r3, r1
|
|
ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
|
|
80029ee: 7e21 ldrb r1, [r4, #24]
|
|
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
|
|
80029f0: 033f lsls r7, r7, #12
|
|
ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
|
|
80029f2: 0389 lsls r1, r1, #14
|
|
80029f4: 430b orrs r3, r1
|
|
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
|
|
80029f6: 7e61 ldrb r1, [r4, #25]
|
|
80029f8: 03c9 lsls r1, r1, #15
|
|
80029fa: 430b orrs r3, r1
|
|
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
|
|
80029fc: 0351 lsls r1, r2, #13
|
|
80029fe: 430b orrs r3, r1
|
|
8002a00: 469c mov ip, r3
|
|
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
|
|
8002a02: 2800 cmp r0, #0
|
|
8002a04: db00 blt.n 8002a08 <HAL_ADC_Init+0x9c>
|
|
8002a06: e085 b.n 8002b14 <HAL_ADC_Init+0x1a8>
|
|
8002a08: 0041 lsls r1, r0, #1
|
|
8002a0a: 0849 lsrs r1, r1, #1
|
|
ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
|
|
8002a0c: 0023 movs r3, r4
|
|
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
|
|
8002a0e: 4666 mov r6, ip
|
|
ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
|
|
8002a10: 332c adds r3, #44 @ 0x2c
|
|
8002a12: 781b ldrb r3, [r3, #0]
|
|
8002a14: 005b lsls r3, r3, #1
|
|
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
|
|
8002a16: 4333 orrs r3, r6
|
|
8002a18: 433b orrs r3, r7
|
|
8002a1a: 430b orrs r3, r1
|
|
|
|
/* Update setting of discontinuous mode only if continuous mode is disabled */
|
|
if (hadc->Init.DiscontinuousConvMode == ENABLE)
|
|
8002a1c: 1c61 adds r1, r4, #1
|
|
8002a1e: 7fc9 ldrb r1, [r1, #31]
|
|
8002a20: 2901 cmp r1, #1
|
|
8002a22: d105 bne.n 8002a30 <HAL_ADC_Init+0xc4>
|
|
{
|
|
if (hadc->Init.ContinuousConvMode == DISABLE)
|
|
8002a24: 2a00 cmp r2, #0
|
|
8002a26: d000 beq.n 8002a2a <HAL_ADC_Init+0xbe>
|
|
8002a28: e077 b.n 8002b1a <HAL_ADC_Init+0x1ae>
|
|
{
|
|
/* Enable the selected ADC group regular discontinuous mode */
|
|
tmpCFGR1 |= ADC_CFGR1_DISCEN;
|
|
8002a2a: 2280 movs r2, #128 @ 0x80
|
|
8002a2c: 0252 lsls r2, r2, #9
|
|
8002a2e: 4313 orrs r3, r2
|
|
/* Enable external trigger if trigger selection is different of software */
|
|
/* start. */
|
|
/* Note: This configuration keeps the hardware feature of parameter */
|
|
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
|
|
/* software start. */
|
|
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
|
|
8002a30: 6a62 ldr r2, [r4, #36] @ 0x24
|
|
8002a32: 2a00 cmp r2, #0
|
|
8002a34: d005 beq.n 8002a42 <HAL_ADC_Init+0xd6>
|
|
{
|
|
tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
|
|
8002a36: 21e0 movs r1, #224 @ 0xe0
|
|
8002a38: 0049 lsls r1, r1, #1
|
|
8002a3a: 400a ands r2, r1
|
|
8002a3c: 6aa1 ldr r1, [r4, #40] @ 0x28
|
|
8002a3e: 430a orrs r2, r1
|
|
8002a40: 4313 orrs r3, r2
|
|
hadc->Init.ExternalTrigConvEdge);
|
|
}
|
|
|
|
/* Update ADC configuration register with previous settings */
|
|
MODIFY_REG(hadc->Instance->CFGR1,
|
|
8002a42: 68ea ldr r2, [r5, #12]
|
|
8002a44: 494a ldr r1, [pc, #296] @ (8002b70 <HAL_ADC_Init+0x204>)
|
|
8002a46: 400a ands r2, r1
|
|
8002a48: 4313 orrs r3, r2
|
|
8002a4a: 60eb str r3, [r5, #12]
|
|
|
|
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
|
|
hadc->Init.TriggerFrequencyMode
|
|
);
|
|
|
|
if (hadc->Init.OversamplingMode == ENABLE)
|
|
8002a4c: 0023 movs r3, r4
|
|
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
|
|
8002a4e: 6862 ldr r2, [r4, #4]
|
|
if (hadc->Init.OversamplingMode == ENABLE)
|
|
8002a50: 333c adds r3, #60 @ 0x3c
|
|
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
|
|
8002a52: 6ce1 ldr r1, [r4, #76] @ 0x4c
|
|
if (hadc->Init.OversamplingMode == ENABLE)
|
|
8002a54: 781b ldrb r3, [r3, #0]
|
|
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
|
|
8002a56: 0f97 lsrs r7, r2, #30
|
|
8002a58: 07bf lsls r7, r7, #30
|
|
if (hadc->Init.OversamplingMode == ENABLE)
|
|
8002a5a: 469c mov ip, r3
|
|
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
|
|
8002a5c: 4339 orrs r1, r7
|
|
if (hadc->Init.OversamplingMode == ENABLE)
|
|
8002a5e: 2b01 cmp r3, #1
|
|
8002a60: d108 bne.n 8002a74 <HAL_ADC_Init+0x108>
|
|
{
|
|
tmpCFGR2 |= (ADC_CFGR2_OVSE |
|
|
8002a62: 6c23 ldr r3, [r4, #64] @ 0x40
|
|
8002a64: 6c66 ldr r6, [r4, #68] @ 0x44
|
|
8002a66: 4333 orrs r3, r6
|
|
8002a68: 430b orrs r3, r1
|
|
8002a6a: 6ca1 ldr r1, [r4, #72] @ 0x48
|
|
8002a6c: 430b orrs r3, r1
|
|
8002a6e: 4661 mov r1, ip
|
|
8002a70: 433b orrs r3, r7
|
|
8002a72: 4319 orrs r1, r3
|
|
hadc->Init.Oversampling.RightBitShift |
|
|
hadc->Init.Oversampling.TriggeredMode
|
|
);
|
|
}
|
|
|
|
MODIFY_REG(hadc->Instance->CFGR2,
|
|
8002a74: 692b ldr r3, [r5, #16]
|
|
8002a76: 4f3f ldr r7, [pc, #252] @ (8002b74 <HAL_ADC_Init+0x208>)
|
|
8002a78: 403b ands r3, r7
|
|
8002a7a: 430b orrs r3, r1
|
|
ADC_CFGR2_TOVS,
|
|
tmpCFGR2);
|
|
|
|
/* Configuration of ADC clock mode: asynchronous clock source */
|
|
/* with selectable prescaler. */
|
|
if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
|
|
8002a7c: 2180 movs r1, #128 @ 0x80
|
|
MODIFY_REG(hadc->Instance->CFGR2,
|
|
8002a7e: 612b str r3, [r5, #16]
|
|
if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
|
|
8002a80: 0053 lsls r3, r2, #1
|
|
8002a82: 085b lsrs r3, r3, #1
|
|
8002a84: 05c9 lsls r1, r1, #23
|
|
8002a86: 428b cmp r3, r1
|
|
8002a88: d00c beq.n 8002aa4 <HAL_ADC_Init+0x138>
|
|
((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
|
|
8002a8a: 2380 movs r3, #128 @ 0x80
|
|
8002a8c: 061b lsls r3, r3, #24
|
|
8002a8e: 429a cmp r2, r3
|
|
8002a90: d008 beq.n 8002aa4 <HAL_ADC_Init+0x138>
|
|
((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4))
|
|
{
|
|
MODIFY_REG(ADC1_COMMON->CCR,
|
|
8002a92: 4939 ldr r1, [pc, #228] @ (8002b78 <HAL_ADC_Init+0x20c>)
|
|
8002a94: 4f39 ldr r7, [pc, #228] @ (8002b7c <HAL_ADC_Init+0x210>)
|
|
8002a96: 680b ldr r3, [r1, #0]
|
|
8002a98: 403b ands r3, r7
|
|
8002a9a: 27f0 movs r7, #240 @ 0xf0
|
|
8002a9c: 03bf lsls r7, r7, #14
|
|
8002a9e: 403a ands r2, r7
|
|
8002aa0: 4313 orrs r3, r2
|
|
8002aa2: 600b str r3, [r1, #0]
|
|
MODIFY_REG(ADCx->SMPR,
|
|
8002aa4: 2107 movs r1, #7
|
|
8002aa6: 2770 movs r7, #112 @ 0x70
|
|
8002aa8: 696b ldr r3, [r5, #20]
|
|
hadc->Init.ClockPrescaler & ADC_CCR_PRESC);
|
|
}
|
|
}
|
|
|
|
/* Channel sampling time configuration */
|
|
LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
|
|
8002aaa: 6b62 ldr r2, [r4, #52] @ 0x34
|
|
8002aac: 438b bics r3, r1
|
|
8002aae: 4313 orrs r3, r2
|
|
8002ab0: 616b str r3, [r5, #20]
|
|
8002ab2: 6969 ldr r1, [r5, #20]
|
|
8002ab4: 6ba3 ldr r3, [r4, #56] @ 0x38
|
|
8002ab6: 43b9 bics r1, r7
|
|
8002ab8: 011b lsls r3, r3, #4
|
|
8002aba: 430b orrs r3, r1
|
|
8002abc: 616b str r3, [r5, #20]
|
|
/* emulated by software for alignment over all STM32 devices. */
|
|
/* - if scan mode is enabled, regular channels sequence length is set to */
|
|
/* parameter "NbrOfConversion". */
|
|
/* Channels must be configured into each rank using function */
|
|
/* "HAL_ADC_ConfigChannel()". */
|
|
if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
|
|
8002abe: 2800 cmp r0, #0
|
|
8002ac0: d133 bne.n 8002b2a <HAL_ADC_Init+0x1be>
|
|
{
|
|
/* Set sequencer scan length by clearing ranks above rank 1 */
|
|
/* and do not modify rank 1 value. */
|
|
SET_BIT(hadc->Instance->CHSELR,
|
|
8002ac2: 2310 movs r3, #16
|
|
8002ac4: 6aa9 ldr r1, [r5, #40] @ 0x28
|
|
8002ac6: 425b negs r3, r3
|
|
/* therefore after the first call of "HAL_ADC_Init()", */
|
|
/* each rank corresponding to parameter "NbrOfConversion" */
|
|
/* must be set using "HAL_ADC_ConfigChannel()". */
|
|
/* - Set sequencer scan length by clearing ranks above maximum rank */
|
|
/* and do not modify other ranks value. */
|
|
MODIFY_REG(hadc->Instance->CHSELR,
|
|
8002ac8: 430b orrs r3, r1
|
|
8002aca: 62ab str r3, [r5, #40] @ 0x28
|
|
return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
|
|
8002acc: 2107 movs r1, #7
|
|
8002ace: 696b ldr r3, [r5, #20]
|
|
8002ad0: 400b ands r3, r1
|
|
{
|
|
/* Nothing to do */
|
|
}
|
|
/* Check back that ADC registers have effectively been configured to */
|
|
/* ensure of no potential problem of ADC core peripheral clocking. */
|
|
if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
|
|
8002ad2: 429a cmp r2, r3
|
|
8002ad4: d138 bne.n 8002b48 <HAL_ADC_Init+0x1dc>
|
|
== hadc->Init.SamplingTimeCommon1)
|
|
{
|
|
/* Set ADC error code to none */
|
|
ADC_CLEAR_ERRORCODE(hadc);
|
|
8002ad6: 2300 movs r3, #0
|
|
8002ad8: 65e3 str r3, [r4, #92] @ 0x5c
|
|
|
|
/* Set the ADC state */
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8002ada: 6da2 ldr r2, [r4, #88] @ 0x58
|
|
8002adc: 3303 adds r3, #3
|
|
8002ade: 439a bics r2, r3
|
|
8002ae0: 3b02 subs r3, #2
|
|
8002ae2: 4313 orrs r3, r2
|
|
8002ae4: 65a3 str r3, [r4, #88] @ 0x58
|
|
tmp_hal_status = HAL_ERROR;
|
|
}
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
8002ae6: 9801 ldr r0, [sp, #4]
|
|
8002ae8: b005 add sp, #20
|
|
8002aea: bdf0 pop {r4, r5, r6, r7, pc}
|
|
MODIFY_REG(ADCx->CR,
|
|
8002aec: 68aa ldr r2, [r5, #8]
|
|
8002aee: 4924 ldr r1, [pc, #144] @ (8002b80 <HAL_ADC_Init+0x214>)
|
|
8002af0: 400a ands r2, r1
|
|
8002af2: 4313 orrs r3, r2
|
|
8002af4: 60ab str r3, [r5, #8]
|
|
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
|
|
8002af6: 4b23 ldr r3, [pc, #140] @ (8002b84 <HAL_ADC_Init+0x218>)
|
|
8002af8: 4923 ldr r1, [pc, #140] @ (8002b88 <HAL_ADC_Init+0x21c>)
|
|
8002afa: 6818 ldr r0, [r3, #0]
|
|
8002afc: f7fd fb18 bl 8000130 <__udivsi3>
|
|
8002b00: 0040 lsls r0, r0, #1
|
|
8002b02: 9003 str r0, [sp, #12]
|
|
while (wait_loop_index != 0UL)
|
|
8002b04: 9b03 ldr r3, [sp, #12]
|
|
8002b06: 2b00 cmp r3, #0
|
|
8002b08: d100 bne.n 8002b0c <HAL_ADC_Init+0x1a0>
|
|
8002b0a: e747 b.n 800299c <HAL_ADC_Init+0x30>
|
|
wait_loop_index--;
|
|
8002b0c: 9b03 ldr r3, [sp, #12]
|
|
8002b0e: 3b01 subs r3, #1
|
|
8002b10: 9303 str r3, [sp, #12]
|
|
8002b12: e7f7 b.n 8002b04 <HAL_ADC_Init+0x198>
|
|
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
|
|
8002b14: 2180 movs r1, #128 @ 0x80
|
|
8002b16: 0389 lsls r1, r1, #14
|
|
8002b18: e778 b.n 8002a0c <HAL_ADC_Init+0xa0>
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
8002b1a: 2220 movs r2, #32
|
|
8002b1c: 6da7 ldr r7, [r4, #88] @ 0x58
|
|
8002b1e: 433a orrs r2, r7
|
|
8002b20: 65a2 str r2, [r4, #88] @ 0x58
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8002b22: 6de2 ldr r2, [r4, #92] @ 0x5c
|
|
8002b24: 4311 orrs r1, r2
|
|
8002b26: 65e1 str r1, [r4, #92] @ 0x5c
|
|
8002b28: e782 b.n 8002a30 <HAL_ADC_Init+0xc4>
|
|
else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
|
|
8002b2a: 2380 movs r3, #128 @ 0x80
|
|
8002b2c: 039b lsls r3, r3, #14
|
|
8002b2e: 4298 cmp r0, r3
|
|
8002b30: d1cc bne.n 8002acc <HAL_ADC_Init+0x160>
|
|
MODIFY_REG(hadc->Instance->CHSELR,
|
|
8002b32: 211c movs r1, #28
|
|
8002b34: 6aab ldr r3, [r5, #40] @ 0x28
|
|
8002b36: 69e3 ldr r3, [r4, #28]
|
|
8002b38: 3b01 subs r3, #1
|
|
8002b3a: 009b lsls r3, r3, #2
|
|
8002b3c: 400b ands r3, r1
|
|
8002b3e: 392c subs r1, #44 @ 0x2c
|
|
8002b40: 4099 lsls r1, r3
|
|
8002b42: 000b movs r3, r1
|
|
8002b44: 6e21 ldr r1, [r4, #96] @ 0x60
|
|
8002b46: e7bf b.n 8002ac8 <HAL_ADC_Init+0x15c>
|
|
ADC_STATE_CLR_SET(hadc->State,
|
|
8002b48: 2312 movs r3, #18
|
|
8002b4a: 6da2 ldr r2, [r4, #88] @ 0x58
|
|
8002b4c: 439a bics r2, r3
|
|
8002b4e: 3b02 subs r3, #2
|
|
8002b50: 4313 orrs r3, r2
|
|
8002b52: 65a3 str r3, [r4, #88] @ 0x58
|
|
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
|
|
8002b54: 2301 movs r3, #1
|
|
8002b56: 6de2 ldr r2, [r4, #92] @ 0x5c
|
|
8002b58: 4313 orrs r3, r2
|
|
8002b5a: 65e3 str r3, [r4, #92] @ 0x5c
|
|
return HAL_ERROR;
|
|
8002b5c: 2301 movs r3, #1
|
|
8002b5e: 9301 str r3, [sp, #4]
|
|
8002b60: e7c1 b.n 8002ae6 <HAL_ADC_Init+0x17a>
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
|
|
8002b62: 6da3 ldr r3, [r4, #88] @ 0x58
|
|
8002b64: 431a orrs r2, r3
|
|
8002b66: 65a2 str r2, [r4, #88] @ 0x58
|
|
tmp_hal_status = HAL_ERROR;
|
|
8002b68: e7f8 b.n 8002b5c <HAL_ADC_Init+0x1f0>
|
|
8002b6a: 46c0 nop @ (mov r8, r8)
|
|
8002b6c: fffffefd .word 0xfffffefd
|
|
8002b70: ffde0201 .word 0xffde0201
|
|
8002b74: 1ffffc02 .word 0x1ffffc02
|
|
8002b78: 40012708 .word 0x40012708
|
|
8002b7c: ffc3ffff .word 0xffc3ffff
|
|
8002b80: 6fffffe8 .word 0x6fffffe8
|
|
8002b84: 20000028 .word 0x20000028
|
|
8002b88: 00030d40 .word 0x00030d40
|
|
|
|
08002b8c <HAL_ADC_ConfigChannel>:
|
|
*/
|
|
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig)
|
|
{
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
uint32_t tmp_config_internal_channel;
|
|
__IO uint32_t wait_loop_index = 0UL;
|
|
8002b8c: 2300 movs r3, #0
|
|
{
|
|
8002b8e: b5f0 push {r4, r5, r6, r7, lr}
|
|
8002b90: b085 sub sp, #20
|
|
__IO uint32_t wait_loop_index = 0UL;
|
|
8002b92: 9303 str r3, [sp, #12]
|
|
|
|
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
|
|
}
|
|
|
|
/* Process locked */
|
|
__HAL_LOCK(hadc);
|
|
8002b94: 0003 movs r3, r0
|
|
{
|
|
8002b96: 9100 str r1, [sp, #0]
|
|
__HAL_LOCK(hadc);
|
|
8002b98: 3354 adds r3, #84 @ 0x54
|
|
8002b9a: 781a ldrb r2, [r3, #0]
|
|
{
|
|
8002b9c: 0004 movs r4, r0
|
|
__HAL_LOCK(hadc);
|
|
8002b9e: 2002 movs r0, #2
|
|
8002ba0: 2a01 cmp r2, #1
|
|
8002ba2: d04d beq.n 8002c40 <HAL_ADC_ConfigChannel+0xb4>
|
|
8002ba4: 2201 movs r2, #1
|
|
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
|
|
8002ba6: 6927 ldr r7, [r4, #16]
|
|
__HAL_LOCK(hadc);
|
|
8002ba8: 701a strb r2, [r3, #0]
|
|
/* Parameters that can be updated when ADC is disabled or enabled without */
|
|
/* conversion on going on regular group: */
|
|
/* - Channel number */
|
|
/* - Channel sampling time */
|
|
/* - Management of internal measurement channels: VrefInt/TempSensor */
|
|
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
|
|
8002baa: 6825 ldr r5, [r4, #0]
|
|
8002bac: 0028 movs r0, r5
|
|
8002bae: f7ff fed9 bl 8002964 <LL_ADC_REG_IsConversionOngoing>
|
|
8002bb2: 2800 cmp r0, #0
|
|
8002bb4: d000 beq.n 8002bb8 <HAL_ADC_ConfigChannel+0x2c>
|
|
8002bb6: e0f9 b.n 8002dac <HAL_ADC_ConfigChannel+0x220>
|
|
/* If sequencer set to not fully configurable with channel rank set to */
|
|
/* none, remove the channel from the sequencer. */
|
|
/* Otherwise (sequencer set to fully configurable or to to not fully */
|
|
/* configurable with channel rank to be set), configure the selected */
|
|
/* channel. */
|
|
if (sConfig->Rank != ADC_RANK_NONE)
|
|
8002bb8: 9b00 ldr r3, [sp, #0]
|
|
/* Note: ADC channel configuration requires few ADC clock cycles */
|
|
/* to be ready. Processing of ADC settings in this function */
|
|
/* induce that a specific wait time is not necessary. */
|
|
/* For more details on ADC channel configuration ready, */
|
|
/* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */
|
|
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
|
|
8002bba: 2204 movs r2, #4
|
|
if (sConfig->Rank != ADC_RANK_NONE)
|
|
8002bbc: 685b ldr r3, [r3, #4]
|
|
8002bbe: 2180 movs r1, #128 @ 0x80
|
|
8002bc0: 469c mov ip, r3
|
|
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
|
|
8002bc2: 4397 bics r7, r2
|
|
if (sConfig->Rank != ADC_RANK_NONE)
|
|
8002bc4: 4662 mov r2, ip
|
|
(hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
|
|
{
|
|
/* Sequencer set to not fully configurable: */
|
|
/* Set the channel by enabling the corresponding bitfield. */
|
|
LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel);
|
|
8002bc6: 9b00 ldr r3, [sp, #0]
|
|
8002bc8: 0609 lsls r1, r1, #24
|
|
8002bca: 681b ldr r3, [r3, #0]
|
|
if (sConfig->Rank != ADC_RANK_NONE)
|
|
8002bcc: 2a02 cmp r2, #2
|
|
8002bce: d100 bne.n 8002bd2 <HAL_ADC_ConfigChannel+0x46>
|
|
8002bd0: e0c7 b.n 8002d62 <HAL_ADC_ConfigChannel+0x1d6>
|
|
SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
|
|
8002bd2: 025a lsls r2, r3, #9
|
|
8002bd4: 0a52 lsrs r2, r2, #9
|
|
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
|
|
8002bd6: 428f cmp r7, r1
|
|
8002bd8: d134 bne.n 8002c44 <HAL_ADC_ConfigChannel+0xb8>
|
|
8002bda: 6aa9 ldr r1, [r5, #40] @ 0x28
|
|
MODIFY_REG(ADCx->CHSELR,
|
|
8002bdc: 430a orrs r2, r1
|
|
8002bde: 62aa str r2, [r5, #40] @ 0x28
|
|
MODIFY_REG(ADCx->SMPR,
|
|
8002be0: 9a00 ldr r2, [sp, #0]
|
|
8002be2: 6968 ldr r0, [r5, #20]
|
|
8002be4: 6892 ldr r2, [r2, #8]
|
|
8002be6: 0219 lsls r1, r3, #8
|
|
8002be8: 4e73 ldr r6, [pc, #460] @ (8002db8 <HAL_ADC_ConfigChannel+0x22c>)
|
|
8002bea: 400a ands r2, r1
|
|
8002bec: 4032 ands r2, r6
|
|
8002bee: 4388 bics r0, r1
|
|
8002bf0: 4302 orrs r2, r0
|
|
8002bf2: 616a str r2, [r5, #20]
|
|
/* internal measurement paths enable: If internal channel selected, */
|
|
/* enable dedicated internal buffers and path. */
|
|
/* Note: these internal measurement paths can be disabled using */
|
|
/* HAL_ADC_DeInit() or removing the channel from sequencer with */
|
|
/* channel configuration parameter "Rank". */
|
|
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
|
|
8002bf4: 2b00 cmp r3, #0
|
|
8002bf6: da1f bge.n 8002c38 <HAL_ADC_ConfigChannel+0xac>
|
|
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
|
|
8002bf8: 20c0 movs r0, #192 @ 0xc0
|
|
8002bfa: 4a70 ldr r2, [pc, #448] @ (8002dbc <HAL_ADC_ConfigChannel+0x230>)
|
|
{
|
|
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
|
|
|
|
/* If the requested internal measurement path has already been enabled, */
|
|
/* bypass the configuration processing. */
|
|
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
|
|
8002bfc: 4970 ldr r1, [pc, #448] @ (8002dc0 <HAL_ADC_ConfigChannel+0x234>)
|
|
8002bfe: 6815 ldr r5, [r2, #0]
|
|
8002c00: 0400 lsls r0, r0, #16
|
|
8002c02: 4028 ands r0, r5
|
|
8002c04: 428b cmp r3, r1
|
|
8002c06: d000 beq.n 8002c0a <HAL_ADC_ConfigChannel+0x7e>
|
|
8002c08: e09b b.n 8002d42 <HAL_ADC_ConfigChannel+0x1b6>
|
|
((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
|
|
8002c0a: 2180 movs r1, #128 @ 0x80
|
|
8002c0c: 0409 lsls r1, r1, #16
|
|
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
|
|
8002c0e: 420d tst r5, r1
|
|
8002c10: d112 bne.n 8002c38 <HAL_ADC_ConfigChannel+0xac>
|
|
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
|
|
8002c12: 6813 ldr r3, [r2, #0]
|
|
8002c14: 4d6b ldr r5, [pc, #428] @ (8002dc4 <HAL_ADC_ConfigChannel+0x238>)
|
|
8002c16: 402b ands r3, r5
|
|
8002c18: 4303 orrs r3, r0
|
|
8002c1a: 4319 orrs r1, r3
|
|
/* Delay for temperature sensor stabilization time */
|
|
/* Wait loop initialization and execution */
|
|
/* Note: Variable divided by 2 to compensate partially */
|
|
/* CPU processing cycles, scaling in us split to not */
|
|
/* exceed 32 bits register capacity and handle low frequency. */
|
|
wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL);
|
|
8002c1c: 4b6a ldr r3, [pc, #424] @ (8002dc8 <HAL_ADC_ConfigChannel+0x23c>)
|
|
8002c1e: 6011 str r1, [r2, #0]
|
|
8002c20: 6818 ldr r0, [r3, #0]
|
|
8002c22: 496a ldr r1, [pc, #424] @ (8002dcc <HAL_ADC_ConfigChannel+0x240>)
|
|
8002c24: f7fd fa84 bl 8000130 <__udivsi3>
|
|
8002c28: 230c movs r3, #12
|
|
8002c2a: 4343 muls r3, r0
|
|
8002c2c: 3301 adds r3, #1
|
|
while (wait_loop_index != 0UL)
|
|
{
|
|
wait_loop_index--;
|
|
8002c2e: 9303 str r3, [sp, #12]
|
|
while (wait_loop_index != 0UL)
|
|
8002c30: 9b03 ldr r3, [sp, #12]
|
|
8002c32: 2b00 cmp r3, #0
|
|
8002c34: d000 beq.n 8002c38 <HAL_ADC_ConfigChannel+0xac>
|
|
8002c36: e081 b.n 8002d3c <HAL_ADC_ConfigChannel+0x1b0>
|
|
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
|
|
8002c38: 2000 movs r0, #0
|
|
|
|
tmp_hal_status = HAL_ERROR;
|
|
}
|
|
|
|
/* Process unlocked */
|
|
__HAL_UNLOCK(hadc);
|
|
8002c3a: 2300 movs r3, #0
|
|
8002c3c: 3454 adds r4, #84 @ 0x54
|
|
8002c3e: 7023 strb r3, [r4, #0]
|
|
|
|
/* Return function status */
|
|
return tmp_hal_status;
|
|
}
|
|
8002c40: b005 add sp, #20
|
|
8002c42: bdf0 pop {r4, r5, r6, r7, pc}
|
|
MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
|
|
8002c44: 211f movs r1, #31
|
|
8002c46: 4667 mov r7, ip
|
|
8002c48: 400f ands r7, r1
|
|
8002c4a: 3910 subs r1, #16
|
|
8002c4c: 40b9 lsls r1, r7
|
|
8002c4e: 43ce mvns r6, r1
|
|
8002c50: 9601 str r6, [sp, #4]
|
|
8002c52: 6e26 ldr r6, [r4, #96] @ 0x60
|
|
8002c54: 438e bics r6, r1
|
|
8002c56: 0031 movs r1, r6
|
|
8002c58: 2a00 cmp r2, #0
|
|
8002c5a: d112 bne.n 8002c82 <HAL_ADC_ConfigChannel+0xf6>
|
|
8002c5c: 0e98 lsrs r0, r3, #26
|
|
8002c5e: 321f adds r2, #31
|
|
8002c60: 4010 ands r0, r2
|
|
8002c62: 40b8 lsls r0, r7
|
|
if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
|
|
8002c64: 4662 mov r2, ip
|
|
MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
|
|
8002c66: 4308 orrs r0, r1
|
|
if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
|
|
8002c68: 0892 lsrs r2, r2, #2
|
|
8002c6a: 69e1 ldr r1, [r4, #28]
|
|
8002c6c: 3201 adds r2, #1
|
|
MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
|
|
8002c6e: 6620 str r0, [r4, #96] @ 0x60
|
|
if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
|
|
8002c70: 428a cmp r2, r1
|
|
8002c72: d8b5 bhi.n 8002be0 <HAL_ADC_ConfigChannel+0x54>
|
|
MODIFY_REG(ADCx->CHSELR,
|
|
8002c74: 6aa9 ldr r1, [r5, #40] @ 0x28
|
|
8002c76: 9801 ldr r0, [sp, #4]
|
|
8002c78: 009a lsls r2, r3, #2
|
|
8002c7a: 0f12 lsrs r2, r2, #28
|
|
8002c7c: 40ba lsls r2, r7
|
|
8002c7e: 4001 ands r1, r0
|
|
8002c80: e7ac b.n 8002bdc <HAL_ADC_ConfigChannel+0x50>
|
|
MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
|
|
8002c82: 2201 movs r2, #1
|
|
8002c84: 4213 tst r3, r2
|
|
8002c86: d1ec bne.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002c88: 1892 adds r2, r2, r2
|
|
8002c8a: 4213 tst r3, r2
|
|
8002c8c: d12c bne.n 8002ce8 <HAL_ADC_ConfigChannel+0x15c>
|
|
8002c8e: 2604 movs r6, #4
|
|
8002c90: 4233 tst r3, r6
|
|
8002c92: d12b bne.n 8002cec <HAL_ADC_ConfigChannel+0x160>
|
|
8002c94: 071a lsls r2, r3, #28
|
|
8002c96: d42b bmi.n 8002cf0 <HAL_ADC_ConfigChannel+0x164>
|
|
8002c98: 06da lsls r2, r3, #27
|
|
8002c9a: d42b bmi.n 8002cf4 <HAL_ADC_ConfigChannel+0x168>
|
|
8002c9c: 069a lsls r2, r3, #26
|
|
8002c9e: d42b bmi.n 8002cf8 <HAL_ADC_ConfigChannel+0x16c>
|
|
8002ca0: 065a lsls r2, r3, #25
|
|
8002ca2: d42b bmi.n 8002cfc <HAL_ADC_ConfigChannel+0x170>
|
|
8002ca4: 061a lsls r2, r3, #24
|
|
8002ca6: d42b bmi.n 8002d00 <HAL_ADC_ConfigChannel+0x174>
|
|
8002ca8: 05da lsls r2, r3, #23
|
|
8002caa: d42b bmi.n 8002d04 <HAL_ADC_ConfigChannel+0x178>
|
|
8002cac: 059a lsls r2, r3, #22
|
|
8002cae: d42b bmi.n 8002d08 <HAL_ADC_ConfigChannel+0x17c>
|
|
8002cb0: 055a lsls r2, r3, #21
|
|
8002cb2: d42b bmi.n 8002d0c <HAL_ADC_ConfigChannel+0x180>
|
|
8002cb4: 051a lsls r2, r3, #20
|
|
8002cb6: d42b bmi.n 8002d10 <HAL_ADC_ConfigChannel+0x184>
|
|
8002cb8: 04da lsls r2, r3, #19
|
|
8002cba: d42b bmi.n 8002d14 <HAL_ADC_ConfigChannel+0x188>
|
|
8002cbc: 049a lsls r2, r3, #18
|
|
8002cbe: d42b bmi.n 8002d18 <HAL_ADC_ConfigChannel+0x18c>
|
|
8002cc0: 045a lsls r2, r3, #17
|
|
8002cc2: d42b bmi.n 8002d1c <HAL_ADC_ConfigChannel+0x190>
|
|
8002cc4: 041a lsls r2, r3, #16
|
|
8002cc6: d42b bmi.n 8002d20 <HAL_ADC_ConfigChannel+0x194>
|
|
8002cc8: 03da lsls r2, r3, #15
|
|
8002cca: d42b bmi.n 8002d24 <HAL_ADC_ConfigChannel+0x198>
|
|
8002ccc: 039a lsls r2, r3, #14
|
|
8002cce: d42b bmi.n 8002d28 <HAL_ADC_ConfigChannel+0x19c>
|
|
8002cd0: 035a lsls r2, r3, #13
|
|
8002cd2: d42b bmi.n 8002d2c <HAL_ADC_ConfigChannel+0x1a0>
|
|
8002cd4: 031a lsls r2, r3, #12
|
|
8002cd6: d42b bmi.n 8002d30 <HAL_ADC_ConfigChannel+0x1a4>
|
|
8002cd8: 02da lsls r2, r3, #11
|
|
8002cda: d42b bmi.n 8002d34 <HAL_ADC_ConfigChannel+0x1a8>
|
|
8002cdc: 029a lsls r2, r3, #10
|
|
8002cde: d42b bmi.n 8002d38 <HAL_ADC_ConfigChannel+0x1ac>
|
|
8002ce0: 025a lsls r2, r3, #9
|
|
8002ce2: d5be bpl.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002ce4: 2016 movs r0, #22
|
|
8002ce6: e7bc b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002ce8: 2001 movs r0, #1
|
|
8002cea: e7ba b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002cec: 0010 movs r0, r2
|
|
8002cee: e7b8 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002cf0: 2003 movs r0, #3
|
|
8002cf2: e7b6 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002cf4: 2004 movs r0, #4
|
|
8002cf6: e7b4 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002cf8: 2005 movs r0, #5
|
|
8002cfa: e7b2 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002cfc: 2006 movs r0, #6
|
|
8002cfe: e7b0 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d00: 2007 movs r0, #7
|
|
8002d02: e7ae b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d04: 2008 movs r0, #8
|
|
8002d06: e7ac b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d08: 2009 movs r0, #9
|
|
8002d0a: e7aa b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d0c: 200a movs r0, #10
|
|
8002d0e: e7a8 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d10: 200b movs r0, #11
|
|
8002d12: e7a6 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d14: 200c movs r0, #12
|
|
8002d16: e7a4 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d18: 200d movs r0, #13
|
|
8002d1a: e7a2 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d1c: 200e movs r0, #14
|
|
8002d1e: e7a0 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d20: 200f movs r0, #15
|
|
8002d22: e79e b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d24: 2010 movs r0, #16
|
|
8002d26: e79c b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d28: 2011 movs r0, #17
|
|
8002d2a: e79a b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d2c: 2012 movs r0, #18
|
|
8002d2e: e798 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d30: 2013 movs r0, #19
|
|
8002d32: e796 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d34: 2014 movs r0, #20
|
|
8002d36: e794 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
8002d38: 2015 movs r0, #21
|
|
8002d3a: e792 b.n 8002c62 <HAL_ADC_ConfigChannel+0xd6>
|
|
wait_loop_index--;
|
|
8002d3c: 9b03 ldr r3, [sp, #12]
|
|
8002d3e: 3b01 subs r3, #1
|
|
8002d40: e775 b.n 8002c2e <HAL_ADC_ConfigChannel+0xa2>
|
|
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) &&
|
|
8002d42: 4923 ldr r1, [pc, #140] @ (8002dd0 <HAL_ADC_ConfigChannel+0x244>)
|
|
8002d44: 428b cmp r3, r1
|
|
8002d46: d000 beq.n 8002d4a <HAL_ADC_ConfigChannel+0x1be>
|
|
8002d48: e776 b.n 8002c38 <HAL_ADC_ConfigChannel+0xac>
|
|
((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
|
|
8002d4a: 2180 movs r1, #128 @ 0x80
|
|
8002d4c: 03c9 lsls r1, r1, #15
|
|
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) &&
|
|
8002d4e: 420d tst r5, r1
|
|
8002d50: d000 beq.n 8002d54 <HAL_ADC_ConfigChannel+0x1c8>
|
|
8002d52: e771 b.n 8002c38 <HAL_ADC_ConfigChannel+0xac>
|
|
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
|
|
8002d54: 6813 ldr r3, [r2, #0]
|
|
8002d56: 4d1b ldr r5, [pc, #108] @ (8002dc4 <HAL_ADC_ConfigChannel+0x238>)
|
|
8002d58: 402b ands r3, r5
|
|
8002d5a: 4303 orrs r3, r0
|
|
8002d5c: 4319 orrs r1, r3
|
|
8002d5e: 6011 str r1, [r2, #0]
|
|
}
|
|
8002d60: e76a b.n 8002c38 <HAL_ADC_ConfigChannel+0xac>
|
|
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
|
|
8002d62: 428f cmp r7, r1
|
|
8002d64: d104 bne.n 8002d70 <HAL_ADC_ConfigChannel+0x1e4>
|
|
CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
|
|
8002d66: 6aaa ldr r2, [r5, #40] @ 0x28
|
|
8002d68: 0259 lsls r1, r3, #9
|
|
8002d6a: 0a49 lsrs r1, r1, #9
|
|
8002d6c: 438a bics r2, r1
|
|
8002d6e: 62aa str r2, [r5, #40] @ 0x28
|
|
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
|
|
8002d70: 2b00 cmp r3, #0
|
|
8002d72: db00 blt.n 8002d76 <HAL_ADC_ConfigChannel+0x1ea>
|
|
8002d74: e760 b.n 8002c38 <HAL_ADC_ConfigChannel+0xac>
|
|
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
|
|
8002d76: 4911 ldr r1, [pc, #68] @ (8002dbc <HAL_ADC_ConfigChannel+0x230>)
|
|
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
|
|
8002d78: 4811 ldr r0, [pc, #68] @ (8002dc0 <HAL_ADC_ConfigChannel+0x234>)
|
|
8002d7a: 680a ldr r2, [r1, #0]
|
|
8002d7c: 4283 cmp r3, r0
|
|
8002d7e: d108 bne.n 8002d92 <HAL_ADC_ConfigChannel+0x206>
|
|
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
|
8002d80: 2380 movs r3, #128 @ 0x80
|
|
8002d82: 03db lsls r3, r3, #15
|
|
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
|
|
8002d84: 6808 ldr r0, [r1, #0]
|
|
8002d86: 4013 ands r3, r2
|
|
8002d88: 4a0e ldr r2, [pc, #56] @ (8002dc4 <HAL_ADC_ConfigChannel+0x238>)
|
|
8002d8a: 4002 ands r2, r0
|
|
8002d8c: 4313 orrs r3, r2
|
|
8002d8e: 600b str r3, [r1, #0]
|
|
}
|
|
8002d90: e752 b.n 8002c38 <HAL_ADC_ConfigChannel+0xac>
|
|
else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
|
|
8002d92: 480f ldr r0, [pc, #60] @ (8002dd0 <HAL_ADC_ConfigChannel+0x244>)
|
|
8002d94: 4283 cmp r3, r0
|
|
8002d96: d000 beq.n 8002d9a <HAL_ADC_ConfigChannel+0x20e>
|
|
8002d98: e74e b.n 8002c38 <HAL_ADC_ConfigChannel+0xac>
|
|
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
|
|
8002d9a: 2080 movs r0, #128 @ 0x80
|
|
8002d9c: 0400 lsls r0, r0, #16
|
|
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
|
|
8002d9e: 680b ldr r3, [r1, #0]
|
|
8002da0: 4002 ands r2, r0
|
|
8002da2: 4808 ldr r0, [pc, #32] @ (8002dc4 <HAL_ADC_ConfigChannel+0x238>)
|
|
8002da4: 4003 ands r3, r0
|
|
8002da6: 431a orrs r2, r3
|
|
8002da8: 600a str r2, [r1, #0]
|
|
}
|
|
8002daa: e745 b.n 8002c38 <HAL_ADC_ConfigChannel+0xac>
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
8002dac: 2320 movs r3, #32
|
|
8002dae: 6da2 ldr r2, [r4, #88] @ 0x58
|
|
tmp_hal_status = HAL_ERROR;
|
|
8002db0: 2001 movs r0, #1
|
|
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
|
|
8002db2: 4313 orrs r3, r2
|
|
8002db4: 65a3 str r3, [r4, #88] @ 0x58
|
|
tmp_hal_status = HAL_ERROR;
|
|
8002db6: e740 b.n 8002c3a <HAL_ADC_ConfigChannel+0xae>
|
|
8002db8: 7fffff00 .word 0x7fffff00
|
|
8002dbc: 40012708 .word 0x40012708
|
|
8002dc0: a4000200 .word 0xa4000200
|
|
8002dc4: ff3fffff .word 0xff3fffff
|
|
8002dc8: 20000028 .word 0x20000028
|
|
8002dcc: 00030d40 .word 0x00030d40
|
|
8002dd0: a8000400 .word 0xa8000400
|
|
|
|
08002dd4 <HAL_NVIC_SetPriority>:
|
|
* with stm32c0xx devices, this parameter is a dummy value and it is ignored, because
|
|
* no subpriority supported in Cortex M0+ based products.
|
|
* @retval None
|
|
*/
|
|
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
|
|
{
|
|
8002dd4: b510 push {r4, lr}
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8002dd6: 24ff movs r4, #255 @ 0xff
|
|
8002dd8: 2203 movs r2, #3
|
|
8002dda: 000b movs r3, r1
|
|
8002ddc: 0021 movs r1, r4
|
|
8002dde: 4002 ands r2, r0
|
|
8002de0: 00d2 lsls r2, r2, #3
|
|
8002de2: 4091 lsls r1, r2
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
8002de4: 019b lsls r3, r3, #6
|
|
8002de6: 4023 ands r3, r4
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8002de8: 43c9 mvns r1, r1
|
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
|
8002dea: 4093 lsls r3, r2
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8002dec: 2800 cmp r0, #0
|
|
8002dee: db0a blt.n 8002e06 <HAL_NVIC_SetPriority+0x32>
|
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8002df0: 24c0 movs r4, #192 @ 0xc0
|
|
8002df2: 4a0b ldr r2, [pc, #44] @ (8002e20 <HAL_NVIC_SetPriority+0x4c>)
|
|
8002df4: 0880 lsrs r0, r0, #2
|
|
8002df6: 0080 lsls r0, r0, #2
|
|
8002df8: 1880 adds r0, r0, r2
|
|
8002dfa: 00a4 lsls r4, r4, #2
|
|
8002dfc: 5902 ldr r2, [r0, r4]
|
|
8002dfe: 400a ands r2, r1
|
|
8002e00: 4313 orrs r3, r2
|
|
8002e02: 5103 str r3, [r0, r4]
|
|
/* Prevent unused argument(s) compilation warning */
|
|
UNUSED(SubPriority);
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
|
NVIC_SetPriority(IRQn, PreemptPriority);
|
|
}
|
|
8002e04: bd10 pop {r4, pc}
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8002e06: 220f movs r2, #15
|
|
8002e08: 4010 ands r0, r2
|
|
8002e0a: 3808 subs r0, #8
|
|
8002e0c: 4a05 ldr r2, [pc, #20] @ (8002e24 <HAL_NVIC_SetPriority+0x50>)
|
|
8002e0e: 0880 lsrs r0, r0, #2
|
|
8002e10: 0080 lsls r0, r0, #2
|
|
8002e12: 1880 adds r0, r0, r2
|
|
8002e14: 69c2 ldr r2, [r0, #28]
|
|
8002e16: 4011 ands r1, r2
|
|
8002e18: 4319 orrs r1, r3
|
|
8002e1a: 61c1 str r1, [r0, #28]
|
|
8002e1c: e7f2 b.n 8002e04 <HAL_NVIC_SetPriority+0x30>
|
|
8002e1e: 46c0 nop @ (mov r8, r8)
|
|
8002e20: e000e100 .word 0xe000e100
|
|
8002e24: e000ed00 .word 0xe000ed00
|
|
|
|
08002e28 <HAL_NVIC_EnableIRQ>:
|
|
if ((int32_t)(IRQn) >= 0)
|
|
8002e28: 2800 cmp r0, #0
|
|
8002e2a: db05 blt.n 8002e38 <HAL_NVIC_EnableIRQ+0x10>
|
|
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
|
8002e2c: 231f movs r3, #31
|
|
8002e2e: 4018 ands r0, r3
|
|
8002e30: 3b1e subs r3, #30
|
|
8002e32: 4083 lsls r3, r0
|
|
8002e34: 4a01 ldr r2, [pc, #4] @ (8002e3c <HAL_NVIC_EnableIRQ+0x14>)
|
|
8002e36: 6013 str r3, [r2, #0]
|
|
/* Check the parameters */
|
|
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
|
|
|
|
/* Enable interrupt */
|
|
NVIC_EnableIRQ(IRQn);
|
|
}
|
|
8002e38: 4770 bx lr
|
|
8002e3a: 46c0 nop @ (mov r8, r8)
|
|
8002e3c: e000e100 .word 0xe000e100
|
|
|
|
08002e40 <HAL_SYSTICK_Config>:
|
|
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
|
must contain a vendor-specific implementation of this function.
|
|
*/
|
|
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
|
{
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8002e40: 2280 movs r2, #128 @ 0x80
|
|
8002e42: 1e43 subs r3, r0, #1
|
|
8002e44: 0452 lsls r2, r2, #17
|
|
{
|
|
return (1UL); /* Reload value impossible */
|
|
8002e46: 2001 movs r0, #1
|
|
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
|
8002e48: 4293 cmp r3, r2
|
|
8002e4a: d20d bcs.n 8002e68 <HAL_SYSTICK_Config+0x28>
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8002e4c: 21c0 movs r1, #192 @ 0xc0
|
|
}
|
|
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8002e4e: 4a07 ldr r2, [pc, #28] @ (8002e6c <HAL_SYSTICK_Config+0x2c>)
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8002e50: 4807 ldr r0, [pc, #28] @ (8002e70 <HAL_SYSTICK_Config+0x30>)
|
|
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
|
8002e52: 6053 str r3, [r2, #4]
|
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
|
8002e54: 6a03 ldr r3, [r0, #32]
|
|
8002e56: 0609 lsls r1, r1, #24
|
|
8002e58: 021b lsls r3, r3, #8
|
|
8002e5a: 0a1b lsrs r3, r3, #8
|
|
8002e5c: 430b orrs r3, r1
|
|
8002e5e: 6203 str r3, [r0, #32]
|
|
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8002e60: 2000 movs r0, #0
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8002e62: 2307 movs r3, #7
|
|
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
|
8002e64: 6090 str r0, [r2, #8]
|
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
|
8002e66: 6013 str r3, [r2, #0]
|
|
* - 1 Function failed.
|
|
*/
|
|
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
|
|
{
|
|
return SysTick_Config(TicksNumb);
|
|
}
|
|
8002e68: 4770 bx lr
|
|
8002e6a: 46c0 nop @ (mov r8, r8)
|
|
8002e6c: e000e010 .word 0xe000e010
|
|
8002e70: e000ed00 .word 0xe000ed00
|
|
|
|
08002e74 <DMA_SetConfig>:
|
|
* @param DstAddress The destination memory Buffer address
|
|
* @param DataLength The length of data to be transferred from source to destination
|
|
* @retval HAL status
|
|
*/
|
|
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
|
|
{
|
|
8002e74: b5f0 push {r4, r5, r6, r7, lr}
|
|
/* Clear the DMAMUX synchro overrun flag */
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8002e76: 6c84 ldr r4, [r0, #72] @ 0x48
|
|
8002e78: 6cc5 ldr r5, [r0, #76] @ 0x4c
|
|
8002e7a: 6065 str r5, [r4, #4]
|
|
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
|
8002e7c: 6d04 ldr r4, [r0, #80] @ 0x50
|
|
8002e7e: 2c00 cmp r4, #0
|
|
8002e80: d002 beq.n 8002e88 <DMA_SetConfig+0x14>
|
|
{
|
|
/* Clear the DMAMUX request generator overrun flag */
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8002e82: 6d44 ldr r4, [r0, #84] @ 0x54
|
|
8002e84: 6d85 ldr r5, [r0, #88] @ 0x58
|
|
8002e86: 6065 str r5, [r4, #4]
|
|
}
|
|
|
|
/* Clear all flags */
|
|
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU)));
|
|
8002e88: 241c movs r4, #28
|
|
8002e8a: 6c05 ldr r5, [r0, #64] @ 0x40
|
|
8002e8c: 4e08 ldr r6, [pc, #32] @ (8002eb0 <DMA_SetConfig+0x3c>)
|
|
8002e8e: 4025 ands r5, r4
|
|
8002e90: 3c1b subs r4, #27
|
|
8002e92: 40ac lsls r4, r5
|
|
8002e94: 6877 ldr r7, [r6, #4]
|
|
8002e96: 433c orrs r4, r7
|
|
8002e98: 6074 str r4, [r6, #4]
|
|
|
|
/* Configure DMA Channel data length */
|
|
hdma->Instance->CNDTR = DataLength;
|
|
8002e9a: 6804 ldr r4, [r0, #0]
|
|
8002e9c: 6063 str r3, [r4, #4]
|
|
|
|
/* Peripheral to Memory */
|
|
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
|
|
8002e9e: 6883 ldr r3, [r0, #8]
|
|
8002ea0: 2b10 cmp r3, #16
|
|
8002ea2: d102 bne.n 8002eaa <DMA_SetConfig+0x36>
|
|
{
|
|
/* Configure DMA Channel destination address */
|
|
hdma->Instance->CPAR = DstAddress;
|
|
8002ea4: 60a2 str r2, [r4, #8]
|
|
|
|
/* Configure DMA Channel source address */
|
|
hdma->Instance->CMAR = SrcAddress;
|
|
8002ea6: 60e1 str r1, [r4, #12]
|
|
hdma->Instance->CPAR = SrcAddress;
|
|
|
|
/* Configure DMA Channel destination address */
|
|
hdma->Instance->CMAR = DstAddress;
|
|
}
|
|
}
|
|
8002ea8: bdf0 pop {r4, r5, r6, r7, pc}
|
|
hdma->Instance->CPAR = SrcAddress;
|
|
8002eaa: 60a1 str r1, [r4, #8]
|
|
hdma->Instance->CMAR = DstAddress;
|
|
8002eac: 60e2 str r2, [r4, #12]
|
|
}
|
|
8002eae: e7fb b.n 8002ea8 <DMA_SetConfig+0x34>
|
|
8002eb0: 40020000 .word 0x40020000
|
|
|
|
08002eb4 <DMA_CalcDMAMUXChannelBaseAndMask>:
|
|
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
|
|
* the configuration information for the specified DMA Stream.
|
|
* @retval None
|
|
*/
|
|
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8002eb4: b510 push {r4, lr}
|
|
8002eb6: 0004 movs r4, r0
|
|
uint32_t channel_number;
|
|
|
|
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
|
|
8002eb8: 6800 ldr r0, [r0, #0]
|
|
8002eba: 2114 movs r1, #20
|
|
8002ebc: b2c0 uxtb r0, r0
|
|
8002ebe: 3808 subs r0, #8
|
|
8002ec0: f7fd f936 bl 8000130 <__udivsi3>
|
|
hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \
|
|
((hdma->ChannelIndex >> 2U) * \
|
|
8002ec4: 6c23 ldr r3, [r4, #64] @ 0x40
|
|
hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \
|
|
8002ec6: 4a06 ldr r2, [pc, #24] @ (8002ee0 <DMA_CalcDMAMUXChannelBaseAndMask+0x2c>)
|
|
((hdma->ChannelIndex >> 2U) * \
|
|
8002ec8: 089b lsrs r3, r3, #2
|
|
hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \
|
|
8002eca: 189b adds r3, r3, r2
|
|
8002ecc: 009b lsls r3, r3, #2
|
|
8002ece: 6463 str r3, [r4, #68] @ 0x44
|
|
((uint32_t)DMAMUX1_Channel1 - \
|
|
(uint32_t)DMAMUX1_Channel0)));
|
|
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
|
|
8002ed0: 4b04 ldr r3, [pc, #16] @ (8002ee4 <DMA_CalcDMAMUXChannelBaseAndMask+0x30>)
|
|
8002ed2: 64a3 str r3, [r4, #72] @ 0x48
|
|
hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU);
|
|
8002ed4: 231c movs r3, #28
|
|
8002ed6: 4018 ands r0, r3
|
|
8002ed8: 3b1b subs r3, #27
|
|
8002eda: 4083 lsls r3, r0
|
|
8002edc: 64e3 str r3, [r4, #76] @ 0x4c
|
|
}
|
|
8002ede: bd10 pop {r4, pc}
|
|
8002ee0: 10008200 .word 0x10008200
|
|
8002ee4: 40020880 .word 0x40020880
|
|
|
|
08002ee8 <HAL_DMA_Init>:
|
|
{
|
|
8002ee8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8002eea: 0004 movs r4, r0
|
|
return HAL_ERROR;
|
|
8002eec: 2001 movs r0, #1
|
|
if (hdma == NULL)
|
|
8002eee: 2c00 cmp r4, #0
|
|
8002ef0: d045 beq.n 8002f7e <HAL_DMA_Init+0x96>
|
|
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \
|
|
8002ef2: 6825 ldr r5, [r4, #0]
|
|
8002ef4: 4b25 ldr r3, [pc, #148] @ (8002f8c <HAL_DMA_Init+0xa4>)
|
|
8002ef6: 2114 movs r1, #20
|
|
8002ef8: 18e8 adds r0, r5, r3
|
|
8002efa: f7fd f919 bl 8000130 <__udivsi3>
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
8002efe: 2302 movs r3, #2
|
|
(uint32_t)DMA1_Channel1)) << 2U;
|
|
8002f00: 0080 lsls r0, r0, #2
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
8002f02: 1da6 adds r6, r4, #6
|
|
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \
|
|
8002f04: 6420 str r0, [r4, #64] @ 0x40
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
8002f06: 77f3 strb r3, [r6, #31]
|
|
CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
|
|
8002f08: 682b ldr r3, [r5, #0]
|
|
8002f0a: 4a21 ldr r2, [pc, #132] @ (8002f90 <HAL_DMA_Init+0xa8>)
|
|
SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \
|
|
8002f0c: 68a7 ldr r7, [r4, #8]
|
|
CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
|
|
8002f0e: 4013 ands r3, r2
|
|
8002f10: 602b str r3, [r5, #0]
|
|
SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \
|
|
8002f12: 68e3 ldr r3, [r4, #12]
|
|
8002f14: 6921 ldr r1, [r4, #16]
|
|
8002f16: 433b orrs r3, r7
|
|
8002f18: 430b orrs r3, r1
|
|
8002f1a: 6961 ldr r1, [r4, #20]
|
|
8002f1c: 682a ldr r2, [r5, #0]
|
|
8002f1e: 430b orrs r3, r1
|
|
8002f20: 69a1 ldr r1, [r4, #24]
|
|
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
|
|
8002f22: 0020 movs r0, r4
|
|
SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \
|
|
8002f24: 430b orrs r3, r1
|
|
8002f26: 69e1 ldr r1, [r4, #28]
|
|
8002f28: 430b orrs r3, r1
|
|
8002f2a: 6a21 ldr r1, [r4, #32]
|
|
8002f2c: 430b orrs r3, r1
|
|
8002f2e: 4313 orrs r3, r2
|
|
8002f30: 602b str r3, [r5, #0]
|
|
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
|
|
8002f32: f7ff ffbf bl 8002eb4 <DMA_CalcDMAMUXChannelBaseAndMask>
|
|
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
|
|
8002f36: 2380 movs r3, #128 @ 0x80
|
|
8002f38: 01db lsls r3, r3, #7
|
|
8002f3a: 429f cmp r7, r3
|
|
8002f3c: d101 bne.n 8002f42 <HAL_DMA_Init+0x5a>
|
|
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
|
|
8002f3e: 2300 movs r3, #0
|
|
8002f40: 6063 str r3, [r4, #4]
|
|
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
|
|
8002f42: 6862 ldr r2, [r4, #4]
|
|
8002f44: 6c61 ldr r1, [r4, #68] @ 0x44
|
|
8002f46: b2d3 uxtb r3, r2
|
|
8002f48: 600b str r3, [r1, #0]
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8002f4a: 6ce0 ldr r0, [r4, #76] @ 0x4c
|
|
8002f4c: 6ca1 ldr r1, [r4, #72] @ 0x48
|
|
if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
|
|
8002f4e: 3a01 subs r2, #1
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8002f50: 6048 str r0, [r1, #4]
|
|
if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
|
|
8002f52: 2a03 cmp r2, #3
|
|
8002f54: d814 bhi.n 8002f80 <HAL_DMA_Init+0x98>
|
|
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
|
|
{
|
|
uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
|
|
|
|
/* DMA Channels are connected to DMAMUX1 request generator blocks*/
|
|
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \
|
|
8002f56: 4a0f ldr r2, [pc, #60] @ (8002f94 <HAL_DMA_Init+0xac>)
|
|
((request - 1U) * 4U)));
|
|
|
|
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
|
|
8002f58: 480f ldr r0, [pc, #60] @ (8002f98 <HAL_DMA_Init+0xb0>)
|
|
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \
|
|
8002f5a: 1899 adds r1, r3, r2
|
|
|
|
/* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/
|
|
hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
|
|
8002f5c: 2201 movs r2, #1
|
|
8002f5e: 3b01 subs r3, #1
|
|
8002f60: 409a lsls r2, r3
|
|
8002f62: 65a2 str r2, [r4, #88] @ 0x58
|
|
8002f64: 0013 movs r3, r2
|
|
hdma->DMAmuxRequestGen->RGCR = 0U;
|
|
8002f66: 2200 movs r2, #0
|
|
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \
|
|
8002f68: 0089 lsls r1, r1, #2
|
|
8002f6a: 6521 str r1, [r4, #80] @ 0x50
|
|
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
|
|
8002f6c: 6560 str r0, [r4, #84] @ 0x54
|
|
hdma->DMAmuxRequestGen->RGCR = 0U;
|
|
8002f6e: 600a str r2, [r1, #0]
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8002f70: 6043 str r3, [r0, #4]
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8002f72: 2000 movs r0, #0
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8002f74: 2301 movs r3, #1
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8002f76: 63e0 str r0, [r4, #60] @ 0x3c
|
|
__HAL_UNLOCK(hdma);
|
|
8002f78: 3405 adds r4, #5
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8002f7a: 77f3 strb r3, [r6, #31]
|
|
__HAL_UNLOCK(hdma);
|
|
8002f7c: 77e0 strb r0, [r4, #31]
|
|
}
|
|
8002f7e: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
hdma->DMAmuxRequestGen = 0U;
|
|
8002f80: 2300 movs r3, #0
|
|
8002f82: 6523 str r3, [r4, #80] @ 0x50
|
|
hdma->DMAmuxRequestGenStatus = 0U;
|
|
8002f84: 6563 str r3, [r4, #84] @ 0x54
|
|
hdma->DMAmuxRequestGenStatusMask = 0U;
|
|
8002f86: 65a3 str r3, [r4, #88] @ 0x58
|
|
8002f88: e7f3 b.n 8002f72 <HAL_DMA_Init+0x8a>
|
|
8002f8a: 46c0 nop @ (mov r8, r8)
|
|
8002f8c: bffdfff8 .word 0xbffdfff8
|
|
8002f90: ffff800f .word 0xffff800f
|
|
8002f94: 1000823f .word 0x1000823f
|
|
8002f98: 40020940 .word 0x40020940
|
|
|
|
08002f9c <HAL_DMA_Start_IT>:
|
|
{
|
|
8002f9c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
__HAL_LOCK(hdma);
|
|
8002f9e: 1d46 adds r6, r0, #5
|
|
{
|
|
8002fa0: 9301 str r3, [sp, #4]
|
|
__HAL_LOCK(hdma);
|
|
8002fa2: 7ff4 ldrb r4, [r6, #31]
|
|
{
|
|
8002fa4: 0005 movs r5, r0
|
|
__HAL_LOCK(hdma);
|
|
8002fa6: 2002 movs r0, #2
|
|
8002fa8: 2c01 cmp r4, #1
|
|
8002faa: d036 beq.n 800301a <HAL_DMA_Start_IT+0x7e>
|
|
8002fac: 3801 subs r0, #1
|
|
8002fae: 77f0 strb r0, [r6, #31]
|
|
if (HAL_DMA_STATE_READY == hdma->State)
|
|
8002fb0: 1dac adds r4, r5, #6
|
|
8002fb2: 7fe0 ldrb r0, [r4, #31]
|
|
8002fb4: 2702 movs r7, #2
|
|
8002fb6: 4684 mov ip, r0
|
|
8002fb8: 4663 mov r3, ip
|
|
8002fba: b2c0 uxtb r0, r0
|
|
8002fbc: 9000 str r0, [sp, #0]
|
|
status = HAL_BUSY;
|
|
8002fbe: 0038 movs r0, r7
|
|
if (HAL_DMA_STATE_READY == hdma->State)
|
|
8002fc0: 2b01 cmp r3, #1
|
|
8002fc2: d128 bne.n 8003016 <HAL_DMA_Start_IT+0x7a>
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8002fc4: 2000 movs r0, #0
|
|
hdma->State = HAL_DMA_STATE_BUSY;
|
|
8002fc6: 77e7 strb r7, [r4, #31]
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8002fc8: 682c ldr r4, [r5, #0]
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
|
|
8002fca: 63e8 str r0, [r5, #60] @ 0x3c
|
|
__HAL_DMA_DISABLE(hdma);
|
|
8002fcc: 6820 ldr r0, [r4, #0]
|
|
8002fce: 9b00 ldr r3, [sp, #0]
|
|
8002fd0: 4398 bics r0, r3
|
|
8002fd2: 6020 str r0, [r4, #0]
|
|
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
|
|
8002fd4: 9b01 ldr r3, [sp, #4]
|
|
8002fd6: 0028 movs r0, r5
|
|
8002fd8: f7ff ff4c bl 8002e74 <DMA_SetConfig>
|
|
if (NULL != hdma->XferHalfCpltCallback)
|
|
8002fdc: 6b2b ldr r3, [r5, #48] @ 0x30
|
|
8002fde: 2b00 cmp r3, #0
|
|
8002fe0: d01c beq.n 800301c <HAL_DMA_Start_IT+0x80>
|
|
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8002fe2: 230e movs r3, #14
|
|
8002fe4: 6822 ldr r2, [r4, #0]
|
|
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
|
|
8002fe6: 4313 orrs r3, r2
|
|
8002fe8: 6023 str r3, [r4, #0]
|
|
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
|
|
8002fea: 6c6b ldr r3, [r5, #68] @ 0x44
|
|
8002fec: 681a ldr r2, [r3, #0]
|
|
8002fee: 03d2 lsls r2, r2, #15
|
|
8002ff0: d504 bpl.n 8002ffc <HAL_DMA_Start_IT+0x60>
|
|
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
|
|
8002ff2: 2280 movs r2, #128 @ 0x80
|
|
8002ff4: 6819 ldr r1, [r3, #0]
|
|
8002ff6: 0052 lsls r2, r2, #1
|
|
8002ff8: 430a orrs r2, r1
|
|
8002ffa: 601a str r2, [r3, #0]
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
|
8002ffc: 6d2b ldr r3, [r5, #80] @ 0x50
|
|
8002ffe: 2b00 cmp r3, #0
|
|
8003000: d004 beq.n 800300c <HAL_DMA_Start_IT+0x70>
|
|
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
|
|
8003002: 2280 movs r2, #128 @ 0x80
|
|
8003004: 6819 ldr r1, [r3, #0]
|
|
8003006: 0052 lsls r2, r2, #1
|
|
8003008: 430a orrs r2, r1
|
|
800300a: 601a str r2, [r3, #0]
|
|
__HAL_DMA_ENABLE(hdma);
|
|
800300c: 2301 movs r3, #1
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800300e: 2000 movs r0, #0
|
|
__HAL_DMA_ENABLE(hdma);
|
|
8003010: 6822 ldr r2, [r4, #0]
|
|
8003012: 4313 orrs r3, r2
|
|
8003014: 6023 str r3, [r4, #0]
|
|
__HAL_UNLOCK(hdma);
|
|
8003016: 2300 movs r3, #0
|
|
8003018: 77f3 strb r3, [r6, #31]
|
|
}
|
|
800301a: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
|
800301c: 2204 movs r2, #4
|
|
800301e: 6823 ldr r3, [r4, #0]
|
|
8003020: 4393 bics r3, r2
|
|
8003022: 6023 str r3, [r4, #0]
|
|
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
|
|
8003024: 6822 ldr r2, [r4, #0]
|
|
8003026: 230a movs r3, #10
|
|
8003028: e7dd b.n 8002fe6 <HAL_DMA_Start_IT+0x4a>
|
|
...
|
|
|
|
0800302c <HAL_DMA_Abort>:
|
|
{
|
|
800302c: b5f0 push {r4, r5, r6, r7, lr}
|
|
if (NULL == hdma)
|
|
800302e: 2800 cmp r0, #0
|
|
8003030: d008 beq.n 8003044 <HAL_DMA_Abort+0x18>
|
|
if (hdma->State != HAL_DMA_STATE_BUSY)
|
|
8003032: 1d84 adds r4, r0, #6
|
|
8003034: 7fe3 ldrb r3, [r4, #31]
|
|
8003036: 1d41 adds r1, r0, #5
|
|
8003038: 2b02 cmp r3, #2
|
|
800303a: d005 beq.n 8003048 <HAL_DMA_Abort+0x1c>
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
800303c: 2304 movs r3, #4
|
|
800303e: 63c3 str r3, [r0, #60] @ 0x3c
|
|
__HAL_UNLOCK(hdma);
|
|
8003040: 2300 movs r3, #0
|
|
8003042: 77cb strb r3, [r1, #31]
|
|
return HAL_ERROR;
|
|
8003044: 2001 movs r0, #1
|
|
}
|
|
8003046: bdf0 pop {r4, r5, r6, r7, pc}
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
8003048: 250e movs r5, #14
|
|
800304a: 6802 ldr r2, [r0, #0]
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
800304c: 6c46 ldr r6, [r0, #68] @ 0x44
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
800304e: 6813 ldr r3, [r2, #0]
|
|
8003050: 43ab bics r3, r5
|
|
8003052: 6013 str r3, [r2, #0]
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
8003054: 6833 ldr r3, [r6, #0]
|
|
8003056: 4d10 ldr r5, [pc, #64] @ (8003098 <HAL_DMA_Abort+0x6c>)
|
|
8003058: 402b ands r3, r5
|
|
800305a: 6033 str r3, [r6, #0]
|
|
__HAL_DMA_DISABLE(hdma);
|
|
800305c: 2301 movs r3, #1
|
|
800305e: 6816 ldr r6, [r2, #0]
|
|
8003060: 439e bics r6, r3
|
|
8003062: 6016 str r6, [r2, #0]
|
|
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1cU)));
|
|
8003064: 6c02 ldr r2, [r0, #64] @ 0x40
|
|
8003066: 331b adds r3, #27
|
|
8003068: 401a ands r2, r3
|
|
800306a: 3b1b subs r3, #27
|
|
800306c: 4093 lsls r3, r2
|
|
800306e: 4e0b ldr r6, [pc, #44] @ (800309c <HAL_DMA_Abort+0x70>)
|
|
8003070: 6877 ldr r7, [r6, #4]
|
|
8003072: 433b orrs r3, r7
|
|
8003074: 6073 str r3, [r6, #4]
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
8003076: 6cc2 ldr r2, [r0, #76] @ 0x4c
|
|
8003078: 6c83 ldr r3, [r0, #72] @ 0x48
|
|
800307a: 605a str r2, [r3, #4]
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
|
800307c: 6d03 ldr r3, [r0, #80] @ 0x50
|
|
800307e: 2b00 cmp r3, #0
|
|
8003080: d005 beq.n 800308e <HAL_DMA_Abort+0x62>
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
|
8003082: 681a ldr r2, [r3, #0]
|
|
8003084: 402a ands r2, r5
|
|
8003086: 601a str r2, [r3, #0]
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
8003088: 6d43 ldr r3, [r0, #84] @ 0x54
|
|
800308a: 6d82 ldr r2, [r0, #88] @ 0x58
|
|
800308c: 605a str r2, [r3, #4]
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
800308e: 2301 movs r3, #1
|
|
__HAL_UNLOCK(hdma);
|
|
8003090: 2000 movs r0, #0
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8003092: 77e3 strb r3, [r4, #31]
|
|
__HAL_UNLOCK(hdma);
|
|
8003094: 77c8 strb r0, [r1, #31]
|
|
return HAL_OK;
|
|
8003096: e7d6 b.n 8003046 <HAL_DMA_Abort+0x1a>
|
|
8003098: fffffeff .word 0xfffffeff
|
|
800309c: 40020000 .word 0x40020000
|
|
|
|
080030a0 <HAL_DMA_Abort_IT>:
|
|
{
|
|
80030a0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
__HAL_LOCK(hdma);
|
|
80030a2: 2301 movs r3, #1
|
|
80030a4: 1d41 adds r1, r0, #5
|
|
80030a6: 77cb strb r3, [r1, #31]
|
|
if (HAL_DMA_STATE_BUSY != hdma->State)
|
|
80030a8: 1d84 adds r4, r0, #6
|
|
80030aa: 7fe2 ldrb r2, [r4, #31]
|
|
80030ac: 2a02 cmp r2, #2
|
|
80030ae: d003 beq.n 80030b8 <HAL_DMA_Abort_IT+0x18>
|
|
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
|
|
80030b0: 2204 movs r2, #4
|
|
80030b2: 63c2 str r2, [r0, #60] @ 0x3c
|
|
status = HAL_ERROR;
|
|
80030b4: 0018 movs r0, r3
|
|
}
|
|
80030b6: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
80030b8: 260e movs r6, #14
|
|
80030ba: 6802 ldr r2, [r0, #0]
|
|
80030bc: 6815 ldr r5, [r2, #0]
|
|
80030be: 43b5 bics r5, r6
|
|
80030c0: 6015 str r5, [r2, #0]
|
|
__HAL_DMA_DISABLE(hdma);
|
|
80030c2: 6815 ldr r5, [r2, #0]
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
80030c4: 6c46 ldr r6, [r0, #68] @ 0x44
|
|
__HAL_DMA_DISABLE(hdma);
|
|
80030c6: 439d bics r5, r3
|
|
80030c8: 6015 str r5, [r2, #0]
|
|
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
|
|
80030ca: 6832 ldr r2, [r6, #0]
|
|
80030cc: 4d11 ldr r5, [pc, #68] @ (8003114 <HAL_DMA_Abort_IT+0x74>)
|
|
80030ce: 402a ands r2, r5
|
|
80030d0: 6032 str r2, [r6, #0]
|
|
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1cU)));
|
|
80030d2: 6c02 ldr r2, [r0, #64] @ 0x40
|
|
80030d4: 4e10 ldr r6, [pc, #64] @ (8003118 <HAL_DMA_Abort_IT+0x78>)
|
|
80030d6: 0015 movs r5, r2
|
|
80030d8: 221c movs r2, #28
|
|
80030da: 4015 ands r5, r2
|
|
80030dc: 40ab lsls r3, r5
|
|
80030de: 6877 ldr r7, [r6, #4]
|
|
80030e0: 433b orrs r3, r7
|
|
80030e2: 6073 str r3, [r6, #4]
|
|
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
|
|
80030e4: 6cc2 ldr r2, [r0, #76] @ 0x4c
|
|
80030e6: 6c83 ldr r3, [r0, #72] @ 0x48
|
|
80030e8: 605a str r2, [r3, #4]
|
|
if (hdma->DMAmuxRequestGen != 0U)
|
|
80030ea: 6d03 ldr r3, [r0, #80] @ 0x50
|
|
80030ec: 2b00 cmp r3, #0
|
|
80030ee: d006 beq.n 80030fe <HAL_DMA_Abort_IT+0x5e>
|
|
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
|
|
80030f0: 681a ldr r2, [r3, #0]
|
|
80030f2: 4d08 ldr r5, [pc, #32] @ (8003114 <HAL_DMA_Abort_IT+0x74>)
|
|
80030f4: 402a ands r2, r5
|
|
80030f6: 601a str r2, [r3, #0]
|
|
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
|
|
80030f8: 6d43 ldr r3, [r0, #84] @ 0x54
|
|
80030fa: 6d82 ldr r2, [r0, #88] @ 0x58
|
|
80030fc: 605a str r2, [r3, #4]
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80030fe: 2301 movs r3, #1
|
|
8003100: 77e3 strb r3, [r4, #31]
|
|
__HAL_UNLOCK(hdma);
|
|
8003102: 2300 movs r3, #0
|
|
8003104: 77cb strb r3, [r1, #31]
|
|
if (hdma->XferAbortCallback != NULL)
|
|
8003106: 6b83 ldr r3, [r0, #56] @ 0x38
|
|
8003108: 2b00 cmp r3, #0
|
|
800310a: d000 beq.n 800310e <HAL_DMA_Abort_IT+0x6e>
|
|
hdma->XferAbortCallback(hdma);
|
|
800310c: 4798 blx r3
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800310e: 2000 movs r0, #0
|
|
8003110: e7d1 b.n 80030b6 <HAL_DMA_Abort_IT+0x16>
|
|
8003112: 46c0 nop @ (mov r8, r8)
|
|
8003114: fffffeff .word 0xfffffeff
|
|
8003118: 40020000 .word 0x40020000
|
|
|
|
0800311c <HAL_DMA_IRQHandler>:
|
|
{
|
|
800311c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
|
|
800311e: 241c movs r4, #28
|
|
8003120: 2704 movs r7, #4
|
|
8003122: 6c01 ldr r1, [r0, #64] @ 0x40
|
|
uint32_t flag_it = DMA1->ISR;
|
|
8003124: 4a26 ldr r2, [pc, #152] @ (80031c0 <HAL_DMA_IRQHandler+0xa4>)
|
|
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
|
|
8003126: 4021 ands r1, r4
|
|
8003128: 003c movs r4, r7
|
|
800312a: 408c lsls r4, r1
|
|
uint32_t flag_it = DMA1->ISR;
|
|
800312c: 6816 ldr r6, [r2, #0]
|
|
uint32_t source_it = hdma->Instance->CCR;
|
|
800312e: 6803 ldr r3, [r0, #0]
|
|
8003130: 681d ldr r5, [r3, #0]
|
|
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
|
|
8003132: 4226 tst r6, r4
|
|
8003134: d00f beq.n 8003156 <HAL_DMA_IRQHandler+0x3a>
|
|
8003136: 423d tst r5, r7
|
|
8003138: d00d beq.n 8003156 <HAL_DMA_IRQHandler+0x3a>
|
|
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
|
800313a: 6819 ldr r1, [r3, #0]
|
|
800313c: 0689 lsls r1, r1, #26
|
|
800313e: d402 bmi.n 8003146 <HAL_DMA_IRQHandler+0x2a>
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
|
|
8003140: 6819 ldr r1, [r3, #0]
|
|
8003142: 43b9 bics r1, r7
|
|
8003144: 6019 str r1, [r3, #0]
|
|
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)));
|
|
8003146: 6853 ldr r3, [r2, #4]
|
|
8003148: 431c orrs r4, r3
|
|
if (hdma->XferHalfCpltCallback != NULL)
|
|
800314a: 6b03 ldr r3, [r0, #48] @ 0x30
|
|
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)));
|
|
800314c: 6054 str r4, [r2, #4]
|
|
if (hdma->XferHalfCpltCallback != NULL)
|
|
800314e: 2b00 cmp r3, #0
|
|
8003150: d01b beq.n 800318a <HAL_DMA_IRQHandler+0x6e>
|
|
hdma->XferErrorCallback(hdma);
|
|
8003152: 4798 blx r3
|
|
return;
|
|
8003154: e019 b.n 800318a <HAL_DMA_IRQHandler+0x6e>
|
|
else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC)))
|
|
8003156: 2702 movs r7, #2
|
|
8003158: 003c movs r4, r7
|
|
800315a: 408c lsls r4, r1
|
|
800315c: 4226 tst r6, r4
|
|
800315e: d015 beq.n 800318c <HAL_DMA_IRQHandler+0x70>
|
|
8003160: 423d tst r5, r7
|
|
8003162: d013 beq.n 800318c <HAL_DMA_IRQHandler+0x70>
|
|
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
|
|
8003164: 6819 ldr r1, [r3, #0]
|
|
8003166: 0689 lsls r1, r1, #26
|
|
8003168: d406 bmi.n 8003178 <HAL_DMA_IRQHandler+0x5c>
|
|
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
|
|
800316a: 250a movs r5, #10
|
|
800316c: 6819 ldr r1, [r3, #0]
|
|
800316e: 43a9 bics r1, r5
|
|
8003170: 6019 str r1, [r3, #0]
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
8003172: 2101 movs r1, #1
|
|
8003174: 1d83 adds r3, r0, #6
|
|
8003176: 77d9 strb r1, [r3, #31]
|
|
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)));
|
|
8003178: 6853 ldr r3, [r2, #4]
|
|
800317a: 431c orrs r4, r3
|
|
800317c: 6054 str r4, [r2, #4]
|
|
__HAL_UNLOCK(hdma);
|
|
800317e: 2200 movs r2, #0
|
|
8003180: 1d43 adds r3, r0, #5
|
|
8003182: 77da strb r2, [r3, #31]
|
|
if (hdma->XferCpltCallback != NULL)
|
|
8003184: 6ac3 ldr r3, [r0, #44] @ 0x2c
|
|
if (hdma->XferErrorCallback != NULL)
|
|
8003186: 4293 cmp r3, r2
|
|
8003188: d1e3 bne.n 8003152 <HAL_DMA_IRQHandler+0x36>
|
|
}
|
|
800318a: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
|
|
800318c: 2408 movs r4, #8
|
|
800318e: 0027 movs r7, r4
|
|
8003190: 408f lsls r7, r1
|
|
8003192: 423e tst r6, r7
|
|
8003194: d0f9 beq.n 800318a <HAL_DMA_IRQHandler+0x6e>
|
|
8003196: 4225 tst r5, r4
|
|
8003198: d0f7 beq.n 800318a <HAL_DMA_IRQHandler+0x6e>
|
|
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
|
|
800319a: 250e movs r5, #14
|
|
800319c: 681c ldr r4, [r3, #0]
|
|
800319e: 43ac bics r4, r5
|
|
80031a0: 601c str r4, [r3, #0]
|
|
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU)));
|
|
80031a2: 2301 movs r3, #1
|
|
80031a4: 001d movs r5, r3
|
|
80031a6: 408d lsls r5, r1
|
|
80031a8: 0029 movs r1, r5
|
|
80031aa: 6854 ldr r4, [r2, #4]
|
|
80031ac: 4321 orrs r1, r4
|
|
80031ae: 6051 str r1, [r2, #4]
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80031b0: 1d82 adds r2, r0, #6
|
|
hdma->ErrorCode = HAL_DMA_ERROR_TE;
|
|
80031b2: 63c3 str r3, [r0, #60] @ 0x3c
|
|
hdma->State = HAL_DMA_STATE_READY;
|
|
80031b4: 77d3 strb r3, [r2, #31]
|
|
__HAL_UNLOCK(hdma);
|
|
80031b6: 2200 movs r2, #0
|
|
80031b8: 1d43 adds r3, r0, #5
|
|
80031ba: 77da strb r2, [r3, #31]
|
|
if (hdma->XferErrorCallback != NULL)
|
|
80031bc: 6b43 ldr r3, [r0, #52] @ 0x34
|
|
80031be: e7e2 b.n 8003186 <HAL_DMA_IRQHandler+0x6a>
|
|
80031c0: 40020000 .word 0x40020000
|
|
|
|
080031c4 <HAL_DMA_GetError>:
|
|
return hdma->ErrorCode;
|
|
80031c4: 6bc0 ldr r0, [r0, #60] @ 0x3c
|
|
}
|
|
80031c6: 4770 bx lr
|
|
|
|
080031c8 <HAL_GPIO_Init>:
|
|
*/
|
|
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
|
|
{
|
|
uint32_t tmp;
|
|
uint32_t iocurrent;
|
|
uint32_t position = 0U;
|
|
80031c8: 2300 movs r3, #0
|
|
80031ca: 469c mov ip, r3
|
|
{
|
|
80031cc: b5f0 push {r4, r5, r6, r7, lr}
|
|
80031ce: b085 sub sp, #20
|
|
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
|
|
assert_param(IS_GPIO_PIN(pGPIO_Init->Pin));
|
|
assert_param(IS_GPIO_MODE(pGPIO_Init->Mode));
|
|
|
|
/* Configure the port pins */
|
|
while (((pGPIO_Init->Pin) >> position) != 0U)
|
|
80031d0: 680b ldr r3, [r1, #0]
|
|
80031d2: 4664 mov r4, ip
|
|
80031d4: 001a movs r2, r3
|
|
80031d6: 40e2 lsrs r2, r4
|
|
80031d8: d101 bne.n 80031de <HAL_GPIO_Init+0x16>
|
|
}
|
|
}
|
|
|
|
position++;
|
|
}
|
|
}
|
|
80031da: b005 add sp, #20
|
|
80031dc: bdf0 pop {r4, r5, r6, r7, pc}
|
|
iocurrent = (pGPIO_Init->Pin) & (1UL << position);
|
|
80031de: 4662 mov r2, ip
|
|
80031e0: 2601 movs r6, #1
|
|
80031e2: 4096 lsls r6, r2
|
|
80031e4: 001a movs r2, r3
|
|
80031e6: 4032 ands r2, r6
|
|
80031e8: 9201 str r2, [sp, #4]
|
|
if (iocurrent != 0U)
|
|
80031ea: 4233 tst r3, r6
|
|
80031ec: d100 bne.n 80031f0 <HAL_GPIO_Init+0x28>
|
|
80031ee: e084 b.n 80032fa <HAL_GPIO_Init+0x132>
|
|
if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD))
|
|
80031f0: 684f ldr r7, [r1, #4]
|
|
80031f2: 2310 movs r3, #16
|
|
80031f4: 003d movs r5, r7
|
|
80031f6: 439d bics r5, r3
|
|
80031f8: 9503 str r5, [sp, #12]
|
|
80031fa: 2d02 cmp r5, #2
|
|
80031fc: d114 bne.n 8003228 <HAL_GPIO_Init+0x60>
|
|
tmp = GPIOx->AFR[position >> 3U];
|
|
80031fe: 4663 mov r3, ip
|
|
8003200: 08da lsrs r2, r3, #3
|
|
8003202: 0092 lsls r2, r2, #2
|
|
8003204: 1882 adds r2, r0, r2
|
|
8003206: 6a13 ldr r3, [r2, #32]
|
|
tmp &= ~(0xFUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ;
|
|
8003208: 2407 movs r4, #7
|
|
tmp = GPIOx->AFR[position >> 3U];
|
|
800320a: 001d movs r5, r3
|
|
tmp &= ~(0xFUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ;
|
|
800320c: 4663 mov r3, ip
|
|
800320e: 401c ands r4, r3
|
|
8003210: 230f movs r3, #15
|
|
8003212: 00a4 lsls r4, r4, #2
|
|
8003214: 40a3 lsls r3, r4
|
|
8003216: 439d bics r5, r3
|
|
8003218: 9502 str r5, [sp, #8]
|
|
tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos));
|
|
800321a: 250f movs r5, #15
|
|
800321c: 690b ldr r3, [r1, #16]
|
|
800321e: 402b ands r3, r5
|
|
8003220: 40a3 lsls r3, r4
|
|
8003222: 9c02 ldr r4, [sp, #8]
|
|
8003224: 4323 orrs r3, r4
|
|
GPIOx->AFR[position >> 3U] = tmp;
|
|
8003226: 6213 str r3, [r2, #32]
|
|
tmp = GPIOx->MODER;
|
|
8003228: 4663 mov r3, ip
|
|
800322a: 005a lsls r2, r3, #1
|
|
tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
|
|
800322c: 2303 movs r3, #3
|
|
800322e: 4093 lsls r3, r2
|
|
tmp = GPIOx->MODER;
|
|
8003230: 6804 ldr r4, [r0, #0]
|
|
tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
|
|
8003232: 43dd mvns r5, r3
|
|
8003234: 439c bics r4, r3
|
|
tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos));
|
|
8003236: 2303 movs r3, #3
|
|
8003238: 403b ands r3, r7
|
|
800323a: 4093 lsls r3, r2
|
|
tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
|
|
800323c: 9502 str r5, [sp, #8]
|
|
if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
|
800323e: 9d03 ldr r5, [sp, #12]
|
|
tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos));
|
|
8003240: 4323 orrs r3, r4
|
|
if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
|
8003242: 3d01 subs r5, #1
|
|
GPIOx->MODER = tmp;
|
|
8003244: 6003 str r3, [r0, #0]
|
|
if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
|
|
8003246: 2d01 cmp r5, #1
|
|
8003248: d95a bls.n 8003300 <HAL_GPIO_Init+0x138>
|
|
if (pGPIO_Init->Mode != GPIO_MODE_ANALOG)
|
|
800324a: 2f03 cmp r7, #3
|
|
800324c: d055 beq.n 80032fa <HAL_GPIO_Init+0x132>
|
|
tmp = GPIOx->PUPDR;
|
|
800324e: 68c4 ldr r4, [r0, #12]
|
|
tmp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos));
|
|
8003250: 9b02 ldr r3, [sp, #8]
|
|
8003252: 401c ands r4, r3
|
|
tmp |= ((pGPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos));
|
|
8003254: 688b ldr r3, [r1, #8]
|
|
8003256: 4093 lsls r3, r2
|
|
8003258: 4323 orrs r3, r4
|
|
GPIOx->PUPDR = tmp;
|
|
800325a: 60c3 str r3, [r0, #12]
|
|
if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
|
|
800325c: 2380 movs r3, #128 @ 0x80
|
|
800325e: 055b lsls r3, r3, #21
|
|
8003260: 421f tst r7, r3
|
|
8003262: d04a beq.n 80032fa <HAL_GPIO_Init+0x132>
|
|
tmp = EXTI->EXTICR[position >> 2U];
|
|
8003264: 4663 mov r3, ip
|
|
8003266: 089a lsrs r2, r3, #2
|
|
8003268: 4b2d ldr r3, [pc, #180] @ (8003320 <HAL_GPIO_Init+0x158>)
|
|
800326a: 0092 lsls r2, r2, #2
|
|
800326c: 18d2 adds r2, r2, r3
|
|
tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
|
|
800326e: 2403 movs r4, #3
|
|
8003270: 4663 mov r3, ip
|
|
8003272: 401c ands r4, r3
|
|
8003274: 230f movs r3, #15
|
|
8003276: 00e4 lsls r4, r4, #3
|
|
8003278: 40a3 lsls r3, r4
|
|
tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
|
|
800327a: 26a0 movs r6, #160 @ 0xa0
|
|
tmp = EXTI->EXTICR[position >> 2U];
|
|
800327c: 6e15 ldr r5, [r2, #96] @ 0x60
|
|
tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
|
|
800327e: 05f6 lsls r6, r6, #23
|
|
tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
|
|
8003280: 439d bics r5, r3
|
|
tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
|
|
8003282: 2300 movs r3, #0
|
|
8003284: 42b0 cmp r0, r6
|
|
8003286: d010 beq.n 80032aa <HAL_GPIO_Init+0xe2>
|
|
8003288: 4e26 ldr r6, [pc, #152] @ (8003324 <HAL_GPIO_Init+0x15c>)
|
|
800328a: 3301 adds r3, #1
|
|
800328c: 42b0 cmp r0, r6
|
|
800328e: d00c beq.n 80032aa <HAL_GPIO_Init+0xe2>
|
|
8003290: 4e25 ldr r6, [pc, #148] @ (8003328 <HAL_GPIO_Init+0x160>)
|
|
8003292: 3301 adds r3, #1
|
|
8003294: 42b0 cmp r0, r6
|
|
8003296: d008 beq.n 80032aa <HAL_GPIO_Init+0xe2>
|
|
8003298: 4e24 ldr r6, [pc, #144] @ (800332c <HAL_GPIO_Init+0x164>)
|
|
800329a: 3301 adds r3, #1
|
|
800329c: 42b0 cmp r0, r6
|
|
800329e: d004 beq.n 80032aa <HAL_GPIO_Init+0xe2>
|
|
80032a0: 4b23 ldr r3, [pc, #140] @ (8003330 <HAL_GPIO_Init+0x168>)
|
|
80032a2: 18c3 adds r3, r0, r3
|
|
80032a4: 1e5e subs r6, r3, #1
|
|
80032a6: 41b3 sbcs r3, r6
|
|
80032a8: 3305 adds r3, #5
|
|
80032aa: 40a3 lsls r3, r4
|
|
80032ac: 432b orrs r3, r5
|
|
EXTI->EXTICR[position >> 2U] = tmp;
|
|
80032ae: 6613 str r3, [r2, #96] @ 0x60
|
|
tmp = EXTI->IMR1;
|
|
80032b0: 4b20 ldr r3, [pc, #128] @ (8003334 <HAL_GPIO_Init+0x16c>)
|
|
tmp &= ~((uint32_t)iocurrent);
|
|
80032b2: 9a01 ldr r2, [sp, #4]
|
|
tmp = EXTI->IMR1;
|
|
80032b4: 6fdd ldr r5, [r3, #124] @ 0x7c
|
|
tmp |= iocurrent;
|
|
80032b6: 9c01 ldr r4, [sp, #4]
|
|
tmp &= ~((uint32_t)iocurrent);
|
|
80032b8: 43d2 mvns r2, r2
|
|
tmp |= iocurrent;
|
|
80032ba: 432c orrs r4, r5
|
|
if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
|
|
80032bc: 03fe lsls r6, r7, #15
|
|
80032be: d401 bmi.n 80032c4 <HAL_GPIO_Init+0xfc>
|
|
tmp &= ~((uint32_t)iocurrent);
|
|
80032c0: 002c movs r4, r5
|
|
80032c2: 4014 ands r4, r2
|
|
EXTI->IMR1 = tmp;
|
|
80032c4: 67dc str r4, [r3, #124] @ 0x7c
|
|
tmp = EXTI->EMR1;
|
|
80032c6: 4c1c ldr r4, [pc, #112] @ (8003338 <HAL_GPIO_Init+0x170>)
|
|
tmp |= iocurrent;
|
|
80032c8: 9d01 ldr r5, [sp, #4]
|
|
tmp = EXTI->EMR1;
|
|
80032ca: 6fe3 ldr r3, [r4, #124] @ 0x7c
|
|
tmp |= iocurrent;
|
|
80032cc: 431d orrs r5, r3
|
|
if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
|
|
80032ce: 03be lsls r6, r7, #14
|
|
80032d0: d401 bmi.n 80032d6 <HAL_GPIO_Init+0x10e>
|
|
tmp &= ~((uint32_t)iocurrent);
|
|
80032d2: 4013 ands r3, r2
|
|
80032d4: 001d movs r5, r3
|
|
EXTI->EMR1 = tmp;
|
|
80032d6: 4b12 ldr r3, [pc, #72] @ (8003320 <HAL_GPIO_Init+0x158>)
|
|
80032d8: 67e5 str r5, [r4, #124] @ 0x7c
|
|
tmp = EXTI->RTSR1;
|
|
80032da: 681d ldr r5, [r3, #0]
|
|
tmp |= iocurrent;
|
|
80032dc: 9c01 ldr r4, [sp, #4]
|
|
80032de: 432c orrs r4, r5
|
|
if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
|
|
80032e0: 02fe lsls r6, r7, #11
|
|
80032e2: d401 bmi.n 80032e8 <HAL_GPIO_Init+0x120>
|
|
tmp &= ~((uint32_t)iocurrent);
|
|
80032e4: 002c movs r4, r5
|
|
80032e6: 4014 ands r4, r2
|
|
EXTI->RTSR1 = tmp;
|
|
80032e8: 601c str r4, [r3, #0]
|
|
tmp = EXTI->FTSR1;
|
|
80032ea: 685c ldr r4, [r3, #4]
|
|
tmp |= iocurrent;
|
|
80032ec: 9d01 ldr r5, [sp, #4]
|
|
80032ee: 4325 orrs r5, r4
|
|
if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
|
|
80032f0: 02bf lsls r7, r7, #10
|
|
80032f2: d401 bmi.n 80032f8 <HAL_GPIO_Init+0x130>
|
|
tmp &= ~((uint32_t)iocurrent);
|
|
80032f4: 4014 ands r4, r2
|
|
80032f6: 0025 movs r5, r4
|
|
EXTI->FTSR1 = tmp;
|
|
80032f8: 605d str r5, [r3, #4]
|
|
position++;
|
|
80032fa: 2301 movs r3, #1
|
|
80032fc: 449c add ip, r3
|
|
80032fe: e767 b.n 80031d0 <HAL_GPIO_Init+0x8>
|
|
tmp = GPIOx->OSPEEDR;
|
|
8003300: 6884 ldr r4, [r0, #8]
|
|
tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
|
|
8003302: 9b02 ldr r3, [sp, #8]
|
|
tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
|
|
8003304: 4665 mov r5, ip
|
|
tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
|
|
8003306: 401c ands r4, r3
|
|
tmp |= (pGPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos));
|
|
8003308: 68cb ldr r3, [r1, #12]
|
|
800330a: 4093 lsls r3, r2
|
|
800330c: 4323 orrs r3, r4
|
|
GPIOx->OSPEEDR = tmp;
|
|
800330e: 6083 str r3, [r0, #8]
|
|
tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
|
|
8003310: 093b lsrs r3, r7, #4
|
|
8003312: 40ab lsls r3, r5
|
|
tmp = GPIOx->OTYPER;
|
|
8003314: 6844 ldr r4, [r0, #4]
|
|
tmp &= ~(GPIO_OTYPER_OT0 << position) ;
|
|
8003316: 43b4 bics r4, r6
|
|
tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
|
|
8003318: 4323 orrs r3, r4
|
|
GPIOx->OTYPER = tmp;
|
|
800331a: 6043 str r3, [r0, #4]
|
|
if (pGPIO_Init->Mode != GPIO_MODE_ANALOG)
|
|
800331c: e797 b.n 800324e <HAL_GPIO_Init+0x86>
|
|
800331e: 46c0 nop @ (mov r8, r8)
|
|
8003320: 40021800 .word 0x40021800
|
|
8003324: 50000400 .word 0x50000400
|
|
8003328: 50000800 .word 0x50000800
|
|
800332c: 50000c00 .word 0x50000c00
|
|
8003330: afffec00 .word 0xafffec00
|
|
8003334: 40021804 .word 0x40021804
|
|
8003338: 40021808 .word 0x40021808
|
|
|
|
0800333c <HAL_GPIO_ReadPin>:
|
|
GPIO_PinState bitstatus;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
|
|
if ((GPIOx->IDR & GPIO_Pin) != 0U)
|
|
800333c: 6900 ldr r0, [r0, #16]
|
|
800333e: 4008 ands r0, r1
|
|
8003340: 1e43 subs r3, r0, #1
|
|
8003342: 4198 sbcs r0, r3
|
|
}
|
|
else
|
|
{
|
|
bitstatus = GPIO_PIN_RESET;
|
|
}
|
|
return bitstatus;
|
|
8003344: b2c0 uxtb r0, r0
|
|
}
|
|
8003346: 4770 bx lr
|
|
|
|
08003348 <HAL_GPIO_WritePin>:
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_GPIO_PIN(GPIO_Pin));
|
|
assert_param(IS_GPIO_PIN_ACTION(PinState));
|
|
|
|
if (PinState != GPIO_PIN_RESET)
|
|
8003348: 2a00 cmp r2, #0
|
|
800334a: d001 beq.n 8003350 <HAL_GPIO_WritePin+0x8>
|
|
{
|
|
GPIOx->BSRR = (uint32_t)GPIO_Pin;
|
|
800334c: 6181 str r1, [r0, #24]
|
|
}
|
|
else
|
|
{
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
}
|
|
}
|
|
800334e: 4770 bx lr
|
|
GPIOx->BRR = (uint32_t)GPIO_Pin;
|
|
8003350: 6281 str r1, [r0, #40] @ 0x28
|
|
}
|
|
8003352: e7fc b.n 800334e <HAL_GPIO_WritePin+0x6>
|
|
|
|
08003354 <HAL_GPIO_EXTI_Rising_Callback>:
|
|
UNUSED(GPIO_Pin);
|
|
|
|
/* NOTE: This function should not be modified, when the callback is needed,
|
|
the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file
|
|
*/
|
|
}
|
|
8003354: 4770 bx lr
|
|
...
|
|
|
|
08003358 <HAL_GPIO_EXTI_IRQHandler>:
|
|
{
|
|
8003358: b570 push {r4, r5, r6, lr}
|
|
if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U)
|
|
800335a: 4d08 ldr r5, [pc, #32] @ (800337c <HAL_GPIO_EXTI_IRQHandler+0x24>)
|
|
{
|
|
800335c: 0004 movs r4, r0
|
|
if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U)
|
|
800335e: 68eb ldr r3, [r5, #12]
|
|
8003360: 4218 tst r0, r3
|
|
8003362: d002 beq.n 800336a <HAL_GPIO_EXTI_IRQHandler+0x12>
|
|
__HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
|
|
8003364: 60e8 str r0, [r5, #12]
|
|
HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
|
|
8003366: f7ff fff5 bl 8003354 <HAL_GPIO_EXTI_Rising_Callback>
|
|
if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U)
|
|
800336a: 692b ldr r3, [r5, #16]
|
|
800336c: 4223 tst r3, r4
|
|
800336e: d003 beq.n 8003378 <HAL_GPIO_EXTI_IRQHandler+0x20>
|
|
HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
|
|
8003370: 0020 movs r0, r4
|
|
__HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
|
|
8003372: 612c str r4, [r5, #16]
|
|
HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
|
|
8003374: f7fd fb14 bl 80009a0 <HAL_GPIO_EXTI_Falling_Callback>
|
|
}
|
|
8003378: bd70 pop {r4, r5, r6, pc}
|
|
800337a: 46c0 nop @ (mov r8, r8)
|
|
800337c: 40021800 .word 0x40021800
|
|
|
|
08003380 <HAL_RCC_OscConfig>:
|
|
must adjust the number of CPU wait states in their application (SystemClock_Config() API)
|
|
before calling the HAL_RCC_OscConfig() API to update the HSI48 clock division factor.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
|
|
{
|
|
8003380: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8003382: 1e05 subs r5, r0, #0
|
|
uint32_t tickstart;
|
|
uint32_t temp_sysclksrc;
|
|
|
|
/* Check Null pointer */
|
|
if (RCC_OscInitStruct == NULL)
|
|
8003384: d101 bne.n 800338a <HAL_RCC_OscConfig+0xa>
|
|
{
|
|
return HAL_ERROR;
|
|
8003386: 2001 movs r0, #1
|
|
}
|
|
}
|
|
}
|
|
#endif /* RCC_CR_HSIUSB48ON */
|
|
return HAL_OK;
|
|
}
|
|
8003388: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
|
|
800338a: 6803 ldr r3, [r0, #0]
|
|
800338c: 07db lsls r3, r3, #31
|
|
800338e: d40d bmi.n 80033ac <HAL_RCC_OscConfig+0x2c>
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
|
|
8003390: 682b ldr r3, [r5, #0]
|
|
8003392: 079b lsls r3, r3, #30
|
|
8003394: d44f bmi.n 8003436 <HAL_RCC_OscConfig+0xb6>
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
|
|
8003396: 682b ldr r3, [r5, #0]
|
|
8003398: 071b lsls r3, r3, #28
|
|
800339a: d500 bpl.n 800339e <HAL_RCC_OscConfig+0x1e>
|
|
800339c: e0a4 b.n 80034e8 <HAL_RCC_OscConfig+0x168>
|
|
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
|
|
800339e: 2204 movs r2, #4
|
|
80033a0: 682b ldr r3, [r5, #0]
|
|
80033a2: 4213 tst r3, r2
|
|
80033a4: d000 beq.n 80033a8 <HAL_RCC_OscConfig+0x28>
|
|
80033a6: e0cf b.n 8003548 <HAL_RCC_OscConfig+0x1c8>
|
|
return HAL_OK;
|
|
80033a8: 2000 movs r0, #0
|
|
80033aa: e7ed b.n 8003388 <HAL_RCC_OscConfig+0x8>
|
|
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
80033ac: 2138 movs r1, #56 @ 0x38
|
|
80033ae: 4c85 ldr r4, [pc, #532] @ (80035c4 <HAL_RCC_OscConfig+0x244>)
|
|
if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)
|
|
80033b0: 6843 ldr r3, [r0, #4]
|
|
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
80033b2: 68a2 ldr r2, [r4, #8]
|
|
80033b4: 400a ands r2, r1
|
|
if (temp_sysclksrc == RCC_CFGR_SWS_HSE)
|
|
80033b6: 2a08 cmp r2, #8
|
|
80033b8: d102 bne.n 80033c0 <HAL_RCC_OscConfig+0x40>
|
|
if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)
|
|
80033ba: 2b00 cmp r3, #0
|
|
80033bc: d1e8 bne.n 8003390 <HAL_RCC_OscConfig+0x10>
|
|
80033be: e7e2 b.n 8003386 <HAL_RCC_OscConfig+0x6>
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
80033c0: 2280 movs r2, #128 @ 0x80
|
|
80033c2: 0252 lsls r2, r2, #9
|
|
80033c4: 4293 cmp r3, r2
|
|
80033c6: d111 bne.n 80033ec <HAL_RCC_OscConfig+0x6c>
|
|
80033c8: 6822 ldr r2, [r4, #0]
|
|
80033ca: 4313 orrs r3, r2
|
|
80033cc: 6023 str r3, [r4, #0]
|
|
tickstart = HAL_GetTick();
|
|
80033ce: f7ff fa9f bl 8002910 <HAL_GetTick>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
80033d2: 2780 movs r7, #128 @ 0x80
|
|
tickstart = HAL_GetTick();
|
|
80033d4: 0006 movs r6, r0
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
80033d6: 02bf lsls r7, r7, #10
|
|
80033d8: 6823 ldr r3, [r4, #0]
|
|
80033da: 423b tst r3, r7
|
|
80033dc: d1d8 bne.n 8003390 <HAL_RCC_OscConfig+0x10>
|
|
if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
|
|
80033de: f7ff fa97 bl 8002910 <HAL_GetTick>
|
|
80033e2: 1b80 subs r0, r0, r6
|
|
80033e4: 2864 cmp r0, #100 @ 0x64
|
|
80033e6: d9f7 bls.n 80033d8 <HAL_RCC_OscConfig+0x58>
|
|
return HAL_TIMEOUT;
|
|
80033e8: 2003 movs r0, #3
|
|
80033ea: e7cd b.n 8003388 <HAL_RCC_OscConfig+0x8>
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
80033ec: 21a0 movs r1, #160 @ 0xa0
|
|
80033ee: 02c9 lsls r1, r1, #11
|
|
80033f0: 428b cmp r3, r1
|
|
80033f2: d108 bne.n 8003406 <HAL_RCC_OscConfig+0x86>
|
|
80033f4: 2380 movs r3, #128 @ 0x80
|
|
80033f6: 6821 ldr r1, [r4, #0]
|
|
80033f8: 02db lsls r3, r3, #11
|
|
80033fa: 430b orrs r3, r1
|
|
80033fc: 6023 str r3, [r4, #0]
|
|
80033fe: 6823 ldr r3, [r4, #0]
|
|
8003400: 431a orrs r2, r3
|
|
8003402: 6022 str r2, [r4, #0]
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8003404: e7e3 b.n 80033ce <HAL_RCC_OscConfig+0x4e>
|
|
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
|
|
8003406: 6822 ldr r2, [r4, #0]
|
|
8003408: 496f ldr r1, [pc, #444] @ (80035c8 <HAL_RCC_OscConfig+0x248>)
|
|
800340a: 400a ands r2, r1
|
|
800340c: 6022 str r2, [r4, #0]
|
|
800340e: 6822 ldr r2, [r4, #0]
|
|
8003410: 496e ldr r1, [pc, #440] @ (80035cc <HAL_RCC_OscConfig+0x24c>)
|
|
8003412: 400a ands r2, r1
|
|
8003414: 6022 str r2, [r4, #0]
|
|
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
|
|
8003416: 2b00 cmp r3, #0
|
|
8003418: d1d9 bne.n 80033ce <HAL_RCC_OscConfig+0x4e>
|
|
tickstart = HAL_GetTick();
|
|
800341a: f7ff fa79 bl 8002910 <HAL_GetTick>
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
800341e: 2780 movs r7, #128 @ 0x80
|
|
tickstart = HAL_GetTick();
|
|
8003420: 0006 movs r6, r0
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
|
|
8003422: 02bf lsls r7, r7, #10
|
|
8003424: 6823 ldr r3, [r4, #0]
|
|
8003426: 423b tst r3, r7
|
|
8003428: d0b2 beq.n 8003390 <HAL_RCC_OscConfig+0x10>
|
|
if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
|
|
800342a: f7ff fa71 bl 8002910 <HAL_GetTick>
|
|
800342e: 1b80 subs r0, r0, r6
|
|
8003430: 2864 cmp r0, #100 @ 0x64
|
|
8003432: d9f7 bls.n 8003424 <HAL_RCC_OscConfig+0xa4>
|
|
8003434: e7d8 b.n 80033e8 <HAL_RCC_OscConfig+0x68>
|
|
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
8003436: 2238 movs r2, #56 @ 0x38
|
|
8003438: 4c62 ldr r4, [pc, #392] @ (80035c4 <HAL_RCC_OscConfig+0x244>)
|
|
if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
|
|
800343a: 68eb ldr r3, [r5, #12]
|
|
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
|
|
800343c: 68a1 ldr r1, [r4, #8]
|
|
if (temp_sysclksrc == RCC_CFGR_SWS_HSI)
|
|
800343e: 4211 tst r1, r2
|
|
8003440: d11c bne.n 800347c <HAL_RCC_OscConfig+0xfc>
|
|
if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
|
|
8003442: 2b00 cmp r3, #0
|
|
8003444: d09f beq.n 8003386 <HAL_RCC_OscConfig+0x6>
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
8003446: 6862 ldr r2, [r4, #4]
|
|
8003448: 696b ldr r3, [r5, #20]
|
|
800344a: 4961 ldr r1, [pc, #388] @ (80035d0 <HAL_RCC_OscConfig+0x250>)
|
|
800344c: 021b lsls r3, r3, #8
|
|
800344e: 400a ands r2, r1
|
|
8003450: 4313 orrs r3, r2
|
|
8003452: 6063 str r3, [r4, #4]
|
|
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
|
|
8003454: 6823 ldr r3, [r4, #0]
|
|
8003456: 4a5f ldr r2, [pc, #380] @ (80035d4 <HAL_RCC_OscConfig+0x254>)
|
|
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
|
|
8003458: 495f ldr r1, [pc, #380] @ (80035d8 <HAL_RCC_OscConfig+0x258>)
|
|
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
|
|
800345a: 4013 ands r3, r2
|
|
800345c: 692a ldr r2, [r5, #16]
|
|
800345e: 4313 orrs r3, r2
|
|
8003460: 6023 str r3, [r4, #0]
|
|
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
|
|
8003462: 6823 ldr r3, [r4, #0]
|
|
8003464: 4a5d ldr r2, [pc, #372] @ (80035dc <HAL_RCC_OscConfig+0x25c>)
|
|
8003466: 049b lsls r3, r3, #18
|
|
8003468: 0f5b lsrs r3, r3, #29
|
|
800346a: 40da lsrs r2, r3
|
|
if (HAL_InitTick(uwTickPrio) != HAL_OK)
|
|
800346c: 4b5c ldr r3, [pc, #368] @ (80035e0 <HAL_RCC_OscConfig+0x260>)
|
|
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
|
|
800346e: 600a str r2, [r1, #0]
|
|
if (HAL_InitTick(uwTickPrio) != HAL_OK)
|
|
8003470: 6818 ldr r0, [r3, #0]
|
|
8003472: f7ff fa0d bl 8002890 <HAL_InitTick>
|
|
8003476: 2800 cmp r0, #0
|
|
8003478: d08d beq.n 8003396 <HAL_RCC_OscConfig+0x16>
|
|
800347a: e784 b.n 8003386 <HAL_RCC_OscConfig+0x6>
|
|
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
|
|
800347c: 2b00 cmp r3, #0
|
|
800347e: d020 beq.n 80034c2 <HAL_RCC_OscConfig+0x142>
|
|
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
|
|
8003480: 6823 ldr r3, [r4, #0]
|
|
8003482: 4a54 ldr r2, [pc, #336] @ (80035d4 <HAL_RCC_OscConfig+0x254>)
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
8003484: 2780 movs r7, #128 @ 0x80
|
|
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
|
|
8003486: 4013 ands r3, r2
|
|
8003488: 692a ldr r2, [r5, #16]
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
800348a: 00ff lsls r7, r7, #3
|
|
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
|
|
800348c: 4313 orrs r3, r2
|
|
800348e: 6023 str r3, [r4, #0]
|
|
__HAL_RCC_HSI_ENABLE();
|
|
8003490: 2380 movs r3, #128 @ 0x80
|
|
8003492: 6822 ldr r2, [r4, #0]
|
|
8003494: 005b lsls r3, r3, #1
|
|
8003496: 4313 orrs r3, r2
|
|
8003498: 6023 str r3, [r4, #0]
|
|
tickstart = HAL_GetTick();
|
|
800349a: f7ff fa39 bl 8002910 <HAL_GetTick>
|
|
800349e: 0006 movs r6, r0
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
80034a0: 6823 ldr r3, [r4, #0]
|
|
80034a2: 423b tst r3, r7
|
|
80034a4: d007 beq.n 80034b6 <HAL_RCC_OscConfig+0x136>
|
|
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
|
|
80034a6: 6862 ldr r2, [r4, #4]
|
|
80034a8: 696b ldr r3, [r5, #20]
|
|
80034aa: 4949 ldr r1, [pc, #292] @ (80035d0 <HAL_RCC_OscConfig+0x250>)
|
|
80034ac: 021b lsls r3, r3, #8
|
|
80034ae: 400a ands r2, r1
|
|
80034b0: 4313 orrs r3, r2
|
|
80034b2: 6063 str r3, [r4, #4]
|
|
80034b4: e76f b.n 8003396 <HAL_RCC_OscConfig+0x16>
|
|
if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
|
|
80034b6: f7ff fa2b bl 8002910 <HAL_GetTick>
|
|
80034ba: 1b80 subs r0, r0, r6
|
|
80034bc: 2802 cmp r0, #2
|
|
80034be: d9ef bls.n 80034a0 <HAL_RCC_OscConfig+0x120>
|
|
80034c0: e792 b.n 80033e8 <HAL_RCC_OscConfig+0x68>
|
|
__HAL_RCC_HSI_DISABLE();
|
|
80034c2: 6823 ldr r3, [r4, #0]
|
|
80034c4: 4a47 ldr r2, [pc, #284] @ (80035e4 <HAL_RCC_OscConfig+0x264>)
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
80034c6: 2780 movs r7, #128 @ 0x80
|
|
__HAL_RCC_HSI_DISABLE();
|
|
80034c8: 4013 ands r3, r2
|
|
80034ca: 6023 str r3, [r4, #0]
|
|
tickstart = HAL_GetTick();
|
|
80034cc: f7ff fa20 bl 8002910 <HAL_GetTick>
|
|
80034d0: 0006 movs r6, r0
|
|
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
|
|
80034d2: 00ff lsls r7, r7, #3
|
|
80034d4: 6823 ldr r3, [r4, #0]
|
|
80034d6: 423b tst r3, r7
|
|
80034d8: d100 bne.n 80034dc <HAL_RCC_OscConfig+0x15c>
|
|
80034da: e75c b.n 8003396 <HAL_RCC_OscConfig+0x16>
|
|
if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
|
|
80034dc: f7ff fa18 bl 8002910 <HAL_GetTick>
|
|
80034e0: 1b80 subs r0, r0, r6
|
|
80034e2: 2802 cmp r0, #2
|
|
80034e4: d9f6 bls.n 80034d4 <HAL_RCC_OscConfig+0x154>
|
|
80034e6: e77f b.n 80033e8 <HAL_RCC_OscConfig+0x68>
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
|
|
80034e8: 2138 movs r1, #56 @ 0x38
|
|
80034ea: 4c36 ldr r4, [pc, #216] @ (80035c4 <HAL_RCC_OscConfig+0x244>)
|
|
if (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)
|
|
80034ec: 69aa ldr r2, [r5, #24]
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
|
|
80034ee: 68a3 ldr r3, [r4, #8]
|
|
80034f0: 400b ands r3, r1
|
|
80034f2: 2b18 cmp r3, #24
|
|
80034f4: d103 bne.n 80034fe <HAL_RCC_OscConfig+0x17e>
|
|
if (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)
|
|
80034f6: 2a00 cmp r2, #0
|
|
80034f8: d000 beq.n 80034fc <HAL_RCC_OscConfig+0x17c>
|
|
80034fa: e750 b.n 800339e <HAL_RCC_OscConfig+0x1e>
|
|
80034fc: e743 b.n 8003386 <HAL_RCC_OscConfig+0x6>
|
|
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
|
|
80034fe: 2301 movs r3, #1
|
|
8003500: 2a00 cmp r2, #0
|
|
8003502: d010 beq.n 8003526 <HAL_RCC_OscConfig+0x1a6>
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8003504: 6e22 ldr r2, [r4, #96] @ 0x60
|
|
while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
|
|
8003506: 2702 movs r7, #2
|
|
__HAL_RCC_LSI_ENABLE();
|
|
8003508: 4313 orrs r3, r2
|
|
800350a: 6623 str r3, [r4, #96] @ 0x60
|
|
tickstart = HAL_GetTick();
|
|
800350c: f7ff fa00 bl 8002910 <HAL_GetTick>
|
|
8003510: 0006 movs r6, r0
|
|
while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
|
|
8003512: 6e23 ldr r3, [r4, #96] @ 0x60
|
|
8003514: 423b tst r3, r7
|
|
8003516: d000 beq.n 800351a <HAL_RCC_OscConfig+0x19a>
|
|
8003518: e741 b.n 800339e <HAL_RCC_OscConfig+0x1e>
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE)
|
|
800351a: f7ff f9f9 bl 8002910 <HAL_GetTick>
|
|
800351e: 1b80 subs r0, r0, r6
|
|
8003520: 2802 cmp r0, #2
|
|
8003522: d9f6 bls.n 8003512 <HAL_RCC_OscConfig+0x192>
|
|
8003524: e760 b.n 80033e8 <HAL_RCC_OscConfig+0x68>
|
|
__HAL_RCC_LSI_DISABLE();
|
|
8003526: 6e22 ldr r2, [r4, #96] @ 0x60
|
|
while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U)
|
|
8003528: 2702 movs r7, #2
|
|
__HAL_RCC_LSI_DISABLE();
|
|
800352a: 439a bics r2, r3
|
|
800352c: 6622 str r2, [r4, #96] @ 0x60
|
|
tickstart = HAL_GetTick();
|
|
800352e: f7ff f9ef bl 8002910 <HAL_GetTick>
|
|
8003532: 0006 movs r6, r0
|
|
while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U)
|
|
8003534: 6e23 ldr r3, [r4, #96] @ 0x60
|
|
8003536: 423b tst r3, r7
|
|
8003538: d100 bne.n 800353c <HAL_RCC_OscConfig+0x1bc>
|
|
800353a: e730 b.n 800339e <HAL_RCC_OscConfig+0x1e>
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE)
|
|
800353c: f7ff f9e8 bl 8002910 <HAL_GetTick>
|
|
8003540: 1b80 subs r0, r0, r6
|
|
8003542: 2802 cmp r0, #2
|
|
8003544: d9f6 bls.n 8003534 <HAL_RCC_OscConfig+0x1b4>
|
|
8003546: e74f b.n 80033e8 <HAL_RCC_OscConfig+0x68>
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
|
|
8003548: 2138 movs r1, #56 @ 0x38
|
|
800354a: 4c1e ldr r4, [pc, #120] @ (80035c4 <HAL_RCC_OscConfig+0x244>)
|
|
if (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)
|
|
800354c: 68a8 ldr r0, [r5, #8]
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
|
|
800354e: 68a3 ldr r3, [r4, #8]
|
|
8003550: 400b ands r3, r1
|
|
8003552: 2b20 cmp r3, #32
|
|
8003554: d103 bne.n 800355e <HAL_RCC_OscConfig+0x1de>
|
|
if (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)
|
|
8003556: 4243 negs r3, r0
|
|
8003558: 4158 adcs r0, r3
|
|
800355a: b2c0 uxtb r0, r0
|
|
800355c: e714 b.n 8003388 <HAL_RCC_OscConfig+0x8>
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
800355e: 6de3 ldr r3, [r4, #92] @ 0x5c
|
|
8003560: 2801 cmp r0, #1
|
|
8003562: d110 bne.n 8003586 <HAL_RCC_OscConfig+0x206>
|
|
8003564: 4303 orrs r3, r0
|
|
8003566: 65e3 str r3, [r4, #92] @ 0x5c
|
|
tickstart = HAL_GetTick();
|
|
8003568: f7ff f9d2 bl 8002910 <HAL_GetTick>
|
|
while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
|
|
800356c: 2602 movs r6, #2
|
|
tickstart = HAL_GetTick();
|
|
800356e: 0005 movs r5, r0
|
|
while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
|
|
8003570: 6de3 ldr r3, [r4, #92] @ 0x5c
|
|
8003572: 4233 tst r3, r6
|
|
8003574: d000 beq.n 8003578 <HAL_RCC_OscConfig+0x1f8>
|
|
8003576: e717 b.n 80033a8 <HAL_RCC_OscConfig+0x28>
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
8003578: f7ff f9ca bl 8002910 <HAL_GetTick>
|
|
800357c: 4b1a ldr r3, [pc, #104] @ (80035e8 <HAL_RCC_OscConfig+0x268>)
|
|
800357e: 1b40 subs r0, r0, r5
|
|
8003580: 4298 cmp r0, r3
|
|
8003582: d9f5 bls.n 8003570 <HAL_RCC_OscConfig+0x1f0>
|
|
8003584: e730 b.n 80033e8 <HAL_RCC_OscConfig+0x68>
|
|
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
|
|
8003586: 2805 cmp r0, #5
|
|
8003588: d105 bne.n 8003596 <HAL_RCC_OscConfig+0x216>
|
|
800358a: 4313 orrs r3, r2
|
|
800358c: 65e3 str r3, [r4, #92] @ 0x5c
|
|
800358e: 2301 movs r3, #1
|
|
8003590: 6de2 ldr r2, [r4, #92] @ 0x5c
|
|
8003592: 4313 orrs r3, r2
|
|
8003594: e7e7 b.n 8003566 <HAL_RCC_OscConfig+0x1e6>
|
|
8003596: 2101 movs r1, #1
|
|
8003598: 438b bics r3, r1
|
|
800359a: 65e3 str r3, [r4, #92] @ 0x5c
|
|
800359c: 6de3 ldr r3, [r4, #92] @ 0x5c
|
|
800359e: 4393 bics r3, r2
|
|
80035a0: 65e3 str r3, [r4, #92] @ 0x5c
|
|
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
|
|
80035a2: 2800 cmp r0, #0
|
|
80035a4: d1e0 bne.n 8003568 <HAL_RCC_OscConfig+0x1e8>
|
|
tickstart = HAL_GetTick();
|
|
80035a6: f7ff f9b3 bl 8002910 <HAL_GetTick>
|
|
while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U)
|
|
80035aa: 2602 movs r6, #2
|
|
tickstart = HAL_GetTick();
|
|
80035ac: 0005 movs r5, r0
|
|
while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U)
|
|
80035ae: 6de3 ldr r3, [r4, #92] @ 0x5c
|
|
80035b0: 4233 tst r3, r6
|
|
80035b2: d100 bne.n 80035b6 <HAL_RCC_OscConfig+0x236>
|
|
80035b4: e6f8 b.n 80033a8 <HAL_RCC_OscConfig+0x28>
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
80035b6: f7ff f9ab bl 8002910 <HAL_GetTick>
|
|
80035ba: 4b0b ldr r3, [pc, #44] @ (80035e8 <HAL_RCC_OscConfig+0x268>)
|
|
80035bc: 1b40 subs r0, r0, r5
|
|
80035be: 4298 cmp r0, r3
|
|
80035c0: d9f5 bls.n 80035ae <HAL_RCC_OscConfig+0x22e>
|
|
80035c2: e711 b.n 80033e8 <HAL_RCC_OscConfig+0x68>
|
|
80035c4: 40021000 .word 0x40021000
|
|
80035c8: fffeffff .word 0xfffeffff
|
|
80035cc: fffbffff .word 0xfffbffff
|
|
80035d0: ffff80ff .word 0xffff80ff
|
|
80035d4: ffffc7ff .word 0xffffc7ff
|
|
80035d8: 20000028 .word 0x20000028
|
|
80035dc: 02dc6c00 .word 0x02dc6c00
|
|
80035e0: 20000030 .word 0x20000030
|
|
80035e4: fffffeff .word 0xfffffeff
|
|
80035e8: 00001388 .word 0x00001388
|
|
|
|
080035ec <HAL_RCC_GetSysClockFreq>:
|
|
uint32_t HAL_RCC_GetSysClockFreq(void)
|
|
{
|
|
uint32_t hsidiv;
|
|
uint32_t sysclockfreq;
|
|
#if defined(RCC_CR_SYSDIV)
|
|
uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
|
|
80035ec: 2007 movs r0, #7
|
|
#endif /* RCC_CR_SYSDIV */
|
|
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
|
|
80035ee: 2238 movs r2, #56 @ 0x38
|
|
uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
|
|
80035f0: 4b12 ldr r3, [pc, #72] @ (800363c <HAL_RCC_GetSysClockFreq+0x50>)
|
|
{
|
|
80035f2: b510 push {r4, lr}
|
|
uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
|
|
80035f4: 6819 ldr r1, [r3, #0]
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
|
|
80035f6: 689c ldr r4, [r3, #8]
|
|
uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
|
|
80035f8: 0889 lsrs r1, r1, #2
|
|
80035fa: 4001 ands r1, r0
|
|
80035fc: 3101 adds r1, #1
|
|
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
|
|
80035fe: 4214 tst r4, r2
|
|
8003600: d107 bne.n 8003612 <HAL_RCC_GetSysClockFreq+0x26>
|
|
{
|
|
/* HSISYS can be derived for HSI48 */
|
|
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
|
|
8003602: 681b ldr r3, [r3, #0]
|
|
8003604: 0adb lsrs r3, r3, #11
|
|
8003606: 4003 ands r3, r0
|
|
|
|
/* HSI used as system clock source */
|
|
sysclockfreq = (HSI_VALUE / hsidiv);
|
|
8003608: 480d ldr r0, [pc, #52] @ (8003640 <HAL_RCC_GetSysClockFreq+0x54>)
|
|
800360a: 40d8 lsrs r0, r3
|
|
else
|
|
{
|
|
sysclockfreq = 0U;
|
|
}
|
|
#if defined(RCC_CR_SYSDIV)
|
|
sysclockfreq = sysclockfreq / sysclockdiv;
|
|
800360c: f7fc fd90 bl 8000130 <__udivsi3>
|
|
#endif /* RCC_CR_SYSDIV */
|
|
return sysclockfreq;
|
|
}
|
|
8003610: bd10 pop {r4, pc}
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
|
|
8003612: 6898 ldr r0, [r3, #8]
|
|
8003614: 4010 ands r0, r2
|
|
8003616: 2808 cmp r0, #8
|
|
8003618: d00b beq.n 8003632 <HAL_RCC_GetSysClockFreq+0x46>
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
|
|
800361a: 6898 ldr r0, [r3, #8]
|
|
800361c: 4010 ands r0, r2
|
|
800361e: 2820 cmp r0, #32
|
|
8003620: d009 beq.n 8003636 <HAL_RCC_GetSysClockFreq+0x4a>
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
|
|
8003622: 689b ldr r3, [r3, #8]
|
|
sysclockfreq = 0U;
|
|
8003624: 2000 movs r0, #0
|
|
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
|
|
8003626: 4013 ands r3, r2
|
|
8003628: 2b18 cmp r3, #24
|
|
800362a: d1ef bne.n 800360c <HAL_RCC_GetSysClockFreq+0x20>
|
|
sysclockfreq = LSI_VALUE;
|
|
800362c: 20fa movs r0, #250 @ 0xfa
|
|
800362e: 01c0 lsls r0, r0, #7
|
|
8003630: e7ec b.n 800360c <HAL_RCC_GetSysClockFreq+0x20>
|
|
sysclockfreq = HSE_VALUE;
|
|
8003632: 4804 ldr r0, [pc, #16] @ (8003644 <HAL_RCC_GetSysClockFreq+0x58>)
|
|
8003634: e7ea b.n 800360c <HAL_RCC_GetSysClockFreq+0x20>
|
|
sysclockfreq = LSE_VALUE;
|
|
8003636: 2080 movs r0, #128 @ 0x80
|
|
8003638: 0200 lsls r0, r0, #8
|
|
800363a: e7e7 b.n 800360c <HAL_RCC_GetSysClockFreq+0x20>
|
|
800363c: 40021000 .word 0x40021000
|
|
8003640: 02dc6c00 .word 0x02dc6c00
|
|
8003644: 007a1200 .word 0x007a1200
|
|
|
|
08003648 <HAL_RCC_ClockConfig>:
|
|
{
|
|
8003648: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
800364a: 0004 movs r4, r0
|
|
800364c: 000d movs r5, r1
|
|
if (RCC_ClkInitStruct == NULL)
|
|
800364e: 2800 cmp r0, #0
|
|
8003650: d101 bne.n 8003656 <HAL_RCC_ClockConfig+0xe>
|
|
return HAL_ERROR;
|
|
8003652: 2001 movs r0, #1
|
|
}
|
|
8003654: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
|
|
if (FLatency > __HAL_FLASH_GET_LATENCY())
|
|
8003656: 2707 movs r7, #7
|
|
8003658: 4e4b ldr r6, [pc, #300] @ (8003788 <HAL_RCC_ClockConfig+0x140>)
|
|
800365a: 6833 ldr r3, [r6, #0]
|
|
800365c: 403b ands r3, r7
|
|
800365e: 428b cmp r3, r1
|
|
8003660: d32a bcc.n 80036b8 <HAL_RCC_ClockConfig+0x70>
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
|
|
8003662: 6822 ldr r2, [r4, #0]
|
|
8003664: 0793 lsls r3, r2, #30
|
|
8003666: d43b bmi.n 80036e0 <HAL_RCC_ClockConfig+0x98>
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
|
|
8003668: 07d2 lsls r2, r2, #31
|
|
800366a: d44a bmi.n 8003702 <HAL_RCC_ClockConfig+0xba>
|
|
if (FLatency < __HAL_FLASH_GET_LATENCY())
|
|
800366c: 2707 movs r7, #7
|
|
800366e: 6833 ldr r3, [r6, #0]
|
|
8003670: 403b ands r3, r7
|
|
8003672: 42ab cmp r3, r5
|
|
8003674: d90a bls.n 800368c <HAL_RCC_ClockConfig+0x44>
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
8003676: 6833 ldr r3, [r6, #0]
|
|
8003678: 43bb bics r3, r7
|
|
800367a: 432b orrs r3, r5
|
|
800367c: 6033 str r3, [r6, #0]
|
|
tickstart = HAL_GetTick();
|
|
800367e: f7ff f947 bl 8002910 <HAL_GetTick>
|
|
8003682: 9001 str r0, [sp, #4]
|
|
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
8003684: 6833 ldr r3, [r6, #0]
|
|
8003686: 403b ands r3, r7
|
|
8003688: 42ab cmp r3, r5
|
|
800368a: d16d bne.n 8003768 <HAL_RCC_ClockConfig+0x120>
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
800368c: 6823 ldr r3, [r4, #0]
|
|
800368e: 4d3f ldr r5, [pc, #252] @ (800378c <HAL_RCC_ClockConfig+0x144>)
|
|
8003690: 075b lsls r3, r3, #29
|
|
8003692: d471 bmi.n 8003778 <HAL_RCC_ClockConfig+0x130>
|
|
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
|
|
8003694: f7ff ffaa bl 80035ec <HAL_RCC_GetSysClockFreq>
|
|
8003698: 68ab ldr r3, [r5, #8]
|
|
800369a: 493d ldr r1, [pc, #244] @ (8003790 <HAL_RCC_ClockConfig+0x148>)
|
|
>> RCC_CFGR_HPRE_Pos]) & 0x1FU));
|
|
800369c: 051b lsls r3, r3, #20
|
|
800369e: 0f1b lsrs r3, r3, #28
|
|
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
|
|
80036a0: 009b lsls r3, r3, #2
|
|
>> RCC_CFGR_HPRE_Pos]) & 0x1FU));
|
|
80036a2: 585b ldr r3, [r3, r1]
|
|
80036a4: 211f movs r1, #31
|
|
80036a6: 400b ands r3, r1
|
|
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
|
|
80036a8: 40d8 lsrs r0, r3
|
|
80036aa: 4a3a ldr r2, [pc, #232] @ (8003794 <HAL_RCC_ClockConfig+0x14c>)
|
|
return HAL_InitTick(uwTickPrio);
|
|
80036ac: 4b3a ldr r3, [pc, #232] @ (8003798 <HAL_RCC_ClockConfig+0x150>)
|
|
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
|
|
80036ae: 6010 str r0, [r2, #0]
|
|
return HAL_InitTick(uwTickPrio);
|
|
80036b0: 6818 ldr r0, [r3, #0]
|
|
80036b2: f7ff f8ed bl 8002890 <HAL_InitTick>
|
|
80036b6: e7cd b.n 8003654 <HAL_RCC_ClockConfig+0xc>
|
|
__HAL_FLASH_SET_LATENCY(FLatency);
|
|
80036b8: 6833 ldr r3, [r6, #0]
|
|
80036ba: 43bb bics r3, r7
|
|
80036bc: 430b orrs r3, r1
|
|
80036be: 6033 str r3, [r6, #0]
|
|
tickstart = HAL_GetTick();
|
|
80036c0: f7ff f926 bl 8002910 <HAL_GetTick>
|
|
80036c4: 9001 str r0, [sp, #4]
|
|
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
|
|
80036c6: 6833 ldr r3, [r6, #0]
|
|
80036c8: 403b ands r3, r7
|
|
80036ca: 42ab cmp r3, r5
|
|
80036cc: d0c9 beq.n 8003662 <HAL_RCC_ClockConfig+0x1a>
|
|
if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
|
|
80036ce: f7ff f91f bl 8002910 <HAL_GetTick>
|
|
80036d2: 9b01 ldr r3, [sp, #4]
|
|
80036d4: 1ac0 subs r0, r0, r3
|
|
80036d6: 4b31 ldr r3, [pc, #196] @ (800379c <HAL_RCC_ClockConfig+0x154>)
|
|
80036d8: 4298 cmp r0, r3
|
|
80036da: d9f4 bls.n 80036c6 <HAL_RCC_ClockConfig+0x7e>
|
|
return HAL_TIMEOUT;
|
|
80036dc: 2003 movs r0, #3
|
|
80036de: e7b9 b.n 8003654 <HAL_RCC_ClockConfig+0xc>
|
|
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
|
|
80036e0: 492a ldr r1, [pc, #168] @ (800378c <HAL_RCC_ClockConfig+0x144>)
|
|
80036e2: 0753 lsls r3, r2, #29
|
|
80036e4: d506 bpl.n 80036f4 <HAL_RCC_ClockConfig+0xac>
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
|
|
80036e6: 6888 ldr r0, [r1, #8]
|
|
80036e8: 4b2d ldr r3, [pc, #180] @ (80037a0 <HAL_RCC_ClockConfig+0x158>)
|
|
80036ea: 4018 ands r0, r3
|
|
80036ec: 23b0 movs r3, #176 @ 0xb0
|
|
80036ee: 011b lsls r3, r3, #4
|
|
80036f0: 4303 orrs r3, r0
|
|
80036f2: 608b str r3, [r1, #8]
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
|
|
80036f4: 688b ldr r3, [r1, #8]
|
|
80036f6: 482b ldr r0, [pc, #172] @ (80037a4 <HAL_RCC_ClockConfig+0x15c>)
|
|
80036f8: 4003 ands r3, r0
|
|
80036fa: 68e0 ldr r0, [r4, #12]
|
|
80036fc: 4303 orrs r3, r0
|
|
80036fe: 608b str r3, [r1, #8]
|
|
8003700: e7b2 b.n 8003668 <HAL_RCC_ClockConfig+0x20>
|
|
MODIFY_REG(RCC->CR, RCC_CR_SYSDIV, RCC_ClkInitStruct->SYSCLKDivider);
|
|
8003702: 221c movs r2, #28
|
|
8003704: 4f21 ldr r7, [pc, #132] @ (800378c <HAL_RCC_ClockConfig+0x144>)
|
|
8003706: 683b ldr r3, [r7, #0]
|
|
8003708: 4393 bics r3, r2
|
|
800370a: 68a2 ldr r2, [r4, #8]
|
|
800370c: 4313 orrs r3, r2
|
|
800370e: 603b str r3, [r7, #0]
|
|
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
|
|
8003710: 6862 ldr r2, [r4, #4]
|
|
8003712: 2a01 cmp r2, #1
|
|
8003714: d119 bne.n 800374a <HAL_RCC_ClockConfig+0x102>
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
|
|
8003716: 683b ldr r3, [r7, #0]
|
|
8003718: 039b lsls r3, r3, #14
|
|
800371a: d59a bpl.n 8003652 <HAL_RCC_ClockConfig+0xa>
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
|
|
800371c: 2107 movs r1, #7
|
|
800371e: 68bb ldr r3, [r7, #8]
|
|
8003720: 438b bics r3, r1
|
|
8003722: 4313 orrs r3, r2
|
|
8003724: 60bb str r3, [r7, #8]
|
|
tickstart = HAL_GetTick();
|
|
8003726: f7ff f8f3 bl 8002910 <HAL_GetTick>
|
|
800372a: 9001 str r0, [sp, #4]
|
|
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
|
|
800372c: 2338 movs r3, #56 @ 0x38
|
|
800372e: 68ba ldr r2, [r7, #8]
|
|
8003730: 401a ands r2, r3
|
|
8003732: 6863 ldr r3, [r4, #4]
|
|
8003734: 00db lsls r3, r3, #3
|
|
8003736: 429a cmp r2, r3
|
|
8003738: d098 beq.n 800366c <HAL_RCC_ClockConfig+0x24>
|
|
if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
|
|
800373a: f7ff f8e9 bl 8002910 <HAL_GetTick>
|
|
800373e: 9b01 ldr r3, [sp, #4]
|
|
8003740: 1ac0 subs r0, r0, r3
|
|
8003742: 4b16 ldr r3, [pc, #88] @ (800379c <HAL_RCC_ClockConfig+0x154>)
|
|
8003744: 4298 cmp r0, r3
|
|
8003746: d9f1 bls.n 800372c <HAL_RCC_ClockConfig+0xe4>
|
|
8003748: e7c8 b.n 80036dc <HAL_RCC_ClockConfig+0x94>
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
|
|
800374a: 2a00 cmp r2, #0
|
|
800374c: d103 bne.n 8003756 <HAL_RCC_ClockConfig+0x10e>
|
|
if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
|
|
800374e: 683b ldr r3, [r7, #0]
|
|
8003750: 055b lsls r3, r3, #21
|
|
8003752: d4e3 bmi.n 800371c <HAL_RCC_ClockConfig+0xd4>
|
|
8003754: e77d b.n 8003652 <HAL_RCC_ClockConfig+0xa>
|
|
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
|
|
8003756: 2302 movs r3, #2
|
|
8003758: 2a03 cmp r2, #3
|
|
800375a: d103 bne.n 8003764 <HAL_RCC_ClockConfig+0x11c>
|
|
if (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
|
|
800375c: 6e39 ldr r1, [r7, #96] @ 0x60
|
|
if (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
|
|
800375e: 4219 tst r1, r3
|
|
8003760: d1dc bne.n 800371c <HAL_RCC_ClockConfig+0xd4>
|
|
8003762: e776 b.n 8003652 <HAL_RCC_ClockConfig+0xa>
|
|
8003764: 6df9 ldr r1, [r7, #92] @ 0x5c
|
|
8003766: e7fa b.n 800375e <HAL_RCC_ClockConfig+0x116>
|
|
if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
|
|
8003768: f7ff f8d2 bl 8002910 <HAL_GetTick>
|
|
800376c: 9b01 ldr r3, [sp, #4]
|
|
800376e: 1ac0 subs r0, r0, r3
|
|
8003770: 4b0a ldr r3, [pc, #40] @ (800379c <HAL_RCC_ClockConfig+0x154>)
|
|
8003772: 4298 cmp r0, r3
|
|
8003774: d986 bls.n 8003684 <HAL_RCC_ClockConfig+0x3c>
|
|
8003776: e7b1 b.n 80036dc <HAL_RCC_ClockConfig+0x94>
|
|
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
|
|
8003778: 68ab ldr r3, [r5, #8]
|
|
800377a: 4a0b ldr r2, [pc, #44] @ (80037a8 <HAL_RCC_ClockConfig+0x160>)
|
|
800377c: 4013 ands r3, r2
|
|
800377e: 6922 ldr r2, [r4, #16]
|
|
8003780: 4313 orrs r3, r2
|
|
8003782: 60ab str r3, [r5, #8]
|
|
8003784: e786 b.n 8003694 <HAL_RCC_ClockConfig+0x4c>
|
|
8003786: 46c0 nop @ (mov r8, r8)
|
|
8003788: 40022000 .word 0x40022000
|
|
800378c: 40021000 .word 0x40021000
|
|
8003790: 08005340 .word 0x08005340
|
|
8003794: 20000028 .word 0x20000028
|
|
8003798: 20000030 .word 0x20000030
|
|
800379c: 00001388 .word 0x00001388
|
|
80037a0: ffff84ff .word 0xffff84ff
|
|
80037a4: fffff0ff .word 0xfffff0ff
|
|
80037a8: ffff8fff .word 0xffff8fff
|
|
|
|
080037ac <HAL_RCC_GetHCLKFreq>:
|
|
*
|
|
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
|
|
* @retval HCLK frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetHCLKFreq(void)
|
|
{
|
|
80037ac: b510 push {r4, lr}
|
|
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
|
|
80037ae: f7ff ff1d bl 80035ec <HAL_RCC_GetSysClockFreq>
|
|
80037b2: 4b06 ldr r3, [pc, #24] @ (80037cc <HAL_RCC_GetHCLKFreq+0x20>)
|
|
80037b4: 4a06 ldr r2, [pc, #24] @ (80037d0 <HAL_RCC_GetHCLKFreq+0x24>)
|
|
80037b6: 689b ldr r3, [r3, #8]
|
|
>> RCC_CFGR_HPRE_Pos]) & 0x1FU));
|
|
80037b8: 051b lsls r3, r3, #20
|
|
80037ba: 0f1b lsrs r3, r3, #28
|
|
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
|
|
80037bc: 009b lsls r3, r3, #2
|
|
>> RCC_CFGR_HPRE_Pos]) & 0x1FU));
|
|
80037be: 589b ldr r3, [r3, r2]
|
|
80037c0: 221f movs r2, #31
|
|
80037c2: 4013 ands r3, r2
|
|
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
|
|
80037c4: 40d8 lsrs r0, r3
|
|
80037c6: 4b03 ldr r3, [pc, #12] @ (80037d4 <HAL_RCC_GetHCLKFreq+0x28>)
|
|
80037c8: 6018 str r0, [r3, #0]
|
|
return SystemCoreClock;
|
|
}
|
|
80037ca: bd10 pop {r4, pc}
|
|
80037cc: 40021000 .word 0x40021000
|
|
80037d0: 08005340 .word 0x08005340
|
|
80037d4: 20000028 .word 0x20000028
|
|
|
|
080037d8 <HAL_RCC_GetPCLK1Freq>:
|
|
* @note Each time PCLK1 changes, this function must be called to update the
|
|
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
|
|
* @retval PCLK1 frequency in Hz
|
|
*/
|
|
uint32_t HAL_RCC_GetPCLK1Freq(void)
|
|
{
|
|
80037d8: b510 push {r4, lr}
|
|
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
|
|
return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_Pos]) & 0x1FU));
|
|
80037da: f7ff ffe7 bl 80037ac <HAL_RCC_GetHCLKFreq>
|
|
80037de: 4b05 ldr r3, [pc, #20] @ (80037f4 <HAL_RCC_GetPCLK1Freq+0x1c>)
|
|
80037e0: 4a05 ldr r2, [pc, #20] @ (80037f8 <HAL_RCC_GetPCLK1Freq+0x20>)
|
|
80037e2: 689b ldr r3, [r3, #8]
|
|
80037e4: 045b lsls r3, r3, #17
|
|
80037e6: 0f5b lsrs r3, r3, #29
|
|
80037e8: 009b lsls r3, r3, #2
|
|
80037ea: 589b ldr r3, [r3, r2]
|
|
80037ec: 221f movs r2, #31
|
|
80037ee: 4013 ands r3, r2
|
|
80037f0: 40d8 lsrs r0, r3
|
|
}
|
|
80037f2: bd10 pop {r4, pc}
|
|
80037f4: 40021000 .word 0x40021000
|
|
80037f8: 08005320 .word 0x08005320
|
|
|
|
080037fc <HAL_RCCEx_PeriphCLKConfig>:
|
|
* @note (*) not available on all devices
|
|
*
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit)
|
|
{
|
|
80037fc: b5f0 push {r4, r5, r6, r7, lr}
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
|
|
|
|
/*-------------------------- RTC clock source configuration ----------------------*/
|
|
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
80037fe: 6803 ldr r3, [r0, #0]
|
|
{
|
|
8003800: 0005 movs r5, r0
|
|
8003802: b085 sub sp, #20
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
8003804: 2000 movs r0, #0
|
|
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
|
|
8003806: 065b lsls r3, r3, #25
|
|
8003808: d522 bpl.n 8003850 <HAL_RCCEx_PeriphCLKConfig+0x54>
|
|
|
|
/* Check for RTC Parameters used to output RTCCLK */
|
|
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
|
|
|
|
/* Enable Power Clock */
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
800380a: 2280 movs r2, #128 @ 0x80
|
|
800380c: 4c39 ldr r4, [pc, #228] @ (80038f4 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
|
|
800380e: 0552 lsls r2, r2, #21
|
|
8003810: 6be3 ldr r3, [r4, #60] @ 0x3c
|
|
FlagStatus pwrclkchanged = RESET;
|
|
8003812: 0006 movs r6, r0
|
|
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
|
|
8003814: 4213 tst r3, r2
|
|
8003816: d107 bne.n 8003828 <HAL_RCCEx_PeriphCLKConfig+0x2c>
|
|
{
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
8003818: 6be3 ldr r3, [r4, #60] @ 0x3c
|
|
pwrclkchanged = SET;
|
|
800381a: 3601 adds r6, #1
|
|
__HAL_RCC_PWR_CLK_ENABLE();
|
|
800381c: 4313 orrs r3, r2
|
|
800381e: 63e3 str r3, [r4, #60] @ 0x3c
|
|
8003820: 6be3 ldr r3, [r4, #60] @ 0x3c
|
|
8003822: 4013 ands r3, r2
|
|
8003824: 9303 str r3, [sp, #12]
|
|
8003826: 9b03 ldr r3, [sp, #12]
|
|
}
|
|
|
|
|
|
/* Reset the RTC domain only if the RTC Clock source selection is modified from default */
|
|
tmpregister = READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL);
|
|
8003828: 6de2 ldr r2, [r4, #92] @ 0x5c
|
|
800382a: 23c0 movs r3, #192 @ 0xc0
|
|
800382c: 0011 movs r1, r2
|
|
800382e: 009b lsls r3, r3, #2
|
|
8003830: 4f31 ldr r7, [pc, #196] @ (80038f8 <HAL_RCCEx_PeriphCLKConfig+0xfc>)
|
|
8003832: 4019 ands r1, r3
|
|
|
|
/* Reset the RTC domain only if the RTC Clock source selection is modified */
|
|
if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
|
|
8003834: 421a tst r2, r3
|
|
8003836: d13b bne.n 80038b0 <HAL_RCCEx_PeriphCLKConfig+0xb4>
|
|
HAL_StatusTypeDef status = HAL_OK; /* Final status */
|
|
8003838: 2000 movs r0, #0
|
|
}
|
|
|
|
if (ret == HAL_OK)
|
|
{
|
|
/* Apply new RTC clock source selection */
|
|
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
|
|
800383a: 6de3 ldr r3, [r4, #92] @ 0x5c
|
|
800383c: 69aa ldr r2, [r5, #24]
|
|
800383e: 403b ands r3, r7
|
|
8003840: 4313 orrs r3, r2
|
|
8003842: 65e3 str r3, [r4, #92] @ 0x5c
|
|
/* set overall return value */
|
|
status = ret;
|
|
}
|
|
|
|
/* Restore clock configuration if changed */
|
|
if (pwrclkchanged == SET)
|
|
8003844: 2e01 cmp r6, #1
|
|
8003846: d103 bne.n 8003850 <HAL_RCCEx_PeriphCLKConfig+0x54>
|
|
{
|
|
__HAL_RCC_PWR_CLK_DISABLE();
|
|
8003848: 6be3 ldr r3, [r4, #60] @ 0x3c
|
|
800384a: 4a2c ldr r2, [pc, #176] @ (80038fc <HAL_RCCEx_PeriphCLKConfig+0x100>)
|
|
800384c: 4013 ands r3, r2
|
|
800384e: 63e3 str r3, [r4, #60] @ 0x3c
|
|
}
|
|
}
|
|
|
|
/*-------------------------- USART1 clock source configuration -------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
|
|
8003850: 682a ldr r2, [r5, #0]
|
|
8003852: 07d3 lsls r3, r2, #31
|
|
8003854: d506 bpl.n 8003864 <HAL_RCCEx_PeriphCLKConfig+0x68>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
|
|
|
|
/* Configure the USART1 clock source */
|
|
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
|
|
8003856: 2403 movs r4, #3
|
|
8003858: 4926 ldr r1, [pc, #152] @ (80038f4 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
|
|
800385a: 6d4b ldr r3, [r1, #84] @ 0x54
|
|
800385c: 43a3 bics r3, r4
|
|
800385e: 68ac ldr r4, [r5, #8]
|
|
8003860: 4323 orrs r3, r4
|
|
8003862: 654b str r3, [r1, #84] @ 0x54
|
|
}
|
|
|
|
/*-------------------------- I2C1 clock source configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
|
|
8003864: 0793 lsls r3, r2, #30
|
|
8003866: d506 bpl.n 8003876 <HAL_RCCEx_PeriphCLKConfig+0x7a>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
|
|
|
|
/* Configure the I2C1 clock source */
|
|
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
|
|
8003868: 4922 ldr r1, [pc, #136] @ (80038f4 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
|
|
800386a: 4c25 ldr r4, [pc, #148] @ (8003900 <HAL_RCCEx_PeriphCLKConfig+0x104>)
|
|
800386c: 6d4b ldr r3, [r1, #84] @ 0x54
|
|
800386e: 4023 ands r3, r4
|
|
8003870: 68ec ldr r4, [r5, #12]
|
|
8003872: 4323 orrs r3, r4
|
|
8003874: 654b str r3, [r1, #84] @ 0x54
|
|
}
|
|
|
|
/*-------------------------- ADC clock source configuration ----------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
|
|
8003876: 0693 lsls r3, r2, #26
|
|
8003878: d506 bpl.n 8003888 <HAL_RCCEx_PeriphCLKConfig+0x8c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
|
|
|
|
/* Configure the ADC interface clock source */
|
|
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
|
|
800387a: 491e ldr r1, [pc, #120] @ (80038f4 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
|
|
800387c: 696c ldr r4, [r5, #20]
|
|
800387e: 6d4b ldr r3, [r1, #84] @ 0x54
|
|
8003880: 009b lsls r3, r3, #2
|
|
8003882: 089b lsrs r3, r3, #2
|
|
8003884: 4323 orrs r3, r4
|
|
8003886: 654b str r3, [r1, #84] @ 0x54
|
|
__HAL_RCC_FDCAN1_CONFIG(PeriphClkInit->Fdcan1ClockSelection);
|
|
|
|
}
|
|
#endif /* FDCAN1 */
|
|
/*-------------------------- I2S1 clock source configuration ---------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1)
|
|
8003888: 0753 lsls r3, r2, #29
|
|
800388a: d506 bpl.n 800389a <HAL_RCCEx_PeriphCLKConfig+0x9e>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection));
|
|
|
|
/* Configure the I2S1 clock source */
|
|
__HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection);
|
|
800388c: 4919 ldr r1, [pc, #100] @ (80038f4 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
|
|
800388e: 4c1d ldr r4, [pc, #116] @ (8003904 <HAL_RCCEx_PeriphCLKConfig+0x108>)
|
|
8003890: 6d4b ldr r3, [r1, #84] @ 0x54
|
|
8003892: 4023 ands r3, r4
|
|
8003894: 692c ldr r4, [r5, #16]
|
|
8003896: 4323 orrs r3, r4
|
|
8003898: 654b str r3, [r1, #84] @ 0x54
|
|
}
|
|
/*------------------------------------ HSI Kernel clock source configuration --------------------------------------*/
|
|
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER)
|
|
800389a: 0612 lsls r2, r2, #24
|
|
800389c: d506 bpl.n 80038ac <HAL_RCCEx_PeriphCLKConfig+0xb0>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_RCC_HSIKERDIV(PeriphClkInit->HSIKerClockDivider));
|
|
|
|
/* Configure the HSI Kernel clock source Divider */
|
|
__HAL_RCC_HSIKER_CONFIG(PeriphClkInit->HSIKerClockDivider);
|
|
800389e: 21e0 movs r1, #224 @ 0xe0
|
|
80038a0: 4a14 ldr r2, [pc, #80] @ (80038f4 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
|
|
80038a2: 6813 ldr r3, [r2, #0]
|
|
80038a4: 438b bics r3, r1
|
|
80038a6: 6869 ldr r1, [r5, #4]
|
|
80038a8: 430b orrs r3, r1
|
|
80038aa: 6013 str r3, [r2, #0]
|
|
}
|
|
return status;
|
|
}
|
|
80038ac: b005 add sp, #20
|
|
80038ae: bdf0 pop {r4, r5, r6, r7, pc}
|
|
if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
|
|
80038b0: 69ab ldr r3, [r5, #24]
|
|
80038b2: 428b cmp r3, r1
|
|
80038b4: d0c0 beq.n 8003838 <HAL_RCCEx_PeriphCLKConfig+0x3c>
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
80038b6: 2280 movs r2, #128 @ 0x80
|
|
tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL));
|
|
80038b8: 6de3 ldr r3, [r4, #92] @ 0x5c
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
80038ba: 6de0 ldr r0, [r4, #92] @ 0x5c
|
|
tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL));
|
|
80038bc: 0019 movs r1, r3
|
|
__HAL_RCC_BACKUPRESET_FORCE();
|
|
80038be: 0252 lsls r2, r2, #9
|
|
80038c0: 4302 orrs r2, r0
|
|
80038c2: 65e2 str r2, [r4, #92] @ 0x5c
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
80038c4: 6de2 ldr r2, [r4, #92] @ 0x5c
|
|
80038c6: 4810 ldr r0, [pc, #64] @ (8003908 <HAL_RCCEx_PeriphCLKConfig+0x10c>)
|
|
tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL));
|
|
80038c8: 4039 ands r1, r7
|
|
__HAL_RCC_BACKUPRESET_RELEASE();
|
|
80038ca: 4002 ands r2, r0
|
|
80038cc: 65e2 str r2, [r4, #92] @ 0x5c
|
|
RCC->CSR1 = tmpregister;
|
|
80038ce: 65e1 str r1, [r4, #92] @ 0x5c
|
|
if (HAL_IS_BIT_SET(tmpregister, RCC_CSR1_LSEON))
|
|
80038d0: 07db lsls r3, r3, #31
|
|
80038d2: d5b1 bpl.n 8003838 <HAL_RCCEx_PeriphCLKConfig+0x3c>
|
|
tickstart = HAL_GetTick();
|
|
80038d4: f7ff f81c bl 8002910 <HAL_GetTick>
|
|
80038d8: 9001 str r0, [sp, #4]
|
|
while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
|
|
80038da: 2202 movs r2, #2
|
|
80038dc: 6de3 ldr r3, [r4, #92] @ 0x5c
|
|
80038de: 4213 tst r3, r2
|
|
80038e0: d1aa bne.n 8003838 <HAL_RCCEx_PeriphCLKConfig+0x3c>
|
|
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
|
|
80038e2: f7ff f815 bl 8002910 <HAL_GetTick>
|
|
80038e6: 9b01 ldr r3, [sp, #4]
|
|
80038e8: 1ac0 subs r0, r0, r3
|
|
80038ea: 4b08 ldr r3, [pc, #32] @ (800390c <HAL_RCCEx_PeriphCLKConfig+0x110>)
|
|
80038ec: 4298 cmp r0, r3
|
|
80038ee: d9f4 bls.n 80038da <HAL_RCCEx_PeriphCLKConfig+0xde>
|
|
status = ret;
|
|
80038f0: 2003 movs r0, #3
|
|
80038f2: e7a7 b.n 8003844 <HAL_RCCEx_PeriphCLKConfig+0x48>
|
|
80038f4: 40021000 .word 0x40021000
|
|
80038f8: fffffcff .word 0xfffffcff
|
|
80038fc: efffffff .word 0xefffffff
|
|
8003900: ffffcfff .word 0xffffcfff
|
|
8003904: ffff3fff .word 0xffff3fff
|
|
8003908: fffeffff .word 0xfffeffff
|
|
800390c: 00001388 .word 0x00001388
|
|
|
|
08003910 <TIM_OC1_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8003910: b570 push {r4, r5, r6, lr}
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
|
|
/* Disable the Channel 1: Reset the CC1E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
8003912: 2401 movs r4, #1
|
|
tmpccer = TIMx->CCER;
|
|
8003914: 6a03 ldr r3, [r0, #32]
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
8003916: 6a02 ldr r2, [r0, #32]
|
|
8003918: 43a2 bics r2, r4
|
|
800391a: 6202 str r2, [r0, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
800391c: 6844 ldr r4, [r0, #4]
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR1;
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~TIM_CCMR1_OC1M;
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
800391e: 4a12 ldr r2, [pc, #72] @ (8003968 <TIM_OC1_SetConfig+0x58>)
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8003920: 6985 ldr r5, [r0, #24]
|
|
tmpccmrx &= ~TIM_CCMR1_CC1S;
|
|
8003922: 4015 ands r5, r2
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8003924: 680a ldr r2, [r1, #0]
|
|
8003926: 4315 orrs r5, r2
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1P;
|
|
8003928: 2202 movs r2, #2
|
|
800392a: 4393 bics r3, r2
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= OC_Config->OCPolarity;
|
|
800392c: 688a ldr r2, [r1, #8]
|
|
800392e: 4313 orrs r3, r2
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
|
|
8003930: 4a0e ldr r2, [pc, #56] @ (800396c <TIM_OC1_SetConfig+0x5c>)
|
|
8003932: 4290 cmp r0, r2
|
|
8003934: d005 beq.n 8003942 <TIM_OC1_SetConfig+0x32>
|
|
8003936: 4a0e ldr r2, [pc, #56] @ (8003970 <TIM_OC1_SetConfig+0x60>)
|
|
8003938: 4290 cmp r0, r2
|
|
800393a: d002 beq.n 8003942 <TIM_OC1_SetConfig+0x32>
|
|
800393c: 4a0d ldr r2, [pc, #52] @ (8003974 <TIM_OC1_SetConfig+0x64>)
|
|
800393e: 4290 cmp r0, r2
|
|
8003940: d10b bne.n 800395a <TIM_OC1_SetConfig+0x4a>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC1NP;
|
|
8003942: 2208 movs r2, #8
|
|
8003944: 4393 bics r3, r2
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
8003946: 68ca ldr r2, [r1, #12]
|
|
tmpcr2 &= ~TIM_CR2_OIS1;
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= OC_Config->OCIdleState;
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
8003948: 698e ldr r6, [r1, #24]
|
|
tmpccer |= OC_Config->OCNPolarity;
|
|
800394a: 4313 orrs r3, r2
|
|
tmpccer &= ~TIM_CCER_CC1NE;
|
|
800394c: 2204 movs r2, #4
|
|
800394e: 4393 bics r3, r2
|
|
tmpcr2 &= ~TIM_CR2_OIS1N;
|
|
8003950: 4a09 ldr r2, [pc, #36] @ (8003978 <TIM_OC1_SetConfig+0x68>)
|
|
8003952: 4022 ands r2, r4
|
|
tmpcr2 |= OC_Config->OCNIdleState;
|
|
8003954: 694c ldr r4, [r1, #20]
|
|
8003956: 4334 orrs r4, r6
|
|
8003958: 4314 orrs r4, r2
|
|
|
|
/* Write to TIMx CCMR1 */
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
800395a: 684a ldr r2, [r1, #4]
|
|
TIMx->CR2 = tmpcr2;
|
|
800395c: 6044 str r4, [r0, #4]
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
800395e: 6185 str r5, [r0, #24]
|
|
TIMx->CCR1 = OC_Config->Pulse;
|
|
8003960: 6342 str r2, [r0, #52] @ 0x34
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8003962: 6203 str r3, [r0, #32]
|
|
}
|
|
8003964: bd70 pop {r4, r5, r6, pc}
|
|
8003966: 46c0 nop @ (mov r8, r8)
|
|
8003968: fffeff8c .word 0xfffeff8c
|
|
800396c: 40012c00 .word 0x40012c00
|
|
8003970: 40014400 .word 0x40014400
|
|
8003974: 40014800 .word 0x40014800
|
|
8003978: fffffcff .word 0xfffffcff
|
|
|
|
0800397c <TIM_OC3_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
800397c: b570 push {r4, r5, r6, lr}
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
|
|
/* Disable the Channel 3: Reset the CC2E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
800397e: 4a17 ldr r2, [pc, #92] @ (80039dc <TIM_OC3_SetConfig+0x60>)
|
|
tmpccer = TIMx->CCER;
|
|
8003980: 6a05 ldr r5, [r0, #32]
|
|
TIMx->CCER &= ~TIM_CCER_CC3E;
|
|
8003982: 6a03 ldr r3, [r0, #32]
|
|
8003984: 4013 ands r3, r2
|
|
8003986: 6203 str r3, [r0, #32]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = TIMx->CR2;
|
|
8003988: 6842 ldr r2, [r0, #4]
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC3M;
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
800398a: 4b15 ldr r3, [pc, #84] @ (80039e0 <TIM_OC3_SetConfig+0x64>)
|
|
tmpccmrx = TIMx->CCMR2;
|
|
800398c: 69c4 ldr r4, [r0, #28]
|
|
tmpccmrx &= ~TIM_CCMR2_CC3S;
|
|
800398e: 401c ands r4, r3
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8003990: 680b ldr r3, [r1, #0]
|
|
8003992: 431c orrs r4, r3
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3P;
|
|
8003994: 4b13 ldr r3, [pc, #76] @ (80039e4 <TIM_OC3_SetConfig+0x68>)
|
|
8003996: 401d ands r5, r3
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 8U);
|
|
8003998: 688b ldr r3, [r1, #8]
|
|
800399a: 021b lsls r3, r3, #8
|
|
800399c: 432b orrs r3, r5
|
|
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
|
|
800399e: 4d12 ldr r5, [pc, #72] @ (80039e8 <TIM_OC3_SetConfig+0x6c>)
|
|
80039a0: 42a8 cmp r0, r5
|
|
80039a2: d10e bne.n 80039c2 <TIM_OC3_SetConfig+0x46>
|
|
{
|
|
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
|
|
|
|
/* Reset the Output N Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC3NP;
|
|
80039a4: 4d11 ldr r5, [pc, #68] @ (80039ec <TIM_OC3_SetConfig+0x70>)
|
|
80039a6: 401d ands r5, r3
|
|
/* Set the Output N Polarity */
|
|
tmpccer |= (OC_Config->OCNPolarity << 8U);
|
|
80039a8: 68cb ldr r3, [r1, #12]
|
|
80039aa: 021b lsls r3, r3, #8
|
|
80039ac: 432b orrs r3, r5
|
|
/* Reset the Output N State */
|
|
tmpccer &= ~TIM_CCER_CC3NE;
|
|
80039ae: 4d10 ldr r5, [pc, #64] @ (80039f0 <TIM_OC3_SetConfig+0x74>)
|
|
80039b0: 402b ands r3, r5
|
|
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare and Output Compare N IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS3;
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
80039b2: 4d10 ldr r5, [pc, #64] @ (80039f4 <TIM_OC3_SetConfig+0x78>)
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 4U);
|
|
/* Set the Output N Idle state */
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
80039b4: 698e ldr r6, [r1, #24]
|
|
tmpcr2 &= ~TIM_CR2_OIS3N;
|
|
80039b6: 4015 ands r5, r2
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
|
|
80039b8: 694a ldr r2, [r1, #20]
|
|
80039ba: 4332 orrs r2, r6
|
|
80039bc: 0112 lsls r2, r2, #4
|
|
80039be: 432a orrs r2, r5
|
|
80039c0: e005 b.n 80039ce <TIM_OC3_SetConfig+0x52>
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
80039c2: 4d0d ldr r5, [pc, #52] @ (80039f8 <TIM_OC3_SetConfig+0x7c>)
|
|
80039c4: 42a8 cmp r0, r5
|
|
80039c6: d0f4 beq.n 80039b2 <TIM_OC3_SetConfig+0x36>
|
|
80039c8: 4d0c ldr r5, [pc, #48] @ (80039fc <TIM_OC3_SetConfig+0x80>)
|
|
80039ca: 42a8 cmp r0, r5
|
|
80039cc: d0f1 beq.n 80039b2 <TIM_OC3_SetConfig+0x36>
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
80039ce: 6042 str r2, [r0, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
80039d0: 684a ldr r2, [r1, #4]
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
80039d2: 61c4 str r4, [r0, #28]
|
|
TIMx->CCR3 = OC_Config->Pulse;
|
|
80039d4: 63c2 str r2, [r0, #60] @ 0x3c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
80039d6: 6203 str r3, [r0, #32]
|
|
}
|
|
80039d8: bd70 pop {r4, r5, r6, pc}
|
|
80039da: 46c0 nop @ (mov r8, r8)
|
|
80039dc: fffffeff .word 0xfffffeff
|
|
80039e0: fffeff8c .word 0xfffeff8c
|
|
80039e4: fffffdff .word 0xfffffdff
|
|
80039e8: 40012c00 .word 0x40012c00
|
|
80039ec: fffff7ff .word 0xfffff7ff
|
|
80039f0: fffffbff .word 0xfffffbff
|
|
80039f4: ffffcfff .word 0xffffcfff
|
|
80039f8: 40014400 .word 0x40014400
|
|
80039fc: 40014800 .word 0x40014800
|
|
|
|
08003a00 <TIM_OC4_SetConfig>:
|
|
* @param TIMx to select the TIM peripheral
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8003a00: b530 push {r4, r5, lr}
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
|
|
/* Disable the Channel 4: Reset the CC4E Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
8003a02: 4a12 ldr r2, [pc, #72] @ (8003a4c <TIM_OC4_SetConfig+0x4c>)
|
|
tmpccer = TIMx->CCER;
|
|
8003a04: 6a04 ldr r4, [r0, #32]
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
8003a06: 6a03 ldr r3, [r0, #32]
|
|
/* Get the TIMx CCMR2 register value */
|
|
tmpccmrx = TIMx->CCMR2;
|
|
|
|
/* Reset the Output Compare mode and Capture/Compare selection Bits */
|
|
tmpccmrx &= ~TIM_CCMR2_OC4M;
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
8003a08: 4d11 ldr r5, [pc, #68] @ (8003a50 <TIM_OC4_SetConfig+0x50>)
|
|
TIMx->CCER &= ~TIM_CCER_CC4E;
|
|
8003a0a: 4013 ands r3, r2
|
|
8003a0c: 6203 str r3, [r0, #32]
|
|
tmpcr2 = TIMx->CR2;
|
|
8003a0e: 6843 ldr r3, [r0, #4]
|
|
tmpccmrx = TIMx->CCMR2;
|
|
8003a10: 69c2 ldr r2, [r0, #28]
|
|
tmpccmrx &= ~TIM_CCMR2_CC4S;
|
|
8003a12: 402a ands r2, r5
|
|
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8003a14: 680d ldr r5, [r1, #0]
|
|
8003a16: 022d lsls r5, r5, #8
|
|
8003a18: 4315 orrs r5, r2
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC4P;
|
|
8003a1a: 4a0e ldr r2, [pc, #56] @ (8003a54 <TIM_OC4_SetConfig+0x54>)
|
|
8003a1c: 4014 ands r4, r2
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 12U);
|
|
8003a1e: 688a ldr r2, [r1, #8]
|
|
8003a20: 0312 lsls r2, r2, #12
|
|
8003a22: 4322 orrs r2, r4
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8003a24: 4c0c ldr r4, [pc, #48] @ (8003a58 <TIM_OC4_SetConfig+0x58>)
|
|
8003a26: 42a0 cmp r0, r4
|
|
8003a28: d005 beq.n 8003a36 <TIM_OC4_SetConfig+0x36>
|
|
8003a2a: 4c0c ldr r4, [pc, #48] @ (8003a5c <TIM_OC4_SetConfig+0x5c>)
|
|
8003a2c: 42a0 cmp r0, r4
|
|
8003a2e: d002 beq.n 8003a36 <TIM_OC4_SetConfig+0x36>
|
|
8003a30: 4c0b ldr r4, [pc, #44] @ (8003a60 <TIM_OC4_SetConfig+0x60>)
|
|
8003a32: 42a0 cmp r0, r4
|
|
8003a34: d104 bne.n 8003a40 <TIM_OC4_SetConfig+0x40>
|
|
{
|
|
/* Check parameters */
|
|
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
|
|
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS4;
|
|
8003a36: 4c0b ldr r4, [pc, #44] @ (8003a64 <TIM_OC4_SetConfig+0x64>)
|
|
8003a38: 401c ands r4, r3
|
|
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 6U);
|
|
8003a3a: 694b ldr r3, [r1, #20]
|
|
8003a3c: 019b lsls r3, r3, #6
|
|
8003a3e: 4323 orrs r3, r4
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8003a40: 6043 str r3, [r0, #4]
|
|
|
|
/* Write to TIMx CCMR2 */
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
8003a42: 684b ldr r3, [r1, #4]
|
|
TIMx->CCMR2 = tmpccmrx;
|
|
8003a44: 61c5 str r5, [r0, #28]
|
|
TIMx->CCR4 = OC_Config->Pulse;
|
|
8003a46: 6403 str r3, [r0, #64] @ 0x40
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8003a48: 6202 str r2, [r0, #32]
|
|
}
|
|
8003a4a: bd30 pop {r4, r5, pc}
|
|
8003a4c: ffffefff .word 0xffffefff
|
|
8003a50: feff8cff .word 0xfeff8cff
|
|
8003a54: ffffdfff .word 0xffffdfff
|
|
8003a58: 40012c00 .word 0x40012c00
|
|
8003a5c: 40014400 .word 0x40014400
|
|
8003a60: 40014800 .word 0x40014800
|
|
8003a64: ffffbfff .word 0xffffbfff
|
|
|
|
08003a68 <TIM_OC5_SetConfig>:
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8003a68: b570 push {r4, r5, r6, lr}
|
|
uint32_t tmpccmrx;
|
|
uint32_t tmpccer;
|
|
uint32_t tmpcr2;
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
8003a6a: 6a06 ldr r6, [r0, #32]
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC5E;
|
|
8003a6c: 4c10 ldr r4, [pc, #64] @ (8003ab0 <TIM_OC5_SetConfig+0x48>)
|
|
8003a6e: 6a03 ldr r3, [r0, #32]
|
|
tmpcr2 = TIMx->CR2;
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC5M);
|
|
8003a70: 4a10 ldr r2, [pc, #64] @ (8003ab4 <TIM_OC5_SetConfig+0x4c>)
|
|
TIMx->CCER &= ~TIM_CCER_CC5E;
|
|
8003a72: 4023 ands r3, r4
|
|
8003a74: 6203 str r3, [r0, #32]
|
|
tmpcr2 = TIMx->CR2;
|
|
8003a76: 6843 ldr r3, [r0, #4]
|
|
tmpccmrx = TIMx->CCMR3;
|
|
8003a78: 6d45 ldr r5, [r0, #84] @ 0x54
|
|
tmpccmrx &= ~(TIM_CCMR3_OC5M);
|
|
8003a7a: 4015 ands r5, r2
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= OC_Config->OCMode;
|
|
8003a7c: 680a ldr r2, [r1, #0]
|
|
8003a7e: 4315 orrs r5, r2
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= ~TIM_CCER_CC5P;
|
|
8003a80: 4a0d ldr r2, [pc, #52] @ (8003ab8 <TIM_OC5_SetConfig+0x50>)
|
|
8003a82: 4016 ands r6, r2
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 16U);
|
|
8003a84: 688a ldr r2, [r1, #8]
|
|
8003a86: 0412 lsls r2, r2, #16
|
|
8003a88: 4332 orrs r2, r6
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8003a8a: 4e0c ldr r6, [pc, #48] @ (8003abc <TIM_OC5_SetConfig+0x54>)
|
|
8003a8c: 42b0 cmp r0, r6
|
|
8003a8e: d005 beq.n 8003a9c <TIM_OC5_SetConfig+0x34>
|
|
8003a90: 4e0b ldr r6, [pc, #44] @ (8003ac0 <TIM_OC5_SetConfig+0x58>)
|
|
8003a92: 42b0 cmp r0, r6
|
|
8003a94: d002 beq.n 8003a9c <TIM_OC5_SetConfig+0x34>
|
|
8003a96: 4e0b ldr r6, [pc, #44] @ (8003ac4 <TIM_OC5_SetConfig+0x5c>)
|
|
8003a98: 42b0 cmp r0, r6
|
|
8003a9a: d103 bne.n 8003aa4 <TIM_OC5_SetConfig+0x3c>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS5;
|
|
8003a9c: 401c ands r4, r3
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 8U);
|
|
8003a9e: 694b ldr r3, [r1, #20]
|
|
8003aa0: 021b lsls r3, r3, #8
|
|
8003aa2: 4323 orrs r3, r4
|
|
}
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8003aa4: 6043 str r3, [r0, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR5 = OC_Config->Pulse;
|
|
8003aa6: 684b ldr r3, [r1, #4]
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
8003aa8: 6545 str r5, [r0, #84] @ 0x54
|
|
TIMx->CCR5 = OC_Config->Pulse;
|
|
8003aaa: 6583 str r3, [r0, #88] @ 0x58
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8003aac: 6202 str r2, [r0, #32]
|
|
}
|
|
8003aae: bd70 pop {r4, r5, r6, pc}
|
|
8003ab0: fffeffff .word 0xfffeffff
|
|
8003ab4: fffeff8f .word 0xfffeff8f
|
|
8003ab8: fffdffff .word 0xfffdffff
|
|
8003abc: 40012c00 .word 0x40012c00
|
|
8003ac0: 40014400 .word 0x40014400
|
|
8003ac4: 40014800 .word 0x40014800
|
|
|
|
08003ac8 <TIM_OC6_SetConfig>:
|
|
* @param OC_Config The output configuration structure
|
|
* @retval None
|
|
*/
|
|
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
|
|
const TIM_OC_InitTypeDef *OC_Config)
|
|
{
|
|
8003ac8: b530 push {r4, r5, lr}
|
|
|
|
/* Get the TIMx CCER register value */
|
|
tmpccer = TIMx->CCER;
|
|
|
|
/* Disable the output: Reset the CCxE Bit */
|
|
TIMx->CCER &= ~TIM_CCER_CC6E;
|
|
8003aca: 4a12 ldr r2, [pc, #72] @ (8003b14 <TIM_OC6_SetConfig+0x4c>)
|
|
tmpccer = TIMx->CCER;
|
|
8003acc: 6a04 ldr r4, [r0, #32]
|
|
TIMx->CCER &= ~TIM_CCER_CC6E;
|
|
8003ace: 6a03 ldr r3, [r0, #32]
|
|
tmpcr2 = TIMx->CR2;
|
|
/* Get the TIMx CCMR1 register value */
|
|
tmpccmrx = TIMx->CCMR3;
|
|
|
|
/* Reset the Output Compare Mode Bits */
|
|
tmpccmrx &= ~(TIM_CCMR3_OC6M);
|
|
8003ad0: 4d11 ldr r5, [pc, #68] @ (8003b18 <TIM_OC6_SetConfig+0x50>)
|
|
TIMx->CCER &= ~TIM_CCER_CC6E;
|
|
8003ad2: 4013 ands r3, r2
|
|
8003ad4: 6203 str r3, [r0, #32]
|
|
tmpcr2 = TIMx->CR2;
|
|
8003ad6: 6843 ldr r3, [r0, #4]
|
|
tmpccmrx = TIMx->CCMR3;
|
|
8003ad8: 6d42 ldr r2, [r0, #84] @ 0x54
|
|
tmpccmrx &= ~(TIM_CCMR3_OC6M);
|
|
8003ada: 402a ands r2, r5
|
|
/* Select the Output Compare Mode */
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8003adc: 680d ldr r5, [r1, #0]
|
|
8003ade: 022d lsls r5, r5, #8
|
|
8003ae0: 4315 orrs r5, r2
|
|
|
|
/* Reset the Output Polarity level */
|
|
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
|
|
8003ae2: 4a0e ldr r2, [pc, #56] @ (8003b1c <TIM_OC6_SetConfig+0x54>)
|
|
8003ae4: 4014 ands r4, r2
|
|
/* Set the Output Compare Polarity */
|
|
tmpccer |= (OC_Config->OCPolarity << 20U);
|
|
8003ae6: 688a ldr r2, [r1, #8]
|
|
8003ae8: 0512 lsls r2, r2, #20
|
|
8003aea: 4322 orrs r2, r4
|
|
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8003aec: 4c0c ldr r4, [pc, #48] @ (8003b20 <TIM_OC6_SetConfig+0x58>)
|
|
8003aee: 42a0 cmp r0, r4
|
|
8003af0: d005 beq.n 8003afe <TIM_OC6_SetConfig+0x36>
|
|
8003af2: 4c0c ldr r4, [pc, #48] @ (8003b24 <TIM_OC6_SetConfig+0x5c>)
|
|
8003af4: 42a0 cmp r0, r4
|
|
8003af6: d002 beq.n 8003afe <TIM_OC6_SetConfig+0x36>
|
|
8003af8: 4c0b ldr r4, [pc, #44] @ (8003b28 <TIM_OC6_SetConfig+0x60>)
|
|
8003afa: 42a0 cmp r0, r4
|
|
8003afc: d104 bne.n 8003b08 <TIM_OC6_SetConfig+0x40>
|
|
{
|
|
/* Reset the Output Compare IDLE State */
|
|
tmpcr2 &= ~TIM_CR2_OIS6;
|
|
8003afe: 4c0b ldr r4, [pc, #44] @ (8003b2c <TIM_OC6_SetConfig+0x64>)
|
|
8003b00: 401c ands r4, r3
|
|
/* Set the Output Idle state */
|
|
tmpcr2 |= (OC_Config->OCIdleState << 10U);
|
|
8003b02: 694b ldr r3, [r1, #20]
|
|
8003b04: 029b lsls r3, r3, #10
|
|
8003b06: 4323 orrs r3, r4
|
|
}
|
|
|
|
/* Write to TIMx CR2 */
|
|
TIMx->CR2 = tmpcr2;
|
|
8003b08: 6043 str r3, [r0, #4]
|
|
|
|
/* Write to TIMx CCMR3 */
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
|
|
/* Set the Capture Compare Register value */
|
|
TIMx->CCR6 = OC_Config->Pulse;
|
|
8003b0a: 684b ldr r3, [r1, #4]
|
|
TIMx->CCMR3 = tmpccmrx;
|
|
8003b0c: 6545 str r5, [r0, #84] @ 0x54
|
|
TIMx->CCR6 = OC_Config->Pulse;
|
|
8003b0e: 65c3 str r3, [r0, #92] @ 0x5c
|
|
|
|
/* Write to TIMx CCER */
|
|
TIMx->CCER = tmpccer;
|
|
8003b10: 6202 str r2, [r0, #32]
|
|
}
|
|
8003b12: bd30 pop {r4, r5, pc}
|
|
8003b14: ffefffff .word 0xffefffff
|
|
8003b18: feff8fff .word 0xfeff8fff
|
|
8003b1c: ffdfffff .word 0xffdfffff
|
|
8003b20: 40012c00 .word 0x40012c00
|
|
8003b24: 40014400 .word 0x40014400
|
|
8003b28: 40014800 .word 0x40014800
|
|
8003b2c: fffbffff .word 0xfffbffff
|
|
|
|
08003b30 <HAL_TIM_Base_Stop>:
|
|
__HAL_TIM_DISABLE(htim);
|
|
8003b30: 6803 ldr r3, [r0, #0]
|
|
8003b32: 4a08 ldr r2, [pc, #32] @ (8003b54 <HAL_TIM_Base_Stop+0x24>)
|
|
8003b34: 6a19 ldr r1, [r3, #32]
|
|
8003b36: 4211 tst r1, r2
|
|
8003b38: d107 bne.n 8003b4a <HAL_TIM_Base_Stop+0x1a>
|
|
8003b3a: 6a19 ldr r1, [r3, #32]
|
|
8003b3c: 4a06 ldr r2, [pc, #24] @ (8003b58 <HAL_TIM_Base_Stop+0x28>)
|
|
8003b3e: 4211 tst r1, r2
|
|
8003b40: d103 bne.n 8003b4a <HAL_TIM_Base_Stop+0x1a>
|
|
8003b42: 2101 movs r1, #1
|
|
8003b44: 681a ldr r2, [r3, #0]
|
|
8003b46: 438a bics r2, r1
|
|
8003b48: 601a str r2, [r3, #0]
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8003b4a: 2301 movs r3, #1
|
|
8003b4c: 303d adds r0, #61 @ 0x3d
|
|
8003b4e: 7003 strb r3, [r0, #0]
|
|
}
|
|
8003b50: 2000 movs r0, #0
|
|
8003b52: 4770 bx lr
|
|
8003b54: 00001111 .word 0x00001111
|
|
8003b58: 00000444 .word 0x00000444
|
|
|
|
08003b5c <HAL_TIM_Base_Start_IT>:
|
|
if (htim->State != HAL_TIM_STATE_READY)
|
|
8003b5c: 0001 movs r1, r0
|
|
{
|
|
8003b5e: 0003 movs r3, r0
|
|
return HAL_ERROR;
|
|
8003b60: 2001 movs r0, #1
|
|
{
|
|
8003b62: b510 push {r4, lr}
|
|
if (htim->State != HAL_TIM_STATE_READY)
|
|
8003b64: 313d adds r1, #61 @ 0x3d
|
|
8003b66: 780c ldrb r4, [r1, #0]
|
|
8003b68: b2e2 uxtb r2, r4
|
|
8003b6a: 4284 cmp r4, r0
|
|
8003b6c: d11c bne.n 8003ba8 <HAL_TIM_Base_Start_IT+0x4c>
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8003b6e: 1800 adds r0, r0, r0
|
|
8003b70: 7008 strb r0, [r1, #0]
|
|
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
|
|
8003b72: 681b ldr r3, [r3, #0]
|
|
8003b74: 68d9 ldr r1, [r3, #12]
|
|
8003b76: 4311 orrs r1, r2
|
|
8003b78: 60d9 str r1, [r3, #12]
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8003b7a: 490d ldr r1, [pc, #52] @ (8003bb0 <HAL_TIM_Base_Start_IT+0x54>)
|
|
8003b7c: 428b cmp r3, r1
|
|
8003b7e: d006 beq.n 8003b8e <HAL_TIM_Base_Start_IT+0x32>
|
|
8003b80: 2180 movs r1, #128 @ 0x80
|
|
8003b82: 05c9 lsls r1, r1, #23
|
|
8003b84: 428b cmp r3, r1
|
|
8003b86: d002 beq.n 8003b8e <HAL_TIM_Base_Start_IT+0x32>
|
|
8003b88: 490a ldr r1, [pc, #40] @ (8003bb4 <HAL_TIM_Base_Start_IT+0x58>)
|
|
8003b8a: 428b cmp r3, r1
|
|
8003b8c: d10d bne.n 8003baa <HAL_TIM_Base_Start_IT+0x4e>
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
8003b8e: 689a ldr r2, [r3, #8]
|
|
8003b90: 4909 ldr r1, [pc, #36] @ (8003bb8 <HAL_TIM_Base_Start_IT+0x5c>)
|
|
8003b92: 400a ands r2, r1
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
8003b94: 2a06 cmp r2, #6
|
|
8003b96: d006 beq.n 8003ba6 <HAL_TIM_Base_Start_IT+0x4a>
|
|
8003b98: 3907 subs r1, #7
|
|
8003b9a: 428a cmp r2, r1
|
|
8003b9c: d003 beq.n 8003ba6 <HAL_TIM_Base_Start_IT+0x4a>
|
|
__HAL_TIM_ENABLE(htim);
|
|
8003b9e: 2201 movs r2, #1
|
|
8003ba0: 6819 ldr r1, [r3, #0]
|
|
8003ba2: 430a orrs r2, r1
|
|
8003ba4: 601a str r2, [r3, #0]
|
|
return HAL_OK;
|
|
8003ba6: 2000 movs r0, #0
|
|
}
|
|
8003ba8: bd10 pop {r4, pc}
|
|
__HAL_TIM_ENABLE(htim);
|
|
8003baa: 6819 ldr r1, [r3, #0]
|
|
8003bac: e7f9 b.n 8003ba2 <HAL_TIM_Base_Start_IT+0x46>
|
|
8003bae: 46c0 nop @ (mov r8, r8)
|
|
8003bb0: 40012c00 .word 0x40012c00
|
|
8003bb4: 40000400 .word 0x40000400
|
|
8003bb8: 00010007 .word 0x00010007
|
|
|
|
08003bbc <HAL_TIM_PWM_MspInit>:
|
|
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
|
|
8003bbc: 4770 bx lr
|
|
|
|
08003bbe <HAL_TIM_Encoder_Start>:
|
|
{
|
|
8003bbe: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
|
|
8003bc0: 223e movs r2, #62 @ 0x3e
|
|
{
|
|
8003bc2: 0003 movs r3, r0
|
|
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
|
|
8003bc4: 4694 mov ip, r2
|
|
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
|
|
8003bc6: 001f movs r7, r3
|
|
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
|
|
8003bc8: 4484 add ip, r0
|
|
8003bca: 4662 mov r2, ip
|
|
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
|
|
8003bcc: 001e movs r6, r3
|
|
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
|
|
8003bce: 001d movs r5, r3
|
|
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
|
|
8003bd0: 373f adds r7, #63 @ 0x3f
|
|
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
|
|
8003bd2: 7810 ldrb r0, [r2, #0]
|
|
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
|
|
8003bd4: 783a ldrb r2, [r7, #0]
|
|
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
|
|
8003bd6: 3644 adds r6, #68 @ 0x44
|
|
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
|
|
8003bd8: b2d2 uxtb r2, r2
|
|
8003bda: 9201 str r2, [sp, #4]
|
|
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
|
|
8003bdc: 3545 adds r5, #69 @ 0x45
|
|
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
|
|
8003bde: 7834 ldrb r4, [r6, #0]
|
|
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
|
|
8003be0: 782a ldrb r2, [r5, #0]
|
|
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
|
|
8003be2: b2c0 uxtb r0, r0
|
|
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
|
|
8003be4: b2e4 uxtb r4, r4
|
|
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
|
|
8003be6: b2d2 uxtb r2, r2
|
|
if (Channel == TIM_CHANNEL_1)
|
|
8003be8: 2900 cmp r1, #0
|
|
8003bea: d114 bne.n 8003c16 <HAL_TIM_Encoder_Start+0x58>
|
|
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
8003bec: 2801 cmp r0, #1
|
|
8003bee: d13c bne.n 8003c6a <HAL_TIM_Encoder_Start+0xac>
|
|
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
|
|
8003bf0: 2c01 cmp r4, #1
|
|
8003bf2: d10f bne.n 8003c14 <HAL_TIM_Encoder_Start+0x56>
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8003bf4: 2202 movs r2, #2
|
|
8003bf6: 4661 mov r1, ip
|
|
8003bf8: 700a strb r2, [r1, #0]
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8003bfa: 7032 strb r2, [r6, #0]
|
|
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
8003bfc: 681b ldr r3, [r3, #0]
|
|
assert_param(IS_TIM_CHANNELS(Channel));
|
|
|
|
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
|
|
|
/* Reset the CCxE Bit */
|
|
TIMx->CCER &= ~tmp;
|
|
8003bfe: 6a1a ldr r2, [r3, #32]
|
|
8003c00: 43a2 bics r2, r4
|
|
8003c02: 621a str r2, [r3, #32]
|
|
|
|
/* Set or reset the CCxE Bit */
|
|
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
|
8003c04: 6a1a ldr r2, [r3, #32]
|
|
8003c06: 4322 orrs r2, r4
|
|
8003c08: 621a str r2, [r3, #32]
|
|
__HAL_TIM_ENABLE(htim);
|
|
8003c0a: 2201 movs r2, #1
|
|
return HAL_OK;
|
|
8003c0c: 2000 movs r0, #0
|
|
__HAL_TIM_ENABLE(htim);
|
|
8003c0e: 6819 ldr r1, [r3, #0]
|
|
8003c10: 430a orrs r2, r1
|
|
8003c12: 601a str r2, [r3, #0]
|
|
}
|
|
8003c14: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
|
|
else if (Channel == TIM_CHANNEL_2)
|
|
8003c16: 2904 cmp r1, #4
|
|
8003c18: d110 bne.n 8003c3c <HAL_TIM_Encoder_Start+0x7e>
|
|
return HAL_ERROR;
|
|
8003c1a: 2001 movs r0, #1
|
|
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
8003c1c: 9901 ldr r1, [sp, #4]
|
|
8003c1e: 4281 cmp r1, r0
|
|
8003c20: d1f8 bne.n 8003c14 <HAL_TIM_Encoder_Start+0x56>
|
|
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
|
|
8003c22: 4282 cmp r2, r0
|
|
8003c24: d1f6 bne.n 8003c14 <HAL_TIM_Encoder_Start+0x56>
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8003c26: 2202 movs r2, #2
|
|
8003c28: 703a strb r2, [r7, #0]
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8003c2a: 702a strb r2, [r5, #0]
|
|
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
|
|
8003c2c: 681b ldr r3, [r3, #0]
|
|
TIMx->CCER &= ~tmp;
|
|
8003c2e: 2210 movs r2, #16
|
|
8003c30: 6a19 ldr r1, [r3, #32]
|
|
8003c32: 4391 bics r1, r2
|
|
8003c34: 6219 str r1, [r3, #32]
|
|
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
|
8003c36: 6a19 ldr r1, [r3, #32]
|
|
8003c38: 430a orrs r2, r1
|
|
8003c3a: e7e5 b.n 8003c08 <HAL_TIM_Encoder_Start+0x4a>
|
|
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
8003c3c: 2801 cmp r0, #1
|
|
8003c3e: d114 bne.n 8003c6a <HAL_TIM_Encoder_Start+0xac>
|
|
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
8003c40: 9901 ldr r1, [sp, #4]
|
|
8003c42: 2901 cmp r1, #1
|
|
8003c44: d1e6 bne.n 8003c14 <HAL_TIM_Encoder_Start+0x56>
|
|
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
|
|
8003c46: 2c01 cmp r4, #1
|
|
8003c48: d1e4 bne.n 8003c14 <HAL_TIM_Encoder_Start+0x56>
|
|
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
|
|
8003c4a: 2a01 cmp r2, #1
|
|
8003c4c: d1e2 bne.n 8003c14 <HAL_TIM_Encoder_Start+0x56>
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8003c4e: 4660 mov r0, ip
|
|
8003c50: 3101 adds r1, #1
|
|
8003c52: 7001 strb r1, [r0, #0]
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8003c54: 7039 strb r1, [r7, #0]
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8003c56: 7031 strb r1, [r6, #0]
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8003c58: 7029 strb r1, [r5, #0]
|
|
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
|
|
8003c5a: 681b ldr r3, [r3, #0]
|
|
TIMx->CCER &= ~tmp;
|
|
8003c5c: 6a19 ldr r1, [r3, #32]
|
|
8003c5e: 4391 bics r1, r2
|
|
8003c60: 6219 str r1, [r3, #32]
|
|
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
|
8003c62: 6a19 ldr r1, [r3, #32]
|
|
8003c64: 430a orrs r2, r1
|
|
8003c66: 621a str r2, [r3, #32]
|
|
8003c68: e7e1 b.n 8003c2e <HAL_TIM_Encoder_Start+0x70>
|
|
return HAL_ERROR;
|
|
8003c6a: 2001 movs r0, #1
|
|
8003c6c: e7d2 b.n 8003c14 <HAL_TIM_Encoder_Start+0x56>
|
|
|
|
08003c6e <HAL_TIM_OC_DelayElapsedCallback>:
|
|
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
|
|
8003c6e: 4770 bx lr
|
|
|
|
08003c70 <HAL_TIM_IC_CaptureCallback>:
|
|
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
|
|
8003c70: 4770 bx lr
|
|
|
|
08003c72 <HAL_TIM_PWM_PulseFinishedCallback>:
|
|
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
|
|
8003c72: 4770 bx lr
|
|
|
|
08003c74 <HAL_TIM_TriggerCallback>:
|
|
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
|
|
8003c74: 4770 bx lr
|
|
...
|
|
|
|
08003c78 <HAL_TIM_IRQHandler>:
|
|
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
|
|
8003c78: 2202 movs r2, #2
|
|
uint32_t itsource = htim->Instance->DIER;
|
|
8003c7a: 6803 ldr r3, [r0, #0]
|
|
{
|
|
8003c7c: b570 push {r4, r5, r6, lr}
|
|
uint32_t itsource = htim->Instance->DIER;
|
|
8003c7e: 68dd ldr r5, [r3, #12]
|
|
uint32_t itflag = htim->Instance->SR;
|
|
8003c80: 691e ldr r6, [r3, #16]
|
|
{
|
|
8003c82: 0004 movs r4, r0
|
|
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
|
|
8003c84: 4216 tst r6, r2
|
|
8003c86: d00d beq.n 8003ca4 <HAL_TIM_IRQHandler+0x2c>
|
|
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
|
|
8003c88: 4215 tst r5, r2
|
|
8003c8a: d00b beq.n 8003ca4 <HAL_TIM_IRQHandler+0x2c>
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
|
|
8003c8c: 3a05 subs r2, #5
|
|
8003c8e: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
|
8003c90: 3204 adds r2, #4
|
|
8003c92: 7702 strb r2, [r0, #28]
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
|
|
8003c94: 699b ldr r3, [r3, #24]
|
|
8003c96: 079b lsls r3, r3, #30
|
|
8003c98: d100 bne.n 8003c9c <HAL_TIM_IRQHandler+0x24>
|
|
8003c9a: e07c b.n 8003d96 <HAL_TIM_IRQHandler+0x11e>
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8003c9c: f7ff ffe8 bl 8003c70 <HAL_TIM_IC_CaptureCallback>
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8003ca0: 2300 movs r3, #0
|
|
8003ca2: 7723 strb r3, [r4, #28]
|
|
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
|
|
8003ca4: 2304 movs r3, #4
|
|
8003ca6: 421e tst r6, r3
|
|
8003ca8: d012 beq.n 8003cd0 <HAL_TIM_IRQHandler+0x58>
|
|
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
|
|
8003caa: 421d tst r5, r3
|
|
8003cac: d010 beq.n 8003cd0 <HAL_TIM_IRQHandler+0x58>
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
|
|
8003cae: 2205 movs r2, #5
|
|
8003cb0: 6823 ldr r3, [r4, #0]
|
|
8003cb2: 4252 negs r2, r2
|
|
8003cb4: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
|
8003cb6: 3207 adds r2, #7
|
|
8003cb8: 7722 strb r2, [r4, #28]
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
|
8003cba: 699a ldr r2, [r3, #24]
|
|
8003cbc: 23c0 movs r3, #192 @ 0xc0
|
|
8003cbe: 009b lsls r3, r3, #2
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8003cc0: 0020 movs r0, r4
|
|
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
|
8003cc2: 421a tst r2, r3
|
|
8003cc4: d100 bne.n 8003cc8 <HAL_TIM_IRQHandler+0x50>
|
|
8003cc6: e06c b.n 8003da2 <HAL_TIM_IRQHandler+0x12a>
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8003cc8: f7ff ffd2 bl 8003c70 <HAL_TIM_IC_CaptureCallback>
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8003ccc: 2300 movs r3, #0
|
|
8003cce: 7723 strb r3, [r4, #28]
|
|
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
|
|
8003cd0: 2308 movs r3, #8
|
|
8003cd2: 421e tst r6, r3
|
|
8003cd4: d00f beq.n 8003cf6 <HAL_TIM_IRQHandler+0x7e>
|
|
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
|
|
8003cd6: 421d tst r5, r3
|
|
8003cd8: d00d beq.n 8003cf6 <HAL_TIM_IRQHandler+0x7e>
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
|
|
8003cda: 2209 movs r2, #9
|
|
8003cdc: 6823 ldr r3, [r4, #0]
|
|
8003cde: 4252 negs r2, r2
|
|
8003ce0: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
|
8003ce2: 320d adds r2, #13
|
|
8003ce4: 7722 strb r2, [r4, #28]
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
|
8003ce6: 69db ldr r3, [r3, #28]
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8003ce8: 0020 movs r0, r4
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
|
8003cea: 079b lsls r3, r3, #30
|
|
8003cec: d05f beq.n 8003dae <HAL_TIM_IRQHandler+0x136>
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8003cee: f7ff ffbf bl 8003c70 <HAL_TIM_IC_CaptureCallback>
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8003cf2: 2300 movs r3, #0
|
|
8003cf4: 7723 strb r3, [r4, #28]
|
|
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
|
|
8003cf6: 2310 movs r3, #16
|
|
8003cf8: 421e tst r6, r3
|
|
8003cfa: d011 beq.n 8003d20 <HAL_TIM_IRQHandler+0xa8>
|
|
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
|
|
8003cfc: 421d tst r5, r3
|
|
8003cfe: d00f beq.n 8003d20 <HAL_TIM_IRQHandler+0xa8>
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
|
|
8003d00: 2211 movs r2, #17
|
|
8003d02: 6823 ldr r3, [r4, #0]
|
|
8003d04: 4252 negs r2, r2
|
|
8003d06: 611a str r2, [r3, #16]
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
|
8003d08: 3219 adds r2, #25
|
|
8003d0a: 7722 strb r2, [r4, #28]
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
|
8003d0c: 69da ldr r2, [r3, #28]
|
|
8003d0e: 23c0 movs r3, #192 @ 0xc0
|
|
8003d10: 009b lsls r3, r3, #2
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8003d12: 0020 movs r0, r4
|
|
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
|
8003d14: 421a tst r2, r3
|
|
8003d16: d050 beq.n 8003dba <HAL_TIM_IRQHandler+0x142>
|
|
HAL_TIM_IC_CaptureCallback(htim);
|
|
8003d18: f7ff ffaa bl 8003c70 <HAL_TIM_IC_CaptureCallback>
|
|
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
|
|
8003d1c: 2300 movs r3, #0
|
|
8003d1e: 7723 strb r3, [r4, #28]
|
|
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
|
|
8003d20: 2301 movs r3, #1
|
|
8003d22: 421e tst r6, r3
|
|
8003d24: d008 beq.n 8003d38 <HAL_TIM_IRQHandler+0xc0>
|
|
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
|
|
8003d26: 421d tst r5, r3
|
|
8003d28: d006 beq.n 8003d38 <HAL_TIM_IRQHandler+0xc0>
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
|
|
8003d2a: 2202 movs r2, #2
|
|
8003d2c: 6823 ldr r3, [r4, #0]
|
|
8003d2e: 4252 negs r2, r2
|
|
HAL_TIM_PeriodElapsedCallback(htim);
|
|
8003d30: 0020 movs r0, r4
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
|
|
8003d32: 611a str r2, [r3, #16]
|
|
HAL_TIM_PeriodElapsedCallback(htim);
|
|
8003d34: f7fc fd56 bl 80007e4 <HAL_TIM_PeriodElapsedCallback>
|
|
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
|
|
8003d38: 2382 movs r3, #130 @ 0x82
|
|
8003d3a: 019b lsls r3, r3, #6
|
|
8003d3c: 421e tst r6, r3
|
|
8003d3e: d007 beq.n 8003d50 <HAL_TIM_IRQHandler+0xd8>
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
8003d40: 062b lsls r3, r5, #24
|
|
8003d42: d505 bpl.n 8003d50 <HAL_TIM_IRQHandler+0xd8>
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
|
|
8003d44: 6823 ldr r3, [r4, #0]
|
|
8003d46: 4a20 ldr r2, [pc, #128] @ (8003dc8 <HAL_TIM_IRQHandler+0x150>)
|
|
HAL_TIMEx_BreakCallback(htim);
|
|
8003d48: 0020 movs r0, r4
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
|
|
8003d4a: 611a str r2, [r3, #16]
|
|
HAL_TIMEx_BreakCallback(htim);
|
|
8003d4c: f000 fbb5 bl 80044ba <HAL_TIMEx_BreakCallback>
|
|
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
|
|
8003d50: 05f3 lsls r3, r6, #23
|
|
8003d52: d507 bpl.n 8003d64 <HAL_TIM_IRQHandler+0xec>
|
|
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
|
8003d54: 062b lsls r3, r5, #24
|
|
8003d56: d505 bpl.n 8003d64 <HAL_TIM_IRQHandler+0xec>
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
|
|
8003d58: 6823 ldr r3, [r4, #0]
|
|
8003d5a: 4a1c ldr r2, [pc, #112] @ (8003dcc <HAL_TIM_IRQHandler+0x154>)
|
|
HAL_TIMEx_Break2Callback(htim);
|
|
8003d5c: 0020 movs r0, r4
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
|
|
8003d5e: 611a str r2, [r3, #16]
|
|
HAL_TIMEx_Break2Callback(htim);
|
|
8003d60: f000 fbac bl 80044bc <HAL_TIMEx_Break2Callback>
|
|
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
|
|
8003d64: 2340 movs r3, #64 @ 0x40
|
|
8003d66: 421e tst r6, r3
|
|
8003d68: d008 beq.n 8003d7c <HAL_TIM_IRQHandler+0x104>
|
|
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
|
|
8003d6a: 421d tst r5, r3
|
|
8003d6c: d006 beq.n 8003d7c <HAL_TIM_IRQHandler+0x104>
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
|
|
8003d6e: 2241 movs r2, #65 @ 0x41
|
|
8003d70: 6823 ldr r3, [r4, #0]
|
|
8003d72: 4252 negs r2, r2
|
|
HAL_TIM_TriggerCallback(htim);
|
|
8003d74: 0020 movs r0, r4
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
|
|
8003d76: 611a str r2, [r3, #16]
|
|
HAL_TIM_TriggerCallback(htim);
|
|
8003d78: f7ff ff7c bl 8003c74 <HAL_TIM_TriggerCallback>
|
|
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
|
|
8003d7c: 2320 movs r3, #32
|
|
8003d7e: 421e tst r6, r3
|
|
8003d80: d008 beq.n 8003d94 <HAL_TIM_IRQHandler+0x11c>
|
|
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
|
|
8003d82: 421d tst r5, r3
|
|
8003d84: d006 beq.n 8003d94 <HAL_TIM_IRQHandler+0x11c>
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
|
|
8003d86: 2221 movs r2, #33 @ 0x21
|
|
8003d88: 6823 ldr r3, [r4, #0]
|
|
8003d8a: 4252 negs r2, r2
|
|
HAL_TIMEx_CommutCallback(htim);
|
|
8003d8c: 0020 movs r0, r4
|
|
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
|
|
8003d8e: 611a str r2, [r3, #16]
|
|
HAL_TIMEx_CommutCallback(htim);
|
|
8003d90: f000 fb92 bl 80044b8 <HAL_TIMEx_CommutCallback>
|
|
}
|
|
8003d94: bd70 pop {r4, r5, r6, pc}
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8003d96: f7ff ff6a bl 8003c6e <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8003d9a: 0020 movs r0, r4
|
|
8003d9c: f7ff ff69 bl 8003c72 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
8003da0: e77e b.n 8003ca0 <HAL_TIM_IRQHandler+0x28>
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8003da2: f7ff ff64 bl 8003c6e <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8003da6: 0020 movs r0, r4
|
|
8003da8: f7ff ff63 bl 8003c72 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
8003dac: e78e b.n 8003ccc <HAL_TIM_IRQHandler+0x54>
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8003dae: f7ff ff5e bl 8003c6e <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8003db2: 0020 movs r0, r4
|
|
8003db4: f7ff ff5d bl 8003c72 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
8003db8: e79b b.n 8003cf2 <HAL_TIM_IRQHandler+0x7a>
|
|
HAL_TIM_OC_DelayElapsedCallback(htim);
|
|
8003dba: f7ff ff58 bl 8003c6e <HAL_TIM_OC_DelayElapsedCallback>
|
|
HAL_TIM_PWM_PulseFinishedCallback(htim);
|
|
8003dbe: 0020 movs r0, r4
|
|
8003dc0: f7ff ff57 bl 8003c72 <HAL_TIM_PWM_PulseFinishedCallback>
|
|
8003dc4: e7aa b.n 8003d1c <HAL_TIM_IRQHandler+0xa4>
|
|
8003dc6: 46c0 nop @ (mov r8, r8)
|
|
8003dc8: ffffdf7f .word 0xffffdf7f
|
|
8003dcc: fffffeff .word 0xfffffeff
|
|
|
|
08003dd0 <TIM_Base_SetConfig>:
|
|
{
|
|
8003dd0: b510 push {r4, lr}
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8003dd2: 4c1b ldr r4, [pc, #108] @ (8003e40 <TIM_Base_SetConfig+0x70>)
|
|
tmpcr1 = TIMx->CR1;
|
|
8003dd4: 6803 ldr r3, [r0, #0]
|
|
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
|
|
8003dd6: 42a0 cmp r0, r4
|
|
8003dd8: d006 beq.n 8003de8 <TIM_Base_SetConfig+0x18>
|
|
8003dda: 2280 movs r2, #128 @ 0x80
|
|
8003ddc: 05d2 lsls r2, r2, #23
|
|
8003dde: 4290 cmp r0, r2
|
|
8003de0: d002 beq.n 8003de8 <TIM_Base_SetConfig+0x18>
|
|
8003de2: 4a18 ldr r2, [pc, #96] @ (8003e44 <TIM_Base_SetConfig+0x74>)
|
|
8003de4: 4290 cmp r0, r2
|
|
8003de6: d108 bne.n 8003dfa <TIM_Base_SetConfig+0x2a>
|
|
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
|
|
8003de8: 2270 movs r2, #112 @ 0x70
|
|
8003dea: 4393 bics r3, r2
|
|
tmpcr1 |= Structure->CounterMode;
|
|
8003dec: 684a ldr r2, [r1, #4]
|
|
8003dee: 4313 orrs r3, r2
|
|
tmpcr1 &= ~TIM_CR1_CKD;
|
|
8003df0: 4a15 ldr r2, [pc, #84] @ (8003e48 <TIM_Base_SetConfig+0x78>)
|
|
8003df2: 401a ands r2, r3
|
|
tmpcr1 |= (uint32_t)Structure->ClockDivision;
|
|
8003df4: 68cb ldr r3, [r1, #12]
|
|
8003df6: 4313 orrs r3, r2
|
|
8003df8: e008 b.n 8003e0c <TIM_Base_SetConfig+0x3c>
|
|
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
|
|
8003dfa: 4a14 ldr r2, [pc, #80] @ (8003e4c <TIM_Base_SetConfig+0x7c>)
|
|
8003dfc: 4290 cmp r0, r2
|
|
8003dfe: d0f7 beq.n 8003df0 <TIM_Base_SetConfig+0x20>
|
|
8003e00: 4a13 ldr r2, [pc, #76] @ (8003e50 <TIM_Base_SetConfig+0x80>)
|
|
8003e02: 4290 cmp r0, r2
|
|
8003e04: d0f4 beq.n 8003df0 <TIM_Base_SetConfig+0x20>
|
|
8003e06: 4a13 ldr r2, [pc, #76] @ (8003e54 <TIM_Base_SetConfig+0x84>)
|
|
8003e08: 4290 cmp r0, r2
|
|
8003e0a: d0f1 beq.n 8003df0 <TIM_Base_SetConfig+0x20>
|
|
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
|
|
8003e0c: 2280 movs r2, #128 @ 0x80
|
|
8003e0e: 4393 bics r3, r2
|
|
8003e10: 694a ldr r2, [r1, #20]
|
|
8003e12: 4313 orrs r3, r2
|
|
TIMx->ARR = (uint32_t)Structure->Period ;
|
|
8003e14: 688a ldr r2, [r1, #8]
|
|
8003e16: 62c2 str r2, [r0, #44] @ 0x2c
|
|
TIMx->PSC = Structure->Prescaler;
|
|
8003e18: 680a ldr r2, [r1, #0]
|
|
8003e1a: 6282 str r2, [r0, #40] @ 0x28
|
|
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
|
|
8003e1c: 42a0 cmp r0, r4
|
|
8003e1e: d005 beq.n 8003e2c <TIM_Base_SetConfig+0x5c>
|
|
8003e20: 4a0b ldr r2, [pc, #44] @ (8003e50 <TIM_Base_SetConfig+0x80>)
|
|
8003e22: 4290 cmp r0, r2
|
|
8003e24: d002 beq.n 8003e2c <TIM_Base_SetConfig+0x5c>
|
|
8003e26: 4a0b ldr r2, [pc, #44] @ (8003e54 <TIM_Base_SetConfig+0x84>)
|
|
8003e28: 4290 cmp r0, r2
|
|
8003e2a: d101 bne.n 8003e30 <TIM_Base_SetConfig+0x60>
|
|
TIMx->RCR = Structure->RepetitionCounter;
|
|
8003e2c: 690a ldr r2, [r1, #16]
|
|
8003e2e: 6302 str r2, [r0, #48] @ 0x30
|
|
SET_BIT(TIMx->CR1, TIM_CR1_URS);
|
|
8003e30: 2204 movs r2, #4
|
|
8003e32: 6801 ldr r1, [r0, #0]
|
|
8003e34: 430a orrs r2, r1
|
|
8003e36: 6002 str r2, [r0, #0]
|
|
TIMx->EGR = TIM_EGR_UG;
|
|
8003e38: 2201 movs r2, #1
|
|
8003e3a: 6142 str r2, [r0, #20]
|
|
TIMx->CR1 = tmpcr1;
|
|
8003e3c: 6003 str r3, [r0, #0]
|
|
}
|
|
8003e3e: bd10 pop {r4, pc}
|
|
8003e40: 40012c00 .word 0x40012c00
|
|
8003e44: 40000400 .word 0x40000400
|
|
8003e48: fffffcff .word 0xfffffcff
|
|
8003e4c: 40002000 .word 0x40002000
|
|
8003e50: 40014400 .word 0x40014400
|
|
8003e54: 40014800 .word 0x40014800
|
|
|
|
08003e58 <HAL_TIM_Base_Init>:
|
|
{
|
|
8003e58: b570 push {r4, r5, r6, lr}
|
|
8003e5a: 0004 movs r4, r0
|
|
return HAL_ERROR;
|
|
8003e5c: 2001 movs r0, #1
|
|
if (htim == NULL)
|
|
8003e5e: 2c00 cmp r4, #0
|
|
8003e60: d023 beq.n 8003eaa <HAL_TIM_Base_Init+0x52>
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8003e62: 0025 movs r5, r4
|
|
8003e64: 353d adds r5, #61 @ 0x3d
|
|
8003e66: 782b ldrb r3, [r5, #0]
|
|
8003e68: b2da uxtb r2, r3
|
|
8003e6a: 2b00 cmp r3, #0
|
|
8003e6c: d105 bne.n 8003e7a <HAL_TIM_Base_Init+0x22>
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8003e6e: 0023 movs r3, r4
|
|
8003e70: 333c adds r3, #60 @ 0x3c
|
|
HAL_TIM_Base_MspInit(htim);
|
|
8003e72: 0020 movs r0, r4
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8003e74: 701a strb r2, [r3, #0]
|
|
HAL_TIM_Base_MspInit(htim);
|
|
8003e76: f7fe fb35 bl 80024e4 <HAL_TIM_Base_MspInit>
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8003e7a: 2302 movs r3, #2
|
|
8003e7c: 702b strb r3, [r5, #0]
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8003e7e: 6820 ldr r0, [r4, #0]
|
|
8003e80: 1d21 adds r1, r4, #4
|
|
8003e82: f7ff ffa5 bl 8003dd0 <TIM_Base_SetConfig>
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8003e86: 0022 movs r2, r4
|
|
8003e88: 2301 movs r3, #1
|
|
return HAL_OK;
|
|
8003e8a: 2000 movs r0, #0
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8003e8c: 3248 adds r2, #72 @ 0x48
|
|
8003e8e: 7013 strb r3, [r2, #0]
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8003e90: 3447 adds r4, #71 @ 0x47
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8003e92: 3a0a subs r2, #10
|
|
8003e94: 7013 strb r3, [r2, #0]
|
|
8003e96: 7053 strb r3, [r2, #1]
|
|
8003e98: 7093 strb r3, [r2, #2]
|
|
8003e9a: 70d3 strb r3, [r2, #3]
|
|
8003e9c: 7113 strb r3, [r2, #4]
|
|
8003e9e: 7153 strb r3, [r2, #5]
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8003ea0: 7193 strb r3, [r2, #6]
|
|
8003ea2: 71d3 strb r3, [r2, #7]
|
|
8003ea4: 7213 strb r3, [r2, #8]
|
|
8003ea6: 7023 strb r3, [r4, #0]
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8003ea8: 702b strb r3, [r5, #0]
|
|
}
|
|
8003eaa: bd70 pop {r4, r5, r6, pc}
|
|
|
|
08003eac <HAL_TIM_PWM_Init>:
|
|
{
|
|
8003eac: b570 push {r4, r5, r6, lr}
|
|
8003eae: 0004 movs r4, r0
|
|
return HAL_ERROR;
|
|
8003eb0: 2001 movs r0, #1
|
|
if (htim == NULL)
|
|
8003eb2: 2c00 cmp r4, #0
|
|
8003eb4: d023 beq.n 8003efe <HAL_TIM_PWM_Init+0x52>
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8003eb6: 0025 movs r5, r4
|
|
8003eb8: 353d adds r5, #61 @ 0x3d
|
|
8003eba: 782b ldrb r3, [r5, #0]
|
|
8003ebc: b2da uxtb r2, r3
|
|
8003ebe: 2b00 cmp r3, #0
|
|
8003ec0: d105 bne.n 8003ece <HAL_TIM_PWM_Init+0x22>
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8003ec2: 0023 movs r3, r4
|
|
8003ec4: 333c adds r3, #60 @ 0x3c
|
|
HAL_TIM_PWM_MspInit(htim);
|
|
8003ec6: 0020 movs r0, r4
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8003ec8: 701a strb r2, [r3, #0]
|
|
HAL_TIM_PWM_MspInit(htim);
|
|
8003eca: f7ff fe77 bl 8003bbc <HAL_TIM_PWM_MspInit>
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8003ece: 2302 movs r3, #2
|
|
8003ed0: 702b strb r3, [r5, #0]
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8003ed2: 6820 ldr r0, [r4, #0]
|
|
8003ed4: 1d21 adds r1, r4, #4
|
|
8003ed6: f7ff ff7b bl 8003dd0 <TIM_Base_SetConfig>
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8003eda: 0022 movs r2, r4
|
|
8003edc: 2301 movs r3, #1
|
|
return HAL_OK;
|
|
8003ede: 2000 movs r0, #0
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8003ee0: 3248 adds r2, #72 @ 0x48
|
|
8003ee2: 7013 strb r3, [r2, #0]
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8003ee4: 3447 adds r4, #71 @ 0x47
|
|
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8003ee6: 3a0a subs r2, #10
|
|
8003ee8: 7013 strb r3, [r2, #0]
|
|
8003eea: 7053 strb r3, [r2, #1]
|
|
8003eec: 7093 strb r3, [r2, #2]
|
|
8003eee: 70d3 strb r3, [r2, #3]
|
|
8003ef0: 7113 strb r3, [r2, #4]
|
|
8003ef2: 7153 strb r3, [r2, #5]
|
|
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
|
|
8003ef4: 7193 strb r3, [r2, #6]
|
|
8003ef6: 71d3 strb r3, [r2, #7]
|
|
8003ef8: 7213 strb r3, [r2, #8]
|
|
8003efa: 7023 strb r3, [r4, #0]
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8003efc: 702b strb r3, [r5, #0]
|
|
}
|
|
8003efe: bd70 pop {r4, r5, r6, pc}
|
|
|
|
08003f00 <HAL_TIM_Encoder_Init>:
|
|
{
|
|
8003f00: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
8003f02: 0004 movs r4, r0
|
|
8003f04: 000d movs r5, r1
|
|
return HAL_ERROR;
|
|
8003f06: 2001 movs r0, #1
|
|
if (htim == NULL)
|
|
8003f08: 2c00 cmp r4, #0
|
|
8003f0a: d047 beq.n 8003f9c <HAL_TIM_Encoder_Init+0x9c>
|
|
if (htim->State == HAL_TIM_STATE_RESET)
|
|
8003f0c: 0026 movs r6, r4
|
|
8003f0e: 363d adds r6, #61 @ 0x3d
|
|
8003f10: 7833 ldrb r3, [r6, #0]
|
|
8003f12: b2da uxtb r2, r3
|
|
8003f14: 2b00 cmp r3, #0
|
|
8003f16: d105 bne.n 8003f24 <HAL_TIM_Encoder_Init+0x24>
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8003f18: 0023 movs r3, r4
|
|
8003f1a: 333c adds r3, #60 @ 0x3c
|
|
HAL_TIM_Encoder_MspInit(htim);
|
|
8003f1c: 0020 movs r0, r4
|
|
htim->Lock = HAL_UNLOCKED;
|
|
8003f1e: 701a strb r2, [r3, #0]
|
|
HAL_TIM_Encoder_MspInit(htim);
|
|
8003f20: f7fe fb3a bl 8002598 <HAL_TIM_Encoder_MspInit>
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8003f24: 2302 movs r3, #2
|
|
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
|
|
8003f26: 0021 movs r1, r4
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8003f28: 7033 strb r3, [r6, #0]
|
|
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
|
|
8003f2a: c980 ldmia r1!, {r7}
|
|
8003f2c: 4a1c ldr r2, [pc, #112] @ (8003fa0 <HAL_TIM_Encoder_Init+0xa0>)
|
|
8003f2e: 68bb ldr r3, [r7, #8]
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8003f30: 0038 movs r0, r7
|
|
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
|
|
8003f32: 4013 ands r3, r2
|
|
8003f34: 60bb str r3, [r7, #8]
|
|
TIM_Base_SetConfig(htim->Instance, &htim->Init);
|
|
8003f36: f7ff ff4b bl 8003dd0 <TIM_Base_SetConfig>
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8003f3a: 68b9 ldr r1, [r7, #8]
|
|
tmpsmcr |= sConfig->EncoderMode;
|
|
8003f3c: 682a ldr r2, [r5, #0]
|
|
tmpccmr1 = htim->Instance->CCMR1;
|
|
8003f3e: 69bb ldr r3, [r7, #24]
|
|
tmpsmcr |= sConfig->EncoderMode;
|
|
8003f40: 4311 orrs r1, r2
|
|
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
|
|
8003f42: 4a18 ldr r2, [pc, #96] @ (8003fa4 <HAL_TIM_Encoder_Init+0xa4>)
|
|
tmpsmcr |= sConfig->EncoderMode;
|
|
8003f44: 9101 str r1, [sp, #4]
|
|
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
|
|
8003f46: 4013 ands r3, r2
|
|
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
|
|
8003f48: 69aa ldr r2, [r5, #24]
|
|
8003f4a: 68a9 ldr r1, [r5, #8]
|
|
8003f4c: 0212 lsls r2, r2, #8
|
|
8003f4e: 430a orrs r2, r1
|
|
8003f50: 431a orrs r2, r3
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
|
|
8003f52: 4b15 ldr r3, [pc, #84] @ (8003fa8 <HAL_TIM_Encoder_Init+0xa8>)
|
|
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
|
|
8003f54: 6929 ldr r1, [r5, #16]
|
|
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
|
|
8003f56: 401a ands r2, r3
|
|
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
|
|
8003f58: 69eb ldr r3, [r5, #28]
|
|
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
|
|
8003f5a: 0109 lsls r1, r1, #4
|
|
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
|
|
8003f5c: 021b lsls r3, r3, #8
|
|
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
|
|
8003f5e: 430b orrs r3, r1
|
|
8003f60: 68e9 ldr r1, [r5, #12]
|
|
tmpccer = htim->Instance->CCER;
|
|
8003f62: 6a38 ldr r0, [r7, #32]
|
|
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
|
|
8003f64: 430b orrs r3, r1
|
|
8003f66: 6a29 ldr r1, [r5, #32]
|
|
8003f68: 0309 lsls r1, r1, #12
|
|
8003f6a: 430b orrs r3, r1
|
|
8003f6c: 4313 orrs r3, r2
|
|
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
|
|
8003f6e: 22aa movs r2, #170 @ 0xaa
|
|
8003f70: 4390 bics r0, r2
|
|
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
|
|
8003f72: 696a ldr r2, [r5, #20]
|
|
8003f74: 686d ldr r5, [r5, #4]
|
|
8003f76: 0112 lsls r2, r2, #4
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8003f78: 9901 ldr r1, [sp, #4]
|
|
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
|
|
8003f7a: 432a orrs r2, r5
|
|
8003f7c: 4302 orrs r2, r0
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
8003f7e: 60b9 str r1, [r7, #8]
|
|
htim->Instance->CCMR1 = tmpccmr1;
|
|
8003f80: 61bb str r3, [r7, #24]
|
|
htim->Instance->CCER = tmpccer;
|
|
8003f82: 623a str r2, [r7, #32]
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8003f84: 0022 movs r2, r4
|
|
8003f86: 2301 movs r3, #1
|
|
return HAL_OK;
|
|
8003f88: 2000 movs r0, #0
|
|
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
|
|
8003f8a: 3248 adds r2, #72 @ 0x48
|
|
8003f8c: 7013 strb r3, [r2, #0]
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
8003f8e: 3445 adds r4, #69 @ 0x45
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
8003f90: 3a0a subs r2, #10
|
|
8003f92: 7013 strb r3, [r2, #0]
|
|
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
8003f94: 7053 strb r3, [r2, #1]
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
|
|
8003f96: 7193 strb r3, [r2, #6]
|
|
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
|
|
8003f98: 7023 strb r3, [r4, #0]
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
8003f9a: 7033 strb r3, [r6, #0]
|
|
}
|
|
8003f9c: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
|
|
8003f9e: 46c0 nop @ (mov r8, r8)
|
|
8003fa0: fffebff8 .word 0xfffebff8
|
|
8003fa4: fffffcfc .word 0xfffffcfc
|
|
8003fa8: ffff0303 .word 0xffff0303
|
|
|
|
08003fac <TIM_OC2_SetConfig>:
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8003fac: 2210 movs r2, #16
|
|
{
|
|
8003fae: b570 push {r4, r5, r6, lr}
|
|
tmpccer = TIMx->CCER;
|
|
8003fb0: 6a05 ldr r5, [r0, #32]
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8003fb2: 6a03 ldr r3, [r0, #32]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
8003fb4: 4c16 ldr r4, [pc, #88] @ (8004010 <TIM_OC2_SetConfig+0x64>)
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8003fb6: 4393 bics r3, r2
|
|
8003fb8: 6203 str r3, [r0, #32]
|
|
tmpcr2 = TIMx->CR2;
|
|
8003fba: 6842 ldr r2, [r0, #4]
|
|
tmpccmrx = TIMx->CCMR1;
|
|
8003fbc: 6983 ldr r3, [r0, #24]
|
|
tmpccmrx &= ~TIM_CCMR1_CC2S;
|
|
8003fbe: 4023 ands r3, r4
|
|
tmpccmrx |= (OC_Config->OCMode << 8U);
|
|
8003fc0: 680c ldr r4, [r1, #0]
|
|
8003fc2: 0224 lsls r4, r4, #8
|
|
8003fc4: 431c orrs r4, r3
|
|
tmpccer &= ~TIM_CCER_CC2P;
|
|
8003fc6: 2320 movs r3, #32
|
|
8003fc8: 439d bics r5, r3
|
|
tmpccer |= (OC_Config->OCPolarity << 4U);
|
|
8003fca: 688b ldr r3, [r1, #8]
|
|
8003fcc: 011b lsls r3, r3, #4
|
|
8003fce: 432b orrs r3, r5
|
|
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
|
|
8003fd0: 4d10 ldr r5, [pc, #64] @ (8004014 <TIM_OC2_SetConfig+0x68>)
|
|
8003fd2: 42a8 cmp r0, r5
|
|
8003fd4: d10f bne.n 8003ff6 <TIM_OC2_SetConfig+0x4a>
|
|
tmpccer &= ~TIM_CCER_CC2NP;
|
|
8003fd6: 2580 movs r5, #128 @ 0x80
|
|
8003fd8: 43ab bics r3, r5
|
|
8003fda: 001e movs r6, r3
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
8003fdc: 68cb ldr r3, [r1, #12]
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
8003fde: 3d40 subs r5, #64 @ 0x40
|
|
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
|
8003fe0: 011b lsls r3, r3, #4
|
|
8003fe2: 4333 orrs r3, r6
|
|
tmpccer &= ~TIM_CCER_CC2NE;
|
|
8003fe4: 43ab bics r3, r5
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
8003fe6: 4d0c ldr r5, [pc, #48] @ (8004018 <TIM_OC2_SetConfig+0x6c>)
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
8003fe8: 698e ldr r6, [r1, #24]
|
|
tmpcr2 &= ~TIM_CR2_OIS2N;
|
|
8003fea: 4015 ands r5, r2
|
|
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
|
|
8003fec: 694a ldr r2, [r1, #20]
|
|
8003fee: 4332 orrs r2, r6
|
|
8003ff0: 0092 lsls r2, r2, #2
|
|
8003ff2: 432a orrs r2, r5
|
|
8003ff4: e005 b.n 8004002 <TIM_OC2_SetConfig+0x56>
|
|
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
|
8003ff6: 4d09 ldr r5, [pc, #36] @ (800401c <TIM_OC2_SetConfig+0x70>)
|
|
8003ff8: 42a8 cmp r0, r5
|
|
8003ffa: d0f4 beq.n 8003fe6 <TIM_OC2_SetConfig+0x3a>
|
|
8003ffc: 4d08 ldr r5, [pc, #32] @ (8004020 <TIM_OC2_SetConfig+0x74>)
|
|
8003ffe: 42a8 cmp r0, r5
|
|
8004000: d0f1 beq.n 8003fe6 <TIM_OC2_SetConfig+0x3a>
|
|
TIMx->CR2 = tmpcr2;
|
|
8004002: 6042 str r2, [r0, #4]
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
8004004: 684a ldr r2, [r1, #4]
|
|
TIMx->CCMR1 = tmpccmrx;
|
|
8004006: 6184 str r4, [r0, #24]
|
|
TIMx->CCR2 = OC_Config->Pulse;
|
|
8004008: 6382 str r2, [r0, #56] @ 0x38
|
|
TIMx->CCER = tmpccer;
|
|
800400a: 6203 str r3, [r0, #32]
|
|
}
|
|
800400c: bd70 pop {r4, r5, r6, pc}
|
|
800400e: 46c0 nop @ (mov r8, r8)
|
|
8004010: feff8cff .word 0xfeff8cff
|
|
8004014: 40012c00 .word 0x40012c00
|
|
8004018: fffff3ff .word 0xfffff3ff
|
|
800401c: 40014400 .word 0x40014400
|
|
8004020: 40014800 .word 0x40014800
|
|
|
|
08004024 <HAL_TIM_PWM_ConfigChannel>:
|
|
{
|
|
8004024: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
__HAL_LOCK(htim);
|
|
8004026: 0007 movs r7, r0
|
|
8004028: 373c adds r7, #60 @ 0x3c
|
|
{
|
|
800402a: 0015 movs r5, r2
|
|
__HAL_LOCK(htim);
|
|
800402c: 783a ldrb r2, [r7, #0]
|
|
{
|
|
800402e: 0003 movs r3, r0
|
|
8004030: 000c movs r4, r1
|
|
__HAL_LOCK(htim);
|
|
8004032: 2002 movs r0, #2
|
|
8004034: 2a01 cmp r2, #1
|
|
8004036: d00c beq.n 8004052 <HAL_TIM_PWM_ConfigChannel+0x2e>
|
|
8004038: 3801 subs r0, #1
|
|
800403a: 7038 strb r0, [r7, #0]
|
|
switch (Channel)
|
|
800403c: 2d0c cmp r5, #12
|
|
800403e: d051 beq.n 80040e4 <HAL_TIM_PWM_ConfigChannel+0xc0>
|
|
8004040: d808 bhi.n 8004054 <HAL_TIM_PWM_ConfigChannel+0x30>
|
|
8004042: 2d04 cmp r5, #4
|
|
8004044: d02d beq.n 80040a2 <HAL_TIM_PWM_ConfigChannel+0x7e>
|
|
8004046: 2d08 cmp r5, #8
|
|
8004048: d03c beq.n 80040c4 <HAL_TIM_PWM_ConfigChannel+0xa0>
|
|
800404a: 2d00 cmp r5, #0
|
|
800404c: d017 beq.n 800407e <HAL_TIM_PWM_ConfigChannel+0x5a>
|
|
__HAL_UNLOCK(htim);
|
|
800404e: 2300 movs r3, #0
|
|
8004050: 703b strb r3, [r7, #0]
|
|
}
|
|
8004052: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
switch (Channel)
|
|
8004054: 2d10 cmp r5, #16
|
|
8004056: d058 beq.n 800410a <HAL_TIM_PWM_ConfigChannel+0xe6>
|
|
8004058: 2d14 cmp r5, #20
|
|
800405a: d1f8 bne.n 800404e <HAL_TIM_PWM_ConfigChannel+0x2a>
|
|
TIM_OC6_SetConfig(htim->Instance, sConfig);
|
|
800405c: 681d ldr r5, [r3, #0]
|
|
800405e: 0028 movs r0, r5
|
|
8004060: f7ff fd32 bl 8003ac8 <TIM_OC6_SetConfig>
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
|
|
8004064: 2380 movs r3, #128 @ 0x80
|
|
8004066: 6d6a ldr r2, [r5, #84] @ 0x54
|
|
8004068: 011b lsls r3, r3, #4
|
|
800406a: 4313 orrs r3, r2
|
|
800406c: 656b str r3, [r5, #84] @ 0x54
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
|
|
800406e: 6d6b ldr r3, [r5, #84] @ 0x54
|
|
8004070: 4a2e ldr r2, [pc, #184] @ (800412c <HAL_TIM_PWM_ConfigChannel+0x108>)
|
|
8004072: 4013 ands r3, r2
|
|
8004074: 656b str r3, [r5, #84] @ 0x54
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
|
|
8004076: 6923 ldr r3, [r4, #16]
|
|
8004078: 6d6a ldr r2, [r5, #84] @ 0x54
|
|
800407a: 021b lsls r3, r3, #8
|
|
800407c: e053 b.n 8004126 <HAL_TIM_PWM_ConfigChannel+0x102>
|
|
TIM_OC1_SetConfig(htim->Instance, sConfig);
|
|
800407e: 681d ldr r5, [r3, #0]
|
|
8004080: 0028 movs r0, r5
|
|
8004082: f7ff fc45 bl 8003910 <TIM_OC1_SetConfig>
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
8004086: 2308 movs r3, #8
|
|
8004088: 69aa ldr r2, [r5, #24]
|
|
800408a: 4313 orrs r3, r2
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
800408c: 2204 movs r2, #4
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
|
|
800408e: 61ab str r3, [r5, #24]
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
|
|
8004090: 69ab ldr r3, [r5, #24]
|
|
8004092: 4393 bics r3, r2
|
|
8004094: 61ab str r3, [r5, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode;
|
|
8004096: 69ab ldr r3, [r5, #24]
|
|
8004098: 6922 ldr r2, [r4, #16]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
|
|
800409a: 4313 orrs r3, r2
|
|
800409c: 61ab str r3, [r5, #24]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
800409e: 2000 movs r0, #0
|
|
80040a0: e7d5 b.n 800404e <HAL_TIM_PWM_ConfigChannel+0x2a>
|
|
TIM_OC2_SetConfig(htim->Instance, sConfig);
|
|
80040a2: 681d ldr r5, [r3, #0]
|
|
80040a4: 0028 movs r0, r5
|
|
80040a6: f7ff ff81 bl 8003fac <TIM_OC2_SetConfig>
|
|
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
|
|
80040aa: 2380 movs r3, #128 @ 0x80
|
|
80040ac: 69aa ldr r2, [r5, #24]
|
|
80040ae: 011b lsls r3, r3, #4
|
|
80040b0: 4313 orrs r3, r2
|
|
80040b2: 61ab str r3, [r5, #24]
|
|
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
|
|
80040b4: 69ab ldr r3, [r5, #24]
|
|
80040b6: 4a1d ldr r2, [pc, #116] @ (800412c <HAL_TIM_PWM_ConfigChannel+0x108>)
|
|
80040b8: 4013 ands r3, r2
|
|
80040ba: 61ab str r3, [r5, #24]
|
|
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
|
|
80040bc: 6923 ldr r3, [r4, #16]
|
|
80040be: 69aa ldr r2, [r5, #24]
|
|
80040c0: 021b lsls r3, r3, #8
|
|
80040c2: e7ea b.n 800409a <HAL_TIM_PWM_ConfigChannel+0x76>
|
|
TIM_OC3_SetConfig(htim->Instance, sConfig);
|
|
80040c4: 681e ldr r6, [r3, #0]
|
|
80040c6: 0030 movs r0, r6
|
|
80040c8: f7ff fc58 bl 800397c <TIM_OC3_SetConfig>
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
80040cc: 2204 movs r2, #4
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
|
|
80040ce: 69f3 ldr r3, [r6, #28]
|
|
80040d0: 431d orrs r5, r3
|
|
80040d2: 61f5 str r5, [r6, #28]
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
|
|
80040d4: 69f3 ldr r3, [r6, #28]
|
|
80040d6: 4393 bics r3, r2
|
|
80040d8: 61f3 str r3, [r6, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode;
|
|
80040da: 69f3 ldr r3, [r6, #28]
|
|
80040dc: 6922 ldr r2, [r4, #16]
|
|
80040de: 4313 orrs r3, r2
|
|
80040e0: 61f3 str r3, [r6, #28]
|
|
break;
|
|
80040e2: e7dc b.n 800409e <HAL_TIM_PWM_ConfigChannel+0x7a>
|
|
TIM_OC4_SetConfig(htim->Instance, sConfig);
|
|
80040e4: 681d ldr r5, [r3, #0]
|
|
80040e6: 0028 movs r0, r5
|
|
80040e8: f7ff fc8a bl 8003a00 <TIM_OC4_SetConfig>
|
|
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
|
|
80040ec: 2380 movs r3, #128 @ 0x80
|
|
80040ee: 69ea ldr r2, [r5, #28]
|
|
80040f0: 011b lsls r3, r3, #4
|
|
80040f2: 4313 orrs r3, r2
|
|
80040f4: 61eb str r3, [r5, #28]
|
|
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
|
|
80040f6: 69eb ldr r3, [r5, #28]
|
|
80040f8: 4a0c ldr r2, [pc, #48] @ (800412c <HAL_TIM_PWM_ConfigChannel+0x108>)
|
|
80040fa: 4013 ands r3, r2
|
|
80040fc: 61eb str r3, [r5, #28]
|
|
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
|
|
80040fe: 6923 ldr r3, [r4, #16]
|
|
8004100: 69ea ldr r2, [r5, #28]
|
|
8004102: 021b lsls r3, r3, #8
|
|
8004104: 4313 orrs r3, r2
|
|
8004106: 61eb str r3, [r5, #28]
|
|
break;
|
|
8004108: e7c9 b.n 800409e <HAL_TIM_PWM_ConfigChannel+0x7a>
|
|
TIM_OC5_SetConfig(htim->Instance, sConfig);
|
|
800410a: 681d ldr r5, [r3, #0]
|
|
800410c: 0028 movs r0, r5
|
|
800410e: f7ff fcab bl 8003a68 <TIM_OC5_SetConfig>
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
|
|
8004112: 2308 movs r3, #8
|
|
8004114: 6d6a ldr r2, [r5, #84] @ 0x54
|
|
8004116: 4313 orrs r3, r2
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
|
|
8004118: 2204 movs r2, #4
|
|
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
|
|
800411a: 656b str r3, [r5, #84] @ 0x54
|
|
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
|
|
800411c: 6d6b ldr r3, [r5, #84] @ 0x54
|
|
800411e: 4393 bics r3, r2
|
|
8004120: 656b str r3, [r5, #84] @ 0x54
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode;
|
|
8004122: 6d6b ldr r3, [r5, #84] @ 0x54
|
|
8004124: 6922 ldr r2, [r4, #16]
|
|
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
|
|
8004126: 4313 orrs r3, r2
|
|
8004128: 656b str r3, [r5, #84] @ 0x54
|
|
break;
|
|
800412a: e7b8 b.n 800409e <HAL_TIM_PWM_ConfigChannel+0x7a>
|
|
800412c: fffffbff .word 0xfffffbff
|
|
|
|
08004130 <TIM_ETR_SetConfig>:
|
|
{
|
|
8004130: b530 push {r4, r5, lr}
|
|
tmpsmcr = TIMx->SMCR;
|
|
8004132: 6884 ldr r4, [r0, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
8004134: 4d03 ldr r5, [pc, #12] @ (8004144 <TIM_ETR_SetConfig+0x14>)
|
|
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
|
|
8004136: 430a orrs r2, r1
|
|
8004138: 021b lsls r3, r3, #8
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
800413a: 402c ands r4, r5
|
|
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
|
|
800413c: 4313 orrs r3, r2
|
|
800413e: 4323 orrs r3, r4
|
|
TIMx->SMCR = tmpsmcr;
|
|
8004140: 6083 str r3, [r0, #8]
|
|
}
|
|
8004142: bd30 pop {r4, r5, pc}
|
|
8004144: ffff00ff .word 0xffff00ff
|
|
|
|
08004148 <HAL_TIM_ConfigClockSource>:
|
|
{
|
|
8004148: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
__HAL_LOCK(htim);
|
|
800414a: 0005 movs r5, r0
|
|
800414c: 2202 movs r2, #2
|
|
800414e: 353c adds r5, #60 @ 0x3c
|
|
8004150: 782c ldrb r4, [r5, #0]
|
|
{
|
|
8004152: 0003 movs r3, r0
|
|
__HAL_LOCK(htim);
|
|
8004154: 0010 movs r0, r2
|
|
8004156: 2c01 cmp r4, #1
|
|
8004158: d01b beq.n 8004192 <HAL_TIM_ConfigClockSource+0x4a>
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800415a: 001e movs r6, r3
|
|
__HAL_LOCK(htim);
|
|
800415c: 3801 subs r0, #1
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
800415e: 363d adds r6, #61 @ 0x3d
|
|
__HAL_LOCK(htim);
|
|
8004160: 7028 strb r0, [r5, #0]
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
8004162: 7032 strb r2, [r6, #0]
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8004164: 681c ldr r4, [r3, #0]
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
8004166: 4a41 ldr r2, [pc, #260] @ (800426c <HAL_TIM_ConfigClockSource+0x124>)
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
8004168: 68a3 ldr r3, [r4, #8]
|
|
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
|
|
800416a: 4013 ands r3, r2
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
800416c: 60a3 str r3, [r4, #8]
|
|
switch (sClockSourceConfig->ClockSource)
|
|
800416e: 680b ldr r3, [r1, #0]
|
|
8004170: 2b60 cmp r3, #96 @ 0x60
|
|
8004172: d04e beq.n 8004212 <HAL_TIM_ConfigClockSource+0xca>
|
|
8004174: d82d bhi.n 80041d2 <HAL_TIM_ConfigClockSource+0x8a>
|
|
8004176: 2b40 cmp r3, #64 @ 0x40
|
|
8004178: d062 beq.n 8004240 <HAL_TIM_ConfigClockSource+0xf8>
|
|
800417a: d813 bhi.n 80041a4 <HAL_TIM_ConfigClockSource+0x5c>
|
|
800417c: 2b20 cmp r3, #32
|
|
800417e: d00b beq.n 8004198 <HAL_TIM_ConfigClockSource+0x50>
|
|
8004180: d808 bhi.n 8004194 <HAL_TIM_ConfigClockSource+0x4c>
|
|
8004182: 2210 movs r2, #16
|
|
8004184: 0019 movs r1, r3
|
|
8004186: 4391 bics r1, r2
|
|
8004188: d006 beq.n 8004198 <HAL_TIM_ConfigClockSource+0x50>
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
800418a: 2301 movs r3, #1
|
|
800418c: 7033 strb r3, [r6, #0]
|
|
__HAL_UNLOCK(htim);
|
|
800418e: 2300 movs r3, #0
|
|
8004190: 702b strb r3, [r5, #0]
|
|
}
|
|
8004192: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
switch (sClockSourceConfig->ClockSource)
|
|
8004194: 2b30 cmp r3, #48 @ 0x30
|
|
8004196: d1f8 bne.n 800418a <HAL_TIM_ConfigClockSource+0x42>
|
|
tmpsmcr = TIMx->SMCR;
|
|
8004198: 68a2 ldr r2, [r4, #8]
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
800419a: 4935 ldr r1, [pc, #212] @ (8004270 <HAL_TIM_ConfigClockSource+0x128>)
|
|
800419c: 400a ands r2, r1
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
800419e: 4313 orrs r3, r2
|
|
80041a0: 2207 movs r2, #7
|
|
80041a2: e028 b.n 80041f6 <HAL_TIM_ConfigClockSource+0xae>
|
|
switch (sClockSourceConfig->ClockSource)
|
|
80041a4: 2b50 cmp r3, #80 @ 0x50
|
|
80041a6: d1f0 bne.n 800418a <HAL_TIM_ConfigClockSource+0x42>
|
|
sClockSourceConfig->ClockPolarity,
|
|
80041a8: 684a ldr r2, [r1, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
80041aa: 68cb ldr r3, [r1, #12]
|
|
tmpccer = TIMx->CCER;
|
|
80041ac: 6a21 ldr r1, [r4, #32]
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
80041ae: 6a27 ldr r7, [r4, #32]
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
80041b0: 011b lsls r3, r3, #4
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
80041b2: 4387 bics r7, r0
|
|
80041b4: 6227 str r7, [r4, #32]
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
80041b6: 27f0 movs r7, #240 @ 0xf0
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
80041b8: 69a0 ldr r0, [r4, #24]
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
80041ba: 43b8 bics r0, r7
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
80041bc: 4303 orrs r3, r0
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
80041be: 200a movs r0, #10
|
|
80041c0: 4381 bics r1, r0
|
|
tmpccer |= TIM_ICPolarity;
|
|
80041c2: 430a orrs r2, r1
|
|
TIMx->CCMR1 = tmpccmr1;
|
|
80041c4: 61a3 str r3, [r4, #24]
|
|
TIMx->CCER = tmpccer;
|
|
80041c6: 6222 str r2, [r4, #32]
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
80041c8: 4b29 ldr r3, [pc, #164] @ (8004270 <HAL_TIM_ConfigClockSource+0x128>)
|
|
tmpsmcr = TIMx->SMCR;
|
|
80041ca: 68a2 ldr r2, [r4, #8]
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
80041cc: 401a ands r2, r3
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
80041ce: 2357 movs r3, #87 @ 0x57
|
|
80041d0: e011 b.n 80041f6 <HAL_TIM_ConfigClockSource+0xae>
|
|
switch (sClockSourceConfig->ClockSource)
|
|
80041d2: 2280 movs r2, #128 @ 0x80
|
|
80041d4: 0152 lsls r2, r2, #5
|
|
80041d6: 4293 cmp r3, r2
|
|
80041d8: d00f beq.n 80041fa <HAL_TIM_ConfigClockSource+0xb2>
|
|
80041da: 2280 movs r2, #128 @ 0x80
|
|
80041dc: 0192 lsls r2, r2, #6
|
|
80041de: 4293 cmp r3, r2
|
|
80041e0: d00d beq.n 80041fe <HAL_TIM_ConfigClockSource+0xb6>
|
|
80041e2: 2b70 cmp r3, #112 @ 0x70
|
|
80041e4: d1d1 bne.n 800418a <HAL_TIM_ConfigClockSource+0x42>
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
80041e6: 68cb ldr r3, [r1, #12]
|
|
80041e8: 684a ldr r2, [r1, #4]
|
|
80041ea: 0020 movs r0, r4
|
|
80041ec: 6889 ldr r1, [r1, #8]
|
|
80041ee: f7ff ff9f bl 8004130 <TIM_ETR_SetConfig>
|
|
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
80041f2: 2377 movs r3, #119 @ 0x77
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80041f4: 68a2 ldr r2, [r4, #8]
|
|
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
|
|
80041f6: 4313 orrs r3, r2
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
80041f8: 60a3 str r3, [r4, #8]
|
|
HAL_StatusTypeDef status = HAL_OK;
|
|
80041fa: 2000 movs r0, #0
|
|
80041fc: e7c5 b.n 800418a <HAL_TIM_ConfigClockSource+0x42>
|
|
TIM_ETR_SetConfig(htim->Instance,
|
|
80041fe: 68cb ldr r3, [r1, #12]
|
|
8004200: 684a ldr r2, [r1, #4]
|
|
8004202: 0020 movs r0, r4
|
|
8004204: 6889 ldr r1, [r1, #8]
|
|
8004206: f7ff ff93 bl 8004130 <TIM_ETR_SetConfig>
|
|
htim->Instance->SMCR |= TIM_SMCR_ECE;
|
|
800420a: 2380 movs r3, #128 @ 0x80
|
|
800420c: 68a2 ldr r2, [r4, #8]
|
|
800420e: 01db lsls r3, r3, #7
|
|
8004210: e7f1 b.n 80041f6 <HAL_TIM_ConfigClockSource+0xae>
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
8004212: 2710 movs r7, #16
|
|
sClockSourceConfig->ClockPolarity,
|
|
8004214: 684b ldr r3, [r1, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8004216: 68ca ldr r2, [r1, #12]
|
|
tmpccer = TIMx->CCER;
|
|
8004218: 6a21 ldr r1, [r4, #32]
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
800421a: 6a20 ldr r0, [r4, #32]
|
|
tmpccmr1 |= (TIM_ICFilter << 12U);
|
|
800421c: 0312 lsls r2, r2, #12
|
|
TIMx->CCER &= ~TIM_CCER_CC2E;
|
|
800421e: 43b8 bics r0, r7
|
|
8004220: 6220 str r0, [r4, #32]
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
8004222: 69a0 ldr r0, [r4, #24]
|
|
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
8004224: 4f13 ldr r7, [pc, #76] @ (8004274 <HAL_TIM_ConfigClockSource+0x12c>)
|
|
tmpccer |= (TIM_ICPolarity << 4U);
|
|
8004226: 011b lsls r3, r3, #4
|
|
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
|
8004228: 4038 ands r0, r7
|
|
tmpccmr1 |= (TIM_ICFilter << 12U);
|
|
800422a: 4302 orrs r2, r0
|
|
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
|
|
800422c: 20a0 movs r0, #160 @ 0xa0
|
|
800422e: 4381 bics r1, r0
|
|
tmpccer |= (TIM_ICPolarity << 4U);
|
|
8004230: 430b orrs r3, r1
|
|
TIMx->CCMR1 = tmpccmr1 ;
|
|
8004232: 61a2 str r2, [r4, #24]
|
|
TIMx->CCER = tmpccer;
|
|
8004234: 6223 str r3, [r4, #32]
|
|
tmpsmcr = TIMx->SMCR;
|
|
8004236: 68a2 ldr r2, [r4, #8]
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
8004238: 4b0d ldr r3, [pc, #52] @ (8004270 <HAL_TIM_ConfigClockSource+0x128>)
|
|
800423a: 401a ands r2, r3
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
800423c: 2367 movs r3, #103 @ 0x67
|
|
800423e: e7da b.n 80041f6 <HAL_TIM_ConfigClockSource+0xae>
|
|
sClockSourceConfig->ClockPolarity,
|
|
8004240: 684a ldr r2, [r1, #4]
|
|
sClockSourceConfig->ClockFilter);
|
|
8004242: 68cb ldr r3, [r1, #12]
|
|
tmpccer = TIMx->CCER;
|
|
8004244: 6a21 ldr r1, [r4, #32]
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
8004246: 6a27 ldr r7, [r4, #32]
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
8004248: 011b lsls r3, r3, #4
|
|
TIMx->CCER &= ~TIM_CCER_CC1E;
|
|
800424a: 4387 bics r7, r0
|
|
800424c: 6227 str r7, [r4, #32]
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
800424e: 27f0 movs r7, #240 @ 0xf0
|
|
tmpccmr1 = TIMx->CCMR1;
|
|
8004250: 69a0 ldr r0, [r4, #24]
|
|
tmpccmr1 &= ~TIM_CCMR1_IC1F;
|
|
8004252: 43b8 bics r0, r7
|
|
tmpccmr1 |= (TIM_ICFilter << 4U);
|
|
8004254: 4303 orrs r3, r0
|
|
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
|
|
8004256: 200a movs r0, #10
|
|
8004258: 4381 bics r1, r0
|
|
tmpccer |= TIM_ICPolarity;
|
|
800425a: 430a orrs r2, r1
|
|
TIMx->CCMR1 = tmpccmr1;
|
|
800425c: 61a3 str r3, [r4, #24]
|
|
TIMx->CCER = tmpccer;
|
|
800425e: 6222 str r2, [r4, #32]
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
8004260: 4b03 ldr r3, [pc, #12] @ (8004270 <HAL_TIM_ConfigClockSource+0x128>)
|
|
tmpsmcr = TIMx->SMCR;
|
|
8004262: 68a2 ldr r2, [r4, #8]
|
|
tmpsmcr &= ~TIM_SMCR_TS;
|
|
8004264: 401a ands r2, r3
|
|
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
|
|
8004266: 2347 movs r3, #71 @ 0x47
|
|
8004268: e7c5 b.n 80041f6 <HAL_TIM_ConfigClockSource+0xae>
|
|
800426a: 46c0 nop @ (mov r8, r8)
|
|
800426c: ffce0088 .word 0xffce0088
|
|
8004270: ffcfff8f .word 0xffcfff8f
|
|
8004274: ffff0fff .word 0xffff0fff
|
|
|
|
08004278 <TIM_CCxChannelCmd>:
|
|
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
|
8004278: 231f movs r3, #31
|
|
{
|
|
800427a: b510 push {r4, lr}
|
|
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
|
800427c: 2401 movs r4, #1
|
|
800427e: 4019 ands r1, r3
|
|
8004280: 408c lsls r4, r1
|
|
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
|
8004282: 408a lsls r2, r1
|
|
TIMx->CCER &= ~tmp;
|
|
8004284: 6a03 ldr r3, [r0, #32]
|
|
8004286: 43a3 bics r3, r4
|
|
8004288: 6203 str r3, [r0, #32]
|
|
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
|
800428a: 6a03 ldr r3, [r0, #32]
|
|
800428c: 431a orrs r2, r3
|
|
800428e: 6202 str r2, [r0, #32]
|
|
}
|
|
8004290: bd10 pop {r4, pc}
|
|
...
|
|
|
|
08004294 <HAL_TIM_OC_Start>:
|
|
{
|
|
8004294: 0002 movs r2, r0
|
|
8004296: b510 push {r4, lr}
|
|
8004298: 2908 cmp r1, #8
|
|
800429a: d01c beq.n 80042d6 <HAL_TIM_OC_Start+0x42>
|
|
800429c: d806 bhi.n 80042ac <HAL_TIM_OC_Start+0x18>
|
|
800429e: 2900 cmp r1, #0
|
|
80042a0: d00b beq.n 80042ba <HAL_TIM_OC_Start+0x26>
|
|
80042a2: 2904 cmp r1, #4
|
|
80042a4: d014 beq.n 80042d0 <HAL_TIM_OC_Start+0x3c>
|
|
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
|
80042a6: 0013 movs r3, r2
|
|
80042a8: 3343 adds r3, #67 @ 0x43
|
|
80042aa: e008 b.n 80042be <HAL_TIM_OC_Start+0x2a>
|
|
80042ac: 290c cmp r1, #12
|
|
80042ae: d015 beq.n 80042dc <HAL_TIM_OC_Start+0x48>
|
|
80042b0: 2910 cmp r1, #16
|
|
80042b2: d1f8 bne.n 80042a6 <HAL_TIM_OC_Start+0x12>
|
|
80042b4: 0003 movs r3, r0
|
|
80042b6: 3342 adds r3, #66 @ 0x42
|
|
80042b8: e001 b.n 80042be <HAL_TIM_OC_Start+0x2a>
|
|
80042ba: 0003 movs r3, r0
|
|
80042bc: 333e adds r3, #62 @ 0x3e
|
|
80042be: 781b ldrb r3, [r3, #0]
|
|
80042c0: 3b01 subs r3, #1
|
|
80042c2: 1e58 subs r0, r3, #1
|
|
80042c4: 4183 sbcs r3, r0
|
|
80042c6: b2db uxtb r3, r3
|
|
return HAL_ERROR;
|
|
80042c8: 2001 movs r0, #1
|
|
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
|
80042ca: 2b00 cmp r3, #0
|
|
80042cc: d009 beq.n 80042e2 <HAL_TIM_OC_Start+0x4e>
|
|
}
|
|
80042ce: bd10 pop {r4, pc}
|
|
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
|
80042d0: 0003 movs r3, r0
|
|
80042d2: 333f adds r3, #63 @ 0x3f
|
|
80042d4: e7f3 b.n 80042be <HAL_TIM_OC_Start+0x2a>
|
|
80042d6: 0003 movs r3, r0
|
|
80042d8: 3340 adds r3, #64 @ 0x40
|
|
80042da: e7f0 b.n 80042be <HAL_TIM_OC_Start+0x2a>
|
|
80042dc: 0003 movs r3, r0
|
|
80042de: 3341 adds r3, #65 @ 0x41
|
|
80042e0: e7ed b.n 80042be <HAL_TIM_OC_Start+0x2a>
|
|
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
80042e2: 2302 movs r3, #2
|
|
80042e4: 2908 cmp r1, #8
|
|
80042e6: d030 beq.n 800434a <HAL_TIM_OC_Start+0xb6>
|
|
80042e8: d806 bhi.n 80042f8 <HAL_TIM_OC_Start+0x64>
|
|
80042ea: 2900 cmp r1, #0
|
|
80042ec: d00b beq.n 8004306 <HAL_TIM_OC_Start+0x72>
|
|
80042ee: 2904 cmp r1, #4
|
|
80042f0: d028 beq.n 8004344 <HAL_TIM_OC_Start+0xb0>
|
|
80042f2: 0010 movs r0, r2
|
|
80042f4: 3043 adds r0, #67 @ 0x43
|
|
80042f6: e008 b.n 800430a <HAL_TIM_OC_Start+0x76>
|
|
80042f8: 290c cmp r1, #12
|
|
80042fa: d029 beq.n 8004350 <HAL_TIM_OC_Start+0xbc>
|
|
80042fc: 2910 cmp r1, #16
|
|
80042fe: d1f8 bne.n 80042f2 <HAL_TIM_OC_Start+0x5e>
|
|
8004300: 0010 movs r0, r2
|
|
8004302: 3042 adds r0, #66 @ 0x42
|
|
8004304: e001 b.n 800430a <HAL_TIM_OC_Start+0x76>
|
|
8004306: 0010 movs r0, r2
|
|
8004308: 303e adds r0, #62 @ 0x3e
|
|
800430a: 7003 strb r3, [r0, #0]
|
|
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
|
|
800430c: 6814 ldr r4, [r2, #0]
|
|
800430e: 2201 movs r2, #1
|
|
8004310: 0020 movs r0, r4
|
|
8004312: f7ff ffb1 bl 8004278 <TIM_CCxChannelCmd>
|
|
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
|
|
8004316: 4a18 ldr r2, [pc, #96] @ (8004378 <HAL_TIM_OC_Start+0xe4>)
|
|
8004318: 4294 cmp r4, r2
|
|
800431a: d005 beq.n 8004328 <HAL_TIM_OC_Start+0x94>
|
|
800431c: 4b17 ldr r3, [pc, #92] @ (800437c <HAL_TIM_OC_Start+0xe8>)
|
|
800431e: 429c cmp r4, r3
|
|
8004320: d002 beq.n 8004328 <HAL_TIM_OC_Start+0x94>
|
|
8004322: 4b17 ldr r3, [pc, #92] @ (8004380 <HAL_TIM_OC_Start+0xec>)
|
|
8004324: 429c cmp r4, r3
|
|
8004326: d116 bne.n 8004356 <HAL_TIM_OC_Start+0xc2>
|
|
__HAL_TIM_MOE_ENABLE(htim);
|
|
8004328: 2380 movs r3, #128 @ 0x80
|
|
800432a: 6c61 ldr r1, [r4, #68] @ 0x44
|
|
800432c: 021b lsls r3, r3, #8
|
|
800432e: 430b orrs r3, r1
|
|
8004330: 6463 str r3, [r4, #68] @ 0x44
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8004332: 4294 cmp r4, r2
|
|
8004334: d116 bne.n 8004364 <HAL_TIM_OC_Start+0xd0>
|
|
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
|
|
8004336: 68a3 ldr r3, [r4, #8]
|
|
8004338: 4a12 ldr r2, [pc, #72] @ (8004384 <HAL_TIM_OC_Start+0xf0>)
|
|
800433a: 4013 ands r3, r2
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
800433c: 2b06 cmp r3, #6
|
|
800433e: d116 bne.n 800436e <HAL_TIM_OC_Start+0xda>
|
|
return HAL_OK;
|
|
8004340: 2000 movs r0, #0
|
|
8004342: e7c4 b.n 80042ce <HAL_TIM_OC_Start+0x3a>
|
|
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
|
|
8004344: 0010 movs r0, r2
|
|
8004346: 303f adds r0, #63 @ 0x3f
|
|
8004348: e7df b.n 800430a <HAL_TIM_OC_Start+0x76>
|
|
800434a: 0010 movs r0, r2
|
|
800434c: 3040 adds r0, #64 @ 0x40
|
|
800434e: e7dc b.n 800430a <HAL_TIM_OC_Start+0x76>
|
|
8004350: 0010 movs r0, r2
|
|
8004352: 3041 adds r0, #65 @ 0x41
|
|
8004354: e7d9 b.n 800430a <HAL_TIM_OC_Start+0x76>
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
8004356: 2380 movs r3, #128 @ 0x80
|
|
8004358: 05db lsls r3, r3, #23
|
|
800435a: 429c cmp r4, r3
|
|
800435c: d0eb beq.n 8004336 <HAL_TIM_OC_Start+0xa2>
|
|
800435e: 4b0a ldr r3, [pc, #40] @ (8004388 <HAL_TIM_OC_Start+0xf4>)
|
|
8004360: 429c cmp r4, r3
|
|
8004362: d0e8 beq.n 8004336 <HAL_TIM_OC_Start+0xa2>
|
|
__HAL_TIM_ENABLE(htim);
|
|
8004364: 2301 movs r3, #1
|
|
8004366: 6822 ldr r2, [r4, #0]
|
|
8004368: 4313 orrs r3, r2
|
|
800436a: 6023 str r3, [r4, #0]
|
|
800436c: e7e8 b.n 8004340 <HAL_TIM_OC_Start+0xac>
|
|
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
|
|
800436e: 2280 movs r2, #128 @ 0x80
|
|
8004370: 0252 lsls r2, r2, #9
|
|
8004372: 4293 cmp r3, r2
|
|
8004374: d1f6 bne.n 8004364 <HAL_TIM_OC_Start+0xd0>
|
|
8004376: e7e3 b.n 8004340 <HAL_TIM_OC_Start+0xac>
|
|
8004378: 40012c00 .word 0x40012c00
|
|
800437c: 40014400 .word 0x40014400
|
|
8004380: 40014800 .word 0x40014800
|
|
8004384: 00010007 .word 0x00010007
|
|
8004388: 40000400 .word 0x40000400
|
|
|
|
0800438c <HAL_TIM_PWM_Start>:
|
|
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
|
800438c: b510 push {r4, lr}
|
|
800438e: f7ff ff81 bl 8004294 <HAL_TIM_OC_Start>
|
|
8004392: bd10 pop {r4, pc}
|
|
|
|
08004394 <HAL_TIMEx_MasterConfigSynchronization>:
|
|
* mode.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
|
|
const TIM_MasterConfigTypeDef *sMasterConfig)
|
|
{
|
|
8004394: b5f0 push {r4, r5, r6, r7, lr}
|
|
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
|
|
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
|
|
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
8004396: 0004 movs r4, r0
|
|
8004398: 2202 movs r2, #2
|
|
800439a: 343c adds r4, #60 @ 0x3c
|
|
800439c: 7825 ldrb r5, [r4, #0]
|
|
{
|
|
800439e: 0003 movs r3, r0
|
|
__HAL_LOCK(htim);
|
|
80043a0: 0010 movs r0, r2
|
|
80043a2: 2d01 cmp r5, #1
|
|
80043a4: d023 beq.n 80043ee <HAL_TIMEx_MasterConfigSynchronization+0x5a>
|
|
|
|
/* Change the handler state */
|
|
htim->State = HAL_TIM_STATE_BUSY;
|
|
80043a6: 001d movs r5, r3
|
|
80043a8: 353d adds r5, #61 @ 0x3d
|
|
80043aa: 702a strb r2, [r5, #0]
|
|
|
|
/* Get the TIMx CR2 register value */
|
|
tmpcr2 = htim->Instance->CR2;
|
|
80043ac: 681a ldr r2, [r3, #0]
|
|
|
|
/* Get the TIMx SMCR register value */
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
|
|
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
|
|
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
|
|
80043ae: 4e10 ldr r6, [pc, #64] @ (80043f0 <HAL_TIMEx_MasterConfigSynchronization+0x5c>)
|
|
tmpcr2 = htim->Instance->CR2;
|
|
80043b0: 6853 ldr r3, [r2, #4]
|
|
tmpsmcr = htim->Instance->SMCR;
|
|
80043b2: 6890 ldr r0, [r2, #8]
|
|
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
|
|
80043b4: 42b2 cmp r2, r6
|
|
80043b6: d103 bne.n 80043c0 <HAL_TIMEx_MasterConfigSynchronization+0x2c>
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
|
|
|
|
/* Clear the MMS2 bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS2;
|
|
80043b8: 4f0e ldr r7, [pc, #56] @ (80043f4 <HAL_TIMEx_MasterConfigSynchronization+0x60>)
|
|
80043ba: 403b ands r3, r7
|
|
/* Select the TRGO2 source*/
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
|
|
80043bc: 684f ldr r7, [r1, #4]
|
|
80043be: 433b orrs r3, r7
|
|
}
|
|
|
|
/* Reset the MMS Bits */
|
|
tmpcr2 &= ~TIM_CR2_MMS;
|
|
80043c0: 2770 movs r7, #112 @ 0x70
|
|
80043c2: 43bb bics r3, r7
|
|
/* Select the TRGO source */
|
|
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
|
|
80043c4: 680f ldr r7, [r1, #0]
|
|
80043c6: 433b orrs r3, r7
|
|
|
|
/* Update TIMx CR2 */
|
|
htim->Instance->CR2 = tmpcr2;
|
|
80043c8: 6053 str r3, [r2, #4]
|
|
|
|
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
|
|
80043ca: 42b2 cmp r2, r6
|
|
80043cc: d006 beq.n 80043dc <HAL_TIMEx_MasterConfigSynchronization+0x48>
|
|
80043ce: 2380 movs r3, #128 @ 0x80
|
|
80043d0: 05db lsls r3, r3, #23
|
|
80043d2: 429a cmp r2, r3
|
|
80043d4: d002 beq.n 80043dc <HAL_TIMEx_MasterConfigSynchronization+0x48>
|
|
80043d6: 4b08 ldr r3, [pc, #32] @ (80043f8 <HAL_TIMEx_MasterConfigSynchronization+0x64>)
|
|
80043d8: 429a cmp r2, r3
|
|
80043da: d104 bne.n 80043e6 <HAL_TIMEx_MasterConfigSynchronization+0x52>
|
|
{
|
|
/* Reset the MSM Bit */
|
|
tmpsmcr &= ~TIM_SMCR_MSM;
|
|
80043dc: 2380 movs r3, #128 @ 0x80
|
|
80043de: 4398 bics r0, r3
|
|
/* Set master mode */
|
|
tmpsmcr |= sMasterConfig->MasterSlaveMode;
|
|
80043e0: 688b ldr r3, [r1, #8]
|
|
80043e2: 4318 orrs r0, r3
|
|
|
|
/* Update TIMx SMCR */
|
|
htim->Instance->SMCR = tmpsmcr;
|
|
80043e4: 6090 str r0, [r2, #8]
|
|
}
|
|
|
|
/* Change the htim state */
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80043e6: 2301 movs r3, #1
|
|
|
|
__HAL_UNLOCK(htim);
|
|
80043e8: 2000 movs r0, #0
|
|
htim->State = HAL_TIM_STATE_READY;
|
|
80043ea: 702b strb r3, [r5, #0]
|
|
__HAL_UNLOCK(htim);
|
|
80043ec: 7020 strb r0, [r4, #0]
|
|
|
|
return HAL_OK;
|
|
}
|
|
80043ee: bdf0 pop {r4, r5, r6, r7, pc}
|
|
80043f0: 40012c00 .word 0x40012c00
|
|
80043f4: ff0fffff .word 0xff0fffff
|
|
80043f8: 40000400 .word 0x40000400
|
|
|
|
080043fc <HAL_TIMEx_ConfigBreakDeadTime>:
|
|
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
|
|
* @retval HAL status
|
|
*/
|
|
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
|
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
|
|
{
|
|
80043fc: b510 push {r4, lr}
|
|
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
|
|
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
|
|
assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
|
|
|
|
/* Check input state */
|
|
__HAL_LOCK(htim);
|
|
80043fe: 0004 movs r4, r0
|
|
8004400: 343c adds r4, #60 @ 0x3c
|
|
8004402: 7823 ldrb r3, [r4, #0]
|
|
{
|
|
8004404: 0002 movs r2, r0
|
|
__HAL_LOCK(htim);
|
|
8004406: 2002 movs r0, #2
|
|
8004408: 2b01 cmp r3, #1
|
|
800440a: d039 beq.n 8004480 <HAL_TIMEx_ConfigBreakDeadTime+0x84>
|
|
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
|
|
the OSSI State, the dead time value and the Automatic Output Enable Bit */
|
|
|
|
/* Set the BDTR bits */
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
|
|
800440c: 481d ldr r0, [pc, #116] @ (8004484 <HAL_TIMEx_ConfigBreakDeadTime+0x88>)
|
|
800440e: 68cb ldr r3, [r1, #12]
|
|
8004410: 4003 ands r3, r0
|
|
8004412: 6888 ldr r0, [r1, #8]
|
|
8004414: 4303 orrs r3, r0
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
|
|
8004416: 481c ldr r0, [pc, #112] @ (8004488 <HAL_TIMEx_ConfigBreakDeadTime+0x8c>)
|
|
8004418: 4003 ands r3, r0
|
|
800441a: 6848 ldr r0, [r1, #4]
|
|
800441c: 4303 orrs r3, r0
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
|
|
800441e: 481b ldr r0, [pc, #108] @ (800448c <HAL_TIMEx_ConfigBreakDeadTime+0x90>)
|
|
8004420: 4003 ands r3, r0
|
|
8004422: 6808 ldr r0, [r1, #0]
|
|
8004424: 4303 orrs r3, r0
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
|
|
8004426: 481a ldr r0, [pc, #104] @ (8004490 <HAL_TIMEx_ConfigBreakDeadTime+0x94>)
|
|
8004428: 4003 ands r3, r0
|
|
800442a: 6908 ldr r0, [r1, #16]
|
|
800442c: 4303 orrs r3, r0
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
|
|
800442e: 4819 ldr r0, [pc, #100] @ (8004494 <HAL_TIMEx_ConfigBreakDeadTime+0x98>)
|
|
8004430: 4003 ands r3, r0
|
|
8004432: 6948 ldr r0, [r1, #20]
|
|
8004434: 4303 orrs r3, r0
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
|
|
8004436: 4818 ldr r0, [pc, #96] @ (8004498 <HAL_TIMEx_ConfigBreakDeadTime+0x9c>)
|
|
8004438: 4003 ands r3, r0
|
|
800443a: 6b08 ldr r0, [r1, #48] @ 0x30
|
|
800443c: 4303 orrs r3, r0
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
|
|
800443e: 4817 ldr r0, [pc, #92] @ (800449c <HAL_TIMEx_ConfigBreakDeadTime+0xa0>)
|
|
8004440: 4003 ands r3, r0
|
|
8004442: 6988 ldr r0, [r1, #24]
|
|
8004444: 0400 lsls r0, r0, #16
|
|
8004446: 4303 orrs r3, r0
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
|
|
8004448: 4815 ldr r0, [pc, #84] @ (80044a0 <HAL_TIMEx_ConfigBreakDeadTime+0xa4>)
|
|
800444a: 4003 ands r3, r0
|
|
800444c: 69c8 ldr r0, [r1, #28]
|
|
800444e: 4303 orrs r3, r0
|
|
|
|
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
|
|
8004450: 6810 ldr r0, [r2, #0]
|
|
8004452: 4a14 ldr r2, [pc, #80] @ (80044a4 <HAL_TIMEx_ConfigBreakDeadTime+0xa8>)
|
|
8004454: 4290 cmp r0, r2
|
|
8004456: d110 bne.n 800447a <HAL_TIMEx_ConfigBreakDeadTime+0x7e>
|
|
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
|
|
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
|
|
assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
|
|
|
|
/* Set the BREAK2 input related BDTR bits */
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
|
|
8004458: 4a13 ldr r2, [pc, #76] @ (80044a8 <HAL_TIMEx_ConfigBreakDeadTime+0xac>)
|
|
800445a: 4013 ands r3, r2
|
|
800445c: 6a8a ldr r2, [r1, #40] @ 0x28
|
|
800445e: 0512 lsls r2, r2, #20
|
|
8004460: 431a orrs r2, r3
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
|
|
8004462: 4b12 ldr r3, [pc, #72] @ (80044ac <HAL_TIMEx_ConfigBreakDeadTime+0xb0>)
|
|
8004464: 401a ands r2, r3
|
|
8004466: 6a0b ldr r3, [r1, #32]
|
|
8004468: 431a orrs r2, r3
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
|
|
800446a: 4b11 ldr r3, [pc, #68] @ (80044b0 <HAL_TIMEx_ConfigBreakDeadTime+0xb4>)
|
|
800446c: 401a ands r2, r3
|
|
800446e: 6a4b ldr r3, [r1, #36] @ 0x24
|
|
8004470: 431a orrs r2, r3
|
|
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
|
|
8004472: 4b10 ldr r3, [pc, #64] @ (80044b4 <HAL_TIMEx_ConfigBreakDeadTime+0xb8>)
|
|
8004474: 401a ands r2, r3
|
|
8004476: 6acb ldr r3, [r1, #44] @ 0x2c
|
|
8004478: 4313 orrs r3, r2
|
|
}
|
|
|
|
/* Set TIMx_BDTR */
|
|
htim->Instance->BDTR = tmpbdtr;
|
|
800447a: 6443 str r3, [r0, #68] @ 0x44
|
|
|
|
__HAL_UNLOCK(htim);
|
|
800447c: 2000 movs r0, #0
|
|
800447e: 7020 strb r0, [r4, #0]
|
|
|
|
return HAL_OK;
|
|
}
|
|
8004480: bd10 pop {r4, pc}
|
|
8004482: 46c0 nop @ (mov r8, r8)
|
|
8004484: fffffcff .word 0xfffffcff
|
|
8004488: fffffbff .word 0xfffffbff
|
|
800448c: fffff7ff .word 0xfffff7ff
|
|
8004490: ffffefff .word 0xffffefff
|
|
8004494: ffffdfff .word 0xffffdfff
|
|
8004498: ffffbfff .word 0xffffbfff
|
|
800449c: fff0ffff .word 0xfff0ffff
|
|
80044a0: efffffff .word 0xefffffff
|
|
80044a4: 40012c00 .word 0x40012c00
|
|
80044a8: ff0fffff .word 0xff0fffff
|
|
80044ac: feffffff .word 0xfeffffff
|
|
80044b0: fdffffff .word 0xfdffffff
|
|
80044b4: dfffffff .word 0xdfffffff
|
|
|
|
080044b8 <HAL_TIMEx_CommutCallback>:
|
|
/**
|
|
* @brief Commutation callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
|
80044b8: 4770 bx lr
|
|
|
|
080044ba <HAL_TIMEx_BreakCallback>:
|
|
/**
|
|
* @brief Break detection callback in non-blocking mode
|
|
* @param htim TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
|
80044ba: 4770 bx lr
|
|
|
|
080044bc <HAL_TIMEx_Break2Callback>:
|
|
/**
|
|
* @brief Break2 detection callback in non blocking mode
|
|
* @param htim: TIM handle
|
|
* @retval None
|
|
*/
|
|
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
|
|
80044bc: 4770 bx lr
|
|
...
|
|
|
|
080044c0 <UART_EndTxTransfer>:
|
|
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
80044c0: b530 push {r4, r5, lr}
|
|
*/
|
|
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
|
|
{
|
|
uint32_t result;
|
|
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
80044c2: f3ef 8410 mrs r4, PRIMASK
|
|
\details Assigns the given value to the Priority Mask Register.
|
|
\param [in] priMask Priority Mask
|
|
*/
|
|
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
|
|
{
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80044c6: 2201 movs r2, #1
|
|
80044c8: f382 8810 msr PRIMASK, r2
|
|
/* Disable TXEIE, TCIE, TXFT interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
|
|
80044cc: 25c0 movs r5, #192 @ 0xc0
|
|
80044ce: 6801 ldr r1, [r0, #0]
|
|
80044d0: 680b ldr r3, [r1, #0]
|
|
80044d2: 43ab bics r3, r5
|
|
80044d4: 600b str r3, [r1, #0]
|
|
80044d6: f384 8810 msr PRIMASK, r4
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
80044da: f3ef 8110 mrs r1, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80044de: f382 8810 msr PRIMASK, r2
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
|
|
80044e2: 6802 ldr r2, [r0, #0]
|
|
80044e4: 4c04 ldr r4, [pc, #16] @ (80044f8 <UART_EndTxTransfer+0x38>)
|
|
80044e6: 6893 ldr r3, [r2, #8]
|
|
80044e8: 4023 ands r3, r4
|
|
80044ea: 6093 str r3, [r2, #8]
|
|
80044ec: f381 8810 msr PRIMASK, r1
|
|
|
|
/* At end of Tx process, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80044f0: 2320 movs r3, #32
|
|
80044f2: 3088 adds r0, #136 @ 0x88
|
|
80044f4: 6003 str r3, [r0, #0]
|
|
}
|
|
80044f6: bd30 pop {r4, r5, pc}
|
|
80044f8: ff7fffff .word 0xff7fffff
|
|
|
|
080044fc <UART_EndRxTransfer>:
|
|
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
|
|
{
|
|
80044fc: b530 push {r4, r5, lr}
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
80044fe: f3ef 8410 mrs r4, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004502: 2201 movs r2, #1
|
|
8004504: f382 8810 msr PRIMASK, r2
|
|
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8004508: 6801 ldr r1, [r0, #0]
|
|
800450a: 4d13 ldr r5, [pc, #76] @ (8004558 <UART_EndRxTransfer+0x5c>)
|
|
800450c: 680b ldr r3, [r1, #0]
|
|
800450e: 402b ands r3, r5
|
|
8004510: 600b str r3, [r1, #0]
|
|
8004512: f384 8810 msr PRIMASK, r4
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004516: f3ef 8110 mrs r1, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800451a: f382 8810 msr PRIMASK, r2
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
800451e: 6802 ldr r2, [r0, #0]
|
|
8004520: 4c0e ldr r4, [pc, #56] @ (800455c <UART_EndRxTransfer+0x60>)
|
|
8004522: 6893 ldr r3, [r2, #8]
|
|
8004524: 4023 ands r3, r4
|
|
8004526: 6093 str r3, [r2, #8]
|
|
8004528: f381 8810 msr PRIMASK, r1
|
|
|
|
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
800452c: 6ec3 ldr r3, [r0, #108] @ 0x6c
|
|
800452e: 2b01 cmp r3, #1
|
|
8004530: d10a bne.n 8004548 <UART_EndRxTransfer+0x4c>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004532: f3ef 8110 mrs r1, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004536: f383 8810 msr PRIMASK, r3
|
|
{
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
800453a: 2410 movs r4, #16
|
|
800453c: 6802 ldr r2, [r0, #0]
|
|
800453e: 6813 ldr r3, [r2, #0]
|
|
8004540: 43a3 bics r3, r4
|
|
8004542: 6013 str r3, [r2, #0]
|
|
8004544: f381 8810 msr PRIMASK, r1
|
|
}
|
|
|
|
/* At end of Rx process, restore huart->RxState to Ready */
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004548: 0003 movs r3, r0
|
|
800454a: 2220 movs r2, #32
|
|
800454c: 338c adds r3, #140 @ 0x8c
|
|
800454e: 601a str r2, [r3, #0]
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004550: 2300 movs r3, #0
|
|
8004552: 66c3 str r3, [r0, #108] @ 0x6c
|
|
|
|
/* Reset RxIsr function pointer */
|
|
huart->RxISR = NULL;
|
|
8004554: 6743 str r3, [r0, #116] @ 0x74
|
|
}
|
|
8004556: bd30 pop {r4, r5, pc}
|
|
8004558: fffffedf .word 0xfffffedf
|
|
800455c: effffffe .word 0xeffffffe
|
|
|
|
08004560 <HAL_UART_AbortReceive>:
|
|
{
|
|
8004560: b570 push {r4, r5, r6, lr}
|
|
8004562: 0004 movs r4, r0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004564: f3ef 8010 mrs r0, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004568: 2201 movs r2, #1
|
|
800456a: f382 8810 msr PRIMASK, r2
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE));
|
|
800456e: 6821 ldr r1, [r4, #0]
|
|
8004570: 4d29 ldr r5, [pc, #164] @ (8004618 <HAL_UART_AbortReceive+0xb8>)
|
|
8004572: 680b ldr r3, [r1, #0]
|
|
8004574: 402b ands r3, r5
|
|
8004576: 600b str r3, [r1, #0]
|
|
8004578: f380 8810 msr PRIMASK, r0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
800457c: f3ef 8110 mrs r1, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004580: f382 8810 msr PRIMASK, r2
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE);
|
|
8004584: 6822 ldr r2, [r4, #0]
|
|
8004586: 4825 ldr r0, [pc, #148] @ (800461c <HAL_UART_AbortReceive+0xbc>)
|
|
8004588: 6893 ldr r3, [r2, #8]
|
|
800458a: 4003 ands r3, r0
|
|
800458c: 6093 str r3, [r2, #8]
|
|
800458e: f381 8810 msr PRIMASK, r1
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8004592: 6ee3 ldr r3, [r4, #108] @ 0x6c
|
|
8004594: 2b01 cmp r3, #1
|
|
8004596: d10a bne.n 80045ae <HAL_UART_AbortReceive+0x4e>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004598: f3ef 8110 mrs r1, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800459c: f383 8810 msr PRIMASK, r3
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE));
|
|
80045a0: 2010 movs r0, #16
|
|
80045a2: 6822 ldr r2, [r4, #0]
|
|
80045a4: 6813 ldr r3, [r2, #0]
|
|
80045a6: 4383 bics r3, r0
|
|
80045a8: 6013 str r3, [r2, #0]
|
|
80045aa: f381 8810 msr PRIMASK, r1
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80045ae: 2140 movs r1, #64 @ 0x40
|
|
80045b0: 6823 ldr r3, [r4, #0]
|
|
80045b2: 689b ldr r3, [r3, #8]
|
|
80045b4: 420b tst r3, r1
|
|
80045b6: d01e beq.n 80045f6 <HAL_UART_AbortReceive+0x96>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
80045b8: f3ef 8010 mrs r0, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80045bc: 2301 movs r3, #1
|
|
80045be: f383 8810 msr PRIMASK, r3
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
80045c2: 0025 movs r5, r4
|
|
80045c4: cd04 ldmia r5!, {r2}
|
|
80045c6: 6893 ldr r3, [r2, #8]
|
|
80045c8: 438b bics r3, r1
|
|
80045ca: 6093 str r3, [r2, #8]
|
|
80045cc: f380 8810 msr PRIMASK, r0
|
|
if (huart->hdmarx != NULL)
|
|
80045d0: 6fe8 ldr r0, [r5, #124] @ 0x7c
|
|
80045d2: 2800 cmp r0, #0
|
|
80045d4: d00f beq.n 80045f6 <HAL_UART_AbortReceive+0x96>
|
|
huart->hdmarx->XferAbortCallback = NULL;
|
|
80045d6: 2300 movs r3, #0
|
|
80045d8: 6383 str r3, [r0, #56] @ 0x38
|
|
if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK)
|
|
80045da: f7fe fd27 bl 800302c <HAL_DMA_Abort>
|
|
80045de: 2800 cmp r0, #0
|
|
80045e0: d009 beq.n 80045f6 <HAL_UART_AbortReceive+0x96>
|
|
if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT)
|
|
80045e2: 6fe8 ldr r0, [r5, #124] @ 0x7c
|
|
80045e4: f7fe fdee bl 80031c4 <HAL_DMA_GetError>
|
|
80045e8: 2820 cmp r0, #32
|
|
80045ea: d104 bne.n 80045f6 <HAL_UART_AbortReceive+0x96>
|
|
huart->ErrorCode = HAL_UART_ERROR_DMA;
|
|
80045ec: 2310 movs r3, #16
|
|
80045ee: 3490 adds r4, #144 @ 0x90
|
|
80045f0: 6023 str r3, [r4, #0]
|
|
return HAL_TIMEOUT;
|
|
80045f2: 381d subs r0, #29
|
|
}
|
|
80045f4: bd70 pop {r4, r5, r6, pc}
|
|
huart->RxXferCount = 0U;
|
|
80045f6: 0023 movs r3, r4
|
|
80045f8: 2000 movs r0, #0
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
|
|
80045fa: 220f movs r2, #15
|
|
huart->RxXferCount = 0U;
|
|
80045fc: 335e adds r3, #94 @ 0x5e
|
|
80045fe: 8018 strh r0, [r3, #0]
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF);
|
|
8004600: 6823 ldr r3, [r4, #0]
|
|
8004602: 621a str r2, [r3, #32]
|
|
__HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST);
|
|
8004604: 6999 ldr r1, [r3, #24]
|
|
8004606: 3a07 subs r2, #7
|
|
8004608: 430a orrs r2, r1
|
|
800460a: 619a str r2, [r3, #24]
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800460c: 0023 movs r3, r4
|
|
800460e: 2220 movs r2, #32
|
|
8004610: 338c adds r3, #140 @ 0x8c
|
|
8004612: 601a str r2, [r3, #0]
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004614: 66e0 str r0, [r4, #108] @ 0x6c
|
|
return HAL_OK;
|
|
8004616: e7ed b.n 80045f4 <HAL_UART_AbortReceive+0x94>
|
|
8004618: fffffedf .word 0xfffffedf
|
|
800461c: effffffe .word 0xeffffffe
|
|
|
|
08004620 <HAL_UART_TxCpltCallback>:
|
|
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
|
|
8004620: 4770 bx lr
|
|
|
|
08004622 <HAL_UART_RxCpltCallback>:
|
|
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
|
|
8004622: 4770 bx lr
|
|
|
|
08004624 <HAL_UART_RxHalfCpltCallback>:
|
|
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
|
|
8004624: 4770 bx lr
|
|
|
|
08004626 <UART_DMAError>:
|
|
* @brief DMA UART communication error callback.
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
8004626: b570 push {r4, r5, r6, lr}
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
8004628: 6a84 ldr r4, [r0, #40] @ 0x28
|
|
|
|
const HAL_UART_StateTypeDef gstate = huart->gState;
|
|
800462a: 0023 movs r3, r4
|
|
800462c: 3388 adds r3, #136 @ 0x88
|
|
800462e: 681a ldr r2, [r3, #0]
|
|
const HAL_UART_StateTypeDef rxstate = huart->RxState;
|
|
8004630: 685d ldr r5, [r3, #4]
|
|
|
|
/* Stop UART DMA Tx request if ongoing */
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
|
|
8004632: 6823 ldr r3, [r4, #0]
|
|
8004634: 689b ldr r3, [r3, #8]
|
|
8004636: 061b lsls r3, r3, #24
|
|
8004638: d508 bpl.n 800464c <UART_DMAError+0x26>
|
|
800463a: 2a21 cmp r2, #33 @ 0x21
|
|
800463c: d106 bne.n 800464c <UART_DMAError+0x26>
|
|
(gstate == HAL_UART_STATE_BUSY_TX))
|
|
{
|
|
huart->TxXferCount = 0U;
|
|
800463e: 0023 movs r3, r4
|
|
8004640: 2200 movs r2, #0
|
|
8004642: 3356 adds r3, #86 @ 0x56
|
|
UART_EndTxTransfer(huart);
|
|
8004644: 0020 movs r0, r4
|
|
huart->TxXferCount = 0U;
|
|
8004646: 801a strh r2, [r3, #0]
|
|
UART_EndTxTransfer(huart);
|
|
8004648: f7ff ff3a bl 80044c0 <UART_EndTxTransfer>
|
|
}
|
|
|
|
/* Stop UART DMA Rx request if ongoing */
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
|
|
800464c: 6823 ldr r3, [r4, #0]
|
|
800464e: 689b ldr r3, [r3, #8]
|
|
8004650: 065b lsls r3, r3, #25
|
|
8004652: d508 bpl.n 8004666 <UART_DMAError+0x40>
|
|
8004654: 2d22 cmp r5, #34 @ 0x22
|
|
8004656: d106 bne.n 8004666 <UART_DMAError+0x40>
|
|
(rxstate == HAL_UART_STATE_BUSY_RX))
|
|
{
|
|
huart->RxXferCount = 0U;
|
|
8004658: 0023 movs r3, r4
|
|
800465a: 2200 movs r2, #0
|
|
800465c: 335e adds r3, #94 @ 0x5e
|
|
UART_EndRxTransfer(huart);
|
|
800465e: 0020 movs r0, r4
|
|
huart->RxXferCount = 0U;
|
|
8004660: 801a strh r2, [r3, #0]
|
|
UART_EndRxTransfer(huart);
|
|
8004662: f7ff ff4b bl 80044fc <UART_EndRxTransfer>
|
|
}
|
|
|
|
huart->ErrorCode |= HAL_UART_ERROR_DMA;
|
|
8004666: 0022 movs r2, r4
|
|
8004668: 2310 movs r3, #16
|
|
800466a: 3290 adds r2, #144 @ 0x90
|
|
800466c: 6811 ldr r1, [r2, #0]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
800466e: 0020 movs r0, r4
|
|
huart->ErrorCode |= HAL_UART_ERROR_DMA;
|
|
8004670: 430b orrs r3, r1
|
|
8004672: 6013 str r3, [r2, #0]
|
|
HAL_UART_ErrorCallback(huart);
|
|
8004674: f7fc f9f0 bl 8000a58 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
8004678: bd70 pop {r4, r5, r6, pc}
|
|
|
|
0800467a <UART_DMAAbortOnError>:
|
|
* @param hdma DMA handle.
|
|
* @retval None
|
|
*/
|
|
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
|
|
{
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
800467a: 6a80 ldr r0, [r0, #40] @ 0x28
|
|
huart->RxXferCount = 0U;
|
|
800467c: 2200 movs r2, #0
|
|
800467e: 0003 movs r3, r0
|
|
{
|
|
8004680: b510 push {r4, lr}
|
|
huart->RxXferCount = 0U;
|
|
8004682: 335e adds r3, #94 @ 0x5e
|
|
8004684: 801a strh r2, [r3, #0]
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered error callback*/
|
|
huart->ErrorCallback(huart);
|
|
#else
|
|
/*Call legacy weak error callback*/
|
|
HAL_UART_ErrorCallback(huart);
|
|
8004686: f7fc f9e7 bl 8000a58 <HAL_UART_ErrorCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
800468a: bd10 pop {r4, pc}
|
|
|
|
0800468c <HAL_UART_IRQHandler>:
|
|
{
|
|
800468c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
800468e: 6801 ldr r1, [r0, #0]
|
|
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
|
|
8004690: 4dc3 ldr r5, [pc, #780] @ (80049a0 <HAL_UART_IRQHandler+0x314>)
|
|
uint32_t isrflags = READ_REG(huart->Instance->ISR);
|
|
8004692: 69cb ldr r3, [r1, #28]
|
|
{
|
|
8004694: 0004 movs r4, r0
|
|
uint32_t cr1its = READ_REG(huart->Instance->CR1);
|
|
8004696: 680a ldr r2, [r1, #0]
|
|
uint32_t cr3its = READ_REG(huart->Instance->CR3);
|
|
8004698: 6888 ldr r0, [r1, #8]
|
|
if (errorflags == 0U)
|
|
800469a: 422b tst r3, r5
|
|
800469c: d110 bne.n 80046c0 <HAL_UART_IRQHandler+0x34>
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
800469e: 2520 movs r5, #32
|
|
80046a0: 422b tst r3, r5
|
|
80046a2: d100 bne.n 80046a6 <HAL_UART_IRQHandler+0x1a>
|
|
80046a4: e09b b.n 80047de <HAL_UART_IRQHandler+0x152>
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
80046a6: 2680 movs r6, #128 @ 0x80
|
|
80046a8: 0576 lsls r6, r6, #21
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
80046aa: 4015 ands r5, r2
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
80046ac: 4006 ands r6, r0
|
|
80046ae: 4335 orrs r5, r6
|
|
80046b0: d100 bne.n 80046b4 <HAL_UART_IRQHandler+0x28>
|
|
80046b2: e094 b.n 80047de <HAL_UART_IRQHandler+0x152>
|
|
if (huart->RxISR != NULL)
|
|
80046b4: 6f63 ldr r3, [r4, #116] @ 0x74
|
|
huart->TxISR(huart);
|
|
80046b6: 0020 movs r0, r4
|
|
if (huart->TxISR != NULL)
|
|
80046b8: 2b00 cmp r3, #0
|
|
80046ba: d000 beq.n 80046be <HAL_UART_IRQHandler+0x32>
|
|
80046bc: e085 b.n 80047ca <HAL_UART_IRQHandler+0x13e>
|
|
80046be: e085 b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
|
|
80046c0: 4db8 ldr r5, [pc, #736] @ (80049a4 <HAL_UART_IRQHandler+0x318>)
|
|
80046c2: 4005 ands r5, r0
|
|
80046c4: 9500 str r5, [sp, #0]
|
|
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
|
|
80046c6: 4db8 ldr r5, [pc, #736] @ (80049a8 <HAL_UART_IRQHandler+0x31c>)
|
|
80046c8: 9e00 ldr r6, [sp, #0]
|
|
80046ca: 4015 ands r5, r2
|
|
80046cc: 4335 orrs r5, r6
|
|
80046ce: d100 bne.n 80046d2 <HAL_UART_IRQHandler+0x46>
|
|
80046d0: e085 b.n 80047de <HAL_UART_IRQHandler+0x152>
|
|
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
|
|
80046d2: 0025 movs r5, r4
|
|
80046d4: 2601 movs r6, #1
|
|
80046d6: 3590 adds r5, #144 @ 0x90
|
|
80046d8: 4233 tst r3, r6
|
|
80046da: d005 beq.n 80046e8 <HAL_UART_IRQHandler+0x5c>
|
|
80046dc: 05d7 lsls r7, r2, #23
|
|
80046de: d503 bpl.n 80046e8 <HAL_UART_IRQHandler+0x5c>
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
|
|
80046e0: 620e str r6, [r1, #32]
|
|
huart->ErrorCode |= HAL_UART_ERROR_PE;
|
|
80046e2: 682f ldr r7, [r5, #0]
|
|
80046e4: 433e orrs r6, r7
|
|
80046e6: 602e str r6, [r5, #0]
|
|
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
80046e8: 2602 movs r6, #2
|
|
80046ea: 4233 tst r3, r6
|
|
80046ec: d00c beq.n 8004708 <HAL_UART_IRQHandler+0x7c>
|
|
80046ee: 07c7 lsls r7, r0, #31
|
|
80046f0: d50a bpl.n 8004708 <HAL_UART_IRQHandler+0x7c>
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
80046f2: 0027 movs r7, r4
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
|
|
80046f4: 620e str r6, [r1, #32]
|
|
huart->ErrorCode |= HAL_UART_ERROR_FE;
|
|
80046f6: 3790 adds r7, #144 @ 0x90
|
|
80046f8: 683e ldr r6, [r7, #0]
|
|
80046fa: 9701 str r7, [sp, #4]
|
|
80046fc: 46b4 mov ip, r6
|
|
80046fe: 2604 movs r6, #4
|
|
8004700: 4667 mov r7, ip
|
|
8004702: 433e orrs r6, r7
|
|
8004704: 9f01 ldr r7, [sp, #4]
|
|
8004706: 603e str r6, [r7, #0]
|
|
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
|
|
8004708: 2604 movs r6, #4
|
|
800470a: 4233 tst r3, r6
|
|
800470c: d00c beq.n 8004728 <HAL_UART_IRQHandler+0x9c>
|
|
800470e: 07c7 lsls r7, r0, #31
|
|
8004710: d50a bpl.n 8004728 <HAL_UART_IRQHandler+0x9c>
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
8004712: 0027 movs r7, r4
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
|
|
8004714: 620e str r6, [r1, #32]
|
|
huart->ErrorCode |= HAL_UART_ERROR_NE;
|
|
8004716: 3790 adds r7, #144 @ 0x90
|
|
8004718: 683e ldr r6, [r7, #0]
|
|
800471a: 9701 str r7, [sp, #4]
|
|
800471c: 46b4 mov ip, r6
|
|
800471e: 2602 movs r6, #2
|
|
8004720: 4667 mov r7, ip
|
|
8004722: 433e orrs r6, r7
|
|
8004724: 9f01 ldr r7, [sp, #4]
|
|
8004726: 603e str r6, [r7, #0]
|
|
if (((isrflags & USART_ISR_ORE) != 0U)
|
|
8004728: 2608 movs r6, #8
|
|
800472a: 46b4 mov ip, r6
|
|
800472c: 4233 tst r3, r6
|
|
800472e: d009 beq.n 8004744 <HAL_UART_IRQHandler+0xb8>
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
|
|
8004730: 2720 movs r7, #32
|
|
8004732: 9e00 ldr r6, [sp, #0]
|
|
8004734: 4017 ands r7, r2
|
|
8004736: 4337 orrs r7, r6
|
|
8004738: d004 beq.n 8004744 <HAL_UART_IRQHandler+0xb8>
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
800473a: 4666 mov r6, ip
|
|
800473c: 620e str r6, [r1, #32]
|
|
huart->ErrorCode |= HAL_UART_ERROR_ORE;
|
|
800473e: 682f ldr r7, [r5, #0]
|
|
8004740: 433e orrs r6, r7
|
|
8004742: 602e str r6, [r5, #0]
|
|
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
|
|
8004744: 2680 movs r6, #128 @ 0x80
|
|
8004746: 0136 lsls r6, r6, #4
|
|
8004748: 4233 tst r3, r6
|
|
800474a: d006 beq.n 800475a <HAL_UART_IRQHandler+0xce>
|
|
800474c: 0157 lsls r7, r2, #5
|
|
800474e: d504 bpl.n 800475a <HAL_UART_IRQHandler+0xce>
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
8004750: 620e str r6, [r1, #32]
|
|
huart->ErrorCode |= HAL_UART_ERROR_RTO;
|
|
8004752: 2120 movs r1, #32
|
|
8004754: 682e ldr r6, [r5, #0]
|
|
8004756: 4331 orrs r1, r6
|
|
8004758: 6029 str r1, [r5, #0]
|
|
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
|
|
800475a: 6829 ldr r1, [r5, #0]
|
|
800475c: 2900 cmp r1, #0
|
|
800475e: d035 beq.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
|
|
8004760: 2120 movs r1, #32
|
|
8004762: 420b tst r3, r1
|
|
8004764: d00a beq.n 800477c <HAL_UART_IRQHandler+0xf0>
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
8004766: 2380 movs r3, #128 @ 0x80
|
|
8004768: 055b lsls r3, r3, #21
|
|
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
|
|
800476a: 4011 ands r1, r2
|
|
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
|
|
800476c: 4003 ands r3, r0
|
|
800476e: 4319 orrs r1, r3
|
|
8004770: d004 beq.n 800477c <HAL_UART_IRQHandler+0xf0>
|
|
if (huart->RxISR != NULL)
|
|
8004772: 6f63 ldr r3, [r4, #116] @ 0x74
|
|
8004774: 2b00 cmp r3, #0
|
|
8004776: d001 beq.n 800477c <HAL_UART_IRQHandler+0xf0>
|
|
huart->RxISR(huart);
|
|
8004778: 0020 movs r0, r4
|
|
800477a: 4798 blx r3
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
800477c: 6822 ldr r2, [r4, #0]
|
|
errorcode = huart->ErrorCode;
|
|
800477e: 682b ldr r3, [r5, #0]
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
8004780: 2740 movs r7, #64 @ 0x40
|
|
8004782: 6896 ldr r6, [r2, #8]
|
|
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
|
|
8004784: 2228 movs r2, #40 @ 0x28
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
8004786: 403e ands r6, r7
|
|
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
|
|
8004788: 4013 ands r3, r2
|
|
UART_EndRxTransfer(huart);
|
|
800478a: 0020 movs r0, r4
|
|
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
|
|
800478c: 431e orrs r6, r3
|
|
800478e: d022 beq.n 80047d6 <HAL_UART_IRQHandler+0x14a>
|
|
UART_EndRxTransfer(huart);
|
|
8004790: f7ff feb4 bl 80044fc <UART_EndRxTransfer>
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8004794: 6823 ldr r3, [r4, #0]
|
|
8004796: 689b ldr r3, [r3, #8]
|
|
8004798: 423b tst r3, r7
|
|
800479a: d018 beq.n 80047ce <HAL_UART_IRQHandler+0x142>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
800479c: f3ef 8110 mrs r1, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80047a0: 2301 movs r3, #1
|
|
80047a2: f383 8810 msr PRIMASK, r3
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
80047a6: 0025 movs r5, r4
|
|
80047a8: cd04 ldmia r5!, {r2}
|
|
80047aa: 6893 ldr r3, [r2, #8]
|
|
80047ac: 43bb bics r3, r7
|
|
80047ae: 6093 str r3, [r2, #8]
|
|
80047b0: f381 8810 msr PRIMASK, r1
|
|
if (huart->hdmarx != NULL)
|
|
80047b4: 6fe8 ldr r0, [r5, #124] @ 0x7c
|
|
80047b6: 2800 cmp r0, #0
|
|
80047b8: d009 beq.n 80047ce <HAL_UART_IRQHandler+0x142>
|
|
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
|
|
80047ba: 4b7c ldr r3, [pc, #496] @ (80049ac <HAL_UART_IRQHandler+0x320>)
|
|
80047bc: 6383 str r3, [r0, #56] @ 0x38
|
|
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
|
|
80047be: f7fe fc6f bl 80030a0 <HAL_DMA_Abort_IT>
|
|
80047c2: 2800 cmp r0, #0
|
|
80047c4: d002 beq.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
huart->hdmarx->XferAbortCallback(huart->hdmarx);
|
|
80047c6: 6fe8 ldr r0, [r5, #124] @ 0x7c
|
|
80047c8: 6b83 ldr r3, [r0, #56] @ 0x38
|
|
80047ca: 4798 blx r3
|
|
}
|
|
80047cc: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
|
|
HAL_UART_ErrorCallback(huart);
|
|
80047ce: 0020 movs r0, r4
|
|
80047d0: f7fc f942 bl 8000a58 <HAL_UART_ErrorCallback>
|
|
80047d4: e7fa b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
HAL_UART_ErrorCallback(huart);
|
|
80047d6: f7fc f93f bl 8000a58 <HAL_UART_ErrorCallback>
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
80047da: 602e str r6, [r5, #0]
|
|
80047dc: e7f6 b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80047de: 6ee5 ldr r5, [r4, #108] @ 0x6c
|
|
80047e0: 2d01 cmp r5, #1
|
|
80047e2: d000 beq.n 80047e6 <HAL_UART_IRQHandler+0x15a>
|
|
80047e4: e0a4 b.n 8004930 <HAL_UART_IRQHandler+0x2a4>
|
|
&& ((isrflags & USART_ISR_IDLE) != 0U)
|
|
80047e6: 2610 movs r6, #16
|
|
80047e8: 4233 tst r3, r6
|
|
80047ea: d100 bne.n 80047ee <HAL_UART_IRQHandler+0x162>
|
|
80047ec: e0a0 b.n 8004930 <HAL_UART_IRQHandler+0x2a4>
|
|
&& ((cr1its & USART_ISR_IDLE) != 0U))
|
|
80047ee: 4232 tst r2, r6
|
|
80047f0: d100 bne.n 80047f4 <HAL_UART_IRQHandler+0x168>
|
|
80047f2: e09d b.n 8004930 <HAL_UART_IRQHandler+0x2a4>
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
80047f4: 0023 movs r3, r4
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
80047f6: 620e str r6, [r1, #32]
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80047f8: 6889 ldr r1, [r1, #8]
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
80047fa: 335c adds r3, #92 @ 0x5c
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
80047fc: 0008 movs r0, r1
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
80047fe: 881a ldrh r2, [r3, #0]
|
|
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
|
|
8004800: 2340 movs r3, #64 @ 0x40
|
|
8004802: 4018 ands r0, r3
|
|
8004804: 4219 tst r1, r3
|
|
8004806: d05e beq.n 80048c6 <HAL_UART_IRQHandler+0x23a>
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
|
|
8004808: 1d20 adds r0, r4, #4
|
|
800480a: 6fc1 ldr r1, [r0, #124] @ 0x7c
|
|
800480c: 680f ldr r7, [r1, #0]
|
|
800480e: 6879 ldr r1, [r7, #4]
|
|
8004810: b289 uxth r1, r1
|
|
if ((nb_remaining_rx_data > 0U)
|
|
8004812: 2900 cmp r1, #0
|
|
8004814: d04d beq.n 80048b2 <HAL_UART_IRQHandler+0x226>
|
|
&& (nb_remaining_rx_data < huart->RxXferSize))
|
|
8004816: 4291 cmp r1, r2
|
|
8004818: d24b bcs.n 80048b2 <HAL_UART_IRQHandler+0x226>
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
800481a: 0022 movs r2, r4
|
|
800481c: 325e adds r2, #94 @ 0x5e
|
|
800481e: 8011 strh r1, [r2, #0]
|
|
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
8004820: 2120 movs r1, #32
|
|
8004822: 468c mov ip, r1
|
|
8004824: 683a ldr r2, [r7, #0]
|
|
8004826: 4011 ands r1, r2
|
|
8004828: 9100 str r1, [sp, #0]
|
|
800482a: 4661 mov r1, ip
|
|
800482c: 420a tst r2, r1
|
|
800482e: d132 bne.n 8004896 <HAL_UART_IRQHandler+0x20a>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004830: f3ef 8710 mrs r7, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004834: f385 8810 msr PRIMASK, r5
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8004838: 6821 ldr r1, [r4, #0]
|
|
800483a: 4e5d ldr r6, [pc, #372] @ (80049b0 <HAL_UART_IRQHandler+0x324>)
|
|
800483c: 680a ldr r2, [r1, #0]
|
|
800483e: 4032 ands r2, r6
|
|
8004840: 600a str r2, [r1, #0]
|
|
8004842: f387 8810 msr PRIMASK, r7
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004846: f3ef 8710 mrs r7, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800484a: f385 8810 msr PRIMASK, r5
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
800484e: 6821 ldr r1, [r4, #0]
|
|
8004850: 688a ldr r2, [r1, #8]
|
|
8004852: 43aa bics r2, r5
|
|
8004854: 608a str r2, [r1, #8]
|
|
8004856: f387 8810 msr PRIMASK, r7
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
800485a: f3ef 8710 mrs r7, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800485e: f385 8810 msr PRIMASK, r5
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8004862: 6821 ldr r1, [r4, #0]
|
|
8004864: 688a ldr r2, [r1, #8]
|
|
8004866: 439a bics r2, r3
|
|
8004868: 608a str r2, [r1, #8]
|
|
800486a: f387 8810 msr PRIMASK, r7
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800486e: 0023 movs r3, r4
|
|
8004870: 4662 mov r2, ip
|
|
8004872: 338c adds r3, #140 @ 0x8c
|
|
8004874: 601a str r2, [r3, #0]
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004876: 9b00 ldr r3, [sp, #0]
|
|
8004878: 66e3 str r3, [r4, #108] @ 0x6c
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
800487a: f3ef 8110 mrs r1, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800487e: f385 8810 msr PRIMASK, r5
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8004882: 6822 ldr r2, [r4, #0]
|
|
8004884: 350f adds r5, #15
|
|
8004886: 6813 ldr r3, [r2, #0]
|
|
8004888: 43ab bics r3, r5
|
|
800488a: 6013 str r3, [r2, #0]
|
|
800488c: f381 8810 msr PRIMASK, r1
|
|
(void)HAL_DMA_Abort(huart->hdmarx);
|
|
8004890: 6fc0 ldr r0, [r0, #124] @ 0x7c
|
|
8004892: f7fe fbcb bl 800302c <HAL_DMA_Abort>
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
8004896: 2302 movs r3, #2
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
8004898: 0022 movs r2, r4
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
800489a: 6723 str r3, [r4, #112] @ 0x70
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
800489c: 0023 movs r3, r4
|
|
800489e: 325c adds r2, #92 @ 0x5c
|
|
80048a0: 335e adds r3, #94 @ 0x5e
|
|
80048a2: 881b ldrh r3, [r3, #0]
|
|
80048a4: 8811 ldrh r1, [r2, #0]
|
|
80048a6: 1ac9 subs r1, r1, r3
|
|
80048a8: b289 uxth r1, r1
|
|
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
|
|
80048aa: 0020 movs r0, r4
|
|
80048ac: f7fc f89c bl 80009e8 <HAL_UARTEx_RxEventCallback>
|
|
80048b0: e78c b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
if (nb_remaining_rx_data == huart->RxXferSize)
|
|
80048b2: 4291 cmp r1, r2
|
|
80048b4: d000 beq.n 80048b8 <HAL_UART_IRQHandler+0x22c>
|
|
80048b6: e789 b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
|
|
80048b8: 683b ldr r3, [r7, #0]
|
|
80048ba: 069b lsls r3, r3, #26
|
|
80048bc: d400 bmi.n 80048c0 <HAL_UART_IRQHandler+0x234>
|
|
80048be: e785 b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
80048c0: 2302 movs r3, #2
|
|
80048c2: 6723 str r3, [r4, #112] @ 0x70
|
|
80048c4: e7f1 b.n 80048aa <HAL_UART_IRQHandler+0x21e>
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
80048c6: 0021 movs r1, r4
|
|
80048c8: 315e adds r1, #94 @ 0x5e
|
|
80048ca: 880b ldrh r3, [r1, #0]
|
|
if ((huart->RxXferCount > 0U)
|
|
80048cc: 8809 ldrh r1, [r1, #0]
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
80048ce: b29b uxth r3, r3
|
|
if ((huart->RxXferCount > 0U)
|
|
80048d0: 2900 cmp r1, #0
|
|
80048d2: d100 bne.n 80048d6 <HAL_UART_IRQHandler+0x24a>
|
|
80048d4: e77a b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
|
|
80048d6: 1ad2 subs r2, r2, r3
|
|
80048d8: b291 uxth r1, r2
|
|
&& (nb_rx_data > 0U))
|
|
80048da: 2900 cmp r1, #0
|
|
80048dc: d100 bne.n 80048e0 <HAL_UART_IRQHandler+0x254>
|
|
80048de: e775 b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
80048e0: f3ef 8710 mrs r7, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80048e4: f385 8810 msr PRIMASK, r5
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
80048e8: 6822 ldr r2, [r4, #0]
|
|
80048ea: 4e32 ldr r6, [pc, #200] @ (80049b4 <HAL_UART_IRQHandler+0x328>)
|
|
80048ec: 6813 ldr r3, [r2, #0]
|
|
80048ee: 4033 ands r3, r6
|
|
80048f0: 6013 str r3, [r2, #0]
|
|
80048f2: f387 8810 msr PRIMASK, r7
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
80048f6: f3ef 8710 mrs r7, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
80048fa: f385 8810 msr PRIMASK, r5
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
|
|
80048fe: 6822 ldr r2, [r4, #0]
|
|
8004900: 4e2d ldr r6, [pc, #180] @ (80049b8 <HAL_UART_IRQHandler+0x32c>)
|
|
8004902: 6893 ldr r3, [r2, #8]
|
|
8004904: 4033 ands r3, r6
|
|
8004906: 6093 str r3, [r2, #8]
|
|
8004908: f387 8810 msr PRIMASK, r7
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
800490c: 0023 movs r3, r4
|
|
800490e: 2220 movs r2, #32
|
|
8004910: 338c adds r3, #140 @ 0x8c
|
|
8004912: 601a str r2, [r3, #0]
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004914: 66e0 str r0, [r4, #108] @ 0x6c
|
|
huart->RxISR = NULL;
|
|
8004916: 6760 str r0, [r4, #116] @ 0x74
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004918: f3ef 8010 mrs r0, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800491c: f385 8810 msr PRIMASK, r5
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8004920: 2510 movs r5, #16
|
|
8004922: 6822 ldr r2, [r4, #0]
|
|
8004924: 6813 ldr r3, [r2, #0]
|
|
8004926: 43ab bics r3, r5
|
|
8004928: 6013 str r3, [r2, #0]
|
|
800492a: f380 8810 msr PRIMASK, r0
|
|
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
|
|
800492e: e7c7 b.n 80048c0 <HAL_UART_IRQHandler+0x234>
|
|
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
|
|
8004930: 2580 movs r5, #128 @ 0x80
|
|
8004932: 036d lsls r5, r5, #13
|
|
8004934: 422b tst r3, r5
|
|
8004936: d006 beq.n 8004946 <HAL_UART_IRQHandler+0x2ba>
|
|
8004938: 0246 lsls r6, r0, #9
|
|
800493a: d504 bpl.n 8004946 <HAL_UART_IRQHandler+0x2ba>
|
|
HAL_UARTEx_WakeupCallback(huart);
|
|
800493c: 0020 movs r0, r4
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
|
|
800493e: 620d str r5, [r1, #32]
|
|
HAL_UARTEx_WakeupCallback(huart);
|
|
8004940: f000 fbfa bl 8005138 <HAL_UARTEx_WakeupCallback>
|
|
return;
|
|
8004944: e742 b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
|
|
8004946: 2180 movs r1, #128 @ 0x80
|
|
8004948: 420b tst r3, r1
|
|
800494a: d007 beq.n 800495c <HAL_UART_IRQHandler+0x2d0>
|
|
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
|
|
800494c: 2580 movs r5, #128 @ 0x80
|
|
800494e: 042d lsls r5, r5, #16
|
|
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
|
|
8004950: 4011 ands r1, r2
|
|
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
|
|
8004952: 4028 ands r0, r5
|
|
8004954: 4301 orrs r1, r0
|
|
8004956: d001 beq.n 800495c <HAL_UART_IRQHandler+0x2d0>
|
|
if (huart->TxISR != NULL)
|
|
8004958: 6fa3 ldr r3, [r4, #120] @ 0x78
|
|
800495a: e6ac b.n 80046b6 <HAL_UART_IRQHandler+0x2a>
|
|
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
|
|
800495c: 2140 movs r1, #64 @ 0x40
|
|
800495e: 420b tst r3, r1
|
|
8004960: d016 beq.n 8004990 <HAL_UART_IRQHandler+0x304>
|
|
8004962: 420a tst r2, r1
|
|
8004964: d014 beq.n 8004990 <HAL_UART_IRQHandler+0x304>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004966: f3ef 8010 mrs r0, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800496a: 2301 movs r3, #1
|
|
800496c: f383 8810 msr PRIMASK, r3
|
|
* @retval None
|
|
*/
|
|
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
|
|
{
|
|
/* Disable the UART Transmit Complete Interrupt */
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
|
|
8004970: 6822 ldr r2, [r4, #0]
|
|
8004972: 6813 ldr r3, [r2, #0]
|
|
8004974: 438b bics r3, r1
|
|
8004976: 6013 str r3, [r2, #0]
|
|
8004978: f380 8810 msr PRIMASK, r0
|
|
|
|
/* Tx process is ended, restore huart->gState to Ready */
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800497c: 0023 movs r3, r4
|
|
800497e: 2220 movs r2, #32
|
|
8004980: 3388 adds r3, #136 @ 0x88
|
|
8004982: 601a str r2, [r3, #0]
|
|
|
|
/* Cleat TxISR function pointer */
|
|
huart->TxISR = NULL;
|
|
8004984: 2300 movs r3, #0
|
|
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
|
/*Call registered Tx complete callback*/
|
|
huart->TxCpltCallback(huart);
|
|
#else
|
|
/*Call legacy weak Tx complete callback*/
|
|
HAL_UART_TxCpltCallback(huart);
|
|
8004986: 0020 movs r0, r4
|
|
huart->TxISR = NULL;
|
|
8004988: 67a3 str r3, [r4, #120] @ 0x78
|
|
HAL_UART_TxCpltCallback(huart);
|
|
800498a: f7ff fe49 bl 8004620 <HAL_UART_TxCpltCallback>
|
|
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
|
|
}
|
|
800498e: e71d b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
|
|
8004990: 0219 lsls r1, r3, #8
|
|
8004992: d513 bpl.n 80049bc <HAL_UART_IRQHandler+0x330>
|
|
8004994: 0051 lsls r1, r2, #1
|
|
8004996: d511 bpl.n 80049bc <HAL_UART_IRQHandler+0x330>
|
|
HAL_UARTEx_TxFifoEmptyCallback(huart);
|
|
8004998: 0020 movs r0, r4
|
|
800499a: f000 fbcf bl 800513c <HAL_UARTEx_TxFifoEmptyCallback>
|
|
return;
|
|
800499e: e715 b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
80049a0: 0000080f .word 0x0000080f
|
|
80049a4: 10000001 .word 0x10000001
|
|
80049a8: 04000120 .word 0x04000120
|
|
80049ac: 0800467b .word 0x0800467b
|
|
80049b0: fffffeff .word 0xfffffeff
|
|
80049b4: fffffedf .word 0xfffffedf
|
|
80049b8: effffffe .word 0xeffffffe
|
|
if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
|
|
80049bc: 01db lsls r3, r3, #7
|
|
80049be: d400 bmi.n 80049c2 <HAL_UART_IRQHandler+0x336>
|
|
80049c0: e704 b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
80049c2: 2a00 cmp r2, #0
|
|
80049c4: db00 blt.n 80049c8 <HAL_UART_IRQHandler+0x33c>
|
|
80049c6: e701 b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
HAL_UARTEx_RxFifoFullCallback(huart);
|
|
80049c8: 0020 movs r0, r4
|
|
80049ca: f000 fbb6 bl 800513a <HAL_UARTEx_RxFifoFullCallback>
|
|
return;
|
|
80049ce: e6fd b.n 80047cc <HAL_UART_IRQHandler+0x140>
|
|
|
|
080049d0 <UART_DMARxHalfCplt>:
|
|
huart->RxEventType = HAL_UART_RXEVENT_HT;
|
|
80049d0: 2201 movs r2, #1
|
|
{
|
|
80049d2: 0003 movs r3, r0
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
80049d4: 6a80 ldr r0, [r0, #40] @ 0x28
|
|
{
|
|
80049d6: b510 push {r4, lr}
|
|
huart->RxEventType = HAL_UART_RXEVENT_HT;
|
|
80049d8: 6702 str r2, [r0, #112] @ 0x70
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
80049da: 6ec2 ldr r2, [r0, #108] @ 0x6c
|
|
80049dc: 2a01 cmp r2, #1
|
|
80049de: d111 bne.n 8004a04 <UART_DMARxHalfCplt+0x34>
|
|
huart->RxXferCount = huart->RxXferSize / 2U;
|
|
80049e0: 0002 movs r2, r0
|
|
80049e2: 325c adds r2, #92 @ 0x5c
|
|
80049e4: 8811 ldrh r1, [r2, #0]
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
|
|
80049e6: 681b ldr r3, [r3, #0]
|
|
huart->RxXferCount = huart->RxXferSize / 2U;
|
|
80049e8: 084c lsrs r4, r1, #1
|
|
80049ea: 8054 strh r4, [r2, #2]
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
|
|
80049ec: 685b ldr r3, [r3, #4]
|
|
huart->RxXferCount = huart->RxXferSize / 2U;
|
|
80049ee: 3202 adds r2, #2
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
|
|
80049f0: b29b uxth r3, r3
|
|
if (nb_remaining_rx_data <= huart->RxXferSize)
|
|
80049f2: 4299 cmp r1, r3
|
|
80049f4: d300 bcc.n 80049f8 <UART_DMARxHalfCplt+0x28>
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
80049f6: 8013 strh r3, [r2, #0]
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
80049f8: 8813 ldrh r3, [r2, #0]
|
|
80049fa: 1ac9 subs r1, r1, r3
|
|
80049fc: b289 uxth r1, r1
|
|
80049fe: f7fb fff3 bl 80009e8 <HAL_UARTEx_RxEventCallback>
|
|
}
|
|
8004a02: bd10 pop {r4, pc}
|
|
HAL_UART_RxHalfCpltCallback(huart);
|
|
8004a04: f7ff fe0e bl 8004624 <HAL_UART_RxHalfCpltCallback>
|
|
}
|
|
8004a08: e7fb b.n 8004a02 <UART_DMARxHalfCplt+0x32>
|
|
...
|
|
|
|
08004a0c <UART_DMAReceiveCplt>:
|
|
{
|
|
8004a0c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8004a0e: 0003 movs r3, r0
|
|
if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
|
|
8004a10: 681a ldr r2, [r3, #0]
|
|
8004a12: 2120 movs r1, #32
|
|
8004a14: 6812 ldr r2, [r2, #0]
|
|
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
|
|
8004a16: 6a80 ldr r0, [r0, #40] @ 0x28
|
|
if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
|
|
8004a18: 0014 movs r4, r2
|
|
8004a1a: 400c ands r4, r1
|
|
8004a1c: 420a tst r2, r1
|
|
8004a1e: d134 bne.n 8004a8a <UART_DMAReceiveCplt+0x7e>
|
|
huart->RxXferCount = 0U;
|
|
8004a20: 0002 movs r2, r0
|
|
8004a22: 325e adds r2, #94 @ 0x5e
|
|
8004a24: 8014 strh r4, [r2, #0]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004a26: f3ef 8610 mrs r6, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004a2a: 2201 movs r2, #1
|
|
8004a2c: f382 8810 msr PRIMASK, r2
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8004a30: 6805 ldr r5, [r0, #0]
|
|
8004a32: 4f23 ldr r7, [pc, #140] @ (8004ac0 <UART_DMAReceiveCplt+0xb4>)
|
|
8004a34: 682c ldr r4, [r5, #0]
|
|
8004a36: 403c ands r4, r7
|
|
8004a38: 602c str r4, [r5, #0]
|
|
8004a3a: f386 8810 msr PRIMASK, r6
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004a3e: f3ef 8610 mrs r6, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004a42: f382 8810 msr PRIMASK, r2
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8004a46: 6805 ldr r5, [r0, #0]
|
|
8004a48: 68ac ldr r4, [r5, #8]
|
|
8004a4a: 4394 bics r4, r2
|
|
8004a4c: 60ac str r4, [r5, #8]
|
|
8004a4e: f386 8810 msr PRIMASK, r6
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004a52: f3ef 8510 mrs r5, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004a56: f382 8810 msr PRIMASK, r2
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
8004a5a: 2640 movs r6, #64 @ 0x40
|
|
8004a5c: 6804 ldr r4, [r0, #0]
|
|
8004a5e: 68a2 ldr r2, [r4, #8]
|
|
8004a60: 43b2 bics r2, r6
|
|
8004a62: 60a2 str r2, [r4, #8]
|
|
8004a64: f385 8810 msr PRIMASK, r5
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004a68: 0002 movs r2, r0
|
|
8004a6a: 328c adds r2, #140 @ 0x8c
|
|
8004a6c: 6011 str r1, [r2, #0]
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8004a6e: 6ec2 ldr r2, [r0, #108] @ 0x6c
|
|
8004a70: 2a01 cmp r2, #1
|
|
8004a72: d10a bne.n 8004a8a <UART_DMAReceiveCplt+0x7e>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004a74: f3ef 8410 mrs r4, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004a78: f382 8810 msr PRIMASK, r2
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8004a7c: 2510 movs r5, #16
|
|
8004a7e: 6801 ldr r1, [r0, #0]
|
|
8004a80: 680a ldr r2, [r1, #0]
|
|
8004a82: 43aa bics r2, r5
|
|
8004a84: 600a str r2, [r1, #0]
|
|
8004a86: f384 8810 msr PRIMASK, r4
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8004a8a: 2100 movs r1, #0
|
|
8004a8c: 6701 str r1, [r0, #112] @ 0x70
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8004a8e: 6ec2 ldr r2, [r0, #108] @ 0x6c
|
|
8004a90: 2a01 cmp r2, #1
|
|
8004a92: d111 bne.n 8004ab8 <UART_DMAReceiveCplt+0xac>
|
|
huart->RxXferCount = 0;
|
|
8004a94: 0002 movs r2, r0
|
|
8004a96: 325e adds r2, #94 @ 0x5e
|
|
8004a98: 8011 strh r1, [r2, #0]
|
|
if (nb_remaining_rx_data < huart->RxXferSize)
|
|
8004a9a: 0001 movs r1, r0
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
|
|
8004a9c: 681b ldr r3, [r3, #0]
|
|
if (nb_remaining_rx_data < huart->RxXferSize)
|
|
8004a9e: 315c adds r1, #92 @ 0x5c
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
|
|
8004aa0: 685b ldr r3, [r3, #4]
|
|
if (nb_remaining_rx_data < huart->RxXferSize)
|
|
8004aa2: 8809 ldrh r1, [r1, #0]
|
|
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
|
|
8004aa4: b29b uxth r3, r3
|
|
if (nb_remaining_rx_data < huart->RxXferSize)
|
|
8004aa6: 4299 cmp r1, r3
|
|
8004aa8: d900 bls.n 8004aac <UART_DMAReceiveCplt+0xa0>
|
|
huart->RxXferCount = nb_remaining_rx_data;
|
|
8004aaa: 8013 strh r3, [r2, #0]
|
|
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
|
|
8004aac: 8813 ldrh r3, [r2, #0]
|
|
8004aae: 1ac9 subs r1, r1, r3
|
|
8004ab0: b289 uxth r1, r1
|
|
8004ab2: f7fb ff99 bl 80009e8 <HAL_UARTEx_RxEventCallback>
|
|
}
|
|
8004ab6: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
HAL_UART_RxCpltCallback(huart);
|
|
8004ab8: f7ff fdb3 bl 8004622 <HAL_UART_RxCpltCallback>
|
|
}
|
|
8004abc: e7fb b.n 8004ab6 <UART_DMAReceiveCplt+0xaa>
|
|
8004abe: 46c0 nop @ (mov r8, r8)
|
|
8004ac0: fffffeff .word 0xfffffeff
|
|
|
|
08004ac4 <UART_SetConfig>:
|
|
{
|
|
8004ac4: b570 push {r4, r5, r6, lr}
|
|
8004ac6: 0004 movs r4, r0
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
8004ac8: 6925 ldr r5, [r4, #16]
|
|
8004aca: 68a1 ldr r1, [r4, #8]
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
8004acc: 6803 ldr r3, [r0, #0]
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
8004ace: 4329 orrs r1, r5
|
|
8004ad0: 6965 ldr r5, [r4, #20]
|
|
8004ad2: 69c2 ldr r2, [r0, #28]
|
|
8004ad4: 4329 orrs r1, r5
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
8004ad6: 6818 ldr r0, [r3, #0]
|
|
8004ad8: 4d50 ldr r5, [pc, #320] @ (8004c1c <UART_SetConfig+0x158>)
|
|
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
|
|
8004ada: 4311 orrs r1, r2
|
|
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
|
|
8004adc: 4028 ands r0, r5
|
|
8004ade: 4301 orrs r1, r0
|
|
8004ae0: 6019 str r1, [r3, #0]
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
8004ae2: 6859 ldr r1, [r3, #4]
|
|
8004ae4: 484e ldr r0, [pc, #312] @ (8004c20 <UART_SetConfig+0x15c>)
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
8004ae6: 6a25 ldr r5, [r4, #32]
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
|
|
8004ae8: 4001 ands r1, r0
|
|
8004aea: 68e0 ldr r0, [r4, #12]
|
|
8004aec: 4301 orrs r1, r0
|
|
8004aee: 6059 str r1, [r3, #4]
|
|
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
|
|
8004af0: 69a1 ldr r1, [r4, #24]
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
8004af2: 6898 ldr r0, [r3, #8]
|
|
tmpreg |= huart->Init.OneBitSampling;
|
|
8004af4: 4329 orrs r1, r5
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
8004af6: 4d4b ldr r5, [pc, #300] @ (8004c24 <UART_SetConfig+0x160>)
|
|
8004af8: 4028 ands r0, r5
|
|
8004afa: 4301 orrs r1, r0
|
|
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
|
|
8004afc: 200f movs r0, #15
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
|
|
8004afe: 6099 str r1, [r3, #8]
|
|
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
|
|
8004b00: 6ad9 ldr r1, [r3, #44] @ 0x2c
|
|
8004b02: 4381 bics r1, r0
|
|
8004b04: 6a60 ldr r0, [r4, #36] @ 0x24
|
|
8004b06: 4301 orrs r1, r0
|
|
8004b08: 62d9 str r1, [r3, #44] @ 0x2c
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
8004b0a: 4947 ldr r1, [pc, #284] @ (8004c28 <UART_SetConfig+0x164>)
|
|
8004b0c: 428b cmp r3, r1
|
|
8004b0e: d115 bne.n 8004b3c <UART_SetConfig+0x78>
|
|
8004b10: 2103 movs r1, #3
|
|
8004b12: 4b46 ldr r3, [pc, #280] @ (8004c2c <UART_SetConfig+0x168>)
|
|
8004b14: 6d5b ldr r3, [r3, #84] @ 0x54
|
|
8004b16: 400b ands r3, r1
|
|
8004b18: 3b01 subs r3, #1
|
|
8004b1a: 2b02 cmp r3, #2
|
|
8004b1c: d86f bhi.n 8004bfe <UART_SetConfig+0x13a>
|
|
8004b1e: 4944 ldr r1, [pc, #272] @ (8004c30 <UART_SetConfig+0x16c>)
|
|
8004b20: 5cc8 ldrb r0, [r1, r3]
|
|
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8004b22: 2380 movs r3, #128 @ 0x80
|
|
8004b24: 021b lsls r3, r3, #8
|
|
8004b26: 429a cmp r2, r3
|
|
8004b28: d137 bne.n 8004b9a <UART_SetConfig+0xd6>
|
|
switch (clocksource)
|
|
8004b2a: 2808 cmp r0, #8
|
|
8004b2c: d865 bhi.n 8004bfa <UART_SetConfig+0x136>
|
|
8004b2e: f7fb faeb bl 8000108 <__gnu_thumb1_case_uqi>
|
|
8004b32: 646a .short 0x646a
|
|
8004b34: 6431640b .word 0x6431640b
|
|
8004b38: 6464 .short 0x6464
|
|
8004b3a: 14 .byte 0x14
|
|
8004b3b: 00 .byte 0x00
|
|
UART_GETCLOCKSOURCE(huart, clocksource);
|
|
8004b3c: 493d ldr r1, [pc, #244] @ (8004c34 <UART_SetConfig+0x170>)
|
|
8004b3e: 185b adds r3, r3, r1
|
|
8004b40: 1e59 subs r1, r3, #1
|
|
8004b42: 418b sbcs r3, r1
|
|
8004b44: 0118 lsls r0, r3, #4
|
|
8004b46: e7ec b.n 8004b22 <UART_SetConfig+0x5e>
|
|
pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
|
|
8004b48: 4b38 ldr r3, [pc, #224] @ (8004c2c <UART_SetConfig+0x168>)
|
|
8004b4a: 483b ldr r0, [pc, #236] @ (8004c38 <UART_SetConfig+0x174>)
|
|
8004b4c: 6819 ldr r1, [r3, #0]
|
|
8004b4e: 0609 lsls r1, r1, #24
|
|
8004b50: 0f49 lsrs r1, r1, #29
|
|
8004b52: 3101 adds r1, #1
|
|
8004b54: f7fb faec bl 8000130 <__udivsi3>
|
|
8004b58: 0002 movs r2, r0
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
8004b5a: 6a61 ldr r1, [r4, #36] @ 0x24
|
|
8004b5c: 4b37 ldr r3, [pc, #220] @ (8004c3c <UART_SetConfig+0x178>)
|
|
8004b5e: 0049 lsls r1, r1, #1
|
|
8004b60: 0010 movs r0, r2
|
|
8004b62: 5ac9 ldrh r1, [r1, r3]
|
|
8004b64: f7fb fae4 bl 8000130 <__udivsi3>
|
|
8004b68: 6865 ldr r5, [r4, #4]
|
|
8004b6a: 0040 lsls r0, r0, #1
|
|
8004b6c: 086b lsrs r3, r5, #1
|
|
8004b6e: 18c0 adds r0, r0, r3
|
|
8004b70: 0029 movs r1, r5
|
|
8004b72: f7fb fadd bl 8000130 <__udivsi3>
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8004b76: 0002 movs r2, r0
|
|
8004b78: 4b31 ldr r3, [pc, #196] @ (8004c40 <UART_SetConfig+0x17c>)
|
|
8004b7a: 3a10 subs r2, #16
|
|
8004b7c: 429a cmp r2, r3
|
|
8004b7e: d83c bhi.n 8004bfa <UART_SetConfig+0x136>
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
8004b80: 230f movs r3, #15
|
|
8004b82: 0002 movs r2, r0
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
8004b84: 0700 lsls r0, r0, #28
|
|
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
|
|
8004b86: 439a bics r2, r3
|
|
8004b88: b293 uxth r3, r2
|
|
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
|
|
8004b8a: 0f40 lsrs r0, r0, #29
|
|
huart->Instance->BRR = brrtemp;
|
|
8004b8c: 6822 ldr r2, [r4, #0]
|
|
8004b8e: 4303 orrs r3, r0
|
|
8004b90: 60d3 str r3, [r2, #12]
|
|
8004b92: e03c b.n 8004c0e <UART_SetConfig+0x14a>
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8004b94: f7fe fd2a bl 80035ec <HAL_RCC_GetSysClockFreq>
|
|
8004b98: e037 b.n 8004c0a <UART_SetConfig+0x146>
|
|
switch (clocksource)
|
|
8004b9a: 2808 cmp r0, #8
|
|
8004b9c: d82d bhi.n 8004bfa <UART_SetConfig+0x136>
|
|
8004b9e: f7fb fab3 bl 8000108 <__gnu_thumb1_case_uqi>
|
|
8004ba2: 2c05 .short 0x2c05
|
|
8004ba4: 2c262c0a .word 0x2c262c0a
|
|
8004ba8: 2c2c .short 0x2c2c
|
|
8004baa: 29 .byte 0x29
|
|
8004bab: 00 .byte 0x00
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8004bac: f7fe fe14 bl 80037d8 <HAL_RCC_GetPCLK1Freq>
|
|
if (pclk != 0U)
|
|
8004bb0: 2800 cmp r0, #0
|
|
8004bb2: d02c beq.n 8004c0e <UART_SetConfig+0x14a>
|
|
8004bb4: e007 b.n 8004bc6 <UART_SetConfig+0x102>
|
|
pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
|
|
8004bb6: 4b1d ldr r3, [pc, #116] @ (8004c2c <UART_SetConfig+0x168>)
|
|
8004bb8: 481f ldr r0, [pc, #124] @ (8004c38 <UART_SetConfig+0x174>)
|
|
8004bba: 6819 ldr r1, [r3, #0]
|
|
8004bbc: 0609 lsls r1, r1, #24
|
|
8004bbe: 0f49 lsrs r1, r1, #29
|
|
8004bc0: 3101 adds r1, #1
|
|
8004bc2: f7fb fab5 bl 8000130 <__udivsi3>
|
|
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
|
|
8004bc6: 6a62 ldr r2, [r4, #36] @ 0x24
|
|
8004bc8: 4b1c ldr r3, [pc, #112] @ (8004c3c <UART_SetConfig+0x178>)
|
|
8004bca: 0052 lsls r2, r2, #1
|
|
8004bcc: 5ad1 ldrh r1, [r2, r3]
|
|
8004bce: f7fb faaf bl 8000130 <__udivsi3>
|
|
8004bd2: 6865 ldr r5, [r4, #4]
|
|
8004bd4: 086b lsrs r3, r5, #1
|
|
8004bd6: 18c0 adds r0, r0, r3
|
|
8004bd8: 0029 movs r1, r5
|
|
8004bda: f7fb faa9 bl 8000130 <__udivsi3>
|
|
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
|
|
8004bde: 0002 movs r2, r0
|
|
8004be0: 4b17 ldr r3, [pc, #92] @ (8004c40 <UART_SetConfig+0x17c>)
|
|
8004be2: 3a10 subs r2, #16
|
|
8004be4: 429a cmp r2, r3
|
|
8004be6: d808 bhi.n 8004bfa <UART_SetConfig+0x136>
|
|
huart->Instance->BRR = (uint16_t)usartdiv;
|
|
8004be8: 6823 ldr r3, [r4, #0]
|
|
8004bea: 60d8 str r0, [r3, #12]
|
|
8004bec: e00f b.n 8004c0e <UART_SetConfig+0x14a>
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8004bee: f7fe fcfd bl 80035ec <HAL_RCC_GetSysClockFreq>
|
|
break;
|
|
8004bf2: e7dd b.n 8004bb0 <UART_SetConfig+0xec>
|
|
switch (clocksource)
|
|
8004bf4: 2080 movs r0, #128 @ 0x80
|
|
8004bf6: 0200 lsls r0, r0, #8
|
|
8004bf8: e7e5 b.n 8004bc6 <UART_SetConfig+0x102>
|
|
ret = HAL_ERROR;
|
|
8004bfa: 2001 movs r0, #1
|
|
8004bfc: e008 b.n 8004c10 <UART_SetConfig+0x14c>
|
|
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
|
|
8004bfe: 2380 movs r3, #128 @ 0x80
|
|
8004c00: 021b lsls r3, r3, #8
|
|
8004c02: 429a cmp r2, r3
|
|
8004c04: d1d2 bne.n 8004bac <UART_SetConfig+0xe8>
|
|
pclk = HAL_RCC_GetPCLK1Freq();
|
|
8004c06: f7fe fde7 bl 80037d8 <HAL_RCC_GetPCLK1Freq>
|
|
pclk = HAL_RCC_GetSysClockFreq();
|
|
8004c0a: 1e02 subs r2, r0, #0
|
|
if (pclk != 0U)
|
|
8004c0c: d1a5 bne.n 8004b5a <UART_SetConfig+0x96>
|
|
switch (clocksource)
|
|
8004c0e: 2000 movs r0, #0
|
|
huart->NbRxDataToProcess = 1;
|
|
8004c10: 4b0c ldr r3, [pc, #48] @ (8004c44 <UART_SetConfig+0x180>)
|
|
8004c12: 66a3 str r3, [r4, #104] @ 0x68
|
|
huart->RxISR = NULL;
|
|
8004c14: 2300 movs r3, #0
|
|
8004c16: 6763 str r3, [r4, #116] @ 0x74
|
|
huart->TxISR = NULL;
|
|
8004c18: 67a3 str r3, [r4, #120] @ 0x78
|
|
}
|
|
8004c1a: bd70 pop {r4, r5, r6, pc}
|
|
8004c1c: cfff69f3 .word 0xcfff69f3
|
|
8004c20: ffffcfff .word 0xffffcfff
|
|
8004c24: 11fff4ff .word 0x11fff4ff
|
|
8004c28: 40013800 .word 0x40013800
|
|
8004c2c: 40021000 .word 0x40021000
|
|
8004c30: 08005380 .word 0x08005380
|
|
8004c34: bfffbc00 .word 0xbfffbc00
|
|
8004c38: 02dc6c00 .word 0x02dc6c00
|
|
8004c3c: 08005384 .word 0x08005384
|
|
8004c40: 0000ffef .word 0x0000ffef
|
|
8004c44: 00010001 .word 0x00010001
|
|
|
|
08004c48 <UART_AdvFeatureConfig>:
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
8004c48: 6a83 ldr r3, [r0, #40] @ 0x28
|
|
{
|
|
8004c4a: b530 push {r4, r5, lr}
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
|
8004c4c: 071a lsls r2, r3, #28
|
|
8004c4e: d506 bpl.n 8004c5e <UART_AdvFeatureConfig+0x16>
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
|
8004c50: 6801 ldr r1, [r0, #0]
|
|
8004c52: 4c28 ldr r4, [pc, #160] @ (8004cf4 <UART_AdvFeatureConfig+0xac>)
|
|
8004c54: 684a ldr r2, [r1, #4]
|
|
8004c56: 4022 ands r2, r4
|
|
8004c58: 6b84 ldr r4, [r0, #56] @ 0x38
|
|
8004c5a: 4322 orrs r2, r4
|
|
8004c5c: 604a str r2, [r1, #4]
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
|
8004c5e: 07da lsls r2, r3, #31
|
|
8004c60: d506 bpl.n 8004c70 <UART_AdvFeatureConfig+0x28>
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
|
|
8004c62: 6801 ldr r1, [r0, #0]
|
|
8004c64: 4c24 ldr r4, [pc, #144] @ (8004cf8 <UART_AdvFeatureConfig+0xb0>)
|
|
8004c66: 684a ldr r2, [r1, #4]
|
|
8004c68: 4022 ands r2, r4
|
|
8004c6a: 6ac4 ldr r4, [r0, #44] @ 0x2c
|
|
8004c6c: 4322 orrs r2, r4
|
|
8004c6e: 604a str r2, [r1, #4]
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
|
|
8004c70: 079a lsls r2, r3, #30
|
|
8004c72: d506 bpl.n 8004c82 <UART_AdvFeatureConfig+0x3a>
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
|
|
8004c74: 6801 ldr r1, [r0, #0]
|
|
8004c76: 4c21 ldr r4, [pc, #132] @ (8004cfc <UART_AdvFeatureConfig+0xb4>)
|
|
8004c78: 684a ldr r2, [r1, #4]
|
|
8004c7a: 4022 ands r2, r4
|
|
8004c7c: 6b04 ldr r4, [r0, #48] @ 0x30
|
|
8004c7e: 4322 orrs r2, r4
|
|
8004c80: 604a str r2, [r1, #4]
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
|
|
8004c82: 075a lsls r2, r3, #29
|
|
8004c84: d506 bpl.n 8004c94 <UART_AdvFeatureConfig+0x4c>
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
|
8004c86: 6801 ldr r1, [r0, #0]
|
|
8004c88: 4c1d ldr r4, [pc, #116] @ (8004d00 <UART_AdvFeatureConfig+0xb8>)
|
|
8004c8a: 684a ldr r2, [r1, #4]
|
|
8004c8c: 4022 ands r2, r4
|
|
8004c8e: 6b44 ldr r4, [r0, #52] @ 0x34
|
|
8004c90: 4322 orrs r2, r4
|
|
8004c92: 604a str r2, [r1, #4]
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
|
8004c94: 06da lsls r2, r3, #27
|
|
8004c96: d506 bpl.n 8004ca6 <UART_AdvFeatureConfig+0x5e>
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
|
|
8004c98: 6801 ldr r1, [r0, #0]
|
|
8004c9a: 4c1a ldr r4, [pc, #104] @ (8004d04 <UART_AdvFeatureConfig+0xbc>)
|
|
8004c9c: 688a ldr r2, [r1, #8]
|
|
8004c9e: 4022 ands r2, r4
|
|
8004ca0: 6bc4 ldr r4, [r0, #60] @ 0x3c
|
|
8004ca2: 4322 orrs r2, r4
|
|
8004ca4: 608a str r2, [r1, #8]
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
|
|
8004ca6: 069a lsls r2, r3, #26
|
|
8004ca8: d506 bpl.n 8004cb8 <UART_AdvFeatureConfig+0x70>
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
|
|
8004caa: 6801 ldr r1, [r0, #0]
|
|
8004cac: 4c16 ldr r4, [pc, #88] @ (8004d08 <UART_AdvFeatureConfig+0xc0>)
|
|
8004cae: 688a ldr r2, [r1, #8]
|
|
8004cb0: 4022 ands r2, r4
|
|
8004cb2: 6c04 ldr r4, [r0, #64] @ 0x40
|
|
8004cb4: 4322 orrs r2, r4
|
|
8004cb6: 608a str r2, [r1, #8]
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
|
|
8004cb8: 065a lsls r2, r3, #25
|
|
8004cba: d510 bpl.n 8004cde <UART_AdvFeatureConfig+0x96>
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
|
|
8004cbc: 6801 ldr r1, [r0, #0]
|
|
8004cbe: 4d13 ldr r5, [pc, #76] @ (8004d0c <UART_AdvFeatureConfig+0xc4>)
|
|
8004cc0: 684a ldr r2, [r1, #4]
|
|
8004cc2: 6c44 ldr r4, [r0, #68] @ 0x44
|
|
8004cc4: 402a ands r2, r5
|
|
8004cc6: 4322 orrs r2, r4
|
|
8004cc8: 604a str r2, [r1, #4]
|
|
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
|
|
8004cca: 2280 movs r2, #128 @ 0x80
|
|
8004ccc: 0352 lsls r2, r2, #13
|
|
8004cce: 4294 cmp r4, r2
|
|
8004cd0: d105 bne.n 8004cde <UART_AdvFeatureConfig+0x96>
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
|
|
8004cd2: 684a ldr r2, [r1, #4]
|
|
8004cd4: 4c0e ldr r4, [pc, #56] @ (8004d10 <UART_AdvFeatureConfig+0xc8>)
|
|
8004cd6: 4022 ands r2, r4
|
|
8004cd8: 6c84 ldr r4, [r0, #72] @ 0x48
|
|
8004cda: 4322 orrs r2, r4
|
|
8004cdc: 604a str r2, [r1, #4]
|
|
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
|
|
8004cde: 061b lsls r3, r3, #24
|
|
8004ce0: d506 bpl.n 8004cf0 <UART_AdvFeatureConfig+0xa8>
|
|
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
|
|
8004ce2: 6802 ldr r2, [r0, #0]
|
|
8004ce4: 490b ldr r1, [pc, #44] @ (8004d14 <UART_AdvFeatureConfig+0xcc>)
|
|
8004ce6: 6853 ldr r3, [r2, #4]
|
|
8004ce8: 400b ands r3, r1
|
|
8004cea: 6cc1 ldr r1, [r0, #76] @ 0x4c
|
|
8004cec: 430b orrs r3, r1
|
|
8004cee: 6053 str r3, [r2, #4]
|
|
}
|
|
8004cf0: bd30 pop {r4, r5, pc}
|
|
8004cf2: 46c0 nop @ (mov r8, r8)
|
|
8004cf4: ffff7fff .word 0xffff7fff
|
|
8004cf8: fffdffff .word 0xfffdffff
|
|
8004cfc: fffeffff .word 0xfffeffff
|
|
8004d00: fffbffff .word 0xfffbffff
|
|
8004d04: ffffefff .word 0xffffefff
|
|
8004d08: ffffdfff .word 0xffffdfff
|
|
8004d0c: ffefffff .word 0xffefffff
|
|
8004d10: ff9fffff .word 0xff9fffff
|
|
8004d14: fff7ffff .word 0xfff7ffff
|
|
|
|
08004d18 <UART_WaitOnFlagUntilTimeout>:
|
|
{
|
|
8004d18: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
8004d1a: 0004 movs r4, r0
|
|
8004d1c: 000d movs r5, r1
|
|
8004d1e: 0017 movs r7, r2
|
|
8004d20: 9300 str r3, [sp, #0]
|
|
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
|
|
8004d22: 6822 ldr r2, [r4, #0]
|
|
8004d24: 69d3 ldr r3, [r2, #28]
|
|
8004d26: 402b ands r3, r5
|
|
8004d28: 1b5b subs r3, r3, r5
|
|
8004d2a: 4259 negs r1, r3
|
|
8004d2c: 414b adcs r3, r1
|
|
8004d2e: 42bb cmp r3, r7
|
|
8004d30: d001 beq.n 8004d36 <UART_WaitOnFlagUntilTimeout+0x1e>
|
|
return HAL_OK;
|
|
8004d32: 2000 movs r0, #0
|
|
8004d34: e026 b.n 8004d84 <UART_WaitOnFlagUntilTimeout+0x6c>
|
|
if (Timeout != HAL_MAX_DELAY)
|
|
8004d36: 9b08 ldr r3, [sp, #32]
|
|
8004d38: 3301 adds r3, #1
|
|
8004d3a: d0f3 beq.n 8004d24 <UART_WaitOnFlagUntilTimeout+0xc>
|
|
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
|
8004d3c: f7fd fde8 bl 8002910 <HAL_GetTick>
|
|
8004d40: 9b00 ldr r3, [sp, #0]
|
|
8004d42: 1ac0 subs r0, r0, r3
|
|
8004d44: 9b08 ldr r3, [sp, #32]
|
|
8004d46: 4298 cmp r0, r3
|
|
8004d48: d82d bhi.n 8004da6 <UART_WaitOnFlagUntilTimeout+0x8e>
|
|
8004d4a: 2b00 cmp r3, #0
|
|
8004d4c: d02b beq.n 8004da6 <UART_WaitOnFlagUntilTimeout+0x8e>
|
|
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
|
|
8004d4e: 6823 ldr r3, [r4, #0]
|
|
8004d50: 681a ldr r2, [r3, #0]
|
|
8004d52: 0752 lsls r2, r2, #29
|
|
8004d54: d5e5 bpl.n 8004d22 <UART_WaitOnFlagUntilTimeout+0xa>
|
|
8004d56: 002a movs r2, r5
|
|
8004d58: 2140 movs r1, #64 @ 0x40
|
|
8004d5a: 3a40 subs r2, #64 @ 0x40
|
|
8004d5c: 438a bics r2, r1
|
|
8004d5e: d0e0 beq.n 8004d22 <UART_WaitOnFlagUntilTimeout+0xa>
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
|
8004d60: 69da ldr r2, [r3, #28]
|
|
8004d62: 2608 movs r6, #8
|
|
8004d64: 0011 movs r1, r2
|
|
8004d66: 4031 ands r1, r6
|
|
8004d68: 9101 str r1, [sp, #4]
|
|
8004d6a: 4232 tst r2, r6
|
|
8004d6c: d00b beq.n 8004d86 <UART_WaitOnFlagUntilTimeout+0x6e>
|
|
UART_EndRxTransfer(huart);
|
|
8004d6e: 0020 movs r0, r4
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
|
8004d70: 621e str r6, [r3, #32]
|
|
UART_EndRxTransfer(huart);
|
|
8004d72: f7ff fbc3 bl 80044fc <UART_EndRxTransfer>
|
|
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
|
8004d76: 0023 movs r3, r4
|
|
8004d78: 3390 adds r3, #144 @ 0x90
|
|
8004d7a: 601e str r6, [r3, #0]
|
|
__HAL_UNLOCK(huart);
|
|
8004d7c: 2300 movs r3, #0
|
|
return HAL_ERROR;
|
|
8004d7e: 2001 movs r0, #1
|
|
__HAL_UNLOCK(huart);
|
|
8004d80: 3484 adds r4, #132 @ 0x84
|
|
8004d82: 7023 strb r3, [r4, #0]
|
|
}
|
|
8004d84: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
|
|
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
|
8004d86: 2280 movs r2, #128 @ 0x80
|
|
8004d88: 69d9 ldr r1, [r3, #28]
|
|
8004d8a: 0112 lsls r2, r2, #4
|
|
8004d8c: 4211 tst r1, r2
|
|
8004d8e: d0c8 beq.n 8004d22 <UART_WaitOnFlagUntilTimeout+0xa>
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
|
|
8004d90: 621a str r2, [r3, #32]
|
|
UART_EndRxTransfer(huart);
|
|
8004d92: 0020 movs r0, r4
|
|
8004d94: f7ff fbb2 bl 80044fc <UART_EndRxTransfer>
|
|
huart->ErrorCode = HAL_UART_ERROR_RTO;
|
|
8004d98: 0023 movs r3, r4
|
|
8004d9a: 2220 movs r2, #32
|
|
8004d9c: 3390 adds r3, #144 @ 0x90
|
|
8004d9e: 601a str r2, [r3, #0]
|
|
__HAL_UNLOCK(huart);
|
|
8004da0: 9b01 ldr r3, [sp, #4]
|
|
8004da2: 3484 adds r4, #132 @ 0x84
|
|
8004da4: 7023 strb r3, [r4, #0]
|
|
return HAL_TIMEOUT;
|
|
8004da6: 2003 movs r0, #3
|
|
8004da8: e7ec b.n 8004d84 <UART_WaitOnFlagUntilTimeout+0x6c>
|
|
|
|
08004daa <HAL_UART_Transmit>:
|
|
{
|
|
8004daa: b5f0 push {r4, r5, r6, r7, lr}
|
|
8004dac: 0017 movs r7, r2
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8004dae: 0002 movs r2, r0
|
|
{
|
|
8004db0: b087 sub sp, #28
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8004db2: 3288 adds r2, #136 @ 0x88
|
|
{
|
|
8004db4: 9305 str r3, [sp, #20]
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8004db6: 6813 ldr r3, [r2, #0]
|
|
{
|
|
8004db8: 0004 movs r4, r0
|
|
8004dba: 000d movs r5, r1
|
|
return HAL_BUSY;
|
|
8004dbc: 2002 movs r0, #2
|
|
if (huart->gState == HAL_UART_STATE_READY)
|
|
8004dbe: 2b20 cmp r3, #32
|
|
8004dc0: d139 bne.n 8004e36 <HAL_UART_Transmit+0x8c>
|
|
return HAL_ERROR;
|
|
8004dc2: 3801 subs r0, #1
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8004dc4: 2900 cmp r1, #0
|
|
8004dc6: d036 beq.n 8004e36 <HAL_UART_Transmit+0x8c>
|
|
8004dc8: 2f00 cmp r7, #0
|
|
8004dca: d034 beq.n 8004e36 <HAL_UART_Transmit+0x8c>
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8004dcc: 2380 movs r3, #128 @ 0x80
|
|
8004dce: 68a1 ldr r1, [r4, #8]
|
|
8004dd0: 015b lsls r3, r3, #5
|
|
8004dd2: 4299 cmp r1, r3
|
|
8004dd4: d104 bne.n 8004de0 <HAL_UART_Transmit+0x36>
|
|
8004dd6: 6923 ldr r3, [r4, #16]
|
|
8004dd8: 2b00 cmp r3, #0
|
|
8004dda: d101 bne.n 8004de0 <HAL_UART_Transmit+0x36>
|
|
if ((((uint32_t)pData) & 1U) != 0U)
|
|
8004ddc: 4205 tst r5, r0
|
|
8004dde: d12a bne.n 8004e36 <HAL_UART_Transmit+0x8c>
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004de0: 0023 movs r3, r4
|
|
8004de2: 2600 movs r6, #0
|
|
8004de4: 3390 adds r3, #144 @ 0x90
|
|
8004de6: 601e str r6, [r3, #0]
|
|
huart->gState = HAL_UART_STATE_BUSY_TX;
|
|
8004de8: 2321 movs r3, #33 @ 0x21
|
|
8004dea: 6013 str r3, [r2, #0]
|
|
tickstart = HAL_GetTick();
|
|
8004dec: f7fd fd90 bl 8002910 <HAL_GetTick>
|
|
huart->TxXferSize = Size;
|
|
8004df0: 0023 movs r3, r4
|
|
8004df2: 3354 adds r3, #84 @ 0x54
|
|
8004df4: 801f strh r7, [r3, #0]
|
|
huart->TxXferCount = Size;
|
|
8004df6: 3302 adds r3, #2
|
|
8004df8: 9303 str r3, [sp, #12]
|
|
8004dfa: 801f strh r7, [r3, #0]
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8004dfc: 2380 movs r3, #128 @ 0x80
|
|
8004dfe: 68a2 ldr r2, [r4, #8]
|
|
tickstart = HAL_GetTick();
|
|
8004e00: 9004 str r0, [sp, #16]
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
8004e02: 015b lsls r3, r3, #5
|
|
8004e04: 429a cmp r2, r3
|
|
8004e06: d104 bne.n 8004e12 <HAL_UART_Transmit+0x68>
|
|
8004e08: 6923 ldr r3, [r4, #16]
|
|
8004e0a: 42b3 cmp r3, r6
|
|
8004e0c: d101 bne.n 8004e12 <HAL_UART_Transmit+0x68>
|
|
pdata16bits = (const uint16_t *) pData;
|
|
8004e0e: 002e movs r6, r5
|
|
pdata8bits = NULL;
|
|
8004e10: 001d movs r5, r3
|
|
while (huart->TxXferCount > 0U)
|
|
8004e12: 0023 movs r3, r4
|
|
8004e14: 3356 adds r3, #86 @ 0x56
|
|
8004e16: 881b ldrh r3, [r3, #0]
|
|
8004e18: b29a uxth r2, r3
|
|
8004e1a: 2b00 cmp r3, #0
|
|
8004e1c: d10d bne.n 8004e3a <HAL_UART_Transmit+0x90>
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
|
8004e1e: 9b05 ldr r3, [sp, #20]
|
|
8004e20: 0020 movs r0, r4
|
|
8004e22: 9300 str r3, [sp, #0]
|
|
8004e24: 2140 movs r1, #64 @ 0x40
|
|
8004e26: 9b04 ldr r3, [sp, #16]
|
|
8004e28: f7ff ff76 bl 8004d18 <UART_WaitOnFlagUntilTimeout>
|
|
8004e2c: 2320 movs r3, #32
|
|
8004e2e: 3488 adds r4, #136 @ 0x88
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004e30: 6023 str r3, [r4, #0]
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
|
|
8004e32: 2800 cmp r0, #0
|
|
8004e34: d10e bne.n 8004e54 <HAL_UART_Transmit+0xaa>
|
|
}
|
|
8004e36: b007 add sp, #28
|
|
8004e38: bdf0 pop {r4, r5, r6, r7, pc}
|
|
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
|
|
8004e3a: 9b05 ldr r3, [sp, #20]
|
|
8004e3c: 2200 movs r2, #0
|
|
8004e3e: 9300 str r3, [sp, #0]
|
|
8004e40: 2180 movs r1, #128 @ 0x80
|
|
8004e42: 0020 movs r0, r4
|
|
8004e44: 9b04 ldr r3, [sp, #16]
|
|
8004e46: f7ff ff67 bl 8004d18 <UART_WaitOnFlagUntilTimeout>
|
|
8004e4a: 2800 cmp r0, #0
|
|
8004e4c: d004 beq.n 8004e58 <HAL_UART_Transmit+0xae>
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004e4e: 2320 movs r3, #32
|
|
8004e50: 3488 adds r4, #136 @ 0x88
|
|
8004e52: 6023 str r3, [r4, #0]
|
|
return HAL_TIMEOUT;
|
|
8004e54: 2003 movs r0, #3
|
|
8004e56: e7ee b.n 8004e36 <HAL_UART_Transmit+0x8c>
|
|
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
8004e58: 6822 ldr r2, [r4, #0]
|
|
if (pdata8bits == NULL)
|
|
8004e5a: 2d00 cmp r5, #0
|
|
8004e5c: d10b bne.n 8004e76 <HAL_UART_Transmit+0xcc>
|
|
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
8004e5e: 8833 ldrh r3, [r6, #0]
|
|
pdata16bits++;
|
|
8004e60: 3602 adds r6, #2
|
|
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
|
|
8004e62: 05db lsls r3, r3, #23
|
|
8004e64: 0ddb lsrs r3, r3, #23
|
|
8004e66: 6293 str r3, [r2, #40] @ 0x28
|
|
huart->TxXferCount--;
|
|
8004e68: 9b03 ldr r3, [sp, #12]
|
|
8004e6a: 9a03 ldr r2, [sp, #12]
|
|
8004e6c: 881b ldrh r3, [r3, #0]
|
|
8004e6e: 3b01 subs r3, #1
|
|
8004e70: b29b uxth r3, r3
|
|
8004e72: 8013 strh r3, [r2, #0]
|
|
8004e74: e7cd b.n 8004e12 <HAL_UART_Transmit+0x68>
|
|
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
|
|
8004e76: 782b ldrb r3, [r5, #0]
|
|
pdata8bits++;
|
|
8004e78: 3501 adds r5, #1
|
|
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
|
|
8004e7a: 6293 str r3, [r2, #40] @ 0x28
|
|
pdata8bits++;
|
|
8004e7c: e7f4 b.n 8004e68 <HAL_UART_Transmit+0xbe>
|
|
...
|
|
|
|
08004e80 <UART_CheckIdleState>:
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004e80: 0003 movs r3, r0
|
|
{
|
|
8004e82: b573 push {r0, r1, r4, r5, r6, lr}
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004e84: 2600 movs r6, #0
|
|
{
|
|
8004e86: 0004 movs r4, r0
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004e88: 3390 adds r3, #144 @ 0x90
|
|
8004e8a: 601e str r6, [r3, #0]
|
|
tickstart = HAL_GetTick();
|
|
8004e8c: f7fd fd40 bl 8002910 <HAL_GetTick>
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
8004e90: 6823 ldr r3, [r4, #0]
|
|
tickstart = HAL_GetTick();
|
|
8004e92: 0005 movs r5, r0
|
|
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
|
|
8004e94: 681b ldr r3, [r3, #0]
|
|
8004e96: 071b lsls r3, r3, #28
|
|
8004e98: d51f bpl.n 8004eda <UART_CheckIdleState+0x5a>
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8004e9a: 2180 movs r1, #128 @ 0x80
|
|
8004e9c: 4b28 ldr r3, [pc, #160] @ (8004f40 <UART_CheckIdleState+0xc0>)
|
|
8004e9e: 0032 movs r2, r6
|
|
8004ea0: 9300 str r3, [sp, #0]
|
|
8004ea2: 0389 lsls r1, r1, #14
|
|
8004ea4: 0003 movs r3, r0
|
|
8004ea6: 0020 movs r0, r4
|
|
8004ea8: f7ff ff36 bl 8004d18 <UART_WaitOnFlagUntilTimeout>
|
|
8004eac: 42b0 cmp r0, r6
|
|
8004eae: d014 beq.n 8004eda <UART_CheckIdleState+0x5a>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004eb0: f3ef 8110 mrs r1, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004eb4: 2301 movs r3, #1
|
|
8004eb6: f383 8810 msr PRIMASK, r3
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
|
|
8004eba: 2080 movs r0, #128 @ 0x80
|
|
8004ebc: 6822 ldr r2, [r4, #0]
|
|
8004ebe: 6813 ldr r3, [r2, #0]
|
|
8004ec0: 4383 bics r3, r0
|
|
8004ec2: 6013 str r3, [r2, #0]
|
|
8004ec4: f381 8810 msr PRIMASK, r1
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004ec8: 0023 movs r3, r4
|
|
8004eca: 2220 movs r2, #32
|
|
8004ecc: 3388 adds r3, #136 @ 0x88
|
|
8004ece: 601a str r2, [r3, #0]
|
|
return HAL_TIMEOUT;
|
|
8004ed0: 2003 movs r0, #3
|
|
__HAL_UNLOCK(huart);
|
|
8004ed2: 2300 movs r3, #0
|
|
8004ed4: 3484 adds r4, #132 @ 0x84
|
|
8004ed6: 7023 strb r3, [r4, #0]
|
|
}
|
|
8004ed8: bd76 pop {r1, r2, r4, r5, r6, pc}
|
|
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
|
|
8004eda: 0026 movs r6, r4
|
|
8004edc: 6823 ldr r3, [r4, #0]
|
|
8004ede: 368c adds r6, #140 @ 0x8c
|
|
8004ee0: 681b ldr r3, [r3, #0]
|
|
8004ee2: 075b lsls r3, r3, #29
|
|
8004ee4: d523 bpl.n 8004f2e <UART_CheckIdleState+0xae>
|
|
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
|
|
8004ee6: 2180 movs r1, #128 @ 0x80
|
|
8004ee8: 4b15 ldr r3, [pc, #84] @ (8004f40 <UART_CheckIdleState+0xc0>)
|
|
8004eea: 2200 movs r2, #0
|
|
8004eec: 9300 str r3, [sp, #0]
|
|
8004eee: 0020 movs r0, r4
|
|
8004ef0: 002b movs r3, r5
|
|
8004ef2: 03c9 lsls r1, r1, #15
|
|
8004ef4: f7ff ff10 bl 8004d18 <UART_WaitOnFlagUntilTimeout>
|
|
8004ef8: 2800 cmp r0, #0
|
|
8004efa: d018 beq.n 8004f2e <UART_CheckIdleState+0xae>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004efc: f3ef 8010 mrs r0, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004f00: 2201 movs r2, #1
|
|
8004f02: f382 8810 msr PRIMASK, r2
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
|
|
8004f06: 6821 ldr r1, [r4, #0]
|
|
8004f08: 4d0e ldr r5, [pc, #56] @ (8004f44 <UART_CheckIdleState+0xc4>)
|
|
8004f0a: 680b ldr r3, [r1, #0]
|
|
8004f0c: 402b ands r3, r5
|
|
8004f0e: 600b str r3, [r1, #0]
|
|
8004f10: f380 8810 msr PRIMASK, r0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8004f14: f3ef 8010 mrs r0, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8004f18: f382 8810 msr PRIMASK, r2
|
|
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8004f1c: 6821 ldr r1, [r4, #0]
|
|
8004f1e: 688b ldr r3, [r1, #8]
|
|
8004f20: 4393 bics r3, r2
|
|
8004f22: 608b str r3, [r1, #8]
|
|
8004f24: f380 8810 msr PRIMASK, r0
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004f28: 2320 movs r3, #32
|
|
8004f2a: 6033 str r3, [r6, #0]
|
|
return HAL_TIMEOUT;
|
|
8004f2c: e7d0 b.n 8004ed0 <UART_CheckIdleState+0x50>
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004f2e: 0023 movs r3, r4
|
|
8004f30: 2220 movs r2, #32
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004f32: 2000 movs r0, #0
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8004f34: 3388 adds r3, #136 @ 0x88
|
|
8004f36: 601a str r2, [r3, #0]
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004f38: 6032 str r2, [r6, #0]
|
|
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
|
|
8004f3a: 66e0 str r0, [r4, #108] @ 0x6c
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8004f3c: 6720 str r0, [r4, #112] @ 0x70
|
|
return HAL_OK;
|
|
8004f3e: e7c8 b.n 8004ed2 <UART_CheckIdleState+0x52>
|
|
8004f40: 01ffffff .word 0x01ffffff
|
|
8004f44: fffffedf .word 0xfffffedf
|
|
|
|
08004f48 <HAL_UART_Init>:
|
|
{
|
|
8004f48: b570 push {r4, r5, r6, lr}
|
|
8004f4a: 1e04 subs r4, r0, #0
|
|
if (huart == NULL)
|
|
8004f4c: d101 bne.n 8004f52 <HAL_UART_Init+0xa>
|
|
return HAL_ERROR;
|
|
8004f4e: 2001 movs r0, #1
|
|
}
|
|
8004f50: bd70 pop {r4, r5, r6, pc}
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
8004f52: 0005 movs r5, r0
|
|
8004f54: 3588 adds r5, #136 @ 0x88
|
|
8004f56: 682b ldr r3, [r5, #0]
|
|
8004f58: 2b00 cmp r3, #0
|
|
8004f5a: d104 bne.n 8004f66 <HAL_UART_Init+0x1e>
|
|
huart->Lock = HAL_UNLOCKED;
|
|
8004f5c: 0002 movs r2, r0
|
|
8004f5e: 3284 adds r2, #132 @ 0x84
|
|
8004f60: 7013 strb r3, [r2, #0]
|
|
HAL_UART_MspInit(huart);
|
|
8004f62: f7fd fb7b bl 800265c <HAL_UART_MspInit>
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8004f66: 2324 movs r3, #36 @ 0x24
|
|
__HAL_UART_DISABLE(huart);
|
|
8004f68: 2101 movs r1, #1
|
|
8004f6a: 6822 ldr r2, [r4, #0]
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8004f6c: 602b str r3, [r5, #0]
|
|
__HAL_UART_DISABLE(huart);
|
|
8004f6e: 6813 ldr r3, [r2, #0]
|
|
8004f70: 438b bics r3, r1
|
|
8004f72: 6013 str r3, [r2, #0]
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
8004f74: 6aa3 ldr r3, [r4, #40] @ 0x28
|
|
8004f76: 2b00 cmp r3, #0
|
|
8004f78: d002 beq.n 8004f80 <HAL_UART_Init+0x38>
|
|
UART_AdvFeatureConfig(huart);
|
|
8004f7a: 0020 movs r0, r4
|
|
8004f7c: f7ff fe64 bl 8004c48 <UART_AdvFeatureConfig>
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
8004f80: 0020 movs r0, r4
|
|
8004f82: f7ff fd9f bl 8004ac4 <UART_SetConfig>
|
|
8004f86: 2801 cmp r0, #1
|
|
8004f88: d0e1 beq.n 8004f4e <HAL_UART_Init+0x6>
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8004f8a: 6823 ldr r3, [r4, #0]
|
|
8004f8c: 4907 ldr r1, [pc, #28] @ (8004fac <HAL_UART_Init+0x64>)
|
|
8004f8e: 685a ldr r2, [r3, #4]
|
|
return (UART_CheckIdleState(huart));
|
|
8004f90: 0020 movs r0, r4
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8004f92: 400a ands r2, r1
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8004f94: 212a movs r1, #42 @ 0x2a
|
|
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
|
|
8004f96: 605a str r2, [r3, #4]
|
|
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
|
|
8004f98: 689a ldr r2, [r3, #8]
|
|
8004f9a: 438a bics r2, r1
|
|
8004f9c: 609a str r2, [r3, #8]
|
|
__HAL_UART_ENABLE(huart);
|
|
8004f9e: 2201 movs r2, #1
|
|
8004fa0: 6819 ldr r1, [r3, #0]
|
|
8004fa2: 430a orrs r2, r1
|
|
8004fa4: 601a str r2, [r3, #0]
|
|
return (UART_CheckIdleState(huart));
|
|
8004fa6: f7ff ff6b bl 8004e80 <UART_CheckIdleState>
|
|
8004faa: e7d1 b.n 8004f50 <HAL_UART_Init+0x8>
|
|
8004fac: ffffb7ff .word 0xffffb7ff
|
|
|
|
08004fb0 <UART_Start_Receive_DMA>:
|
|
{
|
|
8004fb0: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
8004fb2: 0013 movs r3, r2
|
|
huart->RxXferSize = Size;
|
|
8004fb4: 0002 movs r2, r0
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004fb6: 0006 movs r6, r0
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
8004fb8: 0005 movs r5, r0
|
|
huart->RxXferSize = Size;
|
|
8004fba: 325c adds r2, #92 @ 0x5c
|
|
huart->pRxBuffPtr = pData;
|
|
8004fbc: 6581 str r1, [r0, #88] @ 0x58
|
|
{
|
|
8004fbe: 000f movs r7, r1
|
|
huart->RxXferSize = Size;
|
|
8004fc0: 8013 strh r3, [r2, #0]
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
8004fc2: 2122 movs r1, #34 @ 0x22
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004fc4: 2200 movs r2, #0
|
|
8004fc6: 3690 adds r6, #144 @ 0x90
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
8004fc8: 358c adds r5, #140 @ 0x8c
|
|
huart->ErrorCode = HAL_UART_ERROR_NONE;
|
|
8004fca: 6032 str r2, [r6, #0]
|
|
huart->RxState = HAL_UART_STATE_BUSY_RX;
|
|
8004fcc: 6029 str r1, [r5, #0]
|
|
if (huart->hdmarx != NULL)
|
|
8004fce: 1d01 adds r1, r0, #4
|
|
{
|
|
8004fd0: 0004 movs r4, r0
|
|
if (huart->hdmarx != NULL)
|
|
8004fd2: 6fc8 ldr r0, [r1, #124] @ 0x7c
|
|
8004fd4: 4290 cmp r0, r2
|
|
8004fd6: d013 beq.n 8005000 <UART_Start_Receive_DMA+0x50>
|
|
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
|
|
8004fd8: 491d ldr r1, [pc, #116] @ (8005050 <UART_Start_Receive_DMA+0xa0>)
|
|
huart->hdmarx->XferAbortCallback = NULL;
|
|
8004fda: 6382 str r2, [r0, #56] @ 0x38
|
|
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
|
|
8004fdc: 62c1 str r1, [r0, #44] @ 0x2c
|
|
huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
|
|
8004fde: 491d ldr r1, [pc, #116] @ (8005054 <UART_Start_Receive_DMA+0xa4>)
|
|
if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
|
|
8004fe0: 003a movs r2, r7
|
|
huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
|
|
8004fe2: 6301 str r1, [r0, #48] @ 0x30
|
|
huart->hdmarx->XferErrorCallback = UART_DMAError;
|
|
8004fe4: 491c ldr r1, [pc, #112] @ (8005058 <UART_Start_Receive_DMA+0xa8>)
|
|
8004fe6: 6341 str r1, [r0, #52] @ 0x34
|
|
if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
|
|
8004fe8: 6821 ldr r1, [r4, #0]
|
|
8004fea: 3124 adds r1, #36 @ 0x24
|
|
8004fec: f7fd ffd6 bl 8002f9c <HAL_DMA_Start_IT>
|
|
8004ff0: 2800 cmp r0, #0
|
|
8004ff2: d005 beq.n 8005000 <UART_Start_Receive_DMA+0x50>
|
|
huart->ErrorCode = HAL_UART_ERROR_DMA;
|
|
8004ff4: 2310 movs r3, #16
|
|
return HAL_ERROR;
|
|
8004ff6: 2001 movs r0, #1
|
|
huart->ErrorCode = HAL_UART_ERROR_DMA;
|
|
8004ff8: 6033 str r3, [r6, #0]
|
|
huart->RxState = HAL_UART_STATE_READY;
|
|
8004ffa: 18db adds r3, r3, r3
|
|
8004ffc: 602b str r3, [r5, #0]
|
|
}
|
|
8004ffe: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
if (huart->Init.Parity != UART_PARITY_NONE)
|
|
8005000: 6923 ldr r3, [r4, #16]
|
|
8005002: 2b00 cmp r3, #0
|
|
8005004: d00b beq.n 800501e <UART_Start_Receive_DMA+0x6e>
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8005006: f3ef 8110 mrs r1, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
800500a: 2301 movs r3, #1
|
|
800500c: f383 8810 msr PRIMASK, r3
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
|
|
8005010: 6822 ldr r2, [r4, #0]
|
|
8005012: 33ff adds r3, #255 @ 0xff
|
|
8005014: 6810 ldr r0, [r2, #0]
|
|
8005016: 4303 orrs r3, r0
|
|
8005018: 6013 str r3, [r2, #0]
|
|
800501a: f381 8810 msr PRIMASK, r1
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
800501e: f3ef 8010 mrs r0, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8005022: 2301 movs r3, #1
|
|
8005024: f383 8810 msr PRIMASK, r3
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
|
|
8005028: 6821 ldr r1, [r4, #0]
|
|
800502a: 688a ldr r2, [r1, #8]
|
|
800502c: 431a orrs r2, r3
|
|
800502e: 608a str r2, [r1, #8]
|
|
8005030: f380 8810 msr PRIMASK, r0
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
8005034: f3ef 8110 mrs r1, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8005038: f383 8810 msr PRIMASK, r3
|
|
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
|
|
800503c: 6822 ldr r2, [r4, #0]
|
|
800503e: 333f adds r3, #63 @ 0x3f
|
|
8005040: 6890 ldr r0, [r2, #8]
|
|
8005042: 4303 orrs r3, r0
|
|
8005044: 6093 str r3, [r2, #8]
|
|
8005046: f381 8810 msr PRIMASK, r1
|
|
return HAL_OK;
|
|
800504a: 2000 movs r0, #0
|
|
800504c: e7d7 b.n 8004ffe <UART_Start_Receive_DMA+0x4e>
|
|
800504e: 46c0 nop @ (mov r8, r8)
|
|
8005050: 08004a0d .word 0x08004a0d
|
|
8005054: 080049d1 .word 0x080049d1
|
|
8005058: 08004627 .word 0x08004627
|
|
|
|
0800505c <UARTEx_SetNbDataToProcess>:
|
|
* the UART configuration registers.
|
|
* @param huart UART handle.
|
|
* @retval None
|
|
*/
|
|
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
|
|
{
|
|
800505c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
800505e: 0007 movs r7, r0
|
|
uint8_t rx_fifo_threshold;
|
|
uint8_t tx_fifo_threshold;
|
|
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
|
|
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
|
|
|
|
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
|
|
8005060: 6e43 ldr r3, [r0, #100] @ 0x64
|
|
{
|
|
8005062: 0004 movs r4, r0
|
|
8005064: 376a adds r7, #106 @ 0x6a
|
|
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
|
|
8005066: 2b00 cmp r3, #0
|
|
8005068: d104 bne.n 8005074 <UARTEx_SetNbDataToProcess+0x18>
|
|
{
|
|
huart->NbTxDataToProcess = 1U;
|
|
800506a: 2001 movs r0, #1
|
|
800506c: 8038 strh r0, [r7, #0]
|
|
huart->NbRxDataToProcess = 1U;
|
|
800506e: 3468 adds r4, #104 @ 0x68
|
|
8005070: 8020 strh r0, [r4, #0]
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
(uint16_t)denominator[tx_fifo_threshold];
|
|
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
|
(uint16_t)denominator[rx_fifo_threshold];
|
|
}
|
|
}
|
|
8005072: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
|
|
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
|
|
8005074: 6803 ldr r3, [r0, #0]
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
8005076: 4e0b ldr r6, [pc, #44] @ (80050a4 <UARTEx_SetNbDataToProcess+0x48>)
|
|
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
|
|
8005078: 689a ldr r2, [r3, #8]
|
|
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
|
|
800507a: 689b ldr r3, [r3, #8]
|
|
(uint16_t)denominator[tx_fifo_threshold];
|
|
800507c: 4d0a ldr r5, [pc, #40] @ (80050a8 <UARTEx_SetNbDataToProcess+0x4c>)
|
|
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
|
|
800507e: 0f5b lsrs r3, r3, #29
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
8005080: 5cf0 ldrb r0, [r6, r3]
|
|
(uint16_t)denominator[tx_fifo_threshold];
|
|
8005082: 5ce9 ldrb r1, [r5, r3]
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
8005084: 00c0 lsls r0, r0, #3
|
|
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
|
|
8005086: 9201 str r2, [sp, #4]
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
8005088: f7fb f8dc bl 8000244 <__divsi3>
|
|
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
|
|
800508c: 9b01 ldr r3, [sp, #4]
|
|
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
|
|
800508e: 8038 strh r0, [r7, #0]
|
|
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
|
|
8005090: 011b lsls r3, r3, #4
|
|
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
|
8005092: 0f5b lsrs r3, r3, #29
|
|
8005094: 5cf0 ldrb r0, [r6, r3]
|
|
(uint16_t)denominator[rx_fifo_threshold];
|
|
8005096: 5ce9 ldrb r1, [r5, r3]
|
|
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
|
|
8005098: 00c0 lsls r0, r0, #3
|
|
800509a: f7fb f8d3 bl 8000244 <__divsi3>
|
|
800509e: b280 uxth r0, r0
|
|
}
|
|
80050a0: e7e5 b.n 800506e <UARTEx_SetNbDataToProcess+0x12>
|
|
80050a2: 46c0 nop @ (mov r8, r8)
|
|
80050a4: 080053a4 .word 0x080053a4
|
|
80050a8: 0800539c .word 0x0800539c
|
|
|
|
080050ac <HAL_RS485Ex_Init>:
|
|
{
|
|
80050ac: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
|
|
80050ae: 0004 movs r4, r0
|
|
80050b0: 000e movs r6, r1
|
|
80050b2: 001d movs r5, r3
|
|
80050b4: 9201 str r2, [sp, #4]
|
|
if (huart == NULL)
|
|
80050b6: 2800 cmp r0, #0
|
|
80050b8: d101 bne.n 80050be <HAL_RS485Ex_Init+0x12>
|
|
return HAL_ERROR;
|
|
80050ba: 2001 movs r0, #1
|
|
}
|
|
80050bc: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
|
|
if (huart->gState == HAL_UART_STATE_RESET)
|
|
80050be: 0007 movs r7, r0
|
|
80050c0: 3788 adds r7, #136 @ 0x88
|
|
80050c2: 683b ldr r3, [r7, #0]
|
|
80050c4: 2b00 cmp r3, #0
|
|
80050c6: d104 bne.n 80050d2 <HAL_RS485Ex_Init+0x26>
|
|
huart->Lock = HAL_UNLOCKED;
|
|
80050c8: 0002 movs r2, r0
|
|
80050ca: 3284 adds r2, #132 @ 0x84
|
|
80050cc: 7013 strb r3, [r2, #0]
|
|
HAL_UART_MspInit(huart);
|
|
80050ce: f7fd fac5 bl 800265c <HAL_UART_MspInit>
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
80050d2: 2324 movs r3, #36 @ 0x24
|
|
__HAL_UART_DISABLE(huart);
|
|
80050d4: 2101 movs r1, #1
|
|
80050d6: 6822 ldr r2, [r4, #0]
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
80050d8: 603b str r3, [r7, #0]
|
|
__HAL_UART_DISABLE(huart);
|
|
80050da: 6813 ldr r3, [r2, #0]
|
|
80050dc: 438b bics r3, r1
|
|
80050de: 6013 str r3, [r2, #0]
|
|
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
|
80050e0: 6aa3 ldr r3, [r4, #40] @ 0x28
|
|
80050e2: 2b00 cmp r3, #0
|
|
80050e4: d002 beq.n 80050ec <HAL_RS485Ex_Init+0x40>
|
|
UART_AdvFeatureConfig(huart);
|
|
80050e6: 0020 movs r0, r4
|
|
80050e8: f7ff fdae bl 8004c48 <UART_AdvFeatureConfig>
|
|
if (UART_SetConfig(huart) == HAL_ERROR)
|
|
80050ec: 0020 movs r0, r4
|
|
80050ee: f7ff fce9 bl 8004ac4 <UART_SetConfig>
|
|
80050f2: 2801 cmp r0, #1
|
|
80050f4: d0e1 beq.n 80050ba <HAL_RS485Ex_Init+0xe>
|
|
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
|
|
80050f6: 2280 movs r2, #128 @ 0x80
|
|
80050f8: 6823 ldr r3, [r4, #0]
|
|
80050fa: 01d2 lsls r2, r2, #7
|
|
80050fc: 6899 ldr r1, [r3, #8]
|
|
temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
|
|
80050fe: 042d lsls r5, r5, #16
|
|
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
|
|
8005100: 430a orrs r2, r1
|
|
8005102: 609a str r2, [r3, #8]
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
|
|
8005104: 689a ldr r2, [r3, #8]
|
|
8005106: 490a ldr r1, [pc, #40] @ (8005130 <HAL_RS485Ex_Init+0x84>)
|
|
return (UART_CheckIdleState(huart));
|
|
8005108: 0020 movs r0, r4
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
|
|
800510a: 400a ands r2, r1
|
|
800510c: 4332 orrs r2, r6
|
|
800510e: 609a str r2, [r3, #8]
|
|
temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
|
|
8005110: 9a01 ldr r2, [sp, #4]
|
|
8005112: 0551 lsls r1, r2, #21
|
|
temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
|
|
8005114: 430d orrs r5, r1
|
|
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
|
|
8005116: 681a ldr r2, [r3, #0]
|
|
8005118: 4906 ldr r1, [pc, #24] @ (8005134 <HAL_RS485Ex_Init+0x88>)
|
|
800511a: 400a ands r2, r1
|
|
800511c: 4315 orrs r5, r2
|
|
__HAL_UART_ENABLE(huart);
|
|
800511e: 2201 movs r2, #1
|
|
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
|
|
8005120: 601d str r5, [r3, #0]
|
|
__HAL_UART_ENABLE(huart);
|
|
8005122: 6819 ldr r1, [r3, #0]
|
|
8005124: 430a orrs r2, r1
|
|
8005126: 601a str r2, [r3, #0]
|
|
return (UART_CheckIdleState(huart));
|
|
8005128: f7ff feaa bl 8004e80 <UART_CheckIdleState>
|
|
800512c: e7c6 b.n 80050bc <HAL_RS485Ex_Init+0x10>
|
|
800512e: 46c0 nop @ (mov r8, r8)
|
|
8005130: ffff7fff .word 0xffff7fff
|
|
8005134: fc00ffff .word 0xfc00ffff
|
|
|
|
08005138 <HAL_UARTEx_WakeupCallback>:
|
|
}
|
|
8005138: 4770 bx lr
|
|
|
|
0800513a <HAL_UARTEx_RxFifoFullCallback>:
|
|
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
|
|
800513a: 4770 bx lr
|
|
|
|
0800513c <HAL_UARTEx_TxFifoEmptyCallback>:
|
|
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
|
|
800513c: 4770 bx lr
|
|
...
|
|
|
|
08005140 <HAL_UARTEx_DisableFifoMode>:
|
|
{
|
|
8005140: b570 push {r4, r5, r6, lr}
|
|
__HAL_LOCK(huart);
|
|
8005142: 0004 movs r4, r0
|
|
8005144: 3484 adds r4, #132 @ 0x84
|
|
8005146: 7822 ldrb r2, [r4, #0]
|
|
{
|
|
8005148: 0003 movs r3, r0
|
|
__HAL_LOCK(huart);
|
|
800514a: 2002 movs r0, #2
|
|
800514c: 2a01 cmp r2, #1
|
|
800514e: d011 beq.n 8005174 <HAL_UARTEx_DisableFifoMode+0x34>
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8005150: 001d movs r5, r3
|
|
8005152: 2224 movs r2, #36 @ 0x24
|
|
__HAL_UART_DISABLE(huart);
|
|
8005154: 2601 movs r6, #1
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8005156: 3588 adds r5, #136 @ 0x88
|
|
8005158: 602a str r2, [r5, #0]
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
800515a: 681a ldr r2, [r3, #0]
|
|
800515c: 6811 ldr r1, [r2, #0]
|
|
__HAL_UART_DISABLE(huart);
|
|
800515e: 6810 ldr r0, [r2, #0]
|
|
8005160: 43b0 bics r0, r6
|
|
8005162: 6010 str r0, [r2, #0]
|
|
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
|
|
8005164: 4804 ldr r0, [pc, #16] @ (8005178 <HAL_UARTEx_DisableFifoMode+0x38>)
|
|
8005166: 4001 ands r1, r0
|
|
huart->FifoMode = UART_FIFOMODE_DISABLE;
|
|
8005168: 2000 movs r0, #0
|
|
800516a: 6658 str r0, [r3, #100] @ 0x64
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
800516c: 2320 movs r3, #32
|
|
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
|
800516e: 6011 str r1, [r2, #0]
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
8005170: 602b str r3, [r5, #0]
|
|
__HAL_UNLOCK(huart);
|
|
8005172: 7020 strb r0, [r4, #0]
|
|
}
|
|
8005174: bd70 pop {r4, r5, r6, pc}
|
|
8005176: 46c0 nop @ (mov r8, r8)
|
|
8005178: dfffffff .word 0xdfffffff
|
|
|
|
0800517c <HAL_UARTEx_SetTxFifoThreshold>:
|
|
{
|
|
800517c: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
__HAL_LOCK(huart);
|
|
800517e: 0005 movs r5, r0
|
|
8005180: 3584 adds r5, #132 @ 0x84
|
|
{
|
|
8005182: 000b movs r3, r1
|
|
__HAL_LOCK(huart);
|
|
8005184: 7829 ldrb r1, [r5, #0]
|
|
8005186: 2202 movs r2, #2
|
|
8005188: 2901 cmp r1, #1
|
|
800518a: d015 beq.n 80051b8 <HAL_UARTEx_SetTxFifoThreshold+0x3c>
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
800518c: 0006 movs r6, r0
|
|
__HAL_UART_DISABLE(huart);
|
|
800518e: 2101 movs r1, #1
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
8005190: 6804 ldr r4, [r0, #0]
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
8005192: 3688 adds r6, #136 @ 0x88
|
|
8005194: 3222 adds r2, #34 @ 0x22
|
|
8005196: 6032 str r2, [r6, #0]
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
8005198: 6827 ldr r7, [r4, #0]
|
|
__HAL_UART_DISABLE(huart);
|
|
800519a: 6822 ldr r2, [r4, #0]
|
|
800519c: 438a bics r2, r1
|
|
800519e: 6022 str r2, [r4, #0]
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
|
|
80051a0: 68a1 ldr r1, [r4, #8]
|
|
80051a2: 00c9 lsls r1, r1, #3
|
|
80051a4: 08c9 lsrs r1, r1, #3
|
|
80051a6: 4319 orrs r1, r3
|
|
80051a8: 60a1 str r1, [r4, #8]
|
|
UARTEx_SetNbDataToProcess(huart);
|
|
80051aa: f7ff ff57 bl 800505c <UARTEx_SetNbDataToProcess>
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80051ae: 2320 movs r3, #32
|
|
__HAL_UNLOCK(huart);
|
|
80051b0: 2200 movs r2, #0
|
|
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
|
80051b2: 6027 str r7, [r4, #0]
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80051b4: 6033 str r3, [r6, #0]
|
|
__HAL_UNLOCK(huart);
|
|
80051b6: 702a strb r2, [r5, #0]
|
|
}
|
|
80051b8: 0010 movs r0, r2
|
|
80051ba: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
|
|
080051bc <HAL_UARTEx_SetRxFifoThreshold>:
|
|
{
|
|
80051bc: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
__HAL_LOCK(huart);
|
|
80051be: 0005 movs r5, r0
|
|
80051c0: 3584 adds r5, #132 @ 0x84
|
|
{
|
|
80051c2: 000a movs r2, r1
|
|
__HAL_LOCK(huart);
|
|
80051c4: 7829 ldrb r1, [r5, #0]
|
|
80051c6: 2302 movs r3, #2
|
|
80051c8: 2901 cmp r1, #1
|
|
80051ca: d015 beq.n 80051f8 <HAL_UARTEx_SetRxFifoThreshold+0x3c>
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
80051cc: 0006 movs r6, r0
|
|
__HAL_UART_DISABLE(huart);
|
|
80051ce: 2101 movs r1, #1
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
80051d0: 6804 ldr r4, [r0, #0]
|
|
huart->gState = HAL_UART_STATE_BUSY;
|
|
80051d2: 3688 adds r6, #136 @ 0x88
|
|
80051d4: 3322 adds r3, #34 @ 0x22
|
|
80051d6: 6033 str r3, [r6, #0]
|
|
tmpcr1 = READ_REG(huart->Instance->CR1);
|
|
80051d8: 6827 ldr r7, [r4, #0]
|
|
__HAL_UART_DISABLE(huart);
|
|
80051da: 6823 ldr r3, [r4, #0]
|
|
80051dc: 438b bics r3, r1
|
|
80051de: 6023 str r3, [r4, #0]
|
|
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
|
|
80051e0: 68a1 ldr r1, [r4, #8]
|
|
80051e2: 4b06 ldr r3, [pc, #24] @ (80051fc <HAL_UARTEx_SetRxFifoThreshold+0x40>)
|
|
80051e4: 4019 ands r1, r3
|
|
80051e6: 4311 orrs r1, r2
|
|
80051e8: 60a1 str r1, [r4, #8]
|
|
UARTEx_SetNbDataToProcess(huart);
|
|
80051ea: f7ff ff37 bl 800505c <UARTEx_SetNbDataToProcess>
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80051ee: 2320 movs r3, #32
|
|
WRITE_REG(huart->Instance->CR1, tmpcr1);
|
|
80051f0: 6027 str r7, [r4, #0]
|
|
huart->gState = HAL_UART_STATE_READY;
|
|
80051f2: 6033 str r3, [r6, #0]
|
|
__HAL_UNLOCK(huart);
|
|
80051f4: 2300 movs r3, #0
|
|
80051f6: 702b strb r3, [r5, #0]
|
|
}
|
|
80051f8: 0018 movs r0, r3
|
|
80051fa: bdf8 pop {r3, r4, r5, r6, r7, pc}
|
|
80051fc: f1ffffff .word 0xf1ffffff
|
|
|
|
08005200 <HAL_UARTEx_ReceiveToIdle_DMA>:
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
8005200: 0003 movs r3, r0
|
|
8005202: 338c adds r3, #140 @ 0x8c
|
|
8005204: 681b ldr r3, [r3, #0]
|
|
{
|
|
8005206: b570 push {r4, r5, r6, lr}
|
|
8005208: 0004 movs r4, r0
|
|
return HAL_BUSY;
|
|
800520a: 2002 movs r0, #2
|
|
if (huart->RxState == HAL_UART_STATE_READY)
|
|
800520c: 2b20 cmp r3, #32
|
|
800520e: d102 bne.n 8005216 <HAL_UARTEx_ReceiveToIdle_DMA+0x16>
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8005210: 2900 cmp r1, #0
|
|
8005212: d101 bne.n 8005218 <HAL_UARTEx_ReceiveToIdle_DMA+0x18>
|
|
return HAL_ERROR;
|
|
8005214: 2001 movs r0, #1
|
|
}
|
|
8005216: bd70 pop {r4, r5, r6, pc}
|
|
if ((pData == NULL) || (Size == 0U))
|
|
8005218: 2a00 cmp r2, #0
|
|
800521a: d0fb beq.n 8005214 <HAL_UARTEx_ReceiveToIdle_DMA+0x14>
|
|
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
|
|
800521c: 2080 movs r0, #128 @ 0x80
|
|
800521e: 68a5 ldr r5, [r4, #8]
|
|
8005220: 2301 movs r3, #1
|
|
8005222: 0140 lsls r0, r0, #5
|
|
8005224: 4285 cmp r5, r0
|
|
8005226: d104 bne.n 8005232 <HAL_UARTEx_ReceiveToIdle_DMA+0x32>
|
|
8005228: 6920 ldr r0, [r4, #16]
|
|
800522a: 2800 cmp r0, #0
|
|
800522c: d101 bne.n 8005232 <HAL_UARTEx_ReceiveToIdle_DMA+0x32>
|
|
if ((((uint32_t)pData) & 1U) != 0U)
|
|
800522e: 4219 tst r1, r3
|
|
8005230: d1f0 bne.n 8005214 <HAL_UARTEx_ReceiveToIdle_DMA+0x14>
|
|
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
|
8005232: 66e3 str r3, [r4, #108] @ 0x6c
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8005234: 2300 movs r3, #0
|
|
status = UART_Start_Receive_DMA(huart, pData, Size);
|
|
8005236: 0020 movs r0, r4
|
|
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
|
8005238: 6723 str r3, [r4, #112] @ 0x70
|
|
status = UART_Start_Receive_DMA(huart, pData, Size);
|
|
800523a: f7ff feb9 bl 8004fb0 <UART_Start_Receive_DMA>
|
|
if (status == HAL_OK)
|
|
800523e: 2800 cmp r0, #0
|
|
8005240: d1e9 bne.n 8005216 <HAL_UARTEx_ReceiveToIdle_DMA+0x16>
|
|
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
|
8005242: 6ee2 ldr r2, [r4, #108] @ 0x6c
|
|
8005244: 2a01 cmp r2, #1
|
|
8005246: d1e5 bne.n 8005214 <HAL_UARTEx_ReceiveToIdle_DMA+0x14>
|
|
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
|
8005248: 2310 movs r3, #16
|
|
800524a: 6821 ldr r1, [r4, #0]
|
|
800524c: 620b str r3, [r1, #32]
|
|
__ASM volatile ("MRS %0, primask" : "=r" (result) );
|
|
800524e: f3ef 8110 mrs r1, PRIMASK
|
|
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
|
|
8005252: f382 8810 msr PRIMASK, r2
|
|
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
|
8005256: 6822 ldr r2, [r4, #0]
|
|
8005258: 6814 ldr r4, [r2, #0]
|
|
800525a: 4323 orrs r3, r4
|
|
800525c: 6013 str r3, [r2, #0]
|
|
800525e: f381 8810 msr PRIMASK, r1
|
|
}
|
|
8005262: e7d8 b.n 8005216 <HAL_UARTEx_ReceiveToIdle_DMA+0x16>
|
|
|
|
08005264 <memcmp>:
|
|
8005264: b530 push {r4, r5, lr}
|
|
8005266: 2400 movs r4, #0
|
|
8005268: 3901 subs r1, #1
|
|
800526a: 42a2 cmp r2, r4
|
|
800526c: d101 bne.n 8005272 <memcmp+0xe>
|
|
800526e: 2000 movs r0, #0
|
|
8005270: e005 b.n 800527e <memcmp+0x1a>
|
|
8005272: 5d03 ldrb r3, [r0, r4]
|
|
8005274: 3401 adds r4, #1
|
|
8005276: 5d0d ldrb r5, [r1, r4]
|
|
8005278: 42ab cmp r3, r5
|
|
800527a: d0f6 beq.n 800526a <memcmp+0x6>
|
|
800527c: 1b58 subs r0, r3, r5
|
|
800527e: bd30 pop {r4, r5, pc}
|
|
|
|
08005280 <memset>:
|
|
8005280: 0003 movs r3, r0
|
|
8005282: 1882 adds r2, r0, r2
|
|
8005284: 4293 cmp r3, r2
|
|
8005286: d100 bne.n 800528a <memset+0xa>
|
|
8005288: 4770 bx lr
|
|
800528a: 7019 strb r1, [r3, #0]
|
|
800528c: 3301 adds r3, #1
|
|
800528e: e7f9 b.n 8005284 <memset+0x4>
|
|
|
|
08005290 <__libc_init_array>:
|
|
8005290: b570 push {r4, r5, r6, lr}
|
|
8005292: 2600 movs r6, #0
|
|
8005294: 4c0c ldr r4, [pc, #48] @ (80052c8 <__libc_init_array+0x38>)
|
|
8005296: 4d0d ldr r5, [pc, #52] @ (80052cc <__libc_init_array+0x3c>)
|
|
8005298: 1b64 subs r4, r4, r5
|
|
800529a: 10a4 asrs r4, r4, #2
|
|
800529c: 42a6 cmp r6, r4
|
|
800529e: d109 bne.n 80052b4 <__libc_init_array+0x24>
|
|
80052a0: 2600 movs r6, #0
|
|
80052a2: f000 f823 bl 80052ec <_init>
|
|
80052a6: 4c0a ldr r4, [pc, #40] @ (80052d0 <__libc_init_array+0x40>)
|
|
80052a8: 4d0a ldr r5, [pc, #40] @ (80052d4 <__libc_init_array+0x44>)
|
|
80052aa: 1b64 subs r4, r4, r5
|
|
80052ac: 10a4 asrs r4, r4, #2
|
|
80052ae: 42a6 cmp r6, r4
|
|
80052b0: d105 bne.n 80052be <__libc_init_array+0x2e>
|
|
80052b2: bd70 pop {r4, r5, r6, pc}
|
|
80052b4: 00b3 lsls r3, r6, #2
|
|
80052b6: 58eb ldr r3, [r5, r3]
|
|
80052b8: 4798 blx r3
|
|
80052ba: 3601 adds r6, #1
|
|
80052bc: e7ee b.n 800529c <__libc_init_array+0xc>
|
|
80052be: 00b3 lsls r3, r6, #2
|
|
80052c0: 58eb ldr r3, [r5, r3]
|
|
80052c2: 4798 blx r3
|
|
80052c4: 3601 adds r6, #1
|
|
80052c6: e7f2 b.n 80052ae <__libc_init_array+0x1e>
|
|
80052c8: 080053b4 .word 0x080053b4
|
|
80052cc: 080053b4 .word 0x080053b4
|
|
80052d0: 080053b8 .word 0x080053b8
|
|
80052d4: 080053b4 .word 0x080053b4
|
|
|
|
080052d8 <memcpy>:
|
|
80052d8: 2300 movs r3, #0
|
|
80052da: b510 push {r4, lr}
|
|
80052dc: 429a cmp r2, r3
|
|
80052de: d100 bne.n 80052e2 <memcpy+0xa>
|
|
80052e0: bd10 pop {r4, pc}
|
|
80052e2: 5ccc ldrb r4, [r1, r3]
|
|
80052e4: 54c4 strb r4, [r0, r3]
|
|
80052e6: 3301 adds r3, #1
|
|
80052e8: e7f8 b.n 80052dc <memcpy+0x4>
|
|
...
|
|
|
|
080052ec <_init>:
|
|
80052ec: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80052ee: 46c0 nop @ (mov r8, r8)
|
|
80052f0: bcf8 pop {r3, r4, r5, r6, r7}
|
|
80052f2: bc08 pop {r3}
|
|
80052f4: 469e mov lr, r3
|
|
80052f6: 4770 bx lr
|
|
|
|
080052f8 <_fini>:
|
|
80052f8: b5f8 push {r3, r4, r5, r6, r7, lr}
|
|
80052fa: 46c0 nop @ (mov r8, r8)
|
|
80052fc: bcf8 pop {r3, r4, r5, r6, r7}
|
|
80052fe: bc08 pop {r3}
|
|
8005300: 469e mov lr, r3
|
|
8005302: 4770 bx lr
|