B4L/feeder_mk2
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542a5ffd2c8c87c930c1a8a52eba8d5f6b398e77
feeder_mk2/code/Debug/feeder_mk2.list

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feeder_mk2.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000000c0 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 00005150 080000c0 080000c0 000010c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 000000a8 08005210 08005210 00006210 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 080052b8 080052b8 00007030 2**0
CONTENTS, READONLY
4 .ARM 00000008 080052b8 080052b8 000062b8 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 080052c0 080052c0 00007030 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 080052c0 080052c0 000062c0 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 080052c4 080052c4 000062c4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 00000030 20000000 080052c8 00007000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 00001334 20000030 080052f8 00007030 2**2
ALLOC
10 ._user_heap_stack 00000604 20001364 080052f8 00007364 2**0
ALLOC
11 .ARM.attributes 00000028 00000000 00000000 00007030 2**0
CONTENTS, READONLY
12 .debug_info 0001b022 00000000 00000000 00007058 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 00002ea9 00000000 00000000 0002207a 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_loclists 0000c0a2 00000000 00000000 00024f23 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_aranges 00000f48 00000000 00000000 00030fc8 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_rnglists 000013d0 00000000 00000000 00031f10 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_macro 00015b92 00000000 00000000 000332e0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_line 0001a310 00000000 00000000 00048e72 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .debug_str 0008ebf3 00000000 00000000 00063182 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
20 .comment 00000043 00000000 00000000 000f1d75 2**0
CONTENTS, READONLY
21 .debug_frame 00002bb0 00000000 00000000 000f1db8 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
22 .debug_line_str 0000004d 00000000 00000000 000f4968 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080000c0 <__do_global_dtors_aux>:
80000c0: b510 push {r4, lr}
80000c2: 4c06 ldr r4, [pc, #24] @ (80000dc <__do_global_dtors_aux+0x1c>)
80000c4: 7823 ldrb r3, [r4, #0]
80000c6: 2b00 cmp r3, #0
80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a>
80000ca: 4b05 ldr r3, [pc, #20] @ (80000e0 <__do_global_dtors_aux+0x20>)
80000cc: 2b00 cmp r3, #0
80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16>
80000d0: 4804 ldr r0, [pc, #16] @ (80000e4 <__do_global_dtors_aux+0x24>)
80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16>
80000d4: bf00 nop
80000d6: 2301 movs r3, #1
80000d8: 7023 strb r3, [r4, #0]
80000da: bd10 pop {r4, pc}
80000dc: 20000030 .word 0x20000030
80000e0: 00000000 .word 0x00000000
80000e4: 080051f8 .word 0x080051f8
080000e8 <frame_dummy>:
80000e8: 4b04 ldr r3, [pc, #16] @ (80000fc <frame_dummy+0x14>)
80000ea: b510 push {r4, lr}
80000ec: 2b00 cmp r3, #0
80000ee: d003 beq.n 80000f8 <frame_dummy+0x10>
80000f0: 4903 ldr r1, [pc, #12] @ (8000100 <frame_dummy+0x18>)
80000f2: 4804 ldr r0, [pc, #16] @ (8000104 <frame_dummy+0x1c>)
80000f4: e000 b.n 80000f8 <frame_dummy+0x10>
80000f6: bf00 nop
80000f8: bd10 pop {r4, pc}
80000fa: 46c0 nop @ (mov r8, r8)
80000fc: 00000000 .word 0x00000000
8000100: 20000034 .word 0x20000034
8000104: 080051f8 .word 0x080051f8
08000108 <__gnu_thumb1_case_uqi>:
8000108: b402 push {r1}
800010a: 4671 mov r1, lr
800010c: 0849 lsrs r1, r1, #1
800010e: 0049 lsls r1, r1, #1
8000110: 5c09 ldrb r1, [r1, r0]
8000112: 0049 lsls r1, r1, #1
8000114: 448e add lr, r1
8000116: bc02 pop {r1}
8000118: 4770 bx lr
800011a: 46c0 nop @ (mov r8, r8)
0800011c <__gnu_thumb1_case_uhi>:
800011c: b403 push {r0, r1}
800011e: 4671 mov r1, lr
8000120: 0849 lsrs r1, r1, #1
8000122: 0040 lsls r0, r0, #1
8000124: 0049 lsls r1, r1, #1
8000126: 5a09 ldrh r1, [r1, r0]
8000128: 0049 lsls r1, r1, #1
800012a: 448e add lr, r1
800012c: bc03 pop {r0, r1}
800012e: 4770 bx lr
08000130 <__udivsi3>:
8000130: 2200 movs r2, #0
8000132: 0843 lsrs r3, r0, #1
8000134: 428b cmp r3, r1
8000136: d374 bcc.n 8000222 <__udivsi3+0xf2>
8000138: 0903 lsrs r3, r0, #4
800013a: 428b cmp r3, r1
800013c: d35f bcc.n 80001fe <__udivsi3+0xce>
800013e: 0a03 lsrs r3, r0, #8
8000140: 428b cmp r3, r1
8000142: d344 bcc.n 80001ce <__udivsi3+0x9e>
8000144: 0b03 lsrs r3, r0, #12
8000146: 428b cmp r3, r1
8000148: d328 bcc.n 800019c <__udivsi3+0x6c>
800014a: 0c03 lsrs r3, r0, #16
800014c: 428b cmp r3, r1
800014e: d30d bcc.n 800016c <__udivsi3+0x3c>
8000150: 22ff movs r2, #255 @ 0xff
8000152: 0209 lsls r1, r1, #8
8000154: ba12 rev r2, r2
8000156: 0c03 lsrs r3, r0, #16
8000158: 428b cmp r3, r1
800015a: d302 bcc.n 8000162 <__udivsi3+0x32>
800015c: 1212 asrs r2, r2, #8
800015e: 0209 lsls r1, r1, #8
8000160: d065 beq.n 800022e <__udivsi3+0xfe>
8000162: 0b03 lsrs r3, r0, #12
8000164: 428b cmp r3, r1
8000166: d319 bcc.n 800019c <__udivsi3+0x6c>
8000168: e000 b.n 800016c <__udivsi3+0x3c>
800016a: 0a09 lsrs r1, r1, #8
800016c: 0bc3 lsrs r3, r0, #15
800016e: 428b cmp r3, r1
8000170: d301 bcc.n 8000176 <__udivsi3+0x46>
8000172: 03cb lsls r3, r1, #15
8000174: 1ac0 subs r0, r0, r3
8000176: 4152 adcs r2, r2
8000178: 0b83 lsrs r3, r0, #14
800017a: 428b cmp r3, r1
800017c: d301 bcc.n 8000182 <__udivsi3+0x52>
800017e: 038b lsls r3, r1, #14
8000180: 1ac0 subs r0, r0, r3
8000182: 4152 adcs r2, r2
8000184: 0b43 lsrs r3, r0, #13
8000186: 428b cmp r3, r1
8000188: d301 bcc.n 800018e <__udivsi3+0x5e>
800018a: 034b lsls r3, r1, #13
800018c: 1ac0 subs r0, r0, r3
800018e: 4152 adcs r2, r2
8000190: 0b03 lsrs r3, r0, #12
8000192: 428b cmp r3, r1
8000194: d301 bcc.n 800019a <__udivsi3+0x6a>
8000196: 030b lsls r3, r1, #12
8000198: 1ac0 subs r0, r0, r3
800019a: 4152 adcs r2, r2
800019c: 0ac3 lsrs r3, r0, #11
800019e: 428b cmp r3, r1
80001a0: d301 bcc.n 80001a6 <__udivsi3+0x76>
80001a2: 02cb lsls r3, r1, #11
80001a4: 1ac0 subs r0, r0, r3
80001a6: 4152 adcs r2, r2
80001a8: 0a83 lsrs r3, r0, #10
80001aa: 428b cmp r3, r1
80001ac: d301 bcc.n 80001b2 <__udivsi3+0x82>
80001ae: 028b lsls r3, r1, #10
80001b0: 1ac0 subs r0, r0, r3
80001b2: 4152 adcs r2, r2
80001b4: 0a43 lsrs r3, r0, #9
80001b6: 428b cmp r3, r1
80001b8: d301 bcc.n 80001be <__udivsi3+0x8e>
80001ba: 024b lsls r3, r1, #9
80001bc: 1ac0 subs r0, r0, r3
80001be: 4152 adcs r2, r2
80001c0: 0a03 lsrs r3, r0, #8
80001c2: 428b cmp r3, r1
80001c4: d301 bcc.n 80001ca <__udivsi3+0x9a>
80001c6: 020b lsls r3, r1, #8
80001c8: 1ac0 subs r0, r0, r3
80001ca: 4152 adcs r2, r2
80001cc: d2cd bcs.n 800016a <__udivsi3+0x3a>
80001ce: 09c3 lsrs r3, r0, #7
80001d0: 428b cmp r3, r1
80001d2: d301 bcc.n 80001d8 <__udivsi3+0xa8>
80001d4: 01cb lsls r3, r1, #7
80001d6: 1ac0 subs r0, r0, r3
80001d8: 4152 adcs r2, r2
80001da: 0983 lsrs r3, r0, #6
80001dc: 428b cmp r3, r1
80001de: d301 bcc.n 80001e4 <__udivsi3+0xb4>
80001e0: 018b lsls r3, r1, #6
80001e2: 1ac0 subs r0, r0, r3
80001e4: 4152 adcs r2, r2
80001e6: 0943 lsrs r3, r0, #5
80001e8: 428b cmp r3, r1
80001ea: d301 bcc.n 80001f0 <__udivsi3+0xc0>
80001ec: 014b lsls r3, r1, #5
80001ee: 1ac0 subs r0, r0, r3
80001f0: 4152 adcs r2, r2
80001f2: 0903 lsrs r3, r0, #4
80001f4: 428b cmp r3, r1
80001f6: d301 bcc.n 80001fc <__udivsi3+0xcc>
80001f8: 010b lsls r3, r1, #4
80001fa: 1ac0 subs r0, r0, r3
80001fc: 4152 adcs r2, r2
80001fe: 08c3 lsrs r3, r0, #3
8000200: 428b cmp r3, r1
8000202: d301 bcc.n 8000208 <__udivsi3+0xd8>
8000204: 00cb lsls r3, r1, #3
8000206: 1ac0 subs r0, r0, r3
8000208: 4152 adcs r2, r2
800020a: 0883 lsrs r3, r0, #2
800020c: 428b cmp r3, r1
800020e: d301 bcc.n 8000214 <__udivsi3+0xe4>
8000210: 008b lsls r3, r1, #2
8000212: 1ac0 subs r0, r0, r3
8000214: 4152 adcs r2, r2
8000216: 0843 lsrs r3, r0, #1
8000218: 428b cmp r3, r1
800021a: d301 bcc.n 8000220 <__udivsi3+0xf0>
800021c: 004b lsls r3, r1, #1
800021e: 1ac0 subs r0, r0, r3
8000220: 4152 adcs r2, r2
8000222: 1a41 subs r1, r0, r1
8000224: d200 bcs.n 8000228 <__udivsi3+0xf8>
8000226: 4601 mov r1, r0
8000228: 4152 adcs r2, r2
800022a: 4610 mov r0, r2
800022c: 4770 bx lr
800022e: e7ff b.n 8000230 <__udivsi3+0x100>
8000230: b501 push {r0, lr}
8000232: 2000 movs r0, #0
8000234: f000 f8f0 bl 8000418 <__aeabi_idiv0>
8000238: bd02 pop {r1, pc}
800023a: 46c0 nop @ (mov r8, r8)
0800023c <__aeabi_uidivmod>:
800023c: 2900 cmp r1, #0
800023e: d0f7 beq.n 8000230 <__udivsi3+0x100>
8000240: e776 b.n 8000130 <__udivsi3>
8000242: 4770 bx lr
08000244 <__divsi3>:
8000244: 4603 mov r3, r0
8000246: 430b orrs r3, r1
8000248: d47f bmi.n 800034a <__divsi3+0x106>
800024a: 2200 movs r2, #0
800024c: 0843 lsrs r3, r0, #1
800024e: 428b cmp r3, r1
8000250: d374 bcc.n 800033c <__divsi3+0xf8>
8000252: 0903 lsrs r3, r0, #4
8000254: 428b cmp r3, r1
8000256: d35f bcc.n 8000318 <__divsi3+0xd4>
8000258: 0a03 lsrs r3, r0, #8
800025a: 428b cmp r3, r1
800025c: d344 bcc.n 80002e8 <__divsi3+0xa4>
800025e: 0b03 lsrs r3, r0, #12
8000260: 428b cmp r3, r1
8000262: d328 bcc.n 80002b6 <__divsi3+0x72>
8000264: 0c03 lsrs r3, r0, #16
8000266: 428b cmp r3, r1
8000268: d30d bcc.n 8000286 <__divsi3+0x42>
800026a: 22ff movs r2, #255 @ 0xff
800026c: 0209 lsls r1, r1, #8
800026e: ba12 rev r2, r2
8000270: 0c03 lsrs r3, r0, #16
8000272: 428b cmp r3, r1
8000274: d302 bcc.n 800027c <__divsi3+0x38>
8000276: 1212 asrs r2, r2, #8
8000278: 0209 lsls r1, r1, #8
800027a: d065 beq.n 8000348 <__divsi3+0x104>
800027c: 0b03 lsrs r3, r0, #12
800027e: 428b cmp r3, r1
8000280: d319 bcc.n 80002b6 <__divsi3+0x72>
8000282: e000 b.n 8000286 <__divsi3+0x42>
8000284: 0a09 lsrs r1, r1, #8
8000286: 0bc3 lsrs r3, r0, #15
8000288: 428b cmp r3, r1
800028a: d301 bcc.n 8000290 <__divsi3+0x4c>
800028c: 03cb lsls r3, r1, #15
800028e: 1ac0 subs r0, r0, r3
8000290: 4152 adcs r2, r2
8000292: 0b83 lsrs r3, r0, #14
8000294: 428b cmp r3, r1
8000296: d301 bcc.n 800029c <__divsi3+0x58>
8000298: 038b lsls r3, r1, #14
800029a: 1ac0 subs r0, r0, r3
800029c: 4152 adcs r2, r2
800029e: 0b43 lsrs r3, r0, #13
80002a0: 428b cmp r3, r1
80002a2: d301 bcc.n 80002a8 <__divsi3+0x64>
80002a4: 034b lsls r3, r1, #13
80002a6: 1ac0 subs r0, r0, r3
80002a8: 4152 adcs r2, r2
80002aa: 0b03 lsrs r3, r0, #12
80002ac: 428b cmp r3, r1
80002ae: d301 bcc.n 80002b4 <__divsi3+0x70>
80002b0: 030b lsls r3, r1, #12
80002b2: 1ac0 subs r0, r0, r3
80002b4: 4152 adcs r2, r2
80002b6: 0ac3 lsrs r3, r0, #11
80002b8: 428b cmp r3, r1
80002ba: d301 bcc.n 80002c0 <__divsi3+0x7c>
80002bc: 02cb lsls r3, r1, #11
80002be: 1ac0 subs r0, r0, r3
80002c0: 4152 adcs r2, r2
80002c2: 0a83 lsrs r3, r0, #10
80002c4: 428b cmp r3, r1
80002c6: d301 bcc.n 80002cc <__divsi3+0x88>
80002c8: 028b lsls r3, r1, #10
80002ca: 1ac0 subs r0, r0, r3
80002cc: 4152 adcs r2, r2
80002ce: 0a43 lsrs r3, r0, #9
80002d0: 428b cmp r3, r1
80002d2: d301 bcc.n 80002d8 <__divsi3+0x94>
80002d4: 024b lsls r3, r1, #9
80002d6: 1ac0 subs r0, r0, r3
80002d8: 4152 adcs r2, r2
80002da: 0a03 lsrs r3, r0, #8
80002dc: 428b cmp r3, r1
80002de: d301 bcc.n 80002e4 <__divsi3+0xa0>
80002e0: 020b lsls r3, r1, #8
80002e2: 1ac0 subs r0, r0, r3
80002e4: 4152 adcs r2, r2
80002e6: d2cd bcs.n 8000284 <__divsi3+0x40>
80002e8: 09c3 lsrs r3, r0, #7
80002ea: 428b cmp r3, r1
80002ec: d301 bcc.n 80002f2 <__divsi3+0xae>
80002ee: 01cb lsls r3, r1, #7
80002f0: 1ac0 subs r0, r0, r3
80002f2: 4152 adcs r2, r2
80002f4: 0983 lsrs r3, r0, #6
80002f6: 428b cmp r3, r1
80002f8: d301 bcc.n 80002fe <__divsi3+0xba>
80002fa: 018b lsls r3, r1, #6
80002fc: 1ac0 subs r0, r0, r3
80002fe: 4152 adcs r2, r2
8000300: 0943 lsrs r3, r0, #5
8000302: 428b cmp r3, r1
8000304: d301 bcc.n 800030a <__divsi3+0xc6>
8000306: 014b lsls r3, r1, #5
8000308: 1ac0 subs r0, r0, r3
800030a: 4152 adcs r2, r2
800030c: 0903 lsrs r3, r0, #4
800030e: 428b cmp r3, r1
8000310: d301 bcc.n 8000316 <__divsi3+0xd2>
8000312: 010b lsls r3, r1, #4
8000314: 1ac0 subs r0, r0, r3
8000316: 4152 adcs r2, r2
8000318: 08c3 lsrs r3, r0, #3
800031a: 428b cmp r3, r1
800031c: d301 bcc.n 8000322 <__divsi3+0xde>
800031e: 00cb lsls r3, r1, #3
8000320: 1ac0 subs r0, r0, r3
8000322: 4152 adcs r2, r2
8000324: 0883 lsrs r3, r0, #2
8000326: 428b cmp r3, r1
8000328: d301 bcc.n 800032e <__divsi3+0xea>
800032a: 008b lsls r3, r1, #2
800032c: 1ac0 subs r0, r0, r3
800032e: 4152 adcs r2, r2
8000330: 0843 lsrs r3, r0, #1
8000332: 428b cmp r3, r1
8000334: d301 bcc.n 800033a <__divsi3+0xf6>
8000336: 004b lsls r3, r1, #1
8000338: 1ac0 subs r0, r0, r3
800033a: 4152 adcs r2, r2
800033c: 1a41 subs r1, r0, r1
800033e: d200 bcs.n 8000342 <__divsi3+0xfe>
8000340: 4601 mov r1, r0
8000342: 4152 adcs r2, r2
8000344: 4610 mov r0, r2
8000346: 4770 bx lr
8000348: e05d b.n 8000406 <__divsi3+0x1c2>
800034a: 0fca lsrs r2, r1, #31
800034c: d000 beq.n 8000350 <__divsi3+0x10c>
800034e: 4249 negs r1, r1
8000350: 1003 asrs r3, r0, #32
8000352: d300 bcc.n 8000356 <__divsi3+0x112>
8000354: 4240 negs r0, r0
8000356: 4053 eors r3, r2
8000358: 2200 movs r2, #0
800035a: 469c mov ip, r3
800035c: 0903 lsrs r3, r0, #4
800035e: 428b cmp r3, r1
8000360: d32d bcc.n 80003be <__divsi3+0x17a>
8000362: 0a03 lsrs r3, r0, #8
8000364: 428b cmp r3, r1
8000366: d312 bcc.n 800038e <__divsi3+0x14a>
8000368: 22fc movs r2, #252 @ 0xfc
800036a: 0189 lsls r1, r1, #6
800036c: ba12 rev r2, r2
800036e: 0a03 lsrs r3, r0, #8
8000370: 428b cmp r3, r1
8000372: d30c bcc.n 800038e <__divsi3+0x14a>
8000374: 0189 lsls r1, r1, #6
8000376: 1192 asrs r2, r2, #6
8000378: 428b cmp r3, r1
800037a: d308 bcc.n 800038e <__divsi3+0x14a>
800037c: 0189 lsls r1, r1, #6
800037e: 1192 asrs r2, r2, #6
8000380: 428b cmp r3, r1
8000382: d304 bcc.n 800038e <__divsi3+0x14a>
8000384: 0189 lsls r1, r1, #6
8000386: d03a beq.n 80003fe <__divsi3+0x1ba>
8000388: 1192 asrs r2, r2, #6
800038a: e000 b.n 800038e <__divsi3+0x14a>
800038c: 0989 lsrs r1, r1, #6
800038e: 09c3 lsrs r3, r0, #7
8000390: 428b cmp r3, r1
8000392: d301 bcc.n 8000398 <__divsi3+0x154>
8000394: 01cb lsls r3, r1, #7
8000396: 1ac0 subs r0, r0, r3
8000398: 4152 adcs r2, r2
800039a: 0983 lsrs r3, r0, #6
800039c: 428b cmp r3, r1
800039e: d301 bcc.n 80003a4 <__divsi3+0x160>
80003a0: 018b lsls r3, r1, #6
80003a2: 1ac0 subs r0, r0, r3
80003a4: 4152 adcs r2, r2
80003a6: 0943 lsrs r3, r0, #5
80003a8: 428b cmp r3, r1
80003aa: d301 bcc.n 80003b0 <__divsi3+0x16c>
80003ac: 014b lsls r3, r1, #5
80003ae: 1ac0 subs r0, r0, r3
80003b0: 4152 adcs r2, r2
80003b2: 0903 lsrs r3, r0, #4
80003b4: 428b cmp r3, r1
80003b6: d301 bcc.n 80003bc <__divsi3+0x178>
80003b8: 010b lsls r3, r1, #4
80003ba: 1ac0 subs r0, r0, r3
80003bc: 4152 adcs r2, r2
80003be: 08c3 lsrs r3, r0, #3
80003c0: 428b cmp r3, r1
80003c2: d301 bcc.n 80003c8 <__divsi3+0x184>
80003c4: 00cb lsls r3, r1, #3
80003c6: 1ac0 subs r0, r0, r3
80003c8: 4152 adcs r2, r2
80003ca: 0883 lsrs r3, r0, #2
80003cc: 428b cmp r3, r1
80003ce: d301 bcc.n 80003d4 <__divsi3+0x190>
80003d0: 008b lsls r3, r1, #2
80003d2: 1ac0 subs r0, r0, r3
80003d4: 4152 adcs r2, r2
80003d6: d2d9 bcs.n 800038c <__divsi3+0x148>
80003d8: 0843 lsrs r3, r0, #1
80003da: 428b cmp r3, r1
80003dc: d301 bcc.n 80003e2 <__divsi3+0x19e>
80003de: 004b lsls r3, r1, #1
80003e0: 1ac0 subs r0, r0, r3
80003e2: 4152 adcs r2, r2
80003e4: 1a41 subs r1, r0, r1
80003e6: d200 bcs.n 80003ea <__divsi3+0x1a6>
80003e8: 4601 mov r1, r0
80003ea: 4663 mov r3, ip
80003ec: 4152 adcs r2, r2
80003ee: 105b asrs r3, r3, #1
80003f0: 4610 mov r0, r2
80003f2: d301 bcc.n 80003f8 <__divsi3+0x1b4>
80003f4: 4240 negs r0, r0
80003f6: 2b00 cmp r3, #0
80003f8: d500 bpl.n 80003fc <__divsi3+0x1b8>
80003fa: 4249 negs r1, r1
80003fc: 4770 bx lr
80003fe: 4663 mov r3, ip
8000400: 105b asrs r3, r3, #1
8000402: d300 bcc.n 8000406 <__divsi3+0x1c2>
8000404: 4240 negs r0, r0
8000406: b501 push {r0, lr}
8000408: 2000 movs r0, #0
800040a: f000 f805 bl 8000418 <__aeabi_idiv0>
800040e: bd02 pop {r1, pc}
08000410 <__aeabi_idivmod>:
8000410: 2900 cmp r1, #0
8000412: d0f8 beq.n 8000406 <__divsi3+0x1c2>
8000414: e716 b.n 8000244 <__divsi3>
8000416: 4770 bx lr
08000418 <__aeabi_idiv0>:
8000418: 4770 bx lr
800041a: 46c0 nop @ (mov r8, r8)
0800041c <__aeabi_ldivmod>:
800041c: 2b00 cmp r3, #0
800041e: d115 bne.n 800044c <__aeabi_ldivmod+0x30>
8000420: 2a00 cmp r2, #0
8000422: d113 bne.n 800044c <__aeabi_ldivmod+0x30>
8000424: 2900 cmp r1, #0
8000426: db06 blt.n 8000436 <__aeabi_ldivmod+0x1a>
8000428: dc01 bgt.n 800042e <__aeabi_ldivmod+0x12>
800042a: 2800 cmp r0, #0
800042c: d006 beq.n 800043c <__aeabi_ldivmod+0x20>
800042e: 2000 movs r0, #0
8000430: 43c0 mvns r0, r0
8000432: 0841 lsrs r1, r0, #1
8000434: e002 b.n 800043c <__aeabi_ldivmod+0x20>
8000436: 2180 movs r1, #128 @ 0x80
8000438: 0609 lsls r1, r1, #24
800043a: 2000 movs r0, #0
800043c: b407 push {r0, r1, r2}
800043e: 4802 ldr r0, [pc, #8] @ (8000448 <__aeabi_ldivmod+0x2c>)
8000440: a101 add r1, pc, #4 @ (adr r1, 8000448 <__aeabi_ldivmod+0x2c>)
8000442: 1840 adds r0, r0, r1
8000444: 9002 str r0, [sp, #8]
8000446: bd03 pop {r0, r1, pc}
8000448: ffffffd1 .word 0xffffffd1
800044c: b403 push {r0, r1}
800044e: 4668 mov r0, sp
8000450: b501 push {r0, lr}
8000452: 9802 ldr r0, [sp, #8]
8000454: f000 f834 bl 80004c0 <__gnu_ldivmod_helper>
8000458: 9b01 ldr r3, [sp, #4]
800045a: 469e mov lr, r3
800045c: b002 add sp, #8
800045e: bc0c pop {r2, r3}
8000460: 4770 bx lr
8000462: 46c0 nop @ (mov r8, r8)
08000464 <__aeabi_lmul>:
8000464: b5f0 push {r4, r5, r6, r7, lr}
8000466: 46ce mov lr, r9
8000468: 4699 mov r9, r3
800046a: 0c03 lsrs r3, r0, #16
800046c: 469c mov ip, r3
800046e: 0413 lsls r3, r2, #16
8000470: 4647 mov r7, r8
8000472: 0c1b lsrs r3, r3, #16
8000474: 001d movs r5, r3
8000476: 000e movs r6, r1
8000478: 4661 mov r1, ip
800047a: 0404 lsls r4, r0, #16
800047c: 0c24 lsrs r4, r4, #16
800047e: b580 push {r7, lr}
8000480: 0007 movs r7, r0
8000482: 0c10 lsrs r0, r2, #16
8000484: 434b muls r3, r1
8000486: 4365 muls r5, r4
8000488: 4341 muls r1, r0
800048a: 4360 muls r0, r4
800048c: 0c2c lsrs r4, r5, #16
800048e: 18c0 adds r0, r0, r3
8000490: 1824 adds r4, r4, r0
8000492: 468c mov ip, r1
8000494: 42a3 cmp r3, r4
8000496: d903 bls.n 80004a0 <__aeabi_lmul+0x3c>
8000498: 2380 movs r3, #128 @ 0x80
800049a: 025b lsls r3, r3, #9
800049c: 4698 mov r8, r3
800049e: 44c4 add ip, r8
80004a0: 4649 mov r1, r9
80004a2: 4379 muls r1, r7
80004a4: 4356 muls r6, r2
80004a6: 0c23 lsrs r3, r4, #16
80004a8: 042d lsls r5, r5, #16
80004aa: 0c2d lsrs r5, r5, #16
80004ac: 1989 adds r1, r1, r6
80004ae: 4463 add r3, ip
80004b0: 0424 lsls r4, r4, #16
80004b2: 1960 adds r0, r4, r5
80004b4: 18c9 adds r1, r1, r3
80004b6: bcc0 pop {r6, r7}
80004b8: 46b9 mov r9, r7
80004ba: 46b0 mov r8, r6
80004bc: bdf0 pop {r4, r5, r6, r7, pc}
80004be: 46c0 nop @ (mov r8, r8)
080004c0 <__gnu_ldivmod_helper>:
80004c0: b5f8 push {r3, r4, r5, r6, r7, lr}
80004c2: 46ce mov lr, r9
80004c4: 4647 mov r7, r8
80004c6: b580 push {r7, lr}
80004c8: 4691 mov r9, r2
80004ca: 4698 mov r8, r3
80004cc: 0004 movs r4, r0
80004ce: 000d movs r5, r1
80004d0: f000 f814 bl 80004fc <__divdi3>
80004d4: 0007 movs r7, r0
80004d6: 000e movs r6, r1
80004d8: 0002 movs r2, r0
80004da: 000b movs r3, r1
80004dc: 4648 mov r0, r9
80004de: 4641 mov r1, r8
80004e0: f7ff ffc0 bl 8000464 <__aeabi_lmul>
80004e4: 1a24 subs r4, r4, r0
80004e6: 418d sbcs r5, r1
80004e8: 9b08 ldr r3, [sp, #32]
80004ea: 0038 movs r0, r7
80004ec: 0031 movs r1, r6
80004ee: 601c str r4, [r3, #0]
80004f0: 605d str r5, [r3, #4]
80004f2: bcc0 pop {r6, r7}
80004f4: 46b9 mov r9, r7
80004f6: 46b0 mov r8, r6
80004f8: bdf8 pop {r3, r4, r5, r6, r7, pc}
80004fa: 46c0 nop @ (mov r8, r8)
080004fc <__divdi3>:
80004fc: b5f0 push {r4, r5, r6, r7, lr}
80004fe: 4645 mov r5, r8
8000500: 46de mov lr, fp
8000502: 4657 mov r7, sl
8000504: 464e mov r6, r9
8000506: b5e0 push {r5, r6, r7, lr}
8000508: b083 sub sp, #12
800050a: 9200 str r2, [sp, #0]
800050c: 9301 str r3, [sp, #4]
800050e: 000d movs r5, r1
8000510: 9900 ldr r1, [sp, #0]
8000512: 9a01 ldr r2, [sp, #4]
8000514: 0004 movs r4, r0
8000516: 2d00 cmp r5, #0
8000518: db61 blt.n 80005de <__divdi3+0xe2>
800051a: 0006 movs r6, r0
800051c: 002f movs r7, r5
800051e: 2a00 cmp r2, #0
8000520: db0c blt.n 800053c <__divdi3+0x40>
8000522: 9c00 ldr r4, [sp, #0]
8000524: 9d01 ldr r5, [sp, #4]
8000526: 42bd cmp r5, r7
8000528: d91a bls.n 8000560 <__divdi3+0x64>
800052a: 2000 movs r0, #0
800052c: 2100 movs r1, #0
800052e: b003 add sp, #12
8000530: bcf0 pop {r4, r5, r6, r7}
8000532: 46bb mov fp, r7
8000534: 46b2 mov sl, r6
8000536: 46a9 mov r9, r5
8000538: 46a0 mov r8, r4
800053a: bdf0 pop {r4, r5, r6, r7, pc}
800053c: 2500 movs r5, #0
800053e: 424c negs r4, r1
8000540: 4195 sbcs r5, r2
8000542: 42bd cmp r5, r7
8000544: d8f1 bhi.n 800052a <__divdi3+0x2e>
8000546: d100 bne.n 800054a <__divdi3+0x4e>
8000548: e0ae b.n 80006a8 <__divdi3+0x1ac>
800054a: 2301 movs r3, #1
800054c: 425b negs r3, r3
800054e: 4699 mov r9, r3
8000550: e00b b.n 800056a <__divdi3+0x6e>
8000552: 9a00 ldr r2, [sp, #0]
8000554: 9b01 ldr r3, [sp, #4]
8000556: 2500 movs r5, #0
8000558: 4254 negs r4, r2
800055a: 419d sbcs r5, r3
800055c: 42bd cmp r5, r7
800055e: d8e4 bhi.n 800052a <__divdi3+0x2e>
8000560: 42bd cmp r5, r7
8000562: d100 bne.n 8000566 <__divdi3+0x6a>
8000564: e09c b.n 80006a0 <__divdi3+0x1a4>
8000566: 2300 movs r3, #0
8000568: 4699 mov r9, r3
800056a: 0029 movs r1, r5
800056c: 0020 movs r0, r4
800056e: f000 f8c3 bl 80006f8 <__clzdi2>
8000572: 4680 mov r8, r0
8000574: 0039 movs r1, r7
8000576: 0030 movs r0, r6
8000578: f000 f8be bl 80006f8 <__clzdi2>
800057c: 4643 mov r3, r8
800057e: 1a1b subs r3, r3, r0
8000580: 4698 mov r8, r3
8000582: 3b20 subs r3, #32
8000584: d500 bpl.n 8000588 <__divdi3+0x8c>
8000586: e080 b.n 800068a <__divdi3+0x18e>
8000588: 0021 movs r1, r4
800058a: 4099 lsls r1, r3
800058c: 469a mov sl, r3
800058e: 000b movs r3, r1
8000590: 0021 movs r1, r4
8000592: 4640 mov r0, r8
8000594: 4081 lsls r1, r0
8000596: 000a movs r2, r1
8000598: 42bb cmp r3, r7
800059a: d82d bhi.n 80005f8 <__divdi3+0xfc>
800059c: d02a beq.n 80005f4 <__divdi3+0xf8>
800059e: 4651 mov r1, sl
80005a0: 1ab6 subs r6, r6, r2
80005a2: 419f sbcs r7, r3
80005a4: 2900 cmp r1, #0
80005a6: da00 bge.n 80005aa <__divdi3+0xae>
80005a8: e09b b.n 80006e2 <__divdi3+0x1e6>
80005aa: 2100 movs r1, #0
80005ac: 2000 movs r0, #0
80005ae: 2401 movs r4, #1
80005b0: 9000 str r0, [sp, #0]
80005b2: 9101 str r1, [sp, #4]
80005b4: 4651 mov r1, sl
80005b6: 408c lsls r4, r1
80005b8: 9401 str r4, [sp, #4]
80005ba: 2401 movs r4, #1
80005bc: 4645 mov r5, r8
80005be: 40ac lsls r4, r5
80005c0: 9400 str r4, [sp, #0]
80005c2: 4644 mov r4, r8
80005c4: 2c00 cmp r4, #0
80005c6: d11e bne.n 8000606 <__divdi3+0x10a>
80005c8: 9800 ldr r0, [sp, #0]
80005ca: 9901 ldr r1, [sp, #4]
80005cc: 464b mov r3, r9
80005ce: 2b00 cmp r3, #0
80005d0: d0ad beq.n 800052e <__divdi3+0x32>
80005d2: 0003 movs r3, r0
80005d4: 000c movs r4, r1
80005d6: 2100 movs r1, #0
80005d8: 4258 negs r0, r3
80005da: 41a1 sbcs r1, r4
80005dc: e7a7 b.n 800052e <__divdi3+0x32>
80005de: 2700 movs r7, #0
80005e0: 4266 negs r6, r4
80005e2: 41af sbcs r7, r5
80005e4: 2a00 cmp r2, #0
80005e6: dbb4 blt.n 8000552 <__divdi3+0x56>
80005e8: 9c00 ldr r4, [sp, #0]
80005ea: 9d01 ldr r5, [sp, #4]
80005ec: 42bd cmp r5, r7
80005ee: d89c bhi.n 800052a <__divdi3+0x2e>
80005f0: d1ab bne.n 800054a <__divdi3+0x4e>
80005f2: e059 b.n 80006a8 <__divdi3+0x1ac>
80005f4: 42b1 cmp r1, r6
80005f6: d9d2 bls.n 800059e <__divdi3+0xa2>
80005f8: 2000 movs r0, #0
80005fa: 2100 movs r1, #0
80005fc: 4644 mov r4, r8
80005fe: 9000 str r0, [sp, #0]
8000600: 9101 str r1, [sp, #4]
8000602: 2c00 cmp r4, #0
8000604: d0e0 beq.n 80005c8 <__divdi3+0xcc>
8000606: 07dc lsls r4, r3, #31
8000608: 46a4 mov ip, r4
800060a: 4661 mov r1, ip
800060c: 0854 lsrs r4, r2, #1
800060e: 46c4 mov ip, r8
8000610: 430c orrs r4, r1
8000612: 085d lsrs r5, r3, #1
8000614: e014 b.n 8000640 <__divdi3+0x144>
8000616: 42bd cmp r5, r7
8000618: d101 bne.n 800061e <__divdi3+0x122>
800061a: 42b4 cmp r4, r6
800061c: d812 bhi.n 8000644 <__divdi3+0x148>
800061e: 0032 movs r2, r6
8000620: 003b movs r3, r7
8000622: 1b12 subs r2, r2, r4
8000624: 41ab sbcs r3, r5
8000626: 2601 movs r6, #1
8000628: 1892 adds r2, r2, r2
800062a: 415b adcs r3, r3
800062c: 2700 movs r7, #0
800062e: 18b6 adds r6, r6, r2
8000630: 415f adcs r7, r3
8000632: 2301 movs r3, #1
8000634: 425b negs r3, r3
8000636: 469b mov fp, r3
8000638: 44dc add ip, fp
800063a: 4663 mov r3, ip
800063c: 2b00 cmp r3, #0
800063e: d00a beq.n 8000656 <__divdi3+0x15a>
8000640: 42bd cmp r5, r7
8000642: d9e8 bls.n 8000616 <__divdi3+0x11a>
8000644: 2301 movs r3, #1
8000646: 425b negs r3, r3
8000648: 469b mov fp, r3
800064a: 44dc add ip, fp
800064c: 4663 mov r3, ip
800064e: 19b6 adds r6, r6, r6
8000650: 417f adcs r7, r7
8000652: 2b00 cmp r3, #0
8000654: d1f4 bne.n 8000640 <__divdi3+0x144>
8000656: 9a00 ldr r2, [sp, #0]
8000658: 9b01 ldr r3, [sp, #4]
800065a: 4651 mov r1, sl
800065c: 1992 adds r2, r2, r6
800065e: 417b adcs r3, r7
8000660: 2900 cmp r1, #0
8000662: db25 blt.n 80006b0 <__divdi3+0x1b4>
8000664: 003c movs r4, r7
8000666: 003d movs r5, r7
8000668: 40cc lsrs r4, r1
800066a: 4641 mov r1, r8
800066c: 40cd lsrs r5, r1
800066e: 4651 mov r1, sl
8000670: 2900 cmp r1, #0
8000672: db2d blt.n 80006d0 <__divdi3+0x1d4>
8000674: 0025 movs r5, r4
8000676: 408d lsls r5, r1
8000678: 0029 movs r1, r5
800067a: 4645 mov r5, r8
800067c: 40ac lsls r4, r5
800067e: 0020 movs r0, r4
8000680: 1a12 subs r2, r2, r0
8000682: 418b sbcs r3, r1
8000684: 9200 str r2, [sp, #0]
8000686: 9301 str r3, [sp, #4]
8000688: e79e b.n 80005c8 <__divdi3+0xcc>
800068a: 4642 mov r2, r8
800068c: 0028 movs r0, r5
800068e: 469a mov sl, r3
8000690: 2320 movs r3, #32
8000692: 0021 movs r1, r4
8000694: 4090 lsls r0, r2
8000696: 1a9b subs r3, r3, r2
8000698: 40d9 lsrs r1, r3
800069a: 0003 movs r3, r0
800069c: 430b orrs r3, r1
800069e: e777 b.n 8000590 <__divdi3+0x94>
80006a0: 42b4 cmp r4, r6
80006a2: d900 bls.n 80006a6 <__divdi3+0x1aa>
80006a4: e741 b.n 800052a <__divdi3+0x2e>
80006a6: e75e b.n 8000566 <__divdi3+0x6a>
80006a8: 42b4 cmp r4, r6
80006aa: d800 bhi.n 80006ae <__divdi3+0x1b2>
80006ac: e74d b.n 800054a <__divdi3+0x4e>
80006ae: e73c b.n 800052a <__divdi3+0x2e>
80006b0: 4640 mov r0, r8
80006b2: 2120 movs r1, #32
80006b4: 1a09 subs r1, r1, r0
80006b6: 0038 movs r0, r7
80006b8: 4088 lsls r0, r1
80006ba: 0034 movs r4, r6
80006bc: 0001 movs r1, r0
80006be: 4640 mov r0, r8
80006c0: 40c4 lsrs r4, r0
80006c2: 003d movs r5, r7
80006c4: 430c orrs r4, r1
80006c6: 4641 mov r1, r8
80006c8: 40cd lsrs r5, r1
80006ca: 4651 mov r1, sl
80006cc: 2900 cmp r1, #0
80006ce: dad1 bge.n 8000674 <__divdi3+0x178>
80006d0: 4640 mov r0, r8
80006d2: 2120 movs r1, #32
80006d4: 0026 movs r6, r4
80006d6: 4085 lsls r5, r0
80006d8: 1a09 subs r1, r1, r0
80006da: 40ce lsrs r6, r1
80006dc: 0029 movs r1, r5
80006de: 4331 orrs r1, r6
80006e0: e7cb b.n 800067a <__divdi3+0x17e>
80006e2: 4641 mov r1, r8
80006e4: 2420 movs r4, #32
80006e6: 2501 movs r5, #1
80006e8: 1a64 subs r4, r4, r1
80006ea: 2000 movs r0, #0
80006ec: 2100 movs r1, #0
80006ee: 40e5 lsrs r5, r4
80006f0: 9000 str r0, [sp, #0]
80006f2: 9101 str r1, [sp, #4]
80006f4: 9501 str r5, [sp, #4]
80006f6: e760 b.n 80005ba <__divdi3+0xbe>
080006f8 <__clzdi2>:
80006f8: b510 push {r4, lr}
80006fa: 2900 cmp r1, #0
80006fc: d103 bne.n 8000706 <__clzdi2+0xe>
80006fe: f000 f807 bl 8000710 <__clzsi2>
8000702: 3020 adds r0, #32
8000704: e002 b.n 800070c <__clzdi2+0x14>
8000706: 0008 movs r0, r1
8000708: f000 f802 bl 8000710 <__clzsi2>
800070c: bd10 pop {r4, pc}
800070e: 46c0 nop @ (mov r8, r8)
08000710 <__clzsi2>:
8000710: 211c movs r1, #28
8000712: 2301 movs r3, #1
8000714: 041b lsls r3, r3, #16
8000716: 4298 cmp r0, r3
8000718: d301 bcc.n 800071e <__clzsi2+0xe>
800071a: 0c00 lsrs r0, r0, #16
800071c: 3910 subs r1, #16
800071e: 0a1b lsrs r3, r3, #8
8000720: 4298 cmp r0, r3
8000722: d301 bcc.n 8000728 <__clzsi2+0x18>
8000724: 0a00 lsrs r0, r0, #8
8000726: 3908 subs r1, #8
8000728: 091b lsrs r3, r3, #4
800072a: 4298 cmp r0, r3
800072c: d301 bcc.n 8000732 <__clzsi2+0x22>
800072e: 0900 lsrs r0, r0, #4
8000730: 3904 subs r1, #4
8000732: a202 add r2, pc, #8 @ (adr r2, 800073c <__clzsi2+0x2c>)
8000734: 5c10 ldrb r0, [r2, r0]
8000736: 1840 adds r0, r0, r1
8000738: 4770 bx lr
800073a: 46c0 nop @ (mov r8, r8)
800073c: 02020304 .word 0x02020304
8000740: 01010101 .word 0x01010101
...
0800074c <CRC8_107_add>:
#include "crc.h"
void CRC8_107_add(CRC8_107 *ctx, uint8_t data)
{
ctx->crc ^= ((uint32_t)data << 8);
800074c: 6803 ldr r3, [r0, #0]
for (size_t bit_n = 0; bit_n < 8; bit_n++) {
if (ctx->crc & 0x8000u) {
800074e: 2280 movs r2, #128 @ 0x80
ctx->crc ^= ((uint32_t)data << 8);
8000750: 0209 lsls r1, r1, #8
8000752: 4059 eors r1, r3
8000754: 2308 movs r3, #8
{
8000756: b510 push {r4, lr}
ctx->crc ^= ((uint32_t)0x1070u << 3); // same as 0x8380
8000758: 4c05 ldr r4, [pc, #20] @ (8000770 <CRC8_107_add+0x24>)
if (ctx->crc & 0x8000u) {
800075a: 0212 lsls r2, r2, #8
800075c: 4211 tst r1, r2
800075e: d000 beq.n 8000762 <CRC8_107_add+0x16>
ctx->crc ^= ((uint32_t)0x1070u << 3); // same as 0x8380
8000760: 4061 eors r1, r4
for (size_t bit_n = 0; bit_n < 8; bit_n++) {
8000762: 3b01 subs r3, #1
}
ctx->crc <<= 1;
8000764: 0049 lsls r1, r1, #1
for (size_t bit_n = 0; bit_n < 8; bit_n++) {
8000766: 2b00 cmp r3, #0
8000768: d1f8 bne.n 800075c <CRC8_107_add+0x10>
}
}
800076a: 6001 str r1, [r0, #0]
800076c: bd10 pop {r4, pc}
800076e: 46c0 nop @ (mov r8, r8)
8000770: 00008380 .word 0x00008380
08000774 <CRC8_107_getChecksum>:
uint8_t CRC8_107_getChecksum(const CRC8_107 *ctx)
{
return (uint8_t)(ctx->crc >> 8);
8000774: 6800 ldr r0, [r0, #0]
8000776: 0a00 lsrs r0, r0, #8
8000778: b2c0 uxtb r0, r0
}
800077a: 4770 bx lr
0800077c <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
800077c: b570 push {r4, r5, r6, lr}
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1);
800077e: 2607 movs r6, #7
8000780: 2501 movs r5, #1
{
8000782: b08c sub sp, #48 @ 0x30
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000784: 2218 movs r2, #24
8000786: 2100 movs r1, #0
8000788: a806 add r0, sp, #24
800078a: f004 fcff bl 800518c <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
800078e: 2214 movs r2, #20
8000790: 2100 movs r1, #0
8000792: 4668 mov r0, sp
8000794: f004 fcfa bl 800518c <memset>
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1);
8000798: 4a11 ldr r2, [pc, #68] @ (80007e0 <SystemClock_Config+0x64>)
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
800079a: a805 add r0, sp, #20
__HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1);
800079c: 6813 ldr r3, [r2, #0]
800079e: 43b3 bics r3, r6
80007a0: 432b orrs r3, r5
80007a2: 6013 str r3, [r2, #0]
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
80007a4: 2302 movs r3, #2
80007a6: 9305 str r3, [sp, #20]
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
80007a8: 33fe adds r3, #254 @ 0xfe
80007aa: 9308 str r3, [sp, #32]
RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
80007ac: 2300 movs r3, #0
80007ae: 9309 str r3, [sp, #36] @ 0x24
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
80007b0: 3340 adds r3, #64 @ 0x40
80007b2: 930a str r3, [sp, #40] @ 0x28
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80007b4: f002 fdca bl 800334c <HAL_RCC_OscConfig>
80007b8: 2800 cmp r0, #0
80007ba: d001 beq.n 80007c0 <SystemClock_Config+0x44>
\details Disables IRQ interrupts by setting special-purpose register PRIMASK.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
80007bc: b672 cpsid i
void Error_Handler(void)
{
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
__disable_irq();
while (1)
80007be: e7fe b.n 80007be <SystemClock_Config+0x42>
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
80007c0: 9001 str r0, [sp, #4]
RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
80007c2: 9002 str r0, [sp, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
80007c4: 9003 str r0, [sp, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
80007c6: 9004 str r0, [sp, #16]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
80007c8: 0029 movs r1, r5
80007ca: 4668 mov r0, sp
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80007cc: 9600 str r6, [sp, #0]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
80007ce: f002 ff21 bl 8003614 <HAL_RCC_ClockConfig>
80007d2: 2800 cmp r0, #0
80007d4: d001 beq.n 80007da <SystemClock_Config+0x5e>
80007d6: b672 cpsid i
while (1)
80007d8: e7fe b.n 80007d8 <SystemClock_Config+0x5c>
}
80007da: b00c add sp, #48 @ 0x30
80007dc: bd70 pop {r4, r5, r6, pc}
80007de: 46c0 nop @ (mov r8, r8)
80007e0: 40022000 .word 0x40022000
080007e4 <HAL_TIM_PeriodElapsedCallback>:
{
80007e4: b5f8 push {r3, r4, r5, r6, r7, lr}
if (htim == &htim14) // encoder check timer (runs at 20khz)
80007e6: 4b53 ldr r3, [pc, #332] @ (8000934 <HAL_TIM_PeriodElapsedCallback+0x150>)
80007e8: 4c53 ldr r4, [pc, #332] @ (8000938 <HAL_TIM_PeriodElapsedCallback+0x154>)
80007ea: 4298 cmp r0, r3
80007ec: d000 beq.n 80007f0 <HAL_TIM_PeriodElapsedCallback+0xc>
80007ee: e093 b.n 8000918 <HAL_TIM_PeriodElapsedCallback+0x134>
uint16_t count = htim3.Instance->CNT;
80007f0: 4b52 ldr r3, [pc, #328] @ (800093c <HAL_TIM_PeriodElapsedCallback+0x158>)
if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
80007f2: 4d53 ldr r5, [pc, #332] @ (8000940 <HAL_TIM_PeriodElapsedCallback+0x15c>)
uint16_t count = htim3.Instance->CNT;
80007f4: 681b ldr r3, [r3, #0]
80007f6: 27fa movs r7, #250 @ 0xfa
80007f8: 6a59 ldr r1, [r3, #36] @ 0x24
if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
80007fa: 882b ldrh r3, [r5, #0]
encoder_count_extra ++;
80007fc: 4851 ldr r0, [pc, #324] @ (8000944 <HAL_TIM_PeriodElapsedCallback+0x160>)
if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
80007fe: 469c mov ip, r3
8000800: 4e51 ldr r6, [pc, #324] @ (8000948 <HAL_TIM_PeriodElapsedCallback+0x164>)
encoder_count_extra ++;
8000802: 6803 ldr r3, [r0, #0]
uint16_t count = htim3.Instance->CNT;
8000804: b28a uxth r2, r1
if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
8000806: 00bf lsls r7, r7, #2
8000808: 45b4 cmp ip, r6
800080a: d958 bls.n 80008be <HAL_TIM_PeriodElapsedCallback+0xda>
encoder_count_extra ++;
800080c: 3301 adds r3, #1
if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
800080e: 42ba cmp r2, r7
8000810: d35a bcc.n 80008c8 <HAL_TIM_PeriodElapsedCallback+0xe4>
if (total_count > POSITION_OVERFLOW_THRESHOLD)
8000812: 2780 movs r7, #128 @ 0x80
encoder_previous = count; // update previous for next cycle
8000814: 802a strh r2, [r5, #0]
total_count = (encoder_count_extra * 65536) + count;
8000816: 4d4b ldr r5, [pc, #300] @ (8000944 <HAL_TIM_PeriodElapsedCallback+0x160>)
8000818: b289 uxth r1, r1
800081a: 682a ldr r2, [r5, #0]
800081c: 4e4b ldr r6, [pc, #300] @ (800094c <HAL_TIM_PeriodElapsedCallback+0x168>)
800081e: 0413 lsls r3, r2, #16
8000820: 185b adds r3, r3, r1
target_count -= adjustment;
8000822: 494b ldr r1, [pc, #300] @ (8000950 <HAL_TIM_PeriodElapsedCallback+0x16c>)
total_count = (encoder_count_extra * 65536) + count;
8000824: 6033 str r3, [r6, #0]
target_count -= adjustment;
8000826: 6808 ldr r0, [r1, #0]
if (total_count > POSITION_OVERFLOW_THRESHOLD)
8000828: 05ff lsls r7, r7, #23
800082a: 42bb cmp r3, r7
800082c: db4e blt.n 80008cc <HAL_TIM_PeriodElapsedCallback+0xe8>
total_count -= adjustment;
800082e: 4f49 ldr r7, [pc, #292] @ (8000954 <HAL_TIM_PeriodElapsedCallback+0x170>)
8000830: 19db adds r3, r3, r7
8000832: 6033 str r3, [r6, #0]
feed_target_position -= adjustment;
8000834: 4e48 ldr r6, [pc, #288] @ (8000958 <HAL_TIM_PeriodElapsedCallback+0x174>)
target_count -= adjustment;
8000836: 19c0 adds r0, r0, r7
8000838: 6008 str r0, [r1, #0]
feed_target_position -= adjustment;
800083a: 6830 ldr r0, [r6, #0]
800083c: 19c0 adds r0, r0, r7
800083e: 6030 str r0, [r6, #0]
encoder_count_extra -= (adjustment / 65536);
8000840: 4846 ldr r0, [pc, #280] @ (800095c <HAL_TIM_PeriodElapsedCallback+0x178>)
encoder_count_extra += (adjustment / 65536);
8000842: 1812 adds r2, r2, r0
mm_position = 0;
8000844: 2000 movs r0, #0
encoder_count_extra += (adjustment / 65536);
8000846: 602a str r2, [r5, #0]
mm_position = 0;
8000848: 4a45 ldr r2, [pc, #276] @ (8000960 <HAL_TIM_PeriodElapsedCallback+0x17c>)
800084a: 6010 str r0, [r2, #0]
if (pid_add!=0)
800084c: 4845 ldr r0, [pc, #276] @ (8000964 <HAL_TIM_PeriodElapsedCallback+0x180>)
800084e: 6802 ldr r2, [r0, #0]
8000850: 2a00 cmp r2, #0
8000852: d004 beq.n 800085e <HAL_TIM_PeriodElapsedCallback+0x7a>
int64_t temp = target_count + pid_add;
8000854: 680d ldr r5, [r1, #0]
8000856: 1952 adds r2, r2, r5
pid_add = 0;
8000858: 2500 movs r5, #0
target_count = temp;
800085a: 600a str r2, [r1, #0]
pid_add = 0;
800085c: 6005 str r5, [r0, #0]
vel_counter++;
800085e: 4842 ldr r0, [pc, #264] @ (8000968 <HAL_TIM_PeriodElapsedCallback+0x184>)
8000860: 7802 ldrb r2, [r0, #0]
8000862: 3201 adds r2, #1
8000864: b2d2 uxtb r2, r2
8000866: 7002 strb r2, [r0, #0]
if (vel_counter >= 20)
8000868: 2a13 cmp r2, #19
800086a: d907 bls.n 800087c <HAL_TIM_PeriodElapsedCallback+0x98>
velocity = total_count - vel_prev_pos;
800086c: 4d3f ldr r5, [pc, #252] @ (800096c <HAL_TIM_PeriodElapsedCallback+0x188>)
800086e: 4e40 ldr r6, [pc, #256] @ (8000970 <HAL_TIM_PeriodElapsedCallback+0x18c>)
8000870: 682a ldr r2, [r5, #0]
vel_prev_pos = total_count;
8000872: 602b str r3, [r5, #0]
velocity = total_count - vel_prev_pos;
8000874: 1a9a subs r2, r3, r2
8000876: 6032 str r2, [r6, #0]
vel_counter = 0;
8000878: 2200 movs r2, #0
800087a: 7002 strb r2, [r0, #0]
if (total_count != last_moved_pos)
800087c: 4a3d ldr r2, [pc, #244] @ (8000974 <HAL_TIM_PeriodElapsedCallback+0x190>)
800087e: 483e ldr r0, [pc, #248] @ (8000978 <HAL_TIM_PeriodElapsedCallback+0x194>)
8000880: 6815 ldr r5, [r2, #0]
8000882: 429d cmp r5, r3
8000884: d031 beq.n 80008ea <HAL_TIM_PeriodElapsedCallback+0x106>
last_moved_pos = total_count;
8000886: 6013 str r3, [r2, #0]
still_counter = 0;
8000888: 2200 movs r2, #0
still_counter++;
800088a: 8002 strh r2, [r0, #0]
int32_t error = target_count - total_count;
800088c: 680d ldr r5, [r1, #0]
htim1.Instance->CCR1 = PWM;
800088e: 6824 ldr r4, [r4, #0]
int32_t error = target_count - total_count;
8000890: 1aed subs r5, r5, r3
int32_t brake_distance = velocity * brake_time_tenths / 10;
8000892: 4b3a ldr r3, [pc, #232] @ (800097c <HAL_TIM_PeriodElapsedCallback+0x198>)
8000894: 4e3a ldr r6, [pc, #232] @ (8000980 <HAL_TIM_PeriodElapsedCallback+0x19c>)
8000896: 681b ldr r3, [r3, #0]
if (error > FEED_POSITION_TOLERANCE && (is_stopped || error > brake_distance))
8000898: 2d0a cmp r5, #10
800089a: dd2e ble.n 80008fa <HAL_TIM_PeriodElapsedCallback+0x116>
800089c: 2a28 cmp r2, #40 @ 0x28
800089e: d807 bhi.n 80008b0 <HAL_TIM_PeriodElapsedCallback+0xcc>
int32_t brake_distance = velocity * brake_time_tenths / 10;
80008a0: 4a33 ldr r2, [pc, #204] @ (8000970 <HAL_TIM_PeriodElapsedCallback+0x18c>)
80008a2: 210a movs r1, #10
80008a4: 6810 ldr r0, [r2, #0]
80008a6: 4358 muls r0, r3
80008a8: f7ff fccc bl 8000244 <__divsi3>
if (error > FEED_POSITION_TOLERANCE && (is_stopped || error > brake_distance))
80008ac: 4285 cmp r5, r0
80008ae: dd2d ble.n 800090c <HAL_TIM_PeriodElapsedCallback+0x128>
htim1.Instance->CCR1 = PWM;
80008b0: 2396 movs r3, #150 @ 0x96
htim1.Instance->CCR2 = 0;
80008b2: 2200 movs r2, #0
htim1.Instance->CCR1 = PWM;
80008b4: 011b lsls r3, r3, #4
80008b6: 6363 str r3, [r4, #52] @ 0x34
htim1.Instance->CCR2 = 0;
80008b8: 63a2 str r2, [r4, #56] @ 0x38
debug_pid_output = -PWM_MAX;
80008ba: 8033 strh r3, [r6, #0]
}
80008bc: bdf8 pop {r3, r4, r5, r6, r7, pc}
else if ((encoder_previous < CNT_LIMIT_ZONE) && (count > CNT_MAX-CNT_LIMIT_ZONE)) // negative turnaround
80008be: 45bc cmp ip, r7
80008c0: d2a7 bcs.n 8000812 <HAL_TIM_PeriodElapsedCallback+0x2e>
80008c2: 42b2 cmp r2, r6
80008c4: d9a5 bls.n 8000812 <HAL_TIM_PeriodElapsedCallback+0x2e>
encoder_count_extra --;
80008c6: 3b01 subs r3, #1
80008c8: 6003 str r3, [r0, #0]
80008ca: e7a2 b.n 8000812 <HAL_TIM_PeriodElapsedCallback+0x2e>
else if (total_count < -POSITION_OVERFLOW_THRESHOLD)
80008cc: 27c0 movs r7, #192 @ 0xc0
80008ce: 063f lsls r7, r7, #24
80008d0: 42bb cmp r3, r7
80008d2: dcbb bgt.n 800084c <HAL_TIM_PeriodElapsedCallback+0x68>
total_count += adjustment;
80008d4: 4f2b ldr r7, [pc, #172] @ (8000984 <HAL_TIM_PeriodElapsedCallback+0x1a0>)
80008d6: 19db adds r3, r3, r7
80008d8: 6033 str r3, [r6, #0]
feed_target_position += adjustment;
80008da: 4e1f ldr r6, [pc, #124] @ (8000958 <HAL_TIM_PeriodElapsedCallback+0x174>)
target_count += adjustment;
80008dc: 19c0 adds r0, r0, r7
80008de: 6008 str r0, [r1, #0]
feed_target_position += adjustment;
80008e0: 6830 ldr r0, [r6, #0]
80008e2: 19c0 adds r0, r0, r7
80008e4: 6030 str r0, [r6, #0]
encoder_count_extra += (adjustment / 65536);
80008e6: 4828 ldr r0, [pc, #160] @ (8000988 <HAL_TIM_PeriodElapsedCallback+0x1a4>)
80008e8: e7ab b.n 8000842 <HAL_TIM_PeriodElapsedCallback+0x5e>
else if (still_counter < 1000)
80008ea: 25fa movs r5, #250 @ 0xfa
80008ec: 8802 ldrh r2, [r0, #0]
80008ee: 00ad lsls r5, r5, #2
80008f0: 42aa cmp r2, r5
80008f2: d2cb bcs.n 800088c <HAL_TIM_PeriodElapsedCallback+0xa8>
still_counter++;
80008f4: 3201 adds r2, #1
80008f6: b292 uxth r2, r2
80008f8: e7c7 b.n 800088a <HAL_TIM_PeriodElapsedCallback+0xa6>
else if (error < -FEED_POSITION_TOLERANCE)
80008fa: 350a adds r5, #10
80008fc: da06 bge.n 800090c <HAL_TIM_PeriodElapsedCallback+0x128>
htim1.Instance->CCR1 = 0;
80008fe: 2300 movs r3, #0
8000900: 6363 str r3, [r4, #52] @ 0x34
htim1.Instance->CCR2 = PWM;
8000902: 2396 movs r3, #150 @ 0x96
8000904: 011b lsls r3, r3, #4
8000906: 63a3 str r3, [r4, #56] @ 0x38
debug_pid_output = -PWM_MAX;
8000908: 4b20 ldr r3, [pc, #128] @ (800098c <HAL_TIM_PeriodElapsedCallback+0x1a8>)
800090a: e7d6 b.n 80008ba <HAL_TIM_PeriodElapsedCallback+0xd6>
htim1.Instance->CCR1 = PWM_MAX;
800090c: 2396 movs r3, #150 @ 0x96
800090e: 011b lsls r3, r3, #4
8000910: 6363 str r3, [r4, #52] @ 0x34
htim1.Instance->CCR2 = PWM_MAX;
8000912: 63a3 str r3, [r4, #56] @ 0x38
debug_pid_output = 0;
8000914: 2300 movs r3, #0
8000916: e7d0 b.n 80008ba <HAL_TIM_PeriodElapsedCallback+0xd6>
if (htim == &htim1) return; // PWM timer
8000918: 42a0 cmp r0, r4
800091a: d0cf beq.n 80008bc <HAL_TIM_PeriodElapsedCallback+0xd8>
if (htim == &htim16) //SW1 timer
800091c: 4b1c ldr r3, [pc, #112] @ (8000990 <HAL_TIM_PeriodElapsedCallback+0x1ac>)
800091e: 4298 cmp r0, r3
8000920: d103 bne.n 800092a <HAL_TIM_PeriodElapsedCallback+0x146>
sw1_pressed = 0;
8000922: 4b1c ldr r3, [pc, #112] @ (8000994 <HAL_TIM_PeriodElapsedCallback+0x1b0>)
sw2_pressed = 0;
8000924: 2200 movs r2, #0
8000926: 701a strb r2, [r3, #0]
8000928: e7c8 b.n 80008bc <HAL_TIM_PeriodElapsedCallback+0xd8>
else if (htim == &htim17) //SW2 timer
800092a: 4b1b ldr r3, [pc, #108] @ (8000998 <HAL_TIM_PeriodElapsedCallback+0x1b4>)
800092c: 4298 cmp r0, r3
800092e: d1c5 bne.n 80008bc <HAL_TIM_PeriodElapsedCallback+0xd8>
sw2_pressed = 0;
8000930: 4b1a ldr r3, [pc, #104] @ (800099c <HAL_TIM_PeriodElapsedCallback+0x1b8>)
8000932: e7f7 b.n 8000924 <HAL_TIM_PeriodElapsedCallback+0x140>
8000934: 20001218 .word 0x20001218
8000938: 200012b0 .word 0x200012b0
800093c: 20001264 .word 0x20001264
8000940: 20000f94 .word 0x20000f94
8000944: 20000f98 .word 0x20000f98
8000948: 0000fc17 .word 0x0000fc17
800094c: 20000154 .word 0x20000154
8000950: 20000150 .word 0x20000150
8000954: e0000001 .word 0xe0000001
8000958: 20000104 .word 0x20000104
800095c: ffffe001 .word 0xffffe001
8000960: 200000e4 .word 0x200000e4
8000964: 20000124 .word 0x20000124
8000968: 2000005c .word 0x2000005c
800096c: 20000058 .word 0x20000058
8000970: 20000054 .word 0x20000054
8000974: 20000050 .word 0x20000050
8000978: 2000004c .word 0x2000004c
800097c: 20000004 .word 0x20000004
8000980: 2000007c .word 0x2000007c
8000984: 1fffffff .word 0x1fffffff
8000988: 00001fff .word 0x00001fff
800098c: fffff6a0 .word 0xfffff6a0
8000990: 200011cc .word 0x200011cc
8000994: 20000f9d .word 0x20000f9d
8000998: 20001180 .word 0x20001180
800099c: 20000f9c .word 0x20000f9c
080009a0 <HAL_GPIO_EXTI_Falling_Callback>:
if(GPIO_Pin == SW1_Pin) // SW1 (lower button)
80009a0: 2380 movs r3, #128 @ 0x80
{
80009a2: b510 push {r4, lr}
if(GPIO_Pin == SW1_Pin) // SW1 (lower button)
80009a4: 009b lsls r3, r3, #2
80009a6: 4298 cmp r0, r3
80009a8: d105 bne.n 80009b6 <HAL_GPIO_EXTI_Falling_Callback+0x16>
if (!sw1_pressed)
80009aa: 4c0b ldr r4, [pc, #44] @ (80009d8 <HAL_GPIO_EXTI_Falling_Callback+0x38>)
htim16.Instance->CNT = 0;
80009ac: 480b ldr r0, [pc, #44] @ (80009dc <HAL_GPIO_EXTI_Falling_Callback+0x3c>)
if (!sw1_pressed)
80009ae: 7823 ldrb r3, [r4, #0]
80009b0: 2b00 cmp r3, #0
80009b2: d009 beq.n 80009c8 <HAL_GPIO_EXTI_Falling_Callback+0x28>
}
80009b4: bd10 pop {r4, pc}
else if (GPIO_Pin == SW2_Pin) // SW2 (upper button)
80009b6: 2380 movs r3, #128 @ 0x80
80009b8: 005b lsls r3, r3, #1
80009ba: 4298 cmp r0, r3
80009bc: d1fa bne.n 80009b4 <HAL_GPIO_EXTI_Falling_Callback+0x14>
if (!sw2_pressed)
80009be: 4c08 ldr r4, [pc, #32] @ (80009e0 <HAL_GPIO_EXTI_Falling_Callback+0x40>)
80009c0: 7823 ldrb r3, [r4, #0]
80009c2: 2b00 cmp r3, #0
80009c4: d1f6 bne.n 80009b4 <HAL_GPIO_EXTI_Falling_Callback+0x14>
htim17.Instance->CNT = 0;
80009c6: 4807 ldr r0, [pc, #28] @ (80009e4 <HAL_GPIO_EXTI_Falling_Callback+0x44>)
80009c8: 6802 ldr r2, [r0, #0]
80009ca: 6253 str r3, [r2, #36] @ 0x24
HAL_TIM_Base_Start_IT(&htim17);
80009cc: f003 f8ac bl 8003b28 <HAL_TIM_Base_Start_IT>
sw2_pressed = 1;
80009d0: 2301 movs r3, #1
80009d2: 7023 strb r3, [r4, #0]
}
80009d4: e7ee b.n 80009b4 <HAL_GPIO_EXTI_Falling_Callback+0x14>
80009d6: 46c0 nop @ (mov r8, r8)
80009d8: 20000f9d .word 0x20000f9d
80009dc: 200011cc .word 0x200011cc
80009e0: 20000f9c .word 0x20000f9c
80009e4: 20001180 .word 0x20001180
080009e8 <HAL_UARTEx_RxEventCallback>:
{
80009e8: b570 push {r4, r5, r6, lr}
80009ea: 000d movs r5, r1
if (Size > 64) return; // todo error handling
80009ec: 2940 cmp r1, #64 @ 0x40
80009ee: d822 bhi.n 8000a36 <HAL_UARTEx_RxEventCallback+0x4e>
rx_msg_count++;
80009f0: 2400 movs r4, #0
80009f2: 4a13 ldr r2, [pc, #76] @ (8000a40 <HAL_UARTEx_RxEventCallback+0x58>)
if (msg_buf_empty[i])
80009f4: 4e13 ldr r6, [pc, #76] @ (8000a44 <HAL_UARTEx_RxEventCallback+0x5c>)
rx_msg_count++;
80009f6: 8813 ldrh r3, [r2, #0]
80009f8: 3301 adds r3, #1
80009fa: b29b uxth r3, r3
80009fc: 8013 strh r3, [r2, #0]
if (msg_buf_empty[i])
80009fe: 5d33 ldrb r3, [r6, r4]
8000a00: 2b00 cmp r3, #0
8000a02: d019 beq.n 8000a38 <HAL_UARTEx_RxEventCallback+0x50>
memcpy(msg_buf[i], DMA_buffer, Size);
8000a04: 4b10 ldr r3, [pc, #64] @ (8000a48 <HAL_UARTEx_RxEventCallback+0x60>)
8000a06: 01a0 lsls r0, r4, #6
8000a08: 002a movs r2, r5
8000a0a: 18c0 adds r0, r0, r3
8000a0c: 490f ldr r1, [pc, #60] @ (8000a4c <HAL_UARTEx_RxEventCallback+0x64>)
8000a0e: f004 fbe9 bl 80051e4 <memcpy>
msg_buf_size[i] = Size;
8000a12: 4b0f ldr r3, [pc, #60] @ (8000a50 <HAL_UARTEx_RxEventCallback+0x68>)
8000a14: b2ed uxtb r5, r5
8000a16: 551d strb r5, [r3, r4]
msg_buf_empty[i] = 0;
8000a18: 2300 movs r3, #0
8000a1a: 5533 strb r3, [r6, r4]
HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
8000a1c: 4c0d ldr r4, [pc, #52] @ (8000a54 <HAL_UARTEx_RxEventCallback+0x6c>)
8000a1e: 2240 movs r2, #64 @ 0x40
8000a20: 0020 movs r0, r4
8000a22: 490a ldr r1, [pc, #40] @ (8000a4c <HAL_UARTEx_RxEventCallback+0x64>)
8000a24: f004 fb72 bl 800510c <HAL_UARTEx_ReceiveToIdle_DMA>
__HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT);
8000a28: 2104 movs r1, #4
8000a2a: 3404 adds r4, #4
8000a2c: 6fe3 ldr r3, [r4, #124] @ 0x7c
8000a2e: 681a ldr r2, [r3, #0]
8000a30: 6813 ldr r3, [r2, #0]
8000a32: 438b bics r3, r1
8000a34: 6013 str r3, [r2, #0]
}
8000a36: bd70 pop {r4, r5, r6, pc}
for (uint8_t i = 0; i < MSG_BUF_COUNT; i++)
8000a38: 3401 adds r4, #1
8000a3a: 2c36 cmp r4, #54 @ 0x36
8000a3c: d1df bne.n 80009fe <HAL_UARTEx_RxEventCallback+0x16>
8000a3e: e7ed b.n 8000a1c <HAL_UARTEx_RxEventCallback+0x34>
8000a40: 20000158 .word 0x20000158
8000a44: 20000f50 .word 0x20000f50
8000a48: 2000019a .word 0x2000019a
8000a4c: 2000015a .word 0x2000015a
8000a50: 20000f1a .word 0x20000f1a
8000a54: 20001058 .word 0x20001058
08000a58 <HAL_UART_ErrorCallback>:
if (huart->Instance == USART2)
8000a58: 4b0c ldr r3, [pc, #48] @ (8000a8c <HAL_UART_ErrorCallback+0x34>)
8000a5a: 6802 ldr r2, [r0, #0]
{
8000a5c: b510 push {r4, lr}
if (huart->Instance == USART2)
8000a5e: 429a cmp r2, r3
8000a60: d113 bne.n 8000a8a <HAL_UART_ErrorCallback+0x32>
uart_error_count++;
8000a62: 490b ldr r1, [pc, #44] @ (8000a90 <HAL_UART_ErrorCallback+0x38>)
HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
8000a64: 4c0b ldr r4, [pc, #44] @ (8000a94 <HAL_UART_ErrorCallback+0x3c>)
uart_error_count++;
8000a66: 880b ldrh r3, [r1, #0]
HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
8000a68: 0020 movs r0, r4
uart_error_count++;
8000a6a: 3301 adds r3, #1
8000a6c: b29b uxth r3, r3
8000a6e: 800b strh r3, [r1, #0]
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_FEF | UART_CLEAR_NEF | UART_CLEAR_PEF);
8000a70: 230f movs r3, #15
HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
8000a72: 4909 ldr r1, [pc, #36] @ (8000a98 <HAL_UART_ErrorCallback+0x40>)
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_FEF | UART_CLEAR_NEF | UART_CLEAR_PEF);
8000a74: 6213 str r3, [r2, #32]
HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
8000a76: 2240 movs r2, #64 @ 0x40
8000a78: f004 fb48 bl 800510c <HAL_UARTEx_ReceiveToIdle_DMA>
__HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT);
8000a7c: 2104 movs r1, #4
8000a7e: 3404 adds r4, #4
8000a80: 6fe3 ldr r3, [r4, #124] @ 0x7c
8000a82: 681a ldr r2, [r3, #0]
8000a84: 6813 ldr r3, [r2, #0]
8000a86: 438b bics r3, r1
8000a88: 6013 str r3, [r2, #0]
}
8000a8a: bd10 pop {r4, pc}
8000a8c: 40004400 .word 0x40004400
8000a90: 2000007a .word 0x2000007a
8000a94: 20001058 .word 0x20001058
8000a98: 2000015a .word 0x2000015a
08000a9c <set_LED>:
{
8000a9c: b570 push {r4, r5, r6, lr}
8000a9e: 000d movs r5, r1
8000aa0: 0014 movs r4, r2
if (R) R = GPIO_PIN_SET;
8000aa2: 1e43 subs r3, r0, #1
8000aa4: 4198 sbcs r0, r3
if (G) G = GPIO_PIN_SET;
8000aa6: 1e6b subs r3, r5, #1
8000aa8: 419d sbcs r5, r3
if (B) B = GPIO_PIN_SET;
8000aaa: 1e63 subs r3, r4, #1
8000aac: 419c sbcs r4, r3
HAL_GPIO_WritePin(LED_R_GPIO_Port,LED_R_Pin,R);
8000aae: b2c2 uxtb r2, r0
8000ab0: 2108 movs r1, #8
8000ab2: 4807 ldr r0, [pc, #28] @ (8000ad0 <set_LED+0x34>)
8000ab4: f002 fc2e bl 8003314 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LED_G_GPIO_Port,LED_G_Pin,G);
8000ab8: b2ea uxtb r2, r5
8000aba: 2120 movs r1, #32
8000abc: 4804 ldr r0, [pc, #16] @ (8000ad0 <set_LED+0x34>)
8000abe: f002 fc29 bl 8003314 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(LED_B_GPIO_Port,LED_B_Pin,B);
8000ac2: 2110 movs r1, #16
8000ac4: 4802 ldr r0, [pc, #8] @ (8000ad0 <set_LED+0x34>)
8000ac6: b2e2 uxtb r2, r4
8000ac8: f002 fc24 bl 8003314 <HAL_GPIO_WritePin>
}
8000acc: bd70 pop {r4, r5, r6, pc}
8000ace: 46c0 nop @ (mov r8, r8)
8000ad0: 50000400 .word 0x50000400
08000ad4 <rs485_transmit>:
{
8000ad4: b570 push {r4, r5, r6, lr}
8000ad6: 0005 movs r5, r0
HAL_Delay(1);
8000ad8: 2001 movs r0, #1
{
8000ada: 000e movs r6, r1
HAL_Delay(1);
8000adc: f001 ff06 bl 80028ec <HAL_Delay>
HAL_GPIO_WritePin(USART2_NRE_GPIO_Port, USART2_NRE_Pin, GPIO_PIN_SET); // NRE high = receiver off
8000ae0: 2201 movs r2, #1
8000ae2: 20a0 movs r0, #160 @ 0xa0
8000ae4: 0011 movs r1, r2
8000ae6: 05c0 lsls r0, r0, #23
8000ae8: f002 fc14 bl 8003314 <HAL_GPIO_WritePin>
HAL_UART_Transmit(&huart2, data, len, 100);
8000aec: 4c0c ldr r4, [pc, #48] @ (8000b20 <rs485_transmit+0x4c>)
8000aee: 2364 movs r3, #100 @ 0x64
8000af0: 0032 movs r2, r6
8000af2: 0029 movs r1, r5
8000af4: 0020 movs r0, r4
8000af6: f004 f8de bl 8004cb6 <HAL_UART_Transmit>
HAL_GPIO_WritePin(USART2_NRE_GPIO_Port, USART2_NRE_Pin, GPIO_PIN_RESET); // NRE low = receiver on
8000afa: 20a0 movs r0, #160 @ 0xa0
8000afc: 2200 movs r2, #0
8000afe: 2101 movs r1, #1
8000b00: 05c0 lsls r0, r0, #23
8000b02: f002 fc07 bl 8003314 <HAL_GPIO_WritePin>
HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
8000b06: 2240 movs r2, #64 @ 0x40
8000b08: 0020 movs r0, r4
8000b0a: 4906 ldr r1, [pc, #24] @ (8000b24 <rs485_transmit+0x50>)
8000b0c: f004 fafe bl 800510c <HAL_UARTEx_ReceiveToIdle_DMA>
__HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT);
8000b10: 2104 movs r1, #4
8000b12: 3404 adds r4, #4
8000b14: 6fe3 ldr r3, [r4, #124] @ 0x7c
8000b16: 681a ldr r2, [r3, #0]
8000b18: 6813 ldr r3, [r2, #0]
8000b1a: 438b bics r3, r1
8000b1c: 6013 str r3, [r2, #0]
}
8000b1e: bd70 pop {r4, r5, r6, pc}
8000b20: 20001058 .word 0x20001058
8000b24: 2000015a .word 0x2000015a
08000b28 <comp_crc_header>:
{
8000b28: b570 push {r4, r5, r6, lr}
8000b2a: 000d movs r5, r1
8000b2c: 0004 movs r4, r0
CRC8_107_add(lcrc,lresponse->header.toAddress);
8000b2e: 7809 ldrb r1, [r1, #0]
8000b30: f7ff fe0c bl 800074c <CRC8_107_add>
CRC8_107_add(lcrc,lresponse->header.fromAddress);
8000b34: 7869 ldrb r1, [r5, #1]
8000b36: 0020 movs r0, r4
8000b38: f7ff fe08 bl 800074c <CRC8_107_add>
CRC8_107_add(lcrc,lresponse->header.packetId);
8000b3c: 78a9 ldrb r1, [r5, #2]
8000b3e: 0020 movs r0, r4
8000b40: f7ff fe04 bl 800074c <CRC8_107_add>
CRC8_107_add(lcrc,lresponse->header.payloadLength);
8000b44: 78e9 ldrb r1, [r5, #3]
8000b46: 0020 movs r0, r4
8000b48: f7ff fe00 bl 800074c <CRC8_107_add>
}
8000b4c: bd70 pop {r4, r5, r6, pc}
...
08000b50 <peel_ramp_update>:
{
8000b50: b5f8 push {r3, r4, r5, r6, r7, lr}
uint32_t now = HAL_GetTick();
8000b52: f001 fec5 bl 80028e0 <HAL_GetTick>
uint32_t dt = now - peel_last_ramp_time;
8000b56: 4b1d ldr r3, [pc, #116] @ (8000bcc <peel_ramp_update+0x7c>)
8000b58: 681a ldr r2, [r3, #0]
8000b5a: 1a81 subs r1, r0, r2
if (dt == 0) return;
8000b5c: 4290 cmp r0, r2
8000b5e: d024 beq.n 8000baa <peel_ramp_update+0x5a>
if (peel_current_pwm == peel_target_pwm) return;
8000b60: 4e1b ldr r6, [pc, #108] @ (8000bd0 <peel_ramp_update+0x80>)
peel_last_ramp_time = now;
8000b62: 6018 str r0, [r3, #0]
if (peel_current_pwm == peel_target_pwm) return;
8000b64: 2300 movs r3, #0
8000b66: 5ef7 ldrsh r7, [r6, r3]
8000b68: 4b1a ldr r3, [pc, #104] @ (8000bd4 <peel_ramp_update+0x84>)
8000b6a: 2400 movs r4, #0
8000b6c: 5f1c ldrsh r4, [r3, r4]
8000b6e: 42a7 cmp r7, r4
8000b70: d01b beq.n 8000baa <peel_ramp_update+0x5a>
int16_t step = (int16_t)((int32_t)PWM_MAX * dt / PEEL_RAMP_TIME_MS);
8000b72: 2096 movs r0, #150 @ 0x96
8000b74: 0100 lsls r0, r0, #4
8000b76: 4348 muls r0, r1
8000b78: 2164 movs r1, #100 @ 0x64
8000b7a: f7ff fad9 bl 8000130 <__udivsi3>
8000b7e: 1c03 adds r3, r0, #0
if (step < 1) step = 1;
8000b80: b200 sxth r0, r0
peel_current_pwm += step;
8000b82: b2bd uxth r5, r7
if (step < 1) step = 1;
8000b84: 2800 cmp r0, #0
8000b86: dc00 bgt.n 8000b8a <peel_ramp_update+0x3a>
8000b88: 2301 movs r3, #1
peel_current_pwm += step;
8000b8a: b29b uxth r3, r3
if (peel_target_pwm > peel_current_pwm)
8000b8c: 42a7 cmp r7, r4
8000b8e: da0d bge.n 8000bac <peel_ramp_update+0x5c>
peel_current_pwm += step;
8000b90: 18eb adds r3, r5, r3
8000b92: b21b sxth r3, r3
if (peel_current_pwm > peel_target_pwm)
8000b94: 429c cmp r4, r3
8000b96: db0d blt.n 8000bb4 <peel_ramp_update+0x64>
if (peel_current_pwm < peel_target_pwm)
8000b98: 001c movs r4, r3
peel_current_pwm = peel_target_pwm;
8000b9a: 8033 strh r3, [r6, #0]
htim1.Instance->CCR3 = peel_current_pwm;
8000b9c: 4b0e ldr r3, [pc, #56] @ (8000bd8 <peel_ramp_update+0x88>)
8000b9e: 681b ldr r3, [r3, #0]
if (peel_current_pwm > 0)
8000ba0: 2c00 cmp r4, #0
8000ba2: dd09 ble.n 8000bb8 <peel_ramp_update+0x68>
htim1.Instance->CCR4 = 0;
8000ba4: 2200 movs r2, #0
htim1.Instance->CCR3 = peel_current_pwm;
8000ba6: 63dc str r4, [r3, #60] @ 0x3c
htim1.Instance->CCR4 = 0;
8000ba8: 641a str r2, [r3, #64] @ 0x40
}
8000baa: bdf8 pop {r3, r4, r5, r6, r7, pc}
peel_current_pwm -= step;
8000bac: 1aeb subs r3, r5, r3
8000bae: b21b sxth r3, r3
if (peel_current_pwm < peel_target_pwm)
8000bb0: 429c cmp r4, r3
8000bb2: ddf1 ble.n 8000b98 <peel_ramp_update+0x48>
8000bb4: 0023 movs r3, r4
8000bb6: e7f0 b.n 8000b9a <peel_ramp_update+0x4a>
else if (peel_current_pwm < 0)
8000bb8: 2c00 cmp r4, #0
8000bba: d004 beq.n 8000bc6 <peel_ramp_update+0x76>
htim1.Instance->CCR3 = 0;
8000bbc: 2200 movs r2, #0
htim1.Instance->CCR4 = -peel_current_pwm;
8000bbe: 4264 negs r4, r4
htim1.Instance->CCR3 = 0;
8000bc0: 63da str r2, [r3, #60] @ 0x3c
htim1.Instance->CCR4 = 0;
8000bc2: 641c str r4, [r3, #64] @ 0x40
8000bc4: e7f1 b.n 8000baa <peel_ramp_update+0x5a>
htim1.Instance->CCR3 = 0;
8000bc6: 63dc str r4, [r3, #60] @ 0x3c
8000bc8: e7fb b.n 8000bc2 <peel_ramp_update+0x72>
8000bca: 46c0 nop @ (mov r8, r8)
8000bcc: 200000f8 .word 0x200000f8
8000bd0: 200000fc .word 0x200000fc
8000bd4: 200000fe .word 0x200000fe
8000bd8: 200012b0 .word 0x200012b0
08000bdc <drive_continuous>:
target_count = total_count + 10000;
8000bdc: 4b05 ldr r3, [pc, #20] @ (8000bf4 <drive_continuous+0x18>)
8000bde: 681a ldr r2, [r3, #0]
target_count = total_count - 10000;
8000be0: 4b05 ldr r3, [pc, #20] @ (8000bf8 <drive_continuous+0x1c>)
8000be2: 18d3 adds r3, r2, r3
if (forward)
8000be4: 2800 cmp r0, #0
8000be6: d001 beq.n 8000bec <drive_continuous+0x10>
target_count = total_count + 10000;
8000be8: 4b04 ldr r3, [pc, #16] @ (8000bfc <drive_continuous+0x20>)
8000bea: 18d3 adds r3, r2, r3
8000bec: 4a04 ldr r2, [pc, #16] @ (8000c00 <drive_continuous+0x24>)
}
8000bee: 6013 str r3, [r2, #0]
8000bf0: 4770 bx lr
8000bf2: 46c0 nop @ (mov r8, r8)
8000bf4: 20000154 .word 0x20000154
8000bf8: ffffd8f0 .word 0xffffd8f0
8000bfc: 00002710 .word 0x00002710
8000c00: 20000150 .word 0x20000150
08000c04 <halt_all>:
htim1.Instance->CCR1 = PWM_MAX;
8000c04: 4b09 ldr r3, [pc, #36] @ (8000c2c <halt_all+0x28>)
peel_target_pwm = 0;
8000c06: 490a ldr r1, [pc, #40] @ (8000c30 <halt_all+0x2c>)
htim1.Instance->CCR1 = PWM_MAX;
8000c08: 681a ldr r2, [r3, #0]
8000c0a: 2396 movs r3, #150 @ 0x96
8000c0c: 011b lsls r3, r3, #4
8000c0e: 6353 str r3, [r2, #52] @ 0x34
htim1.Instance->CCR2 = PWM_MAX;
8000c10: 6393 str r3, [r2, #56] @ 0x38
peel_target_pwm = 0;
8000c12: 2300 movs r3, #0
8000c14: 800b strh r3, [r1, #0]
peel_current_pwm = 0;
8000c16: 4907 ldr r1, [pc, #28] @ (8000c34 <halt_all+0x30>)
htim1.Instance->CCR3 = 0;
8000c18: 63d3 str r3, [r2, #60] @ 0x3c
peel_current_pwm = 0;
8000c1a: 800b strh r3, [r1, #0]
target_count = total_count;
8000c1c: 4906 ldr r1, [pc, #24] @ (8000c38 <halt_all+0x34>)
htim1.Instance->CCR4 = 0;
8000c1e: 6413 str r3, [r2, #64] @ 0x40
target_count = total_count;
8000c20: 6809 ldr r1, [r1, #0]
8000c22: 4a06 ldr r2, [pc, #24] @ (8000c3c <halt_all+0x38>)
8000c24: 6011 str r1, [r2, #0]
pid_add = 0;
8000c26: 4a06 ldr r2, [pc, #24] @ (8000c40 <halt_all+0x3c>)
8000c28: 6013 str r3, [r2, #0]
}
8000c2a: 4770 bx lr
8000c2c: 200012b0 .word 0x200012b0
8000c30: 200000fe .word 0x200000fe
8000c34: 200000fc .word 0x200000fc
8000c38: 20000154 .word 0x20000154
8000c3c: 20000150 .word 0x20000150
8000c40: 20000124 .word 0x20000124
08000c44 <identify_feeder>:
{
8000c44: b510 push {r4, lr}
8000c46: 2403 movs r4, #3
set_LED(1, 1, 1);
8000c48: 2201 movs r2, #1
8000c4a: 0011 movs r1, r2
8000c4c: 0010 movs r0, r2
8000c4e: f7ff ff25 bl 8000a9c <set_LED>
HAL_Delay(300);
8000c52: 2096 movs r0, #150 @ 0x96
8000c54: 0040 lsls r0, r0, #1
8000c56: f001 fe49 bl 80028ec <HAL_Delay>
set_LED(0, 0, 0);
8000c5a: 2200 movs r2, #0
8000c5c: 0010 movs r0, r2
8000c5e: 0011 movs r1, r2
8000c60: f7ff ff1c bl 8000a9c <set_LED>
HAL_Delay(300);
8000c64: 2096 movs r0, #150 @ 0x96
for (int i = 0; i < 3; i++)
8000c66: 3c01 subs r4, #1
HAL_Delay(300);
8000c68: 0040 lsls r0, r0, #1
8000c6a: f001 fe3f bl 80028ec <HAL_Delay>
for (int i = 0; i < 3; i++)
8000c6e: 2c00 cmp r4, #0
8000c70: d1ea bne.n 8000c48 <identify_feeder+0x4>
}
8000c72: bd10 pop {r4, pc}
08000c74 <show_version>:
set_LED(0, 1, 0);
8000c74: 2200 movs r2, #0
{
8000c76: b510 push {r4, lr}
set_LED(0, 1, 0);
8000c78: 0010 movs r0, r2
8000c7a: 2101 movs r1, #1
8000c7c: f7ff ff0e bl 8000a9c <set_LED>
HAL_Delay(250);
8000c80: 20fa movs r0, #250 @ 0xfa
8000c82: f001 fe33 bl 80028ec <HAL_Delay>
set_LED(0, 0, 0);
8000c86: 2200 movs r2, #0
8000c88: 0010 movs r0, r2
8000c8a: 0011 movs r1, r2
8000c8c: f7ff ff06 bl 8000a9c <set_LED>
HAL_Delay(250);
8000c90: 20fa movs r0, #250 @ 0xfa
8000c92: f001 fe2b bl 80028ec <HAL_Delay>
}
8000c96: bd10 pop {r4, pc}
08000c98 <start_feed>:
{
8000c98: b5f0 push {r4, r5, r6, r7, lr}
if (feed_state != FEED_STATE_IDLE)
8000c9a: 4b2a ldr r3, [pc, #168] @ (8000d44 <start_feed+0xac>)
{
8000c9c: b085 sub sp, #20
if (feed_state != FEED_STATE_IDLE)
8000c9e: 9301 str r3, [sp, #4]
8000ca0: 781b ldrb r3, [r3, #0]
{
8000ca2: 0004 movs r4, r0
8000ca4: 9102 str r1, [sp, #8]
if (feed_state != FEED_STATE_IDLE)
8000ca6: b2da uxtb r2, r3
8000ca8: 2b00 cmp r3, #0
8000caa: d13c bne.n 8000d26 <start_feed+0x8e>
feed_in_progress = 1;
8000cac: 2501 movs r5, #1
feed_distance_tenths = distance_tenths;
8000cae: 4b26 ldr r3, [pc, #152] @ (8000d48 <start_feed+0xb0>)
8000cb0: 8018 strh r0, [r3, #0]
feed_direction = forward;
8000cb2: 4b26 ldr r3, [pc, #152] @ (8000d4c <start_feed+0xb4>)
set_LED(1, 1, 1); // White during feed
8000cb4: 0028 movs r0, r5
feed_direction = forward;
8000cb6: 7019 strb r1, [r3, #0]
feed_retry_count = 0;
8000cb8: 4b25 ldr r3, [pc, #148] @ (8000d50 <start_feed+0xb8>)
set_LED(1, 1, 1); // White during feed
8000cba: 0029 movs r1, r5
feed_retry_count = 0;
8000cbc: 701a strb r2, [r3, #0]
feed_in_progress = 1;
8000cbe: 4b25 ldr r3, [pc, #148] @ (8000d54 <start_feed+0xbc>)
8000cc0: 701d strb r5, [r3, #0]
last_feed_status = STATUS_OK;
8000cc2: 4b25 ldr r3, [pc, #148] @ (8000d58 <start_feed+0xc0>)
8000cc4: 701a strb r2, [r3, #0]
set_LED(1, 1, 1); // White during feed
8000cc6: 002a movs r2, r5
8000cc8: f7ff fee8 bl 8000a9c <set_LED>
if (forward)
8000ccc: 4b23 ldr r3, [pc, #140] @ (8000d5c <start_feed+0xc4>)
8000cce: 4f24 ldr r7, [pc, #144] @ (8000d60 <start_feed+0xc8>)
8000cd0: 9303 str r3, [sp, #12]
8000cd2: 9b02 ldr r3, [sp, #8]
8000cd4: 4e23 ldr r6, [pc, #140] @ (8000d64 <start_feed+0xcc>)
8000cd6: 2b00 cmp r3, #0
8000cd8: d027 beq.n 8000d2a <start_feed+0x92>
feed_state = FEED_STATE_PEEL_FORWARD;
8000cda: 9b01 ldr r3, [sp, #4]
8000cdc: 701d strb r5, [r3, #0]
feed_state_start_time = HAL_GetTick();
8000cde: f001 fdff bl 80028e0 <HAL_GetTick>
feed_state_duration = distance_tenths * PEEL_TIME_PER_TENTH_MM;
8000ce2: 2312 movs r3, #18
8000ce4: 4363 muls r3, r4
8000ce6: 6033 str r3, [r6, #0]
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
8000ce8: 2396 movs r3, #150 @ 0x96
8000cea: 9a03 ldr r2, [sp, #12]
8000cec: 011b lsls r3, r3, #4
8000cee: 8013 strh r3, [r2, #0]
feed_state_start_time = HAL_GetTick();
8000cf0: 6038 str r0, [r7, #0]
feed_timeout_time = HAL_GetTick() + (distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
8000cf2: f001 fdf5 bl 80028e0 <HAL_GetTick>
8000cf6: 2364 movs r3, #100 @ 0x64
8000cf8: 4363 muls r3, r4
8000cfa: 33f5 adds r3, #245 @ 0xf5
8000cfc: 4a1a ldr r2, [pc, #104] @ (8000d68 <start_feed+0xd0>)
8000cfe: 33ff adds r3, #255 @ 0xff
8000d00: 181b adds r3, r3, r0
8000d02: 6013 str r3, [r2, #0]
int64_t temp = ((int64_t)tenths * 100 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV;
8000d04: 0020 movs r0, r4
8000d06: 2300 movs r3, #0
8000d08: 4a18 ldr r2, [pc, #96] @ (8000d6c <start_feed+0xd4>)
8000d0a: 17e1 asrs r1, r4, #31
8000d0c: f7ff fbaa bl 8000464 <__aeabi_lmul>
8000d10: 2300 movs r3, #0
8000d12: 4a17 ldr r2, [pc, #92] @ (8000d70 <start_feed+0xd8>)
8000d14: f7ff fb82 bl 800041c <__aeabi_ldivmod>
feed_target_position = total_count + tenths_to_counts(distance_tenths);
8000d18: 4b16 ldr r3, [pc, #88] @ (8000d74 <start_feed+0xdc>)
8000d1a: 681b ldr r3, [r3, #0]
8000d1c: 1818 adds r0, r3, r0
8000d1e: 4b16 ldr r3, [pc, #88] @ (8000d78 <start_feed+0xe0>)
8000d20: 6018 str r0, [r3, #0]
target_count = feed_target_position;
8000d22: 4b16 ldr r3, [pc, #88] @ (8000d7c <start_feed+0xe4>)
8000d24: 6018 str r0, [r3, #0]
}
8000d26: b005 add sp, #20
8000d28: bdf0 pop {r4, r5, r6, r7, pc}
feed_state = FEED_STATE_UNPEEL;
8000d2a: 2303 movs r3, #3
8000d2c: 9a01 ldr r2, [sp, #4]
8000d2e: 7013 strb r3, [r2, #0]
feed_state_start_time = HAL_GetTick();
8000d30: f001 fdd6 bl 80028e0 <HAL_GetTick>
feed_state_duration = distance_tenths * BACKWARDS_PEEL_TIME_PER_TENTH_MM;
8000d34: 231e movs r3, #30
8000d36: 4363 muls r3, r4
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
8000d38: 9a03 ldr r2, [sp, #12]
feed_state_duration = distance_tenths * BACKWARDS_PEEL_TIME_PER_TENTH_MM;
8000d3a: 6033 str r3, [r6, #0]
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
8000d3c: 4b10 ldr r3, [pc, #64] @ (8000d80 <start_feed+0xe8>)
feed_state_start_time = HAL_GetTick();
8000d3e: 6038 str r0, [r7, #0]
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
8000d40: 8013 strh r3, [r2, #0]
}
8000d42: e7f0 b.n 8000d26 <start_feed+0x8e>
8000d44: 20000118 .word 0x20000118
8000d48: 20000108 .word 0x20000108
8000d4c: 20000002 .word 0x20000002
8000d50: 20000100 .word 0x20000100
8000d54: 20000121 .word 0x20000121
8000d58: 20000122 .word 0x20000122
8000d5c: 200000fe .word 0x200000fe
8000d60: 20000114 .word 0x20000114
8000d64: 20000110 .word 0x20000110
8000d68: 2000010c .word 0x2000010c
8000d6c: 002c01a0 .word 0x002c01a0
8000d70: 0001f377 .word 0x0001f377
8000d74: 20000154 .word 0x20000154
8000d78: 20000104 .word 0x20000104
8000d7c: 20000150 .word 0x20000150
8000d80: fffff6a0 .word 0xfffff6a0
08000d84 <feed_state_machine_update>:
{
8000d84: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
if (feed_state == FEED_STATE_IDLE)
8000d86: 4ea6 ldr r6, [pc, #664] @ (8001020 <feed_state_machine_update+0x29c>)
8000d88: 7833 ldrb r3, [r6, #0]
8000d8a: 2b00 cmp r3, #0
8000d8c: d01f beq.n 8000dce <feed_state_machine_update+0x4a>
uint32_t now = HAL_GetTick();
8000d8e: f001 fda7 bl 80028e0 <HAL_GetTick>
uint32_t elapsed = now - feed_state_start_time;
8000d92: 4da4 ldr r5, [pc, #656] @ (8001024 <feed_state_machine_update+0x2a0>)
uint32_t now = HAL_GetTick();
8000d94: 0004 movs r4, r0
uint32_t elapsed = now - feed_state_start_time;
8000d96: 682b ldr r3, [r5, #0]
8000d98: 1ac3 subs r3, r0, r3
switch (feed_state)
8000d9a: 7830 ldrb r0, [r6, #0]
8000d9c: 3801 subs r0, #1
8000d9e: 2808 cmp r0, #8
8000da0: d900 bls.n 8000da4 <feed_state_machine_update+0x20>
8000da2: e135 b.n 8001010 <feed_state_machine_update+0x28c>
8000da4: f7ff f9ba bl 800011c <__gnu_thumb1_case_uhi>
8000da8: 01340009 .word 0x01340009
8000dac: 003a0014 .word 0x003a0014
8000db0: 00c700af .word 0x00c700af
8000db4: 00e500de .word 0x00e500de
8000db8: 00f4 .short 0x00f4
if (elapsed >= feed_state_duration)
8000dba: 4a9b ldr r2, [pc, #620] @ (8001028 <feed_state_machine_update+0x2a4>)
8000dbc: 6812 ldr r2, [r2, #0]
8000dbe: 4293 cmp r3, r2
8000dc0: d305 bcc.n 8000dce <feed_state_machine_update+0x4a>
peel_target_pwm = 0;
8000dc2: 2200 movs r2, #0
8000dc4: 4b99 ldr r3, [pc, #612] @ (800102c <feed_state_machine_update+0x2a8>)
feed_state_start_time = now;
8000dc6: 602c str r4, [r5, #0]
peel_target_pwm = 0;
8000dc8: 801a strh r2, [r3, #0]
feed_state = FEED_STATE_DRIVING;
8000dca: 2304 movs r3, #4
8000dcc: 7033 strb r3, [r6, #0]
}
8000dce: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
if (elapsed >= feed_state_duration)
8000dd0: 4a95 ldr r2, [pc, #596] @ (8001028 <feed_state_machine_update+0x2a4>)
8000dd2: 6812 ldr r2, [r2, #0]
8000dd4: 4293 cmp r3, r2
8000dd6: d3fa bcc.n 8000dce <feed_state_machine_update+0x4a>
peel_target_pwm = 0;
8000dd8: 2200 movs r2, #0
8000dda: 4b94 ldr r3, [pc, #592] @ (800102c <feed_state_machine_update+0x2a8>)
feed_state_start_time = now;
8000ddc: 602c str r4, [r5, #0]
peel_target_pwm = 0;
8000dde: 801a strh r2, [r3, #0]
feed_state = FEED_STATE_DRIVING;
8000de0: 2304 movs r3, #4
8000de2: 7033 strb r3, [r6, #0]
int16_t total_backward = feed_distance_tenths + BACKLASH_COMP_TENTH_MM;
8000de4: 4b92 ldr r3, [pc, #584] @ (8001030 <feed_state_machine_update+0x2ac>)
feed_timeout_time = now + (total_backward * TIMEOUT_TIME_PER_TENTH_MM) + 500;
8000de6: 4a93 ldr r2, [pc, #588] @ (8001034 <feed_state_machine_update+0x2b0>)
int16_t total_backward = feed_distance_tenths + BACKLASH_COMP_TENTH_MM;
8000de8: 8818 ldrh r0, [r3, #0]
feed_timeout_time = now + (total_backward * TIMEOUT_TIME_PER_TENTH_MM) + 500;
8000dea: 2364 movs r3, #100 @ 0x64
int16_t total_backward = feed_distance_tenths + BACKLASH_COMP_TENTH_MM;
8000dec: 300a adds r0, #10
8000dee: b200 sxth r0, r0
feed_timeout_time = now + (total_backward * TIMEOUT_TIME_PER_TENTH_MM) + 500;
8000df0: 4343 muls r3, r0
8000df2: 33f5 adds r3, #245 @ 0xf5
8000df4: 33ff adds r3, #255 @ 0xff
8000df6: 191b adds r3, r3, r4
8000df8: 6013 str r3, [r2, #0]
int64_t temp = ((int64_t)tenths * 100 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV;
8000dfa: 17c1 asrs r1, r0, #31
8000dfc: 2300 movs r3, #0
8000dfe: 4a8e ldr r2, [pc, #568] @ (8001038 <feed_state_machine_update+0x2b4>)
8000e00: f7ff fb30 bl 8000464 <__aeabi_lmul>
8000e04: 2300 movs r3, #0
8000e06: 4a8d ldr r2, [pc, #564] @ (800103c <feed_state_machine_update+0x2b8>)
8000e08: f7ff fb08 bl 800041c <__aeabi_ldivmod>
feed_target_position = total_count - tenths_to_counts(total_backward);
8000e0c: 4c8c ldr r4, [pc, #560] @ (8001040 <feed_state_machine_update+0x2bc>)
8000e0e: 6823 ldr r3, [r4, #0]
8000e10: 1a18 subs r0, r3, r0
8000e12: 4b8c ldr r3, [pc, #560] @ (8001044 <feed_state_machine_update+0x2c0>)
8000e14: 6018 str r0, [r3, #0]
target_count = feed_target_position;
8000e16: 4b8c ldr r3, [pc, #560] @ (8001048 <feed_state_machine_update+0x2c4>)
8000e18: 6018 str r0, [r3, #0]
8000e1a: e7d8 b.n 8000dce <feed_state_machine_update+0x4a>
int32_t error = feed_target_position - total_count;
8000e1c: 4b88 ldr r3, [pc, #544] @ (8001040 <feed_state_machine_update+0x2bc>)
8000e1e: 4f89 ldr r7, [pc, #548] @ (8001044 <feed_state_machine_update+0x2c0>)
8000e20: 681a ldr r2, [r3, #0]
8000e22: 683b ldr r3, [r7, #0]
8000e24: 1a9b subs r3, r3, r2
int32_t abs_error = error < 0 ? -error : error;
8000e26: 17d8 asrs r0, r3, #31
8000e28: 1819 adds r1, r3, r0
8000e2a: 4041 eors r1, r0
int32_t brake_adj = abs_error >= 20 ? 20 : abs_error >= 10 ? 10 : abs_error >= 5 ? 5 : 0;
8000e2c: 2913 cmp r1, #19
8000e2e: dc2e bgt.n 8000e8e <feed_state_machine_update+0x10a>
8000e30: 2909 cmp r1, #9
8000e32: dc59 bgt.n 8000ee8 <feed_state_machine_update+0x164>
8000e34: 2904 cmp r1, #4
8000e36: dd00 ble.n 8000e3a <feed_state_machine_update+0xb6>
8000e38: e0ec b.n 8001014 <feed_state_machine_update+0x290>
if (error < 0) // overshot
8000e3a: 2b00 cmp r3, #0
8000e3c: da14 bge.n 8000e68 <feed_state_machine_update+0xe4>
8000e3e: 2300 movs r3, #0
brake_time_tenths += brake_adj;
8000e40: 4a82 ldr r2, [pc, #520] @ (800104c <feed_state_machine_update+0x2c8>)
8000e42: 6811 ldr r1, [r2, #0]
8000e44: 185b adds r3, r3, r1
8000e46: 6013 str r3, [r2, #0]
if (!feed_direction)
8000e48: 4b81 ldr r3, [pc, #516] @ (8001050 <feed_state_machine_update+0x2cc>)
8000e4a: 781a ldrb r2, [r3, #0]
8000e4c: 4b76 ldr r3, [pc, #472] @ (8001028 <feed_state_machine_update+0x2a4>)
8000e4e: 2a00 cmp r2, #0
8000e50: d117 bne.n 8000e82 <feed_state_machine_update+0xfe>
feed_state = FEED_STATE_SLACK_REMOVAL;
8000e52: 3205 adds r2, #5
8000e54: 7032 strb r2, [r6, #0]
feed_state_duration = BACKWARDS_FEED_FILM_SLACK_REMOVAL_TIME;
8000e56: 325a adds r2, #90 @ 0x5a
8000e58: 32ff adds r2, #255 @ 0xff
8000e5a: 601a str r2, [r3, #0]
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
8000e5c: 2296 movs r2, #150 @ 0x96
8000e5e: 4b73 ldr r3, [pc, #460] @ (800102c <feed_state_machine_update+0x2a8>)
8000e60: 0112 lsls r2, r2, #4
feed_state_start_time = now;
8000e62: 602c str r4, [r5, #0]
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
8000e64: 801a strh r2, [r3, #0]
}
8000e66: e7b2 b.n 8000dce <feed_state_machine_update+0x4a>
else if (error > 0 && brake_time_tenths > brake_adj) // undershot
8000e68: 2b00 cmp r3, #0
8000e6a: d0ed beq.n 8000e48 <feed_state_machine_update+0xc4>
8000e6c: 2200 movs r2, #0
8000e6e: 4b77 ldr r3, [pc, #476] @ (800104c <feed_state_machine_update+0x2c8>)
8000e70: 6819 ldr r1, [r3, #0]
8000e72: 4291 cmp r1, r2
8000e74: dd03 ble.n 8000e7e <feed_state_machine_update+0xfa>
brake_time_tenths -= brake_adj;
8000e76: 6819 ldr r1, [r3, #0]
8000e78: 1a8a subs r2, r1, r2
brake_time_tenths = 1;
8000e7a: 601a str r2, [r3, #0]
8000e7c: e7e4 b.n 8000e48 <feed_state_machine_update+0xc4>
8000e7e: 2201 movs r2, #1
8000e80: e7fb b.n 8000e7a <feed_state_machine_update+0xf6>
feed_state = FEED_STATE_SETTLING;
8000e82: 2207 movs r2, #7
feed_state_start_time = now;
8000e84: 602c str r4, [r5, #0]
feed_state = FEED_STATE_SETTLING;
8000e86: 7032 strb r2, [r6, #0]
feed_state_duration = FEED_SETTLE_TIME;
8000e88: 2232 movs r2, #50 @ 0x32
8000e8a: 601a str r2, [r3, #0]
8000e8c: e79f b.n 8000dce <feed_state_machine_update+0x4a>
int32_t brake_adj = abs_error >= 20 ? 20 : abs_error >= 10 ? 10 : abs_error >= 5 ? 5 : 0;
8000e8e: 2114 movs r1, #20
else if (error < -FEED_POSITION_TOLERANCE)
8000e90: 4e68 ldr r6, [pc, #416] @ (8001034 <feed_state_machine_update+0x2b0>)
8000e92: 330a adds r3, #10
8000e94: da2a bge.n 8000eec <feed_state_machine_update+0x168>
brake_time_tenths += brake_adj;
8000e96: 486d ldr r0, [pc, #436] @ (800104c <feed_state_machine_update+0x2c8>)
8000e98: 6803 ldr r3, [r0, #0]
8000e9a: 185b adds r3, r3, r1
feed_retry_total++;
8000e9c: 496d ldr r1, [pc, #436] @ (8001054 <feed_state_machine_update+0x2d0>)
else brake_time_tenths = 1;
8000e9e: 6003 str r3, [r0, #0]
feed_retry_total++;
8000ea0: 880b ldrh r3, [r1, #0]
target_count = total_count - tenths_to_counts(10);
8000ea2: 3ae1 subs r2, #225 @ 0xe1
feed_retry_total++;
8000ea4: 3301 adds r3, #1
8000ea6: b29b uxth r3, r3
8000ea8: 800b strh r3, [r1, #0]
target_count = total_count - tenths_to_counts(10);
8000eaa: 4b67 ldr r3, [pc, #412] @ (8001048 <feed_state_machine_update+0x2c4>)
HAL_Delay(200);
8000eac: 20c8 movs r0, #200 @ 0xc8
target_count = total_count - tenths_to_counts(10);
8000eae: 601a str r2, [r3, #0]
8000eb0: 9301 str r3, [sp, #4]
HAL_Delay(200);
8000eb2: f001 fd1b bl 80028ec <HAL_Delay>
htim1.Instance->CCR1 = PWM_MAX;
8000eb6: 2296 movs r2, #150 @ 0x96
8000eb8: 4b67 ldr r3, [pc, #412] @ (8001058 <feed_state_machine_update+0x2d4>)
8000eba: 0112 lsls r2, r2, #4
8000ebc: 681b ldr r3, [r3, #0]
HAL_Delay(50);
8000ebe: 2032 movs r0, #50 @ 0x32
htim1.Instance->CCR1 = PWM_MAX;
8000ec0: 635a str r2, [r3, #52] @ 0x34
htim1.Instance->CCR2 = PWM_MAX;
8000ec2: 639a str r2, [r3, #56] @ 0x38
HAL_Delay(50);
8000ec4: f001 fd12 bl 80028ec <HAL_Delay>
target_count = feed_target_position;
8000ec8: 683b ldr r3, [r7, #0]
8000eca: 9a01 ldr r2, [sp, #4]
feed_state_start_time = now;
8000ecc: 602c str r4, [r5, #0]
target_count = feed_target_position;
8000ece: 6013 str r3, [r2, #0]
feed_timeout_time = HAL_GetTick() + (feed_distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
8000ed0: f001 fd06 bl 80028e0 <HAL_GetTick>
8000ed4: 4b56 ldr r3, [pc, #344] @ (8001030 <feed_state_machine_update+0x2ac>)
8000ed6: 2200 movs r2, #0
8000ed8: 5e9a ldrsh r2, [r3, r2]
8000eda: 2364 movs r3, #100 @ 0x64
8000edc: 4353 muls r3, r2
8000ede: 33f5 adds r3, #245 @ 0xf5
8000ee0: 33ff adds r3, #255 @ 0xff
8000ee2: 181b adds r3, r3, r0
8000ee4: 6033 str r3, [r6, #0]
8000ee6: e772 b.n 8000dce <feed_state_machine_update+0x4a>
int32_t brake_adj = abs_error >= 20 ? 20 : abs_error >= 10 ? 10 : abs_error >= 5 ? 5 : 0;
8000ee8: 210a movs r1, #10
8000eea: e7d1 b.n 8000e90 <feed_state_machine_update+0x10c>
else if (now > feed_timeout_time)
8000eec: 6833 ldr r3, [r6, #0]
8000eee: 429c cmp r4, r3
8000ef0: d800 bhi.n 8000ef4 <feed_state_machine_update+0x170>
8000ef2: e76c b.n 8000dce <feed_state_machine_update+0x4a>
if (brake_time_tenths > brake_adj) brake_time_tenths -= brake_adj;
8000ef4: 4855 ldr r0, [pc, #340] @ (800104c <feed_state_machine_update+0x2c8>)
8000ef6: 6803 ldr r3, [r0, #0]
8000ef8: 4299 cmp r1, r3
8000efa: da02 bge.n 8000f02 <feed_state_machine_update+0x17e>
8000efc: 6803 ldr r3, [r0, #0]
8000efe: 1a5b subs r3, r3, r1
8000f00: e7cc b.n 8000e9c <feed_state_machine_update+0x118>
else brake_time_tenths = 1;
8000f02: 2301 movs r3, #1
8000f04: e7ca b.n 8000e9c <feed_state_machine_update+0x118>
if (elapsed >= feed_state_duration)
8000f06: 4a48 ldr r2, [pc, #288] @ (8001028 <feed_state_machine_update+0x2a4>)
8000f08: 6812 ldr r2, [r2, #0]
8000f0a: 4293 cmp r3, r2
8000f0c: d200 bcs.n 8000f10 <feed_state_machine_update+0x18c>
8000f0e: e75e b.n 8000dce <feed_state_machine_update+0x4a>
peel_target_pwm = 0;
8000f10: 2200 movs r2, #0
8000f12: 4b46 ldr r3, [pc, #280] @ (800102c <feed_state_machine_update+0x2a8>)
feed_state_start_time = now;
8000f14: 602c str r4, [r5, #0]
peel_target_pwm = 0;
8000f16: 801a strh r2, [r3, #0]
feed_state = FEED_STATE_DRIVING_BACKLASH;
8000f18: 2306 movs r3, #6
feed_timeout_time = now + (BACKLASH_COMP_TENTH_MM * TIMEOUT_TIME_PER_TENTH_MM) + 200;
8000f1a: 2296 movs r2, #150 @ 0x96
feed_state = FEED_STATE_DRIVING_BACKLASH;
8000f1c: 7033 strb r3, [r6, #0]
feed_timeout_time = now + (BACKLASH_COMP_TENTH_MM * TIMEOUT_TIME_PER_TENTH_MM) + 200;
8000f1e: 00d2 lsls r2, r2, #3
8000f20: 4b44 ldr r3, [pc, #272] @ (8001034 <feed_state_machine_update+0x2b0>)
8000f22: 18a4 adds r4, r4, r2
8000f24: 601c str r4, [r3, #0]
feed_target_position = total_count + tenths_to_counts(BACKLASH_COMP_TENTH_MM);
8000f26: 4b46 ldr r3, [pc, #280] @ (8001040 <feed_state_machine_update+0x2bc>)
8000f28: 4a46 ldr r2, [pc, #280] @ (8001044 <feed_state_machine_update+0x2c0>)
8000f2a: 681b ldr r3, [r3, #0]
8000f2c: 33e1 adds r3, #225 @ 0xe1
8000f2e: 6013 str r3, [r2, #0]
target_count = feed_target_position;
8000f30: 4a45 ldr r2, [pc, #276] @ (8001048 <feed_state_machine_update+0x2c4>)
feed_timeout_time = HAL_GetTick() + (feed_distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
8000f32: 6013 str r3, [r2, #0]
8000f34: e74b b.n 8000dce <feed_state_machine_update+0x4a>
int32_t error = feed_target_position - total_count;
8000f36: 4b43 ldr r3, [pc, #268] @ (8001044 <feed_state_machine_update+0x2c0>)
8000f38: 4a41 ldr r2, [pc, #260] @ (8001040 <feed_state_machine_update+0x2bc>)
8000f3a: 681b ldr r3, [r3, #0]
8000f3c: 6812 ldr r2, [r2, #0]
8000f3e: 1a9b subs r3, r3, r2
if (error < 0) error = -error;
8000f40: 17da asrs r2, r3, #31
8000f42: 189b adds r3, r3, r2
8000f44: 4053 eors r3, r2
if (error < FEED_POSITION_TOLERANCE)
8000f46: 2b09 cmp r3, #9
8000f48: dc04 bgt.n 8000f54 <feed_state_machine_update+0x1d0>
feed_state = FEED_STATE_SETTLING;
8000f4a: 2307 movs r3, #7
feed_state_start_time = now;
8000f4c: 602c str r4, [r5, #0]
feed_state = FEED_STATE_SETTLING;
8000f4e: 7033 strb r3, [r6, #0]
feed_state_duration = FEED_SETTLE_TIME;
8000f50: 4b35 ldr r3, [pc, #212] @ (8001028 <feed_state_machine_update+0x2a4>)
8000f52: e799 b.n 8000e88 <feed_state_machine_update+0x104>
else if (now > feed_timeout_time)
8000f54: 4b37 ldr r3, [pc, #220] @ (8001034 <feed_state_machine_update+0x2b0>)
8000f56: 681b ldr r3, [r3, #0]
8000f58: 429c cmp r4, r3
8000f5a: d800 bhi.n 8000f5e <feed_state_machine_update+0x1da>
8000f5c: e737 b.n 8000dce <feed_state_machine_update+0x4a>
feed_state = FEED_STATE_TIMEOUT;
8000f5e: 2309 movs r3, #9
feed_state = FEED_STATE_IDLE;
8000f60: 7033 strb r3, [r6, #0]
break;
8000f62: e734 b.n 8000dce <feed_state_machine_update+0x4a>
if (elapsed >= feed_state_duration)
8000f64: 4a30 ldr r2, [pc, #192] @ (8001028 <feed_state_machine_update+0x2a4>)
8000f66: 6812 ldr r2, [r2, #0]
8000f68: 4293 cmp r3, r2
8000f6a: d200 bcs.n 8000f6e <feed_state_machine_update+0x1ea>
8000f6c: e72f b.n 8000dce <feed_state_machine_update+0x4a>
feed_state = FEED_STATE_COMPLETE;
8000f6e: 2308 movs r3, #8
8000f70: e7f6 b.n 8000f60 <feed_state_machine_update+0x1dc>
feed_state = FEED_STATE_IDLE;
8000f72: 2300 movs r3, #0
feed_in_progress = 0;
8000f74: 4a39 ldr r2, [pc, #228] @ (800105c <feed_state_machine_update+0x2d8>)
feed_state = FEED_STATE_IDLE;
8000f76: 7033 strb r3, [r6, #0]
feed_in_progress = 0;
8000f78: 7013 strb r3, [r2, #0]
last_feed_status = STATUS_OK;
8000f7a: 4a39 ldr r2, [pc, #228] @ (8001060 <feed_state_machine_update+0x2dc>)
8000f7c: 7013 strb r3, [r2, #0]
feed_just_completed = 1;
8000f7e: 2201 movs r2, #1
8000f80: 4b38 ldr r3, [pc, #224] @ (8001064 <feed_state_machine_update+0x2e0>)
8000f82: 701a strb r2, [r3, #0]
feed_ok_count++;
8000f84: 4a38 ldr r2, [pc, #224] @ (8001068 <feed_state_machine_update+0x2e4>)
8000f86: 8813 ldrh r3, [r2, #0]
8000f88: 3301 adds r3, #1
8000f8a: b29b uxth r3, r3
8000f8c: 8013 strh r3, [r2, #0]
break;
8000f8e: e71e b.n 8000dce <feed_state_machine_update+0x4a>
if (feed_retry_count < FEED_RETRY_LIMIT)
8000f90: 4a36 ldr r2, [pc, #216] @ (800106c <feed_state_machine_update+0x2e8>)
8000f92: 7813 ldrb r3, [r2, #0]
8000f94: 2b02 cmp r3, #2
8000f96: d829 bhi.n 8000fec <feed_state_machine_update+0x268>
feed_retry_count++;
8000f98: 3301 adds r3, #1
8000f9a: 7013 strb r3, [r2, #0]
feed_retry_total++;
8000f9c: 4a2d ldr r2, [pc, #180] @ (8001054 <feed_state_machine_update+0x2d0>)
target_count = total_count - tenths_to_counts(10);
8000f9e: 4f2a ldr r7, [pc, #168] @ (8001048 <feed_state_machine_update+0x2c4>)
feed_retry_total++;
8000fa0: 8813 ldrh r3, [r2, #0]
HAL_Delay(200); // Let motor reverse past backlash
8000fa2: 20c8 movs r0, #200 @ 0xc8
feed_retry_total++;
8000fa4: 3301 adds r3, #1
8000fa6: b29b uxth r3, r3
8000fa8: 8013 strh r3, [r2, #0]
target_count = total_count - tenths_to_counts(10);
8000faa: 4b25 ldr r3, [pc, #148] @ (8001040 <feed_state_machine_update+0x2bc>)
8000fac: 681b ldr r3, [r3, #0]
8000fae: 3be1 subs r3, #225 @ 0xe1
8000fb0: 603b str r3, [r7, #0]
HAL_Delay(200); // Let motor reverse past backlash
8000fb2: f001 fc9b bl 80028ec <HAL_Delay>
htim1.Instance->CCR1 = PWM_MAX;
8000fb6: 2296 movs r2, #150 @ 0x96
8000fb8: 4b27 ldr r3, [pc, #156] @ (8001058 <feed_state_machine_update+0x2d4>)
8000fba: 0112 lsls r2, r2, #4
8000fbc: 681b ldr r3, [r3, #0]
HAL_Delay(50); // Settle
8000fbe: 2032 movs r0, #50 @ 0x32
htim1.Instance->CCR1 = PWM_MAX;
8000fc0: 635a str r2, [r3, #52] @ 0x34
htim1.Instance->CCR2 = PWM_MAX;
8000fc2: 639a str r2, [r3, #56] @ 0x38
HAL_Delay(50); // Settle
8000fc4: f001 fc92 bl 80028ec <HAL_Delay>
target_count = feed_target_position;
8000fc8: 4b1e ldr r3, [pc, #120] @ (8001044 <feed_state_machine_update+0x2c0>)
feed_state_start_time = now;
8000fca: 602c str r4, [r5, #0]
target_count = feed_target_position;
8000fcc: 681b ldr r3, [r3, #0]
8000fce: 603b str r3, [r7, #0]
feed_state = FEED_STATE_DRIVING;
8000fd0: 2304 movs r3, #4
8000fd2: 7033 strb r3, [r6, #0]
feed_timeout_time = HAL_GetTick() + (feed_distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
8000fd4: f001 fc84 bl 80028e0 <HAL_GetTick>
8000fd8: 4b15 ldr r3, [pc, #84] @ (8001030 <feed_state_machine_update+0x2ac>)
8000fda: 4a16 ldr r2, [pc, #88] @ (8001034 <feed_state_machine_update+0x2b0>)
8000fdc: 2100 movs r1, #0
8000fde: 5e59 ldrsh r1, [r3, r1]
8000fe0: 2364 movs r3, #100 @ 0x64
8000fe2: 434b muls r3, r1
8000fe4: 33f5 adds r3, #245 @ 0xf5
8000fe6: 33ff adds r3, #255 @ 0xff
8000fe8: 181b adds r3, r3, r0
8000fea: e7a2 b.n 8000f32 <feed_state_machine_update+0x1ae>
feed_state = FEED_STATE_IDLE;
8000fec: 2300 movs r3, #0
feed_in_progress = 0;
8000fee: 4a1b ldr r2, [pc, #108] @ (800105c <feed_state_machine_update+0x2d8>)
feed_state = FEED_STATE_IDLE;
8000ff0: 7033 strb r3, [r6, #0]
feed_in_progress = 0;
8000ff2: 7013 strb r3, [r2, #0]
last_feed_status = STATUS_COULDNT_REACH;
8000ff4: 2202 movs r2, #2
8000ff6: 4b1a ldr r3, [pc, #104] @ (8001060 <feed_state_machine_update+0x2dc>)
8000ff8: 701a strb r2, [r3, #0]
feed_just_completed = 1;
8000ffa: 4b1a ldr r3, [pc, #104] @ (8001064 <feed_state_machine_update+0x2e0>)
8000ffc: 3a01 subs r2, #1
8000ffe: 701a strb r2, [r3, #0]
feed_fail_count++;
8001000: 4a1b ldr r2, [pc, #108] @ (8001070 <feed_state_machine_update+0x2ec>)
8001002: 8813 ldrh r3, [r2, #0]
8001004: 3301 adds r3, #1
8001006: b29b uxth r3, r3
8001008: 8013 strh r3, [r2, #0]
halt_all();
800100a: f7ff fdfb bl 8000c04 <halt_all>
800100e: e6de b.n 8000dce <feed_state_machine_update+0x4a>
feed_state = FEED_STATE_IDLE;
8001010: 2300 movs r3, #0
8001012: e7a5 b.n 8000f60 <feed_state_machine_update+0x1dc>
if (error < 0) // overshot
8001014: 2205 movs r2, #5
8001016: 2b00 cmp r3, #0
8001018: db00 blt.n 800101c <feed_state_machine_update+0x298>
800101a: e728 b.n 8000e6e <feed_state_machine_update+0xea>
800101c: 2305 movs r3, #5
800101e: e70f b.n 8000e40 <feed_state_machine_update+0xbc>
8001020: 20000118 .word 0x20000118
8001024: 20000114 .word 0x20000114
8001028: 20000110 .word 0x20000110
800102c: 200000fe .word 0x200000fe
8001030: 20000108 .word 0x20000108
8001034: 2000010c .word 0x2000010c
8001038: 002c01a0 .word 0x002c01a0
800103c: 0001f377 .word 0x0001f377
8001040: 20000154 .word 0x20000154
8001044: 20000104 .word 0x20000104
8001048: 20000150 .word 0x20000150
800104c: 20000004 .word 0x20000004
8001050: 20000002 .word 0x20000002
8001054: 2000011a .word 0x2000011a
8001058: 200012b0 .word 0x200012b0
800105c: 20000121 .word 0x20000121
8001060: 20000122 .word 0x20000122
8001064: 20000120 .word 0x20000120
8001068: 2000011e .word 0x2000011e
800106c: 20000100 .word 0x20000100
8001070: 2000011c .word 0x2000011c
08001074 <handle_vendor_options>:
{
8001074: b570 push {r4, r5, r6, lr}
uint8_t command = options[0];
8001076: 7803 ldrb r3, [r0, #0]
{
8001078: 000c movs r4, r1
if (command <= 0x0F)
800107a: 2b0f cmp r3, #15
800107c: d80e bhi.n 800109c <handle_vendor_options+0x28>
size_t start_index = command * VENDOR_SPECIFIC_OPTIONS_LENGTH;
800107e: 2214 movs r2, #20
8001080: 4353 muls r3, r2
if (start_index < version_len)
8001082: 2b08 cmp r3, #8
8001084: dc1a bgt.n 80010bc <handle_vendor_options+0x48>
size_t remaining = version_len - start_index;
8001086: 2509 movs r5, #9
memcpy(response, VERSION_STRING + start_index, copy_len);
8001088: 490f ldr r1, [pc, #60] @ (80010c8 <handle_vendor_options+0x54>)
size_t remaining = version_len - start_index;
800108a: 1aed subs r5, r5, r3
memcpy(response, VERSION_STRING + start_index, copy_len);
800108c: 1859 adds r1, r3, r1
800108e: 002a movs r2, r5
8001090: 0020 movs r0, r4
8001092: f004 f8a7 bl 80051e4 <memcpy>
response[copy_len] = '\0';
8001096: 2300 movs r3, #0
8001098: 5563 strb r3, [r4, r5]
}
800109a: bd70 pop {r4, r5, r6, pc}
switch (command)
800109c: 2b10 cmp r3, #16
800109e: d10c bne.n 80010ba <handle_vendor_options+0x46>
uint8_t led_mask = options[1];
80010a0: 7840 ldrb r0, [r0, #1]
if (set)
80010a2: 0702 lsls r2, r0, #28
80010a4: d5f9 bpl.n 800109a <handle_vendor_options+0x26>
set_LED(red, green, blue);
80010a6: 2401 movs r4, #1
80010a8: 0002 movs r2, r0
int green = (led_mask >> 1) & 1;
80010aa: 0841 lsrs r1, r0, #1
int red = (led_mask >> 2) & 1;
80010ac: 0880 lsrs r0, r0, #2
set_LED(red, green, blue);
80010ae: 4022 ands r2, r4
80010b0: 4021 ands r1, r4
80010b2: 4020 ands r0, r4
80010b4: f7ff fcf2 bl 8000a9c <set_LED>
80010b8: e7ef b.n 800109a <handle_vendor_options+0x26>
memset(response, 0, VENDOR_SPECIFIC_OPTIONS_LENGTH);
80010ba: 2214 movs r2, #20
80010bc: 2100 movs r1, #0
80010be: 0020 movs r0, r4
80010c0: f004 f864 bl 800518c <memset>
break;
80010c4: e7e9 b.n 800109a <handle_vendor_options+0x26>
80010c6: 46c0 nop @ (mov r8, r8)
80010c8: 08005221 .word 0x08005221
080010cc <onewire_delay_us>:
uint32_t cycles = us * 48;
80010cc: 2330 movs r3, #48 @ 0x30
80010ce: 4358 muls r0, r3
uint32_t elapsed = 0;
80010d0: 2300 movs r3, #0
{
80010d2: b570 push {r4, r5, r6, lr}
uint32_t reload = SysTick->LOAD;
80010d4: 4c08 ldr r4, [pc, #32] @ (80010f8 <onewire_delay_us+0x2c>)
80010d6: 6865 ldr r5, [r4, #4]
uint32_t prev = SysTick->VAL;
80010d8: 68a2 ldr r2, [r4, #8]
elapsed += prev + reload + 1 - now;
80010da: 3501 adds r5, #1
while (elapsed < cycles)
80010dc: 4283 cmp r3, r0
80010de: d300 bcc.n 80010e2 <onewire_delay_us+0x16>
}
80010e0: bd70 pop {r4, r5, r6, pc}
uint32_t now = SysTick->VAL;
80010e2: 68a1 ldr r1, [r4, #8]
if (now <= prev)
80010e4: 428a cmp r2, r1
80010e6: d303 bcc.n 80010f0 <onewire_delay_us+0x24>
elapsed += prev - now;
80010e8: 18d3 adds r3, r2, r3
80010ea: 1a5b subs r3, r3, r1
{
80010ec: 000a movs r2, r1
80010ee: e7f5 b.n 80010dc <onewire_delay_us+0x10>
elapsed += prev + reload + 1 - now;
80010f0: 1a6e subs r6, r5, r1
80010f2: 18b2 adds r2, r6, r2
80010f4: 189b adds r3, r3, r2
80010f6: e7f9 b.n 80010ec <onewire_delay_us+0x20>
80010f8: e000e010 .word 0xe000e010
080010fc <onewire_read_bit>:
return (ONEWIRE_GPIO_Port->IDR & ONEWIRE_Pin) ? 1 : 0;
80010fc: 23a0 movs r3, #160 @ 0xa0
80010fe: 05db lsls r3, r3, #23
8001100: 6918 ldr r0, [r3, #16]
8001102: 0640 lsls r0, r0, #25
8001104: 0fc0 lsrs r0, r0, #31
}
8001106: 4770 bx lr
08001108 <onewire_reset>:
{
8001108: b570 push {r4, r5, r6, lr}
ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
800110a: 24a0 movs r4, #160 @ 0xa0
800110c: 2540 movs r5, #64 @ 0x40
onewire_delay_us(ONEWIRE_DELAY_H); // 480us
800110e: 20f0 movs r0, #240 @ 0xf0
ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
8001110: 05e4 lsls r4, r4, #23
8001112: 62a5 str r5, [r4, #40] @ 0x28
onewire_delay_us(ONEWIRE_DELAY_H); // 480us
8001114: 0040 lsls r0, r0, #1
8001116: f7ff ffd9 bl 80010cc <onewire_delay_us>
ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
800111a: 61a5 str r5, [r4, #24]
onewire_delay_us(ONEWIRE_DELAY_I); // 70us
800111c: 2046 movs r0, #70 @ 0x46
800111e: f7ff ffd5 bl 80010cc <onewire_delay_us>
presence = !onewire_read_bit(); // Device pulls low if present
8001122: f7ff ffeb bl 80010fc <onewire_read_bit>
8001126: 0004 movs r4, r0
onewire_delay_us(ONEWIRE_DELAY_J); // 410us
8001128: 20cd movs r0, #205 @ 0xcd
800112a: 0040 lsls r0, r0, #1
800112c: f7ff ffce bl 80010cc <onewire_delay_us>
return presence;
8001130: 2001 movs r0, #1
8001132: 4060 eors r0, r4
8001134: b2c0 uxtb r0, r0
}
8001136: bd70 pop {r4, r5, r6, pc}
08001138 <onewire_write_bit>:
{
8001138: b570 push {r4, r5, r6, lr}
800113a: 25a0 movs r5, #160 @ 0xa0
800113c: 2440 movs r4, #64 @ 0x40
800113e: 05ed lsls r5, r5, #23
ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
8001140: 62ac str r4, [r5, #40] @ 0x28
if (bit)
8001142: 2800 cmp r0, #0
8001144: d007 beq.n 8001156 <onewire_write_bit+0x1e>
onewire_delay_us(ONEWIRE_DELAY_A); // 6us
8001146: 2006 movs r0, #6
8001148: f7ff ffc0 bl 80010cc <onewire_delay_us>
onewire_delay_us(ONEWIRE_DELAY_B); // 64us
800114c: 0020 movs r0, r4
ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
800114e: 61ac str r4, [r5, #24]
onewire_delay_us(ONEWIRE_DELAY_D); // 10us
8001150: f7ff ffbc bl 80010cc <onewire_delay_us>
}
8001154: bd70 pop {r4, r5, r6, pc}
onewire_delay_us(ONEWIRE_DELAY_C); // 60us
8001156: 203c movs r0, #60 @ 0x3c
8001158: f7ff ffb8 bl 80010cc <onewire_delay_us>
onewire_delay_us(ONEWIRE_DELAY_D); // 10us
800115c: 200a movs r0, #10
ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
800115e: 61ac str r4, [r5, #24]
onewire_delay_us(ONEWIRE_DELAY_D); // 10us
8001160: e7f6 b.n 8001150 <onewire_write_bit+0x18>
08001162 <onewire_read_bit_slot>:
{
8001162: b570 push {r4, r5, r6, lr}
ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
8001164: 24a0 movs r4, #160 @ 0xa0
8001166: 2540 movs r5, #64 @ 0x40
8001168: 05e4 lsls r4, r4, #23
800116a: 62a5 str r5, [r4, #40] @ 0x28
onewire_delay_us(ONEWIRE_DELAY_A); // 6us
800116c: 2006 movs r0, #6
800116e: f7ff ffad bl 80010cc <onewire_delay_us>
ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
8001172: 61a5 str r5, [r4, #24]
onewire_delay_us(ONEWIRE_DELAY_E); // 9us
8001174: 2009 movs r0, #9
8001176: f7ff ffa9 bl 80010cc <onewire_delay_us>
bit = onewire_read_bit();
800117a: f7ff ffbf bl 80010fc <onewire_read_bit>
800117e: 0004 movs r4, r0
onewire_delay_us(ONEWIRE_DELAY_F); // 55us
8001180: 2037 movs r0, #55 @ 0x37
8001182: f7ff ffa3 bl 80010cc <onewire_delay_us>
}
8001186: 0020 movs r0, r4
8001188: bd70 pop {r4, r5, r6, pc}
0800118a <onewire_write_byte>:
{
800118a: b570 push {r4, r5, r6, lr}
800118c: 0004 movs r4, r0
800118e: 2508 movs r5, #8
onewire_write_bit(byte & 0x01);
8001190: 2601 movs r6, #1
8001192: 0020 movs r0, r4
for (int i = 0; i < 8; i++)
8001194: 3d01 subs r5, #1
onewire_write_bit(byte & 0x01);
8001196: 4030 ands r0, r6
8001198: f7ff ffce bl 8001138 <onewire_write_bit>
byte >>= 1;
800119c: 0864 lsrs r4, r4, #1
for (int i = 0; i < 8; i++)
800119e: 2d00 cmp r5, #0
80011a0: d1f7 bne.n 8001192 <onewire_write_byte+0x8>
}
80011a2: bd70 pop {r4, r5, r6, pc}
080011a4 <onewire_read_byte>:
{
80011a4: b570 push {r4, r5, r6, lr}
80011a6: 2508 movs r5, #8
uint8_t byte = 0;
80011a8: 2400 movs r4, #0
if (onewire_read_bit_slot())
80011aa: 267f movs r6, #127 @ 0x7f
80011ac: f7ff ffd9 bl 8001162 <onewire_read_bit_slot>
80011b0: 4240 negs r0, r0
byte >>= 1;
80011b2: 0864 lsrs r4, r4, #1
if (onewire_read_bit_slot())
80011b4: 43b0 bics r0, r6
80011b6: 4304 orrs r4, r0
for (int i = 0; i < 8; i++)
80011b8: 3d01 subs r5, #1
if (onewire_read_bit_slot())
80011ba: b2e4 uxtb r4, r4
for (int i = 0; i < 8; i++)
80011bc: 2d00 cmp r5, #0
80011be: d1f5 bne.n 80011ac <onewire_read_byte+0x8>
}
80011c0: 0020 movs r0, r4
80011c2: bd70 pop {r4, r5, r6, pc}
080011c4 <read_floor_address>:
{
80011c4: b510 push {r4, lr}
80011c6: b672 cpsid i
if (!onewire_reset())
80011c8: f7ff ff9e bl 8001108 <onewire_reset>
80011cc: 2800 cmp r0, #0
80011ce: d102 bne.n 80011d6 <read_floor_address+0x12>
__ASM volatile ("cpsie i" : : : "memory");
80011d0: b662 cpsie i
return FLOOR_ADDRESS_NOT_DETECTED;
80011d2: 30ff adds r0, #255 @ 0xff
}
80011d4: bd10 pop {r4, pc}
onewire_write_byte(DS2431_SKIP_ROM);
80011d6: 20cc movs r0, #204 @ 0xcc
80011d8: f7ff ffd7 bl 800118a <onewire_write_byte>
onewire_write_byte(DS2431_READ_MEMORY);
80011dc: 20f0 movs r0, #240 @ 0xf0
80011de: f7ff ffd4 bl 800118a <onewire_write_byte>
onewire_write_byte(FLOOR_ADDRESS_LOCATION & 0xFF);
80011e2: 2000 movs r0, #0
80011e4: f7ff ffd1 bl 800118a <onewire_write_byte>
onewire_write_byte((FLOOR_ADDRESS_LOCATION >> 8) & 0xFF);
80011e8: 2000 movs r0, #0
80011ea: f7ff ffce bl 800118a <onewire_write_byte>
uint8_t address = onewire_read_byte();
80011ee: f7ff ffd9 bl 80011a4 <onewire_read_byte>
80011f2: b662 cpsie i
return address;
80011f4: e7ee b.n 80011d4 <read_floor_address+0x10>
080011f6 <write_floor_address>:
{
80011f6: b5f8 push {r3, r4, r5, r6, r7, lr}
80011f8: 0004 movs r4, r0
__ASM volatile ("cpsid i" : : : "memory");
80011fa: b672 cpsid i
if (!onewire_reset())
80011fc: f7ff ff84 bl 8001108 <onewire_reset>
8001200: 2800 cmp r0, #0
8001202: d102 bne.n 800120a <write_floor_address+0x14>
__ASM volatile ("cpsie i" : : : "memory");
8001204: b662 cpsie i
return 0; // Device not present
8001206: 2000 movs r0, #0
}
8001208: bdf8 pop {r3, r4, r5, r6, r7, pc}
onewire_write_byte(DS2431_SKIP_ROM);
800120a: 20cc movs r0, #204 @ 0xcc
800120c: f7ff ffbd bl 800118a <onewire_write_byte>
onewire_write_byte(DS2431_WRITE_SCRATCHPAD);
8001210: 200f movs r0, #15
8001212: f7ff ffba bl 800118a <onewire_write_byte>
onewire_write_byte(FLOOR_ADDRESS_LOCATION & 0xFF);
8001216: 2000 movs r0, #0
8001218: f7ff ffb7 bl 800118a <onewire_write_byte>
onewire_write_byte((FLOOR_ADDRESS_LOCATION >> 8) & 0xFF);
800121c: 2000 movs r0, #0
800121e: f7ff ffb4 bl 800118a <onewire_write_byte>
onewire_write_byte(address);
8001222: 0020 movs r0, r4
8001224: f7ff ffb1 bl 800118a <onewire_write_byte>
8001228: 2507 movs r5, #7
onewire_write_byte(0xFF); // Pad with 0xFF
800122a: 20ff movs r0, #255 @ 0xff
for (int i = 1; i < 8; i++)
800122c: 3d01 subs r5, #1
onewire_write_byte(0xFF); // Pad with 0xFF
800122e: f7ff ffac bl 800118a <onewire_write_byte>
for (int i = 1; i < 8; i++)
8001232: 2d00 cmp r5, #0
8001234: d1f9 bne.n 800122a <write_floor_address+0x34>
onewire_delay_us(100);
8001236: 2064 movs r0, #100 @ 0x64
8001238: f7ff ff48 bl 80010cc <onewire_delay_us>
if (!onewire_reset())
800123c: f7ff ff64 bl 8001108 <onewire_reset>
8001240: 2800 cmp r0, #0
8001242: d0df beq.n 8001204 <write_floor_address+0xe>
onewire_write_byte(DS2431_SKIP_ROM);
8001244: 20cc movs r0, #204 @ 0xcc
8001246: f7ff ffa0 bl 800118a <onewire_write_byte>
onewire_write_byte(DS2431_READ_SCRATCHPAD);
800124a: 20aa movs r0, #170 @ 0xaa
800124c: f7ff ff9d bl 800118a <onewire_write_byte>
uint8_t ta1 = onewire_read_byte(); // Target address 1
8001250: f7ff ffa8 bl 80011a4 <onewire_read_byte>
8001254: 0007 movs r7, r0
uint8_t ta2 = onewire_read_byte(); // Target address 2
8001256: f7ff ffa5 bl 80011a4 <onewire_read_byte>
800125a: 0006 movs r6, r0
uint8_t es = onewire_read_byte(); // E/S register
800125c: f7ff ffa2 bl 80011a4 <onewire_read_byte>
8001260: 0005 movs r5, r0
uint8_t verify = onewire_read_byte();
8001262: f7ff ff9f bl 80011a4 <onewire_read_byte>
if (verify != address)
8001266: 4284 cmp r4, r0
8001268: d1cc bne.n 8001204 <write_floor_address+0xe>
onewire_read_byte();
800126a: f7ff ff9b bl 80011a4 <onewire_read_byte>
800126e: f7ff ff99 bl 80011a4 <onewire_read_byte>
8001272: f7ff ff97 bl 80011a4 <onewire_read_byte>
8001276: f7ff ff95 bl 80011a4 <onewire_read_byte>
800127a: f7ff ff93 bl 80011a4 <onewire_read_byte>
800127e: f7ff ff91 bl 80011a4 <onewire_read_byte>
8001282: f7ff ff8f bl 80011a4 <onewire_read_byte>
if (!onewire_reset())
8001286: f7ff ff3f bl 8001108 <onewire_reset>
800128a: 2800 cmp r0, #0
800128c: d0ba beq.n 8001204 <write_floor_address+0xe>
onewire_write_byte(DS2431_SKIP_ROM);
800128e: 20cc movs r0, #204 @ 0xcc
8001290: f7ff ff7b bl 800118a <onewire_write_byte>
onewire_write_byte(DS2431_COPY_SCRATCHPAD);
8001294: 2055 movs r0, #85 @ 0x55
8001296: f7ff ff78 bl 800118a <onewire_write_byte>
onewire_write_byte(ta1);
800129a: 0038 movs r0, r7
800129c: f7ff ff75 bl 800118a <onewire_write_byte>
onewire_write_byte(ta2);
80012a0: 0030 movs r0, r6
80012a2: f7ff ff72 bl 800118a <onewire_write_byte>
onewire_write_byte(es);
80012a6: 0028 movs r0, r5
80012a8: f7ff ff6f bl 800118a <onewire_write_byte>
80012ac: b662 cpsie i
HAL_Delay(15);
80012ae: 200f movs r0, #15
80012b0: f001 fb1c bl 80028ec <HAL_Delay>
uint8_t read_back = read_floor_address();
80012b4: f7ff ff86 bl 80011c4 <read_floor_address>
return (read_back == address) ? 1 : 0;
80012b8: 1a20 subs r0, r4, r0
80012ba: 4243 negs r3, r0
80012bc: 4158 adcs r0, r3
80012be: b2c0 uxtb r0, r0
80012c0: e7a2 b.n 8001208 <write_floor_address+0x12>
...
080012c4 <handleRS485Message>:
{
80012c4: b5f0 push {r4, r5, r6, r7, lr}
last_rx_size = size;
80012c6: 4bbb ldr r3, [pc, #748] @ (80015b4 <handleRS485Message+0x2f0>)
{
80012c8: b08b sub sp, #44 @ 0x2c
last_rx_size = size;
80012ca: 7019 strb r1, [r3, #0]
80012cc: 2300 movs r3, #0
{
80012ce: 0005 movs r5, r0
for (uint8_t i = 0; i < 8 && i < size; i++) last_rx_bytes[i] = buffer[i];
80012d0: 48b9 ldr r0, [pc, #740] @ (80015b8 <handleRS485Message+0x2f4>)
80012d2: b2da uxtb r2, r3
80012d4: 4291 cmp r1, r2
80012d6: d807 bhi.n 80012e8 <handleRS485Message+0x24>
if (size >= 1 && buffer[0] == my_address)
80012d8: 2900 cmp r1, #0
80012da: d10a bne.n 80012f2 <handleRS485Message+0x2e>
drop_size++;
80012dc: 4ab7 ldr r2, [pc, #732] @ (80015bc <handleRS485Message+0x2f8>)
drop_addr++;
80012de: 8813 ldrh r3, [r2, #0]
80012e0: 3301 adds r3, #1
80012e2: b29b uxth r3, r3
80012e4: 8013 strh r3, [r2, #0]
return; // message not for us
80012e6: e036 b.n 8001356 <handleRS485Message+0x92>
for (uint8_t i = 0; i < 8 && i < size; i++) last_rx_bytes[i] = buffer[i];
80012e8: 5cea ldrb r2, [r5, r3]
80012ea: 54c2 strb r2, [r0, r3]
80012ec: 3301 adds r3, #1
80012ee: 2b08 cmp r3, #8
80012f0: d1ef bne.n 80012d2 <handleRS485Message+0xe>
if (size >= 1 && buffer[0] == my_address)
80012f2: 4fb3 ldr r7, [pc, #716] @ (80015c0 <handleRS485Message+0x2fc>)
80012f4: 782a ldrb r2, [r5, #0]
80012f6: 783b ldrb r3, [r7, #0]
80012f8: 429a cmp r2, r3
80012fa: d02e beq.n 800135a <handleRS485Message+0x96>
if (size < sizeof(PhotonPacketHeader) + 1) // header + at least commandId
80012fc: 2905 cmp r1, #5
80012fe: d9ed bls.n 80012dc <handleRS485Message+0x18>
uint32_t crc;
} CRC8_107;
static inline void CRC8_107_init(CRC8_107 *ctx)
{
ctx->crc = 0x0u;
8001300: 2400 movs r4, #0
last_rx_to = header->toAddress;
8001302: 4bb0 ldr r3, [pc, #704] @ (80015c4 <handleRS485Message+0x300>)
8001304: 7829 ldrb r1, [r5, #0]
CRC8_107_add(&rx_crc, header->toAddress);
8001306: a801 add r0, sp, #4
last_rx_to = header->toAddress;
8001308: 7019 strb r1, [r3, #0]
800130a: 9401 str r4, [sp, #4]
CRC8_107_add(&rx_crc, header->toAddress);
800130c: f7ff fa1e bl 800074c <CRC8_107_add>
CRC8_107_add(&rx_crc, header->fromAddress);
8001310: 7869 ldrb r1, [r5, #1]
8001312: a801 add r0, sp, #4
8001314: f7ff fa1a bl 800074c <CRC8_107_add>
CRC8_107_add(&rx_crc, header->packetId);
8001318: 78a9 ldrb r1, [r5, #2]
800131a: a801 add r0, sp, #4
800131c: f7ff fa16 bl 800074c <CRC8_107_add>
CRC8_107_add(&rx_crc, header->payloadLength);
8001320: 78e9 ldrb r1, [r5, #3]
8001322: a801 add r0, sp, #4
8001324: f7ff fa12 bl 800074c <CRC8_107_add>
for (uint8_t i = 0; i < header->payloadLength; i++)
8001328: 78eb ldrb r3, [r5, #3]
800132a: 42a3 cmp r3, r4
800132c: d822 bhi.n 8001374 <handleRS485Message+0xb0>
if (CRC8_107_getChecksum(&rx_crc) != header->crc)
800132e: a801 add r0, sp, #4
8001330: f7ff fa20 bl 8000774 <CRC8_107_getChecksum>
8001334: 792b ldrb r3, [r5, #4]
if (header->toAddress == my_address)
8001336: 782c ldrb r4, [r5, #0]
8001338: 783a ldrb r2, [r7, #0]
if (CRC8_107_getChecksum(&rx_crc) != header->crc)
800133a: 4283 cmp r3, r0
800133c: d022 beq.n 8001384 <handleRS485Message+0xc0>
drop_crc++;
800133e: 49a2 ldr r1, [pc, #648] @ (80015c8 <handleRS485Message+0x304>)
8001340: 880b ldrh r3, [r1, #0]
8001342: 3301 adds r3, #1
8001344: b29b uxth r3, r3
8001346: 800b strh r3, [r1, #0]
if (header->toAddress == my_address)
8001348: 4294 cmp r4, r2
800134a: d104 bne.n 8001356 <handleRS485Message+0x92>
my_addr_crc_exp = CRC8_107_getChecksum(&rx_crc);
800134c: a801 add r0, sp, #4
800134e: f7ff fa11 bl 8000774 <CRC8_107_getChecksum>
8001352: 4b9e ldr r3, [pc, #632] @ (80015cc <handleRS485Message+0x308>)
8001354: 7018 strb r0, [r3, #0]
}
8001356: b00b add sp, #44 @ 0x2c
8001358: bdf0 pop {r4, r5, r6, r7, pc}
my_addr_size = size;
800135a: 4b9d ldr r3, [pc, #628] @ (80015d0 <handleRS485Message+0x30c>)
for (uint8_t i = 0; i < 8 && i < size; i++) my_addr_bytes[i] = buffer[i];
800135c: 489d ldr r0, [pc, #628] @ (80015d4 <handleRS485Message+0x310>)
my_addr_size = size;
800135e: 7019 strb r1, [r3, #0]
8001360: 2300 movs r3, #0
for (uint8_t i = 0; i < 8 && i < size; i++) my_addr_bytes[i] = buffer[i];
8001362: 5cea ldrb r2, [r5, r3]
8001364: 54c2 strb r2, [r0, r3]
8001366: 2b07 cmp r3, #7
8001368: d0c8 beq.n 80012fc <handleRS485Message+0x38>
800136a: 3301 adds r3, #1
800136c: b2da uxtb r2, r3
800136e: 428a cmp r2, r1
8001370: d3f7 bcc.n 8001362 <handleRS485Message+0x9e>
8001372: e7c3 b.n 80012fc <handleRS485Message+0x38>
CRC8_107_add(&rx_crc, buffer[sizeof(PhotonPacketHeader) + i]);
8001374: 192b adds r3, r5, r4
8001376: 7959 ldrb r1, [r3, #5]
8001378: a801 add r0, sp, #4
for (uint8_t i = 0; i < header->payloadLength; i++)
800137a: 3401 adds r4, #1
CRC8_107_add(&rx_crc, buffer[sizeof(PhotonPacketHeader) + i]);
800137c: f7ff f9e6 bl 800074c <CRC8_107_add>
for (uint8_t i = 0; i < header->payloadLength; i++)
8001380: b2e4 uxtb r4, r4
8001382: e7d1 b.n 8001328 <handleRS485Message+0x64>
if ((header->toAddress != PHOTON_NETWORK_BROADCAST_ADDRESS) &&
8001384: 2cff cmp r4, #255 @ 0xff
8001386: d003 beq.n 8001390 <handleRS485Message+0xcc>
8001388: 4294 cmp r4, r2
800138a: d001 beq.n 8001390 <handleRS485Message+0xcc>
drop_addr++;
800138c: 4a92 ldr r2, [pc, #584] @ (80015d8 <handleRS485Message+0x314>)
800138e: e7a6 b.n 80012de <handleRS485Message+0x1a>
8001390: 2600 movs r6, #0
msg_handled++;
8001392: 4992 ldr r1, [pc, #584] @ (80015dc <handleRS485Message+0x318>)
last_rx_cmd = buffer[sizeof(PhotonPacketHeader)]; // commandId
8001394: 7968 ldrb r0, [r5, #5]
msg_handled++;
8001396: 880b ldrh r3, [r1, #0]
response.header.fromAddress = my_address;
8001398: ac03 add r4, sp, #12
msg_handled++;
800139a: 3301 adds r3, #1
800139c: b29b uxth r3, r3
800139e: 800b strh r3, [r1, #0]
last_rx_cmd = buffer[sizeof(PhotonPacketHeader)]; // commandId
80013a0: 4b8f ldr r3, [pc, #572] @ (80015e0 <handleRS485Message+0x31c>)
80013a2: 9602 str r6, [sp, #8]
80013a4: 7018 strb r0, [r3, #0]
response.header.fromAddress = my_address;
80013a6: 7062 strb r2, [r4, #1]
response.header.packetId = command->header.packetId;
80013a8: 78ab ldrb r3, [r5, #2]
80013aa: 70a3 strb r3, [r4, #2]
response.header.toAddress = command->header.fromAddress;
80013ac: 786b ldrb r3, [r5, #1]
80013ae: 7023 strb r3, [r4, #0]
switch (command->commandId)
80013b0: 2806 cmp r0, #6
80013b2: d809 bhi.n 80013c8 <handleRS485Message+0x104>
80013b4: 42b0 cmp r0, r6
80013b6: d0ce beq.n 8001356 <handleRS485Message+0x92>
80013b8: 3802 subs r0, #2
80013ba: 2804 cmp r0, #4
80013bc: d813 bhi.n 80013e6 <handleRS485Message+0x122>
80013be: f7fe fea3 bl 8000108 <__gnu_thumb1_case_uqi>
80013c2: 5430 .short 0x5430
80013c4: aa68 .short 0xaa68
80013c6: f0 .byte 0xf0
80013c7: 00 .byte 0x00
80013c8: 0003 movs r3, r0
80013ca: 3341 adds r3, #65 @ 0x41
80013cc: b2db uxtb r3, r3
80013ce: 2b04 cmp r3, #4
80013d0: d8c1 bhi.n 8001356 <handleRS485Message+0x92>
80013d2: 38c0 subs r0, #192 @ 0xc0
80013d4: 2803 cmp r0, #3
80013d6: d900 bls.n 80013da <handleRS485Message+0x116>
80013d8: e10c b.n 80015f4 <handleRS485Message+0x330>
80013da: f7fe fe9f bl 800011c <__gnu_thumb1_case_uhi>
80013de: 0146 .short 0x0146
80013e0: 0179015a .word 0x0179015a
80013e4: 0189 .short 0x0189
memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH);
80013e6: 2012 movs r0, #18
80013e8: 497e ldr r1, [pc, #504] @ (80015e4 <handleRS485Message+0x320>)
80013ea: 220c movs r2, #12
80013ec: 4468 add r0, sp
80013ee: f003 fef9 bl 80051e4 <memcpy>
response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for status byte
80013f2: 230d movs r3, #13
comp_crc_header(&crc,&response);
80013f4: 0021 movs r1, r4
80013f6: a802 add r0, sp, #8
response.status = STATUS_OK;
80013f8: 7166 strb r6, [r4, #5]
response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for status byte
80013fa: 70e3 strb r3, [r4, #3]
comp_crc_header(&crc,&response);
80013fc: f7ff fb94 bl 8000b28 <comp_crc_header>
for (uint32_t i = 0; i<response.header.payloadLength; i++)
8001400: 78e3 ldrb r3, [r4, #3]
8001402: 42b3 cmp r3, r6
8001404: d806 bhi.n 8001414 <handleRS485Message+0x150>
response.header.crc = CRC8_107_getChecksum(&crc);
8001406: a802 add r0, sp, #8
8001408: f7ff f9b4 bl 8000774 <CRC8_107_getChecksum>
packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
800140c: 78e1 ldrb r1, [r4, #3]
response.header.crc = CRC8_107_getChecksum(&crc);
800140e: 7120 strb r0, [r4, #4]
rs485_transmit((uint8_t *)&response, packet_len);
8001410: 3105 adds r1, #5
8001412: e126 b.n 8001662 <handleRS485Message+0x39e>
CRC8_107_add(&crc,*(payload_ptr+i));
8001414: 19a3 adds r3, r4, r6
8001416: 7959 ldrb r1, [r3, #5]
8001418: a802 add r0, sp, #8
800141a: f7ff f997 bl 800074c <CRC8_107_add>
for (uint32_t i = 0; i<response.header.payloadLength; i++)
800141e: 3601 adds r6, #1
8001420: e7ee b.n 8001400 <handleRS485Message+0x13c>
memcpy(response.payload.initializeFeeder.uuid,UUID,UUID_LENGTH);
8001422: 2012 movs r0, #18
8001424: 4e6f ldr r6, [pc, #444] @ (80015e4 <handleRS485Message+0x320>)
8001426: 220c movs r2, #12
8001428: 0031 movs r1, r6
800142a: 4468 add r0, sp
800142c: f003 feda bl 80051e4 <memcpy>
if(memcmp(UUID,command->payload.initializeFeeder.uuid,UUID_LENGTH) == 0)
8001430: 220c movs r2, #12
8001432: 0030 movs r0, r6
8001434: 1da9 adds r1, r5, #6
8001436: f003 fe9b bl 8005170 <memcmp>
800143a: 2301 movs r3, #1
800143c: 2800 cmp r0, #0
800143e: d102 bne.n 8001446 <handleRS485Message+0x182>
is_initialized = 1;
8001440: 4a69 ldr r2, [pc, #420] @ (80015e8 <handleRS485Message+0x324>)
8001442: 7013 strb r3, [r2, #0]
response.status = STATUS_OK;
8001444: 0003 movs r3, r0
8001446: 7163 strb r3, [r4, #5]
response.header.payloadLength = sizeof(response.payload.initializeFeeder)+1;
8001448: 230d movs r3, #13
comp_crc_header(&crc,&response);
800144a: 0021 movs r1, r4
800144c: a802 add r0, sp, #8
response.header.payloadLength = sizeof(response.payload.initializeFeeder)+1;
800144e: 70e3 strb r3, [r4, #3]
for (uint32_t i = 0; i<response.header.payloadLength; i++)
8001450: 2500 movs r5, #0
comp_crc_header(&crc,&response);
8001452: f7ff fb69 bl 8000b28 <comp_crc_header>
for (uint32_t i = 0; i<response.header.payloadLength; i++)
8001456: 78e3 ldrb r3, [r4, #3]
8001458: 42ab cmp r3, r5
800145a: d9d4 bls.n 8001406 <handleRS485Message+0x142>
CRC8_107_add(&crc,*(payload_ptr+i));
800145c: 1963 adds r3, r4, r5
800145e: 7959 ldrb r1, [r3, #5]
8001460: a802 add r0, sp, #8
8001462: f7ff f973 bl 800074c <CRC8_107_add>
for (uint32_t i = 0; i<response.header.payloadLength; i++)
8001466: 3501 adds r5, #1
8001468: e7f5 b.n 8001456 <handleRS485Message+0x192>
response.payload.protocolVersion.version = PROTOCOL_VERSION;
800146a: 2301 movs r3, #1
response.status = STATUS_OK;
800146c: 2500 movs r5, #0
response.payload.protocolVersion.version = PROTOCOL_VERSION;
800146e: 71a3 strb r3, [r4, #6]
comp_crc_header(&crc,&response);
8001470: 0021 movs r1, r4
response.header.payloadLength = sizeof(response.payload.protocolVersion)+1;
8001472: 18db adds r3, r3, r3
comp_crc_header(&crc,&response);
8001474: a802 add r0, sp, #8
response.status = STATUS_OK;
8001476: 7165 strb r5, [r4, #5]
response.header.payloadLength = sizeof(response.payload.protocolVersion)+1;
8001478: 70e3 strb r3, [r4, #3]
comp_crc_header(&crc,&response);
800147a: f7ff fb55 bl 8000b28 <comp_crc_header>
for (uint32_t i = 0; i<response.header.payloadLength; i++)
800147e: 78e3 ldrb r3, [r4, #3]
8001480: 42ab cmp r3, r5
8001482: d9c0 bls.n 8001406 <handleRS485Message+0x142>
CRC8_107_add(&crc,*(payload_ptr+i));
8001484: 1963 adds r3, r4, r5
8001486: 7959 ldrb r1, [r3, #5]
8001488: a802 add r0, sp, #8
800148a: f7ff f95f bl 800074c <CRC8_107_add>
for (uint32_t i = 0; i<response.header.payloadLength; i++)
800148e: 3501 adds r5, #1
8001490: e7f5 b.n 800147e <handleRS485Message+0x1ba>
if (!is_initialized)
8001492: 4b55 ldr r3, [pc, #340] @ (80015e8 <handleRS485Message+0x324>)
8001494: 781e ldrb r6, [r3, #0]
8001496: 2e00 cmp r6, #0
8001498: d117 bne.n 80014ca <handleRS485Message+0x206>
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
800149a: 2012 movs r0, #18
response.status = STATUS_UNINITIALIZED_FEEDER;
800149c: 2303 movs r3, #3
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
800149e: 4951 ldr r1, [pc, #324] @ (80015e4 <handleRS485Message+0x320>)
80014a0: 220c movs r2, #12
80014a2: 4468 add r0, sp
response.status = STATUS_UNINITIALIZED_FEEDER;
80014a4: 7163 strb r3, [r4, #5]
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
80014a6: f003 fe9d bl 80051e4 <memcpy>
response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
80014aa: 230d movs r3, #13
comp_crc_header(&crc, &response);
80014ac: 0021 movs r1, r4
80014ae: a802 add r0, sp, #8
response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
80014b0: 70e3 strb r3, [r4, #3]
comp_crc_header(&crc, &response);
80014b2: f7ff fb39 bl 8000b28 <comp_crc_header>
for (uint32_t i = 0; i < response.header.payloadLength; i++)
80014b6: 78e3 ldrb r3, [r4, #3]
80014b8: 42b3 cmp r3, r6
80014ba: d9a4 bls.n 8001406 <handleRS485Message+0x142>
CRC8_107_add(&crc, *(payload_ptr + i));
80014bc: 19a3 adds r3, r4, r6
80014be: 7959 ldrb r1, [r3, #5]
80014c0: a802 add r0, sp, #8
80014c2: f7ff f943 bl 800074c <CRC8_107_add>
for (uint32_t i = 0; i < response.header.payloadLength; i++)
80014c6: 3601 adds r6, #1
80014c8: e7f5 b.n 80014b6 <handleRS485Message+0x1f2>
PEEL_BACKOFF_TIME +
80014ca: 2276 movs r2, #118 @ 0x76
80014cc: 79ab ldrb r3, [r5, #6]
response.status = STATUS_OK;
80014ce: 2600 movs r6, #0
PEEL_BACKOFF_TIME +
80014d0: 4353 muls r3, r2
uint16_t time = (distance * PEEL_TIME_PER_TENTH_MM) +
80014d2: 33e6 adds r3, #230 @ 0xe6
uint16_t exp_time_be = (exp_time >> 8) | (exp_time << 8); // byte swap for network order
80014d4: ba5b rev16 r3, r3
response.payload.expectedTimeToFeed.expectedFeedTime = exp_time_be;
80014d6: 80e3 strh r3, [r4, #6]
response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
80014d8: 2303 movs r3, #3
comp_crc_header(&crc, &response);
80014da: 0021 movs r1, r4
80014dc: a802 add r0, sp, #8
response.status = STATUS_OK;
80014de: 7166 strb r6, [r4, #5]
response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
80014e0: 70e3 strb r3, [r4, #3]
comp_crc_header(&crc, &response);
80014e2: f7ff fb21 bl 8000b28 <comp_crc_header>
for (uint32_t i = 0; i < response.header.payloadLength; i++)
80014e6: 78e3 ldrb r3, [r4, #3]
80014e8: 42b3 cmp r3, r6
80014ea: d80d bhi.n 8001508 <handleRS485Message+0x244>
response.header.crc = CRC8_107_getChecksum(&crc);
80014ec: a802 add r0, sp, #8
80014ee: f7ff f941 bl 8000774 <CRC8_107_getChecksum>
packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
80014f2: 78e1 ldrb r1, [r4, #3]
response.header.crc = CRC8_107_getChecksum(&crc);
80014f4: 7120 strb r0, [r4, #4]
rs485_transmit((uint8_t *)&response, packet_len);
80014f6: 3105 adds r1, #5
80014f8: 0020 movs r0, r4
80014fa: f7ff faeb bl 8000ad4 <rs485_transmit>
start_feed(command->payload.move.distance, 1);
80014fe: 2101 movs r1, #1
8001500: 79a8 ldrb r0, [r5, #6]
start_feed(command->payload.move.distance, 0);
8001502: f7ff fbc9 bl 8000c98 <start_feed>
break;
8001506: e726 b.n 8001356 <handleRS485Message+0x92>
CRC8_107_add(&crc, *(payload_ptr + i));
8001508: 19a3 adds r3, r4, r6
800150a: 7959 ldrb r1, [r3, #5]
800150c: a802 add r0, sp, #8
800150e: f7ff f91d bl 800074c <CRC8_107_add>
for (uint32_t i = 0; i < response.header.payloadLength; i++)
8001512: 3601 adds r6, #1
8001514: e7e7 b.n 80014e6 <handleRS485Message+0x222>
if (!is_initialized)
8001516: 4b34 ldr r3, [pc, #208] @ (80015e8 <handleRS485Message+0x324>)
8001518: 781e ldrb r6, [r3, #0]
800151a: 2e00 cmp r6, #0
800151c: d118 bne.n 8001550 <handleRS485Message+0x28c>
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
800151e: 2012 movs r0, #18
response.status = STATUS_UNINITIALIZED_FEEDER;
8001520: 2303 movs r3, #3
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
8001522: 4930 ldr r1, [pc, #192] @ (80015e4 <handleRS485Message+0x320>)
8001524: 220c movs r2, #12
8001526: 4468 add r0, sp
response.status = STATUS_UNINITIALIZED_FEEDER;
8001528: 7163 strb r3, [r4, #5]
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
800152a: f003 fe5b bl 80051e4 <memcpy>
response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
800152e: 230d movs r3, #13
comp_crc_header(&crc, &response);
8001530: 0021 movs r1, r4
8001532: a802 add r0, sp, #8
response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
8001534: 70e3 strb r3, [r4, #3]
comp_crc_header(&crc, &response);
8001536: f7ff faf7 bl 8000b28 <comp_crc_header>
for (uint32_t i = 0; i < response.header.payloadLength; i++)
800153a: 78e3 ldrb r3, [r4, #3]
800153c: 42b3 cmp r3, r6
800153e: d800 bhi.n 8001542 <handleRS485Message+0x27e>
8001540: e761 b.n 8001406 <handleRS485Message+0x142>
CRC8_107_add(&crc, *(payload_ptr + i));
8001542: 19a3 adds r3, r4, r6
8001544: 7959 ldrb r1, [r3, #5]
8001546: a802 add r0, sp, #8
8001548: f7ff f900 bl 800074c <CRC8_107_add>
for (uint32_t i = 0; i < response.header.payloadLength; i++)
800154c: 3601 adds r6, #1
800154e: e7f4 b.n 800153a <handleRS485Message+0x276>
return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) +
8001550: 231e movs r3, #30
8001552: 2164 movs r1, #100 @ 0x64
uint16_t exp_time = calculate_expected_feed_time(command->payload.move.distance, 0);
8001554: 79aa ldrb r2, [r5, #6]
response.status = STATUS_OK;
8001556: 2600 movs r6, #0
return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) +
8001558: 4353 muls r3, r2
((distance + (BACKLASH_COMP_TENTH_MM * 2)) * TIMEOUT_TIME_PER_TENTH_MM) +
800155a: 3214 adds r2, #20
return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) +
800155c: 434a muls r2, r1
BACKWARDS_FEED_FILM_SLACK_REMOVAL_TIME + 50;
800155e: 3391 adds r3, #145 @ 0x91
8001560: 33ff adds r3, #255 @ 0xff
8001562: 189b adds r3, r3, r2
uint16_t exp_time_be = (exp_time >> 8) | (exp_time << 8); // byte swap for network order
8001564: ba5b rev16 r3, r3
response.payload.expectedTimeToFeed.expectedFeedTime = exp_time_be;
8001566: 80e3 strh r3, [r4, #6]
response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
8001568: 2303 movs r3, #3
comp_crc_header(&crc, &response);
800156a: 0021 movs r1, r4
800156c: a802 add r0, sp, #8
response.status = STATUS_OK;
800156e: 7166 strb r6, [r4, #5]
response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
8001570: 70e3 strb r3, [r4, #3]
comp_crc_header(&crc, &response);
8001572: f7ff fad9 bl 8000b28 <comp_crc_header>
for (uint32_t i = 0; i < response.header.payloadLength; i++)
8001576: 78e3 ldrb r3, [r4, #3]
8001578: 42b3 cmp r3, r6
800157a: d80b bhi.n 8001594 <handleRS485Message+0x2d0>
response.header.crc = CRC8_107_getChecksum(&crc);
800157c: a802 add r0, sp, #8
800157e: f7ff f8f9 bl 8000774 <CRC8_107_getChecksum>
packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
8001582: 78e1 ldrb r1, [r4, #3]
response.header.crc = CRC8_107_getChecksum(&crc);
8001584: 7120 strb r0, [r4, #4]
rs485_transmit((uint8_t *)&response, packet_len);
8001586: 3105 adds r1, #5
8001588: 0020 movs r0, r4
800158a: f7ff faa3 bl 8000ad4 <rs485_transmit>
start_feed(command->payload.move.distance, 0);
800158e: 2100 movs r1, #0
8001590: 79a8 ldrb r0, [r5, #6]
8001592: e7b6 b.n 8001502 <handleRS485Message+0x23e>
CRC8_107_add(&crc, *(payload_ptr + i));
8001594: 19a3 adds r3, r4, r6
8001596: 7959 ldrb r1, [r3, #5]
8001598: a802 add r0, sp, #8
800159a: f7ff f8d7 bl 800074c <CRC8_107_add>
for (uint32_t i = 0; i < response.header.payloadLength; i++)
800159e: 3601 adds r6, #1
80015a0: e7e9 b.n 8001576 <handleRS485Message+0x2b2>
if (feed_in_progress)
80015a2: 4b12 ldr r3, [pc, #72] @ (80015ec <handleRS485Message+0x328>)
80015a4: 781a ldrb r2, [r3, #0]
response.status = STATUS_FEEDING_IN_PROGRESS;
80015a6: 2304 movs r3, #4
if (feed_in_progress)
80015a8: 2a00 cmp r2, #0
80015aa: d101 bne.n 80015b0 <handleRS485Message+0x2ec>
response.status = last_feed_status;
80015ac: 4b10 ldr r3, [pc, #64] @ (80015f0 <handleRS485Message+0x32c>)
80015ae: 781b ldrb r3, [r3, #0]
response.status = STATUS_OK;
80015b0: 7163 strb r3, [r4, #5]
80015b2: e063 b.n 800167c <handleRS485Message+0x3b8>
80015b4: 20000071 .word 0x20000071
80015b8: 20000067 .word 0x20000067
80015bc: 20000078 .word 0x20000078
80015c0: 20000020 .word 0x20000020
80015c4: 20000070 .word 0x20000070
80015c8: 20000076 .word 0x20000076
80015cc: 2000005d .word 0x2000005d
80015d0: 2000005e .word 0x2000005e
80015d4: 2000005f .word 0x2000005f
80015d8: 20000074 .word 0x20000074
80015dc: 20000072 .word 0x20000072
80015e0: 2000006f .word 0x2000006f
80015e4: 20000f87 .word 0x20000f87
80015e8: 20000f86 .word 0x20000f86
80015ec: 20000121 .word 0x20000121
80015f0: 20000122 .word 0x20000122
if (!is_initialized)
80015f4: 4b4d ldr r3, [pc, #308] @ (800172c <handleRS485Message+0x468>)
80015f6: 781f ldrb r7, [r3, #0]
80015f8: 2f00 cmp r7, #0
80015fa: d119 bne.n 8001630 <handleRS485Message+0x36c>
response.status = STATUS_UNINITIALIZED_FEEDER;
80015fc: 2303 movs r3, #3
80015fe: 7163 strb r3, [r4, #5]
memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
8001600: 330f adds r3, #15
8001602: 446b add r3, sp
8001604: 0018 movs r0, r3
8001606: 494a ldr r1, [pc, #296] @ (8001730 <handleRS485Message+0x46c>)
8001608: 220c movs r2, #12
800160a: f003 fdeb bl 80051e4 <memcpy>
response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
800160e: 230d movs r3, #13
comp_crc_header(&crc, &response);
8001610: 0021 movs r1, r4
8001612: a802 add r0, sp, #8
response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
8001614: 70e3 strb r3, [r4, #3]
comp_crc_header(&crc, &response);
8001616: f7ff fa87 bl 8000b28 <comp_crc_header>
for (uint32_t i = 0; i < response.header.payloadLength; i++)
800161a: 78e3 ldrb r3, [r4, #3]
800161c: 42bb cmp r3, r7
800161e: d800 bhi.n 8001622 <handleRS485Message+0x35e>
8001620: e6f1 b.n 8001406 <handleRS485Message+0x142>
CRC8_107_add(&crc, *(payload_ptr + i));
8001622: 19e3 adds r3, r4, r7
8001624: 7959 ldrb r1, [r3, #5]
8001626: a802 add r0, sp, #8
8001628: f7ff f890 bl 800074c <CRC8_107_add>
for (uint32_t i = 0; i < response.header.payloadLength; i++)
800162c: 3701 adds r7, #1
800162e: e7f4 b.n 800161a <handleRS485Message+0x356>
handle_vendor_options(command->payload.vendorOptions.options, response.payload.vendorOptions.options);
8001630: 2312 movs r3, #18
8001632: 446b add r3, sp
8001634: 0019 movs r1, r3
8001636: 1da8 adds r0, r5, #6
8001638: f7ff fd1c bl 8001074 <handle_vendor_options>
comp_crc_header(&crc,&response);
800163c: 0021 movs r1, r4
800163e: a802 add r0, sp, #8
response.status = STATUS_OK;
8001640: 7166 strb r6, [r4, #5]
comp_crc_header(&crc,&response);
8001642: f7ff fa71 bl 8000b28 <comp_crc_header>
CRC8_107_add(&crc,*(payload_ptr+i));
8001646: 19a3 adds r3, r4, r6
8001648: 7959 ldrb r1, [r3, #5]
800164a: a802 add r0, sp, #8
for (uint32_t i = 0; i<sizeof(response.payload.vendorOptions)+1; i++)
800164c: 3601 adds r6, #1
CRC8_107_add(&crc,*(payload_ptr+i));
800164e: f7ff f87d bl 800074c <CRC8_107_add>
for (uint32_t i = 0; i<sizeof(response.payload.vendorOptions)+1; i++)
8001652: 2e15 cmp r6, #21
8001654: d1f7 bne.n 8001646 <handleRS485Message+0x382>
response.header.crc = CRC8_107_getChecksum(&crc);
8001656: a802 add r0, sp, #8
8001658: f7ff f88c bl 8000774 <CRC8_107_getChecksum>
rs485_transmit((uint8_t *)&response, packet_len);
800165c: 211a movs r1, #26
response.header.crc = CRC8_107_getChecksum(&crc);
800165e: 7120 strb r0, [r4, #4]
response.header.payloadLength = sizeof(response.payload.vendorOptions)+1; // +1 for the status byte
8001660: 70e6 strb r6, [r4, #3]
rs485_transmit((uint8_t *)&response, packet_len);
8001662: 0020 movs r0, r4
8001664: f7ff fa36 bl 8000ad4 <rs485_transmit>
break;
8001668: e675 b.n 8001356 <handleRS485Message+0x92>
if(memcmp(UUID,command->payload.getFeederAddress.uuid,UUID_LENGTH) == 0)
800166a: 220c movs r2, #12
800166c: 4830 ldr r0, [pc, #192] @ (8001730 <handleRS485Message+0x46c>)
800166e: 1da9 adds r1, r5, #6
8001670: f003 fd7e bl 8005170 <memcmp>
8001674: 2800 cmp r0, #0
8001676: d000 beq.n 800167a <handleRS485Message+0x3b6>
8001678: e66d b.n 8001356 <handleRS485Message+0x92>
response.status = STATUS_OK;
800167a: 7160 strb r0, [r4, #5]
response.header.payloadLength = 1; // only status byte
800167c: 2301 movs r3, #1
comp_crc_header(&crc, &response);
800167e: 0021 movs r1, r4
8001680: a802 add r0, sp, #8
response.header.payloadLength = 1; // only status byte
8001682: 70e3 strb r3, [r4, #3]
comp_crc_header(&crc, &response);
8001684: f7ff fa50 bl 8000b28 <comp_crc_header>
CRC8_107_add(&crc, response.status);
8001688: 7961 ldrb r1, [r4, #5]
800168a: a802 add r0, sp, #8
800168c: f7ff f85e bl 800074c <CRC8_107_add>
response.header.crc = CRC8_107_getChecksum(&crc);
8001690: e6b9 b.n 8001406 <handleRS485Message+0x142>
if(memcmp(UUID,command->payload.identifyFeeder.uuid,UUID_LENGTH) == 0)
8001692: 220c movs r2, #12
8001694: 4826 ldr r0, [pc, #152] @ (8001730 <handleRS485Message+0x46c>)
8001696: 1da9 adds r1, r5, #6
8001698: f003 fd6a bl 8005170 <memcmp>
800169c: 2800 cmp r0, #0
800169e: d000 beq.n 80016a2 <handleRS485Message+0x3de>
80016a0: e659 b.n 8001356 <handleRS485Message+0x92>
response.header.payloadLength = 1; // only status byte
80016a2: 2301 movs r3, #1
comp_crc_header(&crc,&response);
80016a4: 0021 movs r1, r4
response.status = STATUS_OK;
80016a6: 7160 strb r0, [r4, #5]
comp_crc_header(&crc,&response);
80016a8: a802 add r0, sp, #8
response.header.payloadLength = 1; // only status byte
80016aa: 70e3 strb r3, [r4, #3]
comp_crc_header(&crc,&response);
80016ac: f7ff fa3c bl 8000b28 <comp_crc_header>
CRC8_107_add(&crc,response.status);
80016b0: 7961 ldrb r1, [r4, #5]
80016b2: a802 add r0, sp, #8
80016b4: f7ff f84a bl 800074c <CRC8_107_add>
response.header.crc = CRC8_107_getChecksum(&crc);
80016b8: a802 add r0, sp, #8
80016ba: f7ff f85b bl 8000774 <CRC8_107_getChecksum>
packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
80016be: 78e1 ldrb r1, [r4, #3]
response.header.crc = CRC8_107_getChecksum(&crc);
80016c0: 7120 strb r0, [r4, #4]
rs485_transmit((uint8_t *)&response, packet_len);
80016c2: 3105 adds r1, #5
80016c4: 0020 movs r0, r4
80016c6: f7ff fa05 bl 8000ad4 <rs485_transmit>
identify_feeder();
80016ca: f7ff fabb bl 8000c44 <identify_feeder>
break;
80016ce: e642 b.n 8001356 <handleRS485Message+0x92>
uint8_t new_address = command->payload.programFeederFloorAddress.address;
80016d0: 7cad ldrb r5, [r5, #18]
uint8_t write_success = write_floor_address(new_address);
80016d2: 0028 movs r0, r5
80016d4: f7ff fd8f bl 80011f6 <write_floor_address>
if (write_success)
80016d8: 2305 movs r3, #5
80016da: 2800 cmp r0, #0
80016dc: d100 bne.n 80016e0 <handleRS485Message+0x41c>
80016de: e767 b.n 80015b0 <handleRS485Message+0x2ec>
floor_address_status = 2;
80016e0: 2202 movs r2, #2
floor_address = new_address;
80016e2: 4b14 ldr r3, [pc, #80] @ (8001734 <handleRS485Message+0x470>)
my_address = new_address;
80016e4: 703d strb r5, [r7, #0]
floor_address = new_address;
80016e6: 701d strb r5, [r3, #0]
floor_address_status = 2;
80016e8: 4b13 ldr r3, [pc, #76] @ (8001738 <handleRS485Message+0x474>)
80016ea: 701a strb r2, [r3, #0]
response.status = STATUS_OK;
80016ec: 2300 movs r3, #0
80016ee: e75f b.n 80015b0 <handleRS485Message+0x2ec>
if (is_initialized) return;
80016f0: 4b0e ldr r3, [pc, #56] @ (800172c <handleRS485Message+0x468>)
80016f2: 781d ldrb r5, [r3, #0]
80016f4: 2d00 cmp r5, #0
80016f6: d000 beq.n 80016fa <handleRS485Message+0x436>
80016f8: e62d b.n 8001356 <handleRS485Message+0x92>
memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH);
80016fa: 2012 movs r0, #18
80016fc: 490c ldr r1, [pc, #48] @ (8001730 <handleRS485Message+0x46c>)
80016fe: 220c movs r2, #12
8001700: 4468 add r0, sp
8001702: f003 fd6f bl 80051e4 <memcpy>
response.header.payloadLength = sizeof(response.payload.getFeederId)+1;
8001706: 230d movs r3, #13
comp_crc_header(&crc,&response);
8001708: 0021 movs r1, r4
800170a: a802 add r0, sp, #8
response.status=STATUS_OK;
800170c: 7165 strb r5, [r4, #5]
response.header.payloadLength = sizeof(response.payload.getFeederId)+1;
800170e: 70e3 strb r3, [r4, #3]
comp_crc_header(&crc,&response);
8001710: f7ff fa0a bl 8000b28 <comp_crc_header>
for (uint32_t i = 0; i<response.header.payloadLength; i++)
8001714: 78e3 ldrb r3, [r4, #3]
8001716: 42ab cmp r3, r5
8001718: d800 bhi.n 800171c <handleRS485Message+0x458>
800171a: e674 b.n 8001406 <handleRS485Message+0x142>
CRC8_107_add(&crc,*(payload_ptr+i));
800171c: 1963 adds r3, r4, r5
800171e: 7959 ldrb r1, [r3, #5]
8001720: a802 add r0, sp, #8
8001722: f7ff f813 bl 800074c <CRC8_107_add>
for (uint32_t i = 0; i<response.header.payloadLength; i++)
8001726: 3501 adds r5, #1
8001728: e7f4 b.n 8001714 <handleRS485Message+0x450>
800172a: 46c0 nop @ (mov r8, r8)
800172c: 20000f86 .word 0x20000f86
8001730: 20000f87 .word 0x20000f87
8001734: 20000001 .word 0x20000001
8001738: 200000e8 .word 0x200000e8
0800173c <debug_itoa>:
{
800173c: b5f0 push {r4, r5, r6, r7, lr}
800173e: 0004 movs r4, r0
8001740: 000d movs r5, r1
8001742: b087 sub sp, #28
if (val < 0) { neg = 1; val = -val; }
8001744: 2800 cmp r0, #0
8001746: da1a bge.n 800177e <debug_itoa+0x42>
8001748: 2601 movs r6, #1
800174a: 4244 negs r4, r0
uint8_t i = 0, len = 0;
800174c: 2700 movs r7, #0
else { while (val > 0) { tmp[i++] = '0' + (val % 10); val /= 10; } }
800174e: 0020 movs r0, r4
8001750: 210a movs r1, #10
8001752: 9701 str r7, [sp, #4]
8001754: f7fe fe5c bl 8000410 <__aeabi_idivmod>
8001758: 9a01 ldr r2, [sp, #4]
800175a: 3130 adds r1, #48 @ 0x30
800175c: ab03 add r3, sp, #12
800175e: 0020 movs r0, r4
8001760: 5499 strb r1, [r3, r2]
8001762: 210a movs r1, #10
8001764: f7fe fd6e bl 8000244 <__divsi3>
8001768: 3701 adds r7, #1
800176a: 0004 movs r4, r0
800176c: b2ff uxtb r7, r7
800176e: 2800 cmp r0, #0
8001770: d1ed bne.n 800174e <debug_itoa+0x12>
if (neg) { *buf++ = '-'; len++; }
8001772: 2e00 cmp r6, #0
8001774: d00c beq.n 8001790 <debug_itoa+0x54>
8001776: 232d movs r3, #45 @ 0x2d
8001778: 702b strb r3, [r5, #0]
800177a: 3501 adds r5, #1
800177c: e008 b.n 8001790 <debug_itoa+0x54>
if (val == 0) { tmp[i++] = '0'; }
800177e: 2800 cmp r0, #0
8001780: d001 beq.n 8001786 <debug_itoa+0x4a>
8001782: 2600 movs r6, #0
8001784: e7e2 b.n 800174c <debug_itoa+0x10>
8001786: 2330 movs r3, #48 @ 0x30
uint8_t i = 0, len = 0;
8001788: 0006 movs r6, r0
if (val == 0) { tmp[i++] = '0'; }
800178a: 2701 movs r7, #1
800178c: aa02 add r2, sp, #8
800178e: 7113 strb r3, [r2, #4]
8001790: 003b movs r3, r7
while (i > 0) { *buf++ = tmp[--i]; len++; }
8001792: 2b00 cmp r3, #0
8001794: d103 bne.n 800179e <debug_itoa+0x62>
return len;
8001796: 19f0 adds r0, r6, r7
8001798: b2c0 uxtb r0, r0
}
800179a: b007 add sp, #28
800179c: bdf0 pop {r4, r5, r6, r7, pc}
while (i > 0) { *buf++ = tmp[--i]; len++; }
800179e: 3b01 subs r3, #1
80017a0: b2db uxtb r3, r3
80017a2: aa03 add r2, sp, #12
80017a4: 5cd2 ldrb r2, [r2, r3]
80017a6: 702a strb r2, [r5, #0]
80017a8: 3501 adds r5, #1
80017aa: e7f2 b.n 8001792 <debug_itoa+0x56>
080017ac <debug_hex8>:
{
80017ac: b570 push {r4, r5, r6, lr}
80017ae: 0004 movs r4, r0
80017b0: 000d movs r5, r1
80017b2: b086 sub sp, #24
const char hex[] = "0123456789ABCDEF";
80017b4: ae01 add r6, sp, #4
80017b6: 2211 movs r2, #17
80017b8: 0030 movs r0, r6
80017ba: 4906 ldr r1, [pc, #24] @ (80017d4 <debug_hex8+0x28>)
80017bc: f003 fd12 bl 80051e4 <memcpy>
buf[0] = hex[(val >> 4) & 0x0F];
80017c0: 0923 lsrs r3, r4, #4
80017c2: 5cf3 ldrb r3, [r6, r3]
}
80017c4: 2002 movs r0, #2
buf[0] = hex[(val >> 4) & 0x0F];
80017c6: 702b strb r3, [r5, #0]
buf[1] = hex[val & 0x0F];
80017c8: 230f movs r3, #15
80017ca: 401c ands r4, r3
80017cc: 5d33 ldrb r3, [r6, r4]
80017ce: 706b strb r3, [r5, #1]
}
80017d0: b006 add sp, #24
80017d2: bd70 pop {r4, r5, r6, pc}
80017d4: 08005210 .word 0x08005210
080017d8 <debug_output>:
{
80017d8: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
if (!debug_enabled) return;
80017da: 4b6b ldr r3, [pc, #428] @ (8001988 <debug_output+0x1b0>)
80017dc: 781b ldrb r3, [r3, #0]
80017de: 2b00 cmp r3, #0
80017e0: d100 bne.n 80017e4 <debug_output+0xc>
80017e2: e0cf b.n 8001984 <debug_output+0x1ac>
uint32_t now = HAL_GetTick();
80017e4: f001 f87c bl 80028e0 <HAL_GetTick>
if ((now - last_debug_output_time) < DEBUG_OUTPUT_INTERVAL_MS) return;
80017e8: 4a68 ldr r2, [pc, #416] @ (800198c <debug_output+0x1b4>)
80017ea: 6813 ldr r3, [r2, #0]
80017ec: 1ac3 subs r3, r0, r3
80017ee: 2b63 cmp r3, #99 @ 0x63
80017f0: d800 bhi.n 80017f4 <debug_output+0x1c>
80017f2: e0c7 b.n 8001984 <debug_output+0x1ac>
*p++ = '$'; *p++ = 'P'; *p++ = ':';
80017f4: 2324 movs r3, #36 @ 0x24
80017f6: 243a movs r4, #58 @ 0x3a
80017f8: 4d65 ldr r5, [pc, #404] @ (8001990 <debug_output+0x1b8>)
p += debug_itoa(total_count, p);
80017fa: 4e66 ldr r6, [pc, #408] @ (8001994 <debug_output+0x1bc>)
80017fc: 4f66 ldr r7, [pc, #408] @ (8001998 <debug_output+0x1c0>)
last_debug_output_time = now;
80017fe: 6010 str r0, [r2, #0]
p += debug_itoa(total_count, p);
8001800: 0039 movs r1, r7
8001802: 6830 ldr r0, [r6, #0]
*p++ = '$'; *p++ = 'P'; *p++ = ':';
8001804: 702b strb r3, [r5, #0]
8001806: 332c adds r3, #44 @ 0x2c
8001808: 706b strb r3, [r5, #1]
800180a: 70ac strb r4, [r5, #2]
p += debug_itoa(total_count, p);
800180c: f7ff ff96 bl 800173c <debug_itoa>
8001810: 183f adds r7, r7, r0
*p++ = ':';
8001812: 1c7b adds r3, r7, #1
8001814: 703c strb r4, [r7, #0]
p += debug_itoa(target_count, p);
8001816: 4f61 ldr r7, [pc, #388] @ (800199c <debug_output+0x1c4>)
8001818: 0019 movs r1, r3
800181a: 6838 ldr r0, [r7, #0]
*p++ = ':';
800181c: 9301 str r3, [sp, #4]
p += debug_itoa(target_count, p);
800181e: f7ff ff8d bl 800173c <debug_itoa>
8001822: 9b01 ldr r3, [sp, #4]
8001824: 1818 adds r0, r3, r0
*p++ = ':';
8001826: 1c43 adds r3, r0, #1
8001828: 9301 str r3, [sp, #4]
800182a: 7004 strb r4, [r0, #0]
p += debug_itoa(target_count - total_count, p);
800182c: 6833 ldr r3, [r6, #0]
800182e: 6838 ldr r0, [r7, #0]
8001830: 9901 ldr r1, [sp, #4]
8001832: 1ac0 subs r0, r0, r3
8001834: f7ff ff82 bl 800173c <debug_itoa>
8001838: 9b01 ldr r3, [sp, #4]
*p++ = ','; *p++ = 'I'; *p++ = ':';
800183a: 272c movs r7, #44 @ 0x2c
p += debug_itoa(target_count - total_count, p);
800183c: 1818 adds r0, r3, r0
*p++ = ','; *p++ = 'I'; *p++ = ':';
800183e: 2349 movs r3, #73 @ 0x49
8001840: 7043 strb r3, [r0, #1]
p += debug_itoa(debug_pid_output, p);
8001842: 4b57 ldr r3, [pc, #348] @ (80019a0 <debug_output+0x1c8>)
*p++ = ','; *p++ = 'I'; *p++ = ':';
8001844: 1cc6 adds r6, r0, #3
8001846: 7007 strb r7, [r0, #0]
8001848: 7084 strb r4, [r0, #2]
p += debug_itoa(debug_pid_output, p);
800184a: 8818 ldrh r0, [r3, #0]
800184c: 0031 movs r1, r6
800184e: b200 sxth r0, r0
8001850: f7ff ff74 bl 800173c <debug_itoa>
*p++ = ','; *p++ = 'S'; *p++ = ':';
8001854: 2353 movs r3, #83 @ 0x53
p += debug_itoa(debug_pid_output, p);
8001856: 1830 adds r0, r6, r0
*p++ = ','; *p++ = 'S'; *p++ = ':';
8001858: 7043 strb r3, [r0, #1]
*p++ = '0' + feed_state; // State as single digit 0-9
800185a: 4b52 ldr r3, [pc, #328] @ (80019a4 <debug_output+0x1cc>)
*p++ = ','; *p++ = 'C'; *p++ = ':';
800185c: 0006 movs r6, r0
*p++ = '0' + feed_state; // State as single digit 0-9
800185e: 781b ldrb r3, [r3, #0]
*p++ = ','; *p++ = 'S'; *p++ = ':';
8001860: 7007 strb r7, [r0, #0]
*p++ = '0' + feed_state; // State as single digit 0-9
8001862: 3330 adds r3, #48 @ 0x30
8001864: 70c3 strb r3, [r0, #3]
*p++ = ','; *p++ = 'F'; *p++ = ':';
8001866: 2346 movs r3, #70 @ 0x46
8001868: 7143 strb r3, [r0, #5]
*p++ = '0' + is_initialized;
800186a: 4b4f ldr r3, [pc, #316] @ (80019a8 <debug_output+0x1d0>)
*p++ = ','; *p++ = 'S'; *p++ = ':';
800186c: 7084 strb r4, [r0, #2]
*p++ = '0' + is_initialized;
800186e: 781b ldrb r3, [r3, #0]
*p++ = ','; *p++ = 'F'; *p++ = ':';
8001870: 7107 strb r7, [r0, #4]
*p++ = '0' + is_initialized;
8001872: 3330 adds r3, #48 @ 0x30
8001874: 71c3 strb r3, [r0, #7]
*p++ = '0' + feed_in_progress;
8001876: 4b4d ldr r3, [pc, #308] @ (80019ac <debug_output+0x1d4>)
*p++ = ','; *p++ = 'F'; *p++ = ':';
8001878: 7184 strb r4, [r0, #6]
*p++ = '0' + feed_in_progress;
800187a: 781b ldrb r3, [r3, #0]
*p++ = ','; *p++ = 'C'; *p++ = ':';
800187c: 7247 strb r7, [r0, #9]
*p++ = '0' + feed_in_progress;
800187e: 3330 adds r3, #48 @ 0x30
8001880: 7203 strb r3, [r0, #8]
*p++ = ','; *p++ = 'C'; *p++ = ':';
8001882: 2343 movs r3, #67 @ 0x43
8001884: 7283 strb r3, [r0, #10]
p += debug_itoa(feed_ok_count, p);
8001886: 4b4a ldr r3, [pc, #296] @ (80019b0 <debug_output+0x1d8>)
*p++ = ','; *p++ = 'C'; *p++ = ':';
8001888: 72c4 strb r4, [r0, #11]
p += debug_itoa(feed_ok_count, p);
800188a: 8818 ldrh r0, [r3, #0]
*p++ = ','; *p++ = 'C'; *p++ = ':';
800188c: 360c adds r6, #12
p += debug_itoa(feed_ok_count, p);
800188e: 0031 movs r1, r6
8001890: b280 uxth r0, r0
8001892: f7ff ff53 bl 800173c <debug_itoa>
p += debug_itoa(feed_fail_count, p);
8001896: 4b47 ldr r3, [pc, #284] @ (80019b4 <debug_output+0x1dc>)
p += debug_itoa(feed_ok_count, p);
8001898: 1830 adds r0, r6, r0
*p++ = ':';
800189a: 1c46 adds r6, r0, #1
800189c: 7004 strb r4, [r0, #0]
p += debug_itoa(feed_fail_count, p);
800189e: 8818 ldrh r0, [r3, #0]
80018a0: 0031 movs r1, r6
80018a2: b280 uxth r0, r0
80018a4: f7ff ff4a bl 800173c <debug_itoa>
p += debug_itoa(brake_time_tenths, p);
80018a8: 4b43 ldr r3, [pc, #268] @ (80019b8 <debug_output+0x1e0>)
p += debug_itoa(feed_fail_count, p);
80018aa: 1830 adds r0, r6, r0
*p++ = ':';
80018ac: 1c46 adds r6, r0, #1
p += debug_itoa(brake_time_tenths, p);
80018ae: 0031 movs r1, r6
*p++ = ':';
80018b0: 7004 strb r4, [r0, #0]
p += debug_itoa(brake_time_tenths, p);
80018b2: 6818 ldr r0, [r3, #0]
80018b4: f7ff ff42 bl 800173c <debug_itoa>
p += debug_itoa(feed_retry_total, p);
80018b8: 4b40 ldr r3, [pc, #256] @ (80019bc <debug_output+0x1e4>)
p += debug_itoa(brake_time_tenths, p);
80018ba: 1830 adds r0, r6, r0
*p++ = ':';
80018bc: 1c46 adds r6, r0, #1
80018be: 7004 strb r4, [r0, #0]
p += debug_itoa(feed_retry_total, p);
80018c0: 8818 ldrh r0, [r3, #0]
80018c2: 0031 movs r1, r6
80018c4: b280 uxth r0, r0
80018c6: f7ff ff39 bl 800173c <debug_itoa>
*p++ = ','; *p++ = 'A'; *p++ = ':';
80018ca: 2341 movs r3, #65 @ 0x41
p += debug_itoa(feed_retry_total, p);
80018cc: 1836 adds r6, r6, r0
*p++ = ','; *p++ = 'A'; *p++ = ':';
80018ce: 7073 strb r3, [r6, #1]
p += debug_hex8(my_address, p);
80018d0: 4b3b ldr r3, [pc, #236] @ (80019c0 <debug_output+0x1e8>)
*p++ = ','; *p++ = 'A'; *p++ = ':';
80018d2: 7037 strb r7, [r6, #0]
80018d4: 70b4 strb r4, [r6, #2]
80018d6: 1cf1 adds r1, r6, #3
p += debug_hex8(my_address, p);
80018d8: 7818 ldrb r0, [r3, #0]
80018da: f7ff ff67 bl 80017ac <debug_hex8>
*p++ = ','; *p++ = 'R'; *p++ = ':';
80018de: 2352 movs r3, #82 @ 0x52
80018e0: 71b3 strb r3, [r6, #6]
80018e2: 0033 movs r3, r6
80018e4: 3308 adds r3, #8
80018e6: 9301 str r3, [sp, #4]
p += debug_itoa(drop_crc, p);
80018e8: 4b36 ldr r3, [pc, #216] @ (80019c4 <debug_output+0x1ec>)
*p++ = ','; *p++ = 'R'; *p++ = ':';
80018ea: 7177 strb r7, [r6, #5]
p += debug_itoa(drop_crc, p);
80018ec: 8818 ldrh r0, [r3, #0]
*p++ = ','; *p++ = 'R'; *p++ = ':';
80018ee: 71f4 strb r4, [r6, #7]
p += debug_itoa(drop_crc, p);
80018f0: 9901 ldr r1, [sp, #4]
80018f2: b280 uxth r0, r0
80018f4: f7ff ff22 bl 800173c <debug_itoa>
80018f8: 9b01 ldr r3, [sp, #4]
80018fa: 1818 adds r0, r3, r0
p += debug_itoa(msg_handled, p);
80018fc: 4b32 ldr r3, [pc, #200] @ (80019c8 <debug_output+0x1f0>)
*p++ = ':';
80018fe: 1c46 adds r6, r0, #1
8001900: 7004 strb r4, [r0, #0]
p += debug_itoa(msg_handled, p);
8001902: 8818 ldrh r0, [r3, #0]
8001904: 0031 movs r1, r6
8001906: b280 uxth r0, r0
8001908: f7ff ff18 bl 800173c <debug_itoa>
p += debug_itoa(uart_error_count, p);
800190c: 4b2f ldr r3, [pc, #188] @ (80019cc <debug_output+0x1f4>)
p += debug_itoa(msg_handled, p);
800190e: 1830 adds r0, r6, r0
*p++ = ':';
8001910: 1c46 adds r6, r0, #1
8001912: 7004 strb r4, [r0, #0]
p += debug_itoa(uart_error_count, p);
8001914: 8818 ldrh r0, [r3, #0]
8001916: 0031 movs r1, r6
8001918: b280 uxth r0, r0
800191a: f7ff ff0f bl 800173c <debug_itoa>
*p++ = ','; *p++ = 'T'; *p++ = ':';
800191e: 2354 movs r3, #84 @ 0x54
p += debug_itoa(uart_error_count, p);
8001920: 1830 adds r0, r6, r0
*p++ = ','; *p++ = 'T'; *p++ = ':';
8001922: 7007 strb r7, [r0, #0]
p += debug_itoa(my_addr_size, p);
8001924: 4f2a ldr r7, [pc, #168] @ (80019d0 <debug_output+0x1f8>)
*p++ = ','; *p++ = 'T'; *p++ = ':';
8001926: 1cc6 adds r6, r0, #3
8001928: 7084 strb r4, [r0, #2]
800192a: 7043 strb r3, [r0, #1]
p += debug_itoa(my_addr_size, p);
800192c: 7838 ldrb r0, [r7, #0]
800192e: 0031 movs r1, r6
8001930: b2c0 uxtb r0, r0
8001932: f7ff ff03 bl 800173c <debug_itoa>
8001936: 1830 adds r0, r6, r0
*p++ = ':';
8001938: 7004 strb r4, [r0, #0]
800193a: 2400 movs r4, #0
800193c: 1c46 adds r6, r0, #1
for (uint8_t i = 0; i < 8 && i < my_addr_size; i++)
800193e: 783a ldrb r2, [r7, #0]
8001940: b2e3 uxtb r3, r4
8001942: 429a cmp r2, r3
8001944: d909 bls.n 800195a <debug_output+0x182>
p += debug_hex8(my_addr_bytes[i], p);
8001946: 4b23 ldr r3, [pc, #140] @ (80019d4 <debug_output+0x1fc>)
8001948: 0031 movs r1, r6
800194a: 5d18 ldrb r0, [r3, r4]
for (uint8_t i = 0; i < 8 && i < my_addr_size; i++)
800194c: 3401 adds r4, #1
p += debug_hex8(my_addr_bytes[i], p);
800194e: b2c0 uxtb r0, r0
8001950: f7ff ff2c bl 80017ac <debug_hex8>
8001954: 3602 adds r6, #2
for (uint8_t i = 0; i < 8 && i < my_addr_size; i++)
8001956: 2c08 cmp r4, #8
8001958: d1f1 bne.n 800193e <debug_output+0x166>
*p++ = ':';
800195a: 233a movs r3, #58 @ 0x3a
800195c: 7033 strb r3, [r6, #0]
p += debug_hex8(my_addr_crc_exp, p);
800195e: 4b1e ldr r3, [pc, #120] @ (80019d8 <debug_output+0x200>)
*p++ = ':';
8001960: 1c71 adds r1, r6, #1
p += debug_hex8(my_addr_crc_exp, p);
8001962: 7818 ldrb r0, [r3, #0]
8001964: b2c0 uxtb r0, r0
8001966: f7ff ff21 bl 80017ac <debug_hex8>
*p++ = '*'; *p++ = '\r'; *p++ = '\n';
800196a: 232a movs r3, #42 @ 0x2a
800196c: 70f3 strb r3, [r6, #3]
800196e: 3b1d subs r3, #29
8001970: 7133 strb r3, [r6, #4]
8001972: 3b03 subs r3, #3
8001974: 7173 strb r3, [r6, #5]
8001976: 3606 adds r6, #6
HAL_UART_Transmit(&huart1, (uint8_t*)debug_tx_buffer, p - debug_tx_buffer, 10);
8001978: 1b72 subs r2, r6, r5
800197a: 0029 movs r1, r5
800197c: 4817 ldr r0, [pc, #92] @ (80019dc <debug_output+0x204>)
800197e: b292 uxth r2, r2
8001980: f003 f999 bl 8004cb6 <HAL_UART_Transmit>
}
8001984: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
8001986: 46c0 nop @ (mov r8, r8)
8001988: 20000000 .word 0x20000000
800198c: 200000e0 .word 0x200000e0
8001990: 2000007e .word 0x2000007e
8001994: 20000154 .word 0x20000154
8001998: 20000081 .word 0x20000081
800199c: 20000150 .word 0x20000150
80019a0: 2000007c .word 0x2000007c
80019a4: 20000118 .word 0x20000118
80019a8: 20000f86 .word 0x20000f86
80019ac: 20000121 .word 0x20000121
80019b0: 2000011e .word 0x2000011e
80019b4: 2000011c .word 0x2000011c
80019b8: 20000004 .word 0x20000004
80019bc: 2000011a .word 0x2000011a
80019c0: 20000020 .word 0x20000020
80019c4: 20000076 .word 0x20000076
80019c8: 20000072 .word 0x20000072
80019cc: 2000007a .word 0x2000007a
80019d0: 2000005e .word 0x2000005e
80019d4: 2000005f .word 0x2000005f
80019d8: 2000005d .word 0x2000005d
80019dc: 200010ec .word 0x200010ec
080019e0 <reset_position_if_needed>:
{
80019e0: b570 push {r4, r5, r6, lr}
if ((total_count % counts_per_mm) == 0 && feed_state == FEED_STATE_IDLE)
80019e2: 4d12 ldr r5, [pc, #72] @ (8001a2c <reset_position_if_needed+0x4c>)
80019e4: 4b12 ldr r3, [pc, #72] @ (8001a30 <reset_position_if_needed+0x50>)
80019e6: 6828 ldr r0, [r5, #0]
80019e8: 4a12 ldr r2, [pc, #72] @ (8001a34 <reset_position_if_needed+0x54>)
80019ea: 4343 muls r3, r0
80019ec: 189b adds r3, r3, r2
80019ee: 4a12 ldr r2, [pc, #72] @ (8001a38 <reset_position_if_needed+0x58>)
80019f0: 4293 cmp r3, r2
80019f2: d819 bhi.n 8001a28 <reset_position_if_needed+0x48>
80019f4: 4b11 ldr r3, [pc, #68] @ (8001a3c <reset_position_if_needed+0x5c>)
80019f6: 781b ldrb r3, [r3, #0]
80019f8: b2dc uxtb r4, r3
80019fa: 2b00 cmp r3, #0
80019fc: d114 bne.n 8001a28 <reset_position_if_needed+0x48>
int32_t mm_moved = total_count / counts_per_mm;
80019fe: 21e1 movs r1, #225 @ 0xe1
8001a00: f7fe fc20 bl 8000244 <__divsi3>
mm_position += mm_moved;
8001a04: 4e0e ldr r6, [pc, #56] @ (8001a40 <reset_position_if_needed+0x60>)
8001a06: 6833 ldr r3, [r6, #0]
8001a08: 181b adds r3, r3, r0
8001a0a: 6033 str r3, [r6, #0]
__ASM volatile ("cpsid i" : : : "memory");
8001a0c: b672 cpsid i
encoder_count_extra = 0;
8001a0e: 4b0d ldr r3, [pc, #52] @ (8001a44 <reset_position_if_needed+0x64>)
total_count = 0;
8001a10: 602c str r4, [r5, #0]
encoder_count_extra = 0;
8001a12: 601c str r4, [r3, #0]
htim3.Instance->CNT = 0;
8001a14: 4b0c ldr r3, [pc, #48] @ (8001a48 <reset_position_if_needed+0x68>)
8001a16: 681b ldr r3, [r3, #0]
8001a18: 625c str r4, [r3, #36] @ 0x24
encoder_previous = 0;
8001a1a: 4b0c ldr r3, [pc, #48] @ (8001a4c <reset_position_if_needed+0x6c>)
8001a1c: 801c strh r4, [r3, #0]
target_count = 0;
8001a1e: 4b0c ldr r3, [pc, #48] @ (8001a50 <reset_position_if_needed+0x70>)
8001a20: 601c str r4, [r3, #0]
feed_target_position = 0;
8001a22: 4b0c ldr r3, [pc, #48] @ (8001a54 <reset_position_if_needed+0x74>)
8001a24: 601c str r4, [r3, #0]
__ASM volatile ("cpsie i" : : : "memory");
8001a26: b662 cpsie i
}
8001a28: bd70 pop {r4, r5, r6, pc}
8001a2a: 46c0 nop @ (mov r8, r8)
8001a2c: 20000154 .word 0x20000154
8001a30: 87654321 .word 0x87654321
8001a34: 0091a2b3 .word 0x0091a2b3
8001a38: 01234566 .word 0x01234566
8001a3c: 20000118 .word 0x20000118
8001a40: 200000e4 .word 0x200000e4
8001a44: 20000f98 .word 0x20000f98
8001a48: 20001264 .word 0x20001264
8001a4c: 20000f94 .word 0x20000f94
8001a50: 20000150 .word 0x20000150
8001a54: 20000104 .word 0x20000104
08001a58 <main>:
{
8001a58: b5f0 push {r4, r5, r6, r7, lr}
8001a5a: b0a3 sub sp, #140 @ 0x8c
HAL_Init();
8001a5c: f000 ff28 bl 80028b0 <HAL_Init>
pid_init(&motor_pid,kp,ki,kd,i_min,i_max,PWM_MAX,pid_max_step);
8001a60: 4bd4 ldr r3, [pc, #848] @ (8001db4 <main+0x35c>)
8001a62: 4ed5 ldr r6, [pc, #852] @ (8001db8 <main+0x360>)
8001a64: 681d ldr r5, [r3, #0]
8001a66: 4bd5 ldr r3, [pc, #852] @ (8001dbc <main+0x364>)
int32_t integrator_min,
int32_t integrator_max,
int32_t out_max,
int32_t max_output_step)
{
pid->kp = kp;
8001a68: 6836 ldr r6, [r6, #0]
8001a6a: 681c ldr r4, [r3, #0]
8001a6c: 4bd4 ldr r3, [pc, #848] @ (8001dc0 <main+0x368>)
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001a6e: af15 add r7, sp, #84 @ 0x54
pid_init(&motor_pid,kp,ki,kd,i_min,i_max,PWM_MAX,pid_max_step);
8001a70: 6818 ldr r0, [r3, #0]
8001a72: 4bd4 ldr r3, [pc, #848] @ (8001dc4 <main+0x36c>)
8001a74: 6819 ldr r1, [r3, #0]
8001a76: 4bd4 ldr r3, [pc, #848] @ (8001dc8 <main+0x370>)
8001a78: 681a ldr r2, [r3, #0]
8001a7a: 4bd4 ldr r3, [pc, #848] @ (8001dcc <main+0x374>)
pid->integrator = 0;
pid->prev_error = 0;
pid->integrator_min = integrator_min;
pid->integrator_max = integrator_max;
8001a7c: 6199 str r1, [r3, #24]
pid->out_max = out_max;
8001a7e: 2196 movs r1, #150 @ 0x96
pid->ki = ki;
8001a80: 605d str r5, [r3, #4]
pid->integrator = 0;
8001a82: 2500 movs r5, #0
pid->out_max = out_max;
8001a84: 0109 lsls r1, r1, #4
pid->kp = kp;
8001a86: 601e str r6, [r3, #0]
pid->kd = kd;
8001a88: 609c str r4, [r3, #8]
pid->integrator_min = integrator_min;
8001a8a: 6158 str r0, [r3, #20]
pid->out_max = out_max;
8001a8c: 61d9 str r1, [r3, #28]
pid->max_output_step = max_output_step;
8001a8e: 621a str r2, [r3, #32]
pid->integrator = 0;
8001a90: 60dd str r5, [r3, #12]
pid->prev_error = 0;
8001a92: 611d str r5, [r3, #16]
pid->last_output = 0;
8001a94: 625d str r5, [r3, #36] @ 0x24
SystemClock_Config();
8001a96: f7fe fe71 bl 800077c <SystemClock_Config>
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001a9a: 2214 movs r2, #20
8001a9c: 0029 movs r1, r5
8001a9e: 0038 movs r0, r7
8001aa0: f003 fb74 bl 800518c <memset>
__HAL_RCC_GPIOF_CLK_ENABLE();
8001aa4: 2220 movs r2, #32
__HAL_RCC_GPIOA_CLK_ENABLE();
8001aa6: 2601 movs r6, #1
__HAL_RCC_GPIOF_CLK_ENABLE();
8001aa8: 4cc9 ldr r4, [pc, #804] @ (8001dd0 <main+0x378>)
HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
8001aaa: 20a0 movs r0, #160 @ 0xa0
__HAL_RCC_GPIOF_CLK_ENABLE();
8001aac: 6b63 ldr r3, [r4, #52] @ 0x34
HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
8001aae: 2141 movs r1, #65 @ 0x41
__HAL_RCC_GPIOF_CLK_ENABLE();
8001ab0: 4313 orrs r3, r2
8001ab2: 6363 str r3, [r4, #52] @ 0x34
8001ab4: 6b63 ldr r3, [r4, #52] @ 0x34
HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
8001ab6: 05c0 lsls r0, r0, #23
__HAL_RCC_GPIOF_CLK_ENABLE();
8001ab8: 4013 ands r3, r2
8001aba: 9303 str r3, [sp, #12]
8001abc: 9b03 ldr r3, [sp, #12]
__HAL_RCC_GPIOA_CLK_ENABLE();
8001abe: 6b63 ldr r3, [r4, #52] @ 0x34
__HAL_RCC_GPIOB_CLK_ENABLE();
8001ac0: 3a1e subs r2, #30
__HAL_RCC_GPIOA_CLK_ENABLE();
8001ac2: 4333 orrs r3, r6
8001ac4: 6363 str r3, [r4, #52] @ 0x34
8001ac6: 6b63 ldr r3, [r4, #52] @ 0x34
8001ac8: 4033 ands r3, r6
8001aca: 9304 str r3, [sp, #16]
8001acc: 9b04 ldr r3, [sp, #16]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001ace: 6b63 ldr r3, [r4, #52] @ 0x34
8001ad0: 4313 orrs r3, r2
8001ad2: 6363 str r3, [r4, #52] @ 0x34
8001ad4: 6b63 ldr r3, [r4, #52] @ 0x34
8001ad6: 4013 ands r3, r2
8001ad8: 9305 str r3, [sp, #20]
8001ada: 9b05 ldr r3, [sp, #20]
__HAL_RCC_GPIOC_CLK_ENABLE();
8001adc: 6b63 ldr r3, [r4, #52] @ 0x34
8001ade: 3202 adds r2, #2
8001ae0: 4313 orrs r3, r2
8001ae2: 6363 str r3, [r4, #52] @ 0x34
8001ae4: 6b63 ldr r3, [r4, #52] @ 0x34
8001ae6: 4013 ands r3, r2
8001ae8: 9306 str r3, [sp, #24]
HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
8001aea: 002a movs r2, r5
__HAL_RCC_GPIOC_CLK_ENABLE();
8001aec: 9b06 ldr r3, [sp, #24]
HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
8001aee: f001 fc11 bl 8003314 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(GPIOB, LED_R_Pin|LED_B_Pin|LED_G_Pin, GPIO_PIN_RESET);
8001af2: 002a movs r2, r5
8001af4: 2138 movs r1, #56 @ 0x38
8001af6: 48b7 ldr r0, [pc, #732] @ (8001dd4 <main+0x37c>)
8001af8: f001 fc0c bl 8003314 <HAL_GPIO_WritePin>
HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
8001afc: 20a0 movs r0, #160 @ 0xa0
GPIO_InitStruct.Pin = USART2_NRE_Pin;
8001afe: 9615 str r6, [sp, #84] @ 0x54
HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
8001b00: 0039 movs r1, r7
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001b02: 607e str r6, [r7, #4]
HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
8001b04: 05c0 lsls r0, r0, #23
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b06: 60bd str r5, [r7, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001b08: 60fd str r5, [r7, #12]
HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
8001b0a: f001 fb43 bl 8003194 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = ONEWIRE_Pin;
8001b0e: 2340 movs r3, #64 @ 0x40
HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
8001b10: 20a0 movs r0, #160 @ 0xa0
GPIO_InitStruct.Pin = ONEWIRE_Pin;
8001b12: 9315 str r3, [sp, #84] @ 0x54
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
8001b14: 3b2f subs r3, #47 @ 0x2f
HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
8001b16: 0039 movs r1, r7
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
8001b18: 607b str r3, [r7, #4]
HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
8001b1a: 05c0 lsls r0, r0, #23
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b1c: 60bd str r5, [r7, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001b1e: 60fd str r5, [r7, #12]
HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
8001b20: f001 fb38 bl 8003194 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = LED_R_Pin|LED_B_Pin|LED_G_Pin;
8001b24: 2338 movs r3, #56 @ 0x38
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001b26: 0039 movs r1, r7
GPIO_InitStruct.Pin = LED_R_Pin|LED_B_Pin|LED_G_Pin;
8001b28: 9315 str r3, [sp, #84] @ 0x54
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001b2a: 48aa ldr r0, [pc, #680] @ (8001dd4 <main+0x37c>)
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001b2c: 607e str r6, [r7, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b2e: 60bd str r5, [r7, #8]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001b30: 60fd str r5, [r7, #12]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001b32: f001 fb2f bl 8003194 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = SW2_Pin|SW1_Pin;
8001b36: 23c0 movs r3, #192 @ 0xc0
8001b38: 009b lsls r3, r3, #2
8001b3a: 9315 str r3, [sp, #84] @ 0x54
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
8001b3c: 4ba6 ldr r3, [pc, #664] @ (8001dd8 <main+0x380>)
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001b3e: 0039 movs r1, r7
GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
8001b40: 607b str r3, [r7, #4]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001b42: 48a4 ldr r0, [pc, #656] @ (8001dd4 <main+0x37c>)
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001b44: 60bd str r5, [r7, #8]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001b46: f001 fb25 bl 8003194 <HAL_GPIO_Init>
HAL_NVIC_SetPriority(EXTI4_15_IRQn, 0, 0);
8001b4a: 002a movs r2, r5
8001b4c: 0029 movs r1, r5
8001b4e: 2007 movs r0, #7
8001b50: f001 f928 bl 8002da4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(EXTI4_15_IRQn);
8001b54: 2007 movs r0, #7
8001b56: f001 f94f bl 8002df8 <HAL_NVIC_EnableIRQ>
__HAL_RCC_DMA1_CLK_ENABLE();
8001b5a: 6ba3 ldr r3, [r4, #56] @ 0x38
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
8001b5c: 002a movs r2, r5
__HAL_RCC_DMA1_CLK_ENABLE();
8001b5e: 4333 orrs r3, r6
8001b60: 63a3 str r3, [r4, #56] @ 0x38
8001b62: 6ba3 ldr r3, [r4, #56] @ 0x38
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
8001b64: 0029 movs r1, r5
__HAL_RCC_DMA1_CLK_ENABLE();
8001b66: 4033 ands r3, r6
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
8001b68: 2009 movs r0, #9
__HAL_RCC_DMA1_CLK_ENABLE();
8001b6a: 9302 str r3, [sp, #8]
8001b6c: 9b02 ldr r3, [sp, #8]
HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
8001b6e: f001 f919 bl 8002da4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
8001b72: 2009 movs r0, #9
8001b74: f001 f940 bl 8002df8 <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0);
8001b78: 002a movs r2, r5
8001b7a: 0029 movs r1, r5
8001b7c: 200a movs r0, #10
8001b7e: f001 f911 bl 8002da4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
8001b82: 200a movs r0, #10
8001b84: f001 f938 bl 8002df8 <HAL_NVIC_EnableIRQ>
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8001b88: 2210 movs r2, #16
8001b8a: 0029 movs r1, r5
8001b8c: a80a add r0, sp, #40 @ 0x28
8001b8e: f003 fafd bl 800518c <memset>
TIM_OC_InitTypeDef sConfigOC = {0};
8001b92: ae0e add r6, sp, #56 @ 0x38
TIM_MasterConfigTypeDef sMasterConfig = {0};
8001b94: 220c movs r2, #12
8001b96: 0029 movs r1, r5
8001b98: a807 add r0, sp, #28
8001b9a: f003 faf7 bl 800518c <memset>
TIM_OC_InitTypeDef sConfigOC = {0};
8001b9e: 221c movs r2, #28
8001ba0: 0029 movs r1, r5
8001ba2: 0030 movs r0, r6
8001ba4: f003 faf2 bl 800518c <memset>
TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
8001ba8: 0029 movs r1, r5
8001baa: 2234 movs r2, #52 @ 0x34
8001bac: 0038 movs r0, r7
8001bae: f003 faed bl 800518c <memset>
htim1.Init.Period = 2400;
8001bb2: 2196 movs r1, #150 @ 0x96
htim1.Instance = TIM1;
8001bb4: 4c89 ldr r4, [pc, #548] @ (8001ddc <main+0x384>)
8001bb6: 4b8a ldr r3, [pc, #552] @ (8001de0 <main+0x388>)
htim1.Init.Period = 2400;
8001bb8: 0109 lsls r1, r1, #4
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
8001bba: 0020 movs r0, r4
htim1.Instance = TIM1;
8001bbc: 6023 str r3, [r4, #0]
htim1.Init.Prescaler = 0;
8001bbe: 6065 str r5, [r4, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
8001bc0: 60a5 str r5, [r4, #8]
htim1.Init.Period = 2400;
8001bc2: 60e1 str r1, [r4, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001bc4: 6125 str r5, [r4, #16]
htim1.Init.RepetitionCounter = 0;
8001bc6: 6165 str r5, [r4, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001bc8: 61a5 str r5, [r4, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
8001bca: f002 f92b bl 8003e24 <HAL_TIM_Base_Init>
8001bce: 42a8 cmp r0, r5
8001bd0: d001 beq.n 8001bd6 <main+0x17e>
__ASM volatile ("cpsid i" : : : "memory");
8001bd2: b672 cpsid i
while (1)
8001bd4: e7fe b.n 8001bd4 <main+0x17c>
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001bd6: 2380 movs r3, #128 @ 0x80
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8001bd8: 0020 movs r0, r4
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001bda: 015b lsls r3, r3, #5
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8001bdc: a90a add r1, sp, #40 @ 0x28
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8001bde: 930a str r3, [sp, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8001be0: f002 fa98 bl 8004114 <HAL_TIM_ConfigClockSource>
8001be4: 2800 cmp r0, #0
8001be6: d001 beq.n 8001bec <main+0x194>
8001be8: b672 cpsid i
while (1)
8001bea: e7fe b.n 8001bea <main+0x192>
if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
8001bec: 0020 movs r0, r4
8001bee: f002 f943 bl 8003e78 <HAL_TIM_PWM_Init>
8001bf2: 2800 cmp r0, #0
8001bf4: d001 beq.n 8001bfa <main+0x1a2>
8001bf6: b672 cpsid i
while (1)
8001bf8: e7fe b.n 8001bf8 <main+0x1a0>
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001bfa: 9007 str r0, [sp, #28]
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
8001bfc: 9008 str r0, [sp, #32]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001bfe: 9009 str r0, [sp, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
8001c00: a907 add r1, sp, #28
8001c02: 0020 movs r0, r4
8001c04: f002 fbac bl 8004360 <HAL_TIMEx_MasterConfigSynchronization>
8001c08: 1e02 subs r2, r0, #0
8001c0a: d001 beq.n 8001c10 <main+0x1b8>
8001c0c: b672 cpsid i
while (1)
8001c0e: e7fe b.n 8001c0e <main+0x1b6>
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8001c10: 2360 movs r3, #96 @ 0x60
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8001c12: 0031 movs r1, r6
sConfigOC.OCMode = TIM_OCMODE_PWM1;
8001c14: 930e str r3, [sp, #56] @ 0x38
sConfigOC.Pulse = 0;
8001c16: 6070 str r0, [r6, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8001c18: 60b0 str r0, [r6, #8]
sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
8001c1a: 60f0 str r0, [r6, #12]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8001c1c: 6130 str r0, [r6, #16]
sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
8001c1e: 6170 str r0, [r6, #20]
sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
8001c20: 61b0 str r0, [r6, #24]
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
8001c22: 0020 movs r0, r4
8001c24: f002 f9e4 bl 8003ff0 <HAL_TIM_PWM_ConfigChannel>
8001c28: 2800 cmp r0, #0
8001c2a: d001 beq.n 8001c30 <main+0x1d8>
8001c2c: b672 cpsid i
while (1)
8001c2e: e7fe b.n 8001c2e <main+0x1d6>
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
8001c30: 2204 movs r2, #4
8001c32: 0031 movs r1, r6
8001c34: 0020 movs r0, r4
8001c36: f002 f9db bl 8003ff0 <HAL_TIM_PWM_ConfigChannel>
8001c3a: 2800 cmp r0, #0
8001c3c: d001 beq.n 8001c42 <main+0x1ea>
8001c3e: b672 cpsid i
while (1)
8001c40: e7fe b.n 8001c40 <main+0x1e8>
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
8001c42: 2208 movs r2, #8
8001c44: 0031 movs r1, r6
8001c46: 0020 movs r0, r4
8001c48: f002 f9d2 bl 8003ff0 <HAL_TIM_PWM_ConfigChannel>
8001c4c: 2800 cmp r0, #0
8001c4e: d001 beq.n 8001c54 <main+0x1fc>
8001c50: b672 cpsid i
while (1)
8001c52: e7fe b.n 8001c52 <main+0x1fa>
if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
8001c54: 220c movs r2, #12
8001c56: 0031 movs r1, r6
8001c58: 0020 movs r0, r4
8001c5a: f002 f9c9 bl 8003ff0 <HAL_TIM_PWM_ConfigChannel>
8001c5e: 2800 cmp r0, #0
8001c60: d001 beq.n 8001c66 <main+0x20e>
8001c62: b672 cpsid i
while (1)
8001c64: e7fe b.n 8001c64 <main+0x20c>
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8001c66: 2380 movs r3, #128 @ 0x80
8001c68: 019b lsls r3, r3, #6
sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
8001c6a: 9015 str r0, [sp, #84] @ 0x54
sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
8001c6c: 617b str r3, [r7, #20]
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
8001c6e: 2380 movs r3, #128 @ 0x80
8001c70: 049b lsls r3, r3, #18
sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
8001c72: 6078 str r0, [r7, #4]
sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
8001c74: 60b8 str r0, [r7, #8]
sBreakDeadTimeConfig.DeadTime = 0;
8001c76: 60f8 str r0, [r7, #12]
sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
8001c78: 6138 str r0, [r7, #16]
sBreakDeadTimeConfig.BreakFilter = 0;
8001c7a: 61b8 str r0, [r7, #24]
sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT;
8001c7c: 61f8 str r0, [r7, #28]
sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
8001c7e: 6238 str r0, [r7, #32]
sBreakDeadTimeConfig.Break2Filter = 0;
8001c80: 62b8 str r0, [r7, #40] @ 0x28
sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT;
8001c82: 62f8 str r0, [r7, #44] @ 0x2c
sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
8001c84: 6338 str r0, [r7, #48] @ 0x30
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
8001c86: 0039 movs r1, r7
8001c88: 0020 movs r0, r4
sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
8001c8a: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
8001c8c: f002 fb9c bl 80043c8 <HAL_TIMEx_ConfigBreakDeadTime>
8001c90: 1e05 subs r5, r0, #0
8001c92: d001 beq.n 8001c98 <main+0x240>
8001c94: b672 cpsid i
while (1)
8001c96: e7fe b.n 8001c96 <main+0x23e>
HAL_TIM_MspPostInit(&htim1);
8001c98: 0020 movs r0, r4
8001c9a: f000 fc93 bl 80025c4 <HAL_TIM_MspPostInit>
TIM_Encoder_InitTypeDef sConfig = {0};
8001c9e: 2220 movs r2, #32
8001ca0: 0029 movs r1, r5
8001ca2: a816 add r0, sp, #88 @ 0x58
8001ca4: f003 fa72 bl 800518c <memset>
TIM_MasterConfigTypeDef sMasterConfig = {0};
8001ca8: 220c movs r2, #12
8001caa: 0029 movs r1, r5
8001cac: 0030 movs r0, r6
8001cae: f003 fa6d bl 800518c <memset>
htim3.Instance = TIM3;
8001cb2: 4b4c ldr r3, [pc, #304] @ (8001de4 <main+0x38c>)
htim3.Init.Period = 65535;
8001cb4: 4c4c ldr r4, [pc, #304] @ (8001de8 <main+0x390>)
htim3.Instance = TIM3;
8001cb6: 9300 str r3, [sp, #0]
8001cb8: 9a00 ldr r2, [sp, #0]
8001cba: 4b4c ldr r3, [pc, #304] @ (8001dec <main+0x394>)
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
8001cbc: 0039 movs r1, r7
htim3.Instance = TIM3;
8001cbe: 6013 str r3, [r2, #0]
sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
8001cc0: 2303 movs r3, #3
8001cc2: 9315 str r3, [sp, #84] @ 0x54
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
8001cc4: 3b02 subs r3, #2
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
8001cc6: 0010 movs r0, r2
sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
8001cc8: 60bb str r3, [r7, #8]
sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
8001cca: 61bb str r3, [r7, #24]
htim3.Init.Prescaler = 0;
8001ccc: 6055 str r5, [r2, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
8001cce: 6095 str r5, [r2, #8]
htim3.Init.Period = 65535;
8001cd0: 60d4 str r4, [r2, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001cd2: 6115 str r5, [r2, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001cd4: 6195 str r5, [r2, #24]
if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
8001cd6: f002 f8f9 bl 8003ecc <HAL_TIM_Encoder_Init>
8001cda: 2800 cmp r0, #0
8001cdc: d001 beq.n 8001ce2 <main+0x28a>
8001cde: b672 cpsid i
while (1)
8001ce0: e7fe b.n 8001ce0 <main+0x288>
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001ce2: 2300 movs r3, #0
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8001ce4: 0031 movs r1, r6
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8001ce6: 930e str r3, [sp, #56] @ 0x38
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8001ce8: 9800 ldr r0, [sp, #0]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8001cea: 60b3 str r3, [r6, #8]
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8001cec: f002 fb38 bl 8004360 <HAL_TIMEx_MasterConfigSynchronization>
8001cf0: 2800 cmp r0, #0
8001cf2: d001 beq.n 8001cf8 <main+0x2a0>
8001cf4: b672 cpsid i
while (1)
8001cf6: e7fe b.n 8001cf6 <main+0x29e>
huart1.Instance = USART1;
8001cf8: 4d3d ldr r5, [pc, #244] @ (8001df0 <main+0x398>)
8001cfa: 4b3e ldr r3, [pc, #248] @ (8001df4 <main+0x39c>)
huart1.Init.Mode = UART_MODE_TX_RX;
8001cfc: 260c movs r6, #12
huart1.Instance = USART1;
8001cfe: 602b str r3, [r5, #0]
huart1.Init.BaudRate = 115200;
8001d00: 23e1 movs r3, #225 @ 0xe1
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8001d02: 60a8 str r0, [r5, #8]
huart1.Init.BaudRate = 115200;
8001d04: 025b lsls r3, r3, #9
huart1.Init.StopBits = UART_STOPBITS_1;
8001d06: 60e8 str r0, [r5, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8001d08: 6128 str r0, [r5, #16]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8001d0a: 61a8 str r0, [r5, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8001d0c: 61e8 str r0, [r5, #28]
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8001d0e: 6228 str r0, [r5, #32]
huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
8001d10: 6268 str r0, [r5, #36] @ 0x24
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8001d12: 62a8 str r0, [r5, #40] @ 0x28
if (HAL_UART_Init(&huart1) != HAL_OK)
8001d14: 0028 movs r0, r5
huart1.Init.BaudRate = 115200;
8001d16: 606b str r3, [r5, #4]
huart1.Init.Mode = UART_MODE_TX_RX;
8001d18: 616e str r6, [r5, #20]
if (HAL_UART_Init(&huart1) != HAL_OK)
8001d1a: f003 f89b bl 8004e54 <HAL_UART_Init>
8001d1e: 1e01 subs r1, r0, #0
8001d20: d001 beq.n 8001d26 <main+0x2ce>
8001d22: b672 cpsid i
while (1)
8001d24: e7fe b.n 8001d24 <main+0x2cc>
if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
8001d26: 0028 movs r0, r5
8001d28: f003 f9ae bl 8005088 <HAL_UARTEx_SetTxFifoThreshold>
8001d2c: 1e01 subs r1, r0, #0
8001d2e: d001 beq.n 8001d34 <main+0x2dc>
8001d30: b672 cpsid i
while (1)
8001d32: e7fe b.n 8001d32 <main+0x2da>
if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
8001d34: 0028 movs r0, r5
8001d36: f003 f9c7 bl 80050c8 <HAL_UARTEx_SetRxFifoThreshold>
8001d3a: 2800 cmp r0, #0
8001d3c: d001 beq.n 8001d42 <main+0x2ea>
8001d3e: b672 cpsid i
while (1)
8001d40: e7fe b.n 8001d40 <main+0x2e8>
if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
8001d42: 0028 movs r0, r5
8001d44: f003 f982 bl 800504c <HAL_UARTEx_DisableFifoMode>
8001d48: 1e01 subs r1, r0, #0
8001d4a: d001 beq.n 8001d50 <main+0x2f8>
8001d4c: b672 cpsid i
while (1)
8001d4e: e7fe b.n 8001d4e <main+0x2f6>
huart2.Instance = USART2;
8001d50: 4d29 ldr r5, [pc, #164] @ (8001df8 <main+0x3a0>)
8001d52: 4b2a ldr r3, [pc, #168] @ (8001dfc <main+0x3a4>)
huart2.Init.WordLength = UART_WORDLENGTH_8B;
8001d54: 60a8 str r0, [r5, #8]
huart2.Instance = USART2;
8001d56: 602b str r3, [r5, #0]
huart2.Init.BaudRate = 57600;
8001d58: 23e1 movs r3, #225 @ 0xe1
8001d5a: 021b lsls r3, r3, #8
8001d5c: 606b str r3, [r5, #4]
if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 31, 31) != HAL_OK)
8001d5e: 231f movs r3, #31
huart2.Init.StopBits = UART_STOPBITS_1;
8001d60: 60e8 str r0, [r5, #12]
huart2.Init.Parity = UART_PARITY_NONE;
8001d62: 6128 str r0, [r5, #16]
huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8001d64: 61a8 str r0, [r5, #24]
huart2.Init.OverSampling = UART_OVERSAMPLING_16;
8001d66: 61e8 str r0, [r5, #28]
huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8001d68: 6228 str r0, [r5, #32]
huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
8001d6a: 6268 str r0, [r5, #36] @ 0x24
huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
8001d6c: 62a8 str r0, [r5, #40] @ 0x28
if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 31, 31) != HAL_OK)
8001d6e: 001a movs r2, r3
8001d70: 0028 movs r0, r5
huart2.Init.Mode = UART_MODE_TX_RX;
8001d72: 616e str r6, [r5, #20]
if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 31, 31) != HAL_OK)
8001d74: f003 f920 bl 8004fb8 <HAL_RS485Ex_Init>
8001d78: 2800 cmp r0, #0
8001d7a: d001 beq.n 8001d80 <main+0x328>
8001d7c: b672 cpsid i
while (1)
8001d7e: e7fe b.n 8001d7e <main+0x326>
if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_2) != HAL_OK)
8001d80: 2180 movs r1, #128 @ 0x80
8001d82: 0028 movs r0, r5
8001d84: 05c9 lsls r1, r1, #23
8001d86: f003 f97f bl 8005088 <HAL_UARTEx_SetTxFifoThreshold>
8001d8a: 2800 cmp r0, #0
8001d8c: d001 beq.n 8001d92 <main+0x33a>
8001d8e: b672 cpsid i
while (1)
8001d90: e7fe b.n 8001d90 <main+0x338>
if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_2) != HAL_OK)
8001d92: 2180 movs r1, #128 @ 0x80
8001d94: 0028 movs r0, r5
8001d96: 04c9 lsls r1, r1, #19
8001d98: f003 f996 bl 80050c8 <HAL_UARTEx_SetRxFifoThreshold>
8001d9c: 2800 cmp r0, #0
8001d9e: d001 beq.n 8001da4 <main+0x34c>
8001da0: b672 cpsid i
while (1)
8001da2: e7fe b.n 8001da2 <main+0x34a>
if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK)
8001da4: 0028 movs r0, r5
8001da6: f003 f951 bl 800504c <HAL_UARTEx_DisableFifoMode>
8001daa: 1e03 subs r3, r0, #0
8001dac: d028 beq.n 8001e00 <main+0x3a8>
8001dae: b672 cpsid i
while (1)
8001db0: e7fe b.n 8001db0 <main+0x358>
8001db2: 46c0 nop @ (mov r8, r8)
8001db4: 20000018 .word 0x20000018
8001db8: 2000001c .word 0x2000001c
8001dbc: 20000014 .word 0x20000014
8001dc0: 20000010 .word 0x20000010
8001dc4: 2000000c .word 0x2000000c
8001dc8: 20000008 .word 0x20000008
8001dcc: 20000128 .word 0x20000128
8001dd0: 40021000 .word 0x40021000
8001dd4: 50000400 .word 0x50000400
8001dd8: 10210000 .word 0x10210000
8001ddc: 200012b0 .word 0x200012b0
8001de0: 40012c00 .word 0x40012c00
8001de4: 20001264 .word 0x20001264
8001de8: 0000ffff .word 0x0000ffff
8001dec: 40000400 .word 0x40000400
8001df0: 200010ec .word 0x200010ec
8001df4: 40013800 .word 0x40013800
8001df8: 20001058 .word 0x20001058
8001dfc: 40004400 .word 0x40004400
htim16.Instance = TIM16;
8001e00: 48d3 ldr r0, [pc, #844] @ (8002150 <main+0x6f8>)
8001e02: 4ad4 ldr r2, [pc, #848] @ (8002154 <main+0x6fc>)
htim16.Init.Prescaler = 48000-1;
8001e04: 4ed4 ldr r6, [pc, #848] @ (8002158 <main+0x700>)
htim16.Instance = TIM16;
8001e06: 6002 str r2, [r0, #0]
htim16.Init.Prescaler = 48000-1;
8001e08: 6046 str r6, [r0, #4]
htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
8001e0a: 6083 str r3, [r0, #8]
htim16.Init.Period = 65535;
8001e0c: 60c4 str r4, [r0, #12]
htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001e0e: 6103 str r3, [r0, #16]
htim16.Init.RepetitionCounter = 0;
8001e10: 6143 str r3, [r0, #20]
htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001e12: 6183 str r3, [r0, #24]
if (HAL_TIM_Base_Init(&htim16) != HAL_OK)
8001e14: f002 f806 bl 8003e24 <HAL_TIM_Base_Init>
8001e18: 2800 cmp r0, #0
8001e1a: d001 beq.n 8001e20 <main+0x3c8>
8001e1c: b672 cpsid i
while (1)
8001e1e: e7fe b.n 8001e1e <main+0x3c6>
htim17.Instance = TIM17;
8001e20: 48ce ldr r0, [pc, #824] @ (800215c <main+0x704>)
8001e22: 4bcf ldr r3, [pc, #828] @ (8002160 <main+0x708>)
htim17.Init.Prescaler = 48000-1;
8001e24: 6046 str r6, [r0, #4]
htim17.Instance = TIM17;
8001e26: 6003 str r3, [r0, #0]
htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
8001e28: 2300 movs r3, #0
htim17.Init.Period = 65535;
8001e2a: 60c4 str r4, [r0, #12]
htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
8001e2c: 6083 str r3, [r0, #8]
htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001e2e: 6103 str r3, [r0, #16]
htim17.Init.RepetitionCounter = 0;
8001e30: 6143 str r3, [r0, #20]
htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001e32: 6183 str r3, [r0, #24]
if (HAL_TIM_Base_Init(&htim17) != HAL_OK)
8001e34: f001 fff6 bl 8003e24 <HAL_TIM_Base_Init>
8001e38: 2800 cmp r0, #0
8001e3a: d001 beq.n 8001e40 <main+0x3e8>
8001e3c: b672 cpsid i
while (1)
8001e3e: e7fe b.n 8001e3e <main+0x3e6>
htim14.Instance = TIM14;
8001e40: 4bc8 ldr r3, [pc, #800] @ (8002164 <main+0x70c>)
8001e42: 9301 str r3, [sp, #4]
8001e44: 9a01 ldr r2, [sp, #4]
8001e46: 4bc8 ldr r3, [pc, #800] @ (8002168 <main+0x710>)
htim14.Init.CounterMode = TIM_COUNTERMODE_UP;
8001e48: 6090 str r0, [r2, #8]
htim14.Instance = TIM14;
8001e4a: 6013 str r3, [r2, #0]
htim14.Init.Prescaler = 480-1;
8001e4c: 23e0 movs r3, #224 @ 0xe0
8001e4e: 33ff adds r3, #255 @ 0xff
8001e50: 6053 str r3, [r2, #4]
htim14.Init.Period = 50;
8001e52: 2332 movs r3, #50 @ 0x32
htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8001e54: 6110 str r0, [r2, #16]
htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8001e56: 6190 str r0, [r2, #24]
if (HAL_TIM_Base_Init(&htim14) != HAL_OK)
8001e58: 0010 movs r0, r2
htim14.Init.Period = 50;
8001e5a: 60d3 str r3, [r2, #12]
if (HAL_TIM_Base_Init(&htim14) != HAL_OK)
8001e5c: f001 ffe2 bl 8003e24 <HAL_TIM_Base_Init>
8001e60: 1e06 subs r6, r0, #0
8001e62: d001 beq.n 8001e68 <main+0x410>
8001e64: b672 cpsid i
while (1)
8001e66: e7fe b.n 8001e66 <main+0x40e>
ADC_ChannelConfTypeDef sConfig = {0};
8001e68: 0001 movs r1, r0
8001e6a: 220c movs r2, #12
8001e6c: 0038 movs r0, r7
8001e6e: f003 f98d bl 800518c <memset>
hadc1.Instance = ADC1;
8001e72: 4cbe ldr r4, [pc, #760] @ (800216c <main+0x714>)
8001e74: 4bbe ldr r3, [pc, #760] @ (8002170 <main+0x718>)
if (HAL_ADC_Init(&hadc1) != HAL_OK)
8001e76: 0020 movs r0, r4
hadc1.Instance = ADC1;
8001e78: 6023 str r3, [r4, #0]
hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
8001e7a: 2380 movs r3, #128 @ 0x80
8001e7c: 05db lsls r3, r3, #23
8001e7e: 6063 str r3, [r4, #4]
hadc1.Init.ScanConvMode = ADC_SCAN_SEQ_FIXED;
8001e80: 2380 movs r3, #128 @ 0x80
8001e82: 061b lsls r3, r3, #24
8001e84: 6123 str r3, [r4, #16]
hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8001e86: 2304 movs r3, #4
8001e88: 6163 str r3, [r4, #20]
hadc1.Init.NbrOfConversion = 1;
8001e8a: 3b03 subs r3, #3
8001e8c: 61e3 str r3, [r4, #28]
hadc1.Init.DiscontinuousConvMode = DISABLE;
8001e8e: 18e3 adds r3, r4, r3
8001e90: 77de strb r6, [r3, #31]
hadc1.Init.DMAContinuousRequests = DISABLE;
8001e92: 0023 movs r3, r4
8001e94: 332c adds r3, #44 @ 0x2c
8001e96: 701e strb r6, [r3, #0]
hadc1.Init.OversamplingMode = DISABLE;
8001e98: 0023 movs r3, r4
8001e9a: 333c adds r3, #60 @ 0x3c
hadc1.Init.Resolution = ADC_RESOLUTION_12B;
8001e9c: 60a6 str r6, [r4, #8]
hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8001e9e: 60e6 str r6, [r4, #12]
hadc1.Init.LowPowerAutoWait = DISABLE;
8001ea0: 8326 strh r6, [r4, #24]
hadc1.Init.ContinuousConvMode = DISABLE;
8001ea2: 76a6 strb r6, [r4, #26]
hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8001ea4: 6266 str r6, [r4, #36] @ 0x24
hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8001ea6: 62a6 str r6, [r4, #40] @ 0x28
hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
8001ea8: 6326 str r6, [r4, #48] @ 0x30
hadc1.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_1CYCLE_5;
8001eaa: 6366 str r6, [r4, #52] @ 0x34
hadc1.Init.OversamplingMode = DISABLE;
8001eac: 701e strb r6, [r3, #0]
hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
8001eae: 64e6 str r6, [r4, #76] @ 0x4c
if (HAL_ADC_Init(&hadc1) != HAL_OK)
8001eb0: f000 fd44 bl 800293c <HAL_ADC_Init>
8001eb4: 2800 cmp r0, #0
8001eb6: d001 beq.n 8001ebc <main+0x464>
8001eb8: b672 cpsid i
while (1)
8001eba: e7fe b.n 8001eba <main+0x462>
sConfig.Channel = ADC_CHANNEL_7;
8001ebc: 4bad ldr r3, [pc, #692] @ (8002174 <main+0x71c>)
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8001ebe: 0039 movs r1, r7
sConfig.Channel = ADC_CHANNEL_7;
8001ec0: 9315 str r3, [sp, #84] @ 0x54
sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
8001ec2: 2301 movs r3, #1
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8001ec4: 0020 movs r0, r4
sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
8001ec6: 607b str r3, [r7, #4]
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8001ec8: f000 fe48 bl 8002b5c <HAL_ADC_ConfigChannel>
8001ecc: 2800 cmp r0, #0
8001ece: d001 beq.n 8001ed4 <main+0x47c>
8001ed0: b672 cpsid i
while (1)
8001ed2: e7fe b.n 8001ed2 <main+0x47a>
sConfig.Channel = ADC_CHANNEL_22;
8001ed4: 4ba8 ldr r3, [pc, #672] @ (8002178 <main+0x720>)
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8001ed6: 0020 movs r0, r4
8001ed8: 0039 movs r1, r7
sConfig.Channel = ADC_CHANNEL_22;
8001eda: 9315 str r3, [sp, #84] @ 0x54
if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
8001edc: f000 fe3e bl 8002b5c <HAL_ADC_ConfigChannel>
8001ee0: 1e04 subs r4, r0, #0
8001ee2: d001 beq.n 8001ee8 <main+0x490>
8001ee4: b672 cpsid i
while (1)
8001ee6: e7fe b.n 8001ee6 <main+0x48e>
*puuid = HAL_GetUIDw0();
8001ee8: f000 fd12 bl 8002910 <HAL_GetUIDw0>
8001eec: 4ea3 ldr r6, [pc, #652] @ (800217c <main+0x724>)
8001eee: 0a03 lsrs r3, r0, #8
8001ef0: 7030 strb r0, [r6, #0]
8001ef2: 7073 strb r3, [r6, #1]
8001ef4: 0c03 lsrs r3, r0, #16
8001ef6: 0e00 lsrs r0, r0, #24
8001ef8: 70b3 strb r3, [r6, #2]
8001efa: 70f0 strb r0, [r6, #3]
*(puuid+1) = HAL_GetUIDw1();
8001efc: f000 fd0e bl 800291c <HAL_GetUIDw1>
8001f00: 0a03 lsrs r3, r0, #8
8001f02: 7130 strb r0, [r6, #4]
8001f04: 7173 strb r3, [r6, #5]
8001f06: 0c03 lsrs r3, r0, #16
8001f08: 0e00 lsrs r0, r0, #24
8001f0a: 71b3 strb r3, [r6, #6]
8001f0c: 71f0 strb r0, [r6, #7]
*(puuid+2) = HAL_GetUIDw2();
8001f0e: f000 fd0b bl 8002928 <HAL_GetUIDw2>
8001f12: 0a03 lsrs r3, r0, #8
8001f14: 7230 strb r0, [r6, #8]
8001f16: 7273 strb r3, [r6, #9]
8001f18: 0c03 lsrs r3, r0, #16
8001f1a: 0e00 lsrs r0, r0, #24
8001f1c: 72f0 strb r0, [r6, #11]
HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL);
8001f1e: 213c movs r1, #60 @ 0x3c
8001f20: 9800 ldr r0, [sp, #0]
*(puuid+2) = HAL_GetUIDw2();
8001f22: 72b3 strb r3, [r6, #10]
HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL);
8001f24: f001 fe31 bl 8003b8a <HAL_TIM_Encoder_Start>
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1); // Feed motor
8001f28: 4e95 ldr r6, [pc, #596] @ (8002180 <main+0x728>)
8001f2a: 0021 movs r1, r4
8001f2c: 0030 movs r0, r6
8001f2e: f002 fa13 bl 8004358 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_2); // Feed motor
8001f32: 2104 movs r1, #4
8001f34: 0030 movs r0, r6
8001f36: f002 fa0f bl 8004358 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_3); // Peel motor
8001f3a: 2108 movs r1, #8
8001f3c: 0030 movs r0, r6
8001f3e: f002 fa0b bl 8004358 <HAL_TIM_PWM_Start>
HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_4); // Peel motor
8001f42: 210c movs r1, #12
8001f44: 0030 movs r0, r6
8001f46: f002 fa07 bl 8004358 <HAL_TIM_PWM_Start>
HAL_TIM_Base_Start_IT(&htim14);
8001f4a: 9801 ldr r0, [sp, #4]
8001f4c: f001 fdec bl 8003b28 <HAL_TIM_Base_Start_IT>
floor_address = read_floor_address();
8001f50: f7ff f938 bl 80011c4 <read_floor_address>
8001f54: 4b8b ldr r3, [pc, #556] @ (8002184 <main+0x72c>)
8001f56: 7018 strb r0, [r3, #0]
if (floor_address == FLOOR_ADDRESS_NOT_DETECTED)
8001f58: 4b8b ldr r3, [pc, #556] @ (8002188 <main+0x730>)
8001f5a: 28ff cmp r0, #255 @ 0xff
8001f5c: d16c bne.n 8002038 <main+0x5e0>
set_LED(1, 0, 0); // Red = EEPROM not detected
8001f5e: 0022 movs r2, r4
8001f60: 0021 movs r1, r4
floor_address_status = 0;
8001f62: 701c strb r4, [r3, #0]
set_LED(1, 0, 0); // Red = EEPROM not detected
8001f64: 38fe subs r0, #254 @ 0xfe
set_LED(0, 0, 1); // Blue = not programmed
8001f66: f7fe fd99 bl 8000a9c <set_LED>
for (uint8_t i = 0; i < MSG_BUF_COUNT; i++) msg_buf_empty[i] = 1;
8001f6a: 2401 movs r4, #1
{
8001f6c: 2300 movs r3, #0
for (uint8_t i = 0; i < MSG_BUF_COUNT; i++) msg_buf_empty[i] = 1;
8001f6e: 4a87 ldr r2, [pc, #540] @ (800218c <main+0x734>)
8001f70: 9200 str r2, [sp, #0]
8001f72: 9a00 ldr r2, [sp, #0]
8001f74: 54d4 strb r4, [r2, r3]
8001f76: 3301 adds r3, #1
8001f78: 2b36 cmp r3, #54 @ 0x36
8001f7a: d1fa bne.n 8001f72 <main+0x51a>
HAL_UARTEx_ReceiveToIdle_DMA (&huart2,DMA_buffer,64);
8001f7c: 2240 movs r2, #64 @ 0x40
8001f7e: 4984 ldr r1, [pc, #528] @ (8002190 <main+0x738>)
8001f80: 0028 movs r0, r5
8001f82: f003 f8c3 bl 800510c <HAL_UARTEx_ReceiveToIdle_DMA>
__HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT); // Disable half-transfer interrupt
8001f86: 2104 movs r1, #4
8001f88: 1d2b adds r3, r5, #4
8001f8a: 6fdb ldr r3, [r3, #124] @ 0x7c
8001f8c: 681a ldr r2, [r3, #0]
8001f8e: 6813 ldr r3, [r2, #0]
8001f90: 438b bics r3, r1
8001f92: 6013 str r3, [r2, #0]
__HAL_UART_ENABLE_IT(&huart2, UART_IT_ERR); // Enable error interrupt for overrun recovery
8001f94: 682b ldr r3, [r5, #0]
8001f96: 689a ldr r2, [r3, #8]
8001f98: 4314 orrs r4, r2
8001f9a: 609c str r4, [r3, #8]
uint8_t sw1_state = HAL_GPIO_ReadPin(SW1_GPIO_Port, SW1_Pin); // 1 = released, 0 = pressed
8001f9c: 2180 movs r1, #128 @ 0x80
8001f9e: 487d ldr r0, [pc, #500] @ (8002194 <main+0x73c>)
8001fa0: 0089 lsls r1, r1, #2
8001fa2: f001 f9b1 bl 8003308 <HAL_GPIO_ReadPin>
uint8_t sw2_state = HAL_GPIO_ReadPin(SW2_GPIO_Port, SW2_Pin);
8001fa6: 2180 movs r1, #128 @ 0x80
uint8_t sw1_state = HAL_GPIO_ReadPin(SW1_GPIO_Port, SW1_Pin); // 1 = released, 0 = pressed
8001fa8: 0006 movs r6, r0
uint8_t sw2_state = HAL_GPIO_ReadPin(SW2_GPIO_Port, SW2_Pin);
8001faa: 0049 lsls r1, r1, #1
8001fac: 4879 ldr r0, [pc, #484] @ (8002194 <main+0x73c>)
8001fae: f001 f9ab bl 8003308 <HAL_GPIO_ReadPin>
if (driving)
8001fb2: 4f79 ldr r7, [pc, #484] @ (8002198 <main+0x740>)
8001fb4: 783c ldrb r4, [r7, #0]
8001fb6: 2c00 cmp r4, #0
8001fb8: d06e beq.n 8002098 <main+0x640>
if ((driving_direction && sw2_state) || (!driving_direction && sw1_state))
8001fba: 4b78 ldr r3, [pc, #480] @ (800219c <main+0x744>)
8001fbc: 7819 ldrb r1, [r3, #0]
8001fbe: 2900 cmp r1, #0
8001fc0: d050 beq.n 8002064 <main+0x60c>
8001fc2: 2800 cmp r0, #0
8001fc4: d150 bne.n 8002068 <main+0x610>
else if (!drive_mode)
8001fc6: 4b76 ldr r3, [pc, #472] @ (80021a0 <main+0x748>)
8001fc8: 781b ldrb r3, [r3, #0]
8001fca: 2b00 cmp r3, #0
8001fcc: d107 bne.n 8001fde <main+0x586>
target_count = total_count + 10000;
8001fce: 4b75 ldr r3, [pc, #468] @ (80021a4 <main+0x74c>)
8001fd0: 4a75 ldr r2, [pc, #468] @ (80021a8 <main+0x750>)
8001fd2: 681b ldr r3, [r3, #0]
if (driving_direction)
8001fd4: 2900 cmp r1, #0
8001fd6: d05d beq.n 8002094 <main+0x63c>
target_count = total_count + 10000;
8001fd8: 4974 ldr r1, [pc, #464] @ (80021ac <main+0x754>)
target_count = total_count - 10000;
8001fda: 185b adds r3, r3, r1
8001fdc: 6013 str r3, [r2, #0]
feed_state_machine_update();
8001fde: f7fe fed1 bl 8000d84 <feed_state_machine_update>
peel_ramp_update();
8001fe2: f7fe fdb5 bl 8000b50 <peel_ramp_update>
debug_output();
8001fe6: f7ff fbf7 bl 80017d8 <debug_output>
if (feed_just_completed)
8001fea: 4b71 ldr r3, [pc, #452] @ (80021b0 <main+0x758>)
8001fec: 781a ldrb r2, [r3, #0]
8001fee: 2a00 cmp r2, #0
8001ff0: d00c beq.n 800200c <main+0x5b4>
feed_just_completed = 0;
8001ff2: 2100 movs r1, #0
8001ff4: 7019 strb r1, [r3, #0]
if (last_feed_status == STATUS_OK)
8001ff6: 4b6f ldr r3, [pc, #444] @ (80021b4 <main+0x75c>)
8001ff8: 7818 ldrb r0, [r3, #0]
8001ffa: 4288 cmp r0, r1
8001ffc: d000 beq.n 8002000 <main+0x5a8>
8001ffe: e1cc b.n 800239a <main+0x942>
set_LED(0, 0, 0); // Success - LED off
8002000: 0002 movs r2, r0
8002002: 0001 movs r1, r0
8002004: f7fe fd4a bl 8000a9c <set_LED>
reset_position_if_needed();
8002008: f7ff fcea bl 80019e0 <reset_position_if_needed>
uint16_t time2 = sw2_pressed ? htim17.Instance->CNT : 0;
800200c: 2400 movs r4, #0
msg_buf_empty[bi] = 1;
800200e: 2601 movs r6, #1
if (!msg_buf_empty[bi])
8002010: 9b00 ldr r3, [sp, #0]
8002012: 5d1b ldrb r3, [r3, r4]
8002014: b2df uxtb r7, r3
8002016: 2b00 cmp r3, #0
8002018: d10a bne.n 8002030 <main+0x5d8>
handleRS485Message(msg_buf[bi], msg_buf_size[bi]);
800201a: 4d67 ldr r5, [pc, #412] @ (80021b8 <main+0x760>)
800201c: 4b67 ldr r3, [pc, #412] @ (80021bc <main+0x764>)
800201e: 5d29 ldrb r1, [r5, r4]
8002020: 01a0 lsls r0, r4, #6
8002022: 18c0 adds r0, r0, r3
8002024: b2c9 uxtb r1, r1
8002026: f7ff f94d bl 80012c4 <handleRS485Message>
msg_buf_empty[bi] = 1;
800202a: 9b00 ldr r3, [sp, #0]
msg_buf_size[bi] = 0;
800202c: 552f strb r7, [r5, r4]
msg_buf_empty[bi] = 1;
800202e: 551e strb r6, [r3, r4]
for (uint8_t bi = 0; bi < MSG_BUF_COUNT; bi++)
8002030: 3401 adds r4, #1
8002032: 2c36 cmp r4, #54 @ 0x36
8002034: d1ec bne.n 8002010 <main+0x5b8>
8002036: e7b1 b.n 8001f9c <main+0x544>
else if (floor_address == FLOOR_ADDRESS_NOT_PROGRAMMED)
8002038: 2800 cmp r0, #0
800203a: d103 bne.n 8002044 <main+0x5ec>
floor_address_status = 1;
800203c: 2201 movs r2, #1
set_LED(0, 0, 1); // Blue = not programmed
800203e: 0001 movs r1, r0
floor_address_status = 1;
8002040: 701a strb r2, [r3, #0]
set_LED(0, 0, 1); // Blue = not programmed
8002042: e790 b.n 8001f66 <main+0x50e>
floor_address_status = 2;
8002044: 2202 movs r2, #2
8002046: 701a strb r2, [r3, #0]
my_address = floor_address;
8002048: 4b5d ldr r3, [pc, #372] @ (80021c0 <main+0x768>)
set_LED(0, 1, 0); // Green briefly = valid address
800204a: 0022 movs r2, r4
800204c: 2101 movs r1, #1
my_address = floor_address;
800204e: 7018 strb r0, [r3, #0]
set_LED(0, 1, 0); // Green briefly = valid address
8002050: 0020 movs r0, r4
8002052: f7fe fd23 bl 8000a9c <set_LED>
HAL_Delay(200);
8002056: 20c8 movs r0, #200 @ 0xc8
8002058: f000 fc48 bl 80028ec <HAL_Delay>
set_LED(0, 0, 0);
800205c: 0022 movs r2, r4
800205e: 0021 movs r1, r4
8002060: 0020 movs r0, r4
8002062: e780 b.n 8001f66 <main+0x50e>
if ((driving_direction && sw2_state) || (!driving_direction && sw1_state))
8002064: 2e00 cmp r6, #0
8002066: d0ae beq.n 8001fc6 <main+0x56e>
driving = 0;
8002068: 2400 movs r4, #0
halt_all();
800206a: f7fe fdcb bl 8000c04 <halt_all>
HAL_TIM_Base_Stop(&htim16);
800206e: 4838 ldr r0, [pc, #224] @ (8002150 <main+0x6f8>)
driving = 0;
8002070: 703c strb r4, [r7, #0]
HAL_TIM_Base_Stop(&htim16);
8002072: f001 fd43 bl 8003afc <HAL_TIM_Base_Stop>
HAL_TIM_Base_Stop(&htim17);
8002076: 4839 ldr r0, [pc, #228] @ (800215c <main+0x704>)
8002078: f001 fd40 bl 8003afc <HAL_TIM_Base_Stop>
sw1_pressed = 0;
800207c: 4b51 ldr r3, [pc, #324] @ (80021c4 <main+0x76c>)
800207e: 701c strb r4, [r3, #0]
sw2_pressed = 0;
8002080: 4b51 ldr r3, [pc, #324] @ (80021c8 <main+0x770>)
8002082: 701c strb r4, [r3, #0]
sw1_long_handled = 0;
8002084: 4b51 ldr r3, [pc, #324] @ (80021cc <main+0x774>)
8002086: 701c strb r4, [r3, #0]
sw2_long_handled = 0;
8002088: 4b51 ldr r3, [pc, #324] @ (80021d0 <main+0x778>)
800208a: 701c strb r4, [r3, #0]
set_LED(0, 0, 0);
800208c: 0022 movs r2, r4
set_LED(0, 0, 1); // Blue = tape mode
800208e: 0021 movs r1, r4
8002090: 0020 movs r0, r4
8002092: e038 b.n 8002106 <main+0x6ae>
target_count = total_count - 10000;
8002094: 494f ldr r1, [pc, #316] @ (80021d4 <main+0x77c>)
8002096: e7a0 b.n 8001fda <main+0x582>
else if (both_pressed_handled)
8002098: 4b4f ldr r3, [pc, #316] @ (80021d8 <main+0x780>)
800209a: 469c mov ip, r3
800209c: 781b ldrb r3, [r3, #0]
800209e: 2b00 cmp r3, #0
80020a0: d049 beq.n 8002136 <main+0x6de>
if (sw1_state && sw2_state)
80020a2: 2e00 cmp r6, #0
80020a4: d016 beq.n 80020d4 <main+0x67c>
80020a6: 2800 cmp r0, #0
80020a8: d014 beq.n 80020d4 <main+0x67c>
both_pressed_handled = 0;
80020aa: 4663 mov r3, ip
HAL_TIM_Base_Stop(&htim16);
80020ac: 4828 ldr r0, [pc, #160] @ (8002150 <main+0x6f8>)
both_pressed_handled = 0;
80020ae: 701c strb r4, [r3, #0]
HAL_TIM_Base_Stop(&htim16);
80020b0: f001 fd24 bl 8003afc <HAL_TIM_Base_Stop>
HAL_TIM_Base_Stop(&htim17);
80020b4: 4829 ldr r0, [pc, #164] @ (800215c <main+0x704>)
80020b6: f001 fd21 bl 8003afc <HAL_TIM_Base_Stop>
HAL_Delay(400);
80020ba: 20c8 movs r0, #200 @ 0xc8
sw1_pressed = 0;
80020bc: 4b41 ldr r3, [pc, #260] @ (80021c4 <main+0x76c>)
HAL_Delay(400);
80020be: 0040 lsls r0, r0, #1
sw1_pressed = 0;
80020c0: 701c strb r4, [r3, #0]
sw2_pressed = 0;
80020c2: 4b41 ldr r3, [pc, #260] @ (80021c8 <main+0x770>)
80020c4: 701c strb r4, [r3, #0]
sw1_long_handled = 0;
80020c6: 4b41 ldr r3, [pc, #260] @ (80021cc <main+0x774>)
80020c8: 701c strb r4, [r3, #0]
sw2_long_handled = 0;
80020ca: 4b41 ldr r3, [pc, #260] @ (80021d0 <main+0x778>)
80020cc: 701c strb r4, [r3, #0]
HAL_Delay(400);
80020ce: f000 fc0d bl 80028ec <HAL_Delay>
80020d2: e7db b.n 800208c <main+0x634>
uint32_t hold_time = HAL_GetTick() - both_pressed_start;
80020d4: f000 fc04 bl 80028e0 <HAL_GetTick>
80020d8: 4b40 ldr r3, [pc, #256] @ (80021dc <main+0x784>)
80020da: 681b ldr r3, [r3, #0]
80020dc: 1ac0 subs r0, r0, r3
if (hold_time > 2000 && hold_time < 2100)
80020de: 4b40 ldr r3, [pc, #256] @ (80021e0 <main+0x788>)
80020e0: 18c3 adds r3, r0, r3
80020e2: 2b62 cmp r3, #98 @ 0x62
80020e4: d802 bhi.n 80020ec <main+0x694>
show_version();
80020e6: f7fe fdc5 bl 8000c74 <show_version>
80020ea: e778 b.n 8001fde <main+0x586>
else if (hold_time > 4000 && hold_time < 6000)
80020ec: 4b3d ldr r3, [pc, #244] @ (80021e4 <main+0x78c>)
80020ee: 4a3e ldr r2, [pc, #248] @ (80021e8 <main+0x790>)
80020f0: 18c3 adds r3, r0, r3
80020f2: 4293 cmp r3, r2
80020f4: d80a bhi.n 800210c <main+0x6b4>
set_LED((hold_time / 100) % 2, 0, !((hold_time / 100) % 2));
80020f6: 2164 movs r1, #100 @ 0x64
80020f8: f7fe f81a bl 8000130 <__udivsi3>
80020fc: 2301 movs r3, #1
80020fe: 001a movs r2, r3
8002100: 2100 movs r1, #0
8002102: 4382 bics r2, r0
8002104: 4018 ands r0, r3
if (!driving) set_LED(0, 0, 0);
8002106: f7fe fcc9 bl 8000a9c <set_LED>
800210a: e768 b.n 8001fde <main+0x586>
else if (hold_time >= 6000)
800210c: 4b37 ldr r3, [pc, #220] @ (80021ec <main+0x794>)
800210e: 4298 cmp r0, r3
8002110: d800 bhi.n 8002114 <main+0x6bc>
8002112: e764 b.n 8001fde <main+0x586>
set_LED(1, 0, 1);
8002114: 2201 movs r2, #1
8002116: 2100 movs r1, #0
8002118: 0010 movs r0, r2
800211a: f7fe fcbf bl 8000a9c <set_LED>
HAL_Delay(100);
800211e: 2064 movs r0, #100 @ 0x64
8002120: f000 fbe4 bl 80028ec <HAL_Delay>
__ASM volatile ("dsb 0xF":::"memory");
8002124: f3bf 8f4f dsb sy
*/
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
{
__DSB(); /* Ensure all outstanding memory accesses included
buffered write are completed before reset */
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8002128: 4b31 ldr r3, [pc, #196] @ (80021f0 <main+0x798>)
800212a: 4a32 ldr r2, [pc, #200] @ (80021f4 <main+0x79c>)
800212c: 60da str r2, [r3, #12]
800212e: f3bf 8f4f dsb sy
SCB_AIRCR_SYSRESETREQ_Msk);
__DSB(); /* Ensure completion of memory access */
for(;;) /* wait until reset */
{
__NOP();
8002132: 46c0 nop @ (mov r8, r8)
for(;;) /* wait until reset */
8002134: e7fd b.n 8002132 <main+0x6da>
else if (sw1_pressed || sw2_pressed)
8002136: 4a23 ldr r2, [pc, #140] @ (80021c4 <main+0x76c>)
8002138: 7814 ldrb r4, [r2, #0]
800213a: 9201 str r2, [sp, #4]
800213c: 4a22 ldr r2, [pc, #136] @ (80021c8 <main+0x770>)
800213e: 7815 ldrb r5, [r2, #0]
8002140: 2c00 cmp r4, #0
8002142: d159 bne.n 80021f8 <main+0x7a0>
8002144: 2d00 cmp r5, #0
8002146: d100 bne.n 800214a <main+0x6f2>
8002148: e749 b.n 8001fde <main+0x586>
uint16_t time1 = sw1_pressed ? htim16.Instance->CNT : 0;
800214a: 0022 movs r2, r4
800214c: e05a b.n 8002204 <main+0x7ac>
800214e: 46c0 nop @ (mov r8, r8)
8002150: 200011cc .word 0x200011cc
8002154: 40014400 .word 0x40014400
8002158: 0000bb7f .word 0x0000bb7f
800215c: 20001180 .word 0x20001180
8002160: 40014800 .word 0x40014800
8002164: 20001218 .word 0x20001218
8002168: 40002000 .word 0x40002000
800216c: 200012fc .word 0x200012fc
8002170: 40012400 .word 0x40012400
8002174: 1c000080 .word 0x1c000080
8002178: 58400000 .word 0x58400000
800217c: 20000f87 .word 0x20000f87
8002180: 200012b0 .word 0x200012b0
8002184: 20000001 .word 0x20000001
8002188: 200000e8 .word 0x200000e8
800218c: 20000f50 .word 0x20000f50
8002190: 2000015a .word 0x2000015a
8002194: 50000400 .word 0x50000400
8002198: 200000f4 .word 0x200000f4
800219c: 200000f3 .word 0x200000f3
80021a0: 200000f5 .word 0x200000f5
80021a4: 20000154 .word 0x20000154
80021a8: 20000150 .word 0x20000150
80021ac: 00002710 .word 0x00002710
80021b0: 20000120 .word 0x20000120
80021b4: 20000122 .word 0x20000122
80021b8: 20000f1a .word 0x20000f1a
80021bc: 2000019a .word 0x2000019a
80021c0: 20000020 .word 0x20000020
80021c4: 20000f9d .word 0x20000f9d
80021c8: 20000f9c .word 0x20000f9c
80021cc: 200000f2 .word 0x200000f2
80021d0: 200000f1 .word 0x200000f1
80021d4: ffffd8f0 .word 0xffffd8f0
80021d8: 200000f0 .word 0x200000f0
80021dc: 200000ec .word 0x200000ec
80021e0: fffff82f .word 0xfffff82f
80021e4: fffff05f .word 0xfffff05f
80021e8: 000007ce .word 0x000007ce
80021ec: 0000176f .word 0x0000176f
80021f0: e000ed00 .word 0xe000ed00
80021f4: 05fa0004 .word 0x05fa0004
80021f8: 4a6a ldr r2, [pc, #424] @ (80023a4 <main+0x94c>)
80021fa: 6812 ldr r2, [r2, #0]
80021fc: 6a52 ldr r2, [r2, #36] @ 0x24
80021fe: b292 uxth r2, r2
uint16_t time2 = sw2_pressed ? htim17.Instance->CNT : 0;
8002200: 2d00 cmp r5, #0
8002202: d003 beq.n 800220c <main+0x7b4>
8002204: 4b68 ldr r3, [pc, #416] @ (80023a8 <main+0x950>)
8002206: 681b ldr r3, [r3, #0]
8002208: 6a5b ldr r3, [r3, #36] @ 0x24
800220a: b29b uxth r3, r3
uint16_t max_time = (time1 > time2) ? time1 : time2;
800220c: 1c11 adds r1, r2, #0
800220e: 429a cmp r2, r3
8002210: d200 bcs.n 8002214 <main+0x7bc>
8002212: 1c19 adds r1, r3, #0
if (max_time < 100)
8002214: b289 uxth r1, r1
8002216: 2963 cmp r1, #99 @ 0x63
8002218: d800 bhi.n 800221c <main+0x7c4>
800221a: e6e0 b.n 8001fde <main+0x586>
else if (sw1_pressed && sw2_pressed && !sw1_state && !sw2_state)
800221c: 2c00 cmp r4, #0
800221e: d061 beq.n 80022e4 <main+0x88c>
8002220: 2d00 cmp r5, #0
8002222: d017 beq.n 8002254 <main+0x7fc>
8002224: 0034 movs r4, r6
8002226: 4304 orrs r4, r0
8002228: b2e4 uxtb r4, r4
800222a: 2c00 cmp r4, #0
800222c: d000 beq.n 8002230 <main+0x7d8>
800222e: e09f b.n 8002370 <main+0x918>
both_pressed_handled = 1;
8002230: 4663 mov r3, ip
8002232: 2501 movs r5, #1
8002234: 701d strb r5, [r3, #0]
both_pressed_start = HAL_GetTick();
8002236: f000 fb53 bl 80028e0 <HAL_GetTick>
800223a: 4b5c ldr r3, [pc, #368] @ (80023ac <main+0x954>)
800223c: 6018 str r0, [r3, #0]
if (drive_mode)
800223e: 4b5c ldr r3, [pc, #368] @ (80023b0 <main+0x958>)
8002240: 781a ldrb r2, [r3, #0]
8002242: 2a00 cmp r2, #0
8002244: d002 beq.n 800224c <main+0x7f4>
set_LED(0, 0, 1); // Blue = tape mode
8002246: 002a movs r2, r5
drive_mode = 0;
8002248: 701c strb r4, [r3, #0]
set_LED(0, 0, 1); // Blue = tape mode
800224a: e720 b.n 800208e <main+0x636>
set_LED(1, 1, 0); // Yellow = peel mode
800224c: 0029 movs r1, r5
800224e: 0028 movs r0, r5
drive_mode = 1;
8002250: 701d strb r5, [r3, #0]
set_LED(1, 1, 0); // Yellow = peel mode
8002252: e758 b.n 8002106 <main+0x6ae>
if (!sw1_state && time1 > 2000 && !sw1_long_handled)
8002254: 2e00 cmp r6, #0
8002256: d120 bne.n 800229a <main+0x842>
8002258: 23fa movs r3, #250 @ 0xfa
800225a: 00db lsls r3, r3, #3
800225c: 429a cmp r2, r3
800225e: d800 bhi.n 8002262 <main+0x80a>
8002260: e6bd b.n 8001fde <main+0x586>
8002262: 4b54 ldr r3, [pc, #336] @ (80023b4 <main+0x95c>)
8002264: 781a ldrb r2, [r3, #0]
8002266: 2a00 cmp r2, #0
8002268: d000 beq.n 800226c <main+0x814>
800226a: e6b8 b.n 8001fde <main+0x586>
sw1_long_handled = 1;
800226c: 2001 movs r0, #1
set_LED(1, 1, 1);
800226e: 0002 movs r2, r0
8002270: 0001 movs r1, r0
sw1_long_handled = 1;
8002272: 7018 strb r0, [r3, #0]
set_LED(1, 1, 1);
8002274: f7fe fc12 bl 8000a9c <set_LED>
if (drive_mode)
8002278: 4b4d ldr r3, [pc, #308] @ (80023b0 <main+0x958>)
800227a: 781b ldrb r3, [r3, #0]
800227c: 2b00 cmp r3, #0
800227e: d008 beq.n 8002292 <main+0x83a>
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
8002280: 4b4d ldr r3, [pc, #308] @ (80023b8 <main+0x960>)
8002282: 4a4e ldr r2, [pc, #312] @ (80023bc <main+0x964>)
8002284: 801a strh r2, [r3, #0]
driving = 1;
8002286: 2301 movs r3, #1
driving_direction = 0;
8002288: 2200 movs r2, #0
driving = 1;
800228a: 703b strb r3, [r7, #0]
driving_direction = 0;
800228c: 4b4c ldr r3, [pc, #304] @ (80023c0 <main+0x968>)
800228e: 701a strb r2, [r3, #0]
8002290: e6a5 b.n 8001fde <main+0x586>
drive_continuous(0);
8002292: 0028 movs r0, r5
8002294: f7fe fca2 bl 8000bdc <drive_continuous>
8002298: e7f5 b.n 8002286 <main+0x82e>
else if (sw1_state && time1 <= 2000 && time1 > 100)
800229a: 3a65 subs r2, #101 @ 0x65
800229c: 4b49 ldr r3, [pc, #292] @ (80023c4 <main+0x96c>)
800229e: b292 uxth r2, r2
80022a0: 4e40 ldr r6, [pc, #256] @ (80023a4 <main+0x94c>)
80022a2: 4c44 ldr r4, [pc, #272] @ (80023b4 <main+0x95c>)
80022a4: 429a cmp r2, r3
80022a6: d80f bhi.n 80022c8 <main+0x870>
set_LED(1, 1, 1);
80022a8: 2201 movs r2, #1
80022aa: 0011 movs r1, r2
80022ac: 0010 movs r0, r2
80022ae: f7fe fbf5 bl 8000a9c <set_LED>
start_feed(20, 0);
80022b2: 0029 movs r1, r5
80022b4: 2014 movs r0, #20
80022b6: f7fe fcef bl 8000c98 <start_feed>
HAL_TIM_Base_Stop(&htim16);
80022ba: 0030 movs r0, r6
80022bc: f001 fc1e bl 8003afc <HAL_TIM_Base_Stop>
sw1_pressed = 0;
80022c0: 4b41 ldr r3, [pc, #260] @ (80023c8 <main+0x970>)
sw1_long_handled = 0;
80022c2: 7025 strb r5, [r4, #0]
sw1_pressed = 0;
80022c4: 701d strb r5, [r3, #0]
sw1_long_handled = 0;
80022c6: e68a b.n 8001fde <main+0x586>
HAL_TIM_Base_Stop(&htim16);
80022c8: 0030 movs r0, r6
80022ca: f001 fc17 bl 8003afc <HAL_TIM_Base_Stop>
sw1_pressed = 0;
80022ce: 9b01 ldr r3, [sp, #4]
sw1_long_handled = 0;
80022d0: 7025 strb r5, [r4, #0]
sw1_pressed = 0;
80022d2: 701d strb r5, [r3, #0]
if (!driving) set_LED(0, 0, 0);
80022d4: 783b ldrb r3, [r7, #0]
80022d6: 2b00 cmp r3, #0
80022d8: d000 beq.n 80022dc <main+0x884>
80022da: e680 b.n 8001fde <main+0x586>
80022dc: 2200 movs r2, #0
80022de: 0011 movs r1, r2
80022e0: 0010 movs r0, r2
80022e2: e710 b.n 8002106 <main+0x6ae>
else if (sw2_pressed && !sw1_pressed)
80022e4: 2d00 cmp r5, #0
80022e6: d043 beq.n 8002370 <main+0x918>
if (!sw2_state && time2 > 2000 && !sw2_long_handled)
80022e8: 2800 cmp r0, #0
80022ea: d123 bne.n 8002334 <main+0x8dc>
80022ec: 22fa movs r2, #250 @ 0xfa
80022ee: 00d2 lsls r2, r2, #3
80022f0: 4293 cmp r3, r2
80022f2: d800 bhi.n 80022f6 <main+0x89e>
80022f4: e673 b.n 8001fde <main+0x586>
80022f6: 4b35 ldr r3, [pc, #212] @ (80023cc <main+0x974>)
80022f8: 781a ldrb r2, [r3, #0]
80022fa: 2a00 cmp r2, #0
80022fc: d000 beq.n 8002300 <main+0x8a8>
80022fe: e66e b.n 8001fde <main+0x586>
sw2_long_handled = 1;
8002300: 3001 adds r0, #1
set_LED(1, 1, 1);
8002302: 0002 movs r2, r0
8002304: 0001 movs r1, r0
sw2_long_handled = 1;
8002306: 7018 strb r0, [r3, #0]
set_LED(1, 1, 1);
8002308: f7fe fbc8 bl 8000a9c <set_LED>
if (drive_mode)
800230c: 4b28 ldr r3, [pc, #160] @ (80023b0 <main+0x958>)
800230e: 781b ldrb r3, [r3, #0]
8002310: 2b00 cmp r3, #0
8002312: d008 beq.n 8002326 <main+0x8ce>
peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
8002314: 2296 movs r2, #150 @ 0x96
8002316: 4b28 ldr r3, [pc, #160] @ (80023b8 <main+0x960>)
8002318: 0112 lsls r2, r2, #4
800231a: 801a strh r2, [r3, #0]
driving = 1;
800231c: 2301 movs r3, #1
driving_direction = 1;
800231e: 4a28 ldr r2, [pc, #160] @ (80023c0 <main+0x968>)
driving = 1;
8002320: 703b strb r3, [r7, #0]
sw2_long_handled = 0;
8002322: 7013 strb r3, [r2, #0]
8002324: e65b b.n 8001fde <main+0x586>
target_count = total_count + 10000;
8002326: 4b2a ldr r3, [pc, #168] @ (80023d0 <main+0x978>)
8002328: 492a ldr r1, [pc, #168] @ (80023d4 <main+0x97c>)
800232a: 681b ldr r3, [r3, #0]
800232c: 4a2a ldr r2, [pc, #168] @ (80023d8 <main+0x980>)
800232e: 185b adds r3, r3, r1
8002330: 6013 str r3, [r2, #0]
}
8002332: e7f3 b.n 800231c <main+0x8c4>
8002334: 491c ldr r1, [pc, #112] @ (80023a8 <main+0x950>)
else if (sw2_state && time2 <= 2000 && time2 > 100)
8002336: 3b65 subs r3, #101 @ 0x65
8002338: 4a22 ldr r2, [pc, #136] @ (80023c4 <main+0x96c>)
800233a: b29b uxth r3, r3
800233c: 4e27 ldr r6, [pc, #156] @ (80023dc <main+0x984>)
800233e: 4d23 ldr r5, [pc, #140] @ (80023cc <main+0x974>)
8002340: 9101 str r1, [sp, #4]
8002342: 4293 cmp r3, r2
8002344: d80e bhi.n 8002364 <main+0x90c>
set_LED(1, 1, 1);
8002346: 2201 movs r2, #1
8002348: 0011 movs r1, r2
800234a: 0010 movs r0, r2
800234c: f7fe fba6 bl 8000a9c <set_LED>
start_feed(20, 1);
8002350: 2101 movs r1, #1
8002352: 2014 movs r0, #20
8002354: f7fe fca0 bl 8000c98 <start_feed>
HAL_TIM_Base_Stop(&htim17);
8002358: 9801 ldr r0, [sp, #4]
800235a: f001 fbcf bl 8003afc <HAL_TIM_Base_Stop>
sw2_pressed = 0;
800235e: 7034 strb r4, [r6, #0]
sw2_long_handled = 0;
8002360: 702c strb r4, [r5, #0]
8002362: e63c b.n 8001fde <main+0x586>
HAL_TIM_Base_Stop(&htim17);
8002364: 9801 ldr r0, [sp, #4]
8002366: f001 fbc9 bl 8003afc <HAL_TIM_Base_Stop>
sw2_pressed = 0;
800236a: 7034 strb r4, [r6, #0]
sw2_long_handled = 0;
800236c: 702c strb r4, [r5, #0]
if (!driving) set_LED(0, 0, 0);
800236e: e7b1 b.n 80022d4 <main+0x87c>
else if (sw1_state && sw2_state)
8002370: 2e00 cmp r6, #0
8002372: d100 bne.n 8002376 <main+0x91e>
8002374: e633 b.n 8001fde <main+0x586>
8002376: 2800 cmp r0, #0
8002378: d100 bne.n 800237c <main+0x924>
800237a: e630 b.n 8001fde <main+0x586>
HAL_TIM_Base_Stop(&htim16);
800237c: 4809 ldr r0, [pc, #36] @ (80023a4 <main+0x94c>)
800237e: f001 fbbd bl 8003afc <HAL_TIM_Base_Stop>
HAL_TIM_Base_Stop(&htim17);
8002382: 4809 ldr r0, [pc, #36] @ (80023a8 <main+0x950>)
8002384: f001 fbba bl 8003afc <HAL_TIM_Base_Stop>
sw1_pressed = 0;
8002388: 2300 movs r3, #0
800238a: 9a01 ldr r2, [sp, #4]
800238c: 7013 strb r3, [r2, #0]
sw2_pressed = 0;
800238e: 4a13 ldr r2, [pc, #76] @ (80023dc <main+0x984>)
8002390: 7013 strb r3, [r2, #0]
sw1_long_handled = 0;
8002392: 4a08 ldr r2, [pc, #32] @ (80023b4 <main+0x95c>)
8002394: 7013 strb r3, [r2, #0]
sw2_long_handled = 0;
8002396: 4a0d ldr r2, [pc, #52] @ (80023cc <main+0x974>)
8002398: e7c3 b.n 8002322 <main+0x8ca>
set_LED(1, 0, 0); // Error - LED red
800239a: 000a movs r2, r1
800239c: 2001 movs r0, #1
800239e: f7fe fb7d bl 8000a9c <set_LED>
80023a2: e633 b.n 800200c <main+0x5b4>
80023a4: 200011cc .word 0x200011cc
80023a8: 20001180 .word 0x20001180
80023ac: 200000ec .word 0x200000ec
80023b0: 200000f5 .word 0x200000f5
80023b4: 200000f2 .word 0x200000f2
80023b8: 200000fe .word 0x200000fe
80023bc: fffff6a0 .word 0xfffff6a0
80023c0: 200000f3 .word 0x200000f3
80023c4: 0000076b .word 0x0000076b
80023c8: 20000f9d .word 0x20000f9d
80023cc: 200000f1 .word 0x200000f1
80023d0: 20000154 .word 0x20000154
80023d4: 00002710 .word 0x00002710
80023d8: 20000150 .word 0x20000150
80023dc: 20000f9c .word 0x20000f9c
080023e0 <Error_Handler>:
__ASM volatile ("cpsid i" : : : "memory");
80023e0: b672 cpsid i
while (1)
80023e2: e7fe b.n 80023e2 <Error_Handler+0x2>
080023e4 <HAL_MspInit>:
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
80023e4: 2101 movs r1, #1
80023e6: 4b0a ldr r3, [pc, #40] @ (8002410 <HAL_MspInit+0x2c>)
{
80023e8: b082 sub sp, #8
__HAL_RCC_SYSCFG_CLK_ENABLE();
80023ea: 6c1a ldr r2, [r3, #64] @ 0x40
80023ec: 430a orrs r2, r1
80023ee: 641a str r2, [r3, #64] @ 0x40
80023f0: 6c1a ldr r2, [r3, #64] @ 0x40
80023f2: 400a ands r2, r1
__HAL_RCC_PWR_CLK_ENABLE();
80023f4: 2180 movs r1, #128 @ 0x80
__HAL_RCC_SYSCFG_CLK_ENABLE();
80023f6: 9200 str r2, [sp, #0]
80023f8: 9a00 ldr r2, [sp, #0]
__HAL_RCC_PWR_CLK_ENABLE();
80023fa: 6bda ldr r2, [r3, #60] @ 0x3c
80023fc: 0549 lsls r1, r1, #21
80023fe: 430a orrs r2, r1
8002400: 63da str r2, [r3, #60] @ 0x3c
8002402: 6bdb ldr r3, [r3, #60] @ 0x3c
8002404: 400b ands r3, r1
8002406: 9301 str r3, [sp, #4]
8002408: 9b01 ldr r3, [sp, #4]
/* System interrupt init*/
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
800240a: b002 add sp, #8
800240c: 4770 bx lr
800240e: 46c0 nop @ (mov r8, r8)
8002410: 40021000 .word 0x40021000
08002414 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
8002414: b530 push {r4, r5, lr}
8002416: 0004 movs r4, r0
8002418: b091 sub sp, #68 @ 0x44
GPIO_InitTypeDef GPIO_InitStruct = {0};
800241a: 2214 movs r2, #20
800241c: 2100 movs r1, #0
800241e: a804 add r0, sp, #16
8002420: f002 feb4 bl 800518c <memset>
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8002424: 221c movs r2, #28
8002426: 2100 movs r1, #0
8002428: a809 add r0, sp, #36 @ 0x24
800242a: f002 feaf bl 800518c <memset>
if(hadc->Instance==ADC1)
800242e: 4b1e ldr r3, [pc, #120] @ (80024a8 <HAL_ADC_MspInit+0x94>)
8002430: 6822 ldr r2, [r4, #0]
8002432: 429a cmp r2, r3
8002434: d136 bne.n 80024a4 <HAL_ADC_MspInit+0x90>
/* USER CODE END ADC1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
8002436: 2320 movs r3, #32
PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8002438: a809 add r0, sp, #36 @ 0x24
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
800243a: 9309 str r3, [sp, #36] @ 0x24
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
800243c: f001 f9c4 bl 80037c8 <HAL_RCCEx_PeriphCLKConfig>
8002440: 2800 cmp r0, #0
8002442: d001 beq.n 8002448 <HAL_ADC_MspInit+0x34>
{
Error_Handler();
8002444: f7ff ffcc bl 80023e0 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_ADC_CLK_ENABLE();
8002448: 2180 movs r1, #128 @ 0x80
800244a: 4b18 ldr r3, [pc, #96] @ (80024ac <HAL_ADC_MspInit+0x98>)
800244c: 0349 lsls r1, r1, #13
800244e: 6c1a ldr r2, [r3, #64] @ 0x40
PB12 ------> ADC1_IN22
*/
GPIO_InitStruct.Pin = IPROP_PEEL_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
8002450: 20a0 movs r0, #160 @ 0xa0
__HAL_RCC_ADC_CLK_ENABLE();
8002452: 430a orrs r2, r1
8002454: 641a str r2, [r3, #64] @ 0x40
8002456: 6c1a ldr r2, [r3, #64] @ 0x40
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8002458: 2503 movs r5, #3
__HAL_RCC_ADC_CLK_ENABLE();
800245a: 400a ands r2, r1
__HAL_RCC_GPIOA_CLK_ENABLE();
800245c: 2101 movs r1, #1
__HAL_RCC_ADC_CLK_ENABLE();
800245e: 9201 str r2, [sp, #4]
8002460: 9a01 ldr r2, [sp, #4]
__HAL_RCC_GPIOA_CLK_ENABLE();
8002462: 6b5a ldr r2, [r3, #52] @ 0x34
GPIO_InitStruct.Pull = GPIO_NOPULL;
8002464: 2400 movs r4, #0
__HAL_RCC_GPIOA_CLK_ENABLE();
8002466: 430a orrs r2, r1
8002468: 635a str r2, [r3, #52] @ 0x34
800246a: 6b5a ldr r2, [r3, #52] @ 0x34
HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
800246c: 05c0 lsls r0, r0, #23
__HAL_RCC_GPIOA_CLK_ENABLE();
800246e: 400a ands r2, r1
8002470: 9202 str r2, [sp, #8]
8002472: 9a02 ldr r2, [sp, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
8002474: 6b5a ldr r2, [r3, #52] @ 0x34
8002476: 1849 adds r1, r1, r1
8002478: 430a orrs r2, r1
800247a: 635a str r2, [r3, #52] @ 0x34
800247c: 6b5b ldr r3, [r3, #52] @ 0x34
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
800247e: 9505 str r5, [sp, #20]
__HAL_RCC_GPIOB_CLK_ENABLE();
8002480: 400b ands r3, r1
8002482: 9303 str r3, [sp, #12]
8002484: 9b03 ldr r3, [sp, #12]
GPIO_InitStruct.Pin = IPROP_PEEL_Pin;
8002486: 2380 movs r3, #128 @ 0x80
HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
8002488: a904 add r1, sp, #16
GPIO_InitStruct.Pin = IPROP_PEEL_Pin;
800248a: 9304 str r3, [sp, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800248c: 9406 str r4, [sp, #24]
HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
800248e: f000 fe81 bl 8003194 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = IPROP_DRIVE_Pin;
8002492: 2380 movs r3, #128 @ 0x80
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
GPIO_InitStruct.Pull = GPIO_NOPULL;
HAL_GPIO_Init(IPROP_DRIVE_GPIO_Port, &GPIO_InitStruct);
8002494: 4806 ldr r0, [pc, #24] @ (80024b0 <HAL_ADC_MspInit+0x9c>)
GPIO_InitStruct.Pin = IPROP_DRIVE_Pin;
8002496: 015b lsls r3, r3, #5
HAL_GPIO_Init(IPROP_DRIVE_GPIO_Port, &GPIO_InitStruct);
8002498: a904 add r1, sp, #16
GPIO_InitStruct.Pin = IPROP_DRIVE_Pin;
800249a: 9304 str r3, [sp, #16]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
800249c: 9505 str r5, [sp, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800249e: 9406 str r4, [sp, #24]
HAL_GPIO_Init(IPROP_DRIVE_GPIO_Port, &GPIO_InitStruct);
80024a0: f000 fe78 bl 8003194 <HAL_GPIO_Init>
/* USER CODE END ADC1_MspInit 1 */
}
}
80024a4: b011 add sp, #68 @ 0x44
80024a6: bd30 pop {r4, r5, pc}
80024a8: 40012400 .word 0x40012400
80024ac: 40021000 .word 0x40021000
80024b0: 50000400 .word 0x50000400
080024b4 <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
80024b4: b51f push {r0, r1, r2, r3, r4, lr}
if(htim_base->Instance==TIM1)
80024b6: 6803 ldr r3, [r0, #0]
80024b8: 4a26 ldr r2, [pc, #152] @ (8002554 <HAL_TIM_Base_MspInit+0xa0>)
80024ba: 4293 cmp r3, r2
80024bc: d10b bne.n 80024d6 <HAL_TIM_Base_MspInit+0x22>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
80024be: 2180 movs r1, #128 @ 0x80
80024c0: 4b25 ldr r3, [pc, #148] @ (8002558 <HAL_TIM_Base_MspInit+0xa4>)
80024c2: 0109 lsls r1, r1, #4
80024c4: 6c1a ldr r2, [r3, #64] @ 0x40
80024c6: 430a orrs r2, r1
80024c8: 641a str r2, [r3, #64] @ 0x40
80024ca: 6c1b ldr r3, [r3, #64] @ 0x40
80024cc: 400b ands r3, r1
80024ce: 9300 str r3, [sp, #0]
80024d0: 9b00 ldr r3, [sp, #0]
/* USER CODE BEGIN TIM17_MspInit 1 */
/* USER CODE END TIM17_MspInit 1 */
}
}
80024d2: b005 add sp, #20
80024d4: bd00 pop {pc}
else if(htim_base->Instance==TIM14)
80024d6: 4a21 ldr r2, [pc, #132] @ (800255c <HAL_TIM_Base_MspInit+0xa8>)
80024d8: 4293 cmp r3, r2
80024da: d112 bne.n 8002502 <HAL_TIM_Base_MspInit+0x4e>
__HAL_RCC_TIM14_CLK_ENABLE();
80024dc: 2180 movs r1, #128 @ 0x80
80024de: 4b1e ldr r3, [pc, #120] @ (8002558 <HAL_TIM_Base_MspInit+0xa4>)
80024e0: 0209 lsls r1, r1, #8
80024e2: 6c1a ldr r2, [r3, #64] @ 0x40
HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
80024e4: 2013 movs r0, #19
__HAL_RCC_TIM14_CLK_ENABLE();
80024e6: 430a orrs r2, r1
80024e8: 641a str r2, [r3, #64] @ 0x40
HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
80024ea: 2200 movs r2, #0
__HAL_RCC_TIM14_CLK_ENABLE();
80024ec: 6c1b ldr r3, [r3, #64] @ 0x40
80024ee: 400b ands r3, r1
80024f0: 9301 str r3, [sp, #4]
HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
80024f2: 0011 movs r1, r2
__HAL_RCC_TIM14_CLK_ENABLE();
80024f4: 9b01 ldr r3, [sp, #4]
HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
80024f6: f000 fc55 bl 8002da4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM14_IRQn);
80024fa: 2013 movs r0, #19
HAL_NVIC_EnableIRQ(TIM17_IRQn);
80024fc: f000 fc7c bl 8002df8 <HAL_NVIC_EnableIRQ>
}
8002500: e7e7 b.n 80024d2 <HAL_TIM_Base_MspInit+0x1e>
else if(htim_base->Instance==TIM16)
8002502: 4a17 ldr r2, [pc, #92] @ (8002560 <HAL_TIM_Base_MspInit+0xac>)
8002504: 4293 cmp r3, r2
8002506: d110 bne.n 800252a <HAL_TIM_Base_MspInit+0x76>
__HAL_RCC_TIM16_CLK_ENABLE();
8002508: 2180 movs r1, #128 @ 0x80
800250a: 4b13 ldr r3, [pc, #76] @ (8002558 <HAL_TIM_Base_MspInit+0xa4>)
800250c: 0289 lsls r1, r1, #10
800250e: 6c1a ldr r2, [r3, #64] @ 0x40
HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
8002510: 2015 movs r0, #21
__HAL_RCC_TIM16_CLK_ENABLE();
8002512: 430a orrs r2, r1
8002514: 641a str r2, [r3, #64] @ 0x40
HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
8002516: 2200 movs r2, #0
__HAL_RCC_TIM16_CLK_ENABLE();
8002518: 6c1b ldr r3, [r3, #64] @ 0x40
800251a: 400b ands r3, r1
800251c: 9302 str r3, [sp, #8]
HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
800251e: 0011 movs r1, r2
__HAL_RCC_TIM16_CLK_ENABLE();
8002520: 9b02 ldr r3, [sp, #8]
HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
8002522: f000 fc3f bl 8002da4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM16_IRQn);
8002526: 2015 movs r0, #21
8002528: e7e8 b.n 80024fc <HAL_TIM_Base_MspInit+0x48>
else if(htim_base->Instance==TIM17)
800252a: 4a0e ldr r2, [pc, #56] @ (8002564 <HAL_TIM_Base_MspInit+0xb0>)
800252c: 4293 cmp r3, r2
800252e: d1d0 bne.n 80024d2 <HAL_TIM_Base_MspInit+0x1e>
__HAL_RCC_TIM17_CLK_ENABLE();
8002530: 2180 movs r1, #128 @ 0x80
8002532: 4b09 ldr r3, [pc, #36] @ (8002558 <HAL_TIM_Base_MspInit+0xa4>)
8002534: 02c9 lsls r1, r1, #11
8002536: 6c1a ldr r2, [r3, #64] @ 0x40
HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
8002538: 2016 movs r0, #22
__HAL_RCC_TIM17_CLK_ENABLE();
800253a: 430a orrs r2, r1
800253c: 641a str r2, [r3, #64] @ 0x40
HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
800253e: 2200 movs r2, #0
__HAL_RCC_TIM17_CLK_ENABLE();
8002540: 6c1b ldr r3, [r3, #64] @ 0x40
8002542: 400b ands r3, r1
8002544: 9303 str r3, [sp, #12]
HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
8002546: 0011 movs r1, r2
__HAL_RCC_TIM17_CLK_ENABLE();
8002548: 9b03 ldr r3, [sp, #12]
HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
800254a: f000 fc2b bl 8002da4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM17_IRQn);
800254e: 2016 movs r0, #22
8002550: e7d4 b.n 80024fc <HAL_TIM_Base_MspInit+0x48>
8002552: 46c0 nop @ (mov r8, r8)
8002554: 40012c00 .word 0x40012c00
8002558: 40021000 .word 0x40021000
800255c: 40002000 .word 0x40002000
8002560: 40014400 .word 0x40014400
8002564: 40014800 .word 0x40014800
08002568 <HAL_TIM_Encoder_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_encoder: TIM_Encoder handle pointer
* @retval None
*/
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
{
8002568: b510 push {r4, lr}
800256a: 0004 movs r4, r0
800256c: b088 sub sp, #32
GPIO_InitTypeDef GPIO_InitStruct = {0};
800256e: 2214 movs r2, #20
8002570: 2100 movs r1, #0
8002572: a803 add r0, sp, #12
8002574: f002 fe0a bl 800518c <memset>
if(htim_encoder->Instance==TIM3)
8002578: 4b0f ldr r3, [pc, #60] @ (80025b8 <HAL_TIM_Encoder_MspInit+0x50>)
800257a: 6822 ldr r2, [r4, #0]
800257c: 429a cmp r2, r3
800257e: d119 bne.n 80025b4 <HAL_TIM_Encoder_MspInit+0x4c>
{
/* USER CODE BEGIN TIM3_MspInit 0 */
/* USER CODE END TIM3_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM3_CLK_ENABLE();
8002580: 2202 movs r2, #2
__HAL_RCC_GPIOC_CLK_ENABLE();
8002582: 2004 movs r0, #4
__HAL_RCC_TIM3_CLK_ENABLE();
8002584: 4b0d ldr r3, [pc, #52] @ (80025bc <HAL_TIM_Encoder_MspInit+0x54>)
8002586: 6bd9 ldr r1, [r3, #60] @ 0x3c
8002588: 4311 orrs r1, r2
800258a: 63d9 str r1, [r3, #60] @ 0x3c
800258c: 6bd9 ldr r1, [r3, #60] @ 0x3c
800258e: 4011 ands r1, r2
8002590: 9101 str r1, [sp, #4]
8002592: 9901 ldr r1, [sp, #4]
__HAL_RCC_GPIOC_CLK_ENABLE();
8002594: 6b59 ldr r1, [r3, #52] @ 0x34
8002596: 4301 orrs r1, r0
8002598: 6359 str r1, [r3, #52] @ 0x34
800259a: 6b5b ldr r3, [r3, #52] @ 0x34
GPIO_InitStruct.Pin = QUAD_A_Pin|QUAD_B_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
800259c: a903 add r1, sp, #12
__HAL_RCC_GPIOC_CLK_ENABLE();
800259e: 4003 ands r3, r0
80025a0: 9302 str r3, [sp, #8]
80025a2: 9b02 ldr r3, [sp, #8]
GPIO_InitStruct.Pin = QUAD_A_Pin|QUAD_B_Pin;
80025a4: 23c0 movs r3, #192 @ 0xc0
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
80025a6: 4806 ldr r0, [pc, #24] @ (80025c0 <HAL_TIM_Encoder_MspInit+0x58>)
GPIO_InitStruct.Pin = QUAD_A_Pin|QUAD_B_Pin;
80025a8: 9303 str r3, [sp, #12]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
80025aa: 3bbf subs r3, #191 @ 0xbf
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80025ac: 9204 str r2, [sp, #16]
GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
80025ae: 9307 str r3, [sp, #28]
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
80025b0: f000 fdf0 bl 8003194 <HAL_GPIO_Init>
/* USER CODE END TIM3_MspInit 1 */
}
}
80025b4: b008 add sp, #32
80025b6: bd10 pop {r4, pc}
80025b8: 40000400 .word 0x40000400
80025bc: 40021000 .word 0x40021000
80025c0: 50000800 .word 0x50000800
080025c4 <HAL_TIM_MspPostInit>:
void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
{
80025c4: b510 push {r4, lr}
80025c6: 0004 movs r4, r0
80025c8: b086 sub sp, #24
GPIO_InitTypeDef GPIO_InitStruct = {0};
80025ca: 2214 movs r2, #20
80025cc: 2100 movs r1, #0
80025ce: a801 add r0, sp, #4
80025d0: f002 fddc bl 800518c <memset>
if(htim->Instance==TIM1)
80025d4: 4b13 ldr r3, [pc, #76] @ (8002624 <HAL_TIM_MspPostInit+0x60>)
80025d6: 6822 ldr r2, [r4, #0]
80025d8: 429a cmp r2, r3
80025da: d120 bne.n 800261e <HAL_TIM_MspPostInit+0x5a>
{
/* USER CODE BEGIN TIM1_MspPostInit 0 */
/* USER CODE END TIM1_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
80025dc: 2101 movs r1, #1
80025de: 4b12 ldr r3, [pc, #72] @ (8002628 <HAL_TIM_MspPostInit+0x64>)
GPIO_InitStruct.Pin = PEEL1_Pin|PEEL2_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF5_TIM1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80025e0: 20a0 movs r0, #160 @ 0xa0
__HAL_RCC_GPIOA_CLK_ENABLE();
80025e2: 6b5a ldr r2, [r3, #52] @ 0x34
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80025e4: 2402 movs r4, #2
__HAL_RCC_GPIOA_CLK_ENABLE();
80025e6: 430a orrs r2, r1
80025e8: 635a str r2, [r3, #52] @ 0x34
80025ea: 6b5b ldr r3, [r3, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80025ec: 05c0 lsls r0, r0, #23
__HAL_RCC_GPIOA_CLK_ENABLE();
80025ee: 400b ands r3, r1
80025f0: 9300 str r3, [sp, #0]
80025f2: 9b00 ldr r3, [sp, #0]
GPIO_InitStruct.Pin = PEEL1_Pin|PEEL2_Pin;
80025f4: 230c movs r3, #12
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80025f6: a901 add r1, sp, #4
GPIO_InitStruct.Pin = PEEL1_Pin|PEEL2_Pin;
80025f8: 9301 str r3, [sp, #4]
GPIO_InitStruct.Alternate = GPIO_AF5_TIM1;
80025fa: 3b07 subs r3, #7
80025fc: 9305 str r3, [sp, #20]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80025fe: 9402 str r4, [sp, #8]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8002600: f000 fdc8 bl 8003194 <HAL_GPIO_Init>
GPIO_InitStruct.Pin = DRIVE1_Pin|DRIVE2_Pin;
8002604: 23c0 movs r3, #192 @ 0xc0
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF2_TIM1;
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
8002606: 20a0 movs r0, #160 @ 0xa0
GPIO_InitStruct.Pin = DRIVE1_Pin|DRIVE2_Pin;
8002608: 009b lsls r3, r3, #2
800260a: 9301 str r3, [sp, #4]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800260c: 2300 movs r3, #0
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800260e: a901 add r1, sp, #4
8002610: 05c0 lsls r0, r0, #23
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8002612: 9402 str r4, [sp, #8]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8002614: 9303 str r3, [sp, #12]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8002616: 9304 str r3, [sp, #16]
GPIO_InitStruct.Alternate = GPIO_AF2_TIM1;
8002618: 9405 str r4, [sp, #20]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800261a: f000 fdbb bl 8003194 <HAL_GPIO_Init>
/* USER CODE BEGIN TIM1_MspPostInit 1 */
/* USER CODE END TIM1_MspPostInit 1 */
}
}
800261e: b006 add sp, #24
8002620: bd10 pop {r4, pc}
8002622: 46c0 nop @ (mov r8, r8)
8002624: 40012c00 .word 0x40012c00
8002628: 40021000 .word 0x40021000
0800262c <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
800262c: b530 push {r4, r5, lr}
800262e: 0005 movs r5, r0
8002630: b091 sub sp, #68 @ 0x44
GPIO_InitTypeDef GPIO_InitStruct = {0};
8002632: 2214 movs r2, #20
8002634: 2100 movs r1, #0
8002636: a804 add r0, sp, #16
8002638: f002 fda8 bl 800518c <memset>
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
800263c: 221c movs r2, #28
800263e: 2100 movs r1, #0
8002640: a809 add r0, sp, #36 @ 0x24
8002642: f002 fda3 bl 800518c <memset>
if(huart->Instance==USART1)
8002646: 682b ldr r3, [r5, #0]
8002648: 4a43 ldr r2, [pc, #268] @ (8002758 <HAL_UART_MspInit+0x12c>)
800264a: 4293 cmp r3, r2
800264c: d127 bne.n 800269e <HAL_UART_MspInit+0x72>
/* USER CODE END USART1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
800264e: 2301 movs r3, #1
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1;
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8002650: a809 add r0, sp, #36 @ 0x24
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
8002652: 9309 str r3, [sp, #36] @ 0x24
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8002654: f001 f8b8 bl 80037c8 <HAL_RCCEx_PeriphCLKConfig>
8002658: 2800 cmp r0, #0
800265a: d001 beq.n 8002660 <HAL_UART_MspInit+0x34>
{
Error_Handler();
800265c: f7ff fec0 bl 80023e0 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
8002660: 2180 movs r1, #128 @ 0x80
8002662: 4b3e ldr r3, [pc, #248] @ (800275c <HAL_UART_MspInit+0x130>)
8002664: 01c9 lsls r1, r1, #7
8002666: 6c1a ldr r2, [r3, #64] @ 0x40
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
GPIO_InitStruct.Alternate = GPIO_AF0_USART1;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8002668: 483d ldr r0, [pc, #244] @ (8002760 <HAL_UART_MspInit+0x134>)
__HAL_RCC_USART1_CLK_ENABLE();
800266a: 430a orrs r2, r1
800266c: 641a str r2, [r3, #64] @ 0x40
800266e: 6c1a ldr r2, [r3, #64] @ 0x40
8002670: 400a ands r2, r1
8002672: 9200 str r2, [sp, #0]
8002674: 9a00 ldr r2, [sp, #0]
__HAL_RCC_GPIOB_CLK_ENABLE();
8002676: 2202 movs r2, #2
8002678: 6b59 ldr r1, [r3, #52] @ 0x34
800267a: 4311 orrs r1, r2
800267c: 6359 str r1, [r3, #52] @ 0x34
800267e: 6b5b ldr r3, [r3, #52] @ 0x34
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8002680: a904 add r1, sp, #16
__HAL_RCC_GPIOB_CLK_ENABLE();
8002682: 4013 ands r3, r2
8002684: 9301 str r3, [sp, #4]
8002686: 9b01 ldr r3, [sp, #4]
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
8002688: 23c0 movs r3, #192 @ 0xc0
800268a: 9304 str r3, [sp, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800268c: 2300 movs r3, #0
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800268e: 9205 str r2, [sp, #20]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8002690: 9306 str r3, [sp, #24]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8002692: 9307 str r3, [sp, #28]
GPIO_InitStruct.Alternate = GPIO_AF0_USART1;
8002694: 9308 str r3, [sp, #32]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8002696: f000 fd7d bl 8003194 <HAL_GPIO_Init>
/* USER CODE BEGIN USART2_MspInit 1 */
/* USER CODE END USART2_MspInit 1 */
}
}
800269a: b011 add sp, #68 @ 0x44
800269c: bd30 pop {r4, r5, pc}
else if(huart->Instance==USART2)
800269e: 4a31 ldr r2, [pc, #196] @ (8002764 <HAL_UART_MspInit+0x138>)
80026a0: 4293 cmp r3, r2
80026a2: d1fa bne.n 800269a <HAL_UART_MspInit+0x6e>
__HAL_RCC_USART2_CLK_ENABLE();
80026a4: 2180 movs r1, #128 @ 0x80
80026a6: 4b2d ldr r3, [pc, #180] @ (800275c <HAL_UART_MspInit+0x130>)
80026a8: 0289 lsls r1, r1, #10
80026aa: 6bda ldr r2, [r3, #60] @ 0x3c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80026ac: 20a0 movs r0, #160 @ 0xa0
__HAL_RCC_USART2_CLK_ENABLE();
80026ae: 430a orrs r2, r1
80026b0: 63da str r2, [r3, #60] @ 0x3c
80026b2: 6bda ldr r2, [r3, #60] @ 0x3c
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80026b4: 05c0 lsls r0, r0, #23
__HAL_RCC_USART2_CLK_ENABLE();
80026b6: 400a ands r2, r1
80026b8: 9202 str r2, [sp, #8]
80026ba: 9a02 ldr r2, [sp, #8]
__HAL_RCC_GPIOA_CLK_ENABLE();
80026bc: 2201 movs r2, #1
80026be: 6b59 ldr r1, [r3, #52] @ 0x34
80026c0: 4311 orrs r1, r2
80026c2: 6359 str r1, [r3, #52] @ 0x34
80026c4: 6b5b ldr r3, [r3, #52] @ 0x34
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80026c6: a904 add r1, sp, #16
__HAL_RCC_GPIOA_CLK_ENABLE();
80026c8: 4013 ands r3, r2
80026ca: 9303 str r3, [sp, #12]
80026cc: 9b03 ldr r3, [sp, #12]
GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
80026ce: 2332 movs r3, #50 @ 0x32
80026d0: 9304 str r3, [sp, #16]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
80026d2: 3b30 subs r3, #48 @ 0x30
80026d4: 9305 str r3, [sp, #20]
GPIO_InitStruct.Alternate = GPIO_AF1_USART2;
80026d6: 9208 str r2, [sp, #32]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
80026d8: f000 fd5c bl 8003194 <HAL_GPIO_Init>
hdma_usart2_rx.Instance = DMA1_Channel2;
80026dc: 4c22 ldr r4, [pc, #136] @ (8002768 <HAL_UART_MspInit+0x13c>)
80026de: 4b23 ldr r3, [pc, #140] @ (800276c <HAL_UART_MspInit+0x140>)
hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
80026e0: 2280 movs r2, #128 @ 0x80
hdma_usart2_rx.Instance = DMA1_Channel2;
80026e2: 6023 str r3, [r4, #0]
hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX;
80026e4: 2334 movs r3, #52 @ 0x34
80026e6: 6063 str r3, [r4, #4]
hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
80026e8: 2300 movs r3, #0
80026ea: 60a3 str r3, [r4, #8]
hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
80026ec: 60e3 str r3, [r4, #12]
hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
80026ee: 6163 str r3, [r4, #20]
hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
80026f0: 61a3 str r3, [r4, #24]
hdma_usart2_rx.Init.Mode = DMA_NORMAL;
80026f2: 61e3 str r3, [r4, #28]
hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
80026f4: 2380 movs r3, #128 @ 0x80
if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
80026f6: 0020 movs r0, r4
hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
80026f8: 015b lsls r3, r3, #5
hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
80026fa: 6122 str r2, [r4, #16]
hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
80026fc: 6223 str r3, [r4, #32]
if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
80026fe: f000 fbdb bl 8002eb8 <HAL_DMA_Init>
8002702: 2800 cmp r0, #0
8002704: d001 beq.n 800270a <HAL_UART_MspInit+0xde>
Error_Handler();
8002706: f7ff fe6b bl 80023e0 <Error_Handler>
__HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx);
800270a: 1d2b adds r3, r5, #4
800270c: 67dc str r4, [r3, #124] @ 0x7c
800270e: 62a5 str r5, [r4, #40] @ 0x28
hdma_usart2_tx.Instance = DMA1_Channel1;
8002710: 4b17 ldr r3, [pc, #92] @ (8002770 <HAL_UART_MspInit+0x144>)
8002712: 4c18 ldr r4, [pc, #96] @ (8002774 <HAL_UART_MspInit+0x148>)
hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
8002714: 2280 movs r2, #128 @ 0x80
hdma_usart2_tx.Instance = DMA1_Channel1;
8002716: 6023 str r3, [r4, #0]
hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX;
8002718: 2335 movs r3, #53 @ 0x35
800271a: 6063 str r3, [r4, #4]
hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
800271c: 3b25 subs r3, #37 @ 0x25
800271e: 60a3 str r3, [r4, #8]
hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
8002720: 2300 movs r3, #0
8002722: 60e3 str r3, [r4, #12]
hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
8002724: 6163 str r3, [r4, #20]
hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
8002726: 61a3 str r3, [r4, #24]
hdma_usart2_tx.Init.Mode = DMA_NORMAL;
8002728: 61e3 str r3, [r4, #28]
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH;
800272a: 2380 movs r3, #128 @ 0x80
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
800272c: 0020 movs r0, r4
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH;
800272e: 019b lsls r3, r3, #6
hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
8002730: 6122 str r2, [r4, #16]
hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH;
8002732: 6223 str r3, [r4, #32]
if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
8002734: f000 fbc0 bl 8002eb8 <HAL_DMA_Init>
8002738: 2800 cmp r0, #0
800273a: d001 beq.n 8002740 <HAL_UART_MspInit+0x114>
Error_Handler();
800273c: f7ff fe50 bl 80023e0 <Error_Handler>
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
8002740: 2200 movs r2, #0
8002742: 201c movs r0, #28
8002744: 0011 movs r1, r2
__HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx);
8002746: 67ec str r4, [r5, #124] @ 0x7c
8002748: 62a5 str r5, [r4, #40] @ 0x28
HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
800274a: f000 fb2b bl 8002da4 <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(USART2_IRQn);
800274e: 201c movs r0, #28
8002750: f000 fb52 bl 8002df8 <HAL_NVIC_EnableIRQ>
}
8002754: e7a1 b.n 800269a <HAL_UART_MspInit+0x6e>
8002756: 46c0 nop @ (mov r8, r8)
8002758: 40013800 .word 0x40013800
800275c: 40021000 .word 0x40021000
8002760: 50000400 .word 0x50000400
8002764: 40004400 .word 0x40004400
8002768: 20000ffc .word 0x20000ffc
800276c: 4002001c .word 0x4002001c
8002770: 40020008 .word 0x40020008
8002774: 20000fa0 .word 0x20000fa0
08002778 <NMI_Handler>:
{
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
8002778: e7fe b.n 8002778 <NMI_Handler>
0800277a <HardFault_Handler>:
void HardFault_Handler(void)
{
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
800277a: e7fe b.n 800277a <HardFault_Handler>
0800277c <SVC_Handler>:
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
800277c: 4770 bx lr
0800277e <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
800277e: 4770 bx lr
08002780 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8002780: b510 push {r4, lr}
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8002782: f000 f8a1 bl 80028c8 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
8002786: bd10 pop {r4, pc}
08002788 <EXTI4_15_IRQHandler>:
void EXTI4_15_IRQHandler(void)
{
/* USER CODE BEGIN EXTI4_15_IRQn 0 */
/* USER CODE END EXTI4_15_IRQn 0 */
HAL_GPIO_EXTI_IRQHandler(SW2_Pin);
8002788: 2080 movs r0, #128 @ 0x80
{
800278a: b510 push {r4, lr}
HAL_GPIO_EXTI_IRQHandler(SW2_Pin);
800278c: 0040 lsls r0, r0, #1
800278e: f000 fdc9 bl 8003324 <HAL_GPIO_EXTI_IRQHandler>
HAL_GPIO_EXTI_IRQHandler(SW1_Pin);
8002792: 2080 movs r0, #128 @ 0x80
8002794: 0080 lsls r0, r0, #2
8002796: f000 fdc5 bl 8003324 <HAL_GPIO_EXTI_IRQHandler>
/* USER CODE BEGIN EXTI4_15_IRQn 1 */
/* USER CODE END EXTI4_15_IRQn 1 */
}
800279a: bd10 pop {r4, pc}
0800279c <DMA1_Channel1_IRQHandler>:
/**
* @brief This function handles DMA1 channel 1 interrupt.
*/
void DMA1_Channel1_IRQHandler(void)
{
800279c: b510 push {r4, lr}
/* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
/* USER CODE END DMA1_Channel1_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_usart2_tx);
800279e: 4802 ldr r0, [pc, #8] @ (80027a8 <DMA1_Channel1_IRQHandler+0xc>)
80027a0: f000 fca4 bl 80030ec <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
/* USER CODE END DMA1_Channel1_IRQn 1 */
}
80027a4: bd10 pop {r4, pc}
80027a6: 46c0 nop @ (mov r8, r8)
80027a8: 20000fa0 .word 0x20000fa0
080027ac <DMA1_Channel2_3_IRQHandler>:
/**
* @brief This function handles DMA1 channel 2 and channel 3 interrupts.
*/
void DMA1_Channel2_3_IRQHandler(void)
{
80027ac: b510 push {r4, lr}
/* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */
/* USER CODE END DMA1_Channel2_3_IRQn 0 */
HAL_DMA_IRQHandler(&hdma_usart2_rx);
80027ae: 4802 ldr r0, [pc, #8] @ (80027b8 <DMA1_Channel2_3_IRQHandler+0xc>)
80027b0: f000 fc9c bl 80030ec <HAL_DMA_IRQHandler>
/* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */
/* USER CODE END DMA1_Channel2_3_IRQn 1 */
}
80027b4: bd10 pop {r4, pc}
80027b6: 46c0 nop @ (mov r8, r8)
80027b8: 20000ffc .word 0x20000ffc
080027bc <TIM14_IRQHandler>:
/**
* @brief This function handles TIM14 global interrupt.
*/
void TIM14_IRQHandler(void)
{
80027bc: b510 push {r4, lr}
/* USER CODE BEGIN TIM14_IRQn 0 */
/* USER CODE END TIM14_IRQn 0 */
HAL_TIM_IRQHandler(&htim14);
80027be: 4802 ldr r0, [pc, #8] @ (80027c8 <TIM14_IRQHandler+0xc>)
80027c0: f001 fa40 bl 8003c44 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM14_IRQn 1 */
/* USER CODE END TIM14_IRQn 1 */
}
80027c4: bd10 pop {r4, pc}
80027c6: 46c0 nop @ (mov r8, r8)
80027c8: 20001218 .word 0x20001218
080027cc <TIM16_IRQHandler>:
/**
* @brief This function handles TIM16 global interrupt.
*/
void TIM16_IRQHandler(void)
{
80027cc: b510 push {r4, lr}
/* USER CODE BEGIN TIM16_IRQn 0 */
/* USER CODE END TIM16_IRQn 0 */
HAL_TIM_IRQHandler(&htim16);
80027ce: 4802 ldr r0, [pc, #8] @ (80027d8 <TIM16_IRQHandler+0xc>)
80027d0: f001 fa38 bl 8003c44 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM16_IRQn 1 */
/* USER CODE END TIM16_IRQn 1 */
}
80027d4: bd10 pop {r4, pc}
80027d6: 46c0 nop @ (mov r8, r8)
80027d8: 200011cc .word 0x200011cc
080027dc <TIM17_IRQHandler>:
/**
* @brief This function handles TIM17 global interrupt.
*/
void TIM17_IRQHandler(void)
{
80027dc: b510 push {r4, lr}
/* USER CODE BEGIN TIM17_IRQn 0 */
/* USER CODE END TIM17_IRQn 0 */
HAL_TIM_IRQHandler(&htim17);
80027de: 4802 ldr r0, [pc, #8] @ (80027e8 <TIM17_IRQHandler+0xc>)
80027e0: f001 fa30 bl 8003c44 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM17_IRQn 1 */
/* USER CODE END TIM17_IRQn 1 */
}
80027e4: bd10 pop {r4, pc}
80027e6: 46c0 nop @ (mov r8, r8)
80027e8: 20001180 .word 0x20001180
080027ec <USART2_IRQHandler>:
/**
* @brief This function handles USART2 interrupt.
*/
void USART2_IRQHandler(void)
{
80027ec: b510 push {r4, lr}
/* USER CODE BEGIN USART2_IRQn 0 */
/* USER CODE END USART2_IRQn 0 */
HAL_UART_IRQHandler(&huart2);
80027ee: 4802 ldr r0, [pc, #8] @ (80027f8 <USART2_IRQHandler+0xc>)
80027f0: f001 fed2 bl 8004598 <HAL_UART_IRQHandler>
/* USER CODE BEGIN USART2_IRQn 1 */
/* USER CODE END USART2_IRQn 1 */
}
80027f4: bd10 pop {r4, pc}
80027f6: 46c0 nop @ (mov r8, r8)
80027f8: 20001058 .word 0x20001058
080027fc <SystemInit>:
/* Configure the Vector Table location add offset address ------------------*/
#ifdef VECT_TAB_SRAM
SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#else
SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
80027fc: 2280 movs r2, #128 @ 0x80
80027fe: 4b02 ldr r3, [pc, #8] @ (8002808 <SystemInit+0xc>)
8002800: 0512 lsls r2, r2, #20
8002802: 609a str r2, [r3, #8]
#endif
}
8002804: 4770 bx lr
8002806: 46c0 nop @ (mov r8, r8)
8002808: e000ed00 .word 0xe000ed00
0800280c <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
800280c: 480d ldr r0, [pc, #52] @ (8002844 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
800280e: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
8002810: f7ff fff4 bl 80027fc <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
8002814: 2100 movs r1, #0
b LoopCopyDataInit
8002816: e003 b.n 8002820 <LoopCopyDataInit>
08002818 <CopyDataInit>:
CopyDataInit:
ldr r3, =_sidata
8002818: 4b0b ldr r3, [pc, #44] @ (8002848 <LoopForever+0x6>)
ldr r3, [r3, r1]
800281a: 585b ldr r3, [r3, r1]
str r3, [r0, r1]
800281c: 5043 str r3, [r0, r1]
adds r1, r1, #4
800281e: 3104 adds r1, #4
08002820 <LoopCopyDataInit>:
LoopCopyDataInit:
ldr r0, =_sdata
8002820: 480a ldr r0, [pc, #40] @ (800284c <LoopForever+0xa>)
ldr r3, =_edata
8002822: 4b0b ldr r3, [pc, #44] @ (8002850 <LoopForever+0xe>)
adds r2, r0, r1
8002824: 1842 adds r2, r0, r1
cmp r2, r3
8002826: 429a cmp r2, r3
bcc CopyDataInit
8002828: d3f6 bcc.n 8002818 <CopyDataInit>
ldr r2, =_sbss
800282a: 4a0a ldr r2, [pc, #40] @ (8002854 <LoopForever+0x12>)
b LoopFillZerobss
800282c: e002 b.n 8002834 <LoopFillZerobss>
0800282e <FillZerobss>:
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
800282e: 2300 movs r3, #0
str r3, [r2]
8002830: 6013 str r3, [r2, #0]
adds r2, r2, #4
8002832: 3204 adds r2, #4
08002834 <LoopFillZerobss>:
LoopFillZerobss:
ldr r3, = _ebss
8002834: 4b08 ldr r3, [pc, #32] @ (8002858 <LoopForever+0x16>)
cmp r2, r3
8002836: 429a cmp r2, r3
bcc FillZerobss
8002838: d3f9 bcc.n 800282e <FillZerobss>
/* Call static constructors */
bl __libc_init_array
800283a: f002 fcaf bl 800519c <__libc_init_array>
/* Call the application's entry point.*/
bl main
800283e: f7ff f90b bl 8001a58 <main>
08002842 <LoopForever>:
LoopForever:
b LoopForever
8002842: e7fe b.n 8002842 <LoopForever>
ldr r0, =_estack
8002844: 20003000 .word 0x20003000
ldr r3, =_sidata
8002848: 080052c8 .word 0x080052c8
ldr r0, =_sdata
800284c: 20000000 .word 0x20000000
ldr r3, =_edata
8002850: 20000030 .word 0x20000030
ldr r2, =_sbss
8002854: 20000030 .word 0x20000030
ldr r3, = _ebss
8002858: 20001364 .word 0x20001364
0800285c <ADC1_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
800285c: e7fe b.n 800285c <ADC1_IRQHandler>
...
08002860 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8002860: b570 push {r4, r5, r6, lr}
HAL_StatusTypeDef status = HAL_OK;
if ((uint32_t)uwTickFreq != 0UL)
8002862: 4b10 ldr r3, [pc, #64] @ (80028a4 <HAL_InitTick+0x44>)
{
8002864: 0005 movs r5, r0
if ((uint32_t)uwTickFreq != 0UL)
8002866: 7819 ldrb r1, [r3, #0]
8002868: 2900 cmp r1, #0
800286a: d101 bne.n 8002870 <HAL_InitTick+0x10>
status = HAL_ERROR;
}
}
else
{
status = HAL_ERROR;
800286c: 2001 movs r0, #1
status = HAL_ERROR;
}
/* Return function status */
return status;
}
800286e: bd70 pop {r4, r5, r6, pc}
if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) == 0U)
8002870: 20fa movs r0, #250 @ 0xfa
8002872: 0080 lsls r0, r0, #2
8002874: f7fd fc5c bl 8000130 <__udivsi3>
8002878: 4c0b ldr r4, [pc, #44] @ (80028a8 <HAL_InitTick+0x48>)
800287a: 0001 movs r1, r0
800287c: 6820 ldr r0, [r4, #0]
800287e: f7fd fc57 bl 8000130 <__udivsi3>
8002882: f000 fac5 bl 8002e10 <HAL_SYSTICK_Config>
8002886: 1e04 subs r4, r0, #0
8002888: d1f0 bne.n 800286c <HAL_InitTick+0xc>
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
800288a: 2d03 cmp r5, #3
800288c: d8ee bhi.n 800286c <HAL_InitTick+0xc>
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
800288e: 0002 movs r2, r0
8002890: 2001 movs r0, #1
8002892: 0029 movs r1, r5
8002894: 4240 negs r0, r0
8002896: f000 fa85 bl 8002da4 <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
800289a: 4b04 ldr r3, [pc, #16] @ (80028ac <HAL_InitTick+0x4c>)
800289c: 0020 movs r0, r4
800289e: 601d str r5, [r3, #0]
return status;
80028a0: e7e5 b.n 800286e <HAL_InitTick+0xe>
80028a2: 46c0 nop @ (mov r8, r8)
80028a4: 20000028 .word 0x20000028
80028a8: 20000024 .word 0x20000024
80028ac: 2000002c .word 0x2000002c
080028b0 <HAL_Init>:
{
80028b0: b510 push {r4, lr}
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
80028b2: 2003 movs r0, #3
80028b4: f7ff ffd4 bl 8002860 <HAL_InitTick>
80028b8: 1e04 subs r4, r0, #0
80028ba: d103 bne.n 80028c4 <HAL_Init+0x14>
HAL_MspInit();
80028bc: f7ff fd92 bl 80023e4 <HAL_MspInit>
}
80028c0: 0020 movs r0, r4
80028c2: bd10 pop {r4, pc}
status = HAL_ERROR;
80028c4: 2401 movs r4, #1
80028c6: e7fb b.n 80028c0 <HAL_Init+0x10>
080028c8 <HAL_IncTick>:
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
uwTick += (uint32_t)uwTickFreq;
80028c8: 4a03 ldr r2, [pc, #12] @ (80028d8 <HAL_IncTick+0x10>)
80028ca: 4b04 ldr r3, [pc, #16] @ (80028dc <HAL_IncTick+0x14>)
80028cc: 6811 ldr r1, [r2, #0]
80028ce: 781b ldrb r3, [r3, #0]
80028d0: 185b adds r3, r3, r1
80028d2: 6013 str r3, [r2, #0]
}
80028d4: 4770 bx lr
80028d6: 46c0 nop @ (mov r8, r8)
80028d8: 20001360 .word 0x20001360
80028dc: 20000028 .word 0x20000028
080028e0 <HAL_GetTick>:
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
return uwTick;
80028e0: 4b01 ldr r3, [pc, #4] @ (80028e8 <HAL_GetTick+0x8>)
80028e2: 6818 ldr r0, [r3, #0]
}
80028e4: 4770 bx lr
80028e6: 46c0 nop @ (mov r8, r8)
80028e8: 20001360 .word 0x20001360
080028ec <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
80028ec: b570 push {r4, r5, r6, lr}
80028ee: 0004 movs r4, r0
uint32_t tickstart = HAL_GetTick();
80028f0: f7ff fff6 bl 80028e0 <HAL_GetTick>
80028f4: 0005 movs r5, r0
uint32_t wait = Delay;
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
80028f6: 1c63 adds r3, r4, #1
80028f8: d002 beq.n 8002900 <HAL_Delay+0x14>
{
wait += (uint32_t)(uwTickFreq);
80028fa: 4b04 ldr r3, [pc, #16] @ (800290c <HAL_Delay+0x20>)
80028fc: 781b ldrb r3, [r3, #0]
80028fe: 18e4 adds r4, r4, r3
}
while ((HAL_GetTick() - tickstart) < wait)
8002900: f7ff ffee bl 80028e0 <HAL_GetTick>
8002904: 1b40 subs r0, r0, r5
8002906: 42a0 cmp r0, r4
8002908: d3fa bcc.n 8002900 <HAL_Delay+0x14>
{
}
}
800290a: bd70 pop {r4, r5, r6, pc}
800290c: 20000028 .word 0x20000028
08002910 <HAL_GetUIDw0>:
* @brief Returns first word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw0(void)
{
return (READ_REG(*((uint32_t *)UID_BASE)));
8002910: 4b01 ldr r3, [pc, #4] @ (8002918 <HAL_GetUIDw0+0x8>)
8002912: 6818 ldr r0, [r3, #0]
}
8002914: 4770 bx lr
8002916: 46c0 nop @ (mov r8, r8)
8002918: 1fff7550 .word 0x1fff7550
0800291c <HAL_GetUIDw1>:
* @brief Returns second word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw1(void)
{
return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
800291c: 4b01 ldr r3, [pc, #4] @ (8002924 <HAL_GetUIDw1+0x8>)
800291e: 6818 ldr r0, [r3, #0]
}
8002920: 4770 bx lr
8002922: 46c0 nop @ (mov r8, r8)
8002924: 1fff7554 .word 0x1fff7554
08002928 <HAL_GetUIDw2>:
* @brief Returns third word of the unique device identifier (UID based on 96 bits)
* @retval Device identifier
*/
uint32_t HAL_GetUIDw2(void)
{
return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
8002928: 4b01 ldr r3, [pc, #4] @ (8002930 <HAL_GetUIDw2+0x8>)
800292a: 6818 ldr r0, [r3, #0]
}
800292c: 4770 bx lr
800292e: 46c0 nop @ (mov r8, r8)
8002930: 1fff7558 .word 0x1fff7558
08002934 <LL_ADC_REG_IsConversionOngoing>:
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8002934: 6880 ldr r0, [r0, #8]
8002936: 0740 lsls r0, r0, #29
8002938: 0fc0 lsrs r0, r0, #31
}
800293a: 4770 bx lr
0800293c <HAL_ADC_Init>:
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmpCFGR1 = 0UL;
uint32_t tmpCFGR2 = 0UL;
uint32_t tmp_adc_reg_is_conversion_on_going;
__IO uint32_t wait_loop_index = 0UL;
800293c: 2300 movs r3, #0
{
800293e: b5f0 push {r4, r5, r6, r7, lr}
8002940: b085 sub sp, #20
8002942: 0004 movs r4, r0
__IO uint32_t wait_loop_index = 0UL;
8002944: 9303 str r3, [sp, #12]
/* Check ADC handle */
if (hadc == NULL)
8002946: 4298 cmp r0, r3
8002948: d100 bne.n 800294c <HAL_ADC_Init+0x10>
800294a: e0ef b.n 8002b2c <HAL_ADC_Init+0x1f0>
/* continuous mode is disabled. */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
800294c: 6d85 ldr r5, [r0, #88] @ 0x58
800294e: 429d cmp r5, r3
8002950: d105 bne.n 800295e <HAL_ADC_Init+0x22>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8002952: f7ff fd5f bl 8002414 <HAL_ADC_MspInit>
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
/* Initialize Lock */
hadc->Lock = HAL_UNLOCKED;
8002956: 0023 movs r3, r4
8002958: 3354 adds r3, #84 @ 0x54
ADC_CLEAR_ERRORCODE(hadc);
800295a: 65e5 str r5, [r4, #92] @ 0x5c
hadc->Lock = HAL_UNLOCKED;
800295c: 701d strb r5, [r3, #0]
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
800295e: 2380 movs r3, #128 @ 0x80
}
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
8002960: 6825 ldr r5, [r4, #0]
8002962: 055b lsls r3, r3, #21
8002964: 68aa ldr r2, [r5, #8]
8002966: 421a tst r2, r3
8002968: d100 bne.n 800296c <HAL_ADC_Init+0x30>
800296a: e0a7 b.n 8002abc <HAL_ADC_Init+0x180>
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
800296c: 2200 movs r2, #0
800296e: 68ab ldr r3, [r5, #8]
8002970: 9201 str r2, [sp, #4]
8002972: 00db lsls r3, r3, #3
8002974: d408 bmi.n 8002988 <HAL_ADC_Init+0x4c>
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002976: 2310 movs r3, #16
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002978: 2601 movs r6, #1
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800297a: 6da2 ldr r2, [r4, #88] @ 0x58
tmp_hal_status = HAL_ERROR;
800297c: 9601 str r6, [sp, #4]
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800297e: 4313 orrs r3, r2
8002980: 65a3 str r3, [r4, #88] @ 0x58
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002982: 6de3 ldr r3, [r4, #92] @ 0x5c
8002984: 4333 orrs r3, r6
8002986: 65e3 str r3, [r4, #92] @ 0x5c
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
8002988: 0028 movs r0, r5
800298a: f7ff ffd3 bl 8002934 <LL_ADC_REG_IsConversionOngoing>
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
800298e: 2210 movs r2, #16
8002990: 6da3 ldr r3, [r4, #88] @ 0x58
8002992: 4013 ands r3, r2
8002994: 4303 orrs r3, r0
8002996: d000 beq.n 800299a <HAL_ADC_Init+0x5e>
8002998: e0cb b.n 8002b32 <HAL_ADC_Init+0x1f6>
&& (tmp_adc_reg_is_conversion_on_going == 0UL)
)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
800299a: 6da2 ldr r2, [r4, #88] @ 0x58
800299c: 4b67 ldr r3, [pc, #412] @ (8002b3c <HAL_ADC_Init+0x200>)
ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
hadc->Init.DataAlign |
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
800299e: 6920 ldr r0, [r4, #16]
ADC_STATE_CLR_SET(hadc->State,
80029a0: 401a ands r2, r3
80029a2: 3306 adds r3, #6
80029a4: 33ff adds r3, #255 @ 0xff
80029a6: 4313 orrs r3, r2
80029a8: 65a3 str r3, [r4, #88] @ 0x58
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
80029aa: 68ab ldr r3, [r5, #8]
80029ac: 07db lsls r3, r3, #31
80029ae: d461 bmi.n 8002a74 <HAL_ADC_Init+0x138>
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
80029b0: 6b27 ldr r7, [r4, #48] @ 0x30
80029b2: 68e1 ldr r1, [r4, #12]
80029b4: 1e7b subs r3, r7, #1
80029b6: 419f sbcs r7, r3
80029b8: 68a3 ldr r3, [r4, #8]
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80029ba: 7ea2 ldrb r2, [r4, #26]
80029bc: 430b orrs r3, r1
ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
80029be: 7e21 ldrb r1, [r4, #24]
ADC_CFGR1_OVERRUN(hadc->Init.Overrun) |
80029c0: 033f lsls r7, r7, #12
ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
80029c2: 0389 lsls r1, r1, #14
80029c4: 430b orrs r3, r1
ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) |
80029c6: 7e61 ldrb r1, [r4, #25]
80029c8: 03c9 lsls r1, r1, #15
80029ca: 430b orrs r3, r1
ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80029cc: 0351 lsls r1, r2, #13
80029ce: 430b orrs r3, r1
80029d0: 469c mov ip, r3
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
80029d2: 2800 cmp r0, #0
80029d4: db00 blt.n 80029d8 <HAL_ADC_Init+0x9c>
80029d6: e085 b.n 8002ae4 <HAL_ADC_Init+0x1a8>
80029d8: 0041 lsls r1, r0, #1
80029da: 0849 lsrs r1, r1, #1
ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
80029dc: 0023 movs r3, r4
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
80029de: 4666 mov r6, ip
ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
80029e0: 332c adds r3, #44 @ 0x2c
80029e2: 781b ldrb r3, [r3, #0]
80029e4: 005b lsls r3, r3, #1
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
80029e6: 4333 orrs r3, r6
80029e8: 433b orrs r3, r7
80029ea: 430b orrs r3, r1
/* Update setting of discontinuous mode only if continuous mode is disabled */
if (hadc->Init.DiscontinuousConvMode == ENABLE)
80029ec: 1c61 adds r1, r4, #1
80029ee: 7fc9 ldrb r1, [r1, #31]
80029f0: 2901 cmp r1, #1
80029f2: d105 bne.n 8002a00 <HAL_ADC_Init+0xc4>
{
if (hadc->Init.ContinuousConvMode == DISABLE)
80029f4: 2a00 cmp r2, #0
80029f6: d000 beq.n 80029fa <HAL_ADC_Init+0xbe>
80029f8: e077 b.n 8002aea <HAL_ADC_Init+0x1ae>
{
/* Enable the selected ADC group regular discontinuous mode */
tmpCFGR1 |= ADC_CFGR1_DISCEN;
80029fa: 2280 movs r2, #128 @ 0x80
80029fc: 0252 lsls r2, r2, #9
80029fe: 4313 orrs r3, r2
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8002a00: 6a62 ldr r2, [r4, #36] @ 0x24
8002a02: 2a00 cmp r2, #0
8002a04: d005 beq.n 8002a12 <HAL_ADC_Init+0xd6>
{
tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
8002a06: 21e0 movs r1, #224 @ 0xe0
8002a08: 0049 lsls r1, r1, #1
8002a0a: 400a ands r2, r1
8002a0c: 6aa1 ldr r1, [r4, #40] @ 0x28
8002a0e: 430a orrs r2, r1
8002a10: 4313 orrs r3, r2
hadc->Init.ExternalTrigConvEdge);
}
/* Update ADC configuration register with previous settings */
MODIFY_REG(hadc->Instance->CFGR1,
8002a12: 68ea ldr r2, [r5, #12]
8002a14: 494a ldr r1, [pc, #296] @ (8002b40 <HAL_ADC_Init+0x204>)
8002a16: 400a ands r2, r1
8002a18: 4313 orrs r3, r2
8002a1a: 60eb str r3, [r5, #12]
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
hadc->Init.TriggerFrequencyMode
);
if (hadc->Init.OversamplingMode == ENABLE)
8002a1c: 0023 movs r3, r4
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
8002a1e: 6862 ldr r2, [r4, #4]
if (hadc->Init.OversamplingMode == ENABLE)
8002a20: 333c adds r3, #60 @ 0x3c
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
8002a22: 6ce1 ldr r1, [r4, #76] @ 0x4c
if (hadc->Init.OversamplingMode == ENABLE)
8002a24: 781b ldrb r3, [r3, #0]
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
8002a26: 0f97 lsrs r7, r2, #30
8002a28: 07bf lsls r7, r7, #30
if (hadc->Init.OversamplingMode == ENABLE)
8002a2a: 469c mov ip, r3
tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
8002a2c: 4339 orrs r1, r7
if (hadc->Init.OversamplingMode == ENABLE)
8002a2e: 2b01 cmp r3, #1
8002a30: d108 bne.n 8002a44 <HAL_ADC_Init+0x108>
{
tmpCFGR2 |= (ADC_CFGR2_OVSE |
8002a32: 6c23 ldr r3, [r4, #64] @ 0x40
8002a34: 6c66 ldr r6, [r4, #68] @ 0x44
8002a36: 4333 orrs r3, r6
8002a38: 430b orrs r3, r1
8002a3a: 6ca1 ldr r1, [r4, #72] @ 0x48
8002a3c: 430b orrs r3, r1
8002a3e: 4661 mov r1, ip
8002a40: 433b orrs r3, r7
8002a42: 4319 orrs r1, r3
hadc->Init.Oversampling.RightBitShift |
hadc->Init.Oversampling.TriggeredMode
);
}
MODIFY_REG(hadc->Instance->CFGR2,
8002a44: 692b ldr r3, [r5, #16]
8002a46: 4f3f ldr r7, [pc, #252] @ (8002b44 <HAL_ADC_Init+0x208>)
8002a48: 403b ands r3, r7
8002a4a: 430b orrs r3, r1
ADC_CFGR2_TOVS,
tmpCFGR2);
/* Configuration of ADC clock mode: asynchronous clock source */
/* with selectable prescaler. */
if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
8002a4c: 2180 movs r1, #128 @ 0x80
MODIFY_REG(hadc->Instance->CFGR2,
8002a4e: 612b str r3, [r5, #16]
if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
8002a50: 0053 lsls r3, r2, #1
8002a52: 085b lsrs r3, r3, #1
8002a54: 05c9 lsls r1, r1, #23
8002a56: 428b cmp r3, r1
8002a58: d00c beq.n 8002a74 <HAL_ADC_Init+0x138>
((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
8002a5a: 2380 movs r3, #128 @ 0x80
8002a5c: 061b lsls r3, r3, #24
8002a5e: 429a cmp r2, r3
8002a60: d008 beq.n 8002a74 <HAL_ADC_Init+0x138>
((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4))
{
MODIFY_REG(ADC1_COMMON->CCR,
8002a62: 4939 ldr r1, [pc, #228] @ (8002b48 <HAL_ADC_Init+0x20c>)
8002a64: 4f39 ldr r7, [pc, #228] @ (8002b4c <HAL_ADC_Init+0x210>)
8002a66: 680b ldr r3, [r1, #0]
8002a68: 403b ands r3, r7
8002a6a: 27f0 movs r7, #240 @ 0xf0
8002a6c: 03bf lsls r7, r7, #14
8002a6e: 403a ands r2, r7
8002a70: 4313 orrs r3, r2
8002a72: 600b str r3, [r1, #0]
MODIFY_REG(ADCx->SMPR,
8002a74: 2107 movs r1, #7
8002a76: 2770 movs r7, #112 @ 0x70
8002a78: 696b ldr r3, [r5, #20]
hadc->Init.ClockPrescaler & ADC_CCR_PRESC);
}
}
/* Channel sampling time configuration */
LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
8002a7a: 6b62 ldr r2, [r4, #52] @ 0x34
8002a7c: 438b bics r3, r1
8002a7e: 4313 orrs r3, r2
8002a80: 616b str r3, [r5, #20]
8002a82: 6969 ldr r1, [r5, #20]
8002a84: 6ba3 ldr r3, [r4, #56] @ 0x38
8002a86: 43b9 bics r1, r7
8002a88: 011b lsls r3, r3, #4
8002a8a: 430b orrs r3, r1
8002a8c: 616b str r3, [r5, #20]
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion". */
/* Channels must be configured into each rank using function */
/* "HAL_ADC_ConfigChannel()". */
if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
8002a8e: 2800 cmp r0, #0
8002a90: d133 bne.n 8002afa <HAL_ADC_Init+0x1be>
{
/* Set sequencer scan length by clearing ranks above rank 1 */
/* and do not modify rank 1 value. */
SET_BIT(hadc->Instance->CHSELR,
8002a92: 2310 movs r3, #16
8002a94: 6aa9 ldr r1, [r5, #40] @ 0x28
8002a96: 425b negs r3, r3
/* therefore after the first call of "HAL_ADC_Init()", */
/* each rank corresponding to parameter "NbrOfConversion" */
/* must be set using "HAL_ADC_ConfigChannel()". */
/* - Set sequencer scan length by clearing ranks above maximum rank */
/* and do not modify other ranks value. */
MODIFY_REG(hadc->Instance->CHSELR,
8002a98: 430b orrs r3, r1
8002a9a: 62ab str r3, [r5, #40] @ 0x28
return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
8002a9c: 2107 movs r1, #7
8002a9e: 696b ldr r3, [r5, #20]
8002aa0: 400b ands r3, r1
{
/* Nothing to do */
}
/* Check back that ADC registers have effectively been configured to */
/* ensure of no potential problem of ADC core peripheral clocking. */
if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
8002aa2: 429a cmp r2, r3
8002aa4: d138 bne.n 8002b18 <HAL_ADC_Init+0x1dc>
== hadc->Init.SamplingTimeCommon1)
{
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8002aa6: 2300 movs r3, #0
8002aa8: 65e3 str r3, [r4, #92] @ 0x5c
/* Set the ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002aaa: 6da2 ldr r2, [r4, #88] @ 0x58
8002aac: 3303 adds r3, #3
8002aae: 439a bics r2, r3
8002ab0: 3b02 subs r3, #2
8002ab2: 4313 orrs r3, r2
8002ab4: 65a3 str r3, [r4, #88] @ 0x58
tmp_hal_status = HAL_ERROR;
}
/* Return function status */
return tmp_hal_status;
}
8002ab6: 9801 ldr r0, [sp, #4]
8002ab8: b005 add sp, #20
8002aba: bdf0 pop {r4, r5, r6, r7, pc}
MODIFY_REG(ADCx->CR,
8002abc: 68aa ldr r2, [r5, #8]
8002abe: 4924 ldr r1, [pc, #144] @ (8002b50 <HAL_ADC_Init+0x214>)
8002ac0: 400a ands r2, r1
8002ac2: 4313 orrs r3, r2
8002ac4: 60ab str r3, [r5, #8]
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
8002ac6: 4b23 ldr r3, [pc, #140] @ (8002b54 <HAL_ADC_Init+0x218>)
8002ac8: 4923 ldr r1, [pc, #140] @ (8002b58 <HAL_ADC_Init+0x21c>)
8002aca: 6818 ldr r0, [r3, #0]
8002acc: f7fd fb30 bl 8000130 <__udivsi3>
8002ad0: 0040 lsls r0, r0, #1
8002ad2: 9003 str r0, [sp, #12]
while (wait_loop_index != 0UL)
8002ad4: 9b03 ldr r3, [sp, #12]
8002ad6: 2b00 cmp r3, #0
8002ad8: d100 bne.n 8002adc <HAL_ADC_Init+0x1a0>
8002ada: e747 b.n 800296c <HAL_ADC_Init+0x30>
wait_loop_index--;
8002adc: 9b03 ldr r3, [sp, #12]
8002ade: 3b01 subs r3, #1
8002ae0: 9303 str r3, [sp, #12]
8002ae2: e7f7 b.n 8002ad4 <HAL_ADC_Init+0x198>
ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) |
8002ae4: 2180 movs r1, #128 @ 0x80
8002ae6: 0389 lsls r1, r1, #14
8002ae8: e778 b.n 80029dc <HAL_ADC_Init+0xa0>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002aea: 2220 movs r2, #32
8002aec: 6da7 ldr r7, [r4, #88] @ 0x58
8002aee: 433a orrs r2, r7
8002af0: 65a2 str r2, [r4, #88] @ 0x58
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002af2: 6de2 ldr r2, [r4, #92] @ 0x5c
8002af4: 4311 orrs r1, r2
8002af6: 65e1 str r1, [r4, #92] @ 0x5c
8002af8: e782 b.n 8002a00 <HAL_ADC_Init+0xc4>
else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
8002afa: 2380 movs r3, #128 @ 0x80
8002afc: 039b lsls r3, r3, #14
8002afe: 4298 cmp r0, r3
8002b00: d1cc bne.n 8002a9c <HAL_ADC_Init+0x160>
MODIFY_REG(hadc->Instance->CHSELR,
8002b02: 211c movs r1, #28
8002b04: 6aab ldr r3, [r5, #40] @ 0x28
8002b06: 69e3 ldr r3, [r4, #28]
8002b08: 3b01 subs r3, #1
8002b0a: 009b lsls r3, r3, #2
8002b0c: 400b ands r3, r1
8002b0e: 392c subs r1, #44 @ 0x2c
8002b10: 4099 lsls r1, r3
8002b12: 000b movs r3, r1
8002b14: 6e21 ldr r1, [r4, #96] @ 0x60
8002b16: e7bf b.n 8002a98 <HAL_ADC_Init+0x15c>
ADC_STATE_CLR_SET(hadc->State,
8002b18: 2312 movs r3, #18
8002b1a: 6da2 ldr r2, [r4, #88] @ 0x58
8002b1c: 439a bics r2, r3
8002b1e: 3b02 subs r3, #2
8002b20: 4313 orrs r3, r2
8002b22: 65a3 str r3, [r4, #88] @ 0x58
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002b24: 2301 movs r3, #1
8002b26: 6de2 ldr r2, [r4, #92] @ 0x5c
8002b28: 4313 orrs r3, r2
8002b2a: 65e3 str r3, [r4, #92] @ 0x5c
return HAL_ERROR;
8002b2c: 2301 movs r3, #1
8002b2e: 9301 str r3, [sp, #4]
8002b30: e7c1 b.n 8002ab6 <HAL_ADC_Init+0x17a>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002b32: 6da3 ldr r3, [r4, #88] @ 0x58
8002b34: 431a orrs r2, r3
8002b36: 65a2 str r2, [r4, #88] @ 0x58
tmp_hal_status = HAL_ERROR;
8002b38: e7f8 b.n 8002b2c <HAL_ADC_Init+0x1f0>
8002b3a: 46c0 nop @ (mov r8, r8)
8002b3c: fffffefd .word 0xfffffefd
8002b40: ffde0201 .word 0xffde0201
8002b44: 1ffffc02 .word 0x1ffffc02
8002b48: 40012708 .word 0x40012708
8002b4c: ffc3ffff .word 0xffc3ffff
8002b50: 6fffffe8 .word 0x6fffffe8
8002b54: 20000024 .word 0x20000024
8002b58: 00030d40 .word 0x00030d40
08002b5c <HAL_ADC_ConfigChannel>:
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig)
{
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0UL;
8002b5c: 2300 movs r3, #0
{
8002b5e: b5f0 push {r4, r5, r6, r7, lr}
8002b60: b085 sub sp, #20
__IO uint32_t wait_loop_index = 0UL;
8002b62: 9303 str r3, [sp, #12]
assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
}
/* Process locked */
__HAL_LOCK(hadc);
8002b64: 0003 movs r3, r0
{
8002b66: 9100 str r1, [sp, #0]
__HAL_LOCK(hadc);
8002b68: 3354 adds r3, #84 @ 0x54
8002b6a: 781a ldrb r2, [r3, #0]
{
8002b6c: 0004 movs r4, r0
__HAL_LOCK(hadc);
8002b6e: 2002 movs r0, #2
8002b70: 2a01 cmp r2, #1
8002b72: d04d beq.n 8002c10 <HAL_ADC_ConfigChannel+0xb4>
8002b74: 2201 movs r2, #1
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
8002b76: 6927 ldr r7, [r4, #16]
__HAL_LOCK(hadc);
8002b78: 701a strb r2, [r3, #0]
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel sampling time */
/* - Management of internal measurement channels: VrefInt/TempSensor */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
8002b7a: 6825 ldr r5, [r4, #0]
8002b7c: 0028 movs r0, r5
8002b7e: f7ff fed9 bl 8002934 <LL_ADC_REG_IsConversionOngoing>
8002b82: 2800 cmp r0, #0
8002b84: d000 beq.n 8002b88 <HAL_ADC_ConfigChannel+0x2c>
8002b86: e0f9 b.n 8002d7c <HAL_ADC_ConfigChannel+0x220>
/* If sequencer set to not fully configurable with channel rank set to */
/* none, remove the channel from the sequencer. */
/* Otherwise (sequencer set to fully configurable or to to not fully */
/* configurable with channel rank to be set), configure the selected */
/* channel. */
if (sConfig->Rank != ADC_RANK_NONE)
8002b88: 9b00 ldr r3, [sp, #0]
/* Note: ADC channel configuration requires few ADC clock cycles */
/* to be ready. Processing of ADC settings in this function */
/* induce that a specific wait time is not necessary. */
/* For more details on ADC channel configuration ready, */
/* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
8002b8a: 2204 movs r2, #4
if (sConfig->Rank != ADC_RANK_NONE)
8002b8c: 685b ldr r3, [r3, #4]
8002b8e: 2180 movs r1, #128 @ 0x80
8002b90: 469c mov ip, r3
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
8002b92: 4397 bics r7, r2
if (sConfig->Rank != ADC_RANK_NONE)
8002b94: 4662 mov r2, ip
(hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
{
/* Sequencer set to not fully configurable: */
/* Set the channel by enabling the corresponding bitfield. */
LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel);
8002b96: 9b00 ldr r3, [sp, #0]
8002b98: 0609 lsls r1, r1, #24
8002b9a: 681b ldr r3, [r3, #0]
if (sConfig->Rank != ADC_RANK_NONE)
8002b9c: 2a02 cmp r2, #2
8002b9e: d100 bne.n 8002ba2 <HAL_ADC_ConfigChannel+0x46>
8002ba0: e0c7 b.n 8002d32 <HAL_ADC_ConfigChannel+0x1d6>
SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
8002ba2: 025a lsls r2, r3, #9
8002ba4: 0a52 lsrs r2, r2, #9
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
8002ba6: 428f cmp r7, r1
8002ba8: d134 bne.n 8002c14 <HAL_ADC_ConfigChannel+0xb8>
8002baa: 6aa9 ldr r1, [r5, #40] @ 0x28
MODIFY_REG(ADCx->CHSELR,
8002bac: 430a orrs r2, r1
8002bae: 62aa str r2, [r5, #40] @ 0x28
MODIFY_REG(ADCx->SMPR,
8002bb0: 9a00 ldr r2, [sp, #0]
8002bb2: 6968 ldr r0, [r5, #20]
8002bb4: 6892 ldr r2, [r2, #8]
8002bb6: 0219 lsls r1, r3, #8
8002bb8: 4e73 ldr r6, [pc, #460] @ (8002d88 <HAL_ADC_ConfigChannel+0x22c>)
8002bba: 400a ands r2, r1
8002bbc: 4032 ands r2, r6
8002bbe: 4388 bics r0, r1
8002bc0: 4302 orrs r2, r0
8002bc2: 616a str r2, [r5, #20]
/* internal measurement paths enable: If internal channel selected, */
/* enable dedicated internal buffers and path. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit() or removing the channel from sequencer with */
/* channel configuration parameter "Rank". */
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
8002bc4: 2b00 cmp r3, #0
8002bc6: da1f bge.n 8002c08 <HAL_ADC_ConfigChannel+0xac>
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
8002bc8: 20c0 movs r0, #192 @ 0xc0
8002bca: 4a70 ldr r2, [pc, #448] @ (8002d8c <HAL_ADC_ConfigChannel+0x230>)
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
8002bcc: 4970 ldr r1, [pc, #448] @ (8002d90 <HAL_ADC_ConfigChannel+0x234>)
8002bce: 6815 ldr r5, [r2, #0]
8002bd0: 0400 lsls r0, r0, #16
8002bd2: 4028 ands r0, r5
8002bd4: 428b cmp r3, r1
8002bd6: d000 beq.n 8002bda <HAL_ADC_ConfigChannel+0x7e>
8002bd8: e09b b.n 8002d12 <HAL_ADC_ConfigChannel+0x1b6>
((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
8002bda: 2180 movs r1, #128 @ 0x80
8002bdc: 0409 lsls r1, r1, #16
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
8002bde: 420d tst r5, r1
8002be0: d112 bne.n 8002c08 <HAL_ADC_ConfigChannel+0xac>
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
8002be2: 6813 ldr r3, [r2, #0]
8002be4: 4d6b ldr r5, [pc, #428] @ (8002d94 <HAL_ADC_ConfigChannel+0x238>)
8002be6: 402b ands r3, r5
8002be8: 4303 orrs r3, r0
8002bea: 4319 orrs r1, r3
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL);
8002bec: 4b6a ldr r3, [pc, #424] @ (8002d98 <HAL_ADC_ConfigChannel+0x23c>)
8002bee: 6011 str r1, [r2, #0]
8002bf0: 6818 ldr r0, [r3, #0]
8002bf2: 496a ldr r1, [pc, #424] @ (8002d9c <HAL_ADC_ConfigChannel+0x240>)
8002bf4: f7fd fa9c bl 8000130 <__udivsi3>
8002bf8: 230c movs r3, #12
8002bfa: 4343 muls r3, r0
8002bfc: 3301 adds r3, #1
while (wait_loop_index != 0UL)
{
wait_loop_index--;
8002bfe: 9303 str r3, [sp, #12]
while (wait_loop_index != 0UL)
8002c00: 9b03 ldr r3, [sp, #12]
8002c02: 2b00 cmp r3, #0
8002c04: d000 beq.n 8002c08 <HAL_ADC_ConfigChannel+0xac>
8002c06: e081 b.n 8002d0c <HAL_ADC_ConfigChannel+0x1b0>
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002c08: 2000 movs r0, #0
tmp_hal_status = HAL_ERROR;
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002c0a: 2300 movs r3, #0
8002c0c: 3454 adds r4, #84 @ 0x54
8002c0e: 7023 strb r3, [r4, #0]
/* Return function status */
return tmp_hal_status;
}
8002c10: b005 add sp, #20
8002c12: bdf0 pop {r4, r5, r6, r7, pc}
MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
8002c14: 211f movs r1, #31
8002c16: 4667 mov r7, ip
8002c18: 400f ands r7, r1
8002c1a: 3910 subs r1, #16
8002c1c: 40b9 lsls r1, r7
8002c1e: 43ce mvns r6, r1
8002c20: 9601 str r6, [sp, #4]
8002c22: 6e26 ldr r6, [r4, #96] @ 0x60
8002c24: 438e bics r6, r1
8002c26: 0031 movs r1, r6
8002c28: 2a00 cmp r2, #0
8002c2a: d112 bne.n 8002c52 <HAL_ADC_ConfigChannel+0xf6>
8002c2c: 0e98 lsrs r0, r3, #26
8002c2e: 321f adds r2, #31
8002c30: 4010 ands r0, r2
8002c32: 40b8 lsls r0, r7
if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
8002c34: 4662 mov r2, ip
MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
8002c36: 4308 orrs r0, r1
if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
8002c38: 0892 lsrs r2, r2, #2
8002c3a: 69e1 ldr r1, [r4, #28]
8002c3c: 3201 adds r2, #1
MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
8002c3e: 6620 str r0, [r4, #96] @ 0x60
if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
8002c40: 428a cmp r2, r1
8002c42: d8b5 bhi.n 8002bb0 <HAL_ADC_ConfigChannel+0x54>
MODIFY_REG(ADCx->CHSELR,
8002c44: 6aa9 ldr r1, [r5, #40] @ 0x28
8002c46: 9801 ldr r0, [sp, #4]
8002c48: 009a lsls r2, r3, #2
8002c4a: 0f12 lsrs r2, r2, #28
8002c4c: 40ba lsls r2, r7
8002c4e: 4001 ands r1, r0
8002c50: e7ac b.n 8002bac <HAL_ADC_ConfigChannel+0x50>
MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
8002c52: 2201 movs r2, #1
8002c54: 4213 tst r3, r2
8002c56: d1ec bne.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002c58: 1892 adds r2, r2, r2
8002c5a: 4213 tst r3, r2
8002c5c: d12c bne.n 8002cb8 <HAL_ADC_ConfigChannel+0x15c>
8002c5e: 2604 movs r6, #4
8002c60: 4233 tst r3, r6
8002c62: d12b bne.n 8002cbc <HAL_ADC_ConfigChannel+0x160>
8002c64: 071a lsls r2, r3, #28
8002c66: d42b bmi.n 8002cc0 <HAL_ADC_ConfigChannel+0x164>
8002c68: 06da lsls r2, r3, #27
8002c6a: d42b bmi.n 8002cc4 <HAL_ADC_ConfigChannel+0x168>
8002c6c: 069a lsls r2, r3, #26
8002c6e: d42b bmi.n 8002cc8 <HAL_ADC_ConfigChannel+0x16c>
8002c70: 065a lsls r2, r3, #25
8002c72: d42b bmi.n 8002ccc <HAL_ADC_ConfigChannel+0x170>
8002c74: 061a lsls r2, r3, #24
8002c76: d42b bmi.n 8002cd0 <HAL_ADC_ConfigChannel+0x174>
8002c78: 05da lsls r2, r3, #23
8002c7a: d42b bmi.n 8002cd4 <HAL_ADC_ConfigChannel+0x178>
8002c7c: 059a lsls r2, r3, #22
8002c7e: d42b bmi.n 8002cd8 <HAL_ADC_ConfigChannel+0x17c>
8002c80: 055a lsls r2, r3, #21
8002c82: d42b bmi.n 8002cdc <HAL_ADC_ConfigChannel+0x180>
8002c84: 051a lsls r2, r3, #20
8002c86: d42b bmi.n 8002ce0 <HAL_ADC_ConfigChannel+0x184>
8002c88: 04da lsls r2, r3, #19
8002c8a: d42b bmi.n 8002ce4 <HAL_ADC_ConfigChannel+0x188>
8002c8c: 049a lsls r2, r3, #18
8002c8e: d42b bmi.n 8002ce8 <HAL_ADC_ConfigChannel+0x18c>
8002c90: 045a lsls r2, r3, #17
8002c92: d42b bmi.n 8002cec <HAL_ADC_ConfigChannel+0x190>
8002c94: 041a lsls r2, r3, #16
8002c96: d42b bmi.n 8002cf0 <HAL_ADC_ConfigChannel+0x194>
8002c98: 03da lsls r2, r3, #15
8002c9a: d42b bmi.n 8002cf4 <HAL_ADC_ConfigChannel+0x198>
8002c9c: 039a lsls r2, r3, #14
8002c9e: d42b bmi.n 8002cf8 <HAL_ADC_ConfigChannel+0x19c>
8002ca0: 035a lsls r2, r3, #13
8002ca2: d42b bmi.n 8002cfc <HAL_ADC_ConfigChannel+0x1a0>
8002ca4: 031a lsls r2, r3, #12
8002ca6: d42b bmi.n 8002d00 <HAL_ADC_ConfigChannel+0x1a4>
8002ca8: 02da lsls r2, r3, #11
8002caa: d42b bmi.n 8002d04 <HAL_ADC_ConfigChannel+0x1a8>
8002cac: 029a lsls r2, r3, #10
8002cae: d42b bmi.n 8002d08 <HAL_ADC_ConfigChannel+0x1ac>
8002cb0: 025a lsls r2, r3, #9
8002cb2: d5be bpl.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cb4: 2016 movs r0, #22
8002cb6: e7bc b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cb8: 2001 movs r0, #1
8002cba: e7ba b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cbc: 0010 movs r0, r2
8002cbe: e7b8 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cc0: 2003 movs r0, #3
8002cc2: e7b6 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cc4: 2004 movs r0, #4
8002cc6: e7b4 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cc8: 2005 movs r0, #5
8002cca: e7b2 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002ccc: 2006 movs r0, #6
8002cce: e7b0 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cd0: 2007 movs r0, #7
8002cd2: e7ae b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cd4: 2008 movs r0, #8
8002cd6: e7ac b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cd8: 2009 movs r0, #9
8002cda: e7aa b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cdc: 200a movs r0, #10
8002cde: e7a8 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002ce0: 200b movs r0, #11
8002ce2: e7a6 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002ce4: 200c movs r0, #12
8002ce6: e7a4 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002ce8: 200d movs r0, #13
8002cea: e7a2 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cec: 200e movs r0, #14
8002cee: e7a0 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cf0: 200f movs r0, #15
8002cf2: e79e b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cf4: 2010 movs r0, #16
8002cf6: e79c b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cf8: 2011 movs r0, #17
8002cfa: e79a b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002cfc: 2012 movs r0, #18
8002cfe: e798 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002d00: 2013 movs r0, #19
8002d02: e796 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002d04: 2014 movs r0, #20
8002d06: e794 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
8002d08: 2015 movs r0, #21
8002d0a: e792 b.n 8002c32 <HAL_ADC_ConfigChannel+0xd6>
wait_loop_index--;
8002d0c: 9b03 ldr r3, [sp, #12]
8002d0e: 3b01 subs r3, #1
8002d10: e775 b.n 8002bfe <HAL_ADC_ConfigChannel+0xa2>
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) &&
8002d12: 4923 ldr r1, [pc, #140] @ (8002da0 <HAL_ADC_ConfigChannel+0x244>)
8002d14: 428b cmp r3, r1
8002d16: d000 beq.n 8002d1a <HAL_ADC_ConfigChannel+0x1be>
8002d18: e776 b.n 8002c08 <HAL_ADC_ConfigChannel+0xac>
((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
8002d1a: 2180 movs r1, #128 @ 0x80
8002d1c: 03c9 lsls r1, r1, #15
else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) &&
8002d1e: 420d tst r5, r1
8002d20: d000 beq.n 8002d24 <HAL_ADC_ConfigChannel+0x1c8>
8002d22: e771 b.n 8002c08 <HAL_ADC_ConfigChannel+0xac>
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
8002d24: 6813 ldr r3, [r2, #0]
8002d26: 4d1b ldr r5, [pc, #108] @ (8002d94 <HAL_ADC_ConfigChannel+0x238>)
8002d28: 402b ands r3, r5
8002d2a: 4303 orrs r3, r0
8002d2c: 4319 orrs r1, r3
8002d2e: 6011 str r1, [r2, #0]
}
8002d30: e76a b.n 8002c08 <HAL_ADC_ConfigChannel+0xac>
if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) ||
8002d32: 428f cmp r7, r1
8002d34: d104 bne.n 8002d40 <HAL_ADC_ConfigChannel+0x1e4>
CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
8002d36: 6aaa ldr r2, [r5, #40] @ 0x28
8002d38: 0259 lsls r1, r3, #9
8002d3a: 0a49 lsrs r1, r1, #9
8002d3c: 438a bics r2, r1
8002d3e: 62aa str r2, [r5, #40] @ 0x28
if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
8002d40: 2b00 cmp r3, #0
8002d42: db00 blt.n 8002d46 <HAL_ADC_ConfigChannel+0x1ea>
8002d44: e760 b.n 8002c08 <HAL_ADC_ConfigChannel+0xac>
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
8002d46: 4911 ldr r1, [pc, #68] @ (8002d8c <HAL_ADC_ConfigChannel+0x230>)
if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
8002d48: 4811 ldr r0, [pc, #68] @ (8002d90 <HAL_ADC_ConfigChannel+0x234>)
8002d4a: 680a ldr r2, [r1, #0]
8002d4c: 4283 cmp r3, r0
8002d4e: d108 bne.n 8002d62 <HAL_ADC_ConfigChannel+0x206>
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002d50: 2380 movs r3, #128 @ 0x80
8002d52: 03db lsls r3, r3, #15
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
8002d54: 6808 ldr r0, [r1, #0]
8002d56: 4013 ands r3, r2
8002d58: 4a0e ldr r2, [pc, #56] @ (8002d94 <HAL_ADC_ConfigChannel+0x238>)
8002d5a: 4002 ands r2, r0
8002d5c: 4313 orrs r3, r2
8002d5e: 600b str r3, [r1, #0]
}
8002d60: e752 b.n 8002c08 <HAL_ADC_ConfigChannel+0xac>
else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
8002d62: 480f ldr r0, [pc, #60] @ (8002da0 <HAL_ADC_ConfigChannel+0x244>)
8002d64: 4283 cmp r3, r0
8002d66: d000 beq.n 8002d6a <HAL_ADC_ConfigChannel+0x20e>
8002d68: e74e b.n 8002c08 <HAL_ADC_ConfigChannel+0xac>
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002d6a: 2080 movs r0, #128 @ 0x80
8002d6c: 0400 lsls r0, r0, #16
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
8002d6e: 680b ldr r3, [r1, #0]
8002d70: 4002 ands r2, r0
8002d72: 4808 ldr r0, [pc, #32] @ (8002d94 <HAL_ADC_ConfigChannel+0x238>)
8002d74: 4003 ands r3, r0
8002d76: 431a orrs r2, r3
8002d78: 600a str r2, [r1, #0]
}
8002d7a: e745 b.n 8002c08 <HAL_ADC_ConfigChannel+0xac>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002d7c: 2320 movs r3, #32
8002d7e: 6da2 ldr r2, [r4, #88] @ 0x58
tmp_hal_status = HAL_ERROR;
8002d80: 2001 movs r0, #1
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002d82: 4313 orrs r3, r2
8002d84: 65a3 str r3, [r4, #88] @ 0x58
tmp_hal_status = HAL_ERROR;
8002d86: e740 b.n 8002c0a <HAL_ADC_ConfigChannel+0xae>
8002d88: 7fffff00 .word 0x7fffff00
8002d8c: 40012708 .word 0x40012708
8002d90: a4000200 .word 0xa4000200
8002d94: ff3fffff .word 0xff3fffff
8002d98: 20000024 .word 0x20000024
8002d9c: 00030d40 .word 0x00030d40
8002da0: a8000400 .word 0xa8000400
08002da4 <HAL_NVIC_SetPriority>:
* with stm32c0xx devices, this parameter is a dummy value and it is ignored, because
* no subpriority supported in Cortex M0+ based products.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8002da4: b510 push {r4, lr}
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002da6: 24ff movs r4, #255 @ 0xff
8002da8: 2203 movs r2, #3
8002daa: 000b movs r3, r1
8002dac: 0021 movs r1, r4
8002dae: 4002 ands r2, r0
8002db0: 00d2 lsls r2, r2, #3
8002db2: 4091 lsls r1, r2
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8002db4: 019b lsls r3, r3, #6
8002db6: 4023 ands r3, r4
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002db8: 43c9 mvns r1, r1
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
8002dba: 4093 lsls r3, r2
if ((int32_t)(IRQn) >= 0)
8002dbc: 2800 cmp r0, #0
8002dbe: db0a blt.n 8002dd6 <HAL_NVIC_SetPriority+0x32>
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002dc0: 24c0 movs r4, #192 @ 0xc0
8002dc2: 4a0b ldr r2, [pc, #44] @ (8002df0 <HAL_NVIC_SetPriority+0x4c>)
8002dc4: 0880 lsrs r0, r0, #2
8002dc6: 0080 lsls r0, r0, #2
8002dc8: 1880 adds r0, r0, r2
8002dca: 00a4 lsls r4, r4, #2
8002dcc: 5902 ldr r2, [r0, r4]
8002dce: 400a ands r2, r1
8002dd0: 4313 orrs r3, r2
8002dd2: 5103 str r3, [r0, r4]
/* Prevent unused argument(s) compilation warning */
UNUSED(SubPriority);
/* Check the parameters */
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
NVIC_SetPriority(IRQn, PreemptPriority);
}
8002dd4: bd10 pop {r4, pc}
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002dd6: 220f movs r2, #15
8002dd8: 4010 ands r0, r2
8002dda: 3808 subs r0, #8
8002ddc: 4a05 ldr r2, [pc, #20] @ (8002df4 <HAL_NVIC_SetPriority+0x50>)
8002dde: 0880 lsrs r0, r0, #2
8002de0: 0080 lsls r0, r0, #2
8002de2: 1880 adds r0, r0, r2
8002de4: 69c2 ldr r2, [r0, #28]
8002de6: 4011 ands r1, r2
8002de8: 4319 orrs r1, r3
8002dea: 61c1 str r1, [r0, #28]
8002dec: e7f2 b.n 8002dd4 <HAL_NVIC_SetPriority+0x30>
8002dee: 46c0 nop @ (mov r8, r8)
8002df0: e000e100 .word 0xe000e100
8002df4: e000ed00 .word 0xe000ed00
08002df8 <HAL_NVIC_EnableIRQ>:
if ((int32_t)(IRQn) >= 0)
8002df8: 2800 cmp r0, #0
8002dfa: db05 blt.n 8002e08 <HAL_NVIC_EnableIRQ+0x10>
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8002dfc: 231f movs r3, #31
8002dfe: 4018 ands r0, r3
8002e00: 3b1e subs r3, #30
8002e02: 4083 lsls r3, r0
8002e04: 4a01 ldr r2, [pc, #4] @ (8002e0c <HAL_NVIC_EnableIRQ+0x14>)
8002e06: 6013 str r3, [r2, #0]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
}
8002e08: 4770 bx lr
8002e0a: 46c0 nop @ (mov r8, r8)
8002e0c: e000e100 .word 0xe000e100
08002e10 <HAL_SYSTICK_Config>:
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8002e10: 2280 movs r2, #128 @ 0x80
8002e12: 1e43 subs r3, r0, #1
8002e14: 0452 lsls r2, r2, #17
{
return (1UL); /* Reload value impossible */
8002e16: 2001 movs r0, #1
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8002e18: 4293 cmp r3, r2
8002e1a: d20d bcs.n 8002e38 <HAL_SYSTICK_Config+0x28>
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002e1c: 21c0 movs r1, #192 @ 0xc0
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8002e1e: 4a07 ldr r2, [pc, #28] @ (8002e3c <HAL_SYSTICK_Config+0x2c>)
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002e20: 4807 ldr r0, [pc, #28] @ (8002e40 <HAL_SYSTICK_Config+0x30>)
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8002e22: 6053 str r3, [r2, #4]
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
8002e24: 6a03 ldr r3, [r0, #32]
8002e26: 0609 lsls r1, r1, #24
8002e28: 021b lsls r3, r3, #8
8002e2a: 0a1b lsrs r3, r3, #8
8002e2c: 430b orrs r3, r1
8002e2e: 6203 str r3, [r0, #32]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8002e30: 2000 movs r0, #0
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8002e32: 2307 movs r3, #7
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8002e34: 6090 str r0, [r2, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8002e36: 6013 str r3, [r2, #0]
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
return SysTick_Config(TicksNumb);
}
8002e38: 4770 bx lr
8002e3a: 46c0 nop @ (mov r8, r8)
8002e3c: e000e010 .word 0xe000e010
8002e40: e000ed00 .word 0xe000ed00
08002e44 <DMA_SetConfig>:
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
8002e44: b5f0 push {r4, r5, r6, r7, lr}
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8002e46: 6c84 ldr r4, [r0, #72] @ 0x48
8002e48: 6cc5 ldr r5, [r0, #76] @ 0x4c
8002e4a: 6065 str r5, [r4, #4]
if (hdma->DMAmuxRequestGen != 0U)
8002e4c: 6d04 ldr r4, [r0, #80] @ 0x50
8002e4e: 2c00 cmp r4, #0
8002e50: d002 beq.n 8002e58 <DMA_SetConfig+0x14>
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8002e52: 6d44 ldr r4, [r0, #84] @ 0x54
8002e54: 6d85 ldr r5, [r0, #88] @ 0x58
8002e56: 6065 str r5, [r4, #4]
}
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU)));
8002e58: 241c movs r4, #28
8002e5a: 6c05 ldr r5, [r0, #64] @ 0x40
8002e5c: 4e08 ldr r6, [pc, #32] @ (8002e80 <DMA_SetConfig+0x3c>)
8002e5e: 4025 ands r5, r4
8002e60: 3c1b subs r4, #27
8002e62: 40ac lsls r4, r5
8002e64: 6877 ldr r7, [r6, #4]
8002e66: 433c orrs r4, r7
8002e68: 6074 str r4, [r6, #4]
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
8002e6a: 6804 ldr r4, [r0, #0]
8002e6c: 6063 str r3, [r4, #4]
/* Peripheral to Memory */
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
8002e6e: 6883 ldr r3, [r0, #8]
8002e70: 2b10 cmp r3, #16
8002e72: d102 bne.n 8002e7a <DMA_SetConfig+0x36>
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
8002e74: 60a2 str r2, [r4, #8]
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
8002e76: 60e1 str r1, [r4, #12]
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
}
8002e78: bdf0 pop {r4, r5, r6, r7, pc}
hdma->Instance->CPAR = SrcAddress;
8002e7a: 60a1 str r1, [r4, #8]
hdma->Instance->CMAR = DstAddress;
8002e7c: 60e2 str r2, [r4, #12]
}
8002e7e: e7fb b.n 8002e78 <DMA_SetConfig+0x34>
8002e80: 40020000 .word 0x40020000
08002e84 <DMA_CalcDMAMUXChannelBaseAndMask>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval None
*/
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
{
8002e84: b510 push {r4, lr}
8002e86: 0004 movs r4, r0
uint32_t channel_number;
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
8002e88: 6800 ldr r0, [r0, #0]
8002e8a: 2114 movs r1, #20
8002e8c: b2c0 uxtb r0, r0
8002e8e: 3808 subs r0, #8
8002e90: f7fd f94e bl 8000130 <__udivsi3>
hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \
((hdma->ChannelIndex >> 2U) * \
8002e94: 6c23 ldr r3, [r4, #64] @ 0x40
hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \
8002e96: 4a06 ldr r2, [pc, #24] @ (8002eb0 <DMA_CalcDMAMUXChannelBaseAndMask+0x2c>)
((hdma->ChannelIndex >> 2U) * \
8002e98: 089b lsrs r3, r3, #2
hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \
8002e9a: 189b adds r3, r3, r2
8002e9c: 009b lsls r3, r3, #2
8002e9e: 6463 str r3, [r4, #68] @ 0x44
((uint32_t)DMAMUX1_Channel1 - \
(uint32_t)DMAMUX1_Channel0)));
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
8002ea0: 4b04 ldr r3, [pc, #16] @ (8002eb4 <DMA_CalcDMAMUXChannelBaseAndMask+0x30>)
8002ea2: 64a3 str r3, [r4, #72] @ 0x48
hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU);
8002ea4: 231c movs r3, #28
8002ea6: 4018 ands r0, r3
8002ea8: 3b1b subs r3, #27
8002eaa: 4083 lsls r3, r0
8002eac: 64e3 str r3, [r4, #76] @ 0x4c
}
8002eae: bd10 pop {r4, pc}
8002eb0: 10008200 .word 0x10008200
8002eb4: 40020880 .word 0x40020880
08002eb8 <HAL_DMA_Init>:
{
8002eb8: b5f8 push {r3, r4, r5, r6, r7, lr}
8002eba: 0004 movs r4, r0
return HAL_ERROR;
8002ebc: 2001 movs r0, #1
if (hdma == NULL)
8002ebe: 2c00 cmp r4, #0
8002ec0: d045 beq.n 8002f4e <HAL_DMA_Init+0x96>
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \
8002ec2: 6825 ldr r5, [r4, #0]
8002ec4: 4b25 ldr r3, [pc, #148] @ (8002f5c <HAL_DMA_Init+0xa4>)
8002ec6: 2114 movs r1, #20
8002ec8: 18e8 adds r0, r5, r3
8002eca: f7fd f931 bl 8000130 <__udivsi3>
hdma->State = HAL_DMA_STATE_BUSY;
8002ece: 2302 movs r3, #2
(uint32_t)DMA1_Channel1)) << 2U;
8002ed0: 0080 lsls r0, r0, #2
hdma->State = HAL_DMA_STATE_BUSY;
8002ed2: 1da6 adds r6, r4, #6
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \
8002ed4: 6420 str r0, [r4, #64] @ 0x40
hdma->State = HAL_DMA_STATE_BUSY;
8002ed6: 77f3 strb r3, [r6, #31]
CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
8002ed8: 682b ldr r3, [r5, #0]
8002eda: 4a21 ldr r2, [pc, #132] @ (8002f60 <HAL_DMA_Init+0xa8>)
SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \
8002edc: 68a7 ldr r7, [r4, #8]
CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \
8002ede: 4013 ands r3, r2
8002ee0: 602b str r3, [r5, #0]
SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \
8002ee2: 68e3 ldr r3, [r4, #12]
8002ee4: 6921 ldr r1, [r4, #16]
8002ee6: 433b orrs r3, r7
8002ee8: 430b orrs r3, r1
8002eea: 6961 ldr r1, [r4, #20]
8002eec: 682a ldr r2, [r5, #0]
8002eee: 430b orrs r3, r1
8002ef0: 69a1 ldr r1, [r4, #24]
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
8002ef2: 0020 movs r0, r4
SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \
8002ef4: 430b orrs r3, r1
8002ef6: 69e1 ldr r1, [r4, #28]
8002ef8: 430b orrs r3, r1
8002efa: 6a21 ldr r1, [r4, #32]
8002efc: 430b orrs r3, r1
8002efe: 4313 orrs r3, r2
8002f00: 602b str r3, [r5, #0]
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
8002f02: f7ff ffbf bl 8002e84 <DMA_CalcDMAMUXChannelBaseAndMask>
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
8002f06: 2380 movs r3, #128 @ 0x80
8002f08: 01db lsls r3, r3, #7
8002f0a: 429f cmp r7, r3
8002f0c: d101 bne.n 8002f12 <HAL_DMA_Init+0x5a>
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
8002f0e: 2300 movs r3, #0
8002f10: 6063 str r3, [r4, #4]
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
8002f12: 6862 ldr r2, [r4, #4]
8002f14: 6c61 ldr r1, [r4, #68] @ 0x44
8002f16: b2d3 uxtb r3, r2
8002f18: 600b str r3, [r1, #0]
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8002f1a: 6ce0 ldr r0, [r4, #76] @ 0x4c
8002f1c: 6ca1 ldr r1, [r4, #72] @ 0x48
if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
8002f1e: 3a01 subs r2, #1
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8002f20: 6048 str r0, [r1, #4]
if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
8002f22: 2a03 cmp r2, #3
8002f24: d814 bhi.n 8002f50 <HAL_DMA_Init+0x98>
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
{
uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
/* DMA Channels are connected to DMAMUX1 request generator blocks*/
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \
8002f26: 4a0f ldr r2, [pc, #60] @ (8002f64 <HAL_DMA_Init+0xac>)
((request - 1U) * 4U)));
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
8002f28: 480f ldr r0, [pc, #60] @ (8002f68 <HAL_DMA_Init+0xb0>)
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \
8002f2a: 1899 adds r1, r3, r2
/* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/
hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
8002f2c: 2201 movs r2, #1
8002f2e: 3b01 subs r3, #1
8002f30: 409a lsls r2, r3
8002f32: 65a2 str r2, [r4, #88] @ 0x58
8002f34: 0013 movs r3, r2
hdma->DMAmuxRequestGen->RGCR = 0U;
8002f36: 2200 movs r2, #0
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \
8002f38: 0089 lsls r1, r1, #2
8002f3a: 6521 str r1, [r4, #80] @ 0x50
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
8002f3c: 6560 str r0, [r4, #84] @ 0x54
hdma->DMAmuxRequestGen->RGCR = 0U;
8002f3e: 600a str r2, [r1, #0]
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8002f40: 6043 str r3, [r0, #4]
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8002f42: 2000 movs r0, #0
hdma->State = HAL_DMA_STATE_READY;
8002f44: 2301 movs r3, #1
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8002f46: 63e0 str r0, [r4, #60] @ 0x3c
__HAL_UNLOCK(hdma);
8002f48: 3405 adds r4, #5
hdma->State = HAL_DMA_STATE_READY;
8002f4a: 77f3 strb r3, [r6, #31]
__HAL_UNLOCK(hdma);
8002f4c: 77e0 strb r0, [r4, #31]
}
8002f4e: bdf8 pop {r3, r4, r5, r6, r7, pc}
hdma->DMAmuxRequestGen = 0U;
8002f50: 2300 movs r3, #0
8002f52: 6523 str r3, [r4, #80] @ 0x50
hdma->DMAmuxRequestGenStatus = 0U;
8002f54: 6563 str r3, [r4, #84] @ 0x54
hdma->DMAmuxRequestGenStatusMask = 0U;
8002f56: 65a3 str r3, [r4, #88] @ 0x58
8002f58: e7f3 b.n 8002f42 <HAL_DMA_Init+0x8a>
8002f5a: 46c0 nop @ (mov r8, r8)
8002f5c: bffdfff8 .word 0xbffdfff8
8002f60: ffff800f .word 0xffff800f
8002f64: 1000823f .word 0x1000823f
8002f68: 40020940 .word 0x40020940
08002f6c <HAL_DMA_Start_IT>:
{
8002f6c: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
__HAL_LOCK(hdma);
8002f6e: 1d46 adds r6, r0, #5
{
8002f70: 9301 str r3, [sp, #4]
__HAL_LOCK(hdma);
8002f72: 7ff4 ldrb r4, [r6, #31]
{
8002f74: 0005 movs r5, r0
__HAL_LOCK(hdma);
8002f76: 2002 movs r0, #2
8002f78: 2c01 cmp r4, #1
8002f7a: d036 beq.n 8002fea <HAL_DMA_Start_IT+0x7e>
8002f7c: 3801 subs r0, #1
8002f7e: 77f0 strb r0, [r6, #31]
if (HAL_DMA_STATE_READY == hdma->State)
8002f80: 1dac adds r4, r5, #6
8002f82: 7fe0 ldrb r0, [r4, #31]
8002f84: 2702 movs r7, #2
8002f86: 4684 mov ip, r0
8002f88: 4663 mov r3, ip
8002f8a: b2c0 uxtb r0, r0
8002f8c: 9000 str r0, [sp, #0]
status = HAL_BUSY;
8002f8e: 0038 movs r0, r7
if (HAL_DMA_STATE_READY == hdma->State)
8002f90: 2b01 cmp r3, #1
8002f92: d128 bne.n 8002fe6 <HAL_DMA_Start_IT+0x7a>
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8002f94: 2000 movs r0, #0
hdma->State = HAL_DMA_STATE_BUSY;
8002f96: 77e7 strb r7, [r4, #31]
__HAL_DMA_DISABLE(hdma);
8002f98: 682c ldr r4, [r5, #0]
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8002f9a: 63e8 str r0, [r5, #60] @ 0x3c
__HAL_DMA_DISABLE(hdma);
8002f9c: 6820 ldr r0, [r4, #0]
8002f9e: 9b00 ldr r3, [sp, #0]
8002fa0: 4398 bics r0, r3
8002fa2: 6020 str r0, [r4, #0]
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
8002fa4: 9b01 ldr r3, [sp, #4]
8002fa6: 0028 movs r0, r5
8002fa8: f7ff ff4c bl 8002e44 <DMA_SetConfig>
if (NULL != hdma->XferHalfCpltCallback)
8002fac: 6b2b ldr r3, [r5, #48] @ 0x30
8002fae: 2b00 cmp r3, #0
8002fb0: d01c beq.n 8002fec <HAL_DMA_Start_IT+0x80>
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8002fb2: 230e movs r3, #14
8002fb4: 6822 ldr r2, [r4, #0]
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
8002fb6: 4313 orrs r3, r2
8002fb8: 6023 str r3, [r4, #0]
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
8002fba: 6c6b ldr r3, [r5, #68] @ 0x44
8002fbc: 681a ldr r2, [r3, #0]
8002fbe: 03d2 lsls r2, r2, #15
8002fc0: d504 bpl.n 8002fcc <HAL_DMA_Start_IT+0x60>
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
8002fc2: 2280 movs r2, #128 @ 0x80
8002fc4: 6819 ldr r1, [r3, #0]
8002fc6: 0052 lsls r2, r2, #1
8002fc8: 430a orrs r2, r1
8002fca: 601a str r2, [r3, #0]
if (hdma->DMAmuxRequestGen != 0U)
8002fcc: 6d2b ldr r3, [r5, #80] @ 0x50
8002fce: 2b00 cmp r3, #0
8002fd0: d004 beq.n 8002fdc <HAL_DMA_Start_IT+0x70>
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
8002fd2: 2280 movs r2, #128 @ 0x80
8002fd4: 6819 ldr r1, [r3, #0]
8002fd6: 0052 lsls r2, r2, #1
8002fd8: 430a orrs r2, r1
8002fda: 601a str r2, [r3, #0]
__HAL_DMA_ENABLE(hdma);
8002fdc: 2301 movs r3, #1
HAL_StatusTypeDef status = HAL_OK;
8002fde: 2000 movs r0, #0
__HAL_DMA_ENABLE(hdma);
8002fe0: 6822 ldr r2, [r4, #0]
8002fe2: 4313 orrs r3, r2
8002fe4: 6023 str r3, [r4, #0]
__HAL_UNLOCK(hdma);
8002fe6: 2300 movs r3, #0
8002fe8: 77f3 strb r3, [r6, #31]
}
8002fea: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8002fec: 2204 movs r2, #4
8002fee: 6823 ldr r3, [r4, #0]
8002ff0: 4393 bics r3, r2
8002ff2: 6023 str r3, [r4, #0]
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
8002ff4: 6822 ldr r2, [r4, #0]
8002ff6: 230a movs r3, #10
8002ff8: e7dd b.n 8002fb6 <HAL_DMA_Start_IT+0x4a>
...
08002ffc <HAL_DMA_Abort>:
{
8002ffc: b5f0 push {r4, r5, r6, r7, lr}
if (NULL == hdma)
8002ffe: 2800 cmp r0, #0
8003000: d008 beq.n 8003014 <HAL_DMA_Abort+0x18>
if (hdma->State != HAL_DMA_STATE_BUSY)
8003002: 1d84 adds r4, r0, #6
8003004: 7fe3 ldrb r3, [r4, #31]
8003006: 1d41 adds r1, r0, #5
8003008: 2b02 cmp r3, #2
800300a: d005 beq.n 8003018 <HAL_DMA_Abort+0x1c>
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
800300c: 2304 movs r3, #4
800300e: 63c3 str r3, [r0, #60] @ 0x3c
__HAL_UNLOCK(hdma);
8003010: 2300 movs r3, #0
8003012: 77cb strb r3, [r1, #31]
return HAL_ERROR;
8003014: 2001 movs r0, #1
}
8003016: bdf0 pop {r4, r5, r6, r7, pc}
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003018: 250e movs r5, #14
800301a: 6802 ldr r2, [r0, #0]
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
800301c: 6c46 ldr r6, [r0, #68] @ 0x44
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800301e: 6813 ldr r3, [r2, #0]
8003020: 43ab bics r3, r5
8003022: 6013 str r3, [r2, #0]
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8003024: 6833 ldr r3, [r6, #0]
8003026: 4d10 ldr r5, [pc, #64] @ (8003068 <HAL_DMA_Abort+0x6c>)
8003028: 402b ands r3, r5
800302a: 6033 str r3, [r6, #0]
__HAL_DMA_DISABLE(hdma);
800302c: 2301 movs r3, #1
800302e: 6816 ldr r6, [r2, #0]
8003030: 439e bics r6, r3
8003032: 6016 str r6, [r2, #0]
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1cU)));
8003034: 6c02 ldr r2, [r0, #64] @ 0x40
8003036: 331b adds r3, #27
8003038: 401a ands r2, r3
800303a: 3b1b subs r3, #27
800303c: 4093 lsls r3, r2
800303e: 4e0b ldr r6, [pc, #44] @ (800306c <HAL_DMA_Abort+0x70>)
8003040: 6877 ldr r7, [r6, #4]
8003042: 433b orrs r3, r7
8003044: 6073 str r3, [r6, #4]
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8003046: 6cc2 ldr r2, [r0, #76] @ 0x4c
8003048: 6c83 ldr r3, [r0, #72] @ 0x48
800304a: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
800304c: 6d03 ldr r3, [r0, #80] @ 0x50
800304e: 2b00 cmp r3, #0
8003050: d005 beq.n 800305e <HAL_DMA_Abort+0x62>
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
8003052: 681a ldr r2, [r3, #0]
8003054: 402a ands r2, r5
8003056: 601a str r2, [r3, #0]
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
8003058: 6d43 ldr r3, [r0, #84] @ 0x54
800305a: 6d82 ldr r2, [r0, #88] @ 0x58
800305c: 605a str r2, [r3, #4]
hdma->State = HAL_DMA_STATE_READY;
800305e: 2301 movs r3, #1
__HAL_UNLOCK(hdma);
8003060: 2000 movs r0, #0
hdma->State = HAL_DMA_STATE_READY;
8003062: 77e3 strb r3, [r4, #31]
__HAL_UNLOCK(hdma);
8003064: 77c8 strb r0, [r1, #31]
return HAL_OK;
8003066: e7d6 b.n 8003016 <HAL_DMA_Abort+0x1a>
8003068: fffffeff .word 0xfffffeff
800306c: 40020000 .word 0x40020000
08003070 <HAL_DMA_Abort_IT>:
{
8003070: b5f8 push {r3, r4, r5, r6, r7, lr}
__HAL_LOCK(hdma);
8003072: 2301 movs r3, #1
8003074: 1d41 adds r1, r0, #5
8003076: 77cb strb r3, [r1, #31]
if (HAL_DMA_STATE_BUSY != hdma->State)
8003078: 1d84 adds r4, r0, #6
800307a: 7fe2 ldrb r2, [r4, #31]
800307c: 2a02 cmp r2, #2
800307e: d003 beq.n 8003088 <HAL_DMA_Abort_IT+0x18>
hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
8003080: 2204 movs r2, #4
8003082: 63c2 str r2, [r0, #60] @ 0x3c
status = HAL_ERROR;
8003084: 0018 movs r0, r3
}
8003086: bdf8 pop {r3, r4, r5, r6, r7, pc}
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
8003088: 260e movs r6, #14
800308a: 6802 ldr r2, [r0, #0]
800308c: 6815 ldr r5, [r2, #0]
800308e: 43b5 bics r5, r6
8003090: 6015 str r5, [r2, #0]
__HAL_DMA_DISABLE(hdma);
8003092: 6815 ldr r5, [r2, #0]
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
8003094: 6c46 ldr r6, [r0, #68] @ 0x44
__HAL_DMA_DISABLE(hdma);
8003096: 439d bics r5, r3
8003098: 6015 str r5, [r2, #0]
hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
800309a: 6832 ldr r2, [r6, #0]
800309c: 4d11 ldr r5, [pc, #68] @ (80030e4 <HAL_DMA_Abort_IT+0x74>)
800309e: 402a ands r2, r5
80030a0: 6032 str r2, [r6, #0]
__HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1cU)));
80030a2: 6c02 ldr r2, [r0, #64] @ 0x40
80030a4: 4e10 ldr r6, [pc, #64] @ (80030e8 <HAL_DMA_Abort_IT+0x78>)
80030a6: 0015 movs r5, r2
80030a8: 221c movs r2, #28
80030aa: 4015 ands r5, r2
80030ac: 40ab lsls r3, r5
80030ae: 6877 ldr r7, [r6, #4]
80030b0: 433b orrs r3, r7
80030b2: 6073 str r3, [r6, #4]
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
80030b4: 6cc2 ldr r2, [r0, #76] @ 0x4c
80030b6: 6c83 ldr r3, [r0, #72] @ 0x48
80030b8: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
80030ba: 6d03 ldr r3, [r0, #80] @ 0x50
80030bc: 2b00 cmp r3, #0
80030be: d006 beq.n 80030ce <HAL_DMA_Abort_IT+0x5e>
hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
80030c0: 681a ldr r2, [r3, #0]
80030c2: 4d08 ldr r5, [pc, #32] @ (80030e4 <HAL_DMA_Abort_IT+0x74>)
80030c4: 402a ands r2, r5
80030c6: 601a str r2, [r3, #0]
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
80030c8: 6d43 ldr r3, [r0, #84] @ 0x54
80030ca: 6d82 ldr r2, [r0, #88] @ 0x58
80030cc: 605a str r2, [r3, #4]
hdma->State = HAL_DMA_STATE_READY;
80030ce: 2301 movs r3, #1
80030d0: 77e3 strb r3, [r4, #31]
__HAL_UNLOCK(hdma);
80030d2: 2300 movs r3, #0
80030d4: 77cb strb r3, [r1, #31]
if (hdma->XferAbortCallback != NULL)
80030d6: 6b83 ldr r3, [r0, #56] @ 0x38
80030d8: 2b00 cmp r3, #0
80030da: d000 beq.n 80030de <HAL_DMA_Abort_IT+0x6e>
hdma->XferAbortCallback(hdma);
80030dc: 4798 blx r3
HAL_StatusTypeDef status = HAL_OK;
80030de: 2000 movs r0, #0
80030e0: e7d1 b.n 8003086 <HAL_DMA_Abort_IT+0x16>
80030e2: 46c0 nop @ (mov r8, r8)
80030e4: fffffeff .word 0xfffffeff
80030e8: 40020000 .word 0x40020000
080030ec <HAL_DMA_IRQHandler>:
{
80030ec: b5f8 push {r3, r4, r5, r6, r7, lr}
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
80030ee: 241c movs r4, #28
80030f0: 2704 movs r7, #4
80030f2: 6c01 ldr r1, [r0, #64] @ 0x40
uint32_t flag_it = DMA1->ISR;
80030f4: 4a26 ldr r2, [pc, #152] @ (8003190 <HAL_DMA_IRQHandler+0xa4>)
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
80030f6: 4021 ands r1, r4
80030f8: 003c movs r4, r7
80030fa: 408c lsls r4, r1
uint32_t flag_it = DMA1->ISR;
80030fc: 6816 ldr r6, [r2, #0]
uint32_t source_it = hdma->Instance->CCR;
80030fe: 6803 ldr r3, [r0, #0]
8003100: 681d ldr r5, [r3, #0]
if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
8003102: 4226 tst r6, r4
8003104: d00f beq.n 8003126 <HAL_DMA_IRQHandler+0x3a>
8003106: 423d tst r5, r7
8003108: d00d beq.n 8003126 <HAL_DMA_IRQHandler+0x3a>
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
800310a: 6819 ldr r1, [r3, #0]
800310c: 0689 lsls r1, r1, #26
800310e: d402 bmi.n 8003116 <HAL_DMA_IRQHandler+0x2a>
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
8003110: 6819 ldr r1, [r3, #0]
8003112: 43b9 bics r1, r7
8003114: 6019 str r1, [r3, #0]
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)));
8003116: 6853 ldr r3, [r2, #4]
8003118: 431c orrs r4, r3
if (hdma->XferHalfCpltCallback != NULL)
800311a: 6b03 ldr r3, [r0, #48] @ 0x30
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)));
800311c: 6054 str r4, [r2, #4]
if (hdma->XferHalfCpltCallback != NULL)
800311e: 2b00 cmp r3, #0
8003120: d01b beq.n 800315a <HAL_DMA_IRQHandler+0x6e>
hdma->XferErrorCallback(hdma);
8003122: 4798 blx r3
return;
8003124: e019 b.n 800315a <HAL_DMA_IRQHandler+0x6e>
else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC)))
8003126: 2702 movs r7, #2
8003128: 003c movs r4, r7
800312a: 408c lsls r4, r1
800312c: 4226 tst r6, r4
800312e: d015 beq.n 800315c <HAL_DMA_IRQHandler+0x70>
8003130: 423d tst r5, r7
8003132: d013 beq.n 800315c <HAL_DMA_IRQHandler+0x70>
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
8003134: 6819 ldr r1, [r3, #0]
8003136: 0689 lsls r1, r1, #26
8003138: d406 bmi.n 8003148 <HAL_DMA_IRQHandler+0x5c>
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
800313a: 250a movs r5, #10
800313c: 6819 ldr r1, [r3, #0]
800313e: 43a9 bics r1, r5
8003140: 6019 str r1, [r3, #0]
hdma->State = HAL_DMA_STATE_READY;
8003142: 2101 movs r1, #1
8003144: 1d83 adds r3, r0, #6
8003146: 77d9 strb r1, [r3, #31]
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)));
8003148: 6853 ldr r3, [r2, #4]
800314a: 431c orrs r4, r3
800314c: 6054 str r4, [r2, #4]
__HAL_UNLOCK(hdma);
800314e: 2200 movs r2, #0
8003150: 1d43 adds r3, r0, #5
8003152: 77da strb r2, [r3, #31]
if (hdma->XferCpltCallback != NULL)
8003154: 6ac3 ldr r3, [r0, #44] @ 0x2c
if (hdma->XferErrorCallback != NULL)
8003156: 4293 cmp r3, r2
8003158: d1e3 bne.n 8003122 <HAL_DMA_IRQHandler+0x36>
}
800315a: bdf8 pop {r3, r4, r5, r6, r7, pc}
else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
800315c: 2408 movs r4, #8
800315e: 0027 movs r7, r4
8003160: 408f lsls r7, r1
8003162: 423e tst r6, r7
8003164: d0f9 beq.n 800315a <HAL_DMA_IRQHandler+0x6e>
8003166: 4225 tst r5, r4
8003168: d0f7 beq.n 800315a <HAL_DMA_IRQHandler+0x6e>
__HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800316a: 250e movs r5, #14
800316c: 681c ldr r4, [r3, #0]
800316e: 43ac bics r4, r5
8003170: 601c str r4, [r3, #0]
__HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU)));
8003172: 2301 movs r3, #1
8003174: 001d movs r5, r3
8003176: 408d lsls r5, r1
8003178: 0029 movs r1, r5
800317a: 6854 ldr r4, [r2, #4]
800317c: 4321 orrs r1, r4
800317e: 6051 str r1, [r2, #4]
hdma->State = HAL_DMA_STATE_READY;
8003180: 1d82 adds r2, r0, #6
hdma->ErrorCode = HAL_DMA_ERROR_TE;
8003182: 63c3 str r3, [r0, #60] @ 0x3c
hdma->State = HAL_DMA_STATE_READY;
8003184: 77d3 strb r3, [r2, #31]
__HAL_UNLOCK(hdma);
8003186: 2200 movs r2, #0
8003188: 1d43 adds r3, r0, #5
800318a: 77da strb r2, [r3, #31]
if (hdma->XferErrorCallback != NULL)
800318c: 6b43 ldr r3, [r0, #52] @ 0x34
800318e: e7e2 b.n 8003156 <HAL_DMA_IRQHandler+0x6a>
8003190: 40020000 .word 0x40020000
08003194 <HAL_GPIO_Init>:
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
{
uint32_t tmp;
uint32_t iocurrent;
uint32_t position = 0U;
8003194: 2300 movs r3, #0
8003196: 469c mov ip, r3
{
8003198: b5f0 push {r4, r5, r6, r7, lr}
800319a: b085 sub sp, #20
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(pGPIO_Init->Pin));
assert_param(IS_GPIO_MODE(pGPIO_Init->Mode));
/* Configure the port pins */
while (((pGPIO_Init->Pin) >> position) != 0U)
800319c: 680b ldr r3, [r1, #0]
800319e: 4664 mov r4, ip
80031a0: 001a movs r2, r3
80031a2: 40e2 lsrs r2, r4
80031a4: d101 bne.n 80031aa <HAL_GPIO_Init+0x16>
}
}
position++;
}
}
80031a6: b005 add sp, #20
80031a8: bdf0 pop {r4, r5, r6, r7, pc}
iocurrent = (pGPIO_Init->Pin) & (1UL << position);
80031aa: 4662 mov r2, ip
80031ac: 2601 movs r6, #1
80031ae: 4096 lsls r6, r2
80031b0: 001a movs r2, r3
80031b2: 4032 ands r2, r6
80031b4: 9201 str r2, [sp, #4]
if (iocurrent != 0U)
80031b6: 4233 tst r3, r6
80031b8: d100 bne.n 80031bc <HAL_GPIO_Init+0x28>
80031ba: e084 b.n 80032c6 <HAL_GPIO_Init+0x132>
if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD))
80031bc: 684f ldr r7, [r1, #4]
80031be: 2310 movs r3, #16
80031c0: 003d movs r5, r7
80031c2: 439d bics r5, r3
80031c4: 9503 str r5, [sp, #12]
80031c6: 2d02 cmp r5, #2
80031c8: d114 bne.n 80031f4 <HAL_GPIO_Init+0x60>
tmp = GPIOx->AFR[position >> 3U];
80031ca: 4663 mov r3, ip
80031cc: 08da lsrs r2, r3, #3
80031ce: 0092 lsls r2, r2, #2
80031d0: 1882 adds r2, r0, r2
80031d2: 6a13 ldr r3, [r2, #32]
tmp &= ~(0xFUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ;
80031d4: 2407 movs r4, #7
tmp = GPIOx->AFR[position >> 3U];
80031d6: 001d movs r5, r3
tmp &= ~(0xFUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ;
80031d8: 4663 mov r3, ip
80031da: 401c ands r4, r3
80031dc: 230f movs r3, #15
80031de: 00a4 lsls r4, r4, #2
80031e0: 40a3 lsls r3, r4
80031e2: 439d bics r5, r3
80031e4: 9502 str r5, [sp, #8]
tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos));
80031e6: 250f movs r5, #15
80031e8: 690b ldr r3, [r1, #16]
80031ea: 402b ands r3, r5
80031ec: 40a3 lsls r3, r4
80031ee: 9c02 ldr r4, [sp, #8]
80031f0: 4323 orrs r3, r4
GPIOx->AFR[position >> 3U] = tmp;
80031f2: 6213 str r3, [r2, #32]
tmp = GPIOx->MODER;
80031f4: 4663 mov r3, ip
80031f6: 005a lsls r2, r3, #1
tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
80031f8: 2303 movs r3, #3
80031fa: 4093 lsls r3, r2
tmp = GPIOx->MODER;
80031fc: 6804 ldr r4, [r0, #0]
tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
80031fe: 43dd mvns r5, r3
8003200: 439c bics r4, r3
tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos));
8003202: 2303 movs r3, #3
8003204: 403b ands r3, r7
8003206: 4093 lsls r3, r2
tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
8003208: 9502 str r5, [sp, #8]
if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
800320a: 9d03 ldr r5, [sp, #12]
tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos));
800320c: 4323 orrs r3, r4
if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
800320e: 3d01 subs r5, #1
GPIOx->MODER = tmp;
8003210: 6003 str r3, [r0, #0]
if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
8003212: 2d01 cmp r5, #1
8003214: d95a bls.n 80032cc <HAL_GPIO_Init+0x138>
if (pGPIO_Init->Mode != GPIO_MODE_ANALOG)
8003216: 2f03 cmp r7, #3
8003218: d055 beq.n 80032c6 <HAL_GPIO_Init+0x132>
tmp = GPIOx->PUPDR;
800321a: 68c4 ldr r4, [r0, #12]
tmp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos));
800321c: 9b02 ldr r3, [sp, #8]
800321e: 401c ands r4, r3
tmp |= ((pGPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos));
8003220: 688b ldr r3, [r1, #8]
8003222: 4093 lsls r3, r2
8003224: 4323 orrs r3, r4
GPIOx->PUPDR = tmp;
8003226: 60c3 str r3, [r0, #12]
if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
8003228: 2380 movs r3, #128 @ 0x80
800322a: 055b lsls r3, r3, #21
800322c: 421f tst r7, r3
800322e: d04a beq.n 80032c6 <HAL_GPIO_Init+0x132>
tmp = EXTI->EXTICR[position >> 2U];
8003230: 4663 mov r3, ip
8003232: 089a lsrs r2, r3, #2
8003234: 4b2d ldr r3, [pc, #180] @ (80032ec <HAL_GPIO_Init+0x158>)
8003236: 0092 lsls r2, r2, #2
8003238: 18d2 adds r2, r2, r3
tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
800323a: 2403 movs r4, #3
800323c: 4663 mov r3, ip
800323e: 401c ands r4, r3
8003240: 230f movs r3, #15
8003242: 00e4 lsls r4, r4, #3
8003244: 40a3 lsls r3, r4
tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
8003246: 26a0 movs r6, #160 @ 0xa0
tmp = EXTI->EXTICR[position >> 2U];
8003248: 6e15 ldr r5, [r2, #96] @ 0x60
tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
800324a: 05f6 lsls r6, r6, #23
tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
800324c: 439d bics r5, r3
tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
800324e: 2300 movs r3, #0
8003250: 42b0 cmp r0, r6
8003252: d010 beq.n 8003276 <HAL_GPIO_Init+0xe2>
8003254: 4e26 ldr r6, [pc, #152] @ (80032f0 <HAL_GPIO_Init+0x15c>)
8003256: 3301 adds r3, #1
8003258: 42b0 cmp r0, r6
800325a: d00c beq.n 8003276 <HAL_GPIO_Init+0xe2>
800325c: 4e25 ldr r6, [pc, #148] @ (80032f4 <HAL_GPIO_Init+0x160>)
800325e: 3301 adds r3, #1
8003260: 42b0 cmp r0, r6
8003262: d008 beq.n 8003276 <HAL_GPIO_Init+0xe2>
8003264: 4e24 ldr r6, [pc, #144] @ (80032f8 <HAL_GPIO_Init+0x164>)
8003266: 3301 adds r3, #1
8003268: 42b0 cmp r0, r6
800326a: d004 beq.n 8003276 <HAL_GPIO_Init+0xe2>
800326c: 4b23 ldr r3, [pc, #140] @ (80032fc <HAL_GPIO_Init+0x168>)
800326e: 18c3 adds r3, r0, r3
8003270: 1e5e subs r6, r3, #1
8003272: 41b3 sbcs r3, r6
8003274: 3305 adds r3, #5
8003276: 40a3 lsls r3, r4
8003278: 432b orrs r3, r5
EXTI->EXTICR[position >> 2U] = tmp;
800327a: 6613 str r3, [r2, #96] @ 0x60
tmp = EXTI->IMR1;
800327c: 4b20 ldr r3, [pc, #128] @ (8003300 <HAL_GPIO_Init+0x16c>)
tmp &= ~((uint32_t)iocurrent);
800327e: 9a01 ldr r2, [sp, #4]
tmp = EXTI->IMR1;
8003280: 6fdd ldr r5, [r3, #124] @ 0x7c
tmp |= iocurrent;
8003282: 9c01 ldr r4, [sp, #4]
tmp &= ~((uint32_t)iocurrent);
8003284: 43d2 mvns r2, r2
tmp |= iocurrent;
8003286: 432c orrs r4, r5
if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
8003288: 03fe lsls r6, r7, #15
800328a: d401 bmi.n 8003290 <HAL_GPIO_Init+0xfc>
tmp &= ~((uint32_t)iocurrent);
800328c: 002c movs r4, r5
800328e: 4014 ands r4, r2
EXTI->IMR1 = tmp;
8003290: 67dc str r4, [r3, #124] @ 0x7c
tmp = EXTI->EMR1;
8003292: 4c1c ldr r4, [pc, #112] @ (8003304 <HAL_GPIO_Init+0x170>)
tmp |= iocurrent;
8003294: 9d01 ldr r5, [sp, #4]
tmp = EXTI->EMR1;
8003296: 6fe3 ldr r3, [r4, #124] @ 0x7c
tmp |= iocurrent;
8003298: 431d orrs r5, r3
if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
800329a: 03be lsls r6, r7, #14
800329c: d401 bmi.n 80032a2 <HAL_GPIO_Init+0x10e>
tmp &= ~((uint32_t)iocurrent);
800329e: 4013 ands r3, r2
80032a0: 001d movs r5, r3
EXTI->EMR1 = tmp;
80032a2: 4b12 ldr r3, [pc, #72] @ (80032ec <HAL_GPIO_Init+0x158>)
80032a4: 67e5 str r5, [r4, #124] @ 0x7c
tmp = EXTI->RTSR1;
80032a6: 681d ldr r5, [r3, #0]
tmp |= iocurrent;
80032a8: 9c01 ldr r4, [sp, #4]
80032aa: 432c orrs r4, r5
if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
80032ac: 02fe lsls r6, r7, #11
80032ae: d401 bmi.n 80032b4 <HAL_GPIO_Init+0x120>
tmp &= ~((uint32_t)iocurrent);
80032b0: 002c movs r4, r5
80032b2: 4014 ands r4, r2
EXTI->RTSR1 = tmp;
80032b4: 601c str r4, [r3, #0]
tmp = EXTI->FTSR1;
80032b6: 685c ldr r4, [r3, #4]
tmp |= iocurrent;
80032b8: 9d01 ldr r5, [sp, #4]
80032ba: 4325 orrs r5, r4
if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
80032bc: 02bf lsls r7, r7, #10
80032be: d401 bmi.n 80032c4 <HAL_GPIO_Init+0x130>
tmp &= ~((uint32_t)iocurrent);
80032c0: 4014 ands r4, r2
80032c2: 0025 movs r5, r4
EXTI->FTSR1 = tmp;
80032c4: 605d str r5, [r3, #4]
position++;
80032c6: 2301 movs r3, #1
80032c8: 449c add ip, r3
80032ca: e767 b.n 800319c <HAL_GPIO_Init+0x8>
tmp = GPIOx->OSPEEDR;
80032cc: 6884 ldr r4, [r0, #8]
tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
80032ce: 9b02 ldr r3, [sp, #8]
tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
80032d0: 4665 mov r5, ip
tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
80032d2: 401c ands r4, r3
tmp |= (pGPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos));
80032d4: 68cb ldr r3, [r1, #12]
80032d6: 4093 lsls r3, r2
80032d8: 4323 orrs r3, r4
GPIOx->OSPEEDR = tmp;
80032da: 6083 str r3, [r0, #8]
tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
80032dc: 093b lsrs r3, r7, #4
80032de: 40ab lsls r3, r5
tmp = GPIOx->OTYPER;
80032e0: 6844 ldr r4, [r0, #4]
tmp &= ~(GPIO_OTYPER_OT0 << position) ;
80032e2: 43b4 bics r4, r6
tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
80032e4: 4323 orrs r3, r4
GPIOx->OTYPER = tmp;
80032e6: 6043 str r3, [r0, #4]
if (pGPIO_Init->Mode != GPIO_MODE_ANALOG)
80032e8: e797 b.n 800321a <HAL_GPIO_Init+0x86>
80032ea: 46c0 nop @ (mov r8, r8)
80032ec: 40021800 .word 0x40021800
80032f0: 50000400 .word 0x50000400
80032f4: 50000800 .word 0x50000800
80032f8: 50000c00 .word 0x50000c00
80032fc: afffec00 .word 0xafffec00
8003300: 40021804 .word 0x40021804
8003304: 40021808 .word 0x40021808
08003308 <HAL_GPIO_ReadPin>:
GPIO_PinState bitstatus;
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->IDR & GPIO_Pin) != 0U)
8003308: 6900 ldr r0, [r0, #16]
800330a: 4008 ands r0, r1
800330c: 1e43 subs r3, r0, #1
800330e: 4198 sbcs r0, r3
}
else
{
bitstatus = GPIO_PIN_RESET;
}
return bitstatus;
8003310: b2c0 uxtb r0, r0
}
8003312: 4770 bx lr
08003314 <HAL_GPIO_WritePin>:
{
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8003314: 2a00 cmp r2, #0
8003316: d001 beq.n 800331c <HAL_GPIO_WritePin+0x8>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8003318: 6181 str r1, [r0, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
800331a: 4770 bx lr
GPIOx->BRR = (uint32_t)GPIO_Pin;
800331c: 6281 str r1, [r0, #40] @ 0x28
}
800331e: e7fc b.n 800331a <HAL_GPIO_WritePin+0x6>
08003320 <HAL_GPIO_EXTI_Rising_Callback>:
UNUSED(GPIO_Pin);
/* NOTE: This function should not be modified, when the callback is needed,
the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file
*/
}
8003320: 4770 bx lr
...
08003324 <HAL_GPIO_EXTI_IRQHandler>:
{
8003324: b570 push {r4, r5, r6, lr}
if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U)
8003326: 4d08 ldr r5, [pc, #32] @ (8003348 <HAL_GPIO_EXTI_IRQHandler+0x24>)
{
8003328: 0004 movs r4, r0
if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U)
800332a: 68eb ldr r3, [r5, #12]
800332c: 4218 tst r0, r3
800332e: d002 beq.n 8003336 <HAL_GPIO_EXTI_IRQHandler+0x12>
__HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
8003330: 60e8 str r0, [r5, #12]
HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
8003332: f7ff fff5 bl 8003320 <HAL_GPIO_EXTI_Rising_Callback>
if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U)
8003336: 692b ldr r3, [r5, #16]
8003338: 4223 tst r3, r4
800333a: d003 beq.n 8003344 <HAL_GPIO_EXTI_IRQHandler+0x20>
HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
800333c: 0020 movs r0, r4
__HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
800333e: 612c str r4, [r5, #16]
HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
8003340: f7fd fb2e bl 80009a0 <HAL_GPIO_EXTI_Falling_Callback>
}
8003344: bd70 pop {r4, r5, r6, pc}
8003346: 46c0 nop @ (mov r8, r8)
8003348: 40021800 .word 0x40021800
0800334c <HAL_RCC_OscConfig>:
must adjust the number of CPU wait states in their application (SystemClock_Config() API)
before calling the HAL_RCC_OscConfig() API to update the HSI48 clock division factor.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct)
{
800334c: b5f8 push {r3, r4, r5, r6, r7, lr}
800334e: 1e05 subs r5, r0, #0
uint32_t tickstart;
uint32_t temp_sysclksrc;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
8003350: d101 bne.n 8003356 <HAL_RCC_OscConfig+0xa>
{
return HAL_ERROR;
8003352: 2001 movs r0, #1
}
}
}
#endif /* RCC_CR_HSIUSB48ON */
return HAL_OK;
}
8003354: bdf8 pop {r3, r4, r5, r6, r7, pc}
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
8003356: 6803 ldr r3, [r0, #0]
8003358: 07db lsls r3, r3, #31
800335a: d40d bmi.n 8003378 <HAL_RCC_OscConfig+0x2c>
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
800335c: 682b ldr r3, [r5, #0]
800335e: 079b lsls r3, r3, #30
8003360: d44f bmi.n 8003402 <HAL_RCC_OscConfig+0xb6>
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
8003362: 682b ldr r3, [r5, #0]
8003364: 071b lsls r3, r3, #28
8003366: d500 bpl.n 800336a <HAL_RCC_OscConfig+0x1e>
8003368: e0a4 b.n 80034b4 <HAL_RCC_OscConfig+0x168>
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
800336a: 2204 movs r2, #4
800336c: 682b ldr r3, [r5, #0]
800336e: 4213 tst r3, r2
8003370: d000 beq.n 8003374 <HAL_RCC_OscConfig+0x28>
8003372: e0cf b.n 8003514 <HAL_RCC_OscConfig+0x1c8>
return HAL_OK;
8003374: 2000 movs r0, #0
8003376: e7ed b.n 8003354 <HAL_RCC_OscConfig+0x8>
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8003378: 2138 movs r1, #56 @ 0x38
800337a: 4c85 ldr r4, [pc, #532] @ (8003590 <HAL_RCC_OscConfig+0x244>)
if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)
800337c: 6843 ldr r3, [r0, #4]
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
800337e: 68a2 ldr r2, [r4, #8]
8003380: 400a ands r2, r1
if (temp_sysclksrc == RCC_CFGR_SWS_HSE)
8003382: 2a08 cmp r2, #8
8003384: d102 bne.n 800338c <HAL_RCC_OscConfig+0x40>
if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)
8003386: 2b00 cmp r3, #0
8003388: d1e8 bne.n 800335c <HAL_RCC_OscConfig+0x10>
800338a: e7e2 b.n 8003352 <HAL_RCC_OscConfig+0x6>
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800338c: 2280 movs r2, #128 @ 0x80
800338e: 0252 lsls r2, r2, #9
8003390: 4293 cmp r3, r2
8003392: d111 bne.n 80033b8 <HAL_RCC_OscConfig+0x6c>
8003394: 6822 ldr r2, [r4, #0]
8003396: 4313 orrs r3, r2
8003398: 6023 str r3, [r4, #0]
tickstart = HAL_GetTick();
800339a: f7ff faa1 bl 80028e0 <HAL_GetTick>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
800339e: 2780 movs r7, #128 @ 0x80
tickstart = HAL_GetTick();
80033a0: 0006 movs r6, r0
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80033a2: 02bf lsls r7, r7, #10
80033a4: 6823 ldr r3, [r4, #0]
80033a6: 423b tst r3, r7
80033a8: d1d8 bne.n 800335c <HAL_RCC_OscConfig+0x10>
if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
80033aa: f7ff fa99 bl 80028e0 <HAL_GetTick>
80033ae: 1b80 subs r0, r0, r6
80033b0: 2864 cmp r0, #100 @ 0x64
80033b2: d9f7 bls.n 80033a4 <HAL_RCC_OscConfig+0x58>
return HAL_TIMEOUT;
80033b4: 2003 movs r0, #3
80033b6: e7cd b.n 8003354 <HAL_RCC_OscConfig+0x8>
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80033b8: 21a0 movs r1, #160 @ 0xa0
80033ba: 02c9 lsls r1, r1, #11
80033bc: 428b cmp r3, r1
80033be: d108 bne.n 80033d2 <HAL_RCC_OscConfig+0x86>
80033c0: 2380 movs r3, #128 @ 0x80
80033c2: 6821 ldr r1, [r4, #0]
80033c4: 02db lsls r3, r3, #11
80033c6: 430b orrs r3, r1
80033c8: 6023 str r3, [r4, #0]
80033ca: 6823 ldr r3, [r4, #0]
80033cc: 431a orrs r2, r3
80033ce: 6022 str r2, [r4, #0]
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80033d0: e7e3 b.n 800339a <HAL_RCC_OscConfig+0x4e>
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
80033d2: 6822 ldr r2, [r4, #0]
80033d4: 496f ldr r1, [pc, #444] @ (8003594 <HAL_RCC_OscConfig+0x248>)
80033d6: 400a ands r2, r1
80033d8: 6022 str r2, [r4, #0]
80033da: 6822 ldr r2, [r4, #0]
80033dc: 496e ldr r1, [pc, #440] @ (8003598 <HAL_RCC_OscConfig+0x24c>)
80033de: 400a ands r2, r1
80033e0: 6022 str r2, [r4, #0]
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
80033e2: 2b00 cmp r3, #0
80033e4: d1d9 bne.n 800339a <HAL_RCC_OscConfig+0x4e>
tickstart = HAL_GetTick();
80033e6: f7ff fa7b bl 80028e0 <HAL_GetTick>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
80033ea: 2780 movs r7, #128 @ 0x80
tickstart = HAL_GetTick();
80033ec: 0006 movs r6, r0
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
80033ee: 02bf lsls r7, r7, #10
80033f0: 6823 ldr r3, [r4, #0]
80033f2: 423b tst r3, r7
80033f4: d0b2 beq.n 800335c <HAL_RCC_OscConfig+0x10>
if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
80033f6: f7ff fa73 bl 80028e0 <HAL_GetTick>
80033fa: 1b80 subs r0, r0, r6
80033fc: 2864 cmp r0, #100 @ 0x64
80033fe: d9f7 bls.n 80033f0 <HAL_RCC_OscConfig+0xa4>
8003400: e7d8 b.n 80033b4 <HAL_RCC_OscConfig+0x68>
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8003402: 2238 movs r2, #56 @ 0x38
8003404: 4c62 ldr r4, [pc, #392] @ (8003590 <HAL_RCC_OscConfig+0x244>)
if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
8003406: 68eb ldr r3, [r5, #12]
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
8003408: 68a1 ldr r1, [r4, #8]
if (temp_sysclksrc == RCC_CFGR_SWS_HSI)
800340a: 4211 tst r1, r2
800340c: d11c bne.n 8003448 <HAL_RCC_OscConfig+0xfc>
if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
800340e: 2b00 cmp r3, #0
8003410: d09f beq.n 8003352 <HAL_RCC_OscConfig+0x6>
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003412: 6862 ldr r2, [r4, #4]
8003414: 696b ldr r3, [r5, #20]
8003416: 4961 ldr r1, [pc, #388] @ (800359c <HAL_RCC_OscConfig+0x250>)
8003418: 021b lsls r3, r3, #8
800341a: 400a ands r2, r1
800341c: 4313 orrs r3, r2
800341e: 6063 str r3, [r4, #4]
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
8003420: 6823 ldr r3, [r4, #0]
8003422: 4a5f ldr r2, [pc, #380] @ (80035a0 <HAL_RCC_OscConfig+0x254>)
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
8003424: 495f ldr r1, [pc, #380] @ (80035a4 <HAL_RCC_OscConfig+0x258>)
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
8003426: 4013 ands r3, r2
8003428: 692a ldr r2, [r5, #16]
800342a: 4313 orrs r3, r2
800342c: 6023 str r3, [r4, #0]
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
800342e: 6823 ldr r3, [r4, #0]
8003430: 4a5d ldr r2, [pc, #372] @ (80035a8 <HAL_RCC_OscConfig+0x25c>)
8003432: 049b lsls r3, r3, #18
8003434: 0f5b lsrs r3, r3, #29
8003436: 40da lsrs r2, r3
if (HAL_InitTick(uwTickPrio) != HAL_OK)
8003438: 4b5c ldr r3, [pc, #368] @ (80035ac <HAL_RCC_OscConfig+0x260>)
SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
800343a: 600a str r2, [r1, #0]
if (HAL_InitTick(uwTickPrio) != HAL_OK)
800343c: 6818 ldr r0, [r3, #0]
800343e: f7ff fa0f bl 8002860 <HAL_InitTick>
8003442: 2800 cmp r0, #0
8003444: d08d beq.n 8003362 <HAL_RCC_OscConfig+0x16>
8003446: e784 b.n 8003352 <HAL_RCC_OscConfig+0x6>
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
8003448: 2b00 cmp r3, #0
800344a: d020 beq.n 800348e <HAL_RCC_OscConfig+0x142>
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
800344c: 6823 ldr r3, [r4, #0]
800344e: 4a54 ldr r2, [pc, #336] @ (80035a0 <HAL_RCC_OscConfig+0x254>)
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003450: 2780 movs r7, #128 @ 0x80
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
8003452: 4013 ands r3, r2
8003454: 692a ldr r2, [r5, #16]
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8003456: 00ff lsls r7, r7, #3
__HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
8003458: 4313 orrs r3, r2
800345a: 6023 str r3, [r4, #0]
__HAL_RCC_HSI_ENABLE();
800345c: 2380 movs r3, #128 @ 0x80
800345e: 6822 ldr r2, [r4, #0]
8003460: 005b lsls r3, r3, #1
8003462: 4313 orrs r3, r2
8003464: 6023 str r3, [r4, #0]
tickstart = HAL_GetTick();
8003466: f7ff fa3b bl 80028e0 <HAL_GetTick>
800346a: 0006 movs r6, r0
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800346c: 6823 ldr r3, [r4, #0]
800346e: 423b tst r3, r7
8003470: d007 beq.n 8003482 <HAL_RCC_OscConfig+0x136>
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8003472: 6862 ldr r2, [r4, #4]
8003474: 696b ldr r3, [r5, #20]
8003476: 4949 ldr r1, [pc, #292] @ (800359c <HAL_RCC_OscConfig+0x250>)
8003478: 021b lsls r3, r3, #8
800347a: 400a ands r2, r1
800347c: 4313 orrs r3, r2
800347e: 6063 str r3, [r4, #4]
8003480: e76f b.n 8003362 <HAL_RCC_OscConfig+0x16>
if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
8003482: f7ff fa2d bl 80028e0 <HAL_GetTick>
8003486: 1b80 subs r0, r0, r6
8003488: 2802 cmp r0, #2
800348a: d9ef bls.n 800346c <HAL_RCC_OscConfig+0x120>
800348c: e792 b.n 80033b4 <HAL_RCC_OscConfig+0x68>
__HAL_RCC_HSI_DISABLE();
800348e: 6823 ldr r3, [r4, #0]
8003490: 4a47 ldr r2, [pc, #284] @ (80035b0 <HAL_RCC_OscConfig+0x264>)
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
8003492: 2780 movs r7, #128 @ 0x80
__HAL_RCC_HSI_DISABLE();
8003494: 4013 ands r3, r2
8003496: 6023 str r3, [r4, #0]
tickstart = HAL_GetTick();
8003498: f7ff fa22 bl 80028e0 <HAL_GetTick>
800349c: 0006 movs r6, r0
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
800349e: 00ff lsls r7, r7, #3
80034a0: 6823 ldr r3, [r4, #0]
80034a2: 423b tst r3, r7
80034a4: d100 bne.n 80034a8 <HAL_RCC_OscConfig+0x15c>
80034a6: e75c b.n 8003362 <HAL_RCC_OscConfig+0x16>
if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
80034a8: f7ff fa1a bl 80028e0 <HAL_GetTick>
80034ac: 1b80 subs r0, r0, r6
80034ae: 2802 cmp r0, #2
80034b0: d9f6 bls.n 80034a0 <HAL_RCC_OscConfig+0x154>
80034b2: e77f b.n 80033b4 <HAL_RCC_OscConfig+0x68>
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
80034b4: 2138 movs r1, #56 @ 0x38
80034b6: 4c36 ldr r4, [pc, #216] @ (8003590 <HAL_RCC_OscConfig+0x244>)
if (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)
80034b8: 69aa ldr r2, [r5, #24]
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
80034ba: 68a3 ldr r3, [r4, #8]
80034bc: 400b ands r3, r1
80034be: 2b18 cmp r3, #24
80034c0: d103 bne.n 80034ca <HAL_RCC_OscConfig+0x17e>
if (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)
80034c2: 2a00 cmp r2, #0
80034c4: d000 beq.n 80034c8 <HAL_RCC_OscConfig+0x17c>
80034c6: e750 b.n 800336a <HAL_RCC_OscConfig+0x1e>
80034c8: e743 b.n 8003352 <HAL_RCC_OscConfig+0x6>
if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80034ca: 2301 movs r3, #1
80034cc: 2a00 cmp r2, #0
80034ce: d010 beq.n 80034f2 <HAL_RCC_OscConfig+0x1a6>
__HAL_RCC_LSI_ENABLE();
80034d0: 6e22 ldr r2, [r4, #96] @ 0x60
while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
80034d2: 2702 movs r7, #2
__HAL_RCC_LSI_ENABLE();
80034d4: 4313 orrs r3, r2
80034d6: 6623 str r3, [r4, #96] @ 0x60
tickstart = HAL_GetTick();
80034d8: f7ff fa02 bl 80028e0 <HAL_GetTick>
80034dc: 0006 movs r6, r0
while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
80034de: 6e23 ldr r3, [r4, #96] @ 0x60
80034e0: 423b tst r3, r7
80034e2: d000 beq.n 80034e6 <HAL_RCC_OscConfig+0x19a>
80034e4: e741 b.n 800336a <HAL_RCC_OscConfig+0x1e>
if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE)
80034e6: f7ff f9fb bl 80028e0 <HAL_GetTick>
80034ea: 1b80 subs r0, r0, r6
80034ec: 2802 cmp r0, #2
80034ee: d9f6 bls.n 80034de <HAL_RCC_OscConfig+0x192>
80034f0: e760 b.n 80033b4 <HAL_RCC_OscConfig+0x68>
__HAL_RCC_LSI_DISABLE();
80034f2: 6e22 ldr r2, [r4, #96] @ 0x60
while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U)
80034f4: 2702 movs r7, #2
__HAL_RCC_LSI_DISABLE();
80034f6: 439a bics r2, r3
80034f8: 6622 str r2, [r4, #96] @ 0x60
tickstart = HAL_GetTick();
80034fa: f7ff f9f1 bl 80028e0 <HAL_GetTick>
80034fe: 0006 movs r6, r0
while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U)
8003500: 6e23 ldr r3, [r4, #96] @ 0x60
8003502: 423b tst r3, r7
8003504: d100 bne.n 8003508 <HAL_RCC_OscConfig+0x1bc>
8003506: e730 b.n 800336a <HAL_RCC_OscConfig+0x1e>
if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE)
8003508: f7ff f9ea bl 80028e0 <HAL_GetTick>
800350c: 1b80 subs r0, r0, r6
800350e: 2802 cmp r0, #2
8003510: d9f6 bls.n 8003500 <HAL_RCC_OscConfig+0x1b4>
8003512: e74f b.n 80033b4 <HAL_RCC_OscConfig+0x68>
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
8003514: 2138 movs r1, #56 @ 0x38
8003516: 4c1e ldr r4, [pc, #120] @ (8003590 <HAL_RCC_OscConfig+0x244>)
if (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)
8003518: 68a8 ldr r0, [r5, #8]
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
800351a: 68a3 ldr r3, [r4, #8]
800351c: 400b ands r3, r1
800351e: 2b20 cmp r3, #32
8003520: d103 bne.n 800352a <HAL_RCC_OscConfig+0x1de>
if (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)
8003522: 4243 negs r3, r0
8003524: 4158 adcs r0, r3
8003526: b2c0 uxtb r0, r0
8003528: e714 b.n 8003354 <HAL_RCC_OscConfig+0x8>
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
800352a: 6de3 ldr r3, [r4, #92] @ 0x5c
800352c: 2801 cmp r0, #1
800352e: d110 bne.n 8003552 <HAL_RCC_OscConfig+0x206>
8003530: 4303 orrs r3, r0
8003532: 65e3 str r3, [r4, #92] @ 0x5c
tickstart = HAL_GetTick();
8003534: f7ff f9d4 bl 80028e0 <HAL_GetTick>
while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
8003538: 2602 movs r6, #2
tickstart = HAL_GetTick();
800353a: 0005 movs r5, r0
while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
800353c: 6de3 ldr r3, [r4, #92] @ 0x5c
800353e: 4233 tst r3, r6
8003540: d000 beq.n 8003544 <HAL_RCC_OscConfig+0x1f8>
8003542: e717 b.n 8003374 <HAL_RCC_OscConfig+0x28>
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003544: f7ff f9cc bl 80028e0 <HAL_GetTick>
8003548: 4b1a ldr r3, [pc, #104] @ (80035b4 <HAL_RCC_OscConfig+0x268>)
800354a: 1b40 subs r0, r0, r5
800354c: 4298 cmp r0, r3
800354e: d9f5 bls.n 800353c <HAL_RCC_OscConfig+0x1f0>
8003550: e730 b.n 80033b4 <HAL_RCC_OscConfig+0x68>
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
8003552: 2805 cmp r0, #5
8003554: d105 bne.n 8003562 <HAL_RCC_OscConfig+0x216>
8003556: 4313 orrs r3, r2
8003558: 65e3 str r3, [r4, #92] @ 0x5c
800355a: 2301 movs r3, #1
800355c: 6de2 ldr r2, [r4, #92] @ 0x5c
800355e: 4313 orrs r3, r2
8003560: e7e7 b.n 8003532 <HAL_RCC_OscConfig+0x1e6>
8003562: 2101 movs r1, #1
8003564: 438b bics r3, r1
8003566: 65e3 str r3, [r4, #92] @ 0x5c
8003568: 6de3 ldr r3, [r4, #92] @ 0x5c
800356a: 4393 bics r3, r2
800356c: 65e3 str r3, [r4, #92] @ 0x5c
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
800356e: 2800 cmp r0, #0
8003570: d1e0 bne.n 8003534 <HAL_RCC_OscConfig+0x1e8>
tickstart = HAL_GetTick();
8003572: f7ff f9b5 bl 80028e0 <HAL_GetTick>
while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U)
8003576: 2602 movs r6, #2
tickstart = HAL_GetTick();
8003578: 0005 movs r5, r0
while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U)
800357a: 6de3 ldr r3, [r4, #92] @ 0x5c
800357c: 4233 tst r3, r6
800357e: d100 bne.n 8003582 <HAL_RCC_OscConfig+0x236>
8003580: e6f8 b.n 8003374 <HAL_RCC_OscConfig+0x28>
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8003582: f7ff f9ad bl 80028e0 <HAL_GetTick>
8003586: 4b0b ldr r3, [pc, #44] @ (80035b4 <HAL_RCC_OscConfig+0x268>)
8003588: 1b40 subs r0, r0, r5
800358a: 4298 cmp r0, r3
800358c: d9f5 bls.n 800357a <HAL_RCC_OscConfig+0x22e>
800358e: e711 b.n 80033b4 <HAL_RCC_OscConfig+0x68>
8003590: 40021000 .word 0x40021000
8003594: fffeffff .word 0xfffeffff
8003598: fffbffff .word 0xfffbffff
800359c: ffff80ff .word 0xffff80ff
80035a0: ffffc7ff .word 0xffffc7ff
80035a4: 20000024 .word 0x20000024
80035a8: 02dc6c00 .word 0x02dc6c00
80035ac: 2000002c .word 0x2000002c
80035b0: fffffeff .word 0xfffffeff
80035b4: 00001388 .word 0x00001388
080035b8 <HAL_RCC_GetSysClockFreq>:
uint32_t HAL_RCC_GetSysClockFreq(void)
{
uint32_t hsidiv;
uint32_t sysclockfreq;
#if defined(RCC_CR_SYSDIV)
uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
80035b8: 2007 movs r0, #7
#endif /* RCC_CR_SYSDIV */
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
80035ba: 2238 movs r2, #56 @ 0x38
uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
80035bc: 4b12 ldr r3, [pc, #72] @ (8003608 <HAL_RCC_GetSysClockFreq+0x50>)
{
80035be: b510 push {r4, lr}
uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
80035c0: 6819 ldr r1, [r3, #0]
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
80035c2: 689c ldr r4, [r3, #8]
uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
80035c4: 0889 lsrs r1, r1, #2
80035c6: 4001 ands r1, r0
80035c8: 3101 adds r1, #1
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
80035ca: 4214 tst r4, r2
80035cc: d107 bne.n 80035de <HAL_RCC_GetSysClockFreq+0x26>
{
/* HSISYS can be derived for HSI48 */
hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
80035ce: 681b ldr r3, [r3, #0]
80035d0: 0adb lsrs r3, r3, #11
80035d2: 4003 ands r3, r0
/* HSI used as system clock source */
sysclockfreq = (HSI_VALUE / hsidiv);
80035d4: 480d ldr r0, [pc, #52] @ (800360c <HAL_RCC_GetSysClockFreq+0x54>)
80035d6: 40d8 lsrs r0, r3
else
{
sysclockfreq = 0U;
}
#if defined(RCC_CR_SYSDIV)
sysclockfreq = sysclockfreq / sysclockdiv;
80035d8: f7fc fdaa bl 8000130 <__udivsi3>
#endif /* RCC_CR_SYSDIV */
return sysclockfreq;
}
80035dc: bd10 pop {r4, pc}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
80035de: 6898 ldr r0, [r3, #8]
80035e0: 4010 ands r0, r2
80035e2: 2808 cmp r0, #8
80035e4: d00b beq.n 80035fe <HAL_RCC_GetSysClockFreq+0x46>
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
80035e6: 6898 ldr r0, [r3, #8]
80035e8: 4010 ands r0, r2
80035ea: 2820 cmp r0, #32
80035ec: d009 beq.n 8003602 <HAL_RCC_GetSysClockFreq+0x4a>
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
80035ee: 689b ldr r3, [r3, #8]
sysclockfreq = 0U;
80035f0: 2000 movs r0, #0
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
80035f2: 4013 ands r3, r2
80035f4: 2b18 cmp r3, #24
80035f6: d1ef bne.n 80035d8 <HAL_RCC_GetSysClockFreq+0x20>
sysclockfreq = LSI_VALUE;
80035f8: 20fa movs r0, #250 @ 0xfa
80035fa: 01c0 lsls r0, r0, #7
80035fc: e7ec b.n 80035d8 <HAL_RCC_GetSysClockFreq+0x20>
sysclockfreq = HSE_VALUE;
80035fe: 4804 ldr r0, [pc, #16] @ (8003610 <HAL_RCC_GetSysClockFreq+0x58>)
8003600: e7ea b.n 80035d8 <HAL_RCC_GetSysClockFreq+0x20>
sysclockfreq = LSE_VALUE;
8003602: 2080 movs r0, #128 @ 0x80
8003604: 0200 lsls r0, r0, #8
8003606: e7e7 b.n 80035d8 <HAL_RCC_GetSysClockFreq+0x20>
8003608: 40021000 .word 0x40021000
800360c: 02dc6c00 .word 0x02dc6c00
8003610: 007a1200 .word 0x007a1200
08003614 <HAL_RCC_ClockConfig>:
{
8003614: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8003616: 0004 movs r4, r0
8003618: 000d movs r5, r1
if (RCC_ClkInitStruct == NULL)
800361a: 2800 cmp r0, #0
800361c: d101 bne.n 8003622 <HAL_RCC_ClockConfig+0xe>
return HAL_ERROR;
800361e: 2001 movs r0, #1
}
8003620: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
if (FLatency > __HAL_FLASH_GET_LATENCY())
8003622: 2707 movs r7, #7
8003624: 4e4b ldr r6, [pc, #300] @ (8003754 <HAL_RCC_ClockConfig+0x140>)
8003626: 6833 ldr r3, [r6, #0]
8003628: 403b ands r3, r7
800362a: 428b cmp r3, r1
800362c: d32a bcc.n 8003684 <HAL_RCC_ClockConfig+0x70>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
800362e: 6822 ldr r2, [r4, #0]
8003630: 0793 lsls r3, r2, #30
8003632: d43b bmi.n 80036ac <HAL_RCC_ClockConfig+0x98>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8003634: 07d2 lsls r2, r2, #31
8003636: d44a bmi.n 80036ce <HAL_RCC_ClockConfig+0xba>
if (FLatency < __HAL_FLASH_GET_LATENCY())
8003638: 2707 movs r7, #7
800363a: 6833 ldr r3, [r6, #0]
800363c: 403b ands r3, r7
800363e: 42ab cmp r3, r5
8003640: d90a bls.n 8003658 <HAL_RCC_ClockConfig+0x44>
__HAL_FLASH_SET_LATENCY(FLatency);
8003642: 6833 ldr r3, [r6, #0]
8003644: 43bb bics r3, r7
8003646: 432b orrs r3, r5
8003648: 6033 str r3, [r6, #0]
tickstart = HAL_GetTick();
800364a: f7ff f949 bl 80028e0 <HAL_GetTick>
800364e: 9001 str r0, [sp, #4]
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8003650: 6833 ldr r3, [r6, #0]
8003652: 403b ands r3, r7
8003654: 42ab cmp r3, r5
8003656: d16d bne.n 8003734 <HAL_RCC_ClockConfig+0x120>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8003658: 6823 ldr r3, [r4, #0]
800365a: 4d3f ldr r5, [pc, #252] @ (8003758 <HAL_RCC_ClockConfig+0x144>)
800365c: 075b lsls r3, r3, #29
800365e: d471 bmi.n 8003744 <HAL_RCC_ClockConfig+0x130>
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
8003660: f7ff ffaa bl 80035b8 <HAL_RCC_GetSysClockFreq>
8003664: 68ab ldr r3, [r5, #8]
8003666: 493d ldr r1, [pc, #244] @ (800375c <HAL_RCC_ClockConfig+0x148>)
>> RCC_CFGR_HPRE_Pos]) & 0x1FU));
8003668: 051b lsls r3, r3, #20
800366a: 0f1b lsrs r3, r3, #28
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
800366c: 009b lsls r3, r3, #2
>> RCC_CFGR_HPRE_Pos]) & 0x1FU));
800366e: 585b ldr r3, [r3, r1]
8003670: 211f movs r1, #31
8003672: 400b ands r3, r1
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
8003674: 40d8 lsrs r0, r3
8003676: 4a3a ldr r2, [pc, #232] @ (8003760 <HAL_RCC_ClockConfig+0x14c>)
return HAL_InitTick(uwTickPrio);
8003678: 4b3a ldr r3, [pc, #232] @ (8003764 <HAL_RCC_ClockConfig+0x150>)
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
800367a: 6010 str r0, [r2, #0]
return HAL_InitTick(uwTickPrio);
800367c: 6818 ldr r0, [r3, #0]
800367e: f7ff f8ef bl 8002860 <HAL_InitTick>
8003682: e7cd b.n 8003620 <HAL_RCC_ClockConfig+0xc>
__HAL_FLASH_SET_LATENCY(FLatency);
8003684: 6833 ldr r3, [r6, #0]
8003686: 43bb bics r3, r7
8003688: 430b orrs r3, r1
800368a: 6033 str r3, [r6, #0]
tickstart = HAL_GetTick();
800368c: f7ff f928 bl 80028e0 <HAL_GetTick>
8003690: 9001 str r0, [sp, #4]
while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
8003692: 6833 ldr r3, [r6, #0]
8003694: 403b ands r3, r7
8003696: 42ab cmp r3, r5
8003698: d0c9 beq.n 800362e <HAL_RCC_ClockConfig+0x1a>
if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
800369a: f7ff f921 bl 80028e0 <HAL_GetTick>
800369e: 9b01 ldr r3, [sp, #4]
80036a0: 1ac0 subs r0, r0, r3
80036a2: 4b31 ldr r3, [pc, #196] @ (8003768 <HAL_RCC_ClockConfig+0x154>)
80036a4: 4298 cmp r0, r3
80036a6: d9f4 bls.n 8003692 <HAL_RCC_ClockConfig+0x7e>
return HAL_TIMEOUT;
80036a8: 2003 movs r0, #3
80036aa: e7b9 b.n 8003620 <HAL_RCC_ClockConfig+0xc>
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
80036ac: 492a ldr r1, [pc, #168] @ (8003758 <HAL_RCC_ClockConfig+0x144>)
80036ae: 0753 lsls r3, r2, #29
80036b0: d506 bpl.n 80036c0 <HAL_RCC_ClockConfig+0xac>
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
80036b2: 6888 ldr r0, [r1, #8]
80036b4: 4b2d ldr r3, [pc, #180] @ (800376c <HAL_RCC_ClockConfig+0x158>)
80036b6: 4018 ands r0, r3
80036b8: 23b0 movs r3, #176 @ 0xb0
80036ba: 011b lsls r3, r3, #4
80036bc: 4303 orrs r3, r0
80036be: 608b str r3, [r1, #8]
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
80036c0: 688b ldr r3, [r1, #8]
80036c2: 482b ldr r0, [pc, #172] @ (8003770 <HAL_RCC_ClockConfig+0x15c>)
80036c4: 4003 ands r3, r0
80036c6: 68e0 ldr r0, [r4, #12]
80036c8: 4303 orrs r3, r0
80036ca: 608b str r3, [r1, #8]
80036cc: e7b2 b.n 8003634 <HAL_RCC_ClockConfig+0x20>
MODIFY_REG(RCC->CR, RCC_CR_SYSDIV, RCC_ClkInitStruct->SYSCLKDivider);
80036ce: 221c movs r2, #28
80036d0: 4f21 ldr r7, [pc, #132] @ (8003758 <HAL_RCC_ClockConfig+0x144>)
80036d2: 683b ldr r3, [r7, #0]
80036d4: 4393 bics r3, r2
80036d6: 68a2 ldr r2, [r4, #8]
80036d8: 4313 orrs r3, r2
80036da: 603b str r3, [r7, #0]
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
80036dc: 6862 ldr r2, [r4, #4]
80036de: 2a01 cmp r2, #1
80036e0: d119 bne.n 8003716 <HAL_RCC_ClockConfig+0x102>
if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80036e2: 683b ldr r3, [r7, #0]
80036e4: 039b lsls r3, r3, #14
80036e6: d59a bpl.n 800361e <HAL_RCC_ClockConfig+0xa>
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
80036e8: 2107 movs r1, #7
80036ea: 68bb ldr r3, [r7, #8]
80036ec: 438b bics r3, r1
80036ee: 4313 orrs r3, r2
80036f0: 60bb str r3, [r7, #8]
tickstart = HAL_GetTick();
80036f2: f7ff f8f5 bl 80028e0 <HAL_GetTick>
80036f6: 9001 str r0, [sp, #4]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
80036f8: 2338 movs r3, #56 @ 0x38
80036fa: 68ba ldr r2, [r7, #8]
80036fc: 401a ands r2, r3
80036fe: 6863 ldr r3, [r4, #4]
8003700: 00db lsls r3, r3, #3
8003702: 429a cmp r2, r3
8003704: d098 beq.n 8003638 <HAL_RCC_ClockConfig+0x24>
if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
8003706: f7ff f8eb bl 80028e0 <HAL_GetTick>
800370a: 9b01 ldr r3, [sp, #4]
800370c: 1ac0 subs r0, r0, r3
800370e: 4b16 ldr r3, [pc, #88] @ (8003768 <HAL_RCC_ClockConfig+0x154>)
8003710: 4298 cmp r0, r3
8003712: d9f1 bls.n 80036f8 <HAL_RCC_ClockConfig+0xe4>
8003714: e7c8 b.n 80036a8 <HAL_RCC_ClockConfig+0x94>
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
8003716: 2a00 cmp r2, #0
8003718: d103 bne.n 8003722 <HAL_RCC_ClockConfig+0x10e>
if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800371a: 683b ldr r3, [r7, #0]
800371c: 055b lsls r3, r3, #21
800371e: d4e3 bmi.n 80036e8 <HAL_RCC_ClockConfig+0xd4>
8003720: e77d b.n 800361e <HAL_RCC_ClockConfig+0xa>
else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
8003722: 2302 movs r3, #2
8003724: 2a03 cmp r2, #3
8003726: d103 bne.n 8003730 <HAL_RCC_ClockConfig+0x11c>
if (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
8003728: 6e39 ldr r1, [r7, #96] @ 0x60
if (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
800372a: 4219 tst r1, r3
800372c: d1dc bne.n 80036e8 <HAL_RCC_ClockConfig+0xd4>
800372e: e776 b.n 800361e <HAL_RCC_ClockConfig+0xa>
8003730: 6df9 ldr r1, [r7, #92] @ 0x5c
8003732: e7fa b.n 800372a <HAL_RCC_ClockConfig+0x116>
if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
8003734: f7ff f8d4 bl 80028e0 <HAL_GetTick>
8003738: 9b01 ldr r3, [sp, #4]
800373a: 1ac0 subs r0, r0, r3
800373c: 4b0a ldr r3, [pc, #40] @ (8003768 <HAL_RCC_ClockConfig+0x154>)
800373e: 4298 cmp r0, r3
8003740: d986 bls.n 8003650 <HAL_RCC_ClockConfig+0x3c>
8003742: e7b1 b.n 80036a8 <HAL_RCC_ClockConfig+0x94>
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
8003744: 68ab ldr r3, [r5, #8]
8003746: 4a0b ldr r2, [pc, #44] @ (8003774 <HAL_RCC_ClockConfig+0x160>)
8003748: 4013 ands r3, r2
800374a: 6922 ldr r2, [r4, #16]
800374c: 4313 orrs r3, r2
800374e: 60ab str r3, [r5, #8]
8003750: e786 b.n 8003660 <HAL_RCC_ClockConfig+0x4c>
8003752: 46c0 nop @ (mov r8, r8)
8003754: 40022000 .word 0x40022000
8003758: 40021000 .word 0x40021000
800375c: 0800524c .word 0x0800524c
8003760: 20000024 .word 0x20000024
8003764: 2000002c .word 0x2000002c
8003768: 00001388 .word 0x00001388
800376c: ffff84ff .word 0xffff84ff
8003770: fffff0ff .word 0xfffff0ff
8003774: ffff8fff .word 0xffff8fff
08003778 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8003778: b510 push {r4, lr}
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
800377a: f7ff ff1d bl 80035b8 <HAL_RCC_GetSysClockFreq>
800377e: 4b06 ldr r3, [pc, #24] @ (8003798 <HAL_RCC_GetHCLKFreq+0x20>)
8003780: 4a06 ldr r2, [pc, #24] @ (800379c <HAL_RCC_GetHCLKFreq+0x24>)
8003782: 689b ldr r3, [r3, #8]
>> RCC_CFGR_HPRE_Pos]) & 0x1FU));
8003784: 051b lsls r3, r3, #20
8003786: 0f1b lsrs r3, r3, #28
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
8003788: 009b lsls r3, r3, #2
>> RCC_CFGR_HPRE_Pos]) & 0x1FU));
800378a: 589b ldr r3, [r3, r2]
800378c: 221f movs r2, #31
800378e: 4013 ands r3, r2
SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
8003790: 40d8 lsrs r0, r3
8003792: 4b03 ldr r3, [pc, #12] @ (80037a0 <HAL_RCC_GetHCLKFreq+0x28>)
8003794: 6018 str r0, [r3, #0]
return SystemCoreClock;
}
8003796: bd10 pop {r4, pc}
8003798: 40021000 .word 0x40021000
800379c: 0800524c .word 0x0800524c
80037a0: 20000024 .word 0x20000024
080037a4 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
80037a4: b510 push {r4, lr}
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_Pos]) & 0x1FU));
80037a6: f7ff ffe7 bl 8003778 <HAL_RCC_GetHCLKFreq>
80037aa: 4b05 ldr r3, [pc, #20] @ (80037c0 <HAL_RCC_GetPCLK1Freq+0x1c>)
80037ac: 4a05 ldr r2, [pc, #20] @ (80037c4 <HAL_RCC_GetPCLK1Freq+0x20>)
80037ae: 689b ldr r3, [r3, #8]
80037b0: 045b lsls r3, r3, #17
80037b2: 0f5b lsrs r3, r3, #29
80037b4: 009b lsls r3, r3, #2
80037b6: 589b ldr r3, [r3, r2]
80037b8: 221f movs r2, #31
80037ba: 4013 ands r3, r2
80037bc: 40d8 lsrs r0, r3
}
80037be: bd10 pop {r4, pc}
80037c0: 40021000 .word 0x40021000
80037c4: 0800522c .word 0x0800522c
080037c8 <HAL_RCCEx_PeriphCLKConfig>:
* @note (*) not available on all devices
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
80037c8: b5f0 push {r4, r5, r6, r7, lr}
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*-------------------------- RTC clock source configuration ----------------------*/
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
80037ca: 6803 ldr r3, [r0, #0]
{
80037cc: 0005 movs r5, r0
80037ce: b085 sub sp, #20
HAL_StatusTypeDef status = HAL_OK; /* Final status */
80037d0: 2000 movs r0, #0
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
80037d2: 065b lsls r3, r3, #25
80037d4: d522 bpl.n 800381c <HAL_RCCEx_PeriphCLKConfig+0x54>
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
80037d6: 2280 movs r2, #128 @ 0x80
80037d8: 4c39 ldr r4, [pc, #228] @ (80038c0 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
80037da: 0552 lsls r2, r2, #21
80037dc: 6be3 ldr r3, [r4, #60] @ 0x3c
FlagStatus pwrclkchanged = RESET;
80037de: 0006 movs r6, r0
if (__HAL_RCC_PWR_IS_CLK_DISABLED())
80037e0: 4213 tst r3, r2
80037e2: d107 bne.n 80037f4 <HAL_RCCEx_PeriphCLKConfig+0x2c>
{
__HAL_RCC_PWR_CLK_ENABLE();
80037e4: 6be3 ldr r3, [r4, #60] @ 0x3c
pwrclkchanged = SET;
80037e6: 3601 adds r6, #1
__HAL_RCC_PWR_CLK_ENABLE();
80037e8: 4313 orrs r3, r2
80037ea: 63e3 str r3, [r4, #60] @ 0x3c
80037ec: 6be3 ldr r3, [r4, #60] @ 0x3c
80037ee: 4013 ands r3, r2
80037f0: 9303 str r3, [sp, #12]
80037f2: 9b03 ldr r3, [sp, #12]
}
/* Reset the RTC domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL);
80037f4: 6de2 ldr r2, [r4, #92] @ 0x5c
80037f6: 23c0 movs r3, #192 @ 0xc0
80037f8: 0011 movs r1, r2
80037fa: 009b lsls r3, r3, #2
80037fc: 4f31 ldr r7, [pc, #196] @ (80038c4 <HAL_RCCEx_PeriphCLKConfig+0xfc>)
80037fe: 4019 ands r1, r3
/* Reset the RTC domain only if the RTC Clock source selection is modified */
if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
8003800: 421a tst r2, r3
8003802: d13b bne.n 800387c <HAL_RCCEx_PeriphCLKConfig+0xb4>
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8003804: 2000 movs r0, #0
}
if (ret == HAL_OK)
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
8003806: 6de3 ldr r3, [r4, #92] @ 0x5c
8003808: 69aa ldr r2, [r5, #24]
800380a: 403b ands r3, r7
800380c: 4313 orrs r3, r2
800380e: 65e3 str r3, [r4, #92] @ 0x5c
/* set overall return value */
status = ret;
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
8003810: 2e01 cmp r6, #1
8003812: d103 bne.n 800381c <HAL_RCCEx_PeriphCLKConfig+0x54>
{
__HAL_RCC_PWR_CLK_DISABLE();
8003814: 6be3 ldr r3, [r4, #60] @ 0x3c
8003816: 4a2c ldr r2, [pc, #176] @ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x100>)
8003818: 4013 ands r3, r2
800381a: 63e3 str r3, [r4, #60] @ 0x3c
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
800381c: 682a ldr r2, [r5, #0]
800381e: 07d3 lsls r3, r2, #31
8003820: d506 bpl.n 8003830 <HAL_RCCEx_PeriphCLKConfig+0x68>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8003822: 2403 movs r4, #3
8003824: 4926 ldr r1, [pc, #152] @ (80038c0 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
8003826: 6d4b ldr r3, [r1, #84] @ 0x54
8003828: 43a3 bics r3, r4
800382a: 68ac ldr r4, [r5, #8]
800382c: 4323 orrs r3, r4
800382e: 654b str r3, [r1, #84] @ 0x54
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8003830: 0793 lsls r3, r2, #30
8003832: d506 bpl.n 8003842 <HAL_RCCEx_PeriphCLKConfig+0x7a>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8003834: 4922 ldr r1, [pc, #136] @ (80038c0 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
8003836: 4c25 ldr r4, [pc, #148] @ (80038cc <HAL_RCCEx_PeriphCLKConfig+0x104>)
8003838: 6d4b ldr r3, [r1, #84] @ 0x54
800383a: 4023 ands r3, r4
800383c: 68ec ldr r4, [r5, #12]
800383e: 4323 orrs r3, r4
8003840: 654b str r3, [r1, #84] @ 0x54
}
/*-------------------------- ADC clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
8003842: 0693 lsls r3, r2, #26
8003844: d506 bpl.n 8003854 <HAL_RCCEx_PeriphCLKConfig+0x8c>
{
/* Check the parameters */
assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
/* Configure the ADC interface clock source */
__HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
8003846: 491e ldr r1, [pc, #120] @ (80038c0 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
8003848: 696c ldr r4, [r5, #20]
800384a: 6d4b ldr r3, [r1, #84] @ 0x54
800384c: 009b lsls r3, r3, #2
800384e: 089b lsrs r3, r3, #2
8003850: 4323 orrs r3, r4
8003852: 654b str r3, [r1, #84] @ 0x54
__HAL_RCC_FDCAN1_CONFIG(PeriphClkInit->Fdcan1ClockSelection);
}
#endif /* FDCAN1 */
/*-------------------------- I2S1 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1)
8003854: 0753 lsls r3, r2, #29
8003856: d506 bpl.n 8003866 <HAL_RCCEx_PeriphCLKConfig+0x9e>
{
/* Check the parameters */
assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection));
/* Configure the I2S1 clock source */
__HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection);
8003858: 4919 ldr r1, [pc, #100] @ (80038c0 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
800385a: 4c1d ldr r4, [pc, #116] @ (80038d0 <HAL_RCCEx_PeriphCLKConfig+0x108>)
800385c: 6d4b ldr r3, [r1, #84] @ 0x54
800385e: 4023 ands r3, r4
8003860: 692c ldr r4, [r5, #16]
8003862: 4323 orrs r3, r4
8003864: 654b str r3, [r1, #84] @ 0x54
}
/*------------------------------------ HSI Kernel clock source configuration --------------------------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER)
8003866: 0612 lsls r2, r2, #24
8003868: d506 bpl.n 8003878 <HAL_RCCEx_PeriphCLKConfig+0xb0>
{
/* Check the parameters */
assert_param(IS_RCC_HSIKERDIV(PeriphClkInit->HSIKerClockDivider));
/* Configure the HSI Kernel clock source Divider */
__HAL_RCC_HSIKER_CONFIG(PeriphClkInit->HSIKerClockDivider);
800386a: 21e0 movs r1, #224 @ 0xe0
800386c: 4a14 ldr r2, [pc, #80] @ (80038c0 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
800386e: 6813 ldr r3, [r2, #0]
8003870: 438b bics r3, r1
8003872: 6869 ldr r1, [r5, #4]
8003874: 430b orrs r3, r1
8003876: 6013 str r3, [r2, #0]
}
return status;
}
8003878: b005 add sp, #20
800387a: bdf0 pop {r4, r5, r6, r7, pc}
if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
800387c: 69ab ldr r3, [r5, #24]
800387e: 428b cmp r3, r1
8003880: d0c0 beq.n 8003804 <HAL_RCCEx_PeriphCLKConfig+0x3c>
__HAL_RCC_BACKUPRESET_FORCE();
8003882: 2280 movs r2, #128 @ 0x80
tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL));
8003884: 6de3 ldr r3, [r4, #92] @ 0x5c
__HAL_RCC_BACKUPRESET_FORCE();
8003886: 6de0 ldr r0, [r4, #92] @ 0x5c
tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL));
8003888: 0019 movs r1, r3
__HAL_RCC_BACKUPRESET_FORCE();
800388a: 0252 lsls r2, r2, #9
800388c: 4302 orrs r2, r0
800388e: 65e2 str r2, [r4, #92] @ 0x5c
__HAL_RCC_BACKUPRESET_RELEASE();
8003890: 6de2 ldr r2, [r4, #92] @ 0x5c
8003892: 4810 ldr r0, [pc, #64] @ (80038d4 <HAL_RCCEx_PeriphCLKConfig+0x10c>)
tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL));
8003894: 4039 ands r1, r7
__HAL_RCC_BACKUPRESET_RELEASE();
8003896: 4002 ands r2, r0
8003898: 65e2 str r2, [r4, #92] @ 0x5c
RCC->CSR1 = tmpregister;
800389a: 65e1 str r1, [r4, #92] @ 0x5c
if (HAL_IS_BIT_SET(tmpregister, RCC_CSR1_LSEON))
800389c: 07db lsls r3, r3, #31
800389e: d5b1 bpl.n 8003804 <HAL_RCCEx_PeriphCLKConfig+0x3c>
tickstart = HAL_GetTick();
80038a0: f7ff f81e bl 80028e0 <HAL_GetTick>
80038a4: 9001 str r0, [sp, #4]
while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
80038a6: 2202 movs r2, #2
80038a8: 6de3 ldr r3, [r4, #92] @ 0x5c
80038aa: 4213 tst r3, r2
80038ac: d1aa bne.n 8003804 <HAL_RCCEx_PeriphCLKConfig+0x3c>
if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
80038ae: f7ff f817 bl 80028e0 <HAL_GetTick>
80038b2: 9b01 ldr r3, [sp, #4]
80038b4: 1ac0 subs r0, r0, r3
80038b6: 4b08 ldr r3, [pc, #32] @ (80038d8 <HAL_RCCEx_PeriphCLKConfig+0x110>)
80038b8: 4298 cmp r0, r3
80038ba: d9f4 bls.n 80038a6 <HAL_RCCEx_PeriphCLKConfig+0xde>
status = ret;
80038bc: 2003 movs r0, #3
80038be: e7a7 b.n 8003810 <HAL_RCCEx_PeriphCLKConfig+0x48>
80038c0: 40021000 .word 0x40021000
80038c4: fffffcff .word 0xfffffcff
80038c8: efffffff .word 0xefffffff
80038cc: ffffcfff .word 0xffffcfff
80038d0: ffff3fff .word 0xffff3fff
80038d4: fffeffff .word 0xfffeffff
80038d8: 00001388 .word 0x00001388
080038dc <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80038dc: b570 push {r4, r5, r6, lr}
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
80038de: 2401 movs r4, #1
tmpccer = TIMx->CCER;
80038e0: 6a03 ldr r3, [r0, #32]
TIMx->CCER &= ~TIM_CCER_CC1E;
80038e2: 6a02 ldr r2, [r0, #32]
80038e4: 43a2 bics r2, r4
80038e6: 6202 str r2, [r0, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
80038e8: 6844 ldr r4, [r0, #4]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
tmpccmrx &= ~TIM_CCMR1_CC1S;
80038ea: 4a12 ldr r2, [pc, #72] @ (8003934 <TIM_OC1_SetConfig+0x58>)
tmpccmrx = TIMx->CCMR1;
80038ec: 6985 ldr r5, [r0, #24]
tmpccmrx &= ~TIM_CCMR1_CC1S;
80038ee: 4015 ands r5, r2
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80038f0: 680a ldr r2, [r1, #0]
80038f2: 4315 orrs r5, r2
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
80038f4: 2202 movs r2, #2
80038f6: 4393 bics r3, r2
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
80038f8: 688a ldr r2, [r1, #8]
80038fa: 4313 orrs r3, r2
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
80038fc: 4a0e ldr r2, [pc, #56] @ (8003938 <TIM_OC1_SetConfig+0x5c>)
80038fe: 4290 cmp r0, r2
8003900: d005 beq.n 800390e <TIM_OC1_SetConfig+0x32>
8003902: 4a0e ldr r2, [pc, #56] @ (800393c <TIM_OC1_SetConfig+0x60>)
8003904: 4290 cmp r0, r2
8003906: d002 beq.n 800390e <TIM_OC1_SetConfig+0x32>
8003908: 4a0d ldr r2, [pc, #52] @ (8003940 <TIM_OC1_SetConfig+0x64>)
800390a: 4290 cmp r0, r2
800390c: d10b bne.n 8003926 <TIM_OC1_SetConfig+0x4a>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
800390e: 2208 movs r2, #8
8003910: 4393 bics r3, r2
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
8003912: 68ca ldr r2, [r1, #12]
tmpcr2 &= ~TIM_CR2_OIS1;
tmpcr2 &= ~TIM_CR2_OIS1N;
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
8003914: 698e ldr r6, [r1, #24]
tmpccer |= OC_Config->OCNPolarity;
8003916: 4313 orrs r3, r2
tmpccer &= ~TIM_CCER_CC1NE;
8003918: 2204 movs r2, #4
800391a: 4393 bics r3, r2
tmpcr2 &= ~TIM_CR2_OIS1N;
800391c: 4a09 ldr r2, [pc, #36] @ (8003944 <TIM_OC1_SetConfig+0x68>)
800391e: 4022 ands r2, r4
tmpcr2 |= OC_Config->OCNIdleState;
8003920: 694c ldr r4, [r1, #20]
8003922: 4334 orrs r4, r6
8003924: 4314 orrs r4, r2
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
8003926: 684a ldr r2, [r1, #4]
TIMx->CR2 = tmpcr2;
8003928: 6044 str r4, [r0, #4]
TIMx->CCMR1 = tmpccmrx;
800392a: 6185 str r5, [r0, #24]
TIMx->CCR1 = OC_Config->Pulse;
800392c: 6342 str r2, [r0, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800392e: 6203 str r3, [r0, #32]
}
8003930: bd70 pop {r4, r5, r6, pc}
8003932: 46c0 nop @ (mov r8, r8)
8003934: fffeff8c .word 0xfffeff8c
8003938: 40012c00 .word 0x40012c00
800393c: 40014400 .word 0x40014400
8003940: 40014800 .word 0x40014800
8003944: fffffcff .word 0xfffffcff
08003948 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8003948: b570 push {r4, r5, r6, lr}
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
800394a: 4a17 ldr r2, [pc, #92] @ (80039a8 <TIM_OC3_SetConfig+0x60>)
tmpccer = TIMx->CCER;
800394c: 6a05 ldr r5, [r0, #32]
TIMx->CCER &= ~TIM_CCER_CC3E;
800394e: 6a03 ldr r3, [r0, #32]
8003950: 4013 ands r3, r2
8003952: 6203 str r3, [r0, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8003954: 6842 ldr r2, [r0, #4]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
tmpccmrx &= ~TIM_CCMR2_CC3S;
8003956: 4b15 ldr r3, [pc, #84] @ (80039ac <TIM_OC3_SetConfig+0x64>)
tmpccmrx = TIMx->CCMR2;
8003958: 69c4 ldr r4, [r0, #28]
tmpccmrx &= ~TIM_CCMR2_CC3S;
800395a: 401c ands r4, r3
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
800395c: 680b ldr r3, [r1, #0]
800395e: 431c orrs r4, r3
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
8003960: 4b13 ldr r3, [pc, #76] @ (80039b0 <TIM_OC3_SetConfig+0x68>)
8003962: 401d ands r5, r3
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8003964: 688b ldr r3, [r1, #8]
8003966: 021b lsls r3, r3, #8
8003968: 432b orrs r3, r5
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
800396a: 4d12 ldr r5, [pc, #72] @ (80039b4 <TIM_OC3_SetConfig+0x6c>)
800396c: 42a8 cmp r0, r5
800396e: d10e bne.n 800398e <TIM_OC3_SetConfig+0x46>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
8003970: 4d11 ldr r5, [pc, #68] @ (80039b8 <TIM_OC3_SetConfig+0x70>)
8003972: 401d ands r5, r3
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
8003974: 68cb ldr r3, [r1, #12]
8003976: 021b lsls r3, r3, #8
8003978: 432b orrs r3, r5
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
800397a: 4d10 ldr r5, [pc, #64] @ (80039bc <TIM_OC3_SetConfig+0x74>)
800397c: 402b ands r3, r5
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
tmpcr2 &= ~TIM_CR2_OIS3N;
800397e: 4d10 ldr r5, [pc, #64] @ (80039c0 <TIM_OC3_SetConfig+0x78>)
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8003980: 698e ldr r6, [r1, #24]
tmpcr2 &= ~TIM_CR2_OIS3N;
8003982: 4015 ands r5, r2
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8003984: 694a ldr r2, [r1, #20]
8003986: 4332 orrs r2, r6
8003988: 0112 lsls r2, r2, #4
800398a: 432a orrs r2, r5
800398c: e005 b.n 800399a <TIM_OC3_SetConfig+0x52>
if (IS_TIM_BREAK_INSTANCE(TIMx))
800398e: 4d0d ldr r5, [pc, #52] @ (80039c4 <TIM_OC3_SetConfig+0x7c>)
8003990: 42a8 cmp r0, r5
8003992: d0f4 beq.n 800397e <TIM_OC3_SetConfig+0x36>
8003994: 4d0c ldr r5, [pc, #48] @ (80039c8 <TIM_OC3_SetConfig+0x80>)
8003996: 42a8 cmp r0, r5
8003998: d0f1 beq.n 800397e <TIM_OC3_SetConfig+0x36>
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800399a: 6042 str r2, [r0, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800399c: 684a ldr r2, [r1, #4]
TIMx->CCMR2 = tmpccmrx;
800399e: 61c4 str r4, [r0, #28]
TIMx->CCR3 = OC_Config->Pulse;
80039a0: 63c2 str r2, [r0, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80039a2: 6203 str r3, [r0, #32]
}
80039a4: bd70 pop {r4, r5, r6, pc}
80039a6: 46c0 nop @ (mov r8, r8)
80039a8: fffffeff .word 0xfffffeff
80039ac: fffeff8c .word 0xfffeff8c
80039b0: fffffdff .word 0xfffffdff
80039b4: 40012c00 .word 0x40012c00
80039b8: fffff7ff .word 0xfffff7ff
80039bc: fffffbff .word 0xfffffbff
80039c0: ffffcfff .word 0xffffcfff
80039c4: 40014400 .word 0x40014400
80039c8: 40014800 .word 0x40014800
080039cc <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
80039cc: b530 push {r4, r5, lr}
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
80039ce: 4a12 ldr r2, [pc, #72] @ (8003a18 <TIM_OC4_SetConfig+0x4c>)
tmpccer = TIMx->CCER;
80039d0: 6a04 ldr r4, [r0, #32]
TIMx->CCER &= ~TIM_CCER_CC4E;
80039d2: 6a03 ldr r3, [r0, #32]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
tmpccmrx &= ~TIM_CCMR2_CC4S;
80039d4: 4d11 ldr r5, [pc, #68] @ (8003a1c <TIM_OC4_SetConfig+0x50>)
TIMx->CCER &= ~TIM_CCER_CC4E;
80039d6: 4013 ands r3, r2
80039d8: 6203 str r3, [r0, #32]
tmpcr2 = TIMx->CR2;
80039da: 6843 ldr r3, [r0, #4]
tmpccmrx = TIMx->CCMR2;
80039dc: 69c2 ldr r2, [r0, #28]
tmpccmrx &= ~TIM_CCMR2_CC4S;
80039de: 402a ands r2, r5
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
80039e0: 680d ldr r5, [r1, #0]
80039e2: 022d lsls r5, r5, #8
80039e4: 4315 orrs r5, r2
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
80039e6: 4a0e ldr r2, [pc, #56] @ (8003a20 <TIM_OC4_SetConfig+0x54>)
80039e8: 4014 ands r4, r2
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
80039ea: 688a ldr r2, [r1, #8]
80039ec: 0312 lsls r2, r2, #12
80039ee: 4322 orrs r2, r4
if (IS_TIM_BREAK_INSTANCE(TIMx))
80039f0: 4c0c ldr r4, [pc, #48] @ (8003a24 <TIM_OC4_SetConfig+0x58>)
80039f2: 42a0 cmp r0, r4
80039f4: d005 beq.n 8003a02 <TIM_OC4_SetConfig+0x36>
80039f6: 4c0c ldr r4, [pc, #48] @ (8003a28 <TIM_OC4_SetConfig+0x5c>)
80039f8: 42a0 cmp r0, r4
80039fa: d002 beq.n 8003a02 <TIM_OC4_SetConfig+0x36>
80039fc: 4c0b ldr r4, [pc, #44] @ (8003a2c <TIM_OC4_SetConfig+0x60>)
80039fe: 42a0 cmp r0, r4
8003a00: d104 bne.n 8003a0c <TIM_OC4_SetConfig+0x40>
{
/* Check parameters */
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
8003a02: 4c0b ldr r4, [pc, #44] @ (8003a30 <TIM_OC4_SetConfig+0x64>)
8003a04: 401c ands r4, r3
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
8003a06: 694b ldr r3, [r1, #20]
8003a08: 019b lsls r3, r3, #6
8003a0a: 4323 orrs r3, r4
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003a0c: 6043 str r3, [r0, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8003a0e: 684b ldr r3, [r1, #4]
TIMx->CCMR2 = tmpccmrx;
8003a10: 61c5 str r5, [r0, #28]
TIMx->CCR4 = OC_Config->Pulse;
8003a12: 6403 str r3, [r0, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003a14: 6202 str r2, [r0, #32]
}
8003a16: bd30 pop {r4, r5, pc}
8003a18: ffffefff .word 0xffffefff
8003a1c: feff8cff .word 0xfeff8cff
8003a20: ffffdfff .word 0xffffdfff
8003a24: 40012c00 .word 0x40012c00
8003a28: 40014400 .word 0x40014400
8003a2c: 40014800 .word 0x40014800
8003a30: ffffbfff .word 0xffffbfff
08003a34 <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8003a34: b570 push {r4, r5, r6, lr}
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8003a36: 6a06 ldr r6, [r0, #32]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
8003a38: 4c10 ldr r4, [pc, #64] @ (8003a7c <TIM_OC5_SetConfig+0x48>)
8003a3a: 6a03 ldr r3, [r0, #32]
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
8003a3c: 4a10 ldr r2, [pc, #64] @ (8003a80 <TIM_OC5_SetConfig+0x4c>)
TIMx->CCER &= ~TIM_CCER_CC5E;
8003a3e: 4023 ands r3, r4
8003a40: 6203 str r3, [r0, #32]
tmpcr2 = TIMx->CR2;
8003a42: 6843 ldr r3, [r0, #4]
tmpccmrx = TIMx->CCMR3;
8003a44: 6d45 ldr r5, [r0, #84] @ 0x54
tmpccmrx &= ~(TIM_CCMR3_OC5M);
8003a46: 4015 ands r5, r2
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8003a48: 680a ldr r2, [r1, #0]
8003a4a: 4315 orrs r5, r2
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
8003a4c: 4a0d ldr r2, [pc, #52] @ (8003a84 <TIM_OC5_SetConfig+0x50>)
8003a4e: 4016 ands r6, r2
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
8003a50: 688a ldr r2, [r1, #8]
8003a52: 0412 lsls r2, r2, #16
8003a54: 4332 orrs r2, r6
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003a56: 4e0c ldr r6, [pc, #48] @ (8003a88 <TIM_OC5_SetConfig+0x54>)
8003a58: 42b0 cmp r0, r6
8003a5a: d005 beq.n 8003a68 <TIM_OC5_SetConfig+0x34>
8003a5c: 4e0b ldr r6, [pc, #44] @ (8003a8c <TIM_OC5_SetConfig+0x58>)
8003a5e: 42b0 cmp r0, r6
8003a60: d002 beq.n 8003a68 <TIM_OC5_SetConfig+0x34>
8003a62: 4e0b ldr r6, [pc, #44] @ (8003a90 <TIM_OC5_SetConfig+0x5c>)
8003a64: 42b0 cmp r0, r6
8003a66: d103 bne.n 8003a70 <TIM_OC5_SetConfig+0x3c>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
8003a68: 401c ands r4, r3
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
8003a6a: 694b ldr r3, [r1, #20]
8003a6c: 021b lsls r3, r3, #8
8003a6e: 4323 orrs r3, r4
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003a70: 6043 str r3, [r0, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
8003a72: 684b ldr r3, [r1, #4]
TIMx->CCMR3 = tmpccmrx;
8003a74: 6545 str r5, [r0, #84] @ 0x54
TIMx->CCR5 = OC_Config->Pulse;
8003a76: 6583 str r3, [r0, #88] @ 0x58
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003a78: 6202 str r2, [r0, #32]
}
8003a7a: bd70 pop {r4, r5, r6, pc}
8003a7c: fffeffff .word 0xfffeffff
8003a80: fffeff8f .word 0xfffeff8f
8003a84: fffdffff .word 0xfffdffff
8003a88: 40012c00 .word 0x40012c00
8003a8c: 40014400 .word 0x40014400
8003a90: 40014800 .word 0x40014800
08003a94 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8003a94: b530 push {r4, r5, lr}
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
8003a96: 4a12 ldr r2, [pc, #72] @ (8003ae0 <TIM_OC6_SetConfig+0x4c>)
tmpccer = TIMx->CCER;
8003a98: 6a04 ldr r4, [r0, #32]
TIMx->CCER &= ~TIM_CCER_CC6E;
8003a9a: 6a03 ldr r3, [r0, #32]
tmpcr2 = TIMx->CR2;
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
8003a9c: 4d11 ldr r5, [pc, #68] @ (8003ae4 <TIM_OC6_SetConfig+0x50>)
TIMx->CCER &= ~TIM_CCER_CC6E;
8003a9e: 4013 ands r3, r2
8003aa0: 6203 str r3, [r0, #32]
tmpcr2 = TIMx->CR2;
8003aa2: 6843 ldr r3, [r0, #4]
tmpccmrx = TIMx->CCMR3;
8003aa4: 6d42 ldr r2, [r0, #84] @ 0x54
tmpccmrx &= ~(TIM_CCMR3_OC6M);
8003aa6: 402a ands r2, r5
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8003aa8: 680d ldr r5, [r1, #0]
8003aaa: 022d lsls r5, r5, #8
8003aac: 4315 orrs r5, r2
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
8003aae: 4a0e ldr r2, [pc, #56] @ (8003ae8 <TIM_OC6_SetConfig+0x54>)
8003ab0: 4014 ands r4, r2
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
8003ab2: 688a ldr r2, [r1, #8]
8003ab4: 0512 lsls r2, r2, #20
8003ab6: 4322 orrs r2, r4
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003ab8: 4c0c ldr r4, [pc, #48] @ (8003aec <TIM_OC6_SetConfig+0x58>)
8003aba: 42a0 cmp r0, r4
8003abc: d005 beq.n 8003aca <TIM_OC6_SetConfig+0x36>
8003abe: 4c0c ldr r4, [pc, #48] @ (8003af0 <TIM_OC6_SetConfig+0x5c>)
8003ac0: 42a0 cmp r0, r4
8003ac2: d002 beq.n 8003aca <TIM_OC6_SetConfig+0x36>
8003ac4: 4c0b ldr r4, [pc, #44] @ (8003af4 <TIM_OC6_SetConfig+0x60>)
8003ac6: 42a0 cmp r0, r4
8003ac8: d104 bne.n 8003ad4 <TIM_OC6_SetConfig+0x40>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
8003aca: 4c0b ldr r4, [pc, #44] @ (8003af8 <TIM_OC6_SetConfig+0x64>)
8003acc: 401c ands r4, r3
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
8003ace: 694b ldr r3, [r1, #20]
8003ad0: 029b lsls r3, r3, #10
8003ad2: 4323 orrs r3, r4
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8003ad4: 6043 str r3, [r0, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
8003ad6: 684b ldr r3, [r1, #4]
TIMx->CCMR3 = tmpccmrx;
8003ad8: 6545 str r5, [r0, #84] @ 0x54
TIMx->CCR6 = OC_Config->Pulse;
8003ada: 65c3 str r3, [r0, #92] @ 0x5c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8003adc: 6202 str r2, [r0, #32]
}
8003ade: bd30 pop {r4, r5, pc}
8003ae0: ffefffff .word 0xffefffff
8003ae4: feff8fff .word 0xfeff8fff
8003ae8: ffdfffff .word 0xffdfffff
8003aec: 40012c00 .word 0x40012c00
8003af0: 40014400 .word 0x40014400
8003af4: 40014800 .word 0x40014800
8003af8: fffbffff .word 0xfffbffff
08003afc <HAL_TIM_Base_Stop>:
__HAL_TIM_DISABLE(htim);
8003afc: 6803 ldr r3, [r0, #0]
8003afe: 4a08 ldr r2, [pc, #32] @ (8003b20 <HAL_TIM_Base_Stop+0x24>)
8003b00: 6a19 ldr r1, [r3, #32]
8003b02: 4211 tst r1, r2
8003b04: d107 bne.n 8003b16 <HAL_TIM_Base_Stop+0x1a>
8003b06: 6a19 ldr r1, [r3, #32]
8003b08: 4a06 ldr r2, [pc, #24] @ (8003b24 <HAL_TIM_Base_Stop+0x28>)
8003b0a: 4211 tst r1, r2
8003b0c: d103 bne.n 8003b16 <HAL_TIM_Base_Stop+0x1a>
8003b0e: 2101 movs r1, #1
8003b10: 681a ldr r2, [r3, #0]
8003b12: 438a bics r2, r1
8003b14: 601a str r2, [r3, #0]
htim->State = HAL_TIM_STATE_READY;
8003b16: 2301 movs r3, #1
8003b18: 303d adds r0, #61 @ 0x3d
8003b1a: 7003 strb r3, [r0, #0]
}
8003b1c: 2000 movs r0, #0
8003b1e: 4770 bx lr
8003b20: 00001111 .word 0x00001111
8003b24: 00000444 .word 0x00000444
08003b28 <HAL_TIM_Base_Start_IT>:
if (htim->State != HAL_TIM_STATE_READY)
8003b28: 0001 movs r1, r0
{
8003b2a: 0003 movs r3, r0
return HAL_ERROR;
8003b2c: 2001 movs r0, #1
{
8003b2e: b510 push {r4, lr}
if (htim->State != HAL_TIM_STATE_READY)
8003b30: 313d adds r1, #61 @ 0x3d
8003b32: 780c ldrb r4, [r1, #0]
8003b34: b2e2 uxtb r2, r4
8003b36: 4284 cmp r4, r0
8003b38: d11c bne.n 8003b74 <HAL_TIM_Base_Start_IT+0x4c>
htim->State = HAL_TIM_STATE_BUSY;
8003b3a: 1800 adds r0, r0, r0
8003b3c: 7008 strb r0, [r1, #0]
__HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
8003b3e: 681b ldr r3, [r3, #0]
8003b40: 68d9 ldr r1, [r3, #12]
8003b42: 4311 orrs r1, r2
8003b44: 60d9 str r1, [r3, #12]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8003b46: 490d ldr r1, [pc, #52] @ (8003b7c <HAL_TIM_Base_Start_IT+0x54>)
8003b48: 428b cmp r3, r1
8003b4a: d006 beq.n 8003b5a <HAL_TIM_Base_Start_IT+0x32>
8003b4c: 2180 movs r1, #128 @ 0x80
8003b4e: 05c9 lsls r1, r1, #23
8003b50: 428b cmp r3, r1
8003b52: d002 beq.n 8003b5a <HAL_TIM_Base_Start_IT+0x32>
8003b54: 490a ldr r1, [pc, #40] @ (8003b80 <HAL_TIM_Base_Start_IT+0x58>)
8003b56: 428b cmp r3, r1
8003b58: d10d bne.n 8003b76 <HAL_TIM_Base_Start_IT+0x4e>
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8003b5a: 689a ldr r2, [r3, #8]
8003b5c: 4909 ldr r1, [pc, #36] @ (8003b84 <HAL_TIM_Base_Start_IT+0x5c>)
8003b5e: 400a ands r2, r1
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8003b60: 2a06 cmp r2, #6
8003b62: d006 beq.n 8003b72 <HAL_TIM_Base_Start_IT+0x4a>
8003b64: 3907 subs r1, #7
8003b66: 428a cmp r2, r1
8003b68: d003 beq.n 8003b72 <HAL_TIM_Base_Start_IT+0x4a>
__HAL_TIM_ENABLE(htim);
8003b6a: 2201 movs r2, #1
8003b6c: 6819 ldr r1, [r3, #0]
8003b6e: 430a orrs r2, r1
8003b70: 601a str r2, [r3, #0]
return HAL_OK;
8003b72: 2000 movs r0, #0
}
8003b74: bd10 pop {r4, pc}
__HAL_TIM_ENABLE(htim);
8003b76: 6819 ldr r1, [r3, #0]
8003b78: e7f9 b.n 8003b6e <HAL_TIM_Base_Start_IT+0x46>
8003b7a: 46c0 nop @ (mov r8, r8)
8003b7c: 40012c00 .word 0x40012c00
8003b80: 40000400 .word 0x40000400
8003b84: 00010007 .word 0x00010007
08003b88 <HAL_TIM_PWM_MspInit>:
__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
8003b88: 4770 bx lr
08003b8a <HAL_TIM_Encoder_Start>:
{
8003b8a: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
8003b8c: 223e movs r2, #62 @ 0x3e
{
8003b8e: 0003 movs r3, r0
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
8003b90: 4694 mov ip, r2
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
8003b92: 001f movs r7, r3
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
8003b94: 4484 add ip, r0
8003b96: 4662 mov r2, ip
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
8003b98: 001e movs r6, r3
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
8003b9a: 001d movs r5, r3
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
8003b9c: 373f adds r7, #63 @ 0x3f
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
8003b9e: 7810 ldrb r0, [r2, #0]
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
8003ba0: 783a ldrb r2, [r7, #0]
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
8003ba2: 3644 adds r6, #68 @ 0x44
HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
8003ba4: b2d2 uxtb r2, r2
8003ba6: 9201 str r2, [sp, #4]
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
8003ba8: 3545 adds r5, #69 @ 0x45
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
8003baa: 7834 ldrb r4, [r6, #0]
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
8003bac: 782a ldrb r2, [r5, #0]
HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
8003bae: b2c0 uxtb r0, r0
HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
8003bb0: b2e4 uxtb r4, r4
HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
8003bb2: b2d2 uxtb r2, r2
if (Channel == TIM_CHANNEL_1)
8003bb4: 2900 cmp r1, #0
8003bb6: d114 bne.n 8003be2 <HAL_TIM_Encoder_Start+0x58>
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
8003bb8: 2801 cmp r0, #1
8003bba: d13c bne.n 8003c36 <HAL_TIM_Encoder_Start+0xac>
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
8003bbc: 2c01 cmp r4, #1
8003bbe: d10f bne.n 8003be0 <HAL_TIM_Encoder_Start+0x56>
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
8003bc0: 2202 movs r2, #2
8003bc2: 4661 mov r1, ip
8003bc4: 700a strb r2, [r1, #0]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
8003bc6: 7032 strb r2, [r6, #0]
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
8003bc8: 681b ldr r3, [r3, #0]
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8003bca: 6a1a ldr r2, [r3, #32]
8003bcc: 43a2 bics r2, r4
8003bce: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8003bd0: 6a1a ldr r2, [r3, #32]
8003bd2: 4322 orrs r2, r4
8003bd4: 621a str r2, [r3, #32]
__HAL_TIM_ENABLE(htim);
8003bd6: 2201 movs r2, #1
return HAL_OK;
8003bd8: 2000 movs r0, #0
__HAL_TIM_ENABLE(htim);
8003bda: 6819 ldr r1, [r3, #0]
8003bdc: 430a orrs r2, r1
8003bde: 601a str r2, [r3, #0]
}
8003be0: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
else if (Channel == TIM_CHANNEL_2)
8003be2: 2904 cmp r1, #4
8003be4: d110 bne.n 8003c08 <HAL_TIM_Encoder_Start+0x7e>
return HAL_ERROR;
8003be6: 2001 movs r0, #1
if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
8003be8: 9901 ldr r1, [sp, #4]
8003bea: 4281 cmp r1, r0
8003bec: d1f8 bne.n 8003be0 <HAL_TIM_Encoder_Start+0x56>
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
8003bee: 4282 cmp r2, r0
8003bf0: d1f6 bne.n 8003be0 <HAL_TIM_Encoder_Start+0x56>
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
8003bf2: 2202 movs r2, #2
8003bf4: 703a strb r2, [r7, #0]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
8003bf6: 702a strb r2, [r5, #0]
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
8003bf8: 681b ldr r3, [r3, #0]
TIMx->CCER &= ~tmp;
8003bfa: 2210 movs r2, #16
8003bfc: 6a19 ldr r1, [r3, #32]
8003bfe: 4391 bics r1, r2
8003c00: 6219 str r1, [r3, #32]
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8003c02: 6a19 ldr r1, [r3, #32]
8003c04: 430a orrs r2, r1
8003c06: e7e5 b.n 8003bd4 <HAL_TIM_Encoder_Start+0x4a>
if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
8003c08: 2801 cmp r0, #1
8003c0a: d114 bne.n 8003c36 <HAL_TIM_Encoder_Start+0xac>
|| (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
8003c0c: 9901 ldr r1, [sp, #4]
8003c0e: 2901 cmp r1, #1
8003c10: d1e6 bne.n 8003be0 <HAL_TIM_Encoder_Start+0x56>
|| (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
8003c12: 2c01 cmp r4, #1
8003c14: d1e4 bne.n 8003be0 <HAL_TIM_Encoder_Start+0x56>
|| (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
8003c16: 2a01 cmp r2, #1
8003c18: d1e2 bne.n 8003be0 <HAL_TIM_Encoder_Start+0x56>
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
8003c1a: 4660 mov r0, ip
8003c1c: 3101 adds r1, #1
8003c1e: 7001 strb r1, [r0, #0]
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
8003c20: 7039 strb r1, [r7, #0]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
8003c22: 7031 strb r1, [r6, #0]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
8003c24: 7029 strb r1, [r5, #0]
TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
8003c26: 681b ldr r3, [r3, #0]
TIMx->CCER &= ~tmp;
8003c28: 6a19 ldr r1, [r3, #32]
8003c2a: 4391 bics r1, r2
8003c2c: 6219 str r1, [r3, #32]
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8003c2e: 6a19 ldr r1, [r3, #32]
8003c30: 430a orrs r2, r1
8003c32: 621a str r2, [r3, #32]
8003c34: e7e1 b.n 8003bfa <HAL_TIM_Encoder_Start+0x70>
return HAL_ERROR;
8003c36: 2001 movs r0, #1
8003c38: e7d2 b.n 8003be0 <HAL_TIM_Encoder_Start+0x56>
08003c3a <HAL_TIM_OC_DelayElapsedCallback>:
__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
8003c3a: 4770 bx lr
08003c3c <HAL_TIM_IC_CaptureCallback>:
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
8003c3c: 4770 bx lr
08003c3e <HAL_TIM_PWM_PulseFinishedCallback>:
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
8003c3e: 4770 bx lr
08003c40 <HAL_TIM_TriggerCallback>:
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
8003c40: 4770 bx lr
...
08003c44 <HAL_TIM_IRQHandler>:
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8003c44: 2202 movs r2, #2
uint32_t itsource = htim->Instance->DIER;
8003c46: 6803 ldr r3, [r0, #0]
{
8003c48: b570 push {r4, r5, r6, lr}
uint32_t itsource = htim->Instance->DIER;
8003c4a: 68dd ldr r5, [r3, #12]
uint32_t itflag = htim->Instance->SR;
8003c4c: 691e ldr r6, [r3, #16]
{
8003c4e: 0004 movs r4, r0
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8003c50: 4216 tst r6, r2
8003c52: d00d beq.n 8003c70 <HAL_TIM_IRQHandler+0x2c>
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
8003c54: 4215 tst r5, r2
8003c56: d00b beq.n 8003c70 <HAL_TIM_IRQHandler+0x2c>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8003c58: 3a05 subs r2, #5
8003c5a: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
8003c5c: 3204 adds r2, #4
8003c5e: 7702 strb r2, [r0, #28]
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
8003c60: 699b ldr r3, [r3, #24]
8003c62: 079b lsls r3, r3, #30
8003c64: d100 bne.n 8003c68 <HAL_TIM_IRQHandler+0x24>
8003c66: e07c b.n 8003d62 <HAL_TIM_IRQHandler+0x11e>
HAL_TIM_IC_CaptureCallback(htim);
8003c68: f7ff ffe8 bl 8003c3c <HAL_TIM_IC_CaptureCallback>
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003c6c: 2300 movs r3, #0
8003c6e: 7723 strb r3, [r4, #28]
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
8003c70: 2304 movs r3, #4
8003c72: 421e tst r6, r3
8003c74: d012 beq.n 8003c9c <HAL_TIM_IRQHandler+0x58>
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
8003c76: 421d tst r5, r3
8003c78: d010 beq.n 8003c9c <HAL_TIM_IRQHandler+0x58>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
8003c7a: 2205 movs r2, #5
8003c7c: 6823 ldr r3, [r4, #0]
8003c7e: 4252 negs r2, r2
8003c80: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
8003c82: 3207 adds r2, #7
8003c84: 7722 strb r2, [r4, #28]
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8003c86: 699a ldr r2, [r3, #24]
8003c88: 23c0 movs r3, #192 @ 0xc0
8003c8a: 009b lsls r3, r3, #2
HAL_TIM_IC_CaptureCallback(htim);
8003c8c: 0020 movs r0, r4
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
8003c8e: 421a tst r2, r3
8003c90: d100 bne.n 8003c94 <HAL_TIM_IRQHandler+0x50>
8003c92: e06c b.n 8003d6e <HAL_TIM_IRQHandler+0x12a>
HAL_TIM_IC_CaptureCallback(htim);
8003c94: f7ff ffd2 bl 8003c3c <HAL_TIM_IC_CaptureCallback>
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003c98: 2300 movs r3, #0
8003c9a: 7723 strb r3, [r4, #28]
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
8003c9c: 2308 movs r3, #8
8003c9e: 421e tst r6, r3
8003ca0: d00f beq.n 8003cc2 <HAL_TIM_IRQHandler+0x7e>
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
8003ca2: 421d tst r5, r3
8003ca4: d00d beq.n 8003cc2 <HAL_TIM_IRQHandler+0x7e>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
8003ca6: 2209 movs r2, #9
8003ca8: 6823 ldr r3, [r4, #0]
8003caa: 4252 negs r2, r2
8003cac: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8003cae: 320d adds r2, #13
8003cb0: 7722 strb r2, [r4, #28]
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8003cb2: 69db ldr r3, [r3, #28]
HAL_TIM_IC_CaptureCallback(htim);
8003cb4: 0020 movs r0, r4
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
8003cb6: 079b lsls r3, r3, #30
8003cb8: d05f beq.n 8003d7a <HAL_TIM_IRQHandler+0x136>
HAL_TIM_IC_CaptureCallback(htim);
8003cba: f7ff ffbf bl 8003c3c <HAL_TIM_IC_CaptureCallback>
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003cbe: 2300 movs r3, #0
8003cc0: 7723 strb r3, [r4, #28]
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
8003cc2: 2310 movs r3, #16
8003cc4: 421e tst r6, r3
8003cc6: d011 beq.n 8003cec <HAL_TIM_IRQHandler+0xa8>
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
8003cc8: 421d tst r5, r3
8003cca: d00f beq.n 8003cec <HAL_TIM_IRQHandler+0xa8>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
8003ccc: 2211 movs r2, #17
8003cce: 6823 ldr r3, [r4, #0]
8003cd0: 4252 negs r2, r2
8003cd2: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8003cd4: 3219 adds r2, #25
8003cd6: 7722 strb r2, [r4, #28]
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8003cd8: 69da ldr r2, [r3, #28]
8003cda: 23c0 movs r3, #192 @ 0xc0
8003cdc: 009b lsls r3, r3, #2
HAL_TIM_IC_CaptureCallback(htim);
8003cde: 0020 movs r0, r4
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8003ce0: 421a tst r2, r3
8003ce2: d050 beq.n 8003d86 <HAL_TIM_IRQHandler+0x142>
HAL_TIM_IC_CaptureCallback(htim);
8003ce4: f7ff ffaa bl 8003c3c <HAL_TIM_IC_CaptureCallback>
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8003ce8: 2300 movs r3, #0
8003cea: 7723 strb r3, [r4, #28]
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
8003cec: 2301 movs r3, #1
8003cee: 421e tst r6, r3
8003cf0: d008 beq.n 8003d04 <HAL_TIM_IRQHandler+0xc0>
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
8003cf2: 421d tst r5, r3
8003cf4: d006 beq.n 8003d04 <HAL_TIM_IRQHandler+0xc0>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8003cf6: 2202 movs r2, #2
8003cf8: 6823 ldr r3, [r4, #0]
8003cfa: 4252 negs r2, r2
HAL_TIM_PeriodElapsedCallback(htim);
8003cfc: 0020 movs r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
8003cfe: 611a str r2, [r3, #16]
HAL_TIM_PeriodElapsedCallback(htim);
8003d00: f7fc fd70 bl 80007e4 <HAL_TIM_PeriodElapsedCallback>
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
8003d04: 2382 movs r3, #130 @ 0x82
8003d06: 019b lsls r3, r3, #6
8003d08: 421e tst r6, r3
8003d0a: d007 beq.n 8003d1c <HAL_TIM_IRQHandler+0xd8>
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8003d0c: 062b lsls r3, r5, #24
8003d0e: d505 bpl.n 8003d1c <HAL_TIM_IRQHandler+0xd8>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
8003d10: 6823 ldr r3, [r4, #0]
8003d12: 4a20 ldr r2, [pc, #128] @ (8003d94 <HAL_TIM_IRQHandler+0x150>)
HAL_TIMEx_BreakCallback(htim);
8003d14: 0020 movs r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
8003d16: 611a str r2, [r3, #16]
HAL_TIMEx_BreakCallback(htim);
8003d18: f000 fbb5 bl 8004486 <HAL_TIMEx_BreakCallback>
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
8003d1c: 05f3 lsls r3, r6, #23
8003d1e: d507 bpl.n 8003d30 <HAL_TIM_IRQHandler+0xec>
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8003d20: 062b lsls r3, r5, #24
8003d22: d505 bpl.n 8003d30 <HAL_TIM_IRQHandler+0xec>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8003d24: 6823 ldr r3, [r4, #0]
8003d26: 4a1c ldr r2, [pc, #112] @ (8003d98 <HAL_TIM_IRQHandler+0x154>)
HAL_TIMEx_Break2Callback(htim);
8003d28: 0020 movs r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8003d2a: 611a str r2, [r3, #16]
HAL_TIMEx_Break2Callback(htim);
8003d2c: f000 fbac bl 8004488 <HAL_TIMEx_Break2Callback>
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
8003d30: 2340 movs r3, #64 @ 0x40
8003d32: 421e tst r6, r3
8003d34: d008 beq.n 8003d48 <HAL_TIM_IRQHandler+0x104>
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
8003d36: 421d tst r5, r3
8003d38: d006 beq.n 8003d48 <HAL_TIM_IRQHandler+0x104>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
8003d3a: 2241 movs r2, #65 @ 0x41
8003d3c: 6823 ldr r3, [r4, #0]
8003d3e: 4252 negs r2, r2
HAL_TIM_TriggerCallback(htim);
8003d40: 0020 movs r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
8003d42: 611a str r2, [r3, #16]
HAL_TIM_TriggerCallback(htim);
8003d44: f7ff ff7c bl 8003c40 <HAL_TIM_TriggerCallback>
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
8003d48: 2320 movs r3, #32
8003d4a: 421e tst r6, r3
8003d4c: d008 beq.n 8003d60 <HAL_TIM_IRQHandler+0x11c>
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
8003d4e: 421d tst r5, r3
8003d50: d006 beq.n 8003d60 <HAL_TIM_IRQHandler+0x11c>
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
8003d52: 2221 movs r2, #33 @ 0x21
8003d54: 6823 ldr r3, [r4, #0]
8003d56: 4252 negs r2, r2
HAL_TIMEx_CommutCallback(htim);
8003d58: 0020 movs r0, r4
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
8003d5a: 611a str r2, [r3, #16]
HAL_TIMEx_CommutCallback(htim);
8003d5c: f000 fb92 bl 8004484 <HAL_TIMEx_CommutCallback>
}
8003d60: bd70 pop {r4, r5, r6, pc}
HAL_TIM_OC_DelayElapsedCallback(htim);
8003d62: f7ff ff6a bl 8003c3a <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003d66: 0020 movs r0, r4
8003d68: f7ff ff69 bl 8003c3e <HAL_TIM_PWM_PulseFinishedCallback>
8003d6c: e77e b.n 8003c6c <HAL_TIM_IRQHandler+0x28>
HAL_TIM_OC_DelayElapsedCallback(htim);
8003d6e: f7ff ff64 bl 8003c3a <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003d72: 0020 movs r0, r4
8003d74: f7ff ff63 bl 8003c3e <HAL_TIM_PWM_PulseFinishedCallback>
8003d78: e78e b.n 8003c98 <HAL_TIM_IRQHandler+0x54>
HAL_TIM_OC_DelayElapsedCallback(htim);
8003d7a: f7ff ff5e bl 8003c3a <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003d7e: 0020 movs r0, r4
8003d80: f7ff ff5d bl 8003c3e <HAL_TIM_PWM_PulseFinishedCallback>
8003d84: e79b b.n 8003cbe <HAL_TIM_IRQHandler+0x7a>
HAL_TIM_OC_DelayElapsedCallback(htim);
8003d86: f7ff ff58 bl 8003c3a <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8003d8a: 0020 movs r0, r4
8003d8c: f7ff ff57 bl 8003c3e <HAL_TIM_PWM_PulseFinishedCallback>
8003d90: e7aa b.n 8003ce8 <HAL_TIM_IRQHandler+0xa4>
8003d92: 46c0 nop @ (mov r8, r8)
8003d94: ffffdf7f .word 0xffffdf7f
8003d98: fffffeff .word 0xfffffeff
08003d9c <TIM_Base_SetConfig>:
{
8003d9c: b510 push {r4, lr}
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8003d9e: 4c1b ldr r4, [pc, #108] @ (8003e0c <TIM_Base_SetConfig+0x70>)
tmpcr1 = TIMx->CR1;
8003da0: 6803 ldr r3, [r0, #0]
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8003da2: 42a0 cmp r0, r4
8003da4: d006 beq.n 8003db4 <TIM_Base_SetConfig+0x18>
8003da6: 2280 movs r2, #128 @ 0x80
8003da8: 05d2 lsls r2, r2, #23
8003daa: 4290 cmp r0, r2
8003dac: d002 beq.n 8003db4 <TIM_Base_SetConfig+0x18>
8003dae: 4a18 ldr r2, [pc, #96] @ (8003e10 <TIM_Base_SetConfig+0x74>)
8003db0: 4290 cmp r0, r2
8003db2: d108 bne.n 8003dc6 <TIM_Base_SetConfig+0x2a>
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8003db4: 2270 movs r2, #112 @ 0x70
8003db6: 4393 bics r3, r2
tmpcr1 |= Structure->CounterMode;
8003db8: 684a ldr r2, [r1, #4]
8003dba: 4313 orrs r3, r2
tmpcr1 &= ~TIM_CR1_CKD;
8003dbc: 4a15 ldr r2, [pc, #84] @ (8003e14 <TIM_Base_SetConfig+0x78>)
8003dbe: 401a ands r2, r3
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8003dc0: 68cb ldr r3, [r1, #12]
8003dc2: 4313 orrs r3, r2
8003dc4: e008 b.n 8003dd8 <TIM_Base_SetConfig+0x3c>
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8003dc6: 4a14 ldr r2, [pc, #80] @ (8003e18 <TIM_Base_SetConfig+0x7c>)
8003dc8: 4290 cmp r0, r2
8003dca: d0f7 beq.n 8003dbc <TIM_Base_SetConfig+0x20>
8003dcc: 4a13 ldr r2, [pc, #76] @ (8003e1c <TIM_Base_SetConfig+0x80>)
8003dce: 4290 cmp r0, r2
8003dd0: d0f4 beq.n 8003dbc <TIM_Base_SetConfig+0x20>
8003dd2: 4a13 ldr r2, [pc, #76] @ (8003e20 <TIM_Base_SetConfig+0x84>)
8003dd4: 4290 cmp r0, r2
8003dd6: d0f1 beq.n 8003dbc <TIM_Base_SetConfig+0x20>
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8003dd8: 2280 movs r2, #128 @ 0x80
8003dda: 4393 bics r3, r2
8003ddc: 694a ldr r2, [r1, #20]
8003dde: 4313 orrs r3, r2
TIMx->ARR = (uint32_t)Structure->Period ;
8003de0: 688a ldr r2, [r1, #8]
8003de2: 62c2 str r2, [r0, #44] @ 0x2c
TIMx->PSC = Structure->Prescaler;
8003de4: 680a ldr r2, [r1, #0]
8003de6: 6282 str r2, [r0, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8003de8: 42a0 cmp r0, r4
8003dea: d005 beq.n 8003df8 <TIM_Base_SetConfig+0x5c>
8003dec: 4a0b ldr r2, [pc, #44] @ (8003e1c <TIM_Base_SetConfig+0x80>)
8003dee: 4290 cmp r0, r2
8003df0: d002 beq.n 8003df8 <TIM_Base_SetConfig+0x5c>
8003df2: 4a0b ldr r2, [pc, #44] @ (8003e20 <TIM_Base_SetConfig+0x84>)
8003df4: 4290 cmp r0, r2
8003df6: d101 bne.n 8003dfc <TIM_Base_SetConfig+0x60>
TIMx->RCR = Structure->RepetitionCounter;
8003df8: 690a ldr r2, [r1, #16]
8003dfa: 6302 str r2, [r0, #48] @ 0x30
SET_BIT(TIMx->CR1, TIM_CR1_URS);
8003dfc: 2204 movs r2, #4
8003dfe: 6801 ldr r1, [r0, #0]
8003e00: 430a orrs r2, r1
8003e02: 6002 str r2, [r0, #0]
TIMx->EGR = TIM_EGR_UG;
8003e04: 2201 movs r2, #1
8003e06: 6142 str r2, [r0, #20]
TIMx->CR1 = tmpcr1;
8003e08: 6003 str r3, [r0, #0]
}
8003e0a: bd10 pop {r4, pc}
8003e0c: 40012c00 .word 0x40012c00
8003e10: 40000400 .word 0x40000400
8003e14: fffffcff .word 0xfffffcff
8003e18: 40002000 .word 0x40002000
8003e1c: 40014400 .word 0x40014400
8003e20: 40014800 .word 0x40014800
08003e24 <HAL_TIM_Base_Init>:
{
8003e24: b570 push {r4, r5, r6, lr}
8003e26: 0004 movs r4, r0
return HAL_ERROR;
8003e28: 2001 movs r0, #1
if (htim == NULL)
8003e2a: 2c00 cmp r4, #0
8003e2c: d023 beq.n 8003e76 <HAL_TIM_Base_Init+0x52>
if (htim->State == HAL_TIM_STATE_RESET)
8003e2e: 0025 movs r5, r4
8003e30: 353d adds r5, #61 @ 0x3d
8003e32: 782b ldrb r3, [r5, #0]
8003e34: b2da uxtb r2, r3
8003e36: 2b00 cmp r3, #0
8003e38: d105 bne.n 8003e46 <HAL_TIM_Base_Init+0x22>
htim->Lock = HAL_UNLOCKED;
8003e3a: 0023 movs r3, r4
8003e3c: 333c adds r3, #60 @ 0x3c
HAL_TIM_Base_MspInit(htim);
8003e3e: 0020 movs r0, r4
htim->Lock = HAL_UNLOCKED;
8003e40: 701a strb r2, [r3, #0]
HAL_TIM_Base_MspInit(htim);
8003e42: f7fe fb37 bl 80024b4 <HAL_TIM_Base_MspInit>
htim->State = HAL_TIM_STATE_BUSY;
8003e46: 2302 movs r3, #2
8003e48: 702b strb r3, [r5, #0]
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8003e4a: 6820 ldr r0, [r4, #0]
8003e4c: 1d21 adds r1, r4, #4
8003e4e: f7ff ffa5 bl 8003d9c <TIM_Base_SetConfig>
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8003e52: 0022 movs r2, r4
8003e54: 2301 movs r3, #1
return HAL_OK;
8003e56: 2000 movs r0, #0
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8003e58: 3248 adds r2, #72 @ 0x48
8003e5a: 7013 strb r3, [r2, #0]
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003e5c: 3447 adds r4, #71 @ 0x47
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003e5e: 3a0a subs r2, #10
8003e60: 7013 strb r3, [r2, #0]
8003e62: 7053 strb r3, [r2, #1]
8003e64: 7093 strb r3, [r2, #2]
8003e66: 70d3 strb r3, [r2, #3]
8003e68: 7113 strb r3, [r2, #4]
8003e6a: 7153 strb r3, [r2, #5]
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003e6c: 7193 strb r3, [r2, #6]
8003e6e: 71d3 strb r3, [r2, #7]
8003e70: 7213 strb r3, [r2, #8]
8003e72: 7023 strb r3, [r4, #0]
htim->State = HAL_TIM_STATE_READY;
8003e74: 702b strb r3, [r5, #0]
}
8003e76: bd70 pop {r4, r5, r6, pc}
08003e78 <HAL_TIM_PWM_Init>:
{
8003e78: b570 push {r4, r5, r6, lr}
8003e7a: 0004 movs r4, r0
return HAL_ERROR;
8003e7c: 2001 movs r0, #1
if (htim == NULL)
8003e7e: 2c00 cmp r4, #0
8003e80: d023 beq.n 8003eca <HAL_TIM_PWM_Init+0x52>
if (htim->State == HAL_TIM_STATE_RESET)
8003e82: 0025 movs r5, r4
8003e84: 353d adds r5, #61 @ 0x3d
8003e86: 782b ldrb r3, [r5, #0]
8003e88: b2da uxtb r2, r3
8003e8a: 2b00 cmp r3, #0
8003e8c: d105 bne.n 8003e9a <HAL_TIM_PWM_Init+0x22>
htim->Lock = HAL_UNLOCKED;
8003e8e: 0023 movs r3, r4
8003e90: 333c adds r3, #60 @ 0x3c
HAL_TIM_PWM_MspInit(htim);
8003e92: 0020 movs r0, r4
htim->Lock = HAL_UNLOCKED;
8003e94: 701a strb r2, [r3, #0]
HAL_TIM_PWM_MspInit(htim);
8003e96: f7ff fe77 bl 8003b88 <HAL_TIM_PWM_MspInit>
htim->State = HAL_TIM_STATE_BUSY;
8003e9a: 2302 movs r3, #2
8003e9c: 702b strb r3, [r5, #0]
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8003e9e: 6820 ldr r0, [r4, #0]
8003ea0: 1d21 adds r1, r4, #4
8003ea2: f7ff ff7b bl 8003d9c <TIM_Base_SetConfig>
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8003ea6: 0022 movs r2, r4
8003ea8: 2301 movs r3, #1
return HAL_OK;
8003eaa: 2000 movs r0, #0
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8003eac: 3248 adds r2, #72 @ 0x48
8003eae: 7013 strb r3, [r2, #0]
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003eb0: 3447 adds r4, #71 @ 0x47
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003eb2: 3a0a subs r2, #10
8003eb4: 7013 strb r3, [r2, #0]
8003eb6: 7053 strb r3, [r2, #1]
8003eb8: 7093 strb r3, [r2, #2]
8003eba: 70d3 strb r3, [r2, #3]
8003ebc: 7113 strb r3, [r2, #4]
8003ebe: 7153 strb r3, [r2, #5]
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8003ec0: 7193 strb r3, [r2, #6]
8003ec2: 71d3 strb r3, [r2, #7]
8003ec4: 7213 strb r3, [r2, #8]
8003ec6: 7023 strb r3, [r4, #0]
htim->State = HAL_TIM_STATE_READY;
8003ec8: 702b strb r3, [r5, #0]
}
8003eca: bd70 pop {r4, r5, r6, pc}
08003ecc <HAL_TIM_Encoder_Init>:
{
8003ecc: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8003ece: 0004 movs r4, r0
8003ed0: 000d movs r5, r1
return HAL_ERROR;
8003ed2: 2001 movs r0, #1
if (htim == NULL)
8003ed4: 2c00 cmp r4, #0
8003ed6: d047 beq.n 8003f68 <HAL_TIM_Encoder_Init+0x9c>
if (htim->State == HAL_TIM_STATE_RESET)
8003ed8: 0026 movs r6, r4
8003eda: 363d adds r6, #61 @ 0x3d
8003edc: 7833 ldrb r3, [r6, #0]
8003ede: b2da uxtb r2, r3
8003ee0: 2b00 cmp r3, #0
8003ee2: d105 bne.n 8003ef0 <HAL_TIM_Encoder_Init+0x24>
htim->Lock = HAL_UNLOCKED;
8003ee4: 0023 movs r3, r4
8003ee6: 333c adds r3, #60 @ 0x3c
HAL_TIM_Encoder_MspInit(htim);
8003ee8: 0020 movs r0, r4
htim->Lock = HAL_UNLOCKED;
8003eea: 701a strb r2, [r3, #0]
HAL_TIM_Encoder_MspInit(htim);
8003eec: f7fe fb3c bl 8002568 <HAL_TIM_Encoder_MspInit>
htim->State = HAL_TIM_STATE_BUSY;
8003ef0: 2302 movs r3, #2
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
8003ef2: 0021 movs r1, r4
htim->State = HAL_TIM_STATE_BUSY;
8003ef4: 7033 strb r3, [r6, #0]
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
8003ef6: c980 ldmia r1!, {r7}
8003ef8: 4a1c ldr r2, [pc, #112] @ (8003f6c <HAL_TIM_Encoder_Init+0xa0>)
8003efa: 68bb ldr r3, [r7, #8]
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8003efc: 0038 movs r0, r7
htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
8003efe: 4013 ands r3, r2
8003f00: 60bb str r3, [r7, #8]
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8003f02: f7ff ff4b bl 8003d9c <TIM_Base_SetConfig>
tmpsmcr = htim->Instance->SMCR;
8003f06: 68b9 ldr r1, [r7, #8]
tmpsmcr |= sConfig->EncoderMode;
8003f08: 682a ldr r2, [r5, #0]
tmpccmr1 = htim->Instance->CCMR1;
8003f0a: 69bb ldr r3, [r7, #24]
tmpsmcr |= sConfig->EncoderMode;
8003f0c: 4311 orrs r1, r2
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
8003f0e: 4a18 ldr r2, [pc, #96] @ (8003f70 <HAL_TIM_Encoder_Init+0xa4>)
tmpsmcr |= sConfig->EncoderMode;
8003f10: 9101 str r1, [sp, #4]
tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
8003f12: 4013 ands r3, r2
tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
8003f14: 69aa ldr r2, [r5, #24]
8003f16: 68a9 ldr r1, [r5, #8]
8003f18: 0212 lsls r2, r2, #8
8003f1a: 430a orrs r2, r1
8003f1c: 431a orrs r2, r3
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
8003f1e: 4b15 ldr r3, [pc, #84] @ (8003f74 <HAL_TIM_Encoder_Init+0xa8>)
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
8003f20: 6929 ldr r1, [r5, #16]
tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
8003f22: 401a ands r2, r3
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
8003f24: 69eb ldr r3, [r5, #28]
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
8003f26: 0109 lsls r1, r1, #4
tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
8003f28: 021b lsls r3, r3, #8
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
8003f2a: 430b orrs r3, r1
8003f2c: 68e9 ldr r1, [r5, #12]
tmpccer = htim->Instance->CCER;
8003f2e: 6a38 ldr r0, [r7, #32]
tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
8003f30: 430b orrs r3, r1
8003f32: 6a29 ldr r1, [r5, #32]
8003f34: 0309 lsls r1, r1, #12
8003f36: 430b orrs r3, r1
8003f38: 4313 orrs r3, r2
tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
8003f3a: 22aa movs r2, #170 @ 0xaa
8003f3c: 4390 bics r0, r2
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
8003f3e: 696a ldr r2, [r5, #20]
8003f40: 686d ldr r5, [r5, #4]
8003f42: 0112 lsls r2, r2, #4
htim->Instance->SMCR = tmpsmcr;
8003f44: 9901 ldr r1, [sp, #4]
tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
8003f46: 432a orrs r2, r5
8003f48: 4302 orrs r2, r0
htim->Instance->SMCR = tmpsmcr;
8003f4a: 60b9 str r1, [r7, #8]
htim->Instance->CCMR1 = tmpccmr1;
8003f4c: 61bb str r3, [r7, #24]
htim->Instance->CCER = tmpccer;
8003f4e: 623a str r2, [r7, #32]
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8003f50: 0022 movs r2, r4
8003f52: 2301 movs r3, #1
return HAL_OK;
8003f54: 2000 movs r0, #0
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8003f56: 3248 adds r2, #72 @ 0x48
8003f58: 7013 strb r3, [r2, #0]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
8003f5a: 3445 adds r4, #69 @ 0x45
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
8003f5c: 3a0a subs r2, #10
8003f5e: 7013 strb r3, [r2, #0]
TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
8003f60: 7053 strb r3, [r2, #1]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
8003f62: 7193 strb r3, [r2, #6]
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
8003f64: 7023 strb r3, [r4, #0]
htim->State = HAL_TIM_STATE_READY;
8003f66: 7033 strb r3, [r6, #0]
}
8003f68: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
8003f6a: 46c0 nop @ (mov r8, r8)
8003f6c: fffebff8 .word 0xfffebff8
8003f70: fffffcfc .word 0xfffffcfc
8003f74: ffff0303 .word 0xffff0303
08003f78 <TIM_OC2_SetConfig>:
TIMx->CCER &= ~TIM_CCER_CC2E;
8003f78: 2210 movs r2, #16
{
8003f7a: b570 push {r4, r5, r6, lr}
tmpccer = TIMx->CCER;
8003f7c: 6a05 ldr r5, [r0, #32]
TIMx->CCER &= ~TIM_CCER_CC2E;
8003f7e: 6a03 ldr r3, [r0, #32]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8003f80: 4c16 ldr r4, [pc, #88] @ (8003fdc <TIM_OC2_SetConfig+0x64>)
TIMx->CCER &= ~TIM_CCER_CC2E;
8003f82: 4393 bics r3, r2
8003f84: 6203 str r3, [r0, #32]
tmpcr2 = TIMx->CR2;
8003f86: 6842 ldr r2, [r0, #4]
tmpccmrx = TIMx->CCMR1;
8003f88: 6983 ldr r3, [r0, #24]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8003f8a: 4023 ands r3, r4
tmpccmrx |= (OC_Config->OCMode << 8U);
8003f8c: 680c ldr r4, [r1, #0]
8003f8e: 0224 lsls r4, r4, #8
8003f90: 431c orrs r4, r3
tmpccer &= ~TIM_CCER_CC2P;
8003f92: 2320 movs r3, #32
8003f94: 439d bics r5, r3
tmpccer |= (OC_Config->OCPolarity << 4U);
8003f96: 688b ldr r3, [r1, #8]
8003f98: 011b lsls r3, r3, #4
8003f9a: 432b orrs r3, r5
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
8003f9c: 4d10 ldr r5, [pc, #64] @ (8003fe0 <TIM_OC2_SetConfig+0x68>)
8003f9e: 42a8 cmp r0, r5
8003fa0: d10f bne.n 8003fc2 <TIM_OC2_SetConfig+0x4a>
tmpccer &= ~TIM_CCER_CC2NP;
8003fa2: 2580 movs r5, #128 @ 0x80
8003fa4: 43ab bics r3, r5
8003fa6: 001e movs r6, r3
tmpccer |= (OC_Config->OCNPolarity << 4U);
8003fa8: 68cb ldr r3, [r1, #12]
tmpccer &= ~TIM_CCER_CC2NE;
8003faa: 3d40 subs r5, #64 @ 0x40
tmpccer |= (OC_Config->OCNPolarity << 4U);
8003fac: 011b lsls r3, r3, #4
8003fae: 4333 orrs r3, r6
tmpccer &= ~TIM_CCER_CC2NE;
8003fb0: 43ab bics r3, r5
tmpcr2 &= ~TIM_CR2_OIS2N;
8003fb2: 4d0c ldr r5, [pc, #48] @ (8003fe4 <TIM_OC2_SetConfig+0x6c>)
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8003fb4: 698e ldr r6, [r1, #24]
tmpcr2 &= ~TIM_CR2_OIS2N;
8003fb6: 4015 ands r5, r2
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
8003fb8: 694a ldr r2, [r1, #20]
8003fba: 4332 orrs r2, r6
8003fbc: 0092 lsls r2, r2, #2
8003fbe: 432a orrs r2, r5
8003fc0: e005 b.n 8003fce <TIM_OC2_SetConfig+0x56>
if (IS_TIM_BREAK_INSTANCE(TIMx))
8003fc2: 4d09 ldr r5, [pc, #36] @ (8003fe8 <TIM_OC2_SetConfig+0x70>)
8003fc4: 42a8 cmp r0, r5
8003fc6: d0f4 beq.n 8003fb2 <TIM_OC2_SetConfig+0x3a>
8003fc8: 4d08 ldr r5, [pc, #32] @ (8003fec <TIM_OC2_SetConfig+0x74>)
8003fca: 42a8 cmp r0, r5
8003fcc: d0f1 beq.n 8003fb2 <TIM_OC2_SetConfig+0x3a>
TIMx->CR2 = tmpcr2;
8003fce: 6042 str r2, [r0, #4]
TIMx->CCR2 = OC_Config->Pulse;
8003fd0: 684a ldr r2, [r1, #4]
TIMx->CCMR1 = tmpccmrx;
8003fd2: 6184 str r4, [r0, #24]
TIMx->CCR2 = OC_Config->Pulse;
8003fd4: 6382 str r2, [r0, #56] @ 0x38
TIMx->CCER = tmpccer;
8003fd6: 6203 str r3, [r0, #32]
}
8003fd8: bd70 pop {r4, r5, r6, pc}
8003fda: 46c0 nop @ (mov r8, r8)
8003fdc: feff8cff .word 0xfeff8cff
8003fe0: 40012c00 .word 0x40012c00
8003fe4: fffff3ff .word 0xfffff3ff
8003fe8: 40014400 .word 0x40014400
8003fec: 40014800 .word 0x40014800
08003ff0 <HAL_TIM_PWM_ConfigChannel>:
{
8003ff0: b5f8 push {r3, r4, r5, r6, r7, lr}
__HAL_LOCK(htim);
8003ff2: 0007 movs r7, r0
8003ff4: 373c adds r7, #60 @ 0x3c
{
8003ff6: 0015 movs r5, r2
__HAL_LOCK(htim);
8003ff8: 783a ldrb r2, [r7, #0]
{
8003ffa: 0003 movs r3, r0
8003ffc: 000c movs r4, r1
__HAL_LOCK(htim);
8003ffe: 2002 movs r0, #2
8004000: 2a01 cmp r2, #1
8004002: d00c beq.n 800401e <HAL_TIM_PWM_ConfigChannel+0x2e>
8004004: 3801 subs r0, #1
8004006: 7038 strb r0, [r7, #0]
switch (Channel)
8004008: 2d0c cmp r5, #12
800400a: d051 beq.n 80040b0 <HAL_TIM_PWM_ConfigChannel+0xc0>
800400c: d808 bhi.n 8004020 <HAL_TIM_PWM_ConfigChannel+0x30>
800400e: 2d04 cmp r5, #4
8004010: d02d beq.n 800406e <HAL_TIM_PWM_ConfigChannel+0x7e>
8004012: 2d08 cmp r5, #8
8004014: d03c beq.n 8004090 <HAL_TIM_PWM_ConfigChannel+0xa0>
8004016: 2d00 cmp r5, #0
8004018: d017 beq.n 800404a <HAL_TIM_PWM_ConfigChannel+0x5a>
__HAL_UNLOCK(htim);
800401a: 2300 movs r3, #0
800401c: 703b strb r3, [r7, #0]
}
800401e: bdf8 pop {r3, r4, r5, r6, r7, pc}
switch (Channel)
8004020: 2d10 cmp r5, #16
8004022: d058 beq.n 80040d6 <HAL_TIM_PWM_ConfigChannel+0xe6>
8004024: 2d14 cmp r5, #20
8004026: d1f8 bne.n 800401a <HAL_TIM_PWM_ConfigChannel+0x2a>
TIM_OC6_SetConfig(htim->Instance, sConfig);
8004028: 681d ldr r5, [r3, #0]
800402a: 0028 movs r0, r5
800402c: f7ff fd32 bl 8003a94 <TIM_OC6_SetConfig>
htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
8004030: 2380 movs r3, #128 @ 0x80
8004032: 6d6a ldr r2, [r5, #84] @ 0x54
8004034: 011b lsls r3, r3, #4
8004036: 4313 orrs r3, r2
8004038: 656b str r3, [r5, #84] @ 0x54
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
800403a: 6d6b ldr r3, [r5, #84] @ 0x54
800403c: 4a2e ldr r2, [pc, #184] @ (80040f8 <HAL_TIM_PWM_ConfigChannel+0x108>)
800403e: 4013 ands r3, r2
8004040: 656b str r3, [r5, #84] @ 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
8004042: 6923 ldr r3, [r4, #16]
8004044: 6d6a ldr r2, [r5, #84] @ 0x54
8004046: 021b lsls r3, r3, #8
8004048: e053 b.n 80040f2 <HAL_TIM_PWM_ConfigChannel+0x102>
TIM_OC1_SetConfig(htim->Instance, sConfig);
800404a: 681d ldr r5, [r3, #0]
800404c: 0028 movs r0, r5
800404e: f7ff fc45 bl 80038dc <TIM_OC1_SetConfig>
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
8004052: 2308 movs r3, #8
8004054: 69aa ldr r2, [r5, #24]
8004056: 4313 orrs r3, r2
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
8004058: 2204 movs r2, #4
htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
800405a: 61ab str r3, [r5, #24]
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
800405c: 69ab ldr r3, [r5, #24]
800405e: 4393 bics r3, r2
8004060: 61ab str r3, [r5, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode;
8004062: 69ab ldr r3, [r5, #24]
8004064: 6922 ldr r2, [r4, #16]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8004066: 4313 orrs r3, r2
8004068: 61ab str r3, [r5, #24]
HAL_StatusTypeDef status = HAL_OK;
800406a: 2000 movs r0, #0
800406c: e7d5 b.n 800401a <HAL_TIM_PWM_ConfigChannel+0x2a>
TIM_OC2_SetConfig(htim->Instance, sConfig);
800406e: 681d ldr r5, [r3, #0]
8004070: 0028 movs r0, r5
8004072: f7ff ff81 bl 8003f78 <TIM_OC2_SetConfig>
htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
8004076: 2380 movs r3, #128 @ 0x80
8004078: 69aa ldr r2, [r5, #24]
800407a: 011b lsls r3, r3, #4
800407c: 4313 orrs r3, r2
800407e: 61ab str r3, [r5, #24]
htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
8004080: 69ab ldr r3, [r5, #24]
8004082: 4a1d ldr r2, [pc, #116] @ (80040f8 <HAL_TIM_PWM_ConfigChannel+0x108>)
8004084: 4013 ands r3, r2
8004086: 61ab str r3, [r5, #24]
htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
8004088: 6923 ldr r3, [r4, #16]
800408a: 69aa ldr r2, [r5, #24]
800408c: 021b lsls r3, r3, #8
800408e: e7ea b.n 8004066 <HAL_TIM_PWM_ConfigChannel+0x76>
TIM_OC3_SetConfig(htim->Instance, sConfig);
8004090: 681e ldr r6, [r3, #0]
8004092: 0030 movs r0, r6
8004094: f7ff fc58 bl 8003948 <TIM_OC3_SetConfig>
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
8004098: 2204 movs r2, #4
htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
800409a: 69f3 ldr r3, [r6, #28]
800409c: 431d orrs r5, r3
800409e: 61f5 str r5, [r6, #28]
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
80040a0: 69f3 ldr r3, [r6, #28]
80040a2: 4393 bics r3, r2
80040a4: 61f3 str r3, [r6, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode;
80040a6: 69f3 ldr r3, [r6, #28]
80040a8: 6922 ldr r2, [r4, #16]
80040aa: 4313 orrs r3, r2
80040ac: 61f3 str r3, [r6, #28]
break;
80040ae: e7dc b.n 800406a <HAL_TIM_PWM_ConfigChannel+0x7a>
TIM_OC4_SetConfig(htim->Instance, sConfig);
80040b0: 681d ldr r5, [r3, #0]
80040b2: 0028 movs r0, r5
80040b4: f7ff fc8a bl 80039cc <TIM_OC4_SetConfig>
htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
80040b8: 2380 movs r3, #128 @ 0x80
80040ba: 69ea ldr r2, [r5, #28]
80040bc: 011b lsls r3, r3, #4
80040be: 4313 orrs r3, r2
80040c0: 61eb str r3, [r5, #28]
htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
80040c2: 69eb ldr r3, [r5, #28]
80040c4: 4a0c ldr r2, [pc, #48] @ (80040f8 <HAL_TIM_PWM_ConfigChannel+0x108>)
80040c6: 4013 ands r3, r2
80040c8: 61eb str r3, [r5, #28]
htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
80040ca: 6923 ldr r3, [r4, #16]
80040cc: 69ea ldr r2, [r5, #28]
80040ce: 021b lsls r3, r3, #8
80040d0: 4313 orrs r3, r2
80040d2: 61eb str r3, [r5, #28]
break;
80040d4: e7c9 b.n 800406a <HAL_TIM_PWM_ConfigChannel+0x7a>
TIM_OC5_SetConfig(htim->Instance, sConfig);
80040d6: 681d ldr r5, [r3, #0]
80040d8: 0028 movs r0, r5
80040da: f7ff fcab bl 8003a34 <TIM_OC5_SetConfig>
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
80040de: 2308 movs r3, #8
80040e0: 6d6a ldr r2, [r5, #84] @ 0x54
80040e2: 4313 orrs r3, r2
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
80040e4: 2204 movs r2, #4
htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
80040e6: 656b str r3, [r5, #84] @ 0x54
htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
80040e8: 6d6b ldr r3, [r5, #84] @ 0x54
80040ea: 4393 bics r3, r2
80040ec: 656b str r3, [r5, #84] @ 0x54
htim->Instance->CCMR3 |= sConfig->OCFastMode;
80040ee: 6d6b ldr r3, [r5, #84] @ 0x54
80040f0: 6922 ldr r2, [r4, #16]
htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
80040f2: 4313 orrs r3, r2
80040f4: 656b str r3, [r5, #84] @ 0x54
break;
80040f6: e7b8 b.n 800406a <HAL_TIM_PWM_ConfigChannel+0x7a>
80040f8: fffffbff .word 0xfffffbff
080040fc <TIM_ETR_SetConfig>:
{
80040fc: b530 push {r4, r5, lr}
tmpsmcr = TIMx->SMCR;
80040fe: 6884 ldr r4, [r0, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8004100: 4d03 ldr r5, [pc, #12] @ (8004110 <TIM_ETR_SetConfig+0x14>)
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8004102: 430a orrs r2, r1
8004104: 021b lsls r3, r3, #8
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8004106: 402c ands r4, r5
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8004108: 4313 orrs r3, r2
800410a: 4323 orrs r3, r4
TIMx->SMCR = tmpsmcr;
800410c: 6083 str r3, [r0, #8]
}
800410e: bd30 pop {r4, r5, pc}
8004110: ffff00ff .word 0xffff00ff
08004114 <HAL_TIM_ConfigClockSource>:
{
8004114: b5f8 push {r3, r4, r5, r6, r7, lr}
__HAL_LOCK(htim);
8004116: 0005 movs r5, r0
8004118: 2202 movs r2, #2
800411a: 353c adds r5, #60 @ 0x3c
800411c: 782c ldrb r4, [r5, #0]
{
800411e: 0003 movs r3, r0
__HAL_LOCK(htim);
8004120: 0010 movs r0, r2
8004122: 2c01 cmp r4, #1
8004124: d01b beq.n 800415e <HAL_TIM_ConfigClockSource+0x4a>
htim->State = HAL_TIM_STATE_BUSY;
8004126: 001e movs r6, r3
__HAL_LOCK(htim);
8004128: 3801 subs r0, #1
htim->State = HAL_TIM_STATE_BUSY;
800412a: 363d adds r6, #61 @ 0x3d
__HAL_LOCK(htim);
800412c: 7028 strb r0, [r5, #0]
htim->State = HAL_TIM_STATE_BUSY;
800412e: 7032 strb r2, [r6, #0]
tmpsmcr = htim->Instance->SMCR;
8004130: 681c ldr r4, [r3, #0]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8004132: 4a41 ldr r2, [pc, #260] @ (8004238 <HAL_TIM_ConfigClockSource+0x124>)
tmpsmcr = htim->Instance->SMCR;
8004134: 68a3 ldr r3, [r4, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8004136: 4013 ands r3, r2
htim->Instance->SMCR = tmpsmcr;
8004138: 60a3 str r3, [r4, #8]
switch (sClockSourceConfig->ClockSource)
800413a: 680b ldr r3, [r1, #0]
800413c: 2b60 cmp r3, #96 @ 0x60
800413e: d04e beq.n 80041de <HAL_TIM_ConfigClockSource+0xca>
8004140: d82d bhi.n 800419e <HAL_TIM_ConfigClockSource+0x8a>
8004142: 2b40 cmp r3, #64 @ 0x40
8004144: d062 beq.n 800420c <HAL_TIM_ConfigClockSource+0xf8>
8004146: d813 bhi.n 8004170 <HAL_TIM_ConfigClockSource+0x5c>
8004148: 2b20 cmp r3, #32
800414a: d00b beq.n 8004164 <HAL_TIM_ConfigClockSource+0x50>
800414c: d808 bhi.n 8004160 <HAL_TIM_ConfigClockSource+0x4c>
800414e: 2210 movs r2, #16
8004150: 0019 movs r1, r3
8004152: 4391 bics r1, r2
8004154: d006 beq.n 8004164 <HAL_TIM_ConfigClockSource+0x50>
htim->State = HAL_TIM_STATE_READY;
8004156: 2301 movs r3, #1
8004158: 7033 strb r3, [r6, #0]
__HAL_UNLOCK(htim);
800415a: 2300 movs r3, #0
800415c: 702b strb r3, [r5, #0]
}
800415e: bdf8 pop {r3, r4, r5, r6, r7, pc}
switch (sClockSourceConfig->ClockSource)
8004160: 2b30 cmp r3, #48 @ 0x30
8004162: d1f8 bne.n 8004156 <HAL_TIM_ConfigClockSource+0x42>
tmpsmcr = TIMx->SMCR;
8004164: 68a2 ldr r2, [r4, #8]
tmpsmcr &= ~TIM_SMCR_TS;
8004166: 4935 ldr r1, [pc, #212] @ (800423c <HAL_TIM_ConfigClockSource+0x128>)
8004168: 400a ands r2, r1
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
800416a: 4313 orrs r3, r2
800416c: 2207 movs r2, #7
800416e: e028 b.n 80041c2 <HAL_TIM_ConfigClockSource+0xae>
switch (sClockSourceConfig->ClockSource)
8004170: 2b50 cmp r3, #80 @ 0x50
8004172: d1f0 bne.n 8004156 <HAL_TIM_ConfigClockSource+0x42>
sClockSourceConfig->ClockPolarity,
8004174: 684a ldr r2, [r1, #4]
sClockSourceConfig->ClockFilter);
8004176: 68cb ldr r3, [r1, #12]
tmpccer = TIMx->CCER;
8004178: 6a21 ldr r1, [r4, #32]
TIMx->CCER &= ~TIM_CCER_CC1E;
800417a: 6a27 ldr r7, [r4, #32]
tmpccmr1 |= (TIM_ICFilter << 4U);
800417c: 011b lsls r3, r3, #4
TIMx->CCER &= ~TIM_CCER_CC1E;
800417e: 4387 bics r7, r0
8004180: 6227 str r7, [r4, #32]
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8004182: 27f0 movs r7, #240 @ 0xf0
tmpccmr1 = TIMx->CCMR1;
8004184: 69a0 ldr r0, [r4, #24]
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8004186: 43b8 bics r0, r7
tmpccmr1 |= (TIM_ICFilter << 4U);
8004188: 4303 orrs r3, r0
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
800418a: 200a movs r0, #10
800418c: 4381 bics r1, r0
tmpccer |= TIM_ICPolarity;
800418e: 430a orrs r2, r1
TIMx->CCMR1 = tmpccmr1;
8004190: 61a3 str r3, [r4, #24]
TIMx->CCER = tmpccer;
8004192: 6222 str r2, [r4, #32]
tmpsmcr &= ~TIM_SMCR_TS;
8004194: 4b29 ldr r3, [pc, #164] @ (800423c <HAL_TIM_ConfigClockSource+0x128>)
tmpsmcr = TIMx->SMCR;
8004196: 68a2 ldr r2, [r4, #8]
tmpsmcr &= ~TIM_SMCR_TS;
8004198: 401a ands r2, r3
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
800419a: 2357 movs r3, #87 @ 0x57
800419c: e011 b.n 80041c2 <HAL_TIM_ConfigClockSource+0xae>
switch (sClockSourceConfig->ClockSource)
800419e: 2280 movs r2, #128 @ 0x80
80041a0: 0152 lsls r2, r2, #5
80041a2: 4293 cmp r3, r2
80041a4: d00f beq.n 80041c6 <HAL_TIM_ConfigClockSource+0xb2>
80041a6: 2280 movs r2, #128 @ 0x80
80041a8: 0192 lsls r2, r2, #6
80041aa: 4293 cmp r3, r2
80041ac: d00d beq.n 80041ca <HAL_TIM_ConfigClockSource+0xb6>
80041ae: 2b70 cmp r3, #112 @ 0x70
80041b0: d1d1 bne.n 8004156 <HAL_TIM_ConfigClockSource+0x42>
TIM_ETR_SetConfig(htim->Instance,
80041b2: 68cb ldr r3, [r1, #12]
80041b4: 684a ldr r2, [r1, #4]
80041b6: 0020 movs r0, r4
80041b8: 6889 ldr r1, [r1, #8]
80041ba: f7ff ff9f bl 80040fc <TIM_ETR_SetConfig>
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
80041be: 2377 movs r3, #119 @ 0x77
tmpsmcr = htim->Instance->SMCR;
80041c0: 68a2 ldr r2, [r4, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
80041c2: 4313 orrs r3, r2
htim->Instance->SMCR = tmpsmcr;
80041c4: 60a3 str r3, [r4, #8]
HAL_StatusTypeDef status = HAL_OK;
80041c6: 2000 movs r0, #0
80041c8: e7c5 b.n 8004156 <HAL_TIM_ConfigClockSource+0x42>
TIM_ETR_SetConfig(htim->Instance,
80041ca: 68cb ldr r3, [r1, #12]
80041cc: 684a ldr r2, [r1, #4]
80041ce: 0020 movs r0, r4
80041d0: 6889 ldr r1, [r1, #8]
80041d2: f7ff ff93 bl 80040fc <TIM_ETR_SetConfig>
htim->Instance->SMCR |= TIM_SMCR_ECE;
80041d6: 2380 movs r3, #128 @ 0x80
80041d8: 68a2 ldr r2, [r4, #8]
80041da: 01db lsls r3, r3, #7
80041dc: e7f1 b.n 80041c2 <HAL_TIM_ConfigClockSource+0xae>
TIMx->CCER &= ~TIM_CCER_CC2E;
80041de: 2710 movs r7, #16
sClockSourceConfig->ClockPolarity,
80041e0: 684b ldr r3, [r1, #4]
sClockSourceConfig->ClockFilter);
80041e2: 68ca ldr r2, [r1, #12]
tmpccer = TIMx->CCER;
80041e4: 6a21 ldr r1, [r4, #32]
TIMx->CCER &= ~TIM_CCER_CC2E;
80041e6: 6a20 ldr r0, [r4, #32]
tmpccmr1 |= (TIM_ICFilter << 12U);
80041e8: 0312 lsls r2, r2, #12
TIMx->CCER &= ~TIM_CCER_CC2E;
80041ea: 43b8 bics r0, r7
80041ec: 6220 str r0, [r4, #32]
tmpccmr1 = TIMx->CCMR1;
80041ee: 69a0 ldr r0, [r4, #24]
tmpccmr1 &= ~TIM_CCMR1_IC2F;
80041f0: 4f13 ldr r7, [pc, #76] @ (8004240 <HAL_TIM_ConfigClockSource+0x12c>)
tmpccer |= (TIM_ICPolarity << 4U);
80041f2: 011b lsls r3, r3, #4
tmpccmr1 &= ~TIM_CCMR1_IC2F;
80041f4: 4038 ands r0, r7
tmpccmr1 |= (TIM_ICFilter << 12U);
80041f6: 4302 orrs r2, r0
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
80041f8: 20a0 movs r0, #160 @ 0xa0
80041fa: 4381 bics r1, r0
tmpccer |= (TIM_ICPolarity << 4U);
80041fc: 430b orrs r3, r1
TIMx->CCMR1 = tmpccmr1 ;
80041fe: 61a2 str r2, [r4, #24]
TIMx->CCER = tmpccer;
8004200: 6223 str r3, [r4, #32]
tmpsmcr = TIMx->SMCR;
8004202: 68a2 ldr r2, [r4, #8]
tmpsmcr &= ~TIM_SMCR_TS;
8004204: 4b0d ldr r3, [pc, #52] @ (800423c <HAL_TIM_ConfigClockSource+0x128>)
8004206: 401a ands r2, r3
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8004208: 2367 movs r3, #103 @ 0x67
800420a: e7da b.n 80041c2 <HAL_TIM_ConfigClockSource+0xae>
sClockSourceConfig->ClockPolarity,
800420c: 684a ldr r2, [r1, #4]
sClockSourceConfig->ClockFilter);
800420e: 68cb ldr r3, [r1, #12]
tmpccer = TIMx->CCER;
8004210: 6a21 ldr r1, [r4, #32]
TIMx->CCER &= ~TIM_CCER_CC1E;
8004212: 6a27 ldr r7, [r4, #32]
tmpccmr1 |= (TIM_ICFilter << 4U);
8004214: 011b lsls r3, r3, #4
TIMx->CCER &= ~TIM_CCER_CC1E;
8004216: 4387 bics r7, r0
8004218: 6227 str r7, [r4, #32]
tmpccmr1 &= ~TIM_CCMR1_IC1F;
800421a: 27f0 movs r7, #240 @ 0xf0
tmpccmr1 = TIMx->CCMR1;
800421c: 69a0 ldr r0, [r4, #24]
tmpccmr1 &= ~TIM_CCMR1_IC1F;
800421e: 43b8 bics r0, r7
tmpccmr1 |= (TIM_ICFilter << 4U);
8004220: 4303 orrs r3, r0
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8004222: 200a movs r0, #10
8004224: 4381 bics r1, r0
tmpccer |= TIM_ICPolarity;
8004226: 430a orrs r2, r1
TIMx->CCMR1 = tmpccmr1;
8004228: 61a3 str r3, [r4, #24]
TIMx->CCER = tmpccer;
800422a: 6222 str r2, [r4, #32]
tmpsmcr &= ~TIM_SMCR_TS;
800422c: 4b03 ldr r3, [pc, #12] @ (800423c <HAL_TIM_ConfigClockSource+0x128>)
tmpsmcr = TIMx->SMCR;
800422e: 68a2 ldr r2, [r4, #8]
tmpsmcr &= ~TIM_SMCR_TS;
8004230: 401a ands r2, r3
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
8004232: 2347 movs r3, #71 @ 0x47
8004234: e7c5 b.n 80041c2 <HAL_TIM_ConfigClockSource+0xae>
8004236: 46c0 nop @ (mov r8, r8)
8004238: ffce0088 .word 0xffce0088
800423c: ffcfff8f .word 0xffcfff8f
8004240: ffff0fff .word 0xffff0fff
08004244 <TIM_CCxChannelCmd>:
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8004244: 231f movs r3, #31
{
8004246: b510 push {r4, lr}
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8004248: 2401 movs r4, #1
800424a: 4019 ands r1, r3
800424c: 408c lsls r4, r1
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
800424e: 408a lsls r2, r1
TIMx->CCER &= ~tmp;
8004250: 6a03 ldr r3, [r0, #32]
8004252: 43a3 bics r3, r4
8004254: 6203 str r3, [r0, #32]
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8004256: 6a03 ldr r3, [r0, #32]
8004258: 431a orrs r2, r3
800425a: 6202 str r2, [r0, #32]
}
800425c: bd10 pop {r4, pc}
...
08004260 <HAL_TIM_OC_Start>:
{
8004260: 0002 movs r2, r0
8004262: b510 push {r4, lr}
8004264: 2908 cmp r1, #8
8004266: d01c beq.n 80042a2 <HAL_TIM_OC_Start+0x42>
8004268: d806 bhi.n 8004278 <HAL_TIM_OC_Start+0x18>
800426a: 2900 cmp r1, #0
800426c: d00b beq.n 8004286 <HAL_TIM_OC_Start+0x26>
800426e: 2904 cmp r1, #4
8004270: d014 beq.n 800429c <HAL_TIM_OC_Start+0x3c>
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8004272: 0013 movs r3, r2
8004274: 3343 adds r3, #67 @ 0x43
8004276: e008 b.n 800428a <HAL_TIM_OC_Start+0x2a>
8004278: 290c cmp r1, #12
800427a: d015 beq.n 80042a8 <HAL_TIM_OC_Start+0x48>
800427c: 2910 cmp r1, #16
800427e: d1f8 bne.n 8004272 <HAL_TIM_OC_Start+0x12>
8004280: 0003 movs r3, r0
8004282: 3342 adds r3, #66 @ 0x42
8004284: e001 b.n 800428a <HAL_TIM_OC_Start+0x2a>
8004286: 0003 movs r3, r0
8004288: 333e adds r3, #62 @ 0x3e
800428a: 781b ldrb r3, [r3, #0]
800428c: 3b01 subs r3, #1
800428e: 1e58 subs r0, r3, #1
8004290: 4183 sbcs r3, r0
8004292: b2db uxtb r3, r3
return HAL_ERROR;
8004294: 2001 movs r0, #1
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
8004296: 2b00 cmp r3, #0
8004298: d009 beq.n 80042ae <HAL_TIM_OC_Start+0x4e>
}
800429a: bd10 pop {r4, pc}
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
800429c: 0003 movs r3, r0
800429e: 333f adds r3, #63 @ 0x3f
80042a0: e7f3 b.n 800428a <HAL_TIM_OC_Start+0x2a>
80042a2: 0003 movs r3, r0
80042a4: 3340 adds r3, #64 @ 0x40
80042a6: e7f0 b.n 800428a <HAL_TIM_OC_Start+0x2a>
80042a8: 0003 movs r3, r0
80042aa: 3341 adds r3, #65 @ 0x41
80042ac: e7ed b.n 800428a <HAL_TIM_OC_Start+0x2a>
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
80042ae: 2302 movs r3, #2
80042b0: 2908 cmp r1, #8
80042b2: d030 beq.n 8004316 <HAL_TIM_OC_Start+0xb6>
80042b4: d806 bhi.n 80042c4 <HAL_TIM_OC_Start+0x64>
80042b6: 2900 cmp r1, #0
80042b8: d00b beq.n 80042d2 <HAL_TIM_OC_Start+0x72>
80042ba: 2904 cmp r1, #4
80042bc: d028 beq.n 8004310 <HAL_TIM_OC_Start+0xb0>
80042be: 0010 movs r0, r2
80042c0: 3043 adds r0, #67 @ 0x43
80042c2: e008 b.n 80042d6 <HAL_TIM_OC_Start+0x76>
80042c4: 290c cmp r1, #12
80042c6: d029 beq.n 800431c <HAL_TIM_OC_Start+0xbc>
80042c8: 2910 cmp r1, #16
80042ca: d1f8 bne.n 80042be <HAL_TIM_OC_Start+0x5e>
80042cc: 0010 movs r0, r2
80042ce: 3042 adds r0, #66 @ 0x42
80042d0: e001 b.n 80042d6 <HAL_TIM_OC_Start+0x76>
80042d2: 0010 movs r0, r2
80042d4: 303e adds r0, #62 @ 0x3e
80042d6: 7003 strb r3, [r0, #0]
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
80042d8: 6814 ldr r4, [r2, #0]
80042da: 2201 movs r2, #1
80042dc: 0020 movs r0, r4
80042de: f7ff ffb1 bl 8004244 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
80042e2: 4a18 ldr r2, [pc, #96] @ (8004344 <HAL_TIM_OC_Start+0xe4>)
80042e4: 4294 cmp r4, r2
80042e6: d005 beq.n 80042f4 <HAL_TIM_OC_Start+0x94>
80042e8: 4b17 ldr r3, [pc, #92] @ (8004348 <HAL_TIM_OC_Start+0xe8>)
80042ea: 429c cmp r4, r3
80042ec: d002 beq.n 80042f4 <HAL_TIM_OC_Start+0x94>
80042ee: 4b17 ldr r3, [pc, #92] @ (800434c <HAL_TIM_OC_Start+0xec>)
80042f0: 429c cmp r4, r3
80042f2: d116 bne.n 8004322 <HAL_TIM_OC_Start+0xc2>
__HAL_TIM_MOE_ENABLE(htim);
80042f4: 2380 movs r3, #128 @ 0x80
80042f6: 6c61 ldr r1, [r4, #68] @ 0x44
80042f8: 021b lsls r3, r3, #8
80042fa: 430b orrs r3, r1
80042fc: 6463 str r3, [r4, #68] @ 0x44
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80042fe: 4294 cmp r4, r2
8004300: d116 bne.n 8004330 <HAL_TIM_OC_Start+0xd0>
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
8004302: 68a3 ldr r3, [r4, #8]
8004304: 4a12 ldr r2, [pc, #72] @ (8004350 <HAL_TIM_OC_Start+0xf0>)
8004306: 4013 ands r3, r2
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8004308: 2b06 cmp r3, #6
800430a: d116 bne.n 800433a <HAL_TIM_OC_Start+0xda>
return HAL_OK;
800430c: 2000 movs r0, #0
800430e: e7c4 b.n 800429a <HAL_TIM_OC_Start+0x3a>
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8004310: 0010 movs r0, r2
8004312: 303f adds r0, #63 @ 0x3f
8004314: e7df b.n 80042d6 <HAL_TIM_OC_Start+0x76>
8004316: 0010 movs r0, r2
8004318: 3040 adds r0, #64 @ 0x40
800431a: e7dc b.n 80042d6 <HAL_TIM_OC_Start+0x76>
800431c: 0010 movs r0, r2
800431e: 3041 adds r0, #65 @ 0x41
8004320: e7d9 b.n 80042d6 <HAL_TIM_OC_Start+0x76>
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8004322: 2380 movs r3, #128 @ 0x80
8004324: 05db lsls r3, r3, #23
8004326: 429c cmp r4, r3
8004328: d0eb beq.n 8004302 <HAL_TIM_OC_Start+0xa2>
800432a: 4b0a ldr r3, [pc, #40] @ (8004354 <HAL_TIM_OC_Start+0xf4>)
800432c: 429c cmp r4, r3
800432e: d0e8 beq.n 8004302 <HAL_TIM_OC_Start+0xa2>
__HAL_TIM_ENABLE(htim);
8004330: 2301 movs r3, #1
8004332: 6822 ldr r2, [r4, #0]
8004334: 4313 orrs r3, r2
8004336: 6023 str r3, [r4, #0]
8004338: e7e8 b.n 800430c <HAL_TIM_OC_Start+0xac>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800433a: 2280 movs r2, #128 @ 0x80
800433c: 0252 lsls r2, r2, #9
800433e: 4293 cmp r3, r2
8004340: d1f6 bne.n 8004330 <HAL_TIM_OC_Start+0xd0>
8004342: e7e3 b.n 800430c <HAL_TIM_OC_Start+0xac>
8004344: 40012c00 .word 0x40012c00
8004348: 40014400 .word 0x40014400
800434c: 40014800 .word 0x40014800
8004350: 00010007 .word 0x00010007
8004354: 40000400 .word 0x40000400
08004358 <HAL_TIM_PWM_Start>:
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
8004358: b510 push {r4, lr}
800435a: f7ff ff81 bl 8004260 <HAL_TIM_OC_Start>
800435e: bd10 pop {r4, pc}
08004360 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
8004360: b5f0 push {r4, r5, r6, r7, lr}
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
8004362: 0004 movs r4, r0
8004364: 2202 movs r2, #2
8004366: 343c adds r4, #60 @ 0x3c
8004368: 7825 ldrb r5, [r4, #0]
{
800436a: 0003 movs r3, r0
__HAL_LOCK(htim);
800436c: 0010 movs r0, r2
800436e: 2d01 cmp r5, #1
8004370: d023 beq.n 80043ba <HAL_TIMEx_MasterConfigSynchronization+0x5a>
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
8004372: 001d movs r5, r3
8004374: 353d adds r5, #61 @ 0x3d
8004376: 702a strb r2, [r5, #0]
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
8004378: 681a ldr r2, [r3, #0]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
800437a: 4e10 ldr r6, [pc, #64] @ (80043bc <HAL_TIMEx_MasterConfigSynchronization+0x5c>)
tmpcr2 = htim->Instance->CR2;
800437c: 6853 ldr r3, [r2, #4]
tmpsmcr = htim->Instance->SMCR;
800437e: 6890 ldr r0, [r2, #8]
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
8004380: 42b2 cmp r2, r6
8004382: d103 bne.n 800438c <HAL_TIMEx_MasterConfigSynchronization+0x2c>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
8004384: 4f0e ldr r7, [pc, #56] @ (80043c0 <HAL_TIMEx_MasterConfigSynchronization+0x60>)
8004386: 403b ands r3, r7
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
8004388: 684f ldr r7, [r1, #4]
800438a: 433b orrs r3, r7
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
800438c: 2770 movs r7, #112 @ 0x70
800438e: 43bb bics r3, r7
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8004390: 680f ldr r7, [r1, #0]
8004392: 433b orrs r3, r7
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8004394: 6053 str r3, [r2, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
8004396: 42b2 cmp r2, r6
8004398: d006 beq.n 80043a8 <HAL_TIMEx_MasterConfigSynchronization+0x48>
800439a: 2380 movs r3, #128 @ 0x80
800439c: 05db lsls r3, r3, #23
800439e: 429a cmp r2, r3
80043a0: d002 beq.n 80043a8 <HAL_TIMEx_MasterConfigSynchronization+0x48>
80043a2: 4b08 ldr r3, [pc, #32] @ (80043c4 <HAL_TIMEx_MasterConfigSynchronization+0x64>)
80043a4: 429a cmp r2, r3
80043a6: d104 bne.n 80043b2 <HAL_TIMEx_MasterConfigSynchronization+0x52>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
80043a8: 2380 movs r3, #128 @ 0x80
80043aa: 4398 bics r0, r3
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
80043ac: 688b ldr r3, [r1, #8]
80043ae: 4318 orrs r0, r3
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
80043b0: 6090 str r0, [r2, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
80043b2: 2301 movs r3, #1
__HAL_UNLOCK(htim);
80043b4: 2000 movs r0, #0
htim->State = HAL_TIM_STATE_READY;
80043b6: 702b strb r3, [r5, #0]
__HAL_UNLOCK(htim);
80043b8: 7020 strb r0, [r4, #0]
return HAL_OK;
}
80043ba: bdf0 pop {r4, r5, r6, r7, pc}
80043bc: 40012c00 .word 0x40012c00
80043c0: ff0fffff .word 0xff0fffff
80043c4: 40000400 .word 0x40000400
080043c8 <HAL_TIMEx_ConfigBreakDeadTime>:
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
{
80043c8: b510 push {r4, lr}
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
/* Check input state */
__HAL_LOCK(htim);
80043ca: 0004 movs r4, r0
80043cc: 343c adds r4, #60 @ 0x3c
80043ce: 7823 ldrb r3, [r4, #0]
{
80043d0: 0002 movs r2, r0
__HAL_LOCK(htim);
80043d2: 2002 movs r0, #2
80043d4: 2b01 cmp r3, #1
80043d6: d039 beq.n 800444c <HAL_TIMEx_ConfigBreakDeadTime+0x84>
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
/* Set the BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
80043d8: 481d ldr r0, [pc, #116] @ (8004450 <HAL_TIMEx_ConfigBreakDeadTime+0x88>)
80043da: 68cb ldr r3, [r1, #12]
80043dc: 4003 ands r3, r0
80043de: 6888 ldr r0, [r1, #8]
80043e0: 4303 orrs r3, r0
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
80043e2: 481c ldr r0, [pc, #112] @ (8004454 <HAL_TIMEx_ConfigBreakDeadTime+0x8c>)
80043e4: 4003 ands r3, r0
80043e6: 6848 ldr r0, [r1, #4]
80043e8: 4303 orrs r3, r0
MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
80043ea: 481b ldr r0, [pc, #108] @ (8004458 <HAL_TIMEx_ConfigBreakDeadTime+0x90>)
80043ec: 4003 ands r3, r0
80043ee: 6808 ldr r0, [r1, #0]
80043f0: 4303 orrs r3, r0
MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
80043f2: 481a ldr r0, [pc, #104] @ (800445c <HAL_TIMEx_ConfigBreakDeadTime+0x94>)
80043f4: 4003 ands r3, r0
80043f6: 6908 ldr r0, [r1, #16]
80043f8: 4303 orrs r3, r0
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
80043fa: 4819 ldr r0, [pc, #100] @ (8004460 <HAL_TIMEx_ConfigBreakDeadTime+0x98>)
80043fc: 4003 ands r3, r0
80043fe: 6948 ldr r0, [r1, #20]
8004400: 4303 orrs r3, r0
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
8004402: 4818 ldr r0, [pc, #96] @ (8004464 <HAL_TIMEx_ConfigBreakDeadTime+0x9c>)
8004404: 4003 ands r3, r0
8004406: 6b08 ldr r0, [r1, #48] @ 0x30
8004408: 4303 orrs r3, r0
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
800440a: 4817 ldr r0, [pc, #92] @ (8004468 <HAL_TIMEx_ConfigBreakDeadTime+0xa0>)
800440c: 4003 ands r3, r0
800440e: 6988 ldr r0, [r1, #24]
8004410: 0400 lsls r0, r0, #16
8004412: 4303 orrs r3, r0
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
8004414: 4815 ldr r0, [pc, #84] @ (800446c <HAL_TIMEx_ConfigBreakDeadTime+0xa4>)
8004416: 4003 ands r3, r0
8004418: 69c8 ldr r0, [r1, #28]
800441a: 4303 orrs r3, r0
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
800441c: 6810 ldr r0, [r2, #0]
800441e: 4a14 ldr r2, [pc, #80] @ (8004470 <HAL_TIMEx_ConfigBreakDeadTime+0xa8>)
8004420: 4290 cmp r0, r2
8004422: d110 bne.n 8004446 <HAL_TIMEx_ConfigBreakDeadTime+0x7e>
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
/* Set the BREAK2 input related BDTR bits */
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
8004424: 4a13 ldr r2, [pc, #76] @ (8004474 <HAL_TIMEx_ConfigBreakDeadTime+0xac>)
8004426: 4013 ands r3, r2
8004428: 6a8a ldr r2, [r1, #40] @ 0x28
800442a: 0512 lsls r2, r2, #20
800442c: 431a orrs r2, r3
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
800442e: 4b12 ldr r3, [pc, #72] @ (8004478 <HAL_TIMEx_ConfigBreakDeadTime+0xb0>)
8004430: 401a ands r2, r3
8004432: 6a0b ldr r3, [r1, #32]
8004434: 431a orrs r2, r3
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
8004436: 4b11 ldr r3, [pc, #68] @ (800447c <HAL_TIMEx_ConfigBreakDeadTime+0xb4>)
8004438: 401a ands r2, r3
800443a: 6a4b ldr r3, [r1, #36] @ 0x24
800443c: 431a orrs r2, r3
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
800443e: 4b10 ldr r3, [pc, #64] @ (8004480 <HAL_TIMEx_ConfigBreakDeadTime+0xb8>)
8004440: 401a ands r2, r3
8004442: 6acb ldr r3, [r1, #44] @ 0x2c
8004444: 4313 orrs r3, r2
}
/* Set TIMx_BDTR */
htim->Instance->BDTR = tmpbdtr;
8004446: 6443 str r3, [r0, #68] @ 0x44
__HAL_UNLOCK(htim);
8004448: 2000 movs r0, #0
800444a: 7020 strb r0, [r4, #0]
return HAL_OK;
}
800444c: bd10 pop {r4, pc}
800444e: 46c0 nop @ (mov r8, r8)
8004450: fffffcff .word 0xfffffcff
8004454: fffffbff .word 0xfffffbff
8004458: fffff7ff .word 0xfffff7ff
800445c: ffffefff .word 0xffffefff
8004460: ffffdfff .word 0xffffdfff
8004464: ffffbfff .word 0xffffbfff
8004468: fff0ffff .word 0xfff0ffff
800446c: efffffff .word 0xefffffff
8004470: 40012c00 .word 0x40012c00
8004474: ff0fffff .word 0xff0fffff
8004478: feffffff .word 0xfeffffff
800447c: fdffffff .word 0xfdffffff
8004480: dfffffff .word 0xdfffffff
08004484 <HAL_TIMEx_CommutCallback>:
/**
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
8004484: 4770 bx lr
08004486 <HAL_TIMEx_BreakCallback>:
/**
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
8004486: 4770 bx lr
08004488 <HAL_TIMEx_Break2Callback>:
/**
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
8004488: 4770 bx lr
...
0800448c <UART_EndTxTransfer>:
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
{
800448c: b530 push {r4, r5, lr}
*/
__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
800448e: f3ef 8410 mrs r4, PRIMASK
\details Assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004492: 2201 movs r2, #1
8004494: f382 8810 msr PRIMASK, r2
/* Disable TXEIE, TCIE, TXFT interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
8004498: 25c0 movs r5, #192 @ 0xc0
800449a: 6801 ldr r1, [r0, #0]
800449c: 680b ldr r3, [r1, #0]
800449e: 43ab bics r3, r5
80044a0: 600b str r3, [r1, #0]
80044a2: f384 8810 msr PRIMASK, r4
__ASM volatile ("MRS %0, primask" : "=r" (result) );
80044a6: f3ef 8110 mrs r1, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80044aa: f382 8810 msr PRIMASK, r2
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
80044ae: 6802 ldr r2, [r0, #0]
80044b0: 4c04 ldr r4, [pc, #16] @ (80044c4 <UART_EndTxTransfer+0x38>)
80044b2: 6893 ldr r3, [r2, #8]
80044b4: 4023 ands r3, r4
80044b6: 6093 str r3, [r2, #8]
80044b8: f381 8810 msr PRIMASK, r1
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
80044bc: 2320 movs r3, #32
80044be: 3088 adds r0, #136 @ 0x88
80044c0: 6003 str r3, [r0, #0]
}
80044c2: bd30 pop {r4, r5, pc}
80044c4: ff7fffff .word 0xff7fffff
080044c8 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
80044c8: b530 push {r4, r5, lr}
__ASM volatile ("MRS %0, primask" : "=r" (result) );
80044ca: f3ef 8410 mrs r4, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80044ce: 2201 movs r2, #1
80044d0: f382 8810 msr PRIMASK, r2
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
80044d4: 6801 ldr r1, [r0, #0]
80044d6: 4d13 ldr r5, [pc, #76] @ (8004524 <UART_EndRxTransfer+0x5c>)
80044d8: 680b ldr r3, [r1, #0]
80044da: 402b ands r3, r5
80044dc: 600b str r3, [r1, #0]
80044de: f384 8810 msr PRIMASK, r4
__ASM volatile ("MRS %0, primask" : "=r" (result) );
80044e2: f3ef 8110 mrs r1, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80044e6: f382 8810 msr PRIMASK, r2
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
80044ea: 6802 ldr r2, [r0, #0]
80044ec: 4c0e ldr r4, [pc, #56] @ (8004528 <UART_EndRxTransfer+0x60>)
80044ee: 6893 ldr r3, [r2, #8]
80044f0: 4023 ands r3, r4
80044f2: 6093 str r3, [r2, #8]
80044f4: f381 8810 msr PRIMASK, r1
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80044f8: 6ec3 ldr r3, [r0, #108] @ 0x6c
80044fa: 2b01 cmp r3, #1
80044fc: d10a bne.n 8004514 <UART_EndRxTransfer+0x4c>
__ASM volatile ("MRS %0, primask" : "=r" (result) );
80044fe: f3ef 8110 mrs r1, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004502: f383 8810 msr PRIMASK, r3
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004506: 2410 movs r4, #16
8004508: 6802 ldr r2, [r0, #0]
800450a: 6813 ldr r3, [r2, #0]
800450c: 43a3 bics r3, r4
800450e: 6013 str r3, [r2, #0]
8004510: f381 8810 msr PRIMASK, r1
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
8004514: 0003 movs r3, r0
8004516: 2220 movs r2, #32
8004518: 338c adds r3, #140 @ 0x8c
800451a: 601a str r2, [r3, #0]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800451c: 2300 movs r3, #0
800451e: 66c3 str r3, [r0, #108] @ 0x6c
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
8004520: 6743 str r3, [r0, #116] @ 0x74
}
8004522: bd30 pop {r4, r5, pc}
8004524: fffffedf .word 0xfffffedf
8004528: effffffe .word 0xeffffffe
0800452c <HAL_UART_TxCpltCallback>:
__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
800452c: 4770 bx lr
0800452e <HAL_UART_RxCpltCallback>:
__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
800452e: 4770 bx lr
08004530 <HAL_UART_RxHalfCpltCallback>:
__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
8004530: 4770 bx lr
08004532 <UART_DMAError>:
* @brief DMA UART communication error callback.
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAError(DMA_HandleTypeDef *hdma)
{
8004532: b570 push {r4, r5, r6, lr}
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
8004534: 6a84 ldr r4, [r0, #40] @ 0x28
const HAL_UART_StateTypeDef gstate = huart->gState;
8004536: 0023 movs r3, r4
8004538: 3388 adds r3, #136 @ 0x88
800453a: 681a ldr r2, [r3, #0]
const HAL_UART_StateTypeDef rxstate = huart->RxState;
800453c: 685d ldr r5, [r3, #4]
/* Stop UART DMA Tx request if ongoing */
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
800453e: 6823 ldr r3, [r4, #0]
8004540: 689b ldr r3, [r3, #8]
8004542: 061b lsls r3, r3, #24
8004544: d508 bpl.n 8004558 <UART_DMAError+0x26>
8004546: 2a21 cmp r2, #33 @ 0x21
8004548: d106 bne.n 8004558 <UART_DMAError+0x26>
(gstate == HAL_UART_STATE_BUSY_TX))
{
huart->TxXferCount = 0U;
800454a: 0023 movs r3, r4
800454c: 2200 movs r2, #0
800454e: 3356 adds r3, #86 @ 0x56
UART_EndTxTransfer(huart);
8004550: 0020 movs r0, r4
huart->TxXferCount = 0U;
8004552: 801a strh r2, [r3, #0]
UART_EndTxTransfer(huart);
8004554: f7ff ff9a bl 800448c <UART_EndTxTransfer>
}
/* Stop UART DMA Rx request if ongoing */
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
8004558: 6823 ldr r3, [r4, #0]
800455a: 689b ldr r3, [r3, #8]
800455c: 065b lsls r3, r3, #25
800455e: d508 bpl.n 8004572 <UART_DMAError+0x40>
8004560: 2d22 cmp r5, #34 @ 0x22
8004562: d106 bne.n 8004572 <UART_DMAError+0x40>
(rxstate == HAL_UART_STATE_BUSY_RX))
{
huart->RxXferCount = 0U;
8004564: 0023 movs r3, r4
8004566: 2200 movs r2, #0
8004568: 335e adds r3, #94 @ 0x5e
UART_EndRxTransfer(huart);
800456a: 0020 movs r0, r4
huart->RxXferCount = 0U;
800456c: 801a strh r2, [r3, #0]
UART_EndRxTransfer(huart);
800456e: f7ff ffab bl 80044c8 <UART_EndRxTransfer>
}
huart->ErrorCode |= HAL_UART_ERROR_DMA;
8004572: 0022 movs r2, r4
8004574: 2310 movs r3, #16
8004576: 3290 adds r2, #144 @ 0x90
8004578: 6811 ldr r1, [r2, #0]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
800457a: 0020 movs r0, r4
huart->ErrorCode |= HAL_UART_ERROR_DMA;
800457c: 430b orrs r3, r1
800457e: 6013 str r3, [r2, #0]
HAL_UART_ErrorCallback(huart);
8004580: f7fc fa6a bl 8000a58 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8004584: bd70 pop {r4, r5, r6, pc}
08004586 <UART_DMAAbortOnError>:
* @param hdma DMA handle.
* @retval None
*/
static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
{
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
8004586: 6a80 ldr r0, [r0, #40] @ 0x28
huart->RxXferCount = 0U;
8004588: 2200 movs r2, #0
800458a: 0003 movs r3, r0
{
800458c: b510 push {r4, lr}
huart->RxXferCount = 0U;
800458e: 335e adds r3, #94 @ 0x5e
8004590: 801a strh r2, [r3, #0]
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered error callback*/
huart->ErrorCallback(huart);
#else
/*Call legacy weak error callback*/
HAL_UART_ErrorCallback(huart);
8004592: f7fc fa61 bl 8000a58 <HAL_UART_ErrorCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
8004596: bd10 pop {r4, pc}
08004598 <HAL_UART_IRQHandler>:
{
8004598: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
uint32_t isrflags = READ_REG(huart->Instance->ISR);
800459a: 6801 ldr r1, [r0, #0]
errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
800459c: 4dc3 ldr r5, [pc, #780] @ (80048ac <HAL_UART_IRQHandler+0x314>)
uint32_t isrflags = READ_REG(huart->Instance->ISR);
800459e: 69cb ldr r3, [r1, #28]
{
80045a0: 0004 movs r4, r0
uint32_t cr1its = READ_REG(huart->Instance->CR1);
80045a2: 680a ldr r2, [r1, #0]
uint32_t cr3its = READ_REG(huart->Instance->CR3);
80045a4: 6888 ldr r0, [r1, #8]
if (errorflags == 0U)
80045a6: 422b tst r3, r5
80045a8: d110 bne.n 80045cc <HAL_UART_IRQHandler+0x34>
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
80045aa: 2520 movs r5, #32
80045ac: 422b tst r3, r5
80045ae: d100 bne.n 80045b2 <HAL_UART_IRQHandler+0x1a>
80045b0: e09b b.n 80046ea <HAL_UART_IRQHandler+0x152>
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
80045b2: 2680 movs r6, #128 @ 0x80
80045b4: 0576 lsls r6, r6, #21
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
80045b6: 4015 ands r5, r2
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
80045b8: 4006 ands r6, r0
80045ba: 4335 orrs r5, r6
80045bc: d100 bne.n 80045c0 <HAL_UART_IRQHandler+0x28>
80045be: e094 b.n 80046ea <HAL_UART_IRQHandler+0x152>
if (huart->RxISR != NULL)
80045c0: 6f63 ldr r3, [r4, #116] @ 0x74
huart->TxISR(huart);
80045c2: 0020 movs r0, r4
if (huart->TxISR != NULL)
80045c4: 2b00 cmp r3, #0
80045c6: d000 beq.n 80045ca <HAL_UART_IRQHandler+0x32>
80045c8: e085 b.n 80046d6 <HAL_UART_IRQHandler+0x13e>
80045ca: e085 b.n 80046d8 <HAL_UART_IRQHandler+0x140>
&& ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
80045cc: 4db8 ldr r5, [pc, #736] @ (80048b0 <HAL_UART_IRQHandler+0x318>)
80045ce: 4005 ands r5, r0
80045d0: 9500 str r5, [sp, #0]
|| ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
80045d2: 4db8 ldr r5, [pc, #736] @ (80048b4 <HAL_UART_IRQHandler+0x31c>)
80045d4: 9e00 ldr r6, [sp, #0]
80045d6: 4015 ands r5, r2
80045d8: 4335 orrs r5, r6
80045da: d100 bne.n 80045de <HAL_UART_IRQHandler+0x46>
80045dc: e085 b.n 80046ea <HAL_UART_IRQHandler+0x152>
if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
80045de: 0025 movs r5, r4
80045e0: 2601 movs r6, #1
80045e2: 3590 adds r5, #144 @ 0x90
80045e4: 4233 tst r3, r6
80045e6: d005 beq.n 80045f4 <HAL_UART_IRQHandler+0x5c>
80045e8: 05d7 lsls r7, r2, #23
80045ea: d503 bpl.n 80045f4 <HAL_UART_IRQHandler+0x5c>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
80045ec: 620e str r6, [r1, #32]
huart->ErrorCode |= HAL_UART_ERROR_PE;
80045ee: 682f ldr r7, [r5, #0]
80045f0: 433e orrs r6, r7
80045f2: 602e str r6, [r5, #0]
if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
80045f4: 2602 movs r6, #2
80045f6: 4233 tst r3, r6
80045f8: d00c beq.n 8004614 <HAL_UART_IRQHandler+0x7c>
80045fa: 07c7 lsls r7, r0, #31
80045fc: d50a bpl.n 8004614 <HAL_UART_IRQHandler+0x7c>
huart->ErrorCode |= HAL_UART_ERROR_FE;
80045fe: 0027 movs r7, r4
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
8004600: 620e str r6, [r1, #32]
huart->ErrorCode |= HAL_UART_ERROR_FE;
8004602: 3790 adds r7, #144 @ 0x90
8004604: 683e ldr r6, [r7, #0]
8004606: 9701 str r7, [sp, #4]
8004608: 46b4 mov ip, r6
800460a: 2604 movs r6, #4
800460c: 4667 mov r7, ip
800460e: 433e orrs r6, r7
8004610: 9f01 ldr r7, [sp, #4]
8004612: 603e str r6, [r7, #0]
if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
8004614: 2604 movs r6, #4
8004616: 4233 tst r3, r6
8004618: d00c beq.n 8004634 <HAL_UART_IRQHandler+0x9c>
800461a: 07c7 lsls r7, r0, #31
800461c: d50a bpl.n 8004634 <HAL_UART_IRQHandler+0x9c>
huart->ErrorCode |= HAL_UART_ERROR_NE;
800461e: 0027 movs r7, r4
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
8004620: 620e str r6, [r1, #32]
huart->ErrorCode |= HAL_UART_ERROR_NE;
8004622: 3790 adds r7, #144 @ 0x90
8004624: 683e ldr r6, [r7, #0]
8004626: 9701 str r7, [sp, #4]
8004628: 46b4 mov ip, r6
800462a: 2602 movs r6, #2
800462c: 4667 mov r7, ip
800462e: 433e orrs r6, r7
8004630: 9f01 ldr r7, [sp, #4]
8004632: 603e str r6, [r7, #0]
if (((isrflags & USART_ISR_ORE) != 0U)
8004634: 2608 movs r6, #8
8004636: 46b4 mov ip, r6
8004638: 4233 tst r3, r6
800463a: d009 beq.n 8004650 <HAL_UART_IRQHandler+0xb8>
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
800463c: 2720 movs r7, #32
800463e: 9e00 ldr r6, [sp, #0]
8004640: 4017 ands r7, r2
8004642: 4337 orrs r7, r6
8004644: d004 beq.n 8004650 <HAL_UART_IRQHandler+0xb8>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8004646: 4666 mov r6, ip
8004648: 620e str r6, [r1, #32]
huart->ErrorCode |= HAL_UART_ERROR_ORE;
800464a: 682f ldr r7, [r5, #0]
800464c: 433e orrs r6, r7
800464e: 602e str r6, [r5, #0]
if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
8004650: 2680 movs r6, #128 @ 0x80
8004652: 0136 lsls r6, r6, #4
8004654: 4233 tst r3, r6
8004656: d006 beq.n 8004666 <HAL_UART_IRQHandler+0xce>
8004658: 0157 lsls r7, r2, #5
800465a: d504 bpl.n 8004666 <HAL_UART_IRQHandler+0xce>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
800465c: 620e str r6, [r1, #32]
huart->ErrorCode |= HAL_UART_ERROR_RTO;
800465e: 2120 movs r1, #32
8004660: 682e ldr r6, [r5, #0]
8004662: 4331 orrs r1, r6
8004664: 6029 str r1, [r5, #0]
if (huart->ErrorCode != HAL_UART_ERROR_NONE)
8004666: 6829 ldr r1, [r5, #0]
8004668: 2900 cmp r1, #0
800466a: d035 beq.n 80046d8 <HAL_UART_IRQHandler+0x140>
if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
800466c: 2120 movs r1, #32
800466e: 420b tst r3, r1
8004670: d00a beq.n 8004688 <HAL_UART_IRQHandler+0xf0>
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
8004672: 2380 movs r3, #128 @ 0x80
8004674: 055b lsls r3, r3, #21
&& (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
8004676: 4011 ands r1, r2
|| ((cr3its & USART_CR3_RXFTIE) != 0U)))
8004678: 4003 ands r3, r0
800467a: 4319 orrs r1, r3
800467c: d004 beq.n 8004688 <HAL_UART_IRQHandler+0xf0>
if (huart->RxISR != NULL)
800467e: 6f63 ldr r3, [r4, #116] @ 0x74
8004680: 2b00 cmp r3, #0
8004682: d001 beq.n 8004688 <HAL_UART_IRQHandler+0xf0>
huart->RxISR(huart);
8004684: 0020 movs r0, r4
8004686: 4798 blx r3
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
8004688: 6822 ldr r2, [r4, #0]
errorcode = huart->ErrorCode;
800468a: 682b ldr r3, [r5, #0]
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
800468c: 2740 movs r7, #64 @ 0x40
800468e: 6896 ldr r6, [r2, #8]
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
8004690: 2228 movs r2, #40 @ 0x28
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
8004692: 403e ands r6, r7
((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
8004694: 4013 ands r3, r2
UART_EndRxTransfer(huart);
8004696: 0020 movs r0, r4
if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
8004698: 431e orrs r6, r3
800469a: d022 beq.n 80046e2 <HAL_UART_IRQHandler+0x14a>
UART_EndRxTransfer(huart);
800469c: f7ff ff14 bl 80044c8 <UART_EndRxTransfer>
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
80046a0: 6823 ldr r3, [r4, #0]
80046a2: 689b ldr r3, [r3, #8]
80046a4: 423b tst r3, r7
80046a6: d018 beq.n 80046da <HAL_UART_IRQHandler+0x142>
__ASM volatile ("MRS %0, primask" : "=r" (result) );
80046a8: f3ef 8110 mrs r1, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80046ac: 2301 movs r3, #1
80046ae: f383 8810 msr PRIMASK, r3
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
80046b2: 0025 movs r5, r4
80046b4: cd04 ldmia r5!, {r2}
80046b6: 6893 ldr r3, [r2, #8]
80046b8: 43bb bics r3, r7
80046ba: 6093 str r3, [r2, #8]
80046bc: f381 8810 msr PRIMASK, r1
if (huart->hdmarx != NULL)
80046c0: 6fe8 ldr r0, [r5, #124] @ 0x7c
80046c2: 2800 cmp r0, #0
80046c4: d009 beq.n 80046da <HAL_UART_IRQHandler+0x142>
huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
80046c6: 4b7c ldr r3, [pc, #496] @ (80048b8 <HAL_UART_IRQHandler+0x320>)
80046c8: 6383 str r3, [r0, #56] @ 0x38
if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
80046ca: f7fe fcd1 bl 8003070 <HAL_DMA_Abort_IT>
80046ce: 2800 cmp r0, #0
80046d0: d002 beq.n 80046d8 <HAL_UART_IRQHandler+0x140>
huart->hdmarx->XferAbortCallback(huart->hdmarx);
80046d2: 6fe8 ldr r0, [r5, #124] @ 0x7c
80046d4: 6b83 ldr r3, [r0, #56] @ 0x38
80046d6: 4798 blx r3
}
80046d8: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
HAL_UART_ErrorCallback(huart);
80046da: 0020 movs r0, r4
80046dc: f7fc f9bc bl 8000a58 <HAL_UART_ErrorCallback>
80046e0: e7fa b.n 80046d8 <HAL_UART_IRQHandler+0x140>
HAL_UART_ErrorCallback(huart);
80046e2: f7fc f9b9 bl 8000a58 <HAL_UART_ErrorCallback>
huart->ErrorCode = HAL_UART_ERROR_NONE;
80046e6: 602e str r6, [r5, #0]
80046e8: e7f6 b.n 80046d8 <HAL_UART_IRQHandler+0x140>
if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80046ea: 6ee5 ldr r5, [r4, #108] @ 0x6c
80046ec: 2d01 cmp r5, #1
80046ee: d000 beq.n 80046f2 <HAL_UART_IRQHandler+0x15a>
80046f0: e0a4 b.n 800483c <HAL_UART_IRQHandler+0x2a4>
&& ((isrflags & USART_ISR_IDLE) != 0U)
80046f2: 2610 movs r6, #16
80046f4: 4233 tst r3, r6
80046f6: d100 bne.n 80046fa <HAL_UART_IRQHandler+0x162>
80046f8: e0a0 b.n 800483c <HAL_UART_IRQHandler+0x2a4>
&& ((cr1its & USART_ISR_IDLE) != 0U))
80046fa: 4232 tst r2, r6
80046fc: d100 bne.n 8004700 <HAL_UART_IRQHandler+0x168>
80046fe: e09d b.n 800483c <HAL_UART_IRQHandler+0x2a4>
&& (nb_remaining_rx_data < huart->RxXferSize))
8004700: 0023 movs r3, r4
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8004702: 620e str r6, [r1, #32]
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004704: 6889 ldr r1, [r1, #8]
&& (nb_remaining_rx_data < huart->RxXferSize))
8004706: 335c adds r3, #92 @ 0x5c
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
8004708: 0008 movs r0, r1
&& (nb_remaining_rx_data < huart->RxXferSize))
800470a: 881a ldrh r2, [r3, #0]
if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
800470c: 2340 movs r3, #64 @ 0x40
800470e: 4018 ands r0, r3
8004710: 4219 tst r1, r3
8004712: d05e beq.n 80047d2 <HAL_UART_IRQHandler+0x23a>
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
8004714: 1d20 adds r0, r4, #4
8004716: 6fc1 ldr r1, [r0, #124] @ 0x7c
8004718: 680f ldr r7, [r1, #0]
800471a: 6879 ldr r1, [r7, #4]
800471c: b289 uxth r1, r1
if ((nb_remaining_rx_data > 0U)
800471e: 2900 cmp r1, #0
8004720: d04d beq.n 80047be <HAL_UART_IRQHandler+0x226>
&& (nb_remaining_rx_data < huart->RxXferSize))
8004722: 4291 cmp r1, r2
8004724: d24b bcs.n 80047be <HAL_UART_IRQHandler+0x226>
huart->RxXferCount = nb_remaining_rx_data;
8004726: 0022 movs r2, r4
8004728: 325e adds r2, #94 @ 0x5e
800472a: 8011 strh r1, [r2, #0]
if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
800472c: 2120 movs r1, #32
800472e: 468c mov ip, r1
8004730: 683a ldr r2, [r7, #0]
8004732: 4011 ands r1, r2
8004734: 9100 str r1, [sp, #0]
8004736: 4661 mov r1, ip
8004738: 420a tst r2, r1
800473a: d132 bne.n 80047a2 <HAL_UART_IRQHandler+0x20a>
__ASM volatile ("MRS %0, primask" : "=r" (result) );
800473c: f3ef 8710 mrs r7, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004740: f385 8810 msr PRIMASK, r5
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8004744: 6821 ldr r1, [r4, #0]
8004746: 4e5d ldr r6, [pc, #372] @ (80048bc <HAL_UART_IRQHandler+0x324>)
8004748: 680a ldr r2, [r1, #0]
800474a: 4032 ands r2, r6
800474c: 600a str r2, [r1, #0]
800474e: f387 8810 msr PRIMASK, r7
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004752: f3ef 8710 mrs r7, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004756: f385 8810 msr PRIMASK, r5
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
800475a: 6821 ldr r1, [r4, #0]
800475c: 688a ldr r2, [r1, #8]
800475e: 43aa bics r2, r5
8004760: 608a str r2, [r1, #8]
8004762: f387 8810 msr PRIMASK, r7
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004766: f3ef 8710 mrs r7, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800476a: f385 8810 msr PRIMASK, r5
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
800476e: 6821 ldr r1, [r4, #0]
8004770: 688a ldr r2, [r1, #8]
8004772: 439a bics r2, r3
8004774: 608a str r2, [r1, #8]
8004776: f387 8810 msr PRIMASK, r7
huart->RxState = HAL_UART_STATE_READY;
800477a: 0023 movs r3, r4
800477c: 4662 mov r2, ip
800477e: 338c adds r3, #140 @ 0x8c
8004780: 601a str r2, [r3, #0]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004782: 9b00 ldr r3, [sp, #0]
8004784: 66e3 str r3, [r4, #108] @ 0x6c
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004786: f3ef 8110 mrs r1, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800478a: f385 8810 msr PRIMASK, r5
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800478e: 6822 ldr r2, [r4, #0]
8004790: 350f adds r5, #15
8004792: 6813 ldr r3, [r2, #0]
8004794: 43ab bics r3, r5
8004796: 6013 str r3, [r2, #0]
8004798: f381 8810 msr PRIMASK, r1
(void)HAL_DMA_Abort(huart->hdmarx);
800479c: 6fc0 ldr r0, [r0, #124] @ 0x7c
800479e: f7fe fc2d bl 8002ffc <HAL_DMA_Abort>
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
80047a2: 2302 movs r3, #2
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
80047a4: 0022 movs r2, r4
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
80047a6: 6723 str r3, [r4, #112] @ 0x70
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
80047a8: 0023 movs r3, r4
80047aa: 325c adds r2, #92 @ 0x5c
80047ac: 335e adds r3, #94 @ 0x5e
80047ae: 881b ldrh r3, [r3, #0]
80047b0: 8811 ldrh r1, [r2, #0]
80047b2: 1ac9 subs r1, r1, r3
80047b4: b289 uxth r1, r1
HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
80047b6: 0020 movs r0, r4
80047b8: f7fc f916 bl 80009e8 <HAL_UARTEx_RxEventCallback>
80047bc: e78c b.n 80046d8 <HAL_UART_IRQHandler+0x140>
if (nb_remaining_rx_data == huart->RxXferSize)
80047be: 4291 cmp r1, r2
80047c0: d000 beq.n 80047c4 <HAL_UART_IRQHandler+0x22c>
80047c2: e789 b.n 80046d8 <HAL_UART_IRQHandler+0x140>
if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
80047c4: 683b ldr r3, [r7, #0]
80047c6: 069b lsls r3, r3, #26
80047c8: d400 bmi.n 80047cc <HAL_UART_IRQHandler+0x234>
80047ca: e785 b.n 80046d8 <HAL_UART_IRQHandler+0x140>
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
80047cc: 2302 movs r3, #2
80047ce: 6723 str r3, [r4, #112] @ 0x70
80047d0: e7f1 b.n 80047b6 <HAL_UART_IRQHandler+0x21e>
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
80047d2: 0021 movs r1, r4
80047d4: 315e adds r1, #94 @ 0x5e
80047d6: 880b ldrh r3, [r1, #0]
if ((huart->RxXferCount > 0U)
80047d8: 8809 ldrh r1, [r1, #0]
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
80047da: b29b uxth r3, r3
if ((huart->RxXferCount > 0U)
80047dc: 2900 cmp r1, #0
80047de: d100 bne.n 80047e2 <HAL_UART_IRQHandler+0x24a>
80047e0: e77a b.n 80046d8 <HAL_UART_IRQHandler+0x140>
uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
80047e2: 1ad2 subs r2, r2, r3
80047e4: b291 uxth r1, r2
&& (nb_rx_data > 0U))
80047e6: 2900 cmp r1, #0
80047e8: d100 bne.n 80047ec <HAL_UART_IRQHandler+0x254>
80047ea: e775 b.n 80046d8 <HAL_UART_IRQHandler+0x140>
__ASM volatile ("MRS %0, primask" : "=r" (result) );
80047ec: f3ef 8710 mrs r7, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
80047f0: f385 8810 msr PRIMASK, r5
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
80047f4: 6822 ldr r2, [r4, #0]
80047f6: 4e32 ldr r6, [pc, #200] @ (80048c0 <HAL_UART_IRQHandler+0x328>)
80047f8: 6813 ldr r3, [r2, #0]
80047fa: 4033 ands r3, r6
80047fc: 6013 str r3, [r2, #0]
80047fe: f387 8810 msr PRIMASK, r7
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004802: f3ef 8710 mrs r7, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004806: f385 8810 msr PRIMASK, r5
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
800480a: 6822 ldr r2, [r4, #0]
800480c: 4e2d ldr r6, [pc, #180] @ (80048c4 <HAL_UART_IRQHandler+0x32c>)
800480e: 6893 ldr r3, [r2, #8]
8004810: 4033 ands r3, r6
8004812: 6093 str r3, [r2, #8]
8004814: f387 8810 msr PRIMASK, r7
huart->RxState = HAL_UART_STATE_READY;
8004818: 0023 movs r3, r4
800481a: 2220 movs r2, #32
800481c: 338c adds r3, #140 @ 0x8c
800481e: 601a str r2, [r3, #0]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004820: 66e0 str r0, [r4, #108] @ 0x6c
huart->RxISR = NULL;
8004822: 6760 str r0, [r4, #116] @ 0x74
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004824: f3ef 8010 mrs r0, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004828: f385 8810 msr PRIMASK, r5
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
800482c: 2510 movs r5, #16
800482e: 6822 ldr r2, [r4, #0]
8004830: 6813 ldr r3, [r2, #0]
8004832: 43ab bics r3, r5
8004834: 6013 str r3, [r2, #0]
8004836: f380 8810 msr PRIMASK, r0
huart->RxEventType = HAL_UART_RXEVENT_IDLE;
800483a: e7c7 b.n 80047cc <HAL_UART_IRQHandler+0x234>
if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
800483c: 2580 movs r5, #128 @ 0x80
800483e: 036d lsls r5, r5, #13
8004840: 422b tst r3, r5
8004842: d006 beq.n 8004852 <HAL_UART_IRQHandler+0x2ba>
8004844: 0246 lsls r6, r0, #9
8004846: d504 bpl.n 8004852 <HAL_UART_IRQHandler+0x2ba>
HAL_UARTEx_WakeupCallback(huart);
8004848: 0020 movs r0, r4
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
800484a: 620d str r5, [r1, #32]
HAL_UARTEx_WakeupCallback(huart);
800484c: f000 fbfa bl 8005044 <HAL_UARTEx_WakeupCallback>
return;
8004850: e742 b.n 80046d8 <HAL_UART_IRQHandler+0x140>
if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
8004852: 2180 movs r1, #128 @ 0x80
8004854: 420b tst r3, r1
8004856: d007 beq.n 8004868 <HAL_UART_IRQHandler+0x2d0>
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
8004858: 2580 movs r5, #128 @ 0x80
800485a: 042d lsls r5, r5, #16
&& (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
800485c: 4011 ands r1, r2
|| ((cr3its & USART_CR3_TXFTIE) != 0U)))
800485e: 4028 ands r0, r5
8004860: 4301 orrs r1, r0
8004862: d001 beq.n 8004868 <HAL_UART_IRQHandler+0x2d0>
if (huart->TxISR != NULL)
8004864: 6fa3 ldr r3, [r4, #120] @ 0x78
8004866: e6ac b.n 80045c2 <HAL_UART_IRQHandler+0x2a>
if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
8004868: 2140 movs r1, #64 @ 0x40
800486a: 420b tst r3, r1
800486c: d016 beq.n 800489c <HAL_UART_IRQHandler+0x304>
800486e: 420a tst r2, r1
8004870: d014 beq.n 800489c <HAL_UART_IRQHandler+0x304>
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004872: f3ef 8010 mrs r0, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004876: 2301 movs r3, #1
8004878: f383 8810 msr PRIMASK, r3
* @retval None
*/
static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
{
/* Disable the UART Transmit Complete Interrupt */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
800487c: 6822 ldr r2, [r4, #0]
800487e: 6813 ldr r3, [r2, #0]
8004880: 438b bics r3, r1
8004882: 6013 str r3, [r2, #0]
8004884: f380 8810 msr PRIMASK, r0
/* Tx process is ended, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8004888: 0023 movs r3, r4
800488a: 2220 movs r2, #32
800488c: 3388 adds r3, #136 @ 0x88
800488e: 601a str r2, [r3, #0]
/* Cleat TxISR function pointer */
huart->TxISR = NULL;
8004890: 2300 movs r3, #0
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
/*Call registered Tx complete callback*/
huart->TxCpltCallback(huart);
#else
/*Call legacy weak Tx complete callback*/
HAL_UART_TxCpltCallback(huart);
8004892: 0020 movs r0, r4
huart->TxISR = NULL;
8004894: 67a3 str r3, [r4, #120] @ 0x78
HAL_UART_TxCpltCallback(huart);
8004896: f7ff fe49 bl 800452c <HAL_UART_TxCpltCallback>
#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
}
800489a: e71d b.n 80046d8 <HAL_UART_IRQHandler+0x140>
if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
800489c: 0219 lsls r1, r3, #8
800489e: d513 bpl.n 80048c8 <HAL_UART_IRQHandler+0x330>
80048a0: 0051 lsls r1, r2, #1
80048a2: d511 bpl.n 80048c8 <HAL_UART_IRQHandler+0x330>
HAL_UARTEx_TxFifoEmptyCallback(huart);
80048a4: 0020 movs r0, r4
80048a6: f000 fbcf bl 8005048 <HAL_UARTEx_TxFifoEmptyCallback>
return;
80048aa: e715 b.n 80046d8 <HAL_UART_IRQHandler+0x140>
80048ac: 0000080f .word 0x0000080f
80048b0: 10000001 .word 0x10000001
80048b4: 04000120 .word 0x04000120
80048b8: 08004587 .word 0x08004587
80048bc: fffffeff .word 0xfffffeff
80048c0: fffffedf .word 0xfffffedf
80048c4: effffffe .word 0xeffffffe
if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
80048c8: 01db lsls r3, r3, #7
80048ca: d400 bmi.n 80048ce <HAL_UART_IRQHandler+0x336>
80048cc: e704 b.n 80046d8 <HAL_UART_IRQHandler+0x140>
80048ce: 2a00 cmp r2, #0
80048d0: db00 blt.n 80048d4 <HAL_UART_IRQHandler+0x33c>
80048d2: e701 b.n 80046d8 <HAL_UART_IRQHandler+0x140>
HAL_UARTEx_RxFifoFullCallback(huart);
80048d4: 0020 movs r0, r4
80048d6: f000 fbb6 bl 8005046 <HAL_UARTEx_RxFifoFullCallback>
return;
80048da: e6fd b.n 80046d8 <HAL_UART_IRQHandler+0x140>
080048dc <UART_DMARxHalfCplt>:
huart->RxEventType = HAL_UART_RXEVENT_HT;
80048dc: 2201 movs r2, #1
{
80048de: 0003 movs r3, r0
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
80048e0: 6a80 ldr r0, [r0, #40] @ 0x28
{
80048e2: b510 push {r4, lr}
huart->RxEventType = HAL_UART_RXEVENT_HT;
80048e4: 6702 str r2, [r0, #112] @ 0x70
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80048e6: 6ec2 ldr r2, [r0, #108] @ 0x6c
80048e8: 2a01 cmp r2, #1
80048ea: d111 bne.n 8004910 <UART_DMARxHalfCplt+0x34>
huart->RxXferCount = huart->RxXferSize / 2U;
80048ec: 0002 movs r2, r0
80048ee: 325c adds r2, #92 @ 0x5c
80048f0: 8811 ldrh r1, [r2, #0]
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
80048f2: 681b ldr r3, [r3, #0]
huart->RxXferCount = huart->RxXferSize / 2U;
80048f4: 084c lsrs r4, r1, #1
80048f6: 8054 strh r4, [r2, #2]
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
80048f8: 685b ldr r3, [r3, #4]
huart->RxXferCount = huart->RxXferSize / 2U;
80048fa: 3202 adds r2, #2
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
80048fc: b29b uxth r3, r3
if (nb_remaining_rx_data <= huart->RxXferSize)
80048fe: 4299 cmp r1, r3
8004900: d300 bcc.n 8004904 <UART_DMARxHalfCplt+0x28>
huart->RxXferCount = nb_remaining_rx_data;
8004902: 8013 strh r3, [r2, #0]
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
8004904: 8813 ldrh r3, [r2, #0]
8004906: 1ac9 subs r1, r1, r3
8004908: b289 uxth r1, r1
800490a: f7fc f86d bl 80009e8 <HAL_UARTEx_RxEventCallback>
}
800490e: bd10 pop {r4, pc}
HAL_UART_RxHalfCpltCallback(huart);
8004910: f7ff fe0e bl 8004530 <HAL_UART_RxHalfCpltCallback>
}
8004914: e7fb b.n 800490e <UART_DMARxHalfCplt+0x32>
...
08004918 <UART_DMAReceiveCplt>:
{
8004918: b5f8 push {r3, r4, r5, r6, r7, lr}
800491a: 0003 movs r3, r0
if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
800491c: 681a ldr r2, [r3, #0]
800491e: 2120 movs r1, #32
8004920: 6812 ldr r2, [r2, #0]
UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
8004922: 6a80 ldr r0, [r0, #40] @ 0x28
if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
8004924: 0014 movs r4, r2
8004926: 400c ands r4, r1
8004928: 420a tst r2, r1
800492a: d134 bne.n 8004996 <UART_DMAReceiveCplt+0x7e>
huart->RxXferCount = 0U;
800492c: 0002 movs r2, r0
800492e: 325e adds r2, #94 @ 0x5e
8004930: 8014 strh r4, [r2, #0]
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004932: f3ef 8610 mrs r6, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004936: 2201 movs r2, #1
8004938: f382 8810 msr PRIMASK, r2
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
800493c: 6805 ldr r5, [r0, #0]
800493e: 4f23 ldr r7, [pc, #140] @ (80049cc <UART_DMAReceiveCplt+0xb4>)
8004940: 682c ldr r4, [r5, #0]
8004942: 403c ands r4, r7
8004944: 602c str r4, [r5, #0]
8004946: f386 8810 msr PRIMASK, r6
__ASM volatile ("MRS %0, primask" : "=r" (result) );
800494a: f3ef 8610 mrs r6, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800494e: f382 8810 msr PRIMASK, r2
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004952: 6805 ldr r5, [r0, #0]
8004954: 68ac ldr r4, [r5, #8]
8004956: 4394 bics r4, r2
8004958: 60ac str r4, [r5, #8]
800495a: f386 8810 msr PRIMASK, r6
__ASM volatile ("MRS %0, primask" : "=r" (result) );
800495e: f3ef 8510 mrs r5, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004962: f382 8810 msr PRIMASK, r2
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8004966: 2640 movs r6, #64 @ 0x40
8004968: 6804 ldr r4, [r0, #0]
800496a: 68a2 ldr r2, [r4, #8]
800496c: 43b2 bics r2, r6
800496e: 60a2 str r2, [r4, #8]
8004970: f385 8810 msr PRIMASK, r5
huart->RxState = HAL_UART_STATE_READY;
8004974: 0002 movs r2, r0
8004976: 328c adds r2, #140 @ 0x8c
8004978: 6011 str r1, [r2, #0]
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
800497a: 6ec2 ldr r2, [r0, #108] @ 0x6c
800497c: 2a01 cmp r2, #1
800497e: d10a bne.n 8004996 <UART_DMAReceiveCplt+0x7e>
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004980: f3ef 8410 mrs r4, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004984: f382 8810 msr PRIMASK, r2
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8004988: 2510 movs r5, #16
800498a: 6801 ldr r1, [r0, #0]
800498c: 680a ldr r2, [r1, #0]
800498e: 43aa bics r2, r5
8004990: 600a str r2, [r1, #0]
8004992: f384 8810 msr PRIMASK, r4
huart->RxEventType = HAL_UART_RXEVENT_TC;
8004996: 2100 movs r1, #0
8004998: 6701 str r1, [r0, #112] @ 0x70
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
800499a: 6ec2 ldr r2, [r0, #108] @ 0x6c
800499c: 2a01 cmp r2, #1
800499e: d111 bne.n 80049c4 <UART_DMAReceiveCplt+0xac>
huart->RxXferCount = 0;
80049a0: 0002 movs r2, r0
80049a2: 325e adds r2, #94 @ 0x5e
80049a4: 8011 strh r1, [r2, #0]
if (nb_remaining_rx_data < huart->RxXferSize)
80049a6: 0001 movs r1, r0
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
80049a8: 681b ldr r3, [r3, #0]
if (nb_remaining_rx_data < huart->RxXferSize)
80049aa: 315c adds r1, #92 @ 0x5c
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
80049ac: 685b ldr r3, [r3, #4]
if (nb_remaining_rx_data < huart->RxXferSize)
80049ae: 8809 ldrh r1, [r1, #0]
uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
80049b0: b29b uxth r3, r3
if (nb_remaining_rx_data < huart->RxXferSize)
80049b2: 4299 cmp r1, r3
80049b4: d900 bls.n 80049b8 <UART_DMAReceiveCplt+0xa0>
huart->RxXferCount = nb_remaining_rx_data;
80049b6: 8013 strh r3, [r2, #0]
HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
80049b8: 8813 ldrh r3, [r2, #0]
80049ba: 1ac9 subs r1, r1, r3
80049bc: b289 uxth r1, r1
80049be: f7fc f813 bl 80009e8 <HAL_UARTEx_RxEventCallback>
}
80049c2: bdf8 pop {r3, r4, r5, r6, r7, pc}
HAL_UART_RxCpltCallback(huart);
80049c4: f7ff fdb3 bl 800452e <HAL_UART_RxCpltCallback>
}
80049c8: e7fb b.n 80049c2 <UART_DMAReceiveCplt+0xaa>
80049ca: 46c0 nop @ (mov r8, r8)
80049cc: fffffeff .word 0xfffffeff
080049d0 <UART_SetConfig>:
{
80049d0: b570 push {r4, r5, r6, lr}
80049d2: 0004 movs r4, r0
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
80049d4: 6925 ldr r5, [r4, #16]
80049d6: 68a1 ldr r1, [r4, #8]
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
80049d8: 6803 ldr r3, [r0, #0]
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
80049da: 4329 orrs r1, r5
80049dc: 6965 ldr r5, [r4, #20]
80049de: 69c2 ldr r2, [r0, #28]
80049e0: 4329 orrs r1, r5
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
80049e2: 6818 ldr r0, [r3, #0]
80049e4: 4d50 ldr r5, [pc, #320] @ (8004b28 <UART_SetConfig+0x158>)
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
80049e6: 4311 orrs r1, r2
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
80049e8: 4028 ands r0, r5
80049ea: 4301 orrs r1, r0
80049ec: 6019 str r1, [r3, #0]
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
80049ee: 6859 ldr r1, [r3, #4]
80049f0: 484e ldr r0, [pc, #312] @ (8004b2c <UART_SetConfig+0x15c>)
tmpreg |= huart->Init.OneBitSampling;
80049f2: 6a25 ldr r5, [r4, #32]
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
80049f4: 4001 ands r1, r0
80049f6: 68e0 ldr r0, [r4, #12]
80049f8: 4301 orrs r1, r0
80049fa: 6059 str r1, [r3, #4]
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
80049fc: 69a1 ldr r1, [r4, #24]
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
80049fe: 6898 ldr r0, [r3, #8]
tmpreg |= huart->Init.OneBitSampling;
8004a00: 4329 orrs r1, r5
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8004a02: 4d4b ldr r5, [pc, #300] @ (8004b30 <UART_SetConfig+0x160>)
8004a04: 4028 ands r0, r5
8004a06: 4301 orrs r1, r0
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
8004a08: 200f movs r0, #15
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8004a0a: 6099 str r1, [r3, #8]
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
8004a0c: 6ad9 ldr r1, [r3, #44] @ 0x2c
8004a0e: 4381 bics r1, r0
8004a10: 6a60 ldr r0, [r4, #36] @ 0x24
8004a12: 4301 orrs r1, r0
8004a14: 62d9 str r1, [r3, #44] @ 0x2c
UART_GETCLOCKSOURCE(huart, clocksource);
8004a16: 4947 ldr r1, [pc, #284] @ (8004b34 <UART_SetConfig+0x164>)
8004a18: 428b cmp r3, r1
8004a1a: d115 bne.n 8004a48 <UART_SetConfig+0x78>
8004a1c: 2103 movs r1, #3
8004a1e: 4b46 ldr r3, [pc, #280] @ (8004b38 <UART_SetConfig+0x168>)
8004a20: 6d5b ldr r3, [r3, #84] @ 0x54
8004a22: 400b ands r3, r1
8004a24: 3b01 subs r3, #1
8004a26: 2b02 cmp r3, #2
8004a28: d86f bhi.n 8004b0a <UART_SetConfig+0x13a>
8004a2a: 4944 ldr r1, [pc, #272] @ (8004b3c <UART_SetConfig+0x16c>)
8004a2c: 5cc8 ldrb r0, [r1, r3]
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004a2e: 2380 movs r3, #128 @ 0x80
8004a30: 021b lsls r3, r3, #8
8004a32: 429a cmp r2, r3
8004a34: d137 bne.n 8004aa6 <UART_SetConfig+0xd6>
switch (clocksource)
8004a36: 2808 cmp r0, #8
8004a38: d865 bhi.n 8004b06 <UART_SetConfig+0x136>
8004a3a: f7fb fb65 bl 8000108 <__gnu_thumb1_case_uqi>
8004a3e: 646a .short 0x646a
8004a40: 6431640b .word 0x6431640b
8004a44: 6464 .short 0x6464
8004a46: 14 .byte 0x14
8004a47: 00 .byte 0x00
UART_GETCLOCKSOURCE(huart, clocksource);
8004a48: 493d ldr r1, [pc, #244] @ (8004b40 <UART_SetConfig+0x170>)
8004a4a: 185b adds r3, r3, r1
8004a4c: 1e59 subs r1, r3, #1
8004a4e: 418b sbcs r3, r1
8004a50: 0118 lsls r0, r3, #4
8004a52: e7ec b.n 8004a2e <UART_SetConfig+0x5e>
pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
8004a54: 4b38 ldr r3, [pc, #224] @ (8004b38 <UART_SetConfig+0x168>)
8004a56: 483b ldr r0, [pc, #236] @ (8004b44 <UART_SetConfig+0x174>)
8004a58: 6819 ldr r1, [r3, #0]
8004a5a: 0609 lsls r1, r1, #24
8004a5c: 0f49 lsrs r1, r1, #29
8004a5e: 3101 adds r1, #1
8004a60: f7fb fb66 bl 8000130 <__udivsi3>
8004a64: 0002 movs r2, r0
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8004a66: 6a61 ldr r1, [r4, #36] @ 0x24
8004a68: 4b37 ldr r3, [pc, #220] @ (8004b48 <UART_SetConfig+0x178>)
8004a6a: 0049 lsls r1, r1, #1
8004a6c: 0010 movs r0, r2
8004a6e: 5ac9 ldrh r1, [r1, r3]
8004a70: f7fb fb5e bl 8000130 <__udivsi3>
8004a74: 6865 ldr r5, [r4, #4]
8004a76: 0040 lsls r0, r0, #1
8004a78: 086b lsrs r3, r5, #1
8004a7a: 18c0 adds r0, r0, r3
8004a7c: 0029 movs r1, r5
8004a7e: f7fb fb57 bl 8000130 <__udivsi3>
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8004a82: 0002 movs r2, r0
8004a84: 4b31 ldr r3, [pc, #196] @ (8004b4c <UART_SetConfig+0x17c>)
8004a86: 3a10 subs r2, #16
8004a88: 429a cmp r2, r3
8004a8a: d83c bhi.n 8004b06 <UART_SetConfig+0x136>
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8004a8c: 230f movs r3, #15
8004a8e: 0002 movs r2, r0
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8004a90: 0700 lsls r0, r0, #28
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8004a92: 439a bics r2, r3
8004a94: b293 uxth r3, r2
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8004a96: 0f40 lsrs r0, r0, #29
huart->Instance->BRR = brrtemp;
8004a98: 6822 ldr r2, [r4, #0]
8004a9a: 4303 orrs r3, r0
8004a9c: 60d3 str r3, [r2, #12]
8004a9e: e03c b.n 8004b1a <UART_SetConfig+0x14a>
pclk = HAL_RCC_GetSysClockFreq();
8004aa0: f7fe fd8a bl 80035b8 <HAL_RCC_GetSysClockFreq>
8004aa4: e037 b.n 8004b16 <UART_SetConfig+0x146>
switch (clocksource)
8004aa6: 2808 cmp r0, #8
8004aa8: d82d bhi.n 8004b06 <UART_SetConfig+0x136>
8004aaa: f7fb fb2d bl 8000108 <__gnu_thumb1_case_uqi>
8004aae: 2c05 .short 0x2c05
8004ab0: 2c262c0a .word 0x2c262c0a
8004ab4: 2c2c .short 0x2c2c
8004ab6: 29 .byte 0x29
8004ab7: 00 .byte 0x00
pclk = HAL_RCC_GetPCLK1Freq();
8004ab8: f7fe fe74 bl 80037a4 <HAL_RCC_GetPCLK1Freq>
if (pclk != 0U)
8004abc: 2800 cmp r0, #0
8004abe: d02c beq.n 8004b1a <UART_SetConfig+0x14a>
8004ac0: e007 b.n 8004ad2 <UART_SetConfig+0x102>
pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
8004ac2: 4b1d ldr r3, [pc, #116] @ (8004b38 <UART_SetConfig+0x168>)
8004ac4: 481f ldr r0, [pc, #124] @ (8004b44 <UART_SetConfig+0x174>)
8004ac6: 6819 ldr r1, [r3, #0]
8004ac8: 0609 lsls r1, r1, #24
8004aca: 0f49 lsrs r1, r1, #29
8004acc: 3101 adds r1, #1
8004ace: f7fb fb2f bl 8000130 <__udivsi3>
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8004ad2: 6a62 ldr r2, [r4, #36] @ 0x24
8004ad4: 4b1c ldr r3, [pc, #112] @ (8004b48 <UART_SetConfig+0x178>)
8004ad6: 0052 lsls r2, r2, #1
8004ad8: 5ad1 ldrh r1, [r2, r3]
8004ada: f7fb fb29 bl 8000130 <__udivsi3>
8004ade: 6865 ldr r5, [r4, #4]
8004ae0: 086b lsrs r3, r5, #1
8004ae2: 18c0 adds r0, r0, r3
8004ae4: 0029 movs r1, r5
8004ae6: f7fb fb23 bl 8000130 <__udivsi3>
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8004aea: 0002 movs r2, r0
8004aec: 4b17 ldr r3, [pc, #92] @ (8004b4c <UART_SetConfig+0x17c>)
8004aee: 3a10 subs r2, #16
8004af0: 429a cmp r2, r3
8004af2: d808 bhi.n 8004b06 <UART_SetConfig+0x136>
huart->Instance->BRR = (uint16_t)usartdiv;
8004af4: 6823 ldr r3, [r4, #0]
8004af6: 60d8 str r0, [r3, #12]
8004af8: e00f b.n 8004b1a <UART_SetConfig+0x14a>
pclk = HAL_RCC_GetSysClockFreq();
8004afa: f7fe fd5d bl 80035b8 <HAL_RCC_GetSysClockFreq>
break;
8004afe: e7dd b.n 8004abc <UART_SetConfig+0xec>
switch (clocksource)
8004b00: 2080 movs r0, #128 @ 0x80
8004b02: 0200 lsls r0, r0, #8
8004b04: e7e5 b.n 8004ad2 <UART_SetConfig+0x102>
ret = HAL_ERROR;
8004b06: 2001 movs r0, #1
8004b08: e008 b.n 8004b1c <UART_SetConfig+0x14c>
if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8004b0a: 2380 movs r3, #128 @ 0x80
8004b0c: 021b lsls r3, r3, #8
8004b0e: 429a cmp r2, r3
8004b10: d1d2 bne.n 8004ab8 <UART_SetConfig+0xe8>
pclk = HAL_RCC_GetPCLK1Freq();
8004b12: f7fe fe47 bl 80037a4 <HAL_RCC_GetPCLK1Freq>
pclk = HAL_RCC_GetSysClockFreq();
8004b16: 1e02 subs r2, r0, #0
if (pclk != 0U)
8004b18: d1a5 bne.n 8004a66 <UART_SetConfig+0x96>
switch (clocksource)
8004b1a: 2000 movs r0, #0
huart->NbRxDataToProcess = 1;
8004b1c: 4b0c ldr r3, [pc, #48] @ (8004b50 <UART_SetConfig+0x180>)
8004b1e: 66a3 str r3, [r4, #104] @ 0x68
huart->RxISR = NULL;
8004b20: 2300 movs r3, #0
8004b22: 6763 str r3, [r4, #116] @ 0x74
huart->TxISR = NULL;
8004b24: 67a3 str r3, [r4, #120] @ 0x78
}
8004b26: bd70 pop {r4, r5, r6, pc}
8004b28: cfff69f3 .word 0xcfff69f3
8004b2c: ffffcfff .word 0xffffcfff
8004b30: 11fff4ff .word 0x11fff4ff
8004b34: 40013800 .word 0x40013800
8004b38: 40021000 .word 0x40021000
8004b3c: 0800528c .word 0x0800528c
8004b40: bfffbc00 .word 0xbfffbc00
8004b44: 02dc6c00 .word 0x02dc6c00
8004b48: 08005290 .word 0x08005290
8004b4c: 0000ffef .word 0x0000ffef
8004b50: 00010001 .word 0x00010001
08004b54 <UART_AdvFeatureConfig>:
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8004b54: 6a83 ldr r3, [r0, #40] @ 0x28
{
8004b56: b530 push {r4, r5, lr}
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8004b58: 071a lsls r2, r3, #28
8004b5a: d506 bpl.n 8004b6a <UART_AdvFeatureConfig+0x16>
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8004b5c: 6801 ldr r1, [r0, #0]
8004b5e: 4c28 ldr r4, [pc, #160] @ (8004c00 <UART_AdvFeatureConfig+0xac>)
8004b60: 684a ldr r2, [r1, #4]
8004b62: 4022 ands r2, r4
8004b64: 6b84 ldr r4, [r0, #56] @ 0x38
8004b66: 4322 orrs r2, r4
8004b68: 604a str r2, [r1, #4]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
8004b6a: 07da lsls r2, r3, #31
8004b6c: d506 bpl.n 8004b7c <UART_AdvFeatureConfig+0x28>
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
8004b6e: 6801 ldr r1, [r0, #0]
8004b70: 4c24 ldr r4, [pc, #144] @ (8004c04 <UART_AdvFeatureConfig+0xb0>)
8004b72: 684a ldr r2, [r1, #4]
8004b74: 4022 ands r2, r4
8004b76: 6ac4 ldr r4, [r0, #44] @ 0x2c
8004b78: 4322 orrs r2, r4
8004b7a: 604a str r2, [r1, #4]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
8004b7c: 079a lsls r2, r3, #30
8004b7e: d506 bpl.n 8004b8e <UART_AdvFeatureConfig+0x3a>
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8004b80: 6801 ldr r1, [r0, #0]
8004b82: 4c21 ldr r4, [pc, #132] @ (8004c08 <UART_AdvFeatureConfig+0xb4>)
8004b84: 684a ldr r2, [r1, #4]
8004b86: 4022 ands r2, r4
8004b88: 6b04 ldr r4, [r0, #48] @ 0x30
8004b8a: 4322 orrs r2, r4
8004b8c: 604a str r2, [r1, #4]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
8004b8e: 075a lsls r2, r3, #29
8004b90: d506 bpl.n 8004ba0 <UART_AdvFeatureConfig+0x4c>
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
8004b92: 6801 ldr r1, [r0, #0]
8004b94: 4c1d ldr r4, [pc, #116] @ (8004c0c <UART_AdvFeatureConfig+0xb8>)
8004b96: 684a ldr r2, [r1, #4]
8004b98: 4022 ands r2, r4
8004b9a: 6b44 ldr r4, [r0, #52] @ 0x34
8004b9c: 4322 orrs r2, r4
8004b9e: 604a str r2, [r1, #4]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
8004ba0: 06da lsls r2, r3, #27
8004ba2: d506 bpl.n 8004bb2 <UART_AdvFeatureConfig+0x5e>
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
8004ba4: 6801 ldr r1, [r0, #0]
8004ba6: 4c1a ldr r4, [pc, #104] @ (8004c10 <UART_AdvFeatureConfig+0xbc>)
8004ba8: 688a ldr r2, [r1, #8]
8004baa: 4022 ands r2, r4
8004bac: 6bc4 ldr r4, [r0, #60] @ 0x3c
8004bae: 4322 orrs r2, r4
8004bb0: 608a str r2, [r1, #8]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
8004bb2: 069a lsls r2, r3, #26
8004bb4: d506 bpl.n 8004bc4 <UART_AdvFeatureConfig+0x70>
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
8004bb6: 6801 ldr r1, [r0, #0]
8004bb8: 4c16 ldr r4, [pc, #88] @ (8004c14 <UART_AdvFeatureConfig+0xc0>)
8004bba: 688a ldr r2, [r1, #8]
8004bbc: 4022 ands r2, r4
8004bbe: 6c04 ldr r4, [r0, #64] @ 0x40
8004bc0: 4322 orrs r2, r4
8004bc2: 608a str r2, [r1, #8]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
8004bc4: 065a lsls r2, r3, #25
8004bc6: d510 bpl.n 8004bea <UART_AdvFeatureConfig+0x96>
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
8004bc8: 6801 ldr r1, [r0, #0]
8004bca: 4d13 ldr r5, [pc, #76] @ (8004c18 <UART_AdvFeatureConfig+0xc4>)
8004bcc: 684a ldr r2, [r1, #4]
8004bce: 6c44 ldr r4, [r0, #68] @ 0x44
8004bd0: 402a ands r2, r5
8004bd2: 4322 orrs r2, r4
8004bd4: 604a str r2, [r1, #4]
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8004bd6: 2280 movs r2, #128 @ 0x80
8004bd8: 0352 lsls r2, r2, #13
8004bda: 4294 cmp r4, r2
8004bdc: d105 bne.n 8004bea <UART_AdvFeatureConfig+0x96>
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
8004bde: 684a ldr r2, [r1, #4]
8004be0: 4c0e ldr r4, [pc, #56] @ (8004c1c <UART_AdvFeatureConfig+0xc8>)
8004be2: 4022 ands r2, r4
8004be4: 6c84 ldr r4, [r0, #72] @ 0x48
8004be6: 4322 orrs r2, r4
8004be8: 604a str r2, [r1, #4]
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8004bea: 061b lsls r3, r3, #24
8004bec: d506 bpl.n 8004bfc <UART_AdvFeatureConfig+0xa8>
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
8004bee: 6802 ldr r2, [r0, #0]
8004bf0: 490b ldr r1, [pc, #44] @ (8004c20 <UART_AdvFeatureConfig+0xcc>)
8004bf2: 6853 ldr r3, [r2, #4]
8004bf4: 400b ands r3, r1
8004bf6: 6cc1 ldr r1, [r0, #76] @ 0x4c
8004bf8: 430b orrs r3, r1
8004bfa: 6053 str r3, [r2, #4]
}
8004bfc: bd30 pop {r4, r5, pc}
8004bfe: 46c0 nop @ (mov r8, r8)
8004c00: ffff7fff .word 0xffff7fff
8004c04: fffdffff .word 0xfffdffff
8004c08: fffeffff .word 0xfffeffff
8004c0c: fffbffff .word 0xfffbffff
8004c10: ffffefff .word 0xffffefff
8004c14: ffffdfff .word 0xffffdfff
8004c18: ffefffff .word 0xffefffff
8004c1c: ff9fffff .word 0xff9fffff
8004c20: fff7ffff .word 0xfff7ffff
08004c24 <UART_WaitOnFlagUntilTimeout>:
{
8004c24: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8004c26: 0004 movs r4, r0
8004c28: 000d movs r5, r1
8004c2a: 0017 movs r7, r2
8004c2c: 9300 str r3, [sp, #0]
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
8004c2e: 6822 ldr r2, [r4, #0]
8004c30: 69d3 ldr r3, [r2, #28]
8004c32: 402b ands r3, r5
8004c34: 1b5b subs r3, r3, r5
8004c36: 4259 negs r1, r3
8004c38: 414b adcs r3, r1
8004c3a: 42bb cmp r3, r7
8004c3c: d001 beq.n 8004c42 <UART_WaitOnFlagUntilTimeout+0x1e>
return HAL_OK;
8004c3e: 2000 movs r0, #0
8004c40: e026 b.n 8004c90 <UART_WaitOnFlagUntilTimeout+0x6c>
if (Timeout != HAL_MAX_DELAY)
8004c42: 9b08 ldr r3, [sp, #32]
8004c44: 3301 adds r3, #1
8004c46: d0f3 beq.n 8004c30 <UART_WaitOnFlagUntilTimeout+0xc>
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
8004c48: f7fd fe4a bl 80028e0 <HAL_GetTick>
8004c4c: 9b00 ldr r3, [sp, #0]
8004c4e: 1ac0 subs r0, r0, r3
8004c50: 9b08 ldr r3, [sp, #32]
8004c52: 4298 cmp r0, r3
8004c54: d82d bhi.n 8004cb2 <UART_WaitOnFlagUntilTimeout+0x8e>
8004c56: 2b00 cmp r3, #0
8004c58: d02b beq.n 8004cb2 <UART_WaitOnFlagUntilTimeout+0x8e>
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
8004c5a: 6823 ldr r3, [r4, #0]
8004c5c: 681a ldr r2, [r3, #0]
8004c5e: 0752 lsls r2, r2, #29
8004c60: d5e5 bpl.n 8004c2e <UART_WaitOnFlagUntilTimeout+0xa>
8004c62: 002a movs r2, r5
8004c64: 2140 movs r1, #64 @ 0x40
8004c66: 3a40 subs r2, #64 @ 0x40
8004c68: 438a bics r2, r1
8004c6a: d0e0 beq.n 8004c2e <UART_WaitOnFlagUntilTimeout+0xa>
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
8004c6c: 69da ldr r2, [r3, #28]
8004c6e: 2608 movs r6, #8
8004c70: 0011 movs r1, r2
8004c72: 4031 ands r1, r6
8004c74: 9101 str r1, [sp, #4]
8004c76: 4232 tst r2, r6
8004c78: d00b beq.n 8004c92 <UART_WaitOnFlagUntilTimeout+0x6e>
UART_EndRxTransfer(huart);
8004c7a: 0020 movs r0, r4
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8004c7c: 621e str r6, [r3, #32]
UART_EndRxTransfer(huart);
8004c7e: f7ff fc23 bl 80044c8 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8004c82: 0023 movs r3, r4
8004c84: 3390 adds r3, #144 @ 0x90
8004c86: 601e str r6, [r3, #0]
__HAL_UNLOCK(huart);
8004c88: 2300 movs r3, #0
return HAL_ERROR;
8004c8a: 2001 movs r0, #1
__HAL_UNLOCK(huart);
8004c8c: 3484 adds r4, #132 @ 0x84
8004c8e: 7023 strb r3, [r4, #0]
}
8004c90: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8004c92: 2280 movs r2, #128 @ 0x80
8004c94: 69d9 ldr r1, [r3, #28]
8004c96: 0112 lsls r2, r2, #4
8004c98: 4211 tst r1, r2
8004c9a: d0c8 beq.n 8004c2e <UART_WaitOnFlagUntilTimeout+0xa>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8004c9c: 621a str r2, [r3, #32]
UART_EndRxTransfer(huart);
8004c9e: 0020 movs r0, r4
8004ca0: f7ff fc12 bl 80044c8 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
8004ca4: 0023 movs r3, r4
8004ca6: 2220 movs r2, #32
8004ca8: 3390 adds r3, #144 @ 0x90
8004caa: 601a str r2, [r3, #0]
__HAL_UNLOCK(huart);
8004cac: 9b01 ldr r3, [sp, #4]
8004cae: 3484 adds r4, #132 @ 0x84
8004cb0: 7023 strb r3, [r4, #0]
return HAL_TIMEOUT;
8004cb2: 2003 movs r0, #3
8004cb4: e7ec b.n 8004c90 <UART_WaitOnFlagUntilTimeout+0x6c>
08004cb6 <HAL_UART_Transmit>:
{
8004cb6: b5f0 push {r4, r5, r6, r7, lr}
8004cb8: 0017 movs r7, r2
if (huart->gState == HAL_UART_STATE_READY)
8004cba: 0002 movs r2, r0
{
8004cbc: b087 sub sp, #28
if (huart->gState == HAL_UART_STATE_READY)
8004cbe: 3288 adds r2, #136 @ 0x88
{
8004cc0: 9305 str r3, [sp, #20]
if (huart->gState == HAL_UART_STATE_READY)
8004cc2: 6813 ldr r3, [r2, #0]
{
8004cc4: 0004 movs r4, r0
8004cc6: 000d movs r5, r1
return HAL_BUSY;
8004cc8: 2002 movs r0, #2
if (huart->gState == HAL_UART_STATE_READY)
8004cca: 2b20 cmp r3, #32
8004ccc: d139 bne.n 8004d42 <HAL_UART_Transmit+0x8c>
return HAL_ERROR;
8004cce: 3801 subs r0, #1
if ((pData == NULL) || (Size == 0U))
8004cd0: 2900 cmp r1, #0
8004cd2: d036 beq.n 8004d42 <HAL_UART_Transmit+0x8c>
8004cd4: 2f00 cmp r7, #0
8004cd6: d034 beq.n 8004d42 <HAL_UART_Transmit+0x8c>
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8004cd8: 2380 movs r3, #128 @ 0x80
8004cda: 68a1 ldr r1, [r4, #8]
8004cdc: 015b lsls r3, r3, #5
8004cde: 4299 cmp r1, r3
8004ce0: d104 bne.n 8004cec <HAL_UART_Transmit+0x36>
8004ce2: 6923 ldr r3, [r4, #16]
8004ce4: 2b00 cmp r3, #0
8004ce6: d101 bne.n 8004cec <HAL_UART_Transmit+0x36>
if ((((uint32_t)pData) & 1U) != 0U)
8004ce8: 4205 tst r5, r0
8004cea: d12a bne.n 8004d42 <HAL_UART_Transmit+0x8c>
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004cec: 0023 movs r3, r4
8004cee: 2600 movs r6, #0
8004cf0: 3390 adds r3, #144 @ 0x90
8004cf2: 601e str r6, [r3, #0]
huart->gState = HAL_UART_STATE_BUSY_TX;
8004cf4: 2321 movs r3, #33 @ 0x21
8004cf6: 6013 str r3, [r2, #0]
tickstart = HAL_GetTick();
8004cf8: f7fd fdf2 bl 80028e0 <HAL_GetTick>
huart->TxXferSize = Size;
8004cfc: 0023 movs r3, r4
8004cfe: 3354 adds r3, #84 @ 0x54
8004d00: 801f strh r7, [r3, #0]
huart->TxXferCount = Size;
8004d02: 3302 adds r3, #2
8004d04: 9303 str r3, [sp, #12]
8004d06: 801f strh r7, [r3, #0]
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8004d08: 2380 movs r3, #128 @ 0x80
8004d0a: 68a2 ldr r2, [r4, #8]
tickstart = HAL_GetTick();
8004d0c: 9004 str r0, [sp, #16]
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8004d0e: 015b lsls r3, r3, #5
8004d10: 429a cmp r2, r3
8004d12: d104 bne.n 8004d1e <HAL_UART_Transmit+0x68>
8004d14: 6923 ldr r3, [r4, #16]
8004d16: 42b3 cmp r3, r6
8004d18: d101 bne.n 8004d1e <HAL_UART_Transmit+0x68>
pdata16bits = (const uint16_t *) pData;
8004d1a: 002e movs r6, r5
pdata8bits = NULL;
8004d1c: 001d movs r5, r3
while (huart->TxXferCount > 0U)
8004d1e: 0023 movs r3, r4
8004d20: 3356 adds r3, #86 @ 0x56
8004d22: 881b ldrh r3, [r3, #0]
8004d24: b29a uxth r2, r3
8004d26: 2b00 cmp r3, #0
8004d28: d10d bne.n 8004d46 <HAL_UART_Transmit+0x90>
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8004d2a: 9b05 ldr r3, [sp, #20]
8004d2c: 0020 movs r0, r4
8004d2e: 9300 str r3, [sp, #0]
8004d30: 2140 movs r1, #64 @ 0x40
8004d32: 9b04 ldr r3, [sp, #16]
8004d34: f7ff ff76 bl 8004c24 <UART_WaitOnFlagUntilTimeout>
8004d38: 2320 movs r3, #32
8004d3a: 3488 adds r4, #136 @ 0x88
huart->gState = HAL_UART_STATE_READY;
8004d3c: 6023 str r3, [r4, #0]
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8004d3e: 2800 cmp r0, #0
8004d40: d10e bne.n 8004d60 <HAL_UART_Transmit+0xaa>
}
8004d42: b007 add sp, #28
8004d44: bdf0 pop {r4, r5, r6, r7, pc}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8004d46: 9b05 ldr r3, [sp, #20]
8004d48: 2200 movs r2, #0
8004d4a: 9300 str r3, [sp, #0]
8004d4c: 2180 movs r1, #128 @ 0x80
8004d4e: 0020 movs r0, r4
8004d50: 9b04 ldr r3, [sp, #16]
8004d52: f7ff ff67 bl 8004c24 <UART_WaitOnFlagUntilTimeout>
8004d56: 2800 cmp r0, #0
8004d58: d004 beq.n 8004d64 <HAL_UART_Transmit+0xae>
huart->gState = HAL_UART_STATE_READY;
8004d5a: 2320 movs r3, #32
8004d5c: 3488 adds r4, #136 @ 0x88
8004d5e: 6023 str r3, [r4, #0]
return HAL_TIMEOUT;
8004d60: 2003 movs r0, #3
8004d62: e7ee b.n 8004d42 <HAL_UART_Transmit+0x8c>
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
8004d64: 6822 ldr r2, [r4, #0]
if (pdata8bits == NULL)
8004d66: 2d00 cmp r5, #0
8004d68: d10b bne.n 8004d82 <HAL_UART_Transmit+0xcc>
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
8004d6a: 8833 ldrh r3, [r6, #0]
pdata16bits++;
8004d6c: 3602 adds r6, #2
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
8004d6e: 05db lsls r3, r3, #23
8004d70: 0ddb lsrs r3, r3, #23
8004d72: 6293 str r3, [r2, #40] @ 0x28
huart->TxXferCount--;
8004d74: 9b03 ldr r3, [sp, #12]
8004d76: 9a03 ldr r2, [sp, #12]
8004d78: 881b ldrh r3, [r3, #0]
8004d7a: 3b01 subs r3, #1
8004d7c: b29b uxth r3, r3
8004d7e: 8013 strh r3, [r2, #0]
8004d80: e7cd b.n 8004d1e <HAL_UART_Transmit+0x68>
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
8004d82: 782b ldrb r3, [r5, #0]
pdata8bits++;
8004d84: 3501 adds r5, #1
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
8004d86: 6293 str r3, [r2, #40] @ 0x28
pdata8bits++;
8004d88: e7f4 b.n 8004d74 <HAL_UART_Transmit+0xbe>
...
08004d8c <UART_CheckIdleState>:
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004d8c: 0003 movs r3, r0
{
8004d8e: b573 push {r0, r1, r4, r5, r6, lr}
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004d90: 2600 movs r6, #0
{
8004d92: 0004 movs r4, r0
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004d94: 3390 adds r3, #144 @ 0x90
8004d96: 601e str r6, [r3, #0]
tickstart = HAL_GetTick();
8004d98: f7fd fda2 bl 80028e0 <HAL_GetTick>
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8004d9c: 6823 ldr r3, [r4, #0]
tickstart = HAL_GetTick();
8004d9e: 0005 movs r5, r0
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
8004da0: 681b ldr r3, [r3, #0]
8004da2: 071b lsls r3, r3, #28
8004da4: d51f bpl.n 8004de6 <UART_CheckIdleState+0x5a>
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8004da6: 2180 movs r1, #128 @ 0x80
8004da8: 4b28 ldr r3, [pc, #160] @ (8004e4c <UART_CheckIdleState+0xc0>)
8004daa: 0032 movs r2, r6
8004dac: 9300 str r3, [sp, #0]
8004dae: 0389 lsls r1, r1, #14
8004db0: 0003 movs r3, r0
8004db2: 0020 movs r0, r4
8004db4: f7ff ff36 bl 8004c24 <UART_WaitOnFlagUntilTimeout>
8004db8: 42b0 cmp r0, r6
8004dba: d014 beq.n 8004de6 <UART_CheckIdleState+0x5a>
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004dbc: f3ef 8110 mrs r1, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004dc0: 2301 movs r3, #1
8004dc2: f383 8810 msr PRIMASK, r3
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
8004dc6: 2080 movs r0, #128 @ 0x80
8004dc8: 6822 ldr r2, [r4, #0]
8004dca: 6813 ldr r3, [r2, #0]
8004dcc: 4383 bics r3, r0
8004dce: 6013 str r3, [r2, #0]
8004dd0: f381 8810 msr PRIMASK, r1
huart->gState = HAL_UART_STATE_READY;
8004dd4: 0023 movs r3, r4
8004dd6: 2220 movs r2, #32
8004dd8: 3388 adds r3, #136 @ 0x88
8004dda: 601a str r2, [r3, #0]
return HAL_TIMEOUT;
8004ddc: 2003 movs r0, #3
__HAL_UNLOCK(huart);
8004dde: 2300 movs r3, #0
8004de0: 3484 adds r4, #132 @ 0x84
8004de2: 7023 strb r3, [r4, #0]
}
8004de4: bd76 pop {r1, r2, r4, r5, r6, pc}
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
8004de6: 0026 movs r6, r4
8004de8: 6823 ldr r3, [r4, #0]
8004dea: 368c adds r6, #140 @ 0x8c
8004dec: 681b ldr r3, [r3, #0]
8004dee: 075b lsls r3, r3, #29
8004df0: d523 bpl.n 8004e3a <UART_CheckIdleState+0xae>
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8004df2: 2180 movs r1, #128 @ 0x80
8004df4: 4b15 ldr r3, [pc, #84] @ (8004e4c <UART_CheckIdleState+0xc0>)
8004df6: 2200 movs r2, #0
8004df8: 9300 str r3, [sp, #0]
8004dfa: 0020 movs r0, r4
8004dfc: 002b movs r3, r5
8004dfe: 03c9 lsls r1, r1, #15
8004e00: f7ff ff10 bl 8004c24 <UART_WaitOnFlagUntilTimeout>
8004e04: 2800 cmp r0, #0
8004e06: d018 beq.n 8004e3a <UART_CheckIdleState+0xae>
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004e08: f3ef 8010 mrs r0, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004e0c: 2201 movs r2, #1
8004e0e: f382 8810 msr PRIMASK, r2
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8004e12: 6821 ldr r1, [r4, #0]
8004e14: 4d0e ldr r5, [pc, #56] @ (8004e50 <UART_CheckIdleState+0xc4>)
8004e16: 680b ldr r3, [r1, #0]
8004e18: 402b ands r3, r5
8004e1a: 600b str r3, [r1, #0]
8004e1c: f380 8810 msr PRIMASK, r0
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004e20: f3ef 8010 mrs r0, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004e24: f382 8810 msr PRIMASK, r2
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004e28: 6821 ldr r1, [r4, #0]
8004e2a: 688b ldr r3, [r1, #8]
8004e2c: 4393 bics r3, r2
8004e2e: 608b str r3, [r1, #8]
8004e30: f380 8810 msr PRIMASK, r0
huart->RxState = HAL_UART_STATE_READY;
8004e34: 2320 movs r3, #32
8004e36: 6033 str r3, [r6, #0]
return HAL_TIMEOUT;
8004e38: e7d0 b.n 8004ddc <UART_CheckIdleState+0x50>
huart->gState = HAL_UART_STATE_READY;
8004e3a: 0023 movs r3, r4
8004e3c: 2220 movs r2, #32
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004e3e: 2000 movs r0, #0
huart->gState = HAL_UART_STATE_READY;
8004e40: 3388 adds r3, #136 @ 0x88
8004e42: 601a str r2, [r3, #0]
huart->RxState = HAL_UART_STATE_READY;
8004e44: 6032 str r2, [r6, #0]
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8004e46: 66e0 str r0, [r4, #108] @ 0x6c
huart->RxEventType = HAL_UART_RXEVENT_TC;
8004e48: 6720 str r0, [r4, #112] @ 0x70
return HAL_OK;
8004e4a: e7c8 b.n 8004dde <UART_CheckIdleState+0x52>
8004e4c: 01ffffff .word 0x01ffffff
8004e50: fffffedf .word 0xfffffedf
08004e54 <HAL_UART_Init>:
{
8004e54: b570 push {r4, r5, r6, lr}
8004e56: 1e04 subs r4, r0, #0
if (huart == NULL)
8004e58: d101 bne.n 8004e5e <HAL_UART_Init+0xa>
return HAL_ERROR;
8004e5a: 2001 movs r0, #1
}
8004e5c: bd70 pop {r4, r5, r6, pc}
if (huart->gState == HAL_UART_STATE_RESET)
8004e5e: 0005 movs r5, r0
8004e60: 3588 adds r5, #136 @ 0x88
8004e62: 682b ldr r3, [r5, #0]
8004e64: 2b00 cmp r3, #0
8004e66: d104 bne.n 8004e72 <HAL_UART_Init+0x1e>
huart->Lock = HAL_UNLOCKED;
8004e68: 0002 movs r2, r0
8004e6a: 3284 adds r2, #132 @ 0x84
8004e6c: 7013 strb r3, [r2, #0]
HAL_UART_MspInit(huart);
8004e6e: f7fd fbdd bl 800262c <HAL_UART_MspInit>
huart->gState = HAL_UART_STATE_BUSY;
8004e72: 2324 movs r3, #36 @ 0x24
__HAL_UART_DISABLE(huart);
8004e74: 2101 movs r1, #1
8004e76: 6822 ldr r2, [r4, #0]
huart->gState = HAL_UART_STATE_BUSY;
8004e78: 602b str r3, [r5, #0]
__HAL_UART_DISABLE(huart);
8004e7a: 6813 ldr r3, [r2, #0]
8004e7c: 438b bics r3, r1
8004e7e: 6013 str r3, [r2, #0]
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
8004e80: 6aa3 ldr r3, [r4, #40] @ 0x28
8004e82: 2b00 cmp r3, #0
8004e84: d002 beq.n 8004e8c <HAL_UART_Init+0x38>
UART_AdvFeatureConfig(huart);
8004e86: 0020 movs r0, r4
8004e88: f7ff fe64 bl 8004b54 <UART_AdvFeatureConfig>
if (UART_SetConfig(huart) == HAL_ERROR)
8004e8c: 0020 movs r0, r4
8004e8e: f7ff fd9f bl 80049d0 <UART_SetConfig>
8004e92: 2801 cmp r0, #1
8004e94: d0e1 beq.n 8004e5a <HAL_UART_Init+0x6>
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8004e96: 6823 ldr r3, [r4, #0]
8004e98: 4907 ldr r1, [pc, #28] @ (8004eb8 <HAL_UART_Init+0x64>)
8004e9a: 685a ldr r2, [r3, #4]
return (UART_CheckIdleState(huart));
8004e9c: 0020 movs r0, r4
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8004e9e: 400a ands r2, r1
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8004ea0: 212a movs r1, #42 @ 0x2a
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
8004ea2: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
8004ea4: 689a ldr r2, [r3, #8]
8004ea6: 438a bics r2, r1
8004ea8: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
8004eaa: 2201 movs r2, #1
8004eac: 6819 ldr r1, [r3, #0]
8004eae: 430a orrs r2, r1
8004eb0: 601a str r2, [r3, #0]
return (UART_CheckIdleState(huart));
8004eb2: f7ff ff6b bl 8004d8c <UART_CheckIdleState>
8004eb6: e7d1 b.n 8004e5c <HAL_UART_Init+0x8>
8004eb8: ffffb7ff .word 0xffffb7ff
08004ebc <UART_Start_Receive_DMA>:
{
8004ebc: b5f8 push {r3, r4, r5, r6, r7, lr}
8004ebe: 0013 movs r3, r2
huart->RxXferSize = Size;
8004ec0: 0002 movs r2, r0
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004ec2: 0006 movs r6, r0
huart->RxState = HAL_UART_STATE_BUSY_RX;
8004ec4: 0005 movs r5, r0
huart->RxXferSize = Size;
8004ec6: 325c adds r2, #92 @ 0x5c
huart->pRxBuffPtr = pData;
8004ec8: 6581 str r1, [r0, #88] @ 0x58
{
8004eca: 000f movs r7, r1
huart->RxXferSize = Size;
8004ecc: 8013 strh r3, [r2, #0]
huart->RxState = HAL_UART_STATE_BUSY_RX;
8004ece: 2122 movs r1, #34 @ 0x22
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004ed0: 2200 movs r2, #0
8004ed2: 3690 adds r6, #144 @ 0x90
huart->RxState = HAL_UART_STATE_BUSY_RX;
8004ed4: 358c adds r5, #140 @ 0x8c
huart->ErrorCode = HAL_UART_ERROR_NONE;
8004ed6: 6032 str r2, [r6, #0]
huart->RxState = HAL_UART_STATE_BUSY_RX;
8004ed8: 6029 str r1, [r5, #0]
if (huart->hdmarx != NULL)
8004eda: 1d01 adds r1, r0, #4
{
8004edc: 0004 movs r4, r0
if (huart->hdmarx != NULL)
8004ede: 6fc8 ldr r0, [r1, #124] @ 0x7c
8004ee0: 4290 cmp r0, r2
8004ee2: d013 beq.n 8004f0c <UART_Start_Receive_DMA+0x50>
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
8004ee4: 491d ldr r1, [pc, #116] @ (8004f5c <UART_Start_Receive_DMA+0xa0>)
huart->hdmarx->XferAbortCallback = NULL;
8004ee6: 6382 str r2, [r0, #56] @ 0x38
huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
8004ee8: 62c1 str r1, [r0, #44] @ 0x2c
huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
8004eea: 491d ldr r1, [pc, #116] @ (8004f60 <UART_Start_Receive_DMA+0xa4>)
if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
8004eec: 003a movs r2, r7
huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
8004eee: 6301 str r1, [r0, #48] @ 0x30
huart->hdmarx->XferErrorCallback = UART_DMAError;
8004ef0: 491c ldr r1, [pc, #112] @ (8004f64 <UART_Start_Receive_DMA+0xa8>)
8004ef2: 6341 str r1, [r0, #52] @ 0x34
if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
8004ef4: 6821 ldr r1, [r4, #0]
8004ef6: 3124 adds r1, #36 @ 0x24
8004ef8: f7fe f838 bl 8002f6c <HAL_DMA_Start_IT>
8004efc: 2800 cmp r0, #0
8004efe: d005 beq.n 8004f0c <UART_Start_Receive_DMA+0x50>
huart->ErrorCode = HAL_UART_ERROR_DMA;
8004f00: 2310 movs r3, #16
return HAL_ERROR;
8004f02: 2001 movs r0, #1
huart->ErrorCode = HAL_UART_ERROR_DMA;
8004f04: 6033 str r3, [r6, #0]
huart->RxState = HAL_UART_STATE_READY;
8004f06: 18db adds r3, r3, r3
8004f08: 602b str r3, [r5, #0]
}
8004f0a: bdf8 pop {r3, r4, r5, r6, r7, pc}
if (huart->Init.Parity != UART_PARITY_NONE)
8004f0c: 6923 ldr r3, [r4, #16]
8004f0e: 2b00 cmp r3, #0
8004f10: d00b beq.n 8004f2a <UART_Start_Receive_DMA+0x6e>
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004f12: f3ef 8110 mrs r1, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004f16: 2301 movs r3, #1
8004f18: f383 8810 msr PRIMASK, r3
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
8004f1c: 6822 ldr r2, [r4, #0]
8004f1e: 33ff adds r3, #255 @ 0xff
8004f20: 6810 ldr r0, [r2, #0]
8004f22: 4303 orrs r3, r0
8004f24: 6013 str r3, [r2, #0]
8004f26: f381 8810 msr PRIMASK, r1
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004f2a: f3ef 8010 mrs r0, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004f2e: 2301 movs r3, #1
8004f30: f383 8810 msr PRIMASK, r3
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
8004f34: 6821 ldr r1, [r4, #0]
8004f36: 688a ldr r2, [r1, #8]
8004f38: 431a orrs r2, r3
8004f3a: 608a str r2, [r1, #8]
8004f3c: f380 8810 msr PRIMASK, r0
__ASM volatile ("MRS %0, primask" : "=r" (result) );
8004f40: f3ef 8110 mrs r1, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
8004f44: f383 8810 msr PRIMASK, r3
ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
8004f48: 6822 ldr r2, [r4, #0]
8004f4a: 333f adds r3, #63 @ 0x3f
8004f4c: 6890 ldr r0, [r2, #8]
8004f4e: 4303 orrs r3, r0
8004f50: 6093 str r3, [r2, #8]
8004f52: f381 8810 msr PRIMASK, r1
return HAL_OK;
8004f56: 2000 movs r0, #0
8004f58: e7d7 b.n 8004f0a <UART_Start_Receive_DMA+0x4e>
8004f5a: 46c0 nop @ (mov r8, r8)
8004f5c: 08004919 .word 0x08004919
8004f60: 080048dd .word 0x080048dd
8004f64: 08004533 .word 0x08004533
08004f68 <UARTEx_SetNbDataToProcess>:
* the UART configuration registers.
* @param huart UART handle.
* @retval None
*/
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
{
8004f68: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8004f6a: 0007 movs r7, r0
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
8004f6c: 6e43 ldr r3, [r0, #100] @ 0x64
{
8004f6e: 0004 movs r4, r0
8004f70: 376a adds r7, #106 @ 0x6a
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
8004f72: 2b00 cmp r3, #0
8004f74: d104 bne.n 8004f80 <UARTEx_SetNbDataToProcess+0x18>
{
huart->NbTxDataToProcess = 1U;
8004f76: 2001 movs r0, #1
8004f78: 8038 strh r0, [r7, #0]
huart->NbRxDataToProcess = 1U;
8004f7a: 3468 adds r4, #104 @ 0x68
8004f7c: 8020 strh r0, [r4, #0]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
(uint16_t)denominator[tx_fifo_threshold];
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
(uint16_t)denominator[rx_fifo_threshold];
}
}
8004f7e: bdf7 pop {r0, r1, r2, r4, r5, r6, r7, pc}
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
8004f80: 6803 ldr r3, [r0, #0]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8004f82: 4e0b ldr r6, [pc, #44] @ (8004fb0 <UARTEx_SetNbDataToProcess+0x48>)
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
8004f84: 689a ldr r2, [r3, #8]
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
8004f86: 689b ldr r3, [r3, #8]
(uint16_t)denominator[tx_fifo_threshold];
8004f88: 4d0a ldr r5, [pc, #40] @ (8004fb4 <UARTEx_SetNbDataToProcess+0x4c>)
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
8004f8a: 0f5b lsrs r3, r3, #29
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8004f8c: 5cf0 ldrb r0, [r6, r3]
(uint16_t)denominator[tx_fifo_threshold];
8004f8e: 5ce9 ldrb r1, [r5, r3]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8004f90: 00c0 lsls r0, r0, #3
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
8004f92: 9201 str r2, [sp, #4]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8004f94: f7fb f956 bl 8000244 <__divsi3>
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
8004f98: 9b01 ldr r3, [sp, #4]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8004f9a: 8038 strh r0, [r7, #0]
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
8004f9c: 011b lsls r3, r3, #4
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8004f9e: 0f5b lsrs r3, r3, #29
8004fa0: 5cf0 ldrb r0, [r6, r3]
(uint16_t)denominator[rx_fifo_threshold];
8004fa2: 5ce9 ldrb r1, [r5, r3]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8004fa4: 00c0 lsls r0, r0, #3
8004fa6: f7fb f94d bl 8000244 <__divsi3>
8004faa: b280 uxth r0, r0
}
8004fac: e7e5 b.n 8004f7a <UARTEx_SetNbDataToProcess+0x12>
8004fae: 46c0 nop @ (mov r8, r8)
8004fb0: 080052b0 .word 0x080052b0
8004fb4: 080052a8 .word 0x080052a8
08004fb8 <HAL_RS485Ex_Init>:
{
8004fb8: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr}
8004fba: 0004 movs r4, r0
8004fbc: 000e movs r6, r1
8004fbe: 001d movs r5, r3
8004fc0: 9201 str r2, [sp, #4]
if (huart == NULL)
8004fc2: 2800 cmp r0, #0
8004fc4: d101 bne.n 8004fca <HAL_RS485Ex_Init+0x12>
return HAL_ERROR;
8004fc6: 2001 movs r0, #1
}
8004fc8: bdfe pop {r1, r2, r3, r4, r5, r6, r7, pc}
if (huart->gState == HAL_UART_STATE_RESET)
8004fca: 0007 movs r7, r0
8004fcc: 3788 adds r7, #136 @ 0x88
8004fce: 683b ldr r3, [r7, #0]
8004fd0: 2b00 cmp r3, #0
8004fd2: d104 bne.n 8004fde <HAL_RS485Ex_Init+0x26>
huart->Lock = HAL_UNLOCKED;
8004fd4: 0002 movs r2, r0
8004fd6: 3284 adds r2, #132 @ 0x84
8004fd8: 7013 strb r3, [r2, #0]
HAL_UART_MspInit(huart);
8004fda: f7fd fb27 bl 800262c <HAL_UART_MspInit>
huart->gState = HAL_UART_STATE_BUSY;
8004fde: 2324 movs r3, #36 @ 0x24
__HAL_UART_DISABLE(huart);
8004fe0: 2101 movs r1, #1
8004fe2: 6822 ldr r2, [r4, #0]
huart->gState = HAL_UART_STATE_BUSY;
8004fe4: 603b str r3, [r7, #0]
__HAL_UART_DISABLE(huart);
8004fe6: 6813 ldr r3, [r2, #0]
8004fe8: 438b bics r3, r1
8004fea: 6013 str r3, [r2, #0]
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
8004fec: 6aa3 ldr r3, [r4, #40] @ 0x28
8004fee: 2b00 cmp r3, #0
8004ff0: d002 beq.n 8004ff8 <HAL_RS485Ex_Init+0x40>
UART_AdvFeatureConfig(huart);
8004ff2: 0020 movs r0, r4
8004ff4: f7ff fdae bl 8004b54 <UART_AdvFeatureConfig>
if (UART_SetConfig(huart) == HAL_ERROR)
8004ff8: 0020 movs r0, r4
8004ffa: f7ff fce9 bl 80049d0 <UART_SetConfig>
8004ffe: 2801 cmp r0, #1
8005000: d0e1 beq.n 8004fc6 <HAL_RS485Ex_Init+0xe>
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
8005002: 2280 movs r2, #128 @ 0x80
8005004: 6823 ldr r3, [r4, #0]
8005006: 01d2 lsls r2, r2, #7
8005008: 6899 ldr r1, [r3, #8]
temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
800500a: 042d lsls r5, r5, #16
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
800500c: 430a orrs r2, r1
800500e: 609a str r2, [r3, #8]
MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
8005010: 689a ldr r2, [r3, #8]
8005012: 490a ldr r1, [pc, #40] @ (800503c <HAL_RS485Ex_Init+0x84>)
return (UART_CheckIdleState(huart));
8005014: 0020 movs r0, r4
MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
8005016: 400a ands r2, r1
8005018: 4332 orrs r2, r6
800501a: 609a str r2, [r3, #8]
temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
800501c: 9a01 ldr r2, [sp, #4]
800501e: 0551 lsls r1, r2, #21
temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
8005020: 430d orrs r5, r1
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
8005022: 681a ldr r2, [r3, #0]
8005024: 4906 ldr r1, [pc, #24] @ (8005040 <HAL_RS485Ex_Init+0x88>)
8005026: 400a ands r2, r1
8005028: 4315 orrs r5, r2
__HAL_UART_ENABLE(huart);
800502a: 2201 movs r2, #1
MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
800502c: 601d str r5, [r3, #0]
__HAL_UART_ENABLE(huart);
800502e: 6819 ldr r1, [r3, #0]
8005030: 430a orrs r2, r1
8005032: 601a str r2, [r3, #0]
return (UART_CheckIdleState(huart));
8005034: f7ff feaa bl 8004d8c <UART_CheckIdleState>
8005038: e7c6 b.n 8004fc8 <HAL_RS485Ex_Init+0x10>
800503a: 46c0 nop @ (mov r8, r8)
800503c: ffff7fff .word 0xffff7fff
8005040: fc00ffff .word 0xfc00ffff
08005044 <HAL_UARTEx_WakeupCallback>:
}
8005044: 4770 bx lr
08005046 <HAL_UARTEx_RxFifoFullCallback>:
__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
8005046: 4770 bx lr
08005048 <HAL_UARTEx_TxFifoEmptyCallback>:
__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
8005048: 4770 bx lr
...
0800504c <HAL_UARTEx_DisableFifoMode>:
{
800504c: b570 push {r4, r5, r6, lr}
__HAL_LOCK(huart);
800504e: 0004 movs r4, r0
8005050: 3484 adds r4, #132 @ 0x84
8005052: 7822 ldrb r2, [r4, #0]
{
8005054: 0003 movs r3, r0
__HAL_LOCK(huart);
8005056: 2002 movs r0, #2
8005058: 2a01 cmp r2, #1
800505a: d011 beq.n 8005080 <HAL_UARTEx_DisableFifoMode+0x34>
huart->gState = HAL_UART_STATE_BUSY;
800505c: 001d movs r5, r3
800505e: 2224 movs r2, #36 @ 0x24
__HAL_UART_DISABLE(huart);
8005060: 2601 movs r6, #1
huart->gState = HAL_UART_STATE_BUSY;
8005062: 3588 adds r5, #136 @ 0x88
8005064: 602a str r2, [r5, #0]
tmpcr1 = READ_REG(huart->Instance->CR1);
8005066: 681a ldr r2, [r3, #0]
8005068: 6811 ldr r1, [r2, #0]
__HAL_UART_DISABLE(huart);
800506a: 6810 ldr r0, [r2, #0]
800506c: 43b0 bics r0, r6
800506e: 6010 str r0, [r2, #0]
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
8005070: 4804 ldr r0, [pc, #16] @ (8005084 <HAL_UARTEx_DisableFifoMode+0x38>)
8005072: 4001 ands r1, r0
huart->FifoMode = UART_FIFOMODE_DISABLE;
8005074: 2000 movs r0, #0
8005076: 6658 str r0, [r3, #100] @ 0x64
huart->gState = HAL_UART_STATE_READY;
8005078: 2320 movs r3, #32
WRITE_REG(huart->Instance->CR1, tmpcr1);
800507a: 6011 str r1, [r2, #0]
huart->gState = HAL_UART_STATE_READY;
800507c: 602b str r3, [r5, #0]
__HAL_UNLOCK(huart);
800507e: 7020 strb r0, [r4, #0]
}
8005080: bd70 pop {r4, r5, r6, pc}
8005082: 46c0 nop @ (mov r8, r8)
8005084: dfffffff .word 0xdfffffff
08005088 <HAL_UARTEx_SetTxFifoThreshold>:
{
8005088: b5f8 push {r3, r4, r5, r6, r7, lr}
__HAL_LOCK(huart);
800508a: 0005 movs r5, r0
800508c: 3584 adds r5, #132 @ 0x84
{
800508e: 000b movs r3, r1
__HAL_LOCK(huart);
8005090: 7829 ldrb r1, [r5, #0]
8005092: 2202 movs r2, #2
8005094: 2901 cmp r1, #1
8005096: d015 beq.n 80050c4 <HAL_UARTEx_SetTxFifoThreshold+0x3c>
huart->gState = HAL_UART_STATE_BUSY;
8005098: 0006 movs r6, r0
__HAL_UART_DISABLE(huart);
800509a: 2101 movs r1, #1
tmpcr1 = READ_REG(huart->Instance->CR1);
800509c: 6804 ldr r4, [r0, #0]
huart->gState = HAL_UART_STATE_BUSY;
800509e: 3688 adds r6, #136 @ 0x88
80050a0: 3222 adds r2, #34 @ 0x22
80050a2: 6032 str r2, [r6, #0]
tmpcr1 = READ_REG(huart->Instance->CR1);
80050a4: 6827 ldr r7, [r4, #0]
__HAL_UART_DISABLE(huart);
80050a6: 6822 ldr r2, [r4, #0]
80050a8: 438a bics r2, r1
80050aa: 6022 str r2, [r4, #0]
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
80050ac: 68a1 ldr r1, [r4, #8]
80050ae: 00c9 lsls r1, r1, #3
80050b0: 08c9 lsrs r1, r1, #3
80050b2: 4319 orrs r1, r3
80050b4: 60a1 str r1, [r4, #8]
UARTEx_SetNbDataToProcess(huart);
80050b6: f7ff ff57 bl 8004f68 <UARTEx_SetNbDataToProcess>
huart->gState = HAL_UART_STATE_READY;
80050ba: 2320 movs r3, #32
__HAL_UNLOCK(huart);
80050bc: 2200 movs r2, #0
WRITE_REG(huart->Instance->CR1, tmpcr1);
80050be: 6027 str r7, [r4, #0]
huart->gState = HAL_UART_STATE_READY;
80050c0: 6033 str r3, [r6, #0]
__HAL_UNLOCK(huart);
80050c2: 702a strb r2, [r5, #0]
}
80050c4: 0010 movs r0, r2
80050c6: bdf8 pop {r3, r4, r5, r6, r7, pc}
080050c8 <HAL_UARTEx_SetRxFifoThreshold>:
{
80050c8: b5f8 push {r3, r4, r5, r6, r7, lr}
__HAL_LOCK(huart);
80050ca: 0005 movs r5, r0
80050cc: 3584 adds r5, #132 @ 0x84
{
80050ce: 000a movs r2, r1
__HAL_LOCK(huart);
80050d0: 7829 ldrb r1, [r5, #0]
80050d2: 2302 movs r3, #2
80050d4: 2901 cmp r1, #1
80050d6: d015 beq.n 8005104 <HAL_UARTEx_SetRxFifoThreshold+0x3c>
huart->gState = HAL_UART_STATE_BUSY;
80050d8: 0006 movs r6, r0
__HAL_UART_DISABLE(huart);
80050da: 2101 movs r1, #1
tmpcr1 = READ_REG(huart->Instance->CR1);
80050dc: 6804 ldr r4, [r0, #0]
huart->gState = HAL_UART_STATE_BUSY;
80050de: 3688 adds r6, #136 @ 0x88
80050e0: 3322 adds r3, #34 @ 0x22
80050e2: 6033 str r3, [r6, #0]
tmpcr1 = READ_REG(huart->Instance->CR1);
80050e4: 6827 ldr r7, [r4, #0]
__HAL_UART_DISABLE(huart);
80050e6: 6823 ldr r3, [r4, #0]
80050e8: 438b bics r3, r1
80050ea: 6023 str r3, [r4, #0]
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
80050ec: 68a1 ldr r1, [r4, #8]
80050ee: 4b06 ldr r3, [pc, #24] @ (8005108 <HAL_UARTEx_SetRxFifoThreshold+0x40>)
80050f0: 4019 ands r1, r3
80050f2: 4311 orrs r1, r2
80050f4: 60a1 str r1, [r4, #8]
UARTEx_SetNbDataToProcess(huart);
80050f6: f7ff ff37 bl 8004f68 <UARTEx_SetNbDataToProcess>
huart->gState = HAL_UART_STATE_READY;
80050fa: 2320 movs r3, #32
WRITE_REG(huart->Instance->CR1, tmpcr1);
80050fc: 6027 str r7, [r4, #0]
huart->gState = HAL_UART_STATE_READY;
80050fe: 6033 str r3, [r6, #0]
__HAL_UNLOCK(huart);
8005100: 2300 movs r3, #0
8005102: 702b strb r3, [r5, #0]
}
8005104: 0018 movs r0, r3
8005106: bdf8 pop {r3, r4, r5, r6, r7, pc}
8005108: f1ffffff .word 0xf1ffffff
0800510c <HAL_UARTEx_ReceiveToIdle_DMA>:
if (huart->RxState == HAL_UART_STATE_READY)
800510c: 0003 movs r3, r0
800510e: 338c adds r3, #140 @ 0x8c
8005110: 681b ldr r3, [r3, #0]
{
8005112: b570 push {r4, r5, r6, lr}
8005114: 0004 movs r4, r0
return HAL_BUSY;
8005116: 2002 movs r0, #2
if (huart->RxState == HAL_UART_STATE_READY)
8005118: 2b20 cmp r3, #32
800511a: d102 bne.n 8005122 <HAL_UARTEx_ReceiveToIdle_DMA+0x16>
if ((pData == NULL) || (Size == 0U))
800511c: 2900 cmp r1, #0
800511e: d101 bne.n 8005124 <HAL_UARTEx_ReceiveToIdle_DMA+0x18>
return HAL_ERROR;
8005120: 2001 movs r0, #1
}
8005122: bd70 pop {r4, r5, r6, pc}
if ((pData == NULL) || (Size == 0U))
8005124: 2a00 cmp r2, #0
8005126: d0fb beq.n 8005120 <HAL_UARTEx_ReceiveToIdle_DMA+0x14>
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8005128: 2080 movs r0, #128 @ 0x80
800512a: 68a5 ldr r5, [r4, #8]
800512c: 2301 movs r3, #1
800512e: 0140 lsls r0, r0, #5
8005130: 4285 cmp r5, r0
8005132: d104 bne.n 800513e <HAL_UARTEx_ReceiveToIdle_DMA+0x32>
8005134: 6920 ldr r0, [r4, #16]
8005136: 2800 cmp r0, #0
8005138: d101 bne.n 800513e <HAL_UARTEx_ReceiveToIdle_DMA+0x32>
if ((((uint32_t)pData) & 1U) != 0U)
800513a: 4219 tst r1, r3
800513c: d1f0 bne.n 8005120 <HAL_UARTEx_ReceiveToIdle_DMA+0x14>
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
800513e: 66e3 str r3, [r4, #108] @ 0x6c
huart->RxEventType = HAL_UART_RXEVENT_TC;
8005140: 2300 movs r3, #0
status = UART_Start_Receive_DMA(huart, pData, Size);
8005142: 0020 movs r0, r4
huart->RxEventType = HAL_UART_RXEVENT_TC;
8005144: 6723 str r3, [r4, #112] @ 0x70
status = UART_Start_Receive_DMA(huart, pData, Size);
8005146: f7ff feb9 bl 8004ebc <UART_Start_Receive_DMA>
if (status == HAL_OK)
800514a: 2800 cmp r0, #0
800514c: d1e9 bne.n 8005122 <HAL_UARTEx_ReceiveToIdle_DMA+0x16>
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
800514e: 6ee2 ldr r2, [r4, #108] @ 0x6c
8005150: 2a01 cmp r2, #1
8005152: d1e5 bne.n 8005120 <HAL_UARTEx_ReceiveToIdle_DMA+0x14>
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
8005154: 2310 movs r3, #16
8005156: 6821 ldr r1, [r4, #0]
8005158: 620b str r3, [r1, #32]
__ASM volatile ("MRS %0, primask" : "=r" (result) );
800515a: f3ef 8110 mrs r1, PRIMASK
__ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
800515e: f382 8810 msr PRIMASK, r2
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
8005162: 6822 ldr r2, [r4, #0]
8005164: 6814 ldr r4, [r2, #0]
8005166: 4323 orrs r3, r4
8005168: 6013 str r3, [r2, #0]
800516a: f381 8810 msr PRIMASK, r1
}
800516e: e7d8 b.n 8005122 <HAL_UARTEx_ReceiveToIdle_DMA+0x16>
08005170 <memcmp>:
8005170: b530 push {r4, r5, lr}
8005172: 2400 movs r4, #0
8005174: 3901 subs r1, #1
8005176: 42a2 cmp r2, r4
8005178: d101 bne.n 800517e <memcmp+0xe>
800517a: 2000 movs r0, #0
800517c: e005 b.n 800518a <memcmp+0x1a>
800517e: 5d03 ldrb r3, [r0, r4]
8005180: 3401 adds r4, #1
8005182: 5d0d ldrb r5, [r1, r4]
8005184: 42ab cmp r3, r5
8005186: d0f6 beq.n 8005176 <memcmp+0x6>
8005188: 1b58 subs r0, r3, r5
800518a: bd30 pop {r4, r5, pc}
0800518c <memset>:
800518c: 0003 movs r3, r0
800518e: 1882 adds r2, r0, r2
8005190: 4293 cmp r3, r2
8005192: d100 bne.n 8005196 <memset+0xa>
8005194: 4770 bx lr
8005196: 7019 strb r1, [r3, #0]
8005198: 3301 adds r3, #1
800519a: e7f9 b.n 8005190 <memset+0x4>
0800519c <__libc_init_array>:
800519c: b570 push {r4, r5, r6, lr}
800519e: 2600 movs r6, #0
80051a0: 4c0c ldr r4, [pc, #48] @ (80051d4 <__libc_init_array+0x38>)
80051a2: 4d0d ldr r5, [pc, #52] @ (80051d8 <__libc_init_array+0x3c>)
80051a4: 1b64 subs r4, r4, r5
80051a6: 10a4 asrs r4, r4, #2
80051a8: 42a6 cmp r6, r4
80051aa: d109 bne.n 80051c0 <__libc_init_array+0x24>
80051ac: 2600 movs r6, #0
80051ae: f000 f823 bl 80051f8 <_init>
80051b2: 4c0a ldr r4, [pc, #40] @ (80051dc <__libc_init_array+0x40>)
80051b4: 4d0a ldr r5, [pc, #40] @ (80051e0 <__libc_init_array+0x44>)
80051b6: 1b64 subs r4, r4, r5
80051b8: 10a4 asrs r4, r4, #2
80051ba: 42a6 cmp r6, r4
80051bc: d105 bne.n 80051ca <__libc_init_array+0x2e>
80051be: bd70 pop {r4, r5, r6, pc}
80051c0: 00b3 lsls r3, r6, #2
80051c2: 58eb ldr r3, [r5, r3]
80051c4: 4798 blx r3
80051c6: 3601 adds r6, #1
80051c8: e7ee b.n 80051a8 <__libc_init_array+0xc>
80051ca: 00b3 lsls r3, r6, #2
80051cc: 58eb ldr r3, [r5, r3]
80051ce: 4798 blx r3
80051d0: 3601 adds r6, #1
80051d2: e7f2 b.n 80051ba <__libc_init_array+0x1e>
80051d4: 080052c0 .word 0x080052c0
80051d8: 080052c0 .word 0x080052c0
80051dc: 080052c4 .word 0x080052c4
80051e0: 080052c0 .word 0x080052c0
080051e4 <memcpy>:
80051e4: 2300 movs r3, #0
80051e6: b510 push {r4, lr}
80051e8: 429a cmp r2, r3
80051ea: d100 bne.n 80051ee <memcpy+0xa>
80051ec: bd10 pop {r4, pc}
80051ee: 5ccc ldrb r4, [r1, r3]
80051f0: 54c4 strb r4, [r0, r3]
80051f2: 3301 adds r3, #1
80051f4: e7f8 b.n 80051e8 <memcpy+0x4>
...
080051f8 <_init>:
80051f8: b5f8 push {r3, r4, r5, r6, r7, lr}
80051fa: 46c0 nop @ (mov r8, r8)
80051fc: bcf8 pop {r3, r4, r5, r6, r7}
80051fe: bc08 pop {r3}
8005200: 469e mov lr, r3
8005202: 4770 bx lr
08005204 <_fini>:
8005204: b5f8 push {r3, r4, r5, r6, r7, lr}
8005206: 46c0 nop @ (mov r8, r8)
8005208: bcf8 pop {r3, r4, r5, r6, r7}
800520a: bc08 pop {r3}
800520c: 469e mov lr, r3
800520e: 4770 bx lr
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