B4L/C64PSU
5
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
e9775f2ce78dc286cf8bec8b3a4b339598700a0a
C64PSU/code/Debug/C64PSU.list
janik e9775f2ce7
All checks were successful
KiBot PCB Generation / generate (push) Successful in 5m40s
Details
KiBot PCB Generation / deploy (push) Successful in 28s
Details
seperated into transformer / experimental
2025-12-16 17:16:26 +07:00

25732 lines
973 KiB
Plaintext
Raw Blame History

C64PSU.elf: file format elf32-littlearm
Sections:
Idx Name Size VMA LMA File off Algn
0 .isr_vector 000001d8 08000000 08000000 00001000 2**0
CONTENTS, ALLOC, LOAD, READONLY, DATA
1 .text 000095ec 080001d8 080001d8 000011d8 2**2
CONTENTS, ALLOC, LOAD, READONLY, CODE
2 .rodata 0000007c 080097c4 080097c4 0000a7c4 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
3 .ARM.extab 00000000 08009840 08009840 0000b00c 2**0
CONTENTS, READONLY
4 .ARM 00000008 08009840 08009840 0000a840 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
5 .preinit_array 00000000 08009848 08009848 0000b00c 2**0
CONTENTS, ALLOC, LOAD, DATA
6 .init_array 00000004 08009848 08009848 0000a848 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
7 .fini_array 00000004 0800984c 0800984c 0000a84c 2**2
CONTENTS, ALLOC, LOAD, READONLY, DATA
8 .data 0000000c 20000000 08009850 0000b000 2**2
CONTENTS, ALLOC, LOAD, DATA
9 .bss 000004bc 2000000c 0800985c 0000b00c 2**2
ALLOC
10 ._user_heap_stack 00000600 200004c8 0800985c 0000b4c8 2**0
ALLOC
11 .ARM.attributes 00000030 00000000 00000000 0000b00c 2**0
CONTENTS, READONLY
12 .debug_info 000208d0 00000000 00000000 0000b03c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
13 .debug_abbrev 000035bf 00000000 00000000 0002b90c 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
14 .debug_aranges 00001dd0 00000000 00000000 0002eed0 2**3
CONTENTS, READONLY, DEBUGGING, OCTETS
15 .debug_rnglists 0000175a 00000000 00000000 00030ca0 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
16 .debug_macro 0002b9af 00000000 00000000 000323fa 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
17 .debug_line 00020209 00000000 00000000 0005dda9 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
18 .debug_str 0013b287 00000000 00000000 0007dfb2 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
19 .comment 00000043 00000000 00000000 001b9239 2**0
CONTENTS, READONLY
20 .debug_frame 0000842c 00000000 00000000 001b927c 2**2
CONTENTS, READONLY, DEBUGGING, OCTETS
21 .debug_line_str 00000049 00000000 00000000 001c16a8 2**0
CONTENTS, READONLY, DEBUGGING, OCTETS
Disassembly of section .text:
080001d8 <__do_global_dtors_aux>:
80001d8: b510 push {r4, lr}
80001da: 4c05 ldr r4, [pc, #20] @ (80001f0 <__do_global_dtors_aux+0x18>)
80001dc: 7823 ldrb r3, [r4, #0]
80001de: b933 cbnz r3, 80001ee <__do_global_dtors_aux+0x16>
80001e0: 4b04 ldr r3, [pc, #16] @ (80001f4 <__do_global_dtors_aux+0x1c>)
80001e2: b113 cbz r3, 80001ea <__do_global_dtors_aux+0x12>
80001e4: 4804 ldr r0, [pc, #16] @ (80001f8 <__do_global_dtors_aux+0x20>)
80001e6: f3af 8000 nop.w
80001ea: 2301 movs r3, #1
80001ec: 7023 strb r3, [r4, #0]
80001ee: bd10 pop {r4, pc}
80001f0: 2000000c .word 0x2000000c
80001f4: 00000000 .word 0x00000000
80001f8: 080097ac .word 0x080097ac
080001fc <frame_dummy>:
80001fc: b508 push {r3, lr}
80001fe: 4b03 ldr r3, [pc, #12] @ (800020c <frame_dummy+0x10>)
8000200: b11b cbz r3, 800020a <frame_dummy+0xe>
8000202: 4903 ldr r1, [pc, #12] @ (8000210 <frame_dummy+0x14>)
8000204: 4803 ldr r0, [pc, #12] @ (8000214 <frame_dummy+0x18>)
8000206: f3af 8000 nop.w
800020a: bd08 pop {r3, pc}
800020c: 00000000 .word 0x00000000
8000210: 20000010 .word 0x20000010
8000214: 080097ac .word 0x080097ac
08000218 <__aeabi_uldivmod>:
8000218: b953 cbnz r3, 8000230 <__aeabi_uldivmod+0x18>
800021a: b94a cbnz r2, 8000230 <__aeabi_uldivmod+0x18>
800021c: 2900 cmp r1, #0
800021e: bf08 it eq
8000220: 2800 cmpeq r0, #0
8000222: bf1c itt ne
8000224: f04f 31ff movne.w r1, #4294967295
8000228: f04f 30ff movne.w r0, #4294967295
800022c: f000 b988 b.w 8000540 <__aeabi_idiv0>
8000230: f1ad 0c08 sub.w ip, sp, #8
8000234: e96d ce04 strd ip, lr, [sp, #-16]!
8000238: f000 f806 bl 8000248 <__udivmoddi4>
800023c: f8dd e004 ldr.w lr, [sp, #4]
8000240: e9dd 2302 ldrd r2, r3, [sp, #8]
8000244: b004 add sp, #16
8000246: 4770 bx lr
08000248 <__udivmoddi4>:
8000248: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr}
800024c: 9d08 ldr r5, [sp, #32]
800024e: 468e mov lr, r1
8000250: 4604 mov r4, r0
8000252: 4688 mov r8, r1
8000254: 2b00 cmp r3, #0
8000256: d14a bne.n 80002ee <__udivmoddi4+0xa6>
8000258: 428a cmp r2, r1
800025a: 4617 mov r7, r2
800025c: d962 bls.n 8000324 <__udivmoddi4+0xdc>
800025e: fab2 f682 clz r6, r2
8000262: b14e cbz r6, 8000278 <__udivmoddi4+0x30>
8000264: f1c6 0320 rsb r3, r6, #32
8000268: fa01 f806 lsl.w r8, r1, r6
800026c: fa20 f303 lsr.w r3, r0, r3
8000270: 40b7 lsls r7, r6
8000272: ea43 0808 orr.w r8, r3, r8
8000276: 40b4 lsls r4, r6
8000278: ea4f 4e17 mov.w lr, r7, lsr #16
800027c: fa1f fc87 uxth.w ip, r7
8000280: fbb8 f1fe udiv r1, r8, lr
8000284: 0c23 lsrs r3, r4, #16
8000286: fb0e 8811 mls r8, lr, r1, r8
800028a: ea43 4308 orr.w r3, r3, r8, lsl #16
800028e: fb01 f20c mul.w r2, r1, ip
8000292: 429a cmp r2, r3
8000294: d909 bls.n 80002aa <__udivmoddi4+0x62>
8000296: 18fb adds r3, r7, r3
8000298: f101 30ff add.w r0, r1, #4294967295
800029c: f080 80ea bcs.w 8000474 <__udivmoddi4+0x22c>
80002a0: 429a cmp r2, r3
80002a2: f240 80e7 bls.w 8000474 <__udivmoddi4+0x22c>
80002a6: 3902 subs r1, #2
80002a8: 443b add r3, r7
80002aa: 1a9a subs r2, r3, r2
80002ac: b2a3 uxth r3, r4
80002ae: fbb2 f0fe udiv r0, r2, lr
80002b2: fb0e 2210 mls r2, lr, r0, r2
80002b6: ea43 4302 orr.w r3, r3, r2, lsl #16
80002ba: fb00 fc0c mul.w ip, r0, ip
80002be: 459c cmp ip, r3
80002c0: d909 bls.n 80002d6 <__udivmoddi4+0x8e>
80002c2: 18fb adds r3, r7, r3
80002c4: f100 32ff add.w r2, r0, #4294967295
80002c8: f080 80d6 bcs.w 8000478 <__udivmoddi4+0x230>
80002cc: 459c cmp ip, r3
80002ce: f240 80d3 bls.w 8000478 <__udivmoddi4+0x230>
80002d2: 443b add r3, r7
80002d4: 3802 subs r0, #2
80002d6: ea40 4001 orr.w r0, r0, r1, lsl #16
80002da: eba3 030c sub.w r3, r3, ip
80002de: 2100 movs r1, #0
80002e0: b11d cbz r5, 80002ea <__udivmoddi4+0xa2>
80002e2: 40f3 lsrs r3, r6
80002e4: 2200 movs r2, #0
80002e6: e9c5 3200 strd r3, r2, [r5]
80002ea: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc}
80002ee: 428b cmp r3, r1
80002f0: d905 bls.n 80002fe <__udivmoddi4+0xb6>
80002f2: b10d cbz r5, 80002f8 <__udivmoddi4+0xb0>
80002f4: e9c5 0100 strd r0, r1, [r5]
80002f8: 2100 movs r1, #0
80002fa: 4608 mov r0, r1
80002fc: e7f5 b.n 80002ea <__udivmoddi4+0xa2>
80002fe: fab3 f183 clz r1, r3
8000302: 2900 cmp r1, #0
8000304: d146 bne.n 8000394 <__udivmoddi4+0x14c>
8000306: 4573 cmp r3, lr
8000308: d302 bcc.n 8000310 <__udivmoddi4+0xc8>
800030a: 4282 cmp r2, r0
800030c: f200 8105 bhi.w 800051a <__udivmoddi4+0x2d2>
8000310: 1a84 subs r4, r0, r2
8000312: eb6e 0203 sbc.w r2, lr, r3
8000316: 2001 movs r0, #1
8000318: 4690 mov r8, r2
800031a: 2d00 cmp r5, #0
800031c: d0e5 beq.n 80002ea <__udivmoddi4+0xa2>
800031e: e9c5 4800 strd r4, r8, [r5]
8000322: e7e2 b.n 80002ea <__udivmoddi4+0xa2>
8000324: 2a00 cmp r2, #0
8000326: f000 8090 beq.w 800044a <__udivmoddi4+0x202>
800032a: fab2 f682 clz r6, r2
800032e: 2e00 cmp r6, #0
8000330: f040 80a4 bne.w 800047c <__udivmoddi4+0x234>
8000334: 1a8a subs r2, r1, r2
8000336: 0c03 lsrs r3, r0, #16
8000338: ea4f 4e17 mov.w lr, r7, lsr #16
800033c: b280 uxth r0, r0
800033e: b2bc uxth r4, r7
8000340: 2101 movs r1, #1
8000342: fbb2 fcfe udiv ip, r2, lr
8000346: fb0e 221c mls r2, lr, ip, r2
800034a: ea43 4302 orr.w r3, r3, r2, lsl #16
800034e: fb04 f20c mul.w r2, r4, ip
8000352: 429a cmp r2, r3
8000354: d907 bls.n 8000366 <__udivmoddi4+0x11e>
8000356: 18fb adds r3, r7, r3
8000358: f10c 38ff add.w r8, ip, #4294967295
800035c: d202 bcs.n 8000364 <__udivmoddi4+0x11c>
800035e: 429a cmp r2, r3
8000360: f200 80e0 bhi.w 8000524 <__udivmoddi4+0x2dc>
8000364: 46c4 mov ip, r8
8000366: 1a9b subs r3, r3, r2
8000368: fbb3 f2fe udiv r2, r3, lr
800036c: fb0e 3312 mls r3, lr, r2, r3
8000370: ea40 4303 orr.w r3, r0, r3, lsl #16
8000374: fb02 f404 mul.w r4, r2, r4
8000378: 429c cmp r4, r3
800037a: d907 bls.n 800038c <__udivmoddi4+0x144>
800037c: 18fb adds r3, r7, r3
800037e: f102 30ff add.w r0, r2, #4294967295
8000382: d202 bcs.n 800038a <__udivmoddi4+0x142>
8000384: 429c cmp r4, r3
8000386: f200 80ca bhi.w 800051e <__udivmoddi4+0x2d6>
800038a: 4602 mov r2, r0
800038c: 1b1b subs r3, r3, r4
800038e: ea42 400c orr.w r0, r2, ip, lsl #16
8000392: e7a5 b.n 80002e0 <__udivmoddi4+0x98>
8000394: f1c1 0620 rsb r6, r1, #32
8000398: 408b lsls r3, r1
800039a: fa22 f706 lsr.w r7, r2, r6
800039e: 431f orrs r7, r3
80003a0: fa0e f401 lsl.w r4, lr, r1
80003a4: fa20 f306 lsr.w r3, r0, r6
80003a8: fa2e fe06 lsr.w lr, lr, r6
80003ac: ea4f 4917 mov.w r9, r7, lsr #16
80003b0: 4323 orrs r3, r4
80003b2: fa00 f801 lsl.w r8, r0, r1
80003b6: fa1f fc87 uxth.w ip, r7
80003ba: fbbe f0f9 udiv r0, lr, r9
80003be: 0c1c lsrs r4, r3, #16
80003c0: fb09 ee10 mls lr, r9, r0, lr
80003c4: ea44 440e orr.w r4, r4, lr, lsl #16
80003c8: fb00 fe0c mul.w lr, r0, ip
80003cc: 45a6 cmp lr, r4
80003ce: fa02 f201 lsl.w r2, r2, r1
80003d2: d909 bls.n 80003e8 <__udivmoddi4+0x1a0>
80003d4: 193c adds r4, r7, r4
80003d6: f100 3aff add.w sl, r0, #4294967295
80003da: f080 809c bcs.w 8000516 <__udivmoddi4+0x2ce>
80003de: 45a6 cmp lr, r4
80003e0: f240 8099 bls.w 8000516 <__udivmoddi4+0x2ce>
80003e4: 3802 subs r0, #2
80003e6: 443c add r4, r7
80003e8: eba4 040e sub.w r4, r4, lr
80003ec: fa1f fe83 uxth.w lr, r3
80003f0: fbb4 f3f9 udiv r3, r4, r9
80003f4: fb09 4413 mls r4, r9, r3, r4
80003f8: ea4e 4404 orr.w r4, lr, r4, lsl #16
80003fc: fb03 fc0c mul.w ip, r3, ip
8000400: 45a4 cmp ip, r4
8000402: d908 bls.n 8000416 <__udivmoddi4+0x1ce>
8000404: 193c adds r4, r7, r4
8000406: f103 3eff add.w lr, r3, #4294967295
800040a: f080 8082 bcs.w 8000512 <__udivmoddi4+0x2ca>
800040e: 45a4 cmp ip, r4
8000410: d97f bls.n 8000512 <__udivmoddi4+0x2ca>
8000412: 3b02 subs r3, #2
8000414: 443c add r4, r7
8000416: ea43 4000 orr.w r0, r3, r0, lsl #16
800041a: eba4 040c sub.w r4, r4, ip
800041e: fba0 ec02 umull lr, ip, r0, r2
8000422: 4564 cmp r4, ip
8000424: 4673 mov r3, lr
8000426: 46e1 mov r9, ip
8000428: d362 bcc.n 80004f0 <__udivmoddi4+0x2a8>
800042a: d05f beq.n 80004ec <__udivmoddi4+0x2a4>
800042c: b15d cbz r5, 8000446 <__udivmoddi4+0x1fe>
800042e: ebb8 0203 subs.w r2, r8, r3
8000432: eb64 0409 sbc.w r4, r4, r9
8000436: fa04 f606 lsl.w r6, r4, r6
800043a: fa22 f301 lsr.w r3, r2, r1
800043e: 431e orrs r6, r3
8000440: 40cc lsrs r4, r1
8000442: e9c5 6400 strd r6, r4, [r5]
8000446: 2100 movs r1, #0
8000448: e74f b.n 80002ea <__udivmoddi4+0xa2>
800044a: fbb1 fcf2 udiv ip, r1, r2
800044e: 0c01 lsrs r1, r0, #16
8000450: ea41 410e orr.w r1, r1, lr, lsl #16
8000454: b280 uxth r0, r0
8000456: ea40 4201 orr.w r2, r0, r1, lsl #16
800045a: 463b mov r3, r7
800045c: 4638 mov r0, r7
800045e: 463c mov r4, r7
8000460: 46b8 mov r8, r7
8000462: 46be mov lr, r7
8000464: 2620 movs r6, #32
8000466: fbb1 f1f7 udiv r1, r1, r7
800046a: eba2 0208 sub.w r2, r2, r8
800046e: ea41 410c orr.w r1, r1, ip, lsl #16
8000472: e766 b.n 8000342 <__udivmoddi4+0xfa>
8000474: 4601 mov r1, r0
8000476: e718 b.n 80002aa <__udivmoddi4+0x62>
8000478: 4610 mov r0, r2
800047a: e72c b.n 80002d6 <__udivmoddi4+0x8e>
800047c: f1c6 0220 rsb r2, r6, #32
8000480: fa2e f302 lsr.w r3, lr, r2
8000484: 40b7 lsls r7, r6
8000486: 40b1 lsls r1, r6
8000488: fa20 f202 lsr.w r2, r0, r2
800048c: ea4f 4e17 mov.w lr, r7, lsr #16
8000490: 430a orrs r2, r1
8000492: fbb3 f8fe udiv r8, r3, lr
8000496: b2bc uxth r4, r7
8000498: fb0e 3318 mls r3, lr, r8, r3
800049c: 0c11 lsrs r1, r2, #16
800049e: ea41 4103 orr.w r1, r1, r3, lsl #16
80004a2: fb08 f904 mul.w r9, r8, r4
80004a6: 40b0 lsls r0, r6
80004a8: 4589 cmp r9, r1
80004aa: ea4f 4310 mov.w r3, r0, lsr #16
80004ae: b280 uxth r0, r0
80004b0: d93e bls.n 8000530 <__udivmoddi4+0x2e8>
80004b2: 1879 adds r1, r7, r1
80004b4: f108 3cff add.w ip, r8, #4294967295
80004b8: d201 bcs.n 80004be <__udivmoddi4+0x276>
80004ba: 4589 cmp r9, r1
80004bc: d81f bhi.n 80004fe <__udivmoddi4+0x2b6>
80004be: eba1 0109 sub.w r1, r1, r9
80004c2: fbb1 f9fe udiv r9, r1, lr
80004c6: fb09 f804 mul.w r8, r9, r4
80004ca: fb0e 1119 mls r1, lr, r9, r1
80004ce: b292 uxth r2, r2
80004d0: ea42 4201 orr.w r2, r2, r1, lsl #16
80004d4: 4542 cmp r2, r8
80004d6: d229 bcs.n 800052c <__udivmoddi4+0x2e4>
80004d8: 18ba adds r2, r7, r2
80004da: f109 31ff add.w r1, r9, #4294967295
80004de: d2c4 bcs.n 800046a <__udivmoddi4+0x222>
80004e0: 4542 cmp r2, r8
80004e2: d2c2 bcs.n 800046a <__udivmoddi4+0x222>
80004e4: f1a9 0102 sub.w r1, r9, #2
80004e8: 443a add r2, r7
80004ea: e7be b.n 800046a <__udivmoddi4+0x222>
80004ec: 45f0 cmp r8, lr
80004ee: d29d bcs.n 800042c <__udivmoddi4+0x1e4>
80004f0: ebbe 0302 subs.w r3, lr, r2
80004f4: eb6c 0c07 sbc.w ip, ip, r7
80004f8: 3801 subs r0, #1
80004fa: 46e1 mov r9, ip
80004fc: e796 b.n 800042c <__udivmoddi4+0x1e4>
80004fe: eba7 0909 sub.w r9, r7, r9
8000502: 4449 add r1, r9
8000504: f1a8 0c02 sub.w ip, r8, #2
8000508: fbb1 f9fe udiv r9, r1, lr
800050c: fb09 f804 mul.w r8, r9, r4
8000510: e7db b.n 80004ca <__udivmoddi4+0x282>
8000512: 4673 mov r3, lr
8000514: e77f b.n 8000416 <__udivmoddi4+0x1ce>
8000516: 4650 mov r0, sl
8000518: e766 b.n 80003e8 <__udivmoddi4+0x1a0>
800051a: 4608 mov r0, r1
800051c: e6fd b.n 800031a <__udivmoddi4+0xd2>
800051e: 443b add r3, r7
8000520: 3a02 subs r2, #2
8000522: e733 b.n 800038c <__udivmoddi4+0x144>
8000524: f1ac 0c02 sub.w ip, ip, #2
8000528: 443b add r3, r7
800052a: e71c b.n 8000366 <__udivmoddi4+0x11e>
800052c: 4649 mov r1, r9
800052e: e79c b.n 800046a <__udivmoddi4+0x222>
8000530: eba1 0109 sub.w r1, r1, r9
8000534: 46c4 mov ip, r8
8000536: fbb1 f9fe udiv r9, r1, lr
800053a: fb09 f804 mul.w r8, r9, r4
800053e: e7c4 b.n 80004ca <__udivmoddi4+0x282>
08000540 <__aeabi_idiv0>:
8000540: 4770 bx lr
8000542: bf00 nop
08000544 <main>:
/**
* @brief The application entry point.
* @retval int
*/
int main(void)
{
8000544: b580 push {r7, lr}
8000546: b086 sub sp, #24
8000548: af00 add r7, sp, #0
/* USER CODE END 1 */
/* MCU Configuration--------------------------------------------------------*/
/* Reset of all peripherals, Initializes the Flash interface and the Systick. */
HAL_Init();
800054a: f001 fa6a bl 8001a22 <HAL_Init>
/* USER CODE BEGIN Init */
/* USER CODE END Init */
/* Configure the system clock */
SystemClock_Config();
800054e: f000 f897 bl 8000680 <SystemClock_Config>
/* USER CODE BEGIN SysInit */
/* USER CODE END SysInit */
/* Initialize all configured peripherals */
MX_GPIO_Init();
8000552: f000 fdab bl 80010ac <MX_GPIO_Init>
MX_DMA_Init();
8000556: f000 fd85 bl 8001064 <MX_DMA_Init>
MX_TIM1_Init();
800055a: f000 fc71 bl 8000e40 <MX_TIM1_Init>
MX_CORDIC_Init();
800055e: f000 fa07 bl 8000970 <MX_CORDIC_Init>
MX_FMAC_Init();
8000562: f000 fa8d bl 8000a80 <MX_FMAC_Init>
MX_ADC3_Init();
8000566: f000 f8d5 bl 8000714 <MX_ADC3_Init>
MX_ADC4_Init();
800056a: f000 f94d bl 8000808 <MX_ADC4_Init>
MX_COMP5_Init();
800056e: f000 f9b1 bl 80008d4 <MX_COMP5_Init>
MX_COMP7_Init();
8000572: f000 f9d5 bl 8000920 <MX_COMP7_Init>
MX_DAC1_Init();
8000576: f000 fa0f bl 8000998 <MX_DAC1_Init>
MX_DAC4_Init();
800057a: f000 fa47 bl 8000a0c <MX_DAC4_Init>
MX_HRTIM1_Init();
800057e: f000 fa93 bl 8000aa8 <MX_HRTIM1_Init>
MX_USART1_UART_Init();
8000582: f000 fd23 bl 8000fcc <MX_USART1_UART_Init>
MX_TIM3_Init();
8000586: f000 fcad bl 8000ee4 <MX_TIM3_Init>
/* USER CODE BEGIN 2 */
HAL_ADCEx_Calibration_Start(&hadc3, ADC_SINGLE_ENDED);
800058a: 217f movs r1, #127 @ 0x7f
800058c: 4831 ldr r0, [pc, #196] @ (8000654 <main+0x110>)
800058e: f002 fe35 bl 80031fc <HAL_ADCEx_Calibration_Start>
HAL_ADCEx_Calibration_Start(&hadc4, ADC_SINGLE_ENDED);
8000592: 217f movs r1, #127 @ 0x7f
8000594: 4830 ldr r0, [pc, #192] @ (8000658 <main+0x114>)
8000596: f002 fe31 bl 80031fc <HAL_ADCEx_Calibration_Start>
HAL_ADC_Start_DMA(&hadc3,&current,1);
800059a: 2201 movs r2, #1
800059c: 492f ldr r1, [pc, #188] @ (800065c <main+0x118>)
800059e: 482d ldr r0, [pc, #180] @ (8000654 <main+0x110>)
80005a0: f001 ff1e bl 80023e0 <HAL_ADC_Start_DMA>
HAL_ADC_Start_DMA(&hadc4,&voltage,1);
80005a4: 2201 movs r2, #1
80005a6: 492e ldr r1, [pc, #184] @ (8000660 <main+0x11c>)
80005a8: 482b ldr r0, [pc, #172] @ (8000658 <main+0x114>)
80005aa: f001 ff19 bl 80023e0 <HAL_ADC_Start_DMA>
// HAL_DAC_SetValue(&hdac1, DAC_CHANNEL_2, DAC_ALIGN_12B_R, );//voltage
// HAL_DAC_SetValue(&hdac4, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 3500);//current
// HAL_DAC_Start(&hdac1, DAC_CHANNEL_2);
HAL_DAC_Start(&hdac4, DAC_CHANNEL_1); //current
80005ae: 2100 movs r1, #0
80005b0: 482c ldr r0, [pc, #176] @ (8000664 <main+0x120>)
80005b2: f003 fcc3 bl 8003f3c <HAL_DAC_Start>
HAL_DAC_SetValue(&hdac4, DAC_CHANNEL_1, DAC_ALIGN_12B_R, 3500);//current
80005b6: f640 53ac movw r3, #3500 @ 0xdac
80005ba: 2200 movs r2, #0
80005bc: 2100 movs r1, #0
80005be: 4829 ldr r0, [pc, #164] @ (8000664 <main+0x120>)
80005c0: f003 fd28 bl 8004014 <HAL_DAC_SetValue>
HAL_Delay(500);
80005c4: f44f 70fa mov.w r0, #500 @ 0x1f4
80005c8: f001 fa9c bl 8001b04 <HAL_Delay>
HAL_COMP_Start(&hcomp7);//current
80005cc: 4826 ldr r0, [pc, #152] @ (8000668 <main+0x124>)
80005ce: f003 fa95 bl 8003afc <HAL_COMP_Start>
/* USER CODE END 2 */
/* Infinite loop */
/* USER CODE BEGIN WHILE */
HAL_HRTIM_WaveformCountStart(&hhrtim1,HRTIM_TIMERID_MASTER|HRTIM_TIMERID_TIMER_A|HRTIM_TIMERID_TIMER_B);
80005d2: f44f 21e0 mov.w r1, #458752 @ 0x70000
80005d6: 4825 ldr r0, [pc, #148] @ (800066c <main+0x128>)
80005d8: f005 f833 bl 8005642 <HAL_HRTIM_WaveformCountStart>
HAL_HRTIM_WaveformOutputStart(&hhrtim1,HRTIM_OUTPUT_TA1|HRTIM_OUTPUT_TA2|HRTIM_OUTPUT_TB2|HRTIM_OUTPUT_TB1);
80005dc: 210f movs r1, #15
80005de: 4823 ldr r0, [pc, #140] @ (800066c <main+0x128>)
80005e0: f004 ffd5 bl 800558e <HAL_HRTIM_WaveformOutputStart>
HAL_GPIO_WritePin(ENABLE_DRVA1_GPIO_Port,ENABLE_DRVA1_Pin,GPIO_PIN_SET);//LG1
80005e4: 2201 movs r2, #1
80005e6: f44f 6100 mov.w r1, #2048 @ 0x800
80005ea: 4821 ldr r0, [pc, #132] @ (8000670 <main+0x12c>)
80005ec: f004 faec bl 8004bc8 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(ENABLE_DRVA2_GPIO_Port,ENABLE_DRVA2_Pin,GPIO_PIN_SET);//LG2
80005f0: 2201 movs r2, #1
80005f2: 2110 movs r1, #16
80005f4: 481e ldr r0, [pc, #120] @ (8000670 <main+0x12c>)
80005f6: f004 fae7 bl 8004bc8 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(ENABLE_DRVB1_GPIO_Port,ENABLE_DRVB1_Pin,GPIO_PIN_SET);//HG1
80005fa: 2201 movs r2, #1
80005fc: f44f 5180 mov.w r1, #4096 @ 0x1000
8000600: 481b ldr r0, [pc, #108] @ (8000670 <main+0x12c>)
8000602: f004 fae1 bl 8004bc8 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(ENABLE_DRVB2_GPIO_Port,ENABLE_DRVB2_Pin,GPIO_PIN_SET);//HG2
8000606: 2201 movs r2, #1
8000608: 2120 movs r1, #32
800060a: 4819 ldr r0, [pc, #100] @ (8000670 <main+0x12c>)
800060c: f004 fadc bl 8004bc8 <HAL_GPIO_WritePin>
char dtext[20] = "Startup \n\r";
8000610: 4a18 ldr r2, [pc, #96] @ (8000674 <main+0x130>)
8000612: 1d3b adds r3, r7, #4
8000614: ca07 ldmia r2, {r0, r1, r2}
8000616: c303 stmia r3!, {r0, r1}
8000618: 801a strh r2, [r3, #0]
800061a: 3302 adds r3, #2
800061c: 0c12 lsrs r2, r2, #16
800061e: 701a strb r2, [r3, #0]
8000620: f107 030f add.w r3, r7, #15
8000624: 2200 movs r2, #0
8000626: 601a str r2, [r3, #0]
8000628: 605a str r2, [r3, #4]
800062a: 721a strb r2, [r3, #8]
HAL_UART_Transmit(&huart1,(uint8_t *)(dtext),12,10);
800062c: 1d39 adds r1, r7, #4
800062e: 230a movs r3, #10
8000630: 220c movs r2, #12
8000632: 4811 ldr r0, [pc, #68] @ (8000678 <main+0x134>)
8000634: f008 f9e2 bl 80089fc <HAL_UART_Transmit>
#ifndef EXPERIMENTAL
HAL_TIM_Base_Start_IT(&htim1);
#endif
#ifdef EXPERIMENTAL
HAL_TIM_OC_Start_IT (&htim3, TIM_CHANNEL_3);
8000638: 2108 movs r1, #8
800063a: 4810 ldr r0, [pc, #64] @ (800067c <main+0x138>)
800063c: f006 ffb4 bl 80075a8 <HAL_TIM_OC_Start_IT>
__HAL_TIM_ENABLE_IT(&htim3, TIM_IT_UPDATE);
8000640: 4b0e ldr r3, [pc, #56] @ (800067c <main+0x138>)
8000642: 681b ldr r3, [r3, #0]
8000644: 68da ldr r2, [r3, #12]
8000646: 4b0d ldr r3, [pc, #52] @ (800067c <main+0x138>)
8000648: 681b ldr r3, [r3, #0]
800064a: f042 0201 orr.w r2, r2, #1
800064e: 60da str r2, [r3, #12]
#endif
while (1)
8000650: bf00 nop
8000652: e7fd b.n 8000650 <main+0x10c>
8000654: 20000028 .word 0x20000028
8000658: 20000094 .word 0x20000094
800065c: 200004b8 .word 0x200004b8
8000660: 200004bc .word 0x200004bc
8000664: 20000244 .word 0x20000244
8000668: 200001e4 .word 0x200001e4
800066c: 20000290 .word 0x20000290
8000670: 48000400 .word 0x48000400
8000674: 080097c4 .word 0x080097c4
8000678: 20000424 .word 0x20000424
800067c: 200003d8 .word 0x200003d8
08000680 <SystemClock_Config>:
/**
* @brief System Clock Configuration
* @retval None
*/
void SystemClock_Config(void)
{
8000680: b580 push {r7, lr}
8000682: b094 sub sp, #80 @ 0x50
8000684: af00 add r7, sp, #0
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
8000686: f107 0318 add.w r3, r7, #24
800068a: 2238 movs r2, #56 @ 0x38
800068c: 2100 movs r1, #0
800068e: 4618 mov r0, r3
8000690: f009 f860 bl 8009754 <memset>
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
8000694: 1d3b adds r3, r7, #4
8000696: 2200 movs r2, #0
8000698: 601a str r2, [r3, #0]
800069a: 605a str r2, [r3, #4]
800069c: 609a str r2, [r3, #8]
800069e: 60da str r2, [r3, #12]
80006a0: 611a str r2, [r3, #16]
/** Configure the main internal regulator output voltage
*/
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1_BOOST);
80006a2: 2000 movs r0, #0
80006a4: f005 fe68 bl 8006378 <HAL_PWREx_ControlVoltageScaling>
/** Initializes the RCC Oscillators according to the specified parameters
* in the RCC_OscInitTypeDef structure.
*/
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
80006a8: 2301 movs r3, #1
80006aa: 61bb str r3, [r7, #24]
RCC_OscInitStruct.HSEState = RCC_HSE_ON;
80006ac: f44f 3380 mov.w r3, #65536 @ 0x10000
80006b0: 61fb str r3, [r7, #28]
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
80006b2: 2302 movs r3, #2
80006b4: 637b str r3, [r7, #52] @ 0x34
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
80006b6: 2303 movs r3, #3
80006b8: 63bb str r3, [r7, #56] @ 0x38
RCC_OscInitStruct.PLL.PLLM = RCC_PLLM_DIV4;
80006ba: 2304 movs r3, #4
80006bc: 63fb str r3, [r7, #60] @ 0x3c
RCC_OscInitStruct.PLL.PLLN = 34;
80006be: 2322 movs r3, #34 @ 0x22
80006c0: 643b str r3, [r7, #64] @ 0x40
RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
80006c2: 2302 movs r3, #2
80006c4: 647b str r3, [r7, #68] @ 0x44
RCC_OscInitStruct.PLL.PLLQ = RCC_PLLQ_DIV2;
80006c6: 2302 movs r3, #2
80006c8: 64bb str r3, [r7, #72] @ 0x48
RCC_OscInitStruct.PLL.PLLR = RCC_PLLR_DIV2;
80006ca: 2302 movs r3, #2
80006cc: 64fb str r3, [r7, #76] @ 0x4c
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
80006ce: f107 0318 add.w r3, r7, #24
80006d2: 4618 mov r0, r3
80006d4: f005 ff04 bl 80064e0 <HAL_RCC_OscConfig>
80006d8: 4603 mov r3, r0
80006da: 2b00 cmp r3, #0
80006dc: d001 beq.n 80006e2 <SystemClock_Config+0x62>
{
Error_Handler();
80006de: f000 fdb9 bl 8001254 <Error_Handler>
}
/** Initializes the CPU, AHB and APB buses clocks
*/
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
80006e2: 230f movs r3, #15
80006e4: 607b str r3, [r7, #4]
|RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
80006e6: 2303 movs r3, #3
80006e8: 60bb str r3, [r7, #8]
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
80006ea: 2300 movs r3, #0
80006ec: 60fb str r3, [r7, #12]
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
80006ee: 2300 movs r3, #0
80006f0: 613b str r3, [r7, #16]
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
80006f2: 2300 movs r3, #0
80006f4: 617b str r3, [r7, #20]
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
80006f6: 1d3b adds r3, r7, #4
80006f8: 2104 movs r1, #4
80006fa: 4618 mov r0, r3
80006fc: f006 fa02 bl 8006b04 <HAL_RCC_ClockConfig>
8000700: 4603 mov r3, r0
8000702: 2b00 cmp r3, #0
8000704: d001 beq.n 800070a <SystemClock_Config+0x8a>
{
Error_Handler();
8000706: f000 fda5 bl 8001254 <Error_Handler>
}
}
800070a: bf00 nop
800070c: 3750 adds r7, #80 @ 0x50
800070e: 46bd mov sp, r7
8000710: bd80 pop {r7, pc}
...
08000714 <MX_ADC3_Init>:
* @brief ADC3 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC3_Init(void)
{
8000714: b580 push {r7, lr}
8000716: b08c sub sp, #48 @ 0x30
8000718: af00 add r7, sp, #0
/* USER CODE BEGIN ADC3_Init 0 */
/* USER CODE END ADC3_Init 0 */
ADC_MultiModeTypeDef multimode = {0};
800071a: f107 0324 add.w r3, r7, #36 @ 0x24
800071e: 2200 movs r2, #0
8000720: 601a str r2, [r3, #0]
8000722: 605a str r2, [r3, #4]
8000724: 609a str r2, [r3, #8]
ADC_ChannelConfTypeDef sConfig = {0};
8000726: 1d3b adds r3, r7, #4
8000728: 2220 movs r2, #32
800072a: 2100 movs r1, #0
800072c: 4618 mov r0, r3
800072e: f009 f811 bl 8009754 <memset>
/* USER CODE END ADC3_Init 1 */
/** Common config
*/
hadc3.Instance = ADC3;
8000732: 4b32 ldr r3, [pc, #200] @ (80007fc <MX_ADC3_Init+0xe8>)
8000734: 4a32 ldr r2, [pc, #200] @ (8000800 <MX_ADC3_Init+0xec>)
8000736: 601a str r2, [r3, #0]
hadc3.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV32;
8000738: 4b30 ldr r3, [pc, #192] @ (80007fc <MX_ADC3_Init+0xe8>)
800073a: f44f 1200 mov.w r2, #2097152 @ 0x200000
800073e: 605a str r2, [r3, #4]
hadc3.Init.Resolution = ADC_RESOLUTION_12B;
8000740: 4b2e ldr r3, [pc, #184] @ (80007fc <MX_ADC3_Init+0xe8>)
8000742: 2200 movs r2, #0
8000744: 609a str r2, [r3, #8]
hadc3.Init.DataAlign = ADC_DATAALIGN_RIGHT;
8000746: 4b2d ldr r3, [pc, #180] @ (80007fc <MX_ADC3_Init+0xe8>)
8000748: 2200 movs r2, #0
800074a: 60da str r2, [r3, #12]
hadc3.Init.GainCompensation = 0;
800074c: 4b2b ldr r3, [pc, #172] @ (80007fc <MX_ADC3_Init+0xe8>)
800074e: 2200 movs r2, #0
8000750: 611a str r2, [r3, #16]
hadc3.Init.ScanConvMode = ADC_SCAN_DISABLE;
8000752: 4b2a ldr r3, [pc, #168] @ (80007fc <MX_ADC3_Init+0xe8>)
8000754: 2200 movs r2, #0
8000756: 615a str r2, [r3, #20]
hadc3.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000758: 4b28 ldr r3, [pc, #160] @ (80007fc <MX_ADC3_Init+0xe8>)
800075a: 2204 movs r2, #4
800075c: 619a str r2, [r3, #24]
hadc3.Init.LowPowerAutoWait = DISABLE;
800075e: 4b27 ldr r3, [pc, #156] @ (80007fc <MX_ADC3_Init+0xe8>)
8000760: 2200 movs r2, #0
8000762: 771a strb r2, [r3, #28]
hadc3.Init.ContinuousConvMode = ENABLE;
8000764: 4b25 ldr r3, [pc, #148] @ (80007fc <MX_ADC3_Init+0xe8>)
8000766: 2201 movs r2, #1
8000768: 775a strb r2, [r3, #29]
hadc3.Init.NbrOfConversion = 1;
800076a: 4b24 ldr r3, [pc, #144] @ (80007fc <MX_ADC3_Init+0xe8>)
800076c: 2201 movs r2, #1
800076e: 621a str r2, [r3, #32]
hadc3.Init.DiscontinuousConvMode = DISABLE;
8000770: 4b22 ldr r3, [pc, #136] @ (80007fc <MX_ADC3_Init+0xe8>)
8000772: 2200 movs r2, #0
8000774: f883 2024 strb.w r2, [r3, #36] @ 0x24
hadc3.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000778: 4b20 ldr r3, [pc, #128] @ (80007fc <MX_ADC3_Init+0xe8>)
800077a: 2200 movs r2, #0
800077c: 62da str r2, [r3, #44] @ 0x2c
hadc3.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
800077e: 4b1f ldr r3, [pc, #124] @ (80007fc <MX_ADC3_Init+0xe8>)
8000780: 2200 movs r2, #0
8000782: 631a str r2, [r3, #48] @ 0x30
hadc3.Init.DMAContinuousRequests = ENABLE;
8000784: 4b1d ldr r3, [pc, #116] @ (80007fc <MX_ADC3_Init+0xe8>)
8000786: 2201 movs r2, #1
8000788: f883 2038 strb.w r2, [r3, #56] @ 0x38
hadc3.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
800078c: 4b1b ldr r3, [pc, #108] @ (80007fc <MX_ADC3_Init+0xe8>)
800078e: f44f 5280 mov.w r2, #4096 @ 0x1000
8000792: 63da str r2, [r3, #60] @ 0x3c
hadc3.Init.OversamplingMode = DISABLE;
8000794: 4b19 ldr r3, [pc, #100] @ (80007fc <MX_ADC3_Init+0xe8>)
8000796: 2200 movs r2, #0
8000798: f883 2040 strb.w r2, [r3, #64] @ 0x40
if (HAL_ADC_Init(&hadc3) != HAL_OK)
800079c: 4817 ldr r0, [pc, #92] @ (80007fc <MX_ADC3_Init+0xe8>)
800079e: f001 fc63 bl 8002068 <HAL_ADC_Init>
80007a2: 4603 mov r3, r0
80007a4: 2b00 cmp r3, #0
80007a6: d001 beq.n 80007ac <MX_ADC3_Init+0x98>
{
Error_Handler();
80007a8: f000 fd54 bl 8001254 <Error_Handler>
}
/** Configure the ADC multi-mode
*/
multimode.Mode = ADC_MODE_INDEPENDENT;
80007ac: 2300 movs r3, #0
80007ae: 627b str r3, [r7, #36] @ 0x24
if (HAL_ADCEx_MultiModeConfigChannel(&hadc3, &multimode) != HAL_OK)
80007b0: f107 0324 add.w r3, r7, #36 @ 0x24
80007b4: 4619 mov r1, r3
80007b6: 4811 ldr r0, [pc, #68] @ (80007fc <MX_ADC3_Init+0xe8>)
80007b8: f002 fd82 bl 80032c0 <HAL_ADCEx_MultiModeConfigChannel>
80007bc: 4603 mov r3, r0
80007be: 2b00 cmp r3, #0
80007c0: d001 beq.n 80007c6 <MX_ADC3_Init+0xb2>
{
Error_Handler();
80007c2: f000 fd47 bl 8001254 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_5;
80007c6: 4b0f ldr r3, [pc, #60] @ (8000804 <MX_ADC3_Init+0xf0>)
80007c8: 607b str r3, [r7, #4]
sConfig.Rank = ADC_REGULAR_RANK_1;
80007ca: 2306 movs r3, #6
80007cc: 60bb str r3, [r7, #8]
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5;
80007ce: 2307 movs r3, #7
80007d0: 60fb str r3, [r7, #12]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
80007d2: 237f movs r3, #127 @ 0x7f
80007d4: 613b str r3, [r7, #16]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
80007d6: 2304 movs r3, #4
80007d8: 617b str r3, [r7, #20]
sConfig.Offset = 0;
80007da: 2300 movs r3, #0
80007dc: 61bb str r3, [r7, #24]
if (HAL_ADC_ConfigChannel(&hadc3, &sConfig) != HAL_OK)
80007de: 1d3b adds r3, r7, #4
80007e0: 4619 mov r1, r3
80007e2: 4806 ldr r0, [pc, #24] @ (80007fc <MX_ADC3_Init+0xe8>)
80007e4: f001 feee bl 80025c4 <HAL_ADC_ConfigChannel>
80007e8: 4603 mov r3, r0
80007ea: 2b00 cmp r3, #0
80007ec: d001 beq.n 80007f2 <MX_ADC3_Init+0xde>
{
Error_Handler();
80007ee: f000 fd31 bl 8001254 <Error_Handler>
}
/* USER CODE BEGIN ADC3_Init 2 */
/* USER CODE END ADC3_Init 2 */
}
80007f2: bf00 nop
80007f4: 3730 adds r7, #48 @ 0x30
80007f6: 46bd mov sp, r7
80007f8: bd80 pop {r7, pc}
80007fa: bf00 nop
80007fc: 20000028 .word 0x20000028
8000800: 50000400 .word 0x50000400
8000804: 14f00020 .word 0x14f00020
08000808 <MX_ADC4_Init>:
* @brief ADC4 Initialization Function
* @param None
* @retval None
*/
static void MX_ADC4_Init(void)
{
8000808: b580 push {r7, lr}
800080a: b088 sub sp, #32
800080c: af00 add r7, sp, #0
/* USER CODE BEGIN ADC4_Init 0 */
/* USER CODE END ADC4_Init 0 */
ADC_ChannelConfTypeDef sConfig = {0};
800080e: 463b mov r3, r7
8000810: 2220 movs r2, #32
8000812: 2100 movs r1, #0
8000814: 4618 mov r0, r3
8000816: f008 ff9d bl 8009754 <memset>
/* USER CODE END ADC4_Init 1 */
/** Common config
*/
hadc4.Instance = ADC4;
800081a: 4b2b ldr r3, [pc, #172] @ (80008c8 <MX_ADC4_Init+0xc0>)
800081c: 4a2b ldr r2, [pc, #172] @ (80008cc <MX_ADC4_Init+0xc4>)
800081e: 601a str r2, [r3, #0]
hadc4.Init.ClockPrescaler = ADC_CLOCK_ASYNC_DIV32;
8000820: 4b29 ldr r3, [pc, #164] @ (80008c8 <MX_ADC4_Init+0xc0>)
8000822: f44f 1200 mov.w r2, #2097152 @ 0x200000
8000826: 605a str r2, [r3, #4]
hadc4.Init.Resolution = ADC_RESOLUTION_12B;
8000828: 4b27 ldr r3, [pc, #156] @ (80008c8 <MX_ADC4_Init+0xc0>)
800082a: 2200 movs r2, #0
800082c: 609a str r2, [r3, #8]
hadc4.Init.DataAlign = ADC_DATAALIGN_RIGHT;
800082e: 4b26 ldr r3, [pc, #152] @ (80008c8 <MX_ADC4_Init+0xc0>)
8000830: 2200 movs r2, #0
8000832: 60da str r2, [r3, #12]
hadc4.Init.GainCompensation = 0;
8000834: 4b24 ldr r3, [pc, #144] @ (80008c8 <MX_ADC4_Init+0xc0>)
8000836: 2200 movs r2, #0
8000838: 611a str r2, [r3, #16]
hadc4.Init.ScanConvMode = ADC_SCAN_DISABLE;
800083a: 4b23 ldr r3, [pc, #140] @ (80008c8 <MX_ADC4_Init+0xc0>)
800083c: 2200 movs r2, #0
800083e: 615a str r2, [r3, #20]
hadc4.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
8000840: 4b21 ldr r3, [pc, #132] @ (80008c8 <MX_ADC4_Init+0xc0>)
8000842: 2204 movs r2, #4
8000844: 619a str r2, [r3, #24]
hadc4.Init.LowPowerAutoWait = DISABLE;
8000846: 4b20 ldr r3, [pc, #128] @ (80008c8 <MX_ADC4_Init+0xc0>)
8000848: 2200 movs r2, #0
800084a: 771a strb r2, [r3, #28]
hadc4.Init.ContinuousConvMode = ENABLE;
800084c: 4b1e ldr r3, [pc, #120] @ (80008c8 <MX_ADC4_Init+0xc0>)
800084e: 2201 movs r2, #1
8000850: 775a strb r2, [r3, #29]
hadc4.Init.NbrOfConversion = 1;
8000852: 4b1d ldr r3, [pc, #116] @ (80008c8 <MX_ADC4_Init+0xc0>)
8000854: 2201 movs r2, #1
8000856: 621a str r2, [r3, #32]
hadc4.Init.DiscontinuousConvMode = DISABLE;
8000858: 4b1b ldr r3, [pc, #108] @ (80008c8 <MX_ADC4_Init+0xc0>)
800085a: 2200 movs r2, #0
800085c: f883 2024 strb.w r2, [r3, #36] @ 0x24
hadc4.Init.ExternalTrigConv = ADC_SOFTWARE_START;
8000860: 4b19 ldr r3, [pc, #100] @ (80008c8 <MX_ADC4_Init+0xc0>)
8000862: 2200 movs r2, #0
8000864: 62da str r2, [r3, #44] @ 0x2c
hadc4.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
8000866: 4b18 ldr r3, [pc, #96] @ (80008c8 <MX_ADC4_Init+0xc0>)
8000868: 2200 movs r2, #0
800086a: 631a str r2, [r3, #48] @ 0x30
hadc4.Init.DMAContinuousRequests = ENABLE;
800086c: 4b16 ldr r3, [pc, #88] @ (80008c8 <MX_ADC4_Init+0xc0>)
800086e: 2201 movs r2, #1
8000870: f883 2038 strb.w r2, [r3, #56] @ 0x38
hadc4.Init.Overrun = ADC_OVR_DATA_OVERWRITTEN;
8000874: 4b14 ldr r3, [pc, #80] @ (80008c8 <MX_ADC4_Init+0xc0>)
8000876: f44f 5280 mov.w r2, #4096 @ 0x1000
800087a: 63da str r2, [r3, #60] @ 0x3c
hadc4.Init.OversamplingMode = DISABLE;
800087c: 4b12 ldr r3, [pc, #72] @ (80008c8 <MX_ADC4_Init+0xc0>)
800087e: 2200 movs r2, #0
8000880: f883 2040 strb.w r2, [r3, #64] @ 0x40
if (HAL_ADC_Init(&hadc4) != HAL_OK)
8000884: 4810 ldr r0, [pc, #64] @ (80008c8 <MX_ADC4_Init+0xc0>)
8000886: f001 fbef bl 8002068 <HAL_ADC_Init>
800088a: 4603 mov r3, r0
800088c: 2b00 cmp r3, #0
800088e: d001 beq.n 8000894 <MX_ADC4_Init+0x8c>
{
Error_Handler();
8000890: f000 fce0 bl 8001254 <Error_Handler>
}
/** Configure Regular Channel
*/
sConfig.Channel = ADC_CHANNEL_4;
8000894: 4b0e ldr r3, [pc, #56] @ (80008d0 <MX_ADC4_Init+0xc8>)
8000896: 603b str r3, [r7, #0]
sConfig.Rank = ADC_REGULAR_RANK_1;
8000898: 2306 movs r3, #6
800089a: 607b str r3, [r7, #4]
sConfig.SamplingTime = ADC_SAMPLETIME_640CYCLES_5;
800089c: 2307 movs r3, #7
800089e: 60bb str r3, [r7, #8]
sConfig.SingleDiff = ADC_SINGLE_ENDED;
80008a0: 237f movs r3, #127 @ 0x7f
80008a2: 60fb str r3, [r7, #12]
sConfig.OffsetNumber = ADC_OFFSET_NONE;
80008a4: 2304 movs r3, #4
80008a6: 613b str r3, [r7, #16]
sConfig.Offset = 0;
80008a8: 2300 movs r3, #0
80008aa: 617b str r3, [r7, #20]
if (HAL_ADC_ConfigChannel(&hadc4, &sConfig) != HAL_OK)
80008ac: 463b mov r3, r7
80008ae: 4619 mov r1, r3
80008b0: 4805 ldr r0, [pc, #20] @ (80008c8 <MX_ADC4_Init+0xc0>)
80008b2: f001 fe87 bl 80025c4 <HAL_ADC_ConfigChannel>
80008b6: 4603 mov r3, r0
80008b8: 2b00 cmp r3, #0
80008ba: d001 beq.n 80008c0 <MX_ADC4_Init+0xb8>
{
Error_Handler();
80008bc: f000 fcca bl 8001254 <Error_Handler>
}
/* USER CODE BEGIN ADC4_Init 2 */
/* USER CODE END ADC4_Init 2 */
}
80008c0: bf00 nop
80008c2: 3720 adds r7, #32
80008c4: 46bd mov sp, r7
80008c6: bd80 pop {r7, pc}
80008c8: 20000094 .word 0x20000094
80008cc: 50000500 .word 0x50000500
80008d0: 10c00010 .word 0x10c00010
080008d4 <MX_COMP5_Init>:
* @brief COMP5 Initialization Function
* @param None
* @retval None
*/
static void MX_COMP5_Init(void)
{
80008d4: b580 push {r7, lr}
80008d6: af00 add r7, sp, #0
/* USER CODE END COMP5_Init 0 */
/* USER CODE BEGIN COMP5_Init 1 */
/* USER CODE END COMP5_Init 1 */
hcomp5.Instance = COMP5;
80008d8: 4b0f ldr r3, [pc, #60] @ (8000918 <MX_COMP5_Init+0x44>)
80008da: 4a10 ldr r2, [pc, #64] @ (800091c <MX_COMP5_Init+0x48>)
80008dc: 601a str r2, [r3, #0]
hcomp5.Init.InputPlus = COMP_INPUT_PLUS_IO1;
80008de: 4b0e ldr r3, [pc, #56] @ (8000918 <MX_COMP5_Init+0x44>)
80008e0: 2200 movs r2, #0
80008e2: 605a str r2, [r3, #4]
hcomp5.Init.InputMinus = COMP_INPUT_MINUS_DAC1_CH2;
80008e4: 4b0c ldr r3, [pc, #48] @ (8000918 <MX_COMP5_Init+0x44>)
80008e6: 2250 movs r2, #80 @ 0x50
80008e8: 609a str r2, [r3, #8]
hcomp5.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED;
80008ea: 4b0b ldr r3, [pc, #44] @ (8000918 <MX_COMP5_Init+0x44>)
80008ec: 2200 movs r2, #0
80008ee: 611a str r2, [r3, #16]
hcomp5.Init.Hysteresis = COMP_HYSTERESIS_NONE;
80008f0: 4b09 ldr r3, [pc, #36] @ (8000918 <MX_COMP5_Init+0x44>)
80008f2: 2200 movs r2, #0
80008f4: 60da str r2, [r3, #12]
hcomp5.Init.BlankingSrce = COMP_BLANKINGSRC_TIM3_OC3_COMP5;
80008f6: 4b08 ldr r3, [pc, #32] @ (8000918 <MX_COMP5_Init+0x44>)
80008f8: f44f 12c0 mov.w r2, #1572864 @ 0x180000
80008fc: 615a str r2, [r3, #20]
hcomp5.Init.TriggerMode = COMP_TRIGGERMODE_IT_RISING;
80008fe: 4b06 ldr r3, [pc, #24] @ (8000918 <MX_COMP5_Init+0x44>)
8000900: 2211 movs r2, #17
8000902: 619a str r2, [r3, #24]
if (HAL_COMP_Init(&hcomp5) != HAL_OK)
8000904: 4804 ldr r0, [pc, #16] @ (8000918 <MX_COMP5_Init+0x44>)
8000906: f002 ff5f bl 80037c8 <HAL_COMP_Init>
800090a: 4603 mov r3, r0
800090c: 2b00 cmp r3, #0
800090e: d001 beq.n 8000914 <MX_COMP5_Init+0x40>
{
Error_Handler();
8000910: f000 fca0 bl 8001254 <Error_Handler>
}
/* USER CODE BEGIN COMP5_Init 2 */
/* USER CODE END COMP5_Init 2 */
}
8000914: bf00 nop
8000916: bd80 pop {r7, pc}
8000918: 200001c0 .word 0x200001c0
800091c: 40010210 .word 0x40010210
08000920 <MX_COMP7_Init>:
* @brief COMP7 Initialization Function
* @param None
* @retval None
*/
static void MX_COMP7_Init(void)
{
8000920: b580 push {r7, lr}
8000922: af00 add r7, sp, #0
/* USER CODE END COMP7_Init 0 */
/* USER CODE BEGIN COMP7_Init 1 */
/* USER CODE END COMP7_Init 1 */
hcomp7.Instance = COMP7;
8000924: 4b10 ldr r3, [pc, #64] @ (8000968 <MX_COMP7_Init+0x48>)
8000926: 4a11 ldr r2, [pc, #68] @ (800096c <MX_COMP7_Init+0x4c>)
8000928: 601a str r2, [r3, #0]
hcomp7.Init.InputPlus = COMP_INPUT_PLUS_IO1;
800092a: 4b0f ldr r3, [pc, #60] @ (8000968 <MX_COMP7_Init+0x48>)
800092c: 2200 movs r2, #0
800092e: 605a str r2, [r3, #4]
hcomp7.Init.InputMinus = COMP_INPUT_MINUS_DAC4_CH1;
8000930: 4b0d ldr r3, [pc, #52] @ (8000968 <MX_COMP7_Init+0x48>)
8000932: 2240 movs r2, #64 @ 0x40
8000934: 609a str r2, [r3, #8]
hcomp7.Init.OutputPol = COMP_OUTPUTPOL_NONINVERTED;
8000936: 4b0c ldr r3, [pc, #48] @ (8000968 <MX_COMP7_Init+0x48>)
8000938: 2200 movs r2, #0
800093a: 611a str r2, [r3, #16]
hcomp7.Init.Hysteresis = COMP_HYSTERESIS_HIGH;
800093c: 4b0a ldr r3, [pc, #40] @ (8000968 <MX_COMP7_Init+0x48>)
800093e: f44f 22e0 mov.w r2, #458752 @ 0x70000
8000942: 60da str r2, [r3, #12]
hcomp7.Init.BlankingSrce = COMP_BLANKINGSRC_TIM3_OC3_COMP7;
8000944: 4b08 ldr r3, [pc, #32] @ (8000968 <MX_COMP7_Init+0x48>)
8000946: f44f 12c0 mov.w r2, #1572864 @ 0x180000
800094a: 615a str r2, [r3, #20]
hcomp7.Init.TriggerMode = COMP_TRIGGERMODE_IT_RISING;
800094c: 4b06 ldr r3, [pc, #24] @ (8000968 <MX_COMP7_Init+0x48>)
800094e: 2211 movs r2, #17
8000950: 619a str r2, [r3, #24]
if (HAL_COMP_Init(&hcomp7) != HAL_OK)
8000952: 4805 ldr r0, [pc, #20] @ (8000968 <MX_COMP7_Init+0x48>)
8000954: f002 ff38 bl 80037c8 <HAL_COMP_Init>
8000958: 4603 mov r3, r0
800095a: 2b00 cmp r3, #0
800095c: d001 beq.n 8000962 <MX_COMP7_Init+0x42>
{
Error_Handler();
800095e: f000 fc79 bl 8001254 <Error_Handler>
}
/* USER CODE BEGIN COMP7_Init 2 */
/* USER CODE END COMP7_Init 2 */
}
8000962: bf00 nop
8000964: bd80 pop {r7, pc}
8000966: bf00 nop
8000968: 200001e4 .word 0x200001e4
800096c: 40010218 .word 0x40010218
08000970 <MX_CORDIC_Init>:
* @brief CORDIC Initialization Function
* @param None
* @retval None
*/
static void MX_CORDIC_Init(void)
{
8000970: b580 push {r7, lr}
8000972: af00 add r7, sp, #0
/* USER CODE END CORDIC_Init 0 */
/* USER CODE BEGIN CORDIC_Init 1 */
/* USER CODE END CORDIC_Init 1 */
hcordic.Instance = CORDIC;
8000974: 4b06 ldr r3, [pc, #24] @ (8000990 <MX_CORDIC_Init+0x20>)
8000976: 4a07 ldr r2, [pc, #28] @ (8000994 <MX_CORDIC_Init+0x24>)
8000978: 601a str r2, [r3, #0]
if (HAL_CORDIC_Init(&hcordic) != HAL_OK)
800097a: 4805 ldr r0, [pc, #20] @ (8000990 <MX_CORDIC_Init+0x20>)
800097c: f003 f97a bl 8003c74 <HAL_CORDIC_Init>
8000980: 4603 mov r3, r0
8000982: 2b00 cmp r3, #0
8000984: d001 beq.n 800098a <MX_CORDIC_Init+0x1a>
{
Error_Handler();
8000986: f000 fc65 bl 8001254 <Error_Handler>
}
/* USER CODE BEGIN CORDIC_Init 2 */
/* USER CODE END CORDIC_Init 2 */
}
800098a: bf00 nop
800098c: bd80 pop {r7, pc}
800098e: bf00 nop
8000990: 20000208 .word 0x20000208
8000994: 40020c00 .word 0x40020c00
08000998 <MX_DAC1_Init>:
* @brief DAC1 Initialization Function
* @param None
* @retval None
*/
static void MX_DAC1_Init(void)
{
8000998: b580 push {r7, lr}
800099a: b08c sub sp, #48 @ 0x30
800099c: af00 add r7, sp, #0
/* USER CODE BEGIN DAC1_Init 0 */
/* USER CODE END DAC1_Init 0 */
DAC_ChannelConfTypeDef sConfig = {0};
800099e: 463b mov r3, r7
80009a0: 2230 movs r2, #48 @ 0x30
80009a2: 2100 movs r1, #0
80009a4: 4618 mov r0, r3
80009a6: f008 fed5 bl 8009754 <memset>
/* USER CODE END DAC1_Init 1 */
/** DAC Initialization
*/
hdac1.Instance = DAC1;
80009aa: 4b16 ldr r3, [pc, #88] @ (8000a04 <MX_DAC1_Init+0x6c>)
80009ac: 4a16 ldr r2, [pc, #88] @ (8000a08 <MX_DAC1_Init+0x70>)
80009ae: 601a str r2, [r3, #0]
if (HAL_DAC_Init(&hdac1) != HAL_OK)
80009b0: 4814 ldr r0, [pc, #80] @ (8000a04 <MX_DAC1_Init+0x6c>)
80009b2: f003 faa0 bl 8003ef6 <HAL_DAC_Init>
80009b6: 4603 mov r3, r0
80009b8: 2b00 cmp r3, #0
80009ba: d001 beq.n 80009c0 <MX_DAC1_Init+0x28>
{
Error_Handler();
80009bc: f000 fc4a bl 8001254 <Error_Handler>
}
/** DAC channel OUT2 config
*/
sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC;
80009c0: 2302 movs r3, #2
80009c2: 603b str r3, [r7, #0]
sConfig.DAC_DMADoubleDataMode = DISABLE;
80009c4: 2300 movs r3, #0
80009c6: 713b strb r3, [r7, #4]
sConfig.DAC_SignedFormat = DISABLE;
80009c8: 2300 movs r3, #0
80009ca: 717b strb r3, [r7, #5]
sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
80009cc: 2300 movs r3, #0
80009ce: 60bb str r3, [r7, #8]
sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
80009d0: 2300 movs r3, #0
80009d2: 60fb str r3, [r7, #12]
sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE;
80009d4: 2300 movs r3, #0
80009d6: 613b str r3, [r7, #16]
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
80009d8: 2302 movs r3, #2
80009da: 617b str r3, [r7, #20]
sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
80009dc: 2302 movs r3, #2
80009de: 61bb str r3, [r7, #24]
sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
80009e0: 2300 movs r3, #0
80009e2: 61fb str r3, [r7, #28]
if (HAL_DAC_ConfigChannel(&hdac1, &sConfig, DAC_CHANNEL_2) != HAL_OK)
80009e4: 463b mov r3, r7
80009e6: 2210 movs r2, #16
80009e8: 4619 mov r1, r3
80009ea: 4806 ldr r0, [pc, #24] @ (8000a04 <MX_DAC1_Init+0x6c>)
80009ec: f003 fb40 bl 8004070 <HAL_DAC_ConfigChannel>
80009f0: 4603 mov r3, r0
80009f2: 2b00 cmp r3, #0
80009f4: d001 beq.n 80009fa <MX_DAC1_Init+0x62>
{
Error_Handler();
80009f6: f000 fc2d bl 8001254 <Error_Handler>
}
/* USER CODE BEGIN DAC1_Init 2 */
/* USER CODE END DAC1_Init 2 */
}
80009fa: bf00 nop
80009fc: 3730 adds r7, #48 @ 0x30
80009fe: 46bd mov sp, r7
8000a00: bd80 pop {r7, pc}
8000a02: bf00 nop
8000a04: 20000230 .word 0x20000230
8000a08: 50000800 .word 0x50000800
08000a0c <MX_DAC4_Init>:
* @brief DAC4 Initialization Function
* @param None
* @retval None
*/
static void MX_DAC4_Init(void)
{
8000a0c: b580 push {r7, lr}
8000a0e: b08c sub sp, #48 @ 0x30
8000a10: af00 add r7, sp, #0
/* USER CODE BEGIN DAC4_Init 0 */
/* USER CODE END DAC4_Init 0 */
DAC_ChannelConfTypeDef sConfig = {0};
8000a12: 463b mov r3, r7
8000a14: 2230 movs r2, #48 @ 0x30
8000a16: 2100 movs r1, #0
8000a18: 4618 mov r0, r3
8000a1a: f008 fe9b bl 8009754 <memset>
/* USER CODE END DAC4_Init 1 */
/** DAC Initialization
*/
hdac4.Instance = DAC4;
8000a1e: 4b16 ldr r3, [pc, #88] @ (8000a78 <MX_DAC4_Init+0x6c>)
8000a20: 4a16 ldr r2, [pc, #88] @ (8000a7c <MX_DAC4_Init+0x70>)
8000a22: 601a str r2, [r3, #0]
if (HAL_DAC_Init(&hdac4) != HAL_OK)
8000a24: 4814 ldr r0, [pc, #80] @ (8000a78 <MX_DAC4_Init+0x6c>)
8000a26: f003 fa66 bl 8003ef6 <HAL_DAC_Init>
8000a2a: 4603 mov r3, r0
8000a2c: 2b00 cmp r3, #0
8000a2e: d001 beq.n 8000a34 <MX_DAC4_Init+0x28>
{
Error_Handler();
8000a30: f000 fc10 bl 8001254 <Error_Handler>
}
/** DAC channel OUT1 config
*/
sConfig.DAC_HighFrequency = DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC;
8000a34: 2302 movs r3, #2
8000a36: 603b str r3, [r7, #0]
sConfig.DAC_DMADoubleDataMode = DISABLE;
8000a38: 2300 movs r3, #0
8000a3a: 713b strb r3, [r7, #4]
sConfig.DAC_SignedFormat = DISABLE;
8000a3c: 2300 movs r3, #0
8000a3e: 717b strb r3, [r7, #5]
sConfig.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_DISABLE;
8000a40: 2300 movs r3, #0
8000a42: 60bb str r3, [r7, #8]
sConfig.DAC_Trigger = DAC_TRIGGER_NONE;
8000a44: 2300 movs r3, #0
8000a46: 60fb str r3, [r7, #12]
sConfig.DAC_Trigger2 = DAC_TRIGGER_NONE;
8000a48: 2300 movs r3, #0
8000a4a: 613b str r3, [r7, #16]
sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
8000a4c: 2302 movs r3, #2
8000a4e: 617b str r3, [r7, #20]
sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_INTERNAL;
8000a50: 2302 movs r3, #2
8000a52: 61bb str r3, [r7, #24]
sConfig.DAC_UserTrimming = DAC_TRIMMING_FACTORY;
8000a54: 2300 movs r3, #0
8000a56: 61fb str r3, [r7, #28]
if (HAL_DAC_ConfigChannel(&hdac4, &sConfig, DAC_CHANNEL_1) != HAL_OK)
8000a58: 463b mov r3, r7
8000a5a: 2200 movs r2, #0
8000a5c: 4619 mov r1, r3
8000a5e: 4806 ldr r0, [pc, #24] @ (8000a78 <MX_DAC4_Init+0x6c>)
8000a60: f003 fb06 bl 8004070 <HAL_DAC_ConfigChannel>
8000a64: 4603 mov r3, r0
8000a66: 2b00 cmp r3, #0
8000a68: d001 beq.n 8000a6e <MX_DAC4_Init+0x62>
{
Error_Handler();
8000a6a: f000 fbf3 bl 8001254 <Error_Handler>
}
/* USER CODE BEGIN DAC4_Init 2 */
/* USER CODE END DAC4_Init 2 */
}
8000a6e: bf00 nop
8000a70: 3730 adds r7, #48 @ 0x30
8000a72: 46bd mov sp, r7
8000a74: bd80 pop {r7, pc}
8000a76: bf00 nop
8000a78: 20000244 .word 0x20000244
8000a7c: 50001400 .word 0x50001400
08000a80 <MX_FMAC_Init>:
* @brief FMAC Initialization Function
* @param None
* @retval None
*/
static void MX_FMAC_Init(void)
{
8000a80: b580 push {r7, lr}
8000a82: af00 add r7, sp, #0
/* USER CODE END FMAC_Init 0 */
/* USER CODE BEGIN FMAC_Init 1 */
/* USER CODE END FMAC_Init 1 */
hfmac.Instance = FMAC;
8000a84: 4b06 ldr r3, [pc, #24] @ (8000aa0 <MX_FMAC_Init+0x20>)
8000a86: 4a07 ldr r2, [pc, #28] @ (8000aa4 <MX_FMAC_Init+0x24>)
8000a88: 601a str r2, [r3, #0]
if (HAL_FMAC_Init(&hfmac) != HAL_OK)
8000a8a: 4805 ldr r0, [pc, #20] @ (8000aa0 <MX_FMAC_Init+0x20>)
8000a8c: f003 fe6e bl 800476c <HAL_FMAC_Init>
8000a90: 4603 mov r3, r0
8000a92: 2b00 cmp r3, #0
8000a94: d001 beq.n 8000a9a <MX_FMAC_Init+0x1a>
{
Error_Handler();
8000a96: f000 fbdd bl 8001254 <Error_Handler>
}
/* USER CODE BEGIN FMAC_Init 2 */
/* USER CODE END FMAC_Init 2 */
}
8000a9a: bf00 nop
8000a9c: bd80 pop {r7, pc}
8000a9e: bf00 nop
8000aa0: 20000258 .word 0x20000258
8000aa4: 40021400 .word 0x40021400
08000aa8 <MX_HRTIM1_Init>:
* @brief HRTIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_HRTIM1_Init(void)
{
8000aa8: b580 push {r7, lr}
8000aaa: b0bc sub sp, #240 @ 0xf0
8000aac: af00 add r7, sp, #0
/* USER CODE BEGIN HRTIM1_Init 0 */
/* USER CODE END HRTIM1_Init 0 */
HRTIM_EventCfgTypeDef pEventCfg = {0};
8000aae: f107 03dc add.w r3, r7, #220 @ 0xdc
8000ab2: 2200 movs r2, #0
8000ab4: 601a str r2, [r3, #0]
8000ab6: 605a str r2, [r3, #4]
8000ab8: 609a str r2, [r3, #8]
8000aba: 60da str r2, [r3, #12]
8000abc: 611a str r2, [r3, #16]
HRTIM_TimeBaseCfgTypeDef pTimeBaseCfg = {0};
8000abe: f107 03cc add.w r3, r7, #204 @ 0xcc
8000ac2: 2200 movs r2, #0
8000ac4: 601a str r2, [r3, #0]
8000ac6: 605a str r2, [r3, #4]
8000ac8: 609a str r2, [r3, #8]
8000aca: 60da str r2, [r3, #12]
HRTIM_TimerCfgTypeDef pTimerCfg = {0};
8000acc: f107 036c add.w r3, r7, #108 @ 0x6c
8000ad0: 2260 movs r2, #96 @ 0x60
8000ad2: 2100 movs r1, #0
8000ad4: 4618 mov r0, r3
8000ad6: f008 fe3d bl 8009754 <memset>
HRTIM_TimerCtlTypeDef pTimerCtl = {0};
8000ada: f107 0350 add.w r3, r7, #80 @ 0x50
8000ade: 2200 movs r2, #0
8000ae0: 601a str r2, [r3, #0]
8000ae2: 605a str r2, [r3, #4]
8000ae4: 609a str r2, [r3, #8]
8000ae6: 60da str r2, [r3, #12]
8000ae8: 611a str r2, [r3, #16]
8000aea: 615a str r2, [r3, #20]
8000aec: 619a str r2, [r3, #24]
HRTIM_CompareCfgTypeDef pCompareCfg = {0};
8000aee: f107 0344 add.w r3, r7, #68 @ 0x44
8000af2: 2200 movs r2, #0
8000af4: 601a str r2, [r3, #0]
8000af6: 605a str r2, [r3, #4]
8000af8: 609a str r2, [r3, #8]
HRTIM_DeadTimeCfgTypeDef pDeadTimeCfg = {0};
8000afa: f107 0320 add.w r3, r7, #32
8000afe: 2224 movs r2, #36 @ 0x24
8000b00: 2100 movs r1, #0
8000b02: 4618 mov r0, r3
8000b04: f008 fe26 bl 8009754 <memset>
HRTIM_OutputCfgTypeDef pOutputCfg = {0};
8000b08: 463b mov r3, r7
8000b0a: 2220 movs r2, #32
8000b0c: 2100 movs r1, #0
8000b0e: 4618 mov r0, r3
8000b10: f008 fe20 bl 8009754 <memset>
/* USER CODE BEGIN HRTIM1_Init 1 */
/* USER CODE END HRTIM1_Init 1 */
hhrtim1.Instance = HRTIM1;
8000b14: 4bc8 ldr r3, [pc, #800] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000b16: 4ac9 ldr r2, [pc, #804] @ (8000e3c <MX_HRTIM1_Init+0x394>)
8000b18: 601a str r2, [r3, #0]
hhrtim1.Init.HRTIMInterruptResquests = HRTIM_IT_NONE;
8000b1a: 4bc7 ldr r3, [pc, #796] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000b1c: 2200 movs r2, #0
8000b1e: 605a str r2, [r3, #4]
hhrtim1.Init.SyncOptions = HRTIM_SYNCOPTION_NONE;
8000b20: 4bc5 ldr r3, [pc, #788] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000b22: 2200 movs r2, #0
8000b24: 609a str r2, [r3, #8]
if (HAL_HRTIM_Init(&hhrtim1) != HAL_OK)
8000b26: 48c4 ldr r0, [pc, #784] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000b28: f004 f866 bl 8004bf8 <HAL_HRTIM_Init>
8000b2c: 4603 mov r3, r0
8000b2e: 2b00 cmp r3, #0
8000b30: d001 beq.n 8000b36 <MX_HRTIM1_Init+0x8e>
{
Error_Handler();
8000b32: f000 fb8f bl 8001254 <Error_Handler>
}
if (HAL_HRTIM_DLLCalibrationStart(&hhrtim1, HRTIM_CALIBRATIONRATE_3) != HAL_OK)
8000b36: 210c movs r1, #12
8000b38: 48bf ldr r0, [pc, #764] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000b3a: f004 f92d bl 8004d98 <HAL_HRTIM_DLLCalibrationStart>
8000b3e: 4603 mov r3, r0
8000b40: 2b00 cmp r3, #0
8000b42: d001 beq.n 8000b48 <MX_HRTIM1_Init+0xa0>
{
Error_Handler();
8000b44: f000 fb86 bl 8001254 <Error_Handler>
}
if (HAL_HRTIM_PollForDLLCalibration(&hhrtim1, 10) != HAL_OK)
8000b48: 210a movs r1, #10
8000b4a: 48bb ldr r0, [pc, #748] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000b4c: f004 f97c bl 8004e48 <HAL_HRTIM_PollForDLLCalibration>
8000b50: 4603 mov r3, r0
8000b52: 2b00 cmp r3, #0
8000b54: d001 beq.n 8000b5a <MX_HRTIM1_Init+0xb2>
{
Error_Handler();
8000b56: f000 fb7d bl 8001254 <Error_Handler>
}
if (HAL_HRTIM_EventPrescalerConfig(&hhrtim1, HRTIM_EVENTPRESCALER_DIV1) != HAL_OK)
8000b5a: 2100 movs r1, #0
8000b5c: 48b6 ldr r0, [pc, #728] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000b5e: f004 f9fe bl 8004f5e <HAL_HRTIM_EventPrescalerConfig>
8000b62: 4603 mov r3, r0
8000b64: 2b00 cmp r3, #0
8000b66: d001 beq.n 8000b6c <MX_HRTIM1_Init+0xc4>
{
Error_Handler();
8000b68: f000 fb74 bl 8001254 <Error_Handler>
}
pEventCfg.Source = HRTIM_EEV1SRC_COMP2_OUT;
8000b6c: 2301 movs r3, #1
8000b6e: f8c7 30dc str.w r3, [r7, #220] @ 0xdc
pEventCfg.Polarity = HRTIM_EVENTPOLARITY_HIGH;
8000b72: 2300 movs r3, #0
8000b74: f8c7 30e0 str.w r3, [r7, #224] @ 0xe0
pEventCfg.Sensitivity = HRTIM_EVENTSENSITIVITY_LEVEL;
8000b78: 2300 movs r3, #0
8000b7a: f8c7 30e4 str.w r3, [r7, #228] @ 0xe4
pEventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
8000b7e: 2300 movs r3, #0
8000b80: f8c7 30ec str.w r3, [r7, #236] @ 0xec
if (HAL_HRTIM_EventConfig(&hhrtim1, HRTIM_EVENT_1, &pEventCfg) != HAL_OK)
8000b84: f107 03dc add.w r3, r7, #220 @ 0xdc
8000b88: 461a mov r2, r3
8000b8a: 2101 movs r1, #1
8000b8c: 48aa ldr r0, [pc, #680] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000b8e: f004 f9b7 bl 8004f00 <HAL_HRTIM_EventConfig>
8000b92: 4603 mov r3, r0
8000b94: 2b00 cmp r3, #0
8000b96: d001 beq.n 8000b9c <MX_HRTIM1_Init+0xf4>
{
Error_Handler();
8000b98: f000 fb5c bl 8001254 <Error_Handler>
}
pTimeBaseCfg.Period = 0xD480;
8000b9c: f24d 4380 movw r3, #54400 @ 0xd480
8000ba0: f8c7 30cc str.w r3, [r7, #204] @ 0xcc
pTimeBaseCfg.RepetitionCounter = 0x00;
8000ba4: 2300 movs r3, #0
8000ba6: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
pTimeBaseCfg.PrescalerRatio = HRTIM_PRESCALERRATIO_MUL32;
8000baa: 2300 movs r3, #0
8000bac: f8c7 30d4 str.w r3, [r7, #212] @ 0xd4
pTimeBaseCfg.Mode = HRTIM_MODE_CONTINUOUS;
8000bb0: 2308 movs r3, #8
8000bb2: f8c7 30d8 str.w r3, [r7, #216] @ 0xd8
if (HAL_HRTIM_TimeBaseConfig(&hhrtim1, HRTIM_TIMERINDEX_MASTER, &pTimeBaseCfg) != HAL_OK)
8000bb6: f107 03cc add.w r3, r7, #204 @ 0xcc
8000bba: 461a mov r2, r3
8000bbc: 2106 movs r1, #6
8000bbe: 489e ldr r0, [pc, #632] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000bc0: f004 f976 bl 8004eb0 <HAL_HRTIM_TimeBaseConfig>
8000bc4: 4603 mov r3, r0
8000bc6: 2b00 cmp r3, #0
8000bc8: d001 beq.n 8000bce <MX_HRTIM1_Init+0x126>
{
Error_Handler();
8000bca: f000 fb43 bl 8001254 <Error_Handler>
}
pTimerCfg.InterruptRequests = HRTIM_MASTER_IT_NONE;
8000bce: 2300 movs r3, #0
8000bd0: 66fb str r3, [r7, #108] @ 0x6c
pTimerCfg.DMARequests = HRTIM_MASTER_DMA_NONE;
8000bd2: 2300 movs r3, #0
8000bd4: 673b str r3, [r7, #112] @ 0x70
pTimerCfg.DMASrcAddress = 0x0000;
8000bd6: 2300 movs r3, #0
8000bd8: 677b str r3, [r7, #116] @ 0x74
pTimerCfg.DMADstAddress = 0x0000;
8000bda: 2300 movs r3, #0
8000bdc: 67bb str r3, [r7, #120] @ 0x78
pTimerCfg.DMASize = 0x1;
8000bde: 2301 movs r3, #1
8000be0: 67fb str r3, [r7, #124] @ 0x7c
pTimerCfg.HalfModeEnable = HRTIM_HALFMODE_DISABLED;
8000be2: 2300 movs r3, #0
8000be4: f8c7 3080 str.w r3, [r7, #128] @ 0x80
pTimerCfg.InterleavedMode = HRTIM_INTERLEAVED_MODE_DISABLED;
8000be8: 2300 movs r3, #0
8000bea: f8c7 3084 str.w r3, [r7, #132] @ 0x84
pTimerCfg.StartOnSync = HRTIM_SYNCSTART_DISABLED;
8000bee: 2300 movs r3, #0
8000bf0: f8c7 3088 str.w r3, [r7, #136] @ 0x88
pTimerCfg.ResetOnSync = HRTIM_SYNCRESET_DISABLED;
8000bf4: 2300 movs r3, #0
8000bf6: f8c7 308c str.w r3, [r7, #140] @ 0x8c
pTimerCfg.DACSynchro = HRTIM_DACSYNC_NONE;
8000bfa: 2300 movs r3, #0
8000bfc: f8c7 3090 str.w r3, [r7, #144] @ 0x90
pTimerCfg.PreloadEnable = HRTIM_PRELOAD_ENABLED;
8000c00: f04f 6300 mov.w r3, #134217728 @ 0x8000000
8000c04: f8c7 3094 str.w r3, [r7, #148] @ 0x94
pTimerCfg.UpdateGating = HRTIM_UPDATEGATING_INDEPENDENT;
8000c08: 2300 movs r3, #0
8000c0a: f8c7 3098 str.w r3, [r7, #152] @ 0x98
pTimerCfg.BurstMode = HRTIM_TIMERBURSTMODE_MAINTAINCLOCK;
8000c0e: 2300 movs r3, #0
8000c10: f8c7 309c str.w r3, [r7, #156] @ 0x9c
pTimerCfg.RepetitionUpdate = HRTIM_UPDATEONREPETITION_ENABLED;
8000c14: f04f 5300 mov.w r3, #536870912 @ 0x20000000
8000c18: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
pTimerCfg.ReSyncUpdate = HRTIM_TIMERESYNC_UPDATE_UNCONDITIONAL;
8000c1c: 2300 movs r3, #0
8000c1e: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
if (HAL_HRTIM_WaveformTimerConfig(&hhrtim1, HRTIM_TIMERINDEX_MASTER, &pTimerCfg) != HAL_OK)
8000c22: f107 036c add.w r3, r7, #108 @ 0x6c
8000c26: 461a mov r2, r3
8000c28: 2106 movs r1, #6
8000c2a: 4883 ldr r0, [pc, #524] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000c2c: f004 f9d0 bl 8004fd0 <HAL_HRTIM_WaveformTimerConfig>
8000c30: 4603 mov r3, r0
8000c32: 2b00 cmp r3, #0
8000c34: d001 beq.n 8000c3a <MX_HRTIM1_Init+0x192>
{
Error_Handler();
8000c36: f000 fb0d bl 8001254 <Error_Handler>
}
pTimeBaseCfg.RepetitionCounter = 0x0;
8000c3a: 2300 movs r3, #0
8000c3c: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
if (HAL_HRTIM_TimeBaseConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pTimeBaseCfg) != HAL_OK)
8000c40: f107 03cc add.w r3, r7, #204 @ 0xcc
8000c44: 461a mov r2, r3
8000c46: 2100 movs r1, #0
8000c48: 487b ldr r0, [pc, #492] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000c4a: f004 f931 bl 8004eb0 <HAL_HRTIM_TimeBaseConfig>
8000c4e: 4603 mov r3, r0
8000c50: 2b00 cmp r3, #0
8000c52: d001 beq.n 8000c58 <MX_HRTIM1_Init+0x1b0>
{
Error_Handler();
8000c54: f000 fafe bl 8001254 <Error_Handler>
}
pTimerCtl.UpDownMode = HRTIM_TIMERUPDOWNMODE_UP;
8000c58: 2300 movs r3, #0
8000c5a: 653b str r3, [r7, #80] @ 0x50
pTimerCtl.GreaterCMP1 = HRTIM_TIMERGTCMP1_GREATER;
8000c5c: f44f 3380 mov.w r3, #65536 @ 0x10000
8000c60: 65fb str r3, [r7, #92] @ 0x5c
pTimerCtl.DualChannelDacEnable = HRTIM_TIMER_DCDE_DISABLED;
8000c62: 2300 movs r3, #0
8000c64: 66bb str r3, [r7, #104] @ 0x68
if (HAL_HRTIM_WaveformTimerControl(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pTimerCtl) != HAL_OK)
8000c66: f107 0350 add.w r3, r7, #80 @ 0x50
8000c6a: 461a mov r2, r3
8000c6c: 2100 movs r1, #0
8000c6e: 4872 ldr r0, [pc, #456] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000c70: f004 fa3b bl 80050ea <HAL_HRTIM_WaveformTimerControl>
8000c74: 4603 mov r3, r0
8000c76: 2b00 cmp r3, #0
8000c78: d001 beq.n 8000c7e <MX_HRTIM1_Init+0x1d6>
{
Error_Handler();
8000c7a: f000 faeb bl 8001254 <Error_Handler>
}
pTimerCfg.InterruptRequests = HRTIM_TIM_IT_NONE;
8000c7e: 2300 movs r3, #0
8000c80: 66fb str r3, [r7, #108] @ 0x6c
pTimerCfg.DMARequests = HRTIM_TIM_DMA_NONE;
8000c82: 2300 movs r3, #0
8000c84: 673b str r3, [r7, #112] @ 0x70
pTimerCfg.RepetitionUpdate = HRTIM_UPDATEONREPETITION_DISABLED;
8000c86: 2300 movs r3, #0
8000c88: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
pTimerCfg.PushPull = HRTIM_TIMPUSHPULLMODE_DISABLED;
8000c8c: 2300 movs r3, #0
8000c8e: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
pTimerCfg.FaultEnable = HRTIM_TIMFAULTENABLE_NONE;
8000c92: 2300 movs r3, #0
8000c94: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
pTimerCfg.FaultLock = HRTIM_TIMFAULTLOCK_READWRITE;
8000c98: 2300 movs r3, #0
8000c9a: f8c7 30ac str.w r3, [r7, #172] @ 0xac
pTimerCfg.DeadTimeInsertion = HRTIM_TIMDEADTIMEINSERTION_ENABLED;
8000c9e: f44f 7380 mov.w r3, #256 @ 0x100
8000ca2: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
pTimerCfg.DelayedProtectionMode = HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED;
8000ca6: 2300 movs r3, #0
8000ca8: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
pTimerCfg.UpdateTrigger = HRTIM_TIMUPDATETRIGGER_NONE;
8000cac: 2300 movs r3, #0
8000cae: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
pTimerCfg.ResetTrigger = HRTIM_TIMRESETTRIGGER_NONE;
8000cb2: 2300 movs r3, #0
8000cb4: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
pTimerCfg.ResetUpdate = HRTIM_TIMUPDATEONRESET_ENABLED;
8000cb8: f44f 2380 mov.w r3, #262144 @ 0x40000
8000cbc: f8c7 30c4 str.w r3, [r7, #196] @ 0xc4
if (HAL_HRTIM_WaveformTimerConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pTimerCfg) != HAL_OK)
8000cc0: f107 036c add.w r3, r7, #108 @ 0x6c
8000cc4: 461a mov r2, r3
8000cc6: 2100 movs r1, #0
8000cc8: 485b ldr r0, [pc, #364] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000cca: f004 f981 bl 8004fd0 <HAL_HRTIM_WaveformTimerConfig>
8000cce: 4603 mov r3, r0
8000cd0: 2b00 cmp r3, #0
8000cd2: d001 beq.n 8000cd8 <MX_HRTIM1_Init+0x230>
{
Error_Handler();
8000cd4: f000 fabe bl 8001254 <Error_Handler>
}
if (HAL_HRTIM_WaveformTimerConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pTimerCfg) != HAL_OK)
8000cd8: f107 036c add.w r3, r7, #108 @ 0x6c
8000cdc: 461a mov r2, r3
8000cde: 2101 movs r1, #1
8000ce0: 4855 ldr r0, [pc, #340] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000ce2: f004 f975 bl 8004fd0 <HAL_HRTIM_WaveformTimerConfig>
8000ce6: 4603 mov r3, r0
8000ce8: 2b00 cmp r3, #0
8000cea: d001 beq.n 8000cf0 <MX_HRTIM1_Init+0x248>
{
Error_Handler();
8000cec: f000 fab2 bl 8001254 <Error_Handler>
}
pCompareCfg.CompareValue = 0x0;
8000cf0: 2300 movs r3, #0
8000cf2: 647b str r3, [r7, #68] @ 0x44
if (HAL_HRTIM_WaveformCompareConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, HRTIM_COMPAREUNIT_1, &pCompareCfg) != HAL_OK)
8000cf4: f107 0344 add.w r3, r7, #68 @ 0x44
8000cf8: 2201 movs r2, #1
8000cfa: 2100 movs r1, #0
8000cfc: 484e ldr r0, [pc, #312] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000cfe: f004 faa7 bl 8005250 <HAL_HRTIM_WaveformCompareConfig>
8000d02: 4603 mov r3, r0
8000d04: 2b00 cmp r3, #0
8000d06: d001 beq.n 8000d0c <MX_HRTIM1_Init+0x264>
{
Error_Handler();
8000d08: f000 faa4 bl 8001254 <Error_Handler>
}
pDeadTimeCfg.Prescaler = HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8;
8000d0c: 2300 movs r3, #0
8000d0e: 623b str r3, [r7, #32]
pDeadTimeCfg.RisingValue = 0x00A;
8000d10: 230a movs r3, #10
8000d12: 627b str r3, [r7, #36] @ 0x24
pDeadTimeCfg.RisingSign = HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE;
8000d14: 2300 movs r3, #0
8000d16: 62bb str r3, [r7, #40] @ 0x28
pDeadTimeCfg.RisingLock = HRTIM_TIMDEADTIME_RISINGLOCK_WRITE;
8000d18: 2300 movs r3, #0
8000d1a: 62fb str r3, [r7, #44] @ 0x2c
pDeadTimeCfg.RisingSignLock = HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE;
8000d1c: 2300 movs r3, #0
8000d1e: 633b str r3, [r7, #48] @ 0x30
pDeadTimeCfg.FallingValue = 0x00A;
8000d20: 230a movs r3, #10
8000d22: 637b str r3, [r7, #52] @ 0x34
pDeadTimeCfg.FallingSign = HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE;
8000d24: 2300 movs r3, #0
8000d26: 63bb str r3, [r7, #56] @ 0x38
pDeadTimeCfg.FallingLock = HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE;
8000d28: 2300 movs r3, #0
8000d2a: 63fb str r3, [r7, #60] @ 0x3c
pDeadTimeCfg.FallingSignLock = HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE;
8000d2c: 2300 movs r3, #0
8000d2e: 643b str r3, [r7, #64] @ 0x40
if (HAL_HRTIM_DeadTimeConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, &pDeadTimeCfg) != HAL_OK)
8000d30: f107 0320 add.w r3, r7, #32
8000d34: 461a mov r2, r3
8000d36: 2100 movs r1, #0
8000d38: 483f ldr r0, [pc, #252] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000d3a: f004 fa09 bl 8005150 <HAL_HRTIM_DeadTimeConfig>
8000d3e: 4603 mov r3, r0
8000d40: 2b00 cmp r3, #0
8000d42: d001 beq.n 8000d48 <MX_HRTIM1_Init+0x2a0>
{
Error_Handler();
8000d44: f000 fa86 bl 8001254 <Error_Handler>
}
if (HAL_HRTIM_DeadTimeConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pDeadTimeCfg) != HAL_OK)
8000d48: f107 0320 add.w r3, r7, #32
8000d4c: 461a mov r2, r3
8000d4e: 2101 movs r1, #1
8000d50: 4839 ldr r0, [pc, #228] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000d52: f004 f9fd bl 8005150 <HAL_HRTIM_DeadTimeConfig>
8000d56: 4603 mov r3, r0
8000d58: 2b00 cmp r3, #0
8000d5a: d001 beq.n 8000d60 <MX_HRTIM1_Init+0x2b8>
{
Error_Handler();
8000d5c: f000 fa7a bl 8001254 <Error_Handler>
}
pOutputCfg.Polarity = HRTIM_OUTPUTPOLARITY_HIGH;
8000d60: 2300 movs r3, #0
8000d62: 603b str r3, [r7, #0]
pOutputCfg.SetSource = HRTIM_OUTPUTSET_TIMPER;
8000d64: 2304 movs r3, #4
8000d66: 607b str r3, [r7, #4]
pOutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
8000d68: 2308 movs r3, #8
8000d6a: 60bb str r3, [r7, #8]
pOutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
8000d6c: 2300 movs r3, #0
8000d6e: 60fb str r3, [r7, #12]
pOutputCfg.IdleLevel = HRTIM_OUTPUTIDLELEVEL_ACTIVE;
8000d70: 2308 movs r3, #8
8000d72: 613b str r3, [r7, #16]
pOutputCfg.FaultLevel = HRTIM_OUTPUTFAULTLEVEL_NONE;
8000d74: 2300 movs r3, #0
8000d76: 617b str r3, [r7, #20]
pOutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
8000d78: 2300 movs r3, #0
8000d7a: 61bb str r3, [r7, #24]
pOutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
8000d7c: 2300 movs r3, #0
8000d7e: 61fb str r3, [r7, #28]
if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, HRTIM_OUTPUT_TA1, &pOutputCfg) != HAL_OK)
8000d80: 463b mov r3, r7
8000d82: 2201 movs r2, #1
8000d84: 2100 movs r1, #0
8000d86: 482c ldr r0, [pc, #176] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000d88: f004 fbd0 bl 800552c <HAL_HRTIM_WaveformOutputConfig>
8000d8c: 4603 mov r3, r0
8000d8e: 2b00 cmp r3, #0
8000d90: d001 beq.n 8000d96 <MX_HRTIM1_Init+0x2ee>
{
Error_Handler();
8000d92: f000 fa5f bl 8001254 <Error_Handler>
}
if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, HRTIM_OUTPUT_TB1, &pOutputCfg) != HAL_OK)
8000d96: 463b mov r3, r7
8000d98: 2204 movs r2, #4
8000d9a: 2101 movs r1, #1
8000d9c: 4826 ldr r0, [pc, #152] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000d9e: f004 fbc5 bl 800552c <HAL_HRTIM_WaveformOutputConfig>
8000da2: 4603 mov r3, r0
8000da4: 2b00 cmp r3, #0
8000da6: d001 beq.n 8000dac <MX_HRTIM1_Init+0x304>
{
Error_Handler();
8000da8: f000 fa54 bl 8001254 <Error_Handler>
}
pOutputCfg.IdleLevel = HRTIM_OUTPUTIDLELEVEL_INACTIVE;
8000dac: 2300 movs r3, #0
8000dae: 613b str r3, [r7, #16]
if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_A, HRTIM_OUTPUT_TA2, &pOutputCfg) != HAL_OK)
8000db0: 463b mov r3, r7
8000db2: 2202 movs r2, #2
8000db4: 2100 movs r1, #0
8000db6: 4820 ldr r0, [pc, #128] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000db8: f004 fbb8 bl 800552c <HAL_HRTIM_WaveformOutputConfig>
8000dbc: 4603 mov r3, r0
8000dbe: 2b00 cmp r3, #0
8000dc0: d001 beq.n 8000dc6 <MX_HRTIM1_Init+0x31e>
{
Error_Handler();
8000dc2: f000 fa47 bl 8001254 <Error_Handler>
}
if (HAL_HRTIM_WaveformOutputConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, HRTIM_OUTPUT_TB2, &pOutputCfg) != HAL_OK)
8000dc6: 463b mov r3, r7
8000dc8: 2208 movs r2, #8
8000dca: 2101 movs r1, #1
8000dcc: 481a ldr r0, [pc, #104] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000dce: f004 fbad bl 800552c <HAL_HRTIM_WaveformOutputConfig>
8000dd2: 4603 mov r3, r0
8000dd4: 2b00 cmp r3, #0
8000dd6: d001 beq.n 8000ddc <MX_HRTIM1_Init+0x334>
{
Error_Handler();
8000dd8: f000 fa3c bl 8001254 <Error_Handler>
}
pTimeBaseCfg.RepetitionCounter = 0x00;
8000ddc: 2300 movs r3, #0
8000dde: f8c7 30d0 str.w r3, [r7, #208] @ 0xd0
if (HAL_HRTIM_TimeBaseConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pTimeBaseCfg) != HAL_OK)
8000de2: f107 03cc add.w r3, r7, #204 @ 0xcc
8000de6: 461a mov r2, r3
8000de8: 2101 movs r1, #1
8000dea: 4813 ldr r0, [pc, #76] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000dec: f004 f860 bl 8004eb0 <HAL_HRTIM_TimeBaseConfig>
8000df0: 4603 mov r3, r0
8000df2: 2b00 cmp r3, #0
8000df4: d001 beq.n 8000dfa <MX_HRTIM1_Init+0x352>
{
Error_Handler();
8000df6: f000 fa2d bl 8001254 <Error_Handler>
}
if (HAL_HRTIM_WaveformTimerControl(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, &pTimerCtl) != HAL_OK)
8000dfa: f107 0350 add.w r3, r7, #80 @ 0x50
8000dfe: 461a mov r2, r3
8000e00: 2101 movs r1, #1
8000e02: 480d ldr r0, [pc, #52] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000e04: f004 f971 bl 80050ea <HAL_HRTIM_WaveformTimerControl>
8000e08: 4603 mov r3, r0
8000e0a: 2b00 cmp r3, #0
8000e0c: d001 beq.n 8000e12 <MX_HRTIM1_Init+0x36a>
{
Error_Handler();
8000e0e: f000 fa21 bl 8001254 <Error_Handler>
}
if (HAL_HRTIM_WaveformCompareConfig(&hhrtim1, HRTIM_TIMERINDEX_TIMER_B, HRTIM_COMPAREUNIT_1, &pCompareCfg) != HAL_OK)
8000e12: f107 0344 add.w r3, r7, #68 @ 0x44
8000e16: 2201 movs r2, #1
8000e18: 2101 movs r1, #1
8000e1a: 4807 ldr r0, [pc, #28] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000e1c: f004 fa18 bl 8005250 <HAL_HRTIM_WaveformCompareConfig>
8000e20: 4603 mov r3, r0
8000e22: 2b00 cmp r3, #0
8000e24: d001 beq.n 8000e2a <MX_HRTIM1_Init+0x382>
{
Error_Handler();
8000e26: f000 fa15 bl 8001254 <Error_Handler>
}
/* USER CODE BEGIN HRTIM1_Init 2 */
/* USER CODE END HRTIM1_Init 2 */
HAL_HRTIM_MspPostInit(&hhrtim1);
8000e2a: 4803 ldr r0, [pc, #12] @ (8000e38 <MX_HRTIM1_Init+0x390>)
8000e2c: f000 fc5e bl 80016ec <HAL_HRTIM_MspPostInit>
}
8000e30: bf00 nop
8000e32: 37f0 adds r7, #240 @ 0xf0
8000e34: 46bd mov sp, r7
8000e36: bd80 pop {r7, pc}
8000e38: 20000290 .word 0x20000290
8000e3c: 40016800 .word 0x40016800
08000e40 <MX_TIM1_Init>:
* @brief TIM1 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM1_Init(void)
{
8000e40: b580 push {r7, lr}
8000e42: b088 sub sp, #32
8000e44: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_Init 0 */
/* USER CODE END TIM1_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000e46: f107 0310 add.w r3, r7, #16
8000e4a: 2200 movs r2, #0
8000e4c: 601a str r2, [r3, #0]
8000e4e: 605a str r2, [r3, #4]
8000e50: 609a str r2, [r3, #8]
8000e52: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000e54: 1d3b adds r3, r7, #4
8000e56: 2200 movs r2, #0
8000e58: 601a str r2, [r3, #0]
8000e5a: 605a str r2, [r3, #4]
8000e5c: 609a str r2, [r3, #8]
/* USER CODE BEGIN TIM1_Init 1 */
/* USER CODE END TIM1_Init 1 */
htim1.Instance = TIM1;
8000e5e: 4b1f ldr r3, [pc, #124] @ (8000edc <MX_TIM1_Init+0x9c>)
8000e60: 4a1f ldr r2, [pc, #124] @ (8000ee0 <MX_TIM1_Init+0xa0>)
8000e62: 601a str r2, [r3, #0]
htim1.Init.Prescaler = 17-1;
8000e64: 4b1d ldr r3, [pc, #116] @ (8000edc <MX_TIM1_Init+0x9c>)
8000e66: 2210 movs r2, #16
8000e68: 605a str r2, [r3, #4]
htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
8000e6a: 4b1c ldr r3, [pc, #112] @ (8000edc <MX_TIM1_Init+0x9c>)
8000e6c: 2200 movs r2, #0
8000e6e: 609a str r2, [r3, #8]
htim1.Init.Period = 199;
8000e70: 4b1a ldr r3, [pc, #104] @ (8000edc <MX_TIM1_Init+0x9c>)
8000e72: 22c7 movs r2, #199 @ 0xc7
8000e74: 60da str r2, [r3, #12]
htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000e76: 4b19 ldr r3, [pc, #100] @ (8000edc <MX_TIM1_Init+0x9c>)
8000e78: 2200 movs r2, #0
8000e7a: 611a str r2, [r3, #16]
htim1.Init.RepetitionCounter = 0;
8000e7c: 4b17 ldr r3, [pc, #92] @ (8000edc <MX_TIM1_Init+0x9c>)
8000e7e: 2200 movs r2, #0
8000e80: 615a str r2, [r3, #20]
htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000e82: 4b16 ldr r3, [pc, #88] @ (8000edc <MX_TIM1_Init+0x9c>)
8000e84: 2200 movs r2, #0
8000e86: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
8000e88: 4814 ldr r0, [pc, #80] @ (8000edc <MX_TIM1_Init+0x9c>)
8000e8a: f006 faa5 bl 80073d8 <HAL_TIM_Base_Init>
8000e8e: 4603 mov r3, r0
8000e90: 2b00 cmp r3, #0
8000e92: d001 beq.n 8000e98 <MX_TIM1_Init+0x58>
{
Error_Handler();
8000e94: f000 f9de bl 8001254 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000e98: f44f 5380 mov.w r3, #4096 @ 0x1000
8000e9c: 613b str r3, [r7, #16]
if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
8000e9e: f107 0310 add.w r3, r7, #16
8000ea2: 4619 mov r1, r3
8000ea4: 480d ldr r0, [pc, #52] @ (8000edc <MX_TIM1_Init+0x9c>)
8000ea6: f006 fea9 bl 8007bfc <HAL_TIM_ConfigClockSource>
8000eaa: 4603 mov r3, r0
8000eac: 2b00 cmp r3, #0
8000eae: d001 beq.n 8000eb4 <MX_TIM1_Init+0x74>
{
Error_Handler();
8000eb0: f000 f9d0 bl 8001254 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000eb4: 2300 movs r3, #0
8000eb6: 607b str r3, [r7, #4]
sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
8000eb8: 2300 movs r3, #0
8000eba: 60bb str r3, [r7, #8]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000ebc: 2300 movs r3, #0
8000ebe: 60fb str r3, [r7, #12]
if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
8000ec0: 1d3b adds r3, r7, #4
8000ec2: 4619 mov r1, r3
8000ec4: 4805 ldr r0, [pc, #20] @ (8000edc <MX_TIM1_Init+0x9c>)
8000ec6: f007 fc6d bl 80087a4 <HAL_TIMEx_MasterConfigSynchronization>
8000eca: 4603 mov r3, r0
8000ecc: 2b00 cmp r3, #0
8000ece: d001 beq.n 8000ed4 <MX_TIM1_Init+0x94>
{
Error_Handler();
8000ed0: f000 f9c0 bl 8001254 <Error_Handler>
}
/* USER CODE BEGIN TIM1_Init 2 */
/* USER CODE END TIM1_Init 2 */
}
8000ed4: bf00 nop
8000ed6: 3720 adds r7, #32
8000ed8: 46bd mov sp, r7
8000eda: bd80 pop {r7, pc}
8000edc: 2000038c .word 0x2000038c
8000ee0: 40012c00 .word 0x40012c00
08000ee4 <MX_TIM3_Init>:
* @brief TIM3 Initialization Function
* @param None
* @retval None
*/
static void MX_TIM3_Init(void)
{
8000ee4: b580 push {r7, lr}
8000ee6: b08e sub sp, #56 @ 0x38
8000ee8: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_Init 0 */
/* USER CODE END TIM3_Init 0 */
TIM_ClockConfigTypeDef sClockSourceConfig = {0};
8000eea: f107 0328 add.w r3, r7, #40 @ 0x28
8000eee: 2200 movs r2, #0
8000ef0: 601a str r2, [r3, #0]
8000ef2: 605a str r2, [r3, #4]
8000ef4: 609a str r2, [r3, #8]
8000ef6: 60da str r2, [r3, #12]
TIM_MasterConfigTypeDef sMasterConfig = {0};
8000ef8: f107 031c add.w r3, r7, #28
8000efc: 2200 movs r2, #0
8000efe: 601a str r2, [r3, #0]
8000f00: 605a str r2, [r3, #4]
8000f02: 609a str r2, [r3, #8]
TIM_OC_InitTypeDef sConfigOC = {0};
8000f04: 463b mov r3, r7
8000f06: 2200 movs r2, #0
8000f08: 601a str r2, [r3, #0]
8000f0a: 605a str r2, [r3, #4]
8000f0c: 609a str r2, [r3, #8]
8000f0e: 60da str r2, [r3, #12]
8000f10: 611a str r2, [r3, #16]
8000f12: 615a str r2, [r3, #20]
8000f14: 619a str r2, [r3, #24]
/* USER CODE BEGIN TIM3_Init 1 */
/* USER CODE END TIM3_Init 1 */
htim3.Instance = TIM3;
8000f16: 4b2b ldr r3, [pc, #172] @ (8000fc4 <MX_TIM3_Init+0xe0>)
8000f18: 4a2b ldr r2, [pc, #172] @ (8000fc8 <MX_TIM3_Init+0xe4>)
8000f1a: 601a str r2, [r3, #0]
htim3.Init.Prescaler = 17000-1;
8000f1c: 4b29 ldr r3, [pc, #164] @ (8000fc4 <MX_TIM3_Init+0xe0>)
8000f1e: f244 2267 movw r2, #16999 @ 0x4267
8000f22: 605a str r2, [r3, #4]
htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
8000f24: 4b27 ldr r3, [pc, #156] @ (8000fc4 <MX_TIM3_Init+0xe0>)
8000f26: 2200 movs r2, #0
8000f28: 609a str r2, [r3, #8]
htim3.Init.Period = 200;
8000f2a: 4b26 ldr r3, [pc, #152] @ (8000fc4 <MX_TIM3_Init+0xe0>)
8000f2c: 22c8 movs r2, #200 @ 0xc8
8000f2e: 60da str r2, [r3, #12]
htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
8000f30: 4b24 ldr r3, [pc, #144] @ (8000fc4 <MX_TIM3_Init+0xe0>)
8000f32: 2200 movs r2, #0
8000f34: 611a str r2, [r3, #16]
htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
8000f36: 4b23 ldr r3, [pc, #140] @ (8000fc4 <MX_TIM3_Init+0xe0>)
8000f38: 2200 movs r2, #0
8000f3a: 619a str r2, [r3, #24]
if (HAL_TIM_Base_Init(&htim3) != HAL_OK)
8000f3c: 4821 ldr r0, [pc, #132] @ (8000fc4 <MX_TIM3_Init+0xe0>)
8000f3e: f006 fa4b bl 80073d8 <HAL_TIM_Base_Init>
8000f42: 4603 mov r3, r0
8000f44: 2b00 cmp r3, #0
8000f46: d001 beq.n 8000f4c <MX_TIM3_Init+0x68>
{
Error_Handler();
8000f48: f000 f984 bl 8001254 <Error_Handler>
}
sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
8000f4c: f44f 5380 mov.w r3, #4096 @ 0x1000
8000f50: 62bb str r3, [r7, #40] @ 0x28
if (HAL_TIM_ConfigClockSource(&htim3, &sClockSourceConfig) != HAL_OK)
8000f52: f107 0328 add.w r3, r7, #40 @ 0x28
8000f56: 4619 mov r1, r3
8000f58: 481a ldr r0, [pc, #104] @ (8000fc4 <MX_TIM3_Init+0xe0>)
8000f5a: f006 fe4f bl 8007bfc <HAL_TIM_ConfigClockSource>
8000f5e: 4603 mov r3, r0
8000f60: 2b00 cmp r3, #0
8000f62: d001 beq.n 8000f68 <MX_TIM3_Init+0x84>
{
Error_Handler();
8000f64: f000 f976 bl 8001254 <Error_Handler>
}
if (HAL_TIM_OC_Init(&htim3) != HAL_OK)
8000f68: 4816 ldr r0, [pc, #88] @ (8000fc4 <MX_TIM3_Init+0xe0>)
8000f6a: f006 fabb bl 80074e4 <HAL_TIM_OC_Init>
8000f6e: 4603 mov r3, r0
8000f70: 2b00 cmp r3, #0
8000f72: d001 beq.n 8000f78 <MX_TIM3_Init+0x94>
{
Error_Handler();
8000f74: f000 f96e bl 8001254 <Error_Handler>
}
sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
8000f78: 2300 movs r3, #0
8000f7a: 61fb str r3, [r7, #28]
sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
8000f7c: 2300 movs r3, #0
8000f7e: 627b str r3, [r7, #36] @ 0x24
if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
8000f80: f107 031c add.w r3, r7, #28
8000f84: 4619 mov r1, r3
8000f86: 480f ldr r0, [pc, #60] @ (8000fc4 <MX_TIM3_Init+0xe0>)
8000f88: f007 fc0c bl 80087a4 <HAL_TIMEx_MasterConfigSynchronization>
8000f8c: 4603 mov r3, r0
8000f8e: 2b00 cmp r3, #0
8000f90: d001 beq.n 8000f96 <MX_TIM3_Init+0xb2>
{
Error_Handler();
8000f92: f000 f95f bl 8001254 <Error_Handler>
}
sConfigOC.OCMode = TIM_OCMODE_TIMING;
8000f96: 2300 movs r3, #0
8000f98: 603b str r3, [r7, #0]
sConfigOC.Pulse = 100;
8000f9a: 2364 movs r3, #100 @ 0x64
8000f9c: 607b str r3, [r7, #4]
sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
8000f9e: 2300 movs r3, #0
8000fa0: 60bb str r3, [r7, #8]
sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
8000fa2: 2300 movs r3, #0
8000fa4: 613b str r3, [r7, #16]
if (HAL_TIM_OC_ConfigChannel(&htim3, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
8000fa6: 463b mov r3, r7
8000fa8: 2208 movs r2, #8
8000faa: 4619 mov r1, r3
8000fac: 4805 ldr r0, [pc, #20] @ (8000fc4 <MX_TIM3_Init+0xe0>)
8000fae: f006 fdab bl 8007b08 <HAL_TIM_OC_ConfigChannel>
8000fb2: 4603 mov r3, r0
8000fb4: 2b00 cmp r3, #0
8000fb6: d001 beq.n 8000fbc <MX_TIM3_Init+0xd8>
{
Error_Handler();
8000fb8: f000 f94c bl 8001254 <Error_Handler>
}
/* USER CODE BEGIN TIM3_Init 2 */
/* USER CODE END TIM3_Init 2 */
}
8000fbc: bf00 nop
8000fbe: 3738 adds r7, #56 @ 0x38
8000fc0: 46bd mov sp, r7
8000fc2: bd80 pop {r7, pc}
8000fc4: 200003d8 .word 0x200003d8
8000fc8: 40000400 .word 0x40000400
08000fcc <MX_USART1_UART_Init>:
* @brief USART1 Initialization Function
* @param None
* @retval None
*/
static void MX_USART1_UART_Init(void)
{
8000fcc: b580 push {r7, lr}
8000fce: af00 add r7, sp, #0
/* USER CODE END USART1_Init 0 */
/* USER CODE BEGIN USART1_Init 1 */
/* USER CODE END USART1_Init 1 */
huart1.Instance = USART1;
8000fd0: 4b22 ldr r3, [pc, #136] @ (800105c <MX_USART1_UART_Init+0x90>)
8000fd2: 4a23 ldr r2, [pc, #140] @ (8001060 <MX_USART1_UART_Init+0x94>)
8000fd4: 601a str r2, [r3, #0]
huart1.Init.BaudRate = 115200;
8000fd6: 4b21 ldr r3, [pc, #132] @ (800105c <MX_USART1_UART_Init+0x90>)
8000fd8: f44f 32e1 mov.w r2, #115200 @ 0x1c200
8000fdc: 605a str r2, [r3, #4]
huart1.Init.WordLength = UART_WORDLENGTH_8B;
8000fde: 4b1f ldr r3, [pc, #124] @ (800105c <MX_USART1_UART_Init+0x90>)
8000fe0: 2200 movs r2, #0
8000fe2: 609a str r2, [r3, #8]
huart1.Init.StopBits = UART_STOPBITS_1;
8000fe4: 4b1d ldr r3, [pc, #116] @ (800105c <MX_USART1_UART_Init+0x90>)
8000fe6: 2200 movs r2, #0
8000fe8: 60da str r2, [r3, #12]
huart1.Init.Parity = UART_PARITY_NONE;
8000fea: 4b1c ldr r3, [pc, #112] @ (800105c <MX_USART1_UART_Init+0x90>)
8000fec: 2200 movs r2, #0
8000fee: 611a str r2, [r3, #16]
huart1.Init.Mode = UART_MODE_TX_RX;
8000ff0: 4b1a ldr r3, [pc, #104] @ (800105c <MX_USART1_UART_Init+0x90>)
8000ff2: 220c movs r2, #12
8000ff4: 615a str r2, [r3, #20]
huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
8000ff6: 4b19 ldr r3, [pc, #100] @ (800105c <MX_USART1_UART_Init+0x90>)
8000ff8: 2200 movs r2, #0
8000ffa: 619a str r2, [r3, #24]
huart1.Init.OverSampling = UART_OVERSAMPLING_16;
8000ffc: 4b17 ldr r3, [pc, #92] @ (800105c <MX_USART1_UART_Init+0x90>)
8000ffe: 2200 movs r2, #0
8001000: 61da str r2, [r3, #28]
huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
8001002: 4b16 ldr r3, [pc, #88] @ (800105c <MX_USART1_UART_Init+0x90>)
8001004: 2200 movs r2, #0
8001006: 621a str r2, [r3, #32]
huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
8001008: 4b14 ldr r3, [pc, #80] @ (800105c <MX_USART1_UART_Init+0x90>)
800100a: 2200 movs r2, #0
800100c: 625a str r2, [r3, #36] @ 0x24
huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
800100e: 4b13 ldr r3, [pc, #76] @ (800105c <MX_USART1_UART_Init+0x90>)
8001010: 2200 movs r2, #0
8001012: 629a str r2, [r3, #40] @ 0x28
if (HAL_UART_Init(&huart1) != HAL_OK)
8001014: 4811 ldr r0, [pc, #68] @ (800105c <MX_USART1_UART_Init+0x90>)
8001016: f007 fca1 bl 800895c <HAL_UART_Init>
800101a: 4603 mov r3, r0
800101c: 2b00 cmp r3, #0
800101e: d001 beq.n 8001024 <MX_USART1_UART_Init+0x58>
{
Error_Handler();
8001020: f000 f918 bl 8001254 <Error_Handler>
}
if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
8001024: 2100 movs r1, #0
8001026: 480d ldr r0, [pc, #52] @ (800105c <MX_USART1_UART_Init+0x90>)
8001028: f008 faca bl 80095c0 <HAL_UARTEx_SetTxFifoThreshold>
800102c: 4603 mov r3, r0
800102e: 2b00 cmp r3, #0
8001030: d001 beq.n 8001036 <MX_USART1_UART_Init+0x6a>
{
Error_Handler();
8001032: f000 f90f bl 8001254 <Error_Handler>
}
if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
8001036: 2100 movs r1, #0
8001038: 4808 ldr r0, [pc, #32] @ (800105c <MX_USART1_UART_Init+0x90>)
800103a: f008 faff bl 800963c <HAL_UARTEx_SetRxFifoThreshold>
800103e: 4603 mov r3, r0
8001040: 2b00 cmp r3, #0
8001042: d001 beq.n 8001048 <MX_USART1_UART_Init+0x7c>
{
Error_Handler();
8001044: f000 f906 bl 8001254 <Error_Handler>
}
if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
8001048: 4804 ldr r0, [pc, #16] @ (800105c <MX_USART1_UART_Init+0x90>)
800104a: f008 fa80 bl 800954e <HAL_UARTEx_DisableFifoMode>
800104e: 4603 mov r3, r0
8001050: 2b00 cmp r3, #0
8001052: d001 beq.n 8001058 <MX_USART1_UART_Init+0x8c>
{
Error_Handler();
8001054: f000 f8fe bl 8001254 <Error_Handler>
}
/* USER CODE BEGIN USART1_Init 2 */
/* USER CODE END USART1_Init 2 */
}
8001058: bf00 nop
800105a: bd80 pop {r7, pc}
800105c: 20000424 .word 0x20000424
8001060: 40013800 .word 0x40013800
08001064 <MX_DMA_Init>:
/**
* Enable DMA controller clock
*/
static void MX_DMA_Init(void)
{
8001064: b480 push {r7}
8001066: b083 sub sp, #12
8001068: af00 add r7, sp, #0
/* DMA controller clock enable */
__HAL_RCC_DMAMUX1_CLK_ENABLE();
800106a: 4b0f ldr r3, [pc, #60] @ (80010a8 <MX_DMA_Init+0x44>)
800106c: 6c9b ldr r3, [r3, #72] @ 0x48
800106e: 4a0e ldr r2, [pc, #56] @ (80010a8 <MX_DMA_Init+0x44>)
8001070: f043 0304 orr.w r3, r3, #4
8001074: 6493 str r3, [r2, #72] @ 0x48
8001076: 4b0c ldr r3, [pc, #48] @ (80010a8 <MX_DMA_Init+0x44>)
8001078: 6c9b ldr r3, [r3, #72] @ 0x48
800107a: f003 0304 and.w r3, r3, #4
800107e: 607b str r3, [r7, #4]
8001080: 687b ldr r3, [r7, #4]
__HAL_RCC_DMA1_CLK_ENABLE();
8001082: 4b09 ldr r3, [pc, #36] @ (80010a8 <MX_DMA_Init+0x44>)
8001084: 6c9b ldr r3, [r3, #72] @ 0x48
8001086: 4a08 ldr r2, [pc, #32] @ (80010a8 <MX_DMA_Init+0x44>)
8001088: f043 0301 orr.w r3, r3, #1
800108c: 6493 str r3, [r2, #72] @ 0x48
800108e: 4b06 ldr r3, [pc, #24] @ (80010a8 <MX_DMA_Init+0x44>)
8001090: 6c9b ldr r3, [r3, #72] @ 0x48
8001092: f003 0301 and.w r3, r3, #1
8001096: 603b str r3, [r7, #0]
8001098: 683b ldr r3, [r7, #0]
}
800109a: bf00 nop
800109c: 370c adds r7, #12
800109e: 46bd mov sp, r7
80010a0: f85d 7b04 ldr.w r7, [sp], #4
80010a4: 4770 bx lr
80010a6: bf00 nop
80010a8: 40021000 .word 0x40021000
080010ac <MX_GPIO_Init>:
* @brief GPIO Initialization Function
* @param None
* @retval None
*/
static void MX_GPIO_Init(void)
{
80010ac: b580 push {r7, lr}
80010ae: b088 sub sp, #32
80010b0: af00 add r7, sp, #0
GPIO_InitTypeDef GPIO_InitStruct = {0};
80010b2: f107 030c add.w r3, r7, #12
80010b6: 2200 movs r2, #0
80010b8: 601a str r2, [r3, #0]
80010ba: 605a str r2, [r3, #4]
80010bc: 609a str r2, [r3, #8]
80010be: 60da str r2, [r3, #12]
80010c0: 611a str r2, [r3, #16]
/* USER CODE BEGIN MX_GPIO_Init_1 */
/* USER CODE END MX_GPIO_Init_1 */
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOF_CLK_ENABLE();
80010c2: 4b25 ldr r3, [pc, #148] @ (8001158 <MX_GPIO_Init+0xac>)
80010c4: 6cdb ldr r3, [r3, #76] @ 0x4c
80010c6: 4a24 ldr r2, [pc, #144] @ (8001158 <MX_GPIO_Init+0xac>)
80010c8: f043 0320 orr.w r3, r3, #32
80010cc: 64d3 str r3, [r2, #76] @ 0x4c
80010ce: 4b22 ldr r3, [pc, #136] @ (8001158 <MX_GPIO_Init+0xac>)
80010d0: 6cdb ldr r3, [r3, #76] @ 0x4c
80010d2: f003 0320 and.w r3, r3, #32
80010d6: 60bb str r3, [r7, #8]
80010d8: 68bb ldr r3, [r7, #8]
__HAL_RCC_GPIOB_CLK_ENABLE();
80010da: 4b1f ldr r3, [pc, #124] @ (8001158 <MX_GPIO_Init+0xac>)
80010dc: 6cdb ldr r3, [r3, #76] @ 0x4c
80010de: 4a1e ldr r2, [pc, #120] @ (8001158 <MX_GPIO_Init+0xac>)
80010e0: f043 0302 orr.w r3, r3, #2
80010e4: 64d3 str r3, [r2, #76] @ 0x4c
80010e6: 4b1c ldr r3, [pc, #112] @ (8001158 <MX_GPIO_Init+0xac>)
80010e8: 6cdb ldr r3, [r3, #76] @ 0x4c
80010ea: f003 0302 and.w r3, r3, #2
80010ee: 607b str r3, [r7, #4]
80010f0: 687b ldr r3, [r7, #4]
__HAL_RCC_GPIOA_CLK_ENABLE();
80010f2: 4b19 ldr r3, [pc, #100] @ (8001158 <MX_GPIO_Init+0xac>)
80010f4: 6cdb ldr r3, [r3, #76] @ 0x4c
80010f6: 4a18 ldr r2, [pc, #96] @ (8001158 <MX_GPIO_Init+0xac>)
80010f8: f043 0301 orr.w r3, r3, #1
80010fc: 64d3 str r3, [r2, #76] @ 0x4c
80010fe: 4b16 ldr r3, [pc, #88] @ (8001158 <MX_GPIO_Init+0xac>)
8001100: 6cdb ldr r3, [r3, #76] @ 0x4c
8001102: f003 0301 and.w r3, r3, #1
8001106: 603b str r3, [r7, #0]
8001108: 683b ldr r3, [r7, #0]
/*Configure GPIO pin Output Level */
HAL_GPIO_WritePin(GPIOB, ENABLE_DRVA1_Pin|ENABLE_DRVB1_Pin|ENABLE_DRVA2_Pin|ENABLE_DRVB2_Pin, GPIO_PIN_RESET);
800110a: 2200 movs r2, #0
800110c: f641 0130 movw r1, #6192 @ 0x1830
8001110: 4812 ldr r0, [pc, #72] @ (800115c <MX_GPIO_Init+0xb0>)
8001112: f003 fd59 bl 8004bc8 <HAL_GPIO_WritePin>
/*Configure GPIO pins : ENABLE_DRVA1_Pin ENABLE_DRVB1_Pin */
GPIO_InitStruct.Pin = ENABLE_DRVA1_Pin|ENABLE_DRVB1_Pin;
8001116: f44f 53c0 mov.w r3, #6144 @ 0x1800
800111a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
800111c: 2301 movs r3, #1
800111e: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_PULLDOWN;
8001120: 2302 movs r3, #2
8001122: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001124: 2300 movs r3, #0
8001126: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001128: f107 030c add.w r3, r7, #12
800112c: 4619 mov r1, r3
800112e: 480b ldr r0, [pc, #44] @ (800115c <MX_GPIO_Init+0xb0>)
8001130: f003 fbc8 bl 80048c4 <HAL_GPIO_Init>
/*Configure GPIO pins : ENABLE_DRVA2_Pin ENABLE_DRVB2_Pin */
GPIO_InitStruct.Pin = ENABLE_DRVA2_Pin|ENABLE_DRVB2_Pin;
8001134: 2330 movs r3, #48 @ 0x30
8001136: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
8001138: 2301 movs r3, #1
800113a: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800113c: 2300 movs r3, #0
800113e: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001140: 2300 movs r3, #0
8001142: 61bb str r3, [r7, #24]
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
8001144: f107 030c add.w r3, r7, #12
8001148: 4619 mov r1, r3
800114a: 4804 ldr r0, [pc, #16] @ (800115c <MX_GPIO_Init+0xb0>)
800114c: f003 fbba bl 80048c4 <HAL_GPIO_Init>
/* USER CODE BEGIN MX_GPIO_Init_2 */
/* USER CODE END MX_GPIO_Init_2 */
}
8001150: bf00 nop
8001152: 3720 adds r7, #32
8001154: 46bd mov sp, r7
8001156: bd80 pop {r7, pc}
8001158: 40021000 .word 0x40021000
800115c: 48000400 .word 0x48000400
08001160 <HAL_TIM_PeriodElapsedCallback>:
/* USER CODE BEGIN 4 */
void HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef * htim)
{
8001160: b480 push {r7}
8001162: b083 sub sp, #12
8001164: af00 add r7, sp, #0
8001166: 6078 str r0, [r7, #4]
}
#endif
#ifdef EXPERIMENTAL
if (htim == &htim3)
8001168: 687b ldr r3, [r7, #4]
800116a: 4a08 ldr r2, [pc, #32] @ (800118c <HAL_TIM_PeriodElapsedCallback+0x2c>)
800116c: 4293 cmp r3, r2
800116e: d107 bne.n 8001180 <HAL_TIM_PeriodElapsedCallback+0x20>
{
HRTIM1->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].CMP1xR = 0;
8001170: 4b07 ldr r3, [pc, #28] @ (8001190 <HAL_TIM_PeriodElapsedCallback+0x30>)
8001172: 2200 movs r2, #0
8001174: f8c3 209c str.w r2, [r3, #156] @ 0x9c
HRTIM1->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].CMP1xR = 0;
8001178: 4b05 ldr r3, [pc, #20] @ (8001190 <HAL_TIM_PeriodElapsedCallback+0x30>)
800117a: 2200 movs r2, #0
800117c: f8c3 211c str.w r2, [r3, #284] @ 0x11c
}
#endif
}
8001180: bf00 nop
8001182: 370c adds r7, #12
8001184: 46bd mov sp, r7
8001186: f85d 7b04 ldr.w r7, [sp], #4
800118a: 4770 bx lr
800118c: 200003d8 .word 0x200003d8
8001190: 40016800 .word 0x40016800
08001194 <HAL_TIM_OC_DelayElapsedCallback>:
void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
{
8001194: b480 push {r7}
8001196: b083 sub sp, #12
8001198: af00 add r7, sp, #0
800119a: 6078 str r0, [r7, #4]
if (htim == &htim3)
800119c: 687b ldr r3, [r7, #4]
800119e: 4a09 ldr r2, [pc, #36] @ (80011c4 <HAL_TIM_OC_DelayElapsedCallback+0x30>)
80011a0: 4293 cmp r3, r2
80011a2: d108 bne.n 80011b6 <HAL_TIM_OC_DelayElapsedCallback+0x22>
{
//turn on
#ifdef POLARITY
HRTIM1->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].CMP1xR = 0xD480;
80011a4: 4b08 ldr r3, [pc, #32] @ (80011c8 <HAL_TIM_OC_DelayElapsedCallback+0x34>)
80011a6: f24d 4280 movw r2, #54400 @ 0xd480
80011aa: f8c3 209c str.w r2, [r3, #156] @ 0x9c
HRTIM1->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].CMP1xR = 0;
80011ae: 4b06 ldr r3, [pc, #24] @ (80011c8 <HAL_TIM_OC_DelayElapsedCallback+0x34>)
80011b0: 2200 movs r2, #0
80011b2: f8c3 211c str.w r2, [r3, #284] @ 0x11c
HRTIM1->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_B].CMP1xR = 0xD480;
HRTIM1->sTimerxRegs[HRTIM_TIMERINDEX_TIMER_A].CMP1xR = 0;
#endif
}
}
80011b6: bf00 nop
80011b8: 370c adds r7, #12
80011ba: 46bd mov sp, r7
80011bc: f85d 7b04 ldr.w r7, [sp], #4
80011c0: 4770 bx lr
80011c2: bf00 nop
80011c4: 200003d8 .word 0x200003d8
80011c8: 40016800 .word 0x40016800
080011cc <HAL_COMP_TriggerCallback>:
void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
{
80011cc: b580 push {r7, lr}
80011ce: b088 sub sp, #32
80011d0: af00 add r7, sp, #0
80011d2: 6078 str r0, [r7, #4]
HAL_GPIO_WritePin(ENABLE_DRVA1_GPIO_Port,ENABLE_DRVA1_Pin,GPIO_PIN_RESET);//LG1
80011d4: 2200 movs r2, #0
80011d6: f44f 6100 mov.w r1, #2048 @ 0x800
80011da: 4819 ldr r0, [pc, #100] @ (8001240 <HAL_COMP_TriggerCallback+0x74>)
80011dc: f003 fcf4 bl 8004bc8 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(ENABLE_DRVA2_GPIO_Port,ENABLE_DRVA2_Pin,GPIO_PIN_RESET);//LG2
80011e0: 2200 movs r2, #0
80011e2: 2110 movs r1, #16
80011e4: 4816 ldr r0, [pc, #88] @ (8001240 <HAL_COMP_TriggerCallback+0x74>)
80011e6: f003 fcef bl 8004bc8 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(ENABLE_DRVB1_GPIO_Port,ENABLE_DRVB1_Pin,GPIO_PIN_RESET);//HG1
80011ea: 2200 movs r2, #0
80011ec: f44f 5180 mov.w r1, #4096 @ 0x1000
80011f0: 4813 ldr r0, [pc, #76] @ (8001240 <HAL_COMP_TriggerCallback+0x74>)
80011f2: f003 fce9 bl 8004bc8 <HAL_GPIO_WritePin>
HAL_GPIO_WritePin(ENABLE_DRVB2_GPIO_Port,ENABLE_DRVB2_Pin,GPIO_PIN_RESET);//HG2
80011f6: 2200 movs r2, #0
80011f8: 2120 movs r1, #32
80011fa: 4811 ldr r0, [pc, #68] @ (8001240 <HAL_COMP_TriggerCallback+0x74>)
80011fc: f003 fce4 bl 8004bc8 <HAL_GPIO_WritePin>
HAL_HRTIM_WaveformOutputStop(&hhrtim1,HRTIM_OUTPUT_TB2|HRTIM_OUTPUT_TB1|HRTIM_OUTPUT_TA2|HRTIM_OUTPUT_TA1);
8001200: 210f movs r1, #15
8001202: 4810 ldr r0, [pc, #64] @ (8001244 <HAL_COMP_TriggerCallback+0x78>)
8001204: f004 f9f0 bl 80055e8 <HAL_HRTIM_WaveformOutputStop>
HAL_TIM_Base_Stop_IT(&htim1);
8001208: 480f ldr r0, [pc, #60] @ (8001248 <HAL_COMP_TriggerCallback+0x7c>)
800120a: f006 f93c bl 8007486 <HAL_TIM_Base_Stop_IT>
char etext[20] = "COMP IT\n\r";
800120e: 4a0f ldr r2, [pc, #60] @ (800124c <HAL_COMP_TriggerCallback+0x80>)
8001210: f107 030c add.w r3, r7, #12
8001214: ca07 ldmia r2, {r0, r1, r2}
8001216: c303 stmia r3!, {r0, r1}
8001218: 801a strh r2, [r3, #0]
800121a: f107 0316 add.w r3, r7, #22
800121e: 2200 movs r2, #0
8001220: 601a str r2, [r3, #0]
8001222: 605a str r2, [r3, #4]
8001224: 811a strh r2, [r3, #8]
HAL_UART_Transmit(&huart1,(uint8_t *)(etext),11,10);
8001226: f107 010c add.w r1, r7, #12
800122a: 230a movs r3, #10
800122c: 220b movs r2, #11
800122e: 4808 ldr r0, [pc, #32] @ (8001250 <HAL_COMP_TriggerCallback+0x84>)
8001230: f007 fbe4 bl 80089fc <HAL_UART_Transmit>
Error_Handler();
8001234: f000 f80e bl 8001254 <Error_Handler>
}
8001238: bf00 nop
800123a: 3720 adds r7, #32
800123c: 46bd mov sp, r7
800123e: bd80 pop {r7, pc}
8001240: 48000400 .word 0x48000400
8001244: 20000290 .word 0x20000290
8001248: 2000038c .word 0x2000038c
800124c: 080097d8 .word 0x080097d8
8001250: 20000424 .word 0x20000424
08001254 <Error_Handler>:
/**
* @brief This function is executed in case of error occurrence.
* @retval None
*/
void Error_Handler(void)
{
8001254: b580 push {r7, lr}
8001256: b086 sub sp, #24
8001258: af00 add r7, sp, #0
/* USER CODE BEGIN Error_Handler_Debug */
/* User can add his own implementation to report the HAL error return state */
char etext[20] = "Error \n\r";
800125a: 4a0b ldr r2, [pc, #44] @ (8001288 <Error_Handler+0x34>)
800125c: 1d3b adds r3, r7, #4
800125e: ca07 ldmia r2, {r0, r1, r2}
8001260: c303 stmia r3!, {r0, r1}
8001262: 701a strb r2, [r3, #0]
8001264: f107 030d add.w r3, r7, #13
8001268: 2200 movs r2, #0
800126a: 601a str r2, [r3, #0]
800126c: 605a str r2, [r3, #4]
800126e: f8c3 2007 str.w r2, [r3, #7]
HAL_UART_Transmit(&huart1,(uint8_t *)(etext),10,10);
8001272: 1d39 adds r1, r7, #4
8001274: 230a movs r3, #10
8001276: 220a movs r2, #10
8001278: 4804 ldr r0, [pc, #16] @ (800128c <Error_Handler+0x38>)
800127a: f007 fbbf bl 80089fc <HAL_UART_Transmit>
\details Disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__STATIC_FORCEINLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i" : : : "memory");
800127e: b672 cpsid i
}
8001280: bf00 nop
__disable_irq();
while (1)
8001282: bf00 nop
8001284: e7fd b.n 8001282 <Error_Handler+0x2e>
8001286: bf00 nop
8001288: 080097ec .word 0x080097ec
800128c: 20000424 .word 0x20000424
08001290 <HAL_MspInit>:
void HAL_HRTIM_MspPostInit(HRTIM_HandleTypeDef *hhrtim);
/**
* Initializes the Global MSP.
*/
void HAL_MspInit(void)
{
8001290: b580 push {r7, lr}
8001292: b082 sub sp, #8
8001294: af00 add r7, sp, #0
/* USER CODE BEGIN MspInit 0 */
/* USER CODE END MspInit 0 */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8001296: 4b13 ldr r3, [pc, #76] @ (80012e4 <HAL_MspInit+0x54>)
8001298: 6e1b ldr r3, [r3, #96] @ 0x60
800129a: 4a12 ldr r2, [pc, #72] @ (80012e4 <HAL_MspInit+0x54>)
800129c: f043 0301 orr.w r3, r3, #1
80012a0: 6613 str r3, [r2, #96] @ 0x60
80012a2: 4b10 ldr r3, [pc, #64] @ (80012e4 <HAL_MspInit+0x54>)
80012a4: 6e1b ldr r3, [r3, #96] @ 0x60
80012a6: f003 0301 and.w r3, r3, #1
80012aa: 607b str r3, [r7, #4]
80012ac: 687b ldr r3, [r7, #4]
__HAL_RCC_PWR_CLK_ENABLE();
80012ae: 4b0d ldr r3, [pc, #52] @ (80012e4 <HAL_MspInit+0x54>)
80012b0: 6d9b ldr r3, [r3, #88] @ 0x58
80012b2: 4a0c ldr r2, [pc, #48] @ (80012e4 <HAL_MspInit+0x54>)
80012b4: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80012b8: 6593 str r3, [r2, #88] @ 0x58
80012ba: 4b0a ldr r3, [pc, #40] @ (80012e4 <HAL_MspInit+0x54>)
80012bc: 6d9b ldr r3, [r3, #88] @ 0x58
80012be: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80012c2: 603b str r3, [r7, #0]
80012c4: 683b ldr r3, [r7, #0]
/* System interrupt init*/
/** Configure the internal voltage reference buffer voltage scale
*/
HAL_SYSCFG_VREFBUF_VoltageScalingConfig(SYSCFG_VREFBUF_VOLTAGE_SCALE1);
80012c6: 2010 movs r0, #16
80012c8: f000 fc3e bl 8001b48 <HAL_SYSCFG_VREFBUF_VoltageScalingConfig>
/** Configure the internal voltage reference buffer high impedance mode
*/
HAL_SYSCFG_VREFBUF_HighImpedanceConfig(SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE);
80012cc: 2000 movs r0, #0
80012ce: f000 fc4f bl 8001b70 <HAL_SYSCFG_VREFBUF_HighImpedanceConfig>
/** Enable the Internal Voltage Reference buffer
*/
HAL_SYSCFG_EnableVREFBUF();
80012d2: f000 fc61 bl 8001b98 <HAL_SYSCFG_EnableVREFBUF>
/** Disable the internal Pull-Up in Dead Battery pins of UCPD peripheral
*/
HAL_PWREx_DisableUCPDDeadBattery();
80012d6: f005 f8f3 bl 80064c0 <HAL_PWREx_DisableUCPDDeadBattery>
/* USER CODE BEGIN MspInit 1 */
/* USER CODE END MspInit 1 */
}
80012da: bf00 nop
80012dc: 3708 adds r7, #8
80012de: 46bd mov sp, r7
80012e0: bd80 pop {r7, pc}
80012e2: bf00 nop
80012e4: 40021000 .word 0x40021000
080012e8 <HAL_ADC_MspInit>:
* This function configures the hardware resources used in this example
* @param hadc: ADC handle pointer
* @retval None
*/
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
{
80012e8: b580 push {r7, lr}
80012ea: b0a0 sub sp, #128 @ 0x80
80012ec: af00 add r7, sp, #0
80012ee: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80012f0: f107 036c add.w r3, r7, #108 @ 0x6c
80012f4: 2200 movs r2, #0
80012f6: 601a str r2, [r3, #0]
80012f8: 605a str r2, [r3, #4]
80012fa: 609a str r2, [r3, #8]
80012fc: 60da str r2, [r3, #12]
80012fe: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8001300: f107 0318 add.w r3, r7, #24
8001304: 2254 movs r2, #84 @ 0x54
8001306: 2100 movs r1, #0
8001308: 4618 mov r0, r3
800130a: f008 fa23 bl 8009754 <memset>
if(hadc->Instance==ADC3)
800130e: 687b ldr r3, [r7, #4]
8001310: 681b ldr r3, [r3, #0]
8001312: 4a70 ldr r2, [pc, #448] @ (80014d4 <HAL_ADC_MspInit+0x1ec>)
8001314: 4293 cmp r3, r2
8001316: d16a bne.n 80013ee <HAL_ADC_MspInit+0x106>
/* USER CODE END ADC3_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC345;
8001318: f44f 3380 mov.w r3, #65536 @ 0x10000
800131c: 61bb str r3, [r7, #24]
PeriphClkInit.Adc345ClockSelection = RCC_ADC345CLKSOURCE_SYSCLK;
800131e: f04f 4300 mov.w r3, #2147483648 @ 0x80000000
8001322: 663b str r3, [r7, #96] @ 0x60
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001324: f107 0318 add.w r3, r7, #24
8001328: 4618 mov r0, r3
800132a: f005 fe07 bl 8006f3c <HAL_RCCEx_PeriphCLKConfig>
800132e: 4603 mov r3, r0
8001330: 2b00 cmp r3, #0
8001332: d001 beq.n 8001338 <HAL_ADC_MspInit+0x50>
{
Error_Handler();
8001334: f7ff ff8e bl 8001254 <Error_Handler>
}
/* Peripheral clock enable */
HAL_RCC_ADC345_CLK_ENABLED++;
8001338: 4b67 ldr r3, [pc, #412] @ (80014d8 <HAL_ADC_MspInit+0x1f0>)
800133a: 681b ldr r3, [r3, #0]
800133c: 3301 adds r3, #1
800133e: 4a66 ldr r2, [pc, #408] @ (80014d8 <HAL_ADC_MspInit+0x1f0>)
8001340: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC345_CLK_ENABLED==1){
8001342: 4b65 ldr r3, [pc, #404] @ (80014d8 <HAL_ADC_MspInit+0x1f0>)
8001344: 681b ldr r3, [r3, #0]
8001346: 2b01 cmp r3, #1
8001348: d10b bne.n 8001362 <HAL_ADC_MspInit+0x7a>
__HAL_RCC_ADC345_CLK_ENABLE();
800134a: 4b64 ldr r3, [pc, #400] @ (80014dc <HAL_ADC_MspInit+0x1f4>)
800134c: 6cdb ldr r3, [r3, #76] @ 0x4c
800134e: 4a63 ldr r2, [pc, #396] @ (80014dc <HAL_ADC_MspInit+0x1f4>)
8001350: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001354: 64d3 str r3, [r2, #76] @ 0x4c
8001356: 4b61 ldr r3, [pc, #388] @ (80014dc <HAL_ADC_MspInit+0x1f4>)
8001358: 6cdb ldr r3, [r3, #76] @ 0x4c
800135a: f403 4380 and.w r3, r3, #16384 @ 0x4000
800135e: 617b str r3, [r7, #20]
8001360: 697b ldr r3, [r7, #20]
}
__HAL_RCC_GPIOB_CLK_ENABLE();
8001362: 4b5e ldr r3, [pc, #376] @ (80014dc <HAL_ADC_MspInit+0x1f4>)
8001364: 6cdb ldr r3, [r3, #76] @ 0x4c
8001366: 4a5d ldr r2, [pc, #372] @ (80014dc <HAL_ADC_MspInit+0x1f4>)
8001368: f043 0302 orr.w r3, r3, #2
800136c: 64d3 str r3, [r2, #76] @ 0x4c
800136e: 4b5b ldr r3, [pc, #364] @ (80014dc <HAL_ADC_MspInit+0x1f4>)
8001370: 6cdb ldr r3, [r3, #76] @ 0x4c
8001372: f003 0302 and.w r3, r3, #2
8001376: 613b str r3, [r7, #16]
8001378: 693b ldr r3, [r7, #16]
/**ADC3 GPIO Configuration
PB13 ------> ADC3_IN5
*/
GPIO_InitStruct.Pin = VOLTAGE_Pin;
800137a: f44f 5300 mov.w r3, #8192 @ 0x2000
800137e: 66fb str r3, [r7, #108] @ 0x6c
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001380: 2303 movs r3, #3
8001382: 673b str r3, [r7, #112] @ 0x70
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001384: 2300 movs r3, #0
8001386: 677b str r3, [r7, #116] @ 0x74
HAL_GPIO_Init(VOLTAGE_GPIO_Port, &GPIO_InitStruct);
8001388: f107 036c add.w r3, r7, #108 @ 0x6c
800138c: 4619 mov r1, r3
800138e: 4854 ldr r0, [pc, #336] @ (80014e0 <HAL_ADC_MspInit+0x1f8>)
8001390: f003 fa98 bl 80048c4 <HAL_GPIO_Init>
/* ADC3 DMA Init */
/* ADC3 Init */
hdma_adc3.Instance = DMA1_Channel1;
8001394: 4b53 ldr r3, [pc, #332] @ (80014e4 <HAL_ADC_MspInit+0x1fc>)
8001396: 4a54 ldr r2, [pc, #336] @ (80014e8 <HAL_ADC_MspInit+0x200>)
8001398: 601a str r2, [r3, #0]
hdma_adc3.Init.Request = DMA_REQUEST_ADC3;
800139a: 4b52 ldr r3, [pc, #328] @ (80014e4 <HAL_ADC_MspInit+0x1fc>)
800139c: 2225 movs r2, #37 @ 0x25
800139e: 605a str r2, [r3, #4]
hdma_adc3.Init.Direction = DMA_PERIPH_TO_MEMORY;
80013a0: 4b50 ldr r3, [pc, #320] @ (80014e4 <HAL_ADC_MspInit+0x1fc>)
80013a2: 2200 movs r2, #0
80013a4: 609a str r2, [r3, #8]
hdma_adc3.Init.PeriphInc = DMA_PINC_DISABLE;
80013a6: 4b4f ldr r3, [pc, #316] @ (80014e4 <HAL_ADC_MspInit+0x1fc>)
80013a8: 2200 movs r2, #0
80013aa: 60da str r2, [r3, #12]
hdma_adc3.Init.MemInc = DMA_MINC_ENABLE;
80013ac: 4b4d ldr r3, [pc, #308] @ (80014e4 <HAL_ADC_MspInit+0x1fc>)
80013ae: 2280 movs r2, #128 @ 0x80
80013b0: 611a str r2, [r3, #16]
hdma_adc3.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
80013b2: 4b4c ldr r3, [pc, #304] @ (80014e4 <HAL_ADC_MspInit+0x1fc>)
80013b4: f44f 7280 mov.w r2, #256 @ 0x100
80013b8: 615a str r2, [r3, #20]
hdma_adc3.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
80013ba: 4b4a ldr r3, [pc, #296] @ (80014e4 <HAL_ADC_MspInit+0x1fc>)
80013bc: f44f 6280 mov.w r2, #1024 @ 0x400
80013c0: 619a str r2, [r3, #24]
hdma_adc3.Init.Mode = DMA_CIRCULAR;
80013c2: 4b48 ldr r3, [pc, #288] @ (80014e4 <HAL_ADC_MspInit+0x1fc>)
80013c4: 2220 movs r2, #32
80013c6: 61da str r2, [r3, #28]
hdma_adc3.Init.Priority = DMA_PRIORITY_HIGH;
80013c8: 4b46 ldr r3, [pc, #280] @ (80014e4 <HAL_ADC_MspInit+0x1fc>)
80013ca: f44f 5200 mov.w r2, #8192 @ 0x2000
80013ce: 621a str r2, [r3, #32]
if (HAL_DMA_Init(&hdma_adc3) != HAL_OK)
80013d0: 4844 ldr r0, [pc, #272] @ (80014e4 <HAL_ADC_MspInit+0x1fc>)
80013d2: f003 f807 bl 80043e4 <HAL_DMA_Init>
80013d6: 4603 mov r3, r0
80013d8: 2b00 cmp r3, #0
80013da: d001 beq.n 80013e0 <HAL_ADC_MspInit+0xf8>
{
Error_Handler();
80013dc: f7ff ff3a bl 8001254 <Error_Handler>
}
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc3);
80013e0: 687b ldr r3, [r7, #4]
80013e2: 4a40 ldr r2, [pc, #256] @ (80014e4 <HAL_ADC_MspInit+0x1fc>)
80013e4: 655a str r2, [r3, #84] @ 0x54
80013e6: 4a3f ldr r2, [pc, #252] @ (80014e4 <HAL_ADC_MspInit+0x1fc>)
80013e8: 687b ldr r3, [r7, #4]
80013ea: 6293 str r3, [r2, #40] @ 0x28
/* USER CODE BEGIN ADC4_MspInit 1 */
/* USER CODE END ADC4_MspInit 1 */
}
}
80013ec: e06e b.n 80014cc <HAL_ADC_MspInit+0x1e4>
else if(hadc->Instance==ADC4)
80013ee: 687b ldr r3, [r7, #4]
80013f0: 681b ldr r3, [r3, #0]
80013f2: 4a3e ldr r2, [pc, #248] @ (80014ec <HAL_ADC_MspInit+0x204>)
80013f4: 4293 cmp r3, r2
80013f6: d169 bne.n 80014cc <HAL_ADC_MspInit+0x1e4>
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC345;
80013f8: f44f 3380 mov.w r3, #65536 @ 0x10000
80013fc: 61bb str r3, [r7, #24]
PeriphClkInit.Adc345ClockSelection = RCC_ADC345CLKSOURCE_SYSCLK;
80013fe: f04f 4300 mov.w r3, #2147483648 @ 0x80000000
8001402: 663b str r3, [r7, #96] @ 0x60
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001404: f107 0318 add.w r3, r7, #24
8001408: 4618 mov r0, r3
800140a: f005 fd97 bl 8006f3c <HAL_RCCEx_PeriphCLKConfig>
800140e: 4603 mov r3, r0
8001410: 2b00 cmp r3, #0
8001412: d001 beq.n 8001418 <HAL_ADC_MspInit+0x130>
Error_Handler();
8001414: f7ff ff1e bl 8001254 <Error_Handler>
HAL_RCC_ADC345_CLK_ENABLED++;
8001418: 4b2f ldr r3, [pc, #188] @ (80014d8 <HAL_ADC_MspInit+0x1f0>)
800141a: 681b ldr r3, [r3, #0]
800141c: 3301 adds r3, #1
800141e: 4a2e ldr r2, [pc, #184] @ (80014d8 <HAL_ADC_MspInit+0x1f0>)
8001420: 6013 str r3, [r2, #0]
if(HAL_RCC_ADC345_CLK_ENABLED==1){
8001422: 4b2d ldr r3, [pc, #180] @ (80014d8 <HAL_ADC_MspInit+0x1f0>)
8001424: 681b ldr r3, [r3, #0]
8001426: 2b01 cmp r3, #1
8001428: d10b bne.n 8001442 <HAL_ADC_MspInit+0x15a>
__HAL_RCC_ADC345_CLK_ENABLE();
800142a: 4b2c ldr r3, [pc, #176] @ (80014dc <HAL_ADC_MspInit+0x1f4>)
800142c: 6cdb ldr r3, [r3, #76] @ 0x4c
800142e: 4a2b ldr r2, [pc, #172] @ (80014dc <HAL_ADC_MspInit+0x1f4>)
8001430: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001434: 64d3 str r3, [r2, #76] @ 0x4c
8001436: 4b29 ldr r3, [pc, #164] @ (80014dc <HAL_ADC_MspInit+0x1f4>)
8001438: 6cdb ldr r3, [r3, #76] @ 0x4c
800143a: f403 4380 and.w r3, r3, #16384 @ 0x4000
800143e: 60fb str r3, [r7, #12]
8001440: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001442: 4b26 ldr r3, [pc, #152] @ (80014dc <HAL_ADC_MspInit+0x1f4>)
8001444: 6cdb ldr r3, [r3, #76] @ 0x4c
8001446: 4a25 ldr r2, [pc, #148] @ (80014dc <HAL_ADC_MspInit+0x1f4>)
8001448: f043 0302 orr.w r3, r3, #2
800144c: 64d3 str r3, [r2, #76] @ 0x4c
800144e: 4b23 ldr r3, [pc, #140] @ (80014dc <HAL_ADC_MspInit+0x1f4>)
8001450: 6cdb ldr r3, [r3, #76] @ 0x4c
8001452: f003 0302 and.w r3, r3, #2
8001456: 60bb str r3, [r7, #8]
8001458: 68bb ldr r3, [r7, #8]
GPIO_InitStruct.Pin = CURRENT_Pin;
800145a: f44f 4380 mov.w r3, #16384 @ 0x4000
800145e: 66fb str r3, [r7, #108] @ 0x6c
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001460: 2303 movs r3, #3
8001462: 673b str r3, [r7, #112] @ 0x70
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001464: 2300 movs r3, #0
8001466: 677b str r3, [r7, #116] @ 0x74
HAL_GPIO_Init(CURRENT_GPIO_Port, &GPIO_InitStruct);
8001468: f107 036c add.w r3, r7, #108 @ 0x6c
800146c: 4619 mov r1, r3
800146e: 481c ldr r0, [pc, #112] @ (80014e0 <HAL_ADC_MspInit+0x1f8>)
8001470: f003 fa28 bl 80048c4 <HAL_GPIO_Init>
hdma_adc4.Instance = DMA1_Channel2;
8001474: 4b1e ldr r3, [pc, #120] @ (80014f0 <HAL_ADC_MspInit+0x208>)
8001476: 4a1f ldr r2, [pc, #124] @ (80014f4 <HAL_ADC_MspInit+0x20c>)
8001478: 601a str r2, [r3, #0]
hdma_adc4.Init.Request = DMA_REQUEST_ADC4;
800147a: 4b1d ldr r3, [pc, #116] @ (80014f0 <HAL_ADC_MspInit+0x208>)
800147c: 2226 movs r2, #38 @ 0x26
800147e: 605a str r2, [r3, #4]
hdma_adc4.Init.Direction = DMA_PERIPH_TO_MEMORY;
8001480: 4b1b ldr r3, [pc, #108] @ (80014f0 <HAL_ADC_MspInit+0x208>)
8001482: 2200 movs r2, #0
8001484: 609a str r2, [r3, #8]
hdma_adc4.Init.PeriphInc = DMA_PINC_DISABLE;
8001486: 4b1a ldr r3, [pc, #104] @ (80014f0 <HAL_ADC_MspInit+0x208>)
8001488: 2200 movs r2, #0
800148a: 60da str r2, [r3, #12]
hdma_adc4.Init.MemInc = DMA_MINC_ENABLE;
800148c: 4b18 ldr r3, [pc, #96] @ (80014f0 <HAL_ADC_MspInit+0x208>)
800148e: 2280 movs r2, #128 @ 0x80
8001490: 611a str r2, [r3, #16]
hdma_adc4.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
8001492: 4b17 ldr r3, [pc, #92] @ (80014f0 <HAL_ADC_MspInit+0x208>)
8001494: f44f 7280 mov.w r2, #256 @ 0x100
8001498: 615a str r2, [r3, #20]
hdma_adc4.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
800149a: 4b15 ldr r3, [pc, #84] @ (80014f0 <HAL_ADC_MspInit+0x208>)
800149c: f44f 6280 mov.w r2, #1024 @ 0x400
80014a0: 619a str r2, [r3, #24]
hdma_adc4.Init.Mode = DMA_CIRCULAR;
80014a2: 4b13 ldr r3, [pc, #76] @ (80014f0 <HAL_ADC_MspInit+0x208>)
80014a4: 2220 movs r2, #32
80014a6: 61da str r2, [r3, #28]
hdma_adc4.Init.Priority = DMA_PRIORITY_VERY_HIGH;
80014a8: 4b11 ldr r3, [pc, #68] @ (80014f0 <HAL_ADC_MspInit+0x208>)
80014aa: f44f 5240 mov.w r2, #12288 @ 0x3000
80014ae: 621a str r2, [r3, #32]
if (HAL_DMA_Init(&hdma_adc4) != HAL_OK)
80014b0: 480f ldr r0, [pc, #60] @ (80014f0 <HAL_ADC_MspInit+0x208>)
80014b2: f002 ff97 bl 80043e4 <HAL_DMA_Init>
80014b6: 4603 mov r3, r0
80014b8: 2b00 cmp r3, #0
80014ba: d001 beq.n 80014c0 <HAL_ADC_MspInit+0x1d8>
Error_Handler();
80014bc: f7ff feca bl 8001254 <Error_Handler>
__HAL_LINKDMA(hadc,DMA_Handle,hdma_adc4);
80014c0: 687b ldr r3, [r7, #4]
80014c2: 4a0b ldr r2, [pc, #44] @ (80014f0 <HAL_ADC_MspInit+0x208>)
80014c4: 655a str r2, [r3, #84] @ 0x54
80014c6: 4a0a ldr r2, [pc, #40] @ (80014f0 <HAL_ADC_MspInit+0x208>)
80014c8: 687b ldr r3, [r7, #4]
80014ca: 6293 str r3, [r2, #40] @ 0x28
}
80014cc: bf00 nop
80014ce: 3780 adds r7, #128 @ 0x80
80014d0: 46bd mov sp, r7
80014d2: bd80 pop {r7, pc}
80014d4: 50000400 .word 0x50000400
80014d8: 200004c0 .word 0x200004c0
80014dc: 40021000 .word 0x40021000
80014e0: 48000400 .word 0x48000400
80014e4: 20000100 .word 0x20000100
80014e8: 40020008 .word 0x40020008
80014ec: 50000500 .word 0x50000500
80014f0: 20000160 .word 0x20000160
80014f4: 4002001c .word 0x4002001c
080014f8 <HAL_COMP_MspInit>:
* This function configures the hardware resources used in this example
* @param hcomp: COMP handle pointer
* @retval None
*/
void HAL_COMP_MspInit(COMP_HandleTypeDef* hcomp)
{
80014f8: b580 push {r7, lr}
80014fa: b08a sub sp, #40 @ 0x28
80014fc: af00 add r7, sp, #0
80014fe: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001500: f107 0314 add.w r3, r7, #20
8001504: 2200 movs r2, #0
8001506: 601a str r2, [r3, #0]
8001508: 605a str r2, [r3, #4]
800150a: 609a str r2, [r3, #8]
800150c: 60da str r2, [r3, #12]
800150e: 611a str r2, [r3, #16]
if(hcomp->Instance==COMP5)
8001510: 687b ldr r3, [r7, #4]
8001512: 681b ldr r3, [r3, #0]
8001514: 4a27 ldr r2, [pc, #156] @ (80015b4 <HAL_COMP_MspInit+0xbc>)
8001516: 4293 cmp r3, r2
8001518: d121 bne.n 800155e <HAL_COMP_MspInit+0x66>
{
/* USER CODE BEGIN COMP5_MspInit 0 */
/* USER CODE END COMP5_MspInit 0 */
__HAL_RCC_GPIOB_CLK_ENABLE();
800151a: 4b27 ldr r3, [pc, #156] @ (80015b8 <HAL_COMP_MspInit+0xc0>)
800151c: 6cdb ldr r3, [r3, #76] @ 0x4c
800151e: 4a26 ldr r2, [pc, #152] @ (80015b8 <HAL_COMP_MspInit+0xc0>)
8001520: f043 0302 orr.w r3, r3, #2
8001524: 64d3 str r3, [r2, #76] @ 0x4c
8001526: 4b24 ldr r3, [pc, #144] @ (80015b8 <HAL_COMP_MspInit+0xc0>)
8001528: 6cdb ldr r3, [r3, #76] @ 0x4c
800152a: f003 0302 and.w r3, r3, #2
800152e: 613b str r3, [r7, #16]
8001530: 693b ldr r3, [r7, #16]
/**COMP5 GPIO Configuration
PB13 ------> COMP5_INP
*/
GPIO_InitStruct.Pin = VOLTAGE_Pin;
8001532: f44f 5300 mov.w r3, #8192 @ 0x2000
8001536: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001538: 2303 movs r3, #3
800153a: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800153c: 2300 movs r3, #0
800153e: 61fb str r3, [r7, #28]
HAL_GPIO_Init(VOLTAGE_GPIO_Port, &GPIO_InitStruct);
8001540: f107 0314 add.w r3, r7, #20
8001544: 4619 mov r1, r3
8001546: 481d ldr r0, [pc, #116] @ (80015bc <HAL_COMP_MspInit+0xc4>)
8001548: f003 f9bc bl 80048c4 <HAL_GPIO_Init>
/* COMP5 interrupt Init */
HAL_NVIC_SetPriority(COMP4_5_6_IRQn, 0, 0);
800154c: 2200 movs r2, #0
800154e: 2100 movs r1, #0
8001550: 2041 movs r0, #65 @ 0x41
8001552: f002 fc9c bl 8003e8e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(COMP4_5_6_IRQn);
8001556: 2041 movs r0, #65 @ 0x41
8001558: f002 fcb3 bl 8003ec2 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN COMP7_MspInit 1 */
/* USER CODE END COMP7_MspInit 1 */
}
}
800155c: e025 b.n 80015aa <HAL_COMP_MspInit+0xb2>
else if(hcomp->Instance==COMP7)
800155e: 687b ldr r3, [r7, #4]
8001560: 681b ldr r3, [r3, #0]
8001562: 4a17 ldr r2, [pc, #92] @ (80015c0 <HAL_COMP_MspInit+0xc8>)
8001564: 4293 cmp r3, r2
8001566: d120 bne.n 80015aa <HAL_COMP_MspInit+0xb2>
__HAL_RCC_GPIOB_CLK_ENABLE();
8001568: 4b13 ldr r3, [pc, #76] @ (80015b8 <HAL_COMP_MspInit+0xc0>)
800156a: 6cdb ldr r3, [r3, #76] @ 0x4c
800156c: 4a12 ldr r2, [pc, #72] @ (80015b8 <HAL_COMP_MspInit+0xc0>)
800156e: f043 0302 orr.w r3, r3, #2
8001572: 64d3 str r3, [r2, #76] @ 0x4c
8001574: 4b10 ldr r3, [pc, #64] @ (80015b8 <HAL_COMP_MspInit+0xc0>)
8001576: 6cdb ldr r3, [r3, #76] @ 0x4c
8001578: f003 0302 and.w r3, r3, #2
800157c: 60fb str r3, [r7, #12]
800157e: 68fb ldr r3, [r7, #12]
GPIO_InitStruct.Pin = CURRENT_Pin;
8001580: f44f 4380 mov.w r3, #16384 @ 0x4000
8001584: 617b str r3, [r7, #20]
GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
8001586: 2303 movs r3, #3
8001588: 61bb str r3, [r7, #24]
GPIO_InitStruct.Pull = GPIO_NOPULL;
800158a: 2300 movs r3, #0
800158c: 61fb str r3, [r7, #28]
HAL_GPIO_Init(CURRENT_GPIO_Port, &GPIO_InitStruct);
800158e: f107 0314 add.w r3, r7, #20
8001592: 4619 mov r1, r3
8001594: 4809 ldr r0, [pc, #36] @ (80015bc <HAL_COMP_MspInit+0xc4>)
8001596: f003 f995 bl 80048c4 <HAL_GPIO_Init>
HAL_NVIC_SetPriority(COMP7_IRQn, 0, 0);
800159a: 2200 movs r2, #0
800159c: 2100 movs r1, #0
800159e: 2042 movs r0, #66 @ 0x42
80015a0: f002 fc75 bl 8003e8e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(COMP7_IRQn);
80015a4: 2042 movs r0, #66 @ 0x42
80015a6: f002 fc8c bl 8003ec2 <HAL_NVIC_EnableIRQ>
}
80015aa: bf00 nop
80015ac: 3728 adds r7, #40 @ 0x28
80015ae: 46bd mov sp, r7
80015b0: bd80 pop {r7, pc}
80015b2: bf00 nop
80015b4: 40010210 .word 0x40010210
80015b8: 40021000 .word 0x40021000
80015bc: 48000400 .word 0x48000400
80015c0: 40010218 .word 0x40010218
080015c4 <HAL_CORDIC_MspInit>:
* This function configures the hardware resources used in this example
* @param hcordic: CORDIC handle pointer
* @retval None
*/
void HAL_CORDIC_MspInit(CORDIC_HandleTypeDef* hcordic)
{
80015c4: b480 push {r7}
80015c6: b085 sub sp, #20
80015c8: af00 add r7, sp, #0
80015ca: 6078 str r0, [r7, #4]
if(hcordic->Instance==CORDIC)
80015cc: 687b ldr r3, [r7, #4]
80015ce: 681b ldr r3, [r3, #0]
80015d0: 4a0a ldr r2, [pc, #40] @ (80015fc <HAL_CORDIC_MspInit+0x38>)
80015d2: 4293 cmp r3, r2
80015d4: d10b bne.n 80015ee <HAL_CORDIC_MspInit+0x2a>
{
/* USER CODE BEGIN CORDIC_MspInit 0 */
/* USER CODE END CORDIC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_CORDIC_CLK_ENABLE();
80015d6: 4b0a ldr r3, [pc, #40] @ (8001600 <HAL_CORDIC_MspInit+0x3c>)
80015d8: 6c9b ldr r3, [r3, #72] @ 0x48
80015da: 4a09 ldr r2, [pc, #36] @ (8001600 <HAL_CORDIC_MspInit+0x3c>)
80015dc: f043 0308 orr.w r3, r3, #8
80015e0: 6493 str r3, [r2, #72] @ 0x48
80015e2: 4b07 ldr r3, [pc, #28] @ (8001600 <HAL_CORDIC_MspInit+0x3c>)
80015e4: 6c9b ldr r3, [r3, #72] @ 0x48
80015e6: f003 0308 and.w r3, r3, #8
80015ea: 60fb str r3, [r7, #12]
80015ec: 68fb ldr r3, [r7, #12]
/* USER CODE END CORDIC_MspInit 1 */
}
}
80015ee: bf00 nop
80015f0: 3714 adds r7, #20
80015f2: 46bd mov sp, r7
80015f4: f85d 7b04 ldr.w r7, [sp], #4
80015f8: 4770 bx lr
80015fa: bf00 nop
80015fc: 40020c00 .word 0x40020c00
8001600: 40021000 .word 0x40021000
08001604 <HAL_DAC_MspInit>:
* This function configures the hardware resources used in this example
* @param hdac: DAC handle pointer
* @retval None
*/
void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
{
8001604: b480 push {r7}
8001606: b085 sub sp, #20
8001608: af00 add r7, sp, #0
800160a: 6078 str r0, [r7, #4]
if(hdac->Instance==DAC1)
800160c: 687b ldr r3, [r7, #4]
800160e: 681b ldr r3, [r3, #0]
8001610: 4a13 ldr r2, [pc, #76] @ (8001660 <HAL_DAC_MspInit+0x5c>)
8001612: 4293 cmp r3, r2
8001614: d10c bne.n 8001630 <HAL_DAC_MspInit+0x2c>
{
/* USER CODE BEGIN DAC1_MspInit 0 */
/* USER CODE END DAC1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_DAC1_CLK_ENABLE();
8001616: 4b13 ldr r3, [pc, #76] @ (8001664 <HAL_DAC_MspInit+0x60>)
8001618: 6cdb ldr r3, [r3, #76] @ 0x4c
800161a: 4a12 ldr r2, [pc, #72] @ (8001664 <HAL_DAC_MspInit+0x60>)
800161c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8001620: 64d3 str r3, [r2, #76] @ 0x4c
8001622: 4b10 ldr r3, [pc, #64] @ (8001664 <HAL_DAC_MspInit+0x60>)
8001624: 6cdb ldr r3, [r3, #76] @ 0x4c
8001626: f403 3380 and.w r3, r3, #65536 @ 0x10000
800162a: 60fb str r3, [r7, #12]
800162c: 68fb ldr r3, [r7, #12]
/* USER CODE BEGIN DAC4_MspInit 1 */
/* USER CODE END DAC4_MspInit 1 */
}
}
800162e: e010 b.n 8001652 <HAL_DAC_MspInit+0x4e>
else if(hdac->Instance==DAC4)
8001630: 687b ldr r3, [r7, #4]
8001632: 681b ldr r3, [r3, #0]
8001634: 4a0c ldr r2, [pc, #48] @ (8001668 <HAL_DAC_MspInit+0x64>)
8001636: 4293 cmp r3, r2
8001638: d10b bne.n 8001652 <HAL_DAC_MspInit+0x4e>
__HAL_RCC_DAC4_CLK_ENABLE();
800163a: 4b0a ldr r3, [pc, #40] @ (8001664 <HAL_DAC_MspInit+0x60>)
800163c: 6cdb ldr r3, [r3, #76] @ 0x4c
800163e: 4a09 ldr r2, [pc, #36] @ (8001664 <HAL_DAC_MspInit+0x60>)
8001640: f443 2300 orr.w r3, r3, #524288 @ 0x80000
8001644: 64d3 str r3, [r2, #76] @ 0x4c
8001646: 4b07 ldr r3, [pc, #28] @ (8001664 <HAL_DAC_MspInit+0x60>)
8001648: 6cdb ldr r3, [r3, #76] @ 0x4c
800164a: f403 2300 and.w r3, r3, #524288 @ 0x80000
800164e: 60bb str r3, [r7, #8]
8001650: 68bb ldr r3, [r7, #8]
}
8001652: bf00 nop
8001654: 3714 adds r7, #20
8001656: 46bd mov sp, r7
8001658: f85d 7b04 ldr.w r7, [sp], #4
800165c: 4770 bx lr
800165e: bf00 nop
8001660: 50000800 .word 0x50000800
8001664: 40021000 .word 0x40021000
8001668: 50001400 .word 0x50001400
0800166c <HAL_FMAC_MspInit>:
* This function configures the hardware resources used in this example
* @param hfmac: FMAC handle pointer
* @retval None
*/
void HAL_FMAC_MspInit(FMAC_HandleTypeDef* hfmac)
{
800166c: b480 push {r7}
800166e: b085 sub sp, #20
8001670: af00 add r7, sp, #0
8001672: 6078 str r0, [r7, #4]
if(hfmac->Instance==FMAC)
8001674: 687b ldr r3, [r7, #4]
8001676: 681b ldr r3, [r3, #0]
8001678: 4a0a ldr r2, [pc, #40] @ (80016a4 <HAL_FMAC_MspInit+0x38>)
800167a: 4293 cmp r3, r2
800167c: d10b bne.n 8001696 <HAL_FMAC_MspInit+0x2a>
{
/* USER CODE BEGIN FMAC_MspInit 0 */
/* USER CODE END FMAC_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_FMAC_CLK_ENABLE();
800167e: 4b0a ldr r3, [pc, #40] @ (80016a8 <HAL_FMAC_MspInit+0x3c>)
8001680: 6c9b ldr r3, [r3, #72] @ 0x48
8001682: 4a09 ldr r2, [pc, #36] @ (80016a8 <HAL_FMAC_MspInit+0x3c>)
8001684: f043 0310 orr.w r3, r3, #16
8001688: 6493 str r3, [r2, #72] @ 0x48
800168a: 4b07 ldr r3, [pc, #28] @ (80016a8 <HAL_FMAC_MspInit+0x3c>)
800168c: 6c9b ldr r3, [r3, #72] @ 0x48
800168e: f003 0310 and.w r3, r3, #16
8001692: 60fb str r3, [r7, #12]
8001694: 68fb ldr r3, [r7, #12]
/* USER CODE END FMAC_MspInit 1 */
}
}
8001696: bf00 nop
8001698: 3714 adds r7, #20
800169a: 46bd mov sp, r7
800169c: f85d 7b04 ldr.w r7, [sp], #4
80016a0: 4770 bx lr
80016a2: bf00 nop
80016a4: 40021400 .word 0x40021400
80016a8: 40021000 .word 0x40021000
080016ac <HAL_HRTIM_MspInit>:
* This function configures the hardware resources used in this example
* @param hhrtim: HRTIM handle pointer
* @retval None
*/
void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef* hhrtim)
{
80016ac: b480 push {r7}
80016ae: b085 sub sp, #20
80016b0: af00 add r7, sp, #0
80016b2: 6078 str r0, [r7, #4]
if(hhrtim->Instance==HRTIM1)
80016b4: 687b ldr r3, [r7, #4]
80016b6: 681b ldr r3, [r3, #0]
80016b8: 4a0a ldr r2, [pc, #40] @ (80016e4 <HAL_HRTIM_MspInit+0x38>)
80016ba: 4293 cmp r3, r2
80016bc: d10b bne.n 80016d6 <HAL_HRTIM_MspInit+0x2a>
{
/* USER CODE BEGIN HRTIM1_MspInit 0 */
/* USER CODE END HRTIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_HRTIM1_CLK_ENABLE();
80016be: 4b0a ldr r3, [pc, #40] @ (80016e8 <HAL_HRTIM_MspInit+0x3c>)
80016c0: 6e1b ldr r3, [r3, #96] @ 0x60
80016c2: 4a09 ldr r2, [pc, #36] @ (80016e8 <HAL_HRTIM_MspInit+0x3c>)
80016c4: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
80016c8: 6613 str r3, [r2, #96] @ 0x60
80016ca: 4b07 ldr r3, [pc, #28] @ (80016e8 <HAL_HRTIM_MspInit+0x3c>)
80016cc: 6e1b ldr r3, [r3, #96] @ 0x60
80016ce: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
80016d2: 60fb str r3, [r7, #12]
80016d4: 68fb ldr r3, [r7, #12]
/* USER CODE END HRTIM1_MspInit 1 */
}
}
80016d6: bf00 nop
80016d8: 3714 adds r7, #20
80016da: 46bd mov sp, r7
80016dc: f85d 7b04 ldr.w r7, [sp], #4
80016e0: 4770 bx lr
80016e2: bf00 nop
80016e4: 40016800 .word 0x40016800
80016e8: 40021000 .word 0x40021000
080016ec <HAL_HRTIM_MspPostInit>:
void HAL_HRTIM_MspPostInit(HRTIM_HandleTypeDef* hhrtim)
{
80016ec: b580 push {r7, lr}
80016ee: b088 sub sp, #32
80016f0: af00 add r7, sp, #0
80016f2: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
80016f4: f107 030c add.w r3, r7, #12
80016f8: 2200 movs r2, #0
80016fa: 601a str r2, [r3, #0]
80016fc: 605a str r2, [r3, #4]
80016fe: 609a str r2, [r3, #8]
8001700: 60da str r2, [r3, #12]
8001702: 611a str r2, [r3, #16]
if(hhrtim->Instance==HRTIM1)
8001704: 687b ldr r3, [r7, #4]
8001706: 681b ldr r3, [r3, #0]
8001708: 4a12 ldr r2, [pc, #72] @ (8001754 <HAL_HRTIM_MspPostInit+0x68>)
800170a: 4293 cmp r3, r2
800170c: d11d bne.n 800174a <HAL_HRTIM_MspPostInit+0x5e>
{
/* USER CODE BEGIN HRTIM1_MspPostInit 0 */
/* USER CODE END HRTIM1_MspPostInit 0 */
__HAL_RCC_GPIOA_CLK_ENABLE();
800170e: 4b12 ldr r3, [pc, #72] @ (8001758 <HAL_HRTIM_MspPostInit+0x6c>)
8001710: 6cdb ldr r3, [r3, #76] @ 0x4c
8001712: 4a11 ldr r2, [pc, #68] @ (8001758 <HAL_HRTIM_MspPostInit+0x6c>)
8001714: f043 0301 orr.w r3, r3, #1
8001718: 64d3 str r3, [r2, #76] @ 0x4c
800171a: 4b0f ldr r3, [pc, #60] @ (8001758 <HAL_HRTIM_MspPostInit+0x6c>)
800171c: 6cdb ldr r3, [r3, #76] @ 0x4c
800171e: f003 0301 and.w r3, r3, #1
8001722: 60bb str r3, [r7, #8]
8001724: 68bb ldr r3, [r7, #8]
PA8 ------> HRTIM1_CHA1
PA9 ------> HRTIM1_CHA2
PA10 ------> HRTIM1_CHB1
PA11 ------> HRTIM1_CHB2
*/
GPIO_InitStruct.Pin = GPIO_PIN_8|GPIO_PIN_9|GPIO_PIN_10|GPIO_PIN_11;
8001726: f44f 6370 mov.w r3, #3840 @ 0xf00
800172a: 60fb str r3, [r7, #12]
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
800172c: 2302 movs r3, #2
800172e: 613b str r3, [r7, #16]
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001730: 2300 movs r3, #0
8001732: 617b str r3, [r7, #20]
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
8001734: 2303 movs r3, #3
8001736: 61bb str r3, [r7, #24]
GPIO_InitStruct.Alternate = GPIO_AF13_HRTIM1;
8001738: 230d movs r3, #13
800173a: 61fb str r3, [r7, #28]
HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
800173c: f107 030c add.w r3, r7, #12
8001740: 4619 mov r1, r3
8001742: f04f 4090 mov.w r0, #1207959552 @ 0x48000000
8001746: f003 f8bd bl 80048c4 <HAL_GPIO_Init>
/* USER CODE BEGIN HRTIM1_MspPostInit 1 */
/* USER CODE END HRTIM1_MspPostInit 1 */
}
}
800174a: bf00 nop
800174c: 3720 adds r7, #32
800174e: 46bd mov sp, r7
8001750: bd80 pop {r7, pc}
8001752: bf00 nop
8001754: 40016800 .word 0x40016800
8001758: 40021000 .word 0x40021000
0800175c <HAL_TIM_Base_MspInit>:
* This function configures the hardware resources used in this example
* @param htim_base: TIM_Base handle pointer
* @retval None
*/
void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
{
800175c: b580 push {r7, lr}
800175e: b084 sub sp, #16
8001760: af00 add r7, sp, #0
8001762: 6078 str r0, [r7, #4]
if(htim_base->Instance==TIM1)
8001764: 687b ldr r3, [r7, #4]
8001766: 681b ldr r3, [r3, #0]
8001768: 4a26 ldr r2, [pc, #152] @ (8001804 <HAL_TIM_Base_MspInit+0xa8>)
800176a: 4293 cmp r3, r2
800176c: d12c bne.n 80017c8 <HAL_TIM_Base_MspInit+0x6c>
{
/* USER CODE BEGIN TIM1_MspInit 0 */
/* USER CODE END TIM1_MspInit 0 */
/* Peripheral clock enable */
__HAL_RCC_TIM1_CLK_ENABLE();
800176e: 4b26 ldr r3, [pc, #152] @ (8001808 <HAL_TIM_Base_MspInit+0xac>)
8001770: 6e1b ldr r3, [r3, #96] @ 0x60
8001772: 4a25 ldr r2, [pc, #148] @ (8001808 <HAL_TIM_Base_MspInit+0xac>)
8001774: f443 6300 orr.w r3, r3, #2048 @ 0x800
8001778: 6613 str r3, [r2, #96] @ 0x60
800177a: 4b23 ldr r3, [pc, #140] @ (8001808 <HAL_TIM_Base_MspInit+0xac>)
800177c: 6e1b ldr r3, [r3, #96] @ 0x60
800177e: f403 6300 and.w r3, r3, #2048 @ 0x800
8001782: 60fb str r3, [r7, #12]
8001784: 68fb ldr r3, [r7, #12]
/* TIM1 interrupt Init */
HAL_NVIC_SetPriority(TIM1_BRK_TIM15_IRQn, 0, 0);
8001786: 2200 movs r2, #0
8001788: 2100 movs r1, #0
800178a: 2018 movs r0, #24
800178c: f002 fb7f bl 8003e8e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM1_BRK_TIM15_IRQn);
8001790: 2018 movs r0, #24
8001792: f002 fb96 bl 8003ec2 <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(TIM1_UP_TIM16_IRQn, 0, 0);
8001796: 2200 movs r2, #0
8001798: 2100 movs r1, #0
800179a: 2019 movs r0, #25
800179c: f002 fb77 bl 8003e8e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM1_UP_TIM16_IRQn);
80017a0: 2019 movs r0, #25
80017a2: f002 fb8e bl 8003ec2 <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(TIM1_TRG_COM_TIM17_IRQn, 0, 0);
80017a6: 2200 movs r2, #0
80017a8: 2100 movs r1, #0
80017aa: 201a movs r0, #26
80017ac: f002 fb6f bl 8003e8e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM1_TRG_COM_TIM17_IRQn);
80017b0: 201a movs r0, #26
80017b2: f002 fb86 bl 8003ec2 <HAL_NVIC_EnableIRQ>
HAL_NVIC_SetPriority(TIM1_CC_IRQn, 0, 0);
80017b6: 2200 movs r2, #0
80017b8: 2100 movs r1, #0
80017ba: 201b movs r0, #27
80017bc: f002 fb67 bl 8003e8e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM1_CC_IRQn);
80017c0: 201b movs r0, #27
80017c2: f002 fb7e bl 8003ec2 <HAL_NVIC_EnableIRQ>
/* USER CODE BEGIN TIM3_MspInit 1 */
/* USER CODE END TIM3_MspInit 1 */
}
}
80017c6: e018 b.n 80017fa <HAL_TIM_Base_MspInit+0x9e>
else if(htim_base->Instance==TIM3)
80017c8: 687b ldr r3, [r7, #4]
80017ca: 681b ldr r3, [r3, #0]
80017cc: 4a0f ldr r2, [pc, #60] @ (800180c <HAL_TIM_Base_MspInit+0xb0>)
80017ce: 4293 cmp r3, r2
80017d0: d113 bne.n 80017fa <HAL_TIM_Base_MspInit+0x9e>
__HAL_RCC_TIM3_CLK_ENABLE();
80017d2: 4b0d ldr r3, [pc, #52] @ (8001808 <HAL_TIM_Base_MspInit+0xac>)
80017d4: 6d9b ldr r3, [r3, #88] @ 0x58
80017d6: 4a0c ldr r2, [pc, #48] @ (8001808 <HAL_TIM_Base_MspInit+0xac>)
80017d8: f043 0302 orr.w r3, r3, #2
80017dc: 6593 str r3, [r2, #88] @ 0x58
80017de: 4b0a ldr r3, [pc, #40] @ (8001808 <HAL_TIM_Base_MspInit+0xac>)
80017e0: 6d9b ldr r3, [r3, #88] @ 0x58
80017e2: f003 0302 and.w r3, r3, #2
80017e6: 60bb str r3, [r7, #8]
80017e8: 68bb ldr r3, [r7, #8]
HAL_NVIC_SetPriority(TIM3_IRQn, 0, 0);
80017ea: 2200 movs r2, #0
80017ec: 2100 movs r1, #0
80017ee: 201d movs r0, #29
80017f0: f002 fb4d bl 8003e8e <HAL_NVIC_SetPriority>
HAL_NVIC_EnableIRQ(TIM3_IRQn);
80017f4: 201d movs r0, #29
80017f6: f002 fb64 bl 8003ec2 <HAL_NVIC_EnableIRQ>
}
80017fa: bf00 nop
80017fc: 3710 adds r7, #16
80017fe: 46bd mov sp, r7
8001800: bd80 pop {r7, pc}
8001802: bf00 nop
8001804: 40012c00 .word 0x40012c00
8001808: 40021000 .word 0x40021000
800180c: 40000400 .word 0x40000400
08001810 <HAL_UART_MspInit>:
* This function configures the hardware resources used in this example
* @param huart: UART handle pointer
* @retval None
*/
void HAL_UART_MspInit(UART_HandleTypeDef* huart)
{
8001810: b580 push {r7, lr}
8001812: b09e sub sp, #120 @ 0x78
8001814: af00 add r7, sp, #0
8001816: 6078 str r0, [r7, #4]
GPIO_InitTypeDef GPIO_InitStruct = {0};
8001818: f107 0364 add.w r3, r7, #100 @ 0x64
800181c: 2200 movs r2, #0
800181e: 601a str r2, [r3, #0]
8001820: 605a str r2, [r3, #4]
8001822: 609a str r2, [r3, #8]
8001824: 60da str r2, [r3, #12]
8001826: 611a str r2, [r3, #16]
RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
8001828: f107 0310 add.w r3, r7, #16
800182c: 2254 movs r2, #84 @ 0x54
800182e: 2100 movs r1, #0
8001830: 4618 mov r0, r3
8001832: f007 ff8f bl 8009754 <memset>
if(huart->Instance==USART1)
8001836: 687b ldr r3, [r7, #4]
8001838: 681b ldr r3, [r3, #0]
800183a: 4a1e ldr r2, [pc, #120] @ (80018b4 <HAL_UART_MspInit+0xa4>)
800183c: 4293 cmp r3, r2
800183e: d135 bne.n 80018ac <HAL_UART_MspInit+0x9c>
/* USER CODE END USART1_MspInit 0 */
/** Initializes the peripherals clocks
*/
PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
8001840: 2301 movs r3, #1
8001842: 613b str r3, [r7, #16]
PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2;
8001844: 2300 movs r3, #0
8001846: 617b str r3, [r7, #20]
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
8001848: f107 0310 add.w r3, r7, #16
800184c: 4618 mov r0, r3
800184e: f005 fb75 bl 8006f3c <HAL_RCCEx_PeriphCLKConfig>
8001852: 4603 mov r3, r0
8001854: 2b00 cmp r3, #0
8001856: d001 beq.n 800185c <HAL_UART_MspInit+0x4c>
{
Error_Handler();
8001858: f7ff fcfc bl 8001254 <Error_Handler>
}
/* Peripheral clock enable */
__HAL_RCC_USART1_CLK_ENABLE();
800185c: 4b16 ldr r3, [pc, #88] @ (80018b8 <HAL_UART_MspInit+0xa8>)
800185e: 6e1b ldr r3, [r3, #96] @ 0x60
8001860: 4a15 ldr r2, [pc, #84] @ (80018b8 <HAL_UART_MspInit+0xa8>)
8001862: f443 4380 orr.w r3, r3, #16384 @ 0x4000
8001866: 6613 str r3, [r2, #96] @ 0x60
8001868: 4b13 ldr r3, [pc, #76] @ (80018b8 <HAL_UART_MspInit+0xa8>)
800186a: 6e1b ldr r3, [r3, #96] @ 0x60
800186c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8001870: 60fb str r3, [r7, #12]
8001872: 68fb ldr r3, [r7, #12]
__HAL_RCC_GPIOB_CLK_ENABLE();
8001874: 4b10 ldr r3, [pc, #64] @ (80018b8 <HAL_UART_MspInit+0xa8>)
8001876: 6cdb ldr r3, [r3, #76] @ 0x4c
8001878: 4a0f ldr r2, [pc, #60] @ (80018b8 <HAL_UART_MspInit+0xa8>)
800187a: f043 0302 orr.w r3, r3, #2
800187e: 64d3 str r3, [r2, #76] @ 0x4c
8001880: 4b0d ldr r3, [pc, #52] @ (80018b8 <HAL_UART_MspInit+0xa8>)
8001882: 6cdb ldr r3, [r3, #76] @ 0x4c
8001884: f003 0302 and.w r3, r3, #2
8001888: 60bb str r3, [r7, #8]
800188a: 68bb ldr r3, [r7, #8]
/**USART1 GPIO Configuration
PB6 ------> USART1_TX
PB7 ------> USART1_RX
*/
GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
800188c: 23c0 movs r3, #192 @ 0xc0
800188e: 667b str r3, [r7, #100] @ 0x64
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
8001890: 2302 movs r3, #2
8001892: 66bb str r3, [r7, #104] @ 0x68
GPIO_InitStruct.Pull = GPIO_NOPULL;
8001894: 2300 movs r3, #0
8001896: 66fb str r3, [r7, #108] @ 0x6c
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
8001898: 2300 movs r3, #0
800189a: 673b str r3, [r7, #112] @ 0x70
GPIO_InitStruct.Alternate = GPIO_AF7_USART1;
800189c: 2307 movs r3, #7
800189e: 677b str r3, [r7, #116] @ 0x74
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
80018a0: f107 0364 add.w r3, r7, #100 @ 0x64
80018a4: 4619 mov r1, r3
80018a6: 4805 ldr r0, [pc, #20] @ (80018bc <HAL_UART_MspInit+0xac>)
80018a8: f003 f80c bl 80048c4 <HAL_GPIO_Init>
/* USER CODE END USART1_MspInit 1 */
}
}
80018ac: bf00 nop
80018ae: 3778 adds r7, #120 @ 0x78
80018b0: 46bd mov sp, r7
80018b2: bd80 pop {r7, pc}
80018b4: 40013800 .word 0x40013800
80018b8: 40021000 .word 0x40021000
80018bc: 48000400 .word 0x48000400
080018c0 <NMI_Handler>:
/******************************************************************************/
/**
* @brief This function handles Non maskable interrupt.
*/
void NMI_Handler(void)
{
80018c0: b480 push {r7}
80018c2: af00 add r7, sp, #0
/* USER CODE BEGIN NonMaskableInt_IRQn 0 */
/* USER CODE END NonMaskableInt_IRQn 0 */
/* USER CODE BEGIN NonMaskableInt_IRQn 1 */
while (1)
80018c4: bf00 nop
80018c6: e7fd b.n 80018c4 <NMI_Handler+0x4>
080018c8 <HardFault_Handler>:
/**
* @brief This function handles Hard fault interrupt.
*/
void HardFault_Handler(void)
{
80018c8: b480 push {r7}
80018ca: af00 add r7, sp, #0
/* USER CODE BEGIN HardFault_IRQn 0 */
/* USER CODE END HardFault_IRQn 0 */
while (1)
80018cc: bf00 nop
80018ce: e7fd b.n 80018cc <HardFault_Handler+0x4>
080018d0 <MemManage_Handler>:
/**
* @brief This function handles Memory management fault.
*/
void MemManage_Handler(void)
{
80018d0: b480 push {r7}
80018d2: af00 add r7, sp, #0
/* USER CODE BEGIN MemoryManagement_IRQn 0 */
/* USER CODE END MemoryManagement_IRQn 0 */
while (1)
80018d4: bf00 nop
80018d6: e7fd b.n 80018d4 <MemManage_Handler+0x4>
080018d8 <BusFault_Handler>:
/**
* @brief This function handles Prefetch fault, memory access fault.
*/
void BusFault_Handler(void)
{
80018d8: b480 push {r7}
80018da: af00 add r7, sp, #0
/* USER CODE BEGIN BusFault_IRQn 0 */
/* USER CODE END BusFault_IRQn 0 */
while (1)
80018dc: bf00 nop
80018de: e7fd b.n 80018dc <BusFault_Handler+0x4>
080018e0 <UsageFault_Handler>:
/**
* @brief This function handles Undefined instruction or illegal state.
*/
void UsageFault_Handler(void)
{
80018e0: b480 push {r7}
80018e2: af00 add r7, sp, #0
/* USER CODE BEGIN UsageFault_IRQn 0 */
/* USER CODE END UsageFault_IRQn 0 */
while (1)
80018e4: bf00 nop
80018e6: e7fd b.n 80018e4 <UsageFault_Handler+0x4>
080018e8 <SVC_Handler>:
/**
* @brief This function handles System service call via SWI instruction.
*/
void SVC_Handler(void)
{
80018e8: b480 push {r7}
80018ea: af00 add r7, sp, #0
/* USER CODE END SVCall_IRQn 0 */
/* USER CODE BEGIN SVCall_IRQn 1 */
/* USER CODE END SVCall_IRQn 1 */
}
80018ec: bf00 nop
80018ee: 46bd mov sp, r7
80018f0: f85d 7b04 ldr.w r7, [sp], #4
80018f4: 4770 bx lr
080018f6 <DebugMon_Handler>:
/**
* @brief This function handles Debug monitor.
*/
void DebugMon_Handler(void)
{
80018f6: b480 push {r7}
80018f8: af00 add r7, sp, #0
/* USER CODE END DebugMonitor_IRQn 0 */
/* USER CODE BEGIN DebugMonitor_IRQn 1 */
/* USER CODE END DebugMonitor_IRQn 1 */
}
80018fa: bf00 nop
80018fc: 46bd mov sp, r7
80018fe: f85d 7b04 ldr.w r7, [sp], #4
8001902: 4770 bx lr
08001904 <PendSV_Handler>:
/**
* @brief This function handles Pendable request for system service.
*/
void PendSV_Handler(void)
{
8001904: b480 push {r7}
8001906: af00 add r7, sp, #0
/* USER CODE END PendSV_IRQn 0 */
/* USER CODE BEGIN PendSV_IRQn 1 */
/* USER CODE END PendSV_IRQn 1 */
}
8001908: bf00 nop
800190a: 46bd mov sp, r7
800190c: f85d 7b04 ldr.w r7, [sp], #4
8001910: 4770 bx lr
08001912 <SysTick_Handler>:
/**
* @brief This function handles System tick timer.
*/
void SysTick_Handler(void)
{
8001912: b580 push {r7, lr}
8001914: af00 add r7, sp, #0
/* USER CODE BEGIN SysTick_IRQn 0 */
/* USER CODE END SysTick_IRQn 0 */
HAL_IncTick();
8001916: f000 f8d7 bl 8001ac8 <HAL_IncTick>
/* USER CODE BEGIN SysTick_IRQn 1 */
/* USER CODE END SysTick_IRQn 1 */
}
800191a: bf00 nop
800191c: bd80 pop {r7, pc}
...
08001920 <TIM1_BRK_TIM15_IRQHandler>:
/**
* @brief This function handles TIM1 break interrupt and TIM15 global interrupt.
*/
void TIM1_BRK_TIM15_IRQHandler(void)
{
8001920: b580 push {r7, lr}
8001922: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_BRK_TIM15_IRQn 0 */
/* USER CODE END TIM1_BRK_TIM15_IRQn 0 */
HAL_TIM_IRQHandler(&htim1);
8001924: 4802 ldr r0, [pc, #8] @ (8001930 <TIM1_BRK_TIM15_IRQHandler+0x10>)
8001926: f005 ff9f bl 8007868 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM1_BRK_TIM15_IRQn 1 */
/* USER CODE END TIM1_BRK_TIM15_IRQn 1 */
}
800192a: bf00 nop
800192c: bd80 pop {r7, pc}
800192e: bf00 nop
8001930: 2000038c .word 0x2000038c
08001934 <TIM1_UP_TIM16_IRQHandler>:
/**
* @brief This function handles TIM1 update interrupt and TIM16 global interrupt.
*/
void TIM1_UP_TIM16_IRQHandler(void)
{
8001934: b580 push {r7, lr}
8001936: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_UP_TIM16_IRQn 0 */
/* USER CODE END TIM1_UP_TIM16_IRQn 0 */
HAL_TIM_IRQHandler(&htim1);
8001938: 4802 ldr r0, [pc, #8] @ (8001944 <TIM1_UP_TIM16_IRQHandler+0x10>)
800193a: f005 ff95 bl 8007868 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM1_UP_TIM16_IRQn 1 */
/* USER CODE END TIM1_UP_TIM16_IRQn 1 */
}
800193e: bf00 nop
8001940: bd80 pop {r7, pc}
8001942: bf00 nop
8001944: 2000038c .word 0x2000038c
08001948 <TIM1_TRG_COM_TIM17_IRQHandler>:
/**
* @brief This function handles TIM1 trigger and commutation interrupts and TIM17 global interrupt.
*/
void TIM1_TRG_COM_TIM17_IRQHandler(void)
{
8001948: b580 push {r7, lr}
800194a: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 0 */
/* USER CODE END TIM1_TRG_COM_TIM17_IRQn 0 */
HAL_TIM_IRQHandler(&htim1);
800194c: 4802 ldr r0, [pc, #8] @ (8001958 <TIM1_TRG_COM_TIM17_IRQHandler+0x10>)
800194e: f005 ff8b bl 8007868 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM1_TRG_COM_TIM17_IRQn 1 */
/* USER CODE END TIM1_TRG_COM_TIM17_IRQn 1 */
}
8001952: bf00 nop
8001954: bd80 pop {r7, pc}
8001956: bf00 nop
8001958: 2000038c .word 0x2000038c
0800195c <TIM1_CC_IRQHandler>:
/**
* @brief This function handles TIM1 capture compare interrupt.
*/
void TIM1_CC_IRQHandler(void)
{
800195c: b580 push {r7, lr}
800195e: af00 add r7, sp, #0
/* USER CODE BEGIN TIM1_CC_IRQn 0 */
/* USER CODE END TIM1_CC_IRQn 0 */
HAL_TIM_IRQHandler(&htim1);
8001960: 4802 ldr r0, [pc, #8] @ (800196c <TIM1_CC_IRQHandler+0x10>)
8001962: f005 ff81 bl 8007868 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM1_CC_IRQn 1 */
/* USER CODE END TIM1_CC_IRQn 1 */
}
8001966: bf00 nop
8001968: bd80 pop {r7, pc}
800196a: bf00 nop
800196c: 2000038c .word 0x2000038c
08001970 <TIM3_IRQHandler>:
/**
* @brief This function handles TIM3 global interrupt.
*/
void TIM3_IRQHandler(void)
{
8001970: b580 push {r7, lr}
8001972: af00 add r7, sp, #0
/* USER CODE BEGIN TIM3_IRQn 0 */
/* USER CODE END TIM3_IRQn 0 */
HAL_TIM_IRQHandler(&htim3);
8001974: 4802 ldr r0, [pc, #8] @ (8001980 <TIM3_IRQHandler+0x10>)
8001976: f005 ff77 bl 8007868 <HAL_TIM_IRQHandler>
/* USER CODE BEGIN TIM3_IRQn 1 */
/* USER CODE END TIM3_IRQn 1 */
}
800197a: bf00 nop
800197c: bd80 pop {r7, pc}
800197e: bf00 nop
8001980: 200003d8 .word 0x200003d8
08001984 <COMP4_5_6_IRQHandler>:
/**
* @brief This function handles COMP4, COMP5 and COMP6 interrupts through EXTI lines 30, 31 and 32.
*/
void COMP4_5_6_IRQHandler(void)
{
8001984: b580 push {r7, lr}
8001986: af00 add r7, sp, #0
/* USER CODE BEGIN COMP4_5_6_IRQn 0 */
/* USER CODE END COMP4_5_6_IRQn 0 */
HAL_COMP_IRQHandler(&hcomp5);
8001988: 4802 ldr r0, [pc, #8] @ (8001994 <COMP4_5_6_IRQHandler+0x10>)
800198a: f002 f8ff bl 8003b8c <HAL_COMP_IRQHandler>
/* USER CODE BEGIN COMP4_5_6_IRQn 1 */
/* USER CODE END COMP4_5_6_IRQn 1 */
}
800198e: bf00 nop
8001990: bd80 pop {r7, pc}
8001992: bf00 nop
8001994: 200001c0 .word 0x200001c0
08001998 <COMP7_IRQHandler>:
/**
* @brief This function handles COMP7 interrupt through EXTI line 33.
*/
void COMP7_IRQHandler(void)
{
8001998: b580 push {r7, lr}
800199a: af00 add r7, sp, #0
/* USER CODE BEGIN COMP7_IRQn 0 */
/* USER CODE END COMP7_IRQn 0 */
HAL_COMP_IRQHandler(&hcomp7);
800199c: 4802 ldr r0, [pc, #8] @ (80019a8 <COMP7_IRQHandler+0x10>)
800199e: f002 f8f5 bl 8003b8c <HAL_COMP_IRQHandler>
/* USER CODE BEGIN COMP7_IRQn 1 */
/* USER CODE END COMP7_IRQn 1 */
}
80019a2: bf00 nop
80019a4: bd80 pop {r7, pc}
80019a6: bf00 nop
80019a8: 200001e4 .word 0x200001e4
080019ac <SystemInit>:
* @param None
* @retval None
*/
void SystemInit(void)
{
80019ac: b480 push {r7}
80019ae: af00 add r7, sp, #0
/* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
80019b0: 4b06 ldr r3, [pc, #24] @ (80019cc <SystemInit+0x20>)
80019b2: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80019b6: 4a05 ldr r2, [pc, #20] @ (80019cc <SystemInit+0x20>)
80019b8: f443 0370 orr.w r3, r3, #15728640 @ 0xf00000
80019bc: f8c2 3088 str.w r3, [r2, #136] @ 0x88
/* Configure the Vector Table location add offset address ------------------*/
#if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
#endif /* USER_VECT_TAB_ADDRESS */
}
80019c0: bf00 nop
80019c2: 46bd mov sp, r7
80019c4: f85d 7b04 ldr.w r7, [sp], #4
80019c8: 4770 bx lr
80019ca: bf00 nop
80019cc: e000ed00 .word 0xe000ed00
080019d0 <Reset_Handler>:
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
80019d0: 480d ldr r0, [pc, #52] @ (8001a08 <LoopForever+0x2>)
mov sp, r0 /* set stack pointer */
80019d2: 4685 mov sp, r0
/* Call the clock system initialization function.*/
bl SystemInit
80019d4: f7ff ffea bl 80019ac <SystemInit>
/* Copy the data segment initializers from flash to SRAM */
ldr r0, =_sdata
80019d8: 480c ldr r0, [pc, #48] @ (8001a0c <LoopForever+0x6>)
ldr r1, =_edata
80019da: 490d ldr r1, [pc, #52] @ (8001a10 <LoopForever+0xa>)
ldr r2, =_sidata
80019dc: 4a0d ldr r2, [pc, #52] @ (8001a14 <LoopForever+0xe>)
movs r3, #0
80019de: 2300 movs r3, #0
b LoopCopyDataInit
80019e0: e002 b.n 80019e8 <LoopCopyDataInit>
080019e2 <CopyDataInit>:
CopyDataInit:
ldr r4, [r2, r3]
80019e2: 58d4 ldr r4, [r2, r3]
str r4, [r0, r3]
80019e4: 50c4 str r4, [r0, r3]
adds r3, r3, #4
80019e6: 3304 adds r3, #4
080019e8 <LoopCopyDataInit>:
LoopCopyDataInit:
adds r4, r0, r3
80019e8: 18c4 adds r4, r0, r3
cmp r4, r1
80019ea: 428c cmp r4, r1
bcc CopyDataInit
80019ec: d3f9 bcc.n 80019e2 <CopyDataInit>
/* Zero fill the bss segment. */
ldr r2, =_sbss
80019ee: 4a0a ldr r2, [pc, #40] @ (8001a18 <LoopForever+0x12>)
ldr r4, =_ebss
80019f0: 4c0a ldr r4, [pc, #40] @ (8001a1c <LoopForever+0x16>)
movs r3, #0
80019f2: 2300 movs r3, #0
b LoopFillZerobss
80019f4: e001 b.n 80019fa <LoopFillZerobss>
080019f6 <FillZerobss>:
FillZerobss:
str r3, [r2]
80019f6: 6013 str r3, [r2, #0]
adds r2, r2, #4
80019f8: 3204 adds r2, #4
080019fa <LoopFillZerobss>:
LoopFillZerobss:
cmp r2, r4
80019fa: 42a2 cmp r2, r4
bcc FillZerobss
80019fc: d3fb bcc.n 80019f6 <FillZerobss>
/* Call static constructors */
bl __libc_init_array
80019fe: f007 feb1 bl 8009764 <__libc_init_array>
/* Call the application's entry point.*/
bl main
8001a02: f7fe fd9f bl 8000544 <main>
08001a06 <LoopForever>:
LoopForever:
b LoopForever
8001a06: e7fe b.n 8001a06 <LoopForever>
ldr r0, =_estack
8001a08: 20020000 .word 0x20020000
ldr r0, =_sdata
8001a0c: 20000000 .word 0x20000000
ldr r1, =_edata
8001a10: 2000000c .word 0x2000000c
ldr r2, =_sidata
8001a14: 08009850 .word 0x08009850
ldr r2, =_sbss
8001a18: 2000000c .word 0x2000000c
ldr r4, =_ebss
8001a1c: 200004c8 .word 0x200004c8
08001a20 <ADC1_2_IRQHandler>:
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
8001a20: e7fe b.n 8001a20 <ADC1_2_IRQHandler>
08001a22 <HAL_Init>:
* each 1ms in the SysTick_Handler() interrupt handler.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_Init(void)
{
8001a22: b580 push {r7, lr}
8001a24: b082 sub sp, #8
8001a26: af00 add r7, sp, #0
HAL_StatusTypeDef status = HAL_OK;
8001a28: 2300 movs r3, #0
8001a2a: 71fb strb r3, [r7, #7]
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
8001a2c: 2003 movs r0, #3
8001a2e: f002 fa23 bl 8003e78 <HAL_NVIC_SetPriorityGrouping>
/* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
8001a32: 200f movs r0, #15
8001a34: f000 f80e bl 8001a54 <HAL_InitTick>
8001a38: 4603 mov r3, r0
8001a3a: 2b00 cmp r3, #0
8001a3c: d002 beq.n 8001a44 <HAL_Init+0x22>
{
status = HAL_ERROR;
8001a3e: 2301 movs r3, #1
8001a40: 71fb strb r3, [r7, #7]
8001a42: e001 b.n 8001a48 <HAL_Init+0x26>
}
else
{
/* Init the low level hardware */
HAL_MspInit();
8001a44: f7ff fc24 bl 8001290 <HAL_MspInit>
}
/* Return function status */
return status;
8001a48: 79fb ldrb r3, [r7, #7]
}
8001a4a: 4618 mov r0, r3
8001a4c: 3708 adds r7, #8
8001a4e: 46bd mov sp, r7
8001a50: bd80 pop {r7, pc}
...
08001a54 <HAL_InitTick>:
* implementation in user file.
* @param TickPriority: Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
8001a54: b580 push {r7, lr}
8001a56: b084 sub sp, #16
8001a58: af00 add r7, sp, #0
8001a5a: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8001a5c: 2300 movs r3, #0
8001a5e: 73fb strb r3, [r7, #15]
if (uwTickFreq != 0U)
8001a60: 4b16 ldr r3, [pc, #88] @ (8001abc <HAL_InitTick+0x68>)
8001a62: 681b ldr r3, [r3, #0]
8001a64: 2b00 cmp r3, #0
8001a66: d022 beq.n 8001aae <HAL_InitTick+0x5a>
{
/* Configure the SysTick to have interrupt in 1ms time basis*/
if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) == 0U)
8001a68: 4b15 ldr r3, [pc, #84] @ (8001ac0 <HAL_InitTick+0x6c>)
8001a6a: 681a ldr r2, [r3, #0]
8001a6c: 4b13 ldr r3, [pc, #76] @ (8001abc <HAL_InitTick+0x68>)
8001a6e: 681b ldr r3, [r3, #0]
8001a70: f44f 717a mov.w r1, #1000 @ 0x3e8
8001a74: fbb1 f3f3 udiv r3, r1, r3
8001a78: fbb2 f3f3 udiv r3, r2, r3
8001a7c: 4618 mov r0, r3
8001a7e: f002 fa2e bl 8003ede <HAL_SYSTICK_Config>
8001a82: 4603 mov r3, r0
8001a84: 2b00 cmp r3, #0
8001a86: d10f bne.n 8001aa8 <HAL_InitTick+0x54>
{
/* Configure the SysTick IRQ priority */
if (TickPriority < (1UL << __NVIC_PRIO_BITS))
8001a88: 687b ldr r3, [r7, #4]
8001a8a: 2b0f cmp r3, #15
8001a8c: d809 bhi.n 8001aa2 <HAL_InitTick+0x4e>
{
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
8001a8e: 2200 movs r2, #0
8001a90: 6879 ldr r1, [r7, #4]
8001a92: f04f 30ff mov.w r0, #4294967295
8001a96: f002 f9fa bl 8003e8e <HAL_NVIC_SetPriority>
uwTickPrio = TickPriority;
8001a9a: 4a0a ldr r2, [pc, #40] @ (8001ac4 <HAL_InitTick+0x70>)
8001a9c: 687b ldr r3, [r7, #4]
8001a9e: 6013 str r3, [r2, #0]
8001aa0: e007 b.n 8001ab2 <HAL_InitTick+0x5e>
}
else
{
status = HAL_ERROR;
8001aa2: 2301 movs r3, #1
8001aa4: 73fb strb r3, [r7, #15]
8001aa6: e004 b.n 8001ab2 <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8001aa8: 2301 movs r3, #1
8001aaa: 73fb strb r3, [r7, #15]
8001aac: e001 b.n 8001ab2 <HAL_InitTick+0x5e>
}
}
else
{
status = HAL_ERROR;
8001aae: 2301 movs r3, #1
8001ab0: 73fb strb r3, [r7, #15]
}
/* Return function status */
return status;
8001ab2: 7bfb ldrb r3, [r7, #15]
}
8001ab4: 4618 mov r0, r3
8001ab6: 3710 adds r7, #16
8001ab8: 46bd mov sp, r7
8001aba: bd80 pop {r7, pc}
8001abc: 20000008 .word 0x20000008
8001ac0: 20000000 .word 0x20000000
8001ac4: 20000004 .word 0x20000004
08001ac8 <HAL_IncTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
8001ac8: b480 push {r7}
8001aca: af00 add r7, sp, #0
uwTick += uwTickFreq;
8001acc: 4b05 ldr r3, [pc, #20] @ (8001ae4 <HAL_IncTick+0x1c>)
8001ace: 681a ldr r2, [r3, #0]
8001ad0: 4b05 ldr r3, [pc, #20] @ (8001ae8 <HAL_IncTick+0x20>)
8001ad2: 681b ldr r3, [r3, #0]
8001ad4: 4413 add r3, r2
8001ad6: 4a03 ldr r2, [pc, #12] @ (8001ae4 <HAL_IncTick+0x1c>)
8001ad8: 6013 str r3, [r2, #0]
}
8001ada: bf00 nop
8001adc: 46bd mov sp, r7
8001ade: f85d 7b04 ldr.w r7, [sp], #4
8001ae2: 4770 bx lr
8001ae4: 200004c4 .word 0x200004c4
8001ae8: 20000008 .word 0x20000008
08001aec <HAL_GetTick>:
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval tick value
*/
__weak uint32_t HAL_GetTick(void)
{
8001aec: b480 push {r7}
8001aee: af00 add r7, sp, #0
return uwTick;
8001af0: 4b03 ldr r3, [pc, #12] @ (8001b00 <HAL_GetTick+0x14>)
8001af2: 681b ldr r3, [r3, #0]
}
8001af4: 4618 mov r0, r3
8001af6: 46bd mov sp, r7
8001af8: f85d 7b04 ldr.w r7, [sp], #4
8001afc: 4770 bx lr
8001afe: bf00 nop
8001b00: 200004c4 .word 0x200004c4
08001b04 <HAL_Delay>:
* implementations in user file.
* @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
__weak void HAL_Delay(uint32_t Delay)
{
8001b04: b580 push {r7, lr}
8001b06: b084 sub sp, #16
8001b08: af00 add r7, sp, #0
8001b0a: 6078 str r0, [r7, #4]
uint32_t tickstart = HAL_GetTick();
8001b0c: f7ff ffee bl 8001aec <HAL_GetTick>
8001b10: 60b8 str r0, [r7, #8]
uint32_t wait = Delay;
8001b12: 687b ldr r3, [r7, #4]
8001b14: 60fb str r3, [r7, #12]
/* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
8001b16: 68fb ldr r3, [r7, #12]
8001b18: f1b3 3fff cmp.w r3, #4294967295
8001b1c: d004 beq.n 8001b28 <HAL_Delay+0x24>
{
wait += (uint32_t)(uwTickFreq);
8001b1e: 4b09 ldr r3, [pc, #36] @ (8001b44 <HAL_Delay+0x40>)
8001b20: 681b ldr r3, [r3, #0]
8001b22: 68fa ldr r2, [r7, #12]
8001b24: 4413 add r3, r2
8001b26: 60fb str r3, [r7, #12]
}
while ((HAL_GetTick() - tickstart) < wait)
8001b28: bf00 nop
8001b2a: f7ff ffdf bl 8001aec <HAL_GetTick>
8001b2e: 4602 mov r2, r0
8001b30: 68bb ldr r3, [r7, #8]
8001b32: 1ad3 subs r3, r2, r3
8001b34: 68fa ldr r2, [r7, #12]
8001b36: 429a cmp r2, r3
8001b38: d8f7 bhi.n 8001b2a <HAL_Delay+0x26>
{
}
}
8001b3a: bf00 nop
8001b3c: bf00 nop
8001b3e: 3710 adds r7, #16
8001b40: 46bd mov sp, r7
8001b42: bd80 pop {r7, pc}
8001b44: 20000008 .word 0x20000008
08001b48 <HAL_SYSCFG_VREFBUF_VoltageScalingConfig>:
* @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREFBUF_OUT around 2.9 V.
* This requires VDDA equal to or higher than 3.15 V.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling)
{
8001b48: b480 push {r7}
8001b4a: b083 sub sp, #12
8001b4c: af00 add r7, sp, #0
8001b4e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling));
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling);
8001b50: 4b06 ldr r3, [pc, #24] @ (8001b6c <HAL_SYSCFG_VREFBUF_VoltageScalingConfig+0x24>)
8001b52: 681b ldr r3, [r3, #0]
8001b54: f023 0230 bic.w r2, r3, #48 @ 0x30
8001b58: 4904 ldr r1, [pc, #16] @ (8001b6c <HAL_SYSCFG_VREFBUF_VoltageScalingConfig+0x24>)
8001b5a: 687b ldr r3, [r7, #4]
8001b5c: 4313 orrs r3, r2
8001b5e: 600b str r3, [r1, #0]
}
8001b60: bf00 nop
8001b62: 370c adds r7, #12
8001b64: 46bd mov sp, r7
8001b66: f85d 7b04 ldr.w r7, [sp], #4
8001b6a: 4770 bx lr
8001b6c: 40010030 .word 0x40010030
08001b70 <HAL_SYSCFG_VREFBUF_HighImpedanceConfig>:
* @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output.
* @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance.
* @retval None
*/
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode)
{
8001b70: b480 push {r7}
8001b72: b083 sub sp, #12
8001b74: af00 add r7, sp, #0
8001b76: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode));
MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode);
8001b78: 4b06 ldr r3, [pc, #24] @ (8001b94 <HAL_SYSCFG_VREFBUF_HighImpedanceConfig+0x24>)
8001b7a: 681b ldr r3, [r3, #0]
8001b7c: f023 0202 bic.w r2, r3, #2
8001b80: 4904 ldr r1, [pc, #16] @ (8001b94 <HAL_SYSCFG_VREFBUF_HighImpedanceConfig+0x24>)
8001b82: 687b ldr r3, [r7, #4]
8001b84: 4313 orrs r3, r2
8001b86: 600b str r3, [r1, #0]
}
8001b88: bf00 nop
8001b8a: 370c adds r7, #12
8001b8c: 46bd mov sp, r7
8001b8e: f85d 7b04 ldr.w r7, [sp], #4
8001b92: 4770 bx lr
8001b94: 40010030 .word 0x40010030
08001b98 <HAL_SYSCFG_EnableVREFBUF>:
/**
* @brief Enable the Internal Voltage Reference buffer (VREFBUF).
* @retval HAL_OK/HAL_TIMEOUT
*/
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void)
{
8001b98: b580 push {r7, lr}
8001b9a: b082 sub sp, #8
8001b9c: af00 add r7, sp, #0
uint32_t tickstart;
SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR);
8001b9e: 4b0f ldr r3, [pc, #60] @ (8001bdc <HAL_SYSCFG_EnableVREFBUF+0x44>)
8001ba0: 681b ldr r3, [r3, #0]
8001ba2: 4a0e ldr r2, [pc, #56] @ (8001bdc <HAL_SYSCFG_EnableVREFBUF+0x44>)
8001ba4: f043 0301 orr.w r3, r3, #1
8001ba8: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8001baa: f7ff ff9f bl 8001aec <HAL_GetTick>
8001bae: 6078 str r0, [r7, #4]
/* Wait for VRR bit */
while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U)
8001bb0: e008 b.n 8001bc4 <HAL_SYSCFG_EnableVREFBUF+0x2c>
{
if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE)
8001bb2: f7ff ff9b bl 8001aec <HAL_GetTick>
8001bb6: 4602 mov r2, r0
8001bb8: 687b ldr r3, [r7, #4]
8001bba: 1ad3 subs r3, r2, r3
8001bbc: 2b0a cmp r3, #10
8001bbe: d901 bls.n 8001bc4 <HAL_SYSCFG_EnableVREFBUF+0x2c>
{
return HAL_TIMEOUT;
8001bc0: 2303 movs r3, #3
8001bc2: e006 b.n 8001bd2 <HAL_SYSCFG_EnableVREFBUF+0x3a>
while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0x00U)
8001bc4: 4b05 ldr r3, [pc, #20] @ (8001bdc <HAL_SYSCFG_EnableVREFBUF+0x44>)
8001bc6: 681b ldr r3, [r3, #0]
8001bc8: f003 0308 and.w r3, r3, #8
8001bcc: 2b00 cmp r3, #0
8001bce: d0f0 beq.n 8001bb2 <HAL_SYSCFG_EnableVREFBUF+0x1a>
}
}
return HAL_OK;
8001bd0: 2300 movs r3, #0
}
8001bd2: 4618 mov r0, r3
8001bd4: 3708 adds r7, #8
8001bd6: 46bd mov sp, r7
8001bd8: bd80 pop {r7, pc}
8001bda: bf00 nop
8001bdc: 40010030 .word 0x40010030
08001be0 <LL_ADC_SetCommonClock>:
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV128
* @arg @ref LL_ADC_CLOCK_ASYNC_DIV256
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
{
8001be0: b480 push {r7}
8001be2: b083 sub sp, #12
8001be4: af00 add r7, sp, #0
8001be6: 6078 str r0, [r7, #4]
8001be8: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);
8001bea: 687b ldr r3, [r7, #4]
8001bec: 689b ldr r3, [r3, #8]
8001bee: f423 127c bic.w r2, r3, #4128768 @ 0x3f0000
8001bf2: 683b ldr r3, [r7, #0]
8001bf4: 431a orrs r2, r3
8001bf6: 687b ldr r3, [r7, #4]
8001bf8: 609a str r2, [r3, #8]
}
8001bfa: bf00 nop
8001bfc: 370c adds r7, #12
8001bfe: 46bd mov sp, r7
8001c00: f85d 7b04 ldr.w r7, [sp], #4
8001c04: 4770 bx lr
08001c06 <LL_ADC_SetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
{
8001c06: b480 push {r7}
8001c08: b083 sub sp, #12
8001c0a: af00 add r7, sp, #0
8001c0c: 6078 str r0, [r7, #4]
8001c0e: 6039 str r1, [r7, #0]
MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL, PathInternal);
8001c10: 687b ldr r3, [r7, #4]
8001c12: 689b ldr r3, [r3, #8]
8001c14: f023 72e0 bic.w r2, r3, #29360128 @ 0x1c00000
8001c18: 683b ldr r3, [r7, #0]
8001c1a: 431a orrs r2, r3
8001c1c: 687b ldr r3, [r7, #4]
8001c1e: 609a str r2, [r3, #8]
}
8001c20: bf00 nop
8001c22: 370c adds r7, #12
8001c24: 46bd mov sp, r7
8001c26: f85d 7b04 ldr.w r7, [sp], #4
8001c2a: 4770 bx lr
08001c2c <LL_ADC_GetCommonPathInternalCh>:
* @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
* @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
* @arg @ref LL_ADC_PATH_INTERNAL_VBAT
*/
__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
{
8001c2c: b480 push {r7}
8001c2e: b083 sub sp, #12
8001c30: af00 add r7, sp, #0
8001c32: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_VSENSESEL | ADC_CCR_VBATSEL));
8001c34: 687b ldr r3, [r7, #4]
8001c36: 689b ldr r3, [r3, #8]
8001c38: f003 73e0 and.w r3, r3, #29360128 @ 0x1c00000
}
8001c3c: 4618 mov r0, r3
8001c3e: 370c adds r7, #12
8001c40: 46bd mov sp, r7
8001c42: f85d 7b04 ldr.w r7, [sp], #4
8001c46: 4770 bx lr
08001c48 <LL_ADC_SetOffset>:
* (fADC) to convert in 12-bit resolution.\n
* @param OffsetLevel Value between Min_Data=0x000 and Max_Data=0xFFF
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)
{
8001c48: b480 push {r7}
8001c4a: b087 sub sp, #28
8001c4c: af00 add r7, sp, #0
8001c4e: 60f8 str r0, [r7, #12]
8001c50: 60b9 str r1, [r7, #8]
8001c52: 607a str r2, [r7, #4]
8001c54: 603b str r3, [r7, #0]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001c56: 68fb ldr r3, [r7, #12]
8001c58: 3360 adds r3, #96 @ 0x60
8001c5a: 461a mov r2, r3
8001c5c: 68bb ldr r3, [r7, #8]
8001c5e: 009b lsls r3, r3, #2
8001c60: 4413 add r3, r2
8001c62: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001c64: 697b ldr r3, [r7, #20]
8001c66: 681a ldr r2, [r3, #0]
8001c68: 4b08 ldr r3, [pc, #32] @ (8001c8c <LL_ADC_SetOffset+0x44>)
8001c6a: 4013 ands r3, r2
8001c6c: 687a ldr r2, [r7, #4]
8001c6e: f002 41f8 and.w r1, r2, #2080374784 @ 0x7c000000
8001c72: 683a ldr r2, [r7, #0]
8001c74: 430a orrs r2, r1
8001c76: 4313 orrs r3, r2
8001c78: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
8001c7c: 697b ldr r3, [r7, #20]
8001c7e: 601a str r2, [r3, #0]
ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,
ADC_OFR1_OFFSET1_EN | (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);
}
8001c80: bf00 nop
8001c82: 371c adds r7, #28
8001c84: 46bd mov sp, r7
8001c86: f85d 7b04 ldr.w r7, [sp], #4
8001c8a: 4770 bx lr
8001c8c: 03fff000 .word 0x03fff000
08001c90 <LL_ADC_GetOffsetChannel>:
* (1, 2, 3, 4, 5, 7) For ADC channel read back from ADC register,
* comparison with internal channel parameter to be done
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/
__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(const ADC_TypeDef *ADCx, uint32_t Offsety)
{
8001c90: b480 push {r7}
8001c92: b085 sub sp, #20
8001c94: af00 add r7, sp, #0
8001c96: 6078 str r0, [r7, #4]
8001c98: 6039 str r1, [r7, #0]
const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001c9a: 687b ldr r3, [r7, #4]
8001c9c: 3360 adds r3, #96 @ 0x60
8001c9e: 461a mov r2, r3
8001ca0: 683b ldr r3, [r7, #0]
8001ca2: 009b lsls r3, r3, #2
8001ca4: 4413 add r3, r2
8001ca6: 60fb str r3, [r7, #12]
return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);
8001ca8: 68fb ldr r3, [r7, #12]
8001caa: 681b ldr r3, [r3, #0]
8001cac: f003 43f8 and.w r3, r3, #2080374784 @ 0x7c000000
}
8001cb0: 4618 mov r0, r3
8001cb2: 3714 adds r7, #20
8001cb4: 46bd mov sp, r7
8001cb6: f85d 7b04 ldr.w r7, [sp], #4
8001cba: 4770 bx lr
08001cbc <LL_ADC_SetOffsetState>:
* @arg @ref LL_ADC_OFFSET_DISABLE
* @arg @ref LL_ADC_OFFSET_ENABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetState(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetState)
{
8001cbc: b480 push {r7}
8001cbe: b087 sub sp, #28
8001cc0: af00 add r7, sp, #0
8001cc2: 60f8 str r0, [r7, #12]
8001cc4: 60b9 str r1, [r7, #8]
8001cc6: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001cc8: 68fb ldr r3, [r7, #12]
8001cca: 3360 adds r3, #96 @ 0x60
8001ccc: 461a mov r2, r3
8001cce: 68bb ldr r3, [r7, #8]
8001cd0: 009b lsls r3, r3, #2
8001cd2: 4413 add r3, r2
8001cd4: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001cd6: 697b ldr r3, [r7, #20]
8001cd8: 681b ldr r3, [r3, #0]
8001cda: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
8001cde: 687b ldr r3, [r7, #4]
8001ce0: 431a orrs r2, r3
8001ce2: 697b ldr r3, [r7, #20]
8001ce4: 601a str r2, [r3, #0]
ADC_OFR1_OFFSET1_EN,
OffsetState);
}
8001ce6: bf00 nop
8001ce8: 371c adds r7, #28
8001cea: 46bd mov sp, r7
8001cec: f85d 7b04 ldr.w r7, [sp], #4
8001cf0: 4770 bx lr
08001cf2 <LL_ADC_SetOffsetSign>:
* @arg @ref LL_ADC_OFFSET_SIGN_NEGATIVE
* @arg @ref LL_ADC_OFFSET_SIGN_POSITIVE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSign(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSign)
{
8001cf2: b480 push {r7}
8001cf4: b087 sub sp, #28
8001cf6: af00 add r7, sp, #0
8001cf8: 60f8 str r0, [r7, #12]
8001cfa: 60b9 str r1, [r7, #8]
8001cfc: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001cfe: 68fb ldr r3, [r7, #12]
8001d00: 3360 adds r3, #96 @ 0x60
8001d02: 461a mov r2, r3
8001d04: 68bb ldr r3, [r7, #8]
8001d06: 009b lsls r3, r3, #2
8001d08: 4413 add r3, r2
8001d0a: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001d0c: 697b ldr r3, [r7, #20]
8001d0e: 681b ldr r3, [r3, #0]
8001d10: f023 7280 bic.w r2, r3, #16777216 @ 0x1000000
8001d14: 687b ldr r3, [r7, #4]
8001d16: 431a orrs r2, r3
8001d18: 697b ldr r3, [r7, #20]
8001d1a: 601a str r2, [r3, #0]
ADC_OFR1_OFFSETPOS,
OffsetSign);
}
8001d1c: bf00 nop
8001d1e: 371c adds r7, #28
8001d20: 46bd mov sp, r7
8001d22: f85d 7b04 ldr.w r7, [sp], #4
8001d26: 4770 bx lr
08001d28 <LL_ADC_SetOffsetSaturation>:
* @arg @ref LL_ADC_OFFSET_SATURATION_ENABLE
* @arg @ref LL_ADC_OFFSET_SATURATION_DISABLE
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetOffsetSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSaturation)
{
8001d28: b480 push {r7}
8001d2a: b087 sub sp, #28
8001d2c: af00 add r7, sp, #0
8001d2e: 60f8 str r0, [r7, #12]
8001d30: 60b9 str r1, [r7, #8]
8001d32: 607a str r2, [r7, #4]
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);
8001d34: 68fb ldr r3, [r7, #12]
8001d36: 3360 adds r3, #96 @ 0x60
8001d38: 461a mov r2, r3
8001d3a: 68bb ldr r3, [r7, #8]
8001d3c: 009b lsls r3, r3, #2
8001d3e: 4413 add r3, r2
8001d40: 617b str r3, [r7, #20]
MODIFY_REG(*preg,
8001d42: 697b ldr r3, [r7, #20]
8001d44: 681b ldr r3, [r3, #0]
8001d46: f023 7200 bic.w r2, r3, #33554432 @ 0x2000000
8001d4a: 687b ldr r3, [r7, #4]
8001d4c: 431a orrs r2, r3
8001d4e: 697b ldr r3, [r7, #20]
8001d50: 601a str r2, [r3, #0]
ADC_OFR1_SATEN,
OffsetSaturation);
}
8001d52: bf00 nop
8001d54: 371c adds r7, #28
8001d56: 46bd mov sp, r7
8001d58: f85d 7b04 ldr.w r7, [sp], #4
8001d5c: 4770 bx lr
08001d5e <LL_ADC_SetSamplingTimeCommonConfig>:
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_DEFAULT
* @arg @ref LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonConfig(ADC_TypeDef *ADCx, uint32_t SamplingTimeCommonConfig)
{
8001d5e: b480 push {r7}
8001d60: b083 sub sp, #12
8001d62: af00 add r7, sp, #0
8001d64: 6078 str r0, [r7, #4]
8001d66: 6039 str r1, [r7, #0]
MODIFY_REG(ADCx->SMPR1, ADC_SMPR1_SMPPLUS, SamplingTimeCommonConfig);
8001d68: 687b ldr r3, [r7, #4]
8001d6a: 695b ldr r3, [r3, #20]
8001d6c: f023 4200 bic.w r2, r3, #2147483648 @ 0x80000000
8001d70: 683b ldr r3, [r7, #0]
8001d72: 431a orrs r2, r3
8001d74: 687b ldr r3, [r7, #4]
8001d76: 615a str r2, [r3, #20]
}
8001d78: bf00 nop
8001d7a: 370c adds r7, #12
8001d7c: 46bd mov sp, r7
8001d7e: f85d 7b04 ldr.w r7, [sp], #4
8001d82: 4770 bx lr
08001d84 <LL_ADC_REG_IsTriggerSourceSWStart>:
* @param ADCx ADC instance
* @retval Value "0" if trigger source external trigger
* Value "1" if trigger source SW start.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
{
8001d84: b480 push {r7}
8001d86: b083 sub sp, #12
8001d88: af00 add r7, sp, #0
8001d8a: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);
8001d8c: 687b ldr r3, [r7, #4]
8001d8e: 68db ldr r3, [r3, #12]
8001d90: f403 6340 and.w r3, r3, #3072 @ 0xc00
8001d94: 2b00 cmp r3, #0
8001d96: d101 bne.n 8001d9c <LL_ADC_REG_IsTriggerSourceSWStart+0x18>
8001d98: 2301 movs r3, #1
8001d9a: e000 b.n 8001d9e <LL_ADC_REG_IsTriggerSourceSWStart+0x1a>
8001d9c: 2300 movs r3, #0
}
8001d9e: 4618 mov r0, r3
8001da0: 370c adds r7, #12
8001da2: 46bd mov sp, r7
8001da4: f85d 7b04 ldr.w r7, [sp], #4
8001da8: 4770 bx lr
08001daa <LL_ADC_REG_SetSequencerRanks>:
* Other channels are slow channels allows: 6.5 (sampling) + 12.5 (conversion) = 19 ADC clock cycles
* (fADC) to convert in 12-bit resolution.\n
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
{
8001daa: b480 push {r7}
8001dac: b087 sub sp, #28
8001dae: af00 add r7, sp, #0
8001db0: 60f8 str r0, [r7, #12]
8001db2: 60b9 str r1, [r7, #8]
8001db4: 607a str r2, [r7, #4]
/* Set bits with content of parameter "Channel" with bits position */
/* in register and register position depending on parameter "Rank". */
/* Parameters "Rank" and "Channel" are used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1,
8001db6: 68fb ldr r3, [r7, #12]
8001db8: 3330 adds r3, #48 @ 0x30
8001dba: 461a mov r2, r3
8001dbc: 68bb ldr r3, [r7, #8]
8001dbe: 0a1b lsrs r3, r3, #8
8001dc0: 009b lsls r3, r3, #2
8001dc2: f003 030c and.w r3, r3, #12
8001dc6: 4413 add r3, r2
8001dc8: 617b str r3, [r7, #20]
((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));
MODIFY_REG(*preg,
8001dca: 697b ldr r3, [r7, #20]
8001dcc: 681a ldr r2, [r3, #0]
8001dce: 68bb ldr r3, [r7, #8]
8001dd0: f003 031f and.w r3, r3, #31
8001dd4: 211f movs r1, #31
8001dd6: fa01 f303 lsl.w r3, r1, r3
8001dda: 43db mvns r3, r3
8001ddc: 401a ands r2, r3
8001dde: 687b ldr r3, [r7, #4]
8001de0: 0e9b lsrs r3, r3, #26
8001de2: f003 011f and.w r1, r3, #31
8001de6: 68bb ldr r3, [r7, #8]
8001de8: f003 031f and.w r3, r3, #31
8001dec: fa01 f303 lsl.w r3, r1, r3
8001df0: 431a orrs r2, r3
8001df2: 697b ldr r3, [r7, #20]
8001df4: 601a str r2, [r3, #0]
ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
<< (Rank & ADC_REG_RANK_ID_SQRX_MASK));
}
8001df6: bf00 nop
8001df8: 371c adds r7, #28
8001dfa: 46bd mov sp, r7
8001dfc: f85d 7b04 ldr.w r7, [sp], #4
8001e00: 4770 bx lr
08001e02 <LL_ADC_SetChannelSamplingTime>:
* can be replaced by 3.5 ADC clock cycles.
* Refer to function @ref LL_ADC_SetSamplingTimeCommonConfig().
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)
{
8001e02: b480 push {r7}
8001e04: b087 sub sp, #28
8001e06: af00 add r7, sp, #0
8001e08: 60f8 str r0, [r7, #12]
8001e0a: 60b9 str r1, [r7, #8]
8001e0c: 607a str r2, [r7, #4]
/* Set bits with content of parameter "SamplingTime" with bits position */
/* in register and register position depending on parameter "Channel". */
/* Parameter "Channel" is used with masks because containing */
/* other bits reserved for other purpose. */
__IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1,
8001e0e: 68fb ldr r3, [r7, #12]
8001e10: 3314 adds r3, #20
8001e12: 461a mov r2, r3
8001e14: 68bb ldr r3, [r7, #8]
8001e16: 0e5b lsrs r3, r3, #25
8001e18: 009b lsls r3, r3, #2
8001e1a: f003 0304 and.w r3, r3, #4
8001e1e: 4413 add r3, r2
8001e20: 617b str r3, [r7, #20]
((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));
MODIFY_REG(*preg,
8001e22: 697b ldr r3, [r7, #20]
8001e24: 681a ldr r2, [r3, #0]
8001e26: 68bb ldr r3, [r7, #8]
8001e28: 0d1b lsrs r3, r3, #20
8001e2a: f003 031f and.w r3, r3, #31
8001e2e: 2107 movs r1, #7
8001e30: fa01 f303 lsl.w r3, r1, r3
8001e34: 43db mvns r3, r3
8001e36: 401a ands r2, r3
8001e38: 68bb ldr r3, [r7, #8]
8001e3a: 0d1b lsrs r3, r3, #20
8001e3c: f003 031f and.w r3, r3, #31
8001e40: 6879 ldr r1, [r7, #4]
8001e42: fa01 f303 lsl.w r3, r1, r3
8001e46: 431a orrs r2, r3
8001e48: 697b ldr r3, [r7, #20]
8001e4a: 601a str r2, [r3, #0]
ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),
SamplingTime << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));
}
8001e4c: bf00 nop
8001e4e: 371c adds r7, #28
8001e50: 46bd mov sp, r7
8001e52: f85d 7b04 ldr.w r7, [sp], #4
8001e56: 4770 bx lr
08001e58 <LL_ADC_SetChannelSingleDiff>:
* @arg @ref LL_ADC_SINGLE_ENDED
* @arg @ref LL_ADC_DIFFERENTIAL_ENDED
* @retval None
*/
__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)
{
8001e58: b480 push {r7}
8001e5a: b085 sub sp, #20
8001e5c: af00 add r7, sp, #0
8001e5e: 60f8 str r0, [r7, #12]
8001e60: 60b9 str r1, [r7, #8]
8001e62: 607a str r2, [r7, #4]
/* Bits of channels in single or differential mode are set only for */
/* differential mode (for single mode, mask of bits allowed to be set is */
/* shifted out of range of bits of channels in single or differential mode. */
MODIFY_REG(ADCx->DIFSEL,
8001e64: 68fb ldr r3, [r7, #12]
8001e66: f8d3 20b0 ldr.w r2, [r3, #176] @ 0xb0
8001e6a: 68bb ldr r3, [r7, #8]
8001e6c: f3c3 0312 ubfx r3, r3, #0, #19
8001e70: 43db mvns r3, r3
8001e72: 401a ands r2, r3
8001e74: 687b ldr r3, [r7, #4]
8001e76: f003 0318 and.w r3, r3, #24
8001e7a: 4908 ldr r1, [pc, #32] @ (8001e9c <LL_ADC_SetChannelSingleDiff+0x44>)
8001e7c: 40d9 lsrs r1, r3
8001e7e: 68bb ldr r3, [r7, #8]
8001e80: 400b ands r3, r1
8001e82: f3c3 0312 ubfx r3, r3, #0, #19
8001e86: 431a orrs r2, r3
8001e88: 68fb ldr r3, [r7, #12]
8001e8a: f8c3 20b0 str.w r2, [r3, #176] @ 0xb0
Channel & ADC_SINGLEDIFF_CHANNEL_MASK,
(Channel & ADC_SINGLEDIFF_CHANNEL_MASK)
& (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));
}
8001e8e: bf00 nop
8001e90: 3714 adds r7, #20
8001e92: 46bd mov sp, r7
8001e94: f85d 7b04 ldr.w r7, [sp], #4
8001e98: 4770 bx lr
8001e9a: bf00 nop
8001e9c: 0007ffff .word 0x0007ffff
08001ea0 <LL_ADC_GetMultimode>:
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM
* @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT
* @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM
*/
__STATIC_INLINE uint32_t LL_ADC_GetMultimode(const ADC_Common_TypeDef *ADCxy_COMMON)
{
8001ea0: b480 push {r7}
8001ea2: b083 sub sp, #12
8001ea4: af00 add r7, sp, #0
8001ea6: 6078 str r0, [r7, #4]
return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));
8001ea8: 687b ldr r3, [r7, #4]
8001eaa: 689b ldr r3, [r3, #8]
8001eac: f003 031f and.w r3, r3, #31
}
8001eb0: 4618 mov r0, r3
8001eb2: 370c adds r7, #12
8001eb4: 46bd mov sp, r7
8001eb6: f85d 7b04 ldr.w r7, [sp], #4
8001eba: 4770 bx lr
08001ebc <LL_ADC_DisableDeepPowerDown>:
* @rmtoll CR DEEPPWD LL_ADC_DisableDeepPowerDown
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)
{
8001ebc: b480 push {r7}
8001ebe: b083 sub sp, #12
8001ec0: af00 add r7, sp, #0
8001ec2: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));
8001ec4: 687b ldr r3, [r7, #4]
8001ec6: 689b ldr r3, [r3, #8]
8001ec8: f023 4320 bic.w r3, r3, #2684354560 @ 0xa0000000
8001ecc: f023 033f bic.w r3, r3, #63 @ 0x3f
8001ed0: 687a ldr r2, [r7, #4]
8001ed2: 6093 str r3, [r2, #8]
}
8001ed4: bf00 nop
8001ed6: 370c adds r7, #12
8001ed8: 46bd mov sp, r7
8001eda: f85d 7b04 ldr.w r7, [sp], #4
8001ede: 4770 bx lr
08001ee0 <LL_ADC_IsDeepPowerDownEnabled>:
* @rmtoll CR DEEPPWD LL_ADC_IsDeepPowerDownEnabled
* @param ADCx ADC instance
* @retval 0: deep power down is disabled, 1: deep power down is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(const ADC_TypeDef *ADCx)
{
8001ee0: b480 push {r7}
8001ee2: b083 sub sp, #12
8001ee4: af00 add r7, sp, #0
8001ee6: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);
8001ee8: 687b ldr r3, [r7, #4]
8001eea: 689b ldr r3, [r3, #8]
8001eec: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
8001ef0: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
8001ef4: d101 bne.n 8001efa <LL_ADC_IsDeepPowerDownEnabled+0x1a>
8001ef6: 2301 movs r3, #1
8001ef8: e000 b.n 8001efc <LL_ADC_IsDeepPowerDownEnabled+0x1c>
8001efa: 2300 movs r3, #0
}
8001efc: 4618 mov r0, r3
8001efe: 370c adds r7, #12
8001f00: 46bd mov sp, r7
8001f02: f85d 7b04 ldr.w r7, [sp], #4
8001f06: 4770 bx lr
08001f08 <LL_ADC_EnableInternalRegulator>:
* @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
{
8001f08: b480 push {r7}
8001f0a: b083 sub sp, #12
8001f0c: af00 add r7, sp, #0
8001f0e: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001f10: 687b ldr r3, [r7, #4]
8001f12: 689b ldr r3, [r3, #8]
8001f14: f023 4310 bic.w r3, r3, #2415919104 @ 0x90000000
8001f18: f023 033f bic.w r3, r3, #63 @ 0x3f
8001f1c: f043 5280 orr.w r2, r3, #268435456 @ 0x10000000
8001f20: 687b ldr r3, [r7, #4]
8001f22: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADVREGEN);
}
8001f24: bf00 nop
8001f26: 370c adds r7, #12
8001f28: 46bd mov sp, r7
8001f2a: f85d 7b04 ldr.w r7, [sp], #4
8001f2e: 4770 bx lr
08001f30 <LL_ADC_IsInternalRegulatorEnabled>:
* @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled
* @param ADCx ADC instance
* @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
{
8001f30: b480 push {r7}
8001f32: b083 sub sp, #12
8001f34: af00 add r7, sp, #0
8001f36: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
8001f38: 687b ldr r3, [r7, #4]
8001f3a: 689b ldr r3, [r3, #8]
8001f3c: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8001f40: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
8001f44: d101 bne.n 8001f4a <LL_ADC_IsInternalRegulatorEnabled+0x1a>
8001f46: 2301 movs r3, #1
8001f48: e000 b.n 8001f4c <LL_ADC_IsInternalRegulatorEnabled+0x1c>
8001f4a: 2300 movs r3, #0
}
8001f4c: 4618 mov r0, r3
8001f4e: 370c adds r7, #12
8001f50: 46bd mov sp, r7
8001f52: f85d 7b04 ldr.w r7, [sp], #4
8001f56: 4770 bx lr
08001f58 <LL_ADC_Enable>:
* @rmtoll CR ADEN LL_ADC_Enable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
{
8001f58: b480 push {r7}
8001f5a: b083 sub sp, #12
8001f5c: af00 add r7, sp, #0
8001f5e: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001f60: 687b ldr r3, [r7, #4]
8001f62: 689b ldr r3, [r3, #8]
8001f64: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8001f68: f023 033f bic.w r3, r3, #63 @ 0x3f
8001f6c: f043 0201 orr.w r2, r3, #1
8001f70: 687b ldr r3, [r7, #4]
8001f72: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADEN);
}
8001f74: bf00 nop
8001f76: 370c adds r7, #12
8001f78: 46bd mov sp, r7
8001f7a: f85d 7b04 ldr.w r7, [sp], #4
8001f7e: 4770 bx lr
08001f80 <LL_ADC_Disable>:
* @rmtoll CR ADDIS LL_ADC_Disable
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
{
8001f80: b480 push {r7}
8001f82: b083 sub sp, #12
8001f84: af00 add r7, sp, #0
8001f86: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001f88: 687b ldr r3, [r7, #4]
8001f8a: 689b ldr r3, [r3, #8]
8001f8c: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8001f90: f023 033f bic.w r3, r3, #63 @ 0x3f
8001f94: f043 0202 orr.w r2, r3, #2
8001f98: 687b ldr r3, [r7, #4]
8001f9a: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADDIS);
}
8001f9c: bf00 nop
8001f9e: 370c adds r7, #12
8001fa0: 46bd mov sp, r7
8001fa2: f85d 7b04 ldr.w r7, [sp], #4
8001fa6: 4770 bx lr
08001fa8 <LL_ADC_IsEnabled>:
* @rmtoll CR ADEN LL_ADC_IsEnabled
* @param ADCx ADC instance
* @retval 0: ADC is disabled, 1: ADC is enabled.
*/
__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
{
8001fa8: b480 push {r7}
8001faa: b083 sub sp, #12
8001fac: af00 add r7, sp, #0
8001fae: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
8001fb0: 687b ldr r3, [r7, #4]
8001fb2: 689b ldr r3, [r3, #8]
8001fb4: f003 0301 and.w r3, r3, #1
8001fb8: 2b01 cmp r3, #1
8001fba: d101 bne.n 8001fc0 <LL_ADC_IsEnabled+0x18>
8001fbc: 2301 movs r3, #1
8001fbe: e000 b.n 8001fc2 <LL_ADC_IsEnabled+0x1a>
8001fc0: 2300 movs r3, #0
}
8001fc2: 4618 mov r0, r3
8001fc4: 370c adds r7, #12
8001fc6: 46bd mov sp, r7
8001fc8: f85d 7b04 ldr.w r7, [sp], #4
8001fcc: 4770 bx lr
08001fce <LL_ADC_IsDisableOngoing>:
* @rmtoll CR ADDIS LL_ADC_IsDisableOngoing
* @param ADCx ADC instance
* @retval 0: no ADC disable command on going.
*/
__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
{
8001fce: b480 push {r7}
8001fd0: b083 sub sp, #12
8001fd2: af00 add r7, sp, #0
8001fd4: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
8001fd6: 687b ldr r3, [r7, #4]
8001fd8: 689b ldr r3, [r3, #8]
8001fda: f003 0302 and.w r3, r3, #2
8001fde: 2b02 cmp r3, #2
8001fe0: d101 bne.n 8001fe6 <LL_ADC_IsDisableOngoing+0x18>
8001fe2: 2301 movs r3, #1
8001fe4: e000 b.n 8001fe8 <LL_ADC_IsDisableOngoing+0x1a>
8001fe6: 2300 movs r3, #0
}
8001fe8: 4618 mov r0, r3
8001fea: 370c adds r7, #12
8001fec: 46bd mov sp, r7
8001fee: f85d 7b04 ldr.w r7, [sp], #4
8001ff2: 4770 bx lr
08001ff4 <LL_ADC_REG_StartConversion>:
* @rmtoll CR ADSTART LL_ADC_REG_StartConversion
* @param ADCx ADC instance
* @retval None
*/
__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
{
8001ff4: b480 push {r7}
8001ff6: b083 sub sp, #12
8001ff8: af00 add r7, sp, #0
8001ffa: 6078 str r0, [r7, #4]
/* Note: Write register with some additional bits forced to state reset */
/* instead of modifying only the selected bit for this function, */
/* to not interfere with bits with HW property "rs". */
MODIFY_REG(ADCx->CR,
8001ffc: 687b ldr r3, [r7, #4]
8001ffe: 689b ldr r3, [r3, #8]
8002000: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8002004: f023 033f bic.w r3, r3, #63 @ 0x3f
8002008: f043 0204 orr.w r2, r3, #4
800200c: 687b ldr r3, [r7, #4]
800200e: 609a str r2, [r3, #8]
ADC_CR_BITS_PROPERTY_RS,
ADC_CR_ADSTART);
}
8002010: bf00 nop
8002012: 370c adds r7, #12
8002014: 46bd mov sp, r7
8002016: f85d 7b04 ldr.w r7, [sp], #4
800201a: 4770 bx lr
0800201c <LL_ADC_REG_IsConversionOngoing>:
* @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group regular.
*/
__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
800201c: b480 push {r7}
800201e: b083 sub sp, #12
8002020: af00 add r7, sp, #0
8002022: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
8002024: 687b ldr r3, [r7, #4]
8002026: 689b ldr r3, [r3, #8]
8002028: f003 0304 and.w r3, r3, #4
800202c: 2b04 cmp r3, #4
800202e: d101 bne.n 8002034 <LL_ADC_REG_IsConversionOngoing+0x18>
8002030: 2301 movs r3, #1
8002032: e000 b.n 8002036 <LL_ADC_REG_IsConversionOngoing+0x1a>
8002034: 2300 movs r3, #0
}
8002036: 4618 mov r0, r3
8002038: 370c adds r7, #12
800203a: 46bd mov sp, r7
800203c: f85d 7b04 ldr.w r7, [sp], #4
8002040: 4770 bx lr
08002042 <LL_ADC_INJ_IsConversionOngoing>:
* @rmtoll CR JADSTART LL_ADC_INJ_IsConversionOngoing
* @param ADCx ADC instance
* @retval 0: no conversion is on going on ADC group injected.
*/
__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(const ADC_TypeDef *ADCx)
{
8002042: b480 push {r7}
8002044: b083 sub sp, #12
8002046: af00 add r7, sp, #0
8002048: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);
800204a: 687b ldr r3, [r7, #4]
800204c: 689b ldr r3, [r3, #8]
800204e: f003 0308 and.w r3, r3, #8
8002052: 2b08 cmp r3, #8
8002054: d101 bne.n 800205a <LL_ADC_INJ_IsConversionOngoing+0x18>
8002056: 2301 movs r3, #1
8002058: e000 b.n 800205c <LL_ADC_INJ_IsConversionOngoing+0x1a>
800205a: 2300 movs r3, #0
}
800205c: 4618 mov r0, r3
800205e: 370c adds r7, #12
8002060: 46bd mov sp, r7
8002062: f85d 7b04 ldr.w r7, [sp], #4
8002066: 4770 bx lr
08002068 <HAL_ADC_Init>:
* without disabling the other ADCs.
* @param hadc ADC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
{
8002068: b590 push {r4, r7, lr}
800206a: b089 sub sp, #36 @ 0x24
800206c: af00 add r7, sp, #0
800206e: 6078 str r0, [r7, #4]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
8002070: 2300 movs r3, #0
8002072: 77fb strb r3, [r7, #31]
uint32_t tmp_cfgr;
uint32_t tmp_adc_is_conversion_on_going_regular;
uint32_t tmp_adc_is_conversion_on_going_injected;
__IO uint32_t wait_loop_index = 0UL;
8002074: 2300 movs r3, #0
8002076: 60fb str r3, [r7, #12]
/* Check ADC handle */
if (hadc == NULL)
8002078: 687b ldr r3, [r7, #4]
800207a: 2b00 cmp r3, #0
800207c: d101 bne.n 8002082 <HAL_ADC_Init+0x1a>
{
return HAL_ERROR;
800207e: 2301 movs r3, #1
8002080: e1a9 b.n 80023d6 <HAL_ADC_Init+0x36e>
assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
8002082: 687b ldr r3, [r7, #4]
8002084: 695b ldr r3, [r3, #20]
8002086: 2b00 cmp r3, #0
/* DISCEN and CONT bits cannot be set at the same time */
assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
/* Actions performed only if ADC is coming from state reset: */
/* - Initialization of ADC MSP */
if (hadc->State == HAL_ADC_STATE_RESET)
8002088: 687b ldr r3, [r7, #4]
800208a: 6ddb ldr r3, [r3, #92] @ 0x5c
800208c: 2b00 cmp r3, #0
800208e: d109 bne.n 80020a4 <HAL_ADC_Init+0x3c>
/* Init the low level hardware */
hadc->MspInitCallback(hadc);
#else
/* Init the low level hardware */
HAL_ADC_MspInit(hadc);
8002090: 6878 ldr r0, [r7, #4]
8002092: f7ff f929 bl 80012e8 <HAL_ADC_MspInit>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/* Set ADC error code to none */
ADC_CLEAR_ERRORCODE(hadc);
8002096: 687b ldr r3, [r7, #4]
8002098: 2200 movs r2, #0
800209a: 661a str r2, [r3, #96] @ 0x60
/* Initialize Lock */
hadc->Lock = HAL_UNLOCKED;
800209c: 687b ldr r3, [r7, #4]
800209e: 2200 movs r2, #0
80020a0: f883 2058 strb.w r2, [r3, #88] @ 0x58
}
/* - Exit from deep-power-down mode and ADC voltage regulator enable */
if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
80020a4: 687b ldr r3, [r7, #4]
80020a6: 681b ldr r3, [r3, #0]
80020a8: 4618 mov r0, r3
80020aa: f7ff ff19 bl 8001ee0 <LL_ADC_IsDeepPowerDownEnabled>
80020ae: 4603 mov r3, r0
80020b0: 2b00 cmp r3, #0
80020b2: d004 beq.n 80020be <HAL_ADC_Init+0x56>
{
/* Disable ADC deep power down mode */
LL_ADC_DisableDeepPowerDown(hadc->Instance);
80020b4: 687b ldr r3, [r7, #4]
80020b6: 681b ldr r3, [r3, #0]
80020b8: 4618 mov r0, r3
80020ba: f7ff feff bl 8001ebc <LL_ADC_DisableDeepPowerDown>
/* System was in deep power down mode, calibration must
be relaunched or a previously saved calibration factor
re-applied once the ADC voltage regulator is enabled */
}
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
80020be: 687b ldr r3, [r7, #4]
80020c0: 681b ldr r3, [r3, #0]
80020c2: 4618 mov r0, r3
80020c4: f7ff ff34 bl 8001f30 <LL_ADC_IsInternalRegulatorEnabled>
80020c8: 4603 mov r3, r0
80020ca: 2b00 cmp r3, #0
80020cc: d115 bne.n 80020fa <HAL_ADC_Init+0x92>
{
/* Enable ADC internal voltage regulator */
LL_ADC_EnableInternalRegulator(hadc->Instance);
80020ce: 687b ldr r3, [r7, #4]
80020d0: 681b ldr r3, [r3, #0]
80020d2: 4618 mov r0, r3
80020d4: f7ff ff18 bl 8001f08 <LL_ADC_EnableInternalRegulator>
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
80020d8: 4b9c ldr r3, [pc, #624] @ (800234c <HAL_ADC_Init+0x2e4>)
80020da: 681b ldr r3, [r3, #0]
80020dc: 099b lsrs r3, r3, #6
80020de: 4a9c ldr r2, [pc, #624] @ (8002350 <HAL_ADC_Init+0x2e8>)
80020e0: fba2 2303 umull r2, r3, r2, r3
80020e4: 099b lsrs r3, r3, #6
80020e6: 3301 adds r3, #1
80020e8: 005b lsls r3, r3, #1
80020ea: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
80020ec: e002 b.n 80020f4 <HAL_ADC_Init+0x8c>
{
wait_loop_index--;
80020ee: 68fb ldr r3, [r7, #12]
80020f0: 3b01 subs r3, #1
80020f2: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
80020f4: 68fb ldr r3, [r7, #12]
80020f6: 2b00 cmp r3, #0
80020f8: d1f9 bne.n 80020ee <HAL_ADC_Init+0x86>
}
/* Verification that ADC voltage regulator is correctly enabled, whether */
/* or not ADC is coming from state reset (if any potential problem of */
/* clocking, voltage regulator would not be enabled). */
if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
80020fa: 687b ldr r3, [r7, #4]
80020fc: 681b ldr r3, [r3, #0]
80020fe: 4618 mov r0, r3
8002100: f7ff ff16 bl 8001f30 <LL_ADC_IsInternalRegulatorEnabled>
8002104: 4603 mov r3, r0
8002106: 2b00 cmp r3, #0
8002108: d10d bne.n 8002126 <HAL_ADC_Init+0xbe>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800210a: 687b ldr r3, [r7, #4]
800210c: 6ddb ldr r3, [r3, #92] @ 0x5c
800210e: f043 0210 orr.w r2, r3, #16
8002112: 687b ldr r3, [r7, #4]
8002114: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002116: 687b ldr r3, [r7, #4]
8002118: 6e1b ldr r3, [r3, #96] @ 0x60
800211a: f043 0201 orr.w r2, r3, #1
800211e: 687b ldr r3, [r7, #4]
8002120: 661a str r2, [r3, #96] @ 0x60
tmp_hal_status = HAL_ERROR;
8002122: 2301 movs r3, #1
8002124: 77fb strb r3, [r7, #31]
/* Configuration of ADC parameters if previous preliminary actions are */
/* correctly completed and if there is no conversion on going on regular */
/* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
/* called to update a parameter on the fly). */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
8002126: 687b ldr r3, [r7, #4]
8002128: 681b ldr r3, [r3, #0]
800212a: 4618 mov r0, r3
800212c: f7ff ff76 bl 800201c <LL_ADC_REG_IsConversionOngoing>
8002130: 6178 str r0, [r7, #20]
if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
8002132: 687b ldr r3, [r7, #4]
8002134: 6ddb ldr r3, [r3, #92] @ 0x5c
8002136: f003 0310 and.w r3, r3, #16
800213a: 2b00 cmp r3, #0
800213c: f040 8142 bne.w 80023c4 <HAL_ADC_Init+0x35c>
&& (tmp_adc_is_conversion_on_going_regular == 0UL)
8002140: 697b ldr r3, [r7, #20]
8002142: 2b00 cmp r3, #0
8002144: f040 813e bne.w 80023c4 <HAL_ADC_Init+0x35c>
)
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8002148: 687b ldr r3, [r7, #4]
800214a: 6ddb ldr r3, [r3, #92] @ 0x5c
800214c: f423 7381 bic.w r3, r3, #258 @ 0x102
8002150: f043 0202 orr.w r2, r3, #2
8002154: 687b ldr r3, [r7, #4]
8002156: 65da str r2, [r3, #92] @ 0x5c
/* Configuration of common ADC parameters */
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - clock configuration */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8002158: 687b ldr r3, [r7, #4]
800215a: 681b ldr r3, [r3, #0]
800215c: 4618 mov r0, r3
800215e: f7ff ff23 bl 8001fa8 <LL_ADC_IsEnabled>
8002162: 4603 mov r3, r0
8002164: 2b00 cmp r3, #0
8002166: d141 bne.n 80021ec <HAL_ADC_Init+0x184>
{
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
8002168: 687b ldr r3, [r7, #4]
800216a: 681b ldr r3, [r3, #0]
800216c: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8002170: d004 beq.n 800217c <HAL_ADC_Init+0x114>
8002172: 687b ldr r3, [r7, #4]
8002174: 681b ldr r3, [r3, #0]
8002176: 4a77 ldr r2, [pc, #476] @ (8002354 <HAL_ADC_Init+0x2ec>)
8002178: 4293 cmp r3, r2
800217a: d10f bne.n 800219c <HAL_ADC_Init+0x134>
800217c: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
8002180: f7ff ff12 bl 8001fa8 <LL_ADC_IsEnabled>
8002184: 4604 mov r4, r0
8002186: 4873 ldr r0, [pc, #460] @ (8002354 <HAL_ADC_Init+0x2ec>)
8002188: f7ff ff0e bl 8001fa8 <LL_ADC_IsEnabled>
800218c: 4603 mov r3, r0
800218e: 4323 orrs r3, r4
8002190: 2b00 cmp r3, #0
8002192: bf0c ite eq
8002194: 2301 moveq r3, #1
8002196: 2300 movne r3, #0
8002198: b2db uxtb r3, r3
800219a: e012 b.n 80021c2 <HAL_ADC_Init+0x15a>
800219c: 486e ldr r0, [pc, #440] @ (8002358 <HAL_ADC_Init+0x2f0>)
800219e: f7ff ff03 bl 8001fa8 <LL_ADC_IsEnabled>
80021a2: 4604 mov r4, r0
80021a4: 486d ldr r0, [pc, #436] @ (800235c <HAL_ADC_Init+0x2f4>)
80021a6: f7ff feff bl 8001fa8 <LL_ADC_IsEnabled>
80021aa: 4603 mov r3, r0
80021ac: 431c orrs r4, r3
80021ae: 486c ldr r0, [pc, #432] @ (8002360 <HAL_ADC_Init+0x2f8>)
80021b0: f7ff fefa bl 8001fa8 <LL_ADC_IsEnabled>
80021b4: 4603 mov r3, r0
80021b6: 4323 orrs r3, r4
80021b8: 2b00 cmp r3, #0
80021ba: bf0c ite eq
80021bc: 2301 moveq r3, #1
80021be: 2300 movne r3, #0
80021c0: b2db uxtb r3, r3
80021c2: 2b00 cmp r3, #0
80021c4: d012 beq.n 80021ec <HAL_ADC_Init+0x184>
/* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
/* HAL_ADCEx_MultiModeConfigChannel() ) */
/* - internal measurement paths: Vbat, temperature sensor, Vref */
/* (set into HAL_ADC_ConfigChannel() or */
/* HAL_ADCEx_InjectedConfigChannel() ) */
LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
80021c6: 687b ldr r3, [r7, #4]
80021c8: 681b ldr r3, [r3, #0]
80021ca: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
80021ce: d004 beq.n 80021da <HAL_ADC_Init+0x172>
80021d0: 687b ldr r3, [r7, #4]
80021d2: 681b ldr r3, [r3, #0]
80021d4: 4a5f ldr r2, [pc, #380] @ (8002354 <HAL_ADC_Init+0x2ec>)
80021d6: 4293 cmp r3, r2
80021d8: d101 bne.n 80021de <HAL_ADC_Init+0x176>
80021da: 4a62 ldr r2, [pc, #392] @ (8002364 <HAL_ADC_Init+0x2fc>)
80021dc: e000 b.n 80021e0 <HAL_ADC_Init+0x178>
80021de: 4a62 ldr r2, [pc, #392] @ (8002368 <HAL_ADC_Init+0x300>)
80021e0: 687b ldr r3, [r7, #4]
80021e2: 685b ldr r3, [r3, #4]
80021e4: 4619 mov r1, r3
80021e6: 4610 mov r0, r2
80021e8: f7ff fcfa bl 8001be0 <LL_ADC_SetCommonClock>
/* - external trigger polarity Init.ExternalTrigConvEdge */
/* - continuous conversion mode Init.ContinuousConvMode */
/* - overrun Init.Overrun */
/* - discontinuous mode Init.DiscontinuousConvMode */
/* - discontinuous mode channel count Init.NbrOfDiscConversion */
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80021ec: 687b ldr r3, [r7, #4]
80021ee: 7f5b ldrb r3, [r3, #29]
80021f0: 035a lsls r2, r3, #13
hadc->Init.Overrun |
80021f2: 687b ldr r3, [r7, #4]
80021f4: 6bdb ldr r3, [r3, #60] @ 0x3c
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
80021f6: 431a orrs r2, r3
hadc->Init.DataAlign |
80021f8: 687b ldr r3, [r7, #4]
80021fa: 68db ldr r3, [r3, #12]
hadc->Init.Overrun |
80021fc: 431a orrs r2, r3
hadc->Init.Resolution |
80021fe: 687b ldr r3, [r7, #4]
8002200: 689b ldr r3, [r3, #8]
hadc->Init.DataAlign |
8002202: 431a orrs r2, r3
ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
8002204: 687b ldr r3, [r7, #4]
8002206: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
800220a: 041b lsls r3, r3, #16
tmp_cfgr = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
800220c: 4313 orrs r3, r2
800220e: 61bb str r3, [r7, #24]
if (hadc->Init.DiscontinuousConvMode == ENABLE)
8002210: 687b ldr r3, [r7, #4]
8002212: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
8002216: 2b01 cmp r3, #1
8002218: d106 bne.n 8002228 <HAL_ADC_Init+0x1c0>
{
tmp_cfgr |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
800221a: 687b ldr r3, [r7, #4]
800221c: 6a9b ldr r3, [r3, #40] @ 0x28
800221e: 3b01 subs r3, #1
8002220: 045b lsls r3, r3, #17
8002222: 69ba ldr r2, [r7, #24]
8002224: 4313 orrs r3, r2
8002226: 61bb str r3, [r7, #24]
/* Enable external trigger if trigger selection is different of software */
/* start. */
/* Note: This configuration keeps the hardware feature of parameter */
/* ExternalTrigConvEdge "trigger edge none" equivalent to */
/* software start. */
if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
8002228: 687b ldr r3, [r7, #4]
800222a: 6adb ldr r3, [r3, #44] @ 0x2c
800222c: 2b00 cmp r3, #0
800222e: d009 beq.n 8002244 <HAL_ADC_Init+0x1dc>
{
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
8002230: 687b ldr r3, [r7, #4]
8002232: 6adb ldr r3, [r3, #44] @ 0x2c
8002234: f403 7278 and.w r2, r3, #992 @ 0x3e0
| hadc->Init.ExternalTrigConvEdge
8002238: 687b ldr r3, [r7, #4]
800223a: 6b1b ldr r3, [r3, #48] @ 0x30
800223c: 4313 orrs r3, r2
tmp_cfgr |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
800223e: 69ba ldr r2, [r7, #24]
8002240: 4313 orrs r3, r2
8002242: 61bb str r3, [r7, #24]
);
}
/* Update Configuration Register CFGR */
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmp_cfgr);
8002244: 687b ldr r3, [r7, #4]
8002246: 681b ldr r3, [r3, #0]
8002248: 68da ldr r2, [r3, #12]
800224a: 4b48 ldr r3, [pc, #288] @ (800236c <HAL_ADC_Init+0x304>)
800224c: 4013 ands r3, r2
800224e: 687a ldr r2, [r7, #4]
8002250: 6812 ldr r2, [r2, #0]
8002252: 69b9 ldr r1, [r7, #24]
8002254: 430b orrs r3, r1
8002256: 60d3 str r3, [r2, #12]
/* Configuration of sampling mode */
MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
8002258: 687b ldr r3, [r7, #4]
800225a: 681b ldr r3, [r3, #0]
800225c: 691b ldr r3, [r3, #16]
800225e: f023 6140 bic.w r1, r3, #201326592 @ 0xc000000
8002262: 687b ldr r3, [r7, #4]
8002264: 6b5a ldr r2, [r3, #52] @ 0x34
8002266: 687b ldr r3, [r7, #4]
8002268: 681b ldr r3, [r3, #0]
800226a: 430a orrs r2, r1
800226c: 611a str r2, [r3, #16]
/* conversion on going on regular and injected groups: */
/* - Gain Compensation Init.GainCompensation */
/* - DMA continuous request Init.DMAContinuousRequests */
/* - LowPowerAutoWait feature Init.LowPowerAutoWait */
/* - Oversampling parameters Init.Oversampling */
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
800226e: 687b ldr r3, [r7, #4]
8002270: 681b ldr r3, [r3, #0]
8002272: 4618 mov r0, r3
8002274: f7ff fee5 bl 8002042 <LL_ADC_INJ_IsConversionOngoing>
8002278: 6138 str r0, [r7, #16]
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
800227a: 697b ldr r3, [r7, #20]
800227c: 2b00 cmp r3, #0
800227e: d17f bne.n 8002380 <HAL_ADC_Init+0x318>
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
8002280: 693b ldr r3, [r7, #16]
8002282: 2b00 cmp r3, #0
8002284: d17c bne.n 8002380 <HAL_ADC_Init+0x318>
)
{
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
8002286: 687b ldr r3, [r7, #4]
8002288: 7f1b ldrb r3, [r3, #28]
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
800228a: 039a lsls r2, r3, #14
ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
800228c: 687b ldr r3, [r7, #4]
800228e: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
8002292: 005b lsls r3, r3, #1
tmp_cfgr = (ADC_CFGR_DFSDM(hadc) |
8002294: 4313 orrs r3, r2
8002296: 61bb str r3, [r7, #24]
MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmp_cfgr);
8002298: 687b ldr r3, [r7, #4]
800229a: 681b ldr r3, [r3, #0]
800229c: 68db ldr r3, [r3, #12]
800229e: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80022a2: f023 0302 bic.w r3, r3, #2
80022a6: 687a ldr r2, [r7, #4]
80022a8: 6812 ldr r2, [r2, #0]
80022aa: 69b9 ldr r1, [r7, #24]
80022ac: 430b orrs r3, r1
80022ae: 60d3 str r3, [r2, #12]
if (hadc->Init.GainCompensation != 0UL)
80022b0: 687b ldr r3, [r7, #4]
80022b2: 691b ldr r3, [r3, #16]
80022b4: 2b00 cmp r3, #0
80022b6: d017 beq.n 80022e8 <HAL_ADC_Init+0x280>
{
SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
80022b8: 687b ldr r3, [r7, #4]
80022ba: 681b ldr r3, [r3, #0]
80022bc: 691a ldr r2, [r3, #16]
80022be: 687b ldr r3, [r7, #4]
80022c0: 681b ldr r3, [r3, #0]
80022c2: f442 3280 orr.w r2, r2, #65536 @ 0x10000
80022c6: 611a str r2, [r3, #16]
MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
80022c8: 687b ldr r3, [r7, #4]
80022ca: 681b ldr r3, [r3, #0]
80022cc: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0
80022d0: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
80022d4: f023 033f bic.w r3, r3, #63 @ 0x3f
80022d8: 687a ldr r2, [r7, #4]
80022da: 6911 ldr r1, [r2, #16]
80022dc: 687a ldr r2, [r7, #4]
80022de: 6812 ldr r2, [r2, #0]
80022e0: 430b orrs r3, r1
80022e2: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
80022e6: e013 b.n 8002310 <HAL_ADC_Init+0x2a8>
}
else
{
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
80022e8: 687b ldr r3, [r7, #4]
80022ea: 681b ldr r3, [r3, #0]
80022ec: 691a ldr r2, [r3, #16]
80022ee: 687b ldr r3, [r7, #4]
80022f0: 681b ldr r3, [r3, #0]
80022f2: f422 3280 bic.w r2, r2, #65536 @ 0x10000
80022f6: 611a str r2, [r3, #16]
MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
80022f8: 687b ldr r3, [r7, #4]
80022fa: 681b ldr r3, [r3, #0]
80022fc: f8d3 30c0 ldr.w r3, [r3, #192] @ 0xc0
8002300: 687a ldr r2, [r7, #4]
8002302: 6812 ldr r2, [r2, #0]
8002304: f423 537f bic.w r3, r3, #16320 @ 0x3fc0
8002308: f023 033f bic.w r3, r3, #63 @ 0x3f
800230c: f8c2 30c0 str.w r3, [r2, #192] @ 0xc0
}
if (hadc->Init.OversamplingMode == ENABLE)
8002310: 687b ldr r3, [r7, #4]
8002312: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
8002316: 2b01 cmp r3, #1
8002318: d12a bne.n 8002370 <HAL_ADC_Init+0x308>
/* Configuration of Oversampler: */
/* - Oversampling Ratio */
/* - Right bit shift */
/* - Triggered mode */
/* - Oversampling mode (continued/resumed) */
MODIFY_REG(hadc->Instance->CFGR2,
800231a: 687b ldr r3, [r7, #4]
800231c: 681b ldr r3, [r3, #0]
800231e: 691b ldr r3, [r3, #16]
8002320: f423 63ff bic.w r3, r3, #2040 @ 0x7f8
8002324: f023 0304 bic.w r3, r3, #4
8002328: 687a ldr r2, [r7, #4]
800232a: 6c51 ldr r1, [r2, #68] @ 0x44
800232c: 687a ldr r2, [r7, #4]
800232e: 6c92 ldr r2, [r2, #72] @ 0x48
8002330: 4311 orrs r1, r2
8002332: 687a ldr r2, [r7, #4]
8002334: 6cd2 ldr r2, [r2, #76] @ 0x4c
8002336: 4311 orrs r1, r2
8002338: 687a ldr r2, [r7, #4]
800233a: 6d12 ldr r2, [r2, #80] @ 0x50
800233c: 430a orrs r2, r1
800233e: 431a orrs r2, r3
8002340: 687b ldr r3, [r7, #4]
8002342: 681b ldr r3, [r3, #0]
8002344: f042 0201 orr.w r2, r2, #1
8002348: 611a str r2, [r3, #16]
800234a: e019 b.n 8002380 <HAL_ADC_Init+0x318>
800234c: 20000000 .word 0x20000000
8002350: 053e2d63 .word 0x053e2d63
8002354: 50000100 .word 0x50000100
8002358: 50000400 .word 0x50000400
800235c: 50000500 .word 0x50000500
8002360: 50000600 .word 0x50000600
8002364: 50000300 .word 0x50000300
8002368: 50000700 .word 0x50000700
800236c: fff04007 .word 0xfff04007
);
}
else
{
/* Disable ADC oversampling scope on ADC group regular */
CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
8002370: 687b ldr r3, [r7, #4]
8002372: 681b ldr r3, [r3, #0]
8002374: 691a ldr r2, [r3, #16]
8002376: 687b ldr r3, [r7, #4]
8002378: 681b ldr r3, [r3, #0]
800237a: f022 0201 bic.w r2, r2, #1
800237e: 611a str r2, [r3, #16]
/* Note: Scan mode is not present by hardware on this device, but */
/* emulated by software for alignment over all STM32 devices. */
/* - if scan mode is enabled, regular channels sequence length is set to */
/* parameter "NbrOfConversion". */
if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
8002380: 687b ldr r3, [r7, #4]
8002382: 695b ldr r3, [r3, #20]
8002384: 2b01 cmp r3, #1
8002386: d10c bne.n 80023a2 <HAL_ADC_Init+0x33a>
{
/* Set number of ranks in regular group sequencer */
MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
8002388: 687b ldr r3, [r7, #4]
800238a: 681b ldr r3, [r3, #0]
800238c: 6b1b ldr r3, [r3, #48] @ 0x30
800238e: f023 010f bic.w r1, r3, #15
8002392: 687b ldr r3, [r7, #4]
8002394: 6a1b ldr r3, [r3, #32]
8002396: 1e5a subs r2, r3, #1
8002398: 687b ldr r3, [r7, #4]
800239a: 681b ldr r3, [r3, #0]
800239c: 430a orrs r2, r1
800239e: 631a str r2, [r3, #48] @ 0x30
80023a0: e007 b.n 80023b2 <HAL_ADC_Init+0x34a>
}
else
{
CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
80023a2: 687b ldr r3, [r7, #4]
80023a4: 681b ldr r3, [r3, #0]
80023a6: 6b1a ldr r2, [r3, #48] @ 0x30
80023a8: 687b ldr r3, [r7, #4]
80023aa: 681b ldr r3, [r3, #0]
80023ac: f022 020f bic.w r2, r2, #15
80023b0: 631a str r2, [r3, #48] @ 0x30
}
/* Initialize the ADC state */
/* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
80023b2: 687b ldr r3, [r7, #4]
80023b4: 6ddb ldr r3, [r3, #92] @ 0x5c
80023b6: f023 0303 bic.w r3, r3, #3
80023ba: f043 0201 orr.w r2, r3, #1
80023be: 687b ldr r3, [r7, #4]
80023c0: 65da str r2, [r3, #92] @ 0x5c
80023c2: e007 b.n 80023d4 <HAL_ADC_Init+0x36c>
}
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
80023c4: 687b ldr r3, [r7, #4]
80023c6: 6ddb ldr r3, [r3, #92] @ 0x5c
80023c8: f043 0210 orr.w r2, r3, #16
80023cc: 687b ldr r3, [r7, #4]
80023ce: 65da str r2, [r3, #92] @ 0x5c
tmp_hal_status = HAL_ERROR;
80023d0: 2301 movs r3, #1
80023d2: 77fb strb r3, [r7, #31]
}
/* Return function status */
return tmp_hal_status;
80023d4: 7ffb ldrb r3, [r7, #31]
}
80023d6: 4618 mov r0, r3
80023d8: 3724 adds r7, #36 @ 0x24
80023da: 46bd mov sp, r7
80023dc: bd90 pop {r4, r7, pc}
80023de: bf00 nop
080023e0 <HAL_ADC_Start_DMA>:
* @param pData Destination Buffer address.
* @param Length Number of data to be transferred from ADC peripheral to memory
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
{
80023e0: b580 push {r7, lr}
80023e2: b086 sub sp, #24
80023e4: af00 add r7, sp, #0
80023e6: 60f8 str r0, [r7, #12]
80023e8: 60b9 str r1, [r7, #8]
80023ea: 607a str r2, [r7, #4]
HAL_StatusTypeDef tmp_hal_status;
#if defined(ADC_MULTIMODE_SUPPORT)
uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
80023ec: 68fb ldr r3, [r7, #12]
80023ee: 681b ldr r3, [r3, #0]
80023f0: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
80023f4: d004 beq.n 8002400 <HAL_ADC_Start_DMA+0x20>
80023f6: 68fb ldr r3, [r7, #12]
80023f8: 681b ldr r3, [r3, #0]
80023fa: 4a5a ldr r2, [pc, #360] @ (8002564 <HAL_ADC_Start_DMA+0x184>)
80023fc: 4293 cmp r3, r2
80023fe: d101 bne.n 8002404 <HAL_ADC_Start_DMA+0x24>
8002400: 4b59 ldr r3, [pc, #356] @ (8002568 <HAL_ADC_Start_DMA+0x188>)
8002402: e000 b.n 8002406 <HAL_ADC_Start_DMA+0x26>
8002404: 4b59 ldr r3, [pc, #356] @ (800256c <HAL_ADC_Start_DMA+0x18c>)
8002406: 4618 mov r0, r3
8002408: f7ff fd4a bl 8001ea0 <LL_ADC_GetMultimode>
800240c: 6138 str r0, [r7, #16]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
/* Perform ADC enable and conversion start if no conversion is on going */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
800240e: 68fb ldr r3, [r7, #12]
8002410: 681b ldr r3, [r3, #0]
8002412: 4618 mov r0, r3
8002414: f7ff fe02 bl 800201c <LL_ADC_REG_IsConversionOngoing>
8002418: 4603 mov r3, r0
800241a: 2b00 cmp r3, #0
800241c: f040 809b bne.w 8002556 <HAL_ADC_Start_DMA+0x176>
{
/* Process locked */
__HAL_LOCK(hadc);
8002420: 68fb ldr r3, [r7, #12]
8002422: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
8002426: 2b01 cmp r3, #1
8002428: d101 bne.n 800242e <HAL_ADC_Start_DMA+0x4e>
800242a: 2302 movs r3, #2
800242c: e096 b.n 800255c <HAL_ADC_Start_DMA+0x17c>
800242e: 68fb ldr r3, [r7, #12]
8002430: 2201 movs r2, #1
8002432: f883 2058 strb.w r2, [r3, #88] @ 0x58
#if defined(ADC_MULTIMODE_SUPPORT)
/* Ensure that multimode regular conversions are not enabled. */
/* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
if ((ADC_IS_INDEPENDENT(hadc) != RESET)
8002436: 68fb ldr r3, [r7, #12]
8002438: 681b ldr r3, [r3, #0]
800243a: 4a4d ldr r2, [pc, #308] @ (8002570 <HAL_ADC_Start_DMA+0x190>)
800243c: 4293 cmp r3, r2
800243e: d008 beq.n 8002452 <HAL_ADC_Start_DMA+0x72>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
8002440: 693b ldr r3, [r7, #16]
8002442: 2b00 cmp r3, #0
8002444: d005 beq.n 8002452 <HAL_ADC_Start_DMA+0x72>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
8002446: 693b ldr r3, [r7, #16]
8002448: 2b05 cmp r3, #5
800244a: d002 beq.n 8002452 <HAL_ADC_Start_DMA+0x72>
|| (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
800244c: 693b ldr r3, [r7, #16]
800244e: 2b09 cmp r3, #9
8002450: d17a bne.n 8002548 <HAL_ADC_Start_DMA+0x168>
)
#endif /* ADC_MULTIMODE_SUPPORT */
{
/* Enable the ADC peripheral */
tmp_hal_status = ADC_Enable(hadc);
8002452: 68f8 ldr r0, [r7, #12]
8002454: f000 fcf6 bl 8002e44 <ADC_Enable>
8002458: 4603 mov r3, r0
800245a: 75fb strb r3, [r7, #23]
/* Start conversion if ADC is effectively enabled */
if (tmp_hal_status == HAL_OK)
800245c: 7dfb ldrb r3, [r7, #23]
800245e: 2b00 cmp r3, #0
8002460: d16d bne.n 800253e <HAL_ADC_Start_DMA+0x15e>
{
/* Set ADC state */
/* - Clear state bitfield related to regular group conversion results */
/* - Set state bitfield related to regular operation */
ADC_STATE_CLR_SET(hadc->State,
8002462: 68fb ldr r3, [r7, #12]
8002464: 6ddb ldr r3, [r3, #92] @ 0x5c
8002466: f423 6370 bic.w r3, r3, #3840 @ 0xf00
800246a: f023 0301 bic.w r3, r3, #1
800246e: f443 7280 orr.w r2, r3, #256 @ 0x100
8002472: 68fb ldr r3, [r7, #12]
8002474: 65da str r2, [r3, #92] @ 0x5c
#if defined(ADC_MULTIMODE_SUPPORT)
/* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
- if ADC instance is master or if multimode feature is not available
- if multimode setting is disabled (ADC instance slave in independent mode) */
if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
8002476: 68fb ldr r3, [r7, #12]
8002478: 681b ldr r3, [r3, #0]
800247a: 4a3a ldr r2, [pc, #232] @ (8002564 <HAL_ADC_Start_DMA+0x184>)
800247c: 4293 cmp r3, r2
800247e: d009 beq.n 8002494 <HAL_ADC_Start_DMA+0xb4>
8002480: 68fb ldr r3, [r7, #12]
8002482: 681b ldr r3, [r3, #0]
8002484: 4a3b ldr r2, [pc, #236] @ (8002574 <HAL_ADC_Start_DMA+0x194>)
8002486: 4293 cmp r3, r2
8002488: d002 beq.n 8002490 <HAL_ADC_Start_DMA+0xb0>
800248a: 68fb ldr r3, [r7, #12]
800248c: 681b ldr r3, [r3, #0]
800248e: e003 b.n 8002498 <HAL_ADC_Start_DMA+0xb8>
8002490: 4b39 ldr r3, [pc, #228] @ (8002578 <HAL_ADC_Start_DMA+0x198>)
8002492: e001 b.n 8002498 <HAL_ADC_Start_DMA+0xb8>
8002494: f04f 43a0 mov.w r3, #1342177280 @ 0x50000000
8002498: 68fa ldr r2, [r7, #12]
800249a: 6812 ldr r2, [r2, #0]
800249c: 4293 cmp r3, r2
800249e: d002 beq.n 80024a6 <HAL_ADC_Start_DMA+0xc6>
|| (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
80024a0: 693b ldr r3, [r7, #16]
80024a2: 2b00 cmp r3, #0
80024a4: d105 bne.n 80024b2 <HAL_ADC_Start_DMA+0xd2>
)
{
CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
80024a6: 68fb ldr r3, [r7, #12]
80024a8: 6ddb ldr r3, [r3, #92] @ 0x5c
80024aa: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
80024ae: 68fb ldr r3, [r7, #12]
80024b0: 65da str r2, [r3, #92] @ 0x5c
}
#endif /* ADC_MULTIMODE_SUPPORT */
/* Check if a conversion is on going on ADC group injected */
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
80024b2: 68fb ldr r3, [r7, #12]
80024b4: 6ddb ldr r3, [r3, #92] @ 0x5c
80024b6: f403 5380 and.w r3, r3, #4096 @ 0x1000
80024ba: 2b00 cmp r3, #0
80024bc: d006 beq.n 80024cc <HAL_ADC_Start_DMA+0xec>
{
/* Reset ADC error code fields related to regular conversions only */
CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
80024be: 68fb ldr r3, [r7, #12]
80024c0: 6e1b ldr r3, [r3, #96] @ 0x60
80024c2: f023 0206 bic.w r2, r3, #6
80024c6: 68fb ldr r3, [r7, #12]
80024c8: 661a str r2, [r3, #96] @ 0x60
80024ca: e002 b.n 80024d2 <HAL_ADC_Start_DMA+0xf2>
}
else
{
/* Reset all ADC error code fields */
ADC_CLEAR_ERRORCODE(hadc);
80024cc: 68fb ldr r3, [r7, #12]
80024ce: 2200 movs r2, #0
80024d0: 661a str r2, [r3, #96] @ 0x60
}
/* Set the DMA transfer complete callback */
hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
80024d2: 68fb ldr r3, [r7, #12]
80024d4: 6d5b ldr r3, [r3, #84] @ 0x54
80024d6: 4a29 ldr r2, [pc, #164] @ (800257c <HAL_ADC_Start_DMA+0x19c>)
80024d8: 62da str r2, [r3, #44] @ 0x2c
/* Set the DMA half transfer complete callback */
hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
80024da: 68fb ldr r3, [r7, #12]
80024dc: 6d5b ldr r3, [r3, #84] @ 0x54
80024de: 4a28 ldr r2, [pc, #160] @ (8002580 <HAL_ADC_Start_DMA+0x1a0>)
80024e0: 631a str r2, [r3, #48] @ 0x30
/* Set the DMA error callback */
hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
80024e2: 68fb ldr r3, [r7, #12]
80024e4: 6d5b ldr r3, [r3, #84] @ 0x54
80024e6: 4a27 ldr r2, [pc, #156] @ (8002584 <HAL_ADC_Start_DMA+0x1a4>)
80024e8: 635a str r2, [r3, #52] @ 0x34
/* ADC start (in case of SW start): */
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC */
/* operations) */
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
80024ea: 68fb ldr r3, [r7, #12]
80024ec: 681b ldr r3, [r3, #0]
80024ee: 221c movs r2, #28
80024f0: 601a str r2, [r3, #0]
/* Process unlocked */
/* Unlock before starting ADC conversions: in case of potential */
/* interruption, to let the process to ADC IRQ Handler. */
__HAL_UNLOCK(hadc);
80024f2: 68fb ldr r3, [r7, #12]
80024f4: 2200 movs r2, #0
80024f6: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* With DMA, overrun event is always considered as an error even if
hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
ADC_IT_OVR is enabled. */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
80024fa: 68fb ldr r3, [r7, #12]
80024fc: 681b ldr r3, [r3, #0]
80024fe: 685a ldr r2, [r3, #4]
8002500: 68fb ldr r3, [r7, #12]
8002502: 681b ldr r3, [r3, #0]
8002504: f042 0210 orr.w r2, r2, #16
8002508: 605a str r2, [r3, #4]
/* Enable ADC DMA mode */
SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
800250a: 68fb ldr r3, [r7, #12]
800250c: 681b ldr r3, [r3, #0]
800250e: 68da ldr r2, [r3, #12]
8002510: 68fb ldr r3, [r7, #12]
8002512: 681b ldr r3, [r3, #0]
8002514: f042 0201 orr.w r2, r2, #1
8002518: 60da str r2, [r3, #12]
/* Start the DMA channel */
tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
800251a: 68fb ldr r3, [r7, #12]
800251c: 6d58 ldr r0, [r3, #84] @ 0x54
800251e: 68fb ldr r3, [r7, #12]
8002520: 681b ldr r3, [r3, #0]
8002522: 3340 adds r3, #64 @ 0x40
8002524: 4619 mov r1, r3
8002526: 68ba ldr r2, [r7, #8]
8002528: 687b ldr r3, [r7, #4]
800252a: f002 f803 bl 8004534 <HAL_DMA_Start_IT>
800252e: 4603 mov r3, r0
8002530: 75fb strb r3, [r7, #23]
/* Enable conversion of regular group. */
/* If software start has been selected, conversion starts immediately. */
/* If external trigger has been selected, conversion will start at next */
/* trigger event. */
/* Start ADC group regular conversion */
LL_ADC_REG_StartConversion(hadc->Instance);
8002532: 68fb ldr r3, [r7, #12]
8002534: 681b ldr r3, [r3, #0]
8002536: 4618 mov r0, r3
8002538: f7ff fd5c bl 8001ff4 <LL_ADC_REG_StartConversion>
if (tmp_hal_status == HAL_OK)
800253c: e00d b.n 800255a <HAL_ADC_Start_DMA+0x17a>
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hadc);
800253e: 68fb ldr r3, [r7, #12]
8002540: 2200 movs r2, #0
8002542: f883 2058 strb.w r2, [r3, #88] @ 0x58
if (tmp_hal_status == HAL_OK)
8002546: e008 b.n 800255a <HAL_ADC_Start_DMA+0x17a>
}
#if defined(ADC_MULTIMODE_SUPPORT)
else
{
tmp_hal_status = HAL_ERROR;
8002548: 2301 movs r3, #1
800254a: 75fb strb r3, [r7, #23]
/* Process unlocked */
__HAL_UNLOCK(hadc);
800254c: 68fb ldr r3, [r7, #12]
800254e: 2200 movs r2, #0
8002550: f883 2058 strb.w r2, [r3, #88] @ 0x58
8002554: e001 b.n 800255a <HAL_ADC_Start_DMA+0x17a>
}
#endif /* ADC_MULTIMODE_SUPPORT */
}
else
{
tmp_hal_status = HAL_BUSY;
8002556: 2302 movs r3, #2
8002558: 75fb strb r3, [r7, #23]
}
/* Return function status */
return tmp_hal_status;
800255a: 7dfb ldrb r3, [r7, #23]
}
800255c: 4618 mov r0, r3
800255e: 3718 adds r7, #24
8002560: 46bd mov sp, r7
8002562: bd80 pop {r7, pc}
8002564: 50000100 .word 0x50000100
8002568: 50000300 .word 0x50000300
800256c: 50000700 .word 0x50000700
8002570: 50000600 .word 0x50000600
8002574: 50000500 .word 0x50000500
8002578: 50000400 .word 0x50000400
800257c: 0800302f .word 0x0800302f
8002580: 08003107 .word 0x08003107
8002584: 08003123 .word 0x08003123
08002588 <HAL_ADC_ConvCpltCallback>:
* @brief Conversion complete callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
{
8002588: b480 push {r7}
800258a: b083 sub sp, #12
800258c: af00 add r7, sp, #0
800258e: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ConvCpltCallback must be implemented in the user file.
*/
}
8002590: bf00 nop
8002592: 370c adds r7, #12
8002594: 46bd mov sp, r7
8002596: f85d 7b04 ldr.w r7, [sp], #4
800259a: 4770 bx lr
0800259c <HAL_ADC_ConvHalfCpltCallback>:
* @brief Conversion DMA half-transfer callback in non-blocking mode.
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
{
800259c: b480 push {r7}
800259e: b083 sub sp, #12
80025a0: af00 add r7, sp, #0
80025a2: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
*/
}
80025a4: bf00 nop
80025a6: 370c adds r7, #12
80025a8: 46bd mov sp, r7
80025aa: f85d 7b04 ldr.w r7, [sp], #4
80025ae: 4770 bx lr
080025b0 <HAL_ADC_ErrorCallback>:
* (this function is also clearing overrun flag)
* @param hadc ADC handle
* @retval None
*/
__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
{
80025b0: b480 push {r7}
80025b2: b083 sub sp, #12
80025b4: af00 add r7, sp, #0
80025b6: 6078 str r0, [r7, #4]
UNUSED(hadc);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_ADC_ErrorCallback must be implemented in the user file.
*/
}
80025b8: bf00 nop
80025ba: 370c adds r7, #12
80025bc: 46bd mov sp, r7
80025be: f85d 7b04 ldr.w r7, [sp], #4
80025c2: 4770 bx lr
080025c4 <HAL_ADC_ConfigChannel>:
* @param hadc ADC handle
* @param pConfig Structure of ADC channel assigned to ADC group regular.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig)
{
80025c4: b580 push {r7, lr}
80025c6: b0b6 sub sp, #216 @ 0xd8
80025c8: af00 add r7, sp, #0
80025ca: 6078 str r0, [r7, #4]
80025cc: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80025ce: 2300 movs r3, #0
80025d0: f887 30d7 strb.w r3, [r7, #215] @ 0xd7
uint32_t tmpOffsetShifted;
uint32_t tmp_config_internal_channel;
__IO uint32_t wait_loop_index = 0UL;
80025d4: 2300 movs r3, #0
80025d6: 60fb str r3, [r7, #12]
{
assert_param(IS_ADC_DIFF_CHANNEL(hadc, pConfig->Channel));
}
/* Process locked */
__HAL_LOCK(hadc);
80025d8: 687b ldr r3, [r7, #4]
80025da: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
80025de: 2b01 cmp r3, #1
80025e0: d102 bne.n 80025e8 <HAL_ADC_ConfigChannel+0x24>
80025e2: 2302 movs r3, #2
80025e4: f000 bc13 b.w 8002e0e <HAL_ADC_ConfigChannel+0x84a>
80025e8: 687b ldr r3, [r7, #4]
80025ea: 2201 movs r2, #1
80025ec: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel number */
/* - Channel rank */
if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
80025f0: 687b ldr r3, [r7, #4]
80025f2: 681b ldr r3, [r3, #0]
80025f4: 4618 mov r0, r3
80025f6: f7ff fd11 bl 800201c <LL_ADC_REG_IsConversionOngoing>
80025fa: 4603 mov r3, r0
80025fc: 2b00 cmp r3, #0
80025fe: f040 83f3 bne.w 8002de8 <HAL_ADC_ConfigChannel+0x824>
{
/* Set ADC group regular sequence: channel on the selected scan sequence rank */
LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
8002602: 687b ldr r3, [r7, #4]
8002604: 6818 ldr r0, [r3, #0]
8002606: 683b ldr r3, [r7, #0]
8002608: 6859 ldr r1, [r3, #4]
800260a: 683b ldr r3, [r7, #0]
800260c: 681b ldr r3, [r3, #0]
800260e: 461a mov r2, r3
8002610: f7ff fbcb bl 8001daa <LL_ADC_REG_SetSequencerRanks>
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Channel sampling time */
/* - Channel offset */
tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
8002614: 687b ldr r3, [r7, #4]
8002616: 681b ldr r3, [r3, #0]
8002618: 4618 mov r0, r3
800261a: f7ff fcff bl 800201c <LL_ADC_REG_IsConversionOngoing>
800261e: f8c7 00d0 str.w r0, [r7, #208] @ 0xd0
tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
8002622: 687b ldr r3, [r7, #4]
8002624: 681b ldr r3, [r3, #0]
8002626: 4618 mov r0, r3
8002628: f7ff fd0b bl 8002042 <LL_ADC_INJ_IsConversionOngoing>
800262c: f8c7 00cc str.w r0, [r7, #204] @ 0xcc
if ((tmp_adc_is_conversion_on_going_regular == 0UL)
8002630: f8d7 30d0 ldr.w r3, [r7, #208] @ 0xd0
8002634: 2b00 cmp r3, #0
8002636: f040 81d9 bne.w 80029ec <HAL_ADC_ConfigChannel+0x428>
&& (tmp_adc_is_conversion_on_going_injected == 0UL)
800263a: f8d7 30cc ldr.w r3, [r7, #204] @ 0xcc
800263e: 2b00 cmp r3, #0
8002640: f040 81d4 bne.w 80029ec <HAL_ADC_ConfigChannel+0x428>
)
{
/* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
if (pConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
8002644: 683b ldr r3, [r7, #0]
8002646: 689b ldr r3, [r3, #8]
8002648: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
800264c: d10f bne.n 800266e <HAL_ADC_ConfigChannel+0xaa>
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
800264e: 687b ldr r3, [r7, #4]
8002650: 6818 ldr r0, [r3, #0]
8002652: 683b ldr r3, [r7, #0]
8002654: 681b ldr r3, [r3, #0]
8002656: 2200 movs r2, #0
8002658: 4619 mov r1, r3
800265a: f7ff fbd2 bl 8001e02 <LL_ADC_SetChannelSamplingTime>
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
800265e: 687b ldr r3, [r7, #4]
8002660: 681b ldr r3, [r3, #0]
8002662: f04f 4100 mov.w r1, #2147483648 @ 0x80000000
8002666: 4618 mov r0, r3
8002668: f7ff fb79 bl 8001d5e <LL_ADC_SetSamplingTimeCommonConfig>
800266c: e00e b.n 800268c <HAL_ADC_ConfigChannel+0xc8>
}
else
{
/* Set sampling time of the selected ADC channel */
LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
800266e: 687b ldr r3, [r7, #4]
8002670: 6818 ldr r0, [r3, #0]
8002672: 683b ldr r3, [r7, #0]
8002674: 6819 ldr r1, [r3, #0]
8002676: 683b ldr r3, [r7, #0]
8002678: 689b ldr r3, [r3, #8]
800267a: 461a mov r2, r3
800267c: f7ff fbc1 bl 8001e02 <LL_ADC_SetChannelSamplingTime>
/* Set ADC sampling time common configuration */
LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
8002680: 687b ldr r3, [r7, #4]
8002682: 681b ldr r3, [r3, #0]
8002684: 2100 movs r1, #0
8002686: 4618 mov r0, r3
8002688: f7ff fb69 bl 8001d5e <LL_ADC_SetSamplingTimeCommonConfig>
/* Configure the offset: offset enable/disable, channel, offset value */
/* Shift the offset with respect to the selected ADC resolution. */
/* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
800268c: 683b ldr r3, [r7, #0]
800268e: 695a ldr r2, [r3, #20]
8002690: 687b ldr r3, [r7, #4]
8002692: 681b ldr r3, [r3, #0]
8002694: 68db ldr r3, [r3, #12]
8002696: 08db lsrs r3, r3, #3
8002698: f003 0303 and.w r3, r3, #3
800269c: 005b lsls r3, r3, #1
800269e: fa02 f303 lsl.w r3, r2, r3
80026a2: f8c7 30c8 str.w r3, [r7, #200] @ 0xc8
if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
80026a6: 683b ldr r3, [r7, #0]
80026a8: 691b ldr r3, [r3, #16]
80026aa: 2b04 cmp r3, #4
80026ac: d022 beq.n 80026f4 <HAL_ADC_ConfigChannel+0x130>
{
/* Set ADC selected offset number */
LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted);
80026ae: 687b ldr r3, [r7, #4]
80026b0: 6818 ldr r0, [r3, #0]
80026b2: 683b ldr r3, [r7, #0]
80026b4: 6919 ldr r1, [r3, #16]
80026b6: 683b ldr r3, [r7, #0]
80026b8: 681a ldr r2, [r3, #0]
80026ba: f8d7 30c8 ldr.w r3, [r7, #200] @ 0xc8
80026be: f7ff fac3 bl 8001c48 <LL_ADC_SetOffset>
assert_param(IS_ADC_OFFSET_SIGN(pConfig->OffsetSign));
assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSaturation));
/* Set ADC selected offset sign & saturation */
LL_ADC_SetOffsetSign(hadc->Instance, pConfig->OffsetNumber, pConfig->OffsetSign);
80026c2: 687b ldr r3, [r7, #4]
80026c4: 6818 ldr r0, [r3, #0]
80026c6: 683b ldr r3, [r7, #0]
80026c8: 6919 ldr r1, [r3, #16]
80026ca: 683b ldr r3, [r7, #0]
80026cc: 699b ldr r3, [r3, #24]
80026ce: 461a mov r2, r3
80026d0: f7ff fb0f bl 8001cf2 <LL_ADC_SetOffsetSign>
LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
80026d4: 687b ldr r3, [r7, #4]
80026d6: 6818 ldr r0, [r3, #0]
80026d8: 683b ldr r3, [r7, #0]
80026da: 6919 ldr r1, [r3, #16]
(pConfig->OffsetSaturation == ENABLE) ?
80026dc: 683b ldr r3, [r7, #0]
80026de: 7f1b ldrb r3, [r3, #28]
LL_ADC_SetOffsetSaturation(hadc->Instance, pConfig->OffsetNumber,
80026e0: 2b01 cmp r3, #1
80026e2: d102 bne.n 80026ea <HAL_ADC_ConfigChannel+0x126>
80026e4: f04f 7300 mov.w r3, #33554432 @ 0x2000000
80026e8: e000 b.n 80026ec <HAL_ADC_ConfigChannel+0x128>
80026ea: 2300 movs r3, #0
80026ec: 461a mov r2, r3
80026ee: f7ff fb1b bl 8001d28 <LL_ADC_SetOffsetSaturation>
80026f2: e17b b.n 80029ec <HAL_ADC_ConfigChannel+0x428>
}
else
{
/* Scan each offset register to check if the selected channel is targeted. */
/* If this is the case, the corresponding offset number is disabled. */
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
80026f4: 687b ldr r3, [r7, #4]
80026f6: 681b ldr r3, [r3, #0]
80026f8: 2100 movs r1, #0
80026fa: 4618 mov r0, r3
80026fc: f7ff fac8 bl 8001c90 <LL_ADC_GetOffsetChannel>
8002700: 4603 mov r3, r0
8002702: f3c3 0312 ubfx r3, r3, #0, #19
8002706: 2b00 cmp r3, #0
8002708: d10a bne.n 8002720 <HAL_ADC_ConfigChannel+0x15c>
800270a: 687b ldr r3, [r7, #4]
800270c: 681b ldr r3, [r3, #0]
800270e: 2100 movs r1, #0
8002710: 4618 mov r0, r3
8002712: f7ff fabd bl 8001c90 <LL_ADC_GetOffsetChannel>
8002716: 4603 mov r3, r0
8002718: 0e9b lsrs r3, r3, #26
800271a: f003 021f and.w r2, r3, #31
800271e: e01e b.n 800275e <HAL_ADC_ConfigChannel+0x19a>
8002720: 687b ldr r3, [r7, #4]
8002722: 681b ldr r3, [r3, #0]
8002724: 2100 movs r1, #0
8002726: 4618 mov r0, r3
8002728: f7ff fab2 bl 8001c90 <LL_ADC_GetOffsetChannel>
800272c: 4603 mov r3, r0
800272e: f8c7 30bc str.w r3, [r7, #188] @ 0xbc
uint32_t result;
#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002732: f8d7 30bc ldr.w r3, [r7, #188] @ 0xbc
8002736: fa93 f3a3 rbit r3, r3
800273a: f8c7 30c0 str.w r3, [r7, #192] @ 0xc0
result |= value & 1U;
s--;
}
result <<= s; /* shift when v's highest bits are zero */
#endif
return result;
800273e: f8d7 30c0 ldr.w r3, [r7, #192] @ 0xc0
8002742: f8c7 30b8 str.w r3, [r7, #184] @ 0xb8
optimisations using the logic "value was passed to __builtin_clz, so it
is non-zero".
ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
single CLZ instruction.
*/
if (value == 0U)
8002746: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
800274a: 2b00 cmp r3, #0
800274c: d101 bne.n 8002752 <HAL_ADC_ConfigChannel+0x18e>
{
return 32U;
800274e: 2320 movs r3, #32
8002750: e004 b.n 800275c <HAL_ADC_ConfigChannel+0x198>
}
return __builtin_clz(value);
8002752: f8d7 30b8 ldr.w r3, [r7, #184] @ 0xb8
8002756: fab3 f383 clz r3, r3
800275a: b2db uxtb r3, r3
800275c: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
800275e: 683b ldr r3, [r7, #0]
8002760: 681b ldr r3, [r3, #0]
8002762: f3c3 0312 ubfx r3, r3, #0, #19
8002766: 2b00 cmp r3, #0
8002768: d105 bne.n 8002776 <HAL_ADC_ConfigChannel+0x1b2>
800276a: 683b ldr r3, [r7, #0]
800276c: 681b ldr r3, [r3, #0]
800276e: 0e9b lsrs r3, r3, #26
8002770: f003 031f and.w r3, r3, #31
8002774: e018 b.n 80027a8 <HAL_ADC_ConfigChannel+0x1e4>
8002776: 683b ldr r3, [r7, #0]
8002778: 681b ldr r3, [r3, #0]
800277a: f8c7 30b0 str.w r3, [r7, #176] @ 0xb0
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800277e: f8d7 30b0 ldr.w r3, [r7, #176] @ 0xb0
8002782: fa93 f3a3 rbit r3, r3
8002786: f8c7 30ac str.w r3, [r7, #172] @ 0xac
return result;
800278a: f8d7 30ac ldr.w r3, [r7, #172] @ 0xac
800278e: f8c7 30b4 str.w r3, [r7, #180] @ 0xb4
if (value == 0U)
8002792: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
8002796: 2b00 cmp r3, #0
8002798: d101 bne.n 800279e <HAL_ADC_ConfigChannel+0x1da>
return 32U;
800279a: 2320 movs r3, #32
800279c: e004 b.n 80027a8 <HAL_ADC_ConfigChannel+0x1e4>
return __builtin_clz(value);
800279e: f8d7 30b4 ldr.w r3, [r7, #180] @ 0xb4
80027a2: fab3 f383 clz r3, r3
80027a6: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
80027a8: 429a cmp r2, r3
80027aa: d106 bne.n 80027ba <HAL_ADC_ConfigChannel+0x1f6>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
80027ac: 687b ldr r3, [r7, #4]
80027ae: 681b ldr r3, [r3, #0]
80027b0: 2200 movs r2, #0
80027b2: 2100 movs r1, #0
80027b4: 4618 mov r0, r3
80027b6: f7ff fa81 bl 8001cbc <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
80027ba: 687b ldr r3, [r7, #4]
80027bc: 681b ldr r3, [r3, #0]
80027be: 2101 movs r1, #1
80027c0: 4618 mov r0, r3
80027c2: f7ff fa65 bl 8001c90 <LL_ADC_GetOffsetChannel>
80027c6: 4603 mov r3, r0
80027c8: f3c3 0312 ubfx r3, r3, #0, #19
80027cc: 2b00 cmp r3, #0
80027ce: d10a bne.n 80027e6 <HAL_ADC_ConfigChannel+0x222>
80027d0: 687b ldr r3, [r7, #4]
80027d2: 681b ldr r3, [r3, #0]
80027d4: 2101 movs r1, #1
80027d6: 4618 mov r0, r3
80027d8: f7ff fa5a bl 8001c90 <LL_ADC_GetOffsetChannel>
80027dc: 4603 mov r3, r0
80027de: 0e9b lsrs r3, r3, #26
80027e0: f003 021f and.w r2, r3, #31
80027e4: e01e b.n 8002824 <HAL_ADC_ConfigChannel+0x260>
80027e6: 687b ldr r3, [r7, #4]
80027e8: 681b ldr r3, [r3, #0]
80027ea: 2101 movs r1, #1
80027ec: 4618 mov r0, r3
80027ee: f7ff fa4f bl 8001c90 <LL_ADC_GetOffsetChannel>
80027f2: 4603 mov r3, r0
80027f4: f8c7 30a4 str.w r3, [r7, #164] @ 0xa4
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80027f8: f8d7 30a4 ldr.w r3, [r7, #164] @ 0xa4
80027fc: fa93 f3a3 rbit r3, r3
8002800: f8c7 30a0 str.w r3, [r7, #160] @ 0xa0
return result;
8002804: f8d7 30a0 ldr.w r3, [r7, #160] @ 0xa0
8002808: f8c7 30a8 str.w r3, [r7, #168] @ 0xa8
if (value == 0U)
800280c: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
8002810: 2b00 cmp r3, #0
8002812: d101 bne.n 8002818 <HAL_ADC_ConfigChannel+0x254>
return 32U;
8002814: 2320 movs r3, #32
8002816: e004 b.n 8002822 <HAL_ADC_ConfigChannel+0x25e>
return __builtin_clz(value);
8002818: f8d7 30a8 ldr.w r3, [r7, #168] @ 0xa8
800281c: fab3 f383 clz r3, r3
8002820: b2db uxtb r3, r3
8002822: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
8002824: 683b ldr r3, [r7, #0]
8002826: 681b ldr r3, [r3, #0]
8002828: f3c3 0312 ubfx r3, r3, #0, #19
800282c: 2b00 cmp r3, #0
800282e: d105 bne.n 800283c <HAL_ADC_ConfigChannel+0x278>
8002830: 683b ldr r3, [r7, #0]
8002832: 681b ldr r3, [r3, #0]
8002834: 0e9b lsrs r3, r3, #26
8002836: f003 031f and.w r3, r3, #31
800283a: e018 b.n 800286e <HAL_ADC_ConfigChannel+0x2aa>
800283c: 683b ldr r3, [r7, #0]
800283e: 681b ldr r3, [r3, #0]
8002840: f8c7 3098 str.w r3, [r7, #152] @ 0x98
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002844: f8d7 3098 ldr.w r3, [r7, #152] @ 0x98
8002848: fa93 f3a3 rbit r3, r3
800284c: f8c7 3094 str.w r3, [r7, #148] @ 0x94
return result;
8002850: f8d7 3094 ldr.w r3, [r7, #148] @ 0x94
8002854: f8c7 309c str.w r3, [r7, #156] @ 0x9c
if (value == 0U)
8002858: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
800285c: 2b00 cmp r3, #0
800285e: d101 bne.n 8002864 <HAL_ADC_ConfigChannel+0x2a0>
return 32U;
8002860: 2320 movs r3, #32
8002862: e004 b.n 800286e <HAL_ADC_ConfigChannel+0x2aa>
return __builtin_clz(value);
8002864: f8d7 309c ldr.w r3, [r7, #156] @ 0x9c
8002868: fab3 f383 clz r3, r3
800286c: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
800286e: 429a cmp r2, r3
8002870: d106 bne.n 8002880 <HAL_ADC_ConfigChannel+0x2bc>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
8002872: 687b ldr r3, [r7, #4]
8002874: 681b ldr r3, [r3, #0]
8002876: 2200 movs r2, #0
8002878: 2101 movs r1, #1
800287a: 4618 mov r0, r3
800287c: f7ff fa1e bl 8001cbc <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
8002880: 687b ldr r3, [r7, #4]
8002882: 681b ldr r3, [r3, #0]
8002884: 2102 movs r1, #2
8002886: 4618 mov r0, r3
8002888: f7ff fa02 bl 8001c90 <LL_ADC_GetOffsetChannel>
800288c: 4603 mov r3, r0
800288e: f3c3 0312 ubfx r3, r3, #0, #19
8002892: 2b00 cmp r3, #0
8002894: d10a bne.n 80028ac <HAL_ADC_ConfigChannel+0x2e8>
8002896: 687b ldr r3, [r7, #4]
8002898: 681b ldr r3, [r3, #0]
800289a: 2102 movs r1, #2
800289c: 4618 mov r0, r3
800289e: f7ff f9f7 bl 8001c90 <LL_ADC_GetOffsetChannel>
80028a2: 4603 mov r3, r0
80028a4: 0e9b lsrs r3, r3, #26
80028a6: f003 021f and.w r2, r3, #31
80028aa: e01e b.n 80028ea <HAL_ADC_ConfigChannel+0x326>
80028ac: 687b ldr r3, [r7, #4]
80028ae: 681b ldr r3, [r3, #0]
80028b0: 2102 movs r1, #2
80028b2: 4618 mov r0, r3
80028b4: f7ff f9ec bl 8001c90 <LL_ADC_GetOffsetChannel>
80028b8: 4603 mov r3, r0
80028ba: f8c7 308c str.w r3, [r7, #140] @ 0x8c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80028be: f8d7 308c ldr.w r3, [r7, #140] @ 0x8c
80028c2: fa93 f3a3 rbit r3, r3
80028c6: f8c7 3088 str.w r3, [r7, #136] @ 0x88
return result;
80028ca: f8d7 3088 ldr.w r3, [r7, #136] @ 0x88
80028ce: f8c7 3090 str.w r3, [r7, #144] @ 0x90
if (value == 0U)
80028d2: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
80028d6: 2b00 cmp r3, #0
80028d8: d101 bne.n 80028de <HAL_ADC_ConfigChannel+0x31a>
return 32U;
80028da: 2320 movs r3, #32
80028dc: e004 b.n 80028e8 <HAL_ADC_ConfigChannel+0x324>
return __builtin_clz(value);
80028de: f8d7 3090 ldr.w r3, [r7, #144] @ 0x90
80028e2: fab3 f383 clz r3, r3
80028e6: b2db uxtb r3, r3
80028e8: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
80028ea: 683b ldr r3, [r7, #0]
80028ec: 681b ldr r3, [r3, #0]
80028ee: f3c3 0312 ubfx r3, r3, #0, #19
80028f2: 2b00 cmp r3, #0
80028f4: d105 bne.n 8002902 <HAL_ADC_ConfigChannel+0x33e>
80028f6: 683b ldr r3, [r7, #0]
80028f8: 681b ldr r3, [r3, #0]
80028fa: 0e9b lsrs r3, r3, #26
80028fc: f003 031f and.w r3, r3, #31
8002900: e016 b.n 8002930 <HAL_ADC_ConfigChannel+0x36c>
8002902: 683b ldr r3, [r7, #0]
8002904: 681b ldr r3, [r3, #0]
8002906: f8c7 3080 str.w r3, [r7, #128] @ 0x80
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800290a: f8d7 3080 ldr.w r3, [r7, #128] @ 0x80
800290e: fa93 f3a3 rbit r3, r3
8002912: 67fb str r3, [r7, #124] @ 0x7c
return result;
8002914: 6ffb ldr r3, [r7, #124] @ 0x7c
8002916: f8c7 3084 str.w r3, [r7, #132] @ 0x84
if (value == 0U)
800291a: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800291e: 2b00 cmp r3, #0
8002920: d101 bne.n 8002926 <HAL_ADC_ConfigChannel+0x362>
return 32U;
8002922: 2320 movs r3, #32
8002924: e004 b.n 8002930 <HAL_ADC_ConfigChannel+0x36c>
return __builtin_clz(value);
8002926: f8d7 3084 ldr.w r3, [r7, #132] @ 0x84
800292a: fab3 f383 clz r3, r3
800292e: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
8002930: 429a cmp r2, r3
8002932: d106 bne.n 8002942 <HAL_ADC_ConfigChannel+0x37e>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
8002934: 687b ldr r3, [r7, #4]
8002936: 681b ldr r3, [r3, #0]
8002938: 2200 movs r2, #0
800293a: 2102 movs r1, #2
800293c: 4618 mov r0, r3
800293e: f7ff f9bd bl 8001cbc <LL_ADC_SetOffsetState>
}
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
8002942: 687b ldr r3, [r7, #4]
8002944: 681b ldr r3, [r3, #0]
8002946: 2103 movs r1, #3
8002948: 4618 mov r0, r3
800294a: f7ff f9a1 bl 8001c90 <LL_ADC_GetOffsetChannel>
800294e: 4603 mov r3, r0
8002950: f3c3 0312 ubfx r3, r3, #0, #19
8002954: 2b00 cmp r3, #0
8002956: d10a bne.n 800296e <HAL_ADC_ConfigChannel+0x3aa>
8002958: 687b ldr r3, [r7, #4]
800295a: 681b ldr r3, [r3, #0]
800295c: 2103 movs r1, #3
800295e: 4618 mov r0, r3
8002960: f7ff f996 bl 8001c90 <LL_ADC_GetOffsetChannel>
8002964: 4603 mov r3, r0
8002966: 0e9b lsrs r3, r3, #26
8002968: f003 021f and.w r2, r3, #31
800296c: e017 b.n 800299e <HAL_ADC_ConfigChannel+0x3da>
800296e: 687b ldr r3, [r7, #4]
8002970: 681b ldr r3, [r3, #0]
8002972: 2103 movs r1, #3
8002974: 4618 mov r0, r3
8002976: f7ff f98b bl 8001c90 <LL_ADC_GetOffsetChannel>
800297a: 4603 mov r3, r0
800297c: 677b str r3, [r7, #116] @ 0x74
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
800297e: 6f7b ldr r3, [r7, #116] @ 0x74
8002980: fa93 f3a3 rbit r3, r3
8002984: 673b str r3, [r7, #112] @ 0x70
return result;
8002986: 6f3b ldr r3, [r7, #112] @ 0x70
8002988: 67bb str r3, [r7, #120] @ 0x78
if (value == 0U)
800298a: 6fbb ldr r3, [r7, #120] @ 0x78
800298c: 2b00 cmp r3, #0
800298e: d101 bne.n 8002994 <HAL_ADC_ConfigChannel+0x3d0>
return 32U;
8002990: 2320 movs r3, #32
8002992: e003 b.n 800299c <HAL_ADC_ConfigChannel+0x3d8>
return __builtin_clz(value);
8002994: 6fbb ldr r3, [r7, #120] @ 0x78
8002996: fab3 f383 clz r3, r3
800299a: b2db uxtb r3, r3
800299c: 461a mov r2, r3
== __LL_ADC_CHANNEL_TO_DECIMAL_NB(pConfig->Channel))
800299e: 683b ldr r3, [r7, #0]
80029a0: 681b ldr r3, [r3, #0]
80029a2: f3c3 0312 ubfx r3, r3, #0, #19
80029a6: 2b00 cmp r3, #0
80029a8: d105 bne.n 80029b6 <HAL_ADC_ConfigChannel+0x3f2>
80029aa: 683b ldr r3, [r7, #0]
80029ac: 681b ldr r3, [r3, #0]
80029ae: 0e9b lsrs r3, r3, #26
80029b0: f003 031f and.w r3, r3, #31
80029b4: e011 b.n 80029da <HAL_ADC_ConfigChannel+0x416>
80029b6: 683b ldr r3, [r7, #0]
80029b8: 681b ldr r3, [r3, #0]
80029ba: 66bb str r3, [r7, #104] @ 0x68
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
80029bc: 6ebb ldr r3, [r7, #104] @ 0x68
80029be: fa93 f3a3 rbit r3, r3
80029c2: 667b str r3, [r7, #100] @ 0x64
return result;
80029c4: 6e7b ldr r3, [r7, #100] @ 0x64
80029c6: 66fb str r3, [r7, #108] @ 0x6c
if (value == 0U)
80029c8: 6efb ldr r3, [r7, #108] @ 0x6c
80029ca: 2b00 cmp r3, #0
80029cc: d101 bne.n 80029d2 <HAL_ADC_ConfigChannel+0x40e>
return 32U;
80029ce: 2320 movs r3, #32
80029d0: e003 b.n 80029da <HAL_ADC_ConfigChannel+0x416>
return __builtin_clz(value);
80029d2: 6efb ldr r3, [r7, #108] @ 0x6c
80029d4: fab3 f383 clz r3, r3
80029d8: b2db uxtb r3, r3
if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
80029da: 429a cmp r2, r3
80029dc: d106 bne.n 80029ec <HAL_ADC_ConfigChannel+0x428>
{
LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
80029de: 687b ldr r3, [r7, #4]
80029e0: 681b ldr r3, [r3, #0]
80029e2: 2200 movs r2, #0
80029e4: 2103 movs r1, #3
80029e6: 4618 mov r0, r3
80029e8: f7ff f968 bl 8001cbc <LL_ADC_SetOffsetState>
}
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated only when ADC is disabled: */
/* - Single or differential mode */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
80029ec: 687b ldr r3, [r7, #4]
80029ee: 681b ldr r3, [r3, #0]
80029f0: 4618 mov r0, r3
80029f2: f7ff fad9 bl 8001fa8 <LL_ADC_IsEnabled>
80029f6: 4603 mov r3, r0
80029f8: 2b00 cmp r3, #0
80029fa: f040 813d bne.w 8002c78 <HAL_ADC_ConfigChannel+0x6b4>
{
/* Set mode single-ended or differential input of the selected ADC channel */
LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
80029fe: 687b ldr r3, [r7, #4]
8002a00: 6818 ldr r0, [r3, #0]
8002a02: 683b ldr r3, [r7, #0]
8002a04: 6819 ldr r1, [r3, #0]
8002a06: 683b ldr r3, [r7, #0]
8002a08: 68db ldr r3, [r3, #12]
8002a0a: 461a mov r2, r3
8002a0c: f7ff fa24 bl 8001e58 <LL_ADC_SetChannelSingleDiff>
/* Configuration of differential mode */
if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
8002a10: 683b ldr r3, [r7, #0]
8002a12: 68db ldr r3, [r3, #12]
8002a14: 4aa2 ldr r2, [pc, #648] @ (8002ca0 <HAL_ADC_ConfigChannel+0x6dc>)
8002a16: 4293 cmp r3, r2
8002a18: f040 812e bne.w 8002c78 <HAL_ADC_ConfigChannel+0x6b4>
{
/* Set sampling time of the selected ADC channel */
/* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002a1c: 687b ldr r3, [r7, #4]
8002a1e: 6818 ldr r0, [r3, #0]
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002a20: 683b ldr r3, [r7, #0]
8002a22: 681b ldr r3, [r3, #0]
8002a24: f3c3 0312 ubfx r3, r3, #0, #19
8002a28: 2b00 cmp r3, #0
8002a2a: d10b bne.n 8002a44 <HAL_ADC_ConfigChannel+0x480>
8002a2c: 683b ldr r3, [r7, #0]
8002a2e: 681b ldr r3, [r3, #0]
8002a30: 0e9b lsrs r3, r3, #26
8002a32: 3301 adds r3, #1
8002a34: f003 031f and.w r3, r3, #31
8002a38: 2b09 cmp r3, #9
8002a3a: bf94 ite ls
8002a3c: 2301 movls r3, #1
8002a3e: 2300 movhi r3, #0
8002a40: b2db uxtb r3, r3
8002a42: e019 b.n 8002a78 <HAL_ADC_ConfigChannel+0x4b4>
8002a44: 683b ldr r3, [r7, #0]
8002a46: 681b ldr r3, [r3, #0]
8002a48: 65fb str r3, [r7, #92] @ 0x5c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002a4a: 6dfb ldr r3, [r7, #92] @ 0x5c
8002a4c: fa93 f3a3 rbit r3, r3
8002a50: 65bb str r3, [r7, #88] @ 0x58
return result;
8002a52: 6dbb ldr r3, [r7, #88] @ 0x58
8002a54: 663b str r3, [r7, #96] @ 0x60
if (value == 0U)
8002a56: 6e3b ldr r3, [r7, #96] @ 0x60
8002a58: 2b00 cmp r3, #0
8002a5a: d101 bne.n 8002a60 <HAL_ADC_ConfigChannel+0x49c>
return 32U;
8002a5c: 2320 movs r3, #32
8002a5e: e003 b.n 8002a68 <HAL_ADC_ConfigChannel+0x4a4>
return __builtin_clz(value);
8002a60: 6e3b ldr r3, [r7, #96] @ 0x60
8002a62: fab3 f383 clz r3, r3
8002a66: b2db uxtb r3, r3
8002a68: 3301 adds r3, #1
8002a6a: f003 031f and.w r3, r3, #31
8002a6e: 2b09 cmp r3, #9
8002a70: bf94 ite ls
8002a72: 2301 movls r3, #1
8002a74: 2300 movhi r3, #0
8002a76: b2db uxtb r3, r3
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002a78: 2b00 cmp r3, #0
8002a7a: d079 beq.n 8002b70 <HAL_ADC_ConfigChannel+0x5ac>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002a7c: 683b ldr r3, [r7, #0]
8002a7e: 681b ldr r3, [r3, #0]
8002a80: f3c3 0312 ubfx r3, r3, #0, #19
8002a84: 2b00 cmp r3, #0
8002a86: d107 bne.n 8002a98 <HAL_ADC_ConfigChannel+0x4d4>
8002a88: 683b ldr r3, [r7, #0]
8002a8a: 681b ldr r3, [r3, #0]
8002a8c: 0e9b lsrs r3, r3, #26
8002a8e: 3301 adds r3, #1
8002a90: 069b lsls r3, r3, #26
8002a92: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002a96: e015 b.n 8002ac4 <HAL_ADC_ConfigChannel+0x500>
8002a98: 683b ldr r3, [r7, #0]
8002a9a: 681b ldr r3, [r3, #0]
8002a9c: 653b str r3, [r7, #80] @ 0x50
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002a9e: 6d3b ldr r3, [r7, #80] @ 0x50
8002aa0: fa93 f3a3 rbit r3, r3
8002aa4: 64fb str r3, [r7, #76] @ 0x4c
return result;
8002aa6: 6cfb ldr r3, [r7, #76] @ 0x4c
8002aa8: 657b str r3, [r7, #84] @ 0x54
if (value == 0U)
8002aaa: 6d7b ldr r3, [r7, #84] @ 0x54
8002aac: 2b00 cmp r3, #0
8002aae: d101 bne.n 8002ab4 <HAL_ADC_ConfigChannel+0x4f0>
return 32U;
8002ab0: 2320 movs r3, #32
8002ab2: e003 b.n 8002abc <HAL_ADC_ConfigChannel+0x4f8>
return __builtin_clz(value);
8002ab4: 6d7b ldr r3, [r7, #84] @ 0x54
8002ab6: fab3 f383 clz r3, r3
8002aba: b2db uxtb r3, r3
8002abc: 3301 adds r3, #1
8002abe: 069b lsls r3, r3, #26
8002ac0: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002ac4: 683b ldr r3, [r7, #0]
8002ac6: 681b ldr r3, [r3, #0]
8002ac8: f3c3 0312 ubfx r3, r3, #0, #19
8002acc: 2b00 cmp r3, #0
8002ace: d109 bne.n 8002ae4 <HAL_ADC_ConfigChannel+0x520>
8002ad0: 683b ldr r3, [r7, #0]
8002ad2: 681b ldr r3, [r3, #0]
8002ad4: 0e9b lsrs r3, r3, #26
8002ad6: 3301 adds r3, #1
8002ad8: f003 031f and.w r3, r3, #31
8002adc: 2101 movs r1, #1
8002ade: fa01 f303 lsl.w r3, r1, r3
8002ae2: e017 b.n 8002b14 <HAL_ADC_ConfigChannel+0x550>
8002ae4: 683b ldr r3, [r7, #0]
8002ae6: 681b ldr r3, [r3, #0]
8002ae8: 647b str r3, [r7, #68] @ 0x44
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002aea: 6c7b ldr r3, [r7, #68] @ 0x44
8002aec: fa93 f3a3 rbit r3, r3
8002af0: 643b str r3, [r7, #64] @ 0x40
return result;
8002af2: 6c3b ldr r3, [r7, #64] @ 0x40
8002af4: 64bb str r3, [r7, #72] @ 0x48
if (value == 0U)
8002af6: 6cbb ldr r3, [r7, #72] @ 0x48
8002af8: 2b00 cmp r3, #0
8002afa: d101 bne.n 8002b00 <HAL_ADC_ConfigChannel+0x53c>
return 32U;
8002afc: 2320 movs r3, #32
8002afe: e003 b.n 8002b08 <HAL_ADC_ConfigChannel+0x544>
return __builtin_clz(value);
8002b00: 6cbb ldr r3, [r7, #72] @ 0x48
8002b02: fab3 f383 clz r3, r3
8002b06: b2db uxtb r3, r3
8002b08: 3301 adds r3, #1
8002b0a: f003 031f and.w r3, r3, #31
8002b0e: 2101 movs r1, #1
8002b10: fa01 f303 lsl.w r3, r1, r3
8002b14: ea42 0103 orr.w r1, r2, r3
8002b18: 683b ldr r3, [r7, #0]
8002b1a: 681b ldr r3, [r3, #0]
8002b1c: f3c3 0312 ubfx r3, r3, #0, #19
8002b20: 2b00 cmp r3, #0
8002b22: d10a bne.n 8002b3a <HAL_ADC_ConfigChannel+0x576>
8002b24: 683b ldr r3, [r7, #0]
8002b26: 681b ldr r3, [r3, #0]
8002b28: 0e9b lsrs r3, r3, #26
8002b2a: 3301 adds r3, #1
8002b2c: f003 021f and.w r2, r3, #31
8002b30: 4613 mov r3, r2
8002b32: 005b lsls r3, r3, #1
8002b34: 4413 add r3, r2
8002b36: 051b lsls r3, r3, #20
8002b38: e018 b.n 8002b6c <HAL_ADC_ConfigChannel+0x5a8>
8002b3a: 683b ldr r3, [r7, #0]
8002b3c: 681b ldr r3, [r3, #0]
8002b3e: 63bb str r3, [r7, #56] @ 0x38
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002b40: 6bbb ldr r3, [r7, #56] @ 0x38
8002b42: fa93 f3a3 rbit r3, r3
8002b46: 637b str r3, [r7, #52] @ 0x34
return result;
8002b48: 6b7b ldr r3, [r7, #52] @ 0x34
8002b4a: 63fb str r3, [r7, #60] @ 0x3c
if (value == 0U)
8002b4c: 6bfb ldr r3, [r7, #60] @ 0x3c
8002b4e: 2b00 cmp r3, #0
8002b50: d101 bne.n 8002b56 <HAL_ADC_ConfigChannel+0x592>
return 32U;
8002b52: 2320 movs r3, #32
8002b54: e003 b.n 8002b5e <HAL_ADC_ConfigChannel+0x59a>
return __builtin_clz(value);
8002b56: 6bfb ldr r3, [r7, #60] @ 0x3c
8002b58: fab3 f383 clz r3, r3
8002b5c: b2db uxtb r3, r3
8002b5e: 3301 adds r3, #1
8002b60: f003 021f and.w r2, r3, #31
8002b64: 4613 mov r3, r2
8002b66: 005b lsls r3, r3, #1
8002b68: 4413 add r3, r2
8002b6a: 051b lsls r3, r3, #20
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002b6c: 430b orrs r3, r1
8002b6e: e07e b.n 8002c6e <HAL_ADC_ConfigChannel+0x6aa>
(uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL(
8002b70: 683b ldr r3, [r7, #0]
8002b72: 681b ldr r3, [r3, #0]
8002b74: f3c3 0312 ubfx r3, r3, #0, #19
8002b78: 2b00 cmp r3, #0
8002b7a: d107 bne.n 8002b8c <HAL_ADC_ConfigChannel+0x5c8>
8002b7c: 683b ldr r3, [r7, #0]
8002b7e: 681b ldr r3, [r3, #0]
8002b80: 0e9b lsrs r3, r3, #26
8002b82: 3301 adds r3, #1
8002b84: 069b lsls r3, r3, #26
8002b86: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002b8a: e015 b.n 8002bb8 <HAL_ADC_ConfigChannel+0x5f4>
8002b8c: 683b ldr r3, [r7, #0]
8002b8e: 681b ldr r3, [r3, #0]
8002b90: 62fb str r3, [r7, #44] @ 0x2c
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002b92: 6afb ldr r3, [r7, #44] @ 0x2c
8002b94: fa93 f3a3 rbit r3, r3
8002b98: 62bb str r3, [r7, #40] @ 0x28
return result;
8002b9a: 6abb ldr r3, [r7, #40] @ 0x28
8002b9c: 633b str r3, [r7, #48] @ 0x30
if (value == 0U)
8002b9e: 6b3b ldr r3, [r7, #48] @ 0x30
8002ba0: 2b00 cmp r3, #0
8002ba2: d101 bne.n 8002ba8 <HAL_ADC_ConfigChannel+0x5e4>
return 32U;
8002ba4: 2320 movs r3, #32
8002ba6: e003 b.n 8002bb0 <HAL_ADC_ConfigChannel+0x5ec>
return __builtin_clz(value);
8002ba8: 6b3b ldr r3, [r7, #48] @ 0x30
8002baa: fab3 f383 clz r3, r3
8002bae: b2db uxtb r3, r3
8002bb0: 3301 adds r3, #1
8002bb2: 069b lsls r3, r3, #26
8002bb4: f003 42f8 and.w r2, r3, #2080374784 @ 0x7c000000
8002bb8: 683b ldr r3, [r7, #0]
8002bba: 681b ldr r3, [r3, #0]
8002bbc: f3c3 0312 ubfx r3, r3, #0, #19
8002bc0: 2b00 cmp r3, #0
8002bc2: d109 bne.n 8002bd8 <HAL_ADC_ConfigChannel+0x614>
8002bc4: 683b ldr r3, [r7, #0]
8002bc6: 681b ldr r3, [r3, #0]
8002bc8: 0e9b lsrs r3, r3, #26
8002bca: 3301 adds r3, #1
8002bcc: f003 031f and.w r3, r3, #31
8002bd0: 2101 movs r1, #1
8002bd2: fa01 f303 lsl.w r3, r1, r3
8002bd6: e017 b.n 8002c08 <HAL_ADC_ConfigChannel+0x644>
8002bd8: 683b ldr r3, [r7, #0]
8002bda: 681b ldr r3, [r3, #0]
8002bdc: 623b str r3, [r7, #32]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002bde: 6a3b ldr r3, [r7, #32]
8002be0: fa93 f3a3 rbit r3, r3
8002be4: 61fb str r3, [r7, #28]
return result;
8002be6: 69fb ldr r3, [r7, #28]
8002be8: 627b str r3, [r7, #36] @ 0x24
if (value == 0U)
8002bea: 6a7b ldr r3, [r7, #36] @ 0x24
8002bec: 2b00 cmp r3, #0
8002bee: d101 bne.n 8002bf4 <HAL_ADC_ConfigChannel+0x630>
return 32U;
8002bf0: 2320 movs r3, #32
8002bf2: e003 b.n 8002bfc <HAL_ADC_ConfigChannel+0x638>
return __builtin_clz(value);
8002bf4: 6a7b ldr r3, [r7, #36] @ 0x24
8002bf6: fab3 f383 clz r3, r3
8002bfa: b2db uxtb r3, r3
8002bfc: 3301 adds r3, #1
8002bfe: f003 031f and.w r3, r3, #31
8002c02: 2101 movs r1, #1
8002c04: fa01 f303 lsl.w r3, r1, r3
8002c08: ea42 0103 orr.w r1, r2, r3
8002c0c: 683b ldr r3, [r7, #0]
8002c0e: 681b ldr r3, [r3, #0]
8002c10: f3c3 0312 ubfx r3, r3, #0, #19
8002c14: 2b00 cmp r3, #0
8002c16: d10d bne.n 8002c34 <HAL_ADC_ConfigChannel+0x670>
8002c18: 683b ldr r3, [r7, #0]
8002c1a: 681b ldr r3, [r3, #0]
8002c1c: 0e9b lsrs r3, r3, #26
8002c1e: 3301 adds r3, #1
8002c20: f003 021f and.w r2, r3, #31
8002c24: 4613 mov r3, r2
8002c26: 005b lsls r3, r3, #1
8002c28: 4413 add r3, r2
8002c2a: 3b1e subs r3, #30
8002c2c: 051b lsls r3, r3, #20
8002c2e: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
8002c32: e01b b.n 8002c6c <HAL_ADC_ConfigChannel+0x6a8>
8002c34: 683b ldr r3, [r7, #0]
8002c36: 681b ldr r3, [r3, #0]
8002c38: 617b str r3, [r7, #20]
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
8002c3a: 697b ldr r3, [r7, #20]
8002c3c: fa93 f3a3 rbit r3, r3
8002c40: 613b str r3, [r7, #16]
return result;
8002c42: 693b ldr r3, [r7, #16]
8002c44: 61bb str r3, [r7, #24]
if (value == 0U)
8002c46: 69bb ldr r3, [r7, #24]
8002c48: 2b00 cmp r3, #0
8002c4a: d101 bne.n 8002c50 <HAL_ADC_ConfigChannel+0x68c>
return 32U;
8002c4c: 2320 movs r3, #32
8002c4e: e003 b.n 8002c58 <HAL_ADC_ConfigChannel+0x694>
return __builtin_clz(value);
8002c50: 69bb ldr r3, [r7, #24]
8002c52: fab3 f383 clz r3, r3
8002c56: b2db uxtb r3, r3
8002c58: 3301 adds r3, #1
8002c5a: f003 021f and.w r2, r3, #31
8002c5e: 4613 mov r3, r2
8002c60: 005b lsls r3, r3, #1
8002c62: 4413 add r3, r2
8002c64: 3b1e subs r3, #30
8002c66: 051b lsls r3, r3, #20
8002c68: f043 7300 orr.w r3, r3, #33554432 @ 0x2000000
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002c6c: 430b orrs r3, r1
(__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel)
+ 1UL) & 0x1FUL)),
pConfig->SamplingTime);
8002c6e: 683a ldr r2, [r7, #0]
8002c70: 6892 ldr r2, [r2, #8]
LL_ADC_SetChannelSamplingTime(hadc->Instance,
8002c72: 4619 mov r1, r3
8002c74: f7ff f8c5 bl 8001e02 <LL_ADC_SetChannelSamplingTime>
/* If internal channel selected, enable dedicated internal buffers and */
/* paths. */
/* Note: these internal measurement paths can be disabled using */
/* HAL_ADC_DeInit(). */
if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
8002c78: 683b ldr r3, [r7, #0]
8002c7a: 681a ldr r2, [r3, #0]
8002c7c: 4b09 ldr r3, [pc, #36] @ (8002ca4 <HAL_ADC_ConfigChannel+0x6e0>)
8002c7e: 4013 ands r3, r2
8002c80: 2b00 cmp r3, #0
8002c82: f000 80be beq.w 8002e02 <HAL_ADC_ConfigChannel+0x83e>
{
tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
8002c86: 687b ldr r3, [r7, #4]
8002c88: 681b ldr r3, [r3, #0]
8002c8a: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8002c8e: d004 beq.n 8002c9a <HAL_ADC_ConfigChannel+0x6d6>
8002c90: 687b ldr r3, [r7, #4]
8002c92: 681b ldr r3, [r3, #0]
8002c94: 4a04 ldr r2, [pc, #16] @ (8002ca8 <HAL_ADC_ConfigChannel+0x6e4>)
8002c96: 4293 cmp r3, r2
8002c98: d10a bne.n 8002cb0 <HAL_ADC_ConfigChannel+0x6ec>
8002c9a: 4b04 ldr r3, [pc, #16] @ (8002cac <HAL_ADC_ConfigChannel+0x6e8>)
8002c9c: e009 b.n 8002cb2 <HAL_ADC_ConfigChannel+0x6ee>
8002c9e: bf00 nop
8002ca0: 407f0000 .word 0x407f0000
8002ca4: 80080000 .word 0x80080000
8002ca8: 50000100 .word 0x50000100
8002cac: 50000300 .word 0x50000300
8002cb0: 4b59 ldr r3, [pc, #356] @ (8002e18 <HAL_ADC_ConfigChannel+0x854>)
8002cb2: 4618 mov r0, r3
8002cb4: f7fe ffba bl 8001c2c <LL_ADC_GetCommonPathInternalCh>
8002cb8: f8c7 00c4 str.w r0, [r7, #196] @ 0xc4
/* If the requested internal measurement path has already been enabled, */
/* bypass the configuration processing. */
if (((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (pConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5))
8002cbc: 683b ldr r3, [r7, #0]
8002cbe: 681b ldr r3, [r3, #0]
8002cc0: 4a56 ldr r2, [pc, #344] @ (8002e1c <HAL_ADC_ConfigChannel+0x858>)
8002cc2: 4293 cmp r3, r2
8002cc4: d004 beq.n 8002cd0 <HAL_ADC_ConfigChannel+0x70c>
8002cc6: 683b ldr r3, [r7, #0]
8002cc8: 681b ldr r3, [r3, #0]
8002cca: 4a55 ldr r2, [pc, #340] @ (8002e20 <HAL_ADC_ConfigChannel+0x85c>)
8002ccc: 4293 cmp r3, r2
8002cce: d13a bne.n 8002d46 <HAL_ADC_ConfigChannel+0x782>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
8002cd0: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002cd4: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8002cd8: 2b00 cmp r3, #0
8002cda: d134 bne.n 8002d46 <HAL_ADC_ConfigChannel+0x782>
{
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
8002cdc: 687b ldr r3, [r7, #4]
8002cde: 681b ldr r3, [r3, #0]
8002ce0: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8002ce4: d005 beq.n 8002cf2 <HAL_ADC_ConfigChannel+0x72e>
8002ce6: 687b ldr r3, [r7, #4]
8002ce8: 681b ldr r3, [r3, #0]
8002cea: 4a4e ldr r2, [pc, #312] @ (8002e24 <HAL_ADC_ConfigChannel+0x860>)
8002cec: 4293 cmp r3, r2
8002cee: f040 8085 bne.w 8002dfc <HAL_ADC_ConfigChannel+0x838>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002cf2: 687b ldr r3, [r7, #4]
8002cf4: 681b ldr r3, [r3, #0]
8002cf6: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8002cfa: d004 beq.n 8002d06 <HAL_ADC_ConfigChannel+0x742>
8002cfc: 687b ldr r3, [r7, #4]
8002cfe: 681b ldr r3, [r3, #0]
8002d00: 4a49 ldr r2, [pc, #292] @ (8002e28 <HAL_ADC_ConfigChannel+0x864>)
8002d02: 4293 cmp r3, r2
8002d04: d101 bne.n 8002d0a <HAL_ADC_ConfigChannel+0x746>
8002d06: 4a49 ldr r2, [pc, #292] @ (8002e2c <HAL_ADC_ConfigChannel+0x868>)
8002d08: e000 b.n 8002d0c <HAL_ADC_ConfigChannel+0x748>
8002d0a: 4a43 ldr r2, [pc, #268] @ (8002e18 <HAL_ADC_ConfigChannel+0x854>)
8002d0c: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002d10: f443 0300 orr.w r3, r3, #8388608 @ 0x800000
8002d14: 4619 mov r1, r3
8002d16: 4610 mov r0, r2
8002d18: f7fe ff75 bl 8001c06 <LL_ADC_SetCommonPathInternalCh>
/* Delay for temperature sensor stabilization time */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8002d1c: 4b44 ldr r3, [pc, #272] @ (8002e30 <HAL_ADC_ConfigChannel+0x86c>)
8002d1e: 681b ldr r3, [r3, #0]
8002d20: 099b lsrs r3, r3, #6
8002d22: 4a44 ldr r2, [pc, #272] @ (8002e34 <HAL_ADC_ConfigChannel+0x870>)
8002d24: fba2 2303 umull r2, r3, r2, r3
8002d28: 099b lsrs r3, r3, #6
8002d2a: 1c5a adds r2, r3, #1
8002d2c: 4613 mov r3, r2
8002d2e: 005b lsls r3, r3, #1
8002d30: 4413 add r3, r2
8002d32: 009b lsls r3, r3, #2
8002d34: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8002d36: e002 b.n 8002d3e <HAL_ADC_ConfigChannel+0x77a>
{
wait_loop_index--;
8002d38: 68fb ldr r3, [r7, #12]
8002d3a: 3b01 subs r3, #1
8002d3c: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8002d3e: 68fb ldr r3, [r7, #12]
8002d40: 2b00 cmp r3, #0
8002d42: d1f9 bne.n 8002d38 <HAL_ADC_ConfigChannel+0x774>
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
8002d44: e05a b.n 8002dfc <HAL_ADC_ConfigChannel+0x838>
}
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VBAT)
8002d46: 683b ldr r3, [r7, #0]
8002d48: 681b ldr r3, [r3, #0]
8002d4a: 4a3b ldr r2, [pc, #236] @ (8002e38 <HAL_ADC_ConfigChannel+0x874>)
8002d4c: 4293 cmp r3, r2
8002d4e: d125 bne.n 8002d9c <HAL_ADC_ConfigChannel+0x7d8>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
8002d50: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002d54: f003 7380 and.w r3, r3, #16777216 @ 0x1000000
8002d58: 2b00 cmp r3, #0
8002d5a: d11f bne.n 8002d9c <HAL_ADC_ConfigChannel+0x7d8>
{
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
8002d5c: 687b ldr r3, [r7, #4]
8002d5e: 681b ldr r3, [r3, #0]
8002d60: 4a31 ldr r2, [pc, #196] @ (8002e28 <HAL_ADC_ConfigChannel+0x864>)
8002d62: 4293 cmp r3, r2
8002d64: d104 bne.n 8002d70 <HAL_ADC_ConfigChannel+0x7ac>
8002d66: 687b ldr r3, [r7, #4]
8002d68: 681b ldr r3, [r3, #0]
8002d6a: 4a34 ldr r2, [pc, #208] @ (8002e3c <HAL_ADC_ConfigChannel+0x878>)
8002d6c: 4293 cmp r3, r2
8002d6e: d047 beq.n 8002e00 <HAL_ADC_ConfigChannel+0x83c>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002d70: 687b ldr r3, [r7, #4]
8002d72: 681b ldr r3, [r3, #0]
8002d74: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8002d78: d004 beq.n 8002d84 <HAL_ADC_ConfigChannel+0x7c0>
8002d7a: 687b ldr r3, [r7, #4]
8002d7c: 681b ldr r3, [r3, #0]
8002d7e: 4a2a ldr r2, [pc, #168] @ (8002e28 <HAL_ADC_ConfigChannel+0x864>)
8002d80: 4293 cmp r3, r2
8002d82: d101 bne.n 8002d88 <HAL_ADC_ConfigChannel+0x7c4>
8002d84: 4a29 ldr r2, [pc, #164] @ (8002e2c <HAL_ADC_ConfigChannel+0x868>)
8002d86: e000 b.n 8002d8a <HAL_ADC_ConfigChannel+0x7c6>
8002d88: 4a23 ldr r2, [pc, #140] @ (8002e18 <HAL_ADC_ConfigChannel+0x854>)
8002d8a: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002d8e: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8002d92: 4619 mov r1, r3
8002d94: 4610 mov r0, r2
8002d96: f7fe ff36 bl 8001c06 <LL_ADC_SetCommonPathInternalCh>
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
8002d9a: e031 b.n 8002e00 <HAL_ADC_ConfigChannel+0x83c>
LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
}
}
else if ((pConfig->Channel == ADC_CHANNEL_VREFINT)
8002d9c: 683b ldr r3, [r7, #0]
8002d9e: 681b ldr r3, [r3, #0]
8002da0: 4a27 ldr r2, [pc, #156] @ (8002e40 <HAL_ADC_ConfigChannel+0x87c>)
8002da2: 4293 cmp r3, r2
8002da4: d12d bne.n 8002e02 <HAL_ADC_ConfigChannel+0x83e>
&& ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
8002da6: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002daa: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8002dae: 2b00 cmp r3, #0
8002db0: d127 bne.n 8002e02 <HAL_ADC_ConfigChannel+0x83e>
{
if (ADC_VREFINT_INSTANCE(hadc))
8002db2: 687b ldr r3, [r7, #4]
8002db4: 681b ldr r3, [r3, #0]
8002db6: 4a1c ldr r2, [pc, #112] @ (8002e28 <HAL_ADC_ConfigChannel+0x864>)
8002db8: 4293 cmp r3, r2
8002dba: d022 beq.n 8002e02 <HAL_ADC_ConfigChannel+0x83e>
{
LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
8002dbc: 687b ldr r3, [r7, #4]
8002dbe: 681b ldr r3, [r3, #0]
8002dc0: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8002dc4: d004 beq.n 8002dd0 <HAL_ADC_ConfigChannel+0x80c>
8002dc6: 687b ldr r3, [r7, #4]
8002dc8: 681b ldr r3, [r3, #0]
8002dca: 4a17 ldr r2, [pc, #92] @ (8002e28 <HAL_ADC_ConfigChannel+0x864>)
8002dcc: 4293 cmp r3, r2
8002dce: d101 bne.n 8002dd4 <HAL_ADC_ConfigChannel+0x810>
8002dd0: 4a16 ldr r2, [pc, #88] @ (8002e2c <HAL_ADC_ConfigChannel+0x868>)
8002dd2: e000 b.n 8002dd6 <HAL_ADC_ConfigChannel+0x812>
8002dd4: 4a10 ldr r2, [pc, #64] @ (8002e18 <HAL_ADC_ConfigChannel+0x854>)
8002dd6: f8d7 30c4 ldr.w r3, [r7, #196] @ 0xc4
8002dda: f443 0380 orr.w r3, r3, #4194304 @ 0x400000
8002dde: 4619 mov r1, r3
8002de0: 4610 mov r0, r2
8002de2: f7fe ff10 bl 8001c06 <LL_ADC_SetCommonPathInternalCh>
8002de6: e00c b.n 8002e02 <HAL_ADC_ConfigChannel+0x83e>
/* channel could be done on neither of the channel configuration structure */
/* parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8002de8: 687b ldr r3, [r7, #4]
8002dea: 6ddb ldr r3, [r3, #92] @ 0x5c
8002dec: f043 0220 orr.w r2, r3, #32
8002df0: 687b ldr r3, [r7, #4]
8002df2: 65da str r2, [r3, #92] @ 0x5c
tmp_hal_status = HAL_ERROR;
8002df4: 2301 movs r3, #1
8002df6: f887 30d7 strb.w r3, [r7, #215] @ 0xd7
8002dfa: e002 b.n 8002e02 <HAL_ADC_ConfigChannel+0x83e>
if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
8002dfc: bf00 nop
8002dfe: e000 b.n 8002e02 <HAL_ADC_ConfigChannel+0x83e>
if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
8002e00: bf00 nop
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
8002e02: 687b ldr r3, [r7, #4]
8002e04: 2200 movs r2, #0
8002e06: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
8002e0a: f897 30d7 ldrb.w r3, [r7, #215] @ 0xd7
}
8002e0e: 4618 mov r0, r3
8002e10: 37d8 adds r7, #216 @ 0xd8
8002e12: 46bd mov sp, r7
8002e14: bd80 pop {r7, pc}
8002e16: bf00 nop
8002e18: 50000700 .word 0x50000700
8002e1c: c3210000 .word 0xc3210000
8002e20: 90c00010 .word 0x90c00010
8002e24: 50000600 .word 0x50000600
8002e28: 50000100 .word 0x50000100
8002e2c: 50000300 .word 0x50000300
8002e30: 20000000 .word 0x20000000
8002e34: 053e2d63 .word 0x053e2d63
8002e38: c7520000 .word 0xc7520000
8002e3c: 50000500 .word 0x50000500
8002e40: cb840000 .word 0xcb840000
08002e44 <ADC_Enable>:
* and voltage regulator must be enabled (done into HAL_ADC_Init()).
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
{
8002e44: b580 push {r7, lr}
8002e46: b084 sub sp, #16
8002e48: af00 add r7, sp, #0
8002e4a: 6078 str r0, [r7, #4]
uint32_t tickstart;
__IO uint32_t wait_loop_index = 0UL;
8002e4c: 2300 movs r3, #0
8002e4e: 60bb str r3, [r7, #8]
/* ADC enable and wait for ADC ready (in case of ADC is disabled or */
/* enabling phase not yet completed: flag ADC ready not yet set). */
/* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
/* causes: ADC clock not running, ...). */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8002e50: 687b ldr r3, [r7, #4]
8002e52: 681b ldr r3, [r3, #0]
8002e54: 4618 mov r0, r3
8002e56: f7ff f8a7 bl 8001fa8 <LL_ADC_IsEnabled>
8002e5a: 4603 mov r3, r0
8002e5c: 2b00 cmp r3, #0
8002e5e: d176 bne.n 8002f4e <ADC_Enable+0x10a>
{
/* Check if conditions to enable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
8002e60: 687b ldr r3, [r7, #4]
8002e62: 681b ldr r3, [r3, #0]
8002e64: 689a ldr r2, [r3, #8]
8002e66: 4b3c ldr r3, [pc, #240] @ (8002f58 <ADC_Enable+0x114>)
8002e68: 4013 ands r3, r2
8002e6a: 2b00 cmp r3, #0
8002e6c: d00d beq.n 8002e8a <ADC_Enable+0x46>
| ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002e6e: 687b ldr r3, [r7, #4]
8002e70: 6ddb ldr r3, [r3, #92] @ 0x5c
8002e72: f043 0210 orr.w r2, r3, #16
8002e76: 687b ldr r3, [r7, #4]
8002e78: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002e7a: 687b ldr r3, [r7, #4]
8002e7c: 6e1b ldr r3, [r3, #96] @ 0x60
8002e7e: f043 0201 orr.w r2, r3, #1
8002e82: 687b ldr r3, [r7, #4]
8002e84: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8002e86: 2301 movs r3, #1
8002e88: e062 b.n 8002f50 <ADC_Enable+0x10c>
}
/* Enable the ADC peripheral */
LL_ADC_Enable(hadc->Instance);
8002e8a: 687b ldr r3, [r7, #4]
8002e8c: 681b ldr r3, [r3, #0]
8002e8e: 4618 mov r0, r3
8002e90: f7ff f862 bl 8001f58 <LL_ADC_Enable>
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
8002e94: 687b ldr r3, [r7, #4]
8002e96: 681b ldr r3, [r3, #0]
8002e98: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8002e9c: d004 beq.n 8002ea8 <ADC_Enable+0x64>
8002e9e: 687b ldr r3, [r7, #4]
8002ea0: 681b ldr r3, [r3, #0]
8002ea2: 4a2e ldr r2, [pc, #184] @ (8002f5c <ADC_Enable+0x118>)
8002ea4: 4293 cmp r3, r2
8002ea6: d101 bne.n 8002eac <ADC_Enable+0x68>
8002ea8: 4b2d ldr r3, [pc, #180] @ (8002f60 <ADC_Enable+0x11c>)
8002eaa: e000 b.n 8002eae <ADC_Enable+0x6a>
8002eac: 4b2d ldr r3, [pc, #180] @ (8002f64 <ADC_Enable+0x120>)
8002eae: 4618 mov r0, r3
8002eb0: f7fe febc bl 8001c2c <LL_ADC_GetCommonPathInternalCh>
8002eb4: 4603 mov r3, r0
& LL_ADC_PATH_INTERNAL_TEMPSENSOR) != 0UL)
8002eb6: f403 0300 and.w r3, r3, #8388608 @ 0x800000
if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))
8002eba: 2b00 cmp r3, #0
8002ebc: d013 beq.n 8002ee6 <ADC_Enable+0xa2>
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8002ebe: 4b2a ldr r3, [pc, #168] @ (8002f68 <ADC_Enable+0x124>)
8002ec0: 681b ldr r3, [r3, #0]
8002ec2: 099b lsrs r3, r3, #6
8002ec4: 4a29 ldr r2, [pc, #164] @ (8002f6c <ADC_Enable+0x128>)
8002ec6: fba2 2303 umull r2, r3, r2, r3
8002eca: 099b lsrs r3, r3, #6
8002ecc: 1c5a adds r2, r3, #1
8002ece: 4613 mov r3, r2
8002ed0: 005b lsls r3, r3, #1
8002ed2: 4413 add r3, r2
8002ed4: 009b lsls r3, r3, #2
8002ed6: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8002ed8: e002 b.n 8002ee0 <ADC_Enable+0x9c>
{
wait_loop_index--;
8002eda: 68bb ldr r3, [r7, #8]
8002edc: 3b01 subs r3, #1
8002ede: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8002ee0: 68bb ldr r3, [r7, #8]
8002ee2: 2b00 cmp r3, #0
8002ee4: d1f9 bne.n 8002eda <ADC_Enable+0x96>
}
}
/* Wait for ADC effectively enabled */
tickstart = HAL_GetTick();
8002ee6: f7fe fe01 bl 8001aec <HAL_GetTick>
8002eea: 60f8 str r0, [r7, #12]
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8002eec: e028 b.n 8002f40 <ADC_Enable+0xfc>
The workaround is to continue setting ADEN until ADRDY is becomes 1.
Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
4 ADC clock cycle duration */
/* Note: Test of ADC enabled required due to hardware constraint to */
/* not enable ADC if already enabled. */
if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
8002eee: 687b ldr r3, [r7, #4]
8002ef0: 681b ldr r3, [r3, #0]
8002ef2: 4618 mov r0, r3
8002ef4: f7ff f858 bl 8001fa8 <LL_ADC_IsEnabled>
8002ef8: 4603 mov r3, r0
8002efa: 2b00 cmp r3, #0
8002efc: d104 bne.n 8002f08 <ADC_Enable+0xc4>
{
LL_ADC_Enable(hadc->Instance);
8002efe: 687b ldr r3, [r7, #4]
8002f00: 681b ldr r3, [r3, #0]
8002f02: 4618 mov r0, r3
8002f04: f7ff f828 bl 8001f58 <LL_ADC_Enable>
}
if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
8002f08: f7fe fdf0 bl 8001aec <HAL_GetTick>
8002f0c: 4602 mov r2, r0
8002f0e: 68fb ldr r3, [r7, #12]
8002f10: 1ad3 subs r3, r2, r3
8002f12: 2b02 cmp r3, #2
8002f14: d914 bls.n 8002f40 <ADC_Enable+0xfc>
{
/* New check to avoid false timeout detection in case of preemption */
if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8002f16: 687b ldr r3, [r7, #4]
8002f18: 681b ldr r3, [r3, #0]
8002f1a: 681b ldr r3, [r3, #0]
8002f1c: f003 0301 and.w r3, r3, #1
8002f20: 2b01 cmp r3, #1
8002f22: d00d beq.n 8002f40 <ADC_Enable+0xfc>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002f24: 687b ldr r3, [r7, #4]
8002f26: 6ddb ldr r3, [r3, #92] @ 0x5c
8002f28: f043 0210 orr.w r2, r3, #16
8002f2c: 687b ldr r3, [r7, #4]
8002f2e: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002f30: 687b ldr r3, [r7, #4]
8002f32: 6e1b ldr r3, [r3, #96] @ 0x60
8002f34: f043 0201 orr.w r2, r3, #1
8002f38: 687b ldr r3, [r7, #4]
8002f3a: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8002f3c: 2301 movs r3, #1
8002f3e: e007 b.n 8002f50 <ADC_Enable+0x10c>
while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
8002f40: 687b ldr r3, [r7, #4]
8002f42: 681b ldr r3, [r3, #0]
8002f44: 681b ldr r3, [r3, #0]
8002f46: f003 0301 and.w r3, r3, #1
8002f4a: 2b01 cmp r3, #1
8002f4c: d1cf bne.n 8002eee <ADC_Enable+0xaa>
}
}
}
/* Return HAL status */
return HAL_OK;
8002f4e: 2300 movs r3, #0
}
8002f50: 4618 mov r0, r3
8002f52: 3710 adds r7, #16
8002f54: 46bd mov sp, r7
8002f56: bd80 pop {r7, pc}
8002f58: 8000003f .word 0x8000003f
8002f5c: 50000100 .word 0x50000100
8002f60: 50000300 .word 0x50000300
8002f64: 50000700 .word 0x50000700
8002f68: 20000000 .word 0x20000000
8002f6c: 053e2d63 .word 0x053e2d63
08002f70 <ADC_Disable>:
* stopped.
* @param hadc ADC handle
* @retval HAL status.
*/
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
{
8002f70: b580 push {r7, lr}
8002f72: b084 sub sp, #16
8002f74: af00 add r7, sp, #0
8002f76: 6078 str r0, [r7, #4]
uint32_t tickstart;
const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
8002f78: 687b ldr r3, [r7, #4]
8002f7a: 681b ldr r3, [r3, #0]
8002f7c: 4618 mov r0, r3
8002f7e: f7ff f826 bl 8001fce <LL_ADC_IsDisableOngoing>
8002f82: 60f8 str r0, [r7, #12]
/* Verification if ADC is not already disabled: */
/* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
/* disabled. */
if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
8002f84: 687b ldr r3, [r7, #4]
8002f86: 681b ldr r3, [r3, #0]
8002f88: 4618 mov r0, r3
8002f8a: f7ff f80d bl 8001fa8 <LL_ADC_IsEnabled>
8002f8e: 4603 mov r3, r0
8002f90: 2b00 cmp r3, #0
8002f92: d047 beq.n 8003024 <ADC_Disable+0xb4>
&& (tmp_adc_is_disable_on_going == 0UL)
8002f94: 68fb ldr r3, [r7, #12]
8002f96: 2b00 cmp r3, #0
8002f98: d144 bne.n 8003024 <ADC_Disable+0xb4>
)
{
/* Check if conditions to disable the ADC are fulfilled */
if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
8002f9a: 687b ldr r3, [r7, #4]
8002f9c: 681b ldr r3, [r3, #0]
8002f9e: 689b ldr r3, [r3, #8]
8002fa0: f003 030d and.w r3, r3, #13
8002fa4: 2b01 cmp r3, #1
8002fa6: d10c bne.n 8002fc2 <ADC_Disable+0x52>
{
/* Disable the ADC peripheral */
LL_ADC_Disable(hadc->Instance);
8002fa8: 687b ldr r3, [r7, #4]
8002faa: 681b ldr r3, [r3, #0]
8002fac: 4618 mov r0, r3
8002fae: f7fe ffe7 bl 8001f80 <LL_ADC_Disable>
__HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
8002fb2: 687b ldr r3, [r7, #4]
8002fb4: 681b ldr r3, [r3, #0]
8002fb6: 2203 movs r2, #3
8002fb8: 601a str r2, [r3, #0]
return HAL_ERROR;
}
/* Wait for ADC effectively disabled */
/* Get tick count */
tickstart = HAL_GetTick();
8002fba: f7fe fd97 bl 8001aec <HAL_GetTick>
8002fbe: 60b8 str r0, [r7, #8]
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8002fc0: e029 b.n 8003016 <ADC_Disable+0xa6>
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002fc2: 687b ldr r3, [r7, #4]
8002fc4: 6ddb ldr r3, [r3, #92] @ 0x5c
8002fc6: f043 0210 orr.w r2, r3, #16
8002fca: 687b ldr r3, [r7, #4]
8002fcc: 65da str r2, [r3, #92] @ 0x5c
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8002fce: 687b ldr r3, [r7, #4]
8002fd0: 6e1b ldr r3, [r3, #96] @ 0x60
8002fd2: f043 0201 orr.w r2, r3, #1
8002fd6: 687b ldr r3, [r7, #4]
8002fd8: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8002fda: 2301 movs r3, #1
8002fdc: e023 b.n 8003026 <ADC_Disable+0xb6>
{
if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
8002fde: f7fe fd85 bl 8001aec <HAL_GetTick>
8002fe2: 4602 mov r2, r0
8002fe4: 68bb ldr r3, [r7, #8]
8002fe6: 1ad3 subs r3, r2, r3
8002fe8: 2b02 cmp r3, #2
8002fea: d914 bls.n 8003016 <ADC_Disable+0xa6>
{
/* New check to avoid false timeout detection in case of preemption */
if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8002fec: 687b ldr r3, [r7, #4]
8002fee: 681b ldr r3, [r3, #0]
8002ff0: 689b ldr r3, [r3, #8]
8002ff2: f003 0301 and.w r3, r3, #1
8002ff6: 2b00 cmp r3, #0
8002ff8: d00d beq.n 8003016 <ADC_Disable+0xa6>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
8002ffa: 687b ldr r3, [r7, #4]
8002ffc: 6ddb ldr r3, [r3, #92] @ 0x5c
8002ffe: f043 0210 orr.w r2, r3, #16
8003002: 687b ldr r3, [r7, #4]
8003004: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to ADC peripheral internal error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
8003006: 687b ldr r3, [r7, #4]
8003008: 6e1b ldr r3, [r3, #96] @ 0x60
800300a: f043 0201 orr.w r2, r3, #1
800300e: 687b ldr r3, [r7, #4]
8003010: 661a str r2, [r3, #96] @ 0x60
return HAL_ERROR;
8003012: 2301 movs r3, #1
8003014: e007 b.n 8003026 <ADC_Disable+0xb6>
while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
8003016: 687b ldr r3, [r7, #4]
8003018: 681b ldr r3, [r3, #0]
800301a: 689b ldr r3, [r3, #8]
800301c: f003 0301 and.w r3, r3, #1
8003020: 2b00 cmp r3, #0
8003022: d1dc bne.n 8002fde <ADC_Disable+0x6e>
}
}
}
/* Return HAL status */
return HAL_OK;
8003024: 2300 movs r3, #0
}
8003026: 4618 mov r0, r3
8003028: 3710 adds r7, #16
800302a: 46bd mov sp, r7
800302c: bd80 pop {r7, pc}
0800302e <ADC_DMAConvCplt>:
* @brief DMA transfer complete callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
{
800302e: b580 push {r7, lr}
8003030: b084 sub sp, #16
8003032: af00 add r7, sp, #0
8003034: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
8003036: 687b ldr r3, [r7, #4]
8003038: 6a9b ldr r3, [r3, #40] @ 0x28
800303a: 60fb str r3, [r7, #12]
/* Update state machine on conversion status if not in error state */
if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
800303c: 68fb ldr r3, [r7, #12]
800303e: 6ddb ldr r3, [r3, #92] @ 0x5c
8003040: f003 0350 and.w r3, r3, #80 @ 0x50
8003044: 2b00 cmp r3, #0
8003046: d14b bne.n 80030e0 <ADC_DMAConvCplt+0xb2>
{
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
8003048: 68fb ldr r3, [r7, #12]
800304a: 6ddb ldr r3, [r3, #92] @ 0x5c
800304c: f443 7200 orr.w r2, r3, #512 @ 0x200
8003050: 68fb ldr r3, [r7, #12]
8003052: 65da str r2, [r3, #92] @ 0x5c
/* Determine whether any further conversion upcoming on group regular */
/* by external trigger, continuous mode or scan sequence on going */
/* to disable interruption. */
/* Is it the end of the regular sequence ? */
if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
8003054: 68fb ldr r3, [r7, #12]
8003056: 681b ldr r3, [r3, #0]
8003058: 681b ldr r3, [r3, #0]
800305a: f003 0308 and.w r3, r3, #8
800305e: 2b00 cmp r3, #0
8003060: d021 beq.n 80030a6 <ADC_DMAConvCplt+0x78>
{
/* Are conversions software-triggered ? */
if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
8003062: 68fb ldr r3, [r7, #12]
8003064: 681b ldr r3, [r3, #0]
8003066: 4618 mov r0, r3
8003068: f7fe fe8c bl 8001d84 <LL_ADC_REG_IsTriggerSourceSWStart>
800306c: 4603 mov r3, r0
800306e: 2b00 cmp r3, #0
8003070: d032 beq.n 80030d8 <ADC_DMAConvCplt+0xaa>
{
/* Is CONT bit set ? */
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
8003072: 68fb ldr r3, [r7, #12]
8003074: 681b ldr r3, [r3, #0]
8003076: 68db ldr r3, [r3, #12]
8003078: f403 5300 and.w r3, r3, #8192 @ 0x2000
800307c: 2b00 cmp r3, #0
800307e: d12b bne.n 80030d8 <ADC_DMAConvCplt+0xaa>
{
/* CONT bit is not set, no more conversions expected */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
8003080: 68fb ldr r3, [r7, #12]
8003082: 6ddb ldr r3, [r3, #92] @ 0x5c
8003084: f423 7280 bic.w r2, r3, #256 @ 0x100
8003088: 68fb ldr r3, [r7, #12]
800308a: 65da str r2, [r3, #92] @ 0x5c
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
800308c: 68fb ldr r3, [r7, #12]
800308e: 6ddb ldr r3, [r3, #92] @ 0x5c
8003090: f403 5380 and.w r3, r3, #4096 @ 0x1000
8003094: 2b00 cmp r3, #0
8003096: d11f bne.n 80030d8 <ADC_DMAConvCplt+0xaa>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
8003098: 68fb ldr r3, [r7, #12]
800309a: 6ddb ldr r3, [r3, #92] @ 0x5c
800309c: f043 0201 orr.w r2, r3, #1
80030a0: 68fb ldr r3, [r7, #12]
80030a2: 65da str r2, [r3, #92] @ 0x5c
80030a4: e018 b.n 80030d8 <ADC_DMAConvCplt+0xaa>
}
else
{
/* DMA End of Transfer interrupt was triggered but conversions sequence
is not over. If DMACFG is set to 0, conversions are stopped. */
if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL)
80030a6: 68fb ldr r3, [r7, #12]
80030a8: 681b ldr r3, [r3, #0]
80030aa: 68db ldr r3, [r3, #12]
80030ac: f003 0302 and.w r3, r3, #2
80030b0: 2b00 cmp r3, #0
80030b2: d111 bne.n 80030d8 <ADC_DMAConvCplt+0xaa>
{
/* DMACFG bit is not set, conversions are stopped. */
CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
80030b4: 68fb ldr r3, [r7, #12]
80030b6: 6ddb ldr r3, [r3, #92] @ 0x5c
80030b8: f423 7280 bic.w r2, r3, #256 @ 0x100
80030bc: 68fb ldr r3, [r7, #12]
80030be: 65da str r2, [r3, #92] @ 0x5c
if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
80030c0: 68fb ldr r3, [r7, #12]
80030c2: 6ddb ldr r3, [r3, #92] @ 0x5c
80030c4: f403 5380 and.w r3, r3, #4096 @ 0x1000
80030c8: 2b00 cmp r3, #0
80030ca: d105 bne.n 80030d8 <ADC_DMAConvCplt+0xaa>
{
SET_BIT(hadc->State, HAL_ADC_STATE_READY);
80030cc: 68fb ldr r3, [r7, #12]
80030ce: 6ddb ldr r3, [r3, #92] @ 0x5c
80030d0: f043 0201 orr.w r2, r3, #1
80030d4: 68fb ldr r3, [r7, #12]
80030d6: 65da str r2, [r3, #92] @ 0x5c
/* Conversion complete callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvCpltCallback(hadc);
#else
HAL_ADC_ConvCpltCallback(hadc);
80030d8: 68f8 ldr r0, [r7, #12]
80030da: f7ff fa55 bl 8002588 <HAL_ADC_ConvCpltCallback>
{
/* Call ADC DMA error callback */
hadc->DMA_Handle->XferErrorCallback(hdma);
}
}
}
80030de: e00e b.n 80030fe <ADC_DMAConvCplt+0xd0>
if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
80030e0: 68fb ldr r3, [r7, #12]
80030e2: 6ddb ldr r3, [r3, #92] @ 0x5c
80030e4: f003 0310 and.w r3, r3, #16
80030e8: 2b00 cmp r3, #0
80030ea: d003 beq.n 80030f4 <ADC_DMAConvCplt+0xc6>
HAL_ADC_ErrorCallback(hadc);
80030ec: 68f8 ldr r0, [r7, #12]
80030ee: f7ff fa5f bl 80025b0 <HAL_ADC_ErrorCallback>
}
80030f2: e004 b.n 80030fe <ADC_DMAConvCplt+0xd0>
hadc->DMA_Handle->XferErrorCallback(hdma);
80030f4: 68fb ldr r3, [r7, #12]
80030f6: 6d5b ldr r3, [r3, #84] @ 0x54
80030f8: 6b5b ldr r3, [r3, #52] @ 0x34
80030fa: 6878 ldr r0, [r7, #4]
80030fc: 4798 blx r3
}
80030fe: bf00 nop
8003100: 3710 adds r7, #16
8003102: 46bd mov sp, r7
8003104: bd80 pop {r7, pc}
08003106 <ADC_DMAHalfConvCplt>:
* @brief DMA half transfer complete callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
{
8003106: b580 push {r7, lr}
8003108: b084 sub sp, #16
800310a: af00 add r7, sp, #0
800310c: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
800310e: 687b ldr r3, [r7, #4]
8003110: 6a9b ldr r3, [r3, #40] @ 0x28
8003112: 60fb str r3, [r7, #12]
/* Half conversion callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ConvHalfCpltCallback(hadc);
#else
HAL_ADC_ConvHalfCpltCallback(hadc);
8003114: 68f8 ldr r0, [r7, #12]
8003116: f7ff fa41 bl 800259c <HAL_ADC_ConvHalfCpltCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
800311a: bf00 nop
800311c: 3710 adds r7, #16
800311e: 46bd mov sp, r7
8003120: bd80 pop {r7, pc}
08003122 <ADC_DMAError>:
* @brief DMA error callback.
* @param hdma pointer to DMA handle.
* @retval None
*/
void ADC_DMAError(DMA_HandleTypeDef *hdma)
{
8003122: b580 push {r7, lr}
8003124: b084 sub sp, #16
8003126: af00 add r7, sp, #0
8003128: 6078 str r0, [r7, #4]
/* Retrieve ADC handle corresponding to current DMA handle */
ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
800312a: 687b ldr r3, [r7, #4]
800312c: 6a9b ldr r3, [r3, #40] @ 0x28
800312e: 60fb str r3, [r7, #12]
/* Set ADC state */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
8003130: 68fb ldr r3, [r7, #12]
8003132: 6ddb ldr r3, [r3, #92] @ 0x5c
8003134: f043 0240 orr.w r2, r3, #64 @ 0x40
8003138: 68fb ldr r3, [r7, #12]
800313a: 65da str r2, [r3, #92] @ 0x5c
/* Set ADC error code to DMA error */
SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
800313c: 68fb ldr r3, [r7, #12]
800313e: 6e1b ldr r3, [r3, #96] @ 0x60
8003140: f043 0204 orr.w r2, r3, #4
8003144: 68fb ldr r3, [r7, #12]
8003146: 661a str r2, [r3, #96] @ 0x60
/* Error callback */
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
hadc->ErrorCallback(hadc);
#else
HAL_ADC_ErrorCallback(hadc);
8003148: 68f8 ldr r0, [r7, #12]
800314a: f7ff fa31 bl 80025b0 <HAL_ADC_ErrorCallback>
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}
800314e: bf00 nop
8003150: 3710 adds r7, #16
8003152: 46bd mov sp, r7
8003154: bd80 pop {r7, pc}
08003156 <LL_ADC_IsEnabled>:
{
8003156: b480 push {r7}
8003158: b083 sub sp, #12
800315a: af00 add r7, sp, #0
800315c: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
800315e: 687b ldr r3, [r7, #4]
8003160: 689b ldr r3, [r3, #8]
8003162: f003 0301 and.w r3, r3, #1
8003166: 2b01 cmp r3, #1
8003168: d101 bne.n 800316e <LL_ADC_IsEnabled+0x18>
800316a: 2301 movs r3, #1
800316c: e000 b.n 8003170 <LL_ADC_IsEnabled+0x1a>
800316e: 2300 movs r3, #0
}
8003170: 4618 mov r0, r3
8003172: 370c adds r7, #12
8003174: 46bd mov sp, r7
8003176: f85d 7b04 ldr.w r7, [sp], #4
800317a: 4770 bx lr
0800317c <LL_ADC_StartCalibration>:
{
800317c: b480 push {r7}
800317e: b083 sub sp, #12
8003180: af00 add r7, sp, #0
8003182: 6078 str r0, [r7, #4]
8003184: 6039 str r1, [r7, #0]
MODIFY_REG(ADCx->CR,
8003186: 687b ldr r3, [r7, #4]
8003188: 689b ldr r3, [r3, #8]
800318a: f023 4340 bic.w r3, r3, #3221225472 @ 0xc0000000
800318e: f023 033f bic.w r3, r3, #63 @ 0x3f
8003192: 683a ldr r2, [r7, #0]
8003194: f002 4280 and.w r2, r2, #1073741824 @ 0x40000000
8003198: 4313 orrs r3, r2
800319a: f043 4200 orr.w r2, r3, #2147483648 @ 0x80000000
800319e: 687b ldr r3, [r7, #4]
80031a0: 609a str r2, [r3, #8]
}
80031a2: bf00 nop
80031a4: 370c adds r7, #12
80031a6: 46bd mov sp, r7
80031a8: f85d 7b04 ldr.w r7, [sp], #4
80031ac: 4770 bx lr
080031ae <LL_ADC_IsCalibrationOnGoing>:
{
80031ae: b480 push {r7}
80031b0: b083 sub sp, #12
80031b2: af00 add r7, sp, #0
80031b4: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
80031b6: 687b ldr r3, [r7, #4]
80031b8: 689b ldr r3, [r3, #8]
80031ba: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
80031be: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
80031c2: d101 bne.n 80031c8 <LL_ADC_IsCalibrationOnGoing+0x1a>
80031c4: 2301 movs r3, #1
80031c6: e000 b.n 80031ca <LL_ADC_IsCalibrationOnGoing+0x1c>
80031c8: 2300 movs r3, #0
}
80031ca: 4618 mov r0, r3
80031cc: 370c adds r7, #12
80031ce: 46bd mov sp, r7
80031d0: f85d 7b04 ldr.w r7, [sp], #4
80031d4: 4770 bx lr
080031d6 <LL_ADC_REG_IsConversionOngoing>:
{
80031d6: b480 push {r7}
80031d8: b083 sub sp, #12
80031da: af00 add r7, sp, #0
80031dc: 6078 str r0, [r7, #4]
return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
80031de: 687b ldr r3, [r7, #4]
80031e0: 689b ldr r3, [r3, #8]
80031e2: f003 0304 and.w r3, r3, #4
80031e6: 2b04 cmp r3, #4
80031e8: d101 bne.n 80031ee <LL_ADC_REG_IsConversionOngoing+0x18>
80031ea: 2301 movs r3, #1
80031ec: e000 b.n 80031f0 <LL_ADC_REG_IsConversionOngoing+0x1a>
80031ee: 2300 movs r3, #0
}
80031f0: 4618 mov r0, r3
80031f2: 370c adds r7, #12
80031f4: 46bd mov sp, r7
80031f6: f85d 7b04 ldr.w r7, [sp], #4
80031fa: 4770 bx lr
080031fc <HAL_ADCEx_Calibration_Start>:
* @arg @ref ADC_SINGLE_ENDED Channel in mode input single ended
* @arg @ref ADC_DIFFERENTIAL_ENDED Channel in mode input differential ended
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff)
{
80031fc: b580 push {r7, lr}
80031fe: b084 sub sp, #16
8003200: af00 add r7, sp, #0
8003202: 6078 str r0, [r7, #4]
8003204: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status;
__IO uint32_t wait_loop_index = 0UL;
8003206: 2300 movs r3, #0
8003208: 60bb str r3, [r7, #8]
/* Check the parameters */
assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
assert_param(IS_ADC_SINGLE_DIFFERENTIAL(SingleDiff));
/* Process locked */
__HAL_LOCK(hadc);
800320a: 687b ldr r3, [r7, #4]
800320c: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
8003210: 2b01 cmp r3, #1
8003212: d101 bne.n 8003218 <HAL_ADCEx_Calibration_Start+0x1c>
8003214: 2302 movs r3, #2
8003216: e04d b.n 80032b4 <HAL_ADCEx_Calibration_Start+0xb8>
8003218: 687b ldr r3, [r7, #4]
800321a: 2201 movs r2, #1
800321c: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Calibration prerequisite: ADC must be disabled. */
/* Disable the ADC (if not already disabled) */
tmp_hal_status = ADC_Disable(hadc);
8003220: 6878 ldr r0, [r7, #4]
8003222: f7ff fea5 bl 8002f70 <ADC_Disable>
8003226: 4603 mov r3, r0
8003228: 73fb strb r3, [r7, #15]
/* Check if ADC is effectively disabled */
if (tmp_hal_status == HAL_OK)
800322a: 7bfb ldrb r3, [r7, #15]
800322c: 2b00 cmp r3, #0
800322e: d136 bne.n 800329e <HAL_ADCEx_Calibration_Start+0xa2>
{
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
8003230: 687b ldr r3, [r7, #4]
8003232: 6ddb ldr r3, [r3, #92] @ 0x5c
8003234: f423 5388 bic.w r3, r3, #4352 @ 0x1100
8003238: f023 0302 bic.w r3, r3, #2
800323c: f043 0202 orr.w r2, r3, #2
8003240: 687b ldr r3, [r7, #4]
8003242: 65da str r2, [r3, #92] @ 0x5c
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
HAL_ADC_STATE_BUSY_INTERNAL);
/* Start ADC calibration in mode single-ended or differential */
LL_ADC_StartCalibration(hadc->Instance, SingleDiff);
8003244: 687b ldr r3, [r7, #4]
8003246: 681b ldr r3, [r3, #0]
8003248: 6839 ldr r1, [r7, #0]
800324a: 4618 mov r0, r3
800324c: f7ff ff96 bl 800317c <LL_ADC_StartCalibration>
/* Wait for calibration completion */
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
8003250: e014 b.n 800327c <HAL_ADCEx_Calibration_Start+0x80>
{
wait_loop_index++;
8003252: 68bb ldr r3, [r7, #8]
8003254: 3301 adds r3, #1
8003256: 60bb str r3, [r7, #8]
if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
8003258: 68bb ldr r3, [r7, #8]
800325a: 4a18 ldr r2, [pc, #96] @ (80032bc <HAL_ADCEx_Calibration_Start+0xc0>)
800325c: 4293 cmp r3, r2
800325e: d90d bls.n 800327c <HAL_ADCEx_Calibration_Start+0x80>
{
/* Update ADC state machine to error */
ADC_STATE_CLR_SET(hadc->State,
8003260: 687b ldr r3, [r7, #4]
8003262: 6ddb ldr r3, [r3, #92] @ 0x5c
8003264: f023 0312 bic.w r3, r3, #18
8003268: f043 0210 orr.w r2, r3, #16
800326c: 687b ldr r3, [r7, #4]
800326e: 65da str r2, [r3, #92] @ 0x5c
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_ERROR_INTERNAL);
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003270: 687b ldr r3, [r7, #4]
8003272: 2200 movs r2, #0
8003274: f883 2058 strb.w r2, [r3, #88] @ 0x58
return HAL_ERROR;
8003278: 2301 movs r3, #1
800327a: e01b b.n 80032b4 <HAL_ADCEx_Calibration_Start+0xb8>
while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
800327c: 687b ldr r3, [r7, #4]
800327e: 681b ldr r3, [r3, #0]
8003280: 4618 mov r0, r3
8003282: f7ff ff94 bl 80031ae <LL_ADC_IsCalibrationOnGoing>
8003286: 4603 mov r3, r0
8003288: 2b00 cmp r3, #0
800328a: d1e2 bne.n 8003252 <HAL_ADCEx_Calibration_Start+0x56>
}
}
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
800328c: 687b ldr r3, [r7, #4]
800328e: 6ddb ldr r3, [r3, #92] @ 0x5c
8003290: f023 0303 bic.w r3, r3, #3
8003294: f043 0201 orr.w r2, r3, #1
8003298: 687b ldr r3, [r7, #4]
800329a: 65da str r2, [r3, #92] @ 0x5c
800329c: e005 b.n 80032aa <HAL_ADCEx_Calibration_Start+0xae>
HAL_ADC_STATE_BUSY_INTERNAL,
HAL_ADC_STATE_READY);
}
else
{
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
800329e: 687b ldr r3, [r7, #4]
80032a0: 6ddb ldr r3, [r3, #92] @ 0x5c
80032a2: f043 0210 orr.w r2, r3, #16
80032a6: 687b ldr r3, [r7, #4]
80032a8: 65da str r2, [r3, #92] @ 0x5c
/* Note: No need to update variable "tmp_hal_status" here: already set */
/* to state "HAL_ERROR" by function disabling the ADC. */
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80032aa: 687b ldr r3, [r7, #4]
80032ac: 2200 movs r2, #0
80032ae: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
80032b2: 7bfb ldrb r3, [r7, #15]
}
80032b4: 4618 mov r0, r3
80032b6: 3710 adds r7, #16
80032b8: 46bd mov sp, r7
80032ba: bd80 pop {r7, pc}
80032bc: 0004de01 .word 0x0004de01
080032c0 <HAL_ADCEx_MultiModeConfigChannel>:
* @param hadc Master ADC handle
* @param pMultimode Structure of ADC multimode configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, const ADC_MultiModeTypeDef *pMultimode)
{
80032c0: b590 push {r4, r7, lr}
80032c2: b0a1 sub sp, #132 @ 0x84
80032c4: af00 add r7, sp, #0
80032c6: 6078 str r0, [r7, #4]
80032c8: 6039 str r1, [r7, #0]
HAL_StatusTypeDef tmp_hal_status = HAL_OK;
80032ca: 2300 movs r3, #0
80032cc: f887 307f strb.w r3, [r7, #127] @ 0x7f
assert_param(IS_ADC_DMA_ACCESS_MULTIMODE(pMultimode->DMAAccessMode));
assert_param(IS_ADC_SAMPLING_DELAY(pMultimode->TwoSamplingDelay));
}
/* Process locked */
__HAL_LOCK(hadc);
80032d0: 687b ldr r3, [r7, #4]
80032d2: f893 3058 ldrb.w r3, [r3, #88] @ 0x58
80032d6: 2b01 cmp r3, #1
80032d8: d101 bne.n 80032de <HAL_ADCEx_MultiModeConfigChannel+0x1e>
80032da: 2302 movs r3, #2
80032dc: e0e7 b.n 80034ae <HAL_ADCEx_MultiModeConfigChannel+0x1ee>
80032de: 687b ldr r3, [r7, #4]
80032e0: 2201 movs r2, #1
80032e2: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Temporary handle minimum initialization */
__HAL_ADC_RESET_HANDLE_STATE(&tmp_hadc_slave);
80032e6: 2300 movs r3, #0
80032e8: 667b str r3, [r7, #100] @ 0x64
ADC_CLEAR_ERRORCODE(&tmp_hadc_slave);
80032ea: 2300 movs r3, #0
80032ec: 66bb str r3, [r7, #104] @ 0x68
ADC_MULTI_SLAVE(hadc, &tmp_hadc_slave);
80032ee: 687b ldr r3, [r7, #4]
80032f0: 681b ldr r3, [r3, #0]
80032f2: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
80032f6: d102 bne.n 80032fe <HAL_ADCEx_MultiModeConfigChannel+0x3e>
80032f8: 4b6f ldr r3, [pc, #444] @ (80034b8 <HAL_ADCEx_MultiModeConfigChannel+0x1f8>)
80032fa: 60bb str r3, [r7, #8]
80032fc: e009 b.n 8003312 <HAL_ADCEx_MultiModeConfigChannel+0x52>
80032fe: 687b ldr r3, [r7, #4]
8003300: 681b ldr r3, [r3, #0]
8003302: 4a6e ldr r2, [pc, #440] @ (80034bc <HAL_ADCEx_MultiModeConfigChannel+0x1fc>)
8003304: 4293 cmp r3, r2
8003306: d102 bne.n 800330e <HAL_ADCEx_MultiModeConfigChannel+0x4e>
8003308: 4b6d ldr r3, [pc, #436] @ (80034c0 <HAL_ADCEx_MultiModeConfigChannel+0x200>)
800330a: 60bb str r3, [r7, #8]
800330c: e001 b.n 8003312 <HAL_ADCEx_MultiModeConfigChannel+0x52>
800330e: 2300 movs r3, #0
8003310: 60bb str r3, [r7, #8]
if (tmp_hadc_slave.Instance == NULL)
8003312: 68bb ldr r3, [r7, #8]
8003314: 2b00 cmp r3, #0
8003316: d10b bne.n 8003330 <HAL_ADCEx_MultiModeConfigChannel+0x70>
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
8003318: 687b ldr r3, [r7, #4]
800331a: 6ddb ldr r3, [r3, #92] @ 0x5c
800331c: f043 0220 orr.w r2, r3, #32
8003320: 687b ldr r3, [r7, #4]
8003322: 65da str r2, [r3, #92] @ 0x5c
/* Process unlocked */
__HAL_UNLOCK(hadc);
8003324: 687b ldr r3, [r7, #4]
8003326: 2200 movs r2, #0
8003328: f883 2058 strb.w r2, [r3, #88] @ 0x58
return HAL_ERROR;
800332c: 2301 movs r3, #1
800332e: e0be b.n 80034ae <HAL_ADCEx_MultiModeConfigChannel+0x1ee>
/* Parameters update conditioned to ADC state: */
/* Parameters that can be updated when ADC is disabled or enabled without */
/* conversion on going on regular group: */
/* - Multimode DMA configuration */
/* - Multimode DMA mode */
tmp_hadc_slave_conversion_on_going = LL_ADC_REG_IsConversionOngoing((&tmp_hadc_slave)->Instance);
8003330: 68bb ldr r3, [r7, #8]
8003332: 4618 mov r0, r3
8003334: f7ff ff4f bl 80031d6 <LL_ADC_REG_IsConversionOngoing>
8003338: 67b8 str r0, [r7, #120] @ 0x78
if ((LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
800333a: 687b ldr r3, [r7, #4]
800333c: 681b ldr r3, [r3, #0]
800333e: 4618 mov r0, r3
8003340: f7ff ff49 bl 80031d6 <LL_ADC_REG_IsConversionOngoing>
8003344: 4603 mov r3, r0
8003346: 2b00 cmp r3, #0
8003348: f040 80a0 bne.w 800348c <HAL_ADCEx_MultiModeConfigChannel+0x1cc>
&& (tmp_hadc_slave_conversion_on_going == 0UL))
800334c: 6fbb ldr r3, [r7, #120] @ 0x78
800334e: 2b00 cmp r3, #0
8003350: f040 809c bne.w 800348c <HAL_ADCEx_MultiModeConfigChannel+0x1cc>
{
/* Pointer to the common control register */
tmpADC_Common = __LL_ADC_COMMON_INSTANCE(hadc->Instance);
8003354: 687b ldr r3, [r7, #4]
8003356: 681b ldr r3, [r3, #0]
8003358: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
800335c: d004 beq.n 8003368 <HAL_ADCEx_MultiModeConfigChannel+0xa8>
800335e: 687b ldr r3, [r7, #4]
8003360: 681b ldr r3, [r3, #0]
8003362: 4a55 ldr r2, [pc, #340] @ (80034b8 <HAL_ADCEx_MultiModeConfigChannel+0x1f8>)
8003364: 4293 cmp r3, r2
8003366: d101 bne.n 800336c <HAL_ADCEx_MultiModeConfigChannel+0xac>
8003368: 4b56 ldr r3, [pc, #344] @ (80034c4 <HAL_ADCEx_MultiModeConfigChannel+0x204>)
800336a: e000 b.n 800336e <HAL_ADCEx_MultiModeConfigChannel+0xae>
800336c: 4b56 ldr r3, [pc, #344] @ (80034c8 <HAL_ADCEx_MultiModeConfigChannel+0x208>)
800336e: 677b str r3, [r7, #116] @ 0x74
/* If multimode is selected, configure all multimode parameters. */
/* Otherwise, reset multimode parameters (can be used in case of */
/* transition from multimode to independent mode). */
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
8003370: 683b ldr r3, [r7, #0]
8003372: 681b ldr r3, [r3, #0]
8003374: 2b00 cmp r3, #0
8003376: d04b beq.n 8003410 <HAL_ADCEx_MultiModeConfigChannel+0x150>
{
MODIFY_REG(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG,
8003378: 6f7b ldr r3, [r7, #116] @ 0x74
800337a: 689b ldr r3, [r3, #8]
800337c: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8003380: 683b ldr r3, [r7, #0]
8003382: 6859 ldr r1, [r3, #4]
8003384: 687b ldr r3, [r7, #4]
8003386: f893 3038 ldrb.w r3, [r3, #56] @ 0x38
800338a: 035b lsls r3, r3, #13
800338c: 430b orrs r3, r1
800338e: 431a orrs r2, r3
8003390: 6f7b ldr r3, [r7, #116] @ 0x74
8003392: 609a str r2, [r3, #8]
/* from 1 to 10 clock cycles for 10 bits, */
/* from 1 to 8 clock cycles for 8 bits */
/* from 1 to 6 clock cycles for 6 bits */
/* If a higher delay is selected, it will be clipped to maximum delay */
/* range */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
8003394: 687b ldr r3, [r7, #4]
8003396: 681b ldr r3, [r3, #0]
8003398: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
800339c: d004 beq.n 80033a8 <HAL_ADCEx_MultiModeConfigChannel+0xe8>
800339e: 687b ldr r3, [r7, #4]
80033a0: 681b ldr r3, [r3, #0]
80033a2: 4a45 ldr r2, [pc, #276] @ (80034b8 <HAL_ADCEx_MultiModeConfigChannel+0x1f8>)
80033a4: 4293 cmp r3, r2
80033a6: d10f bne.n 80033c8 <HAL_ADCEx_MultiModeConfigChannel+0x108>
80033a8: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
80033ac: f7ff fed3 bl 8003156 <LL_ADC_IsEnabled>
80033b0: 4604 mov r4, r0
80033b2: 4841 ldr r0, [pc, #260] @ (80034b8 <HAL_ADCEx_MultiModeConfigChannel+0x1f8>)
80033b4: f7ff fecf bl 8003156 <LL_ADC_IsEnabled>
80033b8: 4603 mov r3, r0
80033ba: 4323 orrs r3, r4
80033bc: 2b00 cmp r3, #0
80033be: bf0c ite eq
80033c0: 2301 moveq r3, #1
80033c2: 2300 movne r3, #0
80033c4: b2db uxtb r3, r3
80033c6: e012 b.n 80033ee <HAL_ADCEx_MultiModeConfigChannel+0x12e>
80033c8: 483c ldr r0, [pc, #240] @ (80034bc <HAL_ADCEx_MultiModeConfigChannel+0x1fc>)
80033ca: f7ff fec4 bl 8003156 <LL_ADC_IsEnabled>
80033ce: 4604 mov r4, r0
80033d0: 483b ldr r0, [pc, #236] @ (80034c0 <HAL_ADCEx_MultiModeConfigChannel+0x200>)
80033d2: f7ff fec0 bl 8003156 <LL_ADC_IsEnabled>
80033d6: 4603 mov r3, r0
80033d8: 431c orrs r4, r3
80033da: 483c ldr r0, [pc, #240] @ (80034cc <HAL_ADCEx_MultiModeConfigChannel+0x20c>)
80033dc: f7ff febb bl 8003156 <LL_ADC_IsEnabled>
80033e0: 4603 mov r3, r0
80033e2: 4323 orrs r3, r4
80033e4: 2b00 cmp r3, #0
80033e6: bf0c ite eq
80033e8: 2301 moveq r3, #1
80033ea: 2300 movne r3, #0
80033ec: b2db uxtb r3, r3
80033ee: 2b00 cmp r3, #0
80033f0: d056 beq.n 80034a0 <HAL_ADCEx_MultiModeConfigChannel+0x1e0>
{
MODIFY_REG(tmpADC_Common->CCR,
80033f2: 6f7b ldr r3, [r7, #116] @ 0x74
80033f4: 689b ldr r3, [r3, #8]
80033f6: f423 6371 bic.w r3, r3, #3856 @ 0xf10
80033fa: f023 030f bic.w r3, r3, #15
80033fe: 683a ldr r2, [r7, #0]
8003400: 6811 ldr r1, [r2, #0]
8003402: 683a ldr r2, [r7, #0]
8003404: 6892 ldr r2, [r2, #8]
8003406: 430a orrs r2, r1
8003408: 431a orrs r2, r3
800340a: 6f7b ldr r3, [r7, #116] @ 0x74
800340c: 609a str r2, [r3, #8]
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
800340e: e047 b.n 80034a0 <HAL_ADCEx_MultiModeConfigChannel+0x1e0>
);
}
}
else /* ADC_MODE_INDEPENDENT */
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_MDMA | ADC_CCR_DMACFG);
8003410: 6f7b ldr r3, [r7, #116] @ 0x74
8003412: 689b ldr r3, [r3, #8]
8003414: f423 4260 bic.w r2, r3, #57344 @ 0xe000
8003418: 6f7b ldr r3, [r7, #116] @ 0x74
800341a: 609a str r2, [r3, #8]
/* Parameters that can be updated only when ADC is disabled: */
/* - Multimode mode selection */
/* - Multimode delay */
if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
800341c: 687b ldr r3, [r7, #4]
800341e: 681b ldr r3, [r3, #0]
8003420: f1b3 4fa0 cmp.w r3, #1342177280 @ 0x50000000
8003424: d004 beq.n 8003430 <HAL_ADCEx_MultiModeConfigChannel+0x170>
8003426: 687b ldr r3, [r7, #4]
8003428: 681b ldr r3, [r3, #0]
800342a: 4a23 ldr r2, [pc, #140] @ (80034b8 <HAL_ADCEx_MultiModeConfigChannel+0x1f8>)
800342c: 4293 cmp r3, r2
800342e: d10f bne.n 8003450 <HAL_ADCEx_MultiModeConfigChannel+0x190>
8003430: f04f 40a0 mov.w r0, #1342177280 @ 0x50000000
8003434: f7ff fe8f bl 8003156 <LL_ADC_IsEnabled>
8003438: 4604 mov r4, r0
800343a: 481f ldr r0, [pc, #124] @ (80034b8 <HAL_ADCEx_MultiModeConfigChannel+0x1f8>)
800343c: f7ff fe8b bl 8003156 <LL_ADC_IsEnabled>
8003440: 4603 mov r3, r0
8003442: 4323 orrs r3, r4
8003444: 2b00 cmp r3, #0
8003446: bf0c ite eq
8003448: 2301 moveq r3, #1
800344a: 2300 movne r3, #0
800344c: b2db uxtb r3, r3
800344e: e012 b.n 8003476 <HAL_ADCEx_MultiModeConfigChannel+0x1b6>
8003450: 481a ldr r0, [pc, #104] @ (80034bc <HAL_ADCEx_MultiModeConfigChannel+0x1fc>)
8003452: f7ff fe80 bl 8003156 <LL_ADC_IsEnabled>
8003456: 4604 mov r4, r0
8003458: 4819 ldr r0, [pc, #100] @ (80034c0 <HAL_ADCEx_MultiModeConfigChannel+0x200>)
800345a: f7ff fe7c bl 8003156 <LL_ADC_IsEnabled>
800345e: 4603 mov r3, r0
8003460: 431c orrs r4, r3
8003462: 481a ldr r0, [pc, #104] @ (80034cc <HAL_ADCEx_MultiModeConfigChannel+0x20c>)
8003464: f7ff fe77 bl 8003156 <LL_ADC_IsEnabled>
8003468: 4603 mov r3, r0
800346a: 4323 orrs r3, r4
800346c: 2b00 cmp r3, #0
800346e: bf0c ite eq
8003470: 2301 moveq r3, #1
8003472: 2300 movne r3, #0
8003474: b2db uxtb r3, r3
8003476: 2b00 cmp r3, #0
8003478: d012 beq.n 80034a0 <HAL_ADCEx_MultiModeConfigChannel+0x1e0>
{
CLEAR_BIT(tmpADC_Common->CCR, ADC_CCR_DUAL | ADC_CCR_DELAY);
800347a: 6f7b ldr r3, [r7, #116] @ 0x74
800347c: 689b ldr r3, [r3, #8]
800347e: f423 6371 bic.w r3, r3, #3856 @ 0xf10
8003482: f023 030f bic.w r3, r3, #15
8003486: 6f7a ldr r2, [r7, #116] @ 0x74
8003488: 6093 str r3, [r2, #8]
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
800348a: e009 b.n 80034a0 <HAL_ADCEx_MultiModeConfigChannel+0x1e0>
/* If one of the ADC sharing the same common group is enabled, no update */
/* could be done on neither of the multimode structure parameters. */
else
{
/* Update ADC state machine to error */
SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
800348c: 687b ldr r3, [r7, #4]
800348e: 6ddb ldr r3, [r3, #92] @ 0x5c
8003490: f043 0220 orr.w r2, r3, #32
8003494: 687b ldr r3, [r7, #4]
8003496: 65da str r2, [r3, #92] @ 0x5c
tmp_hal_status = HAL_ERROR;
8003498: 2301 movs r3, #1
800349a: f887 307f strb.w r3, [r7, #127] @ 0x7f
800349e: e000 b.n 80034a2 <HAL_ADCEx_MultiModeConfigChannel+0x1e2>
if (pMultimode->Mode != ADC_MODE_INDEPENDENT)
80034a0: bf00 nop
}
/* Process unlocked */
__HAL_UNLOCK(hadc);
80034a2: 687b ldr r3, [r7, #4]
80034a4: 2200 movs r2, #0
80034a6: f883 2058 strb.w r2, [r3, #88] @ 0x58
/* Return function status */
return tmp_hal_status;
80034aa: f897 307f ldrb.w r3, [r7, #127] @ 0x7f
}
80034ae: 4618 mov r0, r3
80034b0: 3784 adds r7, #132 @ 0x84
80034b2: 46bd mov sp, r7
80034b4: bd90 pop {r4, r7, pc}
80034b6: bf00 nop
80034b8: 50000100 .word 0x50000100
80034bc: 50000400 .word 0x50000400
80034c0: 50000500 .word 0x50000500
80034c4: 50000300 .word 0x50000300
80034c8: 50000700 .word 0x50000700
80034cc: 50000600 .word 0x50000600
080034d0 <LL_EXTI_EnableIT_0_31>:
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)
{
80034d0: b480 push {r7}
80034d2: b083 sub sp, #12
80034d4: af00 add r7, sp, #0
80034d6: 6078 str r0, [r7, #4]
SET_BIT(EXTI->IMR1, ExtiLine);
80034d8: 4b05 ldr r3, [pc, #20] @ (80034f0 <LL_EXTI_EnableIT_0_31+0x20>)
80034da: 681a ldr r2, [r3, #0]
80034dc: 4904 ldr r1, [pc, #16] @ (80034f0 <LL_EXTI_EnableIT_0_31+0x20>)
80034de: 687b ldr r3, [r7, #4]
80034e0: 4313 orrs r3, r2
80034e2: 600b str r3, [r1, #0]
}
80034e4: bf00 nop
80034e6: 370c adds r7, #12
80034e8: 46bd mov sp, r7
80034ea: f85d 7b04 ldr.w r7, [sp], #4
80034ee: 4770 bx lr
80034f0: 40010400 .word 0x40010400
080034f4 <LL_EXTI_EnableIT_32_63>:
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)
{
80034f4: b480 push {r7}
80034f6: b083 sub sp, #12
80034f8: af00 add r7, sp, #0
80034fa: 6078 str r0, [r7, #4]
SET_BIT(EXTI->IMR2, ExtiLine);
80034fc: 4b05 ldr r3, [pc, #20] @ (8003514 <LL_EXTI_EnableIT_32_63+0x20>)
80034fe: 6a1a ldr r2, [r3, #32]
8003500: 4904 ldr r1, [pc, #16] @ (8003514 <LL_EXTI_EnableIT_32_63+0x20>)
8003502: 687b ldr r3, [r7, #4]
8003504: 4313 orrs r3, r2
8003506: 620b str r3, [r1, #32]
}
8003508: bf00 nop
800350a: 370c adds r7, #12
800350c: 46bd mov sp, r7
800350e: f85d 7b04 ldr.w r7, [sp], #4
8003512: 4770 bx lr
8003514: 40010400 .word 0x40010400
08003518 <LL_EXTI_DisableIT_0_31>:
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)
{
8003518: b480 push {r7}
800351a: b083 sub sp, #12
800351c: af00 add r7, sp, #0
800351e: 6078 str r0, [r7, #4]
CLEAR_BIT(EXTI->IMR1, ExtiLine);
8003520: 4b06 ldr r3, [pc, #24] @ (800353c <LL_EXTI_DisableIT_0_31+0x24>)
8003522: 681a ldr r2, [r3, #0]
8003524: 687b ldr r3, [r7, #4]
8003526: 43db mvns r3, r3
8003528: 4904 ldr r1, [pc, #16] @ (800353c <LL_EXTI_DisableIT_0_31+0x24>)
800352a: 4013 ands r3, r2
800352c: 600b str r3, [r1, #0]
}
800352e: bf00 nop
8003530: 370c adds r7, #12
8003532: 46bd mov sp, r7
8003534: f85d 7b04 ldr.w r7, [sp], #4
8003538: 4770 bx lr
800353a: bf00 nop
800353c: 40010400 .word 0x40010400
08003540 <LL_EXTI_DisableIT_32_63>:
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)
{
8003540: b480 push {r7}
8003542: b083 sub sp, #12
8003544: af00 add r7, sp, #0
8003546: 6078 str r0, [r7, #4]
CLEAR_BIT(EXTI->IMR2, ExtiLine);
8003548: 4b06 ldr r3, [pc, #24] @ (8003564 <LL_EXTI_DisableIT_32_63+0x24>)
800354a: 6a1a ldr r2, [r3, #32]
800354c: 687b ldr r3, [r7, #4]
800354e: 43db mvns r3, r3
8003550: 4904 ldr r1, [pc, #16] @ (8003564 <LL_EXTI_DisableIT_32_63+0x24>)
8003552: 4013 ands r3, r2
8003554: 620b str r3, [r1, #32]
}
8003556: bf00 nop
8003558: 370c adds r7, #12
800355a: 46bd mov sp, r7
800355c: f85d 7b04 ldr.w r7, [sp], #4
8003560: 4770 bx lr
8003562: bf00 nop
8003564: 40010400 .word 0x40010400
08003568 <LL_EXTI_EnableEvent_0_31>:
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)
{
8003568: b480 push {r7}
800356a: b083 sub sp, #12
800356c: af00 add r7, sp, #0
800356e: 6078 str r0, [r7, #4]
SET_BIT(EXTI->EMR1, ExtiLine);
8003570: 4b05 ldr r3, [pc, #20] @ (8003588 <LL_EXTI_EnableEvent_0_31+0x20>)
8003572: 685a ldr r2, [r3, #4]
8003574: 4904 ldr r1, [pc, #16] @ (8003588 <LL_EXTI_EnableEvent_0_31+0x20>)
8003576: 687b ldr r3, [r7, #4]
8003578: 4313 orrs r3, r2
800357a: 604b str r3, [r1, #4]
}
800357c: bf00 nop
800357e: 370c adds r7, #12
8003580: 46bd mov sp, r7
8003582: f85d 7b04 ldr.w r7, [sp], #4
8003586: 4770 bx lr
8003588: 40010400 .word 0x40010400
0800358c <LL_EXTI_EnableEvent_32_63>:
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)
{
800358c: b480 push {r7}
800358e: b083 sub sp, #12
8003590: af00 add r7, sp, #0
8003592: 6078 str r0, [r7, #4]
SET_BIT(EXTI->EMR2, ExtiLine);
8003594: 4b05 ldr r3, [pc, #20] @ (80035ac <LL_EXTI_EnableEvent_32_63+0x20>)
8003596: 6a5a ldr r2, [r3, #36] @ 0x24
8003598: 4904 ldr r1, [pc, #16] @ (80035ac <LL_EXTI_EnableEvent_32_63+0x20>)
800359a: 687b ldr r3, [r7, #4]
800359c: 4313 orrs r3, r2
800359e: 624b str r3, [r1, #36] @ 0x24
}
80035a0: bf00 nop
80035a2: 370c adds r7, #12
80035a4: 46bd mov sp, r7
80035a6: f85d 7b04 ldr.w r7, [sp], #4
80035aa: 4770 bx lr
80035ac: 40010400 .word 0x40010400
080035b0 <LL_EXTI_DisableEvent_0_31>:
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)
{
80035b0: b480 push {r7}
80035b2: b083 sub sp, #12
80035b4: af00 add r7, sp, #0
80035b6: 6078 str r0, [r7, #4]
CLEAR_BIT(EXTI->EMR1, ExtiLine);
80035b8: 4b06 ldr r3, [pc, #24] @ (80035d4 <LL_EXTI_DisableEvent_0_31+0x24>)
80035ba: 685a ldr r2, [r3, #4]
80035bc: 687b ldr r3, [r7, #4]
80035be: 43db mvns r3, r3
80035c0: 4904 ldr r1, [pc, #16] @ (80035d4 <LL_EXTI_DisableEvent_0_31+0x24>)
80035c2: 4013 ands r3, r2
80035c4: 604b str r3, [r1, #4]
}
80035c6: bf00 nop
80035c8: 370c adds r7, #12
80035ca: 46bd mov sp, r7
80035cc: f85d 7b04 ldr.w r7, [sp], #4
80035d0: 4770 bx lr
80035d2: bf00 nop
80035d4: 40010400 .word 0x40010400
080035d8 <LL_EXTI_DisableEvent_32_63>:
* @arg @ref LL_EXTI_LINE_ALL_32_63
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)
{
80035d8: b480 push {r7}
80035da: b083 sub sp, #12
80035dc: af00 add r7, sp, #0
80035de: 6078 str r0, [r7, #4]
CLEAR_BIT(EXTI->EMR2, ExtiLine);
80035e0: 4b06 ldr r3, [pc, #24] @ (80035fc <LL_EXTI_DisableEvent_32_63+0x24>)
80035e2: 6a5a ldr r2, [r3, #36] @ 0x24
80035e4: 687b ldr r3, [r7, #4]
80035e6: 43db mvns r3, r3
80035e8: 4904 ldr r1, [pc, #16] @ (80035fc <LL_EXTI_DisableEvent_32_63+0x24>)
80035ea: 4013 ands r3, r2
80035ec: 624b str r3, [r1, #36] @ 0x24
}
80035ee: bf00 nop
80035f0: 370c adds r7, #12
80035f2: 46bd mov sp, r7
80035f4: f85d 7b04 ldr.w r7, [sp], #4
80035f8: 4770 bx lr
80035fa: bf00 nop
80035fc: 40010400 .word 0x40010400
08003600 <LL_EXTI_EnableRisingTrig_0_31>:
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)
{
8003600: b480 push {r7}
8003602: b083 sub sp, #12
8003604: af00 add r7, sp, #0
8003606: 6078 str r0, [r7, #4]
SET_BIT(EXTI->RTSR1, ExtiLine);
8003608: 4b05 ldr r3, [pc, #20] @ (8003620 <LL_EXTI_EnableRisingTrig_0_31+0x20>)
800360a: 689a ldr r2, [r3, #8]
800360c: 4904 ldr r1, [pc, #16] @ (8003620 <LL_EXTI_EnableRisingTrig_0_31+0x20>)
800360e: 687b ldr r3, [r7, #4]
8003610: 4313 orrs r3, r2
8003612: 608b str r3, [r1, #8]
}
8003614: bf00 nop
8003616: 370c adds r7, #12
8003618: 46bd mov sp, r7
800361a: f85d 7b04 ldr.w r7, [sp], #4
800361e: 4770 bx lr
8003620: 40010400 .word 0x40010400
08003624 <LL_EXTI_EnableRisingTrig_32_63>:
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)
{
8003624: b480 push {r7}
8003626: b083 sub sp, #12
8003628: af00 add r7, sp, #0
800362a: 6078 str r0, [r7, #4]
SET_BIT(EXTI->RTSR2, ExtiLine);
800362c: 4b05 ldr r3, [pc, #20] @ (8003644 <LL_EXTI_EnableRisingTrig_32_63+0x20>)
800362e: 6a9a ldr r2, [r3, #40] @ 0x28
8003630: 4904 ldr r1, [pc, #16] @ (8003644 <LL_EXTI_EnableRisingTrig_32_63+0x20>)
8003632: 687b ldr r3, [r7, #4]
8003634: 4313 orrs r3, r2
8003636: 628b str r3, [r1, #40] @ 0x28
}
8003638: bf00 nop
800363a: 370c adds r7, #12
800363c: 46bd mov sp, r7
800363e: f85d 7b04 ldr.w r7, [sp], #4
8003642: 4770 bx lr
8003644: 40010400 .word 0x40010400
08003648 <LL_EXTI_DisableRisingTrig_0_31>:
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)
{
8003648: b480 push {r7}
800364a: b083 sub sp, #12
800364c: af00 add r7, sp, #0
800364e: 6078 str r0, [r7, #4]
CLEAR_BIT(EXTI->RTSR1, ExtiLine);
8003650: 4b06 ldr r3, [pc, #24] @ (800366c <LL_EXTI_DisableRisingTrig_0_31+0x24>)
8003652: 689a ldr r2, [r3, #8]
8003654: 687b ldr r3, [r7, #4]
8003656: 43db mvns r3, r3
8003658: 4904 ldr r1, [pc, #16] @ (800366c <LL_EXTI_DisableRisingTrig_0_31+0x24>)
800365a: 4013 ands r3, r2
800365c: 608b str r3, [r1, #8]
}
800365e: bf00 nop
8003660: 370c adds r7, #12
8003662: 46bd mov sp, r7
8003664: f85d 7b04 ldr.w r7, [sp], #4
8003668: 4770 bx lr
800366a: bf00 nop
800366c: 40010400 .word 0x40010400
08003670 <LL_EXTI_DisableRisingTrig_32_63>:
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)
{
8003670: b480 push {r7}
8003672: b083 sub sp, #12
8003674: af00 add r7, sp, #0
8003676: 6078 str r0, [r7, #4]
CLEAR_BIT(EXTI->RTSR2, ExtiLine);
8003678: 4b06 ldr r3, [pc, #24] @ (8003694 <LL_EXTI_DisableRisingTrig_32_63+0x24>)
800367a: 6a9a ldr r2, [r3, #40] @ 0x28
800367c: 687b ldr r3, [r7, #4]
800367e: 43db mvns r3, r3
8003680: 4904 ldr r1, [pc, #16] @ (8003694 <LL_EXTI_DisableRisingTrig_32_63+0x24>)
8003682: 4013 ands r3, r2
8003684: 628b str r3, [r1, #40] @ 0x28
}
8003686: bf00 nop
8003688: 370c adds r7, #12
800368a: 46bd mov sp, r7
800368c: f85d 7b04 ldr.w r7, [sp], #4
8003690: 4770 bx lr
8003692: bf00 nop
8003694: 40010400 .word 0x40010400
08003698 <LL_EXTI_EnableFallingTrig_0_31>:
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)
{
8003698: b480 push {r7}
800369a: b083 sub sp, #12
800369c: af00 add r7, sp, #0
800369e: 6078 str r0, [r7, #4]
SET_BIT(EXTI->FTSR1, ExtiLine);
80036a0: 4b05 ldr r3, [pc, #20] @ (80036b8 <LL_EXTI_EnableFallingTrig_0_31+0x20>)
80036a2: 68da ldr r2, [r3, #12]
80036a4: 4904 ldr r1, [pc, #16] @ (80036b8 <LL_EXTI_EnableFallingTrig_0_31+0x20>)
80036a6: 687b ldr r3, [r7, #4]
80036a8: 4313 orrs r3, r2
80036aa: 60cb str r3, [r1, #12]
}
80036ac: bf00 nop
80036ae: 370c adds r7, #12
80036b0: 46bd mov sp, r7
80036b2: f85d 7b04 ldr.w r7, [sp], #4
80036b6: 4770 bx lr
80036b8: 40010400 .word 0x40010400
080036bc <LL_EXTI_EnableFallingTrig_32_63>:
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)
{
80036bc: b480 push {r7}
80036be: b083 sub sp, #12
80036c0: af00 add r7, sp, #0
80036c2: 6078 str r0, [r7, #4]
SET_BIT(EXTI->FTSR2, ExtiLine);
80036c4: 4b05 ldr r3, [pc, #20] @ (80036dc <LL_EXTI_EnableFallingTrig_32_63+0x20>)
80036c6: 6ada ldr r2, [r3, #44] @ 0x2c
80036c8: 4904 ldr r1, [pc, #16] @ (80036dc <LL_EXTI_EnableFallingTrig_32_63+0x20>)
80036ca: 687b ldr r3, [r7, #4]
80036cc: 4313 orrs r3, r2
80036ce: 62cb str r3, [r1, #44] @ 0x2c
}
80036d0: bf00 nop
80036d2: 370c adds r7, #12
80036d4: 46bd mov sp, r7
80036d6: f85d 7b04 ldr.w r7, [sp], #4
80036da: 4770 bx lr
80036dc: 40010400 .word 0x40010400
080036e0 <LL_EXTI_DisableFallingTrig_0_31>:
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)
{
80036e0: b480 push {r7}
80036e2: b083 sub sp, #12
80036e4: af00 add r7, sp, #0
80036e6: 6078 str r0, [r7, #4]
CLEAR_BIT(EXTI->FTSR1, ExtiLine);
80036e8: 4b06 ldr r3, [pc, #24] @ (8003704 <LL_EXTI_DisableFallingTrig_0_31+0x24>)
80036ea: 68da ldr r2, [r3, #12]
80036ec: 687b ldr r3, [r7, #4]
80036ee: 43db mvns r3, r3
80036f0: 4904 ldr r1, [pc, #16] @ (8003704 <LL_EXTI_DisableFallingTrig_0_31+0x24>)
80036f2: 4013 ands r3, r2
80036f4: 60cb str r3, [r1, #12]
}
80036f6: bf00 nop
80036f8: 370c adds r7, #12
80036fa: 46bd mov sp, r7
80036fc: f85d 7b04 ldr.w r7, [sp], #4
8003700: 4770 bx lr
8003702: bf00 nop
8003704: 40010400 .word 0x40010400
08003708 <LL_EXTI_DisableFallingTrig_32_63>:
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)
{
8003708: b480 push {r7}
800370a: b083 sub sp, #12
800370c: af00 add r7, sp, #0
800370e: 6078 str r0, [r7, #4]
CLEAR_BIT(EXTI->FTSR2, ExtiLine);
8003710: 4b06 ldr r3, [pc, #24] @ (800372c <LL_EXTI_DisableFallingTrig_32_63+0x24>)
8003712: 6ada ldr r2, [r3, #44] @ 0x2c
8003714: 687b ldr r3, [r7, #4]
8003716: 43db mvns r3, r3
8003718: 4904 ldr r1, [pc, #16] @ (800372c <LL_EXTI_DisableFallingTrig_32_63+0x24>)
800371a: 4013 ands r3, r2
800371c: 62cb str r3, [r1, #44] @ 0x2c
}
800371e: bf00 nop
8003720: 370c adds r7, #12
8003722: 46bd mov sp, r7
8003724: f85d 7b04 ldr.w r7, [sp], #4
8003728: 4770 bx lr
800372a: bf00 nop
800372c: 40010400 .word 0x40010400
08003730 <LL_EXTI_IsActiveFlag_0_31>:
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)
{
8003730: b480 push {r7}
8003732: b083 sub sp, #12
8003734: af00 add r7, sp, #0
8003736: 6078 str r0, [r7, #4]
return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
8003738: 4b07 ldr r3, [pc, #28] @ (8003758 <LL_EXTI_IsActiveFlag_0_31+0x28>)
800373a: 695a ldr r2, [r3, #20]
800373c: 687b ldr r3, [r7, #4]
800373e: 4013 ands r3, r2
8003740: 687a ldr r2, [r7, #4]
8003742: 429a cmp r2, r3
8003744: d101 bne.n 800374a <LL_EXTI_IsActiveFlag_0_31+0x1a>
8003746: 2301 movs r3, #1
8003748: e000 b.n 800374c <LL_EXTI_IsActiveFlag_0_31+0x1c>
800374a: 2300 movs r3, #0
}
800374c: 4618 mov r0, r3
800374e: 370c adds r7, #12
8003750: 46bd mov sp, r7
8003752: f85d 7b04 ldr.w r7, [sp], #4
8003756: 4770 bx lr
8003758: 40010400 .word 0x40010400
0800375c <LL_EXTI_IsActiveFlag_32_63>:
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval State of bit (1 or 0).
*/
__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)
{
800375c: b480 push {r7}
800375e: b083 sub sp, #12
8003760: af00 add r7, sp, #0
8003762: 6078 str r0, [r7, #4]
return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1UL : 0UL);
8003764: 4b07 ldr r3, [pc, #28] @ (8003784 <LL_EXTI_IsActiveFlag_32_63+0x28>)
8003766: 6b5a ldr r2, [r3, #52] @ 0x34
8003768: 687b ldr r3, [r7, #4]
800376a: 4013 ands r3, r2
800376c: 687a ldr r2, [r7, #4]
800376e: 429a cmp r2, r3
8003770: d101 bne.n 8003776 <LL_EXTI_IsActiveFlag_32_63+0x1a>
8003772: 2301 movs r3, #1
8003774: e000 b.n 8003778 <LL_EXTI_IsActiveFlag_32_63+0x1c>
8003776: 2300 movs r3, #0
}
8003778: 4618 mov r0, r3
800377a: 370c adds r7, #12
800377c: 46bd mov sp, r7
800377e: f85d 7b04 ldr.w r7, [sp], #4
8003782: 4770 bx lr
8003784: 40010400 .word 0x40010400
08003788 <LL_EXTI_ClearFlag_0_31>:
* @note (*): Available in some devices
* @note Please check each device line mapping for EXTI Line availability
* @retval None
*/
__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)
{
8003788: b480 push {r7}
800378a: b083 sub sp, #12
800378c: af00 add r7, sp, #0
800378e: 6078 str r0, [r7, #4]
WRITE_REG(EXTI->PR1, ExtiLine);
8003790: 4a04 ldr r2, [pc, #16] @ (80037a4 <LL_EXTI_ClearFlag_0_31+0x1c>)
8003792: 687b ldr r3, [r7, #4]
8003794: 6153 str r3, [r2, #20]
}
8003796: bf00 nop
8003798: 370c adds r7, #12
800379a: 46bd mov sp, r7
800379c: f85d 7b04 ldr.w r7, [sp], #4
80037a0: 4770 bx lr
80037a2: bf00 nop
80037a4: 40010400 .word 0x40010400
080037a8 <LL_EXTI_ClearFlag_32_63>:
* @arg @ref LL_EXTI_LINE_41
* @note (*): Available in some devices
* @retval None
*/
__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)
{
80037a8: b480 push {r7}
80037aa: b083 sub sp, #12
80037ac: af00 add r7, sp, #0
80037ae: 6078 str r0, [r7, #4]
WRITE_REG(EXTI->PR2, ExtiLine);
80037b0: 4a04 ldr r2, [pc, #16] @ (80037c4 <LL_EXTI_ClearFlag_32_63+0x1c>)
80037b2: 687b ldr r3, [r7, #4]
80037b4: 6353 str r3, [r2, #52] @ 0x34
}
80037b6: bf00 nop
80037b8: 370c adds r7, #12
80037ba: 46bd mov sp, r7
80037bc: f85d 7b04 ldr.w r7, [sp], #4
80037c0: 4770 bx lr
80037c2: bf00 nop
80037c4: 40010400 .word 0x40010400
080037c8 <HAL_COMP_Init>:
* To unlock the configuration, perform a system reset.
* @param hcomp COMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{
80037c8: b580 push {r7, lr}
80037ca: b088 sub sp, #32
80037cc: af00 add r7, sp, #0
80037ce: 6078 str r0, [r7, #4]
uint32_t tmp_csr;
uint32_t exti_line;
uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */
__IO uint32_t wait_loop_index = 0UL;
80037d0: 2300 movs r3, #0
80037d2: 60fb str r3, [r7, #12]
HAL_StatusTypeDef status = HAL_OK;
80037d4: 2300 movs r3, #0
80037d6: 77fb strb r3, [r7, #31]
/* Check the COMP handle allocation and lock status */
if (hcomp == NULL)
80037d8: 687b ldr r3, [r7, #4]
80037da: 2b00 cmp r3, #0
80037dc: d102 bne.n 80037e4 <HAL_COMP_Init+0x1c>
{
status = HAL_ERROR;
80037de: 2301 movs r3, #1
80037e0: 77fb strb r3, [r7, #31]
80037e2: e181 b.n 8003ae8 <HAL_COMP_Init+0x320>
}
else if (__HAL_COMP_IS_LOCKED(hcomp))
80037e4: 687b ldr r3, [r7, #4]
80037e6: 681b ldr r3, [r3, #0]
80037e8: 681b ldr r3, [r3, #0]
80037ea: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
80037ee: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
80037f2: d102 bne.n 80037fa <HAL_COMP_Init+0x32>
{
status = HAL_ERROR;
80037f4: 2301 movs r3, #1
80037f6: 77fb strb r3, [r7, #31]
80037f8: e176 b.n 8003ae8 <HAL_COMP_Init+0x320>
assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
if (hcomp->State == HAL_COMP_STATE_RESET)
80037fa: 687b ldr r3, [r7, #4]
80037fc: 7f5b ldrb r3, [r3, #29]
80037fe: b2db uxtb r3, r3
8003800: 2b00 cmp r3, #0
8003802: d108 bne.n 8003816 <HAL_COMP_Init+0x4e>
{
/* Allocate lock resource and initialize it */
hcomp->Lock = HAL_UNLOCKED;
8003804: 687b ldr r3, [r7, #4]
8003806: 2200 movs r2, #0
8003808: 771a strb r2, [r3, #28]
/* Set COMP error code to none */
COMP_CLEAR_ERRORCODE(hcomp);
800380a: 687b ldr r3, [r7, #4]
800380c: 2200 movs r2, #0
800380e: 621a str r2, [r3, #32]
#else
/* Init the low level hardware */
/* Note: Internal control clock of the comparators must */
/* be enabled in "HAL_COMP_MspInit()" */
/* using "__HAL_RCC_SYSCFG_CLK_ENABLE()". */
HAL_COMP_MspInit(hcomp);
8003810: 6878 ldr r0, [r7, #4]
8003812: f7fd fe71 bl 80014f8 <HAL_COMP_MspInit>
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
/* Memorize voltage scaler state before initialization */
comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN);
8003816: 687b ldr r3, [r7, #4]
8003818: 681b ldr r3, [r3, #0]
800381a: 681b ldr r3, [r3, #0]
800381c: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8003820: 61bb str r3, [r7, #24]
/* Set COMP parameters */
tmp_csr = (hcomp->Init.InputMinus
8003822: 687b ldr r3, [r7, #4]
8003824: 689a ldr r2, [r3, #8]
| hcomp->Init.InputPlus
8003826: 687b ldr r3, [r7, #4]
8003828: 685b ldr r3, [r3, #4]
800382a: 431a orrs r2, r3
| hcomp->Init.BlankingSrce
800382c: 687b ldr r3, [r7, #4]
800382e: 695b ldr r3, [r3, #20]
8003830: 431a orrs r2, r3
| hcomp->Init.Hysteresis
8003832: 687b ldr r3, [r7, #4]
8003834: 68db ldr r3, [r3, #12]
8003836: 431a orrs r2, r3
| hcomp->Init.OutputPol
8003838: 687b ldr r3, [r7, #4]
800383a: 691b ldr r3, [r3, #16]
tmp_csr = (hcomp->Init.InputMinus
800383c: 4313 orrs r3, r2
800383e: 617b str r3, [r7, #20]
);
/* Set parameters in COMP register */
/* Note: Update all bits except read-only, lock and enable bits */
MODIFY_REG(hcomp->Instance->CSR,
8003840: 687b ldr r3, [r7, #4]
8003842: 681b ldr r3, [r3, #0]
8003844: 681a ldr r2, [r3, #0]
8003846: 4b90 ldr r3, [pc, #576] @ (8003a88 <HAL_COMP_Init+0x2c0>)
8003848: 4013 ands r3, r2
800384a: 687a ldr r2, [r7, #4]
800384c: 6812 ldr r2, [r2, #0]
800384e: 6979 ldr r1, [r7, #20]
8003850: 430b orrs r3, r1
8003852: 6013 str r3, [r2, #0]
tmp_csr
);
/* Delay for COMP scaler bridge voltage stabilization */
/* Apply the delay if voltage scaler bridge is required and not already enabled */
if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) &&
8003854: 687b ldr r3, [r7, #4]
8003856: 681b ldr r3, [r3, #0]
8003858: 681b ldr r3, [r3, #0]
800385a: f403 0300 and.w r3, r3, #8388608 @ 0x800000
800385e: 2b00 cmp r3, #0
8003860: d016 beq.n 8003890 <HAL_COMP_Init+0xc8>
8003862: 69bb ldr r3, [r7, #24]
8003864: 2b00 cmp r3, #0
8003866: d113 bne.n 8003890 <HAL_COMP_Init+0xc8>
{
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles, scaling in us split to not */
/* exceed 32 bits register capacity and handle low frequency. */
wait_loop_index = ((COMP_DELAY_VOLTAGE_SCALER_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8003868: 4b88 ldr r3, [pc, #544] @ (8003a8c <HAL_COMP_Init+0x2c4>)
800386a: 681b ldr r3, [r3, #0]
800386c: 099b lsrs r3, r3, #6
800386e: 4a88 ldr r2, [pc, #544] @ (8003a90 <HAL_COMP_Init+0x2c8>)
8003870: fba2 2303 umull r2, r3, r2, r3
8003874: 099b lsrs r3, r3, #6
8003876: 1c5a adds r2, r3, #1
8003878: 4613 mov r3, r2
800387a: 009b lsls r3, r3, #2
800387c: 4413 add r3, r2
800387e: 009b lsls r3, r3, #2
8003880: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8003882: e002 b.n 800388a <HAL_COMP_Init+0xc2>
{
wait_loop_index--;
8003884: 68fb ldr r3, [r7, #12]
8003886: 3b01 subs r3, #1
8003888: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
800388a: 68fb ldr r3, [r7, #12]
800388c: 2b00 cmp r3, #0
800388e: d1f9 bne.n 8003884 <HAL_COMP_Init+0xbc>
}
}
/* Get the EXTI line corresponding to the selected COMP instance */
exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
8003890: 687b ldr r3, [r7, #4]
8003892: 681b ldr r3, [r3, #0]
8003894: 4a7f ldr r2, [pc, #508] @ (8003a94 <HAL_COMP_Init+0x2cc>)
8003896: 4293 cmp r3, r2
8003898: d028 beq.n 80038ec <HAL_COMP_Init+0x124>
800389a: 687b ldr r3, [r7, #4]
800389c: 681b ldr r3, [r3, #0]
800389e: 4a7e ldr r2, [pc, #504] @ (8003a98 <HAL_COMP_Init+0x2d0>)
80038a0: 4293 cmp r3, r2
80038a2: d020 beq.n 80038e6 <HAL_COMP_Init+0x11e>
80038a4: 687b ldr r3, [r7, #4]
80038a6: 681b ldr r3, [r3, #0]
80038a8: 4a7c ldr r2, [pc, #496] @ (8003a9c <HAL_COMP_Init+0x2d4>)
80038aa: 4293 cmp r3, r2
80038ac: d018 beq.n 80038e0 <HAL_COMP_Init+0x118>
80038ae: 687b ldr r3, [r7, #4]
80038b0: 681b ldr r3, [r3, #0]
80038b2: 4a7b ldr r2, [pc, #492] @ (8003aa0 <HAL_COMP_Init+0x2d8>)
80038b4: 4293 cmp r3, r2
80038b6: d010 beq.n 80038da <HAL_COMP_Init+0x112>
80038b8: 687b ldr r3, [r7, #4]
80038ba: 681b ldr r3, [r3, #0]
80038bc: 4a79 ldr r2, [pc, #484] @ (8003aa4 <HAL_COMP_Init+0x2dc>)
80038be: 4293 cmp r3, r2
80038c0: d008 beq.n 80038d4 <HAL_COMP_Init+0x10c>
80038c2: 687b ldr r3, [r7, #4]
80038c4: 681b ldr r3, [r3, #0]
80038c6: 4a78 ldr r2, [pc, #480] @ (8003aa8 <HAL_COMP_Init+0x2e0>)
80038c8: 4293 cmp r3, r2
80038ca: d101 bne.n 80038d0 <HAL_COMP_Init+0x108>
80038cc: 2301 movs r3, #1
80038ce: e00f b.n 80038f0 <HAL_COMP_Init+0x128>
80038d0: 2302 movs r3, #2
80038d2: e00d b.n 80038f0 <HAL_COMP_Init+0x128>
80038d4: f04f 4300 mov.w r3, #2147483648 @ 0x80000000
80038d8: e00a b.n 80038f0 <HAL_COMP_Init+0x128>
80038da: f04f 4380 mov.w r3, #1073741824 @ 0x40000000
80038de: e007 b.n 80038f0 <HAL_COMP_Init+0x128>
80038e0: f04f 5300 mov.w r3, #536870912 @ 0x20000000
80038e4: e004 b.n 80038f0 <HAL_COMP_Init+0x128>
80038e6: f44f 0380 mov.w r3, #4194304 @ 0x400000
80038ea: e001 b.n 80038f0 <HAL_COMP_Init+0x128>
80038ec: f44f 1300 mov.w r3, #2097152 @ 0x200000
80038f0: 613b str r3, [r7, #16]
/* Manage EXTI settings */
if ((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
80038f2: 687b ldr r3, [r7, #4]
80038f4: 699b ldr r3, [r3, #24]
80038f6: f003 0303 and.w r3, r3, #3
80038fa: 2b00 cmp r3, #0
80038fc: f000 80b6 beq.w 8003a6c <HAL_COMP_Init+0x2a4>
{
/* Configure EXTI rising edge */
if ((hcomp->Init.TriggerMode & COMP_EXTI_RISING) != 0UL)
8003900: 687b ldr r3, [r7, #4]
8003902: 699b ldr r3, [r3, #24]
8003904: f003 0310 and.w r3, r3, #16
8003908: 2b00 cmp r3, #0
800390a: d011 beq.n 8003930 <HAL_COMP_Init+0x168>
{
#if defined(COMP7)
if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
800390c: 687b ldr r3, [r7, #4]
800390e: 681b ldr r3, [r3, #0]
8003910: 4a65 ldr r2, [pc, #404] @ (8003aa8 <HAL_COMP_Init+0x2e0>)
8003912: 4293 cmp r3, r2
8003914: d004 beq.n 8003920 <HAL_COMP_Init+0x158>
8003916: 687b ldr r3, [r7, #4]
8003918: 681b ldr r3, [r3, #0]
800391a: 4a64 ldr r2, [pc, #400] @ (8003aac <HAL_COMP_Init+0x2e4>)
800391c: 4293 cmp r3, r2
800391e: d103 bne.n 8003928 <HAL_COMP_Init+0x160>
{
LL_EXTI_EnableRisingTrig_32_63(exti_line);
8003920: 6938 ldr r0, [r7, #16]
8003922: f7ff fe7f bl 8003624 <LL_EXTI_EnableRisingTrig_32_63>
8003926: e014 b.n 8003952 <HAL_COMP_Init+0x18a>
}
else
{
LL_EXTI_EnableRisingTrig_0_31(exti_line);
8003928: 6938 ldr r0, [r7, #16]
800392a: f7ff fe69 bl 8003600 <LL_EXTI_EnableRisingTrig_0_31>
800392e: e010 b.n 8003952 <HAL_COMP_Init+0x18a>
#endif /* COMP7 */
}
else
{
#if defined(COMP7)
if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
8003930: 687b ldr r3, [r7, #4]
8003932: 681b ldr r3, [r3, #0]
8003934: 4a5c ldr r2, [pc, #368] @ (8003aa8 <HAL_COMP_Init+0x2e0>)
8003936: 4293 cmp r3, r2
8003938: d004 beq.n 8003944 <HAL_COMP_Init+0x17c>
800393a: 687b ldr r3, [r7, #4]
800393c: 681b ldr r3, [r3, #0]
800393e: 4a5b ldr r2, [pc, #364] @ (8003aac <HAL_COMP_Init+0x2e4>)
8003940: 4293 cmp r3, r2
8003942: d103 bne.n 800394c <HAL_COMP_Init+0x184>
{
LL_EXTI_DisableRisingTrig_32_63(exti_line);
8003944: 6938 ldr r0, [r7, #16]
8003946: f7ff fe93 bl 8003670 <LL_EXTI_DisableRisingTrig_32_63>
800394a: e002 b.n 8003952 <HAL_COMP_Init+0x18a>
}
else
{
LL_EXTI_DisableRisingTrig_0_31(exti_line);
800394c: 6938 ldr r0, [r7, #16]
800394e: f7ff fe7b bl 8003648 <LL_EXTI_DisableRisingTrig_0_31>
LL_EXTI_DisableRisingTrig_0_31(exti_line);
#endif /* COMP7 */
}
/* Configure EXTI falling edge */
if ((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
8003952: 687b ldr r3, [r7, #4]
8003954: 699b ldr r3, [r3, #24]
8003956: f003 0320 and.w r3, r3, #32
800395a: 2b00 cmp r3, #0
800395c: d011 beq.n 8003982 <HAL_COMP_Init+0x1ba>
{
#if defined(COMP7)
if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
800395e: 687b ldr r3, [r7, #4]
8003960: 681b ldr r3, [r3, #0]
8003962: 4a51 ldr r2, [pc, #324] @ (8003aa8 <HAL_COMP_Init+0x2e0>)
8003964: 4293 cmp r3, r2
8003966: d004 beq.n 8003972 <HAL_COMP_Init+0x1aa>
8003968: 687b ldr r3, [r7, #4]
800396a: 681b ldr r3, [r3, #0]
800396c: 4a4f ldr r2, [pc, #316] @ (8003aac <HAL_COMP_Init+0x2e4>)
800396e: 4293 cmp r3, r2
8003970: d103 bne.n 800397a <HAL_COMP_Init+0x1b2>
{
LL_EXTI_EnableFallingTrig_32_63(exti_line);
8003972: 6938 ldr r0, [r7, #16]
8003974: f7ff fea2 bl 80036bc <LL_EXTI_EnableFallingTrig_32_63>
8003978: e014 b.n 80039a4 <HAL_COMP_Init+0x1dc>
}
else
{
LL_EXTI_EnableFallingTrig_0_31(exti_line);
800397a: 6938 ldr r0, [r7, #16]
800397c: f7ff fe8c bl 8003698 <LL_EXTI_EnableFallingTrig_0_31>
8003980: e010 b.n 80039a4 <HAL_COMP_Init+0x1dc>
#endif /* COMP7 */
}
else
{
#if defined(COMP7)
if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
8003982: 687b ldr r3, [r7, #4]
8003984: 681b ldr r3, [r3, #0]
8003986: 4a48 ldr r2, [pc, #288] @ (8003aa8 <HAL_COMP_Init+0x2e0>)
8003988: 4293 cmp r3, r2
800398a: d004 beq.n 8003996 <HAL_COMP_Init+0x1ce>
800398c: 687b ldr r3, [r7, #4]
800398e: 681b ldr r3, [r3, #0]
8003990: 4a46 ldr r2, [pc, #280] @ (8003aac <HAL_COMP_Init+0x2e4>)
8003992: 4293 cmp r3, r2
8003994: d103 bne.n 800399e <HAL_COMP_Init+0x1d6>
{
LL_EXTI_DisableFallingTrig_32_63(exti_line);
8003996: 6938 ldr r0, [r7, #16]
8003998: f7ff feb6 bl 8003708 <LL_EXTI_DisableFallingTrig_32_63>
800399c: e002 b.n 80039a4 <HAL_COMP_Init+0x1dc>
}
else
{
LL_EXTI_DisableFallingTrig_0_31(exti_line);
800399e: 6938 ldr r0, [r7, #16]
80039a0: f7ff fe9e bl 80036e0 <LL_EXTI_DisableFallingTrig_0_31>
#endif /* COMP7 */
}
/* Clear COMP EXTI pending bit (if any) */
#if defined(COMP7)
if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
80039a4: 687b ldr r3, [r7, #4]
80039a6: 681b ldr r3, [r3, #0]
80039a8: 4a3f ldr r2, [pc, #252] @ (8003aa8 <HAL_COMP_Init+0x2e0>)
80039aa: 4293 cmp r3, r2
80039ac: d004 beq.n 80039b8 <HAL_COMP_Init+0x1f0>
80039ae: 687b ldr r3, [r7, #4]
80039b0: 681b ldr r3, [r3, #0]
80039b2: 4a3e ldr r2, [pc, #248] @ (8003aac <HAL_COMP_Init+0x2e4>)
80039b4: 4293 cmp r3, r2
80039b6: d103 bne.n 80039c0 <HAL_COMP_Init+0x1f8>
{
LL_EXTI_ClearFlag_32_63(exti_line);
80039b8: 6938 ldr r0, [r7, #16]
80039ba: f7ff fef5 bl 80037a8 <LL_EXTI_ClearFlag_32_63>
80039be: e002 b.n 80039c6 <HAL_COMP_Init+0x1fe>
}
else
{
LL_EXTI_ClearFlag_0_31(exti_line);
80039c0: 6938 ldr r0, [r7, #16]
80039c2: f7ff fee1 bl 8003788 <LL_EXTI_ClearFlag_0_31>
#else
LL_EXTI_ClearFlag_0_31(exti_line);
#endif /* COMP7 */
/* Configure EXTI event mode */
if ((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
80039c6: 687b ldr r3, [r7, #4]
80039c8: 699b ldr r3, [r3, #24]
80039ca: f003 0302 and.w r3, r3, #2
80039ce: 2b00 cmp r3, #0
80039d0: d011 beq.n 80039f6 <HAL_COMP_Init+0x22e>
{
#if defined(COMP7)
if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
80039d2: 687b ldr r3, [r7, #4]
80039d4: 681b ldr r3, [r3, #0]
80039d6: 4a34 ldr r2, [pc, #208] @ (8003aa8 <HAL_COMP_Init+0x2e0>)
80039d8: 4293 cmp r3, r2
80039da: d004 beq.n 80039e6 <HAL_COMP_Init+0x21e>
80039dc: 687b ldr r3, [r7, #4]
80039de: 681b ldr r3, [r3, #0]
80039e0: 4a32 ldr r2, [pc, #200] @ (8003aac <HAL_COMP_Init+0x2e4>)
80039e2: 4293 cmp r3, r2
80039e4: d103 bne.n 80039ee <HAL_COMP_Init+0x226>
{
LL_EXTI_EnableEvent_32_63(exti_line);
80039e6: 6938 ldr r0, [r7, #16]
80039e8: f7ff fdd0 bl 800358c <LL_EXTI_EnableEvent_32_63>
80039ec: e014 b.n 8003a18 <HAL_COMP_Init+0x250>
}
else
{
LL_EXTI_EnableEvent_0_31(exti_line);
80039ee: 6938 ldr r0, [r7, #16]
80039f0: f7ff fdba bl 8003568 <LL_EXTI_EnableEvent_0_31>
80039f4: e010 b.n 8003a18 <HAL_COMP_Init+0x250>
#endif /* COMP7 */
}
else
{
#if defined(COMP7)
if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
80039f6: 687b ldr r3, [r7, #4]
80039f8: 681b ldr r3, [r3, #0]
80039fa: 4a2b ldr r2, [pc, #172] @ (8003aa8 <HAL_COMP_Init+0x2e0>)
80039fc: 4293 cmp r3, r2
80039fe: d004 beq.n 8003a0a <HAL_COMP_Init+0x242>
8003a00: 687b ldr r3, [r7, #4]
8003a02: 681b ldr r3, [r3, #0]
8003a04: 4a29 ldr r2, [pc, #164] @ (8003aac <HAL_COMP_Init+0x2e4>)
8003a06: 4293 cmp r3, r2
8003a08: d103 bne.n 8003a12 <HAL_COMP_Init+0x24a>
{
LL_EXTI_DisableEvent_32_63(exti_line);
8003a0a: 6938 ldr r0, [r7, #16]
8003a0c: f7ff fde4 bl 80035d8 <LL_EXTI_DisableEvent_32_63>
8003a10: e002 b.n 8003a18 <HAL_COMP_Init+0x250>
}
else
{
LL_EXTI_DisableEvent_0_31(exti_line);
8003a12: 6938 ldr r0, [r7, #16]
8003a14: f7ff fdcc bl 80035b0 <LL_EXTI_DisableEvent_0_31>
LL_EXTI_DisableEvent_0_31(exti_line);
#endif /* COMP7 */
}
/* Configure EXTI interrupt mode */
if ((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
8003a18: 687b ldr r3, [r7, #4]
8003a1a: 699b ldr r3, [r3, #24]
8003a1c: f003 0301 and.w r3, r3, #1
8003a20: 2b00 cmp r3, #0
8003a22: d011 beq.n 8003a48 <HAL_COMP_Init+0x280>
{
#if defined(COMP7)
if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
8003a24: 687b ldr r3, [r7, #4]
8003a26: 681b ldr r3, [r3, #0]
8003a28: 4a1f ldr r2, [pc, #124] @ (8003aa8 <HAL_COMP_Init+0x2e0>)
8003a2a: 4293 cmp r3, r2
8003a2c: d004 beq.n 8003a38 <HAL_COMP_Init+0x270>
8003a2e: 687b ldr r3, [r7, #4]
8003a30: 681b ldr r3, [r3, #0]
8003a32: 4a1e ldr r2, [pc, #120] @ (8003aac <HAL_COMP_Init+0x2e4>)
8003a34: 4293 cmp r3, r2
8003a36: d103 bne.n 8003a40 <HAL_COMP_Init+0x278>
{
LL_EXTI_EnableIT_32_63(exti_line);
8003a38: 6938 ldr r0, [r7, #16]
8003a3a: f7ff fd5b bl 80034f4 <LL_EXTI_EnableIT_32_63>
8003a3e: e04b b.n 8003ad8 <HAL_COMP_Init+0x310>
}
else
{
LL_EXTI_EnableIT_0_31(exti_line);
8003a40: 6938 ldr r0, [r7, #16]
8003a42: f7ff fd45 bl 80034d0 <LL_EXTI_EnableIT_0_31>
8003a46: e047 b.n 8003ad8 <HAL_COMP_Init+0x310>
#endif /* COMP7 */
}
else
{
#if defined(COMP7)
if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
8003a48: 687b ldr r3, [r7, #4]
8003a4a: 681b ldr r3, [r3, #0]
8003a4c: 4a16 ldr r2, [pc, #88] @ (8003aa8 <HAL_COMP_Init+0x2e0>)
8003a4e: 4293 cmp r3, r2
8003a50: d004 beq.n 8003a5c <HAL_COMP_Init+0x294>
8003a52: 687b ldr r3, [r7, #4]
8003a54: 681b ldr r3, [r3, #0]
8003a56: 4a15 ldr r2, [pc, #84] @ (8003aac <HAL_COMP_Init+0x2e4>)
8003a58: 4293 cmp r3, r2
8003a5a: d103 bne.n 8003a64 <HAL_COMP_Init+0x29c>
{
LL_EXTI_DisableIT_32_63(exti_line);
8003a5c: 6938 ldr r0, [r7, #16]
8003a5e: f7ff fd6f bl 8003540 <LL_EXTI_DisableIT_32_63>
8003a62: e039 b.n 8003ad8 <HAL_COMP_Init+0x310>
}
else
{
LL_EXTI_DisableIT_0_31(exti_line);
8003a64: 6938 ldr r0, [r7, #16]
8003a66: f7ff fd57 bl 8003518 <LL_EXTI_DisableIT_0_31>
8003a6a: e035 b.n 8003ad8 <HAL_COMP_Init+0x310>
}
else
{
/* Disable EXTI event mode */
#if defined(COMP7)
if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
8003a6c: 687b ldr r3, [r7, #4]
8003a6e: 681b ldr r3, [r3, #0]
8003a70: 4a0d ldr r2, [pc, #52] @ (8003aa8 <HAL_COMP_Init+0x2e0>)
8003a72: 4293 cmp r3, r2
8003a74: d004 beq.n 8003a80 <HAL_COMP_Init+0x2b8>
8003a76: 687b ldr r3, [r7, #4]
8003a78: 681b ldr r3, [r3, #0]
8003a7a: 4a0c ldr r2, [pc, #48] @ (8003aac <HAL_COMP_Init+0x2e4>)
8003a7c: 4293 cmp r3, r2
8003a7e: d117 bne.n 8003ab0 <HAL_COMP_Init+0x2e8>
{
LL_EXTI_DisableEvent_32_63(exti_line);
8003a80: 6938 ldr r0, [r7, #16]
8003a82: f7ff fda9 bl 80035d8 <LL_EXTI_DisableEvent_32_63>
8003a86: e016 b.n 8003ab6 <HAL_COMP_Init+0x2ee>
8003a88: ff007e0f .word 0xff007e0f
8003a8c: 20000000 .word 0x20000000
8003a90: 053e2d63 .word 0x053e2d63
8003a94: 40010200 .word 0x40010200
8003a98: 40010204 .word 0x40010204
8003a9c: 40010208 .word 0x40010208
8003aa0: 4001020c .word 0x4001020c
8003aa4: 40010210 .word 0x40010210
8003aa8: 40010214 .word 0x40010214
8003aac: 40010218 .word 0x40010218
}
else
{
LL_EXTI_DisableEvent_0_31(exti_line);
8003ab0: 6938 ldr r0, [r7, #16]
8003ab2: f7ff fd7d bl 80035b0 <LL_EXTI_DisableEvent_0_31>
LL_EXTI_DisableEvent_0_31(exti_line);
#endif /* COMP7 */
/* Disable EXTI interrupt mode */
#if defined(COMP7)
if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
8003ab6: 687b ldr r3, [r7, #4]
8003ab8: 681b ldr r3, [r3, #0]
8003aba: 4a0e ldr r2, [pc, #56] @ (8003af4 <HAL_COMP_Init+0x32c>)
8003abc: 4293 cmp r3, r2
8003abe: d004 beq.n 8003aca <HAL_COMP_Init+0x302>
8003ac0: 687b ldr r3, [r7, #4]
8003ac2: 681b ldr r3, [r3, #0]
8003ac4: 4a0c ldr r2, [pc, #48] @ (8003af8 <HAL_COMP_Init+0x330>)
8003ac6: 4293 cmp r3, r2
8003ac8: d103 bne.n 8003ad2 <HAL_COMP_Init+0x30a>
{
LL_EXTI_DisableIT_32_63(exti_line);
8003aca: 6938 ldr r0, [r7, #16]
8003acc: f7ff fd38 bl 8003540 <LL_EXTI_DisableIT_32_63>
8003ad0: e002 b.n 8003ad8 <HAL_COMP_Init+0x310>
}
else
{
LL_EXTI_DisableIT_0_31(exti_line);
8003ad2: 6938 ldr r0, [r7, #16]
8003ad4: f7ff fd20 bl 8003518 <LL_EXTI_DisableIT_0_31>
}
/* Set HAL COMP handle state */
/* Note: Transition from state reset to state ready, */
/* otherwise (coming from state ready or busy) no state update. */
if (hcomp->State == HAL_COMP_STATE_RESET)
8003ad8: 687b ldr r3, [r7, #4]
8003ada: 7f5b ldrb r3, [r3, #29]
8003adc: b2db uxtb r3, r3
8003ade: 2b00 cmp r3, #0
8003ae0: d102 bne.n 8003ae8 <HAL_COMP_Init+0x320>
{
hcomp->State = HAL_COMP_STATE_READY;
8003ae2: 687b ldr r3, [r7, #4]
8003ae4: 2201 movs r2, #1
8003ae6: 775a strb r2, [r3, #29]
}
}
return status;
8003ae8: 7ffb ldrb r3, [r7, #31]
}
8003aea: 4618 mov r0, r3
8003aec: 3720 adds r7, #32
8003aee: 46bd mov sp, r7
8003af0: bd80 pop {r7, pc}
8003af2: bf00 nop
8003af4: 40010214 .word 0x40010214
8003af8: 40010218 .word 0x40010218
08003afc <HAL_COMP_Start>:
* @brief Start the comparator.
* @param hcomp COMP handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
{
8003afc: b480 push {r7}
8003afe: b085 sub sp, #20
8003b00: af00 add r7, sp, #0
8003b02: 6078 str r0, [r7, #4]
__IO uint32_t wait_loop_index = 0UL;
8003b04: 2300 movs r3, #0
8003b06: 60bb str r3, [r7, #8]
HAL_StatusTypeDef status = HAL_OK;
8003b08: 2300 movs r3, #0
8003b0a: 73fb strb r3, [r7, #15]
/* Check the COMP handle allocation and lock status */
if (hcomp == NULL)
8003b0c: 687b ldr r3, [r7, #4]
8003b0e: 2b00 cmp r3, #0
8003b10: d102 bne.n 8003b18 <HAL_COMP_Start+0x1c>
{
status = HAL_ERROR;
8003b12: 2301 movs r3, #1
8003b14: 73fb strb r3, [r7, #15]
8003b16: e02e b.n 8003b76 <HAL_COMP_Start+0x7a>
}
else if (__HAL_COMP_IS_LOCKED(hcomp))
8003b18: 687b ldr r3, [r7, #4]
8003b1a: 681b ldr r3, [r3, #0]
8003b1c: 681b ldr r3, [r3, #0]
8003b1e: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8003b22: f1b3 4f00 cmp.w r3, #2147483648 @ 0x80000000
8003b26: d102 bne.n 8003b2e <HAL_COMP_Start+0x32>
{
status = HAL_ERROR;
8003b28: 2301 movs r3, #1
8003b2a: 73fb strb r3, [r7, #15]
8003b2c: e023 b.n 8003b76 <HAL_COMP_Start+0x7a>
else
{
/* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
if (hcomp->State == HAL_COMP_STATE_READY)
8003b2e: 687b ldr r3, [r7, #4]
8003b30: 7f5b ldrb r3, [r3, #29]
8003b32: b2db uxtb r3, r3
8003b34: 2b01 cmp r3, #1
8003b36: d11c bne.n 8003b72 <HAL_COMP_Start+0x76>
{
/* Enable the selected comparator */
SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
8003b38: 687b ldr r3, [r7, #4]
8003b3a: 681b ldr r3, [r3, #0]
8003b3c: 681a ldr r2, [r3, #0]
8003b3e: 687b ldr r3, [r7, #4]
8003b40: 681b ldr r3, [r3, #0]
8003b42: f042 0201 orr.w r2, r2, #1
8003b46: 601a str r2, [r3, #0]
/* Set HAL COMP handle state */
hcomp->State = HAL_COMP_STATE_BUSY;
8003b48: 687b ldr r3, [r7, #4]
8003b4a: 2202 movs r2, #2
8003b4c: 775a strb r2, [r3, #29]
/* Note: Variable divided by 2 to compensate partially */
/* CPU processing cycles. */
/* Note: In case of system low frequency (below 1Mhz), short delay */
/* of startup time (few us) is within CPU processing cycles */
/* of following instructions. */
wait_loop_index = (COMP_DELAY_STARTUP_US * (SystemCoreClock / (1000000UL * 2UL)));
8003b4e: 4b0d ldr r3, [pc, #52] @ (8003b84 <HAL_COMP_Start+0x88>)
8003b50: 681b ldr r3, [r3, #0]
8003b52: 4a0d ldr r2, [pc, #52] @ (8003b88 <HAL_COMP_Start+0x8c>)
8003b54: fba2 2303 umull r2, r3, r2, r3
8003b58: 0cda lsrs r2, r3, #19
8003b5a: 4613 mov r3, r2
8003b5c: 009b lsls r3, r3, #2
8003b5e: 4413 add r3, r2
8003b60: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8003b62: e002 b.n 8003b6a <HAL_COMP_Start+0x6e>
{
wait_loop_index--;
8003b64: 68bb ldr r3, [r7, #8]
8003b66: 3b01 subs r3, #1
8003b68: 60bb str r3, [r7, #8]
while (wait_loop_index != 0UL)
8003b6a: 68bb ldr r3, [r7, #8]
8003b6c: 2b00 cmp r3, #0
8003b6e: d1f9 bne.n 8003b64 <HAL_COMP_Start+0x68>
8003b70: e001 b.n 8003b76 <HAL_COMP_Start+0x7a>
}
}
else
{
status = HAL_ERROR;
8003b72: 2301 movs r3, #1
8003b74: 73fb strb r3, [r7, #15]
}
}
return status;
8003b76: 7bfb ldrb r3, [r7, #15]
}
8003b78: 4618 mov r0, r3
8003b7a: 3714 adds r7, #20
8003b7c: 46bd mov sp, r7
8003b7e: f85d 7b04 ldr.w r7, [sp], #4
8003b82: 4770 bx lr
8003b84: 20000000 .word 0x20000000
8003b88: 431bde83 .word 0x431bde83
08003b8c <HAL_COMP_IRQHandler>:
* @brief Comparator IRQ handler.
* @param hcomp COMP handle
* @retval None
*/
void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
{
8003b8c: b580 push {r7, lr}
8003b8e: b084 sub sp, #16
8003b90: af00 add r7, sp, #0
8003b92: 6078 str r0, [r7, #4]
/* Get the EXTI line corresponding to the selected COMP instance */
uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
8003b94: 687b ldr r3, [r7, #4]
8003b96: 681b ldr r3, [r3, #0]
8003b98: 4a2f ldr r2, [pc, #188] @ (8003c58 <HAL_COMP_IRQHandler+0xcc>)
8003b9a: 4293 cmp r3, r2
8003b9c: d028 beq.n 8003bf0 <HAL_COMP_IRQHandler+0x64>
8003b9e: 687b ldr r3, [r7, #4]
8003ba0: 681b ldr r3, [r3, #0]
8003ba2: 4a2e ldr r2, [pc, #184] @ (8003c5c <HAL_COMP_IRQHandler+0xd0>)
8003ba4: 4293 cmp r3, r2
8003ba6: d020 beq.n 8003bea <HAL_COMP_IRQHandler+0x5e>
8003ba8: 687b ldr r3, [r7, #4]
8003baa: 681b ldr r3, [r3, #0]
8003bac: 4a2c ldr r2, [pc, #176] @ (8003c60 <HAL_COMP_IRQHandler+0xd4>)
8003bae: 4293 cmp r3, r2
8003bb0: d018 beq.n 8003be4 <HAL_COMP_IRQHandler+0x58>
8003bb2: 687b ldr r3, [r7, #4]
8003bb4: 681b ldr r3, [r3, #0]
8003bb6: 4a2b ldr r2, [pc, #172] @ (8003c64 <HAL_COMP_IRQHandler+0xd8>)
8003bb8: 4293 cmp r3, r2
8003bba: d010 beq.n 8003bde <HAL_COMP_IRQHandler+0x52>
8003bbc: 687b ldr r3, [r7, #4]
8003bbe: 681b ldr r3, [r3, #0]
8003bc0: 4a29 ldr r2, [pc, #164] @ (8003c68 <HAL_COMP_IRQHandler+0xdc>)
8003bc2: 4293 cmp r3, r2
8003bc4: d008 beq.n 8003bd8 <HAL_COMP_IRQHandler+0x4c>
8003bc6: 687b ldr r3, [r7, #4]
8003bc8: 681b ldr r3, [r3, #0]
8003bca: 4a28 ldr r2, [pc, #160] @ (8003c6c <HAL_COMP_IRQHandler+0xe0>)
8003bcc: 4293 cmp r3, r2
8003bce: d101 bne.n 8003bd4 <HAL_COMP_IRQHandler+0x48>
8003bd0: 2301 movs r3, #1
8003bd2: e00f b.n 8003bf4 <HAL_COMP_IRQHandler+0x68>
8003bd4: 2302 movs r3, #2
8003bd6: e00d b.n 8003bf4 <HAL_COMP_IRQHandler+0x68>
8003bd8: f04f 4300 mov.w r3, #2147483648 @ 0x80000000
8003bdc: e00a b.n 8003bf4 <HAL_COMP_IRQHandler+0x68>
8003bde: f04f 4380 mov.w r3, #1073741824 @ 0x40000000
8003be2: e007 b.n 8003bf4 <HAL_COMP_IRQHandler+0x68>
8003be4: f04f 5300 mov.w r3, #536870912 @ 0x20000000
8003be8: e004 b.n 8003bf4 <HAL_COMP_IRQHandler+0x68>
8003bea: f44f 0380 mov.w r3, #4194304 @ 0x400000
8003bee: e001 b.n 8003bf4 <HAL_COMP_IRQHandler+0x68>
8003bf0: f44f 1300 mov.w r3, #2097152 @ 0x200000
8003bf4: 60bb str r3, [r7, #8]
uint32_t tmp_comp_exti_flag_set = 0UL;
8003bf6: 2300 movs r3, #0
8003bf8: 60fb str r3, [r7, #12]
/* Check COMP EXTI flag */
#if defined(COMP7)
if ((hcomp->Instance == COMP6) || (hcomp->Instance == COMP7))
8003bfa: 687b ldr r3, [r7, #4]
8003bfc: 681b ldr r3, [r3, #0]
8003bfe: 4a1b ldr r2, [pc, #108] @ (8003c6c <HAL_COMP_IRQHandler+0xe0>)
8003c00: 4293 cmp r3, r2
8003c02: d004 beq.n 8003c0e <HAL_COMP_IRQHandler+0x82>
8003c04: 687b ldr r3, [r7, #4]
8003c06: 681b ldr r3, [r3, #0]
8003c08: 4a19 ldr r2, [pc, #100] @ (8003c70 <HAL_COMP_IRQHandler+0xe4>)
8003c0a: 4293 cmp r3, r2
8003c0c: d108 bne.n 8003c20 <HAL_COMP_IRQHandler+0x94>
{
if (LL_EXTI_IsActiveFlag_32_63(exti_line) != 0UL)
8003c0e: 68b8 ldr r0, [r7, #8]
8003c10: f7ff fda4 bl 800375c <LL_EXTI_IsActiveFlag_32_63>
8003c14: 4603 mov r3, r0
8003c16: 2b00 cmp r3, #0
8003c18: d00a beq.n 8003c30 <HAL_COMP_IRQHandler+0xa4>
{
tmp_comp_exti_flag_set = 2UL;
8003c1a: 2302 movs r3, #2
8003c1c: 60fb str r3, [r7, #12]
if (LL_EXTI_IsActiveFlag_32_63(exti_line) != 0UL)
8003c1e: e007 b.n 8003c30 <HAL_COMP_IRQHandler+0xa4>
}
}
else
{
if (LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL)
8003c20: 68b8 ldr r0, [r7, #8]
8003c22: f7ff fd85 bl 8003730 <LL_EXTI_IsActiveFlag_0_31>
8003c26: 4603 mov r3, r0
8003c28: 2b00 cmp r3, #0
8003c2a: d001 beq.n 8003c30 <HAL_COMP_IRQHandler+0xa4>
{
tmp_comp_exti_flag_set = 1UL;
8003c2c: 2301 movs r3, #1
8003c2e: 60fb str r3, [r7, #12]
{
tmp_comp_exti_flag_set = 1UL;
}
#endif /* COMP7 */
if (tmp_comp_exti_flag_set != 0UL)
8003c30: 68fb ldr r3, [r7, #12]
8003c32: 2b00 cmp r3, #0
8003c34: d00c beq.n 8003c50 <HAL_COMP_IRQHandler+0xc4>
{
/* Clear COMP EXTI line pending bit */
#if defined(COMP7)
if (tmp_comp_exti_flag_set == 2UL)
8003c36: 68fb ldr r3, [r7, #12]
8003c38: 2b02 cmp r3, #2
8003c3a: d103 bne.n 8003c44 <HAL_COMP_IRQHandler+0xb8>
{
LL_EXTI_ClearFlag_32_63(exti_line);
8003c3c: 68b8 ldr r0, [r7, #8]
8003c3e: f7ff fdb3 bl 80037a8 <LL_EXTI_ClearFlag_32_63>
8003c42: e002 b.n 8003c4a <HAL_COMP_IRQHandler+0xbe>
}
else
{
LL_EXTI_ClearFlag_0_31(exti_line);
8003c44: 68b8 ldr r0, [r7, #8]
8003c46: f7ff fd9f bl 8003788 <LL_EXTI_ClearFlag_0_31>
/* COMP trigger user callback */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
hcomp->TriggerCallback(hcomp);
#else
HAL_COMP_TriggerCallback(hcomp);
8003c4a: 6878 ldr r0, [r7, #4]
8003c4c: f7fd fabe bl 80011cc <HAL_COMP_TriggerCallback>
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
}
}
8003c50: bf00 nop
8003c52: 3710 adds r7, #16
8003c54: 46bd mov sp, r7
8003c56: bd80 pop {r7, pc}
8003c58: 40010200 .word 0x40010200
8003c5c: 40010204 .word 0x40010204
8003c60: 40010208 .word 0x40010208
8003c64: 4001020c .word 0x4001020c
8003c68: 40010210 .word 0x40010210
8003c6c: 40010214 .word 0x40010214
8003c70: 40010218 .word 0x40010218
08003c74 <HAL_CORDIC_Init>:
* @brief Initialize the CORDIC peripheral and the associated handle.
* @param hcordic pointer to a CORDIC_HandleTypeDef structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_CORDIC_Init(CORDIC_HandleTypeDef *hcordic)
{
8003c74: b580 push {r7, lr}
8003c76: b082 sub sp, #8
8003c78: af00 add r7, sp, #0
8003c7a: 6078 str r0, [r7, #4]
/* Check the CORDIC handle allocation */
if (hcordic == NULL)
8003c7c: 687b ldr r3, [r7, #4]
8003c7e: 2b00 cmp r3, #0
8003c80: d101 bne.n 8003c86 <HAL_CORDIC_Init+0x12>
{
/* Return error status */
return HAL_ERROR;
8003c82: 2301 movs r3, #1
8003c84: e023 b.n 8003cce <HAL_CORDIC_Init+0x5a>
/* Initialize the low level hardware */
hcordic->MspInitCallback(hcordic);
}
#else
if (hcordic->State == HAL_CORDIC_STATE_RESET)
8003c86: 687b ldr r3, [r7, #4]
8003c88: f893 3021 ldrb.w r3, [r3, #33] @ 0x21
8003c8c: b2db uxtb r3, r3
8003c8e: 2b00 cmp r3, #0
8003c90: d106 bne.n 8003ca0 <HAL_CORDIC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
hcordic->Lock = HAL_UNLOCKED;
8003c92: 687b ldr r3, [r7, #4]
8003c94: 2200 movs r2, #0
8003c96: f883 2020 strb.w r2, [r3, #32]
/* Initialize the low level hardware */
HAL_CORDIC_MspInit(hcordic);
8003c9a: 6878 ldr r0, [r7, #4]
8003c9c: f7fd fc92 bl 80015c4 <HAL_CORDIC_MspInit>
}
#endif /* (USE_HAL_CORDIC_REGISTER_CALLBACKS) */
/* Set CORDIC error code to none */
hcordic->ErrorCode = HAL_CORDIC_ERROR_NONE;
8003ca0: 687b ldr r3, [r7, #4]
8003ca2: 2200 movs r2, #0
8003ca4: 625a str r2, [r3, #36] @ 0x24
/* Reset pInBuff and pOutBuff */
hcordic->pInBuff = NULL;
8003ca6: 687b ldr r3, [r7, #4]
8003ca8: 2200 movs r2, #0
8003caa: 605a str r2, [r3, #4]
hcordic->pOutBuff = NULL;
8003cac: 687b ldr r3, [r7, #4]
8003cae: 2200 movs r2, #0
8003cb0: 609a str r2, [r3, #8]
/* Reset NbCalcToOrder and NbCalcToGet */
hcordic->NbCalcToOrder = 0U;
8003cb2: 687b ldr r3, [r7, #4]
8003cb4: 2200 movs r2, #0
8003cb6: 60da str r2, [r3, #12]
hcordic->NbCalcToGet = 0U;
8003cb8: 687b ldr r3, [r7, #4]
8003cba: 2200 movs r2, #0
8003cbc: 611a str r2, [r3, #16]
/* Reset DMADirection */
hcordic->DMADirection = CORDIC_DMA_DIR_NONE;
8003cbe: 687b ldr r3, [r7, #4]
8003cc0: 2200 movs r2, #0
8003cc2: 615a str r2, [r3, #20]
/* Change CORDIC peripheral state */
hcordic->State = HAL_CORDIC_STATE_READY;
8003cc4: 687b ldr r3, [r7, #4]
8003cc6: 2201 movs r2, #1
8003cc8: f883 2021 strb.w r2, [r3, #33] @ 0x21
/* Return function status */
return HAL_OK;
8003ccc: 2300 movs r3, #0
}
8003cce: 4618 mov r0, r3
8003cd0: 3708 adds r7, #8
8003cd2: 46bd mov sp, r7
8003cd4: bd80 pop {r7, pc}
...
08003cd8 <__NVIC_SetPriorityGrouping>:
In case of a conflict between priority grouping and available
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
\param [in] PriorityGroup Priority grouping field.
*/
__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003cd8: b480 push {r7}
8003cda: b085 sub sp, #20
8003cdc: af00 add r7, sp, #0
8003cde: 6078 str r0, [r7, #4]
uint32_t reg_value;
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003ce0: 687b ldr r3, [r7, #4]
8003ce2: f003 0307 and.w r3, r3, #7
8003ce6: 60fb str r3, [r7, #12]
reg_value = SCB->AIRCR; /* read old register configuration */
8003ce8: 4b0c ldr r3, [pc, #48] @ (8003d1c <__NVIC_SetPriorityGrouping+0x44>)
8003cea: 68db ldr r3, [r3, #12]
8003cec: 60bb str r3, [r7, #8]
reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
8003cee: 68ba ldr r2, [r7, #8]
8003cf0: f64f 03ff movw r3, #63743 @ 0xf8ff
8003cf4: 4013 ands r3, r2
8003cf6: 60bb str r3, [r7, #8]
reg_value = (reg_value |
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
(PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */
8003cf8: 68fb ldr r3, [r7, #12]
8003cfa: 021a lsls r2, r3, #8
((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
8003cfc: 68bb ldr r3, [r7, #8]
8003cfe: 4313 orrs r3, r2
reg_value = (reg_value |
8003d00: f043 63bf orr.w r3, r3, #100139008 @ 0x5f80000
8003d04: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8003d08: 60bb str r3, [r7, #8]
SCB->AIRCR = reg_value;
8003d0a: 4a04 ldr r2, [pc, #16] @ (8003d1c <__NVIC_SetPriorityGrouping+0x44>)
8003d0c: 68bb ldr r3, [r7, #8]
8003d0e: 60d3 str r3, [r2, #12]
}
8003d10: bf00 nop
8003d12: 3714 adds r7, #20
8003d14: 46bd mov sp, r7
8003d16: f85d 7b04 ldr.w r7, [sp], #4
8003d1a: 4770 bx lr
8003d1c: e000ed00 .word 0xe000ed00
08003d20 <__NVIC_GetPriorityGrouping>:
\brief Get Priority Grouping
\details Reads the priority grouping field from the NVIC Interrupt Controller.
\return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
*/
__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void)
{
8003d20: b480 push {r7}
8003d22: af00 add r7, sp, #0
return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
8003d24: 4b04 ldr r3, [pc, #16] @ (8003d38 <__NVIC_GetPriorityGrouping+0x18>)
8003d26: 68db ldr r3, [r3, #12]
8003d28: 0a1b lsrs r3, r3, #8
8003d2a: f003 0307 and.w r3, r3, #7
}
8003d2e: 4618 mov r0, r3
8003d30: 46bd mov sp, r7
8003d32: f85d 7b04 ldr.w r7, [sp], #4
8003d36: 4770 bx lr
8003d38: e000ed00 .word 0xe000ed00
08003d3c <__NVIC_EnableIRQ>:
\details Enables a device specific interrupt in the NVIC interrupt controller.
\param [in] IRQn Device specific interrupt number.
\note IRQn must not be negative.
*/
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
{
8003d3c: b480 push {r7}
8003d3e: b083 sub sp, #12
8003d40: af00 add r7, sp, #0
8003d42: 4603 mov r3, r0
8003d44: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003d46: f997 3007 ldrsb.w r3, [r7, #7]
8003d4a: 2b00 cmp r3, #0
8003d4c: db0b blt.n 8003d66 <__NVIC_EnableIRQ+0x2a>
{
__COMPILER_BARRIER();
NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
8003d4e: 79fb ldrb r3, [r7, #7]
8003d50: f003 021f and.w r2, r3, #31
8003d54: 4907 ldr r1, [pc, #28] @ (8003d74 <__NVIC_EnableIRQ+0x38>)
8003d56: f997 3007 ldrsb.w r3, [r7, #7]
8003d5a: 095b lsrs r3, r3, #5
8003d5c: 2001 movs r0, #1
8003d5e: fa00 f202 lsl.w r2, r0, r2
8003d62: f841 2023 str.w r2, [r1, r3, lsl #2]
__COMPILER_BARRIER();
}
}
8003d66: bf00 nop
8003d68: 370c adds r7, #12
8003d6a: 46bd mov sp, r7
8003d6c: f85d 7b04 ldr.w r7, [sp], #4
8003d70: 4770 bx lr
8003d72: bf00 nop
8003d74: e000e100 .word 0xe000e100
08003d78 <__NVIC_SetPriority>:
\param [in] IRQn Interrupt number.
\param [in] priority Priority to set.
\note The priority cannot be set for every processor exception.
*/
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
8003d78: b480 push {r7}
8003d7a: b083 sub sp, #12
8003d7c: af00 add r7, sp, #0
8003d7e: 4603 mov r3, r0
8003d80: 6039 str r1, [r7, #0]
8003d82: 71fb strb r3, [r7, #7]
if ((int32_t)(IRQn) >= 0)
8003d84: f997 3007 ldrsb.w r3, [r7, #7]
8003d88: 2b00 cmp r3, #0
8003d8a: db0a blt.n 8003da2 <__NVIC_SetPriority+0x2a>
{
NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003d8c: 683b ldr r3, [r7, #0]
8003d8e: b2da uxtb r2, r3
8003d90: 490c ldr r1, [pc, #48] @ (8003dc4 <__NVIC_SetPriority+0x4c>)
8003d92: f997 3007 ldrsb.w r3, [r7, #7]
8003d96: 0112 lsls r2, r2, #4
8003d98: b2d2 uxtb r2, r2
8003d9a: 440b add r3, r1
8003d9c: f883 2300 strb.w r2, [r3, #768] @ 0x300
}
else
{
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
}
}
8003da0: e00a b.n 8003db8 <__NVIC_SetPriority+0x40>
SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
8003da2: 683b ldr r3, [r7, #0]
8003da4: b2da uxtb r2, r3
8003da6: 4908 ldr r1, [pc, #32] @ (8003dc8 <__NVIC_SetPriority+0x50>)
8003da8: 79fb ldrb r3, [r7, #7]
8003daa: f003 030f and.w r3, r3, #15
8003dae: 3b04 subs r3, #4
8003db0: 0112 lsls r2, r2, #4
8003db2: b2d2 uxtb r2, r2
8003db4: 440b add r3, r1
8003db6: 761a strb r2, [r3, #24]
}
8003db8: bf00 nop
8003dba: 370c adds r7, #12
8003dbc: 46bd mov sp, r7
8003dbe: f85d 7b04 ldr.w r7, [sp], #4
8003dc2: 4770 bx lr
8003dc4: e000e100 .word 0xe000e100
8003dc8: e000ed00 .word 0xe000ed00
08003dcc <NVIC_EncodePriority>:
\param [in] PreemptPriority Preemptive priority value (starting from 0).
\param [in] SubPriority Subpriority value (starting from 0).
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
*/
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003dcc: b480 push {r7}
8003dce: b089 sub sp, #36 @ 0x24
8003dd0: af00 add r7, sp, #0
8003dd2: 60f8 str r0, [r7, #12]
8003dd4: 60b9 str r1, [r7, #8]
8003dd6: 607a str r2, [r7, #4]
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
8003dd8: 68fb ldr r3, [r7, #12]
8003dda: f003 0307 and.w r3, r3, #7
8003dde: 61fb str r3, [r7, #28]
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
8003de0: 69fb ldr r3, [r7, #28]
8003de2: f1c3 0307 rsb r3, r3, #7
8003de6: 2b04 cmp r3, #4
8003de8: bf28 it cs
8003dea: 2304 movcs r3, #4
8003dec: 61bb str r3, [r7, #24]
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
8003dee: 69fb ldr r3, [r7, #28]
8003df0: 3304 adds r3, #4
8003df2: 2b06 cmp r3, #6
8003df4: d902 bls.n 8003dfc <NVIC_EncodePriority+0x30>
8003df6: 69fb ldr r3, [r7, #28]
8003df8: 3b03 subs r3, #3
8003dfa: e000 b.n 8003dfe <NVIC_EncodePriority+0x32>
8003dfc: 2300 movs r3, #0
8003dfe: 617b str r3, [r7, #20]
return (
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8003e00: f04f 32ff mov.w r2, #4294967295
8003e04: 69bb ldr r3, [r7, #24]
8003e06: fa02 f303 lsl.w r3, r2, r3
8003e0a: 43da mvns r2, r3
8003e0c: 68bb ldr r3, [r7, #8]
8003e0e: 401a ands r2, r3
8003e10: 697b ldr r3, [r7, #20]
8003e12: 409a lsls r2, r3
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
8003e14: f04f 31ff mov.w r1, #4294967295
8003e18: 697b ldr r3, [r7, #20]
8003e1a: fa01 f303 lsl.w r3, r1, r3
8003e1e: 43d9 mvns r1, r3
8003e20: 687b ldr r3, [r7, #4]
8003e22: 400b ands r3, r1
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
8003e24: 4313 orrs r3, r2
);
}
8003e26: 4618 mov r0, r3
8003e28: 3724 adds r7, #36 @ 0x24
8003e2a: 46bd mov sp, r7
8003e2c: f85d 7b04 ldr.w r7, [sp], #4
8003e30: 4770 bx lr
...
08003e34 <SysTick_Config>:
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
must contain a vendor-specific implementation of this function.
*/
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
{
8003e34: b580 push {r7, lr}
8003e36: b082 sub sp, #8
8003e38: af00 add r7, sp, #0
8003e3a: 6078 str r0, [r7, #4]
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
8003e3c: 687b ldr r3, [r7, #4]
8003e3e: 3b01 subs r3, #1
8003e40: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
8003e44: d301 bcc.n 8003e4a <SysTick_Config+0x16>
{
return (1UL); /* Reload value impossible */
8003e46: 2301 movs r3, #1
8003e48: e00f b.n 8003e6a <SysTick_Config+0x36>
}
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
8003e4a: 4a0a ldr r2, [pc, #40] @ (8003e74 <SysTick_Config+0x40>)
8003e4c: 687b ldr r3, [r7, #4]
8003e4e: 3b01 subs r3, #1
8003e50: 6053 str r3, [r2, #4]
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
8003e52: 210f movs r1, #15
8003e54: f04f 30ff mov.w r0, #4294967295
8003e58: f7ff ff8e bl 8003d78 <__NVIC_SetPriority>
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
8003e5c: 4b05 ldr r3, [pc, #20] @ (8003e74 <SysTick_Config+0x40>)
8003e5e: 2200 movs r2, #0
8003e60: 609a str r2, [r3, #8]
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
8003e62: 4b04 ldr r3, [pc, #16] @ (8003e74 <SysTick_Config+0x40>)
8003e64: 2207 movs r2, #7
8003e66: 601a str r2, [r3, #0]
SysTick_CTRL_TICKINT_Msk |
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
8003e68: 2300 movs r3, #0
}
8003e6a: 4618 mov r0, r3
8003e6c: 3708 adds r7, #8
8003e6e: 46bd mov sp, r7
8003e70: bd80 pop {r7, pc}
8003e72: bf00 nop
8003e74: e000e010 .word 0xe000e010
08003e78 <HAL_NVIC_SetPriorityGrouping>:
* @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible.
* The pending IRQ priority will be managed only by the subpriority.
* @retval None
*/
void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
8003e78: b580 push {r7, lr}
8003e7a: b082 sub sp, #8
8003e7c: af00 add r7, sp, #0
8003e7e: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
/* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
NVIC_SetPriorityGrouping(PriorityGroup);
8003e80: 6878 ldr r0, [r7, #4]
8003e82: f7ff ff29 bl 8003cd8 <__NVIC_SetPriorityGrouping>
}
8003e86: bf00 nop
8003e88: 3708 adds r7, #8
8003e8a: 46bd mov sp, r7
8003e8c: bd80 pop {r7, pc}
08003e8e <HAL_NVIC_SetPriority>:
* This parameter can be a value between 0 and 15
* A lower priority value indicates a higher priority.
* @retval None
*/
void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
8003e8e: b580 push {r7, lr}
8003e90: b086 sub sp, #24
8003e92: af00 add r7, sp, #0
8003e94: 4603 mov r3, r0
8003e96: 60b9 str r1, [r7, #8]
8003e98: 607a str r2, [r7, #4]
8003e9a: 73fb strb r3, [r7, #15]
/* Check the parameters */
assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
prioritygroup = NVIC_GetPriorityGrouping();
8003e9c: f7ff ff40 bl 8003d20 <__NVIC_GetPriorityGrouping>
8003ea0: 6178 str r0, [r7, #20]
NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
8003ea2: 687a ldr r2, [r7, #4]
8003ea4: 68b9 ldr r1, [r7, #8]
8003ea6: 6978 ldr r0, [r7, #20]
8003ea8: f7ff ff90 bl 8003dcc <NVIC_EncodePriority>
8003eac: 4602 mov r2, r0
8003eae: f997 300f ldrsb.w r3, [r7, #15]
8003eb2: 4611 mov r1, r2
8003eb4: 4618 mov r0, r3
8003eb6: f7ff ff5f bl 8003d78 <__NVIC_SetPriority>
}
8003eba: bf00 nop
8003ebc: 3718 adds r7, #24
8003ebe: 46bd mov sp, r7
8003ec0: bd80 pop {r7, pc}
08003ec2 <HAL_NVIC_EnableIRQ>:
* This parameter can be an enumerator of IRQn_Type enumeration
* (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32g4xxxx.h))
* @retval None
*/
void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
{
8003ec2: b580 push {r7, lr}
8003ec4: b082 sub sp, #8
8003ec6: af00 add r7, sp, #0
8003ec8: 4603 mov r3, r0
8003eca: 71fb strb r3, [r7, #7]
/* Check the parameters */
assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
/* Enable interrupt */
NVIC_EnableIRQ(IRQn);
8003ecc: f997 3007 ldrsb.w r3, [r7, #7]
8003ed0: 4618 mov r0, r3
8003ed2: f7ff ff33 bl 8003d3c <__NVIC_EnableIRQ>
}
8003ed6: bf00 nop
8003ed8: 3708 adds r7, #8
8003eda: 46bd mov sp, r7
8003edc: bd80 pop {r7, pc}
08003ede <HAL_SYSTICK_Config>:
* @param TicksNumb: Specifies the ticks Number of ticks between two interrupts.
* @retval status: - 0 Function succeeded.
* - 1 Function failed.
*/
uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
{
8003ede: b580 push {r7, lr}
8003ee0: b082 sub sp, #8
8003ee2: af00 add r7, sp, #0
8003ee4: 6078 str r0, [r7, #4]
return SysTick_Config(TicksNumb);
8003ee6: 6878 ldr r0, [r7, #4]
8003ee8: f7ff ffa4 bl 8003e34 <SysTick_Config>
8003eec: 4603 mov r3, r0
}
8003eee: 4618 mov r0, r3
8003ef0: 3708 adds r7, #8
8003ef2: 46bd mov sp, r7
8003ef4: bd80 pop {r7, pc}
08003ef6 <HAL_DAC_Init>:
* @param hdac pointer to a DAC_HandleTypeDef structure that contains
* the configuration information for the specified DAC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac)
{
8003ef6: b580 push {r7, lr}
8003ef8: b082 sub sp, #8
8003efa: af00 add r7, sp, #0
8003efc: 6078 str r0, [r7, #4]
/* Check the DAC peripheral handle */
if (hdac == NULL)
8003efe: 687b ldr r3, [r7, #4]
8003f00: 2b00 cmp r3, #0
8003f02: d101 bne.n 8003f08 <HAL_DAC_Init+0x12>
{
return HAL_ERROR;
8003f04: 2301 movs r3, #1
8003f06: e014 b.n 8003f32 <HAL_DAC_Init+0x3c>
}
/* Check the parameters */
assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
if (hdac->State == HAL_DAC_STATE_RESET)
8003f08: 687b ldr r3, [r7, #4]
8003f0a: 791b ldrb r3, [r3, #4]
8003f0c: b2db uxtb r3, r3
8003f0e: 2b00 cmp r3, #0
8003f10: d105 bne.n 8003f1e <HAL_DAC_Init+0x28>
hdac->MspInitCallback = HAL_DAC_MspInit;
}
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
/* Allocate lock resource and initialize it */
hdac->Lock = HAL_UNLOCKED;
8003f12: 687b ldr r3, [r7, #4]
8003f14: 2200 movs r2, #0
8003f16: 715a strb r2, [r3, #5]
#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)
/* Init the low level hardware */
hdac->MspInitCallback(hdac);
#else
/* Init the low level hardware */
HAL_DAC_MspInit(hdac);
8003f18: 6878 ldr r0, [r7, #4]
8003f1a: f7fd fb73 bl 8001604 <HAL_DAC_MspInit>
#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */
}
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_BUSY;
8003f1e: 687b ldr r3, [r7, #4]
8003f20: 2202 movs r2, #2
8003f22: 711a strb r2, [r3, #4]
/* Set DAC error code to none */
hdac->ErrorCode = HAL_DAC_ERROR_NONE;
8003f24: 687b ldr r3, [r7, #4]
8003f26: 2200 movs r2, #0
8003f28: 611a str r2, [r3, #16]
/* Initialize the DAC state*/
hdac->State = HAL_DAC_STATE_READY;
8003f2a: 687b ldr r3, [r7, #4]
8003f2c: 2201 movs r2, #1
8003f2e: 711a strb r2, [r3, #4]
/* Return function status */
return HAL_OK;
8003f30: 2300 movs r3, #0
}
8003f32: 4618 mov r0, r3
8003f34: 3708 adds r7, #8
8003f36: 46bd mov sp, r7
8003f38: bd80 pop {r7, pc}
...
08003f3c <HAL_DAC_Start>:
* (1) On this STM32 series, parameter not available on all instances.
* Refer to device datasheet for channels availability.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel)
{
8003f3c: b480 push {r7}
8003f3e: b085 sub sp, #20
8003f40: af00 add r7, sp, #0
8003f42: 6078 str r0, [r7, #4]
8003f44: 6039 str r1, [r7, #0]
__IO uint32_t wait_loop_index;
/* Check the DAC peripheral handle */
if (hdac == NULL)
8003f46: 687b ldr r3, [r7, #4]
8003f48: 2b00 cmp r3, #0
8003f4a: d101 bne.n 8003f50 <HAL_DAC_Start+0x14>
{
return HAL_ERROR;
8003f4c: 2301 movs r3, #1
8003f4e: e056 b.n 8003ffe <HAL_DAC_Start+0xc2>
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
/* Process locked */
__HAL_LOCK(hdac);
8003f50: 687b ldr r3, [r7, #4]
8003f52: 795b ldrb r3, [r3, #5]
8003f54: 2b01 cmp r3, #1
8003f56: d101 bne.n 8003f5c <HAL_DAC_Start+0x20>
8003f58: 2302 movs r3, #2
8003f5a: e050 b.n 8003ffe <HAL_DAC_Start+0xc2>
8003f5c: 687b ldr r3, [r7, #4]
8003f5e: 2201 movs r2, #1
8003f60: 715a strb r2, [r3, #5]
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
8003f62: 687b ldr r3, [r7, #4]
8003f64: 2202 movs r2, #2
8003f66: 711a strb r2, [r3, #4]
/* Enable the Peripheral */
__HAL_DAC_ENABLE(hdac, Channel);
8003f68: 687b ldr r3, [r7, #4]
8003f6a: 681b ldr r3, [r3, #0]
8003f6c: 6819 ldr r1, [r3, #0]
8003f6e: 683b ldr r3, [r7, #0]
8003f70: f003 0310 and.w r3, r3, #16
8003f74: 2201 movs r2, #1
8003f76: 409a lsls r2, r3
8003f78: 687b ldr r3, [r7, #4]
8003f7a: 681b ldr r3, [r3, #0]
8003f7c: 430a orrs r2, r1
8003f7e: 601a str r2, [r3, #0]
/* Ensure minimum wait before using peripheral after enabling it */
/* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially CPU processing cycles, scaling in us split to not exceed 32 */
/* bits register capacity and handle low frequency. */
wait_loop_index = ((DAC_DELAY_STARTUP_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
8003f80: 4b22 ldr r3, [pc, #136] @ (800400c <HAL_DAC_Start+0xd0>)
8003f82: 681b ldr r3, [r3, #0]
8003f84: 099b lsrs r3, r3, #6
8003f86: 4a22 ldr r2, [pc, #136] @ (8004010 <HAL_DAC_Start+0xd4>)
8003f88: fba2 2303 umull r2, r3, r2, r3
8003f8c: 099b lsrs r3, r3, #6
8003f8e: 3301 adds r3, #1
8003f90: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8003f92: e002 b.n 8003f9a <HAL_DAC_Start+0x5e>
{
wait_loop_index--;
8003f94: 68fb ldr r3, [r7, #12]
8003f96: 3b01 subs r3, #1
8003f98: 60fb str r3, [r7, #12]
while (wait_loop_index != 0UL)
8003f9a: 68fb ldr r3, [r7, #12]
8003f9c: 2b00 cmp r3, #0
8003f9e: d1f9 bne.n 8003f94 <HAL_DAC_Start+0x58>
}
if (Channel == DAC_CHANNEL_1)
8003fa0: 683b ldr r3, [r7, #0]
8003fa2: 2b00 cmp r3, #0
8003fa4: d10f bne.n 8003fc6 <HAL_DAC_Start+0x8a>
{
/* Check if software trigger enabled */
if ((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == DAC_TRIGGER_SOFTWARE)
8003fa6: 687b ldr r3, [r7, #4]
8003fa8: 681b ldr r3, [r3, #0]
8003faa: 681b ldr r3, [r3, #0]
8003fac: f003 033e and.w r3, r3, #62 @ 0x3e
8003fb0: 2b02 cmp r3, #2
8003fb2: d11d bne.n 8003ff0 <HAL_DAC_Start+0xb4>
{
/* Enable the selected DAC software conversion */
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
8003fb4: 687b ldr r3, [r7, #4]
8003fb6: 681b ldr r3, [r3, #0]
8003fb8: 685a ldr r2, [r3, #4]
8003fba: 687b ldr r3, [r7, #4]
8003fbc: 681b ldr r3, [r3, #0]
8003fbe: f042 0201 orr.w r2, r2, #1
8003fc2: 605a str r2, [r3, #4]
8003fc4: e014 b.n 8003ff0 <HAL_DAC_Start+0xb4>
}
else
{
/* Check if software trigger enabled */
if ((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_TRIGGER_SOFTWARE << (Channel & 0x10UL)))
8003fc6: 687b ldr r3, [r7, #4]
8003fc8: 681b ldr r3, [r3, #0]
8003fca: 681b ldr r3, [r3, #0]
8003fcc: f403 1278 and.w r2, r3, #4063232 @ 0x3e0000
8003fd0: 683b ldr r3, [r7, #0]
8003fd2: f003 0310 and.w r3, r3, #16
8003fd6: 2102 movs r1, #2
8003fd8: fa01 f303 lsl.w r3, r1, r3
8003fdc: 429a cmp r2, r3
8003fde: d107 bne.n 8003ff0 <HAL_DAC_Start+0xb4>
{
/* Enable the selected DAC software conversion*/
SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
8003fe0: 687b ldr r3, [r7, #4]
8003fe2: 681b ldr r3, [r3, #0]
8003fe4: 685a ldr r2, [r3, #4]
8003fe6: 687b ldr r3, [r7, #4]
8003fe8: 681b ldr r3, [r3, #0]
8003fea: f042 0202 orr.w r2, r2, #2
8003fee: 605a str r2, [r3, #4]
}
}
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
8003ff0: 687b ldr r3, [r7, #4]
8003ff2: 2201 movs r2, #1
8003ff4: 711a strb r2, [r3, #4]
/* Process unlocked */
__HAL_UNLOCK(hdac);
8003ff6: 687b ldr r3, [r7, #4]
8003ff8: 2200 movs r2, #0
8003ffa: 715a strb r2, [r3, #5]
/* Return function status */
return HAL_OK;
8003ffc: 2300 movs r3, #0
}
8003ffe: 4618 mov r0, r3
8004000: 3714 adds r7, #20
8004002: 46bd mov sp, r7
8004004: f85d 7b04 ldr.w r7, [sp], #4
8004008: 4770 bx lr
800400a: bf00 nop
800400c: 20000000 .word 0x20000000
8004010: 053e2d63 .word 0x053e2d63
08004014 <HAL_DAC_SetValue>:
* @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
* @param Data Data to be loaded in the selected data holding register.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
{
8004014: b480 push {r7}
8004016: b087 sub sp, #28
8004018: af00 add r7, sp, #0
800401a: 60f8 str r0, [r7, #12]
800401c: 60b9 str r1, [r7, #8]
800401e: 607a str r2, [r7, #4]
8004020: 603b str r3, [r7, #0]
__IO uint32_t tmp = 0UL;
8004022: 2300 movs r3, #0
8004024: 617b str r3, [r7, #20]
/* Check the DAC peripheral handle */
if (hdac == NULL)
8004026: 68fb ldr r3, [r7, #12]
8004028: 2b00 cmp r3, #0
800402a: d101 bne.n 8004030 <HAL_DAC_SetValue+0x1c>
{
return HAL_ERROR;
800402c: 2301 movs r3, #1
800402e: e018 b.n 8004062 <HAL_DAC_SetValue+0x4e>
/* Check the parameters */
assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
assert_param(IS_DAC_ALIGN(Alignment));
/* In case DMA Double data mode is activated, DATA range is almost full uin32_t one: no check */
if ((hdac->Instance->MCR & (DAC_MCR_DMADOUBLE1 << (Channel & 0x10UL))) == 0UL)
8004030: 68fb ldr r3, [r7, #12]
8004032: 681b ldr r3, [r3, #0]
8004034: 6bdb ldr r3, [r3, #60] @ 0x3c
{
assert_param(IS_DAC_DATA(Data));
}
tmp = (uint32_t)hdac->Instance;
8004036: 68fb ldr r3, [r7, #12]
8004038: 681b ldr r3, [r3, #0]
800403a: 617b str r3, [r7, #20]
if (Channel == DAC_CHANNEL_1)
800403c: 68bb ldr r3, [r7, #8]
800403e: 2b00 cmp r3, #0
8004040: d105 bne.n 800404e <HAL_DAC_SetValue+0x3a>
{
tmp += DAC_DHR12R1_ALIGNMENT(Alignment);
8004042: 697a ldr r2, [r7, #20]
8004044: 687b ldr r3, [r7, #4]
8004046: 4413 add r3, r2
8004048: 3308 adds r3, #8
800404a: 617b str r3, [r7, #20]
800404c: e004 b.n 8004058 <HAL_DAC_SetValue+0x44>
}
else
{
tmp += DAC_DHR12R2_ALIGNMENT(Alignment);
800404e: 697a ldr r2, [r7, #20]
8004050: 687b ldr r3, [r7, #4]
8004052: 4413 add r3, r2
8004054: 3314 adds r3, #20
8004056: 617b str r3, [r7, #20]
}
/* Set the DAC channel selected data holding register */
*(__IO uint32_t *) tmp = Data;
8004058: 697b ldr r3, [r7, #20]
800405a: 461a mov r2, r3
800405c: 683b ldr r3, [r7, #0]
800405e: 6013 str r3, [r2, #0]
/* Return function status */
return HAL_OK;
8004060: 2300 movs r3, #0
}
8004062: 4618 mov r0, r3
8004064: 371c adds r7, #28
8004066: 46bd mov sp, r7
8004068: f85d 7b04 ldr.w r7, [sp], #4
800406c: 4770 bx lr
...
08004070 <HAL_DAC_ConfigChannel>:
* Refer to device datasheet for channels availability.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac,
const DAC_ChannelConfTypeDef *sConfig, uint32_t Channel)
{
8004070: b580 push {r7, lr}
8004072: b08a sub sp, #40 @ 0x28
8004074: af00 add r7, sp, #0
8004076: 60f8 str r0, [r7, #12]
8004078: 60b9 str r1, [r7, #8]
800407a: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
800407c: 2300 movs r3, #0
800407e: 77fb strb r3, [r7, #31]
uint32_t tickstart;
uint32_t hclkfreq;
uint32_t connectOnChip;
/* Check the DAC peripheral handle and channel configuration struct */
if ((hdac == NULL) || (sConfig == NULL))
8004080: 68fb ldr r3, [r7, #12]
8004082: 2b00 cmp r3, #0
8004084: d002 beq.n 800408c <HAL_DAC_ConfigChannel+0x1c>
8004086: 68bb ldr r3, [r7, #8]
8004088: 2b00 cmp r3, #0
800408a: d101 bne.n 8004090 <HAL_DAC_ConfigChannel+0x20>
{
return HAL_ERROR;
800408c: 2301 movs r3, #1
800408e: e1a1 b.n 80043d4 <HAL_DAC_ConfigChannel+0x364>
if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER)
{
assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue));
}
assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold));
if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE)
8004090: 68bb ldr r3, [r7, #8]
8004092: 689b ldr r3, [r3, #8]
8004094: 2b04 cmp r3, #4
assert_param(IS_DAC_CHANNEL(hdac->Instance, Channel));
assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_DMADoubleDataMode));
assert_param(IS_FUNCTIONAL_STATE(sConfig->DAC_SignedFormat));
/* Process locked */
__HAL_LOCK(hdac);
8004096: 68fb ldr r3, [r7, #12]
8004098: 795b ldrb r3, [r3, #5]
800409a: 2b01 cmp r3, #1
800409c: d101 bne.n 80040a2 <HAL_DAC_ConfigChannel+0x32>
800409e: 2302 movs r3, #2
80040a0: e198 b.n 80043d4 <HAL_DAC_ConfigChannel+0x364>
80040a2: 68fb ldr r3, [r7, #12]
80040a4: 2201 movs r2, #1
80040a6: 715a strb r2, [r3, #5]
/* Change DAC state */
hdac->State = HAL_DAC_STATE_BUSY;
80040a8: 68fb ldr r3, [r7, #12]
80040aa: 2202 movs r2, #2
80040ac: 711a strb r2, [r3, #4]
/* Sample and hold configuration */
if (sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE)
80040ae: 68bb ldr r3, [r7, #8]
80040b0: 689b ldr r3, [r3, #8]
80040b2: 2b04 cmp r3, #4
80040b4: d17a bne.n 80041ac <HAL_DAC_ConfigChannel+0x13c>
{
/* Get timeout */
tickstart = HAL_GetTick();
80040b6: f7fd fd19 bl 8001aec <HAL_GetTick>
80040ba: 61b8 str r0, [r7, #24]
if (Channel == DAC_CHANNEL_1)
80040bc: 687b ldr r3, [r7, #4]
80040be: 2b00 cmp r3, #0
80040c0: d13d bne.n 800413e <HAL_DAC_ConfigChannel+0xce>
{
/* SHSR1 can be written when BWST1 is cleared */
while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
80040c2: e018 b.n 80040f6 <HAL_DAC_ConfigChannel+0x86>
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
80040c4: f7fd fd12 bl 8001aec <HAL_GetTick>
80040c8: 4602 mov r2, r0
80040ca: 69bb ldr r3, [r7, #24]
80040cc: 1ad3 subs r3, r2, r3
80040ce: 2b01 cmp r3, #1
80040d0: d911 bls.n 80040f6 <HAL_DAC_ConfigChannel+0x86>
{
/* New check to avoid false timeout detection in case of preemption */
if (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
80040d2: 68fb ldr r3, [r7, #12]
80040d4: 681b ldr r3, [r3, #0]
80040d6: 6b5b ldr r3, [r3, #52] @ 0x34
80040d8: f403 4300 and.w r3, r3, #32768 @ 0x8000
80040dc: 2b00 cmp r3, #0
80040de: d00a beq.n 80040f6 <HAL_DAC_ConfigChannel+0x86>
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
80040e0: 68fb ldr r3, [r7, #12]
80040e2: 691b ldr r3, [r3, #16]
80040e4: f043 0208 orr.w r2, r3, #8
80040e8: 68fb ldr r3, [r7, #12]
80040ea: 611a str r2, [r3, #16]
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
80040ec: 68fb ldr r3, [r7, #12]
80040ee: 2203 movs r2, #3
80040f0: 711a strb r2, [r3, #4]
return HAL_TIMEOUT;
80040f2: 2303 movs r3, #3
80040f4: e16e b.n 80043d4 <HAL_DAC_ConfigChannel+0x364>
while (((hdac->Instance->SR) & DAC_SR_BWST1) != 0UL)
80040f6: 68fb ldr r3, [r7, #12]
80040f8: 681b ldr r3, [r3, #0]
80040fa: 6b5b ldr r3, [r3, #52] @ 0x34
80040fc: f403 4300 and.w r3, r3, #32768 @ 0x8000
8004100: 2b00 cmp r3, #0
8004102: d1df bne.n 80040c4 <HAL_DAC_ConfigChannel+0x54>
}
}
}
hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
8004104: 68fb ldr r3, [r7, #12]
8004106: 681b ldr r3, [r3, #0]
8004108: 68ba ldr r2, [r7, #8]
800410a: 6a52 ldr r2, [r2, #36] @ 0x24
800410c: 641a str r2, [r3, #64] @ 0x40
800410e: e020 b.n 8004152 <HAL_DAC_ConfigChannel+0xe2>
{
/* SHSR2 can be written when BWST2 is cleared */
while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
{
/* Check for the Timeout */
if ((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG)
8004110: f7fd fcec bl 8001aec <HAL_GetTick>
8004114: 4602 mov r2, r0
8004116: 69bb ldr r3, [r7, #24]
8004118: 1ad3 subs r3, r2, r3
800411a: 2b01 cmp r3, #1
800411c: d90f bls.n 800413e <HAL_DAC_ConfigChannel+0xce>
{
/* New check to avoid false timeout detection in case of preemption */
if (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
800411e: 68fb ldr r3, [r7, #12]
8004120: 681b ldr r3, [r3, #0]
8004122: 6b5b ldr r3, [r3, #52] @ 0x34
8004124: 2b00 cmp r3, #0
8004126: da0a bge.n 800413e <HAL_DAC_ConfigChannel+0xce>
{
/* Update error code */
SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT);
8004128: 68fb ldr r3, [r7, #12]
800412a: 691b ldr r3, [r3, #16]
800412c: f043 0208 orr.w r2, r3, #8
8004130: 68fb ldr r3, [r7, #12]
8004132: 611a str r2, [r3, #16]
/* Change the DMA state */
hdac->State = HAL_DAC_STATE_TIMEOUT;
8004134: 68fb ldr r3, [r7, #12]
8004136: 2203 movs r2, #3
8004138: 711a strb r2, [r3, #4]
return HAL_TIMEOUT;
800413a: 2303 movs r3, #3
800413c: e14a b.n 80043d4 <HAL_DAC_ConfigChannel+0x364>
while (((hdac->Instance->SR) & DAC_SR_BWST2) != 0UL)
800413e: 68fb ldr r3, [r7, #12]
8004140: 681b ldr r3, [r3, #0]
8004142: 6b5b ldr r3, [r3, #52] @ 0x34
8004144: 2b00 cmp r3, #0
8004146: dbe3 blt.n 8004110 <HAL_DAC_ConfigChannel+0xa0>
}
}
}
hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime;
8004148: 68fb ldr r3, [r7, #12]
800414a: 681b ldr r3, [r3, #0]
800414c: 68ba ldr r2, [r7, #8]
800414e: 6a52 ldr r2, [r2, #36] @ 0x24
8004150: 645a str r2, [r3, #68] @ 0x44
}
/* HoldTime */
MODIFY_REG(hdac->Instance->SHHR, DAC_SHHR_THOLD1 << (Channel & 0x10UL),
8004152: 68fb ldr r3, [r7, #12]
8004154: 681b ldr r3, [r3, #0]
8004156: 6c9a ldr r2, [r3, #72] @ 0x48
8004158: 687b ldr r3, [r7, #4]
800415a: f003 0310 and.w r3, r3, #16
800415e: f240 31ff movw r1, #1023 @ 0x3ff
8004162: fa01 f303 lsl.w r3, r1, r3
8004166: 43db mvns r3, r3
8004168: ea02 0103 and.w r1, r2, r3
800416c: 68bb ldr r3, [r7, #8]
800416e: 6a9a ldr r2, [r3, #40] @ 0x28
8004170: 687b ldr r3, [r7, #4]
8004172: f003 0310 and.w r3, r3, #16
8004176: 409a lsls r2, r3
8004178: 68fb ldr r3, [r7, #12]
800417a: 681b ldr r3, [r3, #0]
800417c: 430a orrs r2, r1
800417e: 649a str r2, [r3, #72] @ 0x48
(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime) << (Channel & 0x10UL));
/* RefreshTime */
MODIFY_REG(hdac->Instance->SHRR, DAC_SHRR_TREFRESH1 << (Channel & 0x10UL),
8004180: 68fb ldr r3, [r7, #12]
8004182: 681b ldr r3, [r3, #0]
8004184: 6cda ldr r2, [r3, #76] @ 0x4c
8004186: 687b ldr r3, [r7, #4]
8004188: f003 0310 and.w r3, r3, #16
800418c: 21ff movs r1, #255 @ 0xff
800418e: fa01 f303 lsl.w r3, r1, r3
8004192: 43db mvns r3, r3
8004194: ea02 0103 and.w r1, r2, r3
8004198: 68bb ldr r3, [r7, #8]
800419a: 6ada ldr r2, [r3, #44] @ 0x2c
800419c: 687b ldr r3, [r7, #4]
800419e: f003 0310 and.w r3, r3, #16
80041a2: 409a lsls r2, r3
80041a4: 68fb ldr r3, [r7, #12]
80041a6: 681b ldr r3, [r3, #0]
80041a8: 430a orrs r2, r1
80041aa: 64da str r2, [r3, #76] @ 0x4c
(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime) << (Channel & 0x10UL));
}
if (sConfig->DAC_UserTrimming == DAC_TRIMMING_USER)
80041ac: 68bb ldr r3, [r7, #8]
80041ae: 69db ldr r3, [r3, #28]
80041b0: 2b01 cmp r3, #1
80041b2: d11d bne.n 80041f0 <HAL_DAC_ConfigChannel+0x180>
/* USER TRIMMING */
{
/* Get the DAC CCR value */
tmpreg1 = hdac->Instance->CCR;
80041b4: 68fb ldr r3, [r7, #12]
80041b6: 681b ldr r3, [r3, #0]
80041b8: 6b9b ldr r3, [r3, #56] @ 0x38
80041ba: 627b str r3, [r7, #36] @ 0x24
/* Clear trimming value */
tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << (Channel & 0x10UL));
80041bc: 687b ldr r3, [r7, #4]
80041be: f003 0310 and.w r3, r3, #16
80041c2: 221f movs r2, #31
80041c4: fa02 f303 lsl.w r3, r2, r3
80041c8: 43db mvns r3, r3
80041ca: 6a7a ldr r2, [r7, #36] @ 0x24
80041cc: 4013 ands r3, r2
80041ce: 627b str r3, [r7, #36] @ 0x24
/* Configure for the selected trimming offset */
tmpreg2 = sConfig->DAC_TrimmingValue;
80041d0: 68bb ldr r3, [r7, #8]
80041d2: 6a1b ldr r3, [r3, #32]
80041d4: 617b str r3, [r7, #20]
/* Calculate CCR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
80041d6: 687b ldr r3, [r7, #4]
80041d8: f003 0310 and.w r3, r3, #16
80041dc: 697a ldr r2, [r7, #20]
80041de: fa02 f303 lsl.w r3, r2, r3
80041e2: 6a7a ldr r2, [r7, #36] @ 0x24
80041e4: 4313 orrs r3, r2
80041e6: 627b str r3, [r7, #36] @ 0x24
/* Write to DAC CCR */
hdac->Instance->CCR = tmpreg1;
80041e8: 68fb ldr r3, [r7, #12]
80041ea: 681b ldr r3, [r3, #0]
80041ec: 6a7a ldr r2, [r7, #36] @ 0x24
80041ee: 639a str r2, [r3, #56] @ 0x38
}
/* else factory trimming is used (factory setting are available at reset)*/
/* SW Nothing has nothing to do */
/* Get the DAC MCR value */
tmpreg1 = hdac->Instance->MCR;
80041f0: 68fb ldr r3, [r7, #12]
80041f2: 681b ldr r3, [r3, #0]
80041f4: 6bdb ldr r3, [r3, #60] @ 0x3c
80041f6: 627b str r3, [r7, #36] @ 0x24
/* Clear DAC_MCR_MODEx bits */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << (Channel & 0x10UL));
80041f8: 687b ldr r3, [r7, #4]
80041fa: f003 0310 and.w r3, r3, #16
80041fe: 2207 movs r2, #7
8004200: fa02 f303 lsl.w r3, r2, r3
8004204: 43db mvns r3, r3
8004206: 6a7a ldr r2, [r7, #36] @ 0x24
8004208: 4013 ands r3, r2
800420a: 627b str r3, [r7, #36] @ 0x24
/* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */
if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_EXTERNAL)
800420c: 68bb ldr r3, [r7, #8]
800420e: 699b ldr r3, [r3, #24]
8004210: 2b01 cmp r3, #1
8004212: d102 bne.n 800421a <HAL_DAC_ConfigChannel+0x1aa>
{
connectOnChip = 0x00000000UL;
8004214: 2300 movs r3, #0
8004216: 623b str r3, [r7, #32]
8004218: e00f b.n 800423a <HAL_DAC_ConfigChannel+0x1ca>
}
else if (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_INTERNAL)
800421a: 68bb ldr r3, [r7, #8]
800421c: 699b ldr r3, [r3, #24]
800421e: 2b02 cmp r3, #2
8004220: d102 bne.n 8004228 <HAL_DAC_ConfigChannel+0x1b8>
{
connectOnChip = DAC_MCR_MODE1_0;
8004222: 2301 movs r3, #1
8004224: 623b str r3, [r7, #32]
8004226: e008 b.n 800423a <HAL_DAC_ConfigChannel+0x1ca>
}
else /* (sConfig->DAC_ConnectOnChipPeripheral == DAC_CHIPCONNECT_BOTH) */
{
if (sConfig->DAC_OutputBuffer == DAC_OUTPUTBUFFER_ENABLE)
8004228: 68bb ldr r3, [r7, #8]
800422a: 695b ldr r3, [r3, #20]
800422c: 2b00 cmp r3, #0
800422e: d102 bne.n 8004236 <HAL_DAC_ConfigChannel+0x1c6>
{
connectOnChip = DAC_MCR_MODE1_0;
8004230: 2301 movs r3, #1
8004232: 623b str r3, [r7, #32]
8004234: e001 b.n 800423a <HAL_DAC_ConfigChannel+0x1ca>
}
else
{
connectOnChip = 0x00000000UL;
8004236: 2300 movs r3, #0
8004238: 623b str r3, [r7, #32]
}
}
tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | connectOnChip);
800423a: 68bb ldr r3, [r7, #8]
800423c: 689a ldr r2, [r3, #8]
800423e: 68bb ldr r3, [r7, #8]
8004240: 695b ldr r3, [r3, #20]
8004242: 4313 orrs r3, r2
8004244: 6a3a ldr r2, [r7, #32]
8004246: 4313 orrs r3, r2
8004248: 617b str r3, [r7, #20]
/* Clear DAC_MCR_DMADOUBLEx */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_DMADOUBLE1)) << (Channel & 0x10UL));
800424a: 687b ldr r3, [r7, #4]
800424c: f003 0310 and.w r3, r3, #16
8004250: f44f 7280 mov.w r2, #256 @ 0x100
8004254: fa02 f303 lsl.w r3, r2, r3
8004258: 43db mvns r3, r3
800425a: 6a7a ldr r2, [r7, #36] @ 0x24
800425c: 4013 ands r3, r2
800425e: 627b str r3, [r7, #36] @ 0x24
/* Configure for the selected DAC channel: DMA double data mode */
tmpreg2 |= (sConfig->DAC_DMADoubleDataMode == ENABLE) ? DAC_MCR_DMADOUBLE1 : 0UL;
8004260: 68bb ldr r3, [r7, #8]
8004262: 791b ldrb r3, [r3, #4]
8004264: 2b01 cmp r3, #1
8004266: d102 bne.n 800426e <HAL_DAC_ConfigChannel+0x1fe>
8004268: f44f 7380 mov.w r3, #256 @ 0x100
800426c: e000 b.n 8004270 <HAL_DAC_ConfigChannel+0x200>
800426e: 2300 movs r3, #0
8004270: 697a ldr r2, [r7, #20]
8004272: 4313 orrs r3, r2
8004274: 617b str r3, [r7, #20]
/* Clear DAC_MCR_SINFORMATx */
tmpreg1 &= ~(((uint32_t)(DAC_MCR_SINFORMAT1)) << (Channel & 0x10UL));
8004276: 687b ldr r3, [r7, #4]
8004278: f003 0310 and.w r3, r3, #16
800427c: f44f 7200 mov.w r2, #512 @ 0x200
8004280: fa02 f303 lsl.w r3, r2, r3
8004284: 43db mvns r3, r3
8004286: 6a7a ldr r2, [r7, #36] @ 0x24
8004288: 4013 ands r3, r2
800428a: 627b str r3, [r7, #36] @ 0x24
/* Configure for the selected DAC channel: Signed format */
tmpreg2 |= (sConfig->DAC_SignedFormat == ENABLE) ? DAC_MCR_SINFORMAT1 : 0UL;
800428c: 68bb ldr r3, [r7, #8]
800428e: 795b ldrb r3, [r3, #5]
8004290: 2b01 cmp r3, #1
8004292: d102 bne.n 800429a <HAL_DAC_ConfigChannel+0x22a>
8004294: f44f 7300 mov.w r3, #512 @ 0x200
8004298: e000 b.n 800429c <HAL_DAC_ConfigChannel+0x22c>
800429a: 2300 movs r3, #0
800429c: 697a ldr r2, [r7, #20]
800429e: 4313 orrs r3, r2
80042a0: 617b str r3, [r7, #20]
/* Clear DAC_MCR_HFSEL bits */
tmpreg1 &= ~(DAC_MCR_HFSEL);
80042a2: 6a7b ldr r3, [r7, #36] @ 0x24
80042a4: f423 4340 bic.w r3, r3, #49152 @ 0xc000
80042a8: 627b str r3, [r7, #36] @ 0x24
/* Configure for both DAC channels: high frequency mode */
if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_AUTOMATIC == sConfig->DAC_HighFrequency)
80042aa: 68bb ldr r3, [r7, #8]
80042ac: 681b ldr r3, [r3, #0]
80042ae: 2b02 cmp r3, #2
80042b0: d114 bne.n 80042dc <HAL_DAC_ConfigChannel+0x26c>
{
hclkfreq = HAL_RCC_GetHCLKFreq();
80042b2: f002 fdc5 bl 8006e40 <HAL_RCC_GetHCLKFreq>
80042b6: 6138 str r0, [r7, #16]
if (hclkfreq > HFSEL_ENABLE_THRESHOLD_160MHZ)
80042b8: 693b ldr r3, [r7, #16]
80042ba: 4a48 ldr r2, [pc, #288] @ (80043dc <HAL_DAC_ConfigChannel+0x36c>)
80042bc: 4293 cmp r3, r2
80042be: d904 bls.n 80042ca <HAL_DAC_ConfigChannel+0x25a>
{
tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_160MHZ;
80042c0: 6a7b ldr r3, [r7, #36] @ 0x24
80042c2: f443 4300 orr.w r3, r3, #32768 @ 0x8000
80042c6: 627b str r3, [r7, #36] @ 0x24
80042c8: e00f b.n 80042ea <HAL_DAC_ConfigChannel+0x27a>
}
else if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ)
80042ca: 693b ldr r3, [r7, #16]
80042cc: 4a44 ldr r2, [pc, #272] @ (80043e0 <HAL_DAC_ConfigChannel+0x370>)
80042ce: 4293 cmp r3, r2
80042d0: d90a bls.n 80042e8 <HAL_DAC_ConfigChannel+0x278>
{
tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ;
80042d2: 6a7b ldr r3, [r7, #36] @ 0x24
80042d4: f443 4380 orr.w r3, r3, #16384 @ 0x4000
80042d8: 627b str r3, [r7, #36] @ 0x24
80042da: e006 b.n 80042ea <HAL_DAC_ConfigChannel+0x27a>
tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE;
}
}
else
{
tmpreg1 |= sConfig->DAC_HighFrequency;
80042dc: 68bb ldr r3, [r7, #8]
80042de: 681b ldr r3, [r3, #0]
80042e0: 6a7a ldr r2, [r7, #36] @ 0x24
80042e2: 4313 orrs r3, r2
80042e4: 627b str r3, [r7, #36] @ 0x24
80042e6: e000 b.n 80042ea <HAL_DAC_ConfigChannel+0x27a>
tmpreg1 |= DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE;
80042e8: bf00 nop
}
/* Calculate MCR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
80042ea: 687b ldr r3, [r7, #4]
80042ec: f003 0310 and.w r3, r3, #16
80042f0: 697a ldr r2, [r7, #20]
80042f2: fa02 f303 lsl.w r3, r2, r3
80042f6: 6a7a ldr r2, [r7, #36] @ 0x24
80042f8: 4313 orrs r3, r2
80042fa: 627b str r3, [r7, #36] @ 0x24
/* Write to DAC MCR */
hdac->Instance->MCR = tmpreg1;
80042fc: 68fb ldr r3, [r7, #12]
80042fe: 681b ldr r3, [r3, #0]
8004300: 6a7a ldr r2, [r7, #36] @ 0x24
8004302: 63da str r2, [r3, #60] @ 0x3c
/* DAC in normal operating mode hence clear DAC_CR_CENx bit */
CLEAR_BIT(hdac->Instance->CR, DAC_CR_CEN1 << (Channel & 0x10UL));
8004304: 68fb ldr r3, [r7, #12]
8004306: 681b ldr r3, [r3, #0]
8004308: 6819 ldr r1, [r3, #0]
800430a: 687b ldr r3, [r7, #4]
800430c: f003 0310 and.w r3, r3, #16
8004310: f44f 4280 mov.w r2, #16384 @ 0x4000
8004314: fa02 f303 lsl.w r3, r2, r3
8004318: 43da mvns r2, r3
800431a: 68fb ldr r3, [r7, #12]
800431c: 681b ldr r3, [r3, #0]
800431e: 400a ands r2, r1
8004320: 601a str r2, [r3, #0]
/* Get the DAC CR value */
tmpreg1 = hdac->Instance->CR;
8004322: 68fb ldr r3, [r7, #12]
8004324: 681b ldr r3, [r3, #0]
8004326: 681b ldr r3, [r3, #0]
8004328: 627b str r3, [r7, #36] @ 0x24
/* Clear TENx, TSELx, WAVEx and MAMPx bits */
tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << (Channel & 0x10UL));
800432a: 687b ldr r3, [r7, #4]
800432c: f003 0310 and.w r3, r3, #16
8004330: f640 72fe movw r2, #4094 @ 0xffe
8004334: fa02 f303 lsl.w r3, r2, r3
8004338: 43db mvns r3, r3
800433a: 6a7a ldr r2, [r7, #36] @ 0x24
800433c: 4013 ands r3, r2
800433e: 627b str r3, [r7, #36] @ 0x24
/* Configure for the selected DAC channel: trigger */
/* Set TSELx and TENx bits according to DAC_Trigger value */
tmpreg2 = sConfig->DAC_Trigger;
8004340: 68bb ldr r3, [r7, #8]
8004342: 68db ldr r3, [r3, #12]
8004344: 617b str r3, [r7, #20]
/* Calculate CR register value depending on DAC_Channel */
tmpreg1 |= tmpreg2 << (Channel & 0x10UL);
8004346: 687b ldr r3, [r7, #4]
8004348: f003 0310 and.w r3, r3, #16
800434c: 697a ldr r2, [r7, #20]
800434e: fa02 f303 lsl.w r3, r2, r3
8004352: 6a7a ldr r2, [r7, #36] @ 0x24
8004354: 4313 orrs r3, r2
8004356: 627b str r3, [r7, #36] @ 0x24
/* Write to DAC CR */
hdac->Instance->CR = tmpreg1;
8004358: 68fb ldr r3, [r7, #12]
800435a: 681b ldr r3, [r3, #0]
800435c: 6a7a ldr r2, [r7, #36] @ 0x24
800435e: 601a str r2, [r3, #0]
/* Disable wave generation */
CLEAR_BIT(hdac->Instance->CR, (DAC_CR_WAVE1 << (Channel & 0x10UL)));
8004360: 68fb ldr r3, [r7, #12]
8004362: 681b ldr r3, [r3, #0]
8004364: 6819 ldr r1, [r3, #0]
8004366: 687b ldr r3, [r7, #4]
8004368: f003 0310 and.w r3, r3, #16
800436c: 22c0 movs r2, #192 @ 0xc0
800436e: fa02 f303 lsl.w r3, r2, r3
8004372: 43da mvns r2, r3
8004374: 68fb ldr r3, [r7, #12]
8004376: 681b ldr r3, [r3, #0]
8004378: 400a ands r2, r1
800437a: 601a str r2, [r3, #0]
/* Set STRSTTRIGSELx and STINCTRIGSELx bits according to DAC_Trigger & DAC_Trigger2 values */
tmpreg2 = ((sConfig->DAC_Trigger & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STRSTTRIGSEL1_Pos;
800437c: 68bb ldr r3, [r7, #8]
800437e: 68db ldr r3, [r3, #12]
8004380: 089b lsrs r3, r3, #2
8004382: f003 030f and.w r3, r3, #15
8004386: 617b str r3, [r7, #20]
tmpreg2 |= ((sConfig->DAC_Trigger2 & DAC_CR_TSEL1) >> DAC_CR_TSEL1_Pos) << DAC_STMODR_STINCTRIGSEL1_Pos;
8004388: 68bb ldr r3, [r7, #8]
800438a: 691b ldr r3, [r3, #16]
800438c: 089b lsrs r3, r3, #2
800438e: 021b lsls r3, r3, #8
8004390: f403 6370 and.w r3, r3, #3840 @ 0xf00
8004394: 697a ldr r2, [r7, #20]
8004396: 4313 orrs r3, r2
8004398: 617b str r3, [r7, #20]
/* Modify STMODR register value depending on DAC_Channel */
MODIFY_REG(hdac->Instance->STMODR, (DAC_STMODR_STINCTRIGSEL1 | DAC_STMODR_STRSTTRIGSEL1)
800439a: 68fb ldr r3, [r7, #12]
800439c: 681b ldr r3, [r3, #0]
800439e: 6e1a ldr r2, [r3, #96] @ 0x60
80043a0: 687b ldr r3, [r7, #4]
80043a2: f003 0310 and.w r3, r3, #16
80043a6: f640 710f movw r1, #3855 @ 0xf0f
80043aa: fa01 f303 lsl.w r3, r1, r3
80043ae: 43db mvns r3, r3
80043b0: ea02 0103 and.w r1, r2, r3
80043b4: 687b ldr r3, [r7, #4]
80043b6: f003 0310 and.w r3, r3, #16
80043ba: 697a ldr r2, [r7, #20]
80043bc: 409a lsls r2, r3
80043be: 68fb ldr r3, [r7, #12]
80043c0: 681b ldr r3, [r3, #0]
80043c2: 430a orrs r2, r1
80043c4: 661a str r2, [r3, #96] @ 0x60
<< (Channel & 0x10UL), tmpreg2 << (Channel & 0x10UL));
/* Change DAC state */
hdac->State = HAL_DAC_STATE_READY;
80043c6: 68fb ldr r3, [r7, #12]
80043c8: 2201 movs r2, #1
80043ca: 711a strb r2, [r3, #4]
/* Process unlocked */
__HAL_UNLOCK(hdac);
80043cc: 68fb ldr r3, [r7, #12]
80043ce: 2200 movs r2, #0
80043d0: 715a strb r2, [r3, #5]
/* Return function status */
return status;
80043d2: 7ffb ldrb r3, [r7, #31]
}
80043d4: 4618 mov r0, r3
80043d6: 3728 adds r7, #40 @ 0x28
80043d8: 46bd mov sp, r7
80043da: bd80 pop {r7, pc}
80043dc: 09896800 .word 0x09896800
80043e0: 04c4b400 .word 0x04c4b400
080043e4 <HAL_DMA_Init>:
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
{
80043e4: b580 push {r7, lr}
80043e6: b084 sub sp, #16
80043e8: af00 add r7, sp, #0
80043ea: 6078 str r0, [r7, #4]
uint32_t tmp;
/* Check the DMA handle allocation */
if (hdma == NULL)
80043ec: 687b ldr r3, [r7, #4]
80043ee: 2b00 cmp r3, #0
80043f0: d101 bne.n 80043f6 <HAL_DMA_Init+0x12>
{
return HAL_ERROR;
80043f2: 2301 movs r3, #1
80043f4: e08d b.n 8004512 <HAL_DMA_Init+0x12e>
assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
/* Compute the channel index */
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
80043f6: 687b ldr r3, [r7, #4]
80043f8: 681b ldr r3, [r3, #0]
80043fa: 461a mov r2, r3
80043fc: 4b47 ldr r3, [pc, #284] @ (800451c <HAL_DMA_Init+0x138>)
80043fe: 429a cmp r2, r3
8004400: d80f bhi.n 8004422 <HAL_DMA_Init+0x3e>
{
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2;
8004402: 687b ldr r3, [r7, #4]
8004404: 681b ldr r3, [r3, #0]
8004406: 461a mov r2, r3
8004408: 4b45 ldr r3, [pc, #276] @ (8004520 <HAL_DMA_Init+0x13c>)
800440a: 4413 add r3, r2
800440c: 4a45 ldr r2, [pc, #276] @ (8004524 <HAL_DMA_Init+0x140>)
800440e: fba2 2303 umull r2, r3, r2, r3
8004412: 091b lsrs r3, r3, #4
8004414: 009a lsls r2, r3, #2
8004416: 687b ldr r3, [r7, #4]
8004418: 645a str r2, [r3, #68] @ 0x44
hdma->DmaBaseAddress = DMA1;
800441a: 687b ldr r3, [r7, #4]
800441c: 4a42 ldr r2, [pc, #264] @ (8004528 <HAL_DMA_Init+0x144>)
800441e: 641a str r2, [r3, #64] @ 0x40
8004420: e00e b.n 8004440 <HAL_DMA_Init+0x5c>
}
else
{
/* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2;
8004422: 687b ldr r3, [r7, #4]
8004424: 681b ldr r3, [r3, #0]
8004426: 461a mov r2, r3
8004428: 4b40 ldr r3, [pc, #256] @ (800452c <HAL_DMA_Init+0x148>)
800442a: 4413 add r3, r2
800442c: 4a3d ldr r2, [pc, #244] @ (8004524 <HAL_DMA_Init+0x140>)
800442e: fba2 2303 umull r2, r3, r2, r3
8004432: 091b lsrs r3, r3, #4
8004434: 009a lsls r2, r3, #2
8004436: 687b ldr r3, [r7, #4]
8004438: 645a str r2, [r3, #68] @ 0x44
hdma->DmaBaseAddress = DMA2;
800443a: 687b ldr r3, [r7, #4]
800443c: 4a3c ldr r2, [pc, #240] @ (8004530 <HAL_DMA_Init+0x14c>)
800443e: 641a str r2, [r3, #64] @ 0x40
}
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8004440: 687b ldr r3, [r7, #4]
8004442: 2202 movs r2, #2
8004444: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Get the CR register value */
tmp = hdma->Instance->CCR;
8004448: 687b ldr r3, [r7, #4]
800444a: 681b ldr r3, [r3, #0]
800444c: 681b ldr r3, [r3, #0]
800444e: 60fb str r3, [r7, #12]
/* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE |
8004450: 68fb ldr r3, [r7, #12]
8004452: f423 43ff bic.w r3, r3, #32640 @ 0x7f80
8004456: f023 0370 bic.w r3, r3, #112 @ 0x70
800445a: 60fb str r3, [r7, #12]
DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC |
DMA_CCR_DIR | DMA_CCR_MEM2MEM));
/* Prepare the DMA Channel configuration */
tmp |= hdma->Init.Direction |
800445c: 687b ldr r3, [r7, #4]
800445e: 689a ldr r2, [r3, #8]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8004460: 687b ldr r3, [r7, #4]
8004462: 68db ldr r3, [r3, #12]
tmp |= hdma->Init.Direction |
8004464: 431a orrs r2, r3
hdma->Init.PeriphInc | hdma->Init.MemInc |
8004466: 687b ldr r3, [r7, #4]
8004468: 691b ldr r3, [r3, #16]
800446a: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
800446c: 687b ldr r3, [r7, #4]
800446e: 695b ldr r3, [r3, #20]
hdma->Init.PeriphInc | hdma->Init.MemInc |
8004470: 431a orrs r2, r3
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
8004472: 687b ldr r3, [r7, #4]
8004474: 699b ldr r3, [r3, #24]
8004476: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
8004478: 687b ldr r3, [r7, #4]
800447a: 69db ldr r3, [r3, #28]
hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
800447c: 431a orrs r2, r3
hdma->Init.Mode | hdma->Init.Priority;
800447e: 687b ldr r3, [r7, #4]
8004480: 6a1b ldr r3, [r3, #32]
8004482: 4313 orrs r3, r2
tmp |= hdma->Init.Direction |
8004484: 68fa ldr r2, [r7, #12]
8004486: 4313 orrs r3, r2
8004488: 60fb str r3, [r7, #12]
/* Write to DMA Channel CR register */
hdma->Instance->CCR = tmp;
800448a: 687b ldr r3, [r7, #4]
800448c: 681b ldr r3, [r3, #0]
800448e: 68fa ldr r2, [r7, #12]
8004490: 601a str r2, [r3, #0]
/* Initialize parameters for DMAMUX channel :
DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
*/
DMA_CalcDMAMUXChannelBaseAndMask(hdma);
8004492: 6878 ldr r0, [r7, #4]
8004494: f000 f908 bl 80046a8 <DMA_CalcDMAMUXChannelBaseAndMask>
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
8004498: 687b ldr r3, [r7, #4]
800449a: 689b ldr r3, [r3, #8]
800449c: f5b3 4f80 cmp.w r3, #16384 @ 0x4000
80044a0: d102 bne.n 80044a8 <HAL_DMA_Init+0xc4>
{
/* if memory to memory force the request to 0*/
hdma->Init.Request = DMA_REQUEST_MEM2MEM;
80044a2: 687b ldr r3, [r7, #4]
80044a4: 2200 movs r2, #0
80044a6: 605a str r2, [r3, #4]
}
/* Set peripheral request to DMAMUX channel */
hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
80044a8: 687b ldr r3, [r7, #4]
80044aa: 685a ldr r2, [r3, #4]
80044ac: 687b ldr r3, [r7, #4]
80044ae: 6c9b ldr r3, [r3, #72] @ 0x48
80044b0: b2d2 uxtb r2, r2
80044b2: 601a str r2, [r3, #0]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
80044b4: 687b ldr r3, [r7, #4]
80044b6: 6cdb ldr r3, [r3, #76] @ 0x4c
80044b8: 687a ldr r2, [r7, #4]
80044ba: 6d12 ldr r2, [r2, #80] @ 0x50
80044bc: 605a str r2, [r3, #4]
if (((hdma->Init.Request > 0U) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
80044be: 687b ldr r3, [r7, #4]
80044c0: 685b ldr r3, [r3, #4]
80044c2: 2b00 cmp r3, #0
80044c4: d010 beq.n 80044e8 <HAL_DMA_Init+0x104>
80044c6: 687b ldr r3, [r7, #4]
80044c8: 685b ldr r3, [r3, #4]
80044ca: 2b04 cmp r3, #4
80044cc: d80c bhi.n 80044e8 <HAL_DMA_Init+0x104>
{
/* Initialize parameters for DMAMUX request generator :
DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
*/
DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
80044ce: 6878 ldr r0, [r7, #4]
80044d0: f000 f928 bl 8004724 <DMA_CalcDMAMUXRequestGenBaseAndMask>
/* Reset the DMAMUX request generator register*/
hdma->DMAmuxRequestGen->RGCR = 0U;
80044d4: 687b ldr r3, [r7, #4]
80044d6: 6d5b ldr r3, [r3, #84] @ 0x54
80044d8: 2200 movs r2, #0
80044da: 601a str r2, [r3, #0]
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
80044dc: 687b ldr r3, [r7, #4]
80044de: 6d9b ldr r3, [r3, #88] @ 0x58
80044e0: 687a ldr r2, [r7, #4]
80044e2: 6dd2 ldr r2, [r2, #92] @ 0x5c
80044e4: 605a str r2, [r3, #4]
80044e6: e008 b.n 80044fa <HAL_DMA_Init+0x116>
}
else
{
hdma->DMAmuxRequestGen = 0U;
80044e8: 687b ldr r3, [r7, #4]
80044ea: 2200 movs r2, #0
80044ec: 655a str r2, [r3, #84] @ 0x54
hdma->DMAmuxRequestGenStatus = 0U;
80044ee: 687b ldr r3, [r7, #4]
80044f0: 2200 movs r2, #0
80044f2: 659a str r2, [r3, #88] @ 0x58
hdma->DMAmuxRequestGenStatusMask = 0U;
80044f4: 687b ldr r3, [r7, #4]
80044f6: 2200 movs r2, #0
80044f8: 65da str r2, [r3, #92] @ 0x5c
}
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
80044fa: 687b ldr r3, [r7, #4]
80044fc: 2200 movs r2, #0
80044fe: 63da str r2, [r3, #60] @ 0x3c
/* Initialize the DMA state*/
hdma->State = HAL_DMA_STATE_READY;
8004500: 687b ldr r3, [r7, #4]
8004502: 2201 movs r2, #1
8004504: f883 2025 strb.w r2, [r3, #37] @ 0x25
/* Allocate lock resource and initialize it */
hdma->Lock = HAL_UNLOCKED;
8004508: 687b ldr r3, [r7, #4]
800450a: 2200 movs r2, #0
800450c: f883 2024 strb.w r2, [r3, #36] @ 0x24
return HAL_OK;
8004510: 2300 movs r3, #0
}
8004512: 4618 mov r0, r3
8004514: 3710 adds r7, #16
8004516: 46bd mov sp, r7
8004518: bd80 pop {r7, pc}
800451a: bf00 nop
800451c: 40020407 .word 0x40020407
8004520: bffdfff8 .word 0xbffdfff8
8004524: cccccccd .word 0xcccccccd
8004528: 40020000 .word 0x40020000
800452c: bffdfbf8 .word 0xbffdfbf8
8004530: 40020400 .word 0x40020400
08004534 <HAL_DMA_Start_IT>:
* @param DataLength The length of data to be transferred from source to destination (up to 256Kbytes-1)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
uint32_t DataLength)
{
8004534: b580 push {r7, lr}
8004536: b086 sub sp, #24
8004538: af00 add r7, sp, #0
800453a: 60f8 str r0, [r7, #12]
800453c: 60b9 str r1, [r7, #8]
800453e: 607a str r2, [r7, #4]
8004540: 603b str r3, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8004542: 2300 movs r3, #0
8004544: 75fb strb r3, [r7, #23]
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Process locked */
__HAL_LOCK(hdma);
8004546: 68fb ldr r3, [r7, #12]
8004548: f893 3024 ldrb.w r3, [r3, #36] @ 0x24
800454c: 2b01 cmp r3, #1
800454e: d101 bne.n 8004554 <HAL_DMA_Start_IT+0x20>
8004550: 2302 movs r3, #2
8004552: e066 b.n 8004622 <HAL_DMA_Start_IT+0xee>
8004554: 68fb ldr r3, [r7, #12]
8004556: 2201 movs r2, #1
8004558: f883 2024 strb.w r2, [r3, #36] @ 0x24
if (HAL_DMA_STATE_READY == hdma->State)
800455c: 68fb ldr r3, [r7, #12]
800455e: f893 3025 ldrb.w r3, [r3, #37] @ 0x25
8004562: b2db uxtb r3, r3
8004564: 2b01 cmp r3, #1
8004566: d155 bne.n 8004614 <HAL_DMA_Start_IT+0xe0>
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
8004568: 68fb ldr r3, [r7, #12]
800456a: 2202 movs r2, #2
800456c: f883 2025 strb.w r2, [r3, #37] @ 0x25
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
8004570: 68fb ldr r3, [r7, #12]
8004572: 2200 movs r2, #0
8004574: 63da str r2, [r3, #60] @ 0x3c
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
8004576: 68fb ldr r3, [r7, #12]
8004578: 681b ldr r3, [r3, #0]
800457a: 681a ldr r2, [r3, #0]
800457c: 68fb ldr r3, [r7, #12]
800457e: 681b ldr r3, [r3, #0]
8004580: f022 0201 bic.w r2, r2, #1
8004584: 601a str r2, [r3, #0]
/* Configure the source, destination address and the data length & clear flags*/
DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
8004586: 683b ldr r3, [r7, #0]
8004588: 687a ldr r2, [r7, #4]
800458a: 68b9 ldr r1, [r7, #8]
800458c: 68f8 ldr r0, [r7, #12]
800458e: f000 f84c bl 800462a <DMA_SetConfig>
/* Enable the transfer complete interrupt */
/* Enable the transfer Error interrupt */
if (NULL != hdma->XferHalfCpltCallback)
8004592: 68fb ldr r3, [r7, #12]
8004594: 6b1b ldr r3, [r3, #48] @ 0x30
8004596: 2b00 cmp r3, #0
8004598: d008 beq.n 80045ac <HAL_DMA_Start_IT+0x78>
{
/* Enable the Half transfer complete interrupt as well */
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
800459a: 68fb ldr r3, [r7, #12]
800459c: 681b ldr r3, [r3, #0]
800459e: 681a ldr r2, [r3, #0]
80045a0: 68fb ldr r3, [r7, #12]
80045a2: 681b ldr r3, [r3, #0]
80045a4: f042 020e orr.w r2, r2, #14
80045a8: 601a str r2, [r3, #0]
80045aa: e00f b.n 80045cc <HAL_DMA_Start_IT+0x98>
}
else
{
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
80045ac: 68fb ldr r3, [r7, #12]
80045ae: 681b ldr r3, [r3, #0]
80045b0: 681a ldr r2, [r3, #0]
80045b2: 68fb ldr r3, [r7, #12]
80045b4: 681b ldr r3, [r3, #0]
80045b6: f022 0204 bic.w r2, r2, #4
80045ba: 601a str r2, [r3, #0]
__HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
80045bc: 68fb ldr r3, [r7, #12]
80045be: 681b ldr r3, [r3, #0]
80045c0: 681a ldr r2, [r3, #0]
80045c2: 68fb ldr r3, [r7, #12]
80045c4: 681b ldr r3, [r3, #0]
80045c6: f042 020a orr.w r2, r2, #10
80045ca: 601a str r2, [r3, #0]
}
/* Check if DMAMUX Synchronization is enabled*/
if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
80045cc: 68fb ldr r3, [r7, #12]
80045ce: 6c9b ldr r3, [r3, #72] @ 0x48
80045d0: 681b ldr r3, [r3, #0]
80045d2: f403 3380 and.w r3, r3, #65536 @ 0x10000
80045d6: 2b00 cmp r3, #0
80045d8: d007 beq.n 80045ea <HAL_DMA_Start_IT+0xb6>
{
/* Enable DMAMUX sync overrun IT*/
hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
80045da: 68fb ldr r3, [r7, #12]
80045dc: 6c9b ldr r3, [r3, #72] @ 0x48
80045de: 681a ldr r2, [r3, #0]
80045e0: 68fb ldr r3, [r7, #12]
80045e2: 6c9b ldr r3, [r3, #72] @ 0x48
80045e4: f442 7280 orr.w r2, r2, #256 @ 0x100
80045e8: 601a str r2, [r3, #0]
}
if (hdma->DMAmuxRequestGen != 0U)
80045ea: 68fb ldr r3, [r7, #12]
80045ec: 6d5b ldr r3, [r3, #84] @ 0x54
80045ee: 2b00 cmp r3, #0
80045f0: d007 beq.n 8004602 <HAL_DMA_Start_IT+0xce>
{
/* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
/* enable the request gen overrun IT*/
hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
80045f2: 68fb ldr r3, [r7, #12]
80045f4: 6d5b ldr r3, [r3, #84] @ 0x54
80045f6: 681a ldr r2, [r3, #0]
80045f8: 68fb ldr r3, [r7, #12]
80045fa: 6d5b ldr r3, [r3, #84] @ 0x54
80045fc: f442 7280 orr.w r2, r2, #256 @ 0x100
8004600: 601a str r2, [r3, #0]
}
/* Enable the Peripheral */
__HAL_DMA_ENABLE(hdma);
8004602: 68fb ldr r3, [r7, #12]
8004604: 681b ldr r3, [r3, #0]
8004606: 681a ldr r2, [r3, #0]
8004608: 68fb ldr r3, [r7, #12]
800460a: 681b ldr r3, [r3, #0]
800460c: f042 0201 orr.w r2, r2, #1
8004610: 601a str r2, [r3, #0]
8004612: e005 b.n 8004620 <HAL_DMA_Start_IT+0xec>
}
else
{
/* Process Unlocked */
__HAL_UNLOCK(hdma);
8004614: 68fb ldr r3, [r7, #12]
8004616: 2200 movs r2, #0
8004618: f883 2024 strb.w r2, [r3, #36] @ 0x24
/* Remain BUSY */
status = HAL_BUSY;
800461c: 2302 movs r3, #2
800461e: 75fb strb r3, [r7, #23]
}
return status;
8004620: 7dfb ldrb r3, [r7, #23]
}
8004622: 4618 mov r0, r3
8004624: 3718 adds r7, #24
8004626: 46bd mov sp, r7
8004628: bd80 pop {r7, pc}
0800462a <DMA_SetConfig>:
* @param DstAddress The destination memory Buffer address
* @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
800462a: b480 push {r7}
800462c: b085 sub sp, #20
800462e: af00 add r7, sp, #0
8004630: 60f8 str r0, [r7, #12]
8004632: 60b9 str r1, [r7, #8]
8004634: 607a str r2, [r7, #4]
8004636: 603b str r3, [r7, #0]
/* Clear the DMAMUX synchro overrun flag */
hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
8004638: 68fb ldr r3, [r7, #12]
800463a: 6cdb ldr r3, [r3, #76] @ 0x4c
800463c: 68fa ldr r2, [r7, #12]
800463e: 6d12 ldr r2, [r2, #80] @ 0x50
8004640: 605a str r2, [r3, #4]
if (hdma->DMAmuxRequestGen != 0U)
8004642: 68fb ldr r3, [r7, #12]
8004644: 6d5b ldr r3, [r3, #84] @ 0x54
8004646: 2b00 cmp r3, #0
8004648: d004 beq.n 8004654 <DMA_SetConfig+0x2a>
{
/* Clear the DMAMUX request generator overrun flag */
hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
800464a: 68fb ldr r3, [r7, #12]
800464c: 6d9b ldr r3, [r3, #88] @ 0x58
800464e: 68fa ldr r2, [r7, #12]
8004650: 6dd2 ldr r2, [r2, #92] @ 0x5c
8004652: 605a str r2, [r3, #4]
}
/* Clear all flags */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1FU));
8004654: 68fb ldr r3, [r7, #12]
8004656: 6c5b ldr r3, [r3, #68] @ 0x44
8004658: f003 021f and.w r2, r3, #31
800465c: 68fb ldr r3, [r7, #12]
800465e: 6c1b ldr r3, [r3, #64] @ 0x40
8004660: 2101 movs r1, #1
8004662: fa01 f202 lsl.w r2, r1, r2
8004666: 605a str r2, [r3, #4]
/* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength;
8004668: 68fb ldr r3, [r7, #12]
800466a: 681b ldr r3, [r3, #0]
800466c: 683a ldr r2, [r7, #0]
800466e: 605a str r2, [r3, #4]
/* Memory to Peripheral */
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
8004670: 68fb ldr r3, [r7, #12]
8004672: 689b ldr r3, [r3, #8]
8004674: 2b10 cmp r3, #16
8004676: d108 bne.n 800468a <DMA_SetConfig+0x60>
{
/* Configure DMA Channel destination address */
hdma->Instance->CPAR = DstAddress;
8004678: 68fb ldr r3, [r7, #12]
800467a: 681b ldr r3, [r3, #0]
800467c: 687a ldr r2, [r7, #4]
800467e: 609a str r2, [r3, #8]
/* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress;
8004680: 68fb ldr r3, [r7, #12]
8004682: 681b ldr r3, [r3, #0]
8004684: 68ba ldr r2, [r7, #8]
8004686: 60da str r2, [r3, #12]
hdma->Instance->CPAR = SrcAddress;
/* Configure DMA Channel destination address */
hdma->Instance->CMAR = DstAddress;
}
}
8004688: e007 b.n 800469a <DMA_SetConfig+0x70>
hdma->Instance->CPAR = SrcAddress;
800468a: 68fb ldr r3, [r7, #12]
800468c: 681b ldr r3, [r3, #0]
800468e: 68ba ldr r2, [r7, #8]
8004690: 609a str r2, [r3, #8]
hdma->Instance->CMAR = DstAddress;
8004692: 68fb ldr r3, [r7, #12]
8004694: 681b ldr r3, [r3, #0]
8004696: 687a ldr r2, [r7, #4]
8004698: 60da str r2, [r3, #12]
}
800469a: bf00 nop
800469c: 3714 adds r7, #20
800469e: 46bd mov sp, r7
80046a0: f85d 7b04 ldr.w r7, [sp], #4
80046a4: 4770 bx lr
...
080046a8 <DMA_CalcDMAMUXChannelBaseAndMask>:
* @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval None
*/
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
{
80046a8: b480 push {r7}
80046aa: b087 sub sp, #28
80046ac: af00 add r7, sp, #0
80046ae: 6078 str r0, [r7, #4]
uint32_t dmamux_base_addr;
uint32_t channel_number;
DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase;
/* check if instance is not outside the DMA channel range */
if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
80046b0: 687b ldr r3, [r7, #4]
80046b2: 681b ldr r3, [r3, #0]
80046b4: 461a mov r2, r3
80046b6: 4b16 ldr r3, [pc, #88] @ (8004710 <DMA_CalcDMAMUXChannelBaseAndMask+0x68>)
80046b8: 429a cmp r2, r3
80046ba: d802 bhi.n 80046c2 <DMA_CalcDMAMUXChannelBaseAndMask+0x1a>
{
/* DMA1 */
DMAMUX1_ChannelBase = DMAMUX1_Channel0;
80046bc: 4b15 ldr r3, [pc, #84] @ (8004714 <DMA_CalcDMAMUXChannelBaseAndMask+0x6c>)
80046be: 617b str r3, [r7, #20]
80046c0: e001 b.n 80046c6 <DMA_CalcDMAMUXChannelBaseAndMask+0x1e>
}
else
{
/* DMA2 */
#if defined (STM32G471xx) || defined (STM32G473xx) || defined (STM32G474xx) || defined (STM32G414xx) || defined (STM32G483xx) || defined (STM32G484xx) || defined (STM32G491xx) || defined (STM32G4A1xx) || defined (STM32G411xC)
DMAMUX1_ChannelBase = DMAMUX1_Channel8;
80046c2: 4b15 ldr r3, [pc, #84] @ (8004718 <DMA_CalcDMAMUXChannelBaseAndMask+0x70>)
80046c4: 617b str r3, [r7, #20]
DMAMUX1_ChannelBase = DMAMUX1_Channel6;
#else
DMAMUX1_ChannelBase = DMAMUX1_Channel7;
#endif /* STM32G4x1xx) */
}
dmamux_base_addr = (uint32_t)DMAMUX1_ChannelBase;
80046c6: 697b ldr r3, [r7, #20]
80046c8: 613b str r3, [r7, #16]
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
80046ca: 687b ldr r3, [r7, #4]
80046cc: 681b ldr r3, [r3, #0]
80046ce: b2db uxtb r3, r3
80046d0: 3b08 subs r3, #8
80046d2: 4a12 ldr r2, [pc, #72] @ (800471c <DMA_CalcDMAMUXChannelBaseAndMask+0x74>)
80046d4: fba2 2303 umull r2, r3, r2, r3
80046d8: 091b lsrs r3, r3, #4
80046da: 60fb str r3, [r7, #12]
hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)(dmamux_base_addr + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0)));
80046dc: 687b ldr r3, [r7, #4]
80046de: 6c5b ldr r3, [r3, #68] @ 0x44
80046e0: 089b lsrs r3, r3, #2
80046e2: 009a lsls r2, r3, #2
80046e4: 693b ldr r3, [r7, #16]
80046e6: 4413 add r3, r2
80046e8: 461a mov r2, r3
80046ea: 687b ldr r3, [r7, #4]
80046ec: 649a str r2, [r3, #72] @ 0x48
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
80046ee: 687b ldr r3, [r7, #4]
80046f0: 4a0b ldr r2, [pc, #44] @ (8004720 <DMA_CalcDMAMUXChannelBaseAndMask+0x78>)
80046f2: 64da str r2, [r3, #76] @ 0x4c
hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
80046f4: 68fb ldr r3, [r7, #12]
80046f6: f003 031f and.w r3, r3, #31
80046fa: 2201 movs r2, #1
80046fc: 409a lsls r2, r3
80046fe: 687b ldr r3, [r7, #4]
8004700: 651a str r2, [r3, #80] @ 0x50
}
8004702: bf00 nop
8004704: 371c adds r7, #28
8004706: 46bd mov sp, r7
8004708: f85d 7b04 ldr.w r7, [sp], #4
800470c: 4770 bx lr
800470e: bf00 nop
8004710: 40020407 .word 0x40020407
8004714: 40020800 .word 0x40020800
8004718: 40020820 .word 0x40020820
800471c: cccccccd .word 0xcccccccd
8004720: 40020880 .word 0x40020880
08004724 <DMA_CalcDMAMUXRequestGenBaseAndMask>:
* the configuration information for the specified DMA Channel.
* @retval None
*/
static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
{
8004724: b480 push {r7}
8004726: b085 sub sp, #20
8004728: af00 add r7, sp, #0
800472a: 6078 str r0, [r7, #4]
uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
800472c: 687b ldr r3, [r7, #4]
800472e: 685b ldr r3, [r3, #4]
8004730: b2db uxtb r3, r3
8004732: 60fb str r3, [r7, #12]
/* DMA Channels are connected to DMAMUX1 request generator blocks*/
hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U)));
8004734: 68fa ldr r2, [r7, #12]
8004736: 4b0b ldr r3, [pc, #44] @ (8004764 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x40>)
8004738: 4413 add r3, r2
800473a: 009b lsls r3, r3, #2
800473c: 461a mov r2, r3
800473e: 687b ldr r3, [r7, #4]
8004740: 655a str r2, [r3, #84] @ 0x54
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
8004742: 687b ldr r3, [r7, #4]
8004744: 4a08 ldr r2, [pc, #32] @ (8004768 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x44>)
8004746: 659a str r2, [r3, #88] @ 0x58
hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x1FU);
8004748: 68fb ldr r3, [r7, #12]
800474a: 3b01 subs r3, #1
800474c: f003 031f and.w r3, r3, #31
8004750: 2201 movs r2, #1
8004752: 409a lsls r2, r3
8004754: 687b ldr r3, [r7, #4]
8004756: 65da str r2, [r3, #92] @ 0x5c
}
8004758: bf00 nop
800475a: 3714 adds r7, #20
800475c: 46bd mov sp, r7
800475e: f85d 7b04 ldr.w r7, [sp], #4
8004762: 4770 bx lr
8004764: 1000823f .word 0x1000823f
8004768: 40020940 .word 0x40020940
0800476c <HAL_FMAC_Init>:
* @brief Initialize the FMAC peripheral and the associated handle.
* @param hfmac pointer to a FMAC_HandleTypeDef structure.
* @retval HAL_StatusTypeDef HAL status
*/
HAL_StatusTypeDef HAL_FMAC_Init(FMAC_HandleTypeDef *hfmac)
{
800476c: b580 push {r7, lr}
800476e: b084 sub sp, #16
8004770: af00 add r7, sp, #0
8004772: 6078 str r0, [r7, #4]
HAL_StatusTypeDef status;
/* Check the FMAC handle allocation */
if (hfmac == NULL)
8004774: 687b ldr r3, [r7, #4]
8004776: 2b00 cmp r3, #0
8004778: d101 bne.n 800477e <HAL_FMAC_Init+0x12>
{
return HAL_ERROR;
800477a: 2301 movs r3, #1
800477c: e033 b.n 80047e6 <HAL_FMAC_Init+0x7a>
}
/* Check the instance */
assert_param(IS_FMAC_ALL_INSTANCE(hfmac->Instance));
if (hfmac->State == HAL_FMAC_STATE_RESET)
800477e: 687b ldr r3, [r7, #4]
8004780: f893 3031 ldrb.w r3, [r3, #49] @ 0x31
8004784: b2db uxtb r3, r3
8004786: 2b00 cmp r3, #0
8004788: d106 bne.n 8004798 <HAL_FMAC_Init+0x2c>
{
/* Initialize lock resource */
hfmac->Lock = HAL_UNLOCKED;
800478a: 687b ldr r3, [r7, #4]
800478c: 2200 movs r2, #0
800478e: f883 2030 strb.w r2, [r3, #48] @ 0x30
/* Init the low level hardware */
hfmac->MspInitCallback(hfmac);
#else
/* Init the low level hardware */
HAL_FMAC_MspInit(hfmac);
8004792: 6878 ldr r0, [r7, #4]
8004794: f7fc ff6a bl 800166c <HAL_FMAC_MspInit>
#endif /* USE_HAL_FMAC_REGISTER_CALLBACKS */
}
/* Reset pInput and pOutput */
hfmac->FilterParam = 0U;
8004798: 687b ldr r3, [r7, #4]
800479a: 2200 movs r2, #0
800479c: 605a str r2, [r3, #4]
FMAC_ResetDataPointers(hfmac);
800479e: 6878 ldr r0, [r7, #4]
80047a0: f000 f854 bl 800484c <FMAC_ResetDataPointers>
/* Reset FMAC unit (internal pointers) */
if (FMAC_Reset(hfmac) == HAL_ERROR)
80047a4: 6878 ldr r0, [r7, #4]
80047a6: f000 f822 bl 80047ee <FMAC_Reset>
80047aa: 4603 mov r3, r0
80047ac: 2b01 cmp r3, #1
80047ae: d10c bne.n 80047ca <HAL_FMAC_Init+0x5e>
{
/* Update FMAC error code and FMAC peripheral state */
hfmac->ErrorCode |= HAL_FMAC_ERROR_RESET;
80047b0: 687b ldr r3, [r7, #4]
80047b2: 6b5b ldr r3, [r3, #52] @ 0x34
80047b4: f043 0210 orr.w r2, r3, #16
80047b8: 687b ldr r3, [r7, #4]
80047ba: 635a str r2, [r3, #52] @ 0x34
hfmac->State = HAL_FMAC_STATE_TIMEOUT;
80047bc: 687b ldr r3, [r7, #4]
80047be: 22a0 movs r2, #160 @ 0xa0
80047c0: f883 2031 strb.w r2, [r3, #49] @ 0x31
status = HAL_ERROR;
80047c4: 2301 movs r3, #1
80047c6: 73fb strb r3, [r7, #15]
80047c8: e008 b.n 80047dc <HAL_FMAC_Init+0x70>
}
else
{
/* Update FMAC error code and FMAC peripheral state */
hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
80047ca: 687b ldr r3, [r7, #4]
80047cc: 2200 movs r2, #0
80047ce: 635a str r2, [r3, #52] @ 0x34
hfmac->State = HAL_FMAC_STATE_READY;
80047d0: 687b ldr r3, [r7, #4]
80047d2: 2220 movs r2, #32
80047d4: f883 2031 strb.w r2, [r3, #49] @ 0x31
status = HAL_OK;
80047d8: 2300 movs r3, #0
80047da: 73fb strb r3, [r7, #15]
}
__HAL_UNLOCK(hfmac);
80047dc: 687b ldr r3, [r7, #4]
80047de: 2200 movs r2, #0
80047e0: f883 2030 strb.w r2, [r3, #48] @ 0x30
return status;
80047e4: 7bfb ldrb r3, [r7, #15]
}
80047e6: 4618 mov r0, r3
80047e8: 3710 adds r7, #16
80047ea: 46bd mov sp, r7
80047ec: bd80 pop {r7, pc}
080047ee <FMAC_Reset>:
* @brief Perform a reset of the FMAC unit.
* @param hfmac FMAC handle.
* @retval HAL_StatusTypeDef HAL status
*/
static HAL_StatusTypeDef FMAC_Reset(FMAC_HandleTypeDef *hfmac)
{
80047ee: b580 push {r7, lr}
80047f0: b084 sub sp, #16
80047f2: af00 add r7, sp, #0
80047f4: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
80047f6: f7fd f979 bl 8001aec <HAL_GetTick>
80047fa: 60f8 str r0, [r7, #12]
/* Perform the reset */
SET_BIT(hfmac->Instance->CR, FMAC_CR_RESET);
80047fc: 687b ldr r3, [r7, #4]
80047fe: 681b ldr r3, [r3, #0]
8004800: 691a ldr r2, [r3, #16]
8004802: 687b ldr r3, [r7, #4]
8004804: 681b ldr r3, [r3, #0]
8004806: f442 3280 orr.w r2, r2, #65536 @ 0x10000
800480a: 611a str r2, [r3, #16]
/* Wait until flag is reset */
while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0U)
800480c: e00f b.n 800482e <FMAC_Reset+0x40>
{
if ((HAL_GetTick() - tickstart) > HAL_FMAC_RESET_TIMEOUT_VALUE)
800480e: f7fd f96d bl 8001aec <HAL_GetTick>
8004812: 4602 mov r2, r0
8004814: 68fb ldr r3, [r7, #12]
8004816: 1ad3 subs r3, r2, r3
8004818: f5b3 7ffa cmp.w r3, #500 @ 0x1f4
800481c: d907 bls.n 800482e <FMAC_Reset+0x40>
{
hfmac->ErrorCode |= HAL_FMAC_ERROR_TIMEOUT;
800481e: 687b ldr r3, [r7, #4]
8004820: 6b5b ldr r3, [r3, #52] @ 0x34
8004822: f043 0280 orr.w r2, r3, #128 @ 0x80
8004826: 687b ldr r3, [r7, #4]
8004828: 635a str r2, [r3, #52] @ 0x34
return HAL_ERROR;
800482a: 2301 movs r3, #1
800482c: e00a b.n 8004844 <FMAC_Reset+0x56>
while (READ_BIT(hfmac->Instance->CR, FMAC_CR_RESET) != 0U)
800482e: 687b ldr r3, [r7, #4]
8004830: 681b ldr r3, [r3, #0]
8004832: 691b ldr r3, [r3, #16]
8004834: f403 3380 and.w r3, r3, #65536 @ 0x10000
8004838: 2b00 cmp r3, #0
800483a: d1e8 bne.n 800480e <FMAC_Reset+0x20>
}
}
hfmac->ErrorCode = HAL_FMAC_ERROR_NONE;
800483c: 687b ldr r3, [r7, #4]
800483e: 2200 movs r2, #0
8004840: 635a str r2, [r3, #52] @ 0x34
return HAL_OK;
8004842: 2300 movs r3, #0
}
8004844: 4618 mov r0, r3
8004846: 3710 adds r7, #16
8004848: 46bd mov sp, r7
800484a: bd80 pop {r7, pc}
0800484c <FMAC_ResetDataPointers>:
* @brief Reset the data pointers of the FMAC unit.
* @param hfmac FMAC handle.
* @retval None
*/
static void FMAC_ResetDataPointers(FMAC_HandleTypeDef *hfmac)
{
800484c: b580 push {r7, lr}
800484e: b082 sub sp, #8
8004850: af00 add r7, sp, #0
8004852: 6078 str r0, [r7, #4]
FMAC_ResetInputStateAndDataPointers(hfmac);
8004854: 6878 ldr r0, [r7, #4]
8004856: f000 f807 bl 8004868 <FMAC_ResetInputStateAndDataPointers>
FMAC_ResetOutputStateAndDataPointers(hfmac);
800485a: 6878 ldr r0, [r7, #4]
800485c: f000 f81b bl 8004896 <FMAC_ResetOutputStateAndDataPointers>
}
8004860: bf00 nop
8004862: 3708 adds r7, #8
8004864: 46bd mov sp, r7
8004866: bd80 pop {r7, pc}
08004868 <FMAC_ResetInputStateAndDataPointers>:
* @brief Reset the input data pointers of the FMAC unit.
* @param hfmac FMAC handle.
* @retval None
*/
static void FMAC_ResetInputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
{
8004868: b480 push {r7}
800486a: b083 sub sp, #12
800486c: af00 add r7, sp, #0
800486e: 6078 str r0, [r7, #4]
hfmac->pInput = NULL;
8004870: 687b ldr r3, [r7, #4]
8004872: 2200 movs r2, #0
8004874: 60da str r2, [r3, #12]
hfmac->pInputSize = NULL;
8004876: 687b ldr r3, [r7, #4]
8004878: 2200 movs r2, #0
800487a: 615a str r2, [r3, #20]
hfmac->InputCurrentSize = 0U;
800487c: 687b ldr r3, [r7, #4]
800487e: 2200 movs r2, #0
8004880: 821a strh r2, [r3, #16]
hfmac->WrState = HAL_FMAC_STATE_READY;
8004882: 687b ldr r3, [r7, #4]
8004884: 2220 movs r2, #32
8004886: f883 2033 strb.w r2, [r3, #51] @ 0x33
}
800488a: bf00 nop
800488c: 370c adds r7, #12
800488e: 46bd mov sp, r7
8004890: f85d 7b04 ldr.w r7, [sp], #4
8004894: 4770 bx lr
08004896 <FMAC_ResetOutputStateAndDataPointers>:
* @brief Reset the output data pointers of the FMAC unit.
* @param hfmac FMAC handle.
* @retval None
*/
static void FMAC_ResetOutputStateAndDataPointers(FMAC_HandleTypeDef *hfmac)
{
8004896: b480 push {r7}
8004898: b083 sub sp, #12
800489a: af00 add r7, sp, #0
800489c: 6078 str r0, [r7, #4]
hfmac->pOutput = NULL;
800489e: 687b ldr r3, [r7, #4]
80048a0: 2200 movs r2, #0
80048a2: 619a str r2, [r3, #24]
hfmac->pOutputSize = NULL;
80048a4: 687b ldr r3, [r7, #4]
80048a6: 2200 movs r2, #0
80048a8: 621a str r2, [r3, #32]
hfmac->OutputCurrentSize = 0U;
80048aa: 687b ldr r3, [r7, #4]
80048ac: 2200 movs r2, #0
80048ae: 839a strh r2, [r3, #28]
hfmac->RdState = HAL_FMAC_STATE_READY;
80048b0: 687b ldr r3, [r7, #4]
80048b2: 2220 movs r2, #32
80048b4: f883 2032 strb.w r2, [r3, #50] @ 0x32
}
80048b8: bf00 nop
80048ba: 370c adds r7, #12
80048bc: 46bd mov sp, r7
80048be: f85d 7b04 ldr.w r7, [sp], #4
80048c2: 4770 bx lr
080048c4 <HAL_GPIO_Init>:
* @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
* the configuration information for the specified GPIO peripheral.
* @retval None
*/
void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init)
{
80048c4: b480 push {r7}
80048c6: b087 sub sp, #28
80048c8: af00 add r7, sp, #0
80048ca: 6078 str r0, [r7, #4]
80048cc: 6039 str r1, [r7, #0]
uint32_t position = 0x00U;
80048ce: 2300 movs r3, #0
80048d0: 617b str r3, [r7, #20]
assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
/* Configure the port pins */
while (((GPIO_Init->Pin) >> position) != 0U)
80048d2: e15a b.n 8004b8a <HAL_GPIO_Init+0x2c6>
{
/* Get current io position */
iocurrent = (GPIO_Init->Pin) & (1UL << position);
80048d4: 683b ldr r3, [r7, #0]
80048d6: 681a ldr r2, [r3, #0]
80048d8: 2101 movs r1, #1
80048da: 697b ldr r3, [r7, #20]
80048dc: fa01 f303 lsl.w r3, r1, r3
80048e0: 4013 ands r3, r2
80048e2: 60fb str r3, [r7, #12]
if (iocurrent != 0x00u)
80048e4: 68fb ldr r3, [r7, #12]
80048e6: 2b00 cmp r3, #0
80048e8: f000 814c beq.w 8004b84 <HAL_GPIO_Init+0x2c0>
{
/*--------------------- GPIO Mode Configuration ------------------------*/
/* In case of Output or Alternate function mode selection */
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
80048ec: 683b ldr r3, [r7, #0]
80048ee: 685b ldr r3, [r3, #4]
80048f0: f003 0303 and.w r3, r3, #3
80048f4: 2b01 cmp r3, #1
80048f6: d005 beq.n 8004904 <HAL_GPIO_Init+0x40>
((GPIO_Init->Mode & GPIO_MODE) == MODE_AF))
80048f8: 683b ldr r3, [r7, #0]
80048fa: 685b ldr r3, [r3, #4]
80048fc: f003 0303 and.w r3, r3, #3
if(((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) ||
8004900: 2b02 cmp r3, #2
8004902: d130 bne.n 8004966 <HAL_GPIO_Init+0xa2>
{
/* Check the Speed parameter */
assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
/* Configure the IO Speed */
temp = GPIOx->OSPEEDR;
8004904: 687b ldr r3, [r7, #4]
8004906: 689b ldr r3, [r3, #8]
8004908: 613b str r3, [r7, #16]
temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U));
800490a: 697b ldr r3, [r7, #20]
800490c: 005b lsls r3, r3, #1
800490e: 2203 movs r2, #3
8004910: fa02 f303 lsl.w r3, r2, r3
8004914: 43db mvns r3, r3
8004916: 693a ldr r2, [r7, #16]
8004918: 4013 ands r3, r2
800491a: 613b str r3, [r7, #16]
temp |= (GPIO_Init->Speed << (position * 2U));
800491c: 683b ldr r3, [r7, #0]
800491e: 68da ldr r2, [r3, #12]
8004920: 697b ldr r3, [r7, #20]
8004922: 005b lsls r3, r3, #1
8004924: fa02 f303 lsl.w r3, r2, r3
8004928: 693a ldr r2, [r7, #16]
800492a: 4313 orrs r3, r2
800492c: 613b str r3, [r7, #16]
GPIOx->OSPEEDR = temp;
800492e: 687b ldr r3, [r7, #4]
8004930: 693a ldr r2, [r7, #16]
8004932: 609a str r2, [r3, #8]
/* Configure the IO Output Type */
temp = GPIOx->OTYPER;
8004934: 687b ldr r3, [r7, #4]
8004936: 685b ldr r3, [r3, #4]
8004938: 613b str r3, [r7, #16]
temp &= ~(GPIO_OTYPER_OT0 << position) ;
800493a: 2201 movs r2, #1
800493c: 697b ldr r3, [r7, #20]
800493e: fa02 f303 lsl.w r3, r2, r3
8004942: 43db mvns r3, r3
8004944: 693a ldr r2, [r7, #16]
8004946: 4013 ands r3, r2
8004948: 613b str r3, [r7, #16]
temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position);
800494a: 683b ldr r3, [r7, #0]
800494c: 685b ldr r3, [r3, #4]
800494e: 091b lsrs r3, r3, #4
8004950: f003 0201 and.w r2, r3, #1
8004954: 697b ldr r3, [r7, #20]
8004956: fa02 f303 lsl.w r3, r2, r3
800495a: 693a ldr r2, [r7, #16]
800495c: 4313 orrs r3, r2
800495e: 613b str r3, [r7, #16]
GPIOx->OTYPER = temp;
8004960: 687b ldr r3, [r7, #4]
8004962: 693a ldr r2, [r7, #16]
8004964: 605a str r2, [r3, #4]
}
if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG)
8004966: 683b ldr r3, [r7, #0]
8004968: 685b ldr r3, [r3, #4]
800496a: f003 0303 and.w r3, r3, #3
800496e: 2b03 cmp r3, #3
8004970: d017 beq.n 80049a2 <HAL_GPIO_Init+0xde>
{
/* Check the Pull parameter */
assert_param(IS_GPIO_PULL(GPIO_Init->Pull));
/* Activate the Pull-up or Pull down resistor for the current IO */
temp = GPIOx->PUPDR;
8004972: 687b ldr r3, [r7, #4]
8004974: 68db ldr r3, [r3, #12]
8004976: 613b str r3, [r7, #16]
temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U));
8004978: 697b ldr r3, [r7, #20]
800497a: 005b lsls r3, r3, #1
800497c: 2203 movs r2, #3
800497e: fa02 f303 lsl.w r3, r2, r3
8004982: 43db mvns r3, r3
8004984: 693a ldr r2, [r7, #16]
8004986: 4013 ands r3, r2
8004988: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Pull) << (position * 2U));
800498a: 683b ldr r3, [r7, #0]
800498c: 689a ldr r2, [r3, #8]
800498e: 697b ldr r3, [r7, #20]
8004990: 005b lsls r3, r3, #1
8004992: fa02 f303 lsl.w r3, r2, r3
8004996: 693a ldr r2, [r7, #16]
8004998: 4313 orrs r3, r2
800499a: 613b str r3, [r7, #16]
GPIOx->PUPDR = temp;
800499c: 687b ldr r3, [r7, #4]
800499e: 693a ldr r2, [r7, #16]
80049a0: 60da str r2, [r3, #12]
}
/* In case of Alternate function mode selection */
if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)
80049a2: 683b ldr r3, [r7, #0]
80049a4: 685b ldr r3, [r3, #4]
80049a6: f003 0303 and.w r3, r3, #3
80049aa: 2b02 cmp r3, #2
80049ac: d123 bne.n 80049f6 <HAL_GPIO_Init+0x132>
/* Check the Alternate function parameters */
assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
/* Configure Alternate function mapped with the current IO */
temp = GPIOx->AFR[position >> 3U];
80049ae: 697b ldr r3, [r7, #20]
80049b0: 08da lsrs r2, r3, #3
80049b2: 687b ldr r3, [r7, #4]
80049b4: 3208 adds r2, #8
80049b6: f853 3022 ldr.w r3, [r3, r2, lsl #2]
80049ba: 613b str r3, [r7, #16]
temp &= ~(0xFU << ((position & 0x07U) * 4U));
80049bc: 697b ldr r3, [r7, #20]
80049be: f003 0307 and.w r3, r3, #7
80049c2: 009b lsls r3, r3, #2
80049c4: 220f movs r2, #15
80049c6: fa02 f303 lsl.w r3, r2, r3
80049ca: 43db mvns r3, r3
80049cc: 693a ldr r2, [r7, #16]
80049ce: 4013 ands r3, r2
80049d0: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U));
80049d2: 683b ldr r3, [r7, #0]
80049d4: 691a ldr r2, [r3, #16]
80049d6: 697b ldr r3, [r7, #20]
80049d8: f003 0307 and.w r3, r3, #7
80049dc: 009b lsls r3, r3, #2
80049de: fa02 f303 lsl.w r3, r2, r3
80049e2: 693a ldr r2, [r7, #16]
80049e4: 4313 orrs r3, r2
80049e6: 613b str r3, [r7, #16]
GPIOx->AFR[position >> 3U] = temp;
80049e8: 697b ldr r3, [r7, #20]
80049ea: 08da lsrs r2, r3, #3
80049ec: 687b ldr r3, [r7, #4]
80049ee: 3208 adds r2, #8
80049f0: 6939 ldr r1, [r7, #16]
80049f2: f843 1022 str.w r1, [r3, r2, lsl #2]
}
/* Configure IO Direction mode (Input, Output, Alternate or Analog) */
temp = GPIOx->MODER;
80049f6: 687b ldr r3, [r7, #4]
80049f8: 681b ldr r3, [r3, #0]
80049fa: 613b str r3, [r7, #16]
temp &= ~(GPIO_MODER_MODE0 << (position * 2U));
80049fc: 697b ldr r3, [r7, #20]
80049fe: 005b lsls r3, r3, #1
8004a00: 2203 movs r2, #3
8004a02: fa02 f303 lsl.w r3, r2, r3
8004a06: 43db mvns r3, r3
8004a08: 693a ldr r2, [r7, #16]
8004a0a: 4013 ands r3, r2
8004a0c: 613b str r3, [r7, #16]
temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U));
8004a0e: 683b ldr r3, [r7, #0]
8004a10: 685b ldr r3, [r3, #4]
8004a12: f003 0203 and.w r2, r3, #3
8004a16: 697b ldr r3, [r7, #20]
8004a18: 005b lsls r3, r3, #1
8004a1a: fa02 f303 lsl.w r3, r2, r3
8004a1e: 693a ldr r2, [r7, #16]
8004a20: 4313 orrs r3, r2
8004a22: 613b str r3, [r7, #16]
GPIOx->MODER = temp;
8004a24: 687b ldr r3, [r7, #4]
8004a26: 693a ldr r2, [r7, #16]
8004a28: 601a str r2, [r3, #0]
/*--------------------- EXTI Mode Configuration ------------------------*/
/* Configure the External Interrupt or event for the current IO */
if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u)
8004a2a: 683b ldr r3, [r7, #0]
8004a2c: 685b ldr r3, [r3, #4]
8004a2e: f403 3340 and.w r3, r3, #196608 @ 0x30000
8004a32: 2b00 cmp r3, #0
8004a34: f000 80a6 beq.w 8004b84 <HAL_GPIO_Init+0x2c0>
{
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
8004a38: 4b5b ldr r3, [pc, #364] @ (8004ba8 <HAL_GPIO_Init+0x2e4>)
8004a3a: 6e1b ldr r3, [r3, #96] @ 0x60
8004a3c: 4a5a ldr r2, [pc, #360] @ (8004ba8 <HAL_GPIO_Init+0x2e4>)
8004a3e: f043 0301 orr.w r3, r3, #1
8004a42: 6613 str r3, [r2, #96] @ 0x60
8004a44: 4b58 ldr r3, [pc, #352] @ (8004ba8 <HAL_GPIO_Init+0x2e4>)
8004a46: 6e1b ldr r3, [r3, #96] @ 0x60
8004a48: f003 0301 and.w r3, r3, #1
8004a4c: 60bb str r3, [r7, #8]
8004a4e: 68bb ldr r3, [r7, #8]
temp = SYSCFG->EXTICR[position >> 2U];
8004a50: 4a56 ldr r2, [pc, #344] @ (8004bac <HAL_GPIO_Init+0x2e8>)
8004a52: 697b ldr r3, [r7, #20]
8004a54: 089b lsrs r3, r3, #2
8004a56: 3302 adds r3, #2
8004a58: f852 3023 ldr.w r3, [r2, r3, lsl #2]
8004a5c: 613b str r3, [r7, #16]
temp &= ~(0x0FUL << (4U * (position & 0x03U)));
8004a5e: 697b ldr r3, [r7, #20]
8004a60: f003 0303 and.w r3, r3, #3
8004a64: 009b lsls r3, r3, #2
8004a66: 220f movs r2, #15
8004a68: fa02 f303 lsl.w r3, r2, r3
8004a6c: 43db mvns r3, r3
8004a6e: 693a ldr r2, [r7, #16]
8004a70: 4013 ands r3, r2
8004a72: 613b str r3, [r7, #16]
temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)));
8004a74: 687b ldr r3, [r7, #4]
8004a76: f1b3 4f90 cmp.w r3, #1207959552 @ 0x48000000
8004a7a: d01f beq.n 8004abc <HAL_GPIO_Init+0x1f8>
8004a7c: 687b ldr r3, [r7, #4]
8004a7e: 4a4c ldr r2, [pc, #304] @ (8004bb0 <HAL_GPIO_Init+0x2ec>)
8004a80: 4293 cmp r3, r2
8004a82: d019 beq.n 8004ab8 <HAL_GPIO_Init+0x1f4>
8004a84: 687b ldr r3, [r7, #4]
8004a86: 4a4b ldr r2, [pc, #300] @ (8004bb4 <HAL_GPIO_Init+0x2f0>)
8004a88: 4293 cmp r3, r2
8004a8a: d013 beq.n 8004ab4 <HAL_GPIO_Init+0x1f0>
8004a8c: 687b ldr r3, [r7, #4]
8004a8e: 4a4a ldr r2, [pc, #296] @ (8004bb8 <HAL_GPIO_Init+0x2f4>)
8004a90: 4293 cmp r3, r2
8004a92: d00d beq.n 8004ab0 <HAL_GPIO_Init+0x1ec>
8004a94: 687b ldr r3, [r7, #4]
8004a96: 4a49 ldr r2, [pc, #292] @ (8004bbc <HAL_GPIO_Init+0x2f8>)
8004a98: 4293 cmp r3, r2
8004a9a: d007 beq.n 8004aac <HAL_GPIO_Init+0x1e8>
8004a9c: 687b ldr r3, [r7, #4]
8004a9e: 4a48 ldr r2, [pc, #288] @ (8004bc0 <HAL_GPIO_Init+0x2fc>)
8004aa0: 4293 cmp r3, r2
8004aa2: d101 bne.n 8004aa8 <HAL_GPIO_Init+0x1e4>
8004aa4: 2305 movs r3, #5
8004aa6: e00a b.n 8004abe <HAL_GPIO_Init+0x1fa>
8004aa8: 2306 movs r3, #6
8004aaa: e008 b.n 8004abe <HAL_GPIO_Init+0x1fa>
8004aac: 2304 movs r3, #4
8004aae: e006 b.n 8004abe <HAL_GPIO_Init+0x1fa>
8004ab0: 2303 movs r3, #3
8004ab2: e004 b.n 8004abe <HAL_GPIO_Init+0x1fa>
8004ab4: 2302 movs r3, #2
8004ab6: e002 b.n 8004abe <HAL_GPIO_Init+0x1fa>
8004ab8: 2301 movs r3, #1
8004aba: e000 b.n 8004abe <HAL_GPIO_Init+0x1fa>
8004abc: 2300 movs r3, #0
8004abe: 697a ldr r2, [r7, #20]
8004ac0: f002 0203 and.w r2, r2, #3
8004ac4: 0092 lsls r2, r2, #2
8004ac6: 4093 lsls r3, r2
8004ac8: 693a ldr r2, [r7, #16]
8004aca: 4313 orrs r3, r2
8004acc: 613b str r3, [r7, #16]
SYSCFG->EXTICR[position >> 2U] = temp;
8004ace: 4937 ldr r1, [pc, #220] @ (8004bac <HAL_GPIO_Init+0x2e8>)
8004ad0: 697b ldr r3, [r7, #20]
8004ad2: 089b lsrs r3, r3, #2
8004ad4: 3302 adds r3, #2
8004ad6: 693a ldr r2, [r7, #16]
8004ad8: f841 2023 str.w r2, [r1, r3, lsl #2]
/* Clear Rising Falling edge configuration */
temp = EXTI->RTSR1;
8004adc: 4b39 ldr r3, [pc, #228] @ (8004bc4 <HAL_GPIO_Init+0x300>)
8004ade: 689b ldr r3, [r3, #8]
8004ae0: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8004ae2: 68fb ldr r3, [r7, #12]
8004ae4: 43db mvns r3, r3
8004ae6: 693a ldr r2, [r7, #16]
8004ae8: 4013 ands r3, r2
8004aea: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00U)
8004aec: 683b ldr r3, [r7, #0]
8004aee: 685b ldr r3, [r3, #4]
8004af0: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8004af4: 2b00 cmp r3, #0
8004af6: d003 beq.n 8004b00 <HAL_GPIO_Init+0x23c>
{
temp |= iocurrent;
8004af8: 693a ldr r2, [r7, #16]
8004afa: 68fb ldr r3, [r7, #12]
8004afc: 4313 orrs r3, r2
8004afe: 613b str r3, [r7, #16]
}
EXTI->RTSR1 = temp;
8004b00: 4a30 ldr r2, [pc, #192] @ (8004bc4 <HAL_GPIO_Init+0x300>)
8004b02: 693b ldr r3, [r7, #16]
8004b04: 6093 str r3, [r2, #8]
temp = EXTI->FTSR1;
8004b06: 4b2f ldr r3, [pc, #188] @ (8004bc4 <HAL_GPIO_Init+0x300>)
8004b08: 68db ldr r3, [r3, #12]
8004b0a: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8004b0c: 68fb ldr r3, [r7, #12]
8004b0e: 43db mvns r3, r3
8004b10: 693a ldr r2, [r7, #16]
8004b12: 4013 ands r3, r2
8004b14: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00U)
8004b16: 683b ldr r3, [r7, #0]
8004b18: 685b ldr r3, [r3, #4]
8004b1a: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8004b1e: 2b00 cmp r3, #0
8004b20: d003 beq.n 8004b2a <HAL_GPIO_Init+0x266>
{
temp |= iocurrent;
8004b22: 693a ldr r2, [r7, #16]
8004b24: 68fb ldr r3, [r7, #12]
8004b26: 4313 orrs r3, r2
8004b28: 613b str r3, [r7, #16]
}
EXTI->FTSR1 = temp;
8004b2a: 4a26 ldr r2, [pc, #152] @ (8004bc4 <HAL_GPIO_Init+0x300>)
8004b2c: 693b ldr r3, [r7, #16]
8004b2e: 60d3 str r3, [r2, #12]
temp = EXTI->EMR1;
8004b30: 4b24 ldr r3, [pc, #144] @ (8004bc4 <HAL_GPIO_Init+0x300>)
8004b32: 685b ldr r3, [r3, #4]
8004b34: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8004b36: 68fb ldr r3, [r7, #12]
8004b38: 43db mvns r3, r3
8004b3a: 693a ldr r2, [r7, #16]
8004b3c: 4013 ands r3, r2
8004b3e: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_EVT) != 0x00U)
8004b40: 683b ldr r3, [r7, #0]
8004b42: 685b ldr r3, [r3, #4]
8004b44: f403 3300 and.w r3, r3, #131072 @ 0x20000
8004b48: 2b00 cmp r3, #0
8004b4a: d003 beq.n 8004b54 <HAL_GPIO_Init+0x290>
{
temp |= iocurrent;
8004b4c: 693a ldr r2, [r7, #16]
8004b4e: 68fb ldr r3, [r7, #12]
8004b50: 4313 orrs r3, r2
8004b52: 613b str r3, [r7, #16]
}
EXTI->EMR1 = temp;
8004b54: 4a1b ldr r2, [pc, #108] @ (8004bc4 <HAL_GPIO_Init+0x300>)
8004b56: 693b ldr r3, [r7, #16]
8004b58: 6053 str r3, [r2, #4]
/* Clear EXTI line configuration */
temp = EXTI->IMR1;
8004b5a: 4b1a ldr r3, [pc, #104] @ (8004bc4 <HAL_GPIO_Init+0x300>)
8004b5c: 681b ldr r3, [r3, #0]
8004b5e: 613b str r3, [r7, #16]
temp &= ~(iocurrent);
8004b60: 68fb ldr r3, [r7, #12]
8004b62: 43db mvns r3, r3
8004b64: 693a ldr r2, [r7, #16]
8004b66: 4013 ands r3, r2
8004b68: 613b str r3, [r7, #16]
if ((GPIO_Init->Mode & EXTI_IT) != 0x00U)
8004b6a: 683b ldr r3, [r7, #0]
8004b6c: 685b ldr r3, [r3, #4]
8004b6e: f403 3380 and.w r3, r3, #65536 @ 0x10000
8004b72: 2b00 cmp r3, #0
8004b74: d003 beq.n 8004b7e <HAL_GPIO_Init+0x2ba>
{
temp |= iocurrent;
8004b76: 693a ldr r2, [r7, #16]
8004b78: 68fb ldr r3, [r7, #12]
8004b7a: 4313 orrs r3, r2
8004b7c: 613b str r3, [r7, #16]
}
EXTI->IMR1 = temp;
8004b7e: 4a11 ldr r2, [pc, #68] @ (8004bc4 <HAL_GPIO_Init+0x300>)
8004b80: 693b ldr r3, [r7, #16]
8004b82: 6013 str r3, [r2, #0]
}
}
position++;
8004b84: 697b ldr r3, [r7, #20]
8004b86: 3301 adds r3, #1
8004b88: 617b str r3, [r7, #20]
while (((GPIO_Init->Pin) >> position) != 0U)
8004b8a: 683b ldr r3, [r7, #0]
8004b8c: 681a ldr r2, [r3, #0]
8004b8e: 697b ldr r3, [r7, #20]
8004b90: fa22 f303 lsr.w r3, r2, r3
8004b94: 2b00 cmp r3, #0
8004b96: f47f ae9d bne.w 80048d4 <HAL_GPIO_Init+0x10>
}
}
8004b9a: bf00 nop
8004b9c: bf00 nop
8004b9e: 371c adds r7, #28
8004ba0: 46bd mov sp, r7
8004ba2: f85d 7b04 ldr.w r7, [sp], #4
8004ba6: 4770 bx lr
8004ba8: 40021000 .word 0x40021000
8004bac: 40010000 .word 0x40010000
8004bb0: 48000400 .word 0x48000400
8004bb4: 48000800 .word 0x48000800
8004bb8: 48000c00 .word 0x48000c00
8004bbc: 48001000 .word 0x48001000
8004bc0: 48001400 .word 0x48001400
8004bc4: 40010400 .word 0x40010400
08004bc8 <HAL_GPIO_WritePin>:
* @arg GPIO_PIN_RESET: to clear the port pin
* @arg GPIO_PIN_SET: to set the port pin
* @retval None
*/
void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
{
8004bc8: b480 push {r7}
8004bca: b083 sub sp, #12
8004bcc: af00 add r7, sp, #0
8004bce: 6078 str r0, [r7, #4]
8004bd0: 460b mov r3, r1
8004bd2: 807b strh r3, [r7, #2]
8004bd4: 4613 mov r3, r2
8004bd6: 707b strb r3, [r7, #1]
/* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_PIN_ACTION(PinState));
if (PinState != GPIO_PIN_RESET)
8004bd8: 787b ldrb r3, [r7, #1]
8004bda: 2b00 cmp r3, #0
8004bdc: d003 beq.n 8004be6 <HAL_GPIO_WritePin+0x1e>
{
GPIOx->BSRR = (uint32_t)GPIO_Pin;
8004bde: 887a ldrh r2, [r7, #2]
8004be0: 687b ldr r3, [r7, #4]
8004be2: 619a str r2, [r3, #24]
}
else
{
GPIOx->BRR = (uint32_t)GPIO_Pin;
}
}
8004be4: e002 b.n 8004bec <HAL_GPIO_WritePin+0x24>
GPIOx->BRR = (uint32_t)GPIO_Pin;
8004be6: 887a ldrh r2, [r7, #2]
8004be8: 687b ldr r3, [r7, #4]
8004bea: 629a str r2, [r3, #40] @ 0x28
}
8004bec: bf00 nop
8004bee: 370c adds r7, #12
8004bf0: 46bd mov sp, r7
8004bf2: f85d 7b04 ldr.w r7, [sp], #4
8004bf6: 4770 bx lr
08004bf8 <HAL_HRTIM_Init>:
* @brief Initialize a HRTIM instance
* @param hhrtim pointer to HAL HRTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim)
{
8004bf8: b580 push {r7, lr}
8004bfa: b086 sub sp, #24
8004bfc: af00 add r7, sp, #0
8004bfe: 6078 str r0, [r7, #4]
uint8_t timer_idx;
uint32_t hrtim_mcr;
/* Check the HRTIM handle allocation */
if (hhrtim == NULL)
8004c00: 687b ldr r3, [r7, #4]
8004c02: 2b00 cmp r3, #0
8004c04: d101 bne.n 8004c0a <HAL_HRTIM_Init+0x12>
{
return HAL_ERROR;
8004c06: 2301 movs r3, #1
8004c08: e0be b.n 8004d88 <HAL_HRTIM_Init+0x190>
}
}
#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
/* Set the HRTIM state */
hhrtim->State = HAL_HRTIM_STATE_BUSY;
8004c0a: 687b ldr r3, [r7, #4]
8004c0c: 2202 movs r2, #2
8004c0e: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Initialize the DMA handles */
hhrtim->hdmaMaster = (DMA_HandleTypeDef *)NULL;
8004c12: 687b ldr r3, [r7, #4]
8004c14: 2200 movs r2, #0
8004c16: f8c3 20e0 str.w r2, [r3, #224] @ 0xe0
hhrtim->hdmaTimerA = (DMA_HandleTypeDef *)NULL;
8004c1a: 687b ldr r3, [r7, #4]
8004c1c: 2200 movs r2, #0
8004c1e: f8c3 20e4 str.w r2, [r3, #228] @ 0xe4
hhrtim->hdmaTimerB = (DMA_HandleTypeDef *)NULL;
8004c22: 687b ldr r3, [r7, #4]
8004c24: 2200 movs r2, #0
8004c26: f8c3 20e8 str.w r2, [r3, #232] @ 0xe8
hhrtim->hdmaTimerC = (DMA_HandleTypeDef *)NULL;
8004c2a: 687b ldr r3, [r7, #4]
8004c2c: 2200 movs r2, #0
8004c2e: f8c3 20ec str.w r2, [r3, #236] @ 0xec
hhrtim->hdmaTimerD = (DMA_HandleTypeDef *)NULL;
8004c32: 687b ldr r3, [r7, #4]
8004c34: 2200 movs r2, #0
8004c36: f8c3 20f0 str.w r2, [r3, #240] @ 0xf0
hhrtim->hdmaTimerE = (DMA_HandleTypeDef *)NULL;
8004c3a: 687b ldr r3, [r7, #4]
8004c3c: 2200 movs r2, #0
8004c3e: f8c3 20f4 str.w r2, [r3, #244] @ 0xf4
hhrtim->hdmaTimerF = (DMA_HandleTypeDef *)NULL;
8004c42: 687b ldr r3, [r7, #4]
8004c44: 2200 movs r2, #0
8004c46: f8c3 20f8 str.w r2, [r3, #248] @ 0xf8
/* HRTIM output synchronization configuration (if required) */
if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_MASTER) != (uint32_t)RESET)
8004c4a: 687b ldr r3, [r7, #4]
8004c4c: 689b ldr r3, [r3, #8]
8004c4e: f003 0301 and.w r3, r3, #1
8004c52: 2b00 cmp r3, #0
8004c54: d02e beq.n 8004cb4 <HAL_HRTIM_Init+0xbc>
assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(hhrtim->Init.SyncOutputPolarity));
/* The synchronization output initialization procedure must be done prior
to the configuration of the MCU outputs (done within HAL_HRTIM_MspInit)
*/
if (hhrtim->Instance == HRTIM1)
8004c56: 687b ldr r3, [r7, #4]
8004c58: 681b ldr r3, [r3, #0]
8004c5a: 4a4d ldr r2, [pc, #308] @ (8004d90 <HAL_HRTIM_Init+0x198>)
8004c5c: 4293 cmp r3, r2
8004c5e: d10b bne.n 8004c78 <HAL_HRTIM_Init+0x80>
{
/* Enable the HRTIM peripheral clock */
__HAL_RCC_HRTIM1_CLK_ENABLE();
8004c60: 4b4c ldr r3, [pc, #304] @ (8004d94 <HAL_HRTIM_Init+0x19c>)
8004c62: 6e1b ldr r3, [r3, #96] @ 0x60
8004c64: 4a4b ldr r2, [pc, #300] @ (8004d94 <HAL_HRTIM_Init+0x19c>)
8004c66: f043 6380 orr.w r3, r3, #67108864 @ 0x4000000
8004c6a: 6613 str r3, [r2, #96] @ 0x60
8004c6c: 4b49 ldr r3, [pc, #292] @ (8004d94 <HAL_HRTIM_Init+0x19c>)
8004c6e: 6e1b ldr r3, [r3, #96] @ 0x60
8004c70: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8004c74: 60fb str r3, [r7, #12]
8004c76: 68fb ldr r3, [r7, #12]
}
hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
8004c78: 687b ldr r3, [r7, #4]
8004c7a: 681b ldr r3, [r3, #0]
8004c7c: 681b ldr r3, [r3, #0]
8004c7e: 613b str r3, [r7, #16]
/* Set the event to be sent on the synchronization output */
hrtim_mcr &= ~(HRTIM_MCR_SYNC_SRC);
8004c80: 693b ldr r3, [r7, #16]
8004c82: f423 4340 bic.w r3, r3, #49152 @ 0xc000
8004c86: 613b str r3, [r7, #16]
hrtim_mcr |= (hhrtim->Init.SyncOutputSource & HRTIM_MCR_SYNC_SRC);
8004c88: 687b ldr r3, [r7, #4]
8004c8a: 691b ldr r3, [r3, #16]
8004c8c: f403 4340 and.w r3, r3, #49152 @ 0xc000
8004c90: 693a ldr r2, [r7, #16]
8004c92: 4313 orrs r3, r2
8004c94: 613b str r3, [r7, #16]
/* Set the polarity of the synchronization output */
hrtim_mcr &= ~(HRTIM_MCR_SYNC_OUT);
8004c96: 693b ldr r3, [r7, #16]
8004c98: f423 5340 bic.w r3, r3, #12288 @ 0x3000
8004c9c: 613b str r3, [r7, #16]
hrtim_mcr |= (hhrtim->Init.SyncOutputPolarity & HRTIM_MCR_SYNC_OUT);
8004c9e: 687b ldr r3, [r7, #4]
8004ca0: 695b ldr r3, [r3, #20]
8004ca2: f403 5340 and.w r3, r3, #12288 @ 0x3000
8004ca6: 693a ldr r2, [r7, #16]
8004ca8: 4313 orrs r3, r2
8004caa: 613b str r3, [r7, #16]
/* Update the HRTIM registers */
hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
8004cac: 687b ldr r3, [r7, #4]
8004cae: 681b ldr r3, [r3, #0]
8004cb0: 693a ldr r2, [r7, #16]
8004cb2: 601a str r2, [r3, #0]
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)
hhrtim->MspInitCallback(hhrtim);
#else
HAL_HRTIM_MspInit(hhrtim);
8004cb4: 6878 ldr r0, [r7, #4]
8004cb6: f7fc fcf9 bl 80016ac <HAL_HRTIM_MspInit>
#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */
/* HRTIM input synchronization configuration (if required) */
if ((hhrtim->Init.SyncOptions & HRTIM_SYNCOPTION_SLAVE) != (uint32_t)RESET)
8004cba: 687b ldr r3, [r7, #4]
8004cbc: 689b ldr r3, [r3, #8]
8004cbe: f003 0302 and.w r3, r3, #2
8004cc2: 2b00 cmp r3, #0
8004cc4: d012 beq.n 8004cec <HAL_HRTIM_Init+0xf4>
{
/* Check parameters */
assert_param(IS_HRTIM_SYNCINPUTSOURCE(hhrtim->Init.SyncInputSource));
hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
8004cc6: 687b ldr r3, [r7, #4]
8004cc8: 681b ldr r3, [r3, #0]
8004cca: 681b ldr r3, [r3, #0]
8004ccc: 613b str r3, [r7, #16]
/* Set the synchronization input source */
hrtim_mcr &= ~(HRTIM_MCR_SYNC_IN);
8004cce: 693b ldr r3, [r7, #16]
8004cd0: f423 7340 bic.w r3, r3, #768 @ 0x300
8004cd4: 613b str r3, [r7, #16]
hrtim_mcr |= (hhrtim->Init.SyncInputSource & HRTIM_MCR_SYNC_IN);
8004cd6: 687b ldr r3, [r7, #4]
8004cd8: 68db ldr r3, [r3, #12]
8004cda: f403 7340 and.w r3, r3, #768 @ 0x300
8004cde: 693a ldr r2, [r7, #16]
8004ce0: 4313 orrs r3, r2
8004ce2: 613b str r3, [r7, #16]
/* Update the HRTIM registers */
hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
8004ce4: 687b ldr r3, [r7, #4]
8004ce6: 681b ldr r3, [r3, #0]
8004ce8: 693a ldr r2, [r7, #16]
8004cea: 601a str r2, [r3, #0]
}
/* Initialize the HRTIM state*/
hhrtim->State = HAL_HRTIM_STATE_READY;
8004cec: 687b ldr r3, [r7, #4]
8004cee: 2201 movs r2, #1
8004cf0: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Initialize the lock status of the HRTIM HAL API */
__HAL_UNLOCK(hhrtim);
8004cf4: 687b ldr r3, [r7, #4]
8004cf6: 2200 movs r2, #0
8004cf8: f883 20dc strb.w r2, [r3, #220] @ 0xdc
/* Initialize timer related parameters */
for (timer_idx = HRTIM_TIMERINDEX_TIMER_A ;
8004cfc: 2300 movs r3, #0
8004cfe: 75fb strb r3, [r7, #23]
8004d00: e03e b.n 8004d80 <HAL_HRTIM_Init+0x188>
timer_idx <= HRTIM_TIMERINDEX_MASTER ;
timer_idx++)
{
hhrtim->TimerParam[timer_idx].CaptureTrigger1 = HRTIM_CAPTURETRIGGER_NONE;
8004d02: 7dfa ldrb r2, [r7, #23]
8004d04: 6879 ldr r1, [r7, #4]
8004d06: 4613 mov r3, r2
8004d08: 00db lsls r3, r3, #3
8004d0a: 1a9b subs r3, r3, r2
8004d0c: 009b lsls r3, r3, #2
8004d0e: 440b add r3, r1
8004d10: 3318 adds r3, #24
8004d12: 2200 movs r2, #0
8004d14: 601a str r2, [r3, #0]
hhrtim->TimerParam[timer_idx].CaptureTrigger2 = HRTIM_CAPTURETRIGGER_NONE;
8004d16: 7dfa ldrb r2, [r7, #23]
8004d18: 6879 ldr r1, [r7, #4]
8004d1a: 4613 mov r3, r2
8004d1c: 00db lsls r3, r3, #3
8004d1e: 1a9b subs r3, r3, r2
8004d20: 009b lsls r3, r3, #2
8004d22: 440b add r3, r1
8004d24: 331c adds r3, #28
8004d26: 2200 movs r2, #0
8004d28: 601a str r2, [r3, #0]
hhrtim->TimerParam[timer_idx].InterruptRequests = HRTIM_IT_NONE;
8004d2a: 7dfa ldrb r2, [r7, #23]
8004d2c: 6879 ldr r1, [r7, #4]
8004d2e: 4613 mov r3, r2
8004d30: 00db lsls r3, r3, #3
8004d32: 1a9b subs r3, r3, r2
8004d34: 009b lsls r3, r3, #2
8004d36: 440b add r3, r1
8004d38: 3320 adds r3, #32
8004d3a: 2200 movs r2, #0
8004d3c: 601a str r2, [r3, #0]
hhrtim->TimerParam[timer_idx].DMARequests = HRTIM_IT_NONE;
8004d3e: 7dfa ldrb r2, [r7, #23]
8004d40: 6879 ldr r1, [r7, #4]
8004d42: 4613 mov r3, r2
8004d44: 00db lsls r3, r3, #3
8004d46: 1a9b subs r3, r3, r2
8004d48: 009b lsls r3, r3, #2
8004d4a: 440b add r3, r1
8004d4c: 3324 adds r3, #36 @ 0x24
8004d4e: 2200 movs r2, #0
8004d50: 601a str r2, [r3, #0]
hhrtim->TimerParam[timer_idx].DMASrcAddress = 0U;
8004d52: 7dfa ldrb r2, [r7, #23]
8004d54: 6879 ldr r1, [r7, #4]
8004d56: 4613 mov r3, r2
8004d58: 00db lsls r3, r3, #3
8004d5a: 1a9b subs r3, r3, r2
8004d5c: 009b lsls r3, r3, #2
8004d5e: 440b add r3, r1
8004d60: 3328 adds r3, #40 @ 0x28
8004d62: 2200 movs r2, #0
8004d64: 601a str r2, [r3, #0]
hhrtim->TimerParam[timer_idx].DMASize = 0U;
8004d66: 7dfa ldrb r2, [r7, #23]
8004d68: 6879 ldr r1, [r7, #4]
8004d6a: 4613 mov r3, r2
8004d6c: 00db lsls r3, r3, #3
8004d6e: 1a9b subs r3, r3, r2
8004d70: 009b lsls r3, r3, #2
8004d72: 440b add r3, r1
8004d74: 3330 adds r3, #48 @ 0x30
8004d76: 2200 movs r2, #0
8004d78: 601a str r2, [r3, #0]
timer_idx++)
8004d7a: 7dfb ldrb r3, [r7, #23]
8004d7c: 3301 adds r3, #1
8004d7e: 75fb strb r3, [r7, #23]
timer_idx <= HRTIM_TIMERINDEX_MASTER ;
8004d80: 7dfb ldrb r3, [r7, #23]
8004d82: 2b06 cmp r3, #6
8004d84: d9bd bls.n 8004d02 <HAL_HRTIM_Init+0x10a>
}
return HAL_OK;
8004d86: 2300 movs r3, #0
}
8004d88: 4618 mov r0, r3
8004d8a: 3718 adds r7, #24
8004d8c: 46bd mov sp, r7
8004d8e: bd80 pop {r7, pc}
8004d90: 40016800 .word 0x40016800
8004d94: 40021000 .word 0x40021000
08004d98 <HAL_HRTIM_DLLCalibrationStart>:
* within the HAL_HRTIM_PollForDLLCalibration function, just before
* exiting the function.
*/
HAL_StatusTypeDef HAL_HRTIM_DLLCalibrationStart(HRTIM_HandleTypeDef *hhrtim,
uint32_t CalibrationRate)
{
8004d98: b480 push {r7}
8004d9a: b083 sub sp, #12
8004d9c: af00 add r7, sp, #0
8004d9e: 6078 str r0, [r7, #4]
8004da0: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
/* Process Locked */
__HAL_LOCK(hhrtim);
8004da2: 687b ldr r3, [r7, #4]
8004da4: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc
8004da8: 2b01 cmp r3, #1
8004daa: d101 bne.n 8004db0 <HAL_HRTIM_DLLCalibrationStart+0x18>
8004dac: 2302 movs r3, #2
8004dae: e045 b.n 8004e3c <HAL_HRTIM_DLLCalibrationStart+0xa4>
8004db0: 687b ldr r3, [r7, #4]
8004db2: 2201 movs r2, #1
8004db4: f883 20dc strb.w r2, [r3, #220] @ 0xdc
hhrtim->State = HAL_HRTIM_STATE_BUSY;
8004db8: 687b ldr r3, [r7, #4]
8004dba: 2202 movs r2, #2
8004dbc: f883 20dd strb.w r2, [r3, #221] @ 0xdd
if (CalibrationRate == HRTIM_SINGLE_CALIBRATION)
8004dc0: 683b ldr r3, [r7, #0]
8004dc2: f1b3 3fff cmp.w r3, #4294967295
8004dc6: d114 bne.n 8004df2 <HAL_HRTIM_DLLCalibrationStart+0x5a>
{
/* One shot DLL calibration */
CLEAR_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
8004dc8: 687b ldr r3, [r7, #4]
8004dca: 681b ldr r3, [r3, #0]
8004dcc: f8d3 23cc ldr.w r2, [r3, #972] @ 0x3cc
8004dd0: 687b ldr r3, [r7, #4]
8004dd2: 681b ldr r3, [r3, #0]
8004dd4: f022 0202 bic.w r2, r2, #2
8004dd8: f8c3 23cc str.w r2, [r3, #972] @ 0x3cc
SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
8004ddc: 687b ldr r3, [r7, #4]
8004dde: 681b ldr r3, [r3, #0]
8004de0: f8d3 23cc ldr.w r2, [r3, #972] @ 0x3cc
8004de4: 687b ldr r3, [r7, #4]
8004de6: 681b ldr r3, [r3, #0]
8004de8: f042 0201 orr.w r2, r2, #1
8004dec: f8c3 23cc str.w r2, [r3, #972] @ 0x3cc
8004df0: e01f b.n 8004e32 <HAL_HRTIM_DLLCalibrationStart+0x9a>
}
else
{
/* Periodic DLL calibration */
SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALEN);
8004df2: 687b ldr r3, [r7, #4]
8004df4: 681b ldr r3, [r3, #0]
8004df6: f8d3 23cc ldr.w r2, [r3, #972] @ 0x3cc
8004dfa: 687b ldr r3, [r7, #4]
8004dfc: 681b ldr r3, [r3, #0]
8004dfe: f042 0202 orr.w r2, r2, #2
8004e02: f8c3 23cc str.w r2, [r3, #972] @ 0x3cc
MODIFY_REG(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CALRTE, CalibrationRate);
8004e06: 687b ldr r3, [r7, #4]
8004e08: 681b ldr r3, [r3, #0]
8004e0a: f8d3 33cc ldr.w r3, [r3, #972] @ 0x3cc
8004e0e: f023 010c bic.w r1, r3, #12
8004e12: 687b ldr r3, [r7, #4]
8004e14: 681b ldr r3, [r3, #0]
8004e16: 683a ldr r2, [r7, #0]
8004e18: 430a orrs r2, r1
8004e1a: f8c3 23cc str.w r2, [r3, #972] @ 0x3cc
SET_BIT(hhrtim->Instance->sCommonRegs.DLLCR, HRTIM_DLLCR_CAL);
8004e1e: 687b ldr r3, [r7, #4]
8004e20: 681b ldr r3, [r3, #0]
8004e22: f8d3 23cc ldr.w r2, [r3, #972] @ 0x3cc
8004e26: 687b ldr r3, [r7, #4]
8004e28: 681b ldr r3, [r3, #0]
8004e2a: f042 0201 orr.w r2, r2, #1
8004e2e: f8c3 23cc str.w r2, [r3, #972] @ 0x3cc
}
/* Set HRTIM state */
hhrtim->State = HAL_HRTIM_STATE_READY;
8004e32: 687b ldr r3, [r7, #4]
8004e34: 2201 movs r2, #1
8004e36: f883 20dd strb.w r2, [r3, #221] @ 0xdd
return HAL_OK;
8004e3a: 2300 movs r3, #0
}
8004e3c: 4618 mov r0, r3
8004e3e: 370c adds r7, #12
8004e40: 46bd mov sp, r7
8004e42: f85d 7b04 ldr.w r7, [sp], #4
8004e46: 4770 bx lr
08004e48 <HAL_HRTIM_PollForDLLCalibration>:
* @param Timeout Timeout duration in millisecond
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HRTIM_PollForDLLCalibration(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timeout)
{
8004e48: b580 push {r7, lr}
8004e4a: b084 sub sp, #16
8004e4c: af00 add r7, sp, #0
8004e4e: 6078 str r0, [r7, #4]
8004e50: 6039 str r1, [r7, #0]
uint32_t tickstart;
tickstart = HAL_GetTick();
8004e52: f7fc fe4b bl 8001aec <HAL_GetTick>
8004e56: 60f8 str r0, [r7, #12]
/* Check End of conversion flag */
while (__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET)
8004e58: e014 b.n 8004e84 <HAL_HRTIM_PollForDLLCalibration+0x3c>
{
if (Timeout != HAL_MAX_DELAY)
8004e5a: 683b ldr r3, [r7, #0]
8004e5c: f1b3 3fff cmp.w r3, #4294967295
8004e60: d010 beq.n 8004e84 <HAL_HRTIM_PollForDLLCalibration+0x3c>
{
if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
8004e62: f7fc fe43 bl 8001aec <HAL_GetTick>
8004e66: 4602 mov r2, r0
8004e68: 68fb ldr r3, [r7, #12]
8004e6a: 1ad3 subs r3, r2, r3
8004e6c: 683a ldr r2, [r7, #0]
8004e6e: 429a cmp r2, r3
8004e70: d302 bcc.n 8004e78 <HAL_HRTIM_PollForDLLCalibration+0x30>
8004e72: 683b ldr r3, [r7, #0]
8004e74: 2b00 cmp r3, #0
8004e76: d105 bne.n 8004e84 <HAL_HRTIM_PollForDLLCalibration+0x3c>
{
hhrtim->State = HAL_HRTIM_STATE_ERROR;
8004e78: 687b ldr r3, [r7, #4]
8004e7a: 2207 movs r2, #7
8004e7c: f883 20dd strb.w r2, [r3, #221] @ 0xdd
return HAL_TIMEOUT;
8004e80: 2303 movs r3, #3
8004e82: e011 b.n 8004ea8 <HAL_HRTIM_PollForDLLCalibration+0x60>
while (__HAL_HRTIM_GET_FLAG(hhrtim, HRTIM_IT_DLLRDY) == (uint32_t)RESET)
8004e84: 687b ldr r3, [r7, #4]
8004e86: 681b ldr r3, [r3, #0]
8004e88: f8d3 3388 ldr.w r3, [r3, #904] @ 0x388
8004e8c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8004e90: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8004e94: d1e1 bne.n 8004e5a <HAL_HRTIM_PollForDLLCalibration+0x12>
}
}
}
/* Set HRTIM State */
hhrtim->State = HAL_HRTIM_STATE_READY;
8004e96: 687b ldr r3, [r7, #4]
8004e98: 2201 movs r2, #1
8004e9a: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process unlocked */
__HAL_UNLOCK(hhrtim);
8004e9e: 687b ldr r3, [r7, #4]
8004ea0: 2200 movs r2, #0
8004ea2: f883 20dc strb.w r2, [r3, #220] @ 0xdc
return HAL_OK;
8004ea6: 2300 movs r3, #0
}
8004ea8: 4618 mov r0, r3
8004eaa: 3710 adds r7, #16
8004eac: 46bd mov sp, r7
8004eae: bd80 pop {r7, pc}
08004eb0 <HAL_HRTIM_TimeBaseConfig>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
{
8004eb0: b580 push {r7, lr}
8004eb2: b084 sub sp, #16
8004eb4: af00 add r7, sp, #0
8004eb6: 60f8 str r0, [r7, #12]
8004eb8: 60b9 str r1, [r7, #8]
8004eba: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
assert_param(IS_HRTIM_PRESCALERRATIO(pTimeBaseCfg->PrescalerRatio));
assert_param(IS_HRTIM_MODE(pTimeBaseCfg->Mode));
if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
8004ebc: 68fb ldr r3, [r7, #12]
8004ebe: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd
8004ec2: b2db uxtb r3, r3
8004ec4: 2b02 cmp r3, #2
8004ec6: d101 bne.n 8004ecc <HAL_HRTIM_TimeBaseConfig+0x1c>
{
return HAL_BUSY;
8004ec8: 2302 movs r3, #2
8004eca: e015 b.n 8004ef8 <HAL_HRTIM_TimeBaseConfig+0x48>
}
/* Set the HRTIM state */
hhrtim->State = HAL_HRTIM_STATE_BUSY;
8004ecc: 68fb ldr r3, [r7, #12]
8004ece: 2202 movs r2, #2
8004ed0: f883 20dd strb.w r2, [r3, #221] @ 0xdd
if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
8004ed4: 68bb ldr r3, [r7, #8]
8004ed6: 2b06 cmp r3, #6
8004ed8: d104 bne.n 8004ee4 <HAL_HRTIM_TimeBaseConfig+0x34>
{
/* Configure master timer time base unit */
HRTIM_MasterBase_Config(hhrtim, pTimeBaseCfg);
8004eda: 6879 ldr r1, [r7, #4]
8004edc: 68f8 ldr r0, [r7, #12]
8004ede: f000 fbdb bl 8005698 <HRTIM_MasterBase_Config>
8004ee2: e004 b.n 8004eee <HAL_HRTIM_TimeBaseConfig+0x3e>
}
else
{
/* Configure timing unit time base unit */
HRTIM_TimingUnitBase_Config(hhrtim, TimerIdx, pTimeBaseCfg);
8004ee4: 687a ldr r2, [r7, #4]
8004ee6: 68b9 ldr r1, [r7, #8]
8004ee8: 68f8 ldr r0, [r7, #12]
8004eea: f000 fc04 bl 80056f6 <HRTIM_TimingUnitBase_Config>
}
/* Set HRTIM state */
hhrtim->State = HAL_HRTIM_STATE_READY;
8004eee: 68fb ldr r3, [r7, #12]
8004ef0: 2201 movs r2, #1
8004ef2: f883 20dd strb.w r2, [r3, #221] @ 0xdd
return HAL_OK;
8004ef6: 2300 movs r3, #0
}
8004ef8: 4618 mov r0, r3
8004efa: 3710 adds r7, #16
8004efc: 46bd mov sp, r7
8004efe: bd80 pop {r7, pc}
08004f00 <HAL_HRTIM_EventConfig>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t Event,
const HRTIM_EventCfgTypeDef *pEventCfg)
{
8004f00: b580 push {r7, lr}
8004f02: b084 sub sp, #16
8004f04: af00 add r7, sp, #0
8004f06: 60f8 str r0, [r7, #12]
8004f08: 60b9 str r1, [r7, #8]
8004f0a: 607a str r2, [r7, #4]
assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Sensitivity, pEventCfg->Polarity));
assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
assert_param(IS_HRTIM_EVENTFASTMODE(Event, pEventCfg->FastMode));
assert_param(IS_HRTIM_EVENTFILTER(Event, pEventCfg->Filter));
if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
8004f0c: 68fb ldr r3, [r7, #12]
8004f0e: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd
8004f12: b2db uxtb r3, r3
8004f14: 2b02 cmp r3, #2
8004f16: d101 bne.n 8004f1c <HAL_HRTIM_EventConfig+0x1c>
{
return HAL_BUSY;
8004f18: 2302 movs r3, #2
8004f1a: e01c b.n 8004f56 <HAL_HRTIM_EventConfig+0x56>
}
/* Process Locked */
__HAL_LOCK(hhrtim);
8004f1c: 68fb ldr r3, [r7, #12]
8004f1e: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc
8004f22: 2b01 cmp r3, #1
8004f24: d101 bne.n 8004f2a <HAL_HRTIM_EventConfig+0x2a>
8004f26: 2302 movs r3, #2
8004f28: e015 b.n 8004f56 <HAL_HRTIM_EventConfig+0x56>
8004f2a: 68fb ldr r3, [r7, #12]
8004f2c: 2201 movs r2, #1
8004f2e: f883 20dc strb.w r2, [r3, #220] @ 0xdc
hhrtim->State = HAL_HRTIM_STATE_BUSY;
8004f32: 68fb ldr r3, [r7, #12]
8004f34: 2202 movs r2, #2
8004f36: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Configure the event channel */
HRTIM_EventConfig(hhrtim, Event, pEventCfg);
8004f3a: 687a ldr r2, [r7, #4]
8004f3c: 68b9 ldr r1, [r7, #8]
8004f3e: 68f8 ldr r0, [r7, #12]
8004f40: f000 ff84 bl 8005e4c <HRTIM_EventConfig>
hhrtim->State = HAL_HRTIM_STATE_READY;
8004f44: 68fb ldr r3, [r7, #12]
8004f46: 2201 movs r2, #1
8004f48: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
8004f4c: 68fb ldr r3, [r7, #12]
8004f4e: 2200 movs r2, #0
8004f50: f883 20dc strb.w r2, [r3, #220] @ 0xdc
return HAL_OK;
8004f54: 2300 movs r3, #0
}
8004f56: 4618 mov r0, r3
8004f58: 3710 adds r7, #16
8004f5a: 46bd mov sp, r7
8004f5c: bd80 pop {r7, pc}
08004f5e <HAL_HRTIM_EventPrescalerConfig>:
* @note This function must be called before starting the timer
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t Prescaler)
{
8004f5e: b480 push {r7}
8004f60: b083 sub sp, #12
8004f62: af00 add r7, sp, #0
8004f64: 6078 str r0, [r7, #4]
8004f66: 6039 str r1, [r7, #0]
/* Check parameters */
assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
8004f68: 687b ldr r3, [r7, #4]
8004f6a: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd
8004f6e: b2db uxtb r3, r3
8004f70: 2b02 cmp r3, #2
8004f72: d101 bne.n 8004f78 <HAL_HRTIM_EventPrescalerConfig+0x1a>
{
return HAL_BUSY;
8004f74: 2302 movs r3, #2
8004f76: e025 b.n 8004fc4 <HAL_HRTIM_EventPrescalerConfig+0x66>
}
/* Process Locked */
__HAL_LOCK(hhrtim);
8004f78: 687b ldr r3, [r7, #4]
8004f7a: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc
8004f7e: 2b01 cmp r3, #1
8004f80: d101 bne.n 8004f86 <HAL_HRTIM_EventPrescalerConfig+0x28>
8004f82: 2302 movs r3, #2
8004f84: e01e b.n 8004fc4 <HAL_HRTIM_EventPrescalerConfig+0x66>
8004f86: 687b ldr r3, [r7, #4]
8004f88: 2201 movs r2, #1
8004f8a: f883 20dc strb.w r2, [r3, #220] @ 0xdc
hhrtim->State = HAL_HRTIM_STATE_BUSY;
8004f8e: 687b ldr r3, [r7, #4]
8004f90: 2202 movs r2, #2
8004f92: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Set the external event prescaler */
MODIFY_REG(hhrtim->Instance->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, (Prescaler & HRTIM_EECR3_EEVSD));
8004f96: 687b ldr r3, [r7, #4]
8004f98: 681b ldr r3, [r3, #0]
8004f9a: f8d3 33b8 ldr.w r3, [r3, #952] @ 0x3b8
8004f9e: f023 4140 bic.w r1, r3, #3221225472 @ 0xc0000000
8004fa2: 683b ldr r3, [r7, #0]
8004fa4: f003 4240 and.w r2, r3, #3221225472 @ 0xc0000000
8004fa8: 687b ldr r3, [r7, #4]
8004faa: 681b ldr r3, [r3, #0]
8004fac: 430a orrs r2, r1
8004fae: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8
hhrtim->State = HAL_HRTIM_STATE_READY;
8004fb2: 687b ldr r3, [r7, #4]
8004fb4: 2201 movs r2, #1
8004fb6: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
8004fba: 687b ldr r3, [r7, #4]
8004fbc: 2200 movs r2, #0
8004fbe: f883 20dc strb.w r2, [r3, #220] @ 0xdc
return HAL_OK;
8004fc2: 2300 movs r3, #0
}
8004fc4: 4618 mov r0, r3
8004fc6: 370c adds r7, #12
8004fc8: 46bd mov sp, r7
8004fca: f85d 7b04 ldr.w r7, [sp], #4
8004fce: 4770 bx lr
08004fd0 <HAL_HRTIM_WaveformTimerConfig>:
* @note This function must be called before starting the timer
*/
HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
const HRTIM_TimerCfgTypeDef *pTimerCfg)
{
8004fd0: b580 push {r7, lr}
8004fd2: b084 sub sp, #16
8004fd4: af00 add r7, sp, #0
8004fd6: 60f8 str r0, [r7, #12]
8004fd8: 60b9 str r1, [r7, #8]
8004fda: 607a str r2, [r7, #4]
assert_param(IS_HRTIM_DACSYNC(pTimerCfg->DACSynchro));
assert_param(IS_HRTIM_PRELOAD(pTimerCfg->PreloadEnable));
assert_param(IS_HRTIM_TIMERBURSTMODE(pTimerCfg->BurstMode));
assert_param(IS_HRTIM_UPDATEONREPETITION(pTimerCfg->RepetitionUpdate));
if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
8004fdc: 68fb ldr r3, [r7, #12]
8004fde: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd
8004fe2: b2db uxtb r3, r3
8004fe4: 2b02 cmp r3, #2
8004fe6: d101 bne.n 8004fec <HAL_HRTIM_WaveformTimerConfig+0x1c>
{
return HAL_BUSY;
8004fe8: 2302 movs r3, #2
8004fea: e07a b.n 80050e2 <HAL_HRTIM_WaveformTimerConfig+0x112>
}
/* Process Locked */
__HAL_LOCK(hhrtim);
8004fec: 68fb ldr r3, [r7, #12]
8004fee: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc
8004ff2: 2b01 cmp r3, #1
8004ff4: d101 bne.n 8004ffa <HAL_HRTIM_WaveformTimerConfig+0x2a>
8004ff6: 2302 movs r3, #2
8004ff8: e073 b.n 80050e2 <HAL_HRTIM_WaveformTimerConfig+0x112>
8004ffa: 68fb ldr r3, [r7, #12]
8004ffc: 2201 movs r2, #1
8004ffe: f883 20dc strb.w r2, [r3, #220] @ 0xdc
hhrtim->State = HAL_HRTIM_STATE_BUSY;
8005002: 68fb ldr r3, [r7, #12]
8005004: 2202 movs r2, #2
8005006: f883 20dd strb.w r2, [r3, #221] @ 0xdd
if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
800500a: 68bb ldr r3, [r7, #8]
800500c: 2b06 cmp r3, #6
800500e: d104 bne.n 800501a <HAL_HRTIM_WaveformTimerConfig+0x4a>
assert_param(IS_HRTIM_UPDATEGATING_MASTER(pTimerCfg->UpdateGating));
assert_param(IS_HRTIM_MASTER_IT(pTimerCfg->InterruptRequests));
assert_param(IS_HRTIM_MASTER_DMA(pTimerCfg->DMARequests));
/* Configure master timer */
HRTIM_MasterWaveform_Config(hhrtim, pTimerCfg);
8005010: 6879 ldr r1, [r7, #4]
8005012: 68f8 ldr r0, [r7, #12]
8005014: f000 fbaf bl 8005776 <HRTIM_MasterWaveform_Config>
8005018: e004 b.n 8005024 <HAL_HRTIM_WaveformTimerConfig+0x54>
assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
assert_param(IS_HRTIM_TIMSYNCUPDATE(pTimerCfg->ReSyncUpdate));
/* Configure timing unit */
HRTIM_TimingUnitWaveform_Config(hhrtim, TimerIdx, pTimerCfg);
800501a: 687a ldr r2, [r7, #4]
800501c: 68b9 ldr r1, [r7, #8]
800501e: 68f8 ldr r0, [r7, #12]
8005020: f000 fc46 bl 80058b0 <HRTIM_TimingUnitWaveform_Config>
}
/* Update timer parameters */
hhrtim->TimerParam[TimerIdx].InterruptRequests = pTimerCfg->InterruptRequests;
8005024: 687b ldr r3, [r7, #4]
8005026: 6819 ldr r1, [r3, #0]
8005028: 68f8 ldr r0, [r7, #12]
800502a: 68ba ldr r2, [r7, #8]
800502c: 4613 mov r3, r2
800502e: 00db lsls r3, r3, #3
8005030: 1a9b subs r3, r3, r2
8005032: 009b lsls r3, r3, #2
8005034: 4403 add r3, r0
8005036: 3320 adds r3, #32
8005038: 6019 str r1, [r3, #0]
hhrtim->TimerParam[TimerIdx].DMARequests = pTimerCfg->DMARequests;
800503a: 687b ldr r3, [r7, #4]
800503c: 6859 ldr r1, [r3, #4]
800503e: 68f8 ldr r0, [r7, #12]
8005040: 68ba ldr r2, [r7, #8]
8005042: 4613 mov r3, r2
8005044: 00db lsls r3, r3, #3
8005046: 1a9b subs r3, r3, r2
8005048: 009b lsls r3, r3, #2
800504a: 4403 add r3, r0
800504c: 3324 adds r3, #36 @ 0x24
800504e: 6019 str r1, [r3, #0]
hhrtim->TimerParam[TimerIdx].DMASrcAddress = pTimerCfg->DMASrcAddress;
8005050: 687b ldr r3, [r7, #4]
8005052: 6899 ldr r1, [r3, #8]
8005054: 68f8 ldr r0, [r7, #12]
8005056: 68ba ldr r2, [r7, #8]
8005058: 4613 mov r3, r2
800505a: 00db lsls r3, r3, #3
800505c: 1a9b subs r3, r3, r2
800505e: 009b lsls r3, r3, #2
8005060: 4403 add r3, r0
8005062: 3328 adds r3, #40 @ 0x28
8005064: 6019 str r1, [r3, #0]
hhrtim->TimerParam[TimerIdx].DMADstAddress = pTimerCfg->DMADstAddress;
8005066: 687b ldr r3, [r7, #4]
8005068: 68d9 ldr r1, [r3, #12]
800506a: 68f8 ldr r0, [r7, #12]
800506c: 68ba ldr r2, [r7, #8]
800506e: 4613 mov r3, r2
8005070: 00db lsls r3, r3, #3
8005072: 1a9b subs r3, r3, r2
8005074: 009b lsls r3, r3, #2
8005076: 4403 add r3, r0
8005078: 332c adds r3, #44 @ 0x2c
800507a: 6019 str r1, [r3, #0]
hhrtim->TimerParam[TimerIdx].DMASize = pTimerCfg->DMASize;
800507c: 687b ldr r3, [r7, #4]
800507e: 6919 ldr r1, [r3, #16]
8005080: 68f8 ldr r0, [r7, #12]
8005082: 68ba ldr r2, [r7, #8]
8005084: 4613 mov r3, r2
8005086: 00db lsls r3, r3, #3
8005088: 1a9b subs r3, r3, r2
800508a: 009b lsls r3, r3, #2
800508c: 4403 add r3, r0
800508e: 3330 adds r3, #48 @ 0x30
8005090: 6019 str r1, [r3, #0]
/* Force a software update */
HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
8005092: 68b9 ldr r1, [r7, #8]
8005094: 68f8 ldr r0, [r7, #12]
8005096: f001 f901 bl 800629c <HRTIM_ForceRegistersUpdate>
/* Configure slave timer update re-synchronization */
if ((TimerIdx != HRTIM_TIMERINDEX_MASTER)
800509a: 68bb ldr r3, [r7, #8]
800509c: 2b06 cmp r3, #6
800509e: d017 beq.n 80050d0 <HAL_HRTIM_WaveformTimerConfig+0x100>
&& (pTimerCfg->UpdateGating == HRTIM_UPDATEGATING_INDEPENDENT))
80050a0: 687b ldr r3, [r7, #4]
80050a2: 6adb ldr r3, [r3, #44] @ 0x2c
80050a4: 2b00 cmp r3, #0
80050a6: d113 bne.n 80050d0 <HAL_HRTIM_WaveformTimerConfig+0x100>
{
MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR,
80050a8: 68fb ldr r3, [r7, #12]
80050aa: 681a ldr r2, [r3, #0]
80050ac: 68bb ldr r3, [r7, #8]
80050ae: 3301 adds r3, #1
80050b0: 01db lsls r3, r3, #7
80050b2: 4413 add r3, r2
80050b4: 681b ldr r3, [r3, #0]
80050b6: f423 7200 bic.w r2, r3, #512 @ 0x200
80050ba: 687b ldr r3, [r7, #4]
80050bc: 6ddb ldr r3, [r3, #92] @ 0x5c
80050be: 025b lsls r3, r3, #9
80050c0: 68f9 ldr r1, [r7, #12]
80050c2: 6809 ldr r1, [r1, #0]
80050c4: 431a orrs r2, r3
80050c6: 68bb ldr r3, [r7, #8]
80050c8: 3301 adds r3, #1
80050ca: 01db lsls r3, r3, #7
80050cc: 440b add r3, r1
80050ce: 601a str r2, [r3, #0]
HRTIM_TIMCR_RSYNCU_Msk,
pTimerCfg->ReSyncUpdate << HRTIM_TIMCR_RSYNCU_Pos);
}
hhrtim->State = HAL_HRTIM_STATE_READY;
80050d0: 68fb ldr r3, [r7, #12]
80050d2: 2201 movs r2, #1
80050d4: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
80050d8: 68fb ldr r3, [r7, #12]
80050da: 2200 movs r2, #0
80050dc: f883 20dc strb.w r2, [r3, #220] @ 0xdc
return HAL_OK;
80050e0: 2300 movs r3, #0
}
80050e2: 4618 mov r0, r3
80050e4: 3710 adds r7, #16
80050e6: 46bd mov sp, r7
80050e8: bd80 pop {r7, pc}
080050ea <HAL_HRTIM_WaveformTimerControl>:
* @note This function must be called before starting the timer
*/
HAL_StatusTypeDef HAL_HRTIM_WaveformTimerControl(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
const HRTIM_TimerCtlTypeDef *pTimerCtl)
{
80050ea: b580 push {r7, lr}
80050ec: b084 sub sp, #16
80050ee: af00 add r7, sp, #0
80050f0: 60f8 str r0, [r7, #12]
80050f2: 60b9 str r1, [r7, #8]
80050f4: 607a str r2, [r7, #4]
assert_param(IS_HRTIM_TIMERGTCMP1(pTimerCtl->GreaterCMP1));
assert_param(IS_HRTIM_DUALDAC_RESET(pTimerCtl->DualChannelDacReset));
assert_param(IS_HRTIM_DUALDAC_STEP(pTimerCtl->DualChannelDacStep));
assert_param(IS_HRTIM_DUALDAC_ENABLE(pTimerCtl->DualChannelDacEnable));
if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
80050f6: 68fb ldr r3, [r7, #12]
80050f8: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd
80050fc: b2db uxtb r3, r3
80050fe: 2b02 cmp r3, #2
8005100: d101 bne.n 8005106 <HAL_HRTIM_WaveformTimerControl+0x1c>
{
return HAL_BUSY;
8005102: 2302 movs r3, #2
8005104: e020 b.n 8005148 <HAL_HRTIM_WaveformTimerControl+0x5e>
}
/* Process Locked */
__HAL_LOCK(hhrtim);
8005106: 68fb ldr r3, [r7, #12]
8005108: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc
800510c: 2b01 cmp r3, #1
800510e: d101 bne.n 8005114 <HAL_HRTIM_WaveformTimerControl+0x2a>
8005110: 2302 movs r3, #2
8005112: e019 b.n 8005148 <HAL_HRTIM_WaveformTimerControl+0x5e>
8005114: 68fb ldr r3, [r7, #12]
8005116: 2201 movs r2, #1
8005118: f883 20dc strb.w r2, [r3, #220] @ 0xdc
hhrtim->State = HAL_HRTIM_STATE_BUSY;
800511c: 68fb ldr r3, [r7, #12]
800511e: 2202 movs r2, #2
8005120: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Configure timing unit */
HRTIM_TimingUnitWaveform_Control(hhrtim, TimerIdx, pTimerCtl);
8005124: 687a ldr r2, [r7, #4]
8005126: 68b9 ldr r1, [r7, #8]
8005128: 68f8 ldr r0, [r7, #12]
800512a: f000 fd47 bl 8005bbc <HRTIM_TimingUnitWaveform_Control>
/* Force a software update */
HRTIM_ForceRegistersUpdate(hhrtim, TimerIdx);
800512e: 68b9 ldr r1, [r7, #8]
8005130: 68f8 ldr r0, [r7, #12]
8005132: f001 f8b3 bl 800629c <HRTIM_ForceRegistersUpdate>
hhrtim->State = HAL_HRTIM_STATE_READY;
8005136: 68fb ldr r3, [r7, #12]
8005138: 2201 movs r2, #1
800513a: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
800513e: 68fb ldr r3, [r7, #12]
8005140: 2200 movs r2, #0
8005142: f883 20dc strb.w r2, [r3, #220] @ 0xdc
return HAL_OK;
8005146: 2300 movs r3, #0
}
8005148: 4618 mov r0, r3
800514a: 3710 adds r7, #16
800514c: 46bd mov sp, r7
800514e: bd80 pop {r7, pc}
08005150 <HAL_HRTIM_DeadTimeConfig>:
* @note This function must be called before starting the timer
*/
HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
const HRTIM_DeadTimeCfgTypeDef *pDeadTimeCfg)
{
8005150: b480 push {r7}
8005152: b087 sub sp, #28
8005154: af00 add r7, sp, #0
8005156: 60f8 str r0, [r7, #12]
8005158: 60b9 str r1, [r7, #8]
800515a: 607a str r2, [r7, #4]
assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
800515c: 68fb ldr r3, [r7, #12]
800515e: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd
8005162: b2db uxtb r3, r3
8005164: 2b02 cmp r3, #2
8005166: d101 bne.n 800516c <HAL_HRTIM_DeadTimeConfig+0x1c>
{
return HAL_BUSY;
8005168: 2302 movs r3, #2
800516a: e067 b.n 800523c <HAL_HRTIM_DeadTimeConfig+0xec>
}
/* Process Locked */
__HAL_LOCK(hhrtim);
800516c: 68fb ldr r3, [r7, #12]
800516e: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc
8005172: 2b01 cmp r3, #1
8005174: d101 bne.n 800517a <HAL_HRTIM_DeadTimeConfig+0x2a>
8005176: 2302 movs r3, #2
8005178: e060 b.n 800523c <HAL_HRTIM_DeadTimeConfig+0xec>
800517a: 68fb ldr r3, [r7, #12]
800517c: 2201 movs r2, #1
800517e: f883 20dc strb.w r2, [r3, #220] @ 0xdc
hhrtim->State = HAL_HRTIM_STATE_BUSY;
8005182: 68fb ldr r3, [r7, #12]
8005184: 2202 movs r2, #2
8005186: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Set timer deadtime configuration */
hrtim_dtr = (pDeadTimeCfg->Prescaler & HRTIM_DTR_DTPRSC);
800518a: 687b ldr r3, [r7, #4]
800518c: 681b ldr r3, [r3, #0]
800518e: f403 53e0 and.w r3, r3, #7168 @ 0x1c00
8005192: 617b str r3, [r7, #20]
hrtim_dtr |= (pDeadTimeCfg->RisingValue & HRTIM_DTR_DTR);
8005194: 687b ldr r3, [r7, #4]
8005196: 685b ldr r3, [r3, #4]
8005198: f3c3 0308 ubfx r3, r3, #0, #9
800519c: 697a ldr r2, [r7, #20]
800519e: 4313 orrs r3, r2
80051a0: 617b str r3, [r7, #20]
hrtim_dtr |= (pDeadTimeCfg->RisingSign & HRTIM_DTR_SDTR);
80051a2: 687b ldr r3, [r7, #4]
80051a4: 689b ldr r3, [r3, #8]
80051a6: f403 7300 and.w r3, r3, #512 @ 0x200
80051aa: 697a ldr r2, [r7, #20]
80051ac: 4313 orrs r3, r2
80051ae: 617b str r3, [r7, #20]
hrtim_dtr |= (pDeadTimeCfg->RisingSignLock & HRTIM_DTR_DTRSLK);
80051b0: 687b ldr r3, [r7, #4]
80051b2: 691b ldr r3, [r3, #16]
80051b4: f403 4380 and.w r3, r3, #16384 @ 0x4000
80051b8: 697a ldr r2, [r7, #20]
80051ba: 4313 orrs r3, r2
80051bc: 617b str r3, [r7, #20]
hrtim_dtr |= (pDeadTimeCfg->RisingLock & HRTIM_DTR_DTRLK);
80051be: 687b ldr r3, [r7, #4]
80051c0: 68db ldr r3, [r3, #12]
80051c2: f403 4300 and.w r3, r3, #32768 @ 0x8000
80051c6: 697a ldr r2, [r7, #20]
80051c8: 4313 orrs r3, r2
80051ca: 617b str r3, [r7, #20]
hrtim_dtr |= ((pDeadTimeCfg->FallingValue << 16U) & HRTIM_DTR_DTF);
80051cc: 687b ldr r3, [r7, #4]
80051ce: 695b ldr r3, [r3, #20]
80051d0: 041a lsls r2, r3, #16
80051d2: 4b1d ldr r3, [pc, #116] @ (8005248 <HAL_HRTIM_DeadTimeConfig+0xf8>)
80051d4: 4013 ands r3, r2
80051d6: 697a ldr r2, [r7, #20]
80051d8: 4313 orrs r3, r2
80051da: 617b str r3, [r7, #20]
hrtim_dtr |= (pDeadTimeCfg->FallingSign & HRTIM_DTR_SDTF);
80051dc: 687b ldr r3, [r7, #4]
80051de: 699b ldr r3, [r3, #24]
80051e0: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80051e4: 697a ldr r2, [r7, #20]
80051e6: 4313 orrs r3, r2
80051e8: 617b str r3, [r7, #20]
hrtim_dtr |= (pDeadTimeCfg->FallingSignLock & HRTIM_DTR_DTFSLK);
80051ea: 687b ldr r3, [r7, #4]
80051ec: 6a1b ldr r3, [r3, #32]
80051ee: f003 4380 and.w r3, r3, #1073741824 @ 0x40000000
80051f2: 697a ldr r2, [r7, #20]
80051f4: 4313 orrs r3, r2
80051f6: 617b str r3, [r7, #20]
hrtim_dtr |= (pDeadTimeCfg->FallingLock & HRTIM_DTR_DTFLK);
80051f8: 687b ldr r3, [r7, #4]
80051fa: 69db ldr r3, [r3, #28]
80051fc: f003 4300 and.w r3, r3, #2147483648 @ 0x80000000
8005200: 697a ldr r2, [r7, #20]
8005202: 4313 orrs r3, r2
8005204: 617b str r3, [r7, #20]
/* Update the HRTIM registers */
MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR, (
8005206: 68fb ldr r3, [r7, #12]
8005208: 681a ldr r2, [r3, #0]
800520a: 68bb ldr r3, [r7, #8]
800520c: 01db lsls r3, r3, #7
800520e: 4413 add r3, r2
8005210: 33b8 adds r3, #184 @ 0xb8
8005212: 681a ldr r2, [r3, #0]
8005214: 4b0d ldr r3, [pc, #52] @ (800524c <HAL_HRTIM_DeadTimeConfig+0xfc>)
8005216: 4013 ands r3, r2
8005218: 68fa ldr r2, [r7, #12]
800521a: 6811 ldr r1, [r2, #0]
800521c: 697a ldr r2, [r7, #20]
800521e: 431a orrs r2, r3
8005220: 68bb ldr r3, [r7, #8]
8005222: 01db lsls r3, r3, #7
8005224: 440b add r3, r1
8005226: 33b8 adds r3, #184 @ 0xb8
8005228: 601a str r2, [r3, #0]
HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_DTF |
HRTIM_DTR_SDTF | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK), hrtim_dtr);
hhrtim->State = HAL_HRTIM_STATE_READY;
800522a: 68fb ldr r3, [r7, #12]
800522c: 2201 movs r2, #1
800522e: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
8005232: 68fb ldr r3, [r7, #12]
8005234: 2200 movs r2, #0
8005236: f883 20dc strb.w r2, [r3, #220] @ 0xdc
return HAL_OK;
800523a: 2300 movs r3, #0
}
800523c: 4618 mov r0, r3
800523e: 371c adds r7, #28
8005240: 46bd mov sp, r7
8005242: f85d 7b04 ldr.w r7, [sp], #4
8005246: 4770 bx lr
8005248: 01ff0000 .word 0x01ff0000
800524c: 3c002000 .word 0x3c002000
08005250 <HAL_HRTIM_WaveformCompareConfig>:
*/
HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t CompareUnit,
const HRTIM_CompareCfgTypeDef *pCompareCfg)
{
8005250: b480 push {r7}
8005252: b085 sub sp, #20
8005254: af00 add r7, sp, #0
8005256: 60f8 str r0, [r7, #12]
8005258: 60b9 str r1, [r7, #8]
800525a: 607a str r2, [r7, #4]
800525c: 603b str r3, [r7, #0]
/* Check parameters */
assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
800525e: 68fb ldr r3, [r7, #12]
8005260: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd
8005264: b2db uxtb r3, r3
8005266: 2b02 cmp r3, #2
8005268: d101 bne.n 800526e <HAL_HRTIM_WaveformCompareConfig+0x1e>
{
return HAL_BUSY;
800526a: 2302 movs r3, #2
800526c: e157 b.n 800551e <HAL_HRTIM_WaveformCompareConfig+0x2ce>
}
/* Process Locked */
__HAL_LOCK(hhrtim);
800526e: 68fb ldr r3, [r7, #12]
8005270: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc
8005274: 2b01 cmp r3, #1
8005276: d101 bne.n 800527c <HAL_HRTIM_WaveformCompareConfig+0x2c>
8005278: 2302 movs r3, #2
800527a: e150 b.n 800551e <HAL_HRTIM_WaveformCompareConfig+0x2ce>
800527c: 68fb ldr r3, [r7, #12]
800527e: 2201 movs r2, #1
8005280: f883 20dc strb.w r2, [r3, #220] @ 0xdc
hhrtim->State = HAL_HRTIM_STATE_BUSY;
8005284: 68fb ldr r3, [r7, #12]
8005286: 2202 movs r2, #2
8005288: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Configure the compare unit */
if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
800528c: 68bb ldr r3, [r7, #8]
800528e: 2b06 cmp r3, #6
8005290: d140 bne.n 8005314 <HAL_HRTIM_WaveformCompareConfig+0xc4>
{
switch (CompareUnit)
8005292: 687b ldr r3, [r7, #4]
8005294: 3b01 subs r3, #1
8005296: 2b07 cmp r3, #7
8005298: d82a bhi.n 80052f0 <HAL_HRTIM_WaveformCompareConfig+0xa0>
800529a: a201 add r2, pc, #4 @ (adr r2, 80052a0 <HAL_HRTIM_WaveformCompareConfig+0x50>)
800529c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80052a0: 080052c1 .word 0x080052c1
80052a4: 080052cd .word 0x080052cd
80052a8: 080052f1 .word 0x080052f1
80052ac: 080052d9 .word 0x080052d9
80052b0: 080052f1 .word 0x080052f1
80052b4: 080052f1 .word 0x080052f1
80052b8: 080052f1 .word 0x080052f1
80052bc: 080052e5 .word 0x080052e5
{
case HRTIM_COMPAREUNIT_1:
{
hhrtim->Instance->sMasterRegs.MCMP1R = pCompareCfg->CompareValue;
80052c0: 68fb ldr r3, [r7, #12]
80052c2: 681b ldr r3, [r3, #0]
80052c4: 683a ldr r2, [r7, #0]
80052c6: 6812 ldr r2, [r2, #0]
80052c8: 61da str r2, [r3, #28]
break;
80052ca: e01a b.n 8005302 <HAL_HRTIM_WaveformCompareConfig+0xb2>
}
case HRTIM_COMPAREUNIT_2:
{
hhrtim->Instance->sMasterRegs.MCMP2R = pCompareCfg->CompareValue;
80052cc: 68fb ldr r3, [r7, #12]
80052ce: 681b ldr r3, [r3, #0]
80052d0: 683a ldr r2, [r7, #0]
80052d2: 6812 ldr r2, [r2, #0]
80052d4: 625a str r2, [r3, #36] @ 0x24
break;
80052d6: e014 b.n 8005302 <HAL_HRTIM_WaveformCompareConfig+0xb2>
}
case HRTIM_COMPAREUNIT_3:
{
hhrtim->Instance->sMasterRegs.MCMP3R = pCompareCfg->CompareValue;
80052d8: 68fb ldr r3, [r7, #12]
80052da: 681b ldr r3, [r3, #0]
80052dc: 683a ldr r2, [r7, #0]
80052de: 6812 ldr r2, [r2, #0]
80052e0: 629a str r2, [r3, #40] @ 0x28
break;
80052e2: e00e b.n 8005302 <HAL_HRTIM_WaveformCompareConfig+0xb2>
}
case HRTIM_COMPAREUNIT_4:
{
hhrtim->Instance->sMasterRegs.MCMP4R = pCompareCfg->CompareValue;
80052e4: 68fb ldr r3, [r7, #12]
80052e6: 681b ldr r3, [r3, #0]
80052e8: 683a ldr r2, [r7, #0]
80052ea: 6812 ldr r2, [r2, #0]
80052ec: 62da str r2, [r3, #44] @ 0x2c
break;
80052ee: e008 b.n 8005302 <HAL_HRTIM_WaveformCompareConfig+0xb2>
}
default:
{
hhrtim->State = HAL_HRTIM_STATE_ERROR;
80052f0: 68fb ldr r3, [r7, #12]
80052f2: 2207 movs r2, #7
80052f4: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
80052f8: 68fb ldr r3, [r7, #12]
80052fa: 2200 movs r2, #0
80052fc: f883 20dc strb.w r2, [r3, #220] @ 0xdc
break;
8005300: bf00 nop
}
}
if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
8005302: 68fb ldr r3, [r7, #12]
8005304: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd
8005308: b2db uxtb r3, r3
800530a: 2b07 cmp r3, #7
800530c: f040 80fe bne.w 800550c <HAL_HRTIM_WaveformCompareConfig+0x2bc>
{
return HAL_ERROR;
8005310: 2301 movs r3, #1
8005312: e104 b.n 800551e <HAL_HRTIM_WaveformCompareConfig+0x2ce>
}
}
else
{
switch (CompareUnit)
8005314: 687b ldr r3, [r7, #4]
8005316: 3b01 subs r3, #1
8005318: 2b07 cmp r3, #7
800531a: f200 80e3 bhi.w 80054e4 <HAL_HRTIM_WaveformCompareConfig+0x294>
800531e: a201 add r2, pc, #4 @ (adr r2, 8005324 <HAL_HRTIM_WaveformCompareConfig+0xd4>)
8005320: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005324: 08005345 .word 0x08005345
8005328: 08005359 .word 0x08005359
800532c: 080054e5 .word 0x080054e5
8005330: 08005415 .word 0x08005415
8005334: 080054e5 .word 0x080054e5
8005338: 080054e5 .word 0x080054e5
800533c: 080054e5 .word 0x080054e5
8005340: 08005429 .word 0x08005429
{
case HRTIM_COMPAREUNIT_1:
{
/* Set the compare value */
hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
8005344: 68fb ldr r3, [r7, #12]
8005346: 6819 ldr r1, [r3, #0]
8005348: 683b ldr r3, [r7, #0]
800534a: 681a ldr r2, [r3, #0]
800534c: 68bb ldr r3, [r7, #8]
800534e: 01db lsls r3, r3, #7
8005350: 440b add r3, r1
8005352: 339c adds r3, #156 @ 0x9c
8005354: 601a str r2, [r3, #0]
break;
8005356: e0d1 b.n 80054fc <HAL_HRTIM_WaveformCompareConfig+0x2ac>
{
/* Check parameters */
assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
/* Set the compare value */
hhrtim->Instance->sTimerxRegs[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
8005358: 68fb ldr r3, [r7, #12]
800535a: 6819 ldr r1, [r3, #0]
800535c: 683b ldr r3, [r7, #0]
800535e: 681a ldr r2, [r3, #0]
8005360: 68bb ldr r3, [r7, #8]
8005362: 01db lsls r3, r3, #7
8005364: 440b add r3, r1
8005366: 33a4 adds r3, #164 @ 0xa4
8005368: 601a str r2, [r3, #0]
if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
800536a: 683b ldr r3, [r7, #0]
800536c: 685b ldr r3, [r3, #4]
800536e: 2b00 cmp r3, #0
8005370: d03f beq.n 80053f2 <HAL_HRTIM_WaveformCompareConfig+0x1a2>
{
/* Configure auto-delayed mode */
/* DELCMP2 bitfield must be reset when reprogrammed from one value */
/* to the other to reinitialize properly the auto-delayed mechanism */
hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP2;
8005372: 68fb ldr r3, [r7, #12]
8005374: 681a ldr r2, [r3, #0]
8005376: 68bb ldr r3, [r7, #8]
8005378: 3301 adds r3, #1
800537a: 01db lsls r3, r3, #7
800537c: 4413 add r3, r2
800537e: 681b ldr r3, [r3, #0]
8005380: 68fa ldr r2, [r7, #12]
8005382: 6811 ldr r1, [r2, #0]
8005384: f423 5240 bic.w r2, r3, #12288 @ 0x3000
8005388: 68bb ldr r3, [r7, #8]
800538a: 3301 adds r3, #1
800538c: 01db lsls r3, r3, #7
800538e: 440b add r3, r1
8005390: 601a str r2, [r3, #0]
hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= pCompareCfg->AutoDelayedMode;
8005392: 68fb ldr r3, [r7, #12]
8005394: 681a ldr r2, [r3, #0]
8005396: 68bb ldr r3, [r7, #8]
8005398: 3301 adds r3, #1
800539a: 01db lsls r3, r3, #7
800539c: 4413 add r3, r2
800539e: 681a ldr r2, [r3, #0]
80053a0: 683b ldr r3, [r7, #0]
80053a2: 685b ldr r3, [r3, #4]
80053a4: 68f9 ldr r1, [r7, #12]
80053a6: 6809 ldr r1, [r1, #0]
80053a8: 431a orrs r2, r3
80053aa: 68bb ldr r3, [r7, #8]
80053ac: 3301 adds r3, #1
80053ae: 01db lsls r3, r3, #7
80053b0: 440b add r3, r1
80053b2: 601a str r2, [r3, #0]
/* Set the compare value for timeout compare unit (if any) */
if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
80053b4: 683b ldr r3, [r7, #0]
80053b6: 685b ldr r3, [r3, #4]
80053b8: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
80053bc: d109 bne.n 80053d2 <HAL_HRTIM_WaveformCompareConfig+0x182>
{
hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
80053be: 68fb ldr r3, [r7, #12]
80053c0: 6819 ldr r1, [r3, #0]
80053c2: 683b ldr r3, [r7, #0]
80053c4: 689a ldr r2, [r3, #8]
80053c6: 68bb ldr r3, [r7, #8]
80053c8: 01db lsls r3, r3, #7
80053ca: 440b add r3, r1
80053cc: 339c adds r3, #156 @ 0x9c
80053ce: 601a str r2, [r3, #0]
else
{
/* Clear HRTIM_TIMxCR.DELCMP2 bitfield */
MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
}
break;
80053d0: e091 b.n 80054f6 <HAL_HRTIM_WaveformCompareConfig+0x2a6>
else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
80053d2: 683b ldr r3, [r7, #0]
80053d4: 685b ldr r3, [r3, #4]
80053d6: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
80053da: f040 808c bne.w 80054f6 <HAL_HRTIM_WaveformCompareConfig+0x2a6>
hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
80053de: 68fb ldr r3, [r7, #12]
80053e0: 6819 ldr r1, [r3, #0]
80053e2: 683b ldr r3, [r7, #0]
80053e4: 689a ldr r2, [r3, #8]
80053e6: 68bb ldr r3, [r7, #8]
80053e8: 01db lsls r3, r3, #7
80053ea: 440b add r3, r1
80053ec: 33a8 adds r3, #168 @ 0xa8
80053ee: 601a str r2, [r3, #0]
break;
80053f0: e081 b.n 80054f6 <HAL_HRTIM_WaveformCompareConfig+0x2a6>
MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP2, 0U);
80053f2: 68fb ldr r3, [r7, #12]
80053f4: 681a ldr r2, [r3, #0]
80053f6: 68bb ldr r3, [r7, #8]
80053f8: 3301 adds r3, #1
80053fa: 01db lsls r3, r3, #7
80053fc: 4413 add r3, r2
80053fe: 681b ldr r3, [r3, #0]
8005400: 68fa ldr r2, [r7, #12]
8005402: 6811 ldr r1, [r2, #0]
8005404: f423 5240 bic.w r2, r3, #12288 @ 0x3000
8005408: 68bb ldr r3, [r7, #8]
800540a: 3301 adds r3, #1
800540c: 01db lsls r3, r3, #7
800540e: 440b add r3, r1
8005410: 601a str r2, [r3, #0]
break;
8005412: e070 b.n 80054f6 <HAL_HRTIM_WaveformCompareConfig+0x2a6>
}
case HRTIM_COMPAREUNIT_3:
{
/* Set the compare value */
hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
8005414: 68fb ldr r3, [r7, #12]
8005416: 6819 ldr r1, [r3, #0]
8005418: 683b ldr r3, [r7, #0]
800541a: 681a ldr r2, [r3, #0]
800541c: 68bb ldr r3, [r7, #8]
800541e: 01db lsls r3, r3, #7
8005420: 440b add r3, r1
8005422: 33a8 adds r3, #168 @ 0xa8
8005424: 601a str r2, [r3, #0]
break;
8005426: e069 b.n 80054fc <HAL_HRTIM_WaveformCompareConfig+0x2ac>
{
/* Check parameters */
assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
/* Set the compare value */
hhrtim->Instance->sTimerxRegs[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
8005428: 68fb ldr r3, [r7, #12]
800542a: 6819 ldr r1, [r3, #0]
800542c: 683b ldr r3, [r7, #0]
800542e: 681a ldr r2, [r3, #0]
8005430: 68bb ldr r3, [r7, #8]
8005432: 01db lsls r3, r3, #7
8005434: 440b add r3, r1
8005436: 33ac adds r3, #172 @ 0xac
8005438: 601a str r2, [r3, #0]
if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
800543a: 683b ldr r3, [r7, #0]
800543c: 685b ldr r3, [r3, #4]
800543e: 2b00 cmp r3, #0
8005440: d03f beq.n 80054c2 <HAL_HRTIM_WaveformCompareConfig+0x272>
{
/* Configure auto-delayed mode */
/* DELCMP4 bitfield must be reset when reprogrammed from one value */
/* to the other to reinitialize properly the auto-delayed mechanism */
hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~HRTIM_TIMCR_DELCMP4;
8005442: 68fb ldr r3, [r7, #12]
8005444: 681a ldr r2, [r3, #0]
8005446: 68bb ldr r3, [r7, #8]
8005448: 3301 adds r3, #1
800544a: 01db lsls r3, r3, #7
800544c: 4413 add r3, r2
800544e: 681b ldr r3, [r3, #0]
8005450: 68fa ldr r2, [r7, #12]
8005452: 6811 ldr r1, [r2, #0]
8005454: f423 4240 bic.w r2, r3, #49152 @ 0xc000
8005458: 68bb ldr r3, [r7, #8]
800545a: 3301 adds r3, #1
800545c: 01db lsls r3, r3, #7
800545e: 440b add r3, r1
8005460: 601a str r2, [r3, #0]
hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR |= (pCompareCfg->AutoDelayedMode << 2U);
8005462: 68fb ldr r3, [r7, #12]
8005464: 681a ldr r2, [r3, #0]
8005466: 68bb ldr r3, [r7, #8]
8005468: 3301 adds r3, #1
800546a: 01db lsls r3, r3, #7
800546c: 4413 add r3, r2
800546e: 681a ldr r2, [r3, #0]
8005470: 683b ldr r3, [r7, #0]
8005472: 685b ldr r3, [r3, #4]
8005474: 009b lsls r3, r3, #2
8005476: 68f9 ldr r1, [r7, #12]
8005478: 6809 ldr r1, [r1, #0]
800547a: 431a orrs r2, r3
800547c: 68bb ldr r3, [r7, #8]
800547e: 3301 adds r3, #1
8005480: 01db lsls r3, r3, #7
8005482: 440b add r3, r1
8005484: 601a str r2, [r3, #0]
/* Set the compare value for timeout compare unit (if any) */
if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
8005486: 683b ldr r3, [r7, #0]
8005488: 685b ldr r3, [r3, #4]
800548a: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
800548e: d109 bne.n 80054a4 <HAL_HRTIM_WaveformCompareConfig+0x254>
{
hhrtim->Instance->sTimerxRegs[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
8005490: 68fb ldr r3, [r7, #12]
8005492: 6819 ldr r1, [r3, #0]
8005494: 683b ldr r3, [r7, #0]
8005496: 689a ldr r2, [r3, #8]
8005498: 68bb ldr r3, [r7, #8]
800549a: 01db lsls r3, r3, #7
800549c: 440b add r3, r1
800549e: 339c adds r3, #156 @ 0x9c
80054a0: 601a str r2, [r3, #0]
else
{
/* Clear HRTIM_TIMxCR.DELCMP4 bitfield */
MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
}
break;
80054a2: e02a b.n 80054fa <HAL_HRTIM_WaveformCompareConfig+0x2aa>
else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
80054a4: 683b ldr r3, [r7, #0]
80054a6: 685b ldr r3, [r3, #4]
80054a8: f5b3 5f40 cmp.w r3, #12288 @ 0x3000
80054ac: d125 bne.n 80054fa <HAL_HRTIM_WaveformCompareConfig+0x2aa>
hhrtim->Instance->sTimerxRegs[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
80054ae: 68fb ldr r3, [r7, #12]
80054b0: 6819 ldr r1, [r3, #0]
80054b2: 683b ldr r3, [r7, #0]
80054b4: 689a ldr r2, [r3, #8]
80054b6: 68bb ldr r3, [r7, #8]
80054b8: 01db lsls r3, r3, #7
80054ba: 440b add r3, r1
80054bc: 33a8 adds r3, #168 @ 0xa8
80054be: 601a str r2, [r3, #0]
break;
80054c0: e01b b.n 80054fa <HAL_HRTIM_WaveformCompareConfig+0x2aa>
MODIFY_REG(hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR, HRTIM_TIMCR_DELCMP4, 0U);
80054c2: 68fb ldr r3, [r7, #12]
80054c4: 681a ldr r2, [r3, #0]
80054c6: 68bb ldr r3, [r7, #8]
80054c8: 3301 adds r3, #1
80054ca: 01db lsls r3, r3, #7
80054cc: 4413 add r3, r2
80054ce: 681b ldr r3, [r3, #0]
80054d0: 68fa ldr r2, [r7, #12]
80054d2: 6811 ldr r1, [r2, #0]
80054d4: f423 4240 bic.w r2, r3, #49152 @ 0xc000
80054d8: 68bb ldr r3, [r7, #8]
80054da: 3301 adds r3, #1
80054dc: 01db lsls r3, r3, #7
80054de: 440b add r3, r1
80054e0: 601a str r2, [r3, #0]
break;
80054e2: e00a b.n 80054fa <HAL_HRTIM_WaveformCompareConfig+0x2aa>
}
default:
{
hhrtim->State = HAL_HRTIM_STATE_ERROR;
80054e4: 68fb ldr r3, [r7, #12]
80054e6: 2207 movs r2, #7
80054e8: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
80054ec: 68fb ldr r3, [r7, #12]
80054ee: 2200 movs r2, #0
80054f0: f883 20dc strb.w r2, [r3, #220] @ 0xdc
break;
80054f4: e002 b.n 80054fc <HAL_HRTIM_WaveformCompareConfig+0x2ac>
break;
80054f6: bf00 nop
80054f8: e000 b.n 80054fc <HAL_HRTIM_WaveformCompareConfig+0x2ac>
break;
80054fa: bf00 nop
}
}
if (hhrtim->State == HAL_HRTIM_STATE_ERROR)
80054fc: 68fb ldr r3, [r7, #12]
80054fe: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd
8005502: b2db uxtb r3, r3
8005504: 2b07 cmp r3, #7
8005506: d101 bne.n 800550c <HAL_HRTIM_WaveformCompareConfig+0x2bc>
{
return HAL_ERROR;
8005508: 2301 movs r3, #1
800550a: e008 b.n 800551e <HAL_HRTIM_WaveformCompareConfig+0x2ce>
}
}
hhrtim->State = HAL_HRTIM_STATE_READY;
800550c: 68fb ldr r3, [r7, #12]
800550e: 2201 movs r2, #1
8005510: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
8005514: 68fb ldr r3, [r7, #12]
8005516: 2200 movs r2, #0
8005518: f883 20dc strb.w r2, [r3, #220] @ 0xdc
return HAL_OK;
800551c: 2300 movs r3, #0
}
800551e: 4618 mov r0, r3
8005520: 3714 adds r7, #20
8005522: 46bd mov sp, r7
8005524: f85d 7b04 ldr.w r7, [sp], #4
8005528: 4770 bx lr
800552a: bf00 nop
0800552c <HAL_HRTIM_WaveformOutputConfig>:
*/
HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t Output,
const HRTIM_OutputCfgTypeDef *pOutputCfg)
{
800552c: b580 push {r7, lr}
800552e: b084 sub sp, #16
8005530: af00 add r7, sp, #0
8005532: 60f8 str r0, [r7, #12]
8005534: 60b9 str r1, [r7, #8]
8005536: 607a str r2, [r7, #4]
8005538: 603b str r3, [r7, #0]
assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
assert_param(IS_HRTIM_OUTPUTFAULTLEVEL(pOutputCfg->FaultLevel));
assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
if (hhrtim->State == HAL_HRTIM_STATE_BUSY)
800553a: 68fb ldr r3, [r7, #12]
800553c: f893 30dd ldrb.w r3, [r3, #221] @ 0xdd
8005540: b2db uxtb r3, r3
8005542: 2b02 cmp r3, #2
8005544: d101 bne.n 800554a <HAL_HRTIM_WaveformOutputConfig+0x1e>
{
return HAL_BUSY;
8005546: 2302 movs r3, #2
8005548: e01d b.n 8005586 <HAL_HRTIM_WaveformOutputConfig+0x5a>
}
/* Process Locked */
__HAL_LOCK(hhrtim);
800554a: 68fb ldr r3, [r7, #12]
800554c: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc
8005550: 2b01 cmp r3, #1
8005552: d101 bne.n 8005558 <HAL_HRTIM_WaveformOutputConfig+0x2c>
8005554: 2302 movs r3, #2
8005556: e016 b.n 8005586 <HAL_HRTIM_WaveformOutputConfig+0x5a>
8005558: 68fb ldr r3, [r7, #12]
800555a: 2201 movs r2, #1
800555c: f883 20dc strb.w r2, [r3, #220] @ 0xdc
hhrtim->State = HAL_HRTIM_STATE_BUSY;
8005560: 68fb ldr r3, [r7, #12]
8005562: 2202 movs r2, #2
8005564: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Configure the timer output */
HRTIM_OutputConfig(hhrtim,
8005568: 683b ldr r3, [r7, #0]
800556a: 687a ldr r2, [r7, #4]
800556c: 68b9 ldr r1, [r7, #8]
800556e: 68f8 ldr r0, [r7, #12]
8005570: f000 fb84 bl 8005c7c <HRTIM_OutputConfig>
TimerIdx,
Output,
pOutputCfg);
hhrtim->State = HAL_HRTIM_STATE_READY;
8005574: 68fb ldr r3, [r7, #12]
8005576: 2201 movs r2, #1
8005578: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
800557c: 68fb ldr r3, [r7, #12]
800557e: 2200 movs r2, #0
8005580: f883 20dc strb.w r2, [r3, #220] @ 0xdc
return HAL_OK;
8005584: 2300 movs r3, #0
}
8005586: 4618 mov r0, r3
8005588: 3710 adds r7, #16
800558a: 46bd mov sp, r7
800558c: bd80 pop {r7, pc}
0800558e <HAL_HRTIM_WaveformOutputStart>:
* @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,
uint32_t OutputsToStart)
{
800558e: b480 push {r7}
8005590: b083 sub sp, #12
8005592: af00 add r7, sp, #0
8005594: 6078 str r0, [r7, #4]
8005596: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_HRTIM_OUTPUT(OutputsToStart));
/* Process Locked */
__HAL_LOCK(hhrtim);
8005598: 687b ldr r3, [r7, #4]
800559a: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc
800559e: 2b01 cmp r3, #1
80055a0: d101 bne.n 80055a6 <HAL_HRTIM_WaveformOutputStart+0x18>
80055a2: 2302 movs r3, #2
80055a4: e01a b.n 80055dc <HAL_HRTIM_WaveformOutputStart+0x4e>
80055a6: 687b ldr r3, [r7, #4]
80055a8: 2201 movs r2, #1
80055aa: f883 20dc strb.w r2, [r3, #220] @ 0xdc
hhrtim->State = HAL_HRTIM_STATE_BUSY;
80055ae: 687b ldr r3, [r7, #4]
80055b0: 2202 movs r2, #2
80055b2: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Enable the HRTIM outputs */
hhrtim->Instance->sCommonRegs.OENR |= (OutputsToStart);
80055b6: 687b ldr r3, [r7, #4]
80055b8: 681b ldr r3, [r3, #0]
80055ba: f8d3 1394 ldr.w r1, [r3, #916] @ 0x394
80055be: 687b ldr r3, [r7, #4]
80055c0: 681b ldr r3, [r3, #0]
80055c2: 683a ldr r2, [r7, #0]
80055c4: 430a orrs r2, r1
80055c6: f8c3 2394 str.w r2, [r3, #916] @ 0x394
hhrtim->State = HAL_HRTIM_STATE_READY;
80055ca: 687b ldr r3, [r7, #4]
80055cc: 2201 movs r2, #1
80055ce: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
80055d2: 687b ldr r3, [r7, #4]
80055d4: 2200 movs r2, #0
80055d6: f883 20dc strb.w r2, [r3, #220] @ 0xdc
return HAL_OK;
80055da: 2300 movs r3, #0
}
80055dc: 4618 mov r0, r3
80055de: 370c adds r7, #12
80055e0: 46bd mov sp, r7
80055e2: f85d 7b04 ldr.w r7, [sp], #4
80055e6: 4770 bx lr
080055e8 <HAL_HRTIM_WaveformOutputStop>:
* @arg HRTIM_OUTPUT_TF2: Timer F - Output 2
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,
uint32_t OutputsToStop)
{
80055e8: b480 push {r7}
80055ea: b083 sub sp, #12
80055ec: af00 add r7, sp, #0
80055ee: 6078 str r0, [r7, #4]
80055f0: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_HRTIM_OUTPUT(OutputsToStop));
/* Process Locked */
__HAL_LOCK(hhrtim);
80055f2: 687b ldr r3, [r7, #4]
80055f4: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc
80055f8: 2b01 cmp r3, #1
80055fa: d101 bne.n 8005600 <HAL_HRTIM_WaveformOutputStop+0x18>
80055fc: 2302 movs r3, #2
80055fe: e01a b.n 8005636 <HAL_HRTIM_WaveformOutputStop+0x4e>
8005600: 687b ldr r3, [r7, #4]
8005602: 2201 movs r2, #1
8005604: f883 20dc strb.w r2, [r3, #220] @ 0xdc
hhrtim->State = HAL_HRTIM_STATE_BUSY;
8005608: 687b ldr r3, [r7, #4]
800560a: 2202 movs r2, #2
800560c: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Enable the HRTIM outputs */
hhrtim->Instance->sCommonRegs.ODISR |= (OutputsToStop);
8005610: 687b ldr r3, [r7, #4]
8005612: 681b ldr r3, [r3, #0]
8005614: f8d3 1398 ldr.w r1, [r3, #920] @ 0x398
8005618: 687b ldr r3, [r7, #4]
800561a: 681b ldr r3, [r3, #0]
800561c: 683a ldr r2, [r7, #0]
800561e: 430a orrs r2, r1
8005620: f8c3 2398 str.w r2, [r3, #920] @ 0x398
hhrtim->State = HAL_HRTIM_STATE_READY;
8005624: 687b ldr r3, [r7, #4]
8005626: 2201 movs r2, #1
8005628: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
800562c: 687b ldr r3, [r7, #4]
800562e: 2200 movs r2, #0
8005630: f883 20dc strb.w r2, [r3, #220] @ 0xdc
return HAL_OK;
8005634: 2300 movs r3, #0
}
8005636: 4618 mov r0, r3
8005638: 370c adds r7, #12
800563a: 46bd mov sp, r7
800563c: f85d 7b04 ldr.w r7, [sp], #4
8005640: 4770 bx lr
08005642 <HAL_HRTIM_WaveformCountStart>:
* @arg HRTIM_TIMERID_TIMER_F
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim,
uint32_t Timers)
{
8005642: b480 push {r7}
8005644: b083 sub sp, #12
8005646: af00 add r7, sp, #0
8005648: 6078 str r0, [r7, #4]
800564a: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_HRTIM_TIMERID(Timers));
/* Process Locked */
__HAL_LOCK(hhrtim);
800564c: 687b ldr r3, [r7, #4]
800564e: f893 30dc ldrb.w r3, [r3, #220] @ 0xdc
8005652: 2b01 cmp r3, #1
8005654: d101 bne.n 800565a <HAL_HRTIM_WaveformCountStart+0x18>
8005656: 2302 movs r3, #2
8005658: e018 b.n 800568c <HAL_HRTIM_WaveformCountStart+0x4a>
800565a: 687b ldr r3, [r7, #4]
800565c: 2201 movs r2, #1
800565e: f883 20dc strb.w r2, [r3, #220] @ 0xdc
hhrtim->State = HAL_HRTIM_STATE_BUSY;
8005662: 687b ldr r3, [r7, #4]
8005664: 2202 movs r2, #2
8005666: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Enable timer(s) counter */
hhrtim->Instance->sMasterRegs.MCR |= (Timers);
800566a: 687b ldr r3, [r7, #4]
800566c: 681b ldr r3, [r3, #0]
800566e: 6819 ldr r1, [r3, #0]
8005670: 687b ldr r3, [r7, #4]
8005672: 681b ldr r3, [r3, #0]
8005674: 683a ldr r2, [r7, #0]
8005676: 430a orrs r2, r1
8005678: 601a str r2, [r3, #0]
hhrtim->State = HAL_HRTIM_STATE_READY;
800567a: 687b ldr r3, [r7, #4]
800567c: 2201 movs r2, #1
800567e: f883 20dd strb.w r2, [r3, #221] @ 0xdd
/* Process Unlocked */
__HAL_UNLOCK(hhrtim);
8005682: 687b ldr r3, [r7, #4]
8005684: 2200 movs r2, #0
8005686: f883 20dc strb.w r2, [r3, #220] @ 0xdc
return HAL_OK;
800568a: 2300 movs r3, #0
}
800568c: 4618 mov r0, r3
800568e: 370c adds r7, #12
8005690: 46bd mov sp, r7
8005692: f85d 7b04 ldr.w r7, [sp], #4
8005696: 4770 bx lr
08005698 <HRTIM_MasterBase_Config>:
* @param pTimeBaseCfg pointer to the time base configuration structure
* @retval None
*/
static void HRTIM_MasterBase_Config(HRTIM_HandleTypeDef *hhrtim,
const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
{
8005698: b480 push {r7}
800569a: b085 sub sp, #20
800569c: af00 add r7, sp, #0
800569e: 6078 str r0, [r7, #4]
80056a0: 6039 str r1, [r7, #0]
uint32_t hrtim_mcr;
/* Configure master timer */
hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
80056a2: 687b ldr r3, [r7, #4]
80056a4: 681b ldr r3, [r3, #0]
80056a6: 681b ldr r3, [r3, #0]
80056a8: 60fb str r3, [r7, #12]
/* Set the prescaler ratio */
hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
80056aa: 68fb ldr r3, [r7, #12]
80056ac: f023 0307 bic.w r3, r3, #7
80056b0: 60fb str r3, [r7, #12]
hrtim_mcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
80056b2: 683b ldr r3, [r7, #0]
80056b4: 689b ldr r3, [r3, #8]
80056b6: 68fa ldr r2, [r7, #12]
80056b8: 4313 orrs r3, r2
80056ba: 60fb str r3, [r7, #12]
/* Set the operating mode */
hrtim_mcr &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
80056bc: 68fb ldr r3, [r7, #12]
80056be: f023 0318 bic.w r3, r3, #24
80056c2: 60fb str r3, [r7, #12]
hrtim_mcr |= (uint32_t)pTimeBaseCfg->Mode;
80056c4: 683b ldr r3, [r7, #0]
80056c6: 68db ldr r3, [r3, #12]
80056c8: 68fa ldr r2, [r7, #12]
80056ca: 4313 orrs r3, r2
80056cc: 60fb str r3, [r7, #12]
/* Update the HRTIM registers */
hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
80056ce: 687b ldr r3, [r7, #4]
80056d0: 681b ldr r3, [r3, #0]
80056d2: 68fa ldr r2, [r7, #12]
80056d4: 601a str r2, [r3, #0]
hhrtim->Instance->sMasterRegs.MPER = pTimeBaseCfg->Period;
80056d6: 687b ldr r3, [r7, #4]
80056d8: 681b ldr r3, [r3, #0]
80056da: 683a ldr r2, [r7, #0]
80056dc: 6812 ldr r2, [r2, #0]
80056de: 615a str r2, [r3, #20]
hhrtim->Instance->sMasterRegs.MREP = pTimeBaseCfg->RepetitionCounter;
80056e0: 687b ldr r3, [r7, #4]
80056e2: 681b ldr r3, [r3, #0]
80056e4: 683a ldr r2, [r7, #0]
80056e6: 6852 ldr r2, [r2, #4]
80056e8: 619a str r2, [r3, #24]
}
80056ea: bf00 nop
80056ec: 3714 adds r7, #20
80056ee: 46bd mov sp, r7
80056f0: f85d 7b04 ldr.w r7, [sp], #4
80056f4: 4770 bx lr
080056f6 <HRTIM_TimingUnitBase_Config>:
* @retval None
*/
static void HRTIM_TimingUnitBase_Config(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
const HRTIM_TimeBaseCfgTypeDef *pTimeBaseCfg)
{
80056f6: b480 push {r7}
80056f8: b087 sub sp, #28
80056fa: af00 add r7, sp, #0
80056fc: 60f8 str r0, [r7, #12]
80056fe: 60b9 str r1, [r7, #8]
8005700: 607a str r2, [r7, #4]
uint32_t hrtim_timcr;
/* Configure master timing unit */
hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
8005702: 68fb ldr r3, [r7, #12]
8005704: 681a ldr r2, [r3, #0]
8005706: 68bb ldr r3, [r7, #8]
8005708: 3301 adds r3, #1
800570a: 01db lsls r3, r3, #7
800570c: 4413 add r3, r2
800570e: 681b ldr r3, [r3, #0]
8005710: 617b str r3, [r7, #20]
/* Set the prescaler ratio */
hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
8005712: 697b ldr r3, [r7, #20]
8005714: f023 0307 bic.w r3, r3, #7
8005718: 617b str r3, [r7, #20]
hrtim_timcr |= (uint32_t)pTimeBaseCfg->PrescalerRatio;
800571a: 687b ldr r3, [r7, #4]
800571c: 689b ldr r3, [r3, #8]
800571e: 697a ldr r2, [r7, #20]
8005720: 4313 orrs r3, r2
8005722: 617b str r3, [r7, #20]
/* Set the operating mode */
hrtim_timcr &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
8005724: 697b ldr r3, [r7, #20]
8005726: f023 0318 bic.w r3, r3, #24
800572a: 617b str r3, [r7, #20]
hrtim_timcr |= (uint32_t)pTimeBaseCfg->Mode;
800572c: 687b ldr r3, [r7, #4]
800572e: 68db ldr r3, [r3, #12]
8005730: 697a ldr r2, [r7, #20]
8005732: 4313 orrs r3, r2
8005734: 617b str r3, [r7, #20]
/* Update the HRTIM registers */
hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
8005736: 68fb ldr r3, [r7, #12]
8005738: 681a ldr r2, [r3, #0]
800573a: 68bb ldr r3, [r7, #8]
800573c: 3301 adds r3, #1
800573e: 01db lsls r3, r3, #7
8005740: 4413 add r3, r2
8005742: 697a ldr r2, [r7, #20]
8005744: 601a str r2, [r3, #0]
hhrtim->Instance->sTimerxRegs[TimerIdx].PERxR = pTimeBaseCfg->Period;
8005746: 68fb ldr r3, [r7, #12]
8005748: 6819 ldr r1, [r3, #0]
800574a: 687b ldr r3, [r7, #4]
800574c: 681a ldr r2, [r3, #0]
800574e: 68bb ldr r3, [r7, #8]
8005750: 01db lsls r3, r3, #7
8005752: 440b add r3, r1
8005754: 3394 adds r3, #148 @ 0x94
8005756: 601a str r2, [r3, #0]
hhrtim->Instance->sTimerxRegs[TimerIdx].REPxR = pTimeBaseCfg->RepetitionCounter;
8005758: 68fb ldr r3, [r7, #12]
800575a: 6819 ldr r1, [r3, #0]
800575c: 687b ldr r3, [r7, #4]
800575e: 685a ldr r2, [r3, #4]
8005760: 68bb ldr r3, [r7, #8]
8005762: 01db lsls r3, r3, #7
8005764: 440b add r3, r1
8005766: 3398 adds r3, #152 @ 0x98
8005768: 601a str r2, [r3, #0]
}
800576a: bf00 nop
800576c: 371c adds r7, #28
800576e: 46bd mov sp, r7
8005770: f85d 7b04 ldr.w r7, [sp], #4
8005774: 4770 bx lr
08005776 <HRTIM_MasterWaveform_Config>:
* @param pTimerCfg pointer to the timer configuration data structure
* @retval None
*/
static void HRTIM_MasterWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
const HRTIM_TimerCfgTypeDef *pTimerCfg)
{
8005776: b480 push {r7}
8005778: b085 sub sp, #20
800577a: af00 add r7, sp, #0
800577c: 6078 str r0, [r7, #4]
800577e: 6039 str r1, [r7, #0]
uint32_t hrtim_mcr;
uint32_t hrtim_bmcr;
/* Configure master timer */
hrtim_mcr = hhrtim->Instance->sMasterRegs.MCR;
8005780: 687b ldr r3, [r7, #4]
8005782: 681b ldr r3, [r3, #0]
8005784: 681b ldr r3, [r3, #0]
8005786: 60fb str r3, [r7, #12]
hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
8005788: 687b ldr r3, [r7, #4]
800578a: 681b ldr r3, [r3, #0]
800578c: f8d3 33a0 ldr.w r3, [r3, #928] @ 0x3a0
8005790: 60bb str r3, [r7, #8]
/* Enable/Disable the half mode */
hrtim_mcr &= ~(HRTIM_MCR_HALF);
8005792: 68fb ldr r3, [r7, #12]
8005794: f023 0320 bic.w r3, r3, #32
8005798: 60fb str r3, [r7, #12]
hrtim_mcr |= pTimerCfg->HalfModeEnable;
800579a: 683b ldr r3, [r7, #0]
800579c: 695b ldr r3, [r3, #20]
800579e: 68fa ldr r2, [r7, #12]
80057a0: 4313 orrs r3, r2
80057a2: 60fb str r3, [r7, #12]
/* INTLVD bits are set to 00 */
hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
80057a4: 68fb ldr r3, [r7, #12]
80057a6: f023 03c0 bic.w r3, r3, #192 @ 0xc0
80057aa: 60fb str r3, [r7, #12]
if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED)
80057ac: 683b ldr r3, [r7, #0]
80057ae: 695b ldr r3, [r3, #20]
80057b0: 2b20 cmp r3, #32
80057b2: d003 beq.n 80057bc <HRTIM_MasterWaveform_Config+0x46>
|| (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL))
80057b4: 683b ldr r3, [r7, #0]
80057b6: 699b ldr r3, [r3, #24]
80057b8: 2b02 cmp r3, #2
80057ba: d108 bne.n 80057ce <HRTIM_MasterWaveform_Config+0x58>
{
/* INTLVD bits set to 00 */
hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
80057bc: 68fb ldr r3, [r7, #12]
80057be: f023 03c0 bic.w r3, r3, #192 @ 0xc0
80057c2: 60fb str r3, [r7, #12]
hrtim_mcr |= (HRTIM_MCR_HALF);
80057c4: 68fb ldr r3, [r7, #12]
80057c6: f043 0320 orr.w r3, r3, #32
80057ca: 60fb str r3, [r7, #12]
80057cc: e021 b.n 8005812 <HRTIM_MasterWaveform_Config+0x9c>
}
else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE)
80057ce: 683b ldr r3, [r7, #0]
80057d0: 699b ldr r3, [r3, #24]
80057d2: 2b03 cmp r3, #3
80057d4: d108 bne.n 80057e8 <HRTIM_MasterWaveform_Config+0x72>
{
hrtim_mcr |= (HRTIM_MCR_INTLVD_0);
80057d6: 68fb ldr r3, [r7, #12]
80057d8: f043 0340 orr.w r3, r3, #64 @ 0x40
80057dc: 60fb str r3, [r7, #12]
hrtim_mcr &= ~(HRTIM_MCR_INTLVD_1);
80057de: 68fb ldr r3, [r7, #12]
80057e0: f023 0380 bic.w r3, r3, #128 @ 0x80
80057e4: 60fb str r3, [r7, #12]
80057e6: e014 b.n 8005812 <HRTIM_MasterWaveform_Config+0x9c>
}
else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD)
80057e8: 683b ldr r3, [r7, #0]
80057ea: 699b ldr r3, [r3, #24]
80057ec: 2b04 cmp r3, #4
80057ee: d108 bne.n 8005802 <HRTIM_MasterWaveform_Config+0x8c>
{
hrtim_mcr |= (HRTIM_MCR_INTLVD_1);
80057f0: 68fb ldr r3, [r7, #12]
80057f2: f043 0380 orr.w r3, r3, #128 @ 0x80
80057f6: 60fb str r3, [r7, #12]
hrtim_mcr &= ~(HRTIM_MCR_INTLVD_0);
80057f8: 68fb ldr r3, [r7, #12]
80057fa: f023 0340 bic.w r3, r3, #64 @ 0x40
80057fe: 60fb str r3, [r7, #12]
8005800: e007 b.n 8005812 <HRTIM_MasterWaveform_Config+0x9c>
}
else
{
hrtim_mcr &= ~(HRTIM_MCR_HALF);
8005802: 68fb ldr r3, [r7, #12]
8005804: f023 0320 bic.w r3, r3, #32
8005808: 60fb str r3, [r7, #12]
hrtim_mcr &= ~(HRTIM_MCR_INTLVD);
800580a: 68fb ldr r3, [r7, #12]
800580c: f023 03c0 bic.w r3, r3, #192 @ 0xc0
8005810: 60fb str r3, [r7, #12]
}
/* Enable/Disable the timer start upon synchronization event reception */
hrtim_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
8005812: 68fb ldr r3, [r7, #12]
8005814: f423 6300 bic.w r3, r3, #2048 @ 0x800
8005818: 60fb str r3, [r7, #12]
hrtim_mcr |= pTimerCfg->StartOnSync;
800581a: 683b ldr r3, [r7, #0]
800581c: 69db ldr r3, [r3, #28]
800581e: 68fa ldr r2, [r7, #12]
8005820: 4313 orrs r3, r2
8005822: 60fb str r3, [r7, #12]
/* Enable/Disable the timer reset upon synchronization event reception */
hrtim_mcr &= ~(HRTIM_MCR_SYNCRSTM);
8005824: 68fb ldr r3, [r7, #12]
8005826: f423 6380 bic.w r3, r3, #1024 @ 0x400
800582a: 60fb str r3, [r7, #12]
hrtim_mcr |= pTimerCfg->ResetOnSync;
800582c: 683b ldr r3, [r7, #0]
800582e: 6a1b ldr r3, [r3, #32]
8005830: 68fa ldr r2, [r7, #12]
8005832: 4313 orrs r3, r2
8005834: 60fb str r3, [r7, #12]
/* Enable/Disable the DAC synchronization event generation */
hrtim_mcr &= ~(HRTIM_MCR_DACSYNC);
8005836: 68fb ldr r3, [r7, #12]
8005838: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
800583c: 60fb str r3, [r7, #12]
hrtim_mcr |= pTimerCfg->DACSynchro;
800583e: 683b ldr r3, [r7, #0]
8005840: 6a5b ldr r3, [r3, #36] @ 0x24
8005842: 68fa ldr r2, [r7, #12]
8005844: 4313 orrs r3, r2
8005846: 60fb str r3, [r7, #12]
/* Enable/Disable preload mechanism for timer registers */
hrtim_mcr &= ~(HRTIM_MCR_PREEN);
8005848: 68fb ldr r3, [r7, #12]
800584a: f023 6300 bic.w r3, r3, #134217728 @ 0x8000000
800584e: 60fb str r3, [r7, #12]
hrtim_mcr |= pTimerCfg->PreloadEnable;
8005850: 683b ldr r3, [r7, #0]
8005852: 6a9b ldr r3, [r3, #40] @ 0x28
8005854: 68fa ldr r2, [r7, #12]
8005856: 4313 orrs r3, r2
8005858: 60fb str r3, [r7, #12]
/* Master timer registers update handling */
hrtim_mcr &= ~(HRTIM_MCR_BRSTDMA);
800585a: 68fb ldr r3, [r7, #12]
800585c: f023 4340 bic.w r3, r3, #3221225472 @ 0xc0000000
8005860: 60fb str r3, [r7, #12]
hrtim_mcr |= (pTimerCfg->UpdateGating << 2U);
8005862: 683b ldr r3, [r7, #0]
8005864: 6adb ldr r3, [r3, #44] @ 0x2c
8005866: 009b lsls r3, r3, #2
8005868: 68fa ldr r2, [r7, #12]
800586a: 4313 orrs r3, r2
800586c: 60fb str r3, [r7, #12]
/* Enable/Disable registers update on repetition */
hrtim_mcr &= ~(HRTIM_MCR_MREPU);
800586e: 68fb ldr r3, [r7, #12]
8005870: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000
8005874: 60fb str r3, [r7, #12]
hrtim_mcr |= pTimerCfg->RepetitionUpdate;
8005876: 683b ldr r3, [r7, #0]
8005878: 6b5b ldr r3, [r3, #52] @ 0x34
800587a: 68fa ldr r2, [r7, #12]
800587c: 4313 orrs r3, r2
800587e: 60fb str r3, [r7, #12]
/* Set the timer burst mode */
hrtim_bmcr &= ~(HRTIM_BMCR_MTBM);
8005880: 68bb ldr r3, [r7, #8]
8005882: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005886: 60bb str r3, [r7, #8]
hrtim_bmcr |= pTimerCfg->BurstMode;
8005888: 683b ldr r3, [r7, #0]
800588a: 6b1b ldr r3, [r3, #48] @ 0x30
800588c: 68ba ldr r2, [r7, #8]
800588e: 4313 orrs r3, r2
8005890: 60bb str r3, [r7, #8]
/* Update the HRTIM registers */
hhrtim->Instance->sMasterRegs.MCR = hrtim_mcr;
8005892: 687b ldr r3, [r7, #4]
8005894: 681b ldr r3, [r3, #0]
8005896: 68fa ldr r2, [r7, #12]
8005898: 601a str r2, [r3, #0]
hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
800589a: 687b ldr r3, [r7, #4]
800589c: 681b ldr r3, [r3, #0]
800589e: 68ba ldr r2, [r7, #8]
80058a0: f8c3 23a0 str.w r2, [r3, #928] @ 0x3a0
}
80058a4: bf00 nop
80058a6: 3714 adds r7, #20
80058a8: 46bd mov sp, r7
80058aa: f85d 7b04 ldr.w r7, [sp], #4
80058ae: 4770 bx lr
080058b0 <HRTIM_TimingUnitWaveform_Config>:
* @retval None
*/
static void HRTIM_TimingUnitWaveform_Config(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
const HRTIM_TimerCfgTypeDef *pTimerCfg)
{
80058b0: b480 push {r7}
80058b2: b08b sub sp, #44 @ 0x2c
80058b4: af00 add r7, sp, #0
80058b6: 60f8 str r0, [r7, #12]
80058b8: 60b9 str r1, [r7, #8]
80058ba: 607a str r2, [r7, #4]
uint32_t hrtim_timoutr;
uint32_t hrtim_timrstr;
uint32_t hrtim_bmcr;
/* UPDGAT bitfield must be reset before programming a new value */
hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR &= ~(HRTIM_TIMCR_UPDGAT);
80058bc: 68fb ldr r3, [r7, #12]
80058be: 681a ldr r2, [r3, #0]
80058c0: 68bb ldr r3, [r7, #8]
80058c2: 3301 adds r3, #1
80058c4: 01db lsls r3, r3, #7
80058c6: 4413 add r3, r2
80058c8: 681b ldr r3, [r3, #0]
80058ca: 68fa ldr r2, [r7, #12]
80058cc: 6811 ldr r1, [r2, #0]
80058ce: f023 4270 bic.w r2, r3, #4026531840 @ 0xf0000000
80058d2: 68bb ldr r3, [r7, #8]
80058d4: 3301 adds r3, #1
80058d6: 01db lsls r3, r3, #7
80058d8: 440b add r3, r1
80058da: 601a str r2, [r3, #0]
/* Configure timing unit (Timer A to Timer F) */
hrtim_timcr = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR;
80058dc: 68fb ldr r3, [r7, #12]
80058de: 681a ldr r2, [r3, #0]
80058e0: 68bb ldr r3, [r7, #8]
80058e2: 3301 adds r3, #1
80058e4: 01db lsls r3, r3, #7
80058e6: 4413 add r3, r2
80058e8: 681b ldr r3, [r3, #0]
80058ea: 627b str r3, [r7, #36] @ 0x24
hrtim_timfltr = hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR;
80058ec: 68fb ldr r3, [r7, #12]
80058ee: 681a ldr r2, [r3, #0]
80058f0: 68bb ldr r3, [r7, #8]
80058f2: 01db lsls r3, r3, #7
80058f4: 4413 add r3, r2
80058f6: 33e8 adds r3, #232 @ 0xe8
80058f8: 681b ldr r3, [r3, #0]
80058fa: 61bb str r3, [r7, #24]
hrtim_timoutr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
80058fc: 68fb ldr r3, [r7, #12]
80058fe: 681a ldr r2, [r3, #0]
8005900: 68bb ldr r3, [r7, #8]
8005902: 01db lsls r3, r3, #7
8005904: 4413 add r3, r2
8005906: 33e4 adds r3, #228 @ 0xe4
8005908: 681b ldr r3, [r3, #0]
800590a: 623b str r3, [r7, #32]
hrtim_bmcr = hhrtim->Instance->sCommonRegs.BMCR;
800590c: 68fb ldr r3, [r7, #12]
800590e: 681b ldr r3, [r3, #0]
8005910: f8d3 33a0 ldr.w r3, [r3, #928] @ 0x3a0
8005914: 61fb str r3, [r7, #28]
/* Enable/Disable the half mode */
hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
8005916: 6a7b ldr r3, [r7, #36] @ 0x24
8005918: f023 0320 bic.w r3, r3, #32
800591c: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr |= pTimerCfg->HalfModeEnable;
800591e: 687b ldr r3, [r7, #4]
8005920: 695b ldr r3, [r3, #20]
8005922: 6a7a ldr r2, [r7, #36] @ 0x24
8005924: 4313 orrs r3, r2
8005926: 627b str r3, [r7, #36] @ 0x24
if ((pTimerCfg->HalfModeEnable == HRTIM_HALFMODE_ENABLED)
8005928: 687b ldr r3, [r7, #4]
800592a: 695b ldr r3, [r3, #20]
800592c: 2b20 cmp r3, #32
800592e: d003 beq.n 8005938 <HRTIM_TimingUnitWaveform_Config+0x88>
|| (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_DUAL))
8005930: 687b ldr r3, [r7, #4]
8005932: 699b ldr r3, [r3, #24]
8005934: 2b02 cmp r3, #2
8005936: d108 bne.n 800594a <HRTIM_TimingUnitWaveform_Config+0x9a>
{
/* INTLVD bits set to 00 */
hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD);
8005938: 6a7b ldr r3, [r7, #36] @ 0x24
800593a: f423 73c0 bic.w r3, r3, #384 @ 0x180
800593e: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr |= (HRTIM_TIMCR_HALF);
8005940: 6a7b ldr r3, [r7, #36] @ 0x24
8005942: f043 0320 orr.w r3, r3, #32
8005946: 627b str r3, [r7, #36] @ 0x24
8005948: e021 b.n 800598e <HRTIM_TimingUnitWaveform_Config+0xde>
}
else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_TRIPLE)
800594a: 687b ldr r3, [r7, #4]
800594c: 699b ldr r3, [r3, #24]
800594e: 2b03 cmp r3, #3
8005950: d108 bne.n 8005964 <HRTIM_TimingUnitWaveform_Config+0xb4>
{
hrtim_timcr |= (HRTIM_TIMCR_INTLVD_0);
8005952: 6a7b ldr r3, [r7, #36] @ 0x24
8005954: f043 0380 orr.w r3, r3, #128 @ 0x80
8005958: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_1);
800595a: 6a7b ldr r3, [r7, #36] @ 0x24
800595c: f423 7380 bic.w r3, r3, #256 @ 0x100
8005960: 627b str r3, [r7, #36] @ 0x24
8005962: e014 b.n 800598e <HRTIM_TimingUnitWaveform_Config+0xde>
}
else if (pTimerCfg->InterleavedMode == HRTIM_INTERLEAVED_MODE_QUAD)
8005964: 687b ldr r3, [r7, #4]
8005966: 699b ldr r3, [r3, #24]
8005968: 2b04 cmp r3, #4
800596a: d108 bne.n 800597e <HRTIM_TimingUnitWaveform_Config+0xce>
{
hrtim_timcr |= (HRTIM_TIMCR_INTLVD_1);
800596c: 6a7b ldr r3, [r7, #36] @ 0x24
800596e: f443 7380 orr.w r3, r3, #256 @ 0x100
8005972: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD_0);
8005974: 6a7b ldr r3, [r7, #36] @ 0x24
8005976: f023 0380 bic.w r3, r3, #128 @ 0x80
800597a: 627b str r3, [r7, #36] @ 0x24
800597c: e007 b.n 800598e <HRTIM_TimingUnitWaveform_Config+0xde>
}
else
{
hrtim_timcr &= ~(HRTIM_TIMCR_HALF);
800597e: 6a7b ldr r3, [r7, #36] @ 0x24
8005980: f023 0320 bic.w r3, r3, #32
8005984: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr &= ~(HRTIM_TIMCR_INTLVD);
8005986: 6a7b ldr r3, [r7, #36] @ 0x24
8005988: f423 73c0 bic.w r3, r3, #384 @ 0x180
800598c: 627b str r3, [r7, #36] @ 0x24
}
/* Enable/Disable the timer start upon synchronization event reception */
hrtim_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
800598e: 6a7b ldr r3, [r7, #36] @ 0x24
8005990: f423 6300 bic.w r3, r3, #2048 @ 0x800
8005994: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr |= pTimerCfg->StartOnSync;
8005996: 687b ldr r3, [r7, #4]
8005998: 69db ldr r3, [r3, #28]
800599a: 6a7a ldr r2, [r7, #36] @ 0x24
800599c: 4313 orrs r3, r2
800599e: 627b str r3, [r7, #36] @ 0x24
/* Enable/Disable the timer reset upon synchronization event reception */
hrtim_timcr &= ~(HRTIM_TIMCR_SYNCRST);
80059a0: 6a7b ldr r3, [r7, #36] @ 0x24
80059a2: f423 6380 bic.w r3, r3, #1024 @ 0x400
80059a6: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr |= pTimerCfg->ResetOnSync;
80059a8: 687b ldr r3, [r7, #4]
80059aa: 6a1b ldr r3, [r3, #32]
80059ac: 6a7a ldr r2, [r7, #36] @ 0x24
80059ae: 4313 orrs r3, r2
80059b0: 627b str r3, [r7, #36] @ 0x24
/* Enable/Disable the DAC synchronization event generation */
hrtim_timcr &= ~(HRTIM_TIMCR_DACSYNC);
80059b2: 6a7b ldr r3, [r7, #36] @ 0x24
80059b4: f023 63c0 bic.w r3, r3, #100663296 @ 0x6000000
80059b8: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr |= pTimerCfg->DACSynchro;
80059ba: 687b ldr r3, [r7, #4]
80059bc: 6a5b ldr r3, [r3, #36] @ 0x24
80059be: 6a7a ldr r2, [r7, #36] @ 0x24
80059c0: 4313 orrs r3, r2
80059c2: 627b str r3, [r7, #36] @ 0x24
/* Enable/Disable preload mechanism for timer registers */
hrtim_timcr &= ~(HRTIM_TIMCR_PREEN);
80059c4: 6a7b ldr r3, [r7, #36] @ 0x24
80059c6: f023 6300 bic.w r3, r3, #134217728 @ 0x8000000
80059ca: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr |= pTimerCfg->PreloadEnable;
80059cc: 687b ldr r3, [r7, #4]
80059ce: 6a9b ldr r3, [r3, #40] @ 0x28
80059d0: 6a7a ldr r2, [r7, #36] @ 0x24
80059d2: 4313 orrs r3, r2
80059d4: 627b str r3, [r7, #36] @ 0x24
/* Timing unit registers update handling */
hrtim_timcr &= ~(HRTIM_TIMCR_UPDGAT);
80059d6: 6a7b ldr r3, [r7, #36] @ 0x24
80059d8: f023 4370 bic.w r3, r3, #4026531840 @ 0xf0000000
80059dc: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr |= pTimerCfg->UpdateGating;
80059de: 687b ldr r3, [r7, #4]
80059e0: 6adb ldr r3, [r3, #44] @ 0x2c
80059e2: 6a7a ldr r2, [r7, #36] @ 0x24
80059e4: 4313 orrs r3, r2
80059e6: 627b str r3, [r7, #36] @ 0x24
/* Enable/Disable registers update on repetition */
hrtim_timcr &= ~(HRTIM_TIMCR_TREPU);
80059e8: 6a7b ldr r3, [r7, #36] @ 0x24
80059ea: f423 3300 bic.w r3, r3, #131072 @ 0x20000
80059ee: 627b str r3, [r7, #36] @ 0x24
if (pTimerCfg->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
80059f0: 687b ldr r3, [r7, #4]
80059f2: 6b5b ldr r3, [r3, #52] @ 0x34
80059f4: f1b3 5f00 cmp.w r3, #536870912 @ 0x20000000
80059f8: d103 bne.n 8005a02 <HRTIM_TimingUnitWaveform_Config+0x152>
{
hrtim_timcr |= HRTIM_TIMCR_TREPU;
80059fa: 6a7b ldr r3, [r7, #36] @ 0x24
80059fc: f443 3300 orr.w r3, r3, #131072 @ 0x20000
8005a00: 627b str r3, [r7, #36] @ 0x24
}
/* Set the push-pull mode */
hrtim_timcr &= ~(HRTIM_TIMCR_PSHPLL);
8005a02: 6a7b ldr r3, [r7, #36] @ 0x24
8005a04: f023 0340 bic.w r3, r3, #64 @ 0x40
8005a08: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr |= pTimerCfg->PushPull;
8005a0a: 687b ldr r3, [r7, #4]
8005a0c: 6b9b ldr r3, [r3, #56] @ 0x38
8005a0e: 6a7a ldr r2, [r7, #36] @ 0x24
8005a10: 4313 orrs r3, r2
8005a12: 627b str r3, [r7, #36] @ 0x24
/* Enable/Disable registers update on timer counter reset */
hrtim_timcr &= ~(HRTIM_TIMCR_TRSTU);
8005a14: 6a7b ldr r3, [r7, #36] @ 0x24
8005a16: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8005a1a: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr |= pTimerCfg->ResetUpdate;
8005a1c: 687b ldr r3, [r7, #4]
8005a1e: 6d9b ldr r3, [r3, #88] @ 0x58
8005a20: 6a7a ldr r2, [r7, #36] @ 0x24
8005a22: 4313 orrs r3, r2
8005a24: 627b str r3, [r7, #36] @ 0x24
/* Set the timer update trigger */
hrtim_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
8005a26: 6a7b ldr r3, [r7, #36] @ 0x24
8005a28: f023 73fc bic.w r3, r3, #33030144 @ 0x1f80000
8005a2c: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005a30: 627b str r3, [r7, #36] @ 0x24
hrtim_timcr |= pTimerCfg->UpdateTrigger;
8005a32: 687b ldr r3, [r7, #4]
8005a34: 6d1b ldr r3, [r3, #80] @ 0x50
8005a36: 6a7a ldr r2, [r7, #36] @ 0x24
8005a38: 4313 orrs r3, r2
8005a3a: 627b str r3, [r7, #36] @ 0x24
/* Enable/Disable the fault channel at timer level */
hrtim_timfltr &= ~(HRTIM_FLTR_FLTxEN);
8005a3c: 69bb ldr r3, [r7, #24]
8005a3e: f023 033f bic.w r3, r3, #63 @ 0x3f
8005a42: 61bb str r3, [r7, #24]
hrtim_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
8005a44: 687b ldr r3, [r7, #4]
8005a46: 6bdb ldr r3, [r3, #60] @ 0x3c
8005a48: f003 033f and.w r3, r3, #63 @ 0x3f
8005a4c: 69ba ldr r2, [r7, #24]
8005a4e: 4313 orrs r3, r2
8005a50: 61bb str r3, [r7, #24]
/* Lock/Unlock fault sources at timer level */
hrtim_timfltr &= ~(HRTIM_FLTR_FLTLCK);
8005a52: 69bb ldr r3, [r7, #24]
8005a54: f023 4300 bic.w r3, r3, #2147483648 @ 0x80000000
8005a58: 61bb str r3, [r7, #24]
hrtim_timfltr |= pTimerCfg->FaultLock;
8005a5a: 687b ldr r3, [r7, #4]
8005a5c: 6c1b ldr r3, [r3, #64] @ 0x40
8005a5e: 69ba ldr r2, [r7, #24]
8005a60: 4313 orrs r3, r2
8005a62: 61bb str r3, [r7, #24]
/* Enable/Disable dead time insertion at timer level */
hrtim_timoutr &= ~(HRTIM_OUTR_DTEN);
8005a64: 6a3b ldr r3, [r7, #32]
8005a66: f423 7380 bic.w r3, r3, #256 @ 0x100
8005a6a: 623b str r3, [r7, #32]
hrtim_timoutr |= pTimerCfg->DeadTimeInsertion;
8005a6c: 687b ldr r3, [r7, #4]
8005a6e: 6c5b ldr r3, [r3, #68] @ 0x44
8005a70: 6a3a ldr r2, [r7, #32]
8005a72: 4313 orrs r3, r2
8005a74: 623b str r3, [r7, #32]
/* Enable/Disable delayed protection at timer level
Delayed Idle is available whatever the timer operating mode (regular, push-pull)
Balanced Idle is only available in push-pull mode
*/
if (((pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)
8005a76: 687b ldr r3, [r7, #4]
8005a78: 6c9b ldr r3, [r3, #72] @ 0x48
8005a7a: f5b3 6f60 cmp.w r3, #3584 @ 0xe00
8005a7e: d004 beq.n 8005a8a <HRTIM_TimingUnitWaveform_Config+0x1da>
&& (pTimerCfg->DelayedProtectionMode != HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))
8005a80: 687b ldr r3, [r7, #4]
8005a82: 6c9b ldr r3, [r3, #72] @ 0x48
8005a84: f5b3 5ff0 cmp.w r3, #7680 @ 0x1e00
8005a88: d103 bne.n 8005a92 <HRTIM_TimingUnitWaveform_Config+0x1e2>
|| (pTimerCfg->PushPull == HRTIM_TIMPUSHPULLMODE_ENABLED))
8005a8a: 687b ldr r3, [r7, #4]
8005a8c: 6b9b ldr r3, [r3, #56] @ 0x38
8005a8e: 2b40 cmp r3, #64 @ 0x40
8005a90: d108 bne.n 8005aa4 <HRTIM_TimingUnitWaveform_Config+0x1f4>
{
hrtim_timoutr &= ~(HRTIM_OUTR_DLYPRT | HRTIM_OUTR_DLYPRTEN);
8005a92: 6a3b ldr r3, [r7, #32]
8005a94: f423 53f0 bic.w r3, r3, #7680 @ 0x1e00
8005a98: 623b str r3, [r7, #32]
hrtim_timoutr |= pTimerCfg->DelayedProtectionMode;
8005a9a: 687b ldr r3, [r7, #4]
8005a9c: 6c9b ldr r3, [r3, #72] @ 0x48
8005a9e: 6a3a ldr r2, [r7, #32]
8005aa0: 4313 orrs r3, r2
8005aa2: 623b str r3, [r7, #32]
}
/* Set the BIAR mode : one bit for both outputs */
hrtim_timoutr &= ~(HRTIM_OUTR_BIAR);
8005aa4: 6a3b ldr r3, [r7, #32]
8005aa6: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8005aaa: 623b str r3, [r7, #32]
hrtim_timoutr |= (pTimerCfg->BalancedIdleAutomaticResume);
8005aac: 687b ldr r3, [r7, #4]
8005aae: 6cdb ldr r3, [r3, #76] @ 0x4c
8005ab0: 6a3a ldr r2, [r7, #32]
8005ab2: 4313 orrs r3, r2
8005ab4: 623b str r3, [r7, #32]
/* Set the timer counter reset trigger */
hrtim_timrstr = pTimerCfg->ResetTrigger;
8005ab6: 687b ldr r3, [r7, #4]
8005ab8: 6d5b ldr r3, [r3, #84] @ 0x54
8005aba: 617b str r3, [r7, #20]
/* Set the timer burst mode */
switch (TimerIdx)
8005abc: 68bb ldr r3, [r7, #8]
8005abe: 2b05 cmp r3, #5
8005ac0: d850 bhi.n 8005b64 <HRTIM_TimingUnitWaveform_Config+0x2b4>
8005ac2: a201 add r2, pc, #4 @ (adr r2, 8005ac8 <HRTIM_TimingUnitWaveform_Config+0x218>)
8005ac4: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005ac8: 08005ae1 .word 0x08005ae1
8005acc: 08005af7 .word 0x08005af7
8005ad0: 08005b0d .word 0x08005b0d
8005ad4: 08005b23 .word 0x08005b23
8005ad8: 08005b39 .word 0x08005b39
8005adc: 08005b4f .word 0x08005b4f
{
case HRTIM_TIMERINDEX_TIMER_A:
{
hrtim_bmcr &= ~(HRTIM_BMCR_TABM);
8005ae0: 69fb ldr r3, [r7, #28]
8005ae2: f423 3300 bic.w r3, r3, #131072 @ 0x20000
8005ae6: 61fb str r3, [r7, #28]
hrtim_bmcr |= (pTimerCfg->BurstMode << 1U);
8005ae8: 687b ldr r3, [r7, #4]
8005aea: 6b1b ldr r3, [r3, #48] @ 0x30
8005aec: 005b lsls r3, r3, #1
8005aee: 69fa ldr r2, [r7, #28]
8005af0: 4313 orrs r3, r2
8005af2: 61fb str r3, [r7, #28]
break;
8005af4: e037 b.n 8005b66 <HRTIM_TimingUnitWaveform_Config+0x2b6>
}
case HRTIM_TIMERINDEX_TIMER_B:
{
hrtim_bmcr &= ~(HRTIM_BMCR_TBBM);
8005af6: 69fb ldr r3, [r7, #28]
8005af8: f423 2380 bic.w r3, r3, #262144 @ 0x40000
8005afc: 61fb str r3, [r7, #28]
hrtim_bmcr |= (pTimerCfg->BurstMode << 2U);
8005afe: 687b ldr r3, [r7, #4]
8005b00: 6b1b ldr r3, [r3, #48] @ 0x30
8005b02: 009b lsls r3, r3, #2
8005b04: 69fa ldr r2, [r7, #28]
8005b06: 4313 orrs r3, r2
8005b08: 61fb str r3, [r7, #28]
break;
8005b0a: e02c b.n 8005b66 <HRTIM_TimingUnitWaveform_Config+0x2b6>
}
case HRTIM_TIMERINDEX_TIMER_C:
{
hrtim_bmcr &= ~(HRTIM_BMCR_TCBM);
8005b0c: 69fb ldr r3, [r7, #28]
8005b0e: f423 2300 bic.w r3, r3, #524288 @ 0x80000
8005b12: 61fb str r3, [r7, #28]
hrtim_bmcr |= (pTimerCfg->BurstMode << 3U);
8005b14: 687b ldr r3, [r7, #4]
8005b16: 6b1b ldr r3, [r3, #48] @ 0x30
8005b18: 00db lsls r3, r3, #3
8005b1a: 69fa ldr r2, [r7, #28]
8005b1c: 4313 orrs r3, r2
8005b1e: 61fb str r3, [r7, #28]
break;
8005b20: e021 b.n 8005b66 <HRTIM_TimingUnitWaveform_Config+0x2b6>
}
case HRTIM_TIMERINDEX_TIMER_D:
{
hrtim_bmcr &= ~(HRTIM_BMCR_TDBM);
8005b22: 69fb ldr r3, [r7, #28]
8005b24: f423 1380 bic.w r3, r3, #1048576 @ 0x100000
8005b28: 61fb str r3, [r7, #28]
hrtim_bmcr |= (pTimerCfg->BurstMode << 4U);
8005b2a: 687b ldr r3, [r7, #4]
8005b2c: 6b1b ldr r3, [r3, #48] @ 0x30
8005b2e: 011b lsls r3, r3, #4
8005b30: 69fa ldr r2, [r7, #28]
8005b32: 4313 orrs r3, r2
8005b34: 61fb str r3, [r7, #28]
break;
8005b36: e016 b.n 8005b66 <HRTIM_TimingUnitWaveform_Config+0x2b6>
}
case HRTIM_TIMERINDEX_TIMER_E:
{
hrtim_bmcr &= ~(HRTIM_BMCR_TEBM);
8005b38: 69fb ldr r3, [r7, #28]
8005b3a: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
8005b3e: 61fb str r3, [r7, #28]
hrtim_bmcr |= (pTimerCfg->BurstMode << 5U);
8005b40: 687b ldr r3, [r7, #4]
8005b42: 6b1b ldr r3, [r3, #48] @ 0x30
8005b44: 015b lsls r3, r3, #5
8005b46: 69fa ldr r2, [r7, #28]
8005b48: 4313 orrs r3, r2
8005b4a: 61fb str r3, [r7, #28]
break;
8005b4c: e00b b.n 8005b66 <HRTIM_TimingUnitWaveform_Config+0x2b6>
}
case HRTIM_TIMERINDEX_TIMER_F:
{
hrtim_bmcr &= ~(HRTIM_BMCR_TFBM);
8005b4e: 69fb ldr r3, [r7, #28]
8005b50: f423 0380 bic.w r3, r3, #4194304 @ 0x400000
8005b54: 61fb str r3, [r7, #28]
hrtim_bmcr |= (pTimerCfg->BurstMode << 6U);
8005b56: 687b ldr r3, [r7, #4]
8005b58: 6b1b ldr r3, [r3, #48] @ 0x30
8005b5a: 019b lsls r3, r3, #6
8005b5c: 69fa ldr r2, [r7, #28]
8005b5e: 4313 orrs r3, r2
8005b60: 61fb str r3, [r7, #28]
break;
8005b62: e000 b.n 8005b66 <HRTIM_TimingUnitWaveform_Config+0x2b6>
}
default:
break;
8005b64: bf00 nop
}
/* Update the HRTIM registers */
hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR = hrtim_timcr;
8005b66: 68fb ldr r3, [r7, #12]
8005b68: 681a ldr r2, [r3, #0]
8005b6a: 68bb ldr r3, [r7, #8]
8005b6c: 3301 adds r3, #1
8005b6e: 01db lsls r3, r3, #7
8005b70: 4413 add r3, r2
8005b72: 6a7a ldr r2, [r7, #36] @ 0x24
8005b74: 601a str r2, [r3, #0]
hhrtim->Instance->sTimerxRegs[TimerIdx].FLTxR = hrtim_timfltr;
8005b76: 68fb ldr r3, [r7, #12]
8005b78: 681a ldr r2, [r3, #0]
8005b7a: 68bb ldr r3, [r7, #8]
8005b7c: 01db lsls r3, r3, #7
8005b7e: 4413 add r3, r2
8005b80: 33e8 adds r3, #232 @ 0xe8
8005b82: 69ba ldr r2, [r7, #24]
8005b84: 601a str r2, [r3, #0]
hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_timoutr;
8005b86: 68fb ldr r3, [r7, #12]
8005b88: 681a ldr r2, [r3, #0]
8005b8a: 68bb ldr r3, [r7, #8]
8005b8c: 01db lsls r3, r3, #7
8005b8e: 4413 add r3, r2
8005b90: 33e4 adds r3, #228 @ 0xe4
8005b92: 6a3a ldr r2, [r7, #32]
8005b94: 601a str r2, [r3, #0]
hhrtim->Instance->sTimerxRegs[TimerIdx].RSTxR = hrtim_timrstr;
8005b96: 68fb ldr r3, [r7, #12]
8005b98: 681a ldr r2, [r3, #0]
8005b9a: 68bb ldr r3, [r7, #8]
8005b9c: 01db lsls r3, r3, #7
8005b9e: 4413 add r3, r2
8005ba0: 33d4 adds r3, #212 @ 0xd4
8005ba2: 697a ldr r2, [r7, #20]
8005ba4: 601a str r2, [r3, #0]
hhrtim->Instance->sCommonRegs.BMCR = hrtim_bmcr;
8005ba6: 68fb ldr r3, [r7, #12]
8005ba8: 681b ldr r3, [r3, #0]
8005baa: 69fa ldr r2, [r7, #28]
8005bac: f8c3 23a0 str.w r2, [r3, #928] @ 0x3a0
}
8005bb0: bf00 nop
8005bb2: 372c adds r7, #44 @ 0x2c
8005bb4: 46bd mov sp, r7
8005bb6: f85d 7b04 ldr.w r7, [sp], #4
8005bba: 4770 bx lr
08005bbc <HRTIM_TimingUnitWaveform_Control>:
* @retval None
*/
static void HRTIM_TimingUnitWaveform_Control(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
const HRTIM_TimerCtlTypeDef *pTimerCtl)
{
8005bbc: b480 push {r7}
8005bbe: b087 sub sp, #28
8005bc0: af00 add r7, sp, #0
8005bc2: 60f8 str r0, [r7, #12]
8005bc4: 60b9 str r1, [r7, #8]
8005bc6: 607a str r2, [r7, #4]
uint32_t hrtim_timcr2;
/* Configure timing unit (Timer A to Timer F) */
hrtim_timcr2 = hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2;
8005bc8: 68fb ldr r3, [r7, #12]
8005bca: 681a ldr r2, [r3, #0]
8005bcc: 68bb ldr r3, [r7, #8]
8005bce: 01db lsls r3, r3, #7
8005bd0: 4413 add r3, r2
8005bd2: 33ec adds r3, #236 @ 0xec
8005bd4: 681b ldr r3, [r3, #0]
8005bd6: 617b str r3, [r7, #20]
/* Set the UpDown counting Mode */
hrtim_timcr2 &= ~(HRTIM_TIMCR2_UDM);
8005bd8: 697b ldr r3, [r7, #20]
8005bda: f023 0310 bic.w r3, r3, #16
8005bde: 617b str r3, [r7, #20]
hrtim_timcr2 |= (pTimerCtl->UpDownMode << HRTIM_TIMCR2_UDM_Pos) ;
8005be0: 687b ldr r3, [r7, #4]
8005be2: 681b ldr r3, [r3, #0]
8005be4: 011b lsls r3, r3, #4
8005be6: 697a ldr r2, [r7, #20]
8005be8: 4313 orrs r3, r2
8005bea: 617b str r3, [r7, #20]
/* Set the TrigHalf Mode : requires the counter to be disabled */
hrtim_timcr2 &= ~(HRTIM_TIMCR2_TRGHLF);
8005bec: 697b ldr r3, [r7, #20]
8005bee: f423 1380 bic.w r3, r3, #1048576 @ 0x100000
8005bf2: 617b str r3, [r7, #20]
hrtim_timcr2 |= pTimerCtl->TrigHalf;
8005bf4: 687b ldr r3, [r7, #4]
8005bf6: 685b ldr r3, [r3, #4]
8005bf8: 697a ldr r2, [r7, #20]
8005bfa: 4313 orrs r3, r2
8005bfc: 617b str r3, [r7, #20]
/* define the compare event operating mode */
hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP1);
8005bfe: 697b ldr r3, [r7, #20]
8005c00: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8005c04: 617b str r3, [r7, #20]
hrtim_timcr2 |= pTimerCtl->GreaterCMP1;
8005c06: 687b ldr r3, [r7, #4]
8005c08: 68db ldr r3, [r3, #12]
8005c0a: 697a ldr r2, [r7, #20]
8005c0c: 4313 orrs r3, r2
8005c0e: 617b str r3, [r7, #20]
/* define the compare event operating mode */
hrtim_timcr2 &= ~(HRTIM_TIMCR2_GTCMP3);
8005c10: 697b ldr r3, [r7, #20]
8005c12: f423 3300 bic.w r3, r3, #131072 @ 0x20000
8005c16: 617b str r3, [r7, #20]
hrtim_timcr2 |= pTimerCtl->GreaterCMP3;
8005c18: 687b ldr r3, [r7, #4]
8005c1a: 689b ldr r3, [r3, #8]
8005c1c: 697a ldr r2, [r7, #20]
8005c1e: 4313 orrs r3, r2
8005c20: 617b str r3, [r7, #20]
if (pTimerCtl->DualChannelDacEnable == HRTIM_TIMER_DCDE_ENABLED)
8005c22: 687b ldr r3, [r7, #4]
8005c24: 699b ldr r3, [r3, #24]
8005c26: 2b01 cmp r3, #1
8005c28: d11a bne.n 8005c60 <HRTIM_TimingUnitWaveform_Control+0xa4>
{
/* Set the DualChannel DAC Reset trigger : requires DCDE enabled */
hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDR);
8005c2a: 697b ldr r3, [r7, #20]
8005c2c: f023 0304 bic.w r3, r3, #4
8005c30: 617b str r3, [r7, #20]
hrtim_timcr2 |= pTimerCtl->DualChannelDacReset;
8005c32: 687b ldr r3, [r7, #4]
8005c34: 691b ldr r3, [r3, #16]
8005c36: 697a ldr r2, [r7, #20]
8005c38: 4313 orrs r3, r2
8005c3a: 617b str r3, [r7, #20]
/* Set the DualChannel DAC Step trigger : requires DCDE enabled */
hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDS);
8005c3c: 697b ldr r3, [r7, #20]
8005c3e: f023 0302 bic.w r3, r3, #2
8005c42: 617b str r3, [r7, #20]
hrtim_timcr2 |= pTimerCtl->DualChannelDacStep;
8005c44: 687b ldr r3, [r7, #4]
8005c46: 695b ldr r3, [r3, #20]
8005c48: 697a ldr r2, [r7, #20]
8005c4a: 4313 orrs r3, r2
8005c4c: 617b str r3, [r7, #20]
/* Enable the DualChannel DAC trigger */
hrtim_timcr2 &= ~(HRTIM_TIMCR2_DCDE);
8005c4e: 697b ldr r3, [r7, #20]
8005c50: f023 0301 bic.w r3, r3, #1
8005c54: 617b str r3, [r7, #20]
hrtim_timcr2 |= pTimerCtl->DualChannelDacEnable;
8005c56: 687b ldr r3, [r7, #4]
8005c58: 699b ldr r3, [r3, #24]
8005c5a: 697a ldr r2, [r7, #20]
8005c5c: 4313 orrs r3, r2
8005c5e: 617b str r3, [r7, #20]
}
/* Update the HRTIM registers */
hhrtim->Instance->sTimerxRegs[TimerIdx].TIMxCR2 = hrtim_timcr2;
8005c60: 68fb ldr r3, [r7, #12]
8005c62: 681a ldr r2, [r3, #0]
8005c64: 68bb ldr r3, [r7, #8]
8005c66: 01db lsls r3, r3, #7
8005c68: 4413 add r3, r2
8005c6a: 33ec adds r3, #236 @ 0xec
8005c6c: 697a ldr r2, [r7, #20]
8005c6e: 601a str r2, [r3, #0]
}
8005c70: bf00 nop
8005c72: 371c adds r7, #28
8005c74: 46bd mov sp, r7
8005c76: f85d 7b04 ldr.w r7, [sp], #4
8005c7a: 4770 bx lr
08005c7c <HRTIM_OutputConfig>:
*/
static void HRTIM_OutputConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx,
uint32_t Output,
const HRTIM_OutputCfgTypeDef *pOutputCfg)
{
8005c7c: b480 push {r7}
8005c7e: b089 sub sp, #36 @ 0x24
8005c80: af00 add r7, sp, #0
8005c82: 60f8 str r0, [r7, #12]
8005c84: 60b9 str r1, [r7, #8]
8005c86: 607a str r2, [r7, #4]
8005c88: 603b str r3, [r7, #0]
uint32_t hrtim_outr;
uint32_t hrtim_dtr;
uint32_t shift = 0U;
8005c8a: 2300 movs r3, #0
8005c8c: 61bb str r3, [r7, #24]
hrtim_outr = hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR;
8005c8e: 68fb ldr r3, [r7, #12]
8005c90: 681a ldr r2, [r3, #0]
8005c92: 68bb ldr r3, [r7, #8]
8005c94: 01db lsls r3, r3, #7
8005c96: 4413 add r3, r2
8005c98: 33e4 adds r3, #228 @ 0xe4
8005c9a: 681b ldr r3, [r3, #0]
8005c9c: 61fb str r3, [r7, #28]
hrtim_dtr = hhrtim->Instance->sTimerxRegs[TimerIdx].DTxR;
8005c9e: 68fb ldr r3, [r7, #12]
8005ca0: 681a ldr r2, [r3, #0]
8005ca2: 68bb ldr r3, [r7, #8]
8005ca4: 01db lsls r3, r3, #7
8005ca6: 4413 add r3, r2
8005ca8: 33b8 adds r3, #184 @ 0xb8
8005caa: 681b ldr r3, [r3, #0]
8005cac: 617b str r3, [r7, #20]
switch (Output)
8005cae: 687b ldr r3, [r7, #4]
8005cb0: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8005cb4: d05d beq.n 8005d72 <HRTIM_OutputConfig+0xf6>
8005cb6: 687b ldr r3, [r7, #4]
8005cb8: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8005cbc: d86e bhi.n 8005d9c <HRTIM_OutputConfig+0x120>
8005cbe: 687b ldr r3, [r7, #4]
8005cc0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8005cc4: d042 beq.n 8005d4c <HRTIM_OutputConfig+0xd0>
8005cc6: 687b ldr r3, [r7, #4]
8005cc8: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8005ccc: d866 bhi.n 8005d9c <HRTIM_OutputConfig+0x120>
8005cce: 687b ldr r3, [r7, #4]
8005cd0: f5b3 7f00 cmp.w r3, #512 @ 0x200
8005cd4: d04d beq.n 8005d72 <HRTIM_OutputConfig+0xf6>
8005cd6: 687b ldr r3, [r7, #4]
8005cd8: f5b3 7f00 cmp.w r3, #512 @ 0x200
8005cdc: d85e bhi.n 8005d9c <HRTIM_OutputConfig+0x120>
8005cde: 687b ldr r3, [r7, #4]
8005ce0: f5b3 7f80 cmp.w r3, #256 @ 0x100
8005ce4: d032 beq.n 8005d4c <HRTIM_OutputConfig+0xd0>
8005ce6: 687b ldr r3, [r7, #4]
8005ce8: f5b3 7f80 cmp.w r3, #256 @ 0x100
8005cec: d856 bhi.n 8005d9c <HRTIM_OutputConfig+0x120>
8005cee: 687b ldr r3, [r7, #4]
8005cf0: 2b80 cmp r3, #128 @ 0x80
8005cf2: d03e beq.n 8005d72 <HRTIM_OutputConfig+0xf6>
8005cf4: 687b ldr r3, [r7, #4]
8005cf6: 2b80 cmp r3, #128 @ 0x80
8005cf8: d850 bhi.n 8005d9c <HRTIM_OutputConfig+0x120>
8005cfa: 687b ldr r3, [r7, #4]
8005cfc: 2b40 cmp r3, #64 @ 0x40
8005cfe: d025 beq.n 8005d4c <HRTIM_OutputConfig+0xd0>
8005d00: 687b ldr r3, [r7, #4]
8005d02: 2b40 cmp r3, #64 @ 0x40
8005d04: d84a bhi.n 8005d9c <HRTIM_OutputConfig+0x120>
8005d06: 687b ldr r3, [r7, #4]
8005d08: 2b01 cmp r3, #1
8005d0a: d01f beq.n 8005d4c <HRTIM_OutputConfig+0xd0>
8005d0c: 687b ldr r3, [r7, #4]
8005d0e: 2b00 cmp r3, #0
8005d10: d044 beq.n 8005d9c <HRTIM_OutputConfig+0x120>
8005d12: 687b ldr r3, [r7, #4]
8005d14: 2b20 cmp r3, #32
8005d16: d841 bhi.n 8005d9c <HRTIM_OutputConfig+0x120>
8005d18: 687b ldr r3, [r7, #4]
8005d1a: 2b02 cmp r3, #2
8005d1c: d33e bcc.n 8005d9c <HRTIM_OutputConfig+0x120>
8005d1e: 687b ldr r3, [r7, #4]
8005d20: 3b02 subs r3, #2
8005d22: 2201 movs r2, #1
8005d24: 409a lsls r2, r3
8005d26: 4b48 ldr r3, [pc, #288] @ (8005e48 <HRTIM_OutputConfig+0x1cc>)
8005d28: 4013 ands r3, r2
8005d2a: 2b00 cmp r3, #0
8005d2c: bf14 ite ne
8005d2e: 2301 movne r3, #1
8005d30: 2300 moveq r3, #0
8005d32: b2db uxtb r3, r3
8005d34: 2b00 cmp r3, #0
8005d36: d11c bne.n 8005d72 <HRTIM_OutputConfig+0xf6>
8005d38: f244 0304 movw r3, #16388 @ 0x4004
8005d3c: 4013 ands r3, r2
8005d3e: 2b00 cmp r3, #0
8005d40: bf14 ite ne
8005d42: 2301 movne r3, #1
8005d44: 2300 moveq r3, #0
8005d46: b2db uxtb r3, r3
8005d48: 2b00 cmp r3, #0
8005d4a: d027 beq.n 8005d9c <HRTIM_OutputConfig+0x120>
case HRTIM_OUTPUT_TD1:
case HRTIM_OUTPUT_TE1:
case HRTIM_OUTPUT_TF1:
{
/* Set the output set/reset crossbar */
hhrtim->Instance->sTimerxRegs[TimerIdx].SETx1R = pOutputCfg->SetSource;
8005d4c: 68fb ldr r3, [r7, #12]
8005d4e: 6819 ldr r1, [r3, #0]
8005d50: 683b ldr r3, [r7, #0]
8005d52: 685a ldr r2, [r3, #4]
8005d54: 68bb ldr r3, [r7, #8]
8005d56: 01db lsls r3, r3, #7
8005d58: 440b add r3, r1
8005d5a: 33bc adds r3, #188 @ 0xbc
8005d5c: 601a str r2, [r3, #0]
hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
8005d5e: 68fb ldr r3, [r7, #12]
8005d60: 6819 ldr r1, [r3, #0]
8005d62: 683b ldr r3, [r7, #0]
8005d64: 689a ldr r2, [r3, #8]
8005d66: 68bb ldr r3, [r7, #8]
8005d68: 01db lsls r3, r3, #7
8005d6a: 440b add r3, r1
8005d6c: 33c0 adds r3, #192 @ 0xc0
8005d6e: 601a str r2, [r3, #0]
break;
8005d70: e015 b.n 8005d9e <HRTIM_OutputConfig+0x122>
case HRTIM_OUTPUT_TD2:
case HRTIM_OUTPUT_TE2:
case HRTIM_OUTPUT_TF2:
{
/* Set the output set/reset crossbar */
hhrtim->Instance->sTimerxRegs[TimerIdx].SETx2R = pOutputCfg->SetSource;
8005d72: 68fb ldr r3, [r7, #12]
8005d74: 6819 ldr r1, [r3, #0]
8005d76: 683b ldr r3, [r7, #0]
8005d78: 685a ldr r2, [r3, #4]
8005d7a: 68bb ldr r3, [r7, #8]
8005d7c: 01db lsls r3, r3, #7
8005d7e: 440b add r3, r1
8005d80: 33c4 adds r3, #196 @ 0xc4
8005d82: 601a str r2, [r3, #0]
hhrtim->Instance->sTimerxRegs[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
8005d84: 68fb ldr r3, [r7, #12]
8005d86: 6819 ldr r1, [r3, #0]
8005d88: 683b ldr r3, [r7, #0]
8005d8a: 689a ldr r2, [r3, #8]
8005d8c: 68bb ldr r3, [r7, #8]
8005d8e: 01db lsls r3, r3, #7
8005d90: 440b add r3, r1
8005d92: 33c8 adds r3, #200 @ 0xc8
8005d94: 601a str r2, [r3, #0]
shift = 16U;
8005d96: 2310 movs r3, #16
8005d98: 61bb str r3, [r7, #24]
break;
8005d9a: e000 b.n 8005d9e <HRTIM_OutputConfig+0x122>
}
default:
break;
8005d9c: bf00 nop
hrtim_outr &= ~((HRTIM_OUTR_POL1 |
HRTIM_OUTR_IDLM1 |
HRTIM_OUTR_IDLES1 |
HRTIM_OUTR_FAULT1 |
HRTIM_OUTR_CHP1 |
HRTIM_OUTR_DIDL1) << shift);
8005d9e: 22fe movs r2, #254 @ 0xfe
8005da0: 69bb ldr r3, [r7, #24]
8005da2: fa02 f303 lsl.w r3, r2, r3
hrtim_outr &= ~((HRTIM_OUTR_POL1 |
8005da6: 43db mvns r3, r3
8005da8: 69fa ldr r2, [r7, #28]
8005daa: 4013 ands r3, r2
8005dac: 61fb str r3, [r7, #28]
/* Set the polarity */
hrtim_outr |= (pOutputCfg->Polarity << shift);
8005dae: 683b ldr r3, [r7, #0]
8005db0: 681a ldr r2, [r3, #0]
8005db2: 69bb ldr r3, [r7, #24]
8005db4: fa02 f303 lsl.w r3, r2, r3
8005db8: 69fa ldr r2, [r7, #28]
8005dba: 4313 orrs r3, r2
8005dbc: 61fb str r3, [r7, #28]
/* Set the IDLE mode */
hrtim_outr |= (pOutputCfg->IdleMode << shift);
8005dbe: 683b ldr r3, [r7, #0]
8005dc0: 68da ldr r2, [r3, #12]
8005dc2: 69bb ldr r3, [r7, #24]
8005dc4: fa02 f303 lsl.w r3, r2, r3
8005dc8: 69fa ldr r2, [r7, #28]
8005dca: 4313 orrs r3, r2
8005dcc: 61fb str r3, [r7, #28]
/* Set the IDLE state */
hrtim_outr |= (pOutputCfg->IdleLevel << shift);
8005dce: 683b ldr r3, [r7, #0]
8005dd0: 691a ldr r2, [r3, #16]
8005dd2: 69bb ldr r3, [r7, #24]
8005dd4: fa02 f303 lsl.w r3, r2, r3
8005dd8: 69fa ldr r2, [r7, #28]
8005dda: 4313 orrs r3, r2
8005ddc: 61fb str r3, [r7, #28]
/* Set the FAULT state */
hrtim_outr |= (pOutputCfg->FaultLevel << shift);
8005dde: 683b ldr r3, [r7, #0]
8005de0: 695a ldr r2, [r3, #20]
8005de2: 69bb ldr r3, [r7, #24]
8005de4: fa02 f303 lsl.w r3, r2, r3
8005de8: 69fa ldr r2, [r7, #28]
8005dea: 4313 orrs r3, r2
8005dec: 61fb str r3, [r7, #28]
/* Set the chopper mode */
hrtim_outr |= (pOutputCfg->ChopperModeEnable << shift);
8005dee: 683b ldr r3, [r7, #0]
8005df0: 699a ldr r2, [r3, #24]
8005df2: 69bb ldr r3, [r7, #24]
8005df4: fa02 f303 lsl.w r3, r2, r3
8005df8: 69fa ldr r2, [r7, #28]
8005dfa: 4313 orrs r3, r2
8005dfc: 61fb str r3, [r7, #28]
state during a burst mode operation is allowed only under the following
conditions:
- the outputs is active during the burst mode (IDLES=1U)
- positive deadtimes (SDTR/SDTF set to 0U)
*/
if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
8005dfe: 683b ldr r3, [r7, #0]
8005e00: 691b ldr r3, [r3, #16]
8005e02: 2b08 cmp r3, #8
8005e04: d111 bne.n 8005e2a <HRTIM_OutputConfig+0x1ae>
((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
8005e06: 697b ldr r3, [r7, #20]
8005e08: f403 7300 and.w r3, r3, #512 @ 0x200
if ((pOutputCfg->IdleLevel == HRTIM_OUTPUTIDLELEVEL_ACTIVE) &&
8005e0c: 2b00 cmp r3, #0
8005e0e: d10c bne.n 8005e2a <HRTIM_OutputConfig+0x1ae>
((hrtim_dtr & HRTIM_DTR_SDTF) == (uint32_t)RESET))
8005e10: 697b ldr r3, [r7, #20]
8005e12: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
((hrtim_dtr & HRTIM_DTR_SDTR) == (uint32_t)RESET) &&
8005e16: 2b00 cmp r3, #0
8005e18: d107 bne.n 8005e2a <HRTIM_OutputConfig+0x1ae>
{
hrtim_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
8005e1a: 683b ldr r3, [r7, #0]
8005e1c: 69da ldr r2, [r3, #28]
8005e1e: 69bb ldr r3, [r7, #24]
8005e20: fa02 f303 lsl.w r3, r2, r3
8005e24: 69fa ldr r2, [r7, #28]
8005e26: 4313 orrs r3, r2
8005e28: 61fb str r3, [r7, #28]
}
/* Update HRTIM register */
hhrtim->Instance->sTimerxRegs[TimerIdx].OUTxR = hrtim_outr;
8005e2a: 68fb ldr r3, [r7, #12]
8005e2c: 681a ldr r2, [r3, #0]
8005e2e: 68bb ldr r3, [r7, #8]
8005e30: 01db lsls r3, r3, #7
8005e32: 4413 add r3, r2
8005e34: 33e4 adds r3, #228 @ 0xe4
8005e36: 69fa ldr r2, [r7, #28]
8005e38: 601a str r2, [r3, #0]
}
8005e3a: bf00 nop
8005e3c: 3724 adds r7, #36 @ 0x24
8005e3e: 46bd mov sp, r7
8005e40: f85d 7b04 ldr.w r7, [sp], #4
8005e44: 4770 bx lr
8005e46: bf00 nop
8005e48: 40000041 .word 0x40000041
08005e4c <HRTIM_EventConfig>:
* @retval None
*/
static void HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,
uint32_t Event,
const HRTIM_EventCfgTypeDef *pEventCfg)
{
8005e4c: b480 push {r7}
8005e4e: b089 sub sp, #36 @ 0x24
8005e50: af00 add r7, sp, #0
8005e52: 60f8 str r0, [r7, #12]
8005e54: 60b9 str r1, [r7, #8]
8005e56: 607a str r2, [r7, #4]
uint32_t hrtim_eecr1;
uint32_t hrtim_eecr2;
uint32_t hrtim_eecr3;
/* Configure external event channel */
hrtim_eecr1 = hhrtim->Instance->sCommonRegs.EECR1;
8005e58: 68fb ldr r3, [r7, #12]
8005e5a: 681b ldr r3, [r3, #0]
8005e5c: f8d3 33b0 ldr.w r3, [r3, #944] @ 0x3b0
8005e60: 61fb str r3, [r7, #28]
hrtim_eecr2 = hhrtim->Instance->sCommonRegs.EECR2;
8005e62: 68fb ldr r3, [r7, #12]
8005e64: 681b ldr r3, [r3, #0]
8005e66: f8d3 33b4 ldr.w r3, [r3, #948] @ 0x3b4
8005e6a: 61bb str r3, [r7, #24]
hrtim_eecr3 = hhrtim->Instance->sCommonRegs.EECR3;
8005e6c: 68fb ldr r3, [r7, #12]
8005e6e: 681b ldr r3, [r3, #0]
8005e70: f8d3 33b8 ldr.w r3, [r3, #952] @ 0x3b8
8005e74: 617b str r3, [r7, #20]
switch (Event)
8005e76: 68bb ldr r3, [r7, #8]
8005e78: 2b0a cmp r3, #10
8005e7a: f200 8208 bhi.w 800628e <HRTIM_EventConfig+0x442>
8005e7e: a201 add r2, pc, #4 @ (adr r2, 8005e84 <HRTIM_EventConfig+0x38>)
8005e80: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8005e84: 08005eb1 .word 0x08005eb1
8005e88: 08005ed1 .word 0x08005ed1
8005e8c: 08005f27 .word 0x08005f27
8005e90: 08005f83 .word 0x08005f83
8005e94: 08005fe1 .word 0x08005fe1
8005e98: 0800603f .word 0x0800603f
8005e9c: 0800609d .word 0x0800609d
8005ea0: 080060fb .word 0x080060fb
8005ea4: 0800615f .word 0x0800615f
8005ea8: 080061c3 .word 0x080061c3
8005eac: 08006229 .word 0x08006229
{
case HRTIM_EVENT_NONE:
{
/* Update the HRTIM registers */
hhrtim->Instance->sCommonRegs.EECR1 = 0U;
8005eb0: 68fb ldr r3, [r7, #12]
8005eb2: 681b ldr r3, [r3, #0]
8005eb4: 2200 movs r2, #0
8005eb6: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0
hhrtim->Instance->sCommonRegs.EECR2 = 0U;
8005eba: 68fb ldr r3, [r7, #12]
8005ebc: 681b ldr r3, [r3, #0]
8005ebe: 2200 movs r2, #0
8005ec0: f8c3 23b4 str.w r2, [r3, #948] @ 0x3b4
hhrtim->Instance->sCommonRegs.EECR3 = 0U;
8005ec4: 68fb ldr r3, [r7, #12]
8005ec6: 681b ldr r3, [r3, #0]
8005ec8: 2200 movs r2, #0
8005eca: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8
break;
8005ece: e1df b.n 8006290 <HRTIM_EventConfig+0x444>
}
case HRTIM_EVENT_1:
{
hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
8005ed0: 69fb ldr r3, [r7, #28]
8005ed2: f023 033f bic.w r3, r3, #63 @ 0x3f
8005ed6: 61fb str r3, [r7, #28]
hrtim_eecr1 |= (pEventCfg->Source & HRTIM_EECR1_EE1SRC);
8005ed8: 687b ldr r3, [r7, #4]
8005eda: 681b ldr r3, [r3, #0]
8005edc: f003 0303 and.w r3, r3, #3
8005ee0: 69fa ldr r2, [r7, #28]
8005ee2: 4313 orrs r3, r2
8005ee4: 61fb str r3, [r7, #28]
hrtim_eecr1 |= (pEventCfg->Polarity & HRTIM_EECR1_EE1POL);
8005ee6: 687b ldr r3, [r7, #4]
8005ee8: 685b ldr r3, [r3, #4]
8005eea: f003 0304 and.w r3, r3, #4
8005eee: 69fa ldr r2, [r7, #28]
8005ef0: 4313 orrs r3, r2
8005ef2: 61fb str r3, [r7, #28]
hrtim_eecr1 |= (pEventCfg->Sensitivity & HRTIM_EECR1_EE1SNS);
8005ef4: 687b ldr r3, [r7, #4]
8005ef6: 689b ldr r3, [r3, #8]
8005ef8: f003 0318 and.w r3, r3, #24
8005efc: 69fa ldr r2, [r7, #28]
8005efe: 4313 orrs r3, r2
8005f00: 61fb str r3, [r7, #28]
/* Update the HRTIM registers (all bitfields but EE1FAST bit) */
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8005f02: 68fb ldr r3, [r7, #12]
8005f04: 681b ldr r3, [r3, #0]
8005f06: 69fa ldr r2, [r7, #28]
8005f08: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0
/* Update the HRTIM registers (EE1FAST bit) */
hrtim_eecr1 |= (pEventCfg->FastMode & HRTIM_EECR1_EE1FAST);
8005f0c: 687b ldr r3, [r7, #4]
8005f0e: 691b ldr r3, [r3, #16]
8005f10: f003 0320 and.w r3, r3, #32
8005f14: 69fa ldr r2, [r7, #28]
8005f16: 4313 orrs r3, r2
8005f18: 61fb str r3, [r7, #28]
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8005f1a: 68fb ldr r3, [r7, #12]
8005f1c: 681b ldr r3, [r3, #0]
8005f1e: 69fa ldr r2, [r7, #28]
8005f20: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0
break;
8005f24: e1b4 b.n 8006290 <HRTIM_EventConfig+0x444>
}
case HRTIM_EVENT_2:
{
hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
8005f26: 69fb ldr r3, [r7, #28]
8005f28: f423 637c bic.w r3, r3, #4032 @ 0xfc0
8005f2c: 61fb str r3, [r7, #28]
hrtim_eecr1 |= ((pEventCfg->Source << 6U) & HRTIM_EECR1_EE2SRC);
8005f2e: 687b ldr r3, [r7, #4]
8005f30: 681b ldr r3, [r3, #0]
8005f32: 019b lsls r3, r3, #6
8005f34: b2db uxtb r3, r3
8005f36: 69fa ldr r2, [r7, #28]
8005f38: 4313 orrs r3, r2
8005f3a: 61fb str r3, [r7, #28]
hrtim_eecr1 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR1_EE2POL);
8005f3c: 687b ldr r3, [r7, #4]
8005f3e: 685b ldr r3, [r3, #4]
8005f40: 019b lsls r3, r3, #6
8005f42: f403 7380 and.w r3, r3, #256 @ 0x100
8005f46: 69fa ldr r2, [r7, #28]
8005f48: 4313 orrs r3, r2
8005f4a: 61fb str r3, [r7, #28]
hrtim_eecr1 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR1_EE2SNS);
8005f4c: 687b ldr r3, [r7, #4]
8005f4e: 689b ldr r3, [r3, #8]
8005f50: 019b lsls r3, r3, #6
8005f52: f403 63c0 and.w r3, r3, #1536 @ 0x600
8005f56: 69fa ldr r2, [r7, #28]
8005f58: 4313 orrs r3, r2
8005f5a: 61fb str r3, [r7, #28]
/* Update the HRTIM registers (all bitfields but EE2FAST bit) */
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8005f5c: 68fb ldr r3, [r7, #12]
8005f5e: 681b ldr r3, [r3, #0]
8005f60: 69fa ldr r2, [r7, #28]
8005f62: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0
/* Update the HRTIM registers (EE2FAST bit) */
hrtim_eecr1 |= ((pEventCfg->FastMode << 6U) & HRTIM_EECR1_EE2FAST);
8005f66: 687b ldr r3, [r7, #4]
8005f68: 691b ldr r3, [r3, #16]
8005f6a: 019b lsls r3, r3, #6
8005f6c: f403 6300 and.w r3, r3, #2048 @ 0x800
8005f70: 69fa ldr r2, [r7, #28]
8005f72: 4313 orrs r3, r2
8005f74: 61fb str r3, [r7, #28]
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8005f76: 68fb ldr r3, [r7, #12]
8005f78: 681b ldr r3, [r3, #0]
8005f7a: 69fa ldr r2, [r7, #28]
8005f7c: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0
break;
8005f80: e186 b.n 8006290 <HRTIM_EventConfig+0x444>
}
case HRTIM_EVENT_3:
{
hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
8005f82: 69fb ldr r3, [r7, #28]
8005f84: f423 337c bic.w r3, r3, #258048 @ 0x3f000
8005f88: 61fb str r3, [r7, #28]
hrtim_eecr1 |= ((pEventCfg->Source << 12U) & HRTIM_EECR1_EE3SRC);
8005f8a: 687b ldr r3, [r7, #4]
8005f8c: 681b ldr r3, [r3, #0]
8005f8e: 031b lsls r3, r3, #12
8005f90: f403 5340 and.w r3, r3, #12288 @ 0x3000
8005f94: 69fa ldr r2, [r7, #28]
8005f96: 4313 orrs r3, r2
8005f98: 61fb str r3, [r7, #28]
hrtim_eecr1 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR1_EE3POL);
8005f9a: 687b ldr r3, [r7, #4]
8005f9c: 685b ldr r3, [r3, #4]
8005f9e: 031b lsls r3, r3, #12
8005fa0: f403 4380 and.w r3, r3, #16384 @ 0x4000
8005fa4: 69fa ldr r2, [r7, #28]
8005fa6: 4313 orrs r3, r2
8005fa8: 61fb str r3, [r7, #28]
hrtim_eecr1 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR1_EE3SNS);
8005faa: 687b ldr r3, [r7, #4]
8005fac: 689b ldr r3, [r3, #8]
8005fae: 031b lsls r3, r3, #12
8005fb0: f403 33c0 and.w r3, r3, #98304 @ 0x18000
8005fb4: 69fa ldr r2, [r7, #28]
8005fb6: 4313 orrs r3, r2
8005fb8: 61fb str r3, [r7, #28]
/* Update the HRTIM registers (all bitfields but EE3FAST bit) */
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8005fba: 68fb ldr r3, [r7, #12]
8005fbc: 681b ldr r3, [r3, #0]
8005fbe: 69fa ldr r2, [r7, #28]
8005fc0: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0
/* Update the HRTIM registers (EE3FAST bit) */
hrtim_eecr1 |= ((pEventCfg->FastMode << 12U) & HRTIM_EECR1_EE3FAST);
8005fc4: 687b ldr r3, [r7, #4]
8005fc6: 691b ldr r3, [r3, #16]
8005fc8: 031b lsls r3, r3, #12
8005fca: f403 3300 and.w r3, r3, #131072 @ 0x20000
8005fce: 69fa ldr r2, [r7, #28]
8005fd0: 4313 orrs r3, r2
8005fd2: 61fb str r3, [r7, #28]
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8005fd4: 68fb ldr r3, [r7, #12]
8005fd6: 681b ldr r3, [r3, #0]
8005fd8: 69fa ldr r2, [r7, #28]
8005fda: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0
break;
8005fde: e157 b.n 8006290 <HRTIM_EventConfig+0x444>
}
case HRTIM_EVENT_4:
{
hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
8005fe0: 69fb ldr r3, [r7, #28]
8005fe2: f423 037c bic.w r3, r3, #16515072 @ 0xfc0000
8005fe6: 61fb str r3, [r7, #28]
hrtim_eecr1 |= ((pEventCfg->Source << 18U) & HRTIM_EECR1_EE4SRC);
8005fe8: 687b ldr r3, [r7, #4]
8005fea: 681b ldr r3, [r3, #0]
8005fec: 049b lsls r3, r3, #18
8005fee: f403 2340 and.w r3, r3, #786432 @ 0xc0000
8005ff2: 69fa ldr r2, [r7, #28]
8005ff4: 4313 orrs r3, r2
8005ff6: 61fb str r3, [r7, #28]
hrtim_eecr1 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR1_EE4POL);
8005ff8: 687b ldr r3, [r7, #4]
8005ffa: 685b ldr r3, [r3, #4]
8005ffc: 049b lsls r3, r3, #18
8005ffe: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8006002: 69fa ldr r2, [r7, #28]
8006004: 4313 orrs r3, r2
8006006: 61fb str r3, [r7, #28]
hrtim_eecr1 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR1_EE4SNS);
8006008: 687b ldr r3, [r7, #4]
800600a: 689b ldr r3, [r3, #8]
800600c: 049b lsls r3, r3, #18
800600e: f403 03c0 and.w r3, r3, #6291456 @ 0x600000
8006012: 69fa ldr r2, [r7, #28]
8006014: 4313 orrs r3, r2
8006016: 61fb str r3, [r7, #28]
/* Update the HRTIM registers (all bitfields but EE4FAST bit) */
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8006018: 68fb ldr r3, [r7, #12]
800601a: 681b ldr r3, [r3, #0]
800601c: 69fa ldr r2, [r7, #28]
800601e: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0
/* Update the HRTIM registers (EE4FAST bit) */
hrtim_eecr1 |= ((pEventCfg->FastMode << 18U) & HRTIM_EECR1_EE4FAST);
8006022: 687b ldr r3, [r7, #4]
8006024: 691b ldr r3, [r3, #16]
8006026: 049b lsls r3, r3, #18
8006028: f403 0300 and.w r3, r3, #8388608 @ 0x800000
800602c: 69fa ldr r2, [r7, #28]
800602e: 4313 orrs r3, r2
8006030: 61fb str r3, [r7, #28]
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8006032: 68fb ldr r3, [r7, #12]
8006034: 681b ldr r3, [r3, #0]
8006036: 69fa ldr r2, [r7, #28]
8006038: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0
break;
800603c: e128 b.n 8006290 <HRTIM_EventConfig+0x444>
}
case HRTIM_EVENT_5:
{
hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
800603e: 69fb ldr r3, [r7, #28]
8006040: f023 537c bic.w r3, r3, #1056964608 @ 0x3f000000
8006044: 61fb str r3, [r7, #28]
hrtim_eecr1 |= ((pEventCfg->Source << 24U) & HRTIM_EECR1_EE5SRC);
8006046: 687b ldr r3, [r7, #4]
8006048: 681b ldr r3, [r3, #0]
800604a: 061b lsls r3, r3, #24
800604c: f003 7340 and.w r3, r3, #50331648 @ 0x3000000
8006050: 69fa ldr r2, [r7, #28]
8006052: 4313 orrs r3, r2
8006054: 61fb str r3, [r7, #28]
hrtim_eecr1 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR1_EE5POL);
8006056: 687b ldr r3, [r7, #4]
8006058: 685b ldr r3, [r3, #4]
800605a: 061b lsls r3, r3, #24
800605c: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
8006060: 69fa ldr r2, [r7, #28]
8006062: 4313 orrs r3, r2
8006064: 61fb str r3, [r7, #28]
hrtim_eecr1 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR1_EE5SNS);
8006066: 687b ldr r3, [r7, #4]
8006068: 689b ldr r3, [r3, #8]
800606a: 061b lsls r3, r3, #24
800606c: f003 53c0 and.w r3, r3, #402653184 @ 0x18000000
8006070: 69fa ldr r2, [r7, #28]
8006072: 4313 orrs r3, r2
8006074: 61fb str r3, [r7, #28]
/* Update the HRTIM registers (all bitfields but EE5FAST bit) */
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8006076: 68fb ldr r3, [r7, #12]
8006078: 681b ldr r3, [r3, #0]
800607a: 69fa ldr r2, [r7, #28]
800607c: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0
/* Update the HRTIM registers (EE5FAST bit) */
hrtim_eecr1 |= ((pEventCfg->FastMode << 24U) & HRTIM_EECR1_EE5FAST);
8006080: 687b ldr r3, [r7, #4]
8006082: 691b ldr r3, [r3, #16]
8006084: 061b lsls r3, r3, #24
8006086: f003 5300 and.w r3, r3, #536870912 @ 0x20000000
800608a: 69fa ldr r2, [r7, #28]
800608c: 4313 orrs r3, r2
800608e: 61fb str r3, [r7, #28]
hhrtim->Instance->sCommonRegs.EECR1 = hrtim_eecr1;
8006090: 68fb ldr r3, [r7, #12]
8006092: 681b ldr r3, [r3, #0]
8006094: 69fa ldr r2, [r7, #28]
8006096: f8c3 23b0 str.w r2, [r3, #944] @ 0x3b0
break;
800609a: e0f9 b.n 8006290 <HRTIM_EventConfig+0x444>
}
case HRTIM_EVENT_6:
{
hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
800609c: 69bb ldr r3, [r7, #24]
800609e: f023 031f bic.w r3, r3, #31
80060a2: 61bb str r3, [r7, #24]
hrtim_eecr2 |= (pEventCfg->Source & HRTIM_EECR2_EE6SRC);
80060a4: 687b ldr r3, [r7, #4]
80060a6: 681b ldr r3, [r3, #0]
80060a8: f003 0303 and.w r3, r3, #3
80060ac: 69ba ldr r2, [r7, #24]
80060ae: 4313 orrs r3, r2
80060b0: 61bb str r3, [r7, #24]
hrtim_eecr2 |= (pEventCfg->Polarity & HRTIM_EECR2_EE6POL);
80060b2: 687b ldr r3, [r7, #4]
80060b4: 685b ldr r3, [r3, #4]
80060b6: f003 0304 and.w r3, r3, #4
80060ba: 69ba ldr r2, [r7, #24]
80060bc: 4313 orrs r3, r2
80060be: 61bb str r3, [r7, #24]
hrtim_eecr2 |= (pEventCfg->Sensitivity & HRTIM_EECR2_EE6SNS);
80060c0: 687b ldr r3, [r7, #4]
80060c2: 689b ldr r3, [r3, #8]
80060c4: f003 0318 and.w r3, r3, #24
80060c8: 69ba ldr r2, [r7, #24]
80060ca: 4313 orrs r3, r2
80060cc: 61bb str r3, [r7, #24]
hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
80060ce: 697b ldr r3, [r7, #20]
80060d0: f023 030f bic.w r3, r3, #15
80060d4: 617b str r3, [r7, #20]
hrtim_eecr3 |= (pEventCfg->Filter & HRTIM_EECR3_EE6F);
80060d6: 687b ldr r3, [r7, #4]
80060d8: 68db ldr r3, [r3, #12]
80060da: f003 030f and.w r3, r3, #15
80060de: 697a ldr r2, [r7, #20]
80060e0: 4313 orrs r3, r2
80060e2: 617b str r3, [r7, #20]
/* Update the HRTIM registers */
hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
80060e4: 68fb ldr r3, [r7, #12]
80060e6: 681b ldr r3, [r3, #0]
80060e8: 69ba ldr r2, [r7, #24]
80060ea: f8c3 23b4 str.w r2, [r3, #948] @ 0x3b4
hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
80060ee: 68fb ldr r3, [r7, #12]
80060f0: 681b ldr r3, [r3, #0]
80060f2: 697a ldr r2, [r7, #20]
80060f4: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8
break;
80060f8: e0ca b.n 8006290 <HRTIM_EventConfig+0x444>
}
case HRTIM_EVENT_7:
{
hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
80060fa: 69bb ldr r3, [r7, #24]
80060fc: f423 63f8 bic.w r3, r3, #1984 @ 0x7c0
8006100: 61bb str r3, [r7, #24]
hrtim_eecr2 |= ((pEventCfg->Source << 6U) & HRTIM_EECR2_EE7SRC);
8006102: 687b ldr r3, [r7, #4]
8006104: 681b ldr r3, [r3, #0]
8006106: 019b lsls r3, r3, #6
8006108: b2db uxtb r3, r3
800610a: 69ba ldr r2, [r7, #24]
800610c: 4313 orrs r3, r2
800610e: 61bb str r3, [r7, #24]
hrtim_eecr2 |= ((pEventCfg->Polarity << 6U) & HRTIM_EECR2_EE7POL);
8006110: 687b ldr r3, [r7, #4]
8006112: 685b ldr r3, [r3, #4]
8006114: 019b lsls r3, r3, #6
8006116: f403 7380 and.w r3, r3, #256 @ 0x100
800611a: 69ba ldr r2, [r7, #24]
800611c: 4313 orrs r3, r2
800611e: 61bb str r3, [r7, #24]
hrtim_eecr2 |= ((pEventCfg->Sensitivity << 6U) & HRTIM_EECR2_EE7SNS);
8006120: 687b ldr r3, [r7, #4]
8006122: 689b ldr r3, [r3, #8]
8006124: 019b lsls r3, r3, #6
8006126: f403 63c0 and.w r3, r3, #1536 @ 0x600
800612a: 69ba ldr r2, [r7, #24]
800612c: 4313 orrs r3, r2
800612e: 61bb str r3, [r7, #24]
hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
8006130: 697b ldr r3, [r7, #20]
8006132: f423 7370 bic.w r3, r3, #960 @ 0x3c0
8006136: 617b str r3, [r7, #20]
hrtim_eecr3 |= ((pEventCfg->Filter << 6U) & HRTIM_EECR3_EE7F);
8006138: 687b ldr r3, [r7, #4]
800613a: 68db ldr r3, [r3, #12]
800613c: 019b lsls r3, r3, #6
800613e: f403 7370 and.w r3, r3, #960 @ 0x3c0
8006142: 697a ldr r2, [r7, #20]
8006144: 4313 orrs r3, r2
8006146: 617b str r3, [r7, #20]
/* Update the HRTIM registers */
hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8006148: 68fb ldr r3, [r7, #12]
800614a: 681b ldr r3, [r3, #0]
800614c: 69ba ldr r2, [r7, #24]
800614e: f8c3 23b4 str.w r2, [r3, #948] @ 0x3b4
hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8006152: 68fb ldr r3, [r7, #12]
8006154: 681b ldr r3, [r3, #0]
8006156: 697a ldr r2, [r7, #20]
8006158: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8
break;
800615c: e098 b.n 8006290 <HRTIM_EventConfig+0x444>
}
case HRTIM_EVENT_8:
{
hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
800615e: 69bb ldr r3, [r7, #24]
8006160: f423 33f8 bic.w r3, r3, #126976 @ 0x1f000
8006164: 61bb str r3, [r7, #24]
hrtim_eecr2 |= ((pEventCfg->Source << 12U) & HRTIM_EECR2_EE8SRC);
8006166: 687b ldr r3, [r7, #4]
8006168: 681b ldr r3, [r3, #0]
800616a: 031b lsls r3, r3, #12
800616c: f403 5340 and.w r3, r3, #12288 @ 0x3000
8006170: 69ba ldr r2, [r7, #24]
8006172: 4313 orrs r3, r2
8006174: 61bb str r3, [r7, #24]
hrtim_eecr2 |= ((pEventCfg->Polarity << 12U) & HRTIM_EECR2_EE8POL);
8006176: 687b ldr r3, [r7, #4]
8006178: 685b ldr r3, [r3, #4]
800617a: 031b lsls r3, r3, #12
800617c: f403 4380 and.w r3, r3, #16384 @ 0x4000
8006180: 69ba ldr r2, [r7, #24]
8006182: 4313 orrs r3, r2
8006184: 61bb str r3, [r7, #24]
hrtim_eecr2 |= ((pEventCfg->Sensitivity << 12U) & HRTIM_EECR2_EE8SNS);
8006186: 687b ldr r3, [r7, #4]
8006188: 689b ldr r3, [r3, #8]
800618a: 031b lsls r3, r3, #12
800618c: f403 33c0 and.w r3, r3, #98304 @ 0x18000
8006190: 69ba ldr r2, [r7, #24]
8006192: 4313 orrs r3, r2
8006194: 61bb str r3, [r7, #24]
hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
8006196: 697b ldr r3, [r7, #20]
8006198: f423 4370 bic.w r3, r3, #61440 @ 0xf000
800619c: 617b str r3, [r7, #20]
hrtim_eecr3 |= ((pEventCfg->Filter << 12U) & HRTIM_EECR3_EE8F);
800619e: 687b ldr r3, [r7, #4]
80061a0: 68db ldr r3, [r3, #12]
80061a2: 031b lsls r3, r3, #12
80061a4: b29b uxth r3, r3
80061a6: 697a ldr r2, [r7, #20]
80061a8: 4313 orrs r3, r2
80061aa: 617b str r3, [r7, #20]
/* Update the HRTIM registers */
hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
80061ac: 68fb ldr r3, [r7, #12]
80061ae: 681b ldr r3, [r3, #0]
80061b0: 69ba ldr r2, [r7, #24]
80061b2: f8c3 23b4 str.w r2, [r3, #948] @ 0x3b4
hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
80061b6: 68fb ldr r3, [r7, #12]
80061b8: 681b ldr r3, [r3, #0]
80061ba: 697a ldr r2, [r7, #20]
80061bc: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8
break;
80061c0: e066 b.n 8006290 <HRTIM_EventConfig+0x444>
}
case HRTIM_EVENT_9:
{
hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
80061c2: 69bb ldr r3, [r7, #24]
80061c4: f423 03f8 bic.w r3, r3, #8126464 @ 0x7c0000
80061c8: 61bb str r3, [r7, #24]
hrtim_eecr2 |= ((pEventCfg->Source << 18U) & HRTIM_EECR2_EE9SRC);
80061ca: 687b ldr r3, [r7, #4]
80061cc: 681b ldr r3, [r3, #0]
80061ce: 049b lsls r3, r3, #18
80061d0: f403 2340 and.w r3, r3, #786432 @ 0xc0000
80061d4: 69ba ldr r2, [r7, #24]
80061d6: 4313 orrs r3, r2
80061d8: 61bb str r3, [r7, #24]
hrtim_eecr2 |= ((pEventCfg->Polarity << 18U) & HRTIM_EECR2_EE9POL);
80061da: 687b ldr r3, [r7, #4]
80061dc: 685b ldr r3, [r3, #4]
80061de: 049b lsls r3, r3, #18
80061e0: f403 1380 and.w r3, r3, #1048576 @ 0x100000
80061e4: 69ba ldr r2, [r7, #24]
80061e6: 4313 orrs r3, r2
80061e8: 61bb str r3, [r7, #24]
hrtim_eecr2 |= ((pEventCfg->Sensitivity << 18U) & HRTIM_EECR2_EE9SNS);
80061ea: 687b ldr r3, [r7, #4]
80061ec: 689b ldr r3, [r3, #8]
80061ee: 049b lsls r3, r3, #18
80061f0: f403 03c0 and.w r3, r3, #6291456 @ 0x600000
80061f4: 69ba ldr r2, [r7, #24]
80061f6: 4313 orrs r3, r2
80061f8: 61bb str r3, [r7, #24]
hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
80061fa: 697b ldr r3, [r7, #20]
80061fc: f423 1370 bic.w r3, r3, #3932160 @ 0x3c0000
8006200: 617b str r3, [r7, #20]
hrtim_eecr3 |= ((pEventCfg->Filter << 18U) & HRTIM_EECR3_EE9F);
8006202: 687b ldr r3, [r7, #4]
8006204: 68db ldr r3, [r3, #12]
8006206: 049b lsls r3, r3, #18
8006208: f403 1370 and.w r3, r3, #3932160 @ 0x3c0000
800620c: 697a ldr r2, [r7, #20]
800620e: 4313 orrs r3, r2
8006210: 617b str r3, [r7, #20]
/* Update the HRTIM registers */
hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8006212: 68fb ldr r3, [r7, #12]
8006214: 681b ldr r3, [r3, #0]
8006216: 69ba ldr r2, [r7, #24]
8006218: f8c3 23b4 str.w r2, [r3, #948] @ 0x3b4
hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
800621c: 68fb ldr r3, [r7, #12]
800621e: 681b ldr r3, [r3, #0]
8006220: 697a ldr r2, [r7, #20]
8006222: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8
break;
8006226: e033 b.n 8006290 <HRTIM_EventConfig+0x444>
}
case HRTIM_EVENT_10:
{
hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
8006228: 69bb ldr r3, [r7, #24]
800622a: f023 53f8 bic.w r3, r3, #520093696 @ 0x1f000000
800622e: 61bb str r3, [r7, #24]
hrtim_eecr2 |= ((pEventCfg->Source << 24U) & HRTIM_EECR2_EE10SRC);
8006230: 687b ldr r3, [r7, #4]
8006232: 681b ldr r3, [r3, #0]
8006234: 061b lsls r3, r3, #24
8006236: f003 7340 and.w r3, r3, #50331648 @ 0x3000000
800623a: 69ba ldr r2, [r7, #24]
800623c: 4313 orrs r3, r2
800623e: 61bb str r3, [r7, #24]
hrtim_eecr2 |= ((pEventCfg->Polarity << 24U) & HRTIM_EECR2_EE10POL);
8006240: 687b ldr r3, [r7, #4]
8006242: 685b ldr r3, [r3, #4]
8006244: 061b lsls r3, r3, #24
8006246: f003 6380 and.w r3, r3, #67108864 @ 0x4000000
800624a: 69ba ldr r2, [r7, #24]
800624c: 4313 orrs r3, r2
800624e: 61bb str r3, [r7, #24]
hrtim_eecr2 |= ((pEventCfg->Sensitivity << 24U) & HRTIM_EECR2_EE10SNS);
8006250: 687b ldr r3, [r7, #4]
8006252: 689b ldr r3, [r3, #8]
8006254: 061b lsls r3, r3, #24
8006256: f003 53c0 and.w r3, r3, #402653184 @ 0x18000000
800625a: 69ba ldr r2, [r7, #24]
800625c: 4313 orrs r3, r2
800625e: 61bb str r3, [r7, #24]
hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
8006260: 697b ldr r3, [r7, #20]
8006262: f023 6370 bic.w r3, r3, #251658240 @ 0xf000000
8006266: 617b str r3, [r7, #20]
hrtim_eecr3 |= ((pEventCfg->Filter << 24U) & HRTIM_EECR3_EE10F);
8006268: 687b ldr r3, [r7, #4]
800626a: 68db ldr r3, [r3, #12]
800626c: 061b lsls r3, r3, #24
800626e: f003 6370 and.w r3, r3, #251658240 @ 0xf000000
8006272: 697a ldr r2, [r7, #20]
8006274: 4313 orrs r3, r2
8006276: 617b str r3, [r7, #20]
/* Update the HRTIM registers */
hhrtim->Instance->sCommonRegs.EECR2 = hrtim_eecr2;
8006278: 68fb ldr r3, [r7, #12]
800627a: 681b ldr r3, [r3, #0]
800627c: 69ba ldr r2, [r7, #24]
800627e: f8c3 23b4 str.w r2, [r3, #948] @ 0x3b4
hhrtim->Instance->sCommonRegs.EECR3 = hrtim_eecr3;
8006282: 68fb ldr r3, [r7, #12]
8006284: 681b ldr r3, [r3, #0]
8006286: 697a ldr r2, [r7, #20]
8006288: f8c3 23b8 str.w r2, [r3, #952] @ 0x3b8
break;
800628c: e000 b.n 8006290 <HRTIM_EventConfig+0x444>
}
default:
break;
800628e: bf00 nop
}
}
8006290: bf00 nop
8006292: 3724 adds r7, #36 @ 0x24
8006294: 46bd mov sp, r7
8006296: f85d 7b04 ldr.w r7, [sp], #4
800629a: 4770 bx lr
0800629c <HRTIM_ForceRegistersUpdate>:
* @param TimerIdx Timer index
* @retval None
*/
static void HRTIM_ForceRegistersUpdate(HRTIM_HandleTypeDef *hhrtim,
uint32_t TimerIdx)
{
800629c: b480 push {r7}
800629e: b083 sub sp, #12
80062a0: af00 add r7, sp, #0
80062a2: 6078 str r0, [r7, #4]
80062a4: 6039 str r1, [r7, #0]
switch (TimerIdx)
80062a6: 683b ldr r3, [r7, #0]
80062a8: 2b06 cmp r3, #6
80062aa: d85e bhi.n 800636a <HRTIM_ForceRegistersUpdate+0xce>
80062ac: a201 add r2, pc, #4 @ (adr r2, 80062b4 <HRTIM_ForceRegistersUpdate+0x18>)
80062ae: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80062b2: bf00 nop
80062b4: 080062e7 .word 0x080062e7
80062b8: 080062fd .word 0x080062fd
80062bc: 08006313 .word 0x08006313
80062c0: 08006329 .word 0x08006329
80062c4: 0800633f .word 0x0800633f
80062c8: 08006355 .word 0x08006355
80062cc: 080062d1 .word 0x080062d1
{
case HRTIM_TIMERINDEX_MASTER:
{
hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_MSWU;
80062d0: 687b ldr r3, [r7, #4]
80062d2: 681b ldr r3, [r3, #0]
80062d4: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384
80062d8: 687b ldr r3, [r7, #4]
80062da: 681b ldr r3, [r3, #0]
80062dc: f042 0201 orr.w r2, r2, #1
80062e0: f8c3 2384 str.w r2, [r3, #900] @ 0x384
break;
80062e4: e042 b.n 800636c <HRTIM_ForceRegistersUpdate+0xd0>
}
case HRTIM_TIMERINDEX_TIMER_A:
{
hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TASWU;
80062e6: 687b ldr r3, [r7, #4]
80062e8: 681b ldr r3, [r3, #0]
80062ea: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384
80062ee: 687b ldr r3, [r7, #4]
80062f0: 681b ldr r3, [r3, #0]
80062f2: f042 0202 orr.w r2, r2, #2
80062f6: f8c3 2384 str.w r2, [r3, #900] @ 0x384
break;
80062fa: e037 b.n 800636c <HRTIM_ForceRegistersUpdate+0xd0>
}
case HRTIM_TIMERINDEX_TIMER_B:
{
hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TBSWU;
80062fc: 687b ldr r3, [r7, #4]
80062fe: 681b ldr r3, [r3, #0]
8006300: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384
8006304: 687b ldr r3, [r7, #4]
8006306: 681b ldr r3, [r3, #0]
8006308: f042 0204 orr.w r2, r2, #4
800630c: f8c3 2384 str.w r2, [r3, #900] @ 0x384
break;
8006310: e02c b.n 800636c <HRTIM_ForceRegistersUpdate+0xd0>
}
case HRTIM_TIMERINDEX_TIMER_C:
{
hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TCSWU;
8006312: 687b ldr r3, [r7, #4]
8006314: 681b ldr r3, [r3, #0]
8006316: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384
800631a: 687b ldr r3, [r7, #4]
800631c: 681b ldr r3, [r3, #0]
800631e: f042 0208 orr.w r2, r2, #8
8006322: f8c3 2384 str.w r2, [r3, #900] @ 0x384
break;
8006326: e021 b.n 800636c <HRTIM_ForceRegistersUpdate+0xd0>
}
case HRTIM_TIMERINDEX_TIMER_D:
{
hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TDSWU;
8006328: 687b ldr r3, [r7, #4]
800632a: 681b ldr r3, [r3, #0]
800632c: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384
8006330: 687b ldr r3, [r7, #4]
8006332: 681b ldr r3, [r3, #0]
8006334: f042 0210 orr.w r2, r2, #16
8006338: f8c3 2384 str.w r2, [r3, #900] @ 0x384
break;
800633c: e016 b.n 800636c <HRTIM_ForceRegistersUpdate+0xd0>
}
case HRTIM_TIMERINDEX_TIMER_E:
{
hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TESWU;
800633e: 687b ldr r3, [r7, #4]
8006340: 681b ldr r3, [r3, #0]
8006342: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384
8006346: 687b ldr r3, [r7, #4]
8006348: 681b ldr r3, [r3, #0]
800634a: f042 0220 orr.w r2, r2, #32
800634e: f8c3 2384 str.w r2, [r3, #900] @ 0x384
break;
8006352: e00b b.n 800636c <HRTIM_ForceRegistersUpdate+0xd0>
}
case HRTIM_TIMERINDEX_TIMER_F:
{
hhrtim->Instance->sCommonRegs.CR2 |= HRTIM_CR2_TFSWU;
8006354: 687b ldr r3, [r7, #4]
8006356: 681b ldr r3, [r3, #0]
8006358: f8d3 2384 ldr.w r2, [r3, #900] @ 0x384
800635c: 687b ldr r3, [r7, #4]
800635e: 681b ldr r3, [r3, #0]
8006360: f042 0240 orr.w r2, r2, #64 @ 0x40
8006364: f8c3 2384 str.w r2, [r3, #900] @ 0x384
break;
8006368: e000 b.n 800636c <HRTIM_ForceRegistersUpdate+0xd0>
}
default:
break;
800636a: bf00 nop
}
}
800636c: bf00 nop
800636e: 370c adds r7, #12
8006370: 46bd mov sp, r7
8006372: f85d 7b04 ldr.w r7, [sp], #4
8006376: 4770 bx lr
08006378 <HAL_PWREx_ControlVoltageScaling>:
* cleared before returning the status. If the flag is not cleared within
* 50 microseconds, HAL_TIMEOUT status is reported.
* @retval HAL Status
*/
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
{
8006378: b480 push {r7}
800637a: b085 sub sp, #20
800637c: af00 add r7, sp, #0
800637e: 6078 str r0, [r7, #4]
uint32_t wait_loop_index;
assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling));
if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST)
8006380: 687b ldr r3, [r7, #4]
8006382: 2b00 cmp r3, #0
8006384: d141 bne.n 800640a <HAL_PWREx_ControlVoltageScaling+0x92>
{
/* If current range is range 2 */
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
8006386: 4b4b ldr r3, [pc, #300] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8006388: 681b ldr r3, [r3, #0]
800638a: f403 63c0 and.w r3, r3, #1536 @ 0x600
800638e: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8006392: d131 bne.n 80063f8 <HAL_PWREx_ControlVoltageScaling+0x80>
{
/* Make sure Range 1 Boost is enabled */
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
8006394: 4b47 ldr r3, [pc, #284] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8006396: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
800639a: 4a46 ldr r2, [pc, #280] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800639c: f423 7380 bic.w r3, r3, #256 @ 0x100
80063a0: f8c2 3080 str.w r3, [r2, #128] @ 0x80
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
80063a4: 4b43 ldr r3, [pc, #268] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80063a6: 681b ldr r3, [r3, #0]
80063a8: f423 63c0 bic.w r3, r3, #1536 @ 0x600
80063ac: 4a41 ldr r2, [pc, #260] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80063ae: f443 7300 orr.w r3, r3, #512 @ 0x200
80063b2: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
80063b4: 4b40 ldr r3, [pc, #256] @ (80064b8 <HAL_PWREx_ControlVoltageScaling+0x140>)
80063b6: 681b ldr r3, [r3, #0]
80063b8: 2232 movs r2, #50 @ 0x32
80063ba: fb02 f303 mul.w r3, r2, r3
80063be: 4a3f ldr r2, [pc, #252] @ (80064bc <HAL_PWREx_ControlVoltageScaling+0x144>)
80063c0: fba2 2303 umull r2, r3, r2, r3
80063c4: 0c9b lsrs r3, r3, #18
80063c6: 3301 adds r3, #1
80063c8: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
80063ca: e002 b.n 80063d2 <HAL_PWREx_ControlVoltageScaling+0x5a>
{
wait_loop_index--;
80063cc: 68fb ldr r3, [r7, #12]
80063ce: 3b01 subs r3, #1
80063d0: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
80063d2: 4b38 ldr r3, [pc, #224] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80063d4: 695b ldr r3, [r3, #20]
80063d6: f403 6380 and.w r3, r3, #1024 @ 0x400
80063da: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80063de: d102 bne.n 80063e6 <HAL_PWREx_ControlVoltageScaling+0x6e>
80063e0: 68fb ldr r3, [r7, #12]
80063e2: 2b00 cmp r3, #0
80063e4: d1f2 bne.n 80063cc <HAL_PWREx_ControlVoltageScaling+0x54>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
80063e6: 4b33 ldr r3, [pc, #204] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80063e8: 695b ldr r3, [r3, #20]
80063ea: f403 6380 and.w r3, r3, #1024 @ 0x400
80063ee: f5b3 6f80 cmp.w r3, #1024 @ 0x400
80063f2: d158 bne.n 80064a6 <HAL_PWREx_ControlVoltageScaling+0x12e>
{
return HAL_TIMEOUT;
80063f4: 2303 movs r3, #3
80063f6: e057 b.n 80064a8 <HAL_PWREx_ControlVoltageScaling+0x130>
}
/* If current range is range 1 normal or boost mode */
else
{
/* Enable Range 1 Boost (no issue if bit already reset) */
CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE);
80063f8: 4b2e ldr r3, [pc, #184] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80063fa: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
80063fe: 4a2d ldr r2, [pc, #180] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8006400: f423 7380 bic.w r3, r3, #256 @ 0x100
8006404: f8c2 3080 str.w r3, [r2, #128] @ 0x80
8006408: e04d b.n 80064a6 <HAL_PWREx_ControlVoltageScaling+0x12e>
}
}
else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1)
800640a: 687b ldr r3, [r7, #4]
800640c: f5b3 7f00 cmp.w r3, #512 @ 0x200
8006410: d141 bne.n 8006496 <HAL_PWREx_ControlVoltageScaling+0x11e>
{
/* If current range is range 2 */
if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2)
8006412: 4b28 ldr r3, [pc, #160] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8006414: 681b ldr r3, [r3, #0]
8006416: f403 63c0 and.w r3, r3, #1536 @ 0x600
800641a: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800641e: d131 bne.n 8006484 <HAL_PWREx_ControlVoltageScaling+0x10c>
{
/* Make sure Range 1 Boost is disabled */
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
8006420: 4b24 ldr r3, [pc, #144] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8006422: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
8006426: 4a23 ldr r2, [pc, #140] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8006428: f443 7380 orr.w r3, r3, #256 @ 0x100
800642c: f8c2 3080 str.w r3, [r2, #128] @ 0x80
/* Set Range 1 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);
8006430: 4b20 ldr r3, [pc, #128] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8006432: 681b ldr r3, [r3, #0]
8006434: f423 63c0 bic.w r3, r3, #1536 @ 0x600
8006438: 4a1e ldr r2, [pc, #120] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800643a: f443 7300 orr.w r3, r3, #512 @ 0x200
800643e: 6013 str r3, [r2, #0]
/* Wait until VOSF is cleared */
wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000U) + 1U;
8006440: 4b1d ldr r3, [pc, #116] @ (80064b8 <HAL_PWREx_ControlVoltageScaling+0x140>)
8006442: 681b ldr r3, [r3, #0]
8006444: 2232 movs r2, #50 @ 0x32
8006446: fb02 f303 mul.w r3, r2, r3
800644a: 4a1c ldr r2, [pc, #112] @ (80064bc <HAL_PWREx_ControlVoltageScaling+0x144>)
800644c: fba2 2303 umull r2, r3, r2, r3
8006450: 0c9b lsrs r3, r3, #18
8006452: 3301 adds r3, #1
8006454: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
8006456: e002 b.n 800645e <HAL_PWREx_ControlVoltageScaling+0xe6>
{
wait_loop_index--;
8006458: 68fb ldr r3, [r7, #12]
800645a: 3b01 subs r3, #1
800645c: 60fb str r3, [r7, #12]
while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) && (wait_loop_index != 0U))
800645e: 4b15 ldr r3, [pc, #84] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8006460: 695b ldr r3, [r3, #20]
8006462: f403 6380 and.w r3, r3, #1024 @ 0x400
8006466: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800646a: d102 bne.n 8006472 <HAL_PWREx_ControlVoltageScaling+0xfa>
800646c: 68fb ldr r3, [r7, #12]
800646e: 2b00 cmp r3, #0
8006470: d1f2 bne.n 8006458 <HAL_PWREx_ControlVoltageScaling+0xe0>
}
if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))
8006472: 4b10 ldr r3, [pc, #64] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8006474: 695b ldr r3, [r3, #20]
8006476: f403 6380 and.w r3, r3, #1024 @ 0x400
800647a: f5b3 6f80 cmp.w r3, #1024 @ 0x400
800647e: d112 bne.n 80064a6 <HAL_PWREx_ControlVoltageScaling+0x12e>
{
return HAL_TIMEOUT;
8006480: 2303 movs r3, #3
8006482: e011 b.n 80064a8 <HAL_PWREx_ControlVoltageScaling+0x130>
}
/* If current range is range 1 normal or boost mode */
else
{
/* Disable Range 1 Boost (no issue if bit already set) */
SET_BIT(PWR->CR5, PWR_CR5_R1MODE);
8006484: 4b0b ldr r3, [pc, #44] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8006486: f8d3 3080 ldr.w r3, [r3, #128] @ 0x80
800648a: 4a0a ldr r2, [pc, #40] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
800648c: f443 7380 orr.w r3, r3, #256 @ 0x100
8006490: f8c2 3080 str.w r3, [r2, #128] @ 0x80
8006494: e007 b.n 80064a6 <HAL_PWREx_ControlVoltageScaling+0x12e>
}
}
else
{
/* Set Range 2 */
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2);
8006496: 4b07 ldr r3, [pc, #28] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
8006498: 681b ldr r3, [r3, #0]
800649a: f423 63c0 bic.w r3, r3, #1536 @ 0x600
800649e: 4a05 ldr r2, [pc, #20] @ (80064b4 <HAL_PWREx_ControlVoltageScaling+0x13c>)
80064a0: f443 6380 orr.w r3, r3, #1024 @ 0x400
80064a4: 6013 str r3, [r2, #0]
/* No need to wait for VOSF to be cleared for this transition */
/* PWR_CR5_R1MODE bit setting has no effect in Range 2 */
}
return HAL_OK;
80064a6: 2300 movs r3, #0
}
80064a8: 4618 mov r0, r3
80064aa: 3714 adds r7, #20
80064ac: 46bd mov sp, r7
80064ae: f85d 7b04 ldr.w r7, [sp], #4
80064b2: 4770 bx lr
80064b4: 40007000 .word 0x40007000
80064b8: 20000000 .word 0x20000000
80064bc: 431bde83 .word 0x431bde83
080064c0 <HAL_PWREx_DisableUCPDDeadBattery>:
* or to hand over control to the UCPD (which should therefore be
* initialized before doing the disable).
* @retval None
*/
void HAL_PWREx_DisableUCPDDeadBattery(void)
{
80064c0: b480 push {r7}
80064c2: af00 add r7, sp, #0
/* Write 1 to disable the USB Type-C dead battery pull-down behavior */
SET_BIT(PWR->CR3, PWR_CR3_UCPD_DBDIS);
80064c4: 4b05 ldr r3, [pc, #20] @ (80064dc <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
80064c6: 689b ldr r3, [r3, #8]
80064c8: 4a04 ldr r2, [pc, #16] @ (80064dc <HAL_PWREx_DisableUCPDDeadBattery+0x1c>)
80064ca: f443 4380 orr.w r3, r3, #16384 @ 0x4000
80064ce: 6093 str r3, [r2, #8]
}
80064d0: bf00 nop
80064d2: 46bd mov sp, r7
80064d4: f85d 7b04 ldr.w r7, [sp], #4
80064d8: 4770 bx lr
80064da: bf00 nop
80064dc: 40007000 .word 0x40007000
080064e0 <HAL_RCC_OscConfig>:
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
80064e0: b580 push {r7, lr}
80064e2: b088 sub sp, #32
80064e4: af00 add r7, sp, #0
80064e6: 6078 str r0, [r7, #4]
uint32_t tickstart;
uint32_t temp_sysclksrc;
uint32_t temp_pllckcfg;
/* Check Null pointer */
if (RCC_OscInitStruct == NULL)
80064e8: 687b ldr r3, [r7, #4]
80064ea: 2b00 cmp r3, #0
80064ec: d101 bne.n 80064f2 <HAL_RCC_OscConfig+0x12>
{
return HAL_ERROR;
80064ee: 2301 movs r3, #1
80064f0: e2fe b.n 8006af0 <HAL_RCC_OscConfig+0x610>
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
80064f2: 687b ldr r3, [r7, #4]
80064f4: 681b ldr r3, [r3, #0]
80064f6: f003 0301 and.w r3, r3, #1
80064fa: 2b00 cmp r3, #0
80064fc: d075 beq.n 80065ea <HAL_RCC_OscConfig+0x10a>
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
80064fe: 4b97 ldr r3, [pc, #604] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006500: 689b ldr r3, [r3, #8]
8006502: f003 030c and.w r3, r3, #12
8006506: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8006508: 4b94 ldr r3, [pc, #592] @ (800675c <HAL_RCC_OscConfig+0x27c>)
800650a: 68db ldr r3, [r3, #12]
800650c: f003 0303 and.w r3, r3, #3
8006510: 617b str r3, [r7, #20]
/* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSE)) || (temp_sysclksrc == RCC_CFGR_SWS_HSE))
8006512: 69bb ldr r3, [r7, #24]
8006514: 2b0c cmp r3, #12
8006516: d102 bne.n 800651e <HAL_RCC_OscConfig+0x3e>
8006518: 697b ldr r3, [r7, #20]
800651a: 2b03 cmp r3, #3
800651c: d002 beq.n 8006524 <HAL_RCC_OscConfig+0x44>
800651e: 69bb ldr r3, [r7, #24]
8006520: 2b08 cmp r3, #8
8006522: d10b bne.n 800653c <HAL_RCC_OscConfig+0x5c>
{
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
8006524: 4b8d ldr r3, [pc, #564] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006526: 681b ldr r3, [r3, #0]
8006528: f403 3300 and.w r3, r3, #131072 @ 0x20000
800652c: 2b00 cmp r3, #0
800652e: d05b beq.n 80065e8 <HAL_RCC_OscConfig+0x108>
8006530: 687b ldr r3, [r7, #4]
8006532: 685b ldr r3, [r3, #4]
8006534: 2b00 cmp r3, #0
8006536: d157 bne.n 80065e8 <HAL_RCC_OscConfig+0x108>
{
return HAL_ERROR;
8006538: 2301 movs r3, #1
800653a: e2d9 b.n 8006af0 <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
800653c: 687b ldr r3, [r7, #4]
800653e: 685b ldr r3, [r3, #4]
8006540: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8006544: d106 bne.n 8006554 <HAL_RCC_OscConfig+0x74>
8006546: 4b85 ldr r3, [pc, #532] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006548: 681b ldr r3, [r3, #0]
800654a: 4a84 ldr r2, [pc, #528] @ (800675c <HAL_RCC_OscConfig+0x27c>)
800654c: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8006550: 6013 str r3, [r2, #0]
8006552: e01d b.n 8006590 <HAL_RCC_OscConfig+0xb0>
8006554: 687b ldr r3, [r7, #4]
8006556: 685b ldr r3, [r3, #4]
8006558: f5b3 2fa0 cmp.w r3, #327680 @ 0x50000
800655c: d10c bne.n 8006578 <HAL_RCC_OscConfig+0x98>
800655e: 4b7f ldr r3, [pc, #508] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006560: 681b ldr r3, [r3, #0]
8006562: 4a7e ldr r2, [pc, #504] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006564: f443 2380 orr.w r3, r3, #262144 @ 0x40000
8006568: 6013 str r3, [r2, #0]
800656a: 4b7c ldr r3, [pc, #496] @ (800675c <HAL_RCC_OscConfig+0x27c>)
800656c: 681b ldr r3, [r3, #0]
800656e: 4a7b ldr r2, [pc, #492] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006570: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8006574: 6013 str r3, [r2, #0]
8006576: e00b b.n 8006590 <HAL_RCC_OscConfig+0xb0>
8006578: 4b78 ldr r3, [pc, #480] @ (800675c <HAL_RCC_OscConfig+0x27c>)
800657a: 681b ldr r3, [r3, #0]
800657c: 4a77 ldr r2, [pc, #476] @ (800675c <HAL_RCC_OscConfig+0x27c>)
800657e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8006582: 6013 str r3, [r2, #0]
8006584: 4b75 ldr r3, [pc, #468] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006586: 681b ldr r3, [r3, #0]
8006588: 4a74 ldr r2, [pc, #464] @ (800675c <HAL_RCC_OscConfig+0x27c>)
800658a: f423 2380 bic.w r3, r3, #262144 @ 0x40000
800658e: 6013 str r3, [r2, #0]
/* Check the HSE State */
if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
8006590: 687b ldr r3, [r7, #4]
8006592: 685b ldr r3, [r3, #4]
8006594: 2b00 cmp r3, #0
8006596: d013 beq.n 80065c0 <HAL_RCC_OscConfig+0xe0>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8006598: f7fb faa8 bl 8001aec <HAL_GetTick>
800659c: 6138 str r0, [r7, #16]
/* Wait till HSE is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
800659e: e008 b.n 80065b2 <HAL_RCC_OscConfig+0xd2>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80065a0: f7fb faa4 bl 8001aec <HAL_GetTick>
80065a4: 4602 mov r2, r0
80065a6: 693b ldr r3, [r7, #16]
80065a8: 1ad3 subs r3, r2, r3
80065aa: 2b64 cmp r3, #100 @ 0x64
80065ac: d901 bls.n 80065b2 <HAL_RCC_OscConfig+0xd2>
{
return HAL_TIMEOUT;
80065ae: 2303 movs r3, #3
80065b0: e29e b.n 8006af0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
80065b2: 4b6a ldr r3, [pc, #424] @ (800675c <HAL_RCC_OscConfig+0x27c>)
80065b4: 681b ldr r3, [r3, #0]
80065b6: f403 3300 and.w r3, r3, #131072 @ 0x20000
80065ba: 2b00 cmp r3, #0
80065bc: d0f0 beq.n 80065a0 <HAL_RCC_OscConfig+0xc0>
80065be: e014 b.n 80065ea <HAL_RCC_OscConfig+0x10a>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
80065c0: f7fb fa94 bl 8001aec <HAL_GetTick>
80065c4: 6138 str r0, [r7, #16]
/* Wait till HSE is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
80065c6: e008 b.n 80065da <HAL_RCC_OscConfig+0xfa>
{
if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
80065c8: f7fb fa90 bl 8001aec <HAL_GetTick>
80065cc: 4602 mov r2, r0
80065ce: 693b ldr r3, [r7, #16]
80065d0: 1ad3 subs r3, r2, r3
80065d2: 2b64 cmp r3, #100 @ 0x64
80065d4: d901 bls.n 80065da <HAL_RCC_OscConfig+0xfa>
{
return HAL_TIMEOUT;
80065d6: 2303 movs r3, #3
80065d8: e28a b.n 8006af0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
80065da: 4b60 ldr r3, [pc, #384] @ (800675c <HAL_RCC_OscConfig+0x27c>)
80065dc: 681b ldr r3, [r3, #0]
80065de: f403 3300 and.w r3, r3, #131072 @ 0x20000
80065e2: 2b00 cmp r3, #0
80065e4: d1f0 bne.n 80065c8 <HAL_RCC_OscConfig+0xe8>
80065e6: e000 b.n 80065ea <HAL_RCC_OscConfig+0x10a>
if ((READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
80065e8: bf00 nop
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
80065ea: 687b ldr r3, [r7, #4]
80065ec: 681b ldr r3, [r3, #0]
80065ee: f003 0302 and.w r3, r3, #2
80065f2: 2b00 cmp r3, #0
80065f4: d075 beq.n 80066e2 <HAL_RCC_OscConfig+0x202>
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
80065f6: 4b59 ldr r3, [pc, #356] @ (800675c <HAL_RCC_OscConfig+0x27c>)
80065f8: 689b ldr r3, [r3, #8]
80065fa: f003 030c and.w r3, r3, #12
80065fe: 61bb str r3, [r7, #24]
temp_pllckcfg = __HAL_RCC_GET_PLL_OSCSOURCE();
8006600: 4b56 ldr r3, [pc, #344] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006602: 68db ldr r3, [r3, #12]
8006604: f003 0303 and.w r3, r3, #3
8006608: 617b str r3, [r7, #20]
if (((temp_sysclksrc == RCC_CFGR_SWS_PLL) && (temp_pllckcfg == RCC_PLLSOURCE_HSI)) || (temp_sysclksrc == RCC_CFGR_SWS_HSI))
800660a: 69bb ldr r3, [r7, #24]
800660c: 2b0c cmp r3, #12
800660e: d102 bne.n 8006616 <HAL_RCC_OscConfig+0x136>
8006610: 697b ldr r3, [r7, #20]
8006612: 2b02 cmp r3, #2
8006614: d002 beq.n 800661c <HAL_RCC_OscConfig+0x13c>
8006616: 69bb ldr r3, [r7, #24]
8006618: 2b04 cmp r3, #4
800661a: d11f bne.n 800665c <HAL_RCC_OscConfig+0x17c>
{
/* When HSI is used as system clock it will not be disabled */
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
800661c: 4b4f ldr r3, [pc, #316] @ (800675c <HAL_RCC_OscConfig+0x27c>)
800661e: 681b ldr r3, [r3, #0]
8006620: f403 6380 and.w r3, r3, #1024 @ 0x400
8006624: 2b00 cmp r3, #0
8006626: d005 beq.n 8006634 <HAL_RCC_OscConfig+0x154>
8006628: 687b ldr r3, [r7, #4]
800662a: 68db ldr r3, [r3, #12]
800662c: 2b00 cmp r3, #0
800662e: d101 bne.n 8006634 <HAL_RCC_OscConfig+0x154>
{
return HAL_ERROR;
8006630: 2301 movs r3, #1
8006632: e25d b.n 8006af0 <HAL_RCC_OscConfig+0x610>
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8006634: 4b49 ldr r3, [pc, #292] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006636: 685b ldr r3, [r3, #4]
8006638: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
800663c: 687b ldr r3, [r7, #4]
800663e: 691b ldr r3, [r3, #16]
8006640: 061b lsls r3, r3, #24
8006642: 4946 ldr r1, [pc, #280] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006644: 4313 orrs r3, r2
8006646: 604b str r3, [r1, #4]
/* Adapt Systick interrupt period */
if (HAL_InitTick(uwTickPrio) != HAL_OK)
8006648: 4b45 ldr r3, [pc, #276] @ (8006760 <HAL_RCC_OscConfig+0x280>)
800664a: 681b ldr r3, [r3, #0]
800664c: 4618 mov r0, r3
800664e: f7fb fa01 bl 8001a54 <HAL_InitTick>
8006652: 4603 mov r3, r0
8006654: 2b00 cmp r3, #0
8006656: d043 beq.n 80066e0 <HAL_RCC_OscConfig+0x200>
{
return HAL_ERROR;
8006658: 2301 movs r3, #1
800665a: e249 b.n 8006af0 <HAL_RCC_OscConfig+0x610>
}
}
else
{
/* Check the HSI State */
if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
800665c: 687b ldr r3, [r7, #4]
800665e: 68db ldr r3, [r3, #12]
8006660: 2b00 cmp r3, #0
8006662: d023 beq.n 80066ac <HAL_RCC_OscConfig+0x1cc>
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
8006664: 4b3d ldr r3, [pc, #244] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006666: 681b ldr r3, [r3, #0]
8006668: 4a3c ldr r2, [pc, #240] @ (800675c <HAL_RCC_OscConfig+0x27c>)
800666a: f443 7380 orr.w r3, r3, #256 @ 0x100
800666e: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8006670: f7fb fa3c bl 8001aec <HAL_GetTick>
8006674: 6138 str r0, [r7, #16]
/* Wait till HSI is ready */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8006676: e008 b.n 800668a <HAL_RCC_OscConfig+0x1aa>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
8006678: f7fb fa38 bl 8001aec <HAL_GetTick>
800667c: 4602 mov r2, r0
800667e: 693b ldr r3, [r7, #16]
8006680: 1ad3 subs r3, r2, r3
8006682: 2b02 cmp r3, #2
8006684: d901 bls.n 800668a <HAL_RCC_OscConfig+0x1aa>
{
return HAL_TIMEOUT;
8006686: 2303 movs r3, #3
8006688: e232 b.n 8006af0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
800668a: 4b34 ldr r3, [pc, #208] @ (800675c <HAL_RCC_OscConfig+0x27c>)
800668c: 681b ldr r3, [r3, #0]
800668e: f403 6380 and.w r3, r3, #1024 @ 0x400
8006692: 2b00 cmp r3, #0
8006694: d0f0 beq.n 8006678 <HAL_RCC_OscConfig+0x198>
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
8006696: 4b31 ldr r3, [pc, #196] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006698: 685b ldr r3, [r3, #4]
800669a: f023 42fe bic.w r2, r3, #2130706432 @ 0x7f000000
800669e: 687b ldr r3, [r7, #4]
80066a0: 691b ldr r3, [r3, #16]
80066a2: 061b lsls r3, r3, #24
80066a4: 492d ldr r1, [pc, #180] @ (800675c <HAL_RCC_OscConfig+0x27c>)
80066a6: 4313 orrs r3, r2
80066a8: 604b str r3, [r1, #4]
80066aa: e01a b.n 80066e2 <HAL_RCC_OscConfig+0x202>
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
80066ac: 4b2b ldr r3, [pc, #172] @ (800675c <HAL_RCC_OscConfig+0x27c>)
80066ae: 681b ldr r3, [r3, #0]
80066b0: 4a2a ldr r2, [pc, #168] @ (800675c <HAL_RCC_OscConfig+0x27c>)
80066b2: f423 7380 bic.w r3, r3, #256 @ 0x100
80066b6: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
80066b8: f7fb fa18 bl 8001aec <HAL_GetTick>
80066bc: 6138 str r0, [r7, #16]
/* Wait till HSI is disabled */
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
80066be: e008 b.n 80066d2 <HAL_RCC_OscConfig+0x1f2>
{
if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
80066c0: f7fb fa14 bl 8001aec <HAL_GetTick>
80066c4: 4602 mov r2, r0
80066c6: 693b ldr r3, [r7, #16]
80066c8: 1ad3 subs r3, r2, r3
80066ca: 2b02 cmp r3, #2
80066cc: d901 bls.n 80066d2 <HAL_RCC_OscConfig+0x1f2>
{
return HAL_TIMEOUT;
80066ce: 2303 movs r3, #3
80066d0: e20e b.n 8006af0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
80066d2: 4b22 ldr r3, [pc, #136] @ (800675c <HAL_RCC_OscConfig+0x27c>)
80066d4: 681b ldr r3, [r3, #0]
80066d6: f403 6380 and.w r3, r3, #1024 @ 0x400
80066da: 2b00 cmp r3, #0
80066dc: d1f0 bne.n 80066c0 <HAL_RCC_OscConfig+0x1e0>
80066de: e000 b.n 80066e2 <HAL_RCC_OscConfig+0x202>
if ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) && (RCC_OscInitStruct->HSIState == RCC_HSI_OFF))
80066e0: bf00 nop
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
80066e2: 687b ldr r3, [r7, #4]
80066e4: 681b ldr r3, [r3, #0]
80066e6: f003 0308 and.w r3, r3, #8
80066ea: 2b00 cmp r3, #0
80066ec: d041 beq.n 8006772 <HAL_RCC_OscConfig+0x292>
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if(RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
80066ee: 687b ldr r3, [r7, #4]
80066f0: 695b ldr r3, [r3, #20]
80066f2: 2b00 cmp r3, #0
80066f4: d01c beq.n 8006730 <HAL_RCC_OscConfig+0x250>
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
80066f6: 4b19 ldr r3, [pc, #100] @ (800675c <HAL_RCC_OscConfig+0x27c>)
80066f8: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
80066fc: 4a17 ldr r2, [pc, #92] @ (800675c <HAL_RCC_OscConfig+0x27c>)
80066fe: f043 0301 orr.w r3, r3, #1
8006702: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8006706: f7fb f9f1 bl 8001aec <HAL_GetTick>
800670a: 6138 str r0, [r7, #16]
/* Wait till LSI is ready */
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
800670c: e008 b.n 8006720 <HAL_RCC_OscConfig+0x240>
{
if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
800670e: f7fb f9ed bl 8001aec <HAL_GetTick>
8006712: 4602 mov r2, r0
8006714: 693b ldr r3, [r7, #16]
8006716: 1ad3 subs r3, r2, r3
8006718: 2b02 cmp r3, #2
800671a: d901 bls.n 8006720 <HAL_RCC_OscConfig+0x240>
{
return HAL_TIMEOUT;
800671c: 2303 movs r3, #3
800671e: e1e7 b.n 8006af0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == 0U)
8006720: 4b0e ldr r3, [pc, #56] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006722: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8006726: f003 0302 and.w r3, r3, #2
800672a: 2b00 cmp r3, #0
800672c: d0ef beq.n 800670e <HAL_RCC_OscConfig+0x22e>
800672e: e020 b.n 8006772 <HAL_RCC_OscConfig+0x292>
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
8006730: 4b0a ldr r3, [pc, #40] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006732: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
8006736: 4a09 ldr r2, [pc, #36] @ (800675c <HAL_RCC_OscConfig+0x27c>)
8006738: f023 0301 bic.w r3, r3, #1
800673c: f8c2 3094 str.w r3, [r2, #148] @ 0x94
/* Get Start Tick*/
tickstart = HAL_GetTick();
8006740: f7fb f9d4 bl 8001aec <HAL_GetTick>
8006744: 6138 str r0, [r7, #16]
/* Wait till LSI is disabled */
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8006746: e00d b.n 8006764 <HAL_RCC_OscConfig+0x284>
{
if((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE)
8006748: f7fb f9d0 bl 8001aec <HAL_GetTick>
800674c: 4602 mov r2, r0
800674e: 693b ldr r3, [r7, #16]
8006750: 1ad3 subs r3, r2, r3
8006752: 2b02 cmp r3, #2
8006754: d906 bls.n 8006764 <HAL_RCC_OscConfig+0x284>
{
return HAL_TIMEOUT;
8006756: 2303 movs r3, #3
8006758: e1ca b.n 8006af0 <HAL_RCC_OscConfig+0x610>
800675a: bf00 nop
800675c: 40021000 .word 0x40021000
8006760: 20000004 .word 0x20000004
while(READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) != 0U)
8006764: 4b8c ldr r3, [pc, #560] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
8006766: f8d3 3094 ldr.w r3, [r3, #148] @ 0x94
800676a: f003 0302 and.w r3, r3, #2
800676e: 2b00 cmp r3, #0
8006770: d1ea bne.n 8006748 <HAL_RCC_OscConfig+0x268>
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
8006772: 687b ldr r3, [r7, #4]
8006774: 681b ldr r3, [r3, #0]
8006776: f003 0304 and.w r3, r3, #4
800677a: 2b00 cmp r3, #0
800677c: f000 80a6 beq.w 80068cc <HAL_RCC_OscConfig+0x3ec>
{
FlagStatus pwrclkchanged = RESET;
8006780: 2300 movs r3, #0
8006782: 77fb strb r3, [r7, #31]
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain if necessary */
if (__HAL_RCC_PWR_IS_CLK_DISABLED() != 0U)
8006784: 4b84 ldr r3, [pc, #528] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
8006786: 6d9b ldr r3, [r3, #88] @ 0x58
8006788: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
800678c: 2b00 cmp r3, #0
800678e: d101 bne.n 8006794 <HAL_RCC_OscConfig+0x2b4>
8006790: 2301 movs r3, #1
8006792: e000 b.n 8006796 <HAL_RCC_OscConfig+0x2b6>
8006794: 2300 movs r3, #0
8006796: 2b00 cmp r3, #0
8006798: d00d beq.n 80067b6 <HAL_RCC_OscConfig+0x2d6>
{
__HAL_RCC_PWR_CLK_ENABLE();
800679a: 4b7f ldr r3, [pc, #508] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
800679c: 6d9b ldr r3, [r3, #88] @ 0x58
800679e: 4a7e ldr r2, [pc, #504] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
80067a0: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
80067a4: 6593 str r3, [r2, #88] @ 0x58
80067a6: 4b7c ldr r3, [pc, #496] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
80067a8: 6d9b ldr r3, [r3, #88] @ 0x58
80067aa: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
80067ae: 60fb str r3, [r7, #12]
80067b0: 68fb ldr r3, [r7, #12]
pwrclkchanged = SET;
80067b2: 2301 movs r3, #1
80067b4: 77fb strb r3, [r7, #31]
}
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80067b6: 4b79 ldr r3, [pc, #484] @ (800699c <HAL_RCC_OscConfig+0x4bc>)
80067b8: 681b ldr r3, [r3, #0]
80067ba: f403 7380 and.w r3, r3, #256 @ 0x100
80067be: 2b00 cmp r3, #0
80067c0: d118 bne.n 80067f4 <HAL_RCC_OscConfig+0x314>
{
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
80067c2: 4b76 ldr r3, [pc, #472] @ (800699c <HAL_RCC_OscConfig+0x4bc>)
80067c4: 681b ldr r3, [r3, #0]
80067c6: 4a75 ldr r2, [pc, #468] @ (800699c <HAL_RCC_OscConfig+0x4bc>)
80067c8: f443 7380 orr.w r3, r3, #256 @ 0x100
80067cc: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
80067ce: f7fb f98d bl 8001aec <HAL_GetTick>
80067d2: 6138 str r0, [r7, #16]
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80067d4: e008 b.n 80067e8 <HAL_RCC_OscConfig+0x308>
{
if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
80067d6: f7fb f989 bl 8001aec <HAL_GetTick>
80067da: 4602 mov r2, r0
80067dc: 693b ldr r3, [r7, #16]
80067de: 1ad3 subs r3, r2, r3
80067e0: 2b02 cmp r3, #2
80067e2: d901 bls.n 80067e8 <HAL_RCC_OscConfig+0x308>
{
return HAL_TIMEOUT;
80067e4: 2303 movs r3, #3
80067e6: e183 b.n 8006af0 <HAL_RCC_OscConfig+0x610>
while (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
80067e8: 4b6c ldr r3, [pc, #432] @ (800699c <HAL_RCC_OscConfig+0x4bc>)
80067ea: 681b ldr r3, [r3, #0]
80067ec: f403 7380 and.w r3, r3, #256 @ 0x100
80067f0: 2b00 cmp r3, #0
80067f2: d0f0 beq.n 80067d6 <HAL_RCC_OscConfig+0x2f6>
}
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
80067f4: 687b ldr r3, [r7, #4]
80067f6: 689b ldr r3, [r3, #8]
80067f8: 2b01 cmp r3, #1
80067fa: d108 bne.n 800680e <HAL_RCC_OscConfig+0x32e>
80067fc: 4b66 ldr r3, [pc, #408] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
80067fe: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8006802: 4a65 ldr r2, [pc, #404] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
8006804: f043 0301 orr.w r3, r3, #1
8006808: f8c2 3090 str.w r3, [r2, #144] @ 0x90
800680c: e024 b.n 8006858 <HAL_RCC_OscConfig+0x378>
800680e: 687b ldr r3, [r7, #4]
8006810: 689b ldr r3, [r3, #8]
8006812: 2b05 cmp r3, #5
8006814: d110 bne.n 8006838 <HAL_RCC_OscConfig+0x358>
8006816: 4b60 ldr r3, [pc, #384] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
8006818: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800681c: 4a5e ldr r2, [pc, #376] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
800681e: f043 0304 orr.w r3, r3, #4
8006822: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8006826: 4b5c ldr r3, [pc, #368] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
8006828: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800682c: 4a5a ldr r2, [pc, #360] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
800682e: f043 0301 orr.w r3, r3, #1
8006832: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8006836: e00f b.n 8006858 <HAL_RCC_OscConfig+0x378>
8006838: 4b57 ldr r3, [pc, #348] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
800683a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800683e: 4a56 ldr r2, [pc, #344] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
8006840: f023 0301 bic.w r3, r3, #1
8006844: f8c2 3090 str.w r3, [r2, #144] @ 0x90
8006848: 4b53 ldr r3, [pc, #332] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
800684a: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
800684e: 4a52 ldr r2, [pc, #328] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
8006850: f023 0304 bic.w r3, r3, #4
8006854: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Check the LSE State */
if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
8006858: 687b ldr r3, [r7, #4]
800685a: 689b ldr r3, [r3, #8]
800685c: 2b00 cmp r3, #0
800685e: d016 beq.n 800688e <HAL_RCC_OscConfig+0x3ae>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
8006860: f7fb f944 bl 8001aec <HAL_GetTick>
8006864: 6138 str r0, [r7, #16]
/* Wait till LSE is ready */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8006866: e00a b.n 800687e <HAL_RCC_OscConfig+0x39e>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8006868: f7fb f940 bl 8001aec <HAL_GetTick>
800686c: 4602 mov r2, r0
800686e: 693b ldr r3, [r7, #16]
8006870: 1ad3 subs r3, r2, r3
8006872: f241 3288 movw r2, #5000 @ 0x1388
8006876: 4293 cmp r3, r2
8006878: d901 bls.n 800687e <HAL_RCC_OscConfig+0x39e>
{
return HAL_TIMEOUT;
800687a: 2303 movs r3, #3
800687c: e138 b.n 8006af0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
800687e: 4b46 ldr r3, [pc, #280] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
8006880: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8006884: f003 0302 and.w r3, r3, #2
8006888: 2b00 cmp r3, #0
800688a: d0ed beq.n 8006868 <HAL_RCC_OscConfig+0x388>
800688c: e015 b.n 80068ba <HAL_RCC_OscConfig+0x3da>
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800688e: f7fb f92d bl 8001aec <HAL_GetTick>
8006892: 6138 str r0, [r7, #16]
/* Wait till LSE is disabled */
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
8006894: e00a b.n 80068ac <HAL_RCC_OscConfig+0x3cc>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8006896: f7fb f929 bl 8001aec <HAL_GetTick>
800689a: 4602 mov r2, r0
800689c: 693b ldr r3, [r7, #16]
800689e: 1ad3 subs r3, r2, r3
80068a0: f241 3288 movw r2, #5000 @ 0x1388
80068a4: 4293 cmp r3, r2
80068a6: d901 bls.n 80068ac <HAL_RCC_OscConfig+0x3cc>
{
return HAL_TIMEOUT;
80068a8: 2303 movs r3, #3
80068aa: e121 b.n 8006af0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U)
80068ac: 4b3a ldr r3, [pc, #232] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
80068ae: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
80068b2: f003 0302 and.w r3, r3, #2
80068b6: 2b00 cmp r3, #0
80068b8: d1ed bne.n 8006896 <HAL_RCC_OscConfig+0x3b6>
}
}
}
/* Restore clock configuration if changed */
if (pwrclkchanged == SET)
80068ba: 7ffb ldrb r3, [r7, #31]
80068bc: 2b01 cmp r3, #1
80068be: d105 bne.n 80068cc <HAL_RCC_OscConfig+0x3ec>
{
__HAL_RCC_PWR_CLK_DISABLE();
80068c0: 4b35 ldr r3, [pc, #212] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
80068c2: 6d9b ldr r3, [r3, #88] @ 0x58
80068c4: 4a34 ldr r2, [pc, #208] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
80068c6: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80068ca: 6593 str r3, [r2, #88] @ 0x58
}
}
/*------------------------------ HSI48 Configuration -----------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48)
80068cc: 687b ldr r3, [r7, #4]
80068ce: 681b ldr r3, [r3, #0]
80068d0: f003 0320 and.w r3, r3, #32
80068d4: 2b00 cmp r3, #0
80068d6: d03c beq.n 8006952 <HAL_RCC_OscConfig+0x472>
{
/* Check the parameters */
assert_param(IS_RCC_HSI48(RCC_OscInitStruct->HSI48State));
/* Check the HSI48 State */
if(RCC_OscInitStruct->HSI48State != RCC_HSI48_OFF)
80068d8: 687b ldr r3, [r7, #4]
80068da: 699b ldr r3, [r3, #24]
80068dc: 2b00 cmp r3, #0
80068de: d01c beq.n 800691a <HAL_RCC_OscConfig+0x43a>
{
/* Enable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_ENABLE();
80068e0: 4b2d ldr r3, [pc, #180] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
80068e2: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
80068e6: 4a2c ldr r2, [pc, #176] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
80068e8: f043 0301 orr.w r3, r3, #1
80068ec: f8c2 3098 str.w r3, [r2, #152] @ 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
80068f0: f7fb f8fc bl 8001aec <HAL_GetTick>
80068f4: 6138 str r0, [r7, #16]
/* Wait till HSI48 is ready */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
80068f6: e008 b.n 800690a <HAL_RCC_OscConfig+0x42a>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
80068f8: f7fb f8f8 bl 8001aec <HAL_GetTick>
80068fc: 4602 mov r2, r0
80068fe: 693b ldr r3, [r7, #16]
8006900: 1ad3 subs r3, r2, r3
8006902: 2b02 cmp r3, #2
8006904: d901 bls.n 800690a <HAL_RCC_OscConfig+0x42a>
{
return HAL_TIMEOUT;
8006906: 2303 movs r3, #3
8006908: e0f2 b.n 8006af0 <HAL_RCC_OscConfig+0x610>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) == 0U)
800690a: 4b23 ldr r3, [pc, #140] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
800690c: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8006910: f003 0302 and.w r3, r3, #2
8006914: 2b00 cmp r3, #0
8006916: d0ef beq.n 80068f8 <HAL_RCC_OscConfig+0x418>
8006918: e01b b.n 8006952 <HAL_RCC_OscConfig+0x472>
}
}
else
{
/* Disable the Internal Low Speed oscillator (HSI48). */
__HAL_RCC_HSI48_DISABLE();
800691a: 4b1f ldr r3, [pc, #124] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
800691c: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
8006920: 4a1d ldr r2, [pc, #116] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
8006922: f023 0301 bic.w r3, r3, #1
8006926: f8c2 3098 str.w r3, [r2, #152] @ 0x98
/* Get Start Tick*/
tickstart = HAL_GetTick();
800692a: f7fb f8df bl 8001aec <HAL_GetTick>
800692e: 6138 str r0, [r7, #16]
/* Wait till HSI48 is disabled */
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
8006930: e008 b.n 8006944 <HAL_RCC_OscConfig+0x464>
{
if((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE)
8006932: f7fb f8db bl 8001aec <HAL_GetTick>
8006936: 4602 mov r2, r0
8006938: 693b ldr r3, [r7, #16]
800693a: 1ad3 subs r3, r2, r3
800693c: 2b02 cmp r3, #2
800693e: d901 bls.n 8006944 <HAL_RCC_OscConfig+0x464>
{
return HAL_TIMEOUT;
8006940: 2303 movs r3, #3
8006942: e0d5 b.n 8006af0 <HAL_RCC_OscConfig+0x610>
while(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48RDY) != 0U)
8006944: 4b14 ldr r3, [pc, #80] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
8006946: f8d3 3098 ldr.w r3, [r3, #152] @ 0x98
800694a: f003 0302 and.w r3, r3, #2
800694e: 2b00 cmp r3, #0
8006950: d1ef bne.n 8006932 <HAL_RCC_OscConfig+0x452>
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE)
8006952: 687b ldr r3, [r7, #4]
8006954: 69db ldr r3, [r3, #28]
8006956: 2b00 cmp r3, #0
8006958: f000 80c9 beq.w 8006aee <HAL_RCC_OscConfig+0x60e>
{
/* Check if the PLL is used as system clock or not */
if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
800695c: 4b0e ldr r3, [pc, #56] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
800695e: 689b ldr r3, [r3, #8]
8006960: f003 030c and.w r3, r3, #12
8006964: 2b0c cmp r3, #12
8006966: f000 8083 beq.w 8006a70 <HAL_RCC_OscConfig+0x590>
{
if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON)
800696a: 687b ldr r3, [r7, #4]
800696c: 69db ldr r3, [r3, #28]
800696e: 2b02 cmp r3, #2
8006970: d15e bne.n 8006a30 <HAL_RCC_OscConfig+0x550>
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8006972: 4b09 ldr r3, [pc, #36] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
8006974: 681b ldr r3, [r3, #0]
8006976: 4a08 ldr r2, [pc, #32] @ (8006998 <HAL_RCC_OscConfig+0x4b8>)
8006978: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800697c: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
800697e: f7fb f8b5 bl 8001aec <HAL_GetTick>
8006982: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8006984: e00c b.n 80069a0 <HAL_RCC_OscConfig+0x4c0>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8006986: f7fb f8b1 bl 8001aec <HAL_GetTick>
800698a: 4602 mov r2, r0
800698c: 693b ldr r3, [r7, #16]
800698e: 1ad3 subs r3, r2, r3
8006990: 2b02 cmp r3, #2
8006992: d905 bls.n 80069a0 <HAL_RCC_OscConfig+0x4c0>
{
return HAL_TIMEOUT;
8006994: 2303 movs r3, #3
8006996: e0ab b.n 8006af0 <HAL_RCC_OscConfig+0x610>
8006998: 40021000 .word 0x40021000
800699c: 40007000 .word 0x40007000
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
80069a0: 4b55 ldr r3, [pc, #340] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
80069a2: 681b ldr r3, [r3, #0]
80069a4: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
80069a8: 2b00 cmp r3, #0
80069aa: d1ec bne.n 8006986 <HAL_RCC_OscConfig+0x4a6>
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
80069ac: 4b52 ldr r3, [pc, #328] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
80069ae: 68da ldr r2, [r3, #12]
80069b0: 4b52 ldr r3, [pc, #328] @ (8006afc <HAL_RCC_OscConfig+0x61c>)
80069b2: 4013 ands r3, r2
80069b4: 687a ldr r2, [r7, #4]
80069b6: 6a11 ldr r1, [r2, #32]
80069b8: 687a ldr r2, [r7, #4]
80069ba: 6a52 ldr r2, [r2, #36] @ 0x24
80069bc: 3a01 subs r2, #1
80069be: 0112 lsls r2, r2, #4
80069c0: 4311 orrs r1, r2
80069c2: 687a ldr r2, [r7, #4]
80069c4: 6a92 ldr r2, [r2, #40] @ 0x28
80069c6: 0212 lsls r2, r2, #8
80069c8: 4311 orrs r1, r2
80069ca: 687a ldr r2, [r7, #4]
80069cc: 6b12 ldr r2, [r2, #48] @ 0x30
80069ce: 0852 lsrs r2, r2, #1
80069d0: 3a01 subs r2, #1
80069d2: 0552 lsls r2, r2, #21
80069d4: 4311 orrs r1, r2
80069d6: 687a ldr r2, [r7, #4]
80069d8: 6b52 ldr r2, [r2, #52] @ 0x34
80069da: 0852 lsrs r2, r2, #1
80069dc: 3a01 subs r2, #1
80069de: 0652 lsls r2, r2, #25
80069e0: 4311 orrs r1, r2
80069e2: 687a ldr r2, [r7, #4]
80069e4: 6ad2 ldr r2, [r2, #44] @ 0x2c
80069e6: 06d2 lsls r2, r2, #27
80069e8: 430a orrs r2, r1
80069ea: 4943 ldr r1, [pc, #268] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
80069ec: 4313 orrs r3, r2
80069ee: 60cb str r3, [r1, #12]
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
80069f0: 4b41 ldr r3, [pc, #260] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
80069f2: 681b ldr r3, [r3, #0]
80069f4: 4a40 ldr r2, [pc, #256] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
80069f6: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
80069fa: 6013 str r3, [r2, #0]
/* Enable PLL System Clock output. */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK);
80069fc: 4b3e ldr r3, [pc, #248] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
80069fe: 68db ldr r3, [r3, #12]
8006a00: 4a3d ldr r2, [pc, #244] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
8006a02: f043 7380 orr.w r3, r3, #16777216 @ 0x1000000
8006a06: 60d3 str r3, [r2, #12]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8006a08: f7fb f870 bl 8001aec <HAL_GetTick>
8006a0c: 6138 str r0, [r7, #16]
/* Wait till PLL is ready */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8006a0e: e008 b.n 8006a22 <HAL_RCC_OscConfig+0x542>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8006a10: f7fb f86c bl 8001aec <HAL_GetTick>
8006a14: 4602 mov r2, r0
8006a16: 693b ldr r3, [r7, #16]
8006a18: 1ad3 subs r3, r2, r3
8006a1a: 2b02 cmp r3, #2
8006a1c: d901 bls.n 8006a22 <HAL_RCC_OscConfig+0x542>
{
return HAL_TIMEOUT;
8006a1e: 2303 movs r3, #3
8006a20: e066 b.n 8006af0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8006a22: 4b35 ldr r3, [pc, #212] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
8006a24: 681b ldr r3, [r3, #0]
8006a26: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8006a2a: 2b00 cmp r3, #0
8006a2c: d0f0 beq.n 8006a10 <HAL_RCC_OscConfig+0x530>
8006a2e: e05e b.n 8006aee <HAL_RCC_OscConfig+0x60e>
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
8006a30: 4b31 ldr r3, [pc, #196] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
8006a32: 681b ldr r3, [r3, #0]
8006a34: 4a30 ldr r2, [pc, #192] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
8006a36: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8006a3a: 6013 str r3, [r2, #0]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8006a3c: f7fb f856 bl 8001aec <HAL_GetTick>
8006a40: 6138 str r0, [r7, #16]
/* Wait till PLL is disabled */
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8006a42: e008 b.n 8006a56 <HAL_RCC_OscConfig+0x576>
{
if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
8006a44: f7fb f852 bl 8001aec <HAL_GetTick>
8006a48: 4602 mov r2, r0
8006a4a: 693b ldr r3, [r7, #16]
8006a4c: 1ad3 subs r3, r2, r3
8006a4e: 2b02 cmp r3, #2
8006a50: d901 bls.n 8006a56 <HAL_RCC_OscConfig+0x576>
{
return HAL_TIMEOUT;
8006a52: 2303 movs r3, #3
8006a54: e04c b.n 8006af0 <HAL_RCC_OscConfig+0x610>
while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != 0U)
8006a56: 4b28 ldr r3, [pc, #160] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
8006a58: 681b ldr r3, [r3, #0]
8006a5a: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8006a5e: 2b00 cmp r3, #0
8006a60: d1f0 bne.n 8006a44 <HAL_RCC_OscConfig+0x564>
}
}
/* Unselect PLL clock source and disable outputs to save power */
RCC->PLLCFGR &= ~(RCC_PLLCFGR_PLLSRC | RCC_PLL_SYSCLK | RCC_PLL_48M1CLK | RCC_PLL_ADCCLK);
8006a62: 4b25 ldr r3, [pc, #148] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
8006a64: 68da ldr r2, [r3, #12]
8006a66: 4924 ldr r1, [pc, #144] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
8006a68: 4b25 ldr r3, [pc, #148] @ (8006b00 <HAL_RCC_OscConfig+0x620>)
8006a6a: 4013 ands r3, r2
8006a6c: 60cb str r3, [r1, #12]
8006a6e: e03e b.n 8006aee <HAL_RCC_OscConfig+0x60e>
}
}
else
{
/* Check if there is a request to disable the PLL used as System clock source */
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
8006a70: 687b ldr r3, [r7, #4]
8006a72: 69db ldr r3, [r3, #28]
8006a74: 2b01 cmp r3, #1
8006a76: d101 bne.n 8006a7c <HAL_RCC_OscConfig+0x59c>
{
return HAL_ERROR;
8006a78: 2301 movs r3, #1
8006a7a: e039 b.n 8006af0 <HAL_RCC_OscConfig+0x610>
}
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
temp_pllckcfg = RCC->PLLCFGR;
8006a7c: 4b1e ldr r3, [pc, #120] @ (8006af8 <HAL_RCC_OscConfig+0x618>)
8006a7e: 68db ldr r3, [r3, #12]
8006a80: 617b str r3, [r7, #20]
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8006a82: 697b ldr r3, [r7, #20]
8006a84: f003 0203 and.w r2, r3, #3
8006a88: 687b ldr r3, [r7, #4]
8006a8a: 6a1b ldr r3, [r3, #32]
8006a8c: 429a cmp r2, r3
8006a8e: d12c bne.n 8006aea <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8006a90: 697b ldr r3, [r7, #20]
8006a92: f003 02f0 and.w r2, r3, #240 @ 0xf0
8006a96: 687b ldr r3, [r7, #4]
8006a98: 6a5b ldr r3, [r3, #36] @ 0x24
8006a9a: 3b01 subs r3, #1
8006a9c: 011b lsls r3, r3, #4
if((READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
8006a9e: 429a cmp r2, r3
8006aa0: d123 bne.n 8006aea <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
8006aa2: 697b ldr r3, [r7, #20]
8006aa4: f403 42fe and.w r2, r3, #32512 @ 0x7f00
8006aa8: 687b ldr r3, [r7, #4]
8006aaa: 6a9b ldr r3, [r3, #40] @ 0x28
8006aac: 021b lsls r3, r3, #8
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLM) != (((RCC_OscInitStruct->PLL.PLLM) - 1U) << RCC_PLLCFGR_PLLM_Pos)) ||
8006aae: 429a cmp r2, r3
8006ab0: d11b bne.n 8006aea <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8006ab2: 697b ldr r3, [r7, #20]
8006ab4: f003 4278 and.w r2, r3, #4160749568 @ 0xf8000000
8006ab8: 687b ldr r3, [r7, #4]
8006aba: 6adb ldr r3, [r3, #44] @ 0x2c
8006abc: 06db lsls r3, r3, #27
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLN) != ((RCC_OscInitStruct->PLL.PLLN) << RCC_PLLCFGR_PLLN_Pos)) ||
8006abe: 429a cmp r2, r3
8006ac0: d113 bne.n 8006aea <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8006ac2: 697b ldr r3, [r7, #20]
8006ac4: f403 02c0 and.w r2, r3, #6291456 @ 0x600000
8006ac8: 687b ldr r3, [r7, #4]
8006aca: 6b1b ldr r3, [r3, #48] @ 0x30
8006acc: 085b lsrs r3, r3, #1
8006ace: 3b01 subs r3, #1
8006ad0: 055b lsls r3, r3, #21
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLPDIV) != ((RCC_OscInitStruct->PLL.PLLP) << RCC_PLLCFGR_PLLPDIV_Pos)) ||
8006ad2: 429a cmp r2, r3
8006ad4: d109 bne.n 8006aea <HAL_RCC_OscConfig+0x60a>
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLR) != ((((RCC_OscInitStruct->PLL.PLLR) >> 1U) - 1U) << RCC_PLLCFGR_PLLR_Pos)))
8006ad6: 697b ldr r3, [r7, #20]
8006ad8: f003 62c0 and.w r2, r3, #100663296 @ 0x6000000
8006adc: 687b ldr r3, [r7, #4]
8006ade: 6b5b ldr r3, [r3, #52] @ 0x34
8006ae0: 085b lsrs r3, r3, #1
8006ae2: 3b01 subs r3, #1
8006ae4: 065b lsls r3, r3, #25
(READ_BIT(temp_pllckcfg, RCC_PLLCFGR_PLLQ) != ((((RCC_OscInitStruct->PLL.PLLQ) >> 1U) - 1U) << RCC_PLLCFGR_PLLQ_Pos)) ||
8006ae6: 429a cmp r2, r3
8006ae8: d001 beq.n 8006aee <HAL_RCC_OscConfig+0x60e>
{
return HAL_ERROR;
8006aea: 2301 movs r3, #1
8006aec: e000 b.n 8006af0 <HAL_RCC_OscConfig+0x610>
}
}
}
}
return HAL_OK;
8006aee: 2300 movs r3, #0
}
8006af0: 4618 mov r0, r3
8006af2: 3720 adds r7, #32
8006af4: 46bd mov sp, r7
8006af6: bd80 pop {r7, pc}
8006af8: 40021000 .word 0x40021000
8006afc: 019f800c .word 0x019f800c
8006b00: feeefffc .word 0xfeeefffc
08006b04 <HAL_RCC_ClockConfig>:
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
* @retval None
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
8006b04: b580 push {r7, lr}
8006b06: b086 sub sp, #24
8006b08: af00 add r7, sp, #0
8006b0a: 6078 str r0, [r7, #4]
8006b0c: 6039 str r1, [r7, #0]
uint32_t tickstart;
uint32_t pllfreq;
uint32_t hpre = RCC_SYSCLK_DIV1;
8006b0e: 2300 movs r3, #0
8006b10: 617b str r3, [r7, #20]
/* Check Null pointer */
if (RCC_ClkInitStruct == NULL)
8006b12: 687b ldr r3, [r7, #4]
8006b14: 2b00 cmp r3, #0
8006b16: d101 bne.n 8006b1c <HAL_RCC_ClockConfig+0x18>
{
return HAL_ERROR;
8006b18: 2301 movs r3, #1
8006b1a: e11e b.n 8006d5a <HAL_RCC_ClockConfig+0x256>
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the number of wait states because of higher CPU frequency */
if (FLatency > __HAL_FLASH_GET_LATENCY())
8006b1c: 4b91 ldr r3, [pc, #580] @ (8006d64 <HAL_RCC_ClockConfig+0x260>)
8006b1e: 681b ldr r3, [r3, #0]
8006b20: f003 030f and.w r3, r3, #15
8006b24: 683a ldr r2, [r7, #0]
8006b26: 429a cmp r2, r3
8006b28: d910 bls.n 8006b4c <HAL_RCC_ClockConfig+0x48>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8006b2a: 4b8e ldr r3, [pc, #568] @ (8006d64 <HAL_RCC_ClockConfig+0x260>)
8006b2c: 681b ldr r3, [r3, #0]
8006b2e: f023 020f bic.w r2, r3, #15
8006b32: 498c ldr r1, [pc, #560] @ (8006d64 <HAL_RCC_ClockConfig+0x260>)
8006b34: 683b ldr r3, [r7, #0]
8006b36: 4313 orrs r3, r2
8006b38: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
if (__HAL_FLASH_GET_LATENCY() != FLatency)
8006b3a: 4b8a ldr r3, [pc, #552] @ (8006d64 <HAL_RCC_ClockConfig+0x260>)
8006b3c: 681b ldr r3, [r3, #0]
8006b3e: f003 030f and.w r3, r3, #15
8006b42: 683a ldr r2, [r7, #0]
8006b44: 429a cmp r2, r3
8006b46: d001 beq.n 8006b4c <HAL_RCC_ClockConfig+0x48>
{
return HAL_ERROR;
8006b48: 2301 movs r3, #1
8006b4a: e106 b.n 8006d5a <HAL_RCC_ClockConfig+0x256>
}
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
8006b4c: 687b ldr r3, [r7, #4]
8006b4e: 681b ldr r3, [r3, #0]
8006b50: f003 0301 and.w r3, r3, #1
8006b54: 2b00 cmp r3, #0
8006b56: d073 beq.n 8006c40 <HAL_RCC_ClockConfig+0x13c>
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* PLL is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
8006b58: 687b ldr r3, [r7, #4]
8006b5a: 685b ldr r3, [r3, #4]
8006b5c: 2b03 cmp r3, #3
8006b5e: d129 bne.n 8006bb4 <HAL_RCC_ClockConfig+0xb0>
{
/* Check the PLL ready flag */
if (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == 0U)
8006b60: 4b81 ldr r3, [pc, #516] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006b62: 681b ldr r3, [r3, #0]
8006b64: f003 7300 and.w r3, r3, #33554432 @ 0x2000000
8006b68: 2b00 cmp r3, #0
8006b6a: d101 bne.n 8006b70 <HAL_RCC_ClockConfig+0x6c>
{
return HAL_ERROR;
8006b6c: 2301 movs r3, #1
8006b6e: e0f4 b.n 8006d5a <HAL_RCC_ClockConfig+0x256>
}
/* Undershoot management when selection PLL as SYSCLK source and frequency above 80Mhz */
/* Compute target PLL output frequency */
pllfreq = RCC_GetSysClockFreqFromPLLSource();
8006b70: f000 f99e bl 8006eb0 <RCC_GetSysClockFreqFromPLLSource>
8006b74: 6138 str r0, [r7, #16]
/* Intermediate step with HCLK prescaler 2 necessary before to go over 80Mhz */
if(pllfreq > 80000000U)
8006b76: 693b ldr r3, [r7, #16]
8006b78: 4a7c ldr r2, [pc, #496] @ (8006d6c <HAL_RCC_ClockConfig+0x268>)
8006b7a: 4293 cmp r3, r2
8006b7c: d93f bls.n 8006bfe <HAL_RCC_ClockConfig+0xfa>
{
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
8006b7e: 4b7a ldr r3, [pc, #488] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006b80: 689b ldr r3, [r3, #8]
8006b82: f003 03f0 and.w r3, r3, #240 @ 0xf0
8006b86: 2b00 cmp r3, #0
8006b88: d009 beq.n 8006b9e <HAL_RCC_ClockConfig+0x9a>
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
8006b8a: 687b ldr r3, [r7, #4]
8006b8c: 681b ldr r3, [r3, #0]
8006b8e: f003 0302 and.w r3, r3, #2
if (((READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) == RCC_SYSCLK_DIV1)) ||
8006b92: 2b00 cmp r3, #0
8006b94: d033 beq.n 8006bfe <HAL_RCC_ClockConfig+0xfa>
(RCC_ClkInitStruct->AHBCLKDivider == RCC_SYSCLK_DIV1))))
8006b96: 687b ldr r3, [r7, #4]
8006b98: 689b ldr r3, [r3, #8]
(((((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) &&
8006b9a: 2b00 cmp r3, #0
8006b9c: d12f bne.n 8006bfe <HAL_RCC_ClockConfig+0xfa>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
8006b9e: 4b72 ldr r3, [pc, #456] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006ba0: 689b ldr r3, [r3, #8]
8006ba2: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8006ba6: 4a70 ldr r2, [pc, #448] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006ba8: f043 0380 orr.w r3, r3, #128 @ 0x80
8006bac: 6093 str r3, [r2, #8]
hpre = RCC_SYSCLK_DIV2;
8006bae: 2380 movs r3, #128 @ 0x80
8006bb0: 617b str r3, [r7, #20]
8006bb2: e024 b.n 8006bfe <HAL_RCC_ClockConfig+0xfa>
}
}
else
{
/* HSE is selected as System Clock Source */
if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
8006bb4: 687b ldr r3, [r7, #4]
8006bb6: 685b ldr r3, [r3, #4]
8006bb8: 2b02 cmp r3, #2
8006bba: d107 bne.n 8006bcc <HAL_RCC_ClockConfig+0xc8>
{
/* Check the HSE ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
8006bbc: 4b6a ldr r3, [pc, #424] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006bbe: 681b ldr r3, [r3, #0]
8006bc0: f403 3300 and.w r3, r3, #131072 @ 0x20000
8006bc4: 2b00 cmp r3, #0
8006bc6: d109 bne.n 8006bdc <HAL_RCC_ClockConfig+0xd8>
{
return HAL_ERROR;
8006bc8: 2301 movs r3, #1
8006bca: e0c6 b.n 8006d5a <HAL_RCC_ClockConfig+0x256>
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
8006bcc: 4b66 ldr r3, [pc, #408] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006bce: 681b ldr r3, [r3, #0]
8006bd0: f403 6380 and.w r3, r3, #1024 @ 0x400
8006bd4: 2b00 cmp r3, #0
8006bd6: d101 bne.n 8006bdc <HAL_RCC_ClockConfig+0xd8>
{
return HAL_ERROR;
8006bd8: 2301 movs r3, #1
8006bda: e0be b.n 8006d5a <HAL_RCC_ClockConfig+0x256>
}
}
/* Overshoot management when going down from PLL as SYSCLK source and frequency above 80Mhz */
pllfreq = HAL_RCC_GetSysClockFreq();
8006bdc: f000 f8ce bl 8006d7c <HAL_RCC_GetSysClockFreq>
8006be0: 6138 str r0, [r7, #16]
/* Intermediate step with HCLK prescaler 2 necessary before to go under 80Mhz */
if(pllfreq > 80000000U)
8006be2: 693b ldr r3, [r7, #16]
8006be4: 4a61 ldr r2, [pc, #388] @ (8006d6c <HAL_RCC_ClockConfig+0x268>)
8006be6: 4293 cmp r3, r2
8006be8: d909 bls.n 8006bfe <HAL_RCC_ClockConfig+0xfa>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV2);
8006bea: 4b5f ldr r3, [pc, #380] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006bec: 689b ldr r3, [r3, #8]
8006bee: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8006bf2: 4a5d ldr r2, [pc, #372] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006bf4: f043 0380 orr.w r3, r3, #128 @ 0x80
8006bf8: 6093 str r3, [r2, #8]
hpre = RCC_SYSCLK_DIV2;
8006bfa: 2380 movs r3, #128 @ 0x80
8006bfc: 617b str r3, [r7, #20]
}
}
MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
8006bfe: 4b5a ldr r3, [pc, #360] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006c00: 689b ldr r3, [r3, #8]
8006c02: f023 0203 bic.w r2, r3, #3
8006c06: 687b ldr r3, [r7, #4]
8006c08: 685b ldr r3, [r3, #4]
8006c0a: 4957 ldr r1, [pc, #348] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006c0c: 4313 orrs r3, r2
8006c0e: 608b str r3, [r1, #8]
/* Get Start Tick*/
tickstart = HAL_GetTick();
8006c10: f7fa ff6c bl 8001aec <HAL_GetTick>
8006c14: 60f8 str r0, [r7, #12]
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8006c16: e00a b.n 8006c2e <HAL_RCC_ClockConfig+0x12a>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8006c18: f7fa ff68 bl 8001aec <HAL_GetTick>
8006c1c: 4602 mov r2, r0
8006c1e: 68fb ldr r3, [r7, #12]
8006c20: 1ad3 subs r3, r2, r3
8006c22: f241 3288 movw r2, #5000 @ 0x1388
8006c26: 4293 cmp r3, r2
8006c28: d901 bls.n 8006c2e <HAL_RCC_ClockConfig+0x12a>
{
return HAL_TIMEOUT;
8006c2a: 2303 movs r3, #3
8006c2c: e095 b.n 8006d5a <HAL_RCC_ClockConfig+0x256>
while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
8006c2e: 4b4e ldr r3, [pc, #312] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006c30: 689b ldr r3, [r3, #8]
8006c32: f003 020c and.w r2, r3, #12
8006c36: 687b ldr r3, [r7, #4]
8006c38: 685b ldr r3, [r3, #4]
8006c3a: 009b lsls r3, r3, #2
8006c3c: 429a cmp r2, r3
8006c3e: d1eb bne.n 8006c18 <HAL_RCC_ClockConfig+0x114>
}
}
}
/*-------------------------- HCLK Configuration --------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
8006c40: 687b ldr r3, [r7, #4]
8006c42: 681b ldr r3, [r3, #0]
8006c44: f003 0302 and.w r3, r3, #2
8006c48: 2b00 cmp r3, #0
8006c4a: d023 beq.n 8006c94 <HAL_RCC_ClockConfig+0x190>
{
/* Set the highest APB divider in order to ensure that we do not go through
a non-spec phase whatever we decrease or increase HCLK. */
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8006c4c: 687b ldr r3, [r7, #4]
8006c4e: 681b ldr r3, [r3, #0]
8006c50: f003 0304 and.w r3, r3, #4
8006c54: 2b00 cmp r3, #0
8006c56: d005 beq.n 8006c64 <HAL_RCC_ClockConfig+0x160>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
8006c58: 4b43 ldr r3, [pc, #268] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006c5a: 689b ldr r3, [r3, #8]
8006c5c: 4a42 ldr r2, [pc, #264] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006c5e: f443 63e0 orr.w r3, r3, #1792 @ 0x700
8006c62: 6093 str r3, [r2, #8]
}
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8006c64: 687b ldr r3, [r7, #4]
8006c66: 681b ldr r3, [r3, #0]
8006c68: f003 0308 and.w r3, r3, #8
8006c6c: 2b00 cmp r3, #0
8006c6e: d007 beq.n 8006c80 <HAL_RCC_ClockConfig+0x17c>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, RCC_HCLK_DIV16);
8006c70: 4b3d ldr r3, [pc, #244] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006c72: 689b ldr r3, [r3, #8]
8006c74: f423 537c bic.w r3, r3, #16128 @ 0x3f00
8006c78: 4a3b ldr r2, [pc, #236] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006c7a: f443 63e0 orr.w r3, r3, #1792 @ 0x700
8006c7e: 6093 str r3, [r2, #8]
}
/* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
8006c80: 4b39 ldr r3, [pc, #228] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006c82: 689b ldr r3, [r3, #8]
8006c84: f023 02f0 bic.w r2, r3, #240 @ 0xf0
8006c88: 687b ldr r3, [r7, #4]
8006c8a: 689b ldr r3, [r3, #8]
8006c8c: 4936 ldr r1, [pc, #216] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006c8e: 4313 orrs r3, r2
8006c90: 608b str r3, [r1, #8]
8006c92: e008 b.n 8006ca6 <HAL_RCC_ClockConfig+0x1a2>
}
else
{
/* Is intermediate HCLK prescaler 2 applied internally, complete with HCLK prescaler 1 */
if(hpre == RCC_SYSCLK_DIV2)
8006c94: 697b ldr r3, [r7, #20]
8006c96: 2b80 cmp r3, #128 @ 0x80
8006c98: d105 bne.n 8006ca6 <HAL_RCC_ClockConfig+0x1a2>
{
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_SYSCLK_DIV1);
8006c9a: 4b33 ldr r3, [pc, #204] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006c9c: 689b ldr r3, [r3, #8]
8006c9e: 4a32 ldr r2, [pc, #200] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006ca0: f023 03f0 bic.w r3, r3, #240 @ 0xf0
8006ca4: 6093 str r3, [r2, #8]
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if (FLatency < __HAL_FLASH_GET_LATENCY())
8006ca6: 4b2f ldr r3, [pc, #188] @ (8006d64 <HAL_RCC_ClockConfig+0x260>)
8006ca8: 681b ldr r3, [r3, #0]
8006caa: f003 030f and.w r3, r3, #15
8006cae: 683a ldr r2, [r7, #0]
8006cb0: 429a cmp r2, r3
8006cb2: d21d bcs.n 8006cf0 <HAL_RCC_ClockConfig+0x1ec>
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
8006cb4: 4b2b ldr r3, [pc, #172] @ (8006d64 <HAL_RCC_ClockConfig+0x260>)
8006cb6: 681b ldr r3, [r3, #0]
8006cb8: f023 020f bic.w r2, r3, #15
8006cbc: 4929 ldr r1, [pc, #164] @ (8006d64 <HAL_RCC_ClockConfig+0x260>)
8006cbe: 683b ldr r3, [r7, #0]
8006cc0: 4313 orrs r3, r2
8006cc2: 600b str r3, [r1, #0]
/* Check that the new number of wait states is taken into account to access the Flash
memory by polling the FLASH_ACR register */
tickstart = HAL_GetTick();
8006cc4: f7fa ff12 bl 8001aec <HAL_GetTick>
8006cc8: 60f8 str r0, [r7, #12]
while (__HAL_FLASH_GET_LATENCY() != FLatency)
8006cca: e00a b.n 8006ce2 <HAL_RCC_ClockConfig+0x1de>
{
if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
8006ccc: f7fa ff0e bl 8001aec <HAL_GetTick>
8006cd0: 4602 mov r2, r0
8006cd2: 68fb ldr r3, [r7, #12]
8006cd4: 1ad3 subs r3, r2, r3
8006cd6: f241 3288 movw r2, #5000 @ 0x1388
8006cda: 4293 cmp r3, r2
8006cdc: d901 bls.n 8006ce2 <HAL_RCC_ClockConfig+0x1de>
{
return HAL_TIMEOUT;
8006cde: 2303 movs r3, #3
8006ce0: e03b b.n 8006d5a <HAL_RCC_ClockConfig+0x256>
while (__HAL_FLASH_GET_LATENCY() != FLatency)
8006ce2: 4b20 ldr r3, [pc, #128] @ (8006d64 <HAL_RCC_ClockConfig+0x260>)
8006ce4: 681b ldr r3, [r3, #0]
8006ce6: f003 030f and.w r3, r3, #15
8006cea: 683a ldr r2, [r7, #0]
8006cec: 429a cmp r2, r3
8006cee: d1ed bne.n 8006ccc <HAL_RCC_ClockConfig+0x1c8>
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
8006cf0: 687b ldr r3, [r7, #4]
8006cf2: 681b ldr r3, [r3, #0]
8006cf4: f003 0304 and.w r3, r3, #4
8006cf8: 2b00 cmp r3, #0
8006cfa: d008 beq.n 8006d0e <HAL_RCC_ClockConfig+0x20a>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
8006cfc: 4b1a ldr r3, [pc, #104] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006cfe: 689b ldr r3, [r3, #8]
8006d00: f423 62e0 bic.w r2, r3, #1792 @ 0x700
8006d04: 687b ldr r3, [r7, #4]
8006d06: 68db ldr r3, [r3, #12]
8006d08: 4917 ldr r1, [pc, #92] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006d0a: 4313 orrs r3, r2
8006d0c: 608b str r3, [r1, #8]
}
/*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
8006d0e: 687b ldr r3, [r7, #4]
8006d10: 681b ldr r3, [r3, #0]
8006d12: f003 0308 and.w r3, r3, #8
8006d16: 2b00 cmp r3, #0
8006d18: d009 beq.n 8006d2e <HAL_RCC_ClockConfig+0x22a>
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3U));
8006d1a: 4b13 ldr r3, [pc, #76] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006d1c: 689b ldr r3, [r3, #8]
8006d1e: f423 5260 bic.w r2, r3, #14336 @ 0x3800
8006d22: 687b ldr r3, [r7, #4]
8006d24: 691b ldr r3, [r3, #16]
8006d26: 00db lsls r3, r3, #3
8006d28: 490f ldr r1, [pc, #60] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006d2a: 4313 orrs r3, r2
8006d2c: 608b str r3, [r1, #8]
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> (AHBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU);
8006d2e: f000 f825 bl 8006d7c <HAL_RCC_GetSysClockFreq>
8006d32: 4602 mov r2, r0
8006d34: 4b0c ldr r3, [pc, #48] @ (8006d68 <HAL_RCC_ClockConfig+0x264>)
8006d36: 689b ldr r3, [r3, #8]
8006d38: 091b lsrs r3, r3, #4
8006d3a: f003 030f and.w r3, r3, #15
8006d3e: 490c ldr r1, [pc, #48] @ (8006d70 <HAL_RCC_ClockConfig+0x26c>)
8006d40: 5ccb ldrb r3, [r1, r3]
8006d42: f003 031f and.w r3, r3, #31
8006d46: fa22 f303 lsr.w r3, r2, r3
8006d4a: 4a0a ldr r2, [pc, #40] @ (8006d74 <HAL_RCC_ClockConfig+0x270>)
8006d4c: 6013 str r3, [r2, #0]
/* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick(uwTickPrio);
8006d4e: 4b0a ldr r3, [pc, #40] @ (8006d78 <HAL_RCC_ClockConfig+0x274>)
8006d50: 681b ldr r3, [r3, #0]
8006d52: 4618 mov r0, r3
8006d54: f7fa fe7e bl 8001a54 <HAL_InitTick>
8006d58: 4603 mov r3, r0
}
8006d5a: 4618 mov r0, r3
8006d5c: 3718 adds r7, #24
8006d5e: 46bd mov sp, r7
8006d60: bd80 pop {r7, pc}
8006d62: bf00 nop
8006d64: 40022000 .word 0x40022000
8006d68: 40021000 .word 0x40021000
8006d6c: 04c4b400 .word 0x04c4b400
8006d70: 08009800 .word 0x08009800
8006d74: 20000000 .word 0x20000000
8006d78: 20000004 .word 0x20000004
08006d7c <HAL_RCC_GetSysClockFreq>:
*
*
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
{
8006d7c: b480 push {r7}
8006d7e: b087 sub sp, #28
8006d80: af00 add r7, sp, #0
uint32_t pllvco, pllsource, pllr, pllm;
uint32_t sysclockfreq;
if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
8006d82: 4b2c ldr r3, [pc, #176] @ (8006e34 <HAL_RCC_GetSysClockFreq+0xb8>)
8006d84: 689b ldr r3, [r3, #8]
8006d86: f003 030c and.w r3, r3, #12
8006d8a: 2b04 cmp r3, #4
8006d8c: d102 bne.n 8006d94 <HAL_RCC_GetSysClockFreq+0x18>
{
/* HSI used as system clock source */
sysclockfreq = HSI_VALUE;
8006d8e: 4b2a ldr r3, [pc, #168] @ (8006e38 <HAL_RCC_GetSysClockFreq+0xbc>)
8006d90: 613b str r3, [r7, #16]
8006d92: e047 b.n 8006e24 <HAL_RCC_GetSysClockFreq+0xa8>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
8006d94: 4b27 ldr r3, [pc, #156] @ (8006e34 <HAL_RCC_GetSysClockFreq+0xb8>)
8006d96: 689b ldr r3, [r3, #8]
8006d98: f003 030c and.w r3, r3, #12
8006d9c: 2b08 cmp r3, #8
8006d9e: d102 bne.n 8006da6 <HAL_RCC_GetSysClockFreq+0x2a>
{
/* HSE used as system clock source */
sysclockfreq = HSE_VALUE;
8006da0: 4b26 ldr r3, [pc, #152] @ (8006e3c <HAL_RCC_GetSysClockFreq+0xc0>)
8006da2: 613b str r3, [r7, #16]
8006da4: e03e b.n 8006e24 <HAL_RCC_GetSysClockFreq+0xa8>
}
else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
8006da6: 4b23 ldr r3, [pc, #140] @ (8006e34 <HAL_RCC_GetSysClockFreq+0xb8>)
8006da8: 689b ldr r3, [r3, #8]
8006daa: f003 030c and.w r3, r3, #12
8006dae: 2b0c cmp r3, #12
8006db0: d136 bne.n 8006e20 <HAL_RCC_GetSysClockFreq+0xa4>
/* PLL used as system clock source */
/* PLL_VCO = ((HSE_VALUE or HSI_VALUE)/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
8006db2: 4b20 ldr r3, [pc, #128] @ (8006e34 <HAL_RCC_GetSysClockFreq+0xb8>)
8006db4: 68db ldr r3, [r3, #12]
8006db6: f003 0303 and.w r3, r3, #3
8006dba: 60fb str r3, [r7, #12]
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8006dbc: 4b1d ldr r3, [pc, #116] @ (8006e34 <HAL_RCC_GetSysClockFreq+0xb8>)
8006dbe: 68db ldr r3, [r3, #12]
8006dc0: 091b lsrs r3, r3, #4
8006dc2: f003 030f and.w r3, r3, #15
8006dc6: 3301 adds r3, #1
8006dc8: 60bb str r3, [r7, #8]
switch (pllsource)
8006dca: 68fb ldr r3, [r7, #12]
8006dcc: 2b03 cmp r3, #3
8006dce: d10c bne.n 8006dea <HAL_RCC_GetSysClockFreq+0x6e>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8006dd0: 4a1a ldr r2, [pc, #104] @ (8006e3c <HAL_RCC_GetSysClockFreq+0xc0>)
8006dd2: 68bb ldr r3, [r7, #8]
8006dd4: fbb2 f3f3 udiv r3, r2, r3
8006dd8: 4a16 ldr r2, [pc, #88] @ (8006e34 <HAL_RCC_GetSysClockFreq+0xb8>)
8006dda: 68d2 ldr r2, [r2, #12]
8006ddc: 0a12 lsrs r2, r2, #8
8006dde: f002 027f and.w r2, r2, #127 @ 0x7f
8006de2: fb02 f303 mul.w r3, r2, r3
8006de6: 617b str r3, [r7, #20]
break;
8006de8: e00c b.n 8006e04 <HAL_RCC_GetSysClockFreq+0x88>
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8006dea: 4a13 ldr r2, [pc, #76] @ (8006e38 <HAL_RCC_GetSysClockFreq+0xbc>)
8006dec: 68bb ldr r3, [r7, #8]
8006dee: fbb2 f3f3 udiv r3, r2, r3
8006df2: 4a10 ldr r2, [pc, #64] @ (8006e34 <HAL_RCC_GetSysClockFreq+0xb8>)
8006df4: 68d2 ldr r2, [r2, #12]
8006df6: 0a12 lsrs r2, r2, #8
8006df8: f002 027f and.w r2, r2, #127 @ 0x7f
8006dfc: fb02 f303 mul.w r3, r2, r3
8006e00: 617b str r3, [r7, #20]
break;
8006e02: bf00 nop
}
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
8006e04: 4b0b ldr r3, [pc, #44] @ (8006e34 <HAL_RCC_GetSysClockFreq+0xb8>)
8006e06: 68db ldr r3, [r3, #12]
8006e08: 0e5b lsrs r3, r3, #25
8006e0a: f003 0303 and.w r3, r3, #3
8006e0e: 3301 adds r3, #1
8006e10: 005b lsls r3, r3, #1
8006e12: 607b str r3, [r7, #4]
sysclockfreq = pllvco/pllr;
8006e14: 697a ldr r2, [r7, #20]
8006e16: 687b ldr r3, [r7, #4]
8006e18: fbb2 f3f3 udiv r3, r2, r3
8006e1c: 613b str r3, [r7, #16]
8006e1e: e001 b.n 8006e24 <HAL_RCC_GetSysClockFreq+0xa8>
}
else
{
sysclockfreq = 0U;
8006e20: 2300 movs r3, #0
8006e22: 613b str r3, [r7, #16]
}
return sysclockfreq;
8006e24: 693b ldr r3, [r7, #16]
}
8006e26: 4618 mov r0, r3
8006e28: 371c adds r7, #28
8006e2a: 46bd mov sp, r7
8006e2c: f85d 7b04 ldr.w r7, [sp], #4
8006e30: 4770 bx lr
8006e32: bf00 nop
8006e34: 40021000 .word 0x40021000
8006e38: 00f42400 .word 0x00f42400
8006e3c: 02625a00 .word 0x02625a00
08006e40 <HAL_RCC_GetHCLKFreq>:
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency in Hz
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
8006e40: b480 push {r7}
8006e42: af00 add r7, sp, #0
return SystemCoreClock;
8006e44: 4b03 ldr r3, [pc, #12] @ (8006e54 <HAL_RCC_GetHCLKFreq+0x14>)
8006e46: 681b ldr r3, [r3, #0]
}
8006e48: 4618 mov r0, r3
8006e4a: 46bd mov sp, r7
8006e4c: f85d 7b04 ldr.w r7, [sp], #4
8006e50: 4770 bx lr
8006e52: bf00 nop
8006e54: 20000000 .word 0x20000000
08006e58 <HAL_RCC_GetPCLK1Freq>:
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
8006e58: b580 push {r7, lr}
8006e5a: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1) >> RCC_CFGR_PPRE1_Pos] & 0x1FU));
8006e5c: f7ff fff0 bl 8006e40 <HAL_RCC_GetHCLKFreq>
8006e60: 4602 mov r2, r0
8006e62: 4b06 ldr r3, [pc, #24] @ (8006e7c <HAL_RCC_GetPCLK1Freq+0x24>)
8006e64: 689b ldr r3, [r3, #8]
8006e66: 0a1b lsrs r3, r3, #8
8006e68: f003 0307 and.w r3, r3, #7
8006e6c: 4904 ldr r1, [pc, #16] @ (8006e80 <HAL_RCC_GetPCLK1Freq+0x28>)
8006e6e: 5ccb ldrb r3, [r1, r3]
8006e70: f003 031f and.w r3, r3, #31
8006e74: fa22 f303 lsr.w r3, r2, r3
}
8006e78: 4618 mov r0, r3
8006e7a: bd80 pop {r7, pc}
8006e7c: 40021000 .word 0x40021000
8006e80: 08009810 .word 0x08009810
08006e84 <HAL_RCC_GetPCLK2Freq>:
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency in Hz
*/
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
8006e84: b580 push {r7, lr}
8006e86: af00 add r7, sp, #0
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> (APBPrescTable[READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2) >> RCC_CFGR_PPRE2_Pos] & 0x1FU));
8006e88: f7ff ffda bl 8006e40 <HAL_RCC_GetHCLKFreq>
8006e8c: 4602 mov r2, r0
8006e8e: 4b06 ldr r3, [pc, #24] @ (8006ea8 <HAL_RCC_GetPCLK2Freq+0x24>)
8006e90: 689b ldr r3, [r3, #8]
8006e92: 0adb lsrs r3, r3, #11
8006e94: f003 0307 and.w r3, r3, #7
8006e98: 4904 ldr r1, [pc, #16] @ (8006eac <HAL_RCC_GetPCLK2Freq+0x28>)
8006e9a: 5ccb ldrb r3, [r1, r3]
8006e9c: f003 031f and.w r3, r3, #31
8006ea0: fa22 f303 lsr.w r3, r2, r3
}
8006ea4: 4618 mov r0, r3
8006ea6: bd80 pop {r7, pc}
8006ea8: 40021000 .word 0x40021000
8006eac: 08009810 .word 0x08009810
08006eb0 <RCC_GetSysClockFreqFromPLLSource>:
/**
* @brief Compute SYSCLK frequency based on PLL SYSCLK source.
* @retval SYSCLK frequency
*/
static uint32_t RCC_GetSysClockFreqFromPLLSource(void)
{
8006eb0: b480 push {r7}
8006eb2: b087 sub sp, #28
8006eb4: af00 add r7, sp, #0
uint32_t sysclockfreq;
/* PLL_VCO = (HSE_VALUE or HSI_VALUE/ PLLM) * PLLN
SYSCLK = PLL_VCO / PLLR
*/
pllsource = READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC);
8006eb6: 4b1e ldr r3, [pc, #120] @ (8006f30 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8006eb8: 68db ldr r3, [r3, #12]
8006eba: f003 0303 and.w r3, r3, #3
8006ebe: 613b str r3, [r7, #16]
pllm = (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1U ;
8006ec0: 4b1b ldr r3, [pc, #108] @ (8006f30 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8006ec2: 68db ldr r3, [r3, #12]
8006ec4: 091b lsrs r3, r3, #4
8006ec6: f003 030f and.w r3, r3, #15
8006eca: 3301 adds r3, #1
8006ecc: 60fb str r3, [r7, #12]
switch (pllsource)
8006ece: 693b ldr r3, [r7, #16]
8006ed0: 2b03 cmp r3, #3
8006ed2: d10c bne.n 8006eee <RCC_GetSysClockFreqFromPLLSource+0x3e>
{
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
pllvco = (HSE_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8006ed4: 4a17 ldr r2, [pc, #92] @ (8006f34 <RCC_GetSysClockFreqFromPLLSource+0x84>)
8006ed6: 68fb ldr r3, [r7, #12]
8006ed8: fbb2 f3f3 udiv r3, r2, r3
8006edc: 4a14 ldr r2, [pc, #80] @ (8006f30 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8006ede: 68d2 ldr r2, [r2, #12]
8006ee0: 0a12 lsrs r2, r2, #8
8006ee2: f002 027f and.w r2, r2, #127 @ 0x7f
8006ee6: fb02 f303 mul.w r3, r2, r3
8006eea: 617b str r3, [r7, #20]
break;
8006eec: e00c b.n 8006f08 <RCC_GetSysClockFreqFromPLLSource+0x58>
case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */
default:
pllvco = (HSI_VALUE / pllm) * (READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
8006eee: 4a12 ldr r2, [pc, #72] @ (8006f38 <RCC_GetSysClockFreqFromPLLSource+0x88>)
8006ef0: 68fb ldr r3, [r7, #12]
8006ef2: fbb2 f3f3 udiv r3, r2, r3
8006ef6: 4a0e ldr r2, [pc, #56] @ (8006f30 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8006ef8: 68d2 ldr r2, [r2, #12]
8006efa: 0a12 lsrs r2, r2, #8
8006efc: f002 027f and.w r2, r2, #127 @ 0x7f
8006f00: fb02 f303 mul.w r3, r2, r3
8006f04: 617b str r3, [r7, #20]
break;
8006f06: bf00 nop
}
pllr = ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1U ) * 2U;
8006f08: 4b09 ldr r3, [pc, #36] @ (8006f30 <RCC_GetSysClockFreqFromPLLSource+0x80>)
8006f0a: 68db ldr r3, [r3, #12]
8006f0c: 0e5b lsrs r3, r3, #25
8006f0e: f003 0303 and.w r3, r3, #3
8006f12: 3301 adds r3, #1
8006f14: 005b lsls r3, r3, #1
8006f16: 60bb str r3, [r7, #8]
sysclockfreq = pllvco/pllr;
8006f18: 697a ldr r2, [r7, #20]
8006f1a: 68bb ldr r3, [r7, #8]
8006f1c: fbb2 f3f3 udiv r3, r2, r3
8006f20: 607b str r3, [r7, #4]
return sysclockfreq;
8006f22: 687b ldr r3, [r7, #4]
}
8006f24: 4618 mov r0, r3
8006f26: 371c adds r7, #28
8006f28: 46bd mov sp, r7
8006f2a: f85d 7b04 ldr.w r7, [sp], #4
8006f2e: 4770 bx lr
8006f30: 40021000 .word 0x40021000
8006f34: 02625a00 .word 0x02625a00
8006f38: 00f42400 .word 0x00f42400
08006f3c <HAL_RCCEx_PeriphCLKConfig>:
* the RTC clock source: in this case the access to Backup domain is enabled.
*
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
8006f3c: b580 push {r7, lr}
8006f3e: b086 sub sp, #24
8006f40: af00 add r7, sp, #0
8006f42: 6078 str r0, [r7, #4]
uint32_t tmpregister;
uint32_t tickstart;
HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */
8006f44: 2300 movs r3, #0
8006f46: 74fb strb r3, [r7, #19]
HAL_StatusTypeDef status = HAL_OK; /* Final status */
8006f48: 2300 movs r3, #0
8006f4a: 74bb strb r3, [r7, #18]
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
/*-------------------------- RTC clock source configuration ----------------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
8006f4c: 687b ldr r3, [r7, #4]
8006f4e: 681b ldr r3, [r3, #0]
8006f50: f403 2300 and.w r3, r3, #524288 @ 0x80000
8006f54: 2b00 cmp r3, #0
8006f56: f000 8098 beq.w 800708a <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
FlagStatus pwrclkchanged = RESET;
8006f5a: 2300 movs r3, #0
8006f5c: 747b strb r3, [r7, #17]
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
8006f5e: 4b43 ldr r3, [pc, #268] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006f60: 6d9b ldr r3, [r3, #88] @ 0x58
8006f62: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8006f66: 2b00 cmp r3, #0
8006f68: d10d bne.n 8006f86 <HAL_RCCEx_PeriphCLKConfig+0x4a>
{
__HAL_RCC_PWR_CLK_ENABLE();
8006f6a: 4b40 ldr r3, [pc, #256] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006f6c: 6d9b ldr r3, [r3, #88] @ 0x58
8006f6e: 4a3f ldr r2, [pc, #252] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006f70: f043 5380 orr.w r3, r3, #268435456 @ 0x10000000
8006f74: 6593 str r3, [r2, #88] @ 0x58
8006f76: 4b3d ldr r3, [pc, #244] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006f78: 6d9b ldr r3, [r3, #88] @ 0x58
8006f7a: f003 5380 and.w r3, r3, #268435456 @ 0x10000000
8006f7e: 60bb str r3, [r7, #8]
8006f80: 68bb ldr r3, [r7, #8]
pwrclkchanged = SET;
8006f82: 2301 movs r3, #1
8006f84: 747b strb r3, [r7, #17]
}
/* Enable write access to Backup domain */
SET_BIT(PWR->CR1, PWR_CR1_DBP);
8006f86: 4b3a ldr r3, [pc, #232] @ (8007070 <HAL_RCCEx_PeriphCLKConfig+0x134>)
8006f88: 681b ldr r3, [r3, #0]
8006f8a: 4a39 ldr r2, [pc, #228] @ (8007070 <HAL_RCCEx_PeriphCLKConfig+0x134>)
8006f8c: f443 7380 orr.w r3, r3, #256 @ 0x100
8006f90: 6013 str r3, [r2, #0]
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
8006f92: f7fa fdab bl 8001aec <HAL_GetTick>
8006f96: 60f8 str r0, [r7, #12]
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
8006f98: e009 b.n 8006fae <HAL_RCCEx_PeriphCLKConfig+0x72>
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
8006f9a: f7fa fda7 bl 8001aec <HAL_GetTick>
8006f9e: 4602 mov r2, r0
8006fa0: 68fb ldr r3, [r7, #12]
8006fa2: 1ad3 subs r3, r2, r3
8006fa4: 2b02 cmp r3, #2
8006fa6: d902 bls.n 8006fae <HAL_RCCEx_PeriphCLKConfig+0x72>
{
ret = HAL_TIMEOUT;
8006fa8: 2303 movs r3, #3
8006faa: 74fb strb r3, [r7, #19]
break;
8006fac: e005 b.n 8006fba <HAL_RCCEx_PeriphCLKConfig+0x7e>
while((PWR->CR1 & PWR_CR1_DBP) == 0U)
8006fae: 4b30 ldr r3, [pc, #192] @ (8007070 <HAL_RCCEx_PeriphCLKConfig+0x134>)
8006fb0: 681b ldr r3, [r3, #0]
8006fb2: f403 7380 and.w r3, r3, #256 @ 0x100
8006fb6: 2b00 cmp r3, #0
8006fb8: d0ef beq.n 8006f9a <HAL_RCCEx_PeriphCLKConfig+0x5e>
}
}
if(ret == HAL_OK)
8006fba: 7cfb ldrb r3, [r7, #19]
8006fbc: 2b00 cmp r3, #0
8006fbe: d159 bne.n 8007074 <HAL_RCCEx_PeriphCLKConfig+0x138>
{
/* Reset the Backup domain only if the RTC Clock source selection is modified from default */
tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL);
8006fc0: 4b2a ldr r3, [pc, #168] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006fc2: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8006fc6: f403 7340 and.w r3, r3, #768 @ 0x300
8006fca: 617b str r3, [r7, #20]
if((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
8006fcc: 697b ldr r3, [r7, #20]
8006fce: 2b00 cmp r3, #0
8006fd0: d01e beq.n 8007010 <HAL_RCCEx_PeriphCLKConfig+0xd4>
8006fd2: 687b ldr r3, [r7, #4]
8006fd4: 6d1b ldr r3, [r3, #80] @ 0x50
8006fd6: 697a ldr r2, [r7, #20]
8006fd8: 429a cmp r2, r3
8006fda: d019 beq.n 8007010 <HAL_RCCEx_PeriphCLKConfig+0xd4>
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL));
8006fdc: 4b23 ldr r3, [pc, #140] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006fde: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8006fe2: f423 7340 bic.w r3, r3, #768 @ 0x300
8006fe6: 617b str r3, [r7, #20]
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
8006fe8: 4b20 ldr r3, [pc, #128] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006fea: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8006fee: 4a1f ldr r2, [pc, #124] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006ff0: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8006ff4: f8c2 3090 str.w r3, [r2, #144] @ 0x90
__HAL_RCC_BACKUPRESET_RELEASE();
8006ff8: 4b1c ldr r3, [pc, #112] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
8006ffa: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8006ffe: 4a1b ldr r2, [pc, #108] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
8007000: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8007004: f8c2 3090 str.w r3, [r2, #144] @ 0x90
/* Restore the Content of BDCR register */
RCC->BDCR = tmpregister;
8007008: 4a18 ldr r2, [pc, #96] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
800700a: 697b ldr r3, [r7, #20]
800700c: f8c2 3090 str.w r3, [r2, #144] @ 0x90
}
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON))
8007010: 697b ldr r3, [r7, #20]
8007012: f003 0301 and.w r3, r3, #1
8007016: 2b00 cmp r3, #0
8007018: d016 beq.n 8007048 <HAL_RCCEx_PeriphCLKConfig+0x10c>
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
800701a: f7fa fd67 bl 8001aec <HAL_GetTick>
800701e: 60f8 str r0, [r7, #12]
/* Wait till LSE is ready */
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
8007020: e00b b.n 800703a <HAL_RCCEx_PeriphCLKConfig+0xfe>
{
if((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
8007022: f7fa fd63 bl 8001aec <HAL_GetTick>
8007026: 4602 mov r2, r0
8007028: 68fb ldr r3, [r7, #12]
800702a: 1ad3 subs r3, r2, r3
800702c: f241 3288 movw r2, #5000 @ 0x1388
8007030: 4293 cmp r3, r2
8007032: d902 bls.n 800703a <HAL_RCCEx_PeriphCLKConfig+0xfe>
{
ret = HAL_TIMEOUT;
8007034: 2303 movs r3, #3
8007036: 74fb strb r3, [r7, #19]
break;
8007038: e006 b.n 8007048 <HAL_RCCEx_PeriphCLKConfig+0x10c>
while(READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U)
800703a: 4b0c ldr r3, [pc, #48] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
800703c: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007040: f003 0302 and.w r3, r3, #2
8007044: 2b00 cmp r3, #0
8007046: d0ec beq.n 8007022 <HAL_RCCEx_PeriphCLKConfig+0xe6>
}
}
}
if(ret == HAL_OK)
8007048: 7cfb ldrb r3, [r7, #19]
800704a: 2b00 cmp r3, #0
800704c: d10b bne.n 8007066 <HAL_RCCEx_PeriphCLKConfig+0x12a>
{
/* Apply new RTC clock source selection */
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
800704e: 4b07 ldr r3, [pc, #28] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
8007050: f8d3 3090 ldr.w r3, [r3, #144] @ 0x90
8007054: f423 7240 bic.w r2, r3, #768 @ 0x300
8007058: 687b ldr r3, [r7, #4]
800705a: 6d1b ldr r3, [r3, #80] @ 0x50
800705c: 4903 ldr r1, [pc, #12] @ (800706c <HAL_RCCEx_PeriphCLKConfig+0x130>)
800705e: 4313 orrs r3, r2
8007060: f8c1 3090 str.w r3, [r1, #144] @ 0x90
8007064: e008 b.n 8007078 <HAL_RCCEx_PeriphCLKConfig+0x13c>
}
else
{
/* set overall return value */
status = ret;
8007066: 7cfb ldrb r3, [r7, #19]
8007068: 74bb strb r3, [r7, #18]
800706a: e005 b.n 8007078 <HAL_RCCEx_PeriphCLKConfig+0x13c>
800706c: 40021000 .word 0x40021000
8007070: 40007000 .word 0x40007000
}
}
else
{
/* set overall return value */
status = ret;
8007074: 7cfb ldrb r3, [r7, #19]
8007076: 74bb strb r3, [r7, #18]
}
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
8007078: 7c7b ldrb r3, [r7, #17]
800707a: 2b01 cmp r3, #1
800707c: d105 bne.n 800708a <HAL_RCCEx_PeriphCLKConfig+0x14e>
{
__HAL_RCC_PWR_CLK_DISABLE();
800707e: 4ba7 ldr r3, [pc, #668] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007080: 6d9b ldr r3, [r3, #88] @ 0x58
8007082: 4aa6 ldr r2, [pc, #664] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007084: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
8007088: 6593 str r3, [r2, #88] @ 0x58
}
}
/*-------------------------- USART1 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
800708a: 687b ldr r3, [r7, #4]
800708c: 681b ldr r3, [r3, #0]
800708e: f003 0301 and.w r3, r3, #1
8007092: 2b00 cmp r3, #0
8007094: d00a beq.n 80070ac <HAL_RCCEx_PeriphCLKConfig+0x170>
{
/* Check the parameters */
assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
/* Configure the USART1 clock source */
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
8007096: 4ba1 ldr r3, [pc, #644] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007098: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800709c: f023 0203 bic.w r2, r3, #3
80070a0: 687b ldr r3, [r7, #4]
80070a2: 685b ldr r3, [r3, #4]
80070a4: 499d ldr r1, [pc, #628] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80070a6: 4313 orrs r3, r2
80070a8: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- USART2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2)
80070ac: 687b ldr r3, [r7, #4]
80070ae: 681b ldr r3, [r3, #0]
80070b0: f003 0302 and.w r3, r3, #2
80070b4: 2b00 cmp r3, #0
80070b6: d00a beq.n 80070ce <HAL_RCCEx_PeriphCLKConfig+0x192>
{
/* Check the parameters */
assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection));
/* Configure the USART2 clock source */
__HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection);
80070b8: 4b98 ldr r3, [pc, #608] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80070ba: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80070be: f023 020c bic.w r2, r3, #12
80070c2: 687b ldr r3, [r7, #4]
80070c4: 689b ldr r3, [r3, #8]
80070c6: 4995 ldr r1, [pc, #596] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80070c8: 4313 orrs r3, r2
80070ca: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(USART3)
/*-------------------------- USART3 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3)
80070ce: 687b ldr r3, [r7, #4]
80070d0: 681b ldr r3, [r3, #0]
80070d2: f003 0304 and.w r3, r3, #4
80070d6: 2b00 cmp r3, #0
80070d8: d00a beq.n 80070f0 <HAL_RCCEx_PeriphCLKConfig+0x1b4>
{
/* Check the parameters */
assert_param(IS_RCC_USART3CLKSOURCE(PeriphClkInit->Usart3ClockSelection));
/* Configure the USART3 clock source */
__HAL_RCC_USART3_CONFIG(PeriphClkInit->Usart3ClockSelection);
80070da: 4b90 ldr r3, [pc, #576] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80070dc: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80070e0: f023 0230 bic.w r2, r3, #48 @ 0x30
80070e4: 687b ldr r3, [r7, #4]
80070e6: 68db ldr r3, [r3, #12]
80070e8: 498c ldr r1, [pc, #560] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80070ea: 4313 orrs r3, r2
80070ec: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* USART3 */
#if defined(UART4)
/*-------------------------- UART4 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4)
80070f0: 687b ldr r3, [r7, #4]
80070f2: 681b ldr r3, [r3, #0]
80070f4: f003 0308 and.w r3, r3, #8
80070f8: 2b00 cmp r3, #0
80070fa: d00a beq.n 8007112 <HAL_RCCEx_PeriphCLKConfig+0x1d6>
{
/* Check the parameters */
assert_param(IS_RCC_UART4CLKSOURCE(PeriphClkInit->Uart4ClockSelection));
/* Configure the UART4 clock source */
__HAL_RCC_UART4_CONFIG(PeriphClkInit->Uart4ClockSelection);
80070fc: 4b87 ldr r3, [pc, #540] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80070fe: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8007102: f023 02c0 bic.w r2, r3, #192 @ 0xc0
8007106: 687b ldr r3, [r7, #4]
8007108: 691b ldr r3, [r3, #16]
800710a: 4984 ldr r1, [pc, #528] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
800710c: 4313 orrs r3, r2
800710e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* UART4 */
#if defined(UART5)
/*-------------------------- UART5 clock source configuration --------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5)
8007112: 687b ldr r3, [r7, #4]
8007114: 681b ldr r3, [r3, #0]
8007116: f003 0310 and.w r3, r3, #16
800711a: 2b00 cmp r3, #0
800711c: d00a beq.n 8007134 <HAL_RCCEx_PeriphCLKConfig+0x1f8>
{
/* Check the parameters */
assert_param(IS_RCC_UART5CLKSOURCE(PeriphClkInit->Uart5ClockSelection));
/* Configure the UART5 clock source */
__HAL_RCC_UART5_CONFIG(PeriphClkInit->Uart5ClockSelection);
800711e: 4b7f ldr r3, [pc, #508] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007120: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8007124: f423 7240 bic.w r2, r3, #768 @ 0x300
8007128: 687b ldr r3, [r7, #4]
800712a: 695b ldr r3, [r3, #20]
800712c: 497b ldr r1, [pc, #492] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
800712e: 4313 orrs r3, r2
8007130: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#endif /* UART5 */
/*-------------------------- LPUART1 clock source configuration ------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
8007134: 687b ldr r3, [r7, #4]
8007136: 681b ldr r3, [r3, #0]
8007138: f003 0320 and.w r3, r3, #32
800713c: 2b00 cmp r3, #0
800713e: d00a beq.n 8007156 <HAL_RCCEx_PeriphCLKConfig+0x21a>
{
/* Check the parameters */
assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection));
/* Configure the LPUAR1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
8007140: 4b76 ldr r3, [pc, #472] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007142: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8007146: f423 6240 bic.w r2, r3, #3072 @ 0xc00
800714a: 687b ldr r3, [r7, #4]
800714c: 699b ldr r3, [r3, #24]
800714e: 4973 ldr r1, [pc, #460] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007150: 4313 orrs r3, r2
8007152: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- I2C1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
8007156: 687b ldr r3, [r7, #4]
8007158: 681b ldr r3, [r3, #0]
800715a: f003 0340 and.w r3, r3, #64 @ 0x40
800715e: 2b00 cmp r3, #0
8007160: d00a beq.n 8007178 <HAL_RCCEx_PeriphCLKConfig+0x23c>
{
/* Check the parameters */
assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
/* Configure the I2C1 clock source */
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
8007162: 4b6e ldr r3, [pc, #440] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007164: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8007168: f423 5240 bic.w r2, r3, #12288 @ 0x3000
800716c: 687b ldr r3, [r7, #4]
800716e: 69db ldr r3, [r3, #28]
8007170: 496a ldr r1, [pc, #424] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007172: 4313 orrs r3, r2
8007174: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
/*-------------------------- I2C2 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2)
8007178: 687b ldr r3, [r7, #4]
800717a: 681b ldr r3, [r3, #0]
800717c: f003 0380 and.w r3, r3, #128 @ 0x80
8007180: 2b00 cmp r3, #0
8007182: d00a beq.n 800719a <HAL_RCCEx_PeriphCLKConfig+0x25e>
{
/* Check the parameters */
assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection));
/* Configure the I2C2 clock source */
__HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection);
8007184: 4b65 ldr r3, [pc, #404] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007186: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800718a: f423 4240 bic.w r2, r3, #49152 @ 0xc000
800718e: 687b ldr r3, [r7, #4]
8007190: 6a1b ldr r3, [r3, #32]
8007192: 4962 ldr r1, [pc, #392] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007194: 4313 orrs r3, r2
8007196: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(I2C3)
/*-------------------------- I2C3 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
800719a: 687b ldr r3, [r7, #4]
800719c: 681b ldr r3, [r3, #0]
800719e: f403 7380 and.w r3, r3, #256 @ 0x100
80071a2: 2b00 cmp r3, #0
80071a4: d00a beq.n 80071bc <HAL_RCCEx_PeriphCLKConfig+0x280>
{
/* Check the parameters */
assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection));
/* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
80071a6: 4b5d ldr r3, [pc, #372] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80071a8: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80071ac: f423 3240 bic.w r2, r3, #196608 @ 0x30000
80071b0: 687b ldr r3, [r7, #4]
80071b2: 6a5b ldr r3, [r3, #36] @ 0x24
80071b4: 4959 ldr r1, [pc, #356] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80071b6: 4313 orrs r3, r2
80071b8: f8c1 3088 str.w r3, [r1, #136] @ 0x88
#endif /* I2C3 */
#if defined(I2C4)
/*-------------------------- I2C4 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4)
80071bc: 687b ldr r3, [r7, #4]
80071be: 681b ldr r3, [r3, #0]
80071c0: f403 3300 and.w r3, r3, #131072 @ 0x20000
80071c4: 2b00 cmp r3, #0
80071c6: d00a beq.n 80071de <HAL_RCCEx_PeriphCLKConfig+0x2a2>
{
/* Check the parameters */
assert_param(IS_RCC_I2C4CLKSOURCE(PeriphClkInit->I2c4ClockSelection));
/* Configure the I2C4 clock source */
__HAL_RCC_I2C4_CONFIG(PeriphClkInit->I2c4ClockSelection);
80071c8: 4b54 ldr r3, [pc, #336] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80071ca: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c
80071ce: f023 0203 bic.w r2, r3, #3
80071d2: 687b ldr r3, [r7, #4]
80071d4: 6a9b ldr r3, [r3, #40] @ 0x28
80071d6: 4951 ldr r1, [pc, #324] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80071d8: 4313 orrs r3, r2
80071da: f8c1 309c str.w r3, [r1, #156] @ 0x9c
}
#endif /* I2C4 */
/*-------------------------- LPTIM1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
80071de: 687b ldr r3, [r7, #4]
80071e0: 681b ldr r3, [r3, #0]
80071e2: f403 7300 and.w r3, r3, #512 @ 0x200
80071e6: 2b00 cmp r3, #0
80071e8: d00a beq.n 8007200 <HAL_RCCEx_PeriphCLKConfig+0x2c4>
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
/* Configure the LPTIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
80071ea: 4b4c ldr r3, [pc, #304] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80071ec: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80071f0: f423 2240 bic.w r2, r3, #786432 @ 0xc0000
80071f4: 687b ldr r3, [r7, #4]
80071f6: 6adb ldr r3, [r3, #44] @ 0x2c
80071f8: 4948 ldr r1, [pc, #288] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80071fa: 4313 orrs r3, r2
80071fc: f8c1 3088 str.w r3, [r1, #136] @ 0x88
}
#if defined(SAI1)
/*-------------------------- SAI1 clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)
8007200: 687b ldr r3, [r7, #4]
8007202: 681b ldr r3, [r3, #0]
8007204: f403 6380 and.w r3, r3, #1024 @ 0x400
8007208: 2b00 cmp r3, #0
800720a: d015 beq.n 8007238 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
/* Configure the SAI1 interface clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
800720c: 4b43 ldr r3, [pc, #268] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
800720e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8007212: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
8007216: 687b ldr r3, [r7, #4]
8007218: 6b1b ldr r3, [r3, #48] @ 0x30
800721a: 4940 ldr r1, [pc, #256] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
800721c: 4313 orrs r3, r2
800721e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLL)
8007222: 687b ldr r3, [r7, #4]
8007224: 6b1b ldr r3, [r3, #48] @ 0x30
8007226: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
800722a: d105 bne.n 8007238 <HAL_RCCEx_PeriphCLKConfig+0x2fc>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
800722c: 4b3b ldr r3, [pc, #236] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
800722e: 68db ldr r3, [r3, #12]
8007230: 4a3a ldr r2, [pc, #232] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007232: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8007236: 60d3 str r3, [r2, #12]
#endif /* SAI1 */
#if defined(SPI_I2S_SUPPORT)
/*-------------------------- I2S clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S)
8007238: 687b ldr r3, [r7, #4]
800723a: 681b ldr r3, [r3, #0]
800723c: f403 6300 and.w r3, r3, #2048 @ 0x800
8007240: 2b00 cmp r3, #0
8007242: d015 beq.n 8007270 <HAL_RCCEx_PeriphCLKConfig+0x334>
{
/* Check the parameters */
assert_param(IS_RCC_I2SCLKSOURCE(PeriphClkInit->I2sClockSelection));
/* Configure the I2S interface clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2sClockSelection);
8007244: 4b35 ldr r3, [pc, #212] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007246: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800724a: f423 0240 bic.w r2, r3, #12582912 @ 0xc00000
800724e: 687b ldr r3, [r7, #4]
8007250: 6b5b ldr r3, [r3, #52] @ 0x34
8007252: 4932 ldr r1, [pc, #200] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007254: 4313 orrs r3, r2
8007256: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->I2sClockSelection == RCC_I2SCLKSOURCE_PLL)
800725a: 687b ldr r3, [r7, #4]
800725c: 6b5b ldr r3, [r3, #52] @ 0x34
800725e: f5b3 0f80 cmp.w r3, #4194304 @ 0x400000
8007262: d105 bne.n 8007270 <HAL_RCCEx_PeriphCLKConfig+0x334>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
8007264: 4b2d ldr r3, [pc, #180] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007266: 68db ldr r3, [r3, #12]
8007268: 4a2c ldr r2, [pc, #176] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
800726a: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
800726e: 60d3 str r3, [r2, #12]
#endif /* SPI_I2S_SUPPORT */
#if defined(FDCAN1)
/*-------------------------- FDCAN clock source configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN) == RCC_PERIPHCLK_FDCAN)
8007270: 687b ldr r3, [r7, #4]
8007272: 681b ldr r3, [r3, #0]
8007274: f403 5380 and.w r3, r3, #4096 @ 0x1000
8007278: 2b00 cmp r3, #0
800727a: d015 beq.n 80072a8 <HAL_RCCEx_PeriphCLKConfig+0x36c>
{
/* Check the parameters */
assert_param(IS_RCC_FDCANCLKSOURCE(PeriphClkInit->FdcanClockSelection));
/* Configure the FDCAN interface clock source */
__HAL_RCC_FDCAN_CONFIG(PeriphClkInit->FdcanClockSelection);
800727c: 4b27 ldr r3, [pc, #156] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
800727e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8007282: f023 7240 bic.w r2, r3, #50331648 @ 0x3000000
8007286: 687b ldr r3, [r7, #4]
8007288: 6b9b ldr r3, [r3, #56] @ 0x38
800728a: 4924 ldr r1, [pc, #144] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
800728c: 4313 orrs r3, r2
800728e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->FdcanClockSelection == RCC_FDCANCLKSOURCE_PLL)
8007292: 687b ldr r3, [r7, #4]
8007294: 6b9b ldr r3, [r3, #56] @ 0x38
8007296: f1b3 7f80 cmp.w r3, #16777216 @ 0x1000000
800729a: d105 bne.n 80072a8 <HAL_RCCEx_PeriphCLKConfig+0x36c>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
800729c: 4b1f ldr r3, [pc, #124] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
800729e: 68db ldr r3, [r3, #12]
80072a0: 4a1e ldr r2, [pc, #120] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80072a2: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
80072a6: 60d3 str r3, [r2, #12]
#endif /* FDCAN1 */
#if defined(USB)
/*-------------------------- USB clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
80072a8: 687b ldr r3, [r7, #4]
80072aa: 681b ldr r3, [r3, #0]
80072ac: f403 5300 and.w r3, r3, #8192 @ 0x2000
80072b0: 2b00 cmp r3, #0
80072b2: d015 beq.n 80072e0 <HAL_RCCEx_PeriphCLKConfig+0x3a4>
{
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
__HAL_RCC_USB_CONFIG(PeriphClkInit->UsbClockSelection);
80072b4: 4b19 ldr r3, [pc, #100] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80072b6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80072ba: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
80072be: 687b ldr r3, [r7, #4]
80072c0: 6bdb ldr r3, [r3, #60] @ 0x3c
80072c2: 4916 ldr r1, [pc, #88] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80072c4: 4313 orrs r3, r2
80072c6: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLL)
80072ca: 687b ldr r3, [r7, #4]
80072cc: 6bdb ldr r3, [r3, #60] @ 0x3c
80072ce: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
80072d2: d105 bne.n 80072e0 <HAL_RCCEx_PeriphCLKConfig+0x3a4>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80072d4: 4b11 ldr r3, [pc, #68] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80072d6: 68db ldr r3, [r3, #12]
80072d8: 4a10 ldr r2, [pc, #64] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80072da: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
80072de: 60d3 str r3, [r2, #12]
}
#endif /* USB */
/*-------------------------- RNG clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
80072e0: 687b ldr r3, [r7, #4]
80072e2: 681b ldr r3, [r3, #0]
80072e4: f403 4380 and.w r3, r3, #16384 @ 0x4000
80072e8: 2b00 cmp r3, #0
80072ea: d019 beq.n 8007320 <HAL_RCCEx_PeriphCLKConfig+0x3e4>
{
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
80072ec: 4b0b ldr r3, [pc, #44] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80072ee: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
80072f2: f023 6240 bic.w r2, r3, #201326592 @ 0xc000000
80072f6: 687b ldr r3, [r7, #4]
80072f8: 6c1b ldr r3, [r3, #64] @ 0x40
80072fa: 4908 ldr r1, [pc, #32] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
80072fc: 4313 orrs r3, r2
80072fe: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
8007302: 687b ldr r3, [r7, #4]
8007304: 6c1b ldr r3, [r3, #64] @ 0x40
8007306: f1b3 6f00 cmp.w r3, #134217728 @ 0x8000000
800730a: d109 bne.n 8007320 <HAL_RCCEx_PeriphCLKConfig+0x3e4>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
800730c: 4b03 ldr r3, [pc, #12] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
800730e: 68db ldr r3, [r3, #12]
8007310: 4a02 ldr r2, [pc, #8] @ (800731c <HAL_RCCEx_PeriphCLKConfig+0x3e0>)
8007312: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
8007316: 60d3 str r3, [r2, #12]
8007318: e002 b.n 8007320 <HAL_RCCEx_PeriphCLKConfig+0x3e4>
800731a: bf00 nop
800731c: 40021000 .word 0x40021000
}
}
/*-------------------------- ADC12 clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC12) == RCC_PERIPHCLK_ADC12)
8007320: 687b ldr r3, [r7, #4]
8007322: 681b ldr r3, [r3, #0]
8007324: f403 4300 and.w r3, r3, #32768 @ 0x8000
8007328: 2b00 cmp r3, #0
800732a: d015 beq.n 8007358 <HAL_RCCEx_PeriphCLKConfig+0x41c>
{
/* Check the parameters */
assert_param(IS_RCC_ADC12CLKSOURCE(PeriphClkInit->Adc12ClockSelection));
/* Configure the ADC12 interface clock source */
__HAL_RCC_ADC12_CONFIG(PeriphClkInit->Adc12ClockSelection);
800732c: 4b29 ldr r3, [pc, #164] @ (80073d4 <HAL_RCCEx_PeriphCLKConfig+0x498>)
800732e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8007332: f023 5240 bic.w r2, r3, #805306368 @ 0x30000000
8007336: 687b ldr r3, [r7, #4]
8007338: 6c5b ldr r3, [r3, #68] @ 0x44
800733a: 4926 ldr r1, [pc, #152] @ (80073d4 <HAL_RCCEx_PeriphCLKConfig+0x498>)
800733c: 4313 orrs r3, r2
800733e: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Adc12ClockSelection == RCC_ADC12CLKSOURCE_PLL)
8007342: 687b ldr r3, [r7, #4]
8007344: 6c5b ldr r3, [r3, #68] @ 0x44
8007346: f1b3 5f80 cmp.w r3, #268435456 @ 0x10000000
800734a: d105 bne.n 8007358 <HAL_RCCEx_PeriphCLKConfig+0x41c>
{
/* Enable PLLADCCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
800734c: 4b21 ldr r3, [pc, #132] @ (80073d4 <HAL_RCCEx_PeriphCLKConfig+0x498>)
800734e: 68db ldr r3, [r3, #12]
8007350: 4a20 ldr r2, [pc, #128] @ (80073d4 <HAL_RCCEx_PeriphCLKConfig+0x498>)
8007352: f443 3380 orr.w r3, r3, #65536 @ 0x10000
8007356: 60d3 str r3, [r2, #12]
}
}
#if defined(ADC345_COMMON)
/*-------------------------- ADC345 clock source configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC345) == RCC_PERIPHCLK_ADC345)
8007358: 687b ldr r3, [r7, #4]
800735a: 681b ldr r3, [r3, #0]
800735c: f403 3380 and.w r3, r3, #65536 @ 0x10000
8007360: 2b00 cmp r3, #0
8007362: d015 beq.n 8007390 <HAL_RCCEx_PeriphCLKConfig+0x454>
{
/* Check the parameters */
assert_param(IS_RCC_ADC345CLKSOURCE(PeriphClkInit->Adc345ClockSelection));
/* Configure the ADC345 interface clock source */
__HAL_RCC_ADC345_CONFIG(PeriphClkInit->Adc345ClockSelection);
8007364: 4b1b ldr r3, [pc, #108] @ (80073d4 <HAL_RCCEx_PeriphCLKConfig+0x498>)
8007366: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
800736a: f023 4240 bic.w r2, r3, #3221225472 @ 0xc0000000
800736e: 687b ldr r3, [r7, #4]
8007370: 6c9b ldr r3, [r3, #72] @ 0x48
8007372: 4918 ldr r1, [pc, #96] @ (80073d4 <HAL_RCCEx_PeriphCLKConfig+0x498>)
8007374: 4313 orrs r3, r2
8007376: f8c1 3088 str.w r3, [r1, #136] @ 0x88
if(PeriphClkInit->Adc345ClockSelection == RCC_ADC345CLKSOURCE_PLL)
800737a: 687b ldr r3, [r7, #4]
800737c: 6c9b ldr r3, [r3, #72] @ 0x48
800737e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8007382: d105 bne.n 8007390 <HAL_RCCEx_PeriphCLKConfig+0x454>
{
/* Enable PLLADCCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
8007384: 4b13 ldr r3, [pc, #76] @ (80073d4 <HAL_RCCEx_PeriphCLKConfig+0x498>)
8007386: 68db ldr r3, [r3, #12]
8007388: 4a12 ldr r2, [pc, #72] @ (80073d4 <HAL_RCCEx_PeriphCLKConfig+0x498>)
800738a: f443 3380 orr.w r3, r3, #65536 @ 0x10000
800738e: 60d3 str r3, [r2, #12]
#endif /* ADC345_COMMON */
#if defined(QUADSPI)
/*-------------------------- QuadSPIx clock source configuration ----------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_QSPI) == RCC_PERIPHCLK_QSPI)
8007390: 687b ldr r3, [r7, #4]
8007392: 681b ldr r3, [r3, #0]
8007394: f403 2380 and.w r3, r3, #262144 @ 0x40000
8007398: 2b00 cmp r3, #0
800739a: d015 beq.n 80073c8 <HAL_RCCEx_PeriphCLKConfig+0x48c>
{
/* Check the parameters */
assert_param(IS_RCC_QSPICLKSOURCE(PeriphClkInit->QspiClockSelection));
/* Configure the QuadSPI clock source */
__HAL_RCC_QSPI_CONFIG(PeriphClkInit->QspiClockSelection);
800739c: 4b0d ldr r3, [pc, #52] @ (80073d4 <HAL_RCCEx_PeriphCLKConfig+0x498>)
800739e: f8d3 309c ldr.w r3, [r3, #156] @ 0x9c
80073a2: f423 1240 bic.w r2, r3, #3145728 @ 0x300000
80073a6: 687b ldr r3, [r7, #4]
80073a8: 6cdb ldr r3, [r3, #76] @ 0x4c
80073aa: 490a ldr r1, [pc, #40] @ (80073d4 <HAL_RCCEx_PeriphCLKConfig+0x498>)
80073ac: 4313 orrs r3, r2
80073ae: f8c1 309c str.w r3, [r1, #156] @ 0x9c
if(PeriphClkInit->QspiClockSelection == RCC_QSPICLKSOURCE_PLL)
80073b2: 687b ldr r3, [r7, #4]
80073b4: 6cdb ldr r3, [r3, #76] @ 0x4c
80073b6: f5b3 1f00 cmp.w r3, #2097152 @ 0x200000
80073ba: d105 bne.n 80073c8 <HAL_RCCEx_PeriphCLKConfig+0x48c>
{
/* Enable PLL48M1CLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_48M1CLK);
80073bc: 4b05 ldr r3, [pc, #20] @ (80073d4 <HAL_RCCEx_PeriphCLKConfig+0x498>)
80073be: 68db ldr r3, [r3, #12]
80073c0: 4a04 ldr r2, [pc, #16] @ (80073d4 <HAL_RCCEx_PeriphCLKConfig+0x498>)
80073c2: f443 1380 orr.w r3, r3, #1048576 @ 0x100000
80073c6: 60d3 str r3, [r2, #12]
}
}
#endif /* QUADSPI */
return status;
80073c8: 7cbb ldrb r3, [r7, #18]
}
80073ca: 4618 mov r0, r3
80073cc: 3718 adds r7, #24
80073ce: 46bd mov sp, r7
80073d0: bd80 pop {r7, pc}
80073d2: bf00 nop
80073d4: 40021000 .word 0x40021000
080073d8 <HAL_TIM_Base_Init>:
* Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
{
80073d8: b580 push {r7, lr}
80073da: b082 sub sp, #8
80073dc: af00 add r7, sp, #0
80073de: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
80073e0: 687b ldr r3, [r7, #4]
80073e2: 2b00 cmp r3, #0
80073e4: d101 bne.n 80073ea <HAL_TIM_Base_Init+0x12>
{
return HAL_ERROR;
80073e6: 2301 movs r3, #1
80073e8: e049 b.n 800747e <HAL_TIM_Base_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80073ea: 687b ldr r3, [r7, #4]
80073ec: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
80073f0: b2db uxtb r3, r3
80073f2: 2b00 cmp r3, #0
80073f4: d106 bne.n 8007404 <HAL_TIM_Base_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
80073f6: 687b ldr r3, [r7, #4]
80073f8: 2200 movs r2, #0
80073fa: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->Base_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
80073fe: 6878 ldr r0, [r7, #4]
8007400: f7fa f9ac bl 800175c <HAL_TIM_Base_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8007404: 687b ldr r3, [r7, #4]
8007406: 2202 movs r2, #2
8007408: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Set the Time Base configuration */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
800740c: 687b ldr r3, [r7, #4]
800740e: 681a ldr r2, [r3, #0]
8007410: 687b ldr r3, [r7, #4]
8007412: 3304 adds r3, #4
8007414: 4619 mov r1, r3
8007416: 4610 mov r0, r2
8007418: f000 fd24 bl 8007e64 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
800741c: 687b ldr r3, [r7, #4]
800741e: 2201 movs r2, #1
8007420: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8007424: 687b ldr r3, [r7, #4]
8007426: 2201 movs r2, #1
8007428: f883 203e strb.w r2, [r3, #62] @ 0x3e
800742c: 687b ldr r3, [r7, #4]
800742e: 2201 movs r2, #1
8007430: f883 203f strb.w r2, [r3, #63] @ 0x3f
8007434: 687b ldr r3, [r7, #4]
8007436: 2201 movs r2, #1
8007438: f883 2040 strb.w r2, [r3, #64] @ 0x40
800743c: 687b ldr r3, [r7, #4]
800743e: 2201 movs r2, #1
8007440: f883 2041 strb.w r2, [r3, #65] @ 0x41
8007444: 687b ldr r3, [r7, #4]
8007446: 2201 movs r2, #1
8007448: f883 2042 strb.w r2, [r3, #66] @ 0x42
800744c: 687b ldr r3, [r7, #4]
800744e: 2201 movs r2, #1
8007450: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8007454: 687b ldr r3, [r7, #4]
8007456: 2201 movs r2, #1
8007458: f883 2044 strb.w r2, [r3, #68] @ 0x44
800745c: 687b ldr r3, [r7, #4]
800745e: 2201 movs r2, #1
8007460: f883 2045 strb.w r2, [r3, #69] @ 0x45
8007464: 687b ldr r3, [r7, #4]
8007466: 2201 movs r2, #1
8007468: f883 2046 strb.w r2, [r3, #70] @ 0x46
800746c: 687b ldr r3, [r7, #4]
800746e: 2201 movs r2, #1
8007470: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8007474: 687b ldr r3, [r7, #4]
8007476: 2201 movs r2, #1
8007478: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
800747c: 2300 movs r3, #0
}
800747e: 4618 mov r0, r3
8007480: 3708 adds r7, #8
8007482: 46bd mov sp, r7
8007484: bd80 pop {r7, pc}
08007486 <HAL_TIM_Base_Stop_IT>:
* @brief Stops the TIM Base generation in interrupt mode.
* @param htim TIM Base handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
{
8007486: b480 push {r7}
8007488: b083 sub sp, #12
800748a: af00 add r7, sp, #0
800748c: 6078 str r0, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
/* Disable the TIM Update interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
800748e: 687b ldr r3, [r7, #4]
8007490: 681b ldr r3, [r3, #0]
8007492: 68da ldr r2, [r3, #12]
8007494: 687b ldr r3, [r7, #4]
8007496: 681b ldr r3, [r3, #0]
8007498: f022 0201 bic.w r2, r2, #1
800749c: 60da str r2, [r3, #12]
/* Disable the Peripheral */
__HAL_TIM_DISABLE(htim);
800749e: 687b ldr r3, [r7, #4]
80074a0: 681b ldr r3, [r3, #0]
80074a2: 6a1a ldr r2, [r3, #32]
80074a4: f241 1311 movw r3, #4369 @ 0x1111
80074a8: 4013 ands r3, r2
80074aa: 2b00 cmp r3, #0
80074ac: d10f bne.n 80074ce <HAL_TIM_Base_Stop_IT+0x48>
80074ae: 687b ldr r3, [r7, #4]
80074b0: 681b ldr r3, [r3, #0]
80074b2: 6a1a ldr r2, [r3, #32]
80074b4: f244 4344 movw r3, #17476 @ 0x4444
80074b8: 4013 ands r3, r2
80074ba: 2b00 cmp r3, #0
80074bc: d107 bne.n 80074ce <HAL_TIM_Base_Stop_IT+0x48>
80074be: 687b ldr r3, [r7, #4]
80074c0: 681b ldr r3, [r3, #0]
80074c2: 681a ldr r2, [r3, #0]
80074c4: 687b ldr r3, [r7, #4]
80074c6: 681b ldr r3, [r3, #0]
80074c8: f022 0201 bic.w r2, r2, #1
80074cc: 601a str r2, [r3, #0]
/* Set the TIM state */
htim->State = HAL_TIM_STATE_READY;
80074ce: 687b ldr r3, [r7, #4]
80074d0: 2201 movs r2, #1
80074d2: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Return function status */
return HAL_OK;
80074d6: 2300 movs r3, #0
}
80074d8: 4618 mov r0, r3
80074da: 370c adds r7, #12
80074dc: 46bd mov sp, r7
80074de: f85d 7b04 ldr.w r7, [sp], #4
80074e2: 4770 bx lr
080074e4 <HAL_TIM_OC_Init>:
* Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
* @param htim TIM Output Compare handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
{
80074e4: b580 push {r7, lr}
80074e6: b082 sub sp, #8
80074e8: af00 add r7, sp, #0
80074ea: 6078 str r0, [r7, #4]
/* Check the TIM handle allocation */
if (htim == NULL)
80074ec: 687b ldr r3, [r7, #4]
80074ee: 2b00 cmp r3, #0
80074f0: d101 bne.n 80074f6 <HAL_TIM_OC_Init+0x12>
{
return HAL_ERROR;
80074f2: 2301 movs r3, #1
80074f4: e049 b.n 800758a <HAL_TIM_OC_Init+0xa6>
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if (htim->State == HAL_TIM_STATE_RESET)
80074f6: 687b ldr r3, [r7, #4]
80074f8: f893 303d ldrb.w r3, [r3, #61] @ 0x3d
80074fc: b2db uxtb r3, r3
80074fe: 2b00 cmp r3, #0
8007500: d106 bne.n 8007510 <HAL_TIM_OC_Init+0x2c>
{
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
8007502: 687b ldr r3, [r7, #4]
8007504: 2200 movs r2, #0
8007506: f883 203c strb.w r2, [r3, #60] @ 0x3c
}
/* Init the low level hardware : GPIO, CLOCK, NVIC */
htim->OC_MspInitCallback(htim);
#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
800750a: 6878 ldr r0, [r7, #4]
800750c: f000 f841 bl 8007592 <HAL_TIM_OC_MspInit>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Set the TIM state */
htim->State = HAL_TIM_STATE_BUSY;
8007510: 687b ldr r3, [r7, #4]
8007512: 2202 movs r2, #2
8007514: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Init the base time for the Output Compare */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
8007518: 687b ldr r3, [r7, #4]
800751a: 681a ldr r2, [r3, #0]
800751c: 687b ldr r3, [r7, #4]
800751e: 3304 adds r3, #4
8007520: 4619 mov r1, r3
8007522: 4610 mov r0, r2
8007524: f000 fc9e bl 8007e64 <TIM_Base_SetConfig>
/* Initialize the DMA burst operation state */
htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
8007528: 687b ldr r3, [r7, #4]
800752a: 2201 movs r2, #1
800752c: f883 2048 strb.w r2, [r3, #72] @ 0x48
/* Initialize the TIM channels state */
TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8007530: 687b ldr r3, [r7, #4]
8007532: 2201 movs r2, #1
8007534: f883 203e strb.w r2, [r3, #62] @ 0x3e
8007538: 687b ldr r3, [r7, #4]
800753a: 2201 movs r2, #1
800753c: f883 203f strb.w r2, [r3, #63] @ 0x3f
8007540: 687b ldr r3, [r7, #4]
8007542: 2201 movs r2, #1
8007544: f883 2040 strb.w r2, [r3, #64] @ 0x40
8007548: 687b ldr r3, [r7, #4]
800754a: 2201 movs r2, #1
800754c: f883 2041 strb.w r2, [r3, #65] @ 0x41
8007550: 687b ldr r3, [r7, #4]
8007552: 2201 movs r2, #1
8007554: f883 2042 strb.w r2, [r3, #66] @ 0x42
8007558: 687b ldr r3, [r7, #4]
800755a: 2201 movs r2, #1
800755c: f883 2043 strb.w r2, [r3, #67] @ 0x43
TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
8007560: 687b ldr r3, [r7, #4]
8007562: 2201 movs r2, #1
8007564: f883 2044 strb.w r2, [r3, #68] @ 0x44
8007568: 687b ldr r3, [r7, #4]
800756a: 2201 movs r2, #1
800756c: f883 2045 strb.w r2, [r3, #69] @ 0x45
8007570: 687b ldr r3, [r7, #4]
8007572: 2201 movs r2, #1
8007574: f883 2046 strb.w r2, [r3, #70] @ 0x46
8007578: 687b ldr r3, [r7, #4]
800757a: 2201 movs r2, #1
800757c: f883 2047 strb.w r2, [r3, #71] @ 0x47
/* Initialize the TIM state*/
htim->State = HAL_TIM_STATE_READY;
8007580: 687b ldr r3, [r7, #4]
8007582: 2201 movs r2, #1
8007584: f883 203d strb.w r2, [r3, #61] @ 0x3d
return HAL_OK;
8007588: 2300 movs r3, #0
}
800758a: 4618 mov r0, r3
800758c: 3708 adds r7, #8
800758e: 46bd mov sp, r7
8007590: bd80 pop {r7, pc}
08007592 <HAL_TIM_OC_MspInit>:
* @brief Initializes the TIM Output Compare MSP.
* @param htim TIM Output Compare handle
* @retval None
*/
__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
{
8007592: b480 push {r7}
8007594: b083 sub sp, #12
8007596: af00 add r7, sp, #0
8007598: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_OC_MspInit could be implemented in the user file
*/
}
800759a: bf00 nop
800759c: 370c adds r7, #12
800759e: 46bd mov sp, r7
80075a0: f85d 7b04 ldr.w r7, [sp], #4
80075a4: 4770 bx lr
...
080075a8 <HAL_TIM_OC_Start_IT>:
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
{
80075a8: b580 push {r7, lr}
80075aa: b084 sub sp, #16
80075ac: af00 add r7, sp, #0
80075ae: 6078 str r0, [r7, #4]
80075b0: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
80075b2: 2300 movs r3, #0
80075b4: 73fb strb r3, [r7, #15]
/* Check the parameters */
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
/* Check the TIM channel state */
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
80075b6: 683b ldr r3, [r7, #0]
80075b8: 2b00 cmp r3, #0
80075ba: d109 bne.n 80075d0 <HAL_TIM_OC_Start_IT+0x28>
80075bc: 687b ldr r3, [r7, #4]
80075be: f893 303e ldrb.w r3, [r3, #62] @ 0x3e
80075c2: b2db uxtb r3, r3
80075c4: 2b01 cmp r3, #1
80075c6: bf14 ite ne
80075c8: 2301 movne r3, #1
80075ca: 2300 moveq r3, #0
80075cc: b2db uxtb r3, r3
80075ce: e03c b.n 800764a <HAL_TIM_OC_Start_IT+0xa2>
80075d0: 683b ldr r3, [r7, #0]
80075d2: 2b04 cmp r3, #4
80075d4: d109 bne.n 80075ea <HAL_TIM_OC_Start_IT+0x42>
80075d6: 687b ldr r3, [r7, #4]
80075d8: f893 303f ldrb.w r3, [r3, #63] @ 0x3f
80075dc: b2db uxtb r3, r3
80075de: 2b01 cmp r3, #1
80075e0: bf14 ite ne
80075e2: 2301 movne r3, #1
80075e4: 2300 moveq r3, #0
80075e6: b2db uxtb r3, r3
80075e8: e02f b.n 800764a <HAL_TIM_OC_Start_IT+0xa2>
80075ea: 683b ldr r3, [r7, #0]
80075ec: 2b08 cmp r3, #8
80075ee: d109 bne.n 8007604 <HAL_TIM_OC_Start_IT+0x5c>
80075f0: 687b ldr r3, [r7, #4]
80075f2: f893 3040 ldrb.w r3, [r3, #64] @ 0x40
80075f6: b2db uxtb r3, r3
80075f8: 2b01 cmp r3, #1
80075fa: bf14 ite ne
80075fc: 2301 movne r3, #1
80075fe: 2300 moveq r3, #0
8007600: b2db uxtb r3, r3
8007602: e022 b.n 800764a <HAL_TIM_OC_Start_IT+0xa2>
8007604: 683b ldr r3, [r7, #0]
8007606: 2b0c cmp r3, #12
8007608: d109 bne.n 800761e <HAL_TIM_OC_Start_IT+0x76>
800760a: 687b ldr r3, [r7, #4]
800760c: f893 3041 ldrb.w r3, [r3, #65] @ 0x41
8007610: b2db uxtb r3, r3
8007612: 2b01 cmp r3, #1
8007614: bf14 ite ne
8007616: 2301 movne r3, #1
8007618: 2300 moveq r3, #0
800761a: b2db uxtb r3, r3
800761c: e015 b.n 800764a <HAL_TIM_OC_Start_IT+0xa2>
800761e: 683b ldr r3, [r7, #0]
8007620: 2b10 cmp r3, #16
8007622: d109 bne.n 8007638 <HAL_TIM_OC_Start_IT+0x90>
8007624: 687b ldr r3, [r7, #4]
8007626: f893 3042 ldrb.w r3, [r3, #66] @ 0x42
800762a: b2db uxtb r3, r3
800762c: 2b01 cmp r3, #1
800762e: bf14 ite ne
8007630: 2301 movne r3, #1
8007632: 2300 moveq r3, #0
8007634: b2db uxtb r3, r3
8007636: e008 b.n 800764a <HAL_TIM_OC_Start_IT+0xa2>
8007638: 687b ldr r3, [r7, #4]
800763a: f893 3043 ldrb.w r3, [r3, #67] @ 0x43
800763e: b2db uxtb r3, r3
8007640: 2b01 cmp r3, #1
8007642: bf14 ite ne
8007644: 2301 movne r3, #1
8007646: 2300 moveq r3, #0
8007648: b2db uxtb r3, r3
800764a: 2b00 cmp r3, #0
800764c: d001 beq.n 8007652 <HAL_TIM_OC_Start_IT+0xaa>
{
return HAL_ERROR;
800764e: 2301 movs r3, #1
8007650: e0f1 b.n 8007836 <HAL_TIM_OC_Start_IT+0x28e>
}
/* Set the TIM channel state */
TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
8007652: 683b ldr r3, [r7, #0]
8007654: 2b00 cmp r3, #0
8007656: d104 bne.n 8007662 <HAL_TIM_OC_Start_IT+0xba>
8007658: 687b ldr r3, [r7, #4]
800765a: 2202 movs r2, #2
800765c: f883 203e strb.w r2, [r3, #62] @ 0x3e
8007660: e023 b.n 80076aa <HAL_TIM_OC_Start_IT+0x102>
8007662: 683b ldr r3, [r7, #0]
8007664: 2b04 cmp r3, #4
8007666: d104 bne.n 8007672 <HAL_TIM_OC_Start_IT+0xca>
8007668: 687b ldr r3, [r7, #4]
800766a: 2202 movs r2, #2
800766c: f883 203f strb.w r2, [r3, #63] @ 0x3f
8007670: e01b b.n 80076aa <HAL_TIM_OC_Start_IT+0x102>
8007672: 683b ldr r3, [r7, #0]
8007674: 2b08 cmp r3, #8
8007676: d104 bne.n 8007682 <HAL_TIM_OC_Start_IT+0xda>
8007678: 687b ldr r3, [r7, #4]
800767a: 2202 movs r2, #2
800767c: f883 2040 strb.w r2, [r3, #64] @ 0x40
8007680: e013 b.n 80076aa <HAL_TIM_OC_Start_IT+0x102>
8007682: 683b ldr r3, [r7, #0]
8007684: 2b0c cmp r3, #12
8007686: d104 bne.n 8007692 <HAL_TIM_OC_Start_IT+0xea>
8007688: 687b ldr r3, [r7, #4]
800768a: 2202 movs r2, #2
800768c: f883 2041 strb.w r2, [r3, #65] @ 0x41
8007690: e00b b.n 80076aa <HAL_TIM_OC_Start_IT+0x102>
8007692: 683b ldr r3, [r7, #0]
8007694: 2b10 cmp r3, #16
8007696: d104 bne.n 80076a2 <HAL_TIM_OC_Start_IT+0xfa>
8007698: 687b ldr r3, [r7, #4]
800769a: 2202 movs r2, #2
800769c: f883 2042 strb.w r2, [r3, #66] @ 0x42
80076a0: e003 b.n 80076aa <HAL_TIM_OC_Start_IT+0x102>
80076a2: 687b ldr r3, [r7, #4]
80076a4: 2202 movs r2, #2
80076a6: f883 2043 strb.w r2, [r3, #67] @ 0x43
switch (Channel)
80076aa: 683b ldr r3, [r7, #0]
80076ac: 2b0c cmp r3, #12
80076ae: d841 bhi.n 8007734 <HAL_TIM_OC_Start_IT+0x18c>
80076b0: a201 add r2, pc, #4 @ (adr r2, 80076b8 <HAL_TIM_OC_Start_IT+0x110>)
80076b2: f852 f023 ldr.w pc, [r2, r3, lsl #2]
80076b6: bf00 nop
80076b8: 080076ed .word 0x080076ed
80076bc: 08007735 .word 0x08007735
80076c0: 08007735 .word 0x08007735
80076c4: 08007735 .word 0x08007735
80076c8: 080076ff .word 0x080076ff
80076cc: 08007735 .word 0x08007735
80076d0: 08007735 .word 0x08007735
80076d4: 08007735 .word 0x08007735
80076d8: 08007711 .word 0x08007711
80076dc: 08007735 .word 0x08007735
80076e0: 08007735 .word 0x08007735
80076e4: 08007735 .word 0x08007735
80076e8: 08007723 .word 0x08007723
{
case TIM_CHANNEL_1:
{
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
80076ec: 687b ldr r3, [r7, #4]
80076ee: 681b ldr r3, [r3, #0]
80076f0: 68da ldr r2, [r3, #12]
80076f2: 687b ldr r3, [r7, #4]
80076f4: 681b ldr r3, [r3, #0]
80076f6: f042 0202 orr.w r2, r2, #2
80076fa: 60da str r2, [r3, #12]
break;
80076fc: e01d b.n 800773a <HAL_TIM_OC_Start_IT+0x192>
}
case TIM_CHANNEL_2:
{
/* Enable the TIM Capture/Compare 2 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
80076fe: 687b ldr r3, [r7, #4]
8007700: 681b ldr r3, [r3, #0]
8007702: 68da ldr r2, [r3, #12]
8007704: 687b ldr r3, [r7, #4]
8007706: 681b ldr r3, [r3, #0]
8007708: f042 0204 orr.w r2, r2, #4
800770c: 60da str r2, [r3, #12]
break;
800770e: e014 b.n 800773a <HAL_TIM_OC_Start_IT+0x192>
}
case TIM_CHANNEL_3:
{
/* Enable the TIM Capture/Compare 3 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
8007710: 687b ldr r3, [r7, #4]
8007712: 681b ldr r3, [r3, #0]
8007714: 68da ldr r2, [r3, #12]
8007716: 687b ldr r3, [r7, #4]
8007718: 681b ldr r3, [r3, #0]
800771a: f042 0208 orr.w r2, r2, #8
800771e: 60da str r2, [r3, #12]
break;
8007720: e00b b.n 800773a <HAL_TIM_OC_Start_IT+0x192>
}
case TIM_CHANNEL_4:
{
/* Enable the TIM Capture/Compare 4 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
8007722: 687b ldr r3, [r7, #4]
8007724: 681b ldr r3, [r3, #0]
8007726: 68da ldr r2, [r3, #12]
8007728: 687b ldr r3, [r7, #4]
800772a: 681b ldr r3, [r3, #0]
800772c: f042 0210 orr.w r2, r2, #16
8007730: 60da str r2, [r3, #12]
break;
8007732: e002 b.n 800773a <HAL_TIM_OC_Start_IT+0x192>
}
default:
status = HAL_ERROR;
8007734: 2301 movs r3, #1
8007736: 73fb strb r3, [r7, #15]
break;
8007738: bf00 nop
}
if (status == HAL_OK)
800773a: 7bfb ldrb r3, [r7, #15]
800773c: 2b00 cmp r3, #0
800773e: d179 bne.n 8007834 <HAL_TIM_OC_Start_IT+0x28c>
{
/* Enable the Output compare channel */
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
8007740: 687b ldr r3, [r7, #4]
8007742: 681b ldr r3, [r3, #0]
8007744: 2201 movs r2, #1
8007746: 6839 ldr r1, [r7, #0]
8007748: 4618 mov r0, r3
800774a: f001 f805 bl 8008758 <TIM_CCxChannelCmd>
if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
800774e: 687b ldr r3, [r7, #4]
8007750: 681b ldr r3, [r3, #0]
8007752: 4a3b ldr r2, [pc, #236] @ (8007840 <HAL_TIM_OC_Start_IT+0x298>)
8007754: 4293 cmp r3, r2
8007756: d018 beq.n 800778a <HAL_TIM_OC_Start_IT+0x1e2>
8007758: 687b ldr r3, [r7, #4]
800775a: 681b ldr r3, [r3, #0]
800775c: 4a39 ldr r2, [pc, #228] @ (8007844 <HAL_TIM_OC_Start_IT+0x29c>)
800775e: 4293 cmp r3, r2
8007760: d013 beq.n 800778a <HAL_TIM_OC_Start_IT+0x1e2>
8007762: 687b ldr r3, [r7, #4]
8007764: 681b ldr r3, [r3, #0]
8007766: 4a38 ldr r2, [pc, #224] @ (8007848 <HAL_TIM_OC_Start_IT+0x2a0>)
8007768: 4293 cmp r3, r2
800776a: d00e beq.n 800778a <HAL_TIM_OC_Start_IT+0x1e2>
800776c: 687b ldr r3, [r7, #4]
800776e: 681b ldr r3, [r3, #0]
8007770: 4a36 ldr r2, [pc, #216] @ (800784c <HAL_TIM_OC_Start_IT+0x2a4>)
8007772: 4293 cmp r3, r2
8007774: d009 beq.n 800778a <HAL_TIM_OC_Start_IT+0x1e2>
8007776: 687b ldr r3, [r7, #4]
8007778: 681b ldr r3, [r3, #0]
800777a: 4a35 ldr r2, [pc, #212] @ (8007850 <HAL_TIM_OC_Start_IT+0x2a8>)
800777c: 4293 cmp r3, r2
800777e: d004 beq.n 800778a <HAL_TIM_OC_Start_IT+0x1e2>
8007780: 687b ldr r3, [r7, #4]
8007782: 681b ldr r3, [r3, #0]
8007784: 4a33 ldr r2, [pc, #204] @ (8007854 <HAL_TIM_OC_Start_IT+0x2ac>)
8007786: 4293 cmp r3, r2
8007788: d101 bne.n 800778e <HAL_TIM_OC_Start_IT+0x1e6>
800778a: 2301 movs r3, #1
800778c: e000 b.n 8007790 <HAL_TIM_OC_Start_IT+0x1e8>
800778e: 2300 movs r3, #0
8007790: 2b00 cmp r3, #0
8007792: d007 beq.n 80077a4 <HAL_TIM_OC_Start_IT+0x1fc>
{
/* Enable the main output */
__HAL_TIM_MOE_ENABLE(htim);
8007794: 687b ldr r3, [r7, #4]
8007796: 681b ldr r3, [r3, #0]
8007798: 6c5a ldr r2, [r3, #68] @ 0x44
800779a: 687b ldr r3, [r7, #4]
800779c: 681b ldr r3, [r3, #0]
800779e: f442 4200 orr.w r2, r2, #32768 @ 0x8000
80077a2: 645a str r2, [r3, #68] @ 0x44
}
/* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
80077a4: 687b ldr r3, [r7, #4]
80077a6: 681b ldr r3, [r3, #0]
80077a8: 4a25 ldr r2, [pc, #148] @ (8007840 <HAL_TIM_OC_Start_IT+0x298>)
80077aa: 4293 cmp r3, r2
80077ac: d022 beq.n 80077f4 <HAL_TIM_OC_Start_IT+0x24c>
80077ae: 687b ldr r3, [r7, #4]
80077b0: 681b ldr r3, [r3, #0]
80077b2: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
80077b6: d01d beq.n 80077f4 <HAL_TIM_OC_Start_IT+0x24c>
80077b8: 687b ldr r3, [r7, #4]
80077ba: 681b ldr r3, [r3, #0]
80077bc: 4a26 ldr r2, [pc, #152] @ (8007858 <HAL_TIM_OC_Start_IT+0x2b0>)
80077be: 4293 cmp r3, r2
80077c0: d018 beq.n 80077f4 <HAL_TIM_OC_Start_IT+0x24c>
80077c2: 687b ldr r3, [r7, #4]
80077c4: 681b ldr r3, [r3, #0]
80077c6: 4a25 ldr r2, [pc, #148] @ (800785c <HAL_TIM_OC_Start_IT+0x2b4>)
80077c8: 4293 cmp r3, r2
80077ca: d013 beq.n 80077f4 <HAL_TIM_OC_Start_IT+0x24c>
80077cc: 687b ldr r3, [r7, #4]
80077ce: 681b ldr r3, [r3, #0]
80077d0: 4a23 ldr r2, [pc, #140] @ (8007860 <HAL_TIM_OC_Start_IT+0x2b8>)
80077d2: 4293 cmp r3, r2
80077d4: d00e beq.n 80077f4 <HAL_TIM_OC_Start_IT+0x24c>
80077d6: 687b ldr r3, [r7, #4]
80077d8: 681b ldr r3, [r3, #0]
80077da: 4a1a ldr r2, [pc, #104] @ (8007844 <HAL_TIM_OC_Start_IT+0x29c>)
80077dc: 4293 cmp r3, r2
80077de: d009 beq.n 80077f4 <HAL_TIM_OC_Start_IT+0x24c>
80077e0: 687b ldr r3, [r7, #4]
80077e2: 681b ldr r3, [r3, #0]
80077e4: 4a18 ldr r2, [pc, #96] @ (8007848 <HAL_TIM_OC_Start_IT+0x2a0>)
80077e6: 4293 cmp r3, r2
80077e8: d004 beq.n 80077f4 <HAL_TIM_OC_Start_IT+0x24c>
80077ea: 687b ldr r3, [r7, #4]
80077ec: 681b ldr r3, [r3, #0]
80077ee: 4a19 ldr r2, [pc, #100] @ (8007854 <HAL_TIM_OC_Start_IT+0x2ac>)
80077f0: 4293 cmp r3, r2
80077f2: d115 bne.n 8007820 <HAL_TIM_OC_Start_IT+0x278>
{
tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
80077f4: 687b ldr r3, [r7, #4]
80077f6: 681b ldr r3, [r3, #0]
80077f8: 689a ldr r2, [r3, #8]
80077fa: 4b1a ldr r3, [pc, #104] @ (8007864 <HAL_TIM_OC_Start_IT+0x2bc>)
80077fc: 4013 ands r3, r2
80077fe: 60bb str r3, [r7, #8]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8007800: 68bb ldr r3, [r7, #8]
8007802: 2b06 cmp r3, #6
8007804: d015 beq.n 8007832 <HAL_TIM_OC_Start_IT+0x28a>
8007806: 68bb ldr r3, [r7, #8]
8007808: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
800780c: d011 beq.n 8007832 <HAL_TIM_OC_Start_IT+0x28a>
{
__HAL_TIM_ENABLE(htim);
800780e: 687b ldr r3, [r7, #4]
8007810: 681b ldr r3, [r3, #0]
8007812: 681a ldr r2, [r3, #0]
8007814: 687b ldr r3, [r7, #4]
8007816: 681b ldr r3, [r3, #0]
8007818: f042 0201 orr.w r2, r2, #1
800781c: 601a str r2, [r3, #0]
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
800781e: e008 b.n 8007832 <HAL_TIM_OC_Start_IT+0x28a>
}
}
else
{
__HAL_TIM_ENABLE(htim);
8007820: 687b ldr r3, [r7, #4]
8007822: 681b ldr r3, [r3, #0]
8007824: 681a ldr r2, [r3, #0]
8007826: 687b ldr r3, [r7, #4]
8007828: 681b ldr r3, [r3, #0]
800782a: f042 0201 orr.w r2, r2, #1
800782e: 601a str r2, [r3, #0]
8007830: e000 b.n 8007834 <HAL_TIM_OC_Start_IT+0x28c>
if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
8007832: bf00 nop
}
}
/* Return function status */
return status;
8007834: 7bfb ldrb r3, [r7, #15]
}
8007836: 4618 mov r0, r3
8007838: 3710 adds r7, #16
800783a: 46bd mov sp, r7
800783c: bd80 pop {r7, pc}
800783e: bf00 nop
8007840: 40012c00 .word 0x40012c00
8007844: 40013400 .word 0x40013400
8007848: 40014000 .word 0x40014000
800784c: 40014400 .word 0x40014400
8007850: 40014800 .word 0x40014800
8007854: 40015000 .word 0x40015000
8007858: 40000400 .word 0x40000400
800785c: 40000800 .word 0x40000800
8007860: 40000c00 .word 0x40000c00
8007864: 00010007 .word 0x00010007
08007868 <HAL_TIM_IRQHandler>:
* @brief This function handles TIM interrupts requests.
* @param htim TIM handle
* @retval None
*/
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
{
8007868: b580 push {r7, lr}
800786a: b084 sub sp, #16
800786c: af00 add r7, sp, #0
800786e: 6078 str r0, [r7, #4]
uint32_t itsource = htim->Instance->DIER;
8007870: 687b ldr r3, [r7, #4]
8007872: 681b ldr r3, [r3, #0]
8007874: 68db ldr r3, [r3, #12]
8007876: 60fb str r3, [r7, #12]
uint32_t itflag = htim->Instance->SR;
8007878: 687b ldr r3, [r7, #4]
800787a: 681b ldr r3, [r3, #0]
800787c: 691b ldr r3, [r3, #16]
800787e: 60bb str r3, [r7, #8]
/* Capture compare 1 event */
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
8007880: 68bb ldr r3, [r7, #8]
8007882: f003 0302 and.w r3, r3, #2
8007886: 2b00 cmp r3, #0
8007888: d020 beq.n 80078cc <HAL_TIM_IRQHandler+0x64>
{
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
800788a: 68fb ldr r3, [r7, #12]
800788c: f003 0302 and.w r3, r3, #2
8007890: 2b00 cmp r3, #0
8007892: d01b beq.n 80078cc <HAL_TIM_IRQHandler+0x64>
{
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
8007894: 687b ldr r3, [r7, #4]
8007896: 681b ldr r3, [r3, #0]
8007898: f06f 0202 mvn.w r2, #2
800789c: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
800789e: 687b ldr r3, [r7, #4]
80078a0: 2201 movs r2, #1
80078a2: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
80078a4: 687b ldr r3, [r7, #4]
80078a6: 681b ldr r3, [r3, #0]
80078a8: 699b ldr r3, [r3, #24]
80078aa: f003 0303 and.w r3, r3, #3
80078ae: 2b00 cmp r3, #0
80078b0: d003 beq.n 80078ba <HAL_TIM_IRQHandler+0x52>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80078b2: 6878 ldr r0, [r7, #4]
80078b4: f000 fab8 bl 8007e28 <HAL_TIM_IC_CaptureCallback>
80078b8: e005 b.n 80078c6 <HAL_TIM_IRQHandler+0x5e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
80078ba: 6878 ldr r0, [r7, #4]
80078bc: f7f9 fc6a bl 8001194 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80078c0: 6878 ldr r0, [r7, #4]
80078c2: f000 fabb bl 8007e3c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80078c6: 687b ldr r3, [r7, #4]
80078c8: 2200 movs r2, #0
80078ca: 771a strb r2, [r3, #28]
}
}
}
/* Capture compare 2 event */
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
80078cc: 68bb ldr r3, [r7, #8]
80078ce: f003 0304 and.w r3, r3, #4
80078d2: 2b00 cmp r3, #0
80078d4: d020 beq.n 8007918 <HAL_TIM_IRQHandler+0xb0>
{
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
80078d6: 68fb ldr r3, [r7, #12]
80078d8: f003 0304 and.w r3, r3, #4
80078dc: 2b00 cmp r3, #0
80078de: d01b beq.n 8007918 <HAL_TIM_IRQHandler+0xb0>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
80078e0: 687b ldr r3, [r7, #4]
80078e2: 681b ldr r3, [r3, #0]
80078e4: f06f 0204 mvn.w r2, #4
80078e8: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
80078ea: 687b ldr r3, [r7, #4]
80078ec: 2202 movs r2, #2
80078ee: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
80078f0: 687b ldr r3, [r7, #4]
80078f2: 681b ldr r3, [r3, #0]
80078f4: 699b ldr r3, [r3, #24]
80078f6: f403 7340 and.w r3, r3, #768 @ 0x300
80078fa: 2b00 cmp r3, #0
80078fc: d003 beq.n 8007906 <HAL_TIM_IRQHandler+0x9e>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
80078fe: 6878 ldr r0, [r7, #4]
8007900: f000 fa92 bl 8007e28 <HAL_TIM_IC_CaptureCallback>
8007904: e005 b.n 8007912 <HAL_TIM_IRQHandler+0xaa>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8007906: 6878 ldr r0, [r7, #4]
8007908: f7f9 fc44 bl 8001194 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
800790c: 6878 ldr r0, [r7, #4]
800790e: f000 fa95 bl 8007e3c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
8007912: 687b ldr r3, [r7, #4]
8007914: 2200 movs r2, #0
8007916: 771a strb r2, [r3, #28]
}
}
/* Capture compare 3 event */
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
8007918: 68bb ldr r3, [r7, #8]
800791a: f003 0308 and.w r3, r3, #8
800791e: 2b00 cmp r3, #0
8007920: d020 beq.n 8007964 <HAL_TIM_IRQHandler+0xfc>
{
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
8007922: 68fb ldr r3, [r7, #12]
8007924: f003 0308 and.w r3, r3, #8
8007928: 2b00 cmp r3, #0
800792a: d01b beq.n 8007964 <HAL_TIM_IRQHandler+0xfc>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
800792c: 687b ldr r3, [r7, #4]
800792e: 681b ldr r3, [r3, #0]
8007930: f06f 0208 mvn.w r2, #8
8007934: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
8007936: 687b ldr r3, [r7, #4]
8007938: 2204 movs r2, #4
800793a: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
800793c: 687b ldr r3, [r7, #4]
800793e: 681b ldr r3, [r3, #0]
8007940: 69db ldr r3, [r3, #28]
8007942: f003 0303 and.w r3, r3, #3
8007946: 2b00 cmp r3, #0
8007948: d003 beq.n 8007952 <HAL_TIM_IRQHandler+0xea>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
800794a: 6878 ldr r0, [r7, #4]
800794c: f000 fa6c bl 8007e28 <HAL_TIM_IC_CaptureCallback>
8007950: e005 b.n 800795e <HAL_TIM_IRQHandler+0xf6>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
8007952: 6878 ldr r0, [r7, #4]
8007954: f7f9 fc1e bl 8001194 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
8007958: 6878 ldr r0, [r7, #4]
800795a: f000 fa6f bl 8007e3c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
800795e: 687b ldr r3, [r7, #4]
8007960: 2200 movs r2, #0
8007962: 771a strb r2, [r3, #28]
}
}
/* Capture compare 4 event */
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
8007964: 68bb ldr r3, [r7, #8]
8007966: f003 0310 and.w r3, r3, #16
800796a: 2b00 cmp r3, #0
800796c: d020 beq.n 80079b0 <HAL_TIM_IRQHandler+0x148>
{
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
800796e: 68fb ldr r3, [r7, #12]
8007970: f003 0310 and.w r3, r3, #16
8007974: 2b00 cmp r3, #0
8007976: d01b beq.n 80079b0 <HAL_TIM_IRQHandler+0x148>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
8007978: 687b ldr r3, [r7, #4]
800797a: 681b ldr r3, [r3, #0]
800797c: f06f 0210 mvn.w r2, #16
8007980: 611a str r2, [r3, #16]
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
8007982: 687b ldr r3, [r7, #4]
8007984: 2208 movs r2, #8
8007986: 771a strb r2, [r3, #28]
/* Input capture event */
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
8007988: 687b ldr r3, [r7, #4]
800798a: 681b ldr r3, [r3, #0]
800798c: 69db ldr r3, [r3, #28]
800798e: f403 7340 and.w r3, r3, #768 @ 0x300
8007992: 2b00 cmp r3, #0
8007994: d003 beq.n 800799e <HAL_TIM_IRQHandler+0x136>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IC_CaptureCallback(htim);
#else
HAL_TIM_IC_CaptureCallback(htim);
8007996: 6878 ldr r0, [r7, #4]
8007998: f000 fa46 bl 8007e28 <HAL_TIM_IC_CaptureCallback>
800799c: e005 b.n 80079aa <HAL_TIM_IRQHandler+0x142>
{
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->OC_DelayElapsedCallback(htim);
htim->PWM_PulseFinishedCallback(htim);
#else
HAL_TIM_OC_DelayElapsedCallback(htim);
800799e: 6878 ldr r0, [r7, #4]
80079a0: f7f9 fbf8 bl 8001194 <HAL_TIM_OC_DelayElapsedCallback>
HAL_TIM_PWM_PulseFinishedCallback(htim);
80079a4: 6878 ldr r0, [r7, #4]
80079a6: f000 fa49 bl 8007e3c <HAL_TIM_PWM_PulseFinishedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
80079aa: 687b ldr r3, [r7, #4]
80079ac: 2200 movs r2, #0
80079ae: 771a strb r2, [r3, #28]
}
}
/* TIM Update event */
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
80079b0: 68bb ldr r3, [r7, #8]
80079b2: f003 0301 and.w r3, r3, #1
80079b6: 2b00 cmp r3, #0
80079b8: d00c beq.n 80079d4 <HAL_TIM_IRQHandler+0x16c>
{
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
80079ba: 68fb ldr r3, [r7, #12]
80079bc: f003 0301 and.w r3, r3, #1
80079c0: 2b00 cmp r3, #0
80079c2: d007 beq.n 80079d4 <HAL_TIM_IRQHandler+0x16c>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
80079c4: 687b ldr r3, [r7, #4]
80079c6: 681b ldr r3, [r3, #0]
80079c8: f06f 0201 mvn.w r2, #1
80079cc: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->PeriodElapsedCallback(htim);
#else
HAL_TIM_PeriodElapsedCallback(htim);
80079ce: 6878 ldr r0, [r7, #4]
80079d0: f7f9 fbc6 bl 8001160 <HAL_TIM_PeriodElapsedCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
80079d4: 68bb ldr r3, [r7, #8]
80079d6: f003 0380 and.w r3, r3, #128 @ 0x80
80079da: 2b00 cmp r3, #0
80079dc: d104 bne.n 80079e8 <HAL_TIM_IRQHandler+0x180>
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
80079de: 68bb ldr r3, [r7, #8]
80079e0: f403 5300 and.w r3, r3, #8192 @ 0x2000
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
80079e4: 2b00 cmp r3, #0
80079e6: d00c beq.n 8007a02 <HAL_TIM_IRQHandler+0x19a>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
80079e8: 68fb ldr r3, [r7, #12]
80079ea: f003 0380 and.w r3, r3, #128 @ 0x80
80079ee: 2b00 cmp r3, #0
80079f0: d007 beq.n 8007a02 <HAL_TIM_IRQHandler+0x19a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
80079f2: 687b ldr r3, [r7, #4]
80079f4: 681b ldr r3, [r3, #0]
80079f6: f46f 5202 mvn.w r2, #8320 @ 0x2080
80079fa: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->BreakCallback(htim);
#else
HAL_TIMEx_BreakCallback(htim);
80079fc: 6878 ldr r0, [r7, #4]
80079fe: f000 ff71 bl 80088e4 <HAL_TIMEx_BreakCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break2 input event */
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
8007a02: 68bb ldr r3, [r7, #8]
8007a04: f403 7380 and.w r3, r3, #256 @ 0x100
8007a08: 2b00 cmp r3, #0
8007a0a: d00c beq.n 8007a26 <HAL_TIM_IRQHandler+0x1be>
{
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
8007a0c: 68fb ldr r3, [r7, #12]
8007a0e: f003 0380 and.w r3, r3, #128 @ 0x80
8007a12: 2b00 cmp r3, #0
8007a14: d007 beq.n 8007a26 <HAL_TIM_IRQHandler+0x1be>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
8007a16: 687b ldr r3, [r7, #4]
8007a18: 681b ldr r3, [r3, #0]
8007a1a: f46f 7280 mvn.w r2, #256 @ 0x100
8007a1e: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->Break2Callback(htim);
#else
HAL_TIMEx_Break2Callback(htim);
8007a20: 6878 ldr r0, [r7, #4]
8007a22: f000 ff69 bl 80088f8 <HAL_TIMEx_Break2Callback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Trigger detection event */
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
8007a26: 68bb ldr r3, [r7, #8]
8007a28: f003 0340 and.w r3, r3, #64 @ 0x40
8007a2c: 2b00 cmp r3, #0
8007a2e: d00c beq.n 8007a4a <HAL_TIM_IRQHandler+0x1e2>
{
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
8007a30: 68fb ldr r3, [r7, #12]
8007a32: f003 0340 and.w r3, r3, #64 @ 0x40
8007a36: 2b00 cmp r3, #0
8007a38: d007 beq.n 8007a4a <HAL_TIM_IRQHandler+0x1e2>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
8007a3a: 687b ldr r3, [r7, #4]
8007a3c: 681b ldr r3, [r3, #0]
8007a3e: f06f 0240 mvn.w r2, #64 @ 0x40
8007a42: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TriggerCallback(htim);
#else
HAL_TIM_TriggerCallback(htim);
8007a44: 6878 ldr r0, [r7, #4]
8007a46: f000 fa03 bl 8007e50 <HAL_TIM_TriggerCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
8007a4a: 68bb ldr r3, [r7, #8]
8007a4c: f003 0320 and.w r3, r3, #32
8007a50: 2b00 cmp r3, #0
8007a52: d00c beq.n 8007a6e <HAL_TIM_IRQHandler+0x206>
{
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
8007a54: 68fb ldr r3, [r7, #12]
8007a56: f003 0320 and.w r3, r3, #32
8007a5a: 2b00 cmp r3, #0
8007a5c: d007 beq.n 8007a6e <HAL_TIM_IRQHandler+0x206>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
8007a5e: 687b ldr r3, [r7, #4]
8007a60: 681b ldr r3, [r3, #0]
8007a62: f06f 0220 mvn.w r2, #32
8007a66: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->CommutationCallback(htim);
#else
HAL_TIMEx_CommutCallback(htim);
8007a68: 6878 ldr r0, [r7, #4]
8007a6a: f000 ff31 bl 80088d0 <HAL_TIMEx_CommutCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Encoder index event */
if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX))
8007a6e: 68bb ldr r3, [r7, #8]
8007a70: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8007a74: 2b00 cmp r3, #0
8007a76: d00c beq.n 8007a92 <HAL_TIM_IRQHandler+0x22a>
{
if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX))
8007a78: 68fb ldr r3, [r7, #12]
8007a7a: f403 1380 and.w r3, r3, #1048576 @ 0x100000
8007a7e: 2b00 cmp r3, #0
8007a80: d007 beq.n 8007a92 <HAL_TIM_IRQHandler+0x22a>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX);
8007a82: 687b ldr r3, [r7, #4]
8007a84: 681b ldr r3, [r3, #0]
8007a86: f46f 1280 mvn.w r2, #1048576 @ 0x100000
8007a8a: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->EncoderIndexCallback(htim);
#else
HAL_TIMEx_EncoderIndexCallback(htim);
8007a8c: 6878 ldr r0, [r7, #4]
8007a8e: f000 ff3d bl 800890c <HAL_TIMEx_EncoderIndexCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Direction change event */
if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR))
8007a92: 68bb ldr r3, [r7, #8]
8007a94: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8007a98: 2b00 cmp r3, #0
8007a9a: d00c beq.n 8007ab6 <HAL_TIM_IRQHandler+0x24e>
{
if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR))
8007a9c: 68fb ldr r3, [r7, #12]
8007a9e: f403 1300 and.w r3, r3, #2097152 @ 0x200000
8007aa2: 2b00 cmp r3, #0
8007aa4: d007 beq.n 8007ab6 <HAL_TIM_IRQHandler+0x24e>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR);
8007aa6: 687b ldr r3, [r7, #4]
8007aa8: 681b ldr r3, [r3, #0]
8007aaa: f46f 1200 mvn.w r2, #2097152 @ 0x200000
8007aae: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->DirectionChangeCallback(htim);
#else
HAL_TIMEx_DirectionChangeCallback(htim);
8007ab0: 6878 ldr r0, [r7, #4]
8007ab2: f000 ff35 bl 8008920 <HAL_TIMEx_DirectionChangeCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Index error event */
if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR))
8007ab6: 68bb ldr r3, [r7, #8]
8007ab8: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8007abc: 2b00 cmp r3, #0
8007abe: d00c beq.n 8007ada <HAL_TIM_IRQHandler+0x272>
{
if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR))
8007ac0: 68fb ldr r3, [r7, #12]
8007ac2: f403 0380 and.w r3, r3, #4194304 @ 0x400000
8007ac6: 2b00 cmp r3, #0
8007ac8: d007 beq.n 8007ada <HAL_TIM_IRQHandler+0x272>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR);
8007aca: 687b ldr r3, [r7, #4]
8007acc: 681b ldr r3, [r3, #0]
8007ace: f46f 0280 mvn.w r2, #4194304 @ 0x400000
8007ad2: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->IndexErrorCallback(htim);
#else
HAL_TIMEx_IndexErrorCallback(htim);
8007ad4: 6878 ldr r0, [r7, #4]
8007ad6: f000 ff2d bl 8008934 <HAL_TIMEx_IndexErrorCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Transition error event */
if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR))
8007ada: 68bb ldr r3, [r7, #8]
8007adc: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8007ae0: 2b00 cmp r3, #0
8007ae2: d00c beq.n 8007afe <HAL_TIM_IRQHandler+0x296>
{
if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR))
8007ae4: 68fb ldr r3, [r7, #12]
8007ae6: f403 0300 and.w r3, r3, #8388608 @ 0x800000
8007aea: 2b00 cmp r3, #0
8007aec: d007 beq.n 8007afe <HAL_TIM_IRQHandler+0x296>
{
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR);
8007aee: 687b ldr r3, [r7, #4]
8007af0: 681b ldr r3, [r3, #0]
8007af2: f46f 0200 mvn.w r2, #8388608 @ 0x800000
8007af6: 611a str r2, [r3, #16]
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
htim->TransitionErrorCallback(htim);
#else
HAL_TIMEx_TransitionErrorCallback(htim);
8007af8: 6878 ldr r0, [r7, #4]
8007afa: f000 ff25 bl 8008948 <HAL_TIMEx_TransitionErrorCallback>
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
8007afe: bf00 nop
8007b00: 3710 adds r7, #16
8007b02: 46bd mov sp, r7
8007b04: bd80 pop {r7, pc}
...
08007b08 <HAL_TIM_OC_ConfigChannel>:
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
const TIM_OC_InitTypeDef *sConfig,
uint32_t Channel)
{
8007b08: b580 push {r7, lr}
8007b0a: b086 sub sp, #24
8007b0c: af00 add r7, sp, #0
8007b0e: 60f8 str r0, [r7, #12]
8007b10: 60b9 str r1, [r7, #8]
8007b12: 607a str r2, [r7, #4]
HAL_StatusTypeDef status = HAL_OK;
8007b14: 2300 movs r3, #0
8007b16: 75fb strb r3, [r7, #23]
assert_param(IS_TIM_CHANNELS(Channel));
assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
/* Process Locked */
__HAL_LOCK(htim);
8007b18: 68fb ldr r3, [r7, #12]
8007b1a: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8007b1e: 2b01 cmp r3, #1
8007b20: d101 bne.n 8007b26 <HAL_TIM_OC_ConfigChannel+0x1e>
8007b22: 2302 movs r3, #2
8007b24: e066 b.n 8007bf4 <HAL_TIM_OC_ConfigChannel+0xec>
8007b26: 68fb ldr r3, [r7, #12]
8007b28: 2201 movs r2, #1
8007b2a: f883 203c strb.w r2, [r3, #60] @ 0x3c
switch (Channel)
8007b2e: 687b ldr r3, [r7, #4]
8007b30: 2b14 cmp r3, #20
8007b32: d857 bhi.n 8007be4 <HAL_TIM_OC_ConfigChannel+0xdc>
8007b34: a201 add r2, pc, #4 @ (adr r2, 8007b3c <HAL_TIM_OC_ConfigChannel+0x34>)
8007b36: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8007b3a: bf00 nop
8007b3c: 08007b91 .word 0x08007b91
8007b40: 08007be5 .word 0x08007be5
8007b44: 08007be5 .word 0x08007be5
8007b48: 08007be5 .word 0x08007be5
8007b4c: 08007b9f .word 0x08007b9f
8007b50: 08007be5 .word 0x08007be5
8007b54: 08007be5 .word 0x08007be5
8007b58: 08007be5 .word 0x08007be5
8007b5c: 08007bad .word 0x08007bad
8007b60: 08007be5 .word 0x08007be5
8007b64: 08007be5 .word 0x08007be5
8007b68: 08007be5 .word 0x08007be5
8007b6c: 08007bbb .word 0x08007bbb
8007b70: 08007be5 .word 0x08007be5
8007b74: 08007be5 .word 0x08007be5
8007b78: 08007be5 .word 0x08007be5
8007b7c: 08007bc9 .word 0x08007bc9
8007b80: 08007be5 .word 0x08007be5
8007b84: 08007be5 .word 0x08007be5
8007b88: 08007be5 .word 0x08007be5
8007b8c: 08007bd7 .word 0x08007bd7
{
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
/* Configure the TIM Channel 1 in Output Compare */
TIM_OC1_SetConfig(htim->Instance, sConfig);
8007b90: 68fb ldr r3, [r7, #12]
8007b92: 681b ldr r3, [r3, #0]
8007b94: 68b9 ldr r1, [r7, #8]
8007b96: 4618 mov r0, r3
8007b98: f000 fa18 bl 8007fcc <TIM_OC1_SetConfig>
break;
8007b9c: e025 b.n 8007bea <HAL_TIM_OC_ConfigChannel+0xe2>
{
/* Check the parameters */
assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
/* Configure the TIM Channel 2 in Output Compare */
TIM_OC2_SetConfig(htim->Instance, sConfig);
8007b9e: 68fb ldr r3, [r7, #12]
8007ba0: 681b ldr r3, [r3, #0]
8007ba2: 68b9 ldr r1, [r7, #8]
8007ba4: 4618 mov r0, r3
8007ba6: f000 faab bl 8008100 <TIM_OC2_SetConfig>
break;
8007baa: e01e b.n 8007bea <HAL_TIM_OC_ConfigChannel+0xe2>
{
/* Check the parameters */
assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
/* Configure the TIM Channel 3 in Output Compare */
TIM_OC3_SetConfig(htim->Instance, sConfig);
8007bac: 68fb ldr r3, [r7, #12]
8007bae: 681b ldr r3, [r3, #0]
8007bb0: 68b9 ldr r1, [r7, #8]
8007bb2: 4618 mov r0, r3
8007bb4: f000 fb38 bl 8008228 <TIM_OC3_SetConfig>
break;
8007bb8: e017 b.n 8007bea <HAL_TIM_OC_ConfigChannel+0xe2>
{
/* Check the parameters */
assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
/* Configure the TIM Channel 4 in Output Compare */
TIM_OC4_SetConfig(htim->Instance, sConfig);
8007bba: 68fb ldr r3, [r7, #12]
8007bbc: 681b ldr r3, [r3, #0]
8007bbe: 68b9 ldr r1, [r7, #8]
8007bc0: 4618 mov r0, r3
8007bc2: f000 fbc3 bl 800834c <TIM_OC4_SetConfig>
break;
8007bc6: e010 b.n 8007bea <HAL_TIM_OC_ConfigChannel+0xe2>
{
/* Check the parameters */
assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
/* Configure the TIM Channel 5 in Output Compare */
TIM_OC5_SetConfig(htim->Instance, sConfig);
8007bc8: 68fb ldr r3, [r7, #12]
8007bca: 681b ldr r3, [r3, #0]
8007bcc: 68b9 ldr r1, [r7, #8]
8007bce: 4618 mov r0, r3
8007bd0: f000 fc50 bl 8008474 <TIM_OC5_SetConfig>
break;
8007bd4: e009 b.n 8007bea <HAL_TIM_OC_ConfigChannel+0xe2>
{
/* Check the parameters */
assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
/* Configure the TIM Channel 6 in Output Compare */
TIM_OC6_SetConfig(htim->Instance, sConfig);
8007bd6: 68fb ldr r3, [r7, #12]
8007bd8: 681b ldr r3, [r3, #0]
8007bda: 68b9 ldr r1, [r7, #8]
8007bdc: 4618 mov r0, r3
8007bde: f000 fcb3 bl 8008548 <TIM_OC6_SetConfig>
break;
8007be2: e002 b.n 8007bea <HAL_TIM_OC_ConfigChannel+0xe2>
}
default:
status = HAL_ERROR;
8007be4: 2301 movs r3, #1
8007be6: 75fb strb r3, [r7, #23]
break;
8007be8: bf00 nop
}
__HAL_UNLOCK(htim);
8007bea: 68fb ldr r3, [r7, #12]
8007bec: 2200 movs r2, #0
8007bee: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8007bf2: 7dfb ldrb r3, [r7, #23]
}
8007bf4: 4618 mov r0, r3
8007bf6: 3718 adds r7, #24
8007bf8: 46bd mov sp, r7
8007bfa: bd80 pop {r7, pc}
08007bfc <HAL_TIM_ConfigClockSource>:
* @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
{
8007bfc: b580 push {r7, lr}
8007bfe: b084 sub sp, #16
8007c00: af00 add r7, sp, #0
8007c02: 6078 str r0, [r7, #4]
8007c04: 6039 str r1, [r7, #0]
HAL_StatusTypeDef status = HAL_OK;
8007c06: 2300 movs r3, #0
8007c08: 73fb strb r3, [r7, #15]
uint32_t tmpsmcr;
/* Process Locked */
__HAL_LOCK(htim);
8007c0a: 687b ldr r3, [r7, #4]
8007c0c: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
8007c10: 2b01 cmp r3, #1
8007c12: d101 bne.n 8007c18 <HAL_TIM_ConfigClockSource+0x1c>
8007c14: 2302 movs r3, #2
8007c16: e0f6 b.n 8007e06 <HAL_TIM_ConfigClockSource+0x20a>
8007c18: 687b ldr r3, [r7, #4]
8007c1a: 2201 movs r2, #1
8007c1c: f883 203c strb.w r2, [r3, #60] @ 0x3c
htim->State = HAL_TIM_STATE_BUSY;
8007c20: 687b ldr r3, [r7, #4]
8007c22: 2202 movs r2, #2
8007c24: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Check the parameters */
assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
/* Reset the SMS, TS, ECE, ETPS and ETRF bits */
tmpsmcr = htim->Instance->SMCR;
8007c28: 687b ldr r3, [r7, #4]
8007c2a: 681b ldr r3, [r3, #0]
8007c2c: 689b ldr r3, [r3, #8]
8007c2e: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
8007c30: 68bb ldr r3, [r7, #8]
8007c32: f423 1344 bic.w r3, r3, #3211264 @ 0x310000
8007c36: f023 0377 bic.w r3, r3, #119 @ 0x77
8007c3a: 60bb str r3, [r7, #8]
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
8007c3c: 68bb ldr r3, [r7, #8]
8007c3e: f423 437f bic.w r3, r3, #65280 @ 0xff00
8007c42: 60bb str r3, [r7, #8]
htim->Instance->SMCR = tmpsmcr;
8007c44: 687b ldr r3, [r7, #4]
8007c46: 681b ldr r3, [r3, #0]
8007c48: 68ba ldr r2, [r7, #8]
8007c4a: 609a str r2, [r3, #8]
switch (sClockSourceConfig->ClockSource)
8007c4c: 683b ldr r3, [r7, #0]
8007c4e: 681b ldr r3, [r3, #0]
8007c50: 4a6f ldr r2, [pc, #444] @ (8007e10 <HAL_TIM_ConfigClockSource+0x214>)
8007c52: 4293 cmp r3, r2
8007c54: f000 80c1 beq.w 8007dda <HAL_TIM_ConfigClockSource+0x1de>
8007c58: 4a6d ldr r2, [pc, #436] @ (8007e10 <HAL_TIM_ConfigClockSource+0x214>)
8007c5a: 4293 cmp r3, r2
8007c5c: f200 80c6 bhi.w 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007c60: 4a6c ldr r2, [pc, #432] @ (8007e14 <HAL_TIM_ConfigClockSource+0x218>)
8007c62: 4293 cmp r3, r2
8007c64: f000 80b9 beq.w 8007dda <HAL_TIM_ConfigClockSource+0x1de>
8007c68: 4a6a ldr r2, [pc, #424] @ (8007e14 <HAL_TIM_ConfigClockSource+0x218>)
8007c6a: 4293 cmp r3, r2
8007c6c: f200 80be bhi.w 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007c70: 4a69 ldr r2, [pc, #420] @ (8007e18 <HAL_TIM_ConfigClockSource+0x21c>)
8007c72: 4293 cmp r3, r2
8007c74: f000 80b1 beq.w 8007dda <HAL_TIM_ConfigClockSource+0x1de>
8007c78: 4a67 ldr r2, [pc, #412] @ (8007e18 <HAL_TIM_ConfigClockSource+0x21c>)
8007c7a: 4293 cmp r3, r2
8007c7c: f200 80b6 bhi.w 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007c80: 4a66 ldr r2, [pc, #408] @ (8007e1c <HAL_TIM_ConfigClockSource+0x220>)
8007c82: 4293 cmp r3, r2
8007c84: f000 80a9 beq.w 8007dda <HAL_TIM_ConfigClockSource+0x1de>
8007c88: 4a64 ldr r2, [pc, #400] @ (8007e1c <HAL_TIM_ConfigClockSource+0x220>)
8007c8a: 4293 cmp r3, r2
8007c8c: f200 80ae bhi.w 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007c90: 4a63 ldr r2, [pc, #396] @ (8007e20 <HAL_TIM_ConfigClockSource+0x224>)
8007c92: 4293 cmp r3, r2
8007c94: f000 80a1 beq.w 8007dda <HAL_TIM_ConfigClockSource+0x1de>
8007c98: 4a61 ldr r2, [pc, #388] @ (8007e20 <HAL_TIM_ConfigClockSource+0x224>)
8007c9a: 4293 cmp r3, r2
8007c9c: f200 80a6 bhi.w 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007ca0: 4a60 ldr r2, [pc, #384] @ (8007e24 <HAL_TIM_ConfigClockSource+0x228>)
8007ca2: 4293 cmp r3, r2
8007ca4: f000 8099 beq.w 8007dda <HAL_TIM_ConfigClockSource+0x1de>
8007ca8: 4a5e ldr r2, [pc, #376] @ (8007e24 <HAL_TIM_ConfigClockSource+0x228>)
8007caa: 4293 cmp r3, r2
8007cac: f200 809e bhi.w 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007cb0: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010
8007cb4: f000 8091 beq.w 8007dda <HAL_TIM_ConfigClockSource+0x1de>
8007cb8: f1b3 1f10 cmp.w r3, #1048592 @ 0x100010
8007cbc: f200 8096 bhi.w 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007cc0: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8007cc4: f000 8089 beq.w 8007dda <HAL_TIM_ConfigClockSource+0x1de>
8007cc8: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8007ccc: f200 808e bhi.w 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007cd0: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8007cd4: d03e beq.n 8007d54 <HAL_TIM_ConfigClockSource+0x158>
8007cd6: f5b3 5f00 cmp.w r3, #8192 @ 0x2000
8007cda: f200 8087 bhi.w 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007cde: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8007ce2: f000 8086 beq.w 8007df2 <HAL_TIM_ConfigClockSource+0x1f6>
8007ce6: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8007cea: d87f bhi.n 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007cec: 2b70 cmp r3, #112 @ 0x70
8007cee: d01a beq.n 8007d26 <HAL_TIM_ConfigClockSource+0x12a>
8007cf0: 2b70 cmp r3, #112 @ 0x70
8007cf2: d87b bhi.n 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007cf4: 2b60 cmp r3, #96 @ 0x60
8007cf6: d050 beq.n 8007d9a <HAL_TIM_ConfigClockSource+0x19e>
8007cf8: 2b60 cmp r3, #96 @ 0x60
8007cfa: d877 bhi.n 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007cfc: 2b50 cmp r3, #80 @ 0x50
8007cfe: d03c beq.n 8007d7a <HAL_TIM_ConfigClockSource+0x17e>
8007d00: 2b50 cmp r3, #80 @ 0x50
8007d02: d873 bhi.n 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007d04: 2b40 cmp r3, #64 @ 0x40
8007d06: d058 beq.n 8007dba <HAL_TIM_ConfigClockSource+0x1be>
8007d08: 2b40 cmp r3, #64 @ 0x40
8007d0a: d86f bhi.n 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007d0c: 2b30 cmp r3, #48 @ 0x30
8007d0e: d064 beq.n 8007dda <HAL_TIM_ConfigClockSource+0x1de>
8007d10: 2b30 cmp r3, #48 @ 0x30
8007d12: d86b bhi.n 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007d14: 2b20 cmp r3, #32
8007d16: d060 beq.n 8007dda <HAL_TIM_ConfigClockSource+0x1de>
8007d18: 2b20 cmp r3, #32
8007d1a: d867 bhi.n 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
8007d1c: 2b00 cmp r3, #0
8007d1e: d05c beq.n 8007dda <HAL_TIM_ConfigClockSource+0x1de>
8007d20: 2b10 cmp r3, #16
8007d22: d05a beq.n 8007dda <HAL_TIM_ConfigClockSource+0x1de>
8007d24: e062 b.n 8007dec <HAL_TIM_ConfigClockSource+0x1f0>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8007d26: 687b ldr r3, [r7, #4]
8007d28: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8007d2a: 683b ldr r3, [r7, #0]
8007d2c: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8007d2e: 683b ldr r3, [r7, #0]
8007d30: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8007d32: 683b ldr r3, [r7, #0]
8007d34: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8007d36: f000 fcef bl 8008718 <TIM_ETR_SetConfig>
/* Select the External clock mode1 and the ETRF trigger */
tmpsmcr = htim->Instance->SMCR;
8007d3a: 687b ldr r3, [r7, #4]
8007d3c: 681b ldr r3, [r3, #0]
8007d3e: 689b ldr r3, [r3, #8]
8007d40: 60bb str r3, [r7, #8]
tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
8007d42: 68bb ldr r3, [r7, #8]
8007d44: f043 0377 orr.w r3, r3, #119 @ 0x77
8007d48: 60bb str r3, [r7, #8]
/* Write to TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
8007d4a: 687b ldr r3, [r7, #4]
8007d4c: 681b ldr r3, [r3, #0]
8007d4e: 68ba ldr r2, [r7, #8]
8007d50: 609a str r2, [r3, #8]
break;
8007d52: e04f b.n 8007df4 <HAL_TIM_ConfigClockSource+0x1f8>
assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
/* Configure the ETR Clock source */
TIM_ETR_SetConfig(htim->Instance,
8007d54: 687b ldr r3, [r7, #4]
8007d56: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPrescaler,
8007d58: 683b ldr r3, [r7, #0]
8007d5a: 6899 ldr r1, [r3, #8]
sClockSourceConfig->ClockPolarity,
8007d5c: 683b ldr r3, [r7, #0]
8007d5e: 685a ldr r2, [r3, #4]
sClockSourceConfig->ClockFilter);
8007d60: 683b ldr r3, [r7, #0]
8007d62: 68db ldr r3, [r3, #12]
TIM_ETR_SetConfig(htim->Instance,
8007d64: f000 fcd8 bl 8008718 <TIM_ETR_SetConfig>
/* Enable the External clock mode2 */
htim->Instance->SMCR |= TIM_SMCR_ECE;
8007d68: 687b ldr r3, [r7, #4]
8007d6a: 681b ldr r3, [r3, #0]
8007d6c: 689a ldr r2, [r3, #8]
8007d6e: 687b ldr r3, [r7, #4]
8007d70: 681b ldr r3, [r3, #0]
8007d72: f442 4280 orr.w r2, r2, #16384 @ 0x4000
8007d76: 609a str r2, [r3, #8]
break;
8007d78: e03c b.n 8007df4 <HAL_TIM_ConfigClockSource+0x1f8>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8007d7a: 687b ldr r3, [r7, #4]
8007d7c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8007d7e: 683b ldr r3, [r7, #0]
8007d80: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8007d82: 683b ldr r3, [r7, #0]
8007d84: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8007d86: 461a mov r2, r3
8007d88: f000 fc4a bl 8008620 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
8007d8c: 687b ldr r3, [r7, #4]
8007d8e: 681b ldr r3, [r3, #0]
8007d90: 2150 movs r1, #80 @ 0x50
8007d92: 4618 mov r0, r3
8007d94: f000 fca3 bl 80086de <TIM_ITRx_SetConfig>
break;
8007d98: e02c b.n 8007df4 <HAL_TIM_ConfigClockSource+0x1f8>
/* Check TI2 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI2_ConfigInputStage(htim->Instance,
8007d9a: 687b ldr r3, [r7, #4]
8007d9c: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8007d9e: 683b ldr r3, [r7, #0]
8007da0: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8007da2: 683b ldr r3, [r7, #0]
8007da4: 68db ldr r3, [r3, #12]
TIM_TI2_ConfigInputStage(htim->Instance,
8007da6: 461a mov r2, r3
8007da8: f000 fc69 bl 800867e <TIM_TI2_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
8007dac: 687b ldr r3, [r7, #4]
8007dae: 681b ldr r3, [r3, #0]
8007db0: 2160 movs r1, #96 @ 0x60
8007db2: 4618 mov r0, r3
8007db4: f000 fc93 bl 80086de <TIM_ITRx_SetConfig>
break;
8007db8: e01c b.n 8007df4 <HAL_TIM_ConfigClockSource+0x1f8>
/* Check TI1 input conditioning related parameters */
assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
TIM_TI1_ConfigInputStage(htim->Instance,
8007dba: 687b ldr r3, [r7, #4]
8007dbc: 6818 ldr r0, [r3, #0]
sClockSourceConfig->ClockPolarity,
8007dbe: 683b ldr r3, [r7, #0]
8007dc0: 6859 ldr r1, [r3, #4]
sClockSourceConfig->ClockFilter);
8007dc2: 683b ldr r3, [r7, #0]
8007dc4: 68db ldr r3, [r3, #12]
TIM_TI1_ConfigInputStage(htim->Instance,
8007dc6: 461a mov r2, r3
8007dc8: f000 fc2a bl 8008620 <TIM_TI1_ConfigInputStage>
TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
8007dcc: 687b ldr r3, [r7, #4]
8007dce: 681b ldr r3, [r3, #0]
8007dd0: 2140 movs r1, #64 @ 0x40
8007dd2: 4618 mov r0, r3
8007dd4: f000 fc83 bl 80086de <TIM_ITRx_SetConfig>
break;
8007dd8: e00c b.n 8007df4 <HAL_TIM_ConfigClockSource+0x1f8>
case TIM_CLOCKSOURCE_ITR11:
{
/* Check whether or not the timer instance supports internal trigger input */
assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
8007dda: 687b ldr r3, [r7, #4]
8007ddc: 681a ldr r2, [r3, #0]
8007dde: 683b ldr r3, [r7, #0]
8007de0: 681b ldr r3, [r3, #0]
8007de2: 4619 mov r1, r3
8007de4: 4610 mov r0, r2
8007de6: f000 fc7a bl 80086de <TIM_ITRx_SetConfig>
break;
8007dea: e003 b.n 8007df4 <HAL_TIM_ConfigClockSource+0x1f8>
}
default:
status = HAL_ERROR;
8007dec: 2301 movs r3, #1
8007dee: 73fb strb r3, [r7, #15]
break;
8007df0: e000 b.n 8007df4 <HAL_TIM_ConfigClockSource+0x1f8>
break;
8007df2: bf00 nop
}
htim->State = HAL_TIM_STATE_READY;
8007df4: 687b ldr r3, [r7, #4]
8007df6: 2201 movs r2, #1
8007df8: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
8007dfc: 687b ldr r3, [r7, #4]
8007dfe: 2200 movs r2, #0
8007e00: f883 203c strb.w r2, [r3, #60] @ 0x3c
return status;
8007e04: 7bfb ldrb r3, [r7, #15]
}
8007e06: 4618 mov r0, r3
8007e08: 3710 adds r7, #16
8007e0a: 46bd mov sp, r7
8007e0c: bd80 pop {r7, pc}
8007e0e: bf00 nop
8007e10: 00100070 .word 0x00100070
8007e14: 00100060 .word 0x00100060
8007e18: 00100050 .word 0x00100050
8007e1c: 00100040 .word 0x00100040
8007e20: 00100030 .word 0x00100030
8007e24: 00100020 .word 0x00100020
08007e28 <HAL_TIM_IC_CaptureCallback>:
* @brief Input Capture callback in non-blocking mode
* @param htim TIM IC handle
* @retval None
*/
__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
{
8007e28: b480 push {r7}
8007e2a: b083 sub sp, #12
8007e2c: af00 add r7, sp, #0
8007e2e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_IC_CaptureCallback could be implemented in the user file
*/
}
8007e30: bf00 nop
8007e32: 370c adds r7, #12
8007e34: 46bd mov sp, r7
8007e36: f85d 7b04 ldr.w r7, [sp], #4
8007e3a: 4770 bx lr
08007e3c <HAL_TIM_PWM_PulseFinishedCallback>:
* @brief PWM Pulse finished callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
{
8007e3c: b480 push {r7}
8007e3e: b083 sub sp, #12
8007e40: af00 add r7, sp, #0
8007e42: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
*/
}
8007e44: bf00 nop
8007e46: 370c adds r7, #12
8007e48: 46bd mov sp, r7
8007e4a: f85d 7b04 ldr.w r7, [sp], #4
8007e4e: 4770 bx lr
08007e50 <HAL_TIM_TriggerCallback>:
* @brief Hall Trigger detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
{
8007e50: b480 push {r7}
8007e52: b083 sub sp, #12
8007e54: af00 add r7, sp, #0
8007e56: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIM_TriggerCallback could be implemented in the user file
*/
}
8007e58: bf00 nop
8007e5a: 370c adds r7, #12
8007e5c: 46bd mov sp, r7
8007e5e: f85d 7b04 ldr.w r7, [sp], #4
8007e62: 4770 bx lr
08007e64 <TIM_Base_SetConfig>:
* @param TIMx TIM peripheral
* @param Structure TIM Base configuration structure
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
{
8007e64: b480 push {r7}
8007e66: b085 sub sp, #20
8007e68: af00 add r7, sp, #0
8007e6a: 6078 str r0, [r7, #4]
8007e6c: 6039 str r1, [r7, #0]
uint32_t tmpcr1;
tmpcr1 = TIMx->CR1;
8007e6e: 687b ldr r3, [r7, #4]
8007e70: 681b ldr r3, [r3, #0]
8007e72: 60fb str r3, [r7, #12]
/* Set TIM Time Base Unit parameters ---------------------------------------*/
if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
8007e74: 687b ldr r3, [r7, #4]
8007e76: 4a4c ldr r2, [pc, #304] @ (8007fa8 <TIM_Base_SetConfig+0x144>)
8007e78: 4293 cmp r3, r2
8007e7a: d017 beq.n 8007eac <TIM_Base_SetConfig+0x48>
8007e7c: 687b ldr r3, [r7, #4]
8007e7e: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8007e82: d013 beq.n 8007eac <TIM_Base_SetConfig+0x48>
8007e84: 687b ldr r3, [r7, #4]
8007e86: 4a49 ldr r2, [pc, #292] @ (8007fac <TIM_Base_SetConfig+0x148>)
8007e88: 4293 cmp r3, r2
8007e8a: d00f beq.n 8007eac <TIM_Base_SetConfig+0x48>
8007e8c: 687b ldr r3, [r7, #4]
8007e8e: 4a48 ldr r2, [pc, #288] @ (8007fb0 <TIM_Base_SetConfig+0x14c>)
8007e90: 4293 cmp r3, r2
8007e92: d00b beq.n 8007eac <TIM_Base_SetConfig+0x48>
8007e94: 687b ldr r3, [r7, #4]
8007e96: 4a47 ldr r2, [pc, #284] @ (8007fb4 <TIM_Base_SetConfig+0x150>)
8007e98: 4293 cmp r3, r2
8007e9a: d007 beq.n 8007eac <TIM_Base_SetConfig+0x48>
8007e9c: 687b ldr r3, [r7, #4]
8007e9e: 4a46 ldr r2, [pc, #280] @ (8007fb8 <TIM_Base_SetConfig+0x154>)
8007ea0: 4293 cmp r3, r2
8007ea2: d003 beq.n 8007eac <TIM_Base_SetConfig+0x48>
8007ea4: 687b ldr r3, [r7, #4]
8007ea6: 4a45 ldr r2, [pc, #276] @ (8007fbc <TIM_Base_SetConfig+0x158>)
8007ea8: 4293 cmp r3, r2
8007eaa: d108 bne.n 8007ebe <TIM_Base_SetConfig+0x5a>
{
/* Select the Counter Mode */
tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
8007eac: 68fb ldr r3, [r7, #12]
8007eae: f023 0370 bic.w r3, r3, #112 @ 0x70
8007eb2: 60fb str r3, [r7, #12]
tmpcr1 |= Structure->CounterMode;
8007eb4: 683b ldr r3, [r7, #0]
8007eb6: 685b ldr r3, [r3, #4]
8007eb8: 68fa ldr r2, [r7, #12]
8007eba: 4313 orrs r3, r2
8007ebc: 60fb str r3, [r7, #12]
}
if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
8007ebe: 687b ldr r3, [r7, #4]
8007ec0: 4a39 ldr r2, [pc, #228] @ (8007fa8 <TIM_Base_SetConfig+0x144>)
8007ec2: 4293 cmp r3, r2
8007ec4: d023 beq.n 8007f0e <TIM_Base_SetConfig+0xaa>
8007ec6: 687b ldr r3, [r7, #4]
8007ec8: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
8007ecc: d01f beq.n 8007f0e <TIM_Base_SetConfig+0xaa>
8007ece: 687b ldr r3, [r7, #4]
8007ed0: 4a36 ldr r2, [pc, #216] @ (8007fac <TIM_Base_SetConfig+0x148>)
8007ed2: 4293 cmp r3, r2
8007ed4: d01b beq.n 8007f0e <TIM_Base_SetConfig+0xaa>
8007ed6: 687b ldr r3, [r7, #4]
8007ed8: 4a35 ldr r2, [pc, #212] @ (8007fb0 <TIM_Base_SetConfig+0x14c>)
8007eda: 4293 cmp r3, r2
8007edc: d017 beq.n 8007f0e <TIM_Base_SetConfig+0xaa>
8007ede: 687b ldr r3, [r7, #4]
8007ee0: 4a34 ldr r2, [pc, #208] @ (8007fb4 <TIM_Base_SetConfig+0x150>)
8007ee2: 4293 cmp r3, r2
8007ee4: d013 beq.n 8007f0e <TIM_Base_SetConfig+0xaa>
8007ee6: 687b ldr r3, [r7, #4]
8007ee8: 4a33 ldr r2, [pc, #204] @ (8007fb8 <TIM_Base_SetConfig+0x154>)
8007eea: 4293 cmp r3, r2
8007eec: d00f beq.n 8007f0e <TIM_Base_SetConfig+0xaa>
8007eee: 687b ldr r3, [r7, #4]
8007ef0: 4a33 ldr r2, [pc, #204] @ (8007fc0 <TIM_Base_SetConfig+0x15c>)
8007ef2: 4293 cmp r3, r2
8007ef4: d00b beq.n 8007f0e <TIM_Base_SetConfig+0xaa>
8007ef6: 687b ldr r3, [r7, #4]
8007ef8: 4a32 ldr r2, [pc, #200] @ (8007fc4 <TIM_Base_SetConfig+0x160>)
8007efa: 4293 cmp r3, r2
8007efc: d007 beq.n 8007f0e <TIM_Base_SetConfig+0xaa>
8007efe: 687b ldr r3, [r7, #4]
8007f00: 4a31 ldr r2, [pc, #196] @ (8007fc8 <TIM_Base_SetConfig+0x164>)
8007f02: 4293 cmp r3, r2
8007f04: d003 beq.n 8007f0e <TIM_Base_SetConfig+0xaa>
8007f06: 687b ldr r3, [r7, #4]
8007f08: 4a2c ldr r2, [pc, #176] @ (8007fbc <TIM_Base_SetConfig+0x158>)
8007f0a: 4293 cmp r3, r2
8007f0c: d108 bne.n 8007f20 <TIM_Base_SetConfig+0xbc>
{
/* Set the clock division */
tmpcr1 &= ~TIM_CR1_CKD;
8007f0e: 68fb ldr r3, [r7, #12]
8007f10: f423 7340 bic.w r3, r3, #768 @ 0x300
8007f14: 60fb str r3, [r7, #12]
tmpcr1 |= (uint32_t)Structure->ClockDivision;
8007f16: 683b ldr r3, [r7, #0]
8007f18: 68db ldr r3, [r3, #12]
8007f1a: 68fa ldr r2, [r7, #12]
8007f1c: 4313 orrs r3, r2
8007f1e: 60fb str r3, [r7, #12]
}
/* Set the auto-reload preload */
MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
8007f20: 68fb ldr r3, [r7, #12]
8007f22: f023 0280 bic.w r2, r3, #128 @ 0x80
8007f26: 683b ldr r3, [r7, #0]
8007f28: 695b ldr r3, [r3, #20]
8007f2a: 4313 orrs r3, r2
8007f2c: 60fb str r3, [r7, #12]
TIMx->CR1 = tmpcr1;
8007f2e: 687b ldr r3, [r7, #4]
8007f30: 68fa ldr r2, [r7, #12]
8007f32: 601a str r2, [r3, #0]
/* Set the Autoreload value */
TIMx->ARR = (uint32_t)Structure->Period ;
8007f34: 683b ldr r3, [r7, #0]
8007f36: 689a ldr r2, [r3, #8]
8007f38: 687b ldr r3, [r7, #4]
8007f3a: 62da str r2, [r3, #44] @ 0x2c
/* Set the Prescaler value */
TIMx->PSC = Structure->Prescaler;
8007f3c: 683b ldr r3, [r7, #0]
8007f3e: 681a ldr r2, [r3, #0]
8007f40: 687b ldr r3, [r7, #4]
8007f42: 629a str r2, [r3, #40] @ 0x28
if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
8007f44: 687b ldr r3, [r7, #4]
8007f46: 4a18 ldr r2, [pc, #96] @ (8007fa8 <TIM_Base_SetConfig+0x144>)
8007f48: 4293 cmp r3, r2
8007f4a: d013 beq.n 8007f74 <TIM_Base_SetConfig+0x110>
8007f4c: 687b ldr r3, [r7, #4]
8007f4e: 4a1a ldr r2, [pc, #104] @ (8007fb8 <TIM_Base_SetConfig+0x154>)
8007f50: 4293 cmp r3, r2
8007f52: d00f beq.n 8007f74 <TIM_Base_SetConfig+0x110>
8007f54: 687b ldr r3, [r7, #4]
8007f56: 4a1a ldr r2, [pc, #104] @ (8007fc0 <TIM_Base_SetConfig+0x15c>)
8007f58: 4293 cmp r3, r2
8007f5a: d00b beq.n 8007f74 <TIM_Base_SetConfig+0x110>
8007f5c: 687b ldr r3, [r7, #4]
8007f5e: 4a19 ldr r2, [pc, #100] @ (8007fc4 <TIM_Base_SetConfig+0x160>)
8007f60: 4293 cmp r3, r2
8007f62: d007 beq.n 8007f74 <TIM_Base_SetConfig+0x110>
8007f64: 687b ldr r3, [r7, #4]
8007f66: 4a18 ldr r2, [pc, #96] @ (8007fc8 <TIM_Base_SetConfig+0x164>)
8007f68: 4293 cmp r3, r2
8007f6a: d003 beq.n 8007f74 <TIM_Base_SetConfig+0x110>
8007f6c: 687b ldr r3, [r7, #4]
8007f6e: 4a13 ldr r2, [pc, #76] @ (8007fbc <TIM_Base_SetConfig+0x158>)
8007f70: 4293 cmp r3, r2
8007f72: d103 bne.n 8007f7c <TIM_Base_SetConfig+0x118>
{
/* Set the Repetition Counter value */
TIMx->RCR = Structure->RepetitionCounter;
8007f74: 683b ldr r3, [r7, #0]
8007f76: 691a ldr r2, [r3, #16]
8007f78: 687b ldr r3, [r7, #4]
8007f7a: 631a str r2, [r3, #48] @ 0x30
}
/* Generate an update event to reload the Prescaler
and the repetition counter (only for advanced timer) value immediately */
TIMx->EGR = TIM_EGR_UG;
8007f7c: 687b ldr r3, [r7, #4]
8007f7e: 2201 movs r2, #1
8007f80: 615a str r2, [r3, #20]
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
8007f82: 687b ldr r3, [r7, #4]
8007f84: 691b ldr r3, [r3, #16]
8007f86: f003 0301 and.w r3, r3, #1
8007f8a: 2b01 cmp r3, #1
8007f8c: d105 bne.n 8007f9a <TIM_Base_SetConfig+0x136>
{
/* Clear the update flag */
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
8007f8e: 687b ldr r3, [r7, #4]
8007f90: 691b ldr r3, [r3, #16]
8007f92: f023 0201 bic.w r2, r3, #1
8007f96: 687b ldr r3, [r7, #4]
8007f98: 611a str r2, [r3, #16]
}
}
8007f9a: bf00 nop
8007f9c: 3714 adds r7, #20
8007f9e: 46bd mov sp, r7
8007fa0: f85d 7b04 ldr.w r7, [sp], #4
8007fa4: 4770 bx lr
8007fa6: bf00 nop
8007fa8: 40012c00 .word 0x40012c00
8007fac: 40000400 .word 0x40000400
8007fb0: 40000800 .word 0x40000800
8007fb4: 40000c00 .word 0x40000c00
8007fb8: 40013400 .word 0x40013400
8007fbc: 40015000 .word 0x40015000
8007fc0: 40014000 .word 0x40014000
8007fc4: 40014400 .word 0x40014400
8007fc8: 40014800 .word 0x40014800
08007fcc <TIM_OC1_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8007fcc: b480 push {r7}
8007fce: b087 sub sp, #28
8007fd0: af00 add r7, sp, #0
8007fd2: 6078 str r0, [r7, #4]
8007fd4: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8007fd6: 687b ldr r3, [r7, #4]
8007fd8: 6a1b ldr r3, [r3, #32]
8007fda: 617b str r3, [r7, #20]
/* Disable the Channel 1: Reset the CC1E Bit */
TIMx->CCER &= ~TIM_CCER_CC1E;
8007fdc: 687b ldr r3, [r7, #4]
8007fde: 6a1b ldr r3, [r3, #32]
8007fe0: f023 0201 bic.w r2, r3, #1
8007fe4: 687b ldr r3, [r7, #4]
8007fe6: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8007fe8: 687b ldr r3, [r7, #4]
8007fea: 685b ldr r3, [r3, #4]
8007fec: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8007fee: 687b ldr r3, [r7, #4]
8007ff0: 699b ldr r3, [r3, #24]
8007ff2: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~TIM_CCMR1_OC1M;
8007ff4: 68fb ldr r3, [r7, #12]
8007ff6: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8007ffa: f023 0370 bic.w r3, r3, #112 @ 0x70
8007ffe: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC1S;
8008000: 68fb ldr r3, [r7, #12]
8008002: f023 0303 bic.w r3, r3, #3
8008006: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8008008: 683b ldr r3, [r7, #0]
800800a: 681b ldr r3, [r3, #0]
800800c: 68fa ldr r2, [r7, #12]
800800e: 4313 orrs r3, r2
8008010: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC1P;
8008012: 697b ldr r3, [r7, #20]
8008014: f023 0302 bic.w r3, r3, #2
8008018: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= OC_Config->OCPolarity;
800801a: 683b ldr r3, [r7, #0]
800801c: 689b ldr r3, [r3, #8]
800801e: 697a ldr r2, [r7, #20]
8008020: 4313 orrs r3, r2
8008022: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
8008024: 687b ldr r3, [r7, #4]
8008026: 4a30 ldr r2, [pc, #192] @ (80080e8 <TIM_OC1_SetConfig+0x11c>)
8008028: 4293 cmp r3, r2
800802a: d013 beq.n 8008054 <TIM_OC1_SetConfig+0x88>
800802c: 687b ldr r3, [r7, #4]
800802e: 4a2f ldr r2, [pc, #188] @ (80080ec <TIM_OC1_SetConfig+0x120>)
8008030: 4293 cmp r3, r2
8008032: d00f beq.n 8008054 <TIM_OC1_SetConfig+0x88>
8008034: 687b ldr r3, [r7, #4]
8008036: 4a2e ldr r2, [pc, #184] @ (80080f0 <TIM_OC1_SetConfig+0x124>)
8008038: 4293 cmp r3, r2
800803a: d00b beq.n 8008054 <TIM_OC1_SetConfig+0x88>
800803c: 687b ldr r3, [r7, #4]
800803e: 4a2d ldr r2, [pc, #180] @ (80080f4 <TIM_OC1_SetConfig+0x128>)
8008040: 4293 cmp r3, r2
8008042: d007 beq.n 8008054 <TIM_OC1_SetConfig+0x88>
8008044: 687b ldr r3, [r7, #4]
8008046: 4a2c ldr r2, [pc, #176] @ (80080f8 <TIM_OC1_SetConfig+0x12c>)
8008048: 4293 cmp r3, r2
800804a: d003 beq.n 8008054 <TIM_OC1_SetConfig+0x88>
800804c: 687b ldr r3, [r7, #4]
800804e: 4a2b ldr r2, [pc, #172] @ (80080fc <TIM_OC1_SetConfig+0x130>)
8008050: 4293 cmp r3, r2
8008052: d10c bne.n 800806e <TIM_OC1_SetConfig+0xa2>
{
/* Check parameters */
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC1NP;
8008054: 697b ldr r3, [r7, #20]
8008056: f023 0308 bic.w r3, r3, #8
800805a: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= OC_Config->OCNPolarity;
800805c: 683b ldr r3, [r7, #0]
800805e: 68db ldr r3, [r3, #12]
8008060: 697a ldr r2, [r7, #20]
8008062: 4313 orrs r3, r2
8008064: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC1NE;
8008066: 697b ldr r3, [r7, #20]
8008068: f023 0304 bic.w r3, r3, #4
800806c: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
800806e: 687b ldr r3, [r7, #4]
8008070: 4a1d ldr r2, [pc, #116] @ (80080e8 <TIM_OC1_SetConfig+0x11c>)
8008072: 4293 cmp r3, r2
8008074: d013 beq.n 800809e <TIM_OC1_SetConfig+0xd2>
8008076: 687b ldr r3, [r7, #4]
8008078: 4a1c ldr r2, [pc, #112] @ (80080ec <TIM_OC1_SetConfig+0x120>)
800807a: 4293 cmp r3, r2
800807c: d00f beq.n 800809e <TIM_OC1_SetConfig+0xd2>
800807e: 687b ldr r3, [r7, #4]
8008080: 4a1b ldr r2, [pc, #108] @ (80080f0 <TIM_OC1_SetConfig+0x124>)
8008082: 4293 cmp r3, r2
8008084: d00b beq.n 800809e <TIM_OC1_SetConfig+0xd2>
8008086: 687b ldr r3, [r7, #4]
8008088: 4a1a ldr r2, [pc, #104] @ (80080f4 <TIM_OC1_SetConfig+0x128>)
800808a: 4293 cmp r3, r2
800808c: d007 beq.n 800809e <TIM_OC1_SetConfig+0xd2>
800808e: 687b ldr r3, [r7, #4]
8008090: 4a19 ldr r2, [pc, #100] @ (80080f8 <TIM_OC1_SetConfig+0x12c>)
8008092: 4293 cmp r3, r2
8008094: d003 beq.n 800809e <TIM_OC1_SetConfig+0xd2>
8008096: 687b ldr r3, [r7, #4]
8008098: 4a18 ldr r2, [pc, #96] @ (80080fc <TIM_OC1_SetConfig+0x130>)
800809a: 4293 cmp r3, r2
800809c: d111 bne.n 80080c2 <TIM_OC1_SetConfig+0xf6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS1;
800809e: 693b ldr r3, [r7, #16]
80080a0: f423 7380 bic.w r3, r3, #256 @ 0x100
80080a4: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS1N;
80080a6: 693b ldr r3, [r7, #16]
80080a8: f423 7300 bic.w r3, r3, #512 @ 0x200
80080ac: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= OC_Config->OCIdleState;
80080ae: 683b ldr r3, [r7, #0]
80080b0: 695b ldr r3, [r3, #20]
80080b2: 693a ldr r2, [r7, #16]
80080b4: 4313 orrs r3, r2
80080b6: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= OC_Config->OCNIdleState;
80080b8: 683b ldr r3, [r7, #0]
80080ba: 699b ldr r3, [r3, #24]
80080bc: 693a ldr r2, [r7, #16]
80080be: 4313 orrs r3, r2
80080c0: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80080c2: 687b ldr r3, [r7, #4]
80080c4: 693a ldr r2, [r7, #16]
80080c6: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
80080c8: 687b ldr r3, [r7, #4]
80080ca: 68fa ldr r2, [r7, #12]
80080cc: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR1 = OC_Config->Pulse;
80080ce: 683b ldr r3, [r7, #0]
80080d0: 685a ldr r2, [r3, #4]
80080d2: 687b ldr r3, [r7, #4]
80080d4: 635a str r2, [r3, #52] @ 0x34
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80080d6: 687b ldr r3, [r7, #4]
80080d8: 697a ldr r2, [r7, #20]
80080da: 621a str r2, [r3, #32]
}
80080dc: bf00 nop
80080de: 371c adds r7, #28
80080e0: 46bd mov sp, r7
80080e2: f85d 7b04 ldr.w r7, [sp], #4
80080e6: 4770 bx lr
80080e8: 40012c00 .word 0x40012c00
80080ec: 40013400 .word 0x40013400
80080f0: 40014000 .word 0x40014000
80080f4: 40014400 .word 0x40014400
80080f8: 40014800 .word 0x40014800
80080fc: 40015000 .word 0x40015000
08008100 <TIM_OC2_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8008100: b480 push {r7}
8008102: b087 sub sp, #28
8008104: af00 add r7, sp, #0
8008106: 6078 str r0, [r7, #4]
8008108: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800810a: 687b ldr r3, [r7, #4]
800810c: 6a1b ldr r3, [r3, #32]
800810e: 617b str r3, [r7, #20]
/* Disable the Channel 2: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC2E;
8008110: 687b ldr r3, [r7, #4]
8008112: 6a1b ldr r3, [r3, #32]
8008114: f023 0210 bic.w r2, r3, #16
8008118: 687b ldr r3, [r7, #4]
800811a: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
800811c: 687b ldr r3, [r7, #4]
800811e: 685b ldr r3, [r3, #4]
8008120: 613b str r3, [r7, #16]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR1;
8008122: 687b ldr r3, [r7, #4]
8008124: 699b ldr r3, [r3, #24]
8008126: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR1_OC2M;
8008128: 68fb ldr r3, [r7, #12]
800812a: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800812e: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
8008132: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR1_CC2S;
8008134: 68fb ldr r3, [r7, #12]
8008136: f423 7340 bic.w r3, r3, #768 @ 0x300
800813a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800813c: 683b ldr r3, [r7, #0]
800813e: 681b ldr r3, [r3, #0]
8008140: 021b lsls r3, r3, #8
8008142: 68fa ldr r2, [r7, #12]
8008144: 4313 orrs r3, r2
8008146: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC2P;
8008148: 697b ldr r3, [r7, #20]
800814a: f023 0320 bic.w r3, r3, #32
800814e: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 4U);
8008150: 683b ldr r3, [r7, #0]
8008152: 689b ldr r3, [r3, #8]
8008154: 011b lsls r3, r3, #4
8008156: 697a ldr r2, [r7, #20]
8008158: 4313 orrs r3, r2
800815a: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
800815c: 687b ldr r3, [r7, #4]
800815e: 4a2c ldr r2, [pc, #176] @ (8008210 <TIM_OC2_SetConfig+0x110>)
8008160: 4293 cmp r3, r2
8008162: d007 beq.n 8008174 <TIM_OC2_SetConfig+0x74>
8008164: 687b ldr r3, [r7, #4]
8008166: 4a2b ldr r2, [pc, #172] @ (8008214 <TIM_OC2_SetConfig+0x114>)
8008168: 4293 cmp r3, r2
800816a: d003 beq.n 8008174 <TIM_OC2_SetConfig+0x74>
800816c: 687b ldr r3, [r7, #4]
800816e: 4a2a ldr r2, [pc, #168] @ (8008218 <TIM_OC2_SetConfig+0x118>)
8008170: 4293 cmp r3, r2
8008172: d10d bne.n 8008190 <TIM_OC2_SetConfig+0x90>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC2NP;
8008174: 697b ldr r3, [r7, #20]
8008176: f023 0380 bic.w r3, r3, #128 @ 0x80
800817a: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 4U);
800817c: 683b ldr r3, [r7, #0]
800817e: 68db ldr r3, [r3, #12]
8008180: 011b lsls r3, r3, #4
8008182: 697a ldr r2, [r7, #20]
8008184: 4313 orrs r3, r2
8008186: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC2NE;
8008188: 697b ldr r3, [r7, #20]
800818a: f023 0340 bic.w r3, r3, #64 @ 0x40
800818e: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
8008190: 687b ldr r3, [r7, #4]
8008192: 4a1f ldr r2, [pc, #124] @ (8008210 <TIM_OC2_SetConfig+0x110>)
8008194: 4293 cmp r3, r2
8008196: d013 beq.n 80081c0 <TIM_OC2_SetConfig+0xc0>
8008198: 687b ldr r3, [r7, #4]
800819a: 4a1e ldr r2, [pc, #120] @ (8008214 <TIM_OC2_SetConfig+0x114>)
800819c: 4293 cmp r3, r2
800819e: d00f beq.n 80081c0 <TIM_OC2_SetConfig+0xc0>
80081a0: 687b ldr r3, [r7, #4]
80081a2: 4a1e ldr r2, [pc, #120] @ (800821c <TIM_OC2_SetConfig+0x11c>)
80081a4: 4293 cmp r3, r2
80081a6: d00b beq.n 80081c0 <TIM_OC2_SetConfig+0xc0>
80081a8: 687b ldr r3, [r7, #4]
80081aa: 4a1d ldr r2, [pc, #116] @ (8008220 <TIM_OC2_SetConfig+0x120>)
80081ac: 4293 cmp r3, r2
80081ae: d007 beq.n 80081c0 <TIM_OC2_SetConfig+0xc0>
80081b0: 687b ldr r3, [r7, #4]
80081b2: 4a1c ldr r2, [pc, #112] @ (8008224 <TIM_OC2_SetConfig+0x124>)
80081b4: 4293 cmp r3, r2
80081b6: d003 beq.n 80081c0 <TIM_OC2_SetConfig+0xc0>
80081b8: 687b ldr r3, [r7, #4]
80081ba: 4a17 ldr r2, [pc, #92] @ (8008218 <TIM_OC2_SetConfig+0x118>)
80081bc: 4293 cmp r3, r2
80081be: d113 bne.n 80081e8 <TIM_OC2_SetConfig+0xe8>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS2;
80081c0: 693b ldr r3, [r7, #16]
80081c2: f423 6380 bic.w r3, r3, #1024 @ 0x400
80081c6: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS2N;
80081c8: 693b ldr r3, [r7, #16]
80081ca: f423 6300 bic.w r3, r3, #2048 @ 0x800
80081ce: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 2U);
80081d0: 683b ldr r3, [r7, #0]
80081d2: 695b ldr r3, [r3, #20]
80081d4: 009b lsls r3, r3, #2
80081d6: 693a ldr r2, [r7, #16]
80081d8: 4313 orrs r3, r2
80081da: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 2U);
80081dc: 683b ldr r3, [r7, #0]
80081de: 699b ldr r3, [r3, #24]
80081e0: 009b lsls r3, r3, #2
80081e2: 693a ldr r2, [r7, #16]
80081e4: 4313 orrs r3, r2
80081e6: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80081e8: 687b ldr r3, [r7, #4]
80081ea: 693a ldr r2, [r7, #16]
80081ec: 605a str r2, [r3, #4]
/* Write to TIMx CCMR1 */
TIMx->CCMR1 = tmpccmrx;
80081ee: 687b ldr r3, [r7, #4]
80081f0: 68fa ldr r2, [r7, #12]
80081f2: 619a str r2, [r3, #24]
/* Set the Capture Compare Register value */
TIMx->CCR2 = OC_Config->Pulse;
80081f4: 683b ldr r3, [r7, #0]
80081f6: 685a ldr r2, [r3, #4]
80081f8: 687b ldr r3, [r7, #4]
80081fa: 639a str r2, [r3, #56] @ 0x38
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80081fc: 687b ldr r3, [r7, #4]
80081fe: 697a ldr r2, [r7, #20]
8008200: 621a str r2, [r3, #32]
}
8008202: bf00 nop
8008204: 371c adds r7, #28
8008206: 46bd mov sp, r7
8008208: f85d 7b04 ldr.w r7, [sp], #4
800820c: 4770 bx lr
800820e: bf00 nop
8008210: 40012c00 .word 0x40012c00
8008214: 40013400 .word 0x40013400
8008218: 40015000 .word 0x40015000
800821c: 40014000 .word 0x40014000
8008220: 40014400 .word 0x40014400
8008224: 40014800 .word 0x40014800
08008228 <TIM_OC3_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
8008228: b480 push {r7}
800822a: b087 sub sp, #28
800822c: af00 add r7, sp, #0
800822e: 6078 str r0, [r7, #4]
8008230: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8008232: 687b ldr r3, [r7, #4]
8008234: 6a1b ldr r3, [r3, #32]
8008236: 617b str r3, [r7, #20]
/* Disable the Channel 3: Reset the CC2E Bit */
TIMx->CCER &= ~TIM_CCER_CC3E;
8008238: 687b ldr r3, [r7, #4]
800823a: 6a1b ldr r3, [r3, #32]
800823c: f423 7280 bic.w r2, r3, #256 @ 0x100
8008240: 687b ldr r3, [r7, #4]
8008242: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8008244: 687b ldr r3, [r7, #4]
8008246: 685b ldr r3, [r3, #4]
8008248: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800824a: 687b ldr r3, [r7, #4]
800824c: 69db ldr r3, [r3, #28]
800824e: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC3M;
8008250: 68fb ldr r3, [r7, #12]
8008252: f423 3380 bic.w r3, r3, #65536 @ 0x10000
8008256: f023 0370 bic.w r3, r3, #112 @ 0x70
800825a: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC3S;
800825c: 68fb ldr r3, [r7, #12]
800825e: f023 0303 bic.w r3, r3, #3
8008262: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
8008264: 683b ldr r3, [r7, #0]
8008266: 681b ldr r3, [r3, #0]
8008268: 68fa ldr r2, [r7, #12]
800826a: 4313 orrs r3, r2
800826c: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC3P;
800826e: 697b ldr r3, [r7, #20]
8008270: f423 7300 bic.w r3, r3, #512 @ 0x200
8008274: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 8U);
8008276: 683b ldr r3, [r7, #0]
8008278: 689b ldr r3, [r3, #8]
800827a: 021b lsls r3, r3, #8
800827c: 697a ldr r2, [r7, #20]
800827e: 4313 orrs r3, r2
8008280: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
8008282: 687b ldr r3, [r7, #4]
8008284: 4a2b ldr r2, [pc, #172] @ (8008334 <TIM_OC3_SetConfig+0x10c>)
8008286: 4293 cmp r3, r2
8008288: d007 beq.n 800829a <TIM_OC3_SetConfig+0x72>
800828a: 687b ldr r3, [r7, #4]
800828c: 4a2a ldr r2, [pc, #168] @ (8008338 <TIM_OC3_SetConfig+0x110>)
800828e: 4293 cmp r3, r2
8008290: d003 beq.n 800829a <TIM_OC3_SetConfig+0x72>
8008292: 687b ldr r3, [r7, #4]
8008294: 4a29 ldr r2, [pc, #164] @ (800833c <TIM_OC3_SetConfig+0x114>)
8008296: 4293 cmp r3, r2
8008298: d10d bne.n 80082b6 <TIM_OC3_SetConfig+0x8e>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC3NP;
800829a: 697b ldr r3, [r7, #20]
800829c: f423 6300 bic.w r3, r3, #2048 @ 0x800
80082a0: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 8U);
80082a2: 683b ldr r3, [r7, #0]
80082a4: 68db ldr r3, [r3, #12]
80082a6: 021b lsls r3, r3, #8
80082a8: 697a ldr r2, [r7, #20]
80082aa: 4313 orrs r3, r2
80082ac: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC3NE;
80082ae: 697b ldr r3, [r7, #20]
80082b0: f423 6380 bic.w r3, r3, #1024 @ 0x400
80082b4: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
80082b6: 687b ldr r3, [r7, #4]
80082b8: 4a1e ldr r2, [pc, #120] @ (8008334 <TIM_OC3_SetConfig+0x10c>)
80082ba: 4293 cmp r3, r2
80082bc: d013 beq.n 80082e6 <TIM_OC3_SetConfig+0xbe>
80082be: 687b ldr r3, [r7, #4]
80082c0: 4a1d ldr r2, [pc, #116] @ (8008338 <TIM_OC3_SetConfig+0x110>)
80082c2: 4293 cmp r3, r2
80082c4: d00f beq.n 80082e6 <TIM_OC3_SetConfig+0xbe>
80082c6: 687b ldr r3, [r7, #4]
80082c8: 4a1d ldr r2, [pc, #116] @ (8008340 <TIM_OC3_SetConfig+0x118>)
80082ca: 4293 cmp r3, r2
80082cc: d00b beq.n 80082e6 <TIM_OC3_SetConfig+0xbe>
80082ce: 687b ldr r3, [r7, #4]
80082d0: 4a1c ldr r2, [pc, #112] @ (8008344 <TIM_OC3_SetConfig+0x11c>)
80082d2: 4293 cmp r3, r2
80082d4: d007 beq.n 80082e6 <TIM_OC3_SetConfig+0xbe>
80082d6: 687b ldr r3, [r7, #4]
80082d8: 4a1b ldr r2, [pc, #108] @ (8008348 <TIM_OC3_SetConfig+0x120>)
80082da: 4293 cmp r3, r2
80082dc: d003 beq.n 80082e6 <TIM_OC3_SetConfig+0xbe>
80082de: 687b ldr r3, [r7, #4]
80082e0: 4a16 ldr r2, [pc, #88] @ (800833c <TIM_OC3_SetConfig+0x114>)
80082e2: 4293 cmp r3, r2
80082e4: d113 bne.n 800830e <TIM_OC3_SetConfig+0xe6>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare and Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS3;
80082e6: 693b ldr r3, [r7, #16]
80082e8: f423 5380 bic.w r3, r3, #4096 @ 0x1000
80082ec: 613b str r3, [r7, #16]
tmpcr2 &= ~TIM_CR2_OIS3N;
80082ee: 693b ldr r3, [r7, #16]
80082f0: f423 5300 bic.w r3, r3, #8192 @ 0x2000
80082f4: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 4U);
80082f6: 683b ldr r3, [r7, #0]
80082f8: 695b ldr r3, [r3, #20]
80082fa: 011b lsls r3, r3, #4
80082fc: 693a ldr r2, [r7, #16]
80082fe: 4313 orrs r3, r2
8008300: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 4U);
8008302: 683b ldr r3, [r7, #0]
8008304: 699b ldr r3, [r3, #24]
8008306: 011b lsls r3, r3, #4
8008308: 693a ldr r2, [r7, #16]
800830a: 4313 orrs r3, r2
800830c: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800830e: 687b ldr r3, [r7, #4]
8008310: 693a ldr r2, [r7, #16]
8008312: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
8008314: 687b ldr r3, [r7, #4]
8008316: 68fa ldr r2, [r7, #12]
8008318: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR3 = OC_Config->Pulse;
800831a: 683b ldr r3, [r7, #0]
800831c: 685a ldr r2, [r3, #4]
800831e: 687b ldr r3, [r7, #4]
8008320: 63da str r2, [r3, #60] @ 0x3c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8008322: 687b ldr r3, [r7, #4]
8008324: 697a ldr r2, [r7, #20]
8008326: 621a str r2, [r3, #32]
}
8008328: bf00 nop
800832a: 371c adds r7, #28
800832c: 46bd mov sp, r7
800832e: f85d 7b04 ldr.w r7, [sp], #4
8008332: 4770 bx lr
8008334: 40012c00 .word 0x40012c00
8008338: 40013400 .word 0x40013400
800833c: 40015000 .word 0x40015000
8008340: 40014000 .word 0x40014000
8008344: 40014400 .word 0x40014400
8008348: 40014800 .word 0x40014800
0800834c <TIM_OC4_SetConfig>:
* @param TIMx to select the TIM peripheral
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
{
800834c: b480 push {r7}
800834e: b087 sub sp, #28
8008350: af00 add r7, sp, #0
8008352: 6078 str r0, [r7, #4]
8008354: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8008356: 687b ldr r3, [r7, #4]
8008358: 6a1b ldr r3, [r3, #32]
800835a: 617b str r3, [r7, #20]
/* Disable the Channel 4: Reset the CC4E Bit */
TIMx->CCER &= ~TIM_CCER_CC4E;
800835c: 687b ldr r3, [r7, #4]
800835e: 6a1b ldr r3, [r3, #32]
8008360: f423 5280 bic.w r2, r3, #4096 @ 0x1000
8008364: 687b ldr r3, [r7, #4]
8008366: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8008368: 687b ldr r3, [r7, #4]
800836a: 685b ldr r3, [r3, #4]
800836c: 613b str r3, [r7, #16]
/* Get the TIMx CCMR2 register value */
tmpccmrx = TIMx->CCMR2;
800836e: 687b ldr r3, [r7, #4]
8008370: 69db ldr r3, [r3, #28]
8008372: 60fb str r3, [r7, #12]
/* Reset the Output Compare mode and Capture/Compare selection Bits */
tmpccmrx &= ~TIM_CCMR2_OC4M;
8008374: 68fb ldr r3, [r7, #12]
8008376: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
800837a: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800837e: 60fb str r3, [r7, #12]
tmpccmrx &= ~TIM_CCMR2_CC4S;
8008380: 68fb ldr r3, [r7, #12]
8008382: f423 7340 bic.w r3, r3, #768 @ 0x300
8008386: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
8008388: 683b ldr r3, [r7, #0]
800838a: 681b ldr r3, [r3, #0]
800838c: 021b lsls r3, r3, #8
800838e: 68fa ldr r2, [r7, #12]
8008390: 4313 orrs r3, r2
8008392: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC4P;
8008394: 697b ldr r3, [r7, #20]
8008396: f423 5300 bic.w r3, r3, #8192 @ 0x2000
800839a: 617b str r3, [r7, #20]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 12U);
800839c: 683b ldr r3, [r7, #0]
800839e: 689b ldr r3, [r3, #8]
80083a0: 031b lsls r3, r3, #12
80083a2: 697a ldr r2, [r7, #20]
80083a4: 4313 orrs r3, r2
80083a6: 617b str r3, [r7, #20]
if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
80083a8: 687b ldr r3, [r7, #4]
80083aa: 4a2c ldr r2, [pc, #176] @ (800845c <TIM_OC4_SetConfig+0x110>)
80083ac: 4293 cmp r3, r2
80083ae: d007 beq.n 80083c0 <TIM_OC4_SetConfig+0x74>
80083b0: 687b ldr r3, [r7, #4]
80083b2: 4a2b ldr r2, [pc, #172] @ (8008460 <TIM_OC4_SetConfig+0x114>)
80083b4: 4293 cmp r3, r2
80083b6: d003 beq.n 80083c0 <TIM_OC4_SetConfig+0x74>
80083b8: 687b ldr r3, [r7, #4]
80083ba: 4a2a ldr r2, [pc, #168] @ (8008464 <TIM_OC4_SetConfig+0x118>)
80083bc: 4293 cmp r3, r2
80083be: d10d bne.n 80083dc <TIM_OC4_SetConfig+0x90>
{
assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
/* Reset the Output N Polarity level */
tmpccer &= ~TIM_CCER_CC4NP;
80083c0: 697b ldr r3, [r7, #20]
80083c2: f423 4300 bic.w r3, r3, #32768 @ 0x8000
80083c6: 617b str r3, [r7, #20]
/* Set the Output N Polarity */
tmpccer |= (OC_Config->OCNPolarity << 12U);
80083c8: 683b ldr r3, [r7, #0]
80083ca: 68db ldr r3, [r3, #12]
80083cc: 031b lsls r3, r3, #12
80083ce: 697a ldr r2, [r7, #20]
80083d0: 4313 orrs r3, r2
80083d2: 617b str r3, [r7, #20]
/* Reset the Output N State */
tmpccer &= ~TIM_CCER_CC4NE;
80083d4: 697b ldr r3, [r7, #20]
80083d6: f423 4380 bic.w r3, r3, #16384 @ 0x4000
80083da: 617b str r3, [r7, #20]
}
if (IS_TIM_BREAK_INSTANCE(TIMx))
80083dc: 687b ldr r3, [r7, #4]
80083de: 4a1f ldr r2, [pc, #124] @ (800845c <TIM_OC4_SetConfig+0x110>)
80083e0: 4293 cmp r3, r2
80083e2: d013 beq.n 800840c <TIM_OC4_SetConfig+0xc0>
80083e4: 687b ldr r3, [r7, #4]
80083e6: 4a1e ldr r2, [pc, #120] @ (8008460 <TIM_OC4_SetConfig+0x114>)
80083e8: 4293 cmp r3, r2
80083ea: d00f beq.n 800840c <TIM_OC4_SetConfig+0xc0>
80083ec: 687b ldr r3, [r7, #4]
80083ee: 4a1e ldr r2, [pc, #120] @ (8008468 <TIM_OC4_SetConfig+0x11c>)
80083f0: 4293 cmp r3, r2
80083f2: d00b beq.n 800840c <TIM_OC4_SetConfig+0xc0>
80083f4: 687b ldr r3, [r7, #4]
80083f6: 4a1d ldr r2, [pc, #116] @ (800846c <TIM_OC4_SetConfig+0x120>)
80083f8: 4293 cmp r3, r2
80083fa: d007 beq.n 800840c <TIM_OC4_SetConfig+0xc0>
80083fc: 687b ldr r3, [r7, #4]
80083fe: 4a1c ldr r2, [pc, #112] @ (8008470 <TIM_OC4_SetConfig+0x124>)
8008400: 4293 cmp r3, r2
8008402: d003 beq.n 800840c <TIM_OC4_SetConfig+0xc0>
8008404: 687b ldr r3, [r7, #4]
8008406: 4a17 ldr r2, [pc, #92] @ (8008464 <TIM_OC4_SetConfig+0x118>)
8008408: 4293 cmp r3, r2
800840a: d113 bne.n 8008434 <TIM_OC4_SetConfig+0xe8>
/* Check parameters */
assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4;
800840c: 693b ldr r3, [r7, #16]
800840e: f423 4380 bic.w r3, r3, #16384 @ 0x4000
8008412: 613b str r3, [r7, #16]
/* Reset the Output Compare N IDLE State */
tmpcr2 &= ~TIM_CR2_OIS4N;
8008414: 693b ldr r3, [r7, #16]
8008416: f423 4300 bic.w r3, r3, #32768 @ 0x8000
800841a: 613b str r3, [r7, #16]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 6U);
800841c: 683b ldr r3, [r7, #0]
800841e: 695b ldr r3, [r3, #20]
8008420: 019b lsls r3, r3, #6
8008422: 693a ldr r2, [r7, #16]
8008424: 4313 orrs r3, r2
8008426: 613b str r3, [r7, #16]
/* Set the Output N Idle state */
tmpcr2 |= (OC_Config->OCNIdleState << 6U);
8008428: 683b ldr r3, [r7, #0]
800842a: 699b ldr r3, [r3, #24]
800842c: 019b lsls r3, r3, #6
800842e: 693a ldr r2, [r7, #16]
8008430: 4313 orrs r3, r2
8008432: 613b str r3, [r7, #16]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
8008434: 687b ldr r3, [r7, #4]
8008436: 693a ldr r2, [r7, #16]
8008438: 605a str r2, [r3, #4]
/* Write to TIMx CCMR2 */
TIMx->CCMR2 = tmpccmrx;
800843a: 687b ldr r3, [r7, #4]
800843c: 68fa ldr r2, [r7, #12]
800843e: 61da str r2, [r3, #28]
/* Set the Capture Compare Register value */
TIMx->CCR4 = OC_Config->Pulse;
8008440: 683b ldr r3, [r7, #0]
8008442: 685a ldr r2, [r3, #4]
8008444: 687b ldr r3, [r7, #4]
8008446: 641a str r2, [r3, #64] @ 0x40
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
8008448: 687b ldr r3, [r7, #4]
800844a: 697a ldr r2, [r7, #20]
800844c: 621a str r2, [r3, #32]
}
800844e: bf00 nop
8008450: 371c adds r7, #28
8008452: 46bd mov sp, r7
8008454: f85d 7b04 ldr.w r7, [sp], #4
8008458: 4770 bx lr
800845a: bf00 nop
800845c: 40012c00 .word 0x40012c00
8008460: 40013400 .word 0x40013400
8008464: 40015000 .word 0x40015000
8008468: 40014000 .word 0x40014000
800846c: 40014400 .word 0x40014400
8008470: 40014800 .word 0x40014800
08008474 <TIM_OC5_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8008474: b480 push {r7}
8008476: b087 sub sp, #28
8008478: af00 add r7, sp, #0
800847a: 6078 str r0, [r7, #4]
800847c: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
800847e: 687b ldr r3, [r7, #4]
8008480: 6a1b ldr r3, [r3, #32]
8008482: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC5E;
8008484: 687b ldr r3, [r7, #4]
8008486: 6a1b ldr r3, [r3, #32]
8008488: f423 3280 bic.w r2, r3, #65536 @ 0x10000
800848c: 687b ldr r3, [r7, #4]
800848e: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8008490: 687b ldr r3, [r7, #4]
8008492: 685b ldr r3, [r3, #4]
8008494: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
8008496: 687b ldr r3, [r7, #4]
8008498: 6d1b ldr r3, [r3, #80] @ 0x50
800849a: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC5M);
800849c: 68fb ldr r3, [r7, #12]
800849e: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80084a2: f023 0370 bic.w r3, r3, #112 @ 0x70
80084a6: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= OC_Config->OCMode;
80084a8: 683b ldr r3, [r7, #0]
80084aa: 681b ldr r3, [r3, #0]
80084ac: 68fa ldr r2, [r7, #12]
80084ae: 4313 orrs r3, r2
80084b0: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= ~TIM_CCER_CC5P;
80084b2: 693b ldr r3, [r7, #16]
80084b4: f423 3300 bic.w r3, r3, #131072 @ 0x20000
80084b8: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 16U);
80084ba: 683b ldr r3, [r7, #0]
80084bc: 689b ldr r3, [r3, #8]
80084be: 041b lsls r3, r3, #16
80084c0: 693a ldr r2, [r7, #16]
80084c2: 4313 orrs r3, r2
80084c4: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
80084c6: 687b ldr r3, [r7, #4]
80084c8: 4a19 ldr r2, [pc, #100] @ (8008530 <TIM_OC5_SetConfig+0xbc>)
80084ca: 4293 cmp r3, r2
80084cc: d013 beq.n 80084f6 <TIM_OC5_SetConfig+0x82>
80084ce: 687b ldr r3, [r7, #4]
80084d0: 4a18 ldr r2, [pc, #96] @ (8008534 <TIM_OC5_SetConfig+0xc0>)
80084d2: 4293 cmp r3, r2
80084d4: d00f beq.n 80084f6 <TIM_OC5_SetConfig+0x82>
80084d6: 687b ldr r3, [r7, #4]
80084d8: 4a17 ldr r2, [pc, #92] @ (8008538 <TIM_OC5_SetConfig+0xc4>)
80084da: 4293 cmp r3, r2
80084dc: d00b beq.n 80084f6 <TIM_OC5_SetConfig+0x82>
80084de: 687b ldr r3, [r7, #4]
80084e0: 4a16 ldr r2, [pc, #88] @ (800853c <TIM_OC5_SetConfig+0xc8>)
80084e2: 4293 cmp r3, r2
80084e4: d007 beq.n 80084f6 <TIM_OC5_SetConfig+0x82>
80084e6: 687b ldr r3, [r7, #4]
80084e8: 4a15 ldr r2, [pc, #84] @ (8008540 <TIM_OC5_SetConfig+0xcc>)
80084ea: 4293 cmp r3, r2
80084ec: d003 beq.n 80084f6 <TIM_OC5_SetConfig+0x82>
80084ee: 687b ldr r3, [r7, #4]
80084f0: 4a14 ldr r2, [pc, #80] @ (8008544 <TIM_OC5_SetConfig+0xd0>)
80084f2: 4293 cmp r3, r2
80084f4: d109 bne.n 800850a <TIM_OC5_SetConfig+0x96>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS5;
80084f6: 697b ldr r3, [r7, #20]
80084f8: f423 3380 bic.w r3, r3, #65536 @ 0x10000
80084fc: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 8U);
80084fe: 683b ldr r3, [r7, #0]
8008500: 695b ldr r3, [r3, #20]
8008502: 021b lsls r3, r3, #8
8008504: 697a ldr r2, [r7, #20]
8008506: 4313 orrs r3, r2
8008508: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
800850a: 687b ldr r3, [r7, #4]
800850c: 697a ldr r2, [r7, #20]
800850e: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
8008510: 687b ldr r3, [r7, #4]
8008512: 68fa ldr r2, [r7, #12]
8008514: 651a str r2, [r3, #80] @ 0x50
/* Set the Capture Compare Register value */
TIMx->CCR5 = OC_Config->Pulse;
8008516: 683b ldr r3, [r7, #0]
8008518: 685a ldr r2, [r3, #4]
800851a: 687b ldr r3, [r7, #4]
800851c: 649a str r2, [r3, #72] @ 0x48
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
800851e: 687b ldr r3, [r7, #4]
8008520: 693a ldr r2, [r7, #16]
8008522: 621a str r2, [r3, #32]
}
8008524: bf00 nop
8008526: 371c adds r7, #28
8008528: 46bd mov sp, r7
800852a: f85d 7b04 ldr.w r7, [sp], #4
800852e: 4770 bx lr
8008530: 40012c00 .word 0x40012c00
8008534: 40013400 .word 0x40013400
8008538: 40014000 .word 0x40014000
800853c: 40014400 .word 0x40014400
8008540: 40014800 .word 0x40014800
8008544: 40015000 .word 0x40015000
08008548 <TIM_OC6_SetConfig>:
* @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
const TIM_OC_InitTypeDef *OC_Config)
{
8008548: b480 push {r7}
800854a: b087 sub sp, #28
800854c: af00 add r7, sp, #0
800854e: 6078 str r0, [r7, #4]
8008550: 6039 str r1, [r7, #0]
uint32_t tmpccmrx;
uint32_t tmpccer;
uint32_t tmpcr2;
/* Get the TIMx CCER register value */
tmpccer = TIMx->CCER;
8008552: 687b ldr r3, [r7, #4]
8008554: 6a1b ldr r3, [r3, #32]
8008556: 613b str r3, [r7, #16]
/* Disable the output: Reset the CCxE Bit */
TIMx->CCER &= ~TIM_CCER_CC6E;
8008558: 687b ldr r3, [r7, #4]
800855a: 6a1b ldr r3, [r3, #32]
800855c: f423 1280 bic.w r2, r3, #1048576 @ 0x100000
8008560: 687b ldr r3, [r7, #4]
8008562: 621a str r2, [r3, #32]
/* Get the TIMx CR2 register value */
tmpcr2 = TIMx->CR2;
8008564: 687b ldr r3, [r7, #4]
8008566: 685b ldr r3, [r3, #4]
8008568: 617b str r3, [r7, #20]
/* Get the TIMx CCMR1 register value */
tmpccmrx = TIMx->CCMR3;
800856a: 687b ldr r3, [r7, #4]
800856c: 6d1b ldr r3, [r3, #80] @ 0x50
800856e: 60fb str r3, [r7, #12]
/* Reset the Output Compare Mode Bits */
tmpccmrx &= ~(TIM_CCMR3_OC6M);
8008570: 68fb ldr r3, [r7, #12]
8008572: f023 7380 bic.w r3, r3, #16777216 @ 0x1000000
8008576: f423 43e0 bic.w r3, r3, #28672 @ 0x7000
800857a: 60fb str r3, [r7, #12]
/* Select the Output Compare Mode */
tmpccmrx |= (OC_Config->OCMode << 8U);
800857c: 683b ldr r3, [r7, #0]
800857e: 681b ldr r3, [r3, #0]
8008580: 021b lsls r3, r3, #8
8008582: 68fa ldr r2, [r7, #12]
8008584: 4313 orrs r3, r2
8008586: 60fb str r3, [r7, #12]
/* Reset the Output Polarity level */
tmpccer &= (uint32_t)~TIM_CCER_CC6P;
8008588: 693b ldr r3, [r7, #16]
800858a: f423 1300 bic.w r3, r3, #2097152 @ 0x200000
800858e: 613b str r3, [r7, #16]
/* Set the Output Compare Polarity */
tmpccer |= (OC_Config->OCPolarity << 20U);
8008590: 683b ldr r3, [r7, #0]
8008592: 689b ldr r3, [r3, #8]
8008594: 051b lsls r3, r3, #20
8008596: 693a ldr r2, [r7, #16]
8008598: 4313 orrs r3, r2
800859a: 613b str r3, [r7, #16]
if (IS_TIM_BREAK_INSTANCE(TIMx))
800859c: 687b ldr r3, [r7, #4]
800859e: 4a1a ldr r2, [pc, #104] @ (8008608 <TIM_OC6_SetConfig+0xc0>)
80085a0: 4293 cmp r3, r2
80085a2: d013 beq.n 80085cc <TIM_OC6_SetConfig+0x84>
80085a4: 687b ldr r3, [r7, #4]
80085a6: 4a19 ldr r2, [pc, #100] @ (800860c <TIM_OC6_SetConfig+0xc4>)
80085a8: 4293 cmp r3, r2
80085aa: d00f beq.n 80085cc <TIM_OC6_SetConfig+0x84>
80085ac: 687b ldr r3, [r7, #4]
80085ae: 4a18 ldr r2, [pc, #96] @ (8008610 <TIM_OC6_SetConfig+0xc8>)
80085b0: 4293 cmp r3, r2
80085b2: d00b beq.n 80085cc <TIM_OC6_SetConfig+0x84>
80085b4: 687b ldr r3, [r7, #4]
80085b6: 4a17 ldr r2, [pc, #92] @ (8008614 <TIM_OC6_SetConfig+0xcc>)
80085b8: 4293 cmp r3, r2
80085ba: d007 beq.n 80085cc <TIM_OC6_SetConfig+0x84>
80085bc: 687b ldr r3, [r7, #4]
80085be: 4a16 ldr r2, [pc, #88] @ (8008618 <TIM_OC6_SetConfig+0xd0>)
80085c0: 4293 cmp r3, r2
80085c2: d003 beq.n 80085cc <TIM_OC6_SetConfig+0x84>
80085c4: 687b ldr r3, [r7, #4]
80085c6: 4a15 ldr r2, [pc, #84] @ (800861c <TIM_OC6_SetConfig+0xd4>)
80085c8: 4293 cmp r3, r2
80085ca: d109 bne.n 80085e0 <TIM_OC6_SetConfig+0x98>
{
/* Reset the Output Compare IDLE State */
tmpcr2 &= ~TIM_CR2_OIS6;
80085cc: 697b ldr r3, [r7, #20]
80085ce: f423 2380 bic.w r3, r3, #262144 @ 0x40000
80085d2: 617b str r3, [r7, #20]
/* Set the Output Idle state */
tmpcr2 |= (OC_Config->OCIdleState << 10U);
80085d4: 683b ldr r3, [r7, #0]
80085d6: 695b ldr r3, [r3, #20]
80085d8: 029b lsls r3, r3, #10
80085da: 697a ldr r2, [r7, #20]
80085dc: 4313 orrs r3, r2
80085de: 617b str r3, [r7, #20]
}
/* Write to TIMx CR2 */
TIMx->CR2 = tmpcr2;
80085e0: 687b ldr r3, [r7, #4]
80085e2: 697a ldr r2, [r7, #20]
80085e4: 605a str r2, [r3, #4]
/* Write to TIMx CCMR3 */
TIMx->CCMR3 = tmpccmrx;
80085e6: 687b ldr r3, [r7, #4]
80085e8: 68fa ldr r2, [r7, #12]
80085ea: 651a str r2, [r3, #80] @ 0x50
/* Set the Capture Compare Register value */
TIMx->CCR6 = OC_Config->Pulse;
80085ec: 683b ldr r3, [r7, #0]
80085ee: 685a ldr r2, [r3, #4]
80085f0: 687b ldr r3, [r7, #4]
80085f2: 64da str r2, [r3, #76] @ 0x4c
/* Write to TIMx CCER */
TIMx->CCER = tmpccer;
80085f4: 687b ldr r3, [r7, #4]
80085f6: 693a ldr r2, [r7, #16]
80085f8: 621a str r2, [r3, #32]
}
80085fa: bf00 nop
80085fc: 371c adds r7, #28
80085fe: 46bd mov sp, r7
8008600: f85d 7b04 ldr.w r7, [sp], #4
8008604: 4770 bx lr
8008606: bf00 nop
8008608: 40012c00 .word 0x40012c00
800860c: 40013400 .word 0x40013400
8008610: 40014000 .word 0x40014000
8008614: 40014400 .word 0x40014400
8008618: 40014800 .word 0x40014800
800861c: 40015000 .word 0x40015000
08008620 <TIM_TI1_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
8008620: b480 push {r7}
8008622: b087 sub sp, #28
8008624: af00 add r7, sp, #0
8008626: 60f8 str r0, [r7, #12]
8008628: 60b9 str r1, [r7, #8]
800862a: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 1: Reset the CC1E Bit */
tmpccer = TIMx->CCER;
800862c: 68fb ldr r3, [r7, #12]
800862e: 6a1b ldr r3, [r3, #32]
8008630: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC1E;
8008632: 68fb ldr r3, [r7, #12]
8008634: 6a1b ldr r3, [r3, #32]
8008636: f023 0201 bic.w r2, r3, #1
800863a: 68fb ldr r3, [r7, #12]
800863c: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800863e: 68fb ldr r3, [r7, #12]
8008640: 699b ldr r3, [r3, #24]
8008642: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC1F;
8008644: 693b ldr r3, [r7, #16]
8008646: f023 03f0 bic.w r3, r3, #240 @ 0xf0
800864a: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 4U);
800864c: 687b ldr r3, [r7, #4]
800864e: 011b lsls r3, r3, #4
8008650: 693a ldr r2, [r7, #16]
8008652: 4313 orrs r3, r2
8008654: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC1E Bit */
tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
8008656: 697b ldr r3, [r7, #20]
8008658: f023 030a bic.w r3, r3, #10
800865c: 617b str r3, [r7, #20]
tmpccer |= TIM_ICPolarity;
800865e: 697a ldr r2, [r7, #20]
8008660: 68bb ldr r3, [r7, #8]
8008662: 4313 orrs r3, r2
8008664: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1;
8008666: 68fb ldr r3, [r7, #12]
8008668: 693a ldr r2, [r7, #16]
800866a: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
800866c: 68fb ldr r3, [r7, #12]
800866e: 697a ldr r2, [r7, #20]
8008670: 621a str r2, [r3, #32]
}
8008672: bf00 nop
8008674: 371c adds r7, #28
8008676: 46bd mov sp, r7
8008678: f85d 7b04 ldr.w r7, [sp], #4
800867c: 4770 bx lr
0800867e <TIM_TI2_ConfigInputStage>:
* @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
{
800867e: b480 push {r7}
8008680: b087 sub sp, #28
8008682: af00 add r7, sp, #0
8008684: 60f8 str r0, [r7, #12]
8008686: 60b9 str r1, [r7, #8]
8008688: 607a str r2, [r7, #4]
uint32_t tmpccmr1;
uint32_t tmpccer;
/* Disable the Channel 2: Reset the CC2E Bit */
tmpccer = TIMx->CCER;
800868a: 68fb ldr r3, [r7, #12]
800868c: 6a1b ldr r3, [r3, #32]
800868e: 617b str r3, [r7, #20]
TIMx->CCER &= ~TIM_CCER_CC2E;
8008690: 68fb ldr r3, [r7, #12]
8008692: 6a1b ldr r3, [r3, #32]
8008694: f023 0210 bic.w r2, r3, #16
8008698: 68fb ldr r3, [r7, #12]
800869a: 621a str r2, [r3, #32]
tmpccmr1 = TIMx->CCMR1;
800869c: 68fb ldr r3, [r7, #12]
800869e: 699b ldr r3, [r3, #24]
80086a0: 613b str r3, [r7, #16]
/* Set the filter */
tmpccmr1 &= ~TIM_CCMR1_IC2F;
80086a2: 693b ldr r3, [r7, #16]
80086a4: f423 4370 bic.w r3, r3, #61440 @ 0xf000
80086a8: 613b str r3, [r7, #16]
tmpccmr1 |= (TIM_ICFilter << 12U);
80086aa: 687b ldr r3, [r7, #4]
80086ac: 031b lsls r3, r3, #12
80086ae: 693a ldr r2, [r7, #16]
80086b0: 4313 orrs r3, r2
80086b2: 613b str r3, [r7, #16]
/* Select the Polarity and set the CC2E Bit */
tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
80086b4: 697b ldr r3, [r7, #20]
80086b6: f023 03a0 bic.w r3, r3, #160 @ 0xa0
80086ba: 617b str r3, [r7, #20]
tmpccer |= (TIM_ICPolarity << 4U);
80086bc: 68bb ldr r3, [r7, #8]
80086be: 011b lsls r3, r3, #4
80086c0: 697a ldr r2, [r7, #20]
80086c2: 4313 orrs r3, r2
80086c4: 617b str r3, [r7, #20]
/* Write to TIMx CCMR1 and CCER registers */
TIMx->CCMR1 = tmpccmr1 ;
80086c6: 68fb ldr r3, [r7, #12]
80086c8: 693a ldr r2, [r7, #16]
80086ca: 619a str r2, [r3, #24]
TIMx->CCER = tmpccer;
80086cc: 68fb ldr r3, [r7, #12]
80086ce: 697a ldr r2, [r7, #20]
80086d0: 621a str r2, [r3, #32]
}
80086d2: bf00 nop
80086d4: 371c adds r7, #28
80086d6: 46bd mov sp, r7
80086d8: f85d 7b04 ldr.w r7, [sp], #4
80086dc: 4770 bx lr
080086de <TIM_ITRx_SetConfig>:
* (*) Value not defined in all devices.
*
* @retval None
*/
static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
{
80086de: b480 push {r7}
80086e0: b085 sub sp, #20
80086e2: af00 add r7, sp, #0
80086e4: 6078 str r0, [r7, #4]
80086e6: 6039 str r1, [r7, #0]
uint32_t tmpsmcr;
/* Get the TIMx SMCR register value */
tmpsmcr = TIMx->SMCR;
80086e8: 687b ldr r3, [r7, #4]
80086ea: 689b ldr r3, [r3, #8]
80086ec: 60fb str r3, [r7, #12]
/* Reset the TS Bits */
tmpsmcr &= ~TIM_SMCR_TS;
80086ee: 68fb ldr r3, [r7, #12]
80086f0: f423 1340 bic.w r3, r3, #3145728 @ 0x300000
80086f4: f023 0370 bic.w r3, r3, #112 @ 0x70
80086f8: 60fb str r3, [r7, #12]
/* Set the Input Trigger source and the slave mode*/
tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
80086fa: 683a ldr r2, [r7, #0]
80086fc: 68fb ldr r3, [r7, #12]
80086fe: 4313 orrs r3, r2
8008700: f043 0307 orr.w r3, r3, #7
8008704: 60fb str r3, [r7, #12]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8008706: 687b ldr r3, [r7, #4]
8008708: 68fa ldr r2, [r7, #12]
800870a: 609a str r2, [r3, #8]
}
800870c: bf00 nop
800870e: 3714 adds r7, #20
8008710: 46bd mov sp, r7
8008712: f85d 7b04 ldr.w r7, [sp], #4
8008716: 4770 bx lr
08008718 <TIM_ETR_SetConfig>:
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
{
8008718: b480 push {r7}
800871a: b087 sub sp, #28
800871c: af00 add r7, sp, #0
800871e: 60f8 str r0, [r7, #12]
8008720: 60b9 str r1, [r7, #8]
8008722: 607a str r2, [r7, #4]
8008724: 603b str r3, [r7, #0]
uint32_t tmpsmcr;
tmpsmcr = TIMx->SMCR;
8008726: 68fb ldr r3, [r7, #12]
8008728: 689b ldr r3, [r3, #8]
800872a: 617b str r3, [r7, #20]
/* Reset the ETR Bits */
tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
800872c: 697b ldr r3, [r7, #20]
800872e: f423 437f bic.w r3, r3, #65280 @ 0xff00
8008732: 617b str r3, [r7, #20]
/* Set the Prescaler, the Filter value and the Polarity */
tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
8008734: 683b ldr r3, [r7, #0]
8008736: 021a lsls r2, r3, #8
8008738: 687b ldr r3, [r7, #4]
800873a: 431a orrs r2, r3
800873c: 68bb ldr r3, [r7, #8]
800873e: 4313 orrs r3, r2
8008740: 697a ldr r2, [r7, #20]
8008742: 4313 orrs r3, r2
8008744: 617b str r3, [r7, #20]
/* Write to TIMx SMCR */
TIMx->SMCR = tmpsmcr;
8008746: 68fb ldr r3, [r7, #12]
8008748: 697a ldr r2, [r7, #20]
800874a: 609a str r2, [r3, #8]
}
800874c: bf00 nop
800874e: 371c adds r7, #28
8008750: 46bd mov sp, r7
8008752: f85d 7b04 ldr.w r7, [sp], #4
8008756: 4770 bx lr
08008758 <TIM_CCxChannelCmd>:
* @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
* @retval None
*/
void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
{
8008758: b480 push {r7}
800875a: b087 sub sp, #28
800875c: af00 add r7, sp, #0
800875e: 60f8 str r0, [r7, #12]
8008760: 60b9 str r1, [r7, #8]
8008762: 607a str r2, [r7, #4]
/* Check the parameters */
assert_param(IS_TIM_CC1_INSTANCE(TIMx));
assert_param(IS_TIM_CHANNELS(Channel));
tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
8008764: 68bb ldr r3, [r7, #8]
8008766: f003 031f and.w r3, r3, #31
800876a: 2201 movs r2, #1
800876c: fa02 f303 lsl.w r3, r2, r3
8008770: 617b str r3, [r7, #20]
/* Reset the CCxE Bit */
TIMx->CCER &= ~tmp;
8008772: 68fb ldr r3, [r7, #12]
8008774: 6a1a ldr r2, [r3, #32]
8008776: 697b ldr r3, [r7, #20]
8008778: 43db mvns r3, r3
800877a: 401a ands r2, r3
800877c: 68fb ldr r3, [r7, #12]
800877e: 621a str r2, [r3, #32]
/* Set or reset the CCxE Bit */
TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
8008780: 68fb ldr r3, [r7, #12]
8008782: 6a1a ldr r2, [r3, #32]
8008784: 68bb ldr r3, [r7, #8]
8008786: f003 031f and.w r3, r3, #31
800878a: 6879 ldr r1, [r7, #4]
800878c: fa01 f303 lsl.w r3, r1, r3
8008790: 431a orrs r2, r3
8008792: 68fb ldr r3, [r7, #12]
8008794: 621a str r2, [r3, #32]
}
8008796: bf00 nop
8008798: 371c adds r7, #28
800879a: 46bd mov sp, r7
800879c: f85d 7b04 ldr.w r7, [sp], #4
80087a0: 4770 bx lr
...
080087a4 <HAL_TIMEx_MasterConfigSynchronization>:
* mode.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
const TIM_MasterConfigTypeDef *sMasterConfig)
{
80087a4: b480 push {r7}
80087a6: b085 sub sp, #20
80087a8: af00 add r7, sp, #0
80087aa: 6078 str r0, [r7, #4]
80087ac: 6039 str r1, [r7, #0]
assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
/* Check input state */
__HAL_LOCK(htim);
80087ae: 687b ldr r3, [r7, #4]
80087b0: f893 303c ldrb.w r3, [r3, #60] @ 0x3c
80087b4: 2b01 cmp r3, #1
80087b6: d101 bne.n 80087bc <HAL_TIMEx_MasterConfigSynchronization+0x18>
80087b8: 2302 movs r3, #2
80087ba: e074 b.n 80088a6 <HAL_TIMEx_MasterConfigSynchronization+0x102>
80087bc: 687b ldr r3, [r7, #4]
80087be: 2201 movs r2, #1
80087c0: f883 203c strb.w r2, [r3, #60] @ 0x3c
/* Change the handler state */
htim->State = HAL_TIM_STATE_BUSY;
80087c4: 687b ldr r3, [r7, #4]
80087c6: 2202 movs r2, #2
80087c8: f883 203d strb.w r2, [r3, #61] @ 0x3d
/* Get the TIMx CR2 register value */
tmpcr2 = htim->Instance->CR2;
80087cc: 687b ldr r3, [r7, #4]
80087ce: 681b ldr r3, [r3, #0]
80087d0: 685b ldr r3, [r3, #4]
80087d2: 60fb str r3, [r7, #12]
/* Get the TIMx SMCR register value */
tmpsmcr = htim->Instance->SMCR;
80087d4: 687b ldr r3, [r7, #4]
80087d6: 681b ldr r3, [r3, #0]
80087d8: 689b ldr r3, [r3, #8]
80087da: 60bb str r3, [r7, #8]
/* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
80087dc: 687b ldr r3, [r7, #4]
80087de: 681b ldr r3, [r3, #0]
80087e0: 4a34 ldr r2, [pc, #208] @ (80088b4 <HAL_TIMEx_MasterConfigSynchronization+0x110>)
80087e2: 4293 cmp r3, r2
80087e4: d009 beq.n 80087fa <HAL_TIMEx_MasterConfigSynchronization+0x56>
80087e6: 687b ldr r3, [r7, #4]
80087e8: 681b ldr r3, [r3, #0]
80087ea: 4a33 ldr r2, [pc, #204] @ (80088b8 <HAL_TIMEx_MasterConfigSynchronization+0x114>)
80087ec: 4293 cmp r3, r2
80087ee: d004 beq.n 80087fa <HAL_TIMEx_MasterConfigSynchronization+0x56>
80087f0: 687b ldr r3, [r7, #4]
80087f2: 681b ldr r3, [r3, #0]
80087f4: 4a31 ldr r2, [pc, #196] @ (80088bc <HAL_TIMEx_MasterConfigSynchronization+0x118>)
80087f6: 4293 cmp r3, r2
80087f8: d108 bne.n 800880c <HAL_TIMEx_MasterConfigSynchronization+0x68>
{
/* Check the parameters */
assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
/* Clear the MMS2 bits */
tmpcr2 &= ~TIM_CR2_MMS2;
80087fa: 68fb ldr r3, [r7, #12]
80087fc: f423 0370 bic.w r3, r3, #15728640 @ 0xf00000
8008800: 60fb str r3, [r7, #12]
/* Select the TRGO2 source*/
tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
8008802: 683b ldr r3, [r7, #0]
8008804: 685b ldr r3, [r3, #4]
8008806: 68fa ldr r2, [r7, #12]
8008808: 4313 orrs r3, r2
800880a: 60fb str r3, [r7, #12]
}
/* Reset the MMS Bits */
tmpcr2 &= ~TIM_CR2_MMS;
800880c: 68fb ldr r3, [r7, #12]
800880e: f023 7300 bic.w r3, r3, #33554432 @ 0x2000000
8008812: f023 0370 bic.w r3, r3, #112 @ 0x70
8008816: 60fb str r3, [r7, #12]
/* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger;
8008818: 683b ldr r3, [r7, #0]
800881a: 681b ldr r3, [r3, #0]
800881c: 68fa ldr r2, [r7, #12]
800881e: 4313 orrs r3, r2
8008820: 60fb str r3, [r7, #12]
/* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2;
8008822: 687b ldr r3, [r7, #4]
8008824: 681b ldr r3, [r3, #0]
8008826: 68fa ldr r2, [r7, #12]
8008828: 605a str r2, [r3, #4]
if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
800882a: 687b ldr r3, [r7, #4]
800882c: 681b ldr r3, [r3, #0]
800882e: 4a21 ldr r2, [pc, #132] @ (80088b4 <HAL_TIMEx_MasterConfigSynchronization+0x110>)
8008830: 4293 cmp r3, r2
8008832: d022 beq.n 800887a <HAL_TIMEx_MasterConfigSynchronization+0xd6>
8008834: 687b ldr r3, [r7, #4]
8008836: 681b ldr r3, [r3, #0]
8008838: f1b3 4f80 cmp.w r3, #1073741824 @ 0x40000000
800883c: d01d beq.n 800887a <HAL_TIMEx_MasterConfigSynchronization+0xd6>
800883e: 687b ldr r3, [r7, #4]
8008840: 681b ldr r3, [r3, #0]
8008842: 4a1f ldr r2, [pc, #124] @ (80088c0 <HAL_TIMEx_MasterConfigSynchronization+0x11c>)
8008844: 4293 cmp r3, r2
8008846: d018 beq.n 800887a <HAL_TIMEx_MasterConfigSynchronization+0xd6>
8008848: 687b ldr r3, [r7, #4]
800884a: 681b ldr r3, [r3, #0]
800884c: 4a1d ldr r2, [pc, #116] @ (80088c4 <HAL_TIMEx_MasterConfigSynchronization+0x120>)
800884e: 4293 cmp r3, r2
8008850: d013 beq.n 800887a <HAL_TIMEx_MasterConfigSynchronization+0xd6>
8008852: 687b ldr r3, [r7, #4]
8008854: 681b ldr r3, [r3, #0]
8008856: 4a1c ldr r2, [pc, #112] @ (80088c8 <HAL_TIMEx_MasterConfigSynchronization+0x124>)
8008858: 4293 cmp r3, r2
800885a: d00e beq.n 800887a <HAL_TIMEx_MasterConfigSynchronization+0xd6>
800885c: 687b ldr r3, [r7, #4]
800885e: 681b ldr r3, [r3, #0]
8008860: 4a15 ldr r2, [pc, #84] @ (80088b8 <HAL_TIMEx_MasterConfigSynchronization+0x114>)
8008862: 4293 cmp r3, r2
8008864: d009 beq.n 800887a <HAL_TIMEx_MasterConfigSynchronization+0xd6>
8008866: 687b ldr r3, [r7, #4]
8008868: 681b ldr r3, [r3, #0]
800886a: 4a18 ldr r2, [pc, #96] @ (80088cc <HAL_TIMEx_MasterConfigSynchronization+0x128>)
800886c: 4293 cmp r3, r2
800886e: d004 beq.n 800887a <HAL_TIMEx_MasterConfigSynchronization+0xd6>
8008870: 687b ldr r3, [r7, #4]
8008872: 681b ldr r3, [r3, #0]
8008874: 4a11 ldr r2, [pc, #68] @ (80088bc <HAL_TIMEx_MasterConfigSynchronization+0x118>)
8008876: 4293 cmp r3, r2
8008878: d10c bne.n 8008894 <HAL_TIMEx_MasterConfigSynchronization+0xf0>
{
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
800887a: 68bb ldr r3, [r7, #8]
800887c: f023 0380 bic.w r3, r3, #128 @ 0x80
8008880: 60bb str r3, [r7, #8]
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
8008882: 683b ldr r3, [r7, #0]
8008884: 689b ldr r3, [r3, #8]
8008886: 68ba ldr r2, [r7, #8]
8008888: 4313 orrs r3, r2
800888a: 60bb str r3, [r7, #8]
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
800888c: 687b ldr r3, [r7, #4]
800888e: 681b ldr r3, [r3, #0]
8008890: 68ba ldr r2, [r7, #8]
8008892: 609a str r2, [r3, #8]
}
/* Change the htim state */
htim->State = HAL_TIM_STATE_READY;
8008894: 687b ldr r3, [r7, #4]
8008896: 2201 movs r2, #1
8008898: f883 203d strb.w r2, [r3, #61] @ 0x3d
__HAL_UNLOCK(htim);
800889c: 687b ldr r3, [r7, #4]
800889e: 2200 movs r2, #0
80088a0: f883 203c strb.w r2, [r3, #60] @ 0x3c
return HAL_OK;
80088a4: 2300 movs r3, #0
}
80088a6: 4618 mov r0, r3
80088a8: 3714 adds r7, #20
80088aa: 46bd mov sp, r7
80088ac: f85d 7b04 ldr.w r7, [sp], #4
80088b0: 4770 bx lr
80088b2: bf00 nop
80088b4: 40012c00 .word 0x40012c00
80088b8: 40013400 .word 0x40013400
80088bc: 40015000 .word 0x40015000
80088c0: 40000400 .word 0x40000400
80088c4: 40000800 .word 0x40000800
80088c8: 40000c00 .word 0x40000c00
80088cc: 40014000 .word 0x40014000
080088d0 <HAL_TIMEx_CommutCallback>:
* @brief Commutation callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
{
80088d0: b480 push {r7}
80088d2: b083 sub sp, #12
80088d4: af00 add r7, sp, #0
80088d6: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_CommutCallback could be implemented in the user file
*/
}
80088d8: bf00 nop
80088da: 370c adds r7, #12
80088dc: 46bd mov sp, r7
80088de: f85d 7b04 ldr.w r7, [sp], #4
80088e2: 4770 bx lr
080088e4 <HAL_TIMEx_BreakCallback>:
* @brief Break detection callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
{
80088e4: b480 push {r7}
80088e6: b083 sub sp, #12
80088e8: af00 add r7, sp, #0
80088ea: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_BreakCallback could be implemented in the user file
*/
}
80088ec: bf00 nop
80088ee: 370c adds r7, #12
80088f0: 46bd mov sp, r7
80088f2: f85d 7b04 ldr.w r7, [sp], #4
80088f6: 4770 bx lr
080088f8 <HAL_TIMEx_Break2Callback>:
* @brief Break2 detection callback in non blocking mode
* @param htim: TIM handle
* @retval None
*/
__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
{
80088f8: b480 push {r7}
80088fa: b083 sub sp, #12
80088fc: af00 add r7, sp, #0
80088fe: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_TIMEx_Break2Callback could be implemented in the user file
*/
}
8008900: bf00 nop
8008902: 370c adds r7, #12
8008904: 46bd mov sp, r7
8008906: f85d 7b04 ldr.w r7, [sp], #4
800890a: 4770 bx lr
0800890c <HAL_TIMEx_EncoderIndexCallback>:
* @brief Encoder index callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim)
{
800890c: b480 push {r7}
800890e: b083 sub sp, #12
8008910: af00 add r7, sp, #0
8008912: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file
*/
}
8008914: bf00 nop
8008916: 370c adds r7, #12
8008918: 46bd mov sp, r7
800891a: f85d 7b04 ldr.w r7, [sp], #4
800891e: 4770 bx lr
08008920 <HAL_TIMEx_DirectionChangeCallback>:
* @brief Direction change callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim)
{
8008920: b480 push {r7}
8008922: b083 sub sp, #12
8008924: af00 add r7, sp, #0
8008926: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file
*/
}
8008928: bf00 nop
800892a: 370c adds r7, #12
800892c: 46bd mov sp, r7
800892e: f85d 7b04 ldr.w r7, [sp], #4
8008932: 4770 bx lr
08008934 <HAL_TIMEx_IndexErrorCallback>:
* @brief Index error callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim)
{
8008934: b480 push {r7}
8008936: b083 sub sp, #12
8008938: af00 add r7, sp, #0
800893a: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_IndexErrorCallback could be implemented in the user file
*/
}
800893c: bf00 nop
800893e: 370c adds r7, #12
8008940: 46bd mov sp, r7
8008942: f85d 7b04 ldr.w r7, [sp], #4
8008946: 4770 bx lr
08008948 <HAL_TIMEx_TransitionErrorCallback>:
* @brief Transition error callback in non-blocking mode
* @param htim TIM handle
* @retval None
*/
__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim)
{
8008948: b480 push {r7}
800894a: b083 sub sp, #12
800894c: af00 add r7, sp, #0
800894e: 6078 str r0, [r7, #4]
UNUSED(htim);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file
*/
}
8008950: bf00 nop
8008952: 370c adds r7, #12
8008954: 46bd mov sp, r7
8008956: f85d 7b04 ldr.w r7, [sp], #4
800895a: 4770 bx lr
0800895c <HAL_UART_Init>:
* parameters in the UART_InitTypeDef and initialize the associated handle.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
{
800895c: b580 push {r7, lr}
800895e: b082 sub sp, #8
8008960: af00 add r7, sp, #0
8008962: 6078 str r0, [r7, #4]
/* Check the UART handle allocation */
if (huart == NULL)
8008964: 687b ldr r3, [r7, #4]
8008966: 2b00 cmp r3, #0
8008968: d101 bne.n 800896e <HAL_UART_Init+0x12>
{
return HAL_ERROR;
800896a: 2301 movs r3, #1
800896c: e042 b.n 80089f4 <HAL_UART_Init+0x98>
{
/* Check the parameters */
assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance)));
}
if (huart->gState == HAL_UART_STATE_RESET)
800896e: 687b ldr r3, [r7, #4]
8008970: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8008974: 2b00 cmp r3, #0
8008976: d106 bne.n 8008986 <HAL_UART_Init+0x2a>
{
/* Allocate lock resource and initialize it */
huart->Lock = HAL_UNLOCKED;
8008978: 687b ldr r3, [r7, #4]
800897a: 2200 movs r2, #0
800897c: f883 2084 strb.w r2, [r3, #132] @ 0x84
/* Init the low level hardware */
huart->MspInitCallback(huart);
#else
/* Init the low level hardware : GPIO, CLOCK */
HAL_UART_MspInit(huart);
8008980: 6878 ldr r0, [r7, #4]
8008982: f7f8 ff45 bl 8001810 <HAL_UART_MspInit>
#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
}
huart->gState = HAL_UART_STATE_BUSY;
8008986: 687b ldr r3, [r7, #4]
8008988: 2224 movs r2, #36 @ 0x24
800898a: f8c3 2088 str.w r2, [r3, #136] @ 0x88
__HAL_UART_DISABLE(huart);
800898e: 687b ldr r3, [r7, #4]
8008990: 681b ldr r3, [r3, #0]
8008992: 681a ldr r2, [r3, #0]
8008994: 687b ldr r3, [r7, #4]
8008996: 681b ldr r3, [r3, #0]
8008998: f022 0201 bic.w r2, r2, #1
800899c: 601a str r2, [r3, #0]
/* Perform advanced settings configuration */
/* For some items, configuration requires to be done prior TE and RE bits are set */
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
800899e: 687b ldr r3, [r7, #4]
80089a0: 6a9b ldr r3, [r3, #40] @ 0x28
80089a2: 2b00 cmp r3, #0
80089a4: d002 beq.n 80089ac <HAL_UART_Init+0x50>
{
UART_AdvFeatureConfig(huart);
80089a6: 6878 ldr r0, [r7, #4]
80089a8: f000 fbb2 bl 8009110 <UART_AdvFeatureConfig>
}
/* Set the UART Communication parameters */
if (UART_SetConfig(huart) == HAL_ERROR)
80089ac: 6878 ldr r0, [r7, #4]
80089ae: f000 f8b3 bl 8008b18 <UART_SetConfig>
80089b2: 4603 mov r3, r0
80089b4: 2b01 cmp r3, #1
80089b6: d101 bne.n 80089bc <HAL_UART_Init+0x60>
{
return HAL_ERROR;
80089b8: 2301 movs r3, #1
80089ba: e01b b.n 80089f4 <HAL_UART_Init+0x98>
}
/* In asynchronous mode, the following bits must be kept cleared:
- LINEN and CLKEN bits in the USART_CR2 register,
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
80089bc: 687b ldr r3, [r7, #4]
80089be: 681b ldr r3, [r3, #0]
80089c0: 685a ldr r2, [r3, #4]
80089c2: 687b ldr r3, [r7, #4]
80089c4: 681b ldr r3, [r3, #0]
80089c6: f422 4290 bic.w r2, r2, #18432 @ 0x4800
80089ca: 605a str r2, [r3, #4]
CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
80089cc: 687b ldr r3, [r7, #4]
80089ce: 681b ldr r3, [r3, #0]
80089d0: 689a ldr r2, [r3, #8]
80089d2: 687b ldr r3, [r7, #4]
80089d4: 681b ldr r3, [r3, #0]
80089d6: f022 022a bic.w r2, r2, #42 @ 0x2a
80089da: 609a str r2, [r3, #8]
__HAL_UART_ENABLE(huart);
80089dc: 687b ldr r3, [r7, #4]
80089de: 681b ldr r3, [r3, #0]
80089e0: 681a ldr r2, [r3, #0]
80089e2: 687b ldr r3, [r7, #4]
80089e4: 681b ldr r3, [r3, #0]
80089e6: f042 0201 orr.w r2, r2, #1
80089ea: 601a str r2, [r3, #0]
/* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
return (UART_CheckIdleState(huart));
80089ec: 6878 ldr r0, [r7, #4]
80089ee: f000 fc31 bl 8009254 <UART_CheckIdleState>
80089f2: 4603 mov r3, r0
}
80089f4: 4618 mov r0, r3
80089f6: 3708 adds r7, #8
80089f8: 46bd mov sp, r7
80089fa: bd80 pop {r7, pc}
080089fc <HAL_UART_Transmit>:
* @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
{
80089fc: b580 push {r7, lr}
80089fe: b08a sub sp, #40 @ 0x28
8008a00: af02 add r7, sp, #8
8008a02: 60f8 str r0, [r7, #12]
8008a04: 60b9 str r1, [r7, #8]
8008a06: 603b str r3, [r7, #0]
8008a08: 4613 mov r3, r2
8008a0a: 80fb strh r3, [r7, #6]
const uint8_t *pdata8bits;
const uint16_t *pdata16bits;
uint32_t tickstart;
/* Check that a Tx process is not already ongoing */
if (huart->gState == HAL_UART_STATE_READY)
8008a0c: 68fb ldr r3, [r7, #12]
8008a0e: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8008a12: 2b20 cmp r3, #32
8008a14: d17b bne.n 8008b0e <HAL_UART_Transmit+0x112>
{
if ((pData == NULL) || (Size == 0U))
8008a16: 68bb ldr r3, [r7, #8]
8008a18: 2b00 cmp r3, #0
8008a1a: d002 beq.n 8008a22 <HAL_UART_Transmit+0x26>
8008a1c: 88fb ldrh r3, [r7, #6]
8008a1e: 2b00 cmp r3, #0
8008a20: d101 bne.n 8008a26 <HAL_UART_Transmit+0x2a>
{
return HAL_ERROR;
8008a22: 2301 movs r3, #1
8008a24: e074 b.n 8008b10 <HAL_UART_Transmit+0x114>
}
huart->ErrorCode = HAL_UART_ERROR_NONE;
8008a26: 68fb ldr r3, [r7, #12]
8008a28: 2200 movs r2, #0
8008a2a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
huart->gState = HAL_UART_STATE_BUSY_TX;
8008a2e: 68fb ldr r3, [r7, #12]
8008a30: 2221 movs r2, #33 @ 0x21
8008a32: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8008a36: f7f9 f859 bl 8001aec <HAL_GetTick>
8008a3a: 6178 str r0, [r7, #20]
huart->TxXferSize = Size;
8008a3c: 68fb ldr r3, [r7, #12]
8008a3e: 88fa ldrh r2, [r7, #6]
8008a40: f8a3 2054 strh.w r2, [r3, #84] @ 0x54
huart->TxXferCount = Size;
8008a44: 68fb ldr r3, [r7, #12]
8008a46: 88fa ldrh r2, [r7, #6]
8008a48: f8a3 2056 strh.w r2, [r3, #86] @ 0x56
/* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
8008a4c: 68fb ldr r3, [r7, #12]
8008a4e: 689b ldr r3, [r3, #8]
8008a50: f5b3 5f80 cmp.w r3, #4096 @ 0x1000
8008a54: d108 bne.n 8008a68 <HAL_UART_Transmit+0x6c>
8008a56: 68fb ldr r3, [r7, #12]
8008a58: 691b ldr r3, [r3, #16]
8008a5a: 2b00 cmp r3, #0
8008a5c: d104 bne.n 8008a68 <HAL_UART_Transmit+0x6c>
{
pdata8bits = NULL;
8008a5e: 2300 movs r3, #0
8008a60: 61fb str r3, [r7, #28]
pdata16bits = (const uint16_t *) pData;
8008a62: 68bb ldr r3, [r7, #8]
8008a64: 61bb str r3, [r7, #24]
8008a66: e003 b.n 8008a70 <HAL_UART_Transmit+0x74>
}
else
{
pdata8bits = pData;
8008a68: 68bb ldr r3, [r7, #8]
8008a6a: 61fb str r3, [r7, #28]
pdata16bits = NULL;
8008a6c: 2300 movs r3, #0
8008a6e: 61bb str r3, [r7, #24]
}
while (huart->TxXferCount > 0U)
8008a70: e030 b.n 8008ad4 <HAL_UART_Transmit+0xd8>
{
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
8008a72: 683b ldr r3, [r7, #0]
8008a74: 9300 str r3, [sp, #0]
8008a76: 697b ldr r3, [r7, #20]
8008a78: 2200 movs r2, #0
8008a7a: 2180 movs r1, #128 @ 0x80
8008a7c: 68f8 ldr r0, [r7, #12]
8008a7e: f000 fc93 bl 80093a8 <UART_WaitOnFlagUntilTimeout>
8008a82: 4603 mov r3, r0
8008a84: 2b00 cmp r3, #0
8008a86: d005 beq.n 8008a94 <HAL_UART_Transmit+0x98>
{
huart->gState = HAL_UART_STATE_READY;
8008a88: 68fb ldr r3, [r7, #12]
8008a8a: 2220 movs r2, #32
8008a8c: f8c3 2088 str.w r2, [r3, #136] @ 0x88
return HAL_TIMEOUT;
8008a90: 2303 movs r3, #3
8008a92: e03d b.n 8008b10 <HAL_UART_Transmit+0x114>
}
if (pdata8bits == NULL)
8008a94: 69fb ldr r3, [r7, #28]
8008a96: 2b00 cmp r3, #0
8008a98: d10b bne.n 8008ab2 <HAL_UART_Transmit+0xb6>
{
huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
8008a9a: 69bb ldr r3, [r7, #24]
8008a9c: 881b ldrh r3, [r3, #0]
8008a9e: 461a mov r2, r3
8008aa0: 68fb ldr r3, [r7, #12]
8008aa2: 681b ldr r3, [r3, #0]
8008aa4: f3c2 0208 ubfx r2, r2, #0, #9
8008aa8: 629a str r2, [r3, #40] @ 0x28
pdata16bits++;
8008aaa: 69bb ldr r3, [r7, #24]
8008aac: 3302 adds r3, #2
8008aae: 61bb str r3, [r7, #24]
8008ab0: e007 b.n 8008ac2 <HAL_UART_Transmit+0xc6>
}
else
{
huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
8008ab2: 69fb ldr r3, [r7, #28]
8008ab4: 781a ldrb r2, [r3, #0]
8008ab6: 68fb ldr r3, [r7, #12]
8008ab8: 681b ldr r3, [r3, #0]
8008aba: 629a str r2, [r3, #40] @ 0x28
pdata8bits++;
8008abc: 69fb ldr r3, [r7, #28]
8008abe: 3301 adds r3, #1
8008ac0: 61fb str r3, [r7, #28]
}
huart->TxXferCount--;
8008ac2: 68fb ldr r3, [r7, #12]
8008ac4: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56
8008ac8: b29b uxth r3, r3
8008aca: 3b01 subs r3, #1
8008acc: b29a uxth r2, r3
8008ace: 68fb ldr r3, [r7, #12]
8008ad0: f8a3 2056 strh.w r2, [r3, #86] @ 0x56
while (huart->TxXferCount > 0U)
8008ad4: 68fb ldr r3, [r7, #12]
8008ad6: f8b3 3056 ldrh.w r3, [r3, #86] @ 0x56
8008ada: b29b uxth r3, r3
8008adc: 2b00 cmp r3, #0
8008ade: d1c8 bne.n 8008a72 <HAL_UART_Transmit+0x76>
}
if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
8008ae0: 683b ldr r3, [r7, #0]
8008ae2: 9300 str r3, [sp, #0]
8008ae4: 697b ldr r3, [r7, #20]
8008ae6: 2200 movs r2, #0
8008ae8: 2140 movs r1, #64 @ 0x40
8008aea: 68f8 ldr r0, [r7, #12]
8008aec: f000 fc5c bl 80093a8 <UART_WaitOnFlagUntilTimeout>
8008af0: 4603 mov r3, r0
8008af2: 2b00 cmp r3, #0
8008af4: d005 beq.n 8008b02 <HAL_UART_Transmit+0x106>
{
huart->gState = HAL_UART_STATE_READY;
8008af6: 68fb ldr r3, [r7, #12]
8008af8: 2220 movs r2, #32
8008afa: f8c3 2088 str.w r2, [r3, #136] @ 0x88
return HAL_TIMEOUT;
8008afe: 2303 movs r3, #3
8008b00: e006 b.n 8008b10 <HAL_UART_Transmit+0x114>
}
/* At end of Tx process, restore huart->gState to Ready */
huart->gState = HAL_UART_STATE_READY;
8008b02: 68fb ldr r3, [r7, #12]
8008b04: 2220 movs r2, #32
8008b06: f8c3 2088 str.w r2, [r3, #136] @ 0x88
return HAL_OK;
8008b0a: 2300 movs r3, #0
8008b0c: e000 b.n 8008b10 <HAL_UART_Transmit+0x114>
}
else
{
return HAL_BUSY;
8008b0e: 2302 movs r3, #2
}
}
8008b10: 4618 mov r0, r3
8008b12: 3720 adds r7, #32
8008b14: 46bd mov sp, r7
8008b16: bd80 pop {r7, pc}
08008b18 <UART_SetConfig>:
* @brief Configure the UART peripheral.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
{
8008b18: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr}
8008b1c: b08c sub sp, #48 @ 0x30
8008b1e: af00 add r7, sp, #0
8008b20: 6178 str r0, [r7, #20]
uint32_t tmpreg;
uint16_t brrtemp;
UART_ClockSourceTypeDef clocksource;
uint32_t usartdiv;
HAL_StatusTypeDef ret = HAL_OK;
8008b22: 2300 movs r3, #0
8008b24: f887 302a strb.w r3, [r7, #42] @ 0x2a
* the UART Word Length, Parity, Mode and oversampling:
* set the M bits according to huart->Init.WordLength value
* set PCE and PS bits according to huart->Init.Parity value
* set TE and RE bits according to huart->Init.Mode value
* set OVER8 bit according to huart->Init.OverSampling value */
tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
8008b28: 697b ldr r3, [r7, #20]
8008b2a: 689a ldr r2, [r3, #8]
8008b2c: 697b ldr r3, [r7, #20]
8008b2e: 691b ldr r3, [r3, #16]
8008b30: 431a orrs r2, r3
8008b32: 697b ldr r3, [r7, #20]
8008b34: 695b ldr r3, [r3, #20]
8008b36: 431a orrs r2, r3
8008b38: 697b ldr r3, [r7, #20]
8008b3a: 69db ldr r3, [r3, #28]
8008b3c: 4313 orrs r3, r2
8008b3e: 62fb str r3, [r7, #44] @ 0x2c
MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
8008b40: 697b ldr r3, [r7, #20]
8008b42: 681b ldr r3, [r3, #0]
8008b44: 681a ldr r2, [r3, #0]
8008b46: 4baa ldr r3, [pc, #680] @ (8008df0 <UART_SetConfig+0x2d8>)
8008b48: 4013 ands r3, r2
8008b4a: 697a ldr r2, [r7, #20]
8008b4c: 6812 ldr r2, [r2, #0]
8008b4e: 6af9 ldr r1, [r7, #44] @ 0x2c
8008b50: 430b orrs r3, r1
8008b52: 6013 str r3, [r2, #0]
/*-------------------------- USART CR2 Configuration -----------------------*/
/* Configure the UART Stop Bits: Set STOP[13:12] bits according
* to huart->Init.StopBits value */
MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
8008b54: 697b ldr r3, [r7, #20]
8008b56: 681b ldr r3, [r3, #0]
8008b58: 685b ldr r3, [r3, #4]
8008b5a: f423 5140 bic.w r1, r3, #12288 @ 0x3000
8008b5e: 697b ldr r3, [r7, #20]
8008b60: 68da ldr r2, [r3, #12]
8008b62: 697b ldr r3, [r7, #20]
8008b64: 681b ldr r3, [r3, #0]
8008b66: 430a orrs r2, r1
8008b68: 605a str r2, [r3, #4]
/* Configure
* - UART HardWare Flow Control: set CTSE and RTSE bits according
* to huart->Init.HwFlowCtl value
* - one-bit sampling method versus three samples' majority rule according
* to huart->Init.OneBitSampling (not applicable to LPUART) */
tmpreg = (uint32_t)huart->Init.HwFlowCtl;
8008b6a: 697b ldr r3, [r7, #20]
8008b6c: 699b ldr r3, [r3, #24]
8008b6e: 62fb str r3, [r7, #44] @ 0x2c
if (!(UART_INSTANCE_LOWPOWER(huart)))
8008b70: 697b ldr r3, [r7, #20]
8008b72: 681b ldr r3, [r3, #0]
8008b74: 4a9f ldr r2, [pc, #636] @ (8008df4 <UART_SetConfig+0x2dc>)
8008b76: 4293 cmp r3, r2
8008b78: d004 beq.n 8008b84 <UART_SetConfig+0x6c>
{
tmpreg |= huart->Init.OneBitSampling;
8008b7a: 697b ldr r3, [r7, #20]
8008b7c: 6a1b ldr r3, [r3, #32]
8008b7e: 6afa ldr r2, [r7, #44] @ 0x2c
8008b80: 4313 orrs r3, r2
8008b82: 62fb str r3, [r7, #44] @ 0x2c
}
MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
8008b84: 697b ldr r3, [r7, #20]
8008b86: 681b ldr r3, [r3, #0]
8008b88: 689b ldr r3, [r3, #8]
8008b8a: f023 436e bic.w r3, r3, #3992977408 @ 0xee000000
8008b8e: f423 6330 bic.w r3, r3, #2816 @ 0xb00
8008b92: 697a ldr r2, [r7, #20]
8008b94: 6812 ldr r2, [r2, #0]
8008b96: 6af9 ldr r1, [r7, #44] @ 0x2c
8008b98: 430b orrs r3, r1
8008b9a: 6093 str r3, [r2, #8]
/*-------------------------- USART PRESC Configuration -----------------------*/
/* Configure
* - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
8008b9c: 697b ldr r3, [r7, #20]
8008b9e: 681b ldr r3, [r3, #0]
8008ba0: 6adb ldr r3, [r3, #44] @ 0x2c
8008ba2: f023 010f bic.w r1, r3, #15
8008ba6: 697b ldr r3, [r7, #20]
8008ba8: 6a5a ldr r2, [r3, #36] @ 0x24
8008baa: 697b ldr r3, [r7, #20]
8008bac: 681b ldr r3, [r3, #0]
8008bae: 430a orrs r2, r1
8008bb0: 62da str r2, [r3, #44] @ 0x2c
/*-------------------------- USART BRR Configuration -----------------------*/
UART_GETCLOCKSOURCE(huart, clocksource);
8008bb2: 697b ldr r3, [r7, #20]
8008bb4: 681b ldr r3, [r3, #0]
8008bb6: 4a90 ldr r2, [pc, #576] @ (8008df8 <UART_SetConfig+0x2e0>)
8008bb8: 4293 cmp r3, r2
8008bba: d125 bne.n 8008c08 <UART_SetConfig+0xf0>
8008bbc: 4b8f ldr r3, [pc, #572] @ (8008dfc <UART_SetConfig+0x2e4>)
8008bbe: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8008bc2: f003 0303 and.w r3, r3, #3
8008bc6: 2b03 cmp r3, #3
8008bc8: d81a bhi.n 8008c00 <UART_SetConfig+0xe8>
8008bca: a201 add r2, pc, #4 @ (adr r2, 8008bd0 <UART_SetConfig+0xb8>)
8008bcc: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8008bd0: 08008be1 .word 0x08008be1
8008bd4: 08008bf1 .word 0x08008bf1
8008bd8: 08008be9 .word 0x08008be9
8008bdc: 08008bf9 .word 0x08008bf9
8008be0: 2301 movs r3, #1
8008be2: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008be6: e116 b.n 8008e16 <UART_SetConfig+0x2fe>
8008be8: 2302 movs r3, #2
8008bea: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008bee: e112 b.n 8008e16 <UART_SetConfig+0x2fe>
8008bf0: 2304 movs r3, #4
8008bf2: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008bf6: e10e b.n 8008e16 <UART_SetConfig+0x2fe>
8008bf8: 2308 movs r3, #8
8008bfa: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008bfe: e10a b.n 8008e16 <UART_SetConfig+0x2fe>
8008c00: 2310 movs r3, #16
8008c02: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008c06: e106 b.n 8008e16 <UART_SetConfig+0x2fe>
8008c08: 697b ldr r3, [r7, #20]
8008c0a: 681b ldr r3, [r3, #0]
8008c0c: 4a7c ldr r2, [pc, #496] @ (8008e00 <UART_SetConfig+0x2e8>)
8008c0e: 4293 cmp r3, r2
8008c10: d138 bne.n 8008c84 <UART_SetConfig+0x16c>
8008c12: 4b7a ldr r3, [pc, #488] @ (8008dfc <UART_SetConfig+0x2e4>)
8008c14: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8008c18: f003 030c and.w r3, r3, #12
8008c1c: 2b0c cmp r3, #12
8008c1e: d82d bhi.n 8008c7c <UART_SetConfig+0x164>
8008c20: a201 add r2, pc, #4 @ (adr r2, 8008c28 <UART_SetConfig+0x110>)
8008c22: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8008c26: bf00 nop
8008c28: 08008c5d .word 0x08008c5d
8008c2c: 08008c7d .word 0x08008c7d
8008c30: 08008c7d .word 0x08008c7d
8008c34: 08008c7d .word 0x08008c7d
8008c38: 08008c6d .word 0x08008c6d
8008c3c: 08008c7d .word 0x08008c7d
8008c40: 08008c7d .word 0x08008c7d
8008c44: 08008c7d .word 0x08008c7d
8008c48: 08008c65 .word 0x08008c65
8008c4c: 08008c7d .word 0x08008c7d
8008c50: 08008c7d .word 0x08008c7d
8008c54: 08008c7d .word 0x08008c7d
8008c58: 08008c75 .word 0x08008c75
8008c5c: 2300 movs r3, #0
8008c5e: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008c62: e0d8 b.n 8008e16 <UART_SetConfig+0x2fe>
8008c64: 2302 movs r3, #2
8008c66: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008c6a: e0d4 b.n 8008e16 <UART_SetConfig+0x2fe>
8008c6c: 2304 movs r3, #4
8008c6e: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008c72: e0d0 b.n 8008e16 <UART_SetConfig+0x2fe>
8008c74: 2308 movs r3, #8
8008c76: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008c7a: e0cc b.n 8008e16 <UART_SetConfig+0x2fe>
8008c7c: 2310 movs r3, #16
8008c7e: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008c82: e0c8 b.n 8008e16 <UART_SetConfig+0x2fe>
8008c84: 697b ldr r3, [r7, #20]
8008c86: 681b ldr r3, [r3, #0]
8008c88: 4a5e ldr r2, [pc, #376] @ (8008e04 <UART_SetConfig+0x2ec>)
8008c8a: 4293 cmp r3, r2
8008c8c: d125 bne.n 8008cda <UART_SetConfig+0x1c2>
8008c8e: 4b5b ldr r3, [pc, #364] @ (8008dfc <UART_SetConfig+0x2e4>)
8008c90: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8008c94: f003 0330 and.w r3, r3, #48 @ 0x30
8008c98: 2b30 cmp r3, #48 @ 0x30
8008c9a: d016 beq.n 8008cca <UART_SetConfig+0x1b2>
8008c9c: 2b30 cmp r3, #48 @ 0x30
8008c9e: d818 bhi.n 8008cd2 <UART_SetConfig+0x1ba>
8008ca0: 2b20 cmp r3, #32
8008ca2: d00a beq.n 8008cba <UART_SetConfig+0x1a2>
8008ca4: 2b20 cmp r3, #32
8008ca6: d814 bhi.n 8008cd2 <UART_SetConfig+0x1ba>
8008ca8: 2b00 cmp r3, #0
8008caa: d002 beq.n 8008cb2 <UART_SetConfig+0x19a>
8008cac: 2b10 cmp r3, #16
8008cae: d008 beq.n 8008cc2 <UART_SetConfig+0x1aa>
8008cb0: e00f b.n 8008cd2 <UART_SetConfig+0x1ba>
8008cb2: 2300 movs r3, #0
8008cb4: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008cb8: e0ad b.n 8008e16 <UART_SetConfig+0x2fe>
8008cba: 2302 movs r3, #2
8008cbc: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008cc0: e0a9 b.n 8008e16 <UART_SetConfig+0x2fe>
8008cc2: 2304 movs r3, #4
8008cc4: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008cc8: e0a5 b.n 8008e16 <UART_SetConfig+0x2fe>
8008cca: 2308 movs r3, #8
8008ccc: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008cd0: e0a1 b.n 8008e16 <UART_SetConfig+0x2fe>
8008cd2: 2310 movs r3, #16
8008cd4: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008cd8: e09d b.n 8008e16 <UART_SetConfig+0x2fe>
8008cda: 697b ldr r3, [r7, #20]
8008cdc: 681b ldr r3, [r3, #0]
8008cde: 4a4a ldr r2, [pc, #296] @ (8008e08 <UART_SetConfig+0x2f0>)
8008ce0: 4293 cmp r3, r2
8008ce2: d125 bne.n 8008d30 <UART_SetConfig+0x218>
8008ce4: 4b45 ldr r3, [pc, #276] @ (8008dfc <UART_SetConfig+0x2e4>)
8008ce6: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8008cea: f003 03c0 and.w r3, r3, #192 @ 0xc0
8008cee: 2bc0 cmp r3, #192 @ 0xc0
8008cf0: d016 beq.n 8008d20 <UART_SetConfig+0x208>
8008cf2: 2bc0 cmp r3, #192 @ 0xc0
8008cf4: d818 bhi.n 8008d28 <UART_SetConfig+0x210>
8008cf6: 2b80 cmp r3, #128 @ 0x80
8008cf8: d00a beq.n 8008d10 <UART_SetConfig+0x1f8>
8008cfa: 2b80 cmp r3, #128 @ 0x80
8008cfc: d814 bhi.n 8008d28 <UART_SetConfig+0x210>
8008cfe: 2b00 cmp r3, #0
8008d00: d002 beq.n 8008d08 <UART_SetConfig+0x1f0>
8008d02: 2b40 cmp r3, #64 @ 0x40
8008d04: d008 beq.n 8008d18 <UART_SetConfig+0x200>
8008d06: e00f b.n 8008d28 <UART_SetConfig+0x210>
8008d08: 2300 movs r3, #0
8008d0a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008d0e: e082 b.n 8008e16 <UART_SetConfig+0x2fe>
8008d10: 2302 movs r3, #2
8008d12: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008d16: e07e b.n 8008e16 <UART_SetConfig+0x2fe>
8008d18: 2304 movs r3, #4
8008d1a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008d1e: e07a b.n 8008e16 <UART_SetConfig+0x2fe>
8008d20: 2308 movs r3, #8
8008d22: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008d26: e076 b.n 8008e16 <UART_SetConfig+0x2fe>
8008d28: 2310 movs r3, #16
8008d2a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008d2e: e072 b.n 8008e16 <UART_SetConfig+0x2fe>
8008d30: 697b ldr r3, [r7, #20]
8008d32: 681b ldr r3, [r3, #0]
8008d34: 4a35 ldr r2, [pc, #212] @ (8008e0c <UART_SetConfig+0x2f4>)
8008d36: 4293 cmp r3, r2
8008d38: d12a bne.n 8008d90 <UART_SetConfig+0x278>
8008d3a: 4b30 ldr r3, [pc, #192] @ (8008dfc <UART_SetConfig+0x2e4>)
8008d3c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8008d40: f403 7340 and.w r3, r3, #768 @ 0x300
8008d44: f5b3 7f40 cmp.w r3, #768 @ 0x300
8008d48: d01a beq.n 8008d80 <UART_SetConfig+0x268>
8008d4a: f5b3 7f40 cmp.w r3, #768 @ 0x300
8008d4e: d81b bhi.n 8008d88 <UART_SetConfig+0x270>
8008d50: f5b3 7f00 cmp.w r3, #512 @ 0x200
8008d54: d00c beq.n 8008d70 <UART_SetConfig+0x258>
8008d56: f5b3 7f00 cmp.w r3, #512 @ 0x200
8008d5a: d815 bhi.n 8008d88 <UART_SetConfig+0x270>
8008d5c: 2b00 cmp r3, #0
8008d5e: d003 beq.n 8008d68 <UART_SetConfig+0x250>
8008d60: f5b3 7f80 cmp.w r3, #256 @ 0x100
8008d64: d008 beq.n 8008d78 <UART_SetConfig+0x260>
8008d66: e00f b.n 8008d88 <UART_SetConfig+0x270>
8008d68: 2300 movs r3, #0
8008d6a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008d6e: e052 b.n 8008e16 <UART_SetConfig+0x2fe>
8008d70: 2302 movs r3, #2
8008d72: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008d76: e04e b.n 8008e16 <UART_SetConfig+0x2fe>
8008d78: 2304 movs r3, #4
8008d7a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008d7e: e04a b.n 8008e16 <UART_SetConfig+0x2fe>
8008d80: 2308 movs r3, #8
8008d82: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008d86: e046 b.n 8008e16 <UART_SetConfig+0x2fe>
8008d88: 2310 movs r3, #16
8008d8a: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008d8e: e042 b.n 8008e16 <UART_SetConfig+0x2fe>
8008d90: 697b ldr r3, [r7, #20]
8008d92: 681b ldr r3, [r3, #0]
8008d94: 4a17 ldr r2, [pc, #92] @ (8008df4 <UART_SetConfig+0x2dc>)
8008d96: 4293 cmp r3, r2
8008d98: d13a bne.n 8008e10 <UART_SetConfig+0x2f8>
8008d9a: 4b18 ldr r3, [pc, #96] @ (8008dfc <UART_SetConfig+0x2e4>)
8008d9c: f8d3 3088 ldr.w r3, [r3, #136] @ 0x88
8008da0: f403 6340 and.w r3, r3, #3072 @ 0xc00
8008da4: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8008da8: d01a beq.n 8008de0 <UART_SetConfig+0x2c8>
8008daa: f5b3 6f40 cmp.w r3, #3072 @ 0xc00
8008dae: d81b bhi.n 8008de8 <UART_SetConfig+0x2d0>
8008db0: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8008db4: d00c beq.n 8008dd0 <UART_SetConfig+0x2b8>
8008db6: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8008dba: d815 bhi.n 8008de8 <UART_SetConfig+0x2d0>
8008dbc: 2b00 cmp r3, #0
8008dbe: d003 beq.n 8008dc8 <UART_SetConfig+0x2b0>
8008dc0: f5b3 6f80 cmp.w r3, #1024 @ 0x400
8008dc4: d008 beq.n 8008dd8 <UART_SetConfig+0x2c0>
8008dc6: e00f b.n 8008de8 <UART_SetConfig+0x2d0>
8008dc8: 2300 movs r3, #0
8008dca: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008dce: e022 b.n 8008e16 <UART_SetConfig+0x2fe>
8008dd0: 2302 movs r3, #2
8008dd2: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008dd6: e01e b.n 8008e16 <UART_SetConfig+0x2fe>
8008dd8: 2304 movs r3, #4
8008dda: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008dde: e01a b.n 8008e16 <UART_SetConfig+0x2fe>
8008de0: 2308 movs r3, #8
8008de2: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008de6: e016 b.n 8008e16 <UART_SetConfig+0x2fe>
8008de8: 2310 movs r3, #16
8008dea: f887 302b strb.w r3, [r7, #43] @ 0x2b
8008dee: e012 b.n 8008e16 <UART_SetConfig+0x2fe>
8008df0: cfff69f3 .word 0xcfff69f3
8008df4: 40008000 .word 0x40008000
8008df8: 40013800 .word 0x40013800
8008dfc: 40021000 .word 0x40021000
8008e00: 40004400 .word 0x40004400
8008e04: 40004800 .word 0x40004800
8008e08: 40004c00 .word 0x40004c00
8008e0c: 40005000 .word 0x40005000
8008e10: 2310 movs r3, #16
8008e12: f887 302b strb.w r3, [r7, #43] @ 0x2b
/* Check LPUART instance */
if (UART_INSTANCE_LOWPOWER(huart))
8008e16: 697b ldr r3, [r7, #20]
8008e18: 681b ldr r3, [r3, #0]
8008e1a: 4aae ldr r2, [pc, #696] @ (80090d4 <UART_SetConfig+0x5bc>)
8008e1c: 4293 cmp r3, r2
8008e1e: f040 8097 bne.w 8008f50 <UART_SetConfig+0x438>
{
/* Retrieve frequency clock */
switch (clocksource)
8008e22: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
8008e26: 2b08 cmp r3, #8
8008e28: d823 bhi.n 8008e72 <UART_SetConfig+0x35a>
8008e2a: a201 add r2, pc, #4 @ (adr r2, 8008e30 <UART_SetConfig+0x318>)
8008e2c: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8008e30: 08008e55 .word 0x08008e55
8008e34: 08008e73 .word 0x08008e73
8008e38: 08008e5d .word 0x08008e5d
8008e3c: 08008e73 .word 0x08008e73
8008e40: 08008e63 .word 0x08008e63
8008e44: 08008e73 .word 0x08008e73
8008e48: 08008e73 .word 0x08008e73
8008e4c: 08008e73 .word 0x08008e73
8008e50: 08008e6b .word 0x08008e6b
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8008e54: f7fe f800 bl 8006e58 <HAL_RCC_GetPCLK1Freq>
8008e58: 6278 str r0, [r7, #36] @ 0x24
break;
8008e5a: e010 b.n 8008e7e <UART_SetConfig+0x366>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8008e5c: 4b9e ldr r3, [pc, #632] @ (80090d8 <UART_SetConfig+0x5c0>)
8008e5e: 627b str r3, [r7, #36] @ 0x24
break;
8008e60: e00d b.n 8008e7e <UART_SetConfig+0x366>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8008e62: f7fd ff8b bl 8006d7c <HAL_RCC_GetSysClockFreq>
8008e66: 6278 str r0, [r7, #36] @ 0x24
break;
8008e68: e009 b.n 8008e7e <UART_SetConfig+0x366>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8008e6a: f44f 4300 mov.w r3, #32768 @ 0x8000
8008e6e: 627b str r3, [r7, #36] @ 0x24
break;
8008e70: e005 b.n 8008e7e <UART_SetConfig+0x366>
default:
pclk = 0U;
8008e72: 2300 movs r3, #0
8008e74: 627b str r3, [r7, #36] @ 0x24
ret = HAL_ERROR;
8008e76: 2301 movs r3, #1
8008e78: f887 302a strb.w r3, [r7, #42] @ 0x2a
break;
8008e7c: bf00 nop
}
/* If proper clock source reported */
if (pclk != 0U)
8008e7e: 6a7b ldr r3, [r7, #36] @ 0x24
8008e80: 2b00 cmp r3, #0
8008e82: f000 8130 beq.w 80090e6 <UART_SetConfig+0x5ce>
{
/* Compute clock after Prescaler */
lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]);
8008e86: 697b ldr r3, [r7, #20]
8008e88: 6a5b ldr r3, [r3, #36] @ 0x24
8008e8a: 4a94 ldr r2, [pc, #592] @ (80090dc <UART_SetConfig+0x5c4>)
8008e8c: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8008e90: 461a mov r2, r3
8008e92: 6a7b ldr r3, [r7, #36] @ 0x24
8008e94: fbb3 f3f2 udiv r3, r3, r2
8008e98: 61bb str r3, [r7, #24]
/* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8008e9a: 697b ldr r3, [r7, #20]
8008e9c: 685a ldr r2, [r3, #4]
8008e9e: 4613 mov r3, r2
8008ea0: 005b lsls r3, r3, #1
8008ea2: 4413 add r3, r2
8008ea4: 69ba ldr r2, [r7, #24]
8008ea6: 429a cmp r2, r3
8008ea8: d305 bcc.n 8008eb6 <UART_SetConfig+0x39e>
(lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate)))
8008eaa: 697b ldr r3, [r7, #20]
8008eac: 685b ldr r3, [r3, #4]
8008eae: 031b lsls r3, r3, #12
if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) ||
8008eb0: 69ba ldr r2, [r7, #24]
8008eb2: 429a cmp r2, r3
8008eb4: d903 bls.n 8008ebe <UART_SetConfig+0x3a6>
{
ret = HAL_ERROR;
8008eb6: 2301 movs r3, #1
8008eb8: f887 302a strb.w r3, [r7, #42] @ 0x2a
8008ebc: e113 b.n 80090e6 <UART_SetConfig+0x5ce>
}
else
{
/* Check computed UsartDiv value is in allocated range
(it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */
usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8008ebe: 6a7b ldr r3, [r7, #36] @ 0x24
8008ec0: 2200 movs r2, #0
8008ec2: 60bb str r3, [r7, #8]
8008ec4: 60fa str r2, [r7, #12]
8008ec6: 697b ldr r3, [r7, #20]
8008ec8: 6a5b ldr r3, [r3, #36] @ 0x24
8008eca: 4a84 ldr r2, [pc, #528] @ (80090dc <UART_SetConfig+0x5c4>)
8008ecc: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8008ed0: b29b uxth r3, r3
8008ed2: 2200 movs r2, #0
8008ed4: 603b str r3, [r7, #0]
8008ed6: 607a str r2, [r7, #4]
8008ed8: e9d7 2300 ldrd r2, r3, [r7]
8008edc: e9d7 0102 ldrd r0, r1, [r7, #8]
8008ee0: f7f7 f99a bl 8000218 <__aeabi_uldivmod>
8008ee4: 4602 mov r2, r0
8008ee6: 460b mov r3, r1
8008ee8: 4610 mov r0, r2
8008eea: 4619 mov r1, r3
8008eec: f04f 0200 mov.w r2, #0
8008ef0: f04f 0300 mov.w r3, #0
8008ef4: 020b lsls r3, r1, #8
8008ef6: ea43 6310 orr.w r3, r3, r0, lsr #24
8008efa: 0202 lsls r2, r0, #8
8008efc: 6979 ldr r1, [r7, #20]
8008efe: 6849 ldr r1, [r1, #4]
8008f00: 0849 lsrs r1, r1, #1
8008f02: 2000 movs r0, #0
8008f04: 460c mov r4, r1
8008f06: 4605 mov r5, r0
8008f08: eb12 0804 adds.w r8, r2, r4
8008f0c: eb43 0905 adc.w r9, r3, r5
8008f10: 697b ldr r3, [r7, #20]
8008f12: 685b ldr r3, [r3, #4]
8008f14: 2200 movs r2, #0
8008f16: 469a mov sl, r3
8008f18: 4693 mov fp, r2
8008f1a: 4652 mov r2, sl
8008f1c: 465b mov r3, fp
8008f1e: 4640 mov r0, r8
8008f20: 4649 mov r1, r9
8008f22: f7f7 f979 bl 8000218 <__aeabi_uldivmod>
8008f26: 4602 mov r2, r0
8008f28: 460b mov r3, r1
8008f2a: 4613 mov r3, r2
8008f2c: 623b str r3, [r7, #32]
if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX))
8008f2e: 6a3b ldr r3, [r7, #32]
8008f30: f5b3 7f40 cmp.w r3, #768 @ 0x300
8008f34: d308 bcc.n 8008f48 <UART_SetConfig+0x430>
8008f36: 6a3b ldr r3, [r7, #32]
8008f38: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
8008f3c: d204 bcs.n 8008f48 <UART_SetConfig+0x430>
{
huart->Instance->BRR = usartdiv;
8008f3e: 697b ldr r3, [r7, #20]
8008f40: 681b ldr r3, [r3, #0]
8008f42: 6a3a ldr r2, [r7, #32]
8008f44: 60da str r2, [r3, #12]
8008f46: e0ce b.n 80090e6 <UART_SetConfig+0x5ce>
}
else
{
ret = HAL_ERROR;
8008f48: 2301 movs r3, #1
8008f4a: f887 302a strb.w r3, [r7, #42] @ 0x2a
8008f4e: e0ca b.n 80090e6 <UART_SetConfig+0x5ce>
} /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) ||
(lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */
} /* if (pclk != 0) */
}
/* Check UART Over Sampling to set Baud Rate Register */
else if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
8008f50: 697b ldr r3, [r7, #20]
8008f52: 69db ldr r3, [r3, #28]
8008f54: f5b3 4f00 cmp.w r3, #32768 @ 0x8000
8008f58: d166 bne.n 8009028 <UART_SetConfig+0x510>
{
switch (clocksource)
8008f5a: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
8008f5e: 2b08 cmp r3, #8
8008f60: d827 bhi.n 8008fb2 <UART_SetConfig+0x49a>
8008f62: a201 add r2, pc, #4 @ (adr r2, 8008f68 <UART_SetConfig+0x450>)
8008f64: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8008f68: 08008f8d .word 0x08008f8d
8008f6c: 08008f95 .word 0x08008f95
8008f70: 08008f9d .word 0x08008f9d
8008f74: 08008fb3 .word 0x08008fb3
8008f78: 08008fa3 .word 0x08008fa3
8008f7c: 08008fb3 .word 0x08008fb3
8008f80: 08008fb3 .word 0x08008fb3
8008f84: 08008fb3 .word 0x08008fb3
8008f88: 08008fab .word 0x08008fab
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
8008f8c: f7fd ff64 bl 8006e58 <HAL_RCC_GetPCLK1Freq>
8008f90: 6278 str r0, [r7, #36] @ 0x24
break;
8008f92: e014 b.n 8008fbe <UART_SetConfig+0x4a6>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8008f94: f7fd ff76 bl 8006e84 <HAL_RCC_GetPCLK2Freq>
8008f98: 6278 str r0, [r7, #36] @ 0x24
break;
8008f9a: e010 b.n 8008fbe <UART_SetConfig+0x4a6>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
8008f9c: 4b4e ldr r3, [pc, #312] @ (80090d8 <UART_SetConfig+0x5c0>)
8008f9e: 627b str r3, [r7, #36] @ 0x24
break;
8008fa0: e00d b.n 8008fbe <UART_SetConfig+0x4a6>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8008fa2: f7fd feeb bl 8006d7c <HAL_RCC_GetSysClockFreq>
8008fa6: 6278 str r0, [r7, #36] @ 0x24
break;
8008fa8: e009 b.n 8008fbe <UART_SetConfig+0x4a6>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
8008faa: f44f 4300 mov.w r3, #32768 @ 0x8000
8008fae: 627b str r3, [r7, #36] @ 0x24
break;
8008fb0: e005 b.n 8008fbe <UART_SetConfig+0x4a6>
default:
pclk = 0U;
8008fb2: 2300 movs r3, #0
8008fb4: 627b str r3, [r7, #36] @ 0x24
ret = HAL_ERROR;
8008fb6: 2301 movs r3, #1
8008fb8: f887 302a strb.w r3, [r7, #42] @ 0x2a
break;
8008fbc: bf00 nop
}
/* USARTDIV must be greater than or equal to 0d16 */
if (pclk != 0U)
8008fbe: 6a7b ldr r3, [r7, #36] @ 0x24
8008fc0: 2b00 cmp r3, #0
8008fc2: f000 8090 beq.w 80090e6 <UART_SetConfig+0x5ce>
{
usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8008fc6: 697b ldr r3, [r7, #20]
8008fc8: 6a5b ldr r3, [r3, #36] @ 0x24
8008fca: 4a44 ldr r2, [pc, #272] @ (80090dc <UART_SetConfig+0x5c4>)
8008fcc: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
8008fd0: 461a mov r2, r3
8008fd2: 6a7b ldr r3, [r7, #36] @ 0x24
8008fd4: fbb3 f3f2 udiv r3, r3, r2
8008fd8: 005a lsls r2, r3, #1
8008fda: 697b ldr r3, [r7, #20]
8008fdc: 685b ldr r3, [r3, #4]
8008fde: 085b lsrs r3, r3, #1
8008fe0: 441a add r2, r3
8008fe2: 697b ldr r3, [r7, #20]
8008fe4: 685b ldr r3, [r3, #4]
8008fe6: fbb2 f3f3 udiv r3, r2, r3
8008fea: 623b str r3, [r7, #32]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
8008fec: 6a3b ldr r3, [r7, #32]
8008fee: 2b0f cmp r3, #15
8008ff0: d916 bls.n 8009020 <UART_SetConfig+0x508>
8008ff2: 6a3b ldr r3, [r7, #32]
8008ff4: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
8008ff8: d212 bcs.n 8009020 <UART_SetConfig+0x508>
{
brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
8008ffa: 6a3b ldr r3, [r7, #32]
8008ffc: b29b uxth r3, r3
8008ffe: f023 030f bic.w r3, r3, #15
8009002: 83fb strh r3, [r7, #30]
brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
8009004: 6a3b ldr r3, [r7, #32]
8009006: 085b lsrs r3, r3, #1
8009008: b29b uxth r3, r3
800900a: f003 0307 and.w r3, r3, #7
800900e: b29a uxth r2, r3
8009010: 8bfb ldrh r3, [r7, #30]
8009012: 4313 orrs r3, r2
8009014: 83fb strh r3, [r7, #30]
huart->Instance->BRR = brrtemp;
8009016: 697b ldr r3, [r7, #20]
8009018: 681b ldr r3, [r3, #0]
800901a: 8bfa ldrh r2, [r7, #30]
800901c: 60da str r2, [r3, #12]
800901e: e062 b.n 80090e6 <UART_SetConfig+0x5ce>
}
else
{
ret = HAL_ERROR;
8009020: 2301 movs r3, #1
8009022: f887 302a strb.w r3, [r7, #42] @ 0x2a
8009026: e05e b.n 80090e6 <UART_SetConfig+0x5ce>
}
}
}
else
{
switch (clocksource)
8009028: f897 302b ldrb.w r3, [r7, #43] @ 0x2b
800902c: 2b08 cmp r3, #8
800902e: d828 bhi.n 8009082 <UART_SetConfig+0x56a>
8009030: a201 add r2, pc, #4 @ (adr r2, 8009038 <UART_SetConfig+0x520>)
8009032: f852 f023 ldr.w pc, [r2, r3, lsl #2]
8009036: bf00 nop
8009038: 0800905d .word 0x0800905d
800903c: 08009065 .word 0x08009065
8009040: 0800906d .word 0x0800906d
8009044: 08009083 .word 0x08009083
8009048: 08009073 .word 0x08009073
800904c: 08009083 .word 0x08009083
8009050: 08009083 .word 0x08009083
8009054: 08009083 .word 0x08009083
8009058: 0800907b .word 0x0800907b
{
case UART_CLOCKSOURCE_PCLK1:
pclk = HAL_RCC_GetPCLK1Freq();
800905c: f7fd fefc bl 8006e58 <HAL_RCC_GetPCLK1Freq>
8009060: 6278 str r0, [r7, #36] @ 0x24
break;
8009062: e014 b.n 800908e <UART_SetConfig+0x576>
case UART_CLOCKSOURCE_PCLK2:
pclk = HAL_RCC_GetPCLK2Freq();
8009064: f7fd ff0e bl 8006e84 <HAL_RCC_GetPCLK2Freq>
8009068: 6278 str r0, [r7, #36] @ 0x24
break;
800906a: e010 b.n 800908e <UART_SetConfig+0x576>
case UART_CLOCKSOURCE_HSI:
pclk = (uint32_t) HSI_VALUE;
800906c: 4b1a ldr r3, [pc, #104] @ (80090d8 <UART_SetConfig+0x5c0>)
800906e: 627b str r3, [r7, #36] @ 0x24
break;
8009070: e00d b.n 800908e <UART_SetConfig+0x576>
case UART_CLOCKSOURCE_SYSCLK:
pclk = HAL_RCC_GetSysClockFreq();
8009072: f7fd fe83 bl 8006d7c <HAL_RCC_GetSysClockFreq>
8009076: 6278 str r0, [r7, #36] @ 0x24
break;
8009078: e009 b.n 800908e <UART_SetConfig+0x576>
case UART_CLOCKSOURCE_LSE:
pclk = (uint32_t) LSE_VALUE;
800907a: f44f 4300 mov.w r3, #32768 @ 0x8000
800907e: 627b str r3, [r7, #36] @ 0x24
break;
8009080: e005 b.n 800908e <UART_SetConfig+0x576>
default:
pclk = 0U;
8009082: 2300 movs r3, #0
8009084: 627b str r3, [r7, #36] @ 0x24
ret = HAL_ERROR;
8009086: 2301 movs r3, #1
8009088: f887 302a strb.w r3, [r7, #42] @ 0x2a
break;
800908c: bf00 nop
}
if (pclk != 0U)
800908e: 6a7b ldr r3, [r7, #36] @ 0x24
8009090: 2b00 cmp r3, #0
8009092: d028 beq.n 80090e6 <UART_SetConfig+0x5ce>
{
/* USARTDIV must be greater than or equal to 0d16 */
usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
8009094: 697b ldr r3, [r7, #20]
8009096: 6a5b ldr r3, [r3, #36] @ 0x24
8009098: 4a10 ldr r2, [pc, #64] @ (80090dc <UART_SetConfig+0x5c4>)
800909a: f832 3013 ldrh.w r3, [r2, r3, lsl #1]
800909e: 461a mov r2, r3
80090a0: 6a7b ldr r3, [r7, #36] @ 0x24
80090a2: fbb3 f2f2 udiv r2, r3, r2
80090a6: 697b ldr r3, [r7, #20]
80090a8: 685b ldr r3, [r3, #4]
80090aa: 085b lsrs r3, r3, #1
80090ac: 441a add r2, r3
80090ae: 697b ldr r3, [r7, #20]
80090b0: 685b ldr r3, [r3, #4]
80090b2: fbb2 f3f3 udiv r3, r2, r3
80090b6: 623b str r3, [r7, #32]
if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
80090b8: 6a3b ldr r3, [r7, #32]
80090ba: 2b0f cmp r3, #15
80090bc: d910 bls.n 80090e0 <UART_SetConfig+0x5c8>
80090be: 6a3b ldr r3, [r7, #32]
80090c0: f5b3 3f80 cmp.w r3, #65536 @ 0x10000
80090c4: d20c bcs.n 80090e0 <UART_SetConfig+0x5c8>
{
huart->Instance->BRR = (uint16_t)usartdiv;
80090c6: 6a3b ldr r3, [r7, #32]
80090c8: b29a uxth r2, r3
80090ca: 697b ldr r3, [r7, #20]
80090cc: 681b ldr r3, [r3, #0]
80090ce: 60da str r2, [r3, #12]
80090d0: e009 b.n 80090e6 <UART_SetConfig+0x5ce>
80090d2: bf00 nop
80090d4: 40008000 .word 0x40008000
80090d8: 00f42400 .word 0x00f42400
80090dc: 08009818 .word 0x08009818
}
else
{
ret = HAL_ERROR;
80090e0: 2301 movs r3, #1
80090e2: f887 302a strb.w r3, [r7, #42] @ 0x2a
}
}
}
/* Initialize the number of data to process during RX/TX ISR execution */
huart->NbTxDataToProcess = 1;
80090e6: 697b ldr r3, [r7, #20]
80090e8: 2201 movs r2, #1
80090ea: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
huart->NbRxDataToProcess = 1;
80090ee: 697b ldr r3, [r7, #20]
80090f0: 2201 movs r2, #1
80090f2: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
/* Clear ISR function pointers */
huart->RxISR = NULL;
80090f6: 697b ldr r3, [r7, #20]
80090f8: 2200 movs r2, #0
80090fa: 675a str r2, [r3, #116] @ 0x74
huart->TxISR = NULL;
80090fc: 697b ldr r3, [r7, #20]
80090fe: 2200 movs r2, #0
8009100: 679a str r2, [r3, #120] @ 0x78
return ret;
8009102: f897 302a ldrb.w r3, [r7, #42] @ 0x2a
}
8009106: 4618 mov r0, r3
8009108: 3730 adds r7, #48 @ 0x30
800910a: 46bd mov sp, r7
800910c: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc}
08009110 <UART_AdvFeatureConfig>:
* @brief Configure the UART peripheral advanced features.
* @param huart UART handle.
* @retval None
*/
void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
{
8009110: b480 push {r7}
8009112: b083 sub sp, #12
8009114: af00 add r7, sp, #0
8009116: 6078 str r0, [r7, #4]
/* Check whether the set of advanced features to configure is properly set */
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
/* if required, configure RX/TX pins swap */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
8009118: 687b ldr r3, [r7, #4]
800911a: 6a9b ldr r3, [r3, #40] @ 0x28
800911c: f003 0308 and.w r3, r3, #8
8009120: 2b00 cmp r3, #0
8009122: d00a beq.n 800913a <UART_AdvFeatureConfig+0x2a>
{
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
8009124: 687b ldr r3, [r7, #4]
8009126: 681b ldr r3, [r3, #0]
8009128: 685b ldr r3, [r3, #4]
800912a: f423 4100 bic.w r1, r3, #32768 @ 0x8000
800912e: 687b ldr r3, [r7, #4]
8009130: 6b9a ldr r2, [r3, #56] @ 0x38
8009132: 687b ldr r3, [r7, #4]
8009134: 681b ldr r3, [r3, #0]
8009136: 430a orrs r2, r1
8009138: 605a str r2, [r3, #4]
}
/* if required, configure TX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
800913a: 687b ldr r3, [r7, #4]
800913c: 6a9b ldr r3, [r3, #40] @ 0x28
800913e: f003 0301 and.w r3, r3, #1
8009142: 2b00 cmp r3, #0
8009144: d00a beq.n 800915c <UART_AdvFeatureConfig+0x4c>
{
assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
8009146: 687b ldr r3, [r7, #4]
8009148: 681b ldr r3, [r3, #0]
800914a: 685b ldr r3, [r3, #4]
800914c: f423 3100 bic.w r1, r3, #131072 @ 0x20000
8009150: 687b ldr r3, [r7, #4]
8009152: 6ada ldr r2, [r3, #44] @ 0x2c
8009154: 687b ldr r3, [r7, #4]
8009156: 681b ldr r3, [r3, #0]
8009158: 430a orrs r2, r1
800915a: 605a str r2, [r3, #4]
}
/* if required, configure RX pin active level inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
800915c: 687b ldr r3, [r7, #4]
800915e: 6a9b ldr r3, [r3, #40] @ 0x28
8009160: f003 0302 and.w r3, r3, #2
8009164: 2b00 cmp r3, #0
8009166: d00a beq.n 800917e <UART_AdvFeatureConfig+0x6e>
{
assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
8009168: 687b ldr r3, [r7, #4]
800916a: 681b ldr r3, [r3, #0]
800916c: 685b ldr r3, [r3, #4]
800916e: f423 3180 bic.w r1, r3, #65536 @ 0x10000
8009172: 687b ldr r3, [r7, #4]
8009174: 6b1a ldr r2, [r3, #48] @ 0x30
8009176: 687b ldr r3, [r7, #4]
8009178: 681b ldr r3, [r3, #0]
800917a: 430a orrs r2, r1
800917c: 605a str r2, [r3, #4]
}
/* if required, configure data inversion */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
800917e: 687b ldr r3, [r7, #4]
8009180: 6a9b ldr r3, [r3, #40] @ 0x28
8009182: f003 0304 and.w r3, r3, #4
8009186: 2b00 cmp r3, #0
8009188: d00a beq.n 80091a0 <UART_AdvFeatureConfig+0x90>
{
assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
800918a: 687b ldr r3, [r7, #4]
800918c: 681b ldr r3, [r3, #0]
800918e: 685b ldr r3, [r3, #4]
8009190: f423 2180 bic.w r1, r3, #262144 @ 0x40000
8009194: 687b ldr r3, [r7, #4]
8009196: 6b5a ldr r2, [r3, #52] @ 0x34
8009198: 687b ldr r3, [r7, #4]
800919a: 681b ldr r3, [r3, #0]
800919c: 430a orrs r2, r1
800919e: 605a str r2, [r3, #4]
}
/* if required, configure RX overrun detection disabling */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
80091a0: 687b ldr r3, [r7, #4]
80091a2: 6a9b ldr r3, [r3, #40] @ 0x28
80091a4: f003 0310 and.w r3, r3, #16
80091a8: 2b00 cmp r3, #0
80091aa: d00a beq.n 80091c2 <UART_AdvFeatureConfig+0xb2>
{
assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
80091ac: 687b ldr r3, [r7, #4]
80091ae: 681b ldr r3, [r3, #0]
80091b0: 689b ldr r3, [r3, #8]
80091b2: f423 5180 bic.w r1, r3, #4096 @ 0x1000
80091b6: 687b ldr r3, [r7, #4]
80091b8: 6bda ldr r2, [r3, #60] @ 0x3c
80091ba: 687b ldr r3, [r7, #4]
80091bc: 681b ldr r3, [r3, #0]
80091be: 430a orrs r2, r1
80091c0: 609a str r2, [r3, #8]
}
/* if required, configure DMA disabling on reception error */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
80091c2: 687b ldr r3, [r7, #4]
80091c4: 6a9b ldr r3, [r3, #40] @ 0x28
80091c6: f003 0320 and.w r3, r3, #32
80091ca: 2b00 cmp r3, #0
80091cc: d00a beq.n 80091e4 <UART_AdvFeatureConfig+0xd4>
{
assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
80091ce: 687b ldr r3, [r7, #4]
80091d0: 681b ldr r3, [r3, #0]
80091d2: 689b ldr r3, [r3, #8]
80091d4: f423 5100 bic.w r1, r3, #8192 @ 0x2000
80091d8: 687b ldr r3, [r7, #4]
80091da: 6c1a ldr r2, [r3, #64] @ 0x40
80091dc: 687b ldr r3, [r7, #4]
80091de: 681b ldr r3, [r3, #0]
80091e0: 430a orrs r2, r1
80091e2: 609a str r2, [r3, #8]
}
/* if required, configure auto Baud rate detection scheme */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
80091e4: 687b ldr r3, [r7, #4]
80091e6: 6a9b ldr r3, [r3, #40] @ 0x28
80091e8: f003 0340 and.w r3, r3, #64 @ 0x40
80091ec: 2b00 cmp r3, #0
80091ee: d01a beq.n 8009226 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
80091f0: 687b ldr r3, [r7, #4]
80091f2: 681b ldr r3, [r3, #0]
80091f4: 685b ldr r3, [r3, #4]
80091f6: f423 1180 bic.w r1, r3, #1048576 @ 0x100000
80091fa: 687b ldr r3, [r7, #4]
80091fc: 6c5a ldr r2, [r3, #68] @ 0x44
80091fe: 687b ldr r3, [r7, #4]
8009200: 681b ldr r3, [r3, #0]
8009202: 430a orrs r2, r1
8009204: 605a str r2, [r3, #4]
/* set auto Baudrate detection parameters if detection is enabled */
if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
8009206: 687b ldr r3, [r7, #4]
8009208: 6c5b ldr r3, [r3, #68] @ 0x44
800920a: f5b3 1f80 cmp.w r3, #1048576 @ 0x100000
800920e: d10a bne.n 8009226 <UART_AdvFeatureConfig+0x116>
{
assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
8009210: 687b ldr r3, [r7, #4]
8009212: 681b ldr r3, [r3, #0]
8009214: 685b ldr r3, [r3, #4]
8009216: f423 01c0 bic.w r1, r3, #6291456 @ 0x600000
800921a: 687b ldr r3, [r7, #4]
800921c: 6c9a ldr r2, [r3, #72] @ 0x48
800921e: 687b ldr r3, [r7, #4]
8009220: 681b ldr r3, [r3, #0]
8009222: 430a orrs r2, r1
8009224: 605a str r2, [r3, #4]
}
}
/* if required, configure MSB first on communication line */
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
8009226: 687b ldr r3, [r7, #4]
8009228: 6a9b ldr r3, [r3, #40] @ 0x28
800922a: f003 0380 and.w r3, r3, #128 @ 0x80
800922e: 2b00 cmp r3, #0
8009230: d00a beq.n 8009248 <UART_AdvFeatureConfig+0x138>
{
assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
8009232: 687b ldr r3, [r7, #4]
8009234: 681b ldr r3, [r3, #0]
8009236: 685b ldr r3, [r3, #4]
8009238: f423 2100 bic.w r1, r3, #524288 @ 0x80000
800923c: 687b ldr r3, [r7, #4]
800923e: 6cda ldr r2, [r3, #76] @ 0x4c
8009240: 687b ldr r3, [r7, #4]
8009242: 681b ldr r3, [r3, #0]
8009244: 430a orrs r2, r1
8009246: 605a str r2, [r3, #4]
}
}
8009248: bf00 nop
800924a: 370c adds r7, #12
800924c: 46bd mov sp, r7
800924e: f85d 7b04 ldr.w r7, [sp], #4
8009252: 4770 bx lr
08009254 <UART_CheckIdleState>:
* @brief Check the UART Idle State.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
{
8009254: b580 push {r7, lr}
8009256: b098 sub sp, #96 @ 0x60
8009258: af02 add r7, sp, #8
800925a: 6078 str r0, [r7, #4]
uint32_t tickstart;
/* Initialize the UART ErrorCode */
huart->ErrorCode = HAL_UART_ERROR_NONE;
800925c: 687b ldr r3, [r7, #4]
800925e: 2200 movs r2, #0
8009260: f8c3 2090 str.w r2, [r3, #144] @ 0x90
/* Init tickstart for timeout management */
tickstart = HAL_GetTick();
8009264: f7f8 fc42 bl 8001aec <HAL_GetTick>
8009268: 6578 str r0, [r7, #84] @ 0x54
/* Check if the Transmitter is enabled */
if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
800926a: 687b ldr r3, [r7, #4]
800926c: 681b ldr r3, [r3, #0]
800926e: 681b ldr r3, [r3, #0]
8009270: f003 0308 and.w r3, r3, #8
8009274: 2b08 cmp r3, #8
8009276: d12f bne.n 80092d8 <UART_CheckIdleState+0x84>
{
/* Wait until TEACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
8009278: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
800927c: 9300 str r3, [sp, #0]
800927e: 6d7b ldr r3, [r7, #84] @ 0x54
8009280: 2200 movs r2, #0
8009282: f44f 1100 mov.w r1, #2097152 @ 0x200000
8009286: 6878 ldr r0, [r7, #4]
8009288: f000 f88e bl 80093a8 <UART_WaitOnFlagUntilTimeout>
800928c: 4603 mov r3, r0
800928e: 2b00 cmp r3, #0
8009290: d022 beq.n 80092d8 <UART_CheckIdleState+0x84>
{
/* Disable TXE interrupt for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
8009292: 687b ldr r3, [r7, #4]
8009294: 681b ldr r3, [r3, #0]
8009296: 63bb str r3, [r7, #56] @ 0x38
*/
__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8009298: 6bbb ldr r3, [r7, #56] @ 0x38
800929a: e853 3f00 ldrex r3, [r3]
800929e: 637b str r3, [r7, #52] @ 0x34
return(result);
80092a0: 6b7b ldr r3, [r7, #52] @ 0x34
80092a2: f023 0380 bic.w r3, r3, #128 @ 0x80
80092a6: 653b str r3, [r7, #80] @ 0x50
80092a8: 687b ldr r3, [r7, #4]
80092aa: 681b ldr r3, [r3, #0]
80092ac: 461a mov r2, r3
80092ae: 6d3b ldr r3, [r7, #80] @ 0x50
80092b0: 647b str r3, [r7, #68] @ 0x44
80092b2: 643a str r2, [r7, #64] @ 0x40
*/
__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80092b4: 6c39 ldr r1, [r7, #64] @ 0x40
80092b6: 6c7a ldr r2, [r7, #68] @ 0x44
80092b8: e841 2300 strex r3, r2, [r1]
80092bc: 63fb str r3, [r7, #60] @ 0x3c
return(result);
80092be: 6bfb ldr r3, [r7, #60] @ 0x3c
80092c0: 2b00 cmp r3, #0
80092c2: d1e6 bne.n 8009292 <UART_CheckIdleState+0x3e>
huart->gState = HAL_UART_STATE_READY;
80092c4: 687b ldr r3, [r7, #4]
80092c6: 2220 movs r2, #32
80092c8: f8c3 2088 str.w r2, [r3, #136] @ 0x88
__HAL_UNLOCK(huart);
80092cc: 687b ldr r3, [r7, #4]
80092ce: 2200 movs r2, #0
80092d0: f883 2084 strb.w r2, [r3, #132] @ 0x84
/* Timeout occurred */
return HAL_TIMEOUT;
80092d4: 2303 movs r3, #3
80092d6: e063 b.n 80093a0 <UART_CheckIdleState+0x14c>
}
}
/* Check if the Receiver is enabled */
if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
80092d8: 687b ldr r3, [r7, #4]
80092da: 681b ldr r3, [r3, #0]
80092dc: 681b ldr r3, [r3, #0]
80092de: f003 0304 and.w r3, r3, #4
80092e2: 2b04 cmp r3, #4
80092e4: d149 bne.n 800937a <UART_CheckIdleState+0x126>
{
/* Wait until REACK flag is set */
if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
80092e6: f06f 437e mvn.w r3, #4261412864 @ 0xfe000000
80092ea: 9300 str r3, [sp, #0]
80092ec: 6d7b ldr r3, [r7, #84] @ 0x54
80092ee: 2200 movs r2, #0
80092f0: f44f 0180 mov.w r1, #4194304 @ 0x400000
80092f4: 6878 ldr r0, [r7, #4]
80092f6: f000 f857 bl 80093a8 <UART_WaitOnFlagUntilTimeout>
80092fa: 4603 mov r3, r0
80092fc: 2b00 cmp r3, #0
80092fe: d03c beq.n 800937a <UART_CheckIdleState+0x126>
{
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
interrupts for the interrupt process */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
8009300: 687b ldr r3, [r7, #4]
8009302: 681b ldr r3, [r3, #0]
8009304: 627b str r3, [r7, #36] @ 0x24
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8009306: 6a7b ldr r3, [r7, #36] @ 0x24
8009308: e853 3f00 ldrex r3, [r3]
800930c: 623b str r3, [r7, #32]
return(result);
800930e: 6a3b ldr r3, [r7, #32]
8009310: f423 7390 bic.w r3, r3, #288 @ 0x120
8009314: 64fb str r3, [r7, #76] @ 0x4c
8009316: 687b ldr r3, [r7, #4]
8009318: 681b ldr r3, [r3, #0]
800931a: 461a mov r2, r3
800931c: 6cfb ldr r3, [r7, #76] @ 0x4c
800931e: 633b str r3, [r7, #48] @ 0x30
8009320: 62fa str r2, [r7, #44] @ 0x2c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8009322: 6af9 ldr r1, [r7, #44] @ 0x2c
8009324: 6b3a ldr r2, [r7, #48] @ 0x30
8009326: e841 2300 strex r3, r2, [r1]
800932a: 62bb str r3, [r7, #40] @ 0x28
return(result);
800932c: 6abb ldr r3, [r7, #40] @ 0x28
800932e: 2b00 cmp r3, #0
8009330: d1e6 bne.n 8009300 <UART_CheckIdleState+0xac>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
8009332: 687b ldr r3, [r7, #4]
8009334: 681b ldr r3, [r3, #0]
8009336: 3308 adds r3, #8
8009338: 613b str r3, [r7, #16]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
800933a: 693b ldr r3, [r7, #16]
800933c: e853 3f00 ldrex r3, [r3]
8009340: 60fb str r3, [r7, #12]
return(result);
8009342: 68fb ldr r3, [r7, #12]
8009344: f023 0301 bic.w r3, r3, #1
8009348: 64bb str r3, [r7, #72] @ 0x48
800934a: 687b ldr r3, [r7, #4]
800934c: 681b ldr r3, [r3, #0]
800934e: 3308 adds r3, #8
8009350: 6cba ldr r2, [r7, #72] @ 0x48
8009352: 61fa str r2, [r7, #28]
8009354: 61bb str r3, [r7, #24]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
8009356: 69b9 ldr r1, [r7, #24]
8009358: 69fa ldr r2, [r7, #28]
800935a: e841 2300 strex r3, r2, [r1]
800935e: 617b str r3, [r7, #20]
return(result);
8009360: 697b ldr r3, [r7, #20]
8009362: 2b00 cmp r3, #0
8009364: d1e5 bne.n 8009332 <UART_CheckIdleState+0xde>
huart->RxState = HAL_UART_STATE_READY;
8009366: 687b ldr r3, [r7, #4]
8009368: 2220 movs r2, #32
800936a: f8c3 208c str.w r2, [r3, #140] @ 0x8c
__HAL_UNLOCK(huart);
800936e: 687b ldr r3, [r7, #4]
8009370: 2200 movs r2, #0
8009372: f883 2084 strb.w r2, [r3, #132] @ 0x84
/* Timeout occurred */
return HAL_TIMEOUT;
8009376: 2303 movs r3, #3
8009378: e012 b.n 80093a0 <UART_CheckIdleState+0x14c>
}
}
/* Initialize the UART State */
huart->gState = HAL_UART_STATE_READY;
800937a: 687b ldr r3, [r7, #4]
800937c: 2220 movs r2, #32
800937e: f8c3 2088 str.w r2, [r3, #136] @ 0x88
huart->RxState = HAL_UART_STATE_READY;
8009382: 687b ldr r3, [r7, #4]
8009384: 2220 movs r2, #32
8009386: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
800938a: 687b ldr r3, [r7, #4]
800938c: 2200 movs r2, #0
800938e: 66da str r2, [r3, #108] @ 0x6c
huart->RxEventType = HAL_UART_RXEVENT_TC;
8009390: 687b ldr r3, [r7, #4]
8009392: 2200 movs r2, #0
8009394: 671a str r2, [r3, #112] @ 0x70
__HAL_UNLOCK(huart);
8009396: 687b ldr r3, [r7, #4]
8009398: 2200 movs r2, #0
800939a: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
800939e: 2300 movs r3, #0
}
80093a0: 4618 mov r0, r3
80093a2: 3758 adds r7, #88 @ 0x58
80093a4: 46bd mov sp, r7
80093a6: bd80 pop {r7, pc}
080093a8 <UART_WaitOnFlagUntilTimeout>:
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
uint32_t Tickstart, uint32_t Timeout)
{
80093a8: b580 push {r7, lr}
80093aa: b084 sub sp, #16
80093ac: af00 add r7, sp, #0
80093ae: 60f8 str r0, [r7, #12]
80093b0: 60b9 str r1, [r7, #8]
80093b2: 603b str r3, [r7, #0]
80093b4: 4613 mov r3, r2
80093b6: 71fb strb r3, [r7, #7]
/* Wait until flag is set */
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
80093b8: e04f b.n 800945a <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Check for the Timeout */
if (Timeout != HAL_MAX_DELAY)
80093ba: 69bb ldr r3, [r7, #24]
80093bc: f1b3 3fff cmp.w r3, #4294967295
80093c0: d04b beq.n 800945a <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
80093c2: f7f8 fb93 bl 8001aec <HAL_GetTick>
80093c6: 4602 mov r2, r0
80093c8: 683b ldr r3, [r7, #0]
80093ca: 1ad3 subs r3, r2, r3
80093cc: 69ba ldr r2, [r7, #24]
80093ce: 429a cmp r2, r3
80093d0: d302 bcc.n 80093d8 <UART_WaitOnFlagUntilTimeout+0x30>
80093d2: 69bb ldr r3, [r7, #24]
80093d4: 2b00 cmp r3, #0
80093d6: d101 bne.n 80093dc <UART_WaitOnFlagUntilTimeout+0x34>
{
return HAL_TIMEOUT;
80093d8: 2303 movs r3, #3
80093da: e04e b.n 800947a <UART_WaitOnFlagUntilTimeout+0xd2>
}
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
80093dc: 68fb ldr r3, [r7, #12]
80093de: 681b ldr r3, [r3, #0]
80093e0: 681b ldr r3, [r3, #0]
80093e2: f003 0304 and.w r3, r3, #4
80093e6: 2b00 cmp r3, #0
80093e8: d037 beq.n 800945a <UART_WaitOnFlagUntilTimeout+0xb2>
80093ea: 68bb ldr r3, [r7, #8]
80093ec: 2b80 cmp r3, #128 @ 0x80
80093ee: d034 beq.n 800945a <UART_WaitOnFlagUntilTimeout+0xb2>
80093f0: 68bb ldr r3, [r7, #8]
80093f2: 2b40 cmp r3, #64 @ 0x40
80093f4: d031 beq.n 800945a <UART_WaitOnFlagUntilTimeout+0xb2>
{
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
80093f6: 68fb ldr r3, [r7, #12]
80093f8: 681b ldr r3, [r3, #0]
80093fa: 69db ldr r3, [r3, #28]
80093fc: f003 0308 and.w r3, r3, #8
8009400: 2b08 cmp r3, #8
8009402: d110 bne.n 8009426 <UART_WaitOnFlagUntilTimeout+0x7e>
{
/* Clear Overrun Error flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
8009404: 68fb ldr r3, [r7, #12]
8009406: 681b ldr r3, [r3, #0]
8009408: 2208 movs r2, #8
800940a: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
800940c: 68f8 ldr r0, [r7, #12]
800940e: f000 f838 bl 8009482 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_ORE;
8009412: 68fb ldr r3, [r7, #12]
8009414: 2208 movs r2, #8
8009416: f8c3 2090 str.w r2, [r3, #144] @ 0x90
/* Process Unlocked */
__HAL_UNLOCK(huart);
800941a: 68fb ldr r3, [r7, #12]
800941c: 2200 movs r2, #0
800941e: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_ERROR;
8009422: 2301 movs r3, #1
8009424: e029 b.n 800947a <UART_WaitOnFlagUntilTimeout+0xd2>
}
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
8009426: 68fb ldr r3, [r7, #12]
8009428: 681b ldr r3, [r3, #0]
800942a: 69db ldr r3, [r3, #28]
800942c: f403 6300 and.w r3, r3, #2048 @ 0x800
8009430: f5b3 6f00 cmp.w r3, #2048 @ 0x800
8009434: d111 bne.n 800945a <UART_WaitOnFlagUntilTimeout+0xb2>
{
/* Clear Receiver Timeout flag*/
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
8009436: 68fb ldr r3, [r7, #12]
8009438: 681b ldr r3, [r3, #0]
800943a: f44f 6200 mov.w r2, #2048 @ 0x800
800943e: 621a str r2, [r3, #32]
/* Blocking error : transfer is aborted
Set the UART state ready to be able to start again the process,
Disable Rx Interrupts if ongoing */
UART_EndRxTransfer(huart);
8009440: 68f8 ldr r0, [r7, #12]
8009442: f000 f81e bl 8009482 <UART_EndRxTransfer>
huart->ErrorCode = HAL_UART_ERROR_RTO;
8009446: 68fb ldr r3, [r7, #12]
8009448: 2220 movs r2, #32
800944a: f8c3 2090 str.w r2, [r3, #144] @ 0x90
/* Process Unlocked */
__HAL_UNLOCK(huart);
800944e: 68fb ldr r3, [r7, #12]
8009450: 2200 movs r2, #0
8009452: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_TIMEOUT;
8009456: 2303 movs r3, #3
8009458: e00f b.n 800947a <UART_WaitOnFlagUntilTimeout+0xd2>
while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
800945a: 68fb ldr r3, [r7, #12]
800945c: 681b ldr r3, [r3, #0]
800945e: 69da ldr r2, [r3, #28]
8009460: 68bb ldr r3, [r7, #8]
8009462: 4013 ands r3, r2
8009464: 68ba ldr r2, [r7, #8]
8009466: 429a cmp r2, r3
8009468: bf0c ite eq
800946a: 2301 moveq r3, #1
800946c: 2300 movne r3, #0
800946e: b2db uxtb r3, r3
8009470: 461a mov r2, r3
8009472: 79fb ldrb r3, [r7, #7]
8009474: 429a cmp r2, r3
8009476: d0a0 beq.n 80093ba <UART_WaitOnFlagUntilTimeout+0x12>
}
}
}
}
return HAL_OK;
8009478: 2300 movs r3, #0
}
800947a: 4618 mov r0, r3
800947c: 3710 adds r7, #16
800947e: 46bd mov sp, r7
8009480: bd80 pop {r7, pc}
08009482 <UART_EndRxTransfer>:
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
* @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
{
8009482: b480 push {r7}
8009484: b095 sub sp, #84 @ 0x54
8009486: af00 add r7, sp, #0
8009488: 6078 str r0, [r7, #4]
/* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
800948a: 687b ldr r3, [r7, #4]
800948c: 681b ldr r3, [r3, #0]
800948e: 637b str r3, [r7, #52] @ 0x34
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8009490: 6b7b ldr r3, [r7, #52] @ 0x34
8009492: e853 3f00 ldrex r3, [r3]
8009496: 633b str r3, [r7, #48] @ 0x30
return(result);
8009498: 6b3b ldr r3, [r7, #48] @ 0x30
800949a: f423 7390 bic.w r3, r3, #288 @ 0x120
800949e: 64fb str r3, [r7, #76] @ 0x4c
80094a0: 687b ldr r3, [r7, #4]
80094a2: 681b ldr r3, [r3, #0]
80094a4: 461a mov r2, r3
80094a6: 6cfb ldr r3, [r7, #76] @ 0x4c
80094a8: 643b str r3, [r7, #64] @ 0x40
80094aa: 63fa str r2, [r7, #60] @ 0x3c
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80094ac: 6bf9 ldr r1, [r7, #60] @ 0x3c
80094ae: 6c3a ldr r2, [r7, #64] @ 0x40
80094b0: e841 2300 strex r3, r2, [r1]
80094b4: 63bb str r3, [r7, #56] @ 0x38
return(result);
80094b6: 6bbb ldr r3, [r7, #56] @ 0x38
80094b8: 2b00 cmp r3, #0
80094ba: d1e6 bne.n 800948a <UART_EndRxTransfer+0x8>
ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
80094bc: 687b ldr r3, [r7, #4]
80094be: 681b ldr r3, [r3, #0]
80094c0: 3308 adds r3, #8
80094c2: 623b str r3, [r7, #32]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
80094c4: 6a3b ldr r3, [r7, #32]
80094c6: e853 3f00 ldrex r3, [r3]
80094ca: 61fb str r3, [r7, #28]
return(result);
80094cc: 69fb ldr r3, [r7, #28]
80094ce: f023 5380 bic.w r3, r3, #268435456 @ 0x10000000
80094d2: f023 0301 bic.w r3, r3, #1
80094d6: 64bb str r3, [r7, #72] @ 0x48
80094d8: 687b ldr r3, [r7, #4]
80094da: 681b ldr r3, [r3, #0]
80094dc: 3308 adds r3, #8
80094de: 6cba ldr r2, [r7, #72] @ 0x48
80094e0: 62fa str r2, [r7, #44] @ 0x2c
80094e2: 62bb str r3, [r7, #40] @ 0x28
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
80094e4: 6ab9 ldr r1, [r7, #40] @ 0x28
80094e6: 6afa ldr r2, [r7, #44] @ 0x2c
80094e8: e841 2300 strex r3, r2, [r1]
80094ec: 627b str r3, [r7, #36] @ 0x24
return(result);
80094ee: 6a7b ldr r3, [r7, #36] @ 0x24
80094f0: 2b00 cmp r3, #0
80094f2: d1e3 bne.n 80094bc <UART_EndRxTransfer+0x3a>
/* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
80094f4: 687b ldr r3, [r7, #4]
80094f6: 6edb ldr r3, [r3, #108] @ 0x6c
80094f8: 2b01 cmp r3, #1
80094fa: d118 bne.n 800952e <UART_EndRxTransfer+0xac>
{
ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
80094fc: 687b ldr r3, [r7, #4]
80094fe: 681b ldr r3, [r3, #0]
8009500: 60fb str r3, [r7, #12]
__ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
8009502: 68fb ldr r3, [r7, #12]
8009504: e853 3f00 ldrex r3, [r3]
8009508: 60bb str r3, [r7, #8]
return(result);
800950a: 68bb ldr r3, [r7, #8]
800950c: f023 0310 bic.w r3, r3, #16
8009510: 647b str r3, [r7, #68] @ 0x44
8009512: 687b ldr r3, [r7, #4]
8009514: 681b ldr r3, [r3, #0]
8009516: 461a mov r2, r3
8009518: 6c7b ldr r3, [r7, #68] @ 0x44
800951a: 61bb str r3, [r7, #24]
800951c: 617a str r2, [r7, #20]
__ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
800951e: 6979 ldr r1, [r7, #20]
8009520: 69ba ldr r2, [r7, #24]
8009522: e841 2300 strex r3, r2, [r1]
8009526: 613b str r3, [r7, #16]
return(result);
8009528: 693b ldr r3, [r7, #16]
800952a: 2b00 cmp r3, #0
800952c: d1e6 bne.n 80094fc <UART_EndRxTransfer+0x7a>
}
/* At end of Rx process, restore huart->RxState to Ready */
huart->RxState = HAL_UART_STATE_READY;
800952e: 687b ldr r3, [r7, #4]
8009530: 2220 movs r2, #32
8009532: f8c3 208c str.w r2, [r3, #140] @ 0x8c
huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
8009536: 687b ldr r3, [r7, #4]
8009538: 2200 movs r2, #0
800953a: 66da str r2, [r3, #108] @ 0x6c
/* Reset RxIsr function pointer */
huart->RxISR = NULL;
800953c: 687b ldr r3, [r7, #4]
800953e: 2200 movs r2, #0
8009540: 675a str r2, [r3, #116] @ 0x74
}
8009542: bf00 nop
8009544: 3754 adds r7, #84 @ 0x54
8009546: 46bd mov sp, r7
8009548: f85d 7b04 ldr.w r7, [sp], #4
800954c: 4770 bx lr
0800954e <HAL_UARTEx_DisableFifoMode>:
* @brief Disable the FIFO mode.
* @param huart UART handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
{
800954e: b480 push {r7}
8009550: b085 sub sp, #20
8009552: af00 add r7, sp, #0
8009554: 6078 str r0, [r7, #4]
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
/* Process Locked */
__HAL_LOCK(huart);
8009556: 687b ldr r3, [r7, #4]
8009558: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
800955c: 2b01 cmp r3, #1
800955e: d101 bne.n 8009564 <HAL_UARTEx_DisableFifoMode+0x16>
8009560: 2302 movs r3, #2
8009562: e027 b.n 80095b4 <HAL_UARTEx_DisableFifoMode+0x66>
8009564: 687b ldr r3, [r7, #4]
8009566: 2201 movs r2, #1
8009568: f883 2084 strb.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY;
800956c: 687b ldr r3, [r7, #4]
800956e: 2224 movs r2, #36 @ 0x24
8009570: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
8009574: 687b ldr r3, [r7, #4]
8009576: 681b ldr r3, [r3, #0]
8009578: 681b ldr r3, [r3, #0]
800957a: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
800957c: 687b ldr r3, [r7, #4]
800957e: 681b ldr r3, [r3, #0]
8009580: 681a ldr r2, [r3, #0]
8009582: 687b ldr r3, [r7, #4]
8009584: 681b ldr r3, [r3, #0]
8009586: f022 0201 bic.w r2, r2, #1
800958a: 601a str r2, [r3, #0]
/* Disable FIFO mode */
CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
800958c: 68fb ldr r3, [r7, #12]
800958e: f023 5300 bic.w r3, r3, #536870912 @ 0x20000000
8009592: 60fb str r3, [r7, #12]
huart->FifoMode = UART_FIFOMODE_DISABLE;
8009594: 687b ldr r3, [r7, #4]
8009596: 2200 movs r2, #0
8009598: 665a str r2, [r3, #100] @ 0x64
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
800959a: 687b ldr r3, [r7, #4]
800959c: 681b ldr r3, [r3, #0]
800959e: 68fa ldr r2, [r7, #12]
80095a0: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
80095a2: 687b ldr r3, [r7, #4]
80095a4: 2220 movs r2, #32
80095a6: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Process Unlocked */
__HAL_UNLOCK(huart);
80095aa: 687b ldr r3, [r7, #4]
80095ac: 2200 movs r2, #0
80095ae: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
80095b2: 2300 movs r3, #0
}
80095b4: 4618 mov r0, r3
80095b6: 3714 adds r7, #20
80095b8: 46bd mov sp, r7
80095ba: f85d 7b04 ldr.w r7, [sp], #4
80095be: 4770 bx lr
080095c0 <HAL_UARTEx_SetTxFifoThreshold>:
* @arg @ref UART_TXFIFO_THRESHOLD_7_8
* @arg @ref UART_TXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
80095c0: b580 push {r7, lr}
80095c2: b084 sub sp, #16
80095c4: af00 add r7, sp, #0
80095c6: 6078 str r0, [r7, #4]
80095c8: 6039 str r1, [r7, #0]
/* Check parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
80095ca: 687b ldr r3, [r7, #4]
80095cc: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
80095d0: 2b01 cmp r3, #1
80095d2: d101 bne.n 80095d8 <HAL_UARTEx_SetTxFifoThreshold+0x18>
80095d4: 2302 movs r3, #2
80095d6: e02d b.n 8009634 <HAL_UARTEx_SetTxFifoThreshold+0x74>
80095d8: 687b ldr r3, [r7, #4]
80095da: 2201 movs r2, #1
80095dc: f883 2084 strb.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY;
80095e0: 687b ldr r3, [r7, #4]
80095e2: 2224 movs r2, #36 @ 0x24
80095e4: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
80095e8: 687b ldr r3, [r7, #4]
80095ea: 681b ldr r3, [r3, #0]
80095ec: 681b ldr r3, [r3, #0]
80095ee: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
80095f0: 687b ldr r3, [r7, #4]
80095f2: 681b ldr r3, [r3, #0]
80095f4: 681a ldr r2, [r3, #0]
80095f6: 687b ldr r3, [r7, #4]
80095f8: 681b ldr r3, [r3, #0]
80095fa: f022 0201 bic.w r2, r2, #1
80095fe: 601a str r2, [r3, #0]
/* Update TX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
8009600: 687b ldr r3, [r7, #4]
8009602: 681b ldr r3, [r3, #0]
8009604: 689b ldr r3, [r3, #8]
8009606: f023 4160 bic.w r1, r3, #3758096384 @ 0xe0000000
800960a: 687b ldr r3, [r7, #4]
800960c: 681b ldr r3, [r3, #0]
800960e: 683a ldr r2, [r7, #0]
8009610: 430a orrs r2, r1
8009612: 609a str r2, [r3, #8]
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
8009614: 6878 ldr r0, [r7, #4]
8009616: f000 f84f bl 80096b8 <UARTEx_SetNbDataToProcess>
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
800961a: 687b ldr r3, [r7, #4]
800961c: 681b ldr r3, [r3, #0]
800961e: 68fa ldr r2, [r7, #12]
8009620: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
8009622: 687b ldr r3, [r7, #4]
8009624: 2220 movs r2, #32
8009626: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Process Unlocked */
__HAL_UNLOCK(huart);
800962a: 687b ldr r3, [r7, #4]
800962c: 2200 movs r2, #0
800962e: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
8009632: 2300 movs r3, #0
}
8009634: 4618 mov r0, r3
8009636: 3710 adds r7, #16
8009638: 46bd mov sp, r7
800963a: bd80 pop {r7, pc}
0800963c <HAL_UARTEx_SetRxFifoThreshold>:
* @arg @ref UART_RXFIFO_THRESHOLD_7_8
* @arg @ref UART_RXFIFO_THRESHOLD_8_8
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
{
800963c: b580 push {r7, lr}
800963e: b084 sub sp, #16
8009640: af00 add r7, sp, #0
8009642: 6078 str r0, [r7, #4]
8009644: 6039 str r1, [r7, #0]
/* Check the parameters */
assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
/* Process Locked */
__HAL_LOCK(huart);
8009646: 687b ldr r3, [r7, #4]
8009648: f893 3084 ldrb.w r3, [r3, #132] @ 0x84
800964c: 2b01 cmp r3, #1
800964e: d101 bne.n 8009654 <HAL_UARTEx_SetRxFifoThreshold+0x18>
8009650: 2302 movs r3, #2
8009652: e02d b.n 80096b0 <HAL_UARTEx_SetRxFifoThreshold+0x74>
8009654: 687b ldr r3, [r7, #4]
8009656: 2201 movs r2, #1
8009658: f883 2084 strb.w r2, [r3, #132] @ 0x84
huart->gState = HAL_UART_STATE_BUSY;
800965c: 687b ldr r3, [r7, #4]
800965e: 2224 movs r2, #36 @ 0x24
8009660: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Save actual UART configuration */
tmpcr1 = READ_REG(huart->Instance->CR1);
8009664: 687b ldr r3, [r7, #4]
8009666: 681b ldr r3, [r3, #0]
8009668: 681b ldr r3, [r3, #0]
800966a: 60fb str r3, [r7, #12]
/* Disable UART */
__HAL_UART_DISABLE(huart);
800966c: 687b ldr r3, [r7, #4]
800966e: 681b ldr r3, [r3, #0]
8009670: 681a ldr r2, [r3, #0]
8009672: 687b ldr r3, [r7, #4]
8009674: 681b ldr r3, [r3, #0]
8009676: f022 0201 bic.w r2, r2, #1
800967a: 601a str r2, [r3, #0]
/* Update RX threshold configuration */
MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
800967c: 687b ldr r3, [r7, #4]
800967e: 681b ldr r3, [r3, #0]
8009680: 689b ldr r3, [r3, #8]
8009682: f023 6160 bic.w r1, r3, #234881024 @ 0xe000000
8009686: 687b ldr r3, [r7, #4]
8009688: 681b ldr r3, [r3, #0]
800968a: 683a ldr r2, [r7, #0]
800968c: 430a orrs r2, r1
800968e: 609a str r2, [r3, #8]
/* Determine the number of data to process during RX/TX ISR execution */
UARTEx_SetNbDataToProcess(huart);
8009690: 6878 ldr r0, [r7, #4]
8009692: f000 f811 bl 80096b8 <UARTEx_SetNbDataToProcess>
/* Restore UART configuration */
WRITE_REG(huart->Instance->CR1, tmpcr1);
8009696: 687b ldr r3, [r7, #4]
8009698: 681b ldr r3, [r3, #0]
800969a: 68fa ldr r2, [r7, #12]
800969c: 601a str r2, [r3, #0]
huart->gState = HAL_UART_STATE_READY;
800969e: 687b ldr r3, [r7, #4]
80096a0: 2220 movs r2, #32
80096a2: f8c3 2088 str.w r2, [r3, #136] @ 0x88
/* Process Unlocked */
__HAL_UNLOCK(huart);
80096a6: 687b ldr r3, [r7, #4]
80096a8: 2200 movs r2, #0
80096aa: f883 2084 strb.w r2, [r3, #132] @ 0x84
return HAL_OK;
80096ae: 2300 movs r3, #0
}
80096b0: 4618 mov r0, r3
80096b2: 3710 adds r7, #16
80096b4: 46bd mov sp, r7
80096b6: bd80 pop {r7, pc}
080096b8 <UARTEx_SetNbDataToProcess>:
* the UART configuration registers.
* @param huart UART handle.
* @retval None
*/
static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
{
80096b8: b480 push {r7}
80096ba: b085 sub sp, #20
80096bc: af00 add r7, sp, #0
80096be: 6078 str r0, [r7, #4]
uint8_t rx_fifo_threshold;
uint8_t tx_fifo_threshold;
static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
if (huart->FifoMode == UART_FIFOMODE_DISABLE)
80096c0: 687b ldr r3, [r7, #4]
80096c2: 6e5b ldr r3, [r3, #100] @ 0x64
80096c4: 2b00 cmp r3, #0
80096c6: d108 bne.n 80096da <UARTEx_SetNbDataToProcess+0x22>
{
huart->NbTxDataToProcess = 1U;
80096c8: 687b ldr r3, [r7, #4]
80096ca: 2201 movs r2, #1
80096cc: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
huart->NbRxDataToProcess = 1U;
80096d0: 687b ldr r3, [r7, #4]
80096d2: 2201 movs r2, #1
80096d4: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
(uint16_t)denominator[tx_fifo_threshold];
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
(uint16_t)denominator[rx_fifo_threshold];
}
}
80096d8: e031 b.n 800973e <UARTEx_SetNbDataToProcess+0x86>
rx_fifo_depth = RX_FIFO_DEPTH;
80096da: 2308 movs r3, #8
80096dc: 73fb strb r3, [r7, #15]
tx_fifo_depth = TX_FIFO_DEPTH;
80096de: 2308 movs r3, #8
80096e0: 73bb strb r3, [r7, #14]
rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
80096e2: 687b ldr r3, [r7, #4]
80096e4: 681b ldr r3, [r3, #0]
80096e6: 689b ldr r3, [r3, #8]
80096e8: 0e5b lsrs r3, r3, #25
80096ea: b2db uxtb r3, r3
80096ec: f003 0307 and.w r3, r3, #7
80096f0: 737b strb r3, [r7, #13]
tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
80096f2: 687b ldr r3, [r7, #4]
80096f4: 681b ldr r3, [r3, #0]
80096f6: 689b ldr r3, [r3, #8]
80096f8: 0f5b lsrs r3, r3, #29
80096fa: b2db uxtb r3, r3
80096fc: f003 0307 and.w r3, r3, #7
8009700: 733b strb r3, [r7, #12]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8009702: 7bbb ldrb r3, [r7, #14]
8009704: 7b3a ldrb r2, [r7, #12]
8009706: 4911 ldr r1, [pc, #68] @ (800974c <UARTEx_SetNbDataToProcess+0x94>)
8009708: 5c8a ldrb r2, [r1, r2]
800970a: fb02 f303 mul.w r3, r2, r3
(uint16_t)denominator[tx_fifo_threshold];
800970e: 7b3a ldrb r2, [r7, #12]
8009710: 490f ldr r1, [pc, #60] @ (8009750 <UARTEx_SetNbDataToProcess+0x98>)
8009712: 5c8a ldrb r2, [r1, r2]
huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
8009714: fb93 f3f2 sdiv r3, r3, r2
8009718: b29a uxth r2, r3
800971a: 687b ldr r3, [r7, #4]
800971c: f8a3 206a strh.w r2, [r3, #106] @ 0x6a
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8009720: 7bfb ldrb r3, [r7, #15]
8009722: 7b7a ldrb r2, [r7, #13]
8009724: 4909 ldr r1, [pc, #36] @ (800974c <UARTEx_SetNbDataToProcess+0x94>)
8009726: 5c8a ldrb r2, [r1, r2]
8009728: fb02 f303 mul.w r3, r2, r3
(uint16_t)denominator[rx_fifo_threshold];
800972c: 7b7a ldrb r2, [r7, #13]
800972e: 4908 ldr r1, [pc, #32] @ (8009750 <UARTEx_SetNbDataToProcess+0x98>)
8009730: 5c8a ldrb r2, [r1, r2]
huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
8009732: fb93 f3f2 sdiv r3, r3, r2
8009736: b29a uxth r2, r3
8009738: 687b ldr r3, [r7, #4]
800973a: f8a3 2068 strh.w r2, [r3, #104] @ 0x68
}
800973e: bf00 nop
8009740: 3714 adds r7, #20
8009742: 46bd mov sp, r7
8009744: f85d 7b04 ldr.w r7, [sp], #4
8009748: 4770 bx lr
800974a: bf00 nop
800974c: 08009830 .word 0x08009830
8009750: 08009838 .word 0x08009838
08009754 <memset>:
8009754: 4402 add r2, r0
8009756: 4603 mov r3, r0
8009758: 4293 cmp r3, r2
800975a: d100 bne.n 800975e <memset+0xa>
800975c: 4770 bx lr
800975e: f803 1b01 strb.w r1, [r3], #1
8009762: e7f9 b.n 8009758 <memset+0x4>
08009764 <__libc_init_array>:
8009764: b570 push {r4, r5, r6, lr}
8009766: 4d0d ldr r5, [pc, #52] @ (800979c <__libc_init_array+0x38>)
8009768: 4c0d ldr r4, [pc, #52] @ (80097a0 <__libc_init_array+0x3c>)
800976a: 1b64 subs r4, r4, r5
800976c: 10a4 asrs r4, r4, #2
800976e: 2600 movs r6, #0
8009770: 42a6 cmp r6, r4
8009772: d109 bne.n 8009788 <__libc_init_array+0x24>
8009774: 4d0b ldr r5, [pc, #44] @ (80097a4 <__libc_init_array+0x40>)
8009776: 4c0c ldr r4, [pc, #48] @ (80097a8 <__libc_init_array+0x44>)
8009778: f000 f818 bl 80097ac <_init>
800977c: 1b64 subs r4, r4, r5
800977e: 10a4 asrs r4, r4, #2
8009780: 2600 movs r6, #0
8009782: 42a6 cmp r6, r4
8009784: d105 bne.n 8009792 <__libc_init_array+0x2e>
8009786: bd70 pop {r4, r5, r6, pc}
8009788: f855 3b04 ldr.w r3, [r5], #4
800978c: 4798 blx r3
800978e: 3601 adds r6, #1
8009790: e7ee b.n 8009770 <__libc_init_array+0xc>
8009792: f855 3b04 ldr.w r3, [r5], #4
8009796: 4798 blx r3
8009798: 3601 adds r6, #1
800979a: e7f2 b.n 8009782 <__libc_init_array+0x1e>
800979c: 08009848 .word 0x08009848
80097a0: 08009848 .word 0x08009848
80097a4: 08009848 .word 0x08009848
80097a8: 0800984c .word 0x0800984c
080097ac <_init>:
80097ac: b5f8 push {r3, r4, r5, r6, r7, lr}
80097ae: bf00 nop
80097b0: bcf8 pop {r3, r4, r5, r6, r7}
80097b2: bc08 pop {r3}
80097b4: 469e mov lr, r3
80097b6: 4770 bx lr
080097b8 <_fini>:
80097b8: b5f8 push {r3, r4, r5, r6, r7, lr}
80097ba: bf00 nop
80097bc: bcf8 pop {r3, r4, r5, r6, r7}
80097be: bc08 pop {r3}
80097c0: 469e mov lr, r3
80097c2: 4770 bx lr
Reference in New Issue View Git Blame Copy Permalink