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C64PSU/c64psu-report.txt

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# PCB
Board size: 86.18x71.89 mm (3.39x2.83 inches)
- This is the size of the rectangle that contains the board
- Thickness: 1.6 mm (63 mils)
- Material: FR4
- Finish: None
- Layers: 4
- Copper thickness: 35 µm
Solder mask: TOP / BOTTOM
- Color: Green
Silk screen: TOP / BOTTOM
- Color: White
Stackup:
| Name | Type | Color | Thickness [µm]| Material | Er | Loss tan |
|----------------------|----------------------|------------------|---------------|-----------------|-----------|--------------|
| F.SilkS | Top Silk Screen | | | | | |
| F.Paste | Top Solder Paste | | | | | |
| F.Mask | Top Solder Mask | | 10 | | | |
| F.Cu | copper | | 35 | | | |
| dielectric 1 | prepreg | | 100 | FR4 | 4.5 | 0.020 |
| In1.Cu | copper | | 35 | | | |
| dielectric 2 | core | | 1240 | FR4 | 4.5 | 0.020 |
| In2.Cu | copper | | 35 | | | |
| dielectric 3 | prepreg | | 100 | FR4 | 4.5 | 0.020 |
| B.Cu | copper | | 35 | | | |
| B.Mask | Bottom Solder Mask | | 10 | | | |
| B.Paste | Bottom Solder Paste | | | | | |
| B.SilkS | Bottom Silk Screen | | | | | |
# Important sizes
Clearance: 0.2 mm (8 mils)
Track width: 0.17 mm (7 mils)
- By design rules: 0.0 mm (0 mils)
Drill: 0.4 mm (16 mils)
- Vias: 0.4 mm (16 mils) [Design: 0.4 mm (16 mils)]
- Pads: 0.75 mm (30 mils)
- The above values are real drill sizes, they add 0.1 mm (4 mils) to plated holes (PTH)
Via: 0.6/0.3 mm (24/12 mils)
- By design rules: 0.5/0.3 mm (20/12 mils)
- Micro via: yes [0.2/0.1 mm (8/4 mils)]
- Buried/blind via: yes
- Total: 242 (thru: 242 buried/blind: 0 micro: 0)
Outer Annular Ring: 0.1 mm (4 mils)
- By design rules: 0.15 mm (6 mils)
Eurocircuits class: 6C
- Using min drill 0.35 mm for an OAR of 0.13 mm
# General stats
Components count: (SMD/THT)
- Top: 87/6 (SMD + THT)
- Bottom: 23/2 (SMD + THT)
Defined tracks:
- 0.17 mm (7 mils)
- 0.21 mm (8 mils)
- 0.3 mm (12 mils)
- 0.4 mm (16 mils)
- 0.6 mm (24 mils)
- 0.8 mm (31 mils)
- 1.0 mm (39 mils)
- 1.5 mm (59 mils)
- 2.0 mm (79 mils)
Used tracks:
- 0.17 mm (7 mils) (43) defined: yes
- 0.21 mm (8 mils) (150) defined: yes
- 0.3 mm (12 mils) (193) defined: yes
- 0.4 mm (16 mils) (16) defined: yes
- 0.6 mm (24 mils) (52) defined: yes
- 0.8 mm (31 mils) (39) defined: yes
- 1.0 mm (39 mils) (83) defined: yes
- 1.5 mm (59 mils) (58) defined: yes
- 2.0 mm (79 mils) (2) defined: yes
Defined vias:
Used vias:
- 0.6/0.3 mm (24/12 mils) (Count: 242, Aspect: 2.7 A) defined: no
Holes (excluding vias):
- 0.8 mm (31 mils) (16)
- 1.0 mm (39 mils) (12)
- 1.3 mm (51 mils) (9)
- 1.5 mm (59 mils) (10)
- 2.4 mm (94 mils) (2)
- 3.2 mm (126 mils) (3)
Oval holes:
- 0.65x1.15 mm (26x45 mils) (2)
- 0.65x1.55 mm (26x61 mils) (2)
Drill tools (including vias and computing adjusts and rounding):
- 0.4 mm (16 mils) (242)
- 0.75 mm (30 mils) (4)
- 0.9 mm (35 mils) (16)
- 1.1 mm (43 mils) (12)
- 1.4 mm (55 mils) (9)
- 1.6 mm (63 mils) (10)
- 2.4 mm (94 mils) (2)
- 3.3 mm (130 mils) (3)
Solder paste stats:
Using a paste with 87.75 % alloy, that has an specific gravity for the alloy of 7.4 g/cm³
and 1.0 g/cm³ for the flux. This paste has an specific gravity of 4.15 g/cm³.
The stencil thickness is 0.12 mm.
| Side | Pads with paste | Area [mm²] | Paste [g] |
|--------|-----------------|------------|-----------|
| Top | 284 | 308.02 | 1.53 |
| Bottom | 53 | 69.05 | 0.34 |
| Total | 337 | 377.08 | 1.88 |
Note: this is just an approximation to the theoretical value. Margins of the solder mask and waste aren't computed.
# Schematic
![Schematic SVG](Schematic/c64psu-schematic.svg){ width=16.5cm height=11.7cm }
# PCB Layers
![PCB PDF](PCB/PDF/c64psu-pcb.pdf){ width=16.5cm height=11.7cm }