156 lines
4.8 KiB
Plaintext
156 lines
4.8 KiB
Plaintext
# PCB
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Board size: 86.18x71.89 mm (3.39x2.83 inches)
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- This is the size of the rectangle that contains the board
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- Thickness: 1.6 mm (63 mils)
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- Material: FR4
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- Finish: None
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- Layers: 4
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- Copper thickness: 35 µm
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Solder mask: TOP / BOTTOM
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- Color: Green
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Silk screen: TOP / BOTTOM
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- Color: White
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Stackup:
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| Name | Type | Color | Thickness [µm]| Material | Er | Loss tan |
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|----------------------|----------------------|------------------|---------------|-----------------|-----------|--------------|
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| F.SilkS | Top Silk Screen | | | | | |
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| F.Paste | Top Solder Paste | | | | | |
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| F.Mask | Top Solder Mask | | 10 | | | |
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| F.Cu | copper | | 35 | | | |
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| dielectric 1 | prepreg | | 100 | FR4 | 4.5 | 0.020 |
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| In1.Cu | copper | | 35 | | | |
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| dielectric 2 | core | | 1240 | FR4 | 4.5 | 0.020 |
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| In2.Cu | copper | | 35 | | | |
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| dielectric 3 | prepreg | | 100 | FR4 | 4.5 | 0.020 |
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| B.Cu | copper | | 35 | | | |
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| B.Mask | Bottom Solder Mask | | 10 | | | |
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| B.Paste | Bottom Solder Paste | | | | | |
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| B.SilkS | Bottom Silk Screen | | | | | |
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# Important sizes
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Clearance: 0.2 mm (8 mils)
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Track width: 0.17 mm (7 mils)
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- By design rules: 0.0 mm (0 mils)
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Drill: 0.4 mm (16 mils)
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- Vias: 0.4 mm (16 mils) [Design: 0.4 mm (16 mils)]
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- Pads: 0.75 mm (30 mils)
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- The above values are real drill sizes, they add 0.1 mm (4 mils) to plated holes (PTH)
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Via: 0.6/0.3 mm (24/12 mils)
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- By design rules: 0.5/0.3 mm (20/12 mils)
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- Micro via: yes [0.2/0.1 mm (8/4 mils)]
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- Buried/blind via: yes
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- Total: 242 (thru: 242 buried/blind: 0 micro: 0)
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Outer Annular Ring: 0.1 mm (4 mils)
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- By design rules: 0.15 mm (6 mils)
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Eurocircuits class: 6C
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- Using min drill 0.35 mm for an OAR of 0.13 mm
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# General stats
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Components count: (SMD/THT)
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- Top: 87/6 (SMD + THT)
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- Bottom: 23/2 (SMD + THT)
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Defined tracks:
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- 0.17 mm (7 mils)
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- 0.21 mm (8 mils)
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- 0.3 mm (12 mils)
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- 0.4 mm (16 mils)
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- 0.6 mm (24 mils)
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- 0.8 mm (31 mils)
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- 1.0 mm (39 mils)
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- 1.5 mm (59 mils)
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- 2.0 mm (79 mils)
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Used tracks:
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- 0.17 mm (7 mils) (43) defined: yes
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- 0.21 mm (8 mils) (150) defined: yes
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- 0.3 mm (12 mils) (193) defined: yes
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- 0.4 mm (16 mils) (16) defined: yes
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- 0.6 mm (24 mils) (52) defined: yes
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- 0.8 mm (31 mils) (39) defined: yes
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- 1.0 mm (39 mils) (83) defined: yes
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- 1.5 mm (59 mils) (58) defined: yes
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- 2.0 mm (79 mils) (2) defined: yes
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Defined vias:
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Used vias:
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- 0.6/0.3 mm (24/12 mils) (Count: 242, Aspect: 2.7 A) defined: no
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Holes (excluding vias):
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- 0.8 mm (31 mils) (16)
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- 1.0 mm (39 mils) (12)
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- 1.3 mm (51 mils) (9)
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- 1.5 mm (59 mils) (10)
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- 2.4 mm (94 mils) (2)
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- 3.2 mm (126 mils) (3)
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Oval holes:
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- 0.65x1.15 mm (26x45 mils) (2)
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- 0.65x1.55 mm (26x61 mils) (2)
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Drill tools (including vias and computing adjusts and rounding):
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- 0.4 mm (16 mils) (242)
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- 0.75 mm (30 mils) (4)
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- 0.9 mm (35 mils) (16)
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- 1.1 mm (43 mils) (12)
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- 1.4 mm (55 mils) (9)
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- 1.6 mm (63 mils) (10)
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- 2.4 mm (94 mils) (2)
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- 3.3 mm (130 mils) (3)
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Solder paste stats:
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Using a paste with 87.75 % alloy, that has an specific gravity for the alloy of 7.4 g/cm³
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and 1.0 g/cm³ for the flux. This paste has an specific gravity of 4.15 g/cm³.
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The stencil thickness is 0.12 mm.
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| Side | Pads with paste | Area [mm²] | Paste [g] |
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|--------|-----------------|------------|-----------|
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| Top | 284 | 308.02 | 1.53 |
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| Bottom | 53 | 69.05 | 0.34 |
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| Total | 337 | 377.08 | 1.88 |
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Note: this is just an approximation to the theoretical value. Margins of the solder mask and waste aren't computed.
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# Schematic
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{ width=16.5cm height=11.7cm }
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# PCB Layers
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{ width=16.5cm height=11.7cm }
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