chore: update deployed documentation
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@@ -1,5 +1,5 @@
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Drill report for c64psu.kicad_pcb
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Created on 2025-10-07T10:16:08+0000
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Created on 2025-10-08T10:55:13+0000
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Copper Layer Stackup:
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=============================================================
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@@ -12,14 +12,16 @@ Copper Layer Stackup:
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Drill file 'c64psu-PTH.drl' contains
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plated through holes:
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=============================================================
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T1 0.300mm 0.0118" (179 holes)
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T2 0.650mm 0.0256" (4 holes) (with 4 slots)
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T3 0.800mm 0.0315" (12 holes)
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T4 1.300mm 0.0512" (9 holes)
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T5 1.500mm 0.0591" (10 holes)
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T6 3.200mm 0.1260" (3 holes)
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T1 0.300mm 0.0118" (133 holes)
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T2 0.500mm 0.0197" (4 holes)
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T3 0.650mm 0.0256" (4 holes) (with 4 slots)
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T4 0.800mm 0.0315" (16 holes)
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T5 1.000mm 0.0394" (12 holes)
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T6 1.300mm 0.0512" (9 holes)
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T7 1.500mm 0.0591" (10 holes)
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T8 3.200mm 0.1260" (3 holes)
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Total plated holes count 217
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Total plated holes count 191
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Drill file 'c64psu-NPTH.drl' contains
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