mob next [ci-skip] [ci skip] [skip ci]
lastFile:routers/yada-house/device.nix
This commit is contained in:
54
routers/yada-house/configuration.nix
Normal file
54
routers/yada-house/configuration.nix
Normal file
@@ -0,0 +1,54 @@
|
||||
{ inputs }:
|
||||
|
||||
{
|
||||
config,
|
||||
pkgs,
|
||||
...
|
||||
}:
|
||||
let
|
||||
svc = config.system.service;
|
||||
|
||||
in
|
||||
rec {
|
||||
imports = [
|
||||
"${inputs.liminix}/modules/network"
|
||||
"${inputs.liminix}/modules/dnsmasq"
|
||||
"${inputs.liminix}/modules/ssh"
|
||||
];
|
||||
|
||||
hostname = "hello";
|
||||
|
||||
# configure the internal network (LAN) with an address
|
||||
services.int = svc.network.address.build {
|
||||
interface = config.hardware.networkInterfaces.lan2;
|
||||
family = "inet";
|
||||
address = "192.168.8.1";
|
||||
prefixLength = 24;
|
||||
};
|
||||
|
||||
services.sshd = svc.ssh.build { };
|
||||
|
||||
users.root = {
|
||||
# the password is "secret". Use mkpasswd -m sha512crypt to
|
||||
# create this hashed password string
|
||||
passwd = "$6$y7WZ5hM6l5nriLmo$5AJlmzQZ6WA.7uBC7S8L4o19ESR28Dg25v64/vDvvCN01Ms9QoHeGByj8lGlJ4/b.dbwR9Hq2KXurSnLigt1W1";
|
||||
};
|
||||
|
||||
services.dns =
|
||||
let
|
||||
interface = services.int;
|
||||
in
|
||||
svc.dnsmasq.build {
|
||||
inherit interface;
|
||||
ranges = [
|
||||
"192.168.8.1,192.168.8.240"
|
||||
"::,constructor:$(output ${interface} ifname),ra-stateless"
|
||||
];
|
||||
|
||||
domain = "example.org";
|
||||
};
|
||||
|
||||
# defaultProfile.packages = with pkgs; [
|
||||
# figlet
|
||||
# ];
|
||||
}
|
||||
127
routers/yada-house/device.nix
Normal file
127
routers/yada-house/device.nix
Normal file
@@ -0,0 +1,127 @@
|
||||
# GL.iNet GL-MT6000
|
||||
{ inputs }:
|
||||
{
|
||||
system = {
|
||||
crossSystem = {
|
||||
config = "aarch64-unknown-linux-musl";
|
||||
gcc = {
|
||||
arch = "armv8-a";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
description = ''
|
||||
Device configuration for Yada/White house router.
|
||||
'';
|
||||
|
||||
module =
|
||||
{
|
||||
pkgs,
|
||||
config,
|
||||
lib,
|
||||
lim,
|
||||
...
|
||||
}:
|
||||
let
|
||||
inherit (pkgs) openwrt_24_10;
|
||||
# mac80211 = pkgs.kmodloader.override {
|
||||
# targets = [ "rt2800soc" ];
|
||||
# inherit (config.system.outputs) kernel;
|
||||
# };
|
||||
in
|
||||
{
|
||||
imports = [
|
||||
"${inputs.liminix}/modules/outputs/mtdimage.nix"
|
||||
"${inputs.liminix}/modules/outputs/squashfs.nix"
|
||||
"${inputs.liminix}/modules/outputs/tftpboot.nix"
|
||||
"${inputs.liminix}/modules/outputs/vmroot.nix"
|
||||
"${inputs.liminix}/modules/arch/aarch64.nix"
|
||||
# "${inputs.liminix}/modules/base.nix"
|
||||
"${inputs.liminix}/modules/vlan"
|
||||
];
|
||||
boot.tftp = {
|
||||
serverip = "192.168.1.254";
|
||||
ipaddr = "192.168.1.1";
|
||||
loadAddress = lim.parseInt "0x46000000";
|
||||
};
|
||||
boot.imageFormat = "fit";
|
||||
boot.loader.fit.enable = true;
|
||||
rootfsType = "squashfs";
|
||||
hardware = {
|
||||
loadAddress = lim.parseInt "0x48080000";
|
||||
entryPoint = lim.parseInt "0x48080000";
|
||||
|
||||
flash = {
|
||||
address = lim.parseInt "0x41e00000";
|
||||
size = lim.parseInt "0x4000";
|
||||
eraseBlockSize = 65536;
|
||||
};
|
||||
rootDevice = "/dev/root";
|
||||
|
||||
dts = {
|
||||
src = "${openwrt_24_10.src}/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts";
|
||||
includePaths = [
|
||||
"${openwrt_24_10.src}/target/linux/mediatek/dts"
|
||||
"${config.system.outputs.kernel.modulesupport}/arch/arm64/boot/dts/mediatek/"
|
||||
];
|
||||
};
|
||||
networkInterfaces =
|
||||
let
|
||||
inherit (config.system.service.network) link;
|
||||
inherit (config.system.service) vlan;
|
||||
in
|
||||
rec {
|
||||
eth0 = link.build { ifname = "eth0"; };
|
||||
wan = link.build { ifname = "eth1"; };
|
||||
|
||||
lan1 = vlan.build {
|
||||
ifname = "lan1@eth0";
|
||||
primary = eth0;
|
||||
vid = "1";
|
||||
};
|
||||
lan2 = vlan.build {
|
||||
ifname = "lan2@eth0";
|
||||
primary = eth0;
|
||||
vid = "2";
|
||||
};
|
||||
lan3 = vlan.build {
|
||||
ifname = "lan3@eth0";
|
||||
primary = eth0;
|
||||
vid = "3";
|
||||
};
|
||||
lan4 = vlan.build {
|
||||
ifname = "lan4@eth0";
|
||||
primary = eth0;
|
||||
vid = "4";
|
||||
};
|
||||
lan5 = vlan.build {
|
||||
ifname = "lan5@eth0";
|
||||
primary = eth0;
|
||||
vid = "5";
|
||||
};
|
||||
|
||||
# wlan = link.build {
|
||||
# ifname = "wlan0";
|
||||
# dependencies = [ mac80211 ];
|
||||
# };
|
||||
};
|
||||
};
|
||||
|
||||
kernel = {
|
||||
src = openwrt_24_10.kernelSrc;
|
||||
version = openwrt_24_10.kernelVersion;
|
||||
extraPatchPhase = ''
|
||||
echo ==================================================
|
||||
ls ${openwrt_24_10.src}/config
|
||||
echo ==================================================
|
||||
patch ${openwrt_24_10.src}/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch
|
||||
echo --------------------------------------------------
|
||||
ls ${openwrt_24_10.src}/config
|
||||
echo --------------------------------------------------
|
||||
${openwrt_24_10.applyPatches.mediatek}
|
||||
'';
|
||||
config = {
|
||||
};
|
||||
};
|
||||
};
|
||||
}
|
||||
645
routers/yada-house/dts/mt7986a.dtsi
Normal file
645
routers/yada-house/dts/mt7986a.dtsi
Normal file
@@ -0,0 +1,645 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
|
||||
/*
|
||||
* Copyright (C) 2021 MediaTek Inc.
|
||||
* Author: Sam.Shih <sam.shih@mediatek.com>
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/mt7986-clk.h>
|
||||
#include <dt-bindings/reset/mt7986-resets.h>
|
||||
#include <dt-bindings/phy/phy.h>
|
||||
|
||||
/ {
|
||||
compatible = "mediatek,mt7986a";
|
||||
interrupt-parent = <&gic>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x0>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x1>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x2>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a53";
|
||||
reg = <0x3>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
#cooling-cells = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
clk40m: oscillator-40m {
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <40000000>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "clkxtal";
|
||||
};
|
||||
|
||||
psci {
|
||||
compatible = "arm,psci-0.2";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
/* 192 KiB reserved for ARM Trusted Firmware (BL31) */
|
||||
secmon_reserved: secmon@43000000 {
|
||||
reg = <0 0x43000000 0 0x30000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wmcpu_emi: wmcpu-reserved@4fc00000 {
|
||||
no-map;
|
||||
reg = <0 0x4fc00000 0 0x00100000>;
|
||||
};
|
||||
|
||||
wo_emi0: wo-emi@4fd00000 {
|
||||
reg = <0 0x4fd00000 0 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wo_emi1: wo-emi@4fd40000 {
|
||||
reg = <0 0x4fd40000 0 0x40000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wo_ilm0: wo-ilm@151e0000 {
|
||||
reg = <0 0x151e0000 0 0x8000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wo_ilm1: wo-ilm@151f0000 {
|
||||
reg = <0 0x151f0000 0 0x8000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wo_data: wo-data@4fd80000 {
|
||||
reg = <0 0x4fd80000 0 0x240000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wo_dlm0: wo-dlm@151e8000 {
|
||||
reg = <0 0x151e8000 0 0x2000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wo_dlm1: wo-dlm@151f8000 {
|
||||
reg = <0 0x151f8000 0 0x2000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
wo_boot: wo-boot@15194000 {
|
||||
reg = <0 0x15194000 0 0x1000>;
|
||||
no-map;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
gic: interrupt-controller@c000000 {
|
||||
compatible = "arm,gic-v3";
|
||||
reg = <0 0x0c000000 0 0x10000>, /* GICD */
|
||||
<0 0x0c080000 0 0x80000>, /* GICR */
|
||||
<0 0x0c400000 0 0x2000>, /* GICC */
|
||||
<0 0x0c410000 0 0x1000>, /* GICH */
|
||||
<0 0x0c420000 0 0x2000>; /* GICV */
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
};
|
||||
|
||||
infracfg: infracfg@10001000 {
|
||||
compatible = "mediatek,mt7986-infracfg", "syscon";
|
||||
reg = <0 0x10001000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
wed_pcie: wed-pcie@10003000 {
|
||||
compatible = "mediatek,mt7986-wed-pcie",
|
||||
"syscon";
|
||||
reg = <0 0x10003000 0 0x10>;
|
||||
};
|
||||
|
||||
topckgen: topckgen@1001b000 {
|
||||
compatible = "mediatek,mt7986-topckgen", "syscon";
|
||||
reg = <0 0x1001B000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
watchdog: watchdog@1001c000 {
|
||||
compatible = "mediatek,mt7986-wdt";
|
||||
reg = <0 0x1001c000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
||||
#reset-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
apmixedsys: apmixedsys@1001e000 {
|
||||
compatible = "mediatek,mt7986-apmixedsys";
|
||||
reg = <0 0x1001E000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
pio: pinctrl@1001f000 {
|
||||
compatible = "mediatek,mt7986a-pinctrl";
|
||||
reg = <0 0x1001f000 0 0x1000>,
|
||||
<0 0x11c30000 0 0x1000>,
|
||||
<0 0x11c40000 0 0x1000>,
|
||||
<0 0x11e20000 0 0x1000>,
|
||||
<0 0x11e30000 0 0x1000>,
|
||||
<0 0x11f00000 0 0x1000>,
|
||||
<0 0x11f10000 0 0x1000>,
|
||||
<0 0x1000b000 0 0x1000>;
|
||||
reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt",
|
||||
"iocfg_lb", "iocfg_tr", "iocfg_tl", "eint";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
gpio-ranges = <&pio 0 0 100>;
|
||||
interrupt-controller;
|
||||
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&gic>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
pwm: pwm@10048000 {
|
||||
compatible = "mediatek,mt7986-pwm";
|
||||
reg = <0 0x10048000 0 0x1000>;
|
||||
#pwm-cells = <2>;
|
||||
interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_PWM_SEL>,
|
||||
<&infracfg CLK_INFRA_PWM_STA>,
|
||||
<&infracfg CLK_INFRA_PWM1_CK>,
|
||||
<&infracfg CLK_INFRA_PWM2_CK>;
|
||||
clock-names = "top", "main", "pwm1", "pwm2";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sgmiisys0: syscon@10060000 {
|
||||
compatible = "mediatek,mt7986-sgmiisys_0",
|
||||
"syscon";
|
||||
reg = <0 0x10060000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
sgmiisys1: syscon@10070000 {
|
||||
compatible = "mediatek,mt7986-sgmiisys_1",
|
||||
"syscon";
|
||||
reg = <0 0x10070000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
|
||||
trng: rng@1020f000 {
|
||||
compatible = "mediatek,mt7986-rng",
|
||||
"mediatek,mt7623-rng";
|
||||
reg = <0 0x1020f000 0 0x100>;
|
||||
clocks = <&infracfg CLK_INFRA_TRNG_CK>;
|
||||
clock-names = "rng";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
crypto: crypto@10320000 {
|
||||
compatible = "inside-secure,safexcel-eip97";
|
||||
reg = <0 0x10320000 0 0x40000>;
|
||||
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "ring0", "ring1", "ring2", "ring3";
|
||||
clocks = <&infracfg CLK_INFRA_EIP97_CK>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>;
|
||||
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart0: serial@11002000 {
|
||||
compatible = "mediatek,mt7986-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11002000 0 0x400>;
|
||||
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_UART0_SEL>,
|
||||
<&infracfg CLK_INFRA_UART0_CK>;
|
||||
clock-names = "baud", "bus";
|
||||
assigned-clocks = <&topckgen CLK_TOP_UART_SEL>,
|
||||
<&infracfg CLK_INFRA_UART0_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_XTAL>,
|
||||
<&topckgen CLK_TOP_UART_SEL>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@11003000 {
|
||||
compatible = "mediatek,mt7986-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11003000 0 0x400>;
|
||||
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_UART1_SEL>,
|
||||
<&infracfg CLK_INFRA_UART1_CK>;
|
||||
clock-names = "baud", "bus";
|
||||
assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@11004000 {
|
||||
compatible = "mediatek,mt7986-uart",
|
||||
"mediatek,mt6577-uart";
|
||||
reg = <0 0x11004000 0 0x400>;
|
||||
interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_UART2_SEL>,
|
||||
<&infracfg CLK_INFRA_UART2_CK>;
|
||||
clock-names = "baud", "bus";
|
||||
assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>;
|
||||
assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c0: i2c@11008000 {
|
||||
compatible = "mediatek,mt7986-i2c";
|
||||
reg = <0 0x11008000 0 0x90>,
|
||||
<0 0x10217080 0 0x80>;
|
||||
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clock-div = <5>;
|
||||
clocks = <&infracfg CLK_INFRA_I2C0_CK>,
|
||||
<&infracfg CLK_INFRA_AP_DMA_CK>;
|
||||
clock-names = "main", "dma";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi0: spi@1100a000 {
|
||||
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
||||
reg = <0 0x1100a000 0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_MPLL_D2>,
|
||||
<&topckgen CLK_TOP_SPI_SEL>,
|
||||
<&infracfg CLK_INFRA_SPI0_CK>,
|
||||
<&infracfg CLK_INFRA_SPI0_HCK_CK>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi1: spi@1100b000 {
|
||||
compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm";
|
||||
reg = <0 0x1100b000 0 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&topckgen CLK_TOP_MPLL_D2>,
|
||||
<&topckgen CLK_TOP_SPIM_MST_SEL>,
|
||||
<&infracfg CLK_INFRA_SPI1_CK>,
|
||||
<&infracfg CLK_INFRA_SPI1_HCK_CK>;
|
||||
clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
thermal: thermal@1100c800 {
|
||||
compatible = "mediatek,mt7986-thermal";
|
||||
reg = <0 0x1100c800 0 0x800>;
|
||||
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_THERM_CK>,
|
||||
<&infracfg CLK_INFRA_ADC_26M_CK>;
|
||||
clock-names = "therm", "auxadc";
|
||||
nvmem-cells = <&thermal_calibration>;
|
||||
nvmem-cell-names = "calibration-data";
|
||||
#thermal-sensor-cells = <1>;
|
||||
mediatek,auxadc = <&auxadc>;
|
||||
mediatek,apmixedsys = <&apmixedsys>;
|
||||
};
|
||||
|
||||
auxadc: adc@1100d000 {
|
||||
compatible = "mediatek,mt7986-auxadc";
|
||||
reg = <0 0x1100d000 0 0x1000>;
|
||||
clocks = <&infracfg CLK_INFRA_ADC_26M_CK>;
|
||||
clock-names = "main";
|
||||
#io-channel-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ssusb: usb@11200000 {
|
||||
compatible = "mediatek,mt7986-xhci",
|
||||
"mediatek,mtk-xhci";
|
||||
reg = <0 0x11200000 0 0x2e00>,
|
||||
<0 0x11203e00 0 0x0100>;
|
||||
reg-names = "mac", "ippc";
|
||||
interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>,
|
||||
<&infracfg CLK_INFRA_IUSB_CK>,
|
||||
<&infracfg CLK_INFRA_IUSB_133_CK>,
|
||||
<&infracfg CLK_INFRA_IUSB_66M_CK>,
|
||||
<&topckgen CLK_TOP_U2U3_XHCI_SEL>;
|
||||
clock-names = "sys_ck",
|
||||
"ref_ck",
|
||||
"mcu_ck",
|
||||
"dma_ck",
|
||||
"xhci_ck";
|
||||
phys = <&u2port0 PHY_TYPE_USB2>,
|
||||
<&u3port0 PHY_TYPE_USB3>,
|
||||
<&u2port1 PHY_TYPE_USB2>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: mmc@11230000 {
|
||||
compatible = "mediatek,mt7986-mmc";
|
||||
reg = <0 0x11230000 0 0x1000>,
|
||||
<0 0x11c20000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
||||
assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
|
||||
<&topckgen CLK_TOP_EMMC_250M_SEL>;
|
||||
assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>,
|
||||
<&topckgen CLK_TOP_NET1PLL_D5_D2>;
|
||||
clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>,
|
||||
<&infracfg CLK_INFRA_MSDC_HCK_CK>,
|
||||
<&infracfg CLK_INFRA_MSDC_CK>,
|
||||
<&infracfg CLK_INFRA_MSDC_133M_CK>,
|
||||
<&infracfg CLK_INFRA_MSDC_66M_CK>;
|
||||
clock-names = "source", "hclk", "source_cg", "bus_clk",
|
||||
"sys_cg";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pcie: pcie@11280000 {
|
||||
compatible = "mediatek,mt7986-pcie",
|
||||
"mediatek,mt8192-pcie";
|
||||
reg = <0x00 0x11280000 0x00 0x4000>;
|
||||
reg-names = "pcie-mac";
|
||||
ranges = <0x82000000 0x00 0x20000000 0x00
|
||||
0x20000000 0x00 0x10000000>;
|
||||
device_type = "pci";
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
bus-range = <0x00 0xff>;
|
||||
clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>,
|
||||
<&infracfg CLK_INFRA_IPCIE_CK>,
|
||||
<&infracfg CLK_INFRA_IPCIER_CK>,
|
||||
<&infracfg CLK_INFRA_IPCIEB_CK>;
|
||||
clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m";
|
||||
|
||||
phys = <&pcie_port PHY_TYPE_PCIE>;
|
||||
phy-names = "pcie-phy";
|
||||
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-map-mask = <0 0 0 0x7>;
|
||||
interrupt-map = <0 0 0 1 &pcie_intc 0>,
|
||||
<0 0 0 2 &pcie_intc 1>,
|
||||
<0 0 0 3 &pcie_intc 2>,
|
||||
<0 0 0 4 &pcie_intc 3>;
|
||||
status = "disabled";
|
||||
|
||||
pcie_intc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
};
|
||||
};
|
||||
|
||||
pcie_phy: t-phy {
|
||||
compatible = "mediatek,mt7986-tphy",
|
||||
"mediatek,generic-tphy-v2";
|
||||
ranges;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
status = "disabled";
|
||||
|
||||
pcie_port: pcie-phy@11c00000 {
|
||||
reg = <0 0x11c00000 0 0x20000>;
|
||||
clocks = <&clk40m>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
efuse: efuse@11d00000 {
|
||||
compatible = "mediatek,mt7986-efuse", "mediatek,efuse";
|
||||
reg = <0 0x11d00000 0 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
thermal_calibration: calib@274 {
|
||||
reg = <0x274 0xc>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_phy: t-phy@11e10000 {
|
||||
compatible = "mediatek,mt7986-tphy",
|
||||
"mediatek,generic-tphy-v2";
|
||||
ranges = <0 0 0x11e10000 0x1700>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
|
||||
u2port0: usb-phy@0 {
|
||||
reg = <0x0 0x700>;
|
||||
clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
|
||||
<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
|
||||
clock-names = "ref", "da_ref";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
u3port0: usb-phy@700 {
|
||||
reg = <0x700 0x900>;
|
||||
clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>;
|
||||
clock-names = "ref";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
|
||||
u2port1: usb-phy@1000 {
|
||||
reg = <0x1000 0x700>;
|
||||
clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>,
|
||||
<&topckgen CLK_TOP_DA_U2_CK_1P_SEL>;
|
||||
clock-names = "ref", "da_ref";
|
||||
#phy-cells = <1>;
|
||||
};
|
||||
};
|
||||
|
||||
ethsys: syscon@15000000 {
|
||||
compatible = "mediatek,mt7986-ethsys",
|
||||
"syscon";
|
||||
reg = <0 0x15000000 0 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
#reset-cells = <1>;
|
||||
};
|
||||
|
||||
wed0: wed@15010000 {
|
||||
compatible = "mediatek,mt7986-wed",
|
||||
"syscon";
|
||||
reg = <0 0x15010000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
|
||||
memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>,
|
||||
<&wo_data>, <&wo_boot>;
|
||||
memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
|
||||
"wo-data", "wo-boot";
|
||||
mediatek,wo-ccif = <&wo_ccif0>;
|
||||
};
|
||||
|
||||
wed1: wed@15011000 {
|
||||
compatible = "mediatek,mt7986-wed",
|
||||
"syscon";
|
||||
reg = <0 0x15011000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
|
||||
memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>,
|
||||
<&wo_data>, <&wo_boot>;
|
||||
memory-region-names = "wo-emi", "wo-ilm", "wo-dlm",
|
||||
"wo-data", "wo-boot";
|
||||
mediatek,wo-ccif = <&wo_ccif1>;
|
||||
};
|
||||
|
||||
eth: ethernet@15100000 {
|
||||
compatible = "mediatek,mt7986-eth";
|
||||
reg = <0 0x15100000 0 0x80000>;
|
||||
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <ðsys CLK_ETH_FE_EN>,
|
||||
<ðsys CLK_ETH_GP2_EN>,
|
||||
<ðsys CLK_ETH_GP1_EN>,
|
||||
<ðsys CLK_ETH_WOCPU1_EN>,
|
||||
<ðsys CLK_ETH_WOCPU0_EN>,
|
||||
<&sgmiisys0 CLK_SGMII0_TX250M_EN>,
|
||||
<&sgmiisys0 CLK_SGMII0_RX250M_EN>,
|
||||
<&sgmiisys0 CLK_SGMII0_CDR_REF>,
|
||||
<&sgmiisys0 CLK_SGMII0_CDR_FB>,
|
||||
<&sgmiisys1 CLK_SGMII1_TX250M_EN>,
|
||||
<&sgmiisys1 CLK_SGMII1_RX250M_EN>,
|
||||
<&sgmiisys1 CLK_SGMII1_CDR_REF>,
|
||||
<&sgmiisys1 CLK_SGMII1_CDR_FB>,
|
||||
<&topckgen CLK_TOP_NETSYS_SEL>,
|
||||
<&topckgen CLK_TOP_NETSYS_500M_SEL>;
|
||||
clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
|
||||
"sgmii_tx250m", "sgmii_rx250m",
|
||||
"sgmii_cdr_ref", "sgmii_cdr_fb",
|
||||
"sgmii2_tx250m", "sgmii2_rx250m",
|
||||
"sgmii2_cdr_ref", "sgmii2_cdr_fb",
|
||||
"netsys0", "netsys1";
|
||||
assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
|
||||
<&topckgen CLK_TOP_SGM_325M_SEL>;
|
||||
assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
|
||||
<&apmixedsys CLK_APMIXED_SGMPLL>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
mediatek,ethsys = <ðsys>;
|
||||
mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
|
||||
mediatek,wed-pcie = <&wed_pcie>;
|
||||
mediatek,wed = <&wed0>, <&wed1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
wo_ccif0: syscon@151a5000 {
|
||||
compatible = "mediatek,mt7986-wo-ccif", "syscon";
|
||||
reg = <0 0x151a5000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wo_ccif1: syscon@151ad000 {
|
||||
compatible = "mediatek,mt7986-wo-ccif", "syscon";
|
||||
reg = <0 0x151ad000 0 0x1000>;
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
wifi: wifi@18000000 {
|
||||
compatible = "mediatek,mt7986-wmac";
|
||||
reg = <0 0x18000000 0 0x1000000>,
|
||||
<0 0x10003000 0 0x1000>,
|
||||
<0 0x11d10000 0 0x1000>;
|
||||
resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>;
|
||||
reset-names = "consys";
|
||||
clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>,
|
||||
<&topckgen CLK_TOP_AP2CNN_HOST_SEL>;
|
||||
clock-names = "mcu", "ap2conn";
|
||||
interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
|
||||
memory-region = <&wmcpu_emi>;
|
||||
};
|
||||
};
|
||||
|
||||
thermal-zones {
|
||||
cpu_thermal: cpu-thermal {
|
||||
polling-delay-passive = <1000>;
|
||||
polling-delay = <1000>;
|
||||
thermal-sensors = <&thermal 0>;
|
||||
|
||||
trips {
|
||||
cpu_trip_crit: crit {
|
||||
temperature = <125000>;
|
||||
hysteresis = <2000>;
|
||||
type = "critical";
|
||||
};
|
||||
|
||||
cpu_trip_hot: hot {
|
||||
temperature = <120000>;
|
||||
hysteresis = <2000>;
|
||||
type = "hot";
|
||||
};
|
||||
|
||||
cpu_trip_active_high: active-high {
|
||||
temperature = <115000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
cpu_trip_active_med: active-med {
|
||||
temperature = <85000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
|
||||
cpu_trip_active_low: active-low {
|
||||
temperature = <60000>;
|
||||
hysteresis = <2000>;
|
||||
type = "active";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
timer {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupt-parent = <&gic>;
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
};
|
||||
2100
routers/yada-house/kconf-from-device.txt
Normal file
2100
routers/yada-house/kconf-from-device.txt
Normal file
File diff suppressed because it is too large
Load Diff
103
routers/yada-house/kconf-from-openwrt.txt
Normal file
103
routers/yada-house/kconf-from-openwrt.txt
Normal file
@@ -0,0 +1,103 @@
|
||||
ARM="y";
|
||||
SYS_HAS_NONCACHED_MEMORY="y";
|
||||
POSITION_INDEPENDENT="y";
|
||||
ARCH_MEDIATEK="y";
|
||||
TEXT_BASE="0x41e00000";
|
||||
SYS_MALLOC_F_LEN="0x4000";
|
||||
NR_DRAM_BANKS="1";
|
||||
ENV_SIZE="0x80000";
|
||||
ENV_OFFSET="0x400000";
|
||||
DEFAULT_DEVICE_TREE="mt7986a-glinet-gl-mt6000";
|
||||
OF_LIBFDT_OVERLAY="y";
|
||||
TARGET_MT7986="y";
|
||||
SYS_LOAD_ADDR="0x46000000";
|
||||
PRE_CON_BUF_ADDR="0x4007EF00";
|
||||
DEBUG_UART_BASE="0x11002000";
|
||||
DEBUG_UART_CLOCK="40000000";
|
||||
DEBUG_UART="y";
|
||||
AHCI="y";
|
||||
FIT="y";
|
||||
AUTOBOOT_KEYED="y";
|
||||
AUTOBOOT_MENU_SHOW="y";
|
||||
DEFAULT_FDT_FILE="mediatek/mt7986a-glinet-gl-mt6000.dtb";
|
||||
LOGLEVEL="7";
|
||||
PRE_CONSOLE_BUFFER="y";
|
||||
LOG="y";
|
||||
BOARD_LATE_INIT="y";
|
||||
HUSH_PARSER="y";
|
||||
SYS_PROMPT="MT7986> ";
|
||||
CMD_CPU="y";
|
||||
CMD_LICENSE="y";
|
||||
CMD_BOOTMENU="y";
|
||||
CMD_ASKENV="y";
|
||||
CMD_ERASEENV="y";
|
||||
CMD_ENV_FLAGS="y";
|
||||
CMD_STRINGS="y";
|
||||
CMD_DM="y";
|
||||
CMD_GPIO="y";
|
||||
CMD_PWM="y";
|
||||
CMD_GPT="y";
|
||||
CMD_MMC="y";
|
||||
CMD_PART="y";
|
||||
CMD_USB="y";
|
||||
CMD_TFTPSRV="y";
|
||||
CMD_RARP="y";
|
||||
CMD_CDP="y";
|
||||
CMD_SNTP="y";
|
||||
CMD_LINK_LOCAL="y";
|
||||
CMD_DHCP="y";
|
||||
CMD_DNS="y";
|
||||
CMD_PING="y";
|
||||
CMD_CACHE="y";
|
||||
CMD_PSTORE="y";
|
||||
CMD_PSTORE_MEM_ADDR="0x42ff0000";
|
||||
CMD_UUID="y";
|
||||
CMD_HASH="y";
|
||||
CMD_SMC="y";
|
||||
OF_EMBED="y";
|
||||
ENV_OVERWRITE="y";
|
||||
ENV_IS_IN_MMC="y";
|
||||
SYS_RELOC_GD_ENV_ADDR="y";
|
||||
USE_DEFAULT_ENV_FILE="y";
|
||||
DEFAULT_ENV_FILE="defenvs/glinet_gl-mt6000_env";
|
||||
ENV_VARS_UBOOT_RUNTIME_CONFIG="y";
|
||||
VERSION_VARIABLE="y";
|
||||
NETCONSOLE="y";
|
||||
USE_IPADDR="y";
|
||||
IPADDR="192.168.1.1";
|
||||
USE_SERVERIP="y";
|
||||
SERVERIP="192.168.1.254";
|
||||
NET_RANDOM_ETHADDR="y";
|
||||
BUTTON="y";
|
||||
BUTTON_GPIO="y";
|
||||
CLK="y";
|
||||
GPIO_HOG="y";
|
||||
LED="y";
|
||||
LED_BLINK="y";
|
||||
LED_GPIO="y";
|
||||
SUPPORT_EMMC_BOOT="y";
|
||||
MMC_HS200_SUPPORT="y";
|
||||
MMC_MTK="y";
|
||||
PHY_FIXED="y";
|
||||
MEDIATEK_ETH="y";
|
||||
PHY="y";
|
||||
PHY_MTK_TPHY="y";
|
||||
PINCTRL="y";
|
||||
PINCONF="y";
|
||||
PINCTRL_MT7986="y";
|
||||
POWER_DOMAIN="y";
|
||||
MTK_POWER_DOMAIN="y";
|
||||
DM_REGULATOR="y";
|
||||
DM_REGULATOR_FIXED="y";
|
||||
DM_REGULATOR_GPIO="y";
|
||||
DM_PWM="y";
|
||||
PWM_MTK="y";
|
||||
RAM="y";
|
||||
DM_SERIAL="y";
|
||||
SERIAL_RX_BUFFER="y";
|
||||
MTK_SERIAL="y";
|
||||
USB="y";
|
||||
USB_XHCI_HCD="y";
|
||||
USB_XHCI_MTK="y";
|
||||
USB_STORAGE="y";
|
||||
HEXDUMP="y";
|
||||
356
routers/yada-house/mt7986a-glinet-gl-mt6000.dts
Normal file
356
routers/yada-house/mt7986a-glinet-gl-mt6000.dts
Normal file
@@ -0,0 +1,356 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
||||
|
||||
/dts-v1/;
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/pinctrl/mt65xx.h>
|
||||
|
||||
#include "mt7986a.dtsi"
|
||||
|
||||
/ {
|
||||
model = "GL.iNet GL-MT6000";
|
||||
compatible = "glinet,gl-mt6000", "mediatek,mt7986a";
|
||||
|
||||
aliases {
|
||||
serial0 = &uart0;
|
||||
label-mac-device = &gmac1;
|
||||
led-boot = &led_blue;
|
||||
led-failsafe = &led_blue;
|
||||
led-running = &led_white;
|
||||
led-upgrade = &led_white;
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = "serial0:115200n8";
|
||||
bootargs-append = " root=PARTLABEL=rootfs rootwait";
|
||||
};
|
||||
|
||||
reg_1p8v: regulator-1p8v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "1.8vd";
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
reg_3p3v: regulator-3p3v {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "fixed-3.3V";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
reset {
|
||||
label = "reset";
|
||||
linux,code = <KEY_RESTART>;
|
||||
gpios = <&pio 9 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led_blue: led-0 {
|
||||
label = "blue:run";
|
||||
gpios = <&pio 38 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
led_white: led-1 {
|
||||
label = "white:system";
|
||||
gpios = <&pio 37 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
};
|
||||
|
||||
usb_vbus: regulator-usb-vbus {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "usb_vbus";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
gpios = <&pio 24 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
regulator-boot-on;
|
||||
};
|
||||
};
|
||||
|
||||
ð {
|
||||
status = "okay";
|
||||
|
||||
gmac0: mac@0 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <0>;
|
||||
phy-mode = "2500base-x";
|
||||
nvmem-cells = <&macaddr_factory_a 2>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
|
||||
gmac1: mac@1 {
|
||||
compatible = "mediatek,eth-mac";
|
||||
reg = <1>;
|
||||
nvmem-cells = <&macaddr_factory_a 0>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
phy-mode = "2500base-x";
|
||||
phy-handle = <&phy1>;
|
||||
};
|
||||
|
||||
mdio: mdio-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
phy1: phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <1>;
|
||||
reset-assert-us = <100000>;
|
||||
reset-deassert-us = <100000>;
|
||||
reset-gpios = <&pio 10 GPIO_ACTIVE_LOW>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <46 IRQ_TYPE_LEVEL_LOW>;
|
||||
realtek,aldps-enable;
|
||||
};
|
||||
|
||||
phy7: ethernet-phy@7 {
|
||||
compatible = "ethernet-phy-ieee802.3-c45";
|
||||
reg = <7>;
|
||||
reset-assert-us = <100000>;
|
||||
reset-deassert-us = <100000>;
|
||||
reset-gpios = <&pio 19 GPIO_ACTIVE_LOW>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <47 IRQ_TYPE_LEVEL_LOW>;
|
||||
realtek,aldps-enable;
|
||||
};
|
||||
|
||||
switch: switch@1f {
|
||||
compatible = "mediatek,mt7531";
|
||||
reg = <31>;
|
||||
reset-gpios = <&pio 18 GPIO_ACTIVE_HIGH>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-parent = <&pio>;
|
||||
interrupts = <66 IRQ_TYPE_LEVEL_HIGH>;
|
||||
|
||||
ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
port@0 {
|
||||
reg = <0>;
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
reg = <1>;
|
||||
label = "lan3";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
reg = <2>;
|
||||
label = "lan4";
|
||||
};
|
||||
|
||||
port@3 {
|
||||
reg = <3>;
|
||||
label = "lan5";
|
||||
};
|
||||
|
||||
port@5 {
|
||||
reg = <5>;
|
||||
label = "lan1";
|
||||
phy-handle = <&phy7>;
|
||||
phy-mode = "2500base-x";
|
||||
};
|
||||
|
||||
port@6 {
|
||||
reg = <6>;
|
||||
ethernet = <&gmac0>;
|
||||
phy-mode = "2500base-x";
|
||||
|
||||
fixed-link {
|
||||
speed = <2500>;
|
||||
full-duplex;
|
||||
pause;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pio {
|
||||
wf_2g_5g_pins: wf_2g_5g-pins {
|
||||
mux {
|
||||
function = "wifi";
|
||||
groups = "wf_2g", "wf_5g";
|
||||
};
|
||||
conf {
|
||||
pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4",
|
||||
"WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6",
|
||||
"WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10",
|
||||
"WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1",
|
||||
"WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0",
|
||||
"WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8",
|
||||
"WF1_TOP_CLK", "WF1_TOP_DATA";
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_default: mmc0-pins {
|
||||
mux {
|
||||
function = "emmc";
|
||||
groups = "emmc_51";
|
||||
};
|
||||
conf-cmd-dat {
|
||||
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
|
||||
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
|
||||
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
|
||||
};
|
||||
conf-clk {
|
||||
pins = "EMMC_CK";
|
||||
drive-strength = <MTK_DRIVE_6mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
|
||||
};
|
||||
conf-ds {
|
||||
pins = "EMMC_DSL";
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
|
||||
};
|
||||
conf-rst {
|
||||
pins = "EMMC_RSTB";
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
|
||||
};
|
||||
};
|
||||
|
||||
mmc0_pins_uhs: mmc0-uhs-pins {
|
||||
mux {
|
||||
function = "emmc";
|
||||
groups = "emmc_51";
|
||||
};
|
||||
conf-cmd-dat {
|
||||
pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2",
|
||||
"EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5",
|
||||
"EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD";
|
||||
input-enable;
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
|
||||
};
|
||||
conf-clk {
|
||||
pins = "EMMC_CK";
|
||||
drive-strength = <MTK_DRIVE_6mA>;
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
|
||||
};
|
||||
conf-ds {
|
||||
pins = "EMMC_DSL";
|
||||
bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */
|
||||
};
|
||||
conf-rst {
|
||||
pins = "EMMC_RSTB";
|
||||
drive-strength = <MTK_DRIVE_4mA>;
|
||||
bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&crypto {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&ssusb {
|
||||
vusb33-supply = <®_3p3v>;
|
||||
vbus-supply = <&usb_vbus>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&trng {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart0 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usb_phy {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&watchdog {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wifi {
|
||||
nvmem-cells = <&eeprom_factory_0>;
|
||||
nvmem-cell-names = "eeprom";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&wf_2g_5g_pins>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mmc0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-names = "default", "state_uhs";
|
||||
pinctrl-0 = <&mmc0_pins_default>;
|
||||
pinctrl-1 = <&mmc0_pins_uhs>;
|
||||
bus-width = <8>;
|
||||
max-frequency = <200000000>;
|
||||
cap-mmc-highspeed;
|
||||
mmc-hs200-1_8v;
|
||||
mmc-hs400-1_8v;
|
||||
hs400-ds-delay = <0x14014>;
|
||||
vmmc-supply = <®_3p3v>;
|
||||
vqmmc-supply = <®_1p8v>;
|
||||
non-removable;
|
||||
no-sd;
|
||||
no-sdio;
|
||||
status = "okay";
|
||||
|
||||
card@0 {
|
||||
compatible = "mmc-card";
|
||||
reg = <0>;
|
||||
|
||||
block {
|
||||
compatible = "block-device";
|
||||
partitions {
|
||||
block-partition-env {
|
||||
partname = "u-boot-env";
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "u-boot,env";
|
||||
};
|
||||
};
|
||||
|
||||
block-partition-factory {
|
||||
partname = "factory";
|
||||
|
||||
nvmem-layout {
|
||||
compatible = "fixed-layout";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
eeprom_factory_0: eeprom@0 {
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
|
||||
macaddr_factory_a: macaddr@a {
|
||||
compatible = "mac-base";
|
||||
reg = <0xa 0x6>;
|
||||
#nvmem-cell-cells = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
Reference in New Issue
Block a user