From d417eb0600a0bfdfe3ad970a6805da68259e2020 Mon Sep 17 00:00:00 2001 From: kurogeek Date: Fri, 10 Oct 2025 14:16:18 +0700 Subject: [PATCH] mob next [ci-skip] [ci skip] [skip ci] lastFile:routers/yada-house/device.nix --- .gitignore | 2 +- flake.lock | 14 + flake.nix | 23 + routers/default.nix | 1 + routers/qemu/configuration.nix | 49 + routers/qemu/device.nix | 58 + routers/vanilla/configuration.nix | 41 + routers/vanilla/device.nix | 86 + routers/yada-house/configuration.nix | 54 + routers/yada-house/device.nix | 127 + routers/yada-house/dts/mt7986a.dtsi | 645 +++++ routers/yada-house/kconf-from-device.txt | 2100 +++++++++++++++++ routers/yada-house/kconf-from-openwrt.txt | 103 + .../yada-house/mt7986a-glinet-gl-mt6000.dts | 356 +++ 14 files changed, 3658 insertions(+), 1 deletion(-) create mode 100644 routers/default.nix create mode 100644 routers/qemu/configuration.nix create mode 100644 routers/qemu/device.nix create mode 100644 routers/vanilla/configuration.nix create mode 100644 routers/vanilla/device.nix create mode 100644 routers/yada-house/configuration.nix create mode 100644 routers/yada-house/device.nix create mode 100644 routers/yada-house/dts/mt7986a.dtsi create mode 100644 routers/yada-house/kconf-from-device.txt create mode 100644 routers/yada-house/kconf-from-openwrt.txt create mode 100644 routers/yada-house/mt7986a-glinet-gl-mt6000.dts diff --git a/.gitignore b/.gitignore index a806510..3d03efb 100644 --- a/.gitignore +++ b/.gitignore @@ -2,4 +2,4 @@ # Ignore build outputs from performing a nix-build or `nix build` command result result-* - +run-vm-* diff --git a/flake.lock b/flake.lock index bff9901..2294b7e 100644 --- a/flake.lock +++ b/flake.lock @@ -136,6 +136,19 @@ "type": "github" } }, + "liminix": { + "flake": false, + "locked": { + "lastModified": 1758271851, + "narHash": "sha256-pfh+oahaVh1HVbZsz+ZM/+YV8FXnjMQ62dcRDUpzzPA=", + "path": "/home/kurogeek/Desktop/gitea/dan/liminix", + "type": "path" + }, + "original": { + "path": "/home/kurogeek/Desktop/gitea/dan/liminix", + "type": "path" + } + }, "nix-darwin": { "inputs": { "nixpkgs": [ @@ -207,6 +220,7 @@ "devshell": "devshell", "flake-parts": "flake-parts", "import-tree": "import-tree", + "liminix": "liminix", "nixpkgs": "nixpkgs", "treefmt-nix": "treefmt-nix" } diff --git a/flake.nix b/flake.nix index e475ff3..f4d140a 100644 --- a/flake.nix +++ b/flake.nix @@ -21,6 +21,11 @@ url = "github:numtide/treefmt-nix"; inputs.nixpkgs.follows = "nixpkgs"; }; + liminix = { + # url = "git+https://gti.telent.net/dan/liminix?ref=refs/heads/main&rev=cb43857ecf45feb0351023946f559e8e3343d12a"; + url = "path:/home/kurogeek/Desktop/gitea/dan/liminix"; + flake = false; + }; }; outputs = { @@ -33,6 +38,24 @@ systems = [ "x86_64-linux" ]; + + flake.legacyPackages.qemu-router = import "${inputs.liminix}/default.nix" { + liminix-config = import "${inputs.liminix}/examples/hello-from-qemu.nix"; + device = (import "${inputs.liminix}/devices/qemu-aarch64/default.nix"); + }; + flake.legacyPackages.yada-router = import "${inputs.liminix}/default.nix" { + liminix-config = import ./routers/yada-house/configuration.nix { inherit inputs; }; + device = (import ./routers/yada-house/device.nix { inherit inputs; }); + }; + flake.legacyPackages.qemu-flake = import "${inputs.liminix}/default.nix" { + liminix-config = import ./routers/qemu/configuration.nix { inherit inputs; }; + device = (import ./routers/qemu/device.nix { inherit inputs; }); + }; + flake.legacyPackages.vanilla = import "${inputs.liminix}/default.nix" { + liminix-config = import ./routers/vanilla/configuration.nix { inherit inputs; }; + device = (import "${inputs.liminix}/devices/gl-mt300a/default.nix"); + }; + imports = [ ./fmt.nix ./shell.nix diff --git a/routers/default.nix b/routers/default.nix new file mode 100644 index 0000000..ffcd441 --- /dev/null +++ b/routers/default.nix @@ -0,0 +1 @@ +{ } diff --git a/routers/qemu/configuration.nix b/routers/qemu/configuration.nix new file mode 100644 index 0000000..d11f1f0 --- /dev/null +++ b/routers/qemu/configuration.nix @@ -0,0 +1,49 @@ +{ inputs }: +{ config, pkgs, ... }: +let + svc = config.system.service; + +in +rec { + imports = [ + "${inputs.liminix}/modules/network" + "${inputs.liminix}/modules/dnsmasq" + "${inputs.liminix}/modules/ssh" + ]; + + hostname = "hello"; + + # configure the internal network (LAN) with an address + services.int = svc.network.address.build { + interface = config.hardware.networkInterfaces.lan; + family = "inet"; + address = "10.3.0.1"; + prefixLength = 16; + }; + + services.sshd = svc.ssh.build { }; + + users.root = { + # the password is "secret". Use mkpasswd -m sha512crypt to + # create this hashed password string + passwd = "$6$y7WZ5hM6l5nriLmo$5AJlmzQZ6WA.7uBC7S8L4o19ESR28Dg25v64/vDvvCN01Ms9QoHeGByj8lGlJ4/b.dbwR9Hq2KXurSnLigt1W1"; + }; + + services.dns = + let + interface = services.int; + in + svc.dnsmasq.build { + inherit interface; + ranges = [ + "10.3.0.10,10.3.0.240" + "::,constructor:$(output ${interface} ifname),ra-stateless" + ]; + + domain = "example.org"; + }; + + defaultProfile.packages = with pkgs; [ + figlet + ]; +} diff --git a/routers/qemu/device.nix b/routers/qemu/device.nix new file mode 100644 index 0000000..7e3bc0c --- /dev/null +++ b/routers/qemu/device.nix @@ -0,0 +1,58 @@ +# This "device" generates images that can be used with the QEMU +# emulator. The default output is a directory containing separate +# kernel ("Image" format) and root filesystem (squashfs or jffs2) +# images +{ inputs }: +{ + system = { + crossSystem = { + config = "aarch64-unknown-linux-musl"; + }; + }; + + description = '' + QEMU Aarch64 + ************ + + This target produces an image for + the `QEMU "virt" platform `_ using a 64 bit CPU type. + + ARM targets differ from MIPS in that the kernel format expected + by QEMU is an "Image" (raw binary file) rather than an ELF + file, but this is taken care of by :command:`run.sh`. Check the + documentation for the :ref:`qemu` target for more information. + + ''; + + # this device is described by the "qemu" device + installer = "vmroot"; + + module = + { config, lim, ... }: + { + imports = [ + "${inputs.liminix}/modules/arch/aarch64.nix" + "${inputs.liminix}/devices/families/qemu.nix" + ]; + kernel = { + config = { + VIRTUALIZATION = "y"; + PCI_HOST_GENERIC = "y"; + + SERIAL_AMBA_PL011 = "y"; + SERIAL_AMBA_PL011_CONSOLE = "y"; + }; + }; + boot.commandLine = [ + "console=ttyAMA0,38400" + ]; + hardware = + let + addr = lim.parseInt "0x40010000"; + in + { + loadAddress = addr; + entryPoint = addr; + }; + }; +} diff --git a/routers/vanilla/configuration.nix b/routers/vanilla/configuration.nix new file mode 100644 index 0000000..797f12f --- /dev/null +++ b/routers/vanilla/configuration.nix @@ -0,0 +1,41 @@ +{ inputs }: +{ config, pkgs, ... }: +let + inherit (pkgs.liminix.services) target; + svc = config.system.service; +in +rec { + imports = [ + "${inputs.liminix}/modules/wlan.nix" + "${inputs.liminix}/modules/network" + "${inputs.liminix}/modules/ntp" + "${inputs.liminix}/modules/vlan" + ]; + + services.dhcpv4 = + let + iface = svc.network.link.build { ifname = "eth1"; }; + in + svc.network.dhcp.client.build { interface = iface; }; + + services.defaultroute4 = svc.network.route.build { + via = "$(output ${services.dhcpv4} ip)"; + target = "default"; + dependencies = [ services.dhcpv4 ]; + }; + + services.packet_forwarding = svc.network.forward.build { }; + + services.ntp = config.system.service.ntp.build { + pools = { + "pool.ntp.org" = [ "iburst" ]; + }; + }; + + boot.tftp = { + serverip = "192.168.8.148"; + ipaddr = "192.168.8.251"; + }; + + defaultProfile.packages = [ pkgs.hello ]; +} diff --git a/routers/vanilla/device.nix b/routers/vanilla/device.nix new file mode 100644 index 0000000..5882447 --- /dev/null +++ b/routers/vanilla/device.nix @@ -0,0 +1,86 @@ +# This "device" generates images that can be used with the QEMU +# emulator. The default output is a directory containing separate +# kernel (uncompressed vmlinux) and initrd (squashfs) images +{ inputs }: +{ + system = { + crossSystem = { + config = "mips-unknown-linux-musl"; + gcc = { + abi = "32"; + arch = "mips32"; # maybe mips_24kc- + }; + }; + }; + + description = '' + QEMU MIPS + ********* + + This target produces an image for + QEMU, the "generic and open source machine emulator and + virtualizer". + + MIPS QEMU emulates a "Malta" board, which was an ATX form factor + evaluation board made by MIPS Technologies, but mostly in Liminix + we use paravirtualized devices (Virtio) instead of emulating + hardware. + + Building an image for QEMU results in a :file:`result/` directory + containing ``run.sh`` ``vmlinux``, and ``rootfs`` files. To invoke + the emulator, run ``run.sh``. + + The configuration includes two emulated "hardware" ethernet + devices and the kernel :code:`mac80211_hwsim` module to + provide an emulated wlan device. To read more about how + to connect to this network, refer to :ref:`qemu-networking` + in the Development manual. + + ''; + module = + { + config, + lib, + lim, + ... + }: + { + imports = [ + "${inputs.liminix}/modules/arch/mipseb.nix" + "${inputs.liminix}/devices/families/qemu.nix" + ]; + kernel = { + config = { + MIPS_MALTA = "y"; + CPU_MIPS32_R2 = "y"; + + POWER_RESET = "y"; + POWER_RESET_SYSCON = "y"; + + SERIAL_8250 = "y"; + SERIAL_8250_CONSOLE = "y"; + }; + }; + hardware = + # from arch/mips/mti-malta/Platform:load-$(CONFIG_MIPS_MALTA) += 0xffffffff80100000 + let + addr = lim.parseInt "0x80100000"; + in + { + loadAddress = addr; + entryPoint = addr; + + # Unlike the arm qemu targets, we need a static dts when + # running u-boot-using tests, qemu dumpdtb command doesn't + # work for this board. I am not at all sure this dts is + # *correct* but it does at least boot + dts = lib.mkForce { + src = "${config.system.outputs.kernel.modulesupport}/arch/mips/boot/dts/mti/malta.dts"; + includePaths = [ + "${config.system.outputs.kernel.modulesupport}/arch/mips/boot/dts/" + ]; + }; + + }; + }; +} diff --git a/routers/yada-house/configuration.nix b/routers/yada-house/configuration.nix new file mode 100644 index 0000000..bac08f0 --- /dev/null +++ b/routers/yada-house/configuration.nix @@ -0,0 +1,54 @@ +{ inputs }: + +{ + config, + pkgs, + ... +}: +let + svc = config.system.service; + +in +rec { + imports = [ + "${inputs.liminix}/modules/network" + "${inputs.liminix}/modules/dnsmasq" + "${inputs.liminix}/modules/ssh" + ]; + + hostname = "hello"; + + # configure the internal network (LAN) with an address + services.int = svc.network.address.build { + interface = config.hardware.networkInterfaces.lan2; + family = "inet"; + address = "192.168.8.1"; + prefixLength = 24; + }; + + services.sshd = svc.ssh.build { }; + + users.root = { + # the password is "secret". Use mkpasswd -m sha512crypt to + # create this hashed password string + passwd = "$6$y7WZ5hM6l5nriLmo$5AJlmzQZ6WA.7uBC7S8L4o19ESR28Dg25v64/vDvvCN01Ms9QoHeGByj8lGlJ4/b.dbwR9Hq2KXurSnLigt1W1"; + }; + + services.dns = + let + interface = services.int; + in + svc.dnsmasq.build { + inherit interface; + ranges = [ + "192.168.8.1,192.168.8.240" + "::,constructor:$(output ${interface} ifname),ra-stateless" + ]; + + domain = "example.org"; + }; + + # defaultProfile.packages = with pkgs; [ + # figlet + # ]; +} diff --git a/routers/yada-house/device.nix b/routers/yada-house/device.nix new file mode 100644 index 0000000..913d274 --- /dev/null +++ b/routers/yada-house/device.nix @@ -0,0 +1,127 @@ +# GL.iNet GL-MT6000 +{ inputs }: +{ + system = { + crossSystem = { + config = "aarch64-unknown-linux-musl"; + gcc = { + arch = "armv8-a"; + }; + }; + }; + + description = '' + Device configuration for Yada/White house router. + ''; + + module = + { + pkgs, + config, + lib, + lim, + ... + }: + let + inherit (pkgs) openwrt_24_10; + # mac80211 = pkgs.kmodloader.override { + # targets = [ "rt2800soc" ]; + # inherit (config.system.outputs) kernel; + # }; + in + { + imports = [ + "${inputs.liminix}/modules/outputs/mtdimage.nix" + "${inputs.liminix}/modules/outputs/squashfs.nix" + "${inputs.liminix}/modules/outputs/tftpboot.nix" + "${inputs.liminix}/modules/outputs/vmroot.nix" + "${inputs.liminix}/modules/arch/aarch64.nix" + # "${inputs.liminix}/modules/base.nix" + "${inputs.liminix}/modules/vlan" + ]; + boot.tftp = { + serverip = "192.168.1.254"; + ipaddr = "192.168.1.1"; + loadAddress = lim.parseInt "0x46000000"; + }; + boot.imageFormat = "fit"; + boot.loader.fit.enable = true; + rootfsType = "squashfs"; + hardware = { + loadAddress = lim.parseInt "0x48080000"; + entryPoint = lim.parseInt "0x48080000"; + + flash = { + address = lim.parseInt "0x41e00000"; + size = lim.parseInt "0x4000"; + eraseBlockSize = 65536; + }; + rootDevice = "/dev/root"; + + dts = { + src = "${openwrt_24_10.src}/target/linux/mediatek/dts/mt7986a-glinet-gl-mt6000.dts"; + includePaths = [ + "${openwrt_24_10.src}/target/linux/mediatek/dts" + "${config.system.outputs.kernel.modulesupport}/arch/arm64/boot/dts/mediatek/" + ]; + }; + networkInterfaces = + let + inherit (config.system.service.network) link; + inherit (config.system.service) vlan; + in + rec { + eth0 = link.build { ifname = "eth0"; }; + wan = link.build { ifname = "eth1"; }; + + lan1 = vlan.build { + ifname = "lan1@eth0"; + primary = eth0; + vid = "1"; + }; + lan2 = vlan.build { + ifname = "lan2@eth0"; + primary = eth0; + vid = "2"; + }; + lan3 = vlan.build { + ifname = "lan3@eth0"; + primary = eth0; + vid = "3"; + }; + lan4 = vlan.build { + ifname = "lan4@eth0"; + primary = eth0; + vid = "4"; + }; + lan5 = vlan.build { + ifname = "lan5@eth0"; + primary = eth0; + vid = "5"; + }; + + # wlan = link.build { + # ifname = "wlan0"; + # dependencies = [ mac80211 ]; + # }; + }; + }; + + kernel = { + src = openwrt_24_10.kernelSrc; + version = openwrt_24_10.kernelVersion; + extraPatchPhase = '' + echo ================================================== + ls ${openwrt_24_10.src}/config + echo ================================================== + patch ${openwrt_24_10.src}/package/boot/uboot-mediatek/patches/436-add-glinet-mt6000.patch + echo -------------------------------------------------- + ls ${openwrt_24_10.src}/config + echo -------------------------------------------------- + ${openwrt_24_10.applyPatches.mediatek} + ''; + config = { + }; + }; + }; +} diff --git a/routers/yada-house/dts/mt7986a.dtsi b/routers/yada-house/dts/mt7986a.dtsi new file mode 100644 index 0000000..559990d --- /dev/null +++ b/routers/yada-house/dts/mt7986a.dtsi @@ -0,0 +1,645 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt7986a"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu0: cpu@0 { + compatible = "arm,cortex-a53"; + reg = <0x0>; + device_type = "cpu"; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + compatible = "arm,cortex-a53"; + reg = <0x1>; + device_type = "cpu"; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + compatible = "arm,cortex-a53"; + reg = <0x2>; + device_type = "cpu"; + enable-method = "psci"; + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + compatible = "arm,cortex-a53"; + reg = <0x3>; + device_type = "cpu"; + enable-method = "psci"; + #cooling-cells = <2>; + }; + }; + + clk40m: oscillator-40m { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + #clock-cells = <0>; + clock-output-names = "clkxtal"; + }; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ + secmon_reserved: secmon@43000000 { + reg = <0 0x43000000 0 0x30000>; + no-map; + }; + + wmcpu_emi: wmcpu-reserved@4fc00000 { + no-map; + reg = <0 0x4fc00000 0 0x00100000>; + }; + + wo_emi0: wo-emi@4fd00000 { + reg = <0 0x4fd00000 0 0x40000>; + no-map; + }; + + wo_emi1: wo-emi@4fd40000 { + reg = <0 0x4fd40000 0 0x40000>; + no-map; + }; + + wo_ilm0: wo-ilm@151e0000 { + reg = <0 0x151e0000 0 0x8000>; + no-map; + }; + + wo_ilm1: wo-ilm@151f0000 { + reg = <0 0x151f0000 0 0x8000>; + no-map; + }; + + wo_data: wo-data@4fd80000 { + reg = <0 0x4fd80000 0 0x240000>; + no-map; + }; + + wo_dlm0: wo-dlm@151e8000 { + reg = <0 0x151e8000 0 0x2000>; + no-map; + }; + + wo_dlm1: wo-dlm@151f8000 { + reg = <0 0x151f8000 0 0x2000>; + no-map; + }; + + wo_boot: wo-boot@15194000 { + reg = <0 0x15194000 0 0x1000>; + no-map; + }; + + }; + + soc { + compatible = "simple-bus"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + reg = <0 0x0c000000 0 0x10000>, /* GICD */ + <0 0x0c080000 0 0x80000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + interrupt-parent = <&gic>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + }; + + infracfg: infracfg@10001000 { + compatible = "mediatek,mt7986-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + wed_pcie: wed-pcie@10003000 { + compatible = "mediatek,mt7986-wed-pcie", + "syscon"; + reg = <0 0x10003000 0 0x10>; + }; + + topckgen: topckgen@1001b000 { + compatible = "mediatek,mt7986-topckgen", "syscon"; + reg = <0 0x1001B000 0 0x1000>; + #clock-cells = <1>; + }; + + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = ; + #reset-cells = <1>; + status = "disabled"; + }; + + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7986-apmixedsys"; + reg = <0 0x1001E000 0 0x1000>; + #clock-cells = <1>; + }; + + pio: pinctrl@1001f000 { + compatible = "mediatek,mt7986a-pinctrl"; + reg = <0 0x1001f000 0 0x1000>, + <0 0x11c30000 0 0x1000>, + <0 0x11c40000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e30000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rb", "iocfg_lt", + "iocfg_lb", "iocfg_tr", "iocfg_tl", "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 100>; + interrupt-controller; + interrupts = ; + interrupt-parent = <&gic>; + #interrupt-cells = <2>; + }; + + pwm: pwm@10048000 { + compatible = "mediatek,mt7986-pwm"; + reg = <0 0x10048000 0 0x1000>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&infracfg CLK_INFRA_PWM_STA>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>; + clock-names = "top", "main", "pwm1", "pwm2"; + status = "disabled"; + }; + + sgmiisys0: syscon@10060000 { + compatible = "mediatek,mt7986-sgmiisys_0", + "syscon"; + reg = <0 0x10060000 0 0x1000>; + #clock-cells = <1>; + }; + + sgmiisys1: syscon@10070000 { + compatible = "mediatek,mt7986-sgmiisys_1", + "syscon"; + reg = <0 0x10070000 0 0x1000>; + #clock-cells = <1>; + }; + + trng: rng@1020f000 { + compatible = "mediatek,mt7986-rng", + "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x100>; + clocks = <&infracfg CLK_INFRA_TRNG_CK>; + clock-names = "rng"; + status = "disabled"; + }; + + crypto: crypto@10320000 { + compatible = "inside-secure,safexcel-eip97"; + reg = <0 0x10320000 0 0x40000>; + interrupts = , + , + , + ; + interrupt-names = "ring0", "ring1", "ring2", "ring3"; + clocks = <&infracfg CLK_INFRA_EIP97_CK>; + assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; + status = "disabled"; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART0_SEL>, + <&infracfg CLK_INFRA_UART0_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&topckgen CLK_TOP_UART_SEL>, + <&infracfg CLK_INFRA_UART0_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_XTAL>, + <&topckgen CLK_TOP_UART_SEL>; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART1_SEL>, + <&infracfg CLK_INFRA_UART1_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART1_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt7986-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x400>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_UART2_SEL>, + <&infracfg CLK_INFRA_UART2_CK>; + clock-names = "baud", "bus"; + assigned-clocks = <&infracfg CLK_INFRA_UART2_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_F26M_SEL>; + status = "disabled"; + }; + + i2c0: i2c@11008000 { + compatible = "mediatek,mt7986-i2c"; + reg = <0 0x11008000 0 0x90>, + <0 0x10217080 0 0x80>; + interrupts = ; + clock-div = <5>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@1100a000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x1100a000 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_INFRA_SPI0_CK>, + <&infracfg CLK_INFRA_SPI0_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + + spi1: spi@1100b000 { + compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + reg = <0 0x1100b000 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MPLL_D2>, + <&topckgen CLK_TOP_SPIM_MST_SEL>, + <&infracfg CLK_INFRA_SPI1_CK>, + <&infracfg CLK_INFRA_SPI1_HCK_CK>; + clock-names = "parent-clk", "sel-clk", "spi-clk", "hclk"; + status = "disabled"; + }; + + thermal: thermal@1100c800 { + compatible = "mediatek,mt7986-thermal"; + reg = <0 0x1100c800 0 0x800>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM_CK>, + <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "therm", "auxadc"; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + #thermal-sensor-cells = <1>; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + }; + + auxadc: adc@1100d000 { + compatible = "mediatek,mt7986-auxadc"; + reg = <0 0x1100d000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; + clock-names = "main"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + ssusb: usb@11200000 { + compatible = "mediatek,mt7986-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, + <&infracfg CLK_INFRA_IUSB_CK>, + <&infracfg CLK_INFRA_IUSB_133_CK>, + <&infracfg CLK_INFRA_IUSB_66M_CK>, + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; + clock-names = "sys_ck", + "ref_ck", + "mcu_ck", + "dma_ck", + "xhci_ck"; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u3port0 PHY_TYPE_USB3>, + <&u2port1 PHY_TYPE_USB2>; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt7986-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11c20000 0 0x1000>; + interrupts = ; + assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, + <&topckgen CLK_TOP_EMMC_250M_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>, + <&topckgen CLK_TOP_NET1PLL_D5_D2>; + clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, + <&infracfg CLK_INFRA_MSDC_HCK_CK>, + <&infracfg CLK_INFRA_MSDC_CK>, + <&infracfg CLK_INFRA_MSDC_133M_CK>, + <&infracfg CLK_INFRA_MSDC_66M_CK>; + clock-names = "source", "hclk", "source_cg", "bus_clk", + "sys_cg"; + status = "disabled"; + }; + + pcie: pcie@11280000 { + compatible = "mediatek,mt7986-pcie", + "mediatek,mt8192-pcie"; + reg = <0x00 0x11280000 0x00 0x4000>; + reg-names = "pcie-mac"; + ranges = <0x82000000 0x00 0x20000000 0x00 + 0x20000000 0x00 0x10000000>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + interrupts = ; + bus-range = <0x00 0xff>; + clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, + <&infracfg CLK_INFRA_IPCIE_CK>, + <&infracfg CLK_INFRA_IPCIER_CK>, + <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; + + phys = <&pcie_port PHY_TYPE_PCIE>; + phy-names = "pcie-phy"; + + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + status = "disabled"; + + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie_phy: t-phy { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + ranges; + #address-cells = <2>; + #size-cells = <2>; + status = "disabled"; + + pcie_port: pcie-phy@11c00000 { + reg = <0 0x11c00000 0 0x20000>; + clocks = <&clk40m>; + clock-names = "ref"; + #phy-cells = <1>; + }; + }; + + efuse: efuse@11d00000 { + compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; + reg = <0 0x11d00000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + thermal_calibration: calib@274 { + reg = <0x274 0xc>; + }; + }; + + usb_phy: t-phy@11e10000 { + compatible = "mediatek,mt7986-tphy", + "mediatek,generic-tphy-v2"; + ranges = <0 0 0x11e10000 0x1700>; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + + u2port0: usb-phy@0 { + reg = <0x0 0x700>; + clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, + <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x900>; + clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; + clock-names = "ref"; + #phy-cells = <1>; + }; + + u2port1: usb-phy@1000 { + reg = <0x1000 0x700>; + clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, + <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + }; + + ethsys: syscon@15000000 { + compatible = "mediatek,mt7986-ethsys", + "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + wed0: wed@15010000 { + compatible = "mediatek,mt7986-wed", + "syscon"; + reg = <0 0x15010000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + memory-region = <&wo_emi0>, <&wo_ilm0>, <&wo_dlm0>, + <&wo_data>, <&wo_boot>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", + "wo-data", "wo-boot"; + mediatek,wo-ccif = <&wo_ccif0>; + }; + + wed1: wed@15011000 { + compatible = "mediatek,mt7986-wed", + "syscon"; + reg = <0 0x15011000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + memory-region = <&wo_emi1>, <&wo_ilm1>, <&wo_dlm1>, + <&wo_data>, <&wo_boot>; + memory-region-names = "wo-emi", "wo-ilm", "wo-dlm", + "wo-data", "wo-boot"; + mediatek,wo-ccif = <&wo_ccif1>; + }; + + eth: ethernet@15100000 { + compatible = "mediatek,mt7986-eth"; + reg = <0 0x15100000 0 0x80000>; + interrupts = , + , + , + ; + clocks = <ðsys CLK_ETH_FE_EN>, + <ðsys CLK_ETH_GP2_EN>, + <ðsys CLK_ETH_GP1_EN>, + <ðsys CLK_ETH_WOCPU1_EN>, + <ðsys CLK_ETH_WOCPU0_EN>, + <&sgmiisys0 CLK_SGMII0_TX250M_EN>, + <&sgmiisys0 CLK_SGMII0_RX250M_EN>, + <&sgmiisys0 CLK_SGMII0_CDR_REF>, + <&sgmiisys0 CLK_SGMII0_CDR_FB>, + <&sgmiisys1 CLK_SGMII1_TX250M_EN>, + <&sgmiisys1 CLK_SGMII1_RX250M_EN>, + <&sgmiisys1 CLK_SGMII1_CDR_REF>, + <&sgmiisys1 CLK_SGMII1_CDR_FB>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>; + clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0", + "sgmii_tx250m", "sgmii_rx250m", + "sgmii_cdr_ref", "sgmii_cdr_fb", + "sgmii2_tx250m", "sgmii2_rx250m", + "sgmii2_cdr_ref", "sgmii2_cdr_fb", + "netsys0", "netsys1"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_SGM_325M_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + #address-cells = <1>; + #size-cells = <0>; + mediatek,ethsys = <ðsys>; + mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>; + mediatek,wed-pcie = <&wed_pcie>; + mediatek,wed = <&wed0>, <&wed1>; + status = "disabled"; + }; + + wo_ccif0: syscon@151a5000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151a5000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + wo_ccif1: syscon@151ad000 { + compatible = "mediatek,mt7986-wo-ccif", "syscon"; + reg = <0 0x151ad000 0 0x1000>; + interrupt-parent = <&gic>; + interrupts = ; + }; + + wifi: wifi@18000000 { + compatible = "mediatek,mt7986-wmac"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; + reset-names = "consys"; + clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, + <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; + clock-names = "mcu", "ap2conn"; + interrupts = , + , + , + ; + memory-region = <&wmcpu_emi>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; + polling-delay = <1000>; + thermal-sensors = <&thermal 0>; + + trips { + cpu_trip_crit: crit { + temperature = <125000>; + hysteresis = <2000>; + type = "critical"; + }; + + cpu_trip_hot: hot { + temperature = <120000>; + hysteresis = <2000>; + type = "hot"; + }; + + cpu_trip_active_high: active-high { + temperature = <115000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_med: active-med { + temperature = <85000>; + hysteresis = <2000>; + type = "active"; + }; + + cpu_trip_active_low: active-low { + temperature = <60000>; + hysteresis = <2000>; + type = "active"; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; +}; diff --git a/routers/yada-house/kconf-from-device.txt b/routers/yada-house/kconf-from-device.txt new file mode 100644 index 0000000..9a8f573 --- /dev/null +++ b/routers/yada-house/kconf-from-device.txt @@ -0,0 +1,2100 @@ + + CC_IS_GCC = "y"; + GCC_VERSION = "80400"; + CLANG_VERSION = "0"; + CC_CAN_LINK = "y"; + CC_HAS_ASM_GOTO = "y"; + CC_HAS_ASM_INLINE = "y"; + IRQ_WORK = "y"; + BUILDTIME_EXTABLE_SORT = "y"; + THREAD_INFO_IN_TASK = "y"; + INIT_ENV_ARG_LIMIT = "32"; + DEFAULT_HOSTNAME = "(none)"; + SWAP = "y"; + SYSVIPC = "y"; + SYSVIPC_SYSCTL = "y"; + POSIX_MQUEUE = "y"; + POSIX_MQUEUE_SYSCTL = "y"; + HAVE_ARCH_AUDITSYSCALL = "y"; + GENERIC_IRQ_PROBE = "y"; + GENERIC_IRQ_SHOW = "y"; + GENERIC_IRQ_SHOW_LEVEL = "y"; + GENERIC_IRQ_EFFECTIVE_AFF_MASK = "y"; + GENERIC_IRQ_MIGRATION = "y"; + HARDIRQS_SW_RESEND = "y"; + IRQ_DOMAIN = "y"; + IRQ_DOMAIN_HIERARCHY = "y"; + GENERIC_MSI_IRQ = "y"; + GENERIC_MSI_IRQ_DOMAIN = "y"; + HANDLE_DOMAIN_IRQ = "y"; + IRQ_FORCED_THREADING = "y"; + SPARSE_IRQ = "y"; + GENERIC_IRQ_MULTI_HANDLER = "y"; + ARCH_CLOCKSOURCE_DATA = "y"; + GENERIC_TIME_VSYSCALL = "y"; + GENERIC_CLOCKEVENTS = "y"; + ARCH_HAS_TICK_BROADCAST = "y"; + GENERIC_CLOCKEVENTS_BROADCAST = "y"; + TICK_ONESHOT = "y"; + NO_HZ_COMMON = "y"; + NO_HZ_IDLE = "y"; + HIGH_RES_TIMERS = "y"; + PREEMPT_NONE = "y"; + TICK_CPU_ACCOUNTING = "y"; + IRQ_TIME_ACCOUNTING = "y"; + HAVE_SCHED_AVG_IRQ = "y"; + BSD_PROCESS_ACCT = "y"; + BSD_PROCESS_ACCT_V3 = "y"; + TREE_RCU = "y"; + RCU_EXPERT = "y"; + SRCU = "y"; + TREE_SRCU = "y"; + RCU_STALL_COMMON = "y"; + RCU_NEED_SEGCBLIST = "y"; + RCU_FANOUT = "32"; + RCU_FANOUT_LEAF = "16"; + IKCONFIG = "y"; + IKCONFIG_PROC = "y"; + LOG_BUF_SHIFT = "17"; + LOG_CPU_MAX_BUF_SHIFT = "12"; + PRINTK_SAFE_LOG_BUF_SHIFT = "13"; + GENERIC_SCHED_CLOCK = "y"; + ARCH_SUPPORTS_NUMA_BALANCING = "y"; + ARCH_SUPPORTS_INT128 = "y"; + CGROUPS = "y"; + PAGE_COUNTER = "y"; + MEMCG = "y"; + MEMCG_SWAP = "y"; + MEMCG_KMEM = "y"; + BLK_CGROUP = "y"; + CGROUP_WRITEBACK = "y"; + CGROUP_SCHED = "y"; + FAIR_GROUP_SCHED = "y"; + CFS_BANDWIDTH = "y"; + RT_GROUP_SCHED = "y"; + CGROUP_PIDS = "y"; + CGROUP_RDMA = "y"; + CPUSETS = "y"; + CGROUP_CPUACCT = "y"; + CGROUP_BPF = "y"; + SOCK_CGROUP_DATA = "y"; + NAMESPACES = "y"; + UTS_NS = "y"; + IPC_NS = "y"; + USER_NS = "y"; + PID_NS = "y"; + NET_NS = "y"; + BLK_DEV_INITRD = "y"; + CC_OPTIMIZE_FOR_PERFORMANCE = "y"; + SYSCTL = "y"; + HAVE_UID16 = "y"; + SYSCTL_EXCEPTION_TRACE = "y"; + KALLSYMS_UNCOMPRESSED = "y"; + BPF = "y"; + EXPERT = "y"; + UID16 = "y"; + MULTIUSER = "y"; + FHANDLE = "y"; + POSIX_TIMERS = "y"; + PRINTK = "y"; + PRINTK_NMI = "y"; + BUG = "y"; + ELF_CORE = "y"; + BASE_FULL = "y"; + FUTEX = "y"; + FUTEX_PI = "y"; + EPOLL = "y"; + SIGNALFD = "y"; + TIMERFD = "y"; + EVENTFD = "y"; + SHMEM = "y"; + AIO = "y"; + IO_URING = "y"; + ADVISE_SYSCALLS = "y"; + MEMBARRIER = "y"; + KALLSYMS = "y"; + KALLSYMS_BASE_RELATIVE = "y"; + BPF_SYSCALL = "y"; + ARCH_HAS_MEMBARRIER_SYNC_CORE = "y"; + EMBEDDED = "y"; + HAVE_PERF_EVENTS = "y"; + SLUB = "y"; + SLAB_MERGE_DEFAULT = "y"; + SLUB_CPU_PARTIAL = "y"; + ARM64 = "y"; + "64BIT" = "y"; + MMU = "y"; + ARM64_PAGE_SHIFT = "12"; + ARM64_CONT_SHIFT = "4"; + ARCH_MMAP_RND_BITS_MIN = "18"; + ARCH_MMAP_RND_BITS_MAX = "24"; + ARCH_MMAP_RND_COMPAT_BITS_MIN = "11"; + ARCH_MMAP_RND_COMPAT_BITS_MAX = "16"; + STACKTRACE_SUPPORT = "y"; + ILLEGAL_POINTER_VALUE = "0xdead000000000000"; + LOCKDEP_SUPPORT = "y"; + TRACE_IRQFLAGS_SUPPORT = "y"; + GENERIC_BUG = "y"; + GENERIC_BUG_RELATIVE_POINTERS = "y"; + GENERIC_HWEIGHT = "y"; + GENERIC_CSUM = "y"; + GENERIC_CALIBRATE_DELAY = "y"; + ZONE_DMA32 = "y"; + ARCH_ENABLE_MEMORY_HOTPLUG = "y"; + SMP = "y"; + KERNEL_MODE_NEON = "y"; + FIX_EARLYCON_MEM = "y"; + PGTABLE_LEVELS = "3"; + ARCH_SUPPORTS_UPROBES = "y"; + ARCH_PROC_KCORE_TEXT = "y"; + ARCH_MEDIATEK = "y"; + ARM64_ERRATUM_1418040 = "y"; + ARM64_ERRATUM_1165522 = "y"; + ARM64_ERRATUM_1286807 = "y"; + CAVIUM_TX2_ERRATUM_219 = "y"; + ARM64_WORKAROUND_REPEAT_TLBI = "y"; + FUJITSU_ERRATUM_010001 = "y"; + ARM64_4K_PAGES = "y"; + ARM64_VA_BITS_39 = "y"; + ARM64_VA_BITS = "39"; + ARM64_PA_BITS_48 = "y"; + ARM64_PA_BITS = "48"; + SCHED_MC = "y"; + NR_CPUS = "4"; + HOTPLUG_CPU = "y"; + HOLES_IN_ZONE = "y"; + HZ_250 = "y"; + HZ = "250"; + SCHED_HRTICK = "y"; + ARCH_SUPPORTS_DEBUG_PAGEALLOC = "y"; + ARCH_SPARSEMEM_ENABLE = "y"; + ARCH_SPARSEMEM_DEFAULT = "y"; + ARCH_SELECT_MEMORY_MODEL = "y"; + ARCH_FLATMEM_ENABLE = "y"; + HAVE_ARCH_PFN_VALID = "y"; + # SYS_SUPPORTS_HUGETLBFS = "y"; + ARCH_WANT_HUGE_PMD_SHARE = "y"; + ARCH_HAS_CACHE_LINE_SIZE = "y"; + ARCH_ENABLE_SPLIT_PMD_PTLOCK = "y"; + SECCOMP = "y"; + FORCE_MAX_ZONEORDER = "11"; + HARDEN_BRANCH_PREDICTOR = "y"; + HARDEN_EL2_VECTORS = "y"; + ARM64_SSBD = "y"; + MITIGATE_SPECTRE_BRANCH_HISTORY = "y"; + RODATA_FULL_DEFAULT_ENABLED = "y"; + ARM64_TAGGED_ADDR_ABI = "y"; + COMPAT = "y"; + KUSER_HELPERS = "y"; + ARM64_HW_AFDBM = "y"; + ARM64_PAN = "y"; + ARM64_VHE = "y"; + ARM64_UAO = "y"; + ARM64_CNP = "y"; + ARM64_PTR_AUTH = "y"; + ARM64_SVE = "y"; + SYSVIPC_COMPAT = "y"; + PM = "y"; + PM_CLK = "y"; + PM_GENERIC_DOMAINS = "y"; + WQ_POWER_EFFICIENT_DEFAULT = "y"; + PM_GENERIC_DOMAINS_OF = "y"; + ARCH_SUSPEND_POSSIBLE = "y"; + CPU_FREQ = "y"; + CPU_FREQ_GOV_ATTR_SET = "y"; + CPU_FREQ_GOV_COMMON = "y"; + CPU_FREQ_STAT = "y"; + CPU_FREQ_DEFAULT_GOV_USERSPACE = "y"; + CPU_FREQ_GOV_PERFORMANCE = "y"; + CPU_FREQ_GOV_POWERSAVE = "y"; + CPU_FREQ_GOV_USERSPACE = "y"; + CPU_FREQ_GOV_ONDEMAND = "y"; + CPU_FREQ_GOV_CONSERVATIVE = "y"; + CPU_FREQ_GOV_SCHEDUTIL = "y"; + ARM_MEDIATEK_CPUFREQ = "y"; + HAVE_ARM_SMCCC = "y"; + ARM_PSCI_FW = "y"; + ARM64_CRYPTO = "y"; + CRYPTO_CHACHA20_NEON = "m"; + CRYPTO_POLY1305_NEON = "m"; + JUMP_LABEL = "y"; + HAVE_EFFICIENT_UNALIGNED_ACCESS = "y"; + HAVE_KPROBES = "y"; + HAVE_KRETPROBES = "y"; + HAVE_FUNCTION_ERROR_INJECTION = "y"; + HAVE_NMI = "y"; + HAVE_ARCH_TRACEHOOK = "y"; + HAVE_DMA_CONTIGUOUS = "y"; + GENERIC_SMP_IDLE_THREAD = "y"; + GENERIC_IDLE_POLL_SETUP = "y"; + ARCH_HAS_FORTIFY_SOURCE = "y"; + ARCH_HAS_KEEPINITRD = "y"; + ARCH_HAS_SET_MEMORY = "y"; + ARCH_HAS_SET_DIRECT_MAP = "y"; + HAVE_ARCH_THREAD_STRUCT_WHITELIST = "y"; + HAVE_ASM_MODVERSIONS = "y"; + HAVE_REGS_AND_STACK_ACCESS_API = "y"; + HAVE_RSEQ = "y"; + HAVE_FUNCTION_ARG_ACCESS_API = "y"; + HAVE_CLK = "y"; + HAVE_PERF_REGS = "y"; + HAVE_PERF_USER_STACK_DUMP = "y"; + HAVE_ARCH_JUMP_LABEL = "y"; + HAVE_ARCH_JUMP_LABEL_RELATIVE = "y"; + HAVE_RCU_TABLE_FREE = "y"; + ARCH_HAVE_NMI_SAFE_CMPXCHG = "y"; + HAVE_ALIGNED_STRUCT_PAGE = "y"; + HAVE_CMPXCHG_LOCAL = "y"; + HAVE_CMPXCHG_DOUBLE = "y"; + ARCH_WANT_COMPAT_IPC_PARSE_VERSION = "y"; + HAVE_ARCH_SECCOMP_FILTER = "y"; + SECCOMP_FILTER = "y"; + HAVE_ARCH_STACKLEAK = "y"; + HAVE_STACKPROTECTOR = "y"; + CC_HAS_STACKPROTECTOR_NONE = "y"; + STACKPROTECTOR = "y"; + HAVE_CONTEXT_TRACKING = "y"; + HAVE_VIRT_CPU_ACCOUNTING_GEN = "y"; + HAVE_IRQ_TIME_ACCOUNTING = "y"; + HAVE_ARCH_TRANSPARENT_HUGEPAGE = "y"; + HAVE_ARCH_HUGE_VMAP = "y"; + MODULES_USE_ELF_RELA = "y"; + ARCH_HAS_ELF_RANDOMIZE = "y"; + HAVE_ARCH_MMAP_RND_BITS = "y"; + ARCH_MMAP_RND_BITS = "18"; + HAVE_ARCH_MMAP_RND_COMPAT_BITS = "y"; + ARCH_MMAP_RND_COMPAT_BITS = "11"; + ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT = "y"; + HAVE_COPY_THREAD_TLS = "y"; + CLONE_BACKWARDS = "y"; + OLD_SIGSUSPEND3 = "y"; + COMPAT_OLD_SIGACTION = "y"; + "64BIT_TIME" = "y"; + COMPAT_32BIT_TIME = "y"; + HAVE_ARCH_VMAP_STACK = "y"; + VMAP_STACK = "y"; + ARCH_HAS_STRICT_KERNEL_RWX = "y"; + STRICT_KERNEL_RWX = "y"; + ARCH_HAS_STRICT_MODULE_RWX = "y"; + STRICT_MODULE_RWX = "y"; + HAVE_ARCH_PREL32_RELOCATIONS = "y"; + ARCH_HAS_GCOV_PROFILE_ALL = "y"; + HAVE_GCC_PLUGINS = "y"; + RT_MUTEXES = "y"; + BASE_SMALL = "0"; + MODULES = "y"; + MODULE_UNLOAD = "y"; + MODULE_STRIPPED = "y"; + BLOCK = "y"; + BLK_SCSI_REQUEST = "y"; + BLK_DEV_BSG = "y"; + BLK_DEV_BSGLIB = "y"; + BLK_DEV_THROTTLING = "y"; + PARTITION_ADVANCED = "y"; + MSDOS_PARTITION = "y"; + EFI_PARTITION = "y"; + BLOCK_COMPAT = "y"; + BLK_MQ_PCI = "y"; + BLK_PM = "y"; + IOSCHED_BFQ = "m"; + BFQ_GROUP_IOSCHED = "y"; + PADATA = "y"; + ASN1 = "m"; + ARCH_INLINE_SPIN_TRYLOCK = "y"; + ARCH_INLINE_SPIN_TRYLOCK_BH = "y"; + ARCH_INLINE_SPIN_LOCK = "y"; + ARCH_INLINE_SPIN_LOCK_BH = "y"; + ARCH_INLINE_SPIN_LOCK_IRQ = "y"; + ARCH_INLINE_SPIN_LOCK_IRQSAVE = "y"; + ARCH_INLINE_SPIN_UNLOCK = "y"; + ARCH_INLINE_SPIN_UNLOCK_BH = "y"; + ARCH_INLINE_SPIN_UNLOCK_IRQ = "y"; + ARCH_INLINE_SPIN_UNLOCK_IRQRESTORE = "y"; + ARCH_INLINE_READ_LOCK = "y"; + ARCH_INLINE_READ_LOCK_BH = "y"; + ARCH_INLINE_READ_LOCK_IRQ = "y"; + ARCH_INLINE_READ_LOCK_IRQSAVE = "y"; + ARCH_INLINE_READ_UNLOCK = "y"; + ARCH_INLINE_READ_UNLOCK_BH = "y"; + ARCH_INLINE_READ_UNLOCK_IRQ = "y"; + ARCH_INLINE_READ_UNLOCK_IRQRESTORE = "y"; + ARCH_INLINE_WRITE_LOCK = "y"; + ARCH_INLINE_WRITE_LOCK_BH = "y"; + ARCH_INLINE_WRITE_LOCK_IRQ = "y"; + ARCH_INLINE_WRITE_LOCK_IRQSAVE = "y"; + ARCH_INLINE_WRITE_UNLOCK = "y"; + ARCH_INLINE_WRITE_UNLOCK_BH = "y"; + ARCH_INLINE_WRITE_UNLOCK_IRQ = "y"; + ARCH_INLINE_WRITE_UNLOCK_IRQRESTORE = "y"; + INLINE_SPIN_TRYLOCK = "y"; + INLINE_SPIN_TRYLOCK_BH = "y"; + INLINE_SPIN_LOCK = "y"; + INLINE_SPIN_LOCK_BH = "y"; + INLINE_SPIN_LOCK_IRQ = "y"; + INLINE_SPIN_LOCK_IRQSAVE = "y"; + INLINE_SPIN_UNLOCK_BH = "y"; + INLINE_SPIN_UNLOCK_IRQ = "y"; + INLINE_SPIN_UNLOCK_IRQRESTORE = "y"; + INLINE_READ_LOCK = "y"; + INLINE_READ_LOCK_BH = "y"; + INLINE_READ_LOCK_IRQ = "y"; + INLINE_READ_LOCK_IRQSAVE = "y"; + INLINE_READ_UNLOCK = "y"; + INLINE_READ_UNLOCK_BH = "y"; + INLINE_READ_UNLOCK_IRQ = "y"; + INLINE_READ_UNLOCK_IRQRESTORE = "y"; + INLINE_WRITE_LOCK = "y"; + INLINE_WRITE_LOCK_BH = "y"; + INLINE_WRITE_LOCK_IRQ = "y"; + INLINE_WRITE_LOCK_IRQSAVE = "y"; + INLINE_WRITE_UNLOCK = "y"; + INLINE_WRITE_UNLOCK_BH = "y"; + INLINE_WRITE_UNLOCK_IRQ = "y"; + INLINE_WRITE_UNLOCK_IRQRESTORE = "y"; + ARCH_SUPPORTS_ATOMIC_RMW = "y"; + MUTEX_SPIN_ON_OWNER = "y"; + RWSEM_SPIN_ON_OWNER = "y"; + LOCK_SPIN_ON_OWNER = "y"; + ARCH_USE_QUEUED_SPINLOCKS = "y"; + QUEUED_SPINLOCKS = "y"; + ARCH_USE_QUEUED_RWLOCKS = "y"; + QUEUED_RWLOCKS = "y"; + ARCH_HAS_SYSCALL_WRAPPER = "y"; + BINFMT_ELF = "y"; + COMPAT_BINFMT_ELF = "y"; + ELFCORE = "y"; + BINFMT_SCRIPT = "y"; + COREDUMP = "y"; + # SELECT_MEMORY_MODEL = "y"; + # SPARSEMEM_MANUAL = "y"; + SPARSEMEM = "y"; + HAVE_MEMORY_PRESENT = "y"; + SPARSEMEM_EXTREME = "y"; + SPARSEMEM_VMEMMAP_ENABLE = "y"; + SPARSEMEM_VMEMMAP = "y"; + HAVE_FAST_GUP = "y"; + ARCH_KEEP_MEMBLOCK = "y"; + SPLIT_PTLOCK_CPUS = "4"; + COMPACTION = "y"; + MIGRATION = "y"; + PHYS_ADDR_T_64BIT = "y"; + DEFAULT_MMAP_MIN_ADDR = "4096"; + ARCH_SUPPORTS_MEMORY_FAILURE = "y"; + ZSMALLOC = "m"; + GENERIC_EARLY_IOREMAP = "y"; + ARCH_HAS_PTE_DEVMAP = "y"; + FRAME_VECTOR = "y"; + ARCH_HAS_PTE_SPECIAL = "y"; + NET = "y"; + COMPAT_NETLINK_MESSAGES = "y"; + NET_INGRESS = "y"; + NET_EGRESS = "y"; + NET_REDIRECT = "y"; + SKB_EXTENSIONS = "y"; + PACKET = "y"; + UNIX = "y"; + UNIX_SCM = "y"; + XFRM = "y"; + XFRM_ALGO = "y"; + XFRM_USER = "y"; + XFRM_INTERFACE = "m"; + XFRM_IPCOMP = "y"; + NET_KEY = "m"; + INET = "y"; + IP_MULTICAST = "y"; + IP_ADVANCED_ROUTER = "y"; + IP_MULTIPLE_TABLES = "y"; + IP_ROUTE_MULTIPATH = "y"; + IP_ROUTE_VERBOSE = "y"; + IP_ROUTE_CLASSID = "y"; + NET_IPIP = "m"; + NET_IPGRE_DEMUX = "m"; + NET_IP_TUNNEL = "m"; + NET_IPGRE = "m"; + NET_IPGRE_BROADCAST = "y"; + IP_MROUTE_COMMON = "y"; + IP_MROUTE = "y"; + IP_MROUTE_MULTIPLE_TABLES = "y"; + SYN_COOKIES = "y"; + NET_IPVTI = "m"; + NET_UDP_TUNNEL = "m"; + NET_FOU = "m"; + NET_FOU_IP_TUNNELS = "y"; + INET_AH = "y"; + INET_ESP = "y"; + INET_IPCOMP = "y"; + INET_TABLE_PERTURB_ORDER = "16"; + INET_XFRM_TUNNEL = "y"; + INET_TUNNEL = "y"; + TCP_CONG_ADVANCED = "y"; + TCP_CONG_CUBIC = "y"; + TCP_CONG_HYBLA = "m"; + TCP_CONG_BBR = "m"; + DEFAULT_CUBIC = "y"; + DEFAULT_TCP_CONG = "cubic"; + IPV6 = "y"; + INET6_AH = "m"; + INET6_ESP = "m"; + INET6_IPCOMP = "m"; + INET6_XFRM_TUNNEL = "m"; + INET6_TUNNEL = "m"; + IPV6_VTI = "m"; + IPV6_SIT = "m"; + IPV6_SIT_6RD = "y"; + IPV6_NDISC_NODETYPE = "y"; + IPV6_TUNNEL = "m"; + IPV6_GRE = "m"; + IPV6_FOU = "m"; + IPV6_FOU_TUNNEL = "m"; + IPV6_MULTIPLE_TABLES = "y"; + IPV6_SUBTREES = "y"; + IPV6_MROUTE = "y"; + IPV6_SEG6_LWTUNNEL = "y"; + IPV6_SEG6_BPF = "y"; + MPTCP = "y"; + MPTCP_IPV6 = "y"; + # SOCK_DIAG = "y"; + NET_PTP_CLASSIFY = "y"; + NETFILTER = "y"; + NETFILTER_ADVANCED = "y"; + BRIDGE_NETFILTER = "y"; + NETFILTER_INGRESS = "y"; + NETFILTER_NETLINK = "m"; + NETFILTER_FAMILY_BRIDGE = "y"; + NETFILTER_FAMILY_ARP = "y"; + NETFILTER_NETLINK_QUEUE = "m"; + NETFILTER_NETLINK_LOG = "m"; + NF_CONNTRACK = "y"; + NF_LOG_COMMON = "m"; + NETFILTER_CONNCOUNT = "m"; + NF_CONNTRACK_MARK = "y"; + NF_CONNTRACK_ZONES = "y"; + NF_CONNTRACK_PROCFS = "y"; + NF_CONNTRACK_EVENTS = "y"; + NF_CONNTRACK_CHAIN_EVENTS = "y"; + NF_CONNTRACK_TIMEOUT = "y"; + NF_CONNTRACK_LABELS = "y"; + NF_CT_PROTO_GRE = "y"; + NF_CONNTRACK_AMANDA = "m"; + NF_CONNTRACK_FTP = "m"; + NF_CONNTRACK_H323 = "m"; + NF_CONNTRACK_IRC = "m"; + NF_CONNTRACK_BROADCAST = "m"; + NF_CONNTRACK_SNMP = "m"; + NF_CONNTRACK_PPTP = "m"; + NF_CONNTRACK_SIP = "y"; + NF_CONNTRACK_TFTP = "m"; + NF_CT_NETLINK = "m"; + NETFILTER_NETLINK_GLUE_CT = "y"; + NF_NAT = "m"; + NF_NAT_AMANDA = "m"; + NF_NAT_FTP = "m"; + NF_NAT_IRC = "m"; + NF_NAT_SIP = "m"; + NF_NAT_TFTP = "m"; + NF_NAT_REDIRECT = "y"; + NF_NAT_MASQUERADE = "y"; + NF_TABLES = "m"; + NF_TABLES_SET = "m"; + NF_TABLES_INET = "y"; + NF_TABLES_NETDEV = "y"; + NFT_NUMGEN = "m"; + NFT_CT = "m"; + NFT_FLOW_OFFLOAD = "m"; + NFT_COUNTER = "m"; + NFT_LOG = "m"; + NFT_LIMIT = "m"; + NFT_MASQ = "m"; + NFT_REDIR = "m"; + NFT_NAT = "m"; + NFT_OBJREF = "m"; + NFT_QUEUE = "m"; + NFT_QUOTA = "m"; + NFT_REJECT = "m"; + NFT_REJECT_INET = "m"; + NFT_HASH = "m"; + NFT_FIB = "m"; + NFT_FIB_INET = "m"; + NF_DUP_NETDEV = "m"; + NFT_DUP_NETDEV = "m"; + NFT_FWD_NETDEV = "m"; + NF_FLOW_TABLE_INET = "m"; + NF_FLOW_TABLE = "m"; + NF_FLOW_TABLE_HW = "m"; + NETFILTER_XTABLES = "m"; + NETFILTER_XT_MARK = "m"; + NETFILTER_XT_CONNMARK = "m"; + NETFILTER_XT_SET = "m"; + NETFILTER_XT_TARGET_CHECKSUM = "m"; + NETFILTER_XT_TARGET_CLASSIFY = "m"; + NETFILTER_XT_TARGET_CT = "m"; + NETFILTER_XT_TARGET_DSCP = "m"; + NETFILTER_XT_TARGET_HL = "m"; + NETFILTER_XT_TARGET_LED = "m"; + NETFILTER_XT_TARGET_LOG = "m"; + NETFILTER_XT_NAT = "m"; + NETFILTER_XT_TARGET_NETMAP = "m"; + NETFILTER_XT_TARGET_NFLOG = "m"; + NETFILTER_XT_TARGET_NFQUEUE = "m"; + NETFILTER_XT_TARGET_FLOWOFFLOAD = "m"; + NETFILTER_XT_TARGET_REDIRECT = "m"; + NETFILTER_XT_TARGET_MASQUERADE = "m"; + NETFILTER_XT_TARGET_TEE = "m"; + NETFILTER_XT_TARGET_TPROXY = "m"; + NETFILTER_XT_TARGET_TRACE = "m"; + NETFILTER_XT_TARGET_TCPMSS = "m"; + NETFILTER_XT_MATCH_ADDRTYPE = "m"; + NETFILTER_XT_MATCH_BPF = "m"; + NETFILTER_XT_MATCH_CLUSTER = "m"; + NETFILTER_XT_MATCH_COMMENT = "m"; + NETFILTER_XT_MATCH_CONNBYTES = "m"; + NETFILTER_XT_MATCH_CONNLABEL = "m"; + NETFILTER_XT_MATCH_CONNLIMIT = "m"; + NETFILTER_XT_MATCH_CONNTRACK = "m"; + NETFILTER_XT_MATCH_DSCP = "m"; + NETFILTER_XT_MATCH_ECN = "m"; + NETFILTER_XT_MATCH_ESP = "m"; + NETFILTER_XT_MATCH_HASHLIMIT = "m"; + NETFILTER_XT_MATCH_HELPER = "m"; + NETFILTER_XT_MATCH_HL = "m"; + NETFILTER_XT_MATCH_IPRANGE = "m"; + NETFILTER_XT_MATCH_IPVS = "m"; + NETFILTER_XT_MATCH_LENGTH = "m"; + NETFILTER_XT_MATCH_LIMIT = "m"; + NETFILTER_XT_MATCH_MAC = "m"; + NETFILTER_XT_MATCH_MULTIPORT = "m"; + NETFILTER_XT_MATCH_OWNER = "m"; + NETFILTER_XT_MATCH_POLICY = "m"; + NETFILTER_XT_MATCH_PHYSDEV = "m"; + NETFILTER_XT_MATCH_PKTTYPE = "m"; + NETFILTER_XT_MATCH_QUOTA = "m"; + NETFILTER_XT_MATCH_RECENT = "m"; + NETFILTER_XT_MATCH_SOCKET = "m"; + NETFILTER_XT_MATCH_STATE = "m"; + NETFILTER_XT_MATCH_STATISTIC = "m"; + NETFILTER_XT_MATCH_STRING = "m"; + NETFILTER_XT_MATCH_TCPMSS = "m"; + NETFILTER_XT_MATCH_TIME = "m"; + NETFILTER_XT_MATCH_U32 = "m"; + IP_SET = "m"; + IP_SET_MAX = "256"; + IP_SET_BITMAP_IP = "m"; + IP_SET_BITMAP_IPMAC = "m"; + IP_SET_BITMAP_PORT = "m"; + IP_SET_HASH_IP = "m"; + IP_SET_HASH_IPMARK = "m"; + IP_SET_HASH_IPPORT = "m"; + IP_SET_HASH_IPPORTIP = "m"; + IP_SET_HASH_IPPORTNET = "m"; + IP_SET_HASH_IPMAC = "m"; + IP_SET_HASH_MAC = "m"; + IP_SET_HASH_NETPORTNET = "m"; + IP_SET_HASH_NET = "m"; + IP_SET_HASH_NETNET = "m"; + IP_SET_HASH_NETPORT = "m"; + IP_SET_HASH_NETIFACE = "m"; + IP_SET_LIST_SET = "m"; + IP_VS = "m"; + IP_VS_IPV6 = "y"; + IP_VS_TAB_BITS = "12"; + IP_VS_PROTO_TCP = "y"; + IP_VS_PROTO_UDP = "y"; + IP_VS_PROTO_AH_ESP = "y"; + IP_VS_PROTO_ESP = "y"; + IP_VS_PROTO_AH = "y"; + IP_VS_PROTO_SCTP = "y"; + IP_VS_RR = "m"; + IP_VS_WRR = "m"; + IP_VS_LC = "m"; + IP_VS_WLC = "m"; + IP_VS_FO = "m"; + IP_VS_OVF = "m"; + IP_VS_LBLC = "m"; + IP_VS_LBLCR = "m"; + IP_VS_DH = "m"; + IP_VS_SH = "m"; + IP_VS_SED = "m"; + IP_VS_NQ = "m"; + IP_VS_SH_TAB_BITS = "8"; + IP_VS_MH_TAB_INDEX = "10"; + IP_VS_FTP = "m"; + IP_VS_NFCT = "y"; + IP_VS_PE_SIP = "m"; + NF_DEFRAG_IPV4 = "y"; + NF_SOCKET_IPV4 = "m"; + NF_TPROXY_IPV4 = "m"; + NF_TABLES_IPV4 = "y"; + NFT_REJECT_IPV4 = "m"; + NFT_FIB_IPV4 = "m"; + NF_TABLES_ARP = "y"; + NF_FLOW_TABLE_IPV4 = "m"; + NF_DUP_IPV4 = "m"; + NF_LOG_IPV4 = "m"; + NF_REJECT_IPV4 = "m"; + NF_NAT_SNMP_BASIC = "m"; + NF_NAT_PPTP = "m"; + NF_NAT_H323 = "m"; + IP_NF_IPTABLES = "m"; + IP_NF_MATCH_AH = "m"; + IP_NF_MATCH_RPFILTER = "m"; + IP_NF_FILTER = "m"; + IP_NF_TARGET_REJECT = "m"; + IP_NF_NAT = "m"; + IP_NF_TARGET_MASQUERADE = "m"; + IP_NF_TARGET_NETMAP = "m"; + IP_NF_MANGLE = "m"; + IP_NF_TARGET_CLUSTERIP = "m"; + IP_NF_TARGET_ECN = "m"; + IP_NF_RAW = "m"; + IP_NF_ARPTABLES = "m"; + IP_NF_ARPFILTER = "m"; + IP_NF_ARP_MANGLE = "m"; + NF_SOCKET_IPV6 = "m"; + NF_TPROXY_IPV6 = "m"; + NF_TABLES_IPV6 = "y"; + NFT_REJECT_IPV6 = "m"; + NFT_FIB_IPV6 = "m"; + NF_FLOW_TABLE_IPV6 = "m"; + NF_DUP_IPV6 = "m"; + NF_REJECT_IPV6 = "m"; + NF_LOG_IPV6 = "m"; + IP6_NF_IPTABLES = "m"; + IP6_NF_MATCH_AH = "m"; + IP6_NF_MATCH_EUI64 = "m"; + IP6_NF_MATCH_FRAG = "m"; + IP6_NF_MATCH_OPTS = "m"; + IP6_NF_MATCH_IPV6HEADER = "m"; + IP6_NF_MATCH_MH = "m"; + IP6_NF_MATCH_RPFILTER = "m"; + IP6_NF_MATCH_RT = "m"; + IP6_NF_FILTER = "m"; + IP6_NF_TARGET_REJECT = "m"; + IP6_NF_MANGLE = "m"; + IP6_NF_RAW = "m"; + IP6_NF_NAT = "m"; + IP6_NF_TARGET_NPT = "m"; + NF_DEFRAG_IPV6 = "y"; + NF_TABLES_BRIDGE = "m"; + NFT_BRIDGE_META = "m"; + NFT_BRIDGE_REJECT = "m"; + BRIDGE_NF_EBTABLES = "m"; + BRIDGE_EBT_BROUTE = "m"; + BRIDGE_EBT_T_FILTER = "m"; + BRIDGE_EBT_T_NAT = "m"; + BRIDGE_EBT_802_3 = "m"; + BRIDGE_EBT_AMONG = "m"; + BRIDGE_EBT_ARP = "m"; + BRIDGE_EBT_IP = "m"; + BRIDGE_EBT_IP6 = "m"; + BRIDGE_EBT_LIMIT = "m"; + BRIDGE_EBT_MARK = "m"; + BRIDGE_EBT_PKTTYPE = "m"; + BRIDGE_EBT_STP = "m"; + BRIDGE_EBT_VLAN = "m"; + BRIDGE_EBT_ARPREPLY = "m"; + BRIDGE_EBT_DNAT = "m"; + BRIDGE_EBT_MARK_T = "m"; + BRIDGE_EBT_REDIRECT = "m"; + BRIDGE_EBT_SNAT = "m"; + BRIDGE_EBT_LOG = "m"; + BRIDGE_EBT_NFLOG = "m"; + IP_SCTP = "m"; + SCTP_DEFAULT_COOKIE_HMAC_MD5 = "y"; + SCTP_COOKIE_HMAC_MD5 = "y"; + ATM = "m"; + ATM_CLIP = "m"; + ATM_CLIP_NO_ICMP = "y"; + ATM_BR2684 = "m"; + ATM_BR2684_IPFILTER = "y"; + L2TP = "m"; + L2TP_V3 = "y"; + L2TP_IP = "m"; + L2TP_ETH = "m"; + STP = "y"; + BRIDGE = "y"; + BRIDGE_IGMP_SNOOPING = "y"; + BRIDGE_VLAN_FILTERING = "y"; + HAVE_NET_DSA = "y"; + NET_DSA = "y"; + NET_DSA_TAG_MTK = "y"; + VLAN_8021Q = "y"; + LLC = "y"; + "6LOWPAN" = "m"; + IEEE802154 = "m"; + IEEE802154_SOCKET = "m"; + IEEE802154_6LOWPAN = "m"; + MAC802154 = "m"; + NET_SCHED = "y"; + NET_SCH_HTB = "m"; + NET_SCH_HFSC = "m"; + NET_SCH_PRIO = "m"; + NET_SCH_MULTIQ = "m"; + NET_SCH_RED = "m"; + NET_SCH_SFQ = "m"; + NET_SCH_TEQL = "m"; + NET_SCH_TBF = "m"; + NET_SCH_GRED = "m"; + NET_SCH_DSMARK = "m"; + NET_SCH_NETEM = "m"; + NET_SCH_MQPRIO = "m"; + NET_SCH_CODEL = "m"; + NET_SCH_FQ_CODEL = "y"; + NET_SCH_CAKE = "m"; + NET_SCH_FQ = "m"; + NET_SCH_PIE = "m"; + NET_SCH_INGRESS = "m"; + NET_CLS = "y"; + NET_CLS_BASIC = "m"; + NET_CLS_ROUTE4 = "m"; + NET_CLS_FW = "m"; + NET_CLS_U32 = "m"; + CLS_U32_MARK = "y"; + NET_CLS_FLOW = "m"; + NET_CLS_BPF = "m"; + NET_CLS_FLOWER = "m"; + NET_CLS_MATCHALL = "m"; + NET_EMATCH = "y"; + NET_EMATCH_STACK = "32"; + NET_EMATCH_CMP = "m"; + NET_EMATCH_NBYTE = "m"; + NET_EMATCH_U32 = "m"; + NET_EMATCH_META = "m"; + NET_EMATCH_TEXT = "m"; + NET_EMATCH_IPSET = "m"; + NET_CLS_ACT = "y"; + NET_ACT_POLICE = "m"; + NET_ACT_GACT = "m"; + GACT_PROB = "y"; + NET_ACT_MIRRED = "m"; + NET_ACT_IPT = "m"; + NET_ACT_PEDIT = "m"; + NET_ACT_SIMP = "m"; + NET_ACT_SKBEDIT = "m"; + NET_ACT_CSUM = "m"; + NET_ACT_VLAN = "m"; + NET_ACT_BPF = "m"; + NET_ACT_CONNMARK = "m"; + NET_ACT_CTINFO = "m"; + NET_SCH_FIFO = "y"; + DNS_RESOLVER = "m"; + NETLINK_DIAG = "m"; + MPLS = "y"; + NET_MPLS_GSO = "m"; + MPLS_ROUTING = "m"; + MPLS_IPTUNNEL = "m"; + NET_NSH = "m"; + NET_SWITCHDEV = "y"; + RPS = "y"; + RFS_ACCEL = "y"; + XPS = "y"; + NET_RX_BUSY_POLL = "y"; + BQL = "y"; + BPF_JIT = "y"; + NET_FLOW_LIMIT = "y"; + NET_PKTGEN = "m"; + HAMRADIO = "y"; + AX25 = "m"; + MKISS = "m"; + CAN = "m"; + CAN_RAW = "m"; + CAN_BCM = "m"; + CAN_GW = "m"; + CAN_VCAN = "m"; + CAN_SLCAN = "m"; + CAN_DEV = "m"; + CAN_CALC_BITTIMING = "y"; + CAN_C_CAN = "m"; + CAN_C_CAN_PLATFORM = "m"; + CAN_C_CAN_PCI = "m"; + CAN_MCP251X = "m"; + CAN_8DEV_USB = "m"; + CAN_EMS_USB = "m"; + CAN_ESD_USB2 = "m"; + CAN_KVASER_USB = "m"; + CAN_PEAK_USB = "m"; + BT = "y"; + BT_BREDR = "y"; + BT_RFCOMM = "m"; + BT_RFCOMM_TTY = "y"; + BT_BNEP = "m"; + BT_BNEP_MC_FILTER = "y"; + BT_BNEP_PROTO_FILTER = "y"; + BT_HIDP = "m"; + BT_HS = "y"; + BT_LE = "y"; + BT_6LOWPAN = "m"; + BT_DEBUGFS = "y"; + BT_INTEL = "m"; + BT_BCM = "y"; + BT_QCA = "y"; + BT_HCIBTUSB = "m"; + BT_HCIUART = "y"; + BT_HCIUART_SERDEV = "y"; + BT_HCIUART_H4 = "y"; + BT_HCIUART_BCSP = "y"; + BT_HCIUART_ATH3K = "y"; + BT_HCIUART_BCM = "y"; + BT_HCIUART_QCA = "y"; + BT_HCIVHCI = "y"; + BT_MRVL = "m"; + BT_MRVL_SDIO = "m"; + BT_ATH3K = "m"; + BT_MTKUART = "y"; + FIB_RULES = "y"; + WIRELESS = "y"; + # WIRELESS_EXT = "y"; + # WEXT_CORE = "y"; + # WEXT_PROC = "y"; + # WEXT_SPY = "y"; + # WEXT_PRIV = "y"; + MAC80211_STA_HASH_MAX_SIZE = "0"; + RFKILL = "y"; + LWTUNNEL = "y"; + DST_CACHE = "y"; + GRO_CELLS = "y"; + NET_DEVLINK = "y"; + PAGE_POOL = "y"; + HAVE_EBPF_JIT = "y"; + # SHORTCUT_FE = "y"; + ARM_AMBA = "y"; + HAVE_PCI = "y"; + PCI = "y"; + PCI_DOMAINS = "y"; + PCI_DOMAINS_GENERIC = "y"; + PCI_SYSCALL = "y"; + PCI_MSI = "y"; + PCI_MSI_IRQ_DOMAIN = "y"; + PCI_QUIRKS = "y"; + PCI_DEBUG = "y"; + PCIE_MEDIATEK_GEN3 = "y"; + UEVENT_HELPER = "y"; + # UEVENT_HELPER_PATH = "/sbin/hotplug"; + STANDALONE = "y"; + PREVENT_FIRMWARE_BUILD = "y"; + FW_LOADER = "y"; + FW_LOADER_PAGED_BUF = "y"; + FW_LOADER_USER_HELPER_FALLBACK = "y"; + WANT_DEV_COREDUMP = "y"; + ALLOW_DEV_COREDUMP = "y"; + DEV_COREDUMP = "y"; + GENERIC_CPU_AUTOPROBE = "y"; + GENERIC_CPU_VULNERABILITIES = "y"; + REGMAP = "y"; + REGMAP_I2C = "m"; + REGMAP_SPI = "m"; + REGMAP_MMIO = "y"; + DMA_SHARED_BUFFER = "m"; + GENERIC_ARCH_TOPOLOGY = "y"; + MTD = "y"; + MTD_ROOTFS_ROOT_DEV = "y"; + MTD_SPLIT_FIRMWARE = "y"; + MTD_SPLIT_FIRMWARE_NAME = "firmware"; + MTD_SPLIT = "y"; + MTD_SPLIT_SUPPORT = "y"; + MTD_SPLIT_SQUASHFS_ROOT = "y"; + MTD_SPLIT_FIT_FW = "y"; + MTD_TESTS = "m"; + MTD_OF_PARTS = "y"; + MTD_BLKDEVS = "y"; + MTD_BLOCK = "y"; + MTD_OOPS = "m"; + MTD_CFI = "y"; + MTD_GEN_PROBE = "y"; + MTD_MAP_BANK_WIDTH_1 = "y"; + MTD_MAP_BANK_WIDTH_2 = "y"; + MTD_MAP_BANK_WIDTH_4 = "y"; + MTD_CFI_I1 = "y"; + MTD_CFI_I2 = "y"; + MTD_CFI_INTELEXT = "y"; + MTD_CFI_AMDSTD = "y"; + MTD_CFI_UTIL = "y"; + MTD_COMPLEX_MAPPINGS = "y"; + MTD_MTDRAM = "m"; + MTDRAM_TOTAL_SIZE = "4096"; + MTDRAM_ERASE_SIZE = "128"; + MTD_BLOCK2MTD = "m"; + MTD_NAND_CORE = "y"; + MTD_NAND_ECC_SW_HAMMING = "y"; + MTD_RAW_NAND = "y"; + MTD_NAND_MTK = "y"; + MTD_SPI_NAND = "y"; + MTD_SPI_NOR = "y"; + MTD_UBI = "y"; + MTD_UBI_WL_THRESHOLD = "4096"; + MTD_UBI_BEB_LIMIT = "20"; + MTD_UBI_BLOCK = "y"; + NMBM = "y"; + NMBM_LOG_LEVEL_INFO = "y"; + NMBM_MTD = "y"; + MTK_SPI_NAND = "y"; + DTC = "y"; + OF = "y"; + OF_FLATTREE = "y"; + OF_EARLY_FLATTREE = "y"; + OF_KOBJ = "y"; + OF_ADDRESS = "y"; + OF_IRQ = "y"; + OF_NET = "y"; + OF_MDIO = "y"; + OF_RESERVED_MEM = "y"; + PARPORT = "m"; + PARPORT_1284 = "y"; + BLK_DEV = "y"; + CDROM = "m"; + ZRAM = "m"; + BLK_DEV_LOOP = "y"; + BLK_DEV_LOOP_MIN_COUNT = "8"; + BLK_DEV_NBD = "m"; + ATA_OVER_ETH = "m"; + NVME_CORE = "m"; + BLK_DEV_NVME = "m"; + EEPROM_AT24 = "m"; + EEPROM_AT25 = "m"; + EEPROM_93CX6 = "m"; + ECHO = "m"; + MTK_ICE_DEBUG = "y"; + SCSI_MOD = "y"; + SCSI = "y"; + SCSI_DMA = "y"; + SCSI_PROC_FS = "y"; + BLK_DEV_SD = "y"; + CHR_DEV_ST = "m"; + BLK_DEV_SR = "m"; + CHR_DEV_SG = "m"; + SCSI_ISCSI_ATTRS = "y"; + SCSI_LOWLEVEL = "y"; + ISCSI_TCP = "m"; + HAVE_PATA_PLATFORM = "y"; + ATA = "y"; + SATA_AHCI = "m"; + SATA_MOBILE_LPM_POLICY = "0"; + AHCI_MTK = "y"; + SATA_SIL24 = "m"; + ATA_SFF = "y"; + ATA_BMDMA = "y"; + ATA_PIIX = "m"; + SATA_MV = "m"; + SATA_NV = "m"; + SATA_SIL = "m"; + SATA_VIA = "m"; + PATA_ARTOP = "m"; + PATA_PDC_OLD = "m"; + MD = "y"; + BLK_DEV_MD = "m"; + MD_LINEAR = "m"; + MD_RAID0 = "m"; + MD_RAID1 = "m"; + MD_RAID10 = "m"; + MD_RAID456 = "m"; + MD_MULTIPATH = "m"; + BLK_DEV_DM_BUILTIN = "y"; + BLK_DEV_DM = "y"; + DM_BUFIO = "y"; + DM_CRYPT = "y"; + DM_INIT = "y"; + DM_VERITY = "y"; + FIREWIRE = "m"; + FIREWIRE_OHCI = "m"; + FIREWIRE_SBP2 = "m"; + FIREWIRE_NET = "m"; + NETDEVICES = "y"; + MII = "y"; + NET_CORE = "y"; + BONDING = "m"; + DUMMY = "m"; + WIREGUARD = "m"; + IFB = "m"; + MACVLAN = "m"; + VXLAN = "m"; + GENEVE = "m"; + MACSEC = "m"; + TUN = "m"; + VETH = "m"; + NLMON = "m"; + ATM_DRIVERS = "y"; + ATM_TCP = "m"; + ATM_SOLOS = "m"; + NET_DSA_MT7530 = "y"; + ETHERNET = "y"; + MDIO = "m"; + NET_VENDOR_3COM = "y"; + VORTEX = "m"; + NET_VENDOR_ADAPTEC = "y"; + NET_VENDOR_AGERE = "y"; + ET131X = "m"; + NET_VENDOR_ALACRITECH = "y"; + NET_VENDOR_ALTEON = "y"; + NET_VENDOR_AMAZON = "y"; + NET_VENDOR_AMD = "y"; + PCNET32 = "m"; + NET_VENDOR_AQUANTIA = "y"; + AQTION = "m"; + NET_VENDOR_ARC = "y"; + NET_VENDOR_ATHEROS = "y"; + ATL2 = "m"; + ATL1 = "m"; + ATL1E = "m"; + ATL1C = "m"; + ALX = "m"; + NET_VENDOR_AURORA = "y"; + NET_VENDOR_BROADCOM = "y"; + B44 = "m"; + B44_PCI_AUTOSELECT = "y"; + B44_PCICORE_AUTOSELECT = "y"; + B44_PCI = "y"; + BNX2 = "m"; + TIGON3 = "m"; + BNX2X = "m"; + NET_VENDOR_BROCADE = "y"; + NET_VENDOR_CADENCE = "y"; + NET_VENDOR_CAVIUM = "y"; + NET_VENDOR_CHELSIO = "y"; + NET_VENDOR_CISCO = "y"; + NET_VENDOR_CORTINA = "y"; + NET_VENDOR_DEC = "y"; + NET_TULIP = "y"; + DE2104X = "m"; + DE2104X_DSL = "0"; + TULIP = "m"; + TULIP_MWI = "y"; + TULIP_MMIO = "y"; + TULIP_NAPI = "y"; + TULIP_NAPI_HW_MITIGATION = "y"; + WINBOND_840 = "m"; + DM9102 = "m"; + ULI526X = "m"; + NET_VENDOR_DLINK = "y"; + NET_VENDOR_EMULEX = "y"; + BE2NET = "m"; + BE2NET_HWMON = "y"; + BE2NET_BE2 = "y"; + BE2NET_BE3 = "y"; + BE2NET_LANCER = "y"; + BE2NET_SKYHAWK = "y"; + NET_VENDOR_EZCHIP = "y"; + NET_VENDOR_GOOGLE = "y"; + NET_VENDOR_HISILICON = "y"; + NET_VENDOR_HP = "y"; + NET_VENDOR_HUAWEI = "y"; + NET_VENDOR_I825XX = "y"; + NET_VENDOR_INTEL = "y"; + E100 = "m"; + E1000 = "m"; + IGB = "m"; + IGB_HWMON = "y"; + IXGBE = "m"; + IXGBE_HWMON = "y"; + IXGBEVF = "m"; + I40E = "m"; + IAVF = "m"; + I40EVF = "m"; + IGC = "m"; + NET_VENDOR_MARVELL = "y"; + SKGE = "m"; + SKY2 = "m"; + NET_VENDOR_MEDIATEK = "y"; + NET_MEDIATEK_SOC = "y"; + MEDIATEK_NETSYS_V2 = "y"; + NET_MEDIATEK_HNAT = "m"; + NET_VENDOR_MELLANOX = "y"; + MLX4_EN = "m"; + MLX4_CORE = "m"; + MLX4_CORE_GEN2 = "y"; + MLX5_CORE = "m"; + MLX5_CORE_EN = "y"; + MLX5_EN_RXNFC = "y"; + MLX5_MPFS = "y"; + NET_VENDOR_MICREL = "y"; + NET_VENDOR_MICROCHIP = "y"; + NET_VENDOR_MICROSEMI = "y"; + NET_VENDOR_MYRI = "y"; + NET_VENDOR_NATSEMI = "y"; + NATSEMI = "m"; + NET_VENDOR_NETERION = "y"; + NET_VENDOR_NETRONOME = "y"; + NET_VENDOR_NI = "y"; + NET_VENDOR_8390 = "y"; + NE2K_PCI = "m"; + NET_VENDOR_NVIDIA = "y"; + FORCEDETH = "m"; + NET_VENDOR_OKI = "y"; + ETHOC = "m"; + NET_VENDOR_PACKET_ENGINES = "y"; + NET_VENDOR_PENSANDO = "y"; + NET_VENDOR_QLOGIC = "y"; + NET_VENDOR_QUALCOMM = "y"; + NET_VENDOR_RDC = "y"; + R6040 = "m"; + NET_VENDOR_REALTEK = "y"; + "8139CP" = "m"; + "8139TOO" = "m"; + "8139TOO_PIO" = "y"; + R8169 = "m"; + NET_VENDOR_RENESAS = "y"; + NET_VENDOR_ROCKER = "y"; + NET_VENDOR_SAMSUNG = "y"; + NET_VENDOR_SEEQ = "y"; + NET_VENDOR_SOLARFLARE = "y"; + SFC = "m"; + SFC_MTD = "y"; + SFC_MCDI_MON = "y"; + SFC_MCDI_LOGGING = "y"; + SFC_FALCON = "m"; + SFC_FALCON_MTD = "y"; + NET_VENDOR_SILAN = "y"; + NET_VENDOR_SIS = "y"; + SIS900 = "m"; + SIS190 = "m"; + NET_VENDOR_SMSC = "y"; + NET_VENDOR_SOCIONEXT = "y"; + NET_VENDOR_STMICRO = "y"; + NET_VENDOR_SUN = "y"; + NIU = "m"; + NET_VENDOR_SYNOPSYS = "y"; + NET_VENDOR_TEHUTI = "y"; + NET_VENDOR_TI = "y"; + NET_VENDOR_VIA = "y"; + VIA_RHINE = "m"; + VIA_RHINE_MMIO = "y"; + VIA_VELOCITY = "m"; + NET_VENDOR_WIZNET = "y"; + MDIO_DEVICE = "y"; + MDIO_BUS = "y"; + MDIO_BITBANG = "m"; + MDIO_GPIO = "m"; + MDIO_I2C = "m"; + PHYLINK = "y"; + PHYLIB = "y"; + SWPHY = "y"; + # SWCONFIG = "m"; + # SWCONFIG_B53 = "m"; + # SWCONFIG_B53_PHY_DRIVER = "m"; + # SWCONFIG_B53_PHY_FIXUP = "y"; + IP17XX_PHY = "m"; + RTL8306_PHY = "m"; + RTL8366_SMI = "m"; + RTL8366S_PHY = "m"; + RTL8366RB_PHY = "m"; + # RTL8367B_PHY = "m"; + MT753X_GSW = "y"; + SFP = "m"; + AIROHA_EN8801SC_PHY = "y"; + AIROHA_EN8811H_PHY = "y"; + BCM_NET_PHYLIB = "m"; + BROADCOM_PHY = "m"; + BCM84881_PHY = "m"; + FIXED_PHY = "y"; + GPY211_PHY = "y"; + ICPLUS_PHY = "y"; + MAXLINEAR_GPHY = "y"; + REALTEK_PHY = "y"; + MICREL_KS8995MA = "m"; + PPP = "m"; + PPP_FILTER = "y"; + PPP_MPPE = "m"; + PPP_MULTILINK = "y"; + PPPOATM = "m"; + PPPOE = "m"; + PPTP = "m"; + PPPOL2TP = "m"; + PPP_ASYNC = "m"; + PPP_SYNC_TTY = "m"; + SLIP = "m"; + SLHC = "m"; + SLIP_COMPRESSED = "y"; + SLIP_SMART = "y"; + SLIP_MODE_SLIP6 = "y"; + USB_NET_DRIVERS = "y"; + USB_KAWETH = "m"; + USB_PEGASUS = "m"; + USB_RTL8150 = "m"; + USB_RTL8152 = "y"; + USB_USBNET = "y"; + USB_NET_AX8817X = "m"; + USB_NET_AX88179_178A = "y"; + # USB_NET_CDCETHER = "m"; + USB_NET_CDC_EEM = "m"; + USB_NET_CDC_NCM = "m"; + USB_NET_HUAWEI_CDC_NCM = "m"; + USB_NET_CDC_MBIM = "m"; + USB_NET_DM9601 = "m"; + USB_NET_SR9700 = "m"; + USB_NET_SMSC95XX = "m"; + USB_NET_PLUSB = "m"; + USB_NET_MCS7830 = "m"; + USB_NET_RNDIS_HOST = "m"; + USB_NET_CDC_SUBSET_ENABLE = "m"; + USB_NET_CDC_SUBSET = "m"; + USB_ALI_M5632 = "y"; + USB_AN2720 = "y"; + USB_BELKIN = "y"; + USB_ARMLINUX = "y"; + USB_NET_KALMIA = "m"; + USB_NET_QMI_WWAN = "m"; + USB_HSO = "m"; + USB_IPHETH = "m"; + USB_SIERRA_NET = "m"; + USB_NET_AQC111 = "m"; + WLAN = "y"; + IEEE802154_DRIVERS = "m"; + IEEE802154_FAKELB = "m"; + IEEE802154_AT86RF230 = "m"; + IEEE802154_MRF24J40 = "m"; + IEEE802154_CC2520 = "m"; + IEEE802154_ATUSB = "m"; + IEEE802154_CA8210 = "m"; + VMXNET3 = "m"; + ISDN = "y"; + MISDN = "m"; + MISDN_DSP = "m"; + MISDN_L1OIP = "m"; + MISDN_HFCPCI = "m"; + MISDN_HFCMULTI = "m"; + INPUT = "m"; + INPUT_POLLDEV = "m"; + INPUT_MATRIXKMAP = "m"; + INPUT_JOYDEV = "m"; + INPUT_EVDEV = "m"; + INPUT_KEYBOARD = "y"; + KEYBOARD_GPIO = "m"; + KEYBOARD_GPIO_POLLED = "m"; + INPUT_TOUCHSCREEN = "y"; + # TOUCHSCREEN_PROPERTIES = "m"; + TOUCHSCREEN_ADS7846 = "m"; + INPUT_MISC = "y"; + INPUT_GPIO_BEEPER = "m"; + INPUT_YEALINK = "m"; + INPUT_CM109 = "m"; + INPUT_UINPUT = "m"; + INPUT_GPIO_ROTARY_ENCODER = "m"; + TTY = "y"; + UNIX98_PTYS = "y"; + LDISC_AUTOLOAD = "y"; + DEVMEM = "y"; + SERIAL_EARLYCON = "y"; + SERIAL_8250 = "y"; + SERIAL_8250_CONSOLE = "y"; + SERIAL_8250_DMA = "y"; + SERIAL_8250_PCI = "m"; + SERIAL_8250_EXAR = "m"; + SERIAL_8250_NR_UARTS = "16"; + SERIAL_8250_RUNTIME_UARTS = "16"; + SERIAL_8250_EXTENDED = "y"; + SERIAL_8250_MANY_PORTS = "y"; + SERIAL_8250_SHARE_IRQ = "y"; + SERIAL_8250_FSL = "y"; + SERIAL_8250_MT6577 = "y"; + SERIAL_OF_PLATFORM = "y"; + SERIAL_CORE = "y"; + SERIAL_CORE_CONSOLE = "y"; + SERIAL_MCTRL_GPIO = "y"; + SERIAL_DEV_BUS = "y"; + SERIAL_DEV_CTRL_TTYPORT = "y"; + PRINTER = "m"; + PPDEV = "m"; + HW_RANDOM = "y"; + HW_RANDOM_MTK = "y"; + TCG_TPM = "m"; + HW_RANDOM_TPM = "y"; + TCG_TIS_I2C_ATMEL = "m"; + TCG_TIS_I2C_INFINEON = "m"; + DEVPORT = "y"; + I2C = "y"; + I2C_BOARDINFO = "y"; + I2C_CHARDEV = "y"; + I2C_MUX = "m"; + I2C_MUX_GPIO = "m"; + I2C_MUX_PCA9541 = "m"; + I2C_MUX_PCA954x = "m"; + I2C_SMBUS = "m"; + I2C_ALGOBIT = "m"; + I2C_ALGOPCF = "m"; + I2C_ALGOPCA = "m"; + I2C_GPIO = "m"; + I2C_MT65XX = "y"; + I2C_TINY_USB = "m"; + SPI = "y"; + SPI_MASTER = "y"; + SPI_MEM = "y"; + SPI_BITBANG = "m"; + SPI_GPIO = "m"; + SPI_MT65XX = "y"; + # SPI_MTK_SNFI = "y"; + SPI_SPIDEV = "m"; + PPS = "m"; + PPS_CLIENT_LDISC = "m"; + PPS_CLIENT_GPIO = "m"; + PTP_1588_CLOCK = "m"; + PINCTRL = "y"; + GENERIC_PINCTRL_GROUPS = "y"; + PINMUX = "y"; + GENERIC_PINMUX_FUNCTIONS = "y"; + PINCONF = "y"; + GENERIC_PINCONF = "y"; + PINCTRL_MCP23S08 = "m"; + PINCTRL_SINGLE = "y"; + EINT_MTK = "y"; + PINCTRL_MTK = "y"; + PINCTRL_MTK_MOORE = "y"; + PINCTRL_MT7986 = "y"; + PINCTRL_MT7988 = "y"; + PINCTRL_MT8516 = "y"; + GPIOLIB = "y"; + GPIOLIB_FASTPATH_LIMIT = "512"; + OF_GPIO = "y"; + GPIOLIB_IRQCHIP = "y"; + GPIO_SYSFS = "y"; + GPIO_PCA953X = "m"; + GPIO_PCF857X = "m"; + GPIO_74X164 = "m"; + W1 = "m"; + W1_MASTER_DS2490 = "m"; + W1_MASTER_DS2482 = "m"; + W1_MASTER_GPIO = "m"; + W1_SLAVE_THERM = "m"; + W1_SLAVE_SMEM = "m"; + W1_SLAVE_DS2413 = "m"; + W1_SLAVE_DS2431 = "m"; + W1_SLAVE_DS2433 = "m"; + POWER_RESET = "y"; + POWER_RESET_SYSCON = "y"; + POWER_SUPPLY = "y"; + HWMON = "y"; + HWMON_VID = "m"; + SENSORS_AD7418 = "m"; + SENSORS_ADT7X10 = "m"; + SENSORS_ADT7410 = "m"; + SENSORS_ADT7475 = "m"; + SENSORS_DRIVETEMP = "m"; + SENSORS_GPIO_FAN = "m"; + SENSORS_IT87 = "m"; + SENSORS_LTC4151 = "m"; + SENSORS_MCP3021 = "m"; + SENSORS_ADCXX = "m"; + SENSORS_LM63 = "m"; + SENSORS_LM75 = "m"; + SENSORS_LM77 = "m"; + SENSORS_LM85 = "m"; + SENSORS_LM90 = "m"; + SENSORS_LM92 = "m"; + SENSORS_LM95241 = "m"; + PMBUS = "m"; + SENSORS_ZL6100 = "m"; + SENSORS_PWM_FAN = "y"; + SENSORS_SHT21 = "m"; + SENSORS_DME1737 = "m"; + SENSORS_SCH56XX_COMMON = "m"; + SENSORS_SCH5627 = "m"; + SENSORS_INA209 = "m"; + SENSORS_INA2XX = "m"; + SENSORS_TMP102 = "m"; + SENSORS_TMP103 = "m"; + SENSORS_TMP421 = "m"; + SENSORS_W83793 = "m"; + THERMAL = "y"; + THERMAL_EMERGENCY_POWEROFF_DELAY_MS = "0"; + THERMAL_OF = "y"; + THERMAL_WRITABLE_TRIPS = "y"; + THERMAL_DEFAULT_GOV_STEP_WISE = "y"; + THERMAL_GOV_FAIR_SHARE = "y"; + THERMAL_GOV_STEP_WISE = "y"; + THERMAL_GOV_BANG_BANG = "y"; + THERMAL_GOV_USER_SPACE = "y"; + # THERMAL_GOV_POWER_ALLOCATOR = "y"; + CPU_THERMAL = "y"; + CLOCK_THERMAL = "y"; + THERMAL_EMULATION = "y"; + MTK_THERMAL = "y"; + WATCHDOG = "y"; + WATCHDOG_CORE = "y"; + WATCHDOG_HANDLE_BOOT_ENABLED = "y"; + WATCHDOG_OPEN_TIMEOUT = "0"; + WATCHDOG_SYSFS = "y"; + WATCHDOG_PRETIMEOUT_GOV = "y"; + WATCHDOG_PRETIMEOUT_GOV_SEL = "m"; + WATCHDOG_PRETIMEOUT_GOV_PANIC = "y"; + WATCHDOG_PRETIMEOUT_DEFAULT_GOV_PANIC = "y"; + SOFT_WATCHDOG = "m"; + MEDIATEK_WATCHDOG = "y"; + SSB_POSSIBLE = "y"; + SSB = "m"; + SSB_SPROM = "y"; + # SSB_BLOCKIO = "y"; + SSB_PCIHOST_POSSIBLE = "y"; + SSB_PCIHOST = "y"; + # SSB_B43_PCI_BRIDGE = "y"; + SSB_SDIOHOST_POSSIBLE = "y"; + SSB_DRIVER_PCICORE_POSSIBLE = "y"; + SSB_DRIVER_PCICORE = "y"; + BCMA_POSSIBLE = "y"; + BCMA = "m"; + BCMA_BLOCKIO = "y"; + BCMA_HOST_PCI_POSSIBLE = "y"; + BCMA_HOST_PCI = "y"; + BCMA_DRIVER_PCI = "y"; + MFD_SYSCON = "y"; + REGULATOR = "y"; + REGULATOR_FIXED_VOLTAGE = "y"; + REGULATOR_MT6380 = "y"; + MEDIA_SUPPORT = "y"; + MEDIA_CAMERA_SUPPORT = "y"; + VIDEO_DEV = "y"; + VIDEO_V4L2 = "y"; + VIDEO_V4L2_I2C = "y"; + MEDIA_USB_SUPPORT = "y"; + USB_VIDEO_CLASS = "m"; + USB_VIDEO_CLASS_INPUT_EVDEV = "y"; + USB_GSPCA = "m"; + USB_M5602 = "m"; + USB_STV06XX = "m"; + USB_GL860 = "m"; + USB_GSPCA_CONEX = "m"; + USB_GSPCA_ETOMS = "m"; + USB_GSPCA_FINEPIX = "m"; + USB_GSPCA_JEILINJ = "m"; + USB_GSPCA_KONICA = "m"; + USB_GSPCA_MARS = "m"; + USB_GSPCA_MR97310A = "m"; + USB_GSPCA_OV519 = "m"; + USB_GSPCA_OV534 = "m"; + USB_GSPCA_OV534_9 = "m"; + USB_GSPCA_PAC207 = "m"; + USB_GSPCA_PAC7311 = "m"; + USB_GSPCA_SE401 = "m"; + USB_GSPCA_SN9C20X = "m"; + USB_GSPCA_SONIXB = "m"; + USB_GSPCA_SONIXJ = "m"; + USB_GSPCA_SPCA500 = "m"; + USB_GSPCA_SPCA501 = "m"; + USB_GSPCA_SPCA505 = "m"; + USB_GSPCA_SPCA506 = "m"; + USB_GSPCA_SPCA508 = "m"; + USB_GSPCA_SPCA561 = "m"; + USB_GSPCA_SQ905 = "m"; + USB_GSPCA_SQ905C = "m"; + USB_GSPCA_STK014 = "m"; + USB_GSPCA_SUNPLUS = "m"; + USB_GSPCA_T613 = "m"; + USB_GSPCA_TV8532 = "m"; + USB_GSPCA_VC032X = "m"; + USB_GSPCA_ZC3XX = "m"; + USB_PWC = "m"; + VIDEO_CPIA2 = "m"; + V4L_PLATFORM_DRIVERS = "y"; + VIDEOBUF2_CORE = "m"; + VIDEOBUF2_V4L2 = "m"; + VIDEOBUF2_MEMOPS = "m"; + VIDEOBUF2_VMALLOC = "m"; + DRM_RCAR_WRITEBACK = "y"; + SOUND = "m"; + SOUND_OSS_CORE = "y"; + SOUND_OSS_CORE_PRECLAIM = "y"; + SND = "m"; + SND_TIMER = "m"; + SND_PCM = "m"; + SND_HWDEP = "m"; + SND_SEQ_DEVICE = "m"; + SND_RAWMIDI = "m"; + # SND_COMPRESS_OFFLOAD = "m"; + SND_OSSEMUL = "y"; + SND_MIXER_OSS = "m"; + SND_PCM_OSS = "m"; + SND_PCM_OSS_PLUGINS = "y"; + SND_PCM_TIMER = "y"; + SND_PROC_FS = "y"; + SND_VERBOSE_PROCFS = "y"; + SND_VMASTER = "y"; + SND_SEQUENCER = "m"; + SND_SEQ_DUMMY = "m"; + SND_SEQUENCER_OSS = "m"; + SND_SEQ_MIDI_EVENT = "m"; + SND_SEQ_MIDI = "m"; + SND_SEQ_VIRMIDI = "m"; + SND_MPU401_UART = "m"; + SND_AC97_CODEC = "m"; + SND_DRIVERS = "y"; + SND_DUMMY = "m"; + SND_VIRMIDI = "m"; + SND_PCI = "y"; + SND_ENS1371 = "m"; + SND_INTEL8X0 = "m"; + SND_VIA82XX = "m"; + SND_HDA_PREALLOC_SIZE = "64"; + SND_USB = "y"; + SND_USB_AUDIO = "m"; + AC97_BUS = "m"; + HID = "m"; + HID_BATTERY_STRENGTH = "y"; + HIDRAW = "y"; + HID_GENERIC = "m"; + HID_CP2112 = "m"; + USB_HID = "m"; + USB_HIDDEV = "y"; + USB_OHCI_LITTLE_ENDIAN = "y"; + USB_SUPPORT = "y"; + USB_COMMON = "y"; + USB_ARCH_HAS_HCD = "y"; + USB = "y"; + USB_PCI = "y"; + USB_DEFAULT_PERSIST = "y"; + USB_LEDS_TRIGGER_USBPORT = "m"; + USB_AUTOSUSPEND_DELAY = "2"; + USB_MON = "m"; + USB_XHCI_HCD = "y"; + USB_XHCI_PCI = "y"; + USB_XHCI_PLATFORM = "m"; + USB_XHCI_MTK = "y"; + # USB_XHCI_MTK_DEBUGFS = "y"; + USB_EHCI_HCD = "m"; + USB_EHCI_ROOT_HUB_TT = "y"; + USB_EHCI_TT_NEWSCHED = "y"; + USB_EHCI_PCI = "m"; + USB_EHCI_FSL = "m"; + USB_EHCI_HCD_PLATFORM = "m"; + USB_OHCI_HCD = "m"; + USB_OHCI_HCD_PCI = "m"; + USB_OHCI_HCD_PLATFORM = "m"; + USB_UHCI_HCD = "m"; + USB_ACM = "m"; + USB_PRINTER = "m"; + USB_WDM = "m"; + USB_STORAGE = "y"; + USB_STORAGE_DATAFAB = "m"; + USB_STORAGE_FREECOM = "m"; + USB_STORAGE_ISD200 = "m"; + USB_STORAGE_USBAT = "m"; + USB_STORAGE_SDDR09 = "m"; + USB_STORAGE_SDDR55 = "m"; + USB_STORAGE_JUMPSHOT = "m"; + USB_STORAGE_ALAUDA = "m"; + USB_STORAGE_KARMA = "m"; + USB_STORAGE_CYPRESS_ATACB = "m"; + USB_UAS = "y"; + USBIP_CORE = "m"; + USBIP_VHCI_HCD = "m"; + USBIP_VHCI_HC_PORTS = "8"; + USBIP_VHCI_NR_HCS = "1"; + USBIP_HOST = "m"; + USB_DWC3 = "m"; + USB_DWC3_HOST = "y"; + USB_DWC2 = "m"; + USB_DWC2_HOST = "y"; + USB_DWC2_PCI = "m"; + USB_SERIAL = "m"; + USB_SERIAL_GENERIC = "y"; + USB_SERIAL_SIMPLE = "m"; + USB_SERIAL_ARK3116 = "m"; + USB_SERIAL_BELKIN = "m"; + USB_SERIAL_CH341 = "m"; + USB_SERIAL_CP210X = "m"; + USB_SERIAL_CYPRESS_M8 = "m"; + USB_SERIAL_FTDI_SIO = "m"; + USB_SERIAL_VISOR = "m"; + USB_SERIAL_EDGEPORT = "m"; + USB_SERIAL_GARMIN = "m"; + USB_SERIAL_IPW = "m"; + USB_SERIAL_KEYSPAN = "m"; + USB_SERIAL_MCT_U232 = "m"; + USB_SERIAL_MOS7720 = "m"; + USB_SERIAL_MOS7840 = "m"; + USB_SERIAL_PL2303 = "m"; + USB_SERIAL_OTI6858 = "m"; + USB_SERIAL_QUALCOMM = "m"; + USB_SERIAL_SIERRAWIRELESS = "m"; + USB_SERIAL_TI = "m"; + USB_SERIAL_WWAN = "m"; + USB_SERIAL_OPTION = "m"; + USB_EZUSB_FX2 = "m"; + USB_CHAOSKEY = "m"; + USB_ATM = "m"; + USB_SPEEDTOUCH = "m"; + USB_CXACRU = "m"; + USB_UEAGLEATM = "m"; + USB_PHY = "y"; + NOP_USB_XCEIV = "m"; + MMC = "y"; + PWRSEQ_EMMC = "y"; + PWRSEQ_SIMPLE = "y"; + MMC_BLOCK = "y"; + MMC_BLOCK_MINORS = "8"; + MMC_SDHCI = "m"; + MMC_SDHCI_PLTFM = "m"; + MMC_SPI = "m"; + MMC_MTK = "y"; + NEW_LEDS = "y"; + LEDS_CLASS = "y"; + LEDS_BRIGHTNESS_HW_CHANGED = "y"; + LEDS_GPIO = "m"; + LEDS_PCA963X = "m"; + LEDS_USER = "m"; + LEDS_TRIGGERS = "y"; + LEDS_TRIGGER_TIMER = "y"; + LEDS_TRIGGER_ONESHOT = "m"; + LEDS_TRIGGER_HEARTBEAT = "y"; + LEDS_TRIGGER_ACTIVITY = "m"; + LEDS_TRIGGER_GPIO = "m"; + LEDS_TRIGGER_DEFAULT_ON = "y"; + LEDS_TRIGGER_TRANSIENT = "m"; + LEDS_TRIGGER_NETDEV = "y"; + LEDS_TRIGGER_PATTERN = "m"; + EDAC_SUPPORT = "y"; + RTC_LIB = "y"; + RTC_CLASS = "y"; + RTC_HCTOSYS = "y"; + RTC_HCTOSYS_DEVICE = "rtc0"; + RTC_SYSTOHC = "y"; + RTC_SYSTOHC_DEVICE = "rtc0"; + RTC_INTF_SYSFS = "y"; + RTC_INTF_PROC = "y"; + RTC_INTF_DEV = "y"; + RTC_DRV_DS1307 = "m"; + RTC_DRV_DS1374 = "m"; + RTC_DRV_DS1672 = "m"; + RTC_DRV_RS5C372 = "m"; + RTC_DRV_ISL1208 = "m"; + RTC_DRV_PCF8563 = "m"; + RTC_DRV_S35390A = "m"; + RTC_DRV_RX8025 = "m"; + RTC_DRV_EM3027 = "m"; + RTC_DRV_PCF2123 = "m"; + RTC_I2C_AND_SPI = "y"; + RTC_DRV_PCF2127 = "m"; + RTC_DRV_MT7622 = "y"; + DMADEVICES = "y"; + DMA_ENGINE = "y"; + DMA_VIRTUAL_CHANNELS = "y"; + DMA_OF = "y"; + MTK_HSDMA = "y"; + DMATEST = "y"; + DMA_ENGINE_RAID = "y"; + VIRTIO_MENU = "y"; + STAGING = "y"; + R8712U = "m"; + CLKDEV_LOOKUP = "y"; + HAVE_CLK_PREPARE = "y"; + COMMON_CLK = "y"; + COMMON_CLK_MEDIATEK = "y"; + COMMON_CLK_MT2712 = "y"; + COMMON_CLK_MT7622 = "y"; + COMMON_CLK_MT7986 = "y"; + COMMON_CLK_MT8183 = "y"; + COMMON_CLK_MT8516 = "y"; + TIMER_OF = "y"; + TIMER_PROBE = "y"; + CLKSRC_MMIO = "y"; + ARM_ARCH_TIMER = "y"; + ARM_ARCH_TIMER_EVTSTREAM = "y"; + MTK_TIMER = "y"; + MTK_INFRACFG = "y"; + MTK_PMIC_WRAP = "y"; + MTK_SCPSYS = "y"; + EXTCON = "y"; + IIO = "y"; + IIO_BUFFER = "y"; + IIO_KFIFO_BUF = "m"; + IIO_TRIGGERED_BUFFER = "m"; + IIO_TRIGGER = "y"; + IIO_CONSUMERS_PER_TRIGGER = "2"; + IIO_ST_ACCEL_3AXIS = "m"; + IIO_ST_ACCEL_I2C_3AXIS = "m"; + IIO_ST_ACCEL_SPI_3AXIS = "m"; + AD799X = "m"; + MEDIATEK_MT6577_AUXADC = "y"; + BME680 = "m"; + BME680_I2C = "m"; + BME680_SPI = "m"; + CCS811 = "m"; + # SPS30 = "m"; + IIO_MS_SENSORS_I2C = "m"; + IIO_ST_SENSORS_I2C = "m"; + IIO_ST_SENSORS_SPI = "m"; + IIO_ST_SENSORS_CORE = "m"; + FXAS21002C = "m"; + FXAS21002C_I2C = "m"; + FXAS21002C_SPI = "m"; + AM2315 = "m"; + DHT11 = "m"; + HTU21 = "m"; + SI7020 = "m"; + FXOS8700 = "m"; + FXOS8700_I2C = "m"; + FXOS8700_SPI = "m"; + IIO_ST_LSM6DSX = "m"; + IIO_ST_LSM6DSX_I2C = "m"; + IIO_ST_LSM6DSX_SPI = "m"; + BH1750 = "m"; + TSL4531 = "m"; + SENSORS_HMC5843 = "m"; + SENSORS_HMC5843_I2C = "m"; + BMP280 = "m"; + BMP280_I2C = "m"; + BMP280_SPI = "m"; + PWM = "y"; + PWM_SYSFS = "y"; + PWM_MEDIATEK = "y"; + IRQCHIP = "y"; + ARM_GIC = "y"; + ARM_GIC_MAX_NR = "1"; + ARM_GIC_V2M = "y"; + ARM_GIC_V3 = "y"; + ARM_GIC_V3_ITS = "y"; + ARM_GIC_V3_ITS_PCI = "y"; + PARTITION_PERCPU = "y"; + RESET_CONTROLLER = "y"; + RESET_TI_SYSCON = "y"; + GENERIC_PHY = "y"; + PHY_MTK_TPHY = "y"; + RAS = "y"; + NVMEM = "y"; + NVMEM_SYSFS = "y"; + MTK_EFUSE = "y"; + PM_OPP = "y"; + DCACHE_WORD_ACCESS = "y"; + FS_IOMAP = "y"; + EXT4_FS = "m"; + EXT4_USE_FOR_EXT2 = "y"; + JBD2 = "m"; + FS_MBCACHE = "m"; + REISERFS_FS = "m"; + REISERFS_FS_XATTR = "y"; + JFS_FS = "m"; + XFS_FS = "m"; + BTRFS_FS = "m"; + F2FS_FS = "m"; + F2FS_STAT_FS = "y"; + F2FS_FS_XATTR = "y"; + FS_POSIX_ACL = "y"; + EXPORTFS = "y"; + FILE_LOCKING = "y"; + FSNOTIFY = "y"; + INOTIFY_USER = "y"; + FANOTIFY = "y"; + AUTOFS4_FS = "m"; + AUTOFS_FS = "m"; + FUSE_FS = "m"; + OVERLAY_FS = "y"; + OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW = "y"; + OVERLAY_FS_XINO_AUTO = "y"; + FSCACHE = "m"; + FSCACHE_STATS = "y"; + CACHEFILES = "m"; + ISO9660_FS = "m"; + JOLIET = "y"; + UDF_FS = "m"; + FAT_FS = "m"; + MSDOS_FS = "m"; + VFAT_FS = "m"; + FAT_DEFAULT_CODEPAGE = "437"; + FAT_DEFAULT_IOCHARSET = "iso8859-1"; + NTFS_FS = "m"; + PROC_FS = "y"; + PROC_SYSCTL = "y"; + KERNFS = "y"; + SYSFS = "y"; + TMPFS = "y"; + TMPFS_XATTR = "y"; + MEMFD_CREATE = "y"; + ARCH_HAS_GIGANTIC_PAGE = "y"; + CONFIGFS_FS = "m"; + MISC_FILESYSTEMS = "y"; + HFS_FS = "m"; + HFSPLUS_FS = "m"; + JFFS2_FS = "y"; + JFFS2_FS_DEBUG = "0"; + JFFS2_FS_WRITEBUFFER = "y"; + JFFS2_SUMMARY = "y"; + JFFS2_FS_XATTR = "y"; + JFFS2_COMPRESSION_OPTIONS = "y"; + JFFS2_LZMA = "y"; + JFFS2_RTIME = "y"; + JFFS2_CMODE_PRIORITY = "y"; + UBIFS_FS = "y"; + UBIFS_FS_ADVANCED_COMPR = "y"; + UBIFS_FS_LZO = "y"; + UBIFS_FS_ZLIB = "y"; + UBIFS_FS_XATTR = "y"; + CRAMFS = "m"; + CRAMFS_BLOCKDEV = "y"; + SQUASHFS = "y"; + SQUASHFS_FILE_DIRECT = "y"; + SQUASHFS_DECOMP_MULTI_PERCPU = "y"; + SQUASHFS_XZ = "y"; + SQUASHFS_EMBEDDED = "y"; + SQUASHFS_FRAGMENT_CACHE_SIZE = "3"; + MINIX_FS = "m"; + PSTORE = "y"; + PSTORE_CONSOLE = "y"; + PSTORE_PMSG = "y"; + PSTORE_RAM = "y"; + NETWORK_FILESYSTEMS = "y"; + NFS_FS = "m"; + NFS_V3 = "m"; + NFS_V4 = "m"; + NFS_USE_KERNEL_DNS = "y"; + NFSD = "m"; + NFSD_V3 = "y"; + NFSD_V4 = "y"; + GRACE_PERIOD = "m"; + LOCKD = "m"; + LOCKD_V4 = "y"; + NFS_COMMON = "y"; + SUNRPC = "m"; + SUNRPC_GSS = "m"; + RPCSEC_GSS_KRB5 = "m"; + SUNRPC_DISABLE_INSECURE_ENCTYPES = "y"; + CIFS = "m"; + CIFS_ALLOW_INSECURE_LEGACY = "y"; + CIFS_XATTR = "y"; + CIFS_POSIX = "y"; + NLS = "y"; + NLS_DEFAULT = "iso8859-1"; + NLS_CODEPAGE_437 = "m"; + NLS_CODEPAGE_775 = "m"; + NLS_CODEPAGE_850 = "m"; + NLS_CODEPAGE_852 = "m"; + NLS_CODEPAGE_862 = "m"; + NLS_CODEPAGE_864 = "m"; + NLS_CODEPAGE_866 = "m"; + NLS_CODEPAGE_936 = "m"; + NLS_CODEPAGE_950 = "m"; + NLS_CODEPAGE_932 = "m"; + NLS_ISO8859_8 = "m"; + NLS_CODEPAGE_1250 = "m"; + NLS_CODEPAGE_1251 = "m"; + NLS_ISO8859_1 = "m"; + NLS_ISO8859_2 = "m"; + NLS_ISO8859_6 = "m"; + NLS_ISO8859_13 = "m"; + NLS_ISO8859_15 = "m"; + NLS_KOI8_R = "m"; + NLS_UTF8 = "m"; + KEYS = "y"; + KEYS_COMPAT = "y"; + TRUSTED_KEYS = "m"; + ENCRYPTED_KEYS = "m"; + SECURITY_DMESG_RESTRICT = "y"; + HAVE_HARDENED_USERCOPY_ALLOCATOR = "y"; + HARDENED_USERCOPY = "y"; + FORTIFY_SOURCE = "y"; + DEFAULT_SECURITY_DAC = "y"; + LSM = "lockdown,yama,loadpin,safesetid,integrity"; + INIT_STACK_NONE = "y"; + XOR_BLOCKS = "m"; + ASYNC_CORE = "m"; + ASYNC_MEMCPY = "m"; + ASYNC_XOR = "m"; + ASYNC_PQ = "m"; + ASYNC_RAID6_RECOV = "m"; + CRYPTO = "y"; + CRYPTO_ALGAPI = "y"; + CRYPTO_ALGAPI2 = "y"; + CRYPTO_AEAD = "y"; + CRYPTO_AEAD2 = "y"; + CRYPTO_BLKCIPHER = "y"; + CRYPTO_BLKCIPHER2 = "y"; + CRYPTO_HASH = "y"; + CRYPTO_HASH2 = "y"; + CRYPTO_RNG = "y"; + CRYPTO_RNG2 = "y"; + CRYPTO_RNG_DEFAULT = "y"; + CRYPTO_KPP2 = "y"; + CRYPTO_KPP = "y"; + CRYPTO_ACOMP2 = "y"; + CRYPTO_MANAGER = "y"; + CRYPTO_MANAGER2 = "y"; + CRYPTO_USER = "m"; + CRYPTO_MANAGER_DISABLE_TESTS = "y"; + CRYPTO_GF128MUL = "m"; + CRYPTO_NULL = "y"; + CRYPTO_NULL2 = "y"; + CRYPTO_PCRYPT = "y"; + CRYPTO_CRYPTD = "y"; + CRYPTO_AUTHENC = "y"; + CRYPTO_TEST = "m"; + CRYPTO_ECC = "y"; + CRYPTO_ECDH = "y"; + CRYPTO_CCM = "m"; + CRYPTO_GCM = "m"; + CRYPTO_SEQIV = "m"; + CRYPTO_ECHAINIV = "y"; + CRYPTO_CBC = "y"; + CRYPTO_CTR = "m"; + CRYPTO_CTS = "m"; + CRYPTO_ECB = "y"; + CRYPTO_PCBC = "m"; + CRYPTO_XTS = "y"; + CRYPTO_ESSIV = "y"; + CRYPTO_CMAC = "y"; + CRYPTO_HMAC = "y"; + CRYPTO_XCBC = "m"; + CRYPTO_CRC32C = "m"; + CRYPTO_CRC32 = "m"; + CRYPTO_GHASH = "m"; + CRYPTO_MD4 = "m"; + CRYPTO_MD5 = "y"; + CRYPTO_MICHAEL_MIC = "m"; + CRYPTO_RMD160 = "m"; + CRYPTO_SHA1 = "y"; + CRYPTO_SHA256 = "y"; + CRYPTO_SHA512 = "y"; + CRYPTO_SHA3 = "y"; + CRYPTO_TGR192 = "m"; + CRYPTO_WP512 = "m"; + CRYPTO_AES = "y"; + CRYPTO_ANUBIS = "m"; + CRYPTO_ARC4 = "m"; + CRYPTO_BLOWFISH = "m"; + CRYPTO_BLOWFISH_COMMON = "m"; + CRYPTO_CAMELLIA = "m"; + CRYPTO_CAST_COMMON = "m"; + CRYPTO_CAST5 = "m"; + CRYPTO_CAST6 = "m"; + CRYPTO_DES = "y"; + CRYPTO_FCRYPT = "m"; + CRYPTO_KHAZAD = "m"; + CRYPTO_SERPENT = "m"; + CRYPTO_TEA = "m"; + CRYPTO_TWOFISH = "m"; + CRYPTO_TWOFISH_COMMON = "m"; + CRYPTO_DEFLATE = "y"; + CRYPTO_LZO = "y"; + CRYPTO_LZ4 = "m"; + CRYPTO_ZSTD = "m"; + CRYPTO_DRBG_MENU = "y"; + CRYPTO_DRBG_HMAC = "y"; + CRYPTO_DRBG = "y"; + CRYPTO_JITTERENTROPY = "y"; + CRYPTO_USER_API = "m"; + CRYPTO_USER_API_HASH = "m"; + CRYPTO_USER_API_SKCIPHER = "m"; + CRYPTO_USER_API_RNG = "m"; + CRYPTO_USER_API_AEAD = "m"; + CRYPTO_HASH_INFO = "y"; + CRYPTO_LIB_AES = "y"; + CRYPTO_LIB_ARC4 = "y"; + CRYPTO_ARCH_HAVE_LIB_CHACHA = "m"; + CRYPTO_LIB_CHACHA_GENERIC = "m"; + CRYPTO_LIB_CHACHA = "m"; + CRYPTO_LIB_CURVE25519_GENERIC = "m"; + CRYPTO_LIB_CURVE25519 = "m"; + CRYPTO_LIB_DES = "y"; + CRYPTO_LIB_POLY1305_RSIZE = "9"; + CRYPTO_ARCH_HAVE_LIB_POLY1305 = "m"; + CRYPTO_LIB_POLY1305 = "m"; + CRYPTO_LIB_CHACHA20POLY1305 = "m"; + CRYPTO_LIB_SHA256 = "y"; + CRYPTO_HW = "y"; + CRYPTO_DEV_SAFEXCEL = "y"; + RAID6_PQ = "m"; + BITREVERSE = "y"; + HAVE_ARCH_BITREVERSE = "y"; + GENERIC_STRNCPY_FROM_USER = "y"; + GENERIC_STRNLEN_USER = "y"; + GENERIC_NET_UTILS = "y"; + CORDIC = "m"; + RATIONAL = "y"; + GENERIC_PCI_IOMAP = "y"; + ARCH_USE_CMPXCHG_LOCKREF = "y"; + ARCH_HAS_FAST_MULTIPLIER = "y"; + CRC_CCITT = "m"; + CRC16 = "y"; + CRC_ITU_T = "m"; + CRC32 = "y"; + CRC32_SARWATE = "y"; + CRC7 = "m"; + LIBCRC32C = "m"; + CRC8 = "m"; + # XXHASH = "m"; + AUDIT_ARCH_COMPAT_GENERIC = "y"; + ZLIB_INFLATE = "y"; + ZLIB_DEFLATE = "y"; + LZO_COMPRESS = "y"; + LZO_DECOMPRESS = "y"; + LZ4_COMPRESS = "m"; + LZ4_DECOMPRESS = "m"; + # ZSTD_COMPRESS = "m"; + # ZSTD_DECOMPRESS = "m"; + XZ_DEC = "y"; + LZMA_COMPRESS = "y"; + LZMA_DECOMPRESS = "y"; + GENERIC_ALLOCATOR = "y"; + REED_SOLOMON = "y"; + REED_SOLOMON_ENC8 = "y"; + REED_SOLOMON_DEC8 = "y"; + TEXTSEARCH = "y"; + TEXTSEARCH_KMP = "m"; + TEXTSEARCH_BM = "m"; + TEXTSEARCH_FSM = "m"; + ASSOCIATIVE_ARRAY = "y"; + HAS_IOMEM = "y"; + HAS_IOPORT_MAP = "y"; + HAS_DMA = "y"; + NEED_SG_DMA_LENGTH = "y"; + NEED_DMA_MAP_STATE = "y"; + ARCH_DMA_ADDR_T_64BIT = "y"; + DMA_DECLARE_COHERENT = "y"; + ARCH_HAS_SETUP_DMA_OPS = "y"; + ARCH_HAS_SYNC_DMA_FOR_DEVICE = "y"; + ARCH_HAS_SYNC_DMA_FOR_CPU = "y"; + ARCH_HAS_DMA_PREP_COHERENT = "y"; + ARCH_HAS_DMA_COHERENT_TO_PFN = "y"; + SWIOTLB = "y"; + DMA_REMAP = "y"; + DMA_DIRECT_REMAP = "y"; + SGL_ALLOC = "y"; + CPU_RMAP = "y"; + DQL = "y"; + GLOB = "y"; + NLATTR = "y"; + DIMLIB = "y"; + LIBFDT = "y"; + OID_REGISTRY = "m"; + HAVE_GENERIC_VDSO = "y"; + GENERIC_GETTIMEOFDAY = "y"; + SG_POOL = "y"; + SBITMAP = "y"; + PRINTK_TIME = "y"; + CONSOLE_LOGLEVEL_DEFAULT = "15"; + CONSOLE_LOGLEVEL_QUIET = "4"; + MESSAGE_LOGLEVEL_DEFAULT = "7"; + DEBUG_INFO = "y"; + DEBUG_INFO_REDUCED = "y"; + FRAME_WARN = "1024"; + STRIP_ASM_SYMS = "y"; + DEBUG_FS = "y"; + OPTIMIZE_INLINING = "y"; + ARCH_WANT_FRAME_POINTERS = "y"; + FRAME_POINTER = "y"; + MAGIC_SYSRQ = "y"; + MAGIC_SYSRQ_DEFAULT_ENABLE = "0x1"; + MAGIC_SYSRQ_SERIAL = "y"; + DEBUG_KERNEL = "y"; + DEBUG_MISC = "y"; + HAVE_DEBUG_KMEMLEAK = "y"; + ARCH_HAS_DEBUG_VIRTUAL = "y"; + HAVE_ARCH_KASAN = "y"; + HAVE_ARCH_KASAN_SW_TAGS = "y"; + CC_HAS_KASAN_GENERIC = "y"; + KASAN_STACK = "1"; + ARCH_HAS_KCOV = "y"; + CC_HAS_SANCOV_TRACE_PC = "y"; + PANIC_ON_OOPS = "y"; + PANIC_ON_OOPS_VALUE = "1"; + PANIC_TIMEOUT = "1"; + LOCK_DEBUGGING_SUPPORT = "y"; + HAVE_DEBUG_BUGVERBOSE = "y"; + DEBUG_BUGVERBOSE = "y"; + RCU_CPU_STALL_TIMEOUT = "60"; + HAVE_FUNCTION_TRACER = "y"; + HAVE_FUNCTION_GRAPH_TRACER = "y"; + HAVE_DYNAMIC_FTRACE = "y"; + HAVE_FTRACE_MCOUNT_RECORD = "y"; + HAVE_SYSCALL_TRACEPOINTS = "y"; + HAVE_C_RECORDMCOUNT = "y"; + TRACING_SUPPORT = "y"; + RUNTIME_TESTING_MENU = "y"; + TEST_BPF = "m"; + HAVE_ARCH_KGDB = "y"; + ARCH_HAS_UBSAN_SANITIZE_ALL = "y"; + # UBSAN_ALIGNMENT = "y"; + ARCH_HAS_DEVMEM_IS_ALLOWED = "y"; diff --git a/routers/yada-house/kconf-from-openwrt.txt b/routers/yada-house/kconf-from-openwrt.txt new file mode 100644 index 0000000..a5f27e6 --- /dev/null +++ b/routers/yada-house/kconf-from-openwrt.txt @@ -0,0 +1,103 @@ +ARM="y"; +SYS_HAS_NONCACHED_MEMORY="y"; +POSITION_INDEPENDENT="y"; +ARCH_MEDIATEK="y"; +TEXT_BASE="0x41e00000"; +SYS_MALLOC_F_LEN="0x4000"; +NR_DRAM_BANKS="1"; +ENV_SIZE="0x80000"; +ENV_OFFSET="0x400000"; +DEFAULT_DEVICE_TREE="mt7986a-glinet-gl-mt6000"; +OF_LIBFDT_OVERLAY="y"; +TARGET_MT7986="y"; +SYS_LOAD_ADDR="0x46000000"; +PRE_CON_BUF_ADDR="0x4007EF00"; +DEBUG_UART_BASE="0x11002000"; +DEBUG_UART_CLOCK="40000000"; +DEBUG_UART="y"; +AHCI="y"; +FIT="y"; +AUTOBOOT_KEYED="y"; +AUTOBOOT_MENU_SHOW="y"; +DEFAULT_FDT_FILE="mediatek/mt7986a-glinet-gl-mt6000.dtb"; +LOGLEVEL="7"; +PRE_CONSOLE_BUFFER="y"; +LOG="y"; +BOARD_LATE_INIT="y"; +HUSH_PARSER="y"; +SYS_PROMPT="MT7986> "; +CMD_CPU="y"; +CMD_LICENSE="y"; +CMD_BOOTMENU="y"; +CMD_ASKENV="y"; +CMD_ERASEENV="y"; +CMD_ENV_FLAGS="y"; +CMD_STRINGS="y"; +CMD_DM="y"; +CMD_GPIO="y"; +CMD_PWM="y"; +CMD_GPT="y"; +CMD_MMC="y"; +CMD_PART="y"; +CMD_USB="y"; +CMD_TFTPSRV="y"; +CMD_RARP="y"; +CMD_CDP="y"; +CMD_SNTP="y"; +CMD_LINK_LOCAL="y"; +CMD_DHCP="y"; +CMD_DNS="y"; +CMD_PING="y"; +CMD_CACHE="y"; +CMD_PSTORE="y"; +CMD_PSTORE_MEM_ADDR="0x42ff0000"; +CMD_UUID="y"; +CMD_HASH="y"; +CMD_SMC="y"; +OF_EMBED="y"; +ENV_OVERWRITE="y"; +ENV_IS_IN_MMC="y"; +SYS_RELOC_GD_ENV_ADDR="y"; +USE_DEFAULT_ENV_FILE="y"; +DEFAULT_ENV_FILE="defenvs/glinet_gl-mt6000_env"; +ENV_VARS_UBOOT_RUNTIME_CONFIG="y"; +VERSION_VARIABLE="y"; +NETCONSOLE="y"; +USE_IPADDR="y"; +IPADDR="192.168.1.1"; +USE_SERVERIP="y"; +SERVERIP="192.168.1.254"; +NET_RANDOM_ETHADDR="y"; +BUTTON="y"; +BUTTON_GPIO="y"; +CLK="y"; +GPIO_HOG="y"; +LED="y"; +LED_BLINK="y"; +LED_GPIO="y"; +SUPPORT_EMMC_BOOT="y"; +MMC_HS200_SUPPORT="y"; +MMC_MTK="y"; +PHY_FIXED="y"; +MEDIATEK_ETH="y"; +PHY="y"; +PHY_MTK_TPHY="y"; +PINCTRL="y"; +PINCONF="y"; +PINCTRL_MT7986="y"; +POWER_DOMAIN="y"; +MTK_POWER_DOMAIN="y"; +DM_REGULATOR="y"; +DM_REGULATOR_FIXED="y"; +DM_REGULATOR_GPIO="y"; +DM_PWM="y"; +PWM_MTK="y"; +RAM="y"; +DM_SERIAL="y"; +SERIAL_RX_BUFFER="y"; +MTK_SERIAL="y"; +USB="y"; +USB_XHCI_HCD="y"; +USB_XHCI_MTK="y"; +USB_STORAGE="y"; +HEXDUMP="y"; diff --git a/routers/yada-house/mt7986a-glinet-gl-mt6000.dts b/routers/yada-house/mt7986a-glinet-gl-mt6000.dts new file mode 100644 index 0000000..529443a --- /dev/null +++ b/routers/yada-house/mt7986a-glinet-gl-mt6000.dts @@ -0,0 +1,356 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include +#include +#include + +#include "mt7986a.dtsi" + +/ { + model = "GL.iNet GL-MT6000"; + compatible = "glinet,gl-mt6000", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + label-mac-device = &gmac1; + led-boot = &led_blue; + led-failsafe = &led_blue; + led-running = &led_white; + led-upgrade = &led_white; + }; + + chosen { + stdout-path = "serial0:115200n8"; + bootargs-append = " root=PARTLABEL=rootfs rootwait"; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1.8vd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = ; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_blue: led-0 { + label = "blue:run"; + gpios = <&pio 38 GPIO_ACTIVE_LOW>; + }; + + led_white: led-1 { + label = "white:system"; + gpios = <&pio 37 GPIO_ACTIVE_LOW>; + }; + }; + + usb_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&pio 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + nvmem-cells = <&macaddr_factory_a 2>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + nvmem-cells = <&macaddr_factory_a 0>; + nvmem-cell-names = "mac-address"; + phy-mode = "2500base-x"; + phy-handle = <&phy1>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + phy1: phy@1 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <1>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + reset-gpios = <&pio 10 GPIO_ACTIVE_LOW>; + interrupt-parent = <&pio>; + interrupts = <46 IRQ_TYPE_LEVEL_LOW>; + realtek,aldps-enable; + }; + + phy7: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + reset-gpios = <&pio 19 GPIO_ACTIVE_LOW>; + interrupt-parent = <&pio>; + interrupts = <47 IRQ_TYPE_LEVEL_LOW>; + realtek,aldps-enable; + }; + + switch: switch@1f { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 18 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan2"; + }; + + port@1 { + reg = <1>; + label = "lan3"; + }; + + port@2 { + reg = <2>; + label = "lan4"; + }; + + port@3 { + reg = <3>; + label = "lan5"; + }; + + port@5 { + reg = <5>; + label = "lan1"; + phy-handle = <&phy7>; + phy-mode = "2500base-x"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; +}; + +&pio { + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = ; + }; + }; + + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = ; + bias-pull-up = ; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = ; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = ; + bias-pull-up = ; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = ; + bias-pull-up = ; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = ; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = ; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = ; + bias-pull-up = ; /* pull-up 10K */ + }; + }; +}; + +&crypto { + status = "okay"; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + nvmem-cells = <&eeprom_factory_0>; + nvmem-cell-names = "eeprom"; + pinctrl-names = "default"; + pinctrl-0 = <&wf_2g_5g_pins>; + status = "okay"; +}; + +&mmc0 { + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + no-sd; + no-sdio; + status = "okay"; + + card@0 { + compatible = "mmc-card"; + reg = <0>; + + block { + compatible = "block-device"; + partitions { + block-partition-env { + partname = "u-boot-env"; + + nvmem-layout { + compatible = "u-boot,env"; + }; + }; + + block-partition-factory { + partname = "factory"; + + nvmem-layout { + compatible = "fixed-layout"; + #address-cells = <1>; + #size-cells = <1>; + + eeprom_factory_0: eeprom@0 { + reg = <0x0 0x1000>; + }; + + macaddr_factory_a: macaddr@a { + compatible = "mac-base"; + reg = <0xa 0x6>; + #nvmem-cell-cells = <1>; + }; + }; + }; + }; + }; + }; +};