From d183bc5fd703aeacd2cff8a9589f016cc705004f Mon Sep 17 00:00:00 2001 From: janik Date: Wed, 15 Jul 2026 16:11:49 +0700 Subject: [PATCH] Document that via capping is deliberately not modeled, with error bound Layer-to-layer the cap (>=15 um plating per fab spec) is parallel to the annular-ring contact, so it cannot change the DC path. In-plane the model treats every via mouth as solid layer-thickness copper; the error is bounded by the dilute-hole correction (~ +2x mouth-area-fraction locally), partially offset by the unmodeled annular-ring copper, and typically well under a few percent of total R. Co-Authored-By: Claude Fable 5 --- README.md | 15 ++++++++++++--- fill_resistance/config.py | 10 ++++++---- 2 files changed, 18 insertions(+), 7 deletions(-) diff --git a/README.md b/README.md index ca18e8d..20011d1 100644 --- a/README.md +++ b/README.md @@ -70,9 +70,18 @@ SWIG API. Requires KiCad **10.0.1+**. barrel lengths. - Via/pad barrels: thin-wall annulus, R = ρ·L/(π·d·t_plating), `VIA_PLATING_UM = 18` in `fill_resistance/config.py`. Vias are always - plated; capped vs uncapped does not change the layer-to-layer DC path - (the ≥5 µm cap sits over the hole mouth in parallel with the - annular-ring contact, not in series). Per layer a barrel attaches to + plated. **Via capping is not modeled.** Layer-to-layer it cannot + matter at DC: the cap (≥15 µm plating per fab spec, thinner than the + foil) sits over the hole mouth in parallel with the annular-ring + contact, not in series. In-plane, the model treats every via mouth as + solid layer-thickness copper (KiCad fills do not subtract the drill), + where reality is a hole (uncapped) or the thin cap. The error is + bounded by the dilute-hole correction ρ_eff ≈ ρ·(1 + 2f) inside via + fields (f = mouth area fraction; 0.3 mm drills on a 1 mm grid give + f ≈ 7 % → ≈ +14 % locally), is partially offset by the unmodeled + annular-ring copper, and largely vanishes where the current descends + into the barrels anyway — typically ≪ a few % of the total R. + Per layer a barrel attaches to the fill cell under it, or to the nearest copper cell within the pad footprint plus one grid cell — fills joined by **thermal-relief spokes** still connect; wider antipads do not, and the barrel bridges diff --git a/fill_resistance/config.py b/fill_resistance/config.py index 732e25e..b1135c6 100644 --- a/fill_resistance/config.py +++ b/fill_resistance/config.py @@ -21,10 +21,12 @@ COPPER_THICKNESS_UM: float | None = None # None -> stackup, fallback 35.0 with FALLBACK_THICKNESS_UM = 35.0 TEST_CURRENT_A = 1.0 # default injected current (dialog/CLI-selectable) VIA_PLATING_UM = 18.0 # barrel plating thickness (always plated). - # Capped vs uncapped vias do not change the - # layer-to-layer DC path: the >=5um cap sits - # over the hole mouth in parallel with the - # annular-ring contact, not in series. + # Via capping is NOT modeled: layer-to-layer + # the cap (>=15um per fab spec, thinner than + # the foil) is parallel to the annular-ring + # contact, not in series; in-plane every via + # mouth is treated as solid layer-thickness + # copper (error bound: see README). INCLUDE_TH_PADS = True # plated through-hole pads stitch layers too SKIN_SIDES = 1 # skin-effect field config: 1 = plane facing a # return plane (conservative), 2 = isolated foil