feeder_mk2.elf: file format elf32-littlearm Sections: Idx Name Size VMA LMA File off Algn 0 .isr_vector 000000c0 08000000 08000000 00001000 2**0 CONTENTS, ALLOC, LOAD, READONLY, DATA 1 .text 00007c78 080000c0 080000c0 000010c0 2**2 CONTENTS, ALLOC, LOAD, READONLY, CODE 2 .rodata 00000154 08007d38 08007d38 00008d38 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 3 .ARM.extab 00000000 08007e8c 08007e8c 00009030 2**0 CONTENTS, READONLY 4 .ARM 00000008 08007e8c 08007e8c 00008e8c 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 5 .preinit_array 00000000 08007e94 08007e94 00009030 2**0 CONTENTS, ALLOC, LOAD, DATA 6 .init_array 00000004 08007e94 08007e94 00008e94 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 7 .fini_array 00000004 08007e98 08007e98 00008e98 2**2 CONTENTS, ALLOC, LOAD, READONLY, DATA 8 .data 00000030 20000000 08007e9c 00009000 2**2 CONTENTS, ALLOC, LOAD, DATA 9 .bss 00000580 20000030 08007ecc 00009030 2**2 ALLOC 10 ._user_heap_stack 00000600 200005b0 08007ecc 000095b0 2**0 ALLOC 11 .ARM.attributes 00000028 00000000 00000000 00009030 2**0 CONTENTS, READONLY 12 .debug_info 00011b87 00000000 00000000 00009058 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 13 .debug_abbrev 00002372 00000000 00000000 0001abdf 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 14 .debug_aranges 00000f58 00000000 00000000 0001cf58 2**3 CONTENTS, READONLY, DEBUGGING, OCTETS 15 .debug_rnglists 00000c68 00000000 00000000 0001deb0 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 16 .debug_macro 00014817 00000000 00000000 0001eb18 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 17 .debug_line 000126c2 00000000 00000000 0003332f 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 18 .debug_str 00084920 00000000 00000000 000459f1 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS 19 .comment 00000043 00000000 00000000 000ca311 2**0 CONTENTS, READONLY 20 .debug_frame 000038f8 00000000 00000000 000ca354 2**2 CONTENTS, READONLY, DEBUGGING, OCTETS 21 .debug_line_str 0000004d 00000000 00000000 000cdc4c 2**0 CONTENTS, READONLY, DEBUGGING, OCTETS Disassembly of section .text: 080000c0 <__do_global_dtors_aux>: 80000c0: b510 push {r4, lr} 80000c2: 4c06 ldr r4, [pc, #24] @ (80000dc <__do_global_dtors_aux+0x1c>) 80000c4: 7823 ldrb r3, [r4, #0] 80000c6: 2b00 cmp r3, #0 80000c8: d107 bne.n 80000da <__do_global_dtors_aux+0x1a> 80000ca: 4b05 ldr r3, [pc, #20] @ (80000e0 <__do_global_dtors_aux+0x20>) 80000cc: 2b00 cmp r3, #0 80000ce: d002 beq.n 80000d6 <__do_global_dtors_aux+0x16> 80000d0: 4804 ldr r0, [pc, #16] @ (80000e4 <__do_global_dtors_aux+0x24>) 80000d2: e000 b.n 80000d6 <__do_global_dtors_aux+0x16> 80000d4: bf00 nop 80000d6: 2301 movs r3, #1 80000d8: 7023 strb r3, [r4, #0] 80000da: bd10 pop {r4, pc} 80000dc: 20000030 .word 0x20000030 80000e0: 00000000 .word 0x00000000 80000e4: 08007d20 .word 0x08007d20 080000e8 : 80000e8: 4b04 ldr r3, [pc, #16] @ (80000fc ) 80000ea: b510 push {r4, lr} 80000ec: 2b00 cmp r3, #0 80000ee: d003 beq.n 80000f8 80000f0: 4903 ldr r1, [pc, #12] @ (8000100 ) 80000f2: 4804 ldr r0, [pc, #16] @ (8000104 ) 80000f4: e000 b.n 80000f8 80000f6: bf00 nop 80000f8: bd10 pop {r4, pc} 80000fa: 46c0 nop @ (mov r8, r8) 80000fc: 00000000 .word 0x00000000 8000100: 20000034 .word 0x20000034 8000104: 08007d20 .word 0x08007d20 08000108 <__udivsi3>: 8000108: 2200 movs r2, #0 800010a: 0843 lsrs r3, r0, #1 800010c: 428b cmp r3, r1 800010e: d374 bcc.n 80001fa <__udivsi3+0xf2> 8000110: 0903 lsrs r3, r0, #4 8000112: 428b cmp r3, r1 8000114: d35f bcc.n 80001d6 <__udivsi3+0xce> 8000116: 0a03 lsrs r3, r0, #8 8000118: 428b cmp r3, r1 800011a: d344 bcc.n 80001a6 <__udivsi3+0x9e> 800011c: 0b03 lsrs r3, r0, #12 800011e: 428b cmp r3, r1 8000120: d328 bcc.n 8000174 <__udivsi3+0x6c> 8000122: 0c03 lsrs r3, r0, #16 8000124: 428b cmp r3, r1 8000126: d30d bcc.n 8000144 <__udivsi3+0x3c> 8000128: 22ff movs r2, #255 @ 0xff 800012a: 0209 lsls r1, r1, #8 800012c: ba12 rev r2, r2 800012e: 0c03 lsrs r3, r0, #16 8000130: 428b cmp r3, r1 8000132: d302 bcc.n 800013a <__udivsi3+0x32> 8000134: 1212 asrs r2, r2, #8 8000136: 0209 lsls r1, r1, #8 8000138: d065 beq.n 8000206 <__udivsi3+0xfe> 800013a: 0b03 lsrs r3, r0, #12 800013c: 428b cmp r3, r1 800013e: d319 bcc.n 8000174 <__udivsi3+0x6c> 8000140: e000 b.n 8000144 <__udivsi3+0x3c> 8000142: 0a09 lsrs r1, r1, #8 8000144: 0bc3 lsrs r3, r0, #15 8000146: 428b cmp r3, r1 8000148: d301 bcc.n 800014e <__udivsi3+0x46> 800014a: 03cb lsls r3, r1, #15 800014c: 1ac0 subs r0, r0, r3 800014e: 4152 adcs r2, r2 8000150: 0b83 lsrs r3, r0, #14 8000152: 428b cmp r3, r1 8000154: d301 bcc.n 800015a <__udivsi3+0x52> 8000156: 038b lsls r3, r1, #14 8000158: 1ac0 subs r0, r0, r3 800015a: 4152 adcs r2, r2 800015c: 0b43 lsrs r3, r0, #13 800015e: 428b cmp r3, r1 8000160: d301 bcc.n 8000166 <__udivsi3+0x5e> 8000162: 034b lsls r3, r1, #13 8000164: 1ac0 subs r0, r0, r3 8000166: 4152 adcs r2, r2 8000168: 0b03 lsrs r3, r0, #12 800016a: 428b cmp r3, r1 800016c: d301 bcc.n 8000172 <__udivsi3+0x6a> 800016e: 030b lsls r3, r1, #12 8000170: 1ac0 subs r0, r0, r3 8000172: 4152 adcs r2, r2 8000174: 0ac3 lsrs r3, r0, #11 8000176: 428b cmp r3, r1 8000178: d301 bcc.n 800017e <__udivsi3+0x76> 800017a: 02cb lsls r3, r1, #11 800017c: 1ac0 subs r0, r0, r3 800017e: 4152 adcs r2, r2 8000180: 0a83 lsrs r3, r0, #10 8000182: 428b cmp r3, r1 8000184: d301 bcc.n 800018a <__udivsi3+0x82> 8000186: 028b lsls r3, r1, #10 8000188: 1ac0 subs r0, r0, r3 800018a: 4152 adcs r2, r2 800018c: 0a43 lsrs r3, r0, #9 800018e: 428b cmp r3, r1 8000190: d301 bcc.n 8000196 <__udivsi3+0x8e> 8000192: 024b lsls r3, r1, #9 8000194: 1ac0 subs r0, r0, r3 8000196: 4152 adcs r2, r2 8000198: 0a03 lsrs r3, r0, #8 800019a: 428b cmp r3, r1 800019c: d301 bcc.n 80001a2 <__udivsi3+0x9a> 800019e: 020b lsls r3, r1, #8 80001a0: 1ac0 subs r0, r0, r3 80001a2: 4152 adcs r2, r2 80001a4: d2cd bcs.n 8000142 <__udivsi3+0x3a> 80001a6: 09c3 lsrs r3, r0, #7 80001a8: 428b cmp r3, r1 80001aa: d301 bcc.n 80001b0 <__udivsi3+0xa8> 80001ac: 01cb lsls r3, r1, #7 80001ae: 1ac0 subs r0, r0, r3 80001b0: 4152 adcs r2, r2 80001b2: 0983 lsrs r3, r0, #6 80001b4: 428b cmp r3, r1 80001b6: d301 bcc.n 80001bc <__udivsi3+0xb4> 80001b8: 018b lsls r3, r1, #6 80001ba: 1ac0 subs r0, r0, r3 80001bc: 4152 adcs r2, r2 80001be: 0943 lsrs r3, r0, #5 80001c0: 428b cmp r3, r1 80001c2: d301 bcc.n 80001c8 <__udivsi3+0xc0> 80001c4: 014b lsls r3, r1, #5 80001c6: 1ac0 subs r0, r0, r3 80001c8: 4152 adcs r2, r2 80001ca: 0903 lsrs r3, r0, #4 80001cc: 428b cmp r3, r1 80001ce: d301 bcc.n 80001d4 <__udivsi3+0xcc> 80001d0: 010b lsls r3, r1, #4 80001d2: 1ac0 subs r0, r0, r3 80001d4: 4152 adcs r2, r2 80001d6: 08c3 lsrs r3, r0, #3 80001d8: 428b cmp r3, r1 80001da: d301 bcc.n 80001e0 <__udivsi3+0xd8> 80001dc: 00cb lsls r3, r1, #3 80001de: 1ac0 subs r0, r0, r3 80001e0: 4152 adcs r2, r2 80001e2: 0883 lsrs r3, r0, #2 80001e4: 428b cmp r3, r1 80001e6: d301 bcc.n 80001ec <__udivsi3+0xe4> 80001e8: 008b lsls r3, r1, #2 80001ea: 1ac0 subs r0, r0, r3 80001ec: 4152 adcs r2, r2 80001ee: 0843 lsrs r3, r0, #1 80001f0: 428b cmp r3, r1 80001f2: d301 bcc.n 80001f8 <__udivsi3+0xf0> 80001f4: 004b lsls r3, r1, #1 80001f6: 1ac0 subs r0, r0, r3 80001f8: 4152 adcs r2, r2 80001fa: 1a41 subs r1, r0, r1 80001fc: d200 bcs.n 8000200 <__udivsi3+0xf8> 80001fe: 4601 mov r1, r0 8000200: 4152 adcs r2, r2 8000202: 4610 mov r0, r2 8000204: 4770 bx lr 8000206: e7ff b.n 8000208 <__udivsi3+0x100> 8000208: b501 push {r0, lr} 800020a: 2000 movs r0, #0 800020c: f000 f8f0 bl 80003f0 <__aeabi_idiv0> 8000210: bd02 pop {r1, pc} 8000212: 46c0 nop @ (mov r8, r8) 08000214 <__aeabi_uidivmod>: 8000214: 2900 cmp r1, #0 8000216: d0f7 beq.n 8000208 <__udivsi3+0x100> 8000218: e776 b.n 8000108 <__udivsi3> 800021a: 4770 bx lr 0800021c <__divsi3>: 800021c: 4603 mov r3, r0 800021e: 430b orrs r3, r1 8000220: d47f bmi.n 8000322 <__divsi3+0x106> 8000222: 2200 movs r2, #0 8000224: 0843 lsrs r3, r0, #1 8000226: 428b cmp r3, r1 8000228: d374 bcc.n 8000314 <__divsi3+0xf8> 800022a: 0903 lsrs r3, r0, #4 800022c: 428b cmp r3, r1 800022e: d35f bcc.n 80002f0 <__divsi3+0xd4> 8000230: 0a03 lsrs r3, r0, #8 8000232: 428b cmp r3, r1 8000234: d344 bcc.n 80002c0 <__divsi3+0xa4> 8000236: 0b03 lsrs r3, r0, #12 8000238: 428b cmp r3, r1 800023a: d328 bcc.n 800028e <__divsi3+0x72> 800023c: 0c03 lsrs r3, r0, #16 800023e: 428b cmp r3, r1 8000240: d30d bcc.n 800025e <__divsi3+0x42> 8000242: 22ff movs r2, #255 @ 0xff 8000244: 0209 lsls r1, r1, #8 8000246: ba12 rev r2, r2 8000248: 0c03 lsrs r3, r0, #16 800024a: 428b cmp r3, r1 800024c: d302 bcc.n 8000254 <__divsi3+0x38> 800024e: 1212 asrs r2, r2, #8 8000250: 0209 lsls r1, r1, #8 8000252: d065 beq.n 8000320 <__divsi3+0x104> 8000254: 0b03 lsrs r3, r0, #12 8000256: 428b cmp r3, r1 8000258: d319 bcc.n 800028e <__divsi3+0x72> 800025a: e000 b.n 800025e <__divsi3+0x42> 800025c: 0a09 lsrs r1, r1, #8 800025e: 0bc3 lsrs r3, r0, #15 8000260: 428b cmp r3, r1 8000262: d301 bcc.n 8000268 <__divsi3+0x4c> 8000264: 03cb lsls r3, r1, #15 8000266: 1ac0 subs r0, r0, r3 8000268: 4152 adcs r2, r2 800026a: 0b83 lsrs r3, r0, #14 800026c: 428b cmp r3, r1 800026e: d301 bcc.n 8000274 <__divsi3+0x58> 8000270: 038b lsls r3, r1, #14 8000272: 1ac0 subs r0, r0, r3 8000274: 4152 adcs r2, r2 8000276: 0b43 lsrs r3, r0, #13 8000278: 428b cmp r3, r1 800027a: d301 bcc.n 8000280 <__divsi3+0x64> 800027c: 034b lsls r3, r1, #13 800027e: 1ac0 subs r0, r0, r3 8000280: 4152 adcs r2, r2 8000282: 0b03 lsrs r3, r0, #12 8000284: 428b cmp r3, r1 8000286: d301 bcc.n 800028c <__divsi3+0x70> 8000288: 030b lsls r3, r1, #12 800028a: 1ac0 subs r0, r0, r3 800028c: 4152 adcs r2, r2 800028e: 0ac3 lsrs r3, r0, #11 8000290: 428b cmp r3, r1 8000292: d301 bcc.n 8000298 <__divsi3+0x7c> 8000294: 02cb lsls r3, r1, #11 8000296: 1ac0 subs r0, r0, r3 8000298: 4152 adcs r2, r2 800029a: 0a83 lsrs r3, r0, #10 800029c: 428b cmp r3, r1 800029e: d301 bcc.n 80002a4 <__divsi3+0x88> 80002a0: 028b lsls r3, r1, #10 80002a2: 1ac0 subs r0, r0, r3 80002a4: 4152 adcs r2, r2 80002a6: 0a43 lsrs r3, r0, #9 80002a8: 428b cmp r3, r1 80002aa: d301 bcc.n 80002b0 <__divsi3+0x94> 80002ac: 024b lsls r3, r1, #9 80002ae: 1ac0 subs r0, r0, r3 80002b0: 4152 adcs r2, r2 80002b2: 0a03 lsrs r3, r0, #8 80002b4: 428b cmp r3, r1 80002b6: d301 bcc.n 80002bc <__divsi3+0xa0> 80002b8: 020b lsls r3, r1, #8 80002ba: 1ac0 subs r0, r0, r3 80002bc: 4152 adcs r2, r2 80002be: d2cd bcs.n 800025c <__divsi3+0x40> 80002c0: 09c3 lsrs r3, r0, #7 80002c2: 428b cmp r3, r1 80002c4: d301 bcc.n 80002ca <__divsi3+0xae> 80002c6: 01cb lsls r3, r1, #7 80002c8: 1ac0 subs r0, r0, r3 80002ca: 4152 adcs r2, r2 80002cc: 0983 lsrs r3, r0, #6 80002ce: 428b cmp r3, r1 80002d0: d301 bcc.n 80002d6 <__divsi3+0xba> 80002d2: 018b lsls r3, r1, #6 80002d4: 1ac0 subs r0, r0, r3 80002d6: 4152 adcs r2, r2 80002d8: 0943 lsrs r3, r0, #5 80002da: 428b cmp r3, r1 80002dc: d301 bcc.n 80002e2 <__divsi3+0xc6> 80002de: 014b lsls r3, r1, #5 80002e0: 1ac0 subs r0, r0, r3 80002e2: 4152 adcs r2, r2 80002e4: 0903 lsrs r3, r0, #4 80002e6: 428b cmp r3, r1 80002e8: d301 bcc.n 80002ee <__divsi3+0xd2> 80002ea: 010b lsls r3, r1, #4 80002ec: 1ac0 subs r0, r0, r3 80002ee: 4152 adcs r2, r2 80002f0: 08c3 lsrs r3, r0, #3 80002f2: 428b cmp r3, r1 80002f4: d301 bcc.n 80002fa <__divsi3+0xde> 80002f6: 00cb lsls r3, r1, #3 80002f8: 1ac0 subs r0, r0, r3 80002fa: 4152 adcs r2, r2 80002fc: 0883 lsrs r3, r0, #2 80002fe: 428b cmp r3, r1 8000300: d301 bcc.n 8000306 <__divsi3+0xea> 8000302: 008b lsls r3, r1, #2 8000304: 1ac0 subs r0, r0, r3 8000306: 4152 adcs r2, r2 8000308: 0843 lsrs r3, r0, #1 800030a: 428b cmp r3, r1 800030c: d301 bcc.n 8000312 <__divsi3+0xf6> 800030e: 004b lsls r3, r1, #1 8000310: 1ac0 subs r0, r0, r3 8000312: 4152 adcs r2, r2 8000314: 1a41 subs r1, r0, r1 8000316: d200 bcs.n 800031a <__divsi3+0xfe> 8000318: 4601 mov r1, r0 800031a: 4152 adcs r2, r2 800031c: 4610 mov r0, r2 800031e: 4770 bx lr 8000320: e05d b.n 80003de <__divsi3+0x1c2> 8000322: 0fca lsrs r2, r1, #31 8000324: d000 beq.n 8000328 <__divsi3+0x10c> 8000326: 4249 negs r1, r1 8000328: 1003 asrs r3, r0, #32 800032a: d300 bcc.n 800032e <__divsi3+0x112> 800032c: 4240 negs r0, r0 800032e: 4053 eors r3, r2 8000330: 2200 movs r2, #0 8000332: 469c mov ip, r3 8000334: 0903 lsrs r3, r0, #4 8000336: 428b cmp r3, r1 8000338: d32d bcc.n 8000396 <__divsi3+0x17a> 800033a: 0a03 lsrs r3, r0, #8 800033c: 428b cmp r3, r1 800033e: d312 bcc.n 8000366 <__divsi3+0x14a> 8000340: 22fc movs r2, #252 @ 0xfc 8000342: 0189 lsls r1, r1, #6 8000344: ba12 rev r2, r2 8000346: 0a03 lsrs r3, r0, #8 8000348: 428b cmp r3, r1 800034a: d30c bcc.n 8000366 <__divsi3+0x14a> 800034c: 0189 lsls r1, r1, #6 800034e: 1192 asrs r2, r2, #6 8000350: 428b cmp r3, r1 8000352: d308 bcc.n 8000366 <__divsi3+0x14a> 8000354: 0189 lsls r1, r1, #6 8000356: 1192 asrs r2, r2, #6 8000358: 428b cmp r3, r1 800035a: d304 bcc.n 8000366 <__divsi3+0x14a> 800035c: 0189 lsls r1, r1, #6 800035e: d03a beq.n 80003d6 <__divsi3+0x1ba> 8000360: 1192 asrs r2, r2, #6 8000362: e000 b.n 8000366 <__divsi3+0x14a> 8000364: 0989 lsrs r1, r1, #6 8000366: 09c3 lsrs r3, r0, #7 8000368: 428b cmp r3, r1 800036a: d301 bcc.n 8000370 <__divsi3+0x154> 800036c: 01cb lsls r3, r1, #7 800036e: 1ac0 subs r0, r0, r3 8000370: 4152 adcs r2, r2 8000372: 0983 lsrs r3, r0, #6 8000374: 428b cmp r3, r1 8000376: d301 bcc.n 800037c <__divsi3+0x160> 8000378: 018b lsls r3, r1, #6 800037a: 1ac0 subs r0, r0, r3 800037c: 4152 adcs r2, r2 800037e: 0943 lsrs r3, r0, #5 8000380: 428b cmp r3, r1 8000382: d301 bcc.n 8000388 <__divsi3+0x16c> 8000384: 014b lsls r3, r1, #5 8000386: 1ac0 subs r0, r0, r3 8000388: 4152 adcs r2, r2 800038a: 0903 lsrs r3, r0, #4 800038c: 428b cmp r3, r1 800038e: d301 bcc.n 8000394 <__divsi3+0x178> 8000390: 010b lsls r3, r1, #4 8000392: 1ac0 subs r0, r0, r3 8000394: 4152 adcs r2, r2 8000396: 08c3 lsrs r3, r0, #3 8000398: 428b cmp r3, r1 800039a: d301 bcc.n 80003a0 <__divsi3+0x184> 800039c: 00cb lsls r3, r1, #3 800039e: 1ac0 subs r0, r0, r3 80003a0: 4152 adcs r2, r2 80003a2: 0883 lsrs r3, r0, #2 80003a4: 428b cmp r3, r1 80003a6: d301 bcc.n 80003ac <__divsi3+0x190> 80003a8: 008b lsls r3, r1, #2 80003aa: 1ac0 subs r0, r0, r3 80003ac: 4152 adcs r2, r2 80003ae: d2d9 bcs.n 8000364 <__divsi3+0x148> 80003b0: 0843 lsrs r3, r0, #1 80003b2: 428b cmp r3, r1 80003b4: d301 bcc.n 80003ba <__divsi3+0x19e> 80003b6: 004b lsls r3, r1, #1 80003b8: 1ac0 subs r0, r0, r3 80003ba: 4152 adcs r2, r2 80003bc: 1a41 subs r1, r0, r1 80003be: d200 bcs.n 80003c2 <__divsi3+0x1a6> 80003c0: 4601 mov r1, r0 80003c2: 4663 mov r3, ip 80003c4: 4152 adcs r2, r2 80003c6: 105b asrs r3, r3, #1 80003c8: 4610 mov r0, r2 80003ca: d301 bcc.n 80003d0 <__divsi3+0x1b4> 80003cc: 4240 negs r0, r0 80003ce: 2b00 cmp r3, #0 80003d0: d500 bpl.n 80003d4 <__divsi3+0x1b8> 80003d2: 4249 negs r1, r1 80003d4: 4770 bx lr 80003d6: 4663 mov r3, ip 80003d8: 105b asrs r3, r3, #1 80003da: d300 bcc.n 80003de <__divsi3+0x1c2> 80003dc: 4240 negs r0, r0 80003de: b501 push {r0, lr} 80003e0: 2000 movs r0, #0 80003e2: f000 f805 bl 80003f0 <__aeabi_idiv0> 80003e6: bd02 pop {r1, pc} 080003e8 <__aeabi_idivmod>: 80003e8: 2900 cmp r1, #0 80003ea: d0f8 beq.n 80003de <__divsi3+0x1c2> 80003ec: e716 b.n 800021c <__divsi3> 80003ee: 4770 bx lr 080003f0 <__aeabi_idiv0>: 80003f0: 4770 bx lr 80003f2: 46c0 nop @ (mov r8, r8) 080003f4 <__aeabi_ldivmod>: 80003f4: 2b00 cmp r3, #0 80003f6: d115 bne.n 8000424 <__aeabi_ldivmod+0x30> 80003f8: 2a00 cmp r2, #0 80003fa: d113 bne.n 8000424 <__aeabi_ldivmod+0x30> 80003fc: 2900 cmp r1, #0 80003fe: db06 blt.n 800040e <__aeabi_ldivmod+0x1a> 8000400: dc01 bgt.n 8000406 <__aeabi_ldivmod+0x12> 8000402: 2800 cmp r0, #0 8000404: d006 beq.n 8000414 <__aeabi_ldivmod+0x20> 8000406: 2000 movs r0, #0 8000408: 43c0 mvns r0, r0 800040a: 0841 lsrs r1, r0, #1 800040c: e002 b.n 8000414 <__aeabi_ldivmod+0x20> 800040e: 2180 movs r1, #128 @ 0x80 8000410: 0609 lsls r1, r1, #24 8000412: 2000 movs r0, #0 8000414: b407 push {r0, r1, r2} 8000416: 4802 ldr r0, [pc, #8] @ (8000420 <__aeabi_ldivmod+0x2c>) 8000418: a101 add r1, pc, #4 @ (adr r1, 8000420 <__aeabi_ldivmod+0x2c>) 800041a: 1840 adds r0, r0, r1 800041c: 9002 str r0, [sp, #8] 800041e: bd03 pop {r0, r1, pc} 8000420: ffffffd1 .word 0xffffffd1 8000424: b403 push {r0, r1} 8000426: 4668 mov r0, sp 8000428: b501 push {r0, lr} 800042a: 9802 ldr r0, [sp, #8] 800042c: f000 f834 bl 8000498 <__gnu_ldivmod_helper> 8000430: 9b01 ldr r3, [sp, #4] 8000432: 469e mov lr, r3 8000434: b002 add sp, #8 8000436: bc0c pop {r2, r3} 8000438: 4770 bx lr 800043a: 46c0 nop @ (mov r8, r8) 0800043c <__aeabi_lmul>: 800043c: b5f0 push {r4, r5, r6, r7, lr} 800043e: 46ce mov lr, r9 8000440: 4699 mov r9, r3 8000442: 0c03 lsrs r3, r0, #16 8000444: 469c mov ip, r3 8000446: 0413 lsls r3, r2, #16 8000448: 4647 mov r7, r8 800044a: 0c1b lsrs r3, r3, #16 800044c: 001d movs r5, r3 800044e: 000e movs r6, r1 8000450: 4661 mov r1, ip 8000452: 0404 lsls r4, r0, #16 8000454: 0c24 lsrs r4, r4, #16 8000456: b580 push {r7, lr} 8000458: 0007 movs r7, r0 800045a: 0c10 lsrs r0, r2, #16 800045c: 434b muls r3, r1 800045e: 4365 muls r5, r4 8000460: 4341 muls r1, r0 8000462: 4360 muls r0, r4 8000464: 0c2c lsrs r4, r5, #16 8000466: 18c0 adds r0, r0, r3 8000468: 1824 adds r4, r4, r0 800046a: 468c mov ip, r1 800046c: 42a3 cmp r3, r4 800046e: d903 bls.n 8000478 <__aeabi_lmul+0x3c> 8000470: 2380 movs r3, #128 @ 0x80 8000472: 025b lsls r3, r3, #9 8000474: 4698 mov r8, r3 8000476: 44c4 add ip, r8 8000478: 4649 mov r1, r9 800047a: 4379 muls r1, r7 800047c: 4356 muls r6, r2 800047e: 0c23 lsrs r3, r4, #16 8000480: 042d lsls r5, r5, #16 8000482: 0c2d lsrs r5, r5, #16 8000484: 1989 adds r1, r1, r6 8000486: 4463 add r3, ip 8000488: 0424 lsls r4, r4, #16 800048a: 1960 adds r0, r4, r5 800048c: 18c9 adds r1, r1, r3 800048e: bcc0 pop {r6, r7} 8000490: 46b9 mov r9, r7 8000492: 46b0 mov r8, r6 8000494: bdf0 pop {r4, r5, r6, r7, pc} 8000496: 46c0 nop @ (mov r8, r8) 08000498 <__gnu_ldivmod_helper>: 8000498: b5f8 push {r3, r4, r5, r6, r7, lr} 800049a: 46ce mov lr, r9 800049c: 4647 mov r7, r8 800049e: b580 push {r7, lr} 80004a0: 4691 mov r9, r2 80004a2: 4698 mov r8, r3 80004a4: 0004 movs r4, r0 80004a6: 000d movs r5, r1 80004a8: f000 f814 bl 80004d4 <__divdi3> 80004ac: 0007 movs r7, r0 80004ae: 000e movs r6, r1 80004b0: 0002 movs r2, r0 80004b2: 000b movs r3, r1 80004b4: 4648 mov r0, r9 80004b6: 4641 mov r1, r8 80004b8: f7ff ffc0 bl 800043c <__aeabi_lmul> 80004bc: 1a24 subs r4, r4, r0 80004be: 418d sbcs r5, r1 80004c0: 9b08 ldr r3, [sp, #32] 80004c2: 0038 movs r0, r7 80004c4: 0031 movs r1, r6 80004c6: 601c str r4, [r3, #0] 80004c8: 605d str r5, [r3, #4] 80004ca: bcc0 pop {r6, r7} 80004cc: 46b9 mov r9, r7 80004ce: 46b0 mov r8, r6 80004d0: bdf8 pop {r3, r4, r5, r6, r7, pc} 80004d2: 46c0 nop @ (mov r8, r8) 080004d4 <__divdi3>: 80004d4: b5f0 push {r4, r5, r6, r7, lr} 80004d6: 464f mov r7, r9 80004d8: 4646 mov r6, r8 80004da: 46d6 mov lr, sl 80004dc: b5c0 push {r6, r7, lr} 80004de: 0006 movs r6, r0 80004e0: 000f movs r7, r1 80004e2: 0010 movs r0, r2 80004e4: 0019 movs r1, r3 80004e6: b082 sub sp, #8 80004e8: 2f00 cmp r7, #0 80004ea: db5d blt.n 80005a8 <__divdi3+0xd4> 80004ec: 0034 movs r4, r6 80004ee: 003d movs r5, r7 80004f0: 2b00 cmp r3, #0 80004f2: db0b blt.n 800050c <__divdi3+0x38> 80004f4: 0016 movs r6, r2 80004f6: 001f movs r7, r3 80004f8: 42ab cmp r3, r5 80004fa: d917 bls.n 800052c <__divdi3+0x58> 80004fc: 2000 movs r0, #0 80004fe: 2100 movs r1, #0 8000500: b002 add sp, #8 8000502: bce0 pop {r5, r6, r7} 8000504: 46ba mov sl, r7 8000506: 46b1 mov r9, r6 8000508: 46a8 mov r8, r5 800050a: bdf0 pop {r4, r5, r6, r7, pc} 800050c: 2700 movs r7, #0 800050e: 4246 negs r6, r0 8000510: 418f sbcs r7, r1 8000512: 42af cmp r7, r5 8000514: d8f2 bhi.n 80004fc <__divdi3+0x28> 8000516: d100 bne.n 800051a <__divdi3+0x46> 8000518: e0a0 b.n 800065c <__divdi3+0x188> 800051a: 2301 movs r3, #1 800051c: 425b negs r3, r3 800051e: 4699 mov r9, r3 8000520: e009 b.n 8000536 <__divdi3+0x62> 8000522: 2700 movs r7, #0 8000524: 4246 negs r6, r0 8000526: 418f sbcs r7, r1 8000528: 42af cmp r7, r5 800052a: d8e7 bhi.n 80004fc <__divdi3+0x28> 800052c: 42af cmp r7, r5 800052e: d100 bne.n 8000532 <__divdi3+0x5e> 8000530: e090 b.n 8000654 <__divdi3+0x180> 8000532: 2300 movs r3, #0 8000534: 4699 mov r9, r3 8000536: 0039 movs r1, r7 8000538: 0030 movs r0, r6 800053a: f000 f8b7 bl 80006ac <__clzdi2> 800053e: 4680 mov r8, r0 8000540: 0029 movs r1, r5 8000542: 0020 movs r0, r4 8000544: f000 f8b2 bl 80006ac <__clzdi2> 8000548: 4643 mov r3, r8 800054a: 1a1b subs r3, r3, r0 800054c: 4698 mov r8, r3 800054e: 3b20 subs r3, #32 8000550: d475 bmi.n 800063e <__divdi3+0x16a> 8000552: 0031 movs r1, r6 8000554: 4099 lsls r1, r3 8000556: 469a mov sl, r3 8000558: 000b movs r3, r1 800055a: 0031 movs r1, r6 800055c: 4640 mov r0, r8 800055e: 4081 lsls r1, r0 8000560: 000a movs r2, r1 8000562: 42ab cmp r3, r5 8000564: d82e bhi.n 80005c4 <__divdi3+0xf0> 8000566: d02b beq.n 80005c0 <__divdi3+0xec> 8000568: 4651 mov r1, sl 800056a: 1aa4 subs r4, r4, r2 800056c: 419d sbcs r5, r3 800056e: 2900 cmp r1, #0 8000570: da00 bge.n 8000574 <__divdi3+0xa0> 8000572: e090 b.n 8000696 <__divdi3+0x1c2> 8000574: 2100 movs r1, #0 8000576: 2000 movs r0, #0 8000578: 2601 movs r6, #1 800057a: 9000 str r0, [sp, #0] 800057c: 9101 str r1, [sp, #4] 800057e: 4651 mov r1, sl 8000580: 408e lsls r6, r1 8000582: 9601 str r6, [sp, #4] 8000584: 4641 mov r1, r8 8000586: 2601 movs r6, #1 8000588: 408e lsls r6, r1 800058a: 4641 mov r1, r8 800058c: 9600 str r6, [sp, #0] 800058e: 2900 cmp r1, #0 8000590: d11f bne.n 80005d2 <__divdi3+0xfe> 8000592: 9800 ldr r0, [sp, #0] 8000594: 9901 ldr r1, [sp, #4] 8000596: 464b mov r3, r9 8000598: 2b00 cmp r3, #0 800059a: d0b1 beq.n 8000500 <__divdi3+0x2c> 800059c: 0003 movs r3, r0 800059e: 000c movs r4, r1 80005a0: 2100 movs r1, #0 80005a2: 4258 negs r0, r3 80005a4: 41a1 sbcs r1, r4 80005a6: e7ab b.n 8000500 <__divdi3+0x2c> 80005a8: 2500 movs r5, #0 80005aa: 4274 negs r4, r6 80005ac: 41bd sbcs r5, r7 80005ae: 2b00 cmp r3, #0 80005b0: dbb7 blt.n 8000522 <__divdi3+0x4e> 80005b2: 0016 movs r6, r2 80005b4: 001f movs r7, r3 80005b6: 42ab cmp r3, r5 80005b8: d8a0 bhi.n 80004fc <__divdi3+0x28> 80005ba: 42af cmp r7, r5 80005bc: d1ad bne.n 800051a <__divdi3+0x46> 80005be: e04d b.n 800065c <__divdi3+0x188> 80005c0: 42a1 cmp r1, r4 80005c2: d9d1 bls.n 8000568 <__divdi3+0x94> 80005c4: 2100 movs r1, #0 80005c6: 2000 movs r0, #0 80005c8: 9000 str r0, [sp, #0] 80005ca: 9101 str r1, [sp, #4] 80005cc: 4641 mov r1, r8 80005ce: 2900 cmp r1, #0 80005d0: d0df beq.n 8000592 <__divdi3+0xbe> 80005d2: 07d9 lsls r1, r3, #31 80005d4: 0856 lsrs r6, r2, #1 80005d6: 085f lsrs r7, r3, #1 80005d8: 430e orrs r6, r1 80005da: 4643 mov r3, r8 80005dc: e00e b.n 80005fc <__divdi3+0x128> 80005de: 42af cmp r7, r5 80005e0: d101 bne.n 80005e6 <__divdi3+0x112> 80005e2: 42a6 cmp r6, r4 80005e4: d80c bhi.n 8000600 <__divdi3+0x12c> 80005e6: 1ba4 subs r4, r4, r6 80005e8: 41bd sbcs r5, r7 80005ea: 2101 movs r1, #1 80005ec: 1924 adds r4, r4, r4 80005ee: 416d adcs r5, r5 80005f0: 2200 movs r2, #0 80005f2: 3b01 subs r3, #1 80005f4: 1864 adds r4, r4, r1 80005f6: 4155 adcs r5, r2 80005f8: 2b00 cmp r3, #0 80005fa: d006 beq.n 800060a <__divdi3+0x136> 80005fc: 42af cmp r7, r5 80005fe: d9ee bls.n 80005de <__divdi3+0x10a> 8000600: 3b01 subs r3, #1 8000602: 1924 adds r4, r4, r4 8000604: 416d adcs r5, r5 8000606: 2b00 cmp r3, #0 8000608: d1f8 bne.n 80005fc <__divdi3+0x128> 800060a: 9a00 ldr r2, [sp, #0] 800060c: 9b01 ldr r3, [sp, #4] 800060e: 4651 mov r1, sl 8000610: 1912 adds r2, r2, r4 8000612: 416b adcs r3, r5 8000614: 2900 cmp r1, #0 8000616: db25 blt.n 8000664 <__divdi3+0x190> 8000618: 002e movs r6, r5 800061a: 002c movs r4, r5 800061c: 40ce lsrs r6, r1 800061e: 4641 mov r1, r8 8000620: 40cc lsrs r4, r1 8000622: 4651 mov r1, sl 8000624: 2900 cmp r1, #0 8000626: db2d blt.n 8000684 <__divdi3+0x1b0> 8000628: 0034 movs r4, r6 800062a: 408c lsls r4, r1 800062c: 0021 movs r1, r4 800062e: 4644 mov r4, r8 8000630: 40a6 lsls r6, r4 8000632: 0030 movs r0, r6 8000634: 1a12 subs r2, r2, r0 8000636: 418b sbcs r3, r1 8000638: 9200 str r2, [sp, #0] 800063a: 9301 str r3, [sp, #4] 800063c: e7a9 b.n 8000592 <__divdi3+0xbe> 800063e: 4642 mov r2, r8 8000640: 0038 movs r0, r7 8000642: 469a mov sl, r3 8000644: 2320 movs r3, #32 8000646: 0031 movs r1, r6 8000648: 4090 lsls r0, r2 800064a: 1a9b subs r3, r3, r2 800064c: 40d9 lsrs r1, r3 800064e: 0003 movs r3, r0 8000650: 430b orrs r3, r1 8000652: e782 b.n 800055a <__divdi3+0x86> 8000654: 42a6 cmp r6, r4 8000656: d900 bls.n 800065a <__divdi3+0x186> 8000658: e750 b.n 80004fc <__divdi3+0x28> 800065a: e76a b.n 8000532 <__divdi3+0x5e> 800065c: 42a6 cmp r6, r4 800065e: d800 bhi.n 8000662 <__divdi3+0x18e> 8000660: e75b b.n 800051a <__divdi3+0x46> 8000662: e74b b.n 80004fc <__divdi3+0x28> 8000664: 4640 mov r0, r8 8000666: 2120 movs r1, #32 8000668: 1a09 subs r1, r1, r0 800066a: 0028 movs r0, r5 800066c: 4088 lsls r0, r1 800066e: 0026 movs r6, r4 8000670: 0001 movs r1, r0 8000672: 4640 mov r0, r8 8000674: 40c6 lsrs r6, r0 8000676: 002c movs r4, r5 8000678: 430e orrs r6, r1 800067a: 4641 mov r1, r8 800067c: 40cc lsrs r4, r1 800067e: 4651 mov r1, sl 8000680: 2900 cmp r1, #0 8000682: dad1 bge.n 8000628 <__divdi3+0x154> 8000684: 4640 mov r0, r8 8000686: 2120 movs r1, #32 8000688: 0035 movs r5, r6 800068a: 4084 lsls r4, r0 800068c: 1a09 subs r1, r1, r0 800068e: 40cd lsrs r5, r1 8000690: 0021 movs r1, r4 8000692: 4329 orrs r1, r5 8000694: e7cb b.n 800062e <__divdi3+0x15a> 8000696: 4641 mov r1, r8 8000698: 2620 movs r6, #32 800069a: 2701 movs r7, #1 800069c: 1a76 subs r6, r6, r1 800069e: 2000 movs r0, #0 80006a0: 2100 movs r1, #0 80006a2: 40f7 lsrs r7, r6 80006a4: 9000 str r0, [sp, #0] 80006a6: 9101 str r1, [sp, #4] 80006a8: 9701 str r7, [sp, #4] 80006aa: e76b b.n 8000584 <__divdi3+0xb0> 080006ac <__clzdi2>: 80006ac: b510 push {r4, lr} 80006ae: 2900 cmp r1, #0 80006b0: d103 bne.n 80006ba <__clzdi2+0xe> 80006b2: f000 f807 bl 80006c4 <__clzsi2> 80006b6: 3020 adds r0, #32 80006b8: e002 b.n 80006c0 <__clzdi2+0x14> 80006ba: 0008 movs r0, r1 80006bc: f000 f802 bl 80006c4 <__clzsi2> 80006c0: bd10 pop {r4, pc} 80006c2: 46c0 nop @ (mov r8, r8) 080006c4 <__clzsi2>: 80006c4: 211c movs r1, #28 80006c6: 2301 movs r3, #1 80006c8: 041b lsls r3, r3, #16 80006ca: 4298 cmp r0, r3 80006cc: d301 bcc.n 80006d2 <__clzsi2+0xe> 80006ce: 0c00 lsrs r0, r0, #16 80006d0: 3910 subs r1, #16 80006d2: 0a1b lsrs r3, r3, #8 80006d4: 4298 cmp r0, r3 80006d6: d301 bcc.n 80006dc <__clzsi2+0x18> 80006d8: 0a00 lsrs r0, r0, #8 80006da: 3908 subs r1, #8 80006dc: 091b lsrs r3, r3, #4 80006de: 4298 cmp r0, r3 80006e0: d301 bcc.n 80006e6 <__clzsi2+0x22> 80006e2: 0900 lsrs r0, r0, #4 80006e4: 3904 subs r1, #4 80006e6: a202 add r2, pc, #8 @ (adr r2, 80006f0 <__clzsi2+0x2c>) 80006e8: 5c10 ldrb r0, [r2, r0] 80006ea: 1840 adds r0, r0, r1 80006ec: 4770 bx lr 80006ee: 46c0 nop @ (mov r8, r8) 80006f0: 02020304 .word 0x02020304 80006f4: 01010101 .word 0x01010101 ... 08000700 : */ #include "crc.h" void CRC8_107_add(CRC8_107 *ctx, uint8_t data) { 8000700: b580 push {r7, lr} 8000702: b084 sub sp, #16 8000704: af00 add r7, sp, #0 8000706: 6078 str r0, [r7, #4] 8000708: 000a movs r2, r1 800070a: 1cfb adds r3, r7, #3 800070c: 701a strb r2, [r3, #0] ctx->crc ^= ((uint32_t)data << 8); 800070e: 687b ldr r3, [r7, #4] 8000710: 681a ldr r2, [r3, #0] 8000712: 1cfb adds r3, r7, #3 8000714: 781b ldrb r3, [r3, #0] 8000716: 021b lsls r3, r3, #8 8000718: 405a eors r2, r3 800071a: 687b ldr r3, [r7, #4] 800071c: 601a str r2, [r3, #0] for (size_t bit_n = 0; bit_n < 8; bit_n++) { 800071e: 2300 movs r3, #0 8000720: 60fb str r3, [r7, #12] 8000722: e013 b.n 800074c if (ctx->crc & 0x8000u) { 8000724: 687b ldr r3, [r7, #4] 8000726: 681a ldr r2, [r3, #0] 8000728: 2380 movs r3, #128 @ 0x80 800072a: 021b lsls r3, r3, #8 800072c: 4013 ands r3, r2 800072e: d005 beq.n 800073c ctx->crc ^= ((uint32_t)0x1070u << 3); // same as 0x8380 8000730: 687b ldr r3, [r7, #4] 8000732: 681b ldr r3, [r3, #0] 8000734: 4a09 ldr r2, [pc, #36] @ (800075c ) 8000736: 405a eors r2, r3 8000738: 687b ldr r3, [r7, #4] 800073a: 601a str r2, [r3, #0] } ctx->crc <<= 1; 800073c: 687b ldr r3, [r7, #4] 800073e: 681b ldr r3, [r3, #0] 8000740: 005a lsls r2, r3, #1 8000742: 687b ldr r3, [r7, #4] 8000744: 601a str r2, [r3, #0] for (size_t bit_n = 0; bit_n < 8; bit_n++) { 8000746: 68fb ldr r3, [r7, #12] 8000748: 3301 adds r3, #1 800074a: 60fb str r3, [r7, #12] 800074c: 68fb ldr r3, [r7, #12] 800074e: 2b07 cmp r3, #7 8000750: d9e8 bls.n 8000724 } } 8000752: 46c0 nop @ (mov r8, r8) 8000754: 46c0 nop @ (mov r8, r8) 8000756: 46bd mov sp, r7 8000758: b004 add sp, #16 800075a: bd80 pop {r7, pc} 800075c: 00008380 .word 0x00008380 08000760 : uint8_t CRC8_107_getChecksum(const CRC8_107 *ctx) { 8000760: b580 push {r7, lr} 8000762: b082 sub sp, #8 8000764: af00 add r7, sp, #0 8000766: 6078 str r0, [r7, #4] return (uint8_t)(ctx->crc >> 8); 8000768: 687b ldr r3, [r7, #4] 800076a: 681b ldr r3, [r3, #0] 800076c: 0a1b lsrs r3, r3, #8 800076e: b2db uxtb r3, r3 } 8000770: 0018 movs r0, r3 8000772: 46bd mov sp, r7 8000774: b002 add sp, #8 8000776: bd80 pop {r7, pc} 08000778 <__NVIC_SystemReset>: /** \brief System Reset \details Initiates a system reset request to reset the MCU. */ __NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) { 8000778: b580 push {r7, lr} 800077a: af00 add r7, sp, #0 \details Acts as a special kind of Data Memory Barrier. It completes when all explicit memory accesses before this instruction complete. */ __STATIC_FORCEINLINE void __DSB(void) { __ASM volatile ("dsb 0xF":::"memory"); 800077c: f3bf 8f4f dsb sy } 8000780: 46c0 nop @ (mov r8, r8) __DSB(); /* Ensure all outstanding memory accesses included buffered write are completed before reset */ SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | 8000782: 4b04 ldr r3, [pc, #16] @ (8000794 <__NVIC_SystemReset+0x1c>) 8000784: 4a04 ldr r2, [pc, #16] @ (8000798 <__NVIC_SystemReset+0x20>) 8000786: 60da str r2, [r3, #12] __ASM volatile ("dsb 0xF":::"memory"); 8000788: f3bf 8f4f dsb sy } 800078c: 46c0 nop @ (mov r8, r8) SCB_AIRCR_SYSRESETREQ_Msk); __DSB(); /* Ensure completion of memory access */ for(;;) /* wait until reset */ { __NOP(); 800078e: 46c0 nop @ (mov r8, r8) 8000790: e7fd b.n 800078e <__NVIC_SystemReset+0x16> 8000792: 46c0 nop @ (mov r8, r8) 8000794: e000ed00 .word 0xe000ed00 8000798: 05fa0004 .word 0x05fa0004 0800079c : uint16_t pwm; // 0..out_max uint8_t dir; // 0 or 1 } pid_motor_cmd_t; static inline int32_t clamp_i32(int32_t x, int32_t lo, int32_t hi) { 800079c: b580 push {r7, lr} 800079e: b084 sub sp, #16 80007a0: af00 add r7, sp, #0 80007a2: 60f8 str r0, [r7, #12] 80007a4: 60b9 str r1, [r7, #8] 80007a6: 607a str r2, [r7, #4] if (x < lo) return lo; 80007a8: 68fa ldr r2, [r7, #12] 80007aa: 68bb ldr r3, [r7, #8] 80007ac: 429a cmp r2, r3 80007ae: da01 bge.n 80007b4 80007b0: 68bb ldr r3, [r7, #8] 80007b2: e006 b.n 80007c2 if (x > hi) return hi; 80007b4: 68fa ldr r2, [r7, #12] 80007b6: 687b ldr r3, [r7, #4] 80007b8: 429a cmp r2, r3 80007ba: dd01 ble.n 80007c0 80007bc: 687b ldr r3, [r7, #4] 80007be: e000 b.n 80007c2 return x; 80007c0: 68fb ldr r3, [r7, #12] } 80007c2: 0018 movs r0, r3 80007c4: 46bd mov sp, r7 80007c6: b004 add sp, #16 80007c8: bd80 pop {r7, pc} 080007ca : int32_t kd, int32_t integrator_min, int32_t integrator_max, int32_t out_max, int32_t max_output_step) { 80007ca: b580 push {r7, lr} 80007cc: b084 sub sp, #16 80007ce: af00 add r7, sp, #0 80007d0: 60f8 str r0, [r7, #12] 80007d2: 60b9 str r1, [r7, #8] 80007d4: 607a str r2, [r7, #4] 80007d6: 603b str r3, [r7, #0] pid->kp = kp; 80007d8: 68fb ldr r3, [r7, #12] 80007da: 68ba ldr r2, [r7, #8] 80007dc: 601a str r2, [r3, #0] pid->ki = ki; 80007de: 68fb ldr r3, [r7, #12] 80007e0: 687a ldr r2, [r7, #4] 80007e2: 605a str r2, [r3, #4] pid->kd = kd; 80007e4: 68fb ldr r3, [r7, #12] 80007e6: 683a ldr r2, [r7, #0] 80007e8: 609a str r2, [r3, #8] pid->integrator = 0; 80007ea: 68fb ldr r3, [r7, #12] 80007ec: 2200 movs r2, #0 80007ee: 60da str r2, [r3, #12] pid->prev_error = 0; 80007f0: 68fb ldr r3, [r7, #12] 80007f2: 2200 movs r2, #0 80007f4: 611a str r2, [r3, #16] pid->integrator_min = integrator_min; 80007f6: 68fb ldr r3, [r7, #12] 80007f8: 69ba ldr r2, [r7, #24] 80007fa: 615a str r2, [r3, #20] pid->integrator_max = integrator_max; 80007fc: 68fb ldr r3, [r7, #12] 80007fe: 69fa ldr r2, [r7, #28] 8000800: 619a str r2, [r3, #24] pid->out_max = out_max; 8000802: 68fb ldr r3, [r7, #12] 8000804: 6a3a ldr r2, [r7, #32] 8000806: 61da str r2, [r3, #28] pid->max_output_step = max_output_step; 8000808: 68fb ldr r3, [r7, #12] 800080a: 6a7a ldr r2, [r7, #36] @ 0x24 800080c: 621a str r2, [r3, #32] pid->last_output = 0; 800080e: 68fb ldr r3, [r7, #12] 8000810: 2200 movs r2, #0 8000812: 625a str r2, [r3, #36] @ 0x24 } 8000814: 46c0 nop @ (mov r8, r8) 8000816: 46bd mov sp, r7 8000818: b004 add sp, #16 800081a: bd80 pop {r7, pc} 0800081c : static inline void pid_reset(pid_i32_t *pid) { 800081c: b580 push {r7, lr} 800081e: b082 sub sp, #8 8000820: af00 add r7, sp, #0 8000822: 6078 str r0, [r7, #4] pid->integrator = 0; 8000824: 687b ldr r3, [r7, #4] 8000826: 2200 movs r2, #0 8000828: 60da str r2, [r3, #12] pid->prev_error = 0; 800082a: 687b ldr r3, [r7, #4] 800082c: 2200 movs r2, #0 800082e: 611a str r2, [r3, #16] pid->last_output = 0; 8000830: 687b ldr r3, [r7, #4] 8000832: 2200 movs r2, #0 8000834: 625a str r2, [r3, #36] @ 0x24 } 8000836: 46c0 nop @ (mov r8, r8) 8000838: 46bd mov sp, r7 800083a: b002 add sp, #8 800083c: bd80 pop {r7, pc} 0800083e : static inline pid_motor_cmd_t pid_update_motor(pid_i32_t *pid, int32_t setpoint, int32_t position) { 800083e: b580 push {r7, lr} 8000840: b090 sub sp, #64 @ 0x40 8000842: af00 add r7, sp, #0 8000844: 60f8 str r0, [r7, #12] 8000846: 60b9 str r1, [r7, #8] 8000848: 607a str r2, [r7, #4] pid_motor_cmd_t cmd; int32_t error = setpoint - position; 800084a: 68ba ldr r2, [r7, #8] 800084c: 687b ldr r3, [r7, #4] 800084e: 1ad3 subs r3, r2, r3 8000850: 637b str r3, [r7, #52] @ 0x34 // Deadband: if within ±3 counts, hold position and reset integrator if (error >= -3 && error <= 3) { 8000852: 6b7b ldr r3, [r7, #52] @ 0x34 8000854: 3303 adds r3, #3 8000856: db18 blt.n 800088a 8000858: 6b7b ldr r3, [r7, #52] @ 0x34 800085a: 2b03 cmp r3, #3 800085c: dc15 bgt.n 800088a pid->integrator = 0; 800085e: 68fb ldr r3, [r7, #12] 8000860: 2200 movs r2, #0 8000862: 60da str r2, [r3, #12] pid->prev_error = 0; 8000864: 68fb ldr r3, [r7, #12] 8000866: 2200 movs r2, #0 8000868: 611a str r2, [r3, #16] pid->last_output = 0; 800086a: 68fb ldr r3, [r7, #12] 800086c: 2200 movs r2, #0 800086e: 625a str r2, [r3, #36] @ 0x24 cmd.pwm = 0; 8000870: 2110 movs r1, #16 8000872: 187b adds r3, r7, r1 8000874: 2200 movs r2, #0 8000876: 801a strh r2, [r3, #0] cmd.dir = 1; 8000878: 187b adds r3, r7, r1 800087a: 2201 movs r2, #1 800087c: 709a strb r2, [r3, #2] return cmd; 800087e: 2314 movs r3, #20 8000880: 18fb adds r3, r7, r3 8000882: 187a adds r2, r7, r1 8000884: 6812 ldr r2, [r2, #0] 8000886: 601a str r2, [r3, #0] 8000888: e08e b.n 80009a8 } int32_t p = pid->kp * error; 800088a: 68fb ldr r3, [r7, #12] 800088c: 681a ldr r2, [r3, #0] 800088e: 6b7b ldr r3, [r7, #52] @ 0x34 8000890: 4353 muls r3, r2 8000892: 633b str r3, [r7, #48] @ 0x30 int32_t i = pid->integrator + pid->ki * error; 8000894: 68fb ldr r3, [r7, #12] 8000896: 68da ldr r2, [r3, #12] 8000898: 68fb ldr r3, [r7, #12] 800089a: 685b ldr r3, [r3, #4] 800089c: 6b79 ldr r1, [r7, #52] @ 0x34 800089e: 434b muls r3, r1 80008a0: 18d3 adds r3, r2, r3 80008a2: 62fb str r3, [r7, #44] @ 0x2c i = clamp_i32(i, pid->integrator_min, pid->integrator_max); 80008a4: 68fb ldr r3, [r7, #12] 80008a6: 6959 ldr r1, [r3, #20] 80008a8: 68fb ldr r3, [r7, #12] 80008aa: 699a ldr r2, [r3, #24] 80008ac: 6afb ldr r3, [r7, #44] @ 0x2c 80008ae: 0018 movs r0, r3 80008b0: f7ff ff74 bl 800079c 80008b4: 0003 movs r3, r0 80008b6: 62fb str r3, [r7, #44] @ 0x2c pid->integrator = i; 80008b8: 68fb ldr r3, [r7, #12] 80008ba: 6afa ldr r2, [r7, #44] @ 0x2c 80008bc: 60da str r2, [r3, #12] int32_t d_error = error - pid->prev_error; 80008be: 68fb ldr r3, [r7, #12] 80008c0: 691b ldr r3, [r3, #16] 80008c2: 6b7a ldr r2, [r7, #52] @ 0x34 80008c4: 1ad3 subs r3, r2, r3 80008c6: 62bb str r3, [r7, #40] @ 0x28 int32_t d = pid->kd * d_error; 80008c8: 68fb ldr r3, [r7, #12] 80008ca: 689a ldr r2, [r3, #8] 80008cc: 6abb ldr r3, [r7, #40] @ 0x28 80008ce: 4353 muls r3, r2 80008d0: 627b str r3, [r7, #36] @ 0x24 pid->prev_error = error; 80008d2: 68fb ldr r3, [r7, #12] 80008d4: 6b7a ldr r2, [r7, #52] @ 0x34 80008d6: 611a str r2, [r3, #16] // Raw control effort int32_t u_raw = p + i + d; 80008d8: 6b3a ldr r2, [r7, #48] @ 0x30 80008da: 6afb ldr r3, [r7, #44] @ 0x2c 80008dc: 18d3 adds r3, r2, r3 80008de: 6a7a ldr r2, [r7, #36] @ 0x24 80008e0: 18d3 adds r3, r2, r3 80008e2: 63fb str r3, [r7, #60] @ 0x3c // Clamp to [-out_max, +out_max] if (u_raw > pid->out_max) u_raw = pid->out_max; 80008e4: 68fb ldr r3, [r7, #12] 80008e6: 69db ldr r3, [r3, #28] 80008e8: 6bfa ldr r2, [r7, #60] @ 0x3c 80008ea: 429a cmp r2, r3 80008ec: dd02 ble.n 80008f4 80008ee: 68fb ldr r3, [r7, #12] 80008f0: 69db ldr r3, [r3, #28] 80008f2: 63fb str r3, [r7, #60] @ 0x3c if (u_raw < -pid->out_max) u_raw = -pid->out_max; 80008f4: 68fb ldr r3, [r7, #12] 80008f6: 69db ldr r3, [r3, #28] 80008f8: 425b negs r3, r3 80008fa: 6bfa ldr r2, [r7, #60] @ 0x3c 80008fc: 429a cmp r2, r3 80008fe: da03 bge.n 8000908 8000900: 68fb ldr r3, [r7, #12] 8000902: 69db ldr r3, [r3, #28] 8000904: 425b negs r3, r3 8000906: 63fb str r3, [r7, #60] @ 0x3c // ---------- Slew limit: avoid instant full reverse ---------- int32_t u_prev = pid->last_output; 8000908: 68fb ldr r3, [r7, #12] 800090a: 6a5b ldr r3, [r3, #36] @ 0x24 800090c: 623b str r3, [r7, #32] int32_t u = u_raw; 800090e: 6bfb ldr r3, [r7, #60] @ 0x3c 8000910: 63bb str r3, [r7, #56] @ 0x38 int32_t max_step = pid->max_output_step; 8000912: 68fb ldr r3, [r7, #12] 8000914: 6a1b ldr r3, [r3, #32] 8000916: 61fb str r3, [r7, #28] if (max_step > 0) { 8000918: 69fb ldr r3, [r7, #28] 800091a: 2b00 cmp r3, #0 800091c: dd18 ble.n 8000950 int32_t du = u_raw - u_prev; 800091e: 6bfa ldr r2, [r7, #60] @ 0x3c 8000920: 6a3b ldr r3, [r7, #32] 8000922: 1ad3 subs r3, r2, r3 8000924: 61bb str r3, [r7, #24] if (du > max_step) { 8000926: 69ba ldr r2, [r7, #24] 8000928: 69fb ldr r3, [r7, #28] 800092a: 429a cmp r2, r3 800092c: dd04 ble.n 8000938 u = u_prev + max_step; 800092e: 6a3a ldr r2, [r7, #32] 8000930: 69fb ldr r3, [r7, #28] 8000932: 18d3 adds r3, r2, r3 8000934: 63bb str r3, [r7, #56] @ 0x38 8000936: e00b b.n 8000950 } else if (du < -max_step) { 8000938: 69fb ldr r3, [r7, #28] 800093a: 425b negs r3, r3 800093c: 69ba ldr r2, [r7, #24] 800093e: 429a cmp r2, r3 8000940: da04 bge.n 800094c u = u_prev - max_step; 8000942: 6a3a ldr r2, [r7, #32] 8000944: 69fb ldr r3, [r7, #28] 8000946: 1ad3 subs r3, r2, r3 8000948: 63bb str r3, [r7, #56] @ 0x38 800094a: e001 b.n 8000950 } else { u = u_raw; 800094c: 6bfb ldr r3, [r7, #60] @ 0x3c 800094e: 63bb str r3, [r7, #56] @ 0x38 } } // Save for next time pid->last_output = u; 8000950: 68fb ldr r3, [r7, #12] 8000952: 6bba ldr r2, [r7, #56] @ 0x38 8000954: 625a str r2, [r3, #36] @ 0x24 // Map signed u to dir + pwm if (u >= 0) { 8000956: 6bbb ldr r3, [r7, #56] @ 0x38 8000958: 2b00 cmp r3, #0 800095a: db08 blt.n 800096e cmd.dir = 1; 800095c: 2110 movs r1, #16 800095e: 187b adds r3, r7, r1 8000960: 2201 movs r2, #1 8000962: 709a strb r2, [r3, #2] cmd.pwm = (uint16_t)u; 8000964: 6bbb ldr r3, [r7, #56] @ 0x38 8000966: b29a uxth r2, r3 8000968: 187b adds r3, r7, r1 800096a: 801a strh r2, [r3, #0] 800096c: e009 b.n 8000982 } else { cmd.dir = 0; 800096e: 2110 movs r1, #16 8000970: 187b adds r3, r7, r1 8000972: 2200 movs r2, #0 8000974: 709a strb r2, [r3, #2] cmd.pwm = (uint16_t)(-u); 8000976: 6bbb ldr r3, [r7, #56] @ 0x38 8000978: b29b uxth r3, r3 800097a: 425b negs r3, r3 800097c: b29a uxth r2, r3 800097e: 187b adds r3, r7, r1 8000980: 801a strh r2, [r3, #0] } if (cmd.pwm > pid->out_max) 8000982: 2110 movs r1, #16 8000984: 187b adds r3, r7, r1 8000986: 881b ldrh r3, [r3, #0] 8000988: 001a movs r2, r3 800098a: 68fb ldr r3, [r7, #12] 800098c: 69db ldr r3, [r3, #28] 800098e: 429a cmp r2, r3 8000990: dd04 ble.n 800099c cmd.pwm = (uint16_t)pid->out_max; 8000992: 68fb ldr r3, [r7, #12] 8000994: 69db ldr r3, [r3, #28] 8000996: b29a uxth r2, r3 8000998: 187b adds r3, r7, r1 800099a: 801a strh r2, [r3, #0] return cmd; 800099c: 2314 movs r3, #20 800099e: 18fb adds r3, r7, r3 80009a0: 2210 movs r2, #16 80009a2: 18ba adds r2, r7, r2 80009a4: 6812 ldr r2, [r2, #0] 80009a6: 601a str r2, [r3, #0] } 80009a8: 2314 movs r3, #20 80009aa: 18fa adds r2, r7, r3 80009ac: 2300 movs r3, #0 80009ae: 8811 ldrh r1, [r2, #0] 80009b0: 0409 lsls r1, r1, #16 80009b2: 0c09 lsrs r1, r1, #16 80009b4: 0c1b lsrs r3, r3, #16 80009b6: 041b lsls r3, r3, #16 80009b8: 430b orrs r3, r1 80009ba: 8852 ldrh r2, [r2, #2] 80009bc: 0412 lsls r2, r2, #16 80009be: 041b lsls r3, r3, #16 80009c0: 0c1b lsrs r3, r3, #16 80009c2: 4313 orrs r3, r2 80009c4: 0018 movs r0, r3 80009c6: 46bd mov sp, r7 80009c8: b010 add sp, #64 @ 0x40 80009ca: bd80 pop {r7, pc} 080009cc : typedef struct { uint32_t crc; } CRC8_107; static inline void CRC8_107_init(CRC8_107 *ctx) { 80009cc: b580 push {r7, lr} 80009ce: b082 sub sp, #8 80009d0: af00 add r7, sp, #0 80009d2: 6078 str r0, [r7, #4] ctx->crc = 0x0u; 80009d4: 687b ldr r3, [r7, #4] 80009d6: 2200 movs r2, #0 80009d8: 601a str r2, [r3, #0] } 80009da: 46c0 nop @ (mov r8, r8) 80009dc: 46bd mov sp, r7 80009de: b002 add sp, #8 80009e0: bd80 pop {r7, pc} ... 080009e4
: /** * @brief The application entry point. * @retval int */ int main(void) { 80009e4: b5f0 push {r4, r5, r6, r7, lr} 80009e6: b08b sub sp, #44 @ 0x2c 80009e8: af04 add r7, sp, #16 /* USER CODE END 1 */ /* MCU Configuration--------------------------------------------------------*/ /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ HAL_Init(); 80009ea: f003 fb02 bl 8003ff2 /* USER CODE BEGIN Init */ pid_init(&motor_pid,kp,ki,kd,i_min,i_max,PWM_MAX,pid_max_step); 80009ee: 4bc8 ldr r3, [pc, #800] @ (8000d10 ) 80009f0: 681c ldr r4, [r3, #0] 80009f2: 4bc8 ldr r3, [pc, #800] @ (8000d14 ) 80009f4: 681d ldr r5, [r3, #0] 80009f6: 4bc8 ldr r3, [pc, #800] @ (8000d18 ) 80009f8: 681e ldr r6, [r3, #0] 80009fa: 4bc8 ldr r3, [pc, #800] @ (8000d1c ) 80009fc: 681a ldr r2, [r3, #0] 80009fe: 4bc8 ldr r3, [pc, #800] @ (8000d20 ) 8000a00: 6819 ldr r1, [r3, #0] 8000a02: 4bc8 ldr r3, [pc, #800] @ (8000d24 ) 8000a04: 681b ldr r3, [r3, #0] 8000a06: 48c8 ldr r0, [pc, #800] @ (8000d28 ) 8000a08: 9303 str r3, [sp, #12] 8000a0a: 2396 movs r3, #150 @ 0x96 8000a0c: 011b lsls r3, r3, #4 8000a0e: 9302 str r3, [sp, #8] 8000a10: 9101 str r1, [sp, #4] 8000a12: 9200 str r2, [sp, #0] 8000a14: 0033 movs r3, r6 8000a16: 002a movs r2, r5 8000a18: 0021 movs r1, r4 8000a1a: f7ff fed6 bl 80007ca /* USER CODE END Init */ /* Configure the system clock */ SystemClock_Config(); 8000a1e: f000 fb9d bl 800115c /* USER CODE BEGIN SysInit */ /* USER CODE END SysInit */ /* Initialize all configured peripherals */ MX_GPIO_Init(); 8000a22: f000 fe79 bl 8001718 MX_DMA_Init(); 8000a26: f000 fe51 bl 80016cc MX_TIM1_Init(); 8000a2a: f000 fbe5 bl 80011f8 MX_TIM3_Init(); 8000a2e: f000 fccf bl 80013d0 MX_USART1_UART_Init(); 8000a32: f000 fda9 bl 8001588 MX_USART2_UART_Init(); 8000a36: f000 fdf5 bl 8001624 MX_TIM16_Init(); 8000a3a: f000 fd51 bl 80014e0 MX_TIM17_Init(); 8000a3e: f000 fd79 bl 8001534 MX_TIM14_Init(); 8000a42: f000 fd29 bl 8001498 /* USER CODE BEGIN 2 */ uint32_t * puuid = (uint32_t *)UUID; 8000a46: 4bb9 ldr r3, [pc, #740] @ (8000d2c ) 8000a48: 613b str r3, [r7, #16] *puuid = HAL_GetUIDw0(); 8000a4a: f003 fb73 bl 8004134 8000a4e: 0002 movs r2, r0 8000a50: 693b ldr r3, [r7, #16] 8000a52: 601a str r2, [r3, #0] *(puuid+1) = HAL_GetUIDw1(); 8000a54: 693b ldr r3, [r7, #16] 8000a56: 1d1c adds r4, r3, #4 8000a58: f003 fb76 bl 8004148 8000a5c: 0003 movs r3, r0 8000a5e: 6023 str r3, [r4, #0] *(puuid+2) = HAL_GetUIDw2(); 8000a60: 693b ldr r3, [r7, #16] 8000a62: 3308 adds r3, #8 8000a64: 001c movs r4, r3 8000a66: f003 fb79 bl 800415c 8000a6a: 0003 movs r3, r0 8000a6c: 6023 str r3, [r4, #0] // Start encoder timer (TIM3) in encoder mode HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL); 8000a6e: 4bb0 ldr r3, [pc, #704] @ (8000d30 ) 8000a70: 213c movs r1, #60 @ 0x3c 8000a72: 0018 movs r0, r3 8000a74: f004 ffa6 bl 80059c4 // Start PWM timer (TIM1) for motor control HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1); // Feed motor 8000a78: 4bae ldr r3, [pc, #696] @ (8000d34 ) 8000a7a: 2100 movs r1, #0 8000a7c: 0018 movs r0, r3 8000a7e: f004 fe1b bl 80056b8 HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_2); // Feed motor 8000a82: 4bac ldr r3, [pc, #688] @ (8000d34 ) 8000a84: 2104 movs r1, #4 8000a86: 0018 movs r0, r3 8000a88: f004 fe16 bl 80056b8 HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_3); // Peel motor 8000a8c: 4ba9 ldr r3, [pc, #676] @ (8000d34 ) 8000a8e: 2108 movs r1, #8 8000a90: 0018 movs r0, r3 8000a92: f004 fe11 bl 80056b8 HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_4); // Peel motor 8000a96: 4ba7 ldr r3, [pc, #668] @ (8000d34 ) 8000a98: 210c movs r1, #12 8000a9a: 0018 movs r0, r3 8000a9c: f004 fe0c bl 80056b8 // Start PID control timer (TIM14) with interrupt HAL_TIM_Base_Start_IT(&htim14); 8000aa0: 4ba5 ldr r3, [pc, #660] @ (8000d38 ) 8000aa2: 0018 movs r0, r3 8000aa4: f004 fd54 bl 8005550 // Initialize stall detection stall_detection_init(); 8000aa8: f002 fab8 bl 800301c // Read floor address from EEPROM floor_address = read_floor_address(); 8000aac: f002 fc81 bl 80033b2 8000ab0: 0003 movs r3, r0 8000ab2: 001a movs r2, r3 8000ab4: 4ba1 ldr r3, [pc, #644] @ (8000d3c ) 8000ab6: 701a strb r2, [r3, #0] if (floor_address == FLOOR_ADDRESS_NOT_DETECTED) 8000ab8: 4ba0 ldr r3, [pc, #640] @ (8000d3c ) 8000aba: 781b ldrb r3, [r3, #0] 8000abc: 2bff cmp r3, #255 @ 0xff 8000abe: d108 bne.n 8000ad2 { floor_address_status = 0; 8000ac0: 4b9f ldr r3, [pc, #636] @ (8000d40 ) 8000ac2: 2200 movs r2, #0 8000ac4: 701a strb r2, [r3, #0] set_LED(1, 0, 0); // Red = EEPROM not detected 8000ac6: 2200 movs r2, #0 8000ac8: 2100 movs r1, #0 8000aca: 2001 movs r0, #1 8000acc: f001 f84e bl 8001b6c 8000ad0: e020 b.n 8000b14 } else if (floor_address == FLOOR_ADDRESS_NOT_PROGRAMMED) 8000ad2: 4b9a ldr r3, [pc, #616] @ (8000d3c ) 8000ad4: 781b ldrb r3, [r3, #0] 8000ad6: 2b00 cmp r3, #0 8000ad8: d108 bne.n 8000aec { floor_address_status = 1; 8000ada: 4b99 ldr r3, [pc, #612] @ (8000d40 ) 8000adc: 2201 movs r2, #1 8000ade: 701a strb r2, [r3, #0] set_LED(0, 0, 1); // Blue = not programmed 8000ae0: 2201 movs r2, #1 8000ae2: 2100 movs r1, #0 8000ae4: 2000 movs r0, #0 8000ae6: f001 f841 bl 8001b6c 8000aea: e013 b.n 8000b14 } else { floor_address_status = 2; 8000aec: 4b94 ldr r3, [pc, #592] @ (8000d40 ) 8000aee: 2202 movs r2, #2 8000af0: 701a strb r2, [r3, #0] my_address = floor_address; 8000af2: 4b92 ldr r3, [pc, #584] @ (8000d3c ) 8000af4: 781a ldrb r2, [r3, #0] 8000af6: 4b93 ldr r3, [pc, #588] @ (8000d44 ) 8000af8: 701a strb r2, [r3, #0] set_LED(0, 1, 0); // Green briefly = valid address 8000afa: 2200 movs r2, #0 8000afc: 2101 movs r1, #1 8000afe: 2000 movs r0, #0 8000b00: f001 f834 bl 8001b6c HAL_Delay(200); 8000b04: 20c8 movs r0, #200 @ 0xc8 8000b06: f003 faf1 bl 80040ec set_LED(0, 0, 0); 8000b0a: 2200 movs r2, #0 8000b0c: 2100 movs r1, #0 8000b0e: 2000 movs r0, #0 8000b10: f001 f82c bl 8001b6c } HAL_UARTEx_ReceiveToIdle_DMA (&huart2,DMA_buffer,64); 8000b14: 498c ldr r1, [pc, #560] @ (8000d48 ) 8000b16: 4b8d ldr r3, [pc, #564] @ (8000d4c ) 8000b18: 2240 movs r2, #64 @ 0x40 8000b1a: 0018 movs r0, r3 8000b1c: f006 fff6 bl 8007b0c /* Infinite loop */ /* USER CODE BEGIN WHILE */ while (1) { uint8_t sw1_state = HAL_GPIO_ReadPin(SW1_GPIO_Port, SW1_Pin); // 1 = released, 0 = pressed 8000b20: 230f movs r3, #15 8000b22: 18fc adds r4, r7, r3 8000b24: 2380 movs r3, #128 @ 0x80 8000b26: 009b lsls r3, r3, #2 8000b28: 4a89 ldr r2, [pc, #548] @ (8000d50 ) 8000b2a: 0019 movs r1, r3 8000b2c: 0010 movs r0, r2 8000b2e: f003 ffc3 bl 8004ab8 8000b32: 0003 movs r3, r0 8000b34: 7023 strb r3, [r4, #0] uint8_t sw2_state = HAL_GPIO_ReadPin(SW2_GPIO_Port, SW2_Pin); 8000b36: 250e movs r5, #14 8000b38: 197c adds r4, r7, r5 8000b3a: 2380 movs r3, #128 @ 0x80 8000b3c: 005b lsls r3, r3, #1 8000b3e: 4a84 ldr r2, [pc, #528] @ (8000d50 ) 8000b40: 0019 movs r1, r3 8000b42: 0010 movs r0, r2 8000b44: f003 ffb8 bl 8004ab8 8000b48: 0003 movs r3, r0 8000b4a: 7023 strb r3, [r4, #0] // Handle ongoing continuous drive - stop when button released if (driving) 8000b4c: 4b81 ldr r3, [pc, #516] @ (8000d54 ) 8000b4e: 781b ldrb r3, [r3, #0] 8000b50: 2b00 cmp r3, #0 8000b52: d046 beq.n 8000be2 { if ((driving_direction && sw2_state) || (!driving_direction && sw1_state)) 8000b54: 4b80 ldr r3, [pc, #512] @ (8000d58 ) 8000b56: 781b ldrb r3, [r3, #0] 8000b58: 2b00 cmp r3, #0 8000b5a: d003 beq.n 8000b64 8000b5c: 197b adds r3, r7, r5 8000b5e: 781b ldrb r3, [r3, #0] 8000b60: 2b00 cmp r3, #0 8000b62: d108 bne.n 8000b76 8000b64: 4b7c ldr r3, [pc, #496] @ (8000d58 ) 8000b66: 781b ldrb r3, [r3, #0] 8000b68: 2b00 cmp r3, #0 8000b6a: d123 bne.n 8000bb4 8000b6c: 230f movs r3, #15 8000b6e: 18fb adds r3, r7, r3 8000b70: 781b ldrb r3, [r3, #0] 8000b72: 2b00 cmp r3, #0 8000b74: d01e beq.n 8000bb4 { halt_all(); 8000b76: f001 fe3b bl 80027f0 driving = 0; 8000b7a: 4b76 ldr r3, [pc, #472] @ (8000d54 ) 8000b7c: 2200 movs r2, #0 8000b7e: 701a strb r2, [r3, #0] HAL_TIM_Base_Stop(&htim16); 8000b80: 4b76 ldr r3, [pc, #472] @ (8000d5c ) 8000b82: 0018 movs r0, r3 8000b84: f004 fcbe bl 8005504 HAL_TIM_Base_Stop(&htim17); 8000b88: 4b75 ldr r3, [pc, #468] @ (8000d60 ) 8000b8a: 0018 movs r0, r3 8000b8c: f004 fcba bl 8005504 sw1_pressed = 0; 8000b90: 4b74 ldr r3, [pc, #464] @ (8000d64 ) 8000b92: 2200 movs r2, #0 8000b94: 701a strb r2, [r3, #0] sw2_pressed = 0; 8000b96: 4b74 ldr r3, [pc, #464] @ (8000d68 ) 8000b98: 2200 movs r2, #0 8000b9a: 701a strb r2, [r3, #0] sw1_long_handled = 0; 8000b9c: 4b73 ldr r3, [pc, #460] @ (8000d6c ) 8000b9e: 2200 movs r2, #0 8000ba0: 701a strb r2, [r3, #0] sw2_long_handled = 0; 8000ba2: 4b73 ldr r3, [pc, #460] @ (8000d70 ) 8000ba4: 2200 movs r2, #0 8000ba6: 701a strb r2, [r3, #0] set_LED(0, 0, 0); 8000ba8: 2200 movs r2, #0 8000baa: 2100 movs r1, #0 8000bac: 2000 movs r0, #0 8000bae: f000 ffdd bl 8001b6c 8000bb2: e240 b.n 8001036 } else if (!drive_mode) 8000bb4: 4b6f ldr r3, [pc, #444] @ (8000d74 ) 8000bb6: 781b ldrb r3, [r3, #0] 8000bb8: 2b00 cmp r3, #0 8000bba: d000 beq.n 8000bbe 8000bbc: e23b b.n 8001036 { // Tape mode: keep target ahead of current position if (driving_direction) 8000bbe: 4b66 ldr r3, [pc, #408] @ (8000d58 ) 8000bc0: 781b ldrb r3, [r3, #0] 8000bc2: 2b00 cmp r3, #0 8000bc4: d006 beq.n 8000bd4 target_count = total_count + 10000; 8000bc6: 4b6c ldr r3, [pc, #432] @ (8000d78 ) 8000bc8: 681b ldr r3, [r3, #0] 8000bca: 4a6c ldr r2, [pc, #432] @ (8000d7c ) 8000bcc: 189a adds r2, r3, r2 8000bce: 4b6c ldr r3, [pc, #432] @ (8000d80 ) 8000bd0: 601a str r2, [r3, #0] 8000bd2: e230 b.n 8001036 else target_count = total_count - 10000; 8000bd4: 4b68 ldr r3, [pc, #416] @ (8000d78 ) 8000bd6: 681b ldr r3, [r3, #0] 8000bd8: 4a6a ldr r2, [pc, #424] @ (8000d84 ) 8000bda: 189a adds r2, r3, r2 8000bdc: 4b68 ldr r3, [pc, #416] @ (8000d80 ) 8000bde: 601a str r2, [r3, #0] 8000be0: e229 b.n 8001036 } } else if (both_pressed_handled) 8000be2: 4b69 ldr r3, [pc, #420] @ (8000d88 ) 8000be4: 781b ldrb r3, [r3, #0] 8000be6: 2b00 cmp r3, #0 8000be8: d100 bne.n 8000bec 8000bea: e072 b.n 8000cd2 { // Both-press mode: wait for release, handle long-hold actions if (sw1_state && sw2_state) 8000bec: 230f movs r3, #15 8000bee: 18fb adds r3, r7, r3 8000bf0: 781b ldrb r3, [r3, #0] 8000bf2: 2b00 cmp r3, #0 8000bf4: d026 beq.n 8000c44 8000bf6: 230e movs r3, #14 8000bf8: 18fb adds r3, r7, r3 8000bfa: 781b ldrb r3, [r3, #0] 8000bfc: 2b00 cmp r3, #0 8000bfe: d021 beq.n 8000c44 { // Both released - show mode color briefly then clear both_pressed_handled = 0; 8000c00: 4b61 ldr r3, [pc, #388] @ (8000d88 ) 8000c02: 2200 movs r2, #0 8000c04: 701a strb r2, [r3, #0] HAL_TIM_Base_Stop(&htim16); 8000c06: 4b55 ldr r3, [pc, #340] @ (8000d5c ) 8000c08: 0018 movs r0, r3 8000c0a: f004 fc7b bl 8005504 HAL_TIM_Base_Stop(&htim17); 8000c0e: 4b54 ldr r3, [pc, #336] @ (8000d60 ) 8000c10: 0018 movs r0, r3 8000c12: f004 fc77 bl 8005504 sw1_pressed = 0; 8000c16: 4b53 ldr r3, [pc, #332] @ (8000d64 ) 8000c18: 2200 movs r2, #0 8000c1a: 701a strb r2, [r3, #0] sw2_pressed = 0; 8000c1c: 4b52 ldr r3, [pc, #328] @ (8000d68 ) 8000c1e: 2200 movs r2, #0 8000c20: 701a strb r2, [r3, #0] sw1_long_handled = 0; 8000c22: 4b52 ldr r3, [pc, #328] @ (8000d6c ) 8000c24: 2200 movs r2, #0 8000c26: 701a strb r2, [r3, #0] sw2_long_handled = 0; 8000c28: 4b51 ldr r3, [pc, #324] @ (8000d70 ) 8000c2a: 2200 movs r2, #0 8000c2c: 701a strb r2, [r3, #0] HAL_Delay(400); 8000c2e: 23c8 movs r3, #200 @ 0xc8 8000c30: 005b lsls r3, r3, #1 8000c32: 0018 movs r0, r3 8000c34: f003 fa5a bl 80040ec set_LED(0, 0, 0); 8000c38: 2200 movs r2, #0 8000c3a: 2100 movs r1, #0 8000c3c: 2000 movs r0, #0 8000c3e: f000 ff95 bl 8001b6c 8000c42: e1f8 b.n 8001036 } else { // Still holding - check for long-hold actions uint32_t hold_time = HAL_GetTick() - both_pressed_start; 8000c44: f003 fa48 bl 80040d8 8000c48: 0002 movs r2, r0 8000c4a: 4b50 ldr r3, [pc, #320] @ (8000d8c ) 8000c4c: 681b ldr r3, [r3, #0] 8000c4e: 1ad3 subs r3, r2, r3 8000c50: 607b str r3, [r7, #4] if (hold_time > 2000 && hold_time < 2100) 8000c52: 687a ldr r2, [r7, #4] 8000c54: 23fa movs r3, #250 @ 0xfa 8000c56: 00db lsls r3, r3, #3 8000c58: 429a cmp r2, r3 8000c5a: d906 bls.n 8000c6a 8000c5c: 687b ldr r3, [r7, #4] 8000c5e: 4a4c ldr r2, [pc, #304] @ (8000d90 ) 8000c60: 4293 cmp r3, r2 8000c62: d802 bhi.n 8000c6a { show_version(); 8000c64: f001 fe1f bl 80028a6 8000c68: e1e5 b.n 8001036 } else if (hold_time > 4000 && hold_time < 6000) 8000c6a: 687a ldr r2, [r7, #4] 8000c6c: 23fa movs r3, #250 @ 0xfa 8000c6e: 011b lsls r3, r3, #4 8000c70: 429a cmp r2, r3 8000c72: d91f bls.n 8000cb4 8000c74: 687b ldr r3, [r7, #4] 8000c76: 4a47 ldr r2, [pc, #284] @ (8000d94 ) 8000c78: 4293 cmp r3, r2 8000c7a: d81b bhi.n 8000cb4 { set_LED((hold_time / 100) % 2, 0, !((hold_time / 100) % 2)); 8000c7c: 687b ldr r3, [r7, #4] 8000c7e: 2164 movs r1, #100 @ 0x64 8000c80: 0018 movs r0, r3 8000c82: f7ff fa41 bl 8000108 <__udivsi3> 8000c86: 0003 movs r3, r0 8000c88: b2db uxtb r3, r3 8000c8a: 2201 movs r2, #1 8000c8c: 4013 ands r3, r2 8000c8e: b2dc uxtb r4, r3 8000c90: 687b ldr r3, [r7, #4] 8000c92: 2164 movs r1, #100 @ 0x64 8000c94: 0018 movs r0, r3 8000c96: f7ff fa37 bl 8000108 <__udivsi3> 8000c9a: 0003 movs r3, r0 8000c9c: 001a movs r2, r3 8000c9e: 2301 movs r3, #1 8000ca0: 4013 ands r3, r2 8000ca2: 425a negs r2, r3 8000ca4: 4153 adcs r3, r2 8000ca6: b2db uxtb r3, r3 8000ca8: 001a movs r2, r3 8000caa: 2100 movs r1, #0 8000cac: 0020 movs r0, r4 8000cae: f000 ff5d bl 8001b6c 8000cb2: e1c0 b.n 8001036 } else if (hold_time >= 6000) 8000cb4: 687b ldr r3, [r7, #4] 8000cb6: 4a37 ldr r2, [pc, #220] @ (8000d94 ) 8000cb8: 4293 cmp r3, r2 8000cba: d800 bhi.n 8000cbe 8000cbc: e1bb b.n 8001036 { set_LED(1, 0, 1); 8000cbe: 2201 movs r2, #1 8000cc0: 2100 movs r1, #0 8000cc2: 2001 movs r0, #1 8000cc4: f000 ff52 bl 8001b6c HAL_Delay(100); 8000cc8: 2064 movs r0, #100 @ 0x64 8000cca: f003 fa0f bl 80040ec NVIC_SystemReset(); 8000cce: f7ff fd53 bl 8000778 <__NVIC_SystemReset> } } } else if (sw1_pressed || sw2_pressed) 8000cd2: 4b24 ldr r3, [pc, #144] @ (8000d64 ) 8000cd4: 781b ldrb r3, [r3, #0] 8000cd6: 2b00 cmp r3, #0 8000cd8: d104 bne.n 8000ce4 8000cda: 4b23 ldr r3, [pc, #140] @ (8000d68 ) 8000cdc: 781b ldrb r3, [r3, #0] 8000cde: 2b00 cmp r3, #0 8000ce0: d100 bne.n 8000ce4 8000ce2: e1a8 b.n 8001036 { // At least one button pressed - use decision window uint16_t time1 = sw1_pressed ? htim16.Instance->CNT : 0; 8000ce4: 4b1f ldr r3, [pc, #124] @ (8000d64 ) 8000ce6: 781b ldrb r3, [r3, #0] 8000ce8: 2b00 cmp r3, #0 8000cea: d004 beq.n 8000cf6 8000cec: 4b1b ldr r3, [pc, #108] @ (8000d5c ) 8000cee: 681b ldr r3, [r3, #0] 8000cf0: 6a5b ldr r3, [r3, #36] @ 0x24 8000cf2: b29a uxth r2, r3 8000cf4: e000 b.n 8000cf8 8000cf6: 2200 movs r2, #0 8000cf8: 230c movs r3, #12 8000cfa: 18fb adds r3, r7, r3 8000cfc: 801a strh r2, [r3, #0] uint16_t time2 = sw2_pressed ? htim17.Instance->CNT : 0; 8000cfe: 4b1a ldr r3, [pc, #104] @ (8000d68 ) 8000d00: 781b ldrb r3, [r3, #0] 8000d02: 2b00 cmp r3, #0 8000d04: d048 beq.n 8000d98 8000d06: 4b16 ldr r3, [pc, #88] @ (8000d60 ) 8000d08: 681b ldr r3, [r3, #0] 8000d0a: 6a5b ldr r3, [r3, #36] @ 0x24 8000d0c: b29a uxth r2, r3 8000d0e: e044 b.n 8000d9a 8000d10: 20000004 .word 0x20000004 8000d14: 20000008 .word 0x20000008 8000d18: 2000000c .word 0x2000000c 8000d1c: 20000010 .word 0x20000010 8000d20: 20000014 .word 0x20000014 8000d24: 20000018 .word 0x20000018 8000d28: 2000048c .word 0x2000048c 8000d2c: 200003b4 .word 0x200003b4 8000d30: 20000098 .word 0x20000098 8000d34: 2000004c .word 0x2000004c 8000d38: 200000e4 .word 0x200000e4 8000d3c: 2000001f .word 0x2000001f 8000d40: 2000054c .word 0x2000054c 8000d44: 20000002 .word 0x20000002 8000d48: 20000444 .word 0x20000444 8000d4c: 2000025c .word 0x2000025c 8000d50: 50000400 .word 0x50000400 8000d54: 200004e1 .word 0x200004e1 8000d58: 200004e2 .word 0x200004e2 8000d5c: 20000130 .word 0x20000130 8000d60: 2000017c .word 0x2000017c 8000d64: 200003a8 .word 0x200003a8 8000d68: 200003a9 .word 0x200003a9 8000d6c: 200004e3 .word 0x200004e3 8000d70: 200004e4 .word 0x200004e4 8000d74: 200004e0 .word 0x200004e0 8000d78: 20000484 .word 0x20000484 8000d7c: 00002710 .word 0x00002710 8000d80: 20000488 .word 0x20000488 8000d84: ffffd8f0 .word 0xffffd8f0 8000d88: 200004e5 .word 0x200004e5 8000d8c: 200004e8 .word 0x200004e8 8000d90: 00000833 .word 0x00000833 8000d94: 0000176f .word 0x0000176f 8000d98: 2200 movs r2, #0 8000d9a: 210a movs r1, #10 8000d9c: 187b adds r3, r7, r1 8000d9e: 801a strh r2, [r3, #0] uint16_t max_time = (time1 > time2) ? time1 : time2; 8000da0: 2308 movs r3, #8 8000da2: 18fa adds r2, r7, r3 8000da4: 187b adds r3, r7, r1 8000da6: 210c movs r1, #12 8000da8: 1879 adds r1, r7, r1 8000daa: 880c ldrh r4, [r1, #0] 8000dac: 881b ldrh r3, [r3, #0] 8000dae: b298 uxth r0, r3 8000db0: b2a1 uxth r1, r4 8000db2: 4288 cmp r0, r1 8000db4: d200 bcs.n 8000db8 8000db6: 1c23 adds r3, r4, #0 8000db8: 8013 strh r3, [r2, #0] // Wait 100ms decision window before acting (unless already past it) if (max_time < 100) 8000dba: 2308 movs r3, #8 8000dbc: 18fb adds r3, r7, r3 8000dbe: 881b ldrh r3, [r3, #0] 8000dc0: 2b63 cmp r3, #99 @ 0x63 8000dc2: d800 bhi.n 8000dc6 8000dc4: e137 b.n 8001036 { // Still in decision window - do nothing yet } else if (sw1_pressed && sw2_pressed && !sw1_state && !sw2_state) 8000dc6: 4bd2 ldr r3, [pc, #840] @ (8001110 ) 8000dc8: 781b ldrb r3, [r3, #0] 8000dca: 2b00 cmp r3, #0 8000dcc: d02b beq.n 8000e26 8000dce: 4bd1 ldr r3, [pc, #836] @ (8001114 ) 8000dd0: 781b ldrb r3, [r3, #0] 8000dd2: 2b00 cmp r3, #0 8000dd4: d027 beq.n 8000e26 8000dd6: 230f movs r3, #15 8000dd8: 18fb adds r3, r7, r3 8000dda: 781b ldrb r3, [r3, #0] 8000ddc: 2b00 cmp r3, #0 8000dde: d122 bne.n 8000e26 8000de0: 230e movs r3, #14 8000de2: 18fb adds r3, r7, r3 8000de4: 781b ldrb r3, [r3, #0] 8000de6: 2b00 cmp r3, #0 8000de8: d11d bne.n 8000e26 { // Both pressed - toggle mode both_pressed_handled = 1; 8000dea: 4bcb ldr r3, [pc, #812] @ (8001118 ) 8000dec: 2201 movs r2, #1 8000dee: 701a strb r2, [r3, #0] both_pressed_start = HAL_GetTick(); 8000df0: f003 f972 bl 80040d8 8000df4: 0002 movs r2, r0 8000df6: 4bc9 ldr r3, [pc, #804] @ (800111c ) 8000df8: 601a str r2, [r3, #0] if (drive_mode) 8000dfa: 4bc9 ldr r3, [pc, #804] @ (8001120 ) 8000dfc: 781b ldrb r3, [r3, #0] 8000dfe: 2b00 cmp r3, #0 8000e00: d008 beq.n 8000e14 { drive_mode = 0; 8000e02: 4bc7 ldr r3, [pc, #796] @ (8001120 ) 8000e04: 2200 movs r2, #0 8000e06: 701a strb r2, [r3, #0] set_LED(0, 0, 1); // Blue = tape mode 8000e08: 2201 movs r2, #1 8000e0a: 2100 movs r1, #0 8000e0c: 2000 movs r0, #0 8000e0e: f000 fead bl 8001b6c if (drive_mode) 8000e12: e110 b.n 8001036 } else { drive_mode = 1; 8000e14: 4bc2 ldr r3, [pc, #776] @ (8001120 ) 8000e16: 2201 movs r2, #1 8000e18: 701a strb r2, [r3, #0] set_LED(1, 1, 0); // Yellow = peel mode 8000e1a: 2200 movs r2, #0 8000e1c: 2101 movs r1, #1 8000e1e: 2001 movs r0, #1 8000e20: f000 fea4 bl 8001b6c if (drive_mode) 8000e24: e107 b.n 8001036 } } else if (sw1_pressed && !sw2_pressed) 8000e26: 4bba ldr r3, [pc, #744] @ (8001110 ) 8000e28: 781b ldrb r3, [r3, #0] 8000e2a: 2b00 cmp r3, #0 8000e2c: d100 bne.n 8000e30 8000e2e: e06e b.n 8000f0e 8000e30: 4bb8 ldr r3, [pc, #736] @ (8001114 ) 8000e32: 781b ldrb r3, [r3, #0] 8000e34: 2b00 cmp r3, #0 8000e36: d000 beq.n 8000e3a 8000e38: e069 b.n 8000f0e { // Single SW1 handling if (!sw1_state && time1 > 2000 && !sw1_long_handled) 8000e3a: 230f movs r3, #15 8000e3c: 18fb adds r3, r7, r3 8000e3e: 781b ldrb r3, [r3, #0] 8000e40: 2b00 cmp r3, #0 8000e42: d124 bne.n 8000e8e 8000e44: 230c movs r3, #12 8000e46: 18fb adds r3, r7, r3 8000e48: 881a ldrh r2, [r3, #0] 8000e4a: 23fa movs r3, #250 @ 0xfa 8000e4c: 00db lsls r3, r3, #3 8000e4e: 429a cmp r2, r3 8000e50: d91d bls.n 8000e8e 8000e52: 4bb4 ldr r3, [pc, #720] @ (8001124 ) 8000e54: 781b ldrb r3, [r3, #0] 8000e56: 2b00 cmp r3, #0 8000e58: d119 bne.n 8000e8e { sw1_long_handled = 1; 8000e5a: 4bb2 ldr r3, [pc, #712] @ (8001124 ) 8000e5c: 2201 movs r2, #1 8000e5e: 701a strb r2, [r3, #0] set_LED(1, 1, 1); 8000e60: 2201 movs r2, #1 8000e62: 2101 movs r1, #1 8000e64: 2001 movs r0, #1 8000e66: f000 fe81 bl 8001b6c if (drive_mode) 8000e6a: 4bad ldr r3, [pc, #692] @ (8001120 ) 8000e6c: 781b ldrb r3, [r3, #0] 8000e6e: 2b00 cmp r3, #0 8000e70: d003 beq.n 8000e7a peel_motor(0); 8000e72: 2000 movs r0, #0 8000e74: f001 fbc6 bl 8002604 8000e78: e002 b.n 8000e80 else drive_continuous(0); 8000e7a: 2000 movs r0, #0 8000e7c: f001 fc8e bl 800279c driving = 1; 8000e80: 4ba9 ldr r3, [pc, #676] @ (8001128 ) 8000e82: 2201 movs r2, #1 8000e84: 701a strb r2, [r3, #0] driving_direction = 0; 8000e86: 4ba9 ldr r3, [pc, #676] @ (800112c ) 8000e88: 2200 movs r2, #0 8000e8a: 701a strb r2, [r3, #0] 8000e8c: e03e b.n 8000f0c } else if (sw1_state && time1 <= 2000 && time1 > 100) 8000e8e: 230f movs r3, #15 8000e90: 18fb adds r3, r7, r3 8000e92: 781b ldrb r3, [r3, #0] 8000e94: 2b00 cmp r3, #0 8000e96: d01e beq.n 8000ed6 8000e98: 210c movs r1, #12 8000e9a: 187b adds r3, r7, r1 8000e9c: 881a ldrh r2, [r3, #0] 8000e9e: 23fa movs r3, #250 @ 0xfa 8000ea0: 00db lsls r3, r3, #3 8000ea2: 429a cmp r2, r3 8000ea4: d817 bhi.n 8000ed6 8000ea6: 187b adds r3, r7, r1 8000ea8: 881b ldrh r3, [r3, #0] 8000eaa: 2b64 cmp r3, #100 @ 0x64 8000eac: d913 bls.n 8000ed6 { set_LED(1, 1, 1); 8000eae: 2201 movs r2, #1 8000eb0: 2101 movs r1, #1 8000eb2: 2001 movs r0, #1 8000eb4: f000 fe5a bl 8001b6c start_feed(20, 0); 8000eb8: 2100 movs r1, #0 8000eba: 2014 movs r0, #20 8000ebc: f001 fd78 bl 80029b0 HAL_TIM_Base_Stop(&htim16); 8000ec0: 4b9b ldr r3, [pc, #620] @ (8001130 ) 8000ec2: 0018 movs r0, r3 8000ec4: f004 fb1e bl 8005504 sw1_pressed = 0; 8000ec8: 4b91 ldr r3, [pc, #580] @ (8001110 ) 8000eca: 2200 movs r2, #0 8000ecc: 701a strb r2, [r3, #0] sw1_long_handled = 0; 8000ece: 4b95 ldr r3, [pc, #596] @ (8001124 ) 8000ed0: 2200 movs r2, #0 8000ed2: 701a strb r2, [r3, #0] 8000ed4: e01a b.n 8000f0c } else if (sw1_state) 8000ed6: 230f movs r3, #15 8000ed8: 18fb adds r3, r7, r3 8000eda: 781b ldrb r3, [r3, #0] 8000edc: 2b00 cmp r3, #0 8000ede: d100 bne.n 8000ee2 8000ee0: e0a6 b.n 8001030 { HAL_TIM_Base_Stop(&htim16); 8000ee2: 4b93 ldr r3, [pc, #588] @ (8001130 ) 8000ee4: 0018 movs r0, r3 8000ee6: f004 fb0d bl 8005504 sw1_pressed = 0; 8000eea: 4b89 ldr r3, [pc, #548] @ (8001110 ) 8000eec: 2200 movs r2, #0 8000eee: 701a strb r2, [r3, #0] sw1_long_handled = 0; 8000ef0: 4b8c ldr r3, [pc, #560] @ (8001124 ) 8000ef2: 2200 movs r2, #0 8000ef4: 701a strb r2, [r3, #0] if (!driving) set_LED(0, 0, 0); 8000ef6: 4b8c ldr r3, [pc, #560] @ (8001128 ) 8000ef8: 781b ldrb r3, [r3, #0] 8000efa: 2b00 cmp r3, #0 8000efc: d000 beq.n 8000f00 8000efe: e097 b.n 8001030 8000f00: 2200 movs r2, #0 8000f02: 2100 movs r1, #0 8000f04: 2000 movs r0, #0 8000f06: f000 fe31 bl 8001b6c if (!sw1_state && time1 > 2000 && !sw1_long_handled) 8000f0a: e091 b.n 8001030 8000f0c: e090 b.n 8001030 } } else if (sw2_pressed && !sw1_pressed) 8000f0e: 4b81 ldr r3, [pc, #516] @ (8001114 ) 8000f10: 781b ldrb r3, [r3, #0] 8000f12: 2b00 cmp r3, #0 8000f14: d100 bne.n 8000f18 8000f16: e06c b.n 8000ff2 8000f18: 4b7d ldr r3, [pc, #500] @ (8001110 ) 8000f1a: 781b ldrb r3, [r3, #0] 8000f1c: 2b00 cmp r3, #0 8000f1e: d000 beq.n 8000f22 8000f20: e067 b.n 8000ff2 { // Single SW2 handling if (!sw2_state && time2 > 2000 && !sw2_long_handled) 8000f22: 230e movs r3, #14 8000f24: 18fb adds r3, r7, r3 8000f26: 781b ldrb r3, [r3, #0] 8000f28: 2b00 cmp r3, #0 8000f2a: d124 bne.n 8000f76 8000f2c: 230a movs r3, #10 8000f2e: 18fb adds r3, r7, r3 8000f30: 881a ldrh r2, [r3, #0] 8000f32: 23fa movs r3, #250 @ 0xfa 8000f34: 00db lsls r3, r3, #3 8000f36: 429a cmp r2, r3 8000f38: d91d bls.n 8000f76 8000f3a: 4b7e ldr r3, [pc, #504] @ (8001134 ) 8000f3c: 781b ldrb r3, [r3, #0] 8000f3e: 2b00 cmp r3, #0 8000f40: d119 bne.n 8000f76 { sw2_long_handled = 1; 8000f42: 4b7c ldr r3, [pc, #496] @ (8001134 ) 8000f44: 2201 movs r2, #1 8000f46: 701a strb r2, [r3, #0] set_LED(1, 1, 1); 8000f48: 2201 movs r2, #1 8000f4a: 2101 movs r1, #1 8000f4c: 2001 movs r0, #1 8000f4e: f000 fe0d bl 8001b6c if (drive_mode) 8000f52: 4b73 ldr r3, [pc, #460] @ (8001120 ) 8000f54: 781b ldrb r3, [r3, #0] 8000f56: 2b00 cmp r3, #0 8000f58: d003 beq.n 8000f62 peel_motor(1); 8000f5a: 2001 movs r0, #1 8000f5c: f001 fb52 bl 8002604 8000f60: e002 b.n 8000f68 else drive_continuous(1); 8000f62: 2001 movs r0, #1 8000f64: f001 fc1a bl 800279c driving = 1; 8000f68: 4b6f ldr r3, [pc, #444] @ (8001128 ) 8000f6a: 2201 movs r2, #1 8000f6c: 701a strb r2, [r3, #0] driving_direction = 1; 8000f6e: 4b6f ldr r3, [pc, #444] @ (800112c ) 8000f70: 2201 movs r2, #1 8000f72: 701a strb r2, [r3, #0] 8000f74: e03c b.n 8000ff0 } else if (sw2_state && time2 <= 2000 && time2 > 100) 8000f76: 230e movs r3, #14 8000f78: 18fb adds r3, r7, r3 8000f7a: 781b ldrb r3, [r3, #0] 8000f7c: 2b00 cmp r3, #0 8000f7e: d01e beq.n 8000fbe 8000f80: 210a movs r1, #10 8000f82: 187b adds r3, r7, r1 8000f84: 881a ldrh r2, [r3, #0] 8000f86: 23fa movs r3, #250 @ 0xfa 8000f88: 00db lsls r3, r3, #3 8000f8a: 429a cmp r2, r3 8000f8c: d817 bhi.n 8000fbe 8000f8e: 187b adds r3, r7, r1 8000f90: 881b ldrh r3, [r3, #0] 8000f92: 2b64 cmp r3, #100 @ 0x64 8000f94: d913 bls.n 8000fbe { set_LED(1, 1, 1); 8000f96: 2201 movs r2, #1 8000f98: 2101 movs r1, #1 8000f9a: 2001 movs r0, #1 8000f9c: f000 fde6 bl 8001b6c start_feed(20, 1); 8000fa0: 2101 movs r1, #1 8000fa2: 2014 movs r0, #20 8000fa4: f001 fd04 bl 80029b0 HAL_TIM_Base_Stop(&htim17); 8000fa8: 4b63 ldr r3, [pc, #396] @ (8001138 ) 8000faa: 0018 movs r0, r3 8000fac: f004 faaa bl 8005504 sw2_pressed = 0; 8000fb0: 4b58 ldr r3, [pc, #352] @ (8001114 ) 8000fb2: 2200 movs r2, #0 8000fb4: 701a strb r2, [r3, #0] sw2_long_handled = 0; 8000fb6: 4b5f ldr r3, [pc, #380] @ (8001134 ) 8000fb8: 2200 movs r2, #0 8000fba: 701a strb r2, [r3, #0] 8000fbc: e018 b.n 8000ff0 } else if (sw2_state) 8000fbe: 230e movs r3, #14 8000fc0: 18fb adds r3, r7, r3 8000fc2: 781b ldrb r3, [r3, #0] 8000fc4: 2b00 cmp r3, #0 8000fc6: d035 beq.n 8001034 { HAL_TIM_Base_Stop(&htim17); 8000fc8: 4b5b ldr r3, [pc, #364] @ (8001138 ) 8000fca: 0018 movs r0, r3 8000fcc: f004 fa9a bl 8005504 sw2_pressed = 0; 8000fd0: 4b50 ldr r3, [pc, #320] @ (8001114 ) 8000fd2: 2200 movs r2, #0 8000fd4: 701a strb r2, [r3, #0] sw2_long_handled = 0; 8000fd6: 4b57 ldr r3, [pc, #348] @ (8001134 ) 8000fd8: 2200 movs r2, #0 8000fda: 701a strb r2, [r3, #0] if (!driving) set_LED(0, 0, 0); 8000fdc: 4b52 ldr r3, [pc, #328] @ (8001128 ) 8000fde: 781b ldrb r3, [r3, #0] 8000fe0: 2b00 cmp r3, #0 8000fe2: d127 bne.n 8001034 8000fe4: 2200 movs r2, #0 8000fe6: 2100 movs r1, #0 8000fe8: 2000 movs r0, #0 8000fea: f000 fdbf bl 8001b6c if (!sw2_state && time2 > 2000 && !sw2_long_handled) 8000fee: e021 b.n 8001034 8000ff0: e020 b.n 8001034 } } else if (sw1_state && sw2_state) 8000ff2: 230f movs r3, #15 8000ff4: 18fb adds r3, r7, r3 8000ff6: 781b ldrb r3, [r3, #0] 8000ff8: 2b00 cmp r3, #0 8000ffa: d01c beq.n 8001036 8000ffc: 230e movs r3, #14 8000ffe: 18fb adds r3, r7, r3 8001000: 781b ldrb r3, [r3, #0] 8001002: 2b00 cmp r3, #0 8001004: d017 beq.n 8001036 { // Both released without triggering both-press (one was released too fast) HAL_TIM_Base_Stop(&htim16); 8001006: 4b4a ldr r3, [pc, #296] @ (8001130 ) 8001008: 0018 movs r0, r3 800100a: f004 fa7b bl 8005504 HAL_TIM_Base_Stop(&htim17); 800100e: 4b4a ldr r3, [pc, #296] @ (8001138 ) 8001010: 0018 movs r0, r3 8001012: f004 fa77 bl 8005504 sw1_pressed = 0; 8001016: 4b3e ldr r3, [pc, #248] @ (8001110 ) 8001018: 2200 movs r2, #0 800101a: 701a strb r2, [r3, #0] sw2_pressed = 0; 800101c: 4b3d ldr r3, [pc, #244] @ (8001114 ) 800101e: 2200 movs r2, #0 8001020: 701a strb r2, [r3, #0] sw1_long_handled = 0; 8001022: 4b40 ldr r3, [pc, #256] @ (8001124 ) 8001024: 2200 movs r2, #0 8001026: 701a strb r2, [r3, #0] sw2_long_handled = 0; 8001028: 4b42 ldr r3, [pc, #264] @ (8001134 ) 800102a: 2200 movs r2, #0 800102c: 701a strb r2, [r3, #0] 800102e: e002 b.n 8001036 if (!sw1_state && time1 > 2000 && !sw1_long_handled) 8001030: 46c0 nop @ (mov r8, r8) 8001032: e000 b.n 8001036 if (!sw2_state && time2 > 2000 && !sw2_long_handled) 8001034: 46c0 nop @ (mov r8, r8) } } // Update feed state machine feed_state_machine_update(); 8001036: f001 fd57 bl 8002ae8 // Ramp peel motor PWM peel_ramp_update(); 800103a: f001 fb05 bl 8002648 // Debug output via USART1 debug_output(); 800103e: f002 fb25 bl 800368c // Turn off LED when feed completes if (feed_just_completed) 8001042: 4b3e ldr r3, [pc, #248] @ (800113c ) 8001044: 781b ldrb r3, [r3, #0] 8001046: b2db uxtb r3, r3 8001048: 2b00 cmp r3, #0 800104a: d013 beq.n 8001074 { feed_just_completed = 0; 800104c: 4b3b ldr r3, [pc, #236] @ (800113c ) 800104e: 2200 movs r2, #0 8001050: 701a strb r2, [r3, #0] if (last_feed_status == STATUS_OK) 8001052: 4b3b ldr r3, [pc, #236] @ (8001140 ) 8001054: 781b ldrb r3, [r3, #0] 8001056: 2b00 cmp r3, #0 8001058: d107 bne.n 800106a { set_LED(0, 0, 0); // Success - LED off 800105a: 2200 movs r2, #0 800105c: 2100 movs r1, #0 800105e: 2000 movs r0, #0 8001060: f000 fd84 bl 8001b6c // Reset position tracking to prevent overflow reset_position_if_needed(); 8001064: f002 fca4 bl 80039b0 8001068: e004 b.n 8001074 } else { set_LED(1, 0, 0); // Error - LED red 800106a: 2200 movs r2, #0 800106c: 2100 movs r1, #0 800106e: 2001 movs r0, #1 8001070: f000 fd7c bl 8001b6c } } if (!msg_buffer1_empty) // msg 1 buffer has a message 8001074: 4b33 ldr r3, [pc, #204] @ (8001144 ) 8001076: 781b ldrb r3, [r3, #0] 8001078: 2b00 cmp r3, #0 800107a: d121 bne.n 80010c0 { handleRS485Message(msg_buffer1, msg_buffer1_size); 800107c: 4b32 ldr r3, [pc, #200] @ (8001148 ) 800107e: 781a ldrb r2, [r3, #0] 8001080: 4b32 ldr r3, [pc, #200] @ (800114c ) 8001082: 0011 movs r1, r2 8001084: 0018 movs r0, r3 8001086: f000 fdd7 bl 8001c38 for (uint8_t i = 0; i<64 ; i++) 800108a: 2317 movs r3, #23 800108c: 18fb adds r3, r7, r3 800108e: 2200 movs r2, #0 8001090: 701a strb r2, [r3, #0] 8001092: e00a b.n 80010aa { msg_buffer1[i]=0; 8001094: 2017 movs r0, #23 8001096: 183b adds r3, r7, r0 8001098: 781b ldrb r3, [r3, #0] 800109a: 4a2c ldr r2, [pc, #176] @ (800114c ) 800109c: 2100 movs r1, #0 800109e: 54d1 strb r1, [r2, r3] for (uint8_t i = 0; i<64 ; i++) 80010a0: 183b adds r3, r7, r0 80010a2: 781a ldrb r2, [r3, #0] 80010a4: 183b adds r3, r7, r0 80010a6: 3201 adds r2, #1 80010a8: 701a strb r2, [r3, #0] 80010aa: 2317 movs r3, #23 80010ac: 18fb adds r3, r7, r3 80010ae: 781b ldrb r3, [r3, #0] 80010b0: 2b3f cmp r3, #63 @ 0x3f 80010b2: d9ef bls.n 8001094 } msg_buffer1_size = 0; 80010b4: 4b24 ldr r3, [pc, #144] @ (8001148 ) 80010b6: 2200 movs r2, #0 80010b8: 701a strb r2, [r3, #0] msg_buffer1_empty = 1; 80010ba: 4b22 ldr r3, [pc, #136] @ (8001144 ) 80010bc: 2201 movs r2, #1 80010be: 701a strb r2, [r3, #0] } if (!msg_buffer2_empty) // msg 2 buffer has a message 80010c0: 4b23 ldr r3, [pc, #140] @ (8001150 ) 80010c2: 781b ldrb r3, [r3, #0] 80010c4: 2b00 cmp r3, #0 80010c6: d000 beq.n 80010ca 80010c8: e52a b.n 8000b20 { handleRS485Message(msg_buffer2, msg_buffer2_size); 80010ca: 4b22 ldr r3, [pc, #136] @ (8001154 ) 80010cc: 781a ldrb r2, [r3, #0] 80010ce: 4b22 ldr r3, [pc, #136] @ (8001158 ) 80010d0: 0011 movs r1, r2 80010d2: 0018 movs r0, r3 80010d4: f000 fdb0 bl 8001c38 for (uint8_t i = 0; i<64 ; i++) 80010d8: 2316 movs r3, #22 80010da: 18fb adds r3, r7, r3 80010dc: 2200 movs r2, #0 80010de: 701a strb r2, [r3, #0] 80010e0: e00a b.n 80010f8 { msg_buffer2[i]=0; 80010e2: 2016 movs r0, #22 80010e4: 183b adds r3, r7, r0 80010e6: 781b ldrb r3, [r3, #0] 80010e8: 4a1b ldr r2, [pc, #108] @ (8001158 ) 80010ea: 2100 movs r1, #0 80010ec: 54d1 strb r1, [r2, r3] for (uint8_t i = 0; i<64 ; i++) 80010ee: 183b adds r3, r7, r0 80010f0: 781a ldrb r2, [r3, #0] 80010f2: 183b adds r3, r7, r0 80010f4: 3201 adds r2, #1 80010f6: 701a strb r2, [r3, #0] 80010f8: 2316 movs r3, #22 80010fa: 18fb adds r3, r7, r3 80010fc: 781b ldrb r3, [r3, #0] 80010fe: 2b3f cmp r3, #63 @ 0x3f 8001100: d9ef bls.n 80010e2 } msg_buffer2_size = 0; 8001102: 4b14 ldr r3, [pc, #80] @ (8001154 ) 8001104: 2200 movs r2, #0 8001106: 701a strb r2, [r3, #0] msg_buffer2_empty = 1; 8001108: 4b11 ldr r3, [pc, #68] @ (8001150 ) 800110a: 2201 movs r2, #1 800110c: 701a strb r2, [r3, #0] { 800110e: e507 b.n 8000b20 8001110: 200003a8 .word 0x200003a8 8001114: 200003a9 .word 0x200003a9 8001118: 200004e5 .word 0x200004e5 800111c: 200004e8 .word 0x200004e8 8001120: 200004e0 .word 0x200004e0 8001124: 200004e3 .word 0x200004e3 8001128: 200004e1 .word 0x200004e1 800112c: 200004e2 .word 0x200004e2 8001130: 20000130 .word 0x20000130 8001134: 200004e4 .word 0x200004e4 8001138: 2000017c .word 0x2000017c 800113c: 200004be .word 0x200004be 8001140: 200004bc .word 0x200004bc 8001144: 20000000 .word 0x20000000 8001148: 200003c1 .word 0x200003c1 800114c: 200003c4 .word 0x200003c4 8001150: 20000001 .word 0x20000001 8001154: 200003c2 .word 0x200003c2 8001158: 20000404 .word 0x20000404 0800115c : /** * @brief System Clock Configuration * @retval None */ void SystemClock_Config(void) { 800115c: b590 push {r4, r7, lr} 800115e: b08d sub sp, #52 @ 0x34 8001160: af00 add r7, sp, #0 RCC_OscInitTypeDef RCC_OscInitStruct = {0}; 8001162: 2414 movs r4, #20 8001164: 193b adds r3, r7, r4 8001166: 0018 movs r0, r3 8001168: 231c movs r3, #28 800116a: 001a movs r2, r3 800116c: 2100 movs r1, #0 800116e: f006 fda1 bl 8007cb4 RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; 8001172: 003b movs r3, r7 8001174: 0018 movs r0, r3 8001176: 2314 movs r3, #20 8001178: 001a movs r2, r3 800117a: 2100 movs r1, #0 800117c: f006 fd9a bl 8007cb4 __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1); 8001180: 4b1c ldr r3, [pc, #112] @ (80011f4 ) 8001182: 681b ldr r3, [r3, #0] 8001184: 2207 movs r2, #7 8001186: 4393 bics r3, r2 8001188: 001a movs r2, r3 800118a: 4b1a ldr r3, [pc, #104] @ (80011f4 ) 800118c: 2101 movs r1, #1 800118e: 430a orrs r2, r1 8001190: 601a str r2, [r3, #0] /** Initializes the RCC Oscillators according to the specified parameters * in the RCC_OscInitTypeDef structure. */ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI; 8001192: 193b adds r3, r7, r4 8001194: 2202 movs r2, #2 8001196: 601a str r2, [r3, #0] RCC_OscInitStruct.HSIState = RCC_HSI_ON; 8001198: 193b adds r3, r7, r4 800119a: 2280 movs r2, #128 @ 0x80 800119c: 0052 lsls r2, r2, #1 800119e: 60da str r2, [r3, #12] RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; 80011a0: 193b adds r3, r7, r4 80011a2: 2200 movs r2, #0 80011a4: 611a str r2, [r3, #16] RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; 80011a6: 193b adds r3, r7, r4 80011a8: 2240 movs r2, #64 @ 0x40 80011aa: 615a str r2, [r3, #20] if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) 80011ac: 193b adds r3, r7, r4 80011ae: 0018 movs r0, r3 80011b0: f003 fcf0 bl 8004b94 80011b4: 1e03 subs r3, r0, #0 80011b6: d001 beq.n 80011bc { Error_Handler(); 80011b8: f002 fc48 bl 8003a4c } /** Initializes the CPU, AHB and APB buses clocks */ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK 80011bc: 003b movs r3, r7 80011be: 2207 movs r2, #7 80011c0: 601a str r2, [r3, #0] |RCC_CLOCKTYPE_PCLK1; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI; 80011c2: 003b movs r3, r7 80011c4: 2200 movs r2, #0 80011c6: 605a str r2, [r3, #4] RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; 80011c8: 003b movs r3, r7 80011ca: 2200 movs r2, #0 80011cc: 609a str r2, [r3, #8] RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1; 80011ce: 003b movs r3, r7 80011d0: 2200 movs r2, #0 80011d2: 60da str r2, [r3, #12] RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1; 80011d4: 003b movs r3, r7 80011d6: 2200 movs r2, #0 80011d8: 611a str r2, [r3, #16] if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) 80011da: 003b movs r3, r7 80011dc: 2101 movs r1, #1 80011de: 0018 movs r0, r3 80011e0: f003 febc bl 8004f5c 80011e4: 1e03 subs r3, r0, #0 80011e6: d001 beq.n 80011ec { Error_Handler(); 80011e8: f002 fc30 bl 8003a4c } } 80011ec: 46c0 nop @ (mov r8, r8) 80011ee: 46bd mov sp, r7 80011f0: b00d add sp, #52 @ 0x34 80011f2: bd90 pop {r4, r7, pc} 80011f4: 40022000 .word 0x40022000 080011f8 : * @brief TIM1 Initialization Function * @param None * @retval None */ static void MX_TIM1_Init(void) { 80011f8: b580 push {r7, lr} 80011fa: b09c sub sp, #112 @ 0x70 80011fc: af00 add r7, sp, #0 /* USER CODE BEGIN TIM1_Init 0 */ /* USER CODE END TIM1_Init 0 */ TIM_ClockConfigTypeDef sClockSourceConfig = {0}; 80011fe: 2360 movs r3, #96 @ 0x60 8001200: 18fb adds r3, r7, r3 8001202: 0018 movs r0, r3 8001204: 2310 movs r3, #16 8001206: 001a movs r2, r3 8001208: 2100 movs r1, #0 800120a: f006 fd53 bl 8007cb4 TIM_MasterConfigTypeDef sMasterConfig = {0}; 800120e: 2354 movs r3, #84 @ 0x54 8001210: 18fb adds r3, r7, r3 8001212: 0018 movs r0, r3 8001214: 230c movs r3, #12 8001216: 001a movs r2, r3 8001218: 2100 movs r1, #0 800121a: f006 fd4b bl 8007cb4 TIM_OC_InitTypeDef sConfigOC = {0}; 800121e: 2338 movs r3, #56 @ 0x38 8001220: 18fb adds r3, r7, r3 8001222: 0018 movs r0, r3 8001224: 231c movs r3, #28 8001226: 001a movs r2, r3 8001228: 2100 movs r1, #0 800122a: f006 fd43 bl 8007cb4 TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0}; 800122e: 1d3b adds r3, r7, #4 8001230: 0018 movs r0, r3 8001232: 2334 movs r3, #52 @ 0x34 8001234: 001a movs r2, r3 8001236: 2100 movs r1, #0 8001238: f006 fd3c bl 8007cb4 /* USER CODE BEGIN TIM1_Init 1 */ /* USER CODE END TIM1_Init 1 */ htim1.Instance = TIM1; 800123c: 4b62 ldr r3, [pc, #392] @ (80013c8 ) 800123e: 4a63 ldr r2, [pc, #396] @ (80013cc ) 8001240: 601a str r2, [r3, #0] htim1.Init.Prescaler = 0; 8001242: 4b61 ldr r3, [pc, #388] @ (80013c8 ) 8001244: 2200 movs r2, #0 8001246: 605a str r2, [r3, #4] htim1.Init.CounterMode = TIM_COUNTERMODE_UP; 8001248: 4b5f ldr r3, [pc, #380] @ (80013c8 ) 800124a: 2200 movs r2, #0 800124c: 609a str r2, [r3, #8] htim1.Init.Period = 2400; 800124e: 4b5e ldr r3, [pc, #376] @ (80013c8 ) 8001250: 2296 movs r2, #150 @ 0x96 8001252: 0112 lsls r2, r2, #4 8001254: 60da str r2, [r3, #12] htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8001256: 4b5c ldr r3, [pc, #368] @ (80013c8 ) 8001258: 2200 movs r2, #0 800125a: 611a str r2, [r3, #16] htim1.Init.RepetitionCounter = 0; 800125c: 4b5a ldr r3, [pc, #360] @ (80013c8 ) 800125e: 2200 movs r2, #0 8001260: 615a str r2, [r3, #20] htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001262: 4b59 ldr r3, [pc, #356] @ (80013c8 ) 8001264: 2200 movs r2, #0 8001266: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim1) != HAL_OK) 8001268: 4b57 ldr r3, [pc, #348] @ (80013c8 ) 800126a: 0018 movs r0, r3 800126c: f004 f8f2 bl 8005454 8001270: 1e03 subs r3, r0, #0 8001272: d001 beq.n 8001278 { Error_Handler(); 8001274: f002 fbea bl 8003a4c } sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL; 8001278: 2160 movs r1, #96 @ 0x60 800127a: 187b adds r3, r7, r1 800127c: 2280 movs r2, #128 @ 0x80 800127e: 0152 lsls r2, r2, #5 8001280: 601a str r2, [r3, #0] if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK) 8001282: 187a adds r2, r7, r1 8001284: 4b50 ldr r3, [pc, #320] @ (80013c8 ) 8001286: 0011 movs r1, r2 8001288: 0018 movs r0, r3 800128a: f004 fe47 bl 8005f1c 800128e: 1e03 subs r3, r0, #0 8001290: d001 beq.n 8001296 { Error_Handler(); 8001292: f002 fbdb bl 8003a4c } if (HAL_TIM_PWM_Init(&htim1) != HAL_OK) 8001296: 4b4c ldr r3, [pc, #304] @ (80013c8 ) 8001298: 0018 movs r0, r3 800129a: f004 f9ad bl 80055f8 800129e: 1e03 subs r3, r0, #0 80012a0: d001 beq.n 80012a6 { Error_Handler(); 80012a2: f002 fbd3 bl 8003a4c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 80012a6: 2154 movs r1, #84 @ 0x54 80012a8: 187b adds r3, r7, r1 80012aa: 2200 movs r2, #0 80012ac: 601a str r2, [r3, #0] sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET; 80012ae: 187b adds r3, r7, r1 80012b0: 2200 movs r2, #0 80012b2: 605a str r2, [r3, #4] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 80012b4: 187b adds r3, r7, r1 80012b6: 2200 movs r2, #0 80012b8: 609a str r2, [r3, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK) 80012ba: 187a adds r2, r7, r1 80012bc: 4b42 ldr r3, [pc, #264] @ (80013c8 ) 80012be: 0011 movs r1, r2 80012c0: 0018 movs r0, r3 80012c2: f005 faf9 bl 80068b8 80012c6: 1e03 subs r3, r0, #0 80012c8: d001 beq.n 80012ce { Error_Handler(); 80012ca: f002 fbbf bl 8003a4c } sConfigOC.OCMode = TIM_OCMODE_PWM1; 80012ce: 2138 movs r1, #56 @ 0x38 80012d0: 187b adds r3, r7, r1 80012d2: 2260 movs r2, #96 @ 0x60 80012d4: 601a str r2, [r3, #0] sConfigOC.Pulse = 0; 80012d6: 187b adds r3, r7, r1 80012d8: 2200 movs r2, #0 80012da: 605a str r2, [r3, #4] sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH; 80012dc: 187b adds r3, r7, r1 80012de: 2200 movs r2, #0 80012e0: 609a str r2, [r3, #8] sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH; 80012e2: 187b adds r3, r7, r1 80012e4: 2200 movs r2, #0 80012e6: 60da str r2, [r3, #12] sConfigOC.OCFastMode = TIM_OCFAST_DISABLE; 80012e8: 187b adds r3, r7, r1 80012ea: 2200 movs r2, #0 80012ec: 611a str r2, [r3, #16] sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET; 80012ee: 187b adds r3, r7, r1 80012f0: 2200 movs r2, #0 80012f2: 615a str r2, [r3, #20] sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET; 80012f4: 187b adds r3, r7, r1 80012f6: 2200 movs r2, #0 80012f8: 619a str r2, [r3, #24] if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK) 80012fa: 1879 adds r1, r7, r1 80012fc: 4b32 ldr r3, [pc, #200] @ (80013c8 ) 80012fe: 2200 movs r2, #0 8001300: 0018 movs r0, r3 8001302: f004 fd0b bl 8005d1c 8001306: 1e03 subs r3, r0, #0 8001308: d001 beq.n 800130e { Error_Handler(); 800130a: f002 fb9f bl 8003a4c } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK) 800130e: 2338 movs r3, #56 @ 0x38 8001310: 18f9 adds r1, r7, r3 8001312: 4b2d ldr r3, [pc, #180] @ (80013c8 ) 8001314: 2204 movs r2, #4 8001316: 0018 movs r0, r3 8001318: f004 fd00 bl 8005d1c 800131c: 1e03 subs r3, r0, #0 800131e: d001 beq.n 8001324 { Error_Handler(); 8001320: f002 fb94 bl 8003a4c } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK) 8001324: 2338 movs r3, #56 @ 0x38 8001326: 18f9 adds r1, r7, r3 8001328: 4b27 ldr r3, [pc, #156] @ (80013c8 ) 800132a: 2208 movs r2, #8 800132c: 0018 movs r0, r3 800132e: f004 fcf5 bl 8005d1c 8001332: 1e03 subs r3, r0, #0 8001334: d001 beq.n 800133a { Error_Handler(); 8001336: f002 fb89 bl 8003a4c } if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK) 800133a: 2338 movs r3, #56 @ 0x38 800133c: 18f9 adds r1, r7, r3 800133e: 4b22 ldr r3, [pc, #136] @ (80013c8 ) 8001340: 220c movs r2, #12 8001342: 0018 movs r0, r3 8001344: f004 fcea bl 8005d1c 8001348: 1e03 subs r3, r0, #0 800134a: d001 beq.n 8001350 { Error_Handler(); 800134c: f002 fb7e bl 8003a4c } sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE; 8001350: 1d3b adds r3, r7, #4 8001352: 2200 movs r2, #0 8001354: 601a str r2, [r3, #0] sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE; 8001356: 1d3b adds r3, r7, #4 8001358: 2200 movs r2, #0 800135a: 605a str r2, [r3, #4] sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF; 800135c: 1d3b adds r3, r7, #4 800135e: 2200 movs r2, #0 8001360: 609a str r2, [r3, #8] sBreakDeadTimeConfig.DeadTime = 0; 8001362: 1d3b adds r3, r7, #4 8001364: 2200 movs r2, #0 8001366: 60da str r2, [r3, #12] sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE; 8001368: 1d3b adds r3, r7, #4 800136a: 2200 movs r2, #0 800136c: 611a str r2, [r3, #16] sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH; 800136e: 1d3b adds r3, r7, #4 8001370: 2280 movs r2, #128 @ 0x80 8001372: 0192 lsls r2, r2, #6 8001374: 615a str r2, [r3, #20] sBreakDeadTimeConfig.BreakFilter = 0; 8001376: 1d3b adds r3, r7, #4 8001378: 2200 movs r2, #0 800137a: 619a str r2, [r3, #24] sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT; 800137c: 1d3b adds r3, r7, #4 800137e: 2200 movs r2, #0 8001380: 61da str r2, [r3, #28] sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE; 8001382: 1d3b adds r3, r7, #4 8001384: 2200 movs r2, #0 8001386: 621a str r2, [r3, #32] sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH; 8001388: 1d3b adds r3, r7, #4 800138a: 2280 movs r2, #128 @ 0x80 800138c: 0492 lsls r2, r2, #18 800138e: 625a str r2, [r3, #36] @ 0x24 sBreakDeadTimeConfig.Break2Filter = 0; 8001390: 1d3b adds r3, r7, #4 8001392: 2200 movs r2, #0 8001394: 629a str r2, [r3, #40] @ 0x28 sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT; 8001396: 1d3b adds r3, r7, #4 8001398: 2200 movs r2, #0 800139a: 62da str r2, [r3, #44] @ 0x2c sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE; 800139c: 1d3b adds r3, r7, #4 800139e: 2200 movs r2, #0 80013a0: 631a str r2, [r3, #48] @ 0x30 if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK) 80013a2: 1d3a adds r2, r7, #4 80013a4: 4b08 ldr r3, [pc, #32] @ (80013c8 ) 80013a6: 0011 movs r1, r2 80013a8: 0018 movs r0, r3 80013aa: f005 faed bl 8006988 80013ae: 1e03 subs r3, r0, #0 80013b0: d001 beq.n 80013b6 { Error_Handler(); 80013b2: f002 fb4b bl 8003a4c } /* USER CODE BEGIN TIM1_Init 2 */ /* USER CODE END TIM1_Init 2 */ HAL_TIM_MspPostInit(&htim1); 80013b6: 4b04 ldr r3, [pc, #16] @ (80013c8 ) 80013b8: 0018 movs r0, r3 80013ba: f002 fc35 bl 8003c28 } 80013be: 46c0 nop @ (mov r8, r8) 80013c0: 46bd mov sp, r7 80013c2: b01c add sp, #112 @ 0x70 80013c4: bd80 pop {r7, pc} 80013c6: 46c0 nop @ (mov r8, r8) 80013c8: 2000004c .word 0x2000004c 80013cc: 40012c00 .word 0x40012c00 080013d0 : * @brief TIM3 Initialization Function * @param None * @retval None */ static void MX_TIM3_Init(void) { 80013d0: b590 push {r4, r7, lr} 80013d2: b08d sub sp, #52 @ 0x34 80013d4: af00 add r7, sp, #0 /* USER CODE BEGIN TIM3_Init 0 */ /* USER CODE END TIM3_Init 0 */ TIM_Encoder_InitTypeDef sConfig = {0}; 80013d6: 240c movs r4, #12 80013d8: 193b adds r3, r7, r4 80013da: 0018 movs r0, r3 80013dc: 2324 movs r3, #36 @ 0x24 80013de: 001a movs r2, r3 80013e0: 2100 movs r1, #0 80013e2: f006 fc67 bl 8007cb4 TIM_MasterConfigTypeDef sMasterConfig = {0}; 80013e6: 003b movs r3, r7 80013e8: 0018 movs r0, r3 80013ea: 230c movs r3, #12 80013ec: 001a movs r2, r3 80013ee: 2100 movs r1, #0 80013f0: f006 fc60 bl 8007cb4 /* USER CODE BEGIN TIM3_Init 1 */ /* USER CODE END TIM3_Init 1 */ htim3.Instance = TIM3; 80013f4: 4b25 ldr r3, [pc, #148] @ (800148c ) 80013f6: 4a26 ldr r2, [pc, #152] @ (8001490 ) 80013f8: 601a str r2, [r3, #0] htim3.Init.Prescaler = 0; 80013fa: 4b24 ldr r3, [pc, #144] @ (800148c ) 80013fc: 2200 movs r2, #0 80013fe: 605a str r2, [r3, #4] htim3.Init.CounterMode = TIM_COUNTERMODE_UP; 8001400: 4b22 ldr r3, [pc, #136] @ (800148c ) 8001402: 2200 movs r2, #0 8001404: 609a str r2, [r3, #8] htim3.Init.Period = 65535; 8001406: 4b21 ldr r3, [pc, #132] @ (800148c ) 8001408: 4a22 ldr r2, [pc, #136] @ (8001494 ) 800140a: 60da str r2, [r3, #12] htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 800140c: 4b1f ldr r3, [pc, #124] @ (800148c ) 800140e: 2200 movs r2, #0 8001410: 611a str r2, [r3, #16] htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001412: 4b1e ldr r3, [pc, #120] @ (800148c ) 8001414: 2200 movs r2, #0 8001416: 619a str r2, [r3, #24] sConfig.EncoderMode = TIM_ENCODERMODE_TI12; 8001418: 0021 movs r1, r4 800141a: 187b adds r3, r7, r1 800141c: 2203 movs r2, #3 800141e: 601a str r2, [r3, #0] sConfig.IC1Polarity = TIM_ICPOLARITY_RISING; 8001420: 187b adds r3, r7, r1 8001422: 2200 movs r2, #0 8001424: 605a str r2, [r3, #4] sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI; 8001426: 187b adds r3, r7, r1 8001428: 2201 movs r2, #1 800142a: 609a str r2, [r3, #8] sConfig.IC1Prescaler = TIM_ICPSC_DIV1; 800142c: 187b adds r3, r7, r1 800142e: 2200 movs r2, #0 8001430: 60da str r2, [r3, #12] sConfig.IC1Filter = 0; 8001432: 187b adds r3, r7, r1 8001434: 2200 movs r2, #0 8001436: 611a str r2, [r3, #16] sConfig.IC2Polarity = TIM_ICPOLARITY_RISING; 8001438: 187b adds r3, r7, r1 800143a: 2200 movs r2, #0 800143c: 615a str r2, [r3, #20] sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI; 800143e: 187b adds r3, r7, r1 8001440: 2201 movs r2, #1 8001442: 619a str r2, [r3, #24] sConfig.IC2Prescaler = TIM_ICPSC_DIV1; 8001444: 187b adds r3, r7, r1 8001446: 2200 movs r2, #0 8001448: 61da str r2, [r3, #28] sConfig.IC2Filter = 0; 800144a: 187b adds r3, r7, r1 800144c: 2200 movs r2, #0 800144e: 621a str r2, [r3, #32] if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK) 8001450: 187a adds r2, r7, r1 8001452: 4b0e ldr r3, [pc, #56] @ (800148c ) 8001454: 0011 movs r1, r2 8001456: 0018 movs r0, r3 8001458: f004 fa0c bl 8005874 800145c: 1e03 subs r3, r0, #0 800145e: d001 beq.n 8001464 { Error_Handler(); 8001460: f002 faf4 bl 8003a4c } sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; 8001464: 003b movs r3, r7 8001466: 2200 movs r2, #0 8001468: 601a str r2, [r3, #0] sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE; 800146a: 003b movs r3, r7 800146c: 2200 movs r2, #0 800146e: 609a str r2, [r3, #8] if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK) 8001470: 003a movs r2, r7 8001472: 4b06 ldr r3, [pc, #24] @ (800148c ) 8001474: 0011 movs r1, r2 8001476: 0018 movs r0, r3 8001478: f005 fa1e bl 80068b8 800147c: 1e03 subs r3, r0, #0 800147e: d001 beq.n 8001484 { Error_Handler(); 8001480: f002 fae4 bl 8003a4c } /* USER CODE BEGIN TIM3_Init 2 */ /* USER CODE END TIM3_Init 2 */ } 8001484: 46c0 nop @ (mov r8, r8) 8001486: 46bd mov sp, r7 8001488: b00d add sp, #52 @ 0x34 800148a: bd90 pop {r4, r7, pc} 800148c: 20000098 .word 0x20000098 8001490: 40000400 .word 0x40000400 8001494: 0000ffff .word 0x0000ffff 08001498 : * @brief TIM14 Initialization Function * @param None * @retval None */ static void MX_TIM14_Init(void) { 8001498: b580 push {r7, lr} 800149a: af00 add r7, sp, #0 /* USER CODE END TIM14_Init 0 */ /* USER CODE BEGIN TIM14_Init 1 */ /* USER CODE END TIM14_Init 1 */ htim14.Instance = TIM14; 800149c: 4b0e ldr r3, [pc, #56] @ (80014d8 ) 800149e: 4a0f ldr r2, [pc, #60] @ (80014dc ) 80014a0: 601a str r2, [r3, #0] htim14.Init.Prescaler = 480-1; 80014a2: 4b0d ldr r3, [pc, #52] @ (80014d8 ) 80014a4: 22e0 movs r2, #224 @ 0xe0 80014a6: 32ff adds r2, #255 @ 0xff 80014a8: 605a str r2, [r3, #4] htim14.Init.CounterMode = TIM_COUNTERMODE_UP; 80014aa: 4b0b ldr r3, [pc, #44] @ (80014d8 ) 80014ac: 2200 movs r2, #0 80014ae: 609a str r2, [r3, #8] htim14.Init.Period = 50; 80014b0: 4b09 ldr r3, [pc, #36] @ (80014d8 ) 80014b2: 2232 movs r2, #50 @ 0x32 80014b4: 60da str r2, [r3, #12] htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80014b6: 4b08 ldr r3, [pc, #32] @ (80014d8 ) 80014b8: 2200 movs r2, #0 80014ba: 611a str r2, [r3, #16] htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 80014bc: 4b06 ldr r3, [pc, #24] @ (80014d8 ) 80014be: 2200 movs r2, #0 80014c0: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim14) != HAL_OK) 80014c2: 4b05 ldr r3, [pc, #20] @ (80014d8 ) 80014c4: 0018 movs r0, r3 80014c6: f003 ffc5 bl 8005454 80014ca: 1e03 subs r3, r0, #0 80014cc: d001 beq.n 80014d2 { Error_Handler(); 80014ce: f002 fabd bl 8003a4c } /* USER CODE BEGIN TIM14_Init 2 */ /* USER CODE END TIM14_Init 2 */ } 80014d2: 46c0 nop @ (mov r8, r8) 80014d4: 46bd mov sp, r7 80014d6: bd80 pop {r7, pc} 80014d8: 200000e4 .word 0x200000e4 80014dc: 40002000 .word 0x40002000 080014e0 : * @brief TIM16 Initialization Function * @param None * @retval None */ static void MX_TIM16_Init(void) { 80014e0: b580 push {r7, lr} 80014e2: af00 add r7, sp, #0 /* USER CODE END TIM16_Init 0 */ /* USER CODE BEGIN TIM16_Init 1 */ /* USER CODE END TIM16_Init 1 */ htim16.Instance = TIM16; 80014e4: 4b0f ldr r3, [pc, #60] @ (8001524 ) 80014e6: 4a10 ldr r2, [pc, #64] @ (8001528 ) 80014e8: 601a str r2, [r3, #0] htim16.Init.Prescaler = 48000-1; 80014ea: 4b0e ldr r3, [pc, #56] @ (8001524 ) 80014ec: 4a0f ldr r2, [pc, #60] @ (800152c ) 80014ee: 605a str r2, [r3, #4] htim16.Init.CounterMode = TIM_COUNTERMODE_UP; 80014f0: 4b0c ldr r3, [pc, #48] @ (8001524 ) 80014f2: 2200 movs r2, #0 80014f4: 609a str r2, [r3, #8] htim16.Init.Period = 65535; 80014f6: 4b0b ldr r3, [pc, #44] @ (8001524 ) 80014f8: 4a0d ldr r2, [pc, #52] @ (8001530 ) 80014fa: 60da str r2, [r3, #12] htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 80014fc: 4b09 ldr r3, [pc, #36] @ (8001524 ) 80014fe: 2200 movs r2, #0 8001500: 611a str r2, [r3, #16] htim16.Init.RepetitionCounter = 0; 8001502: 4b08 ldr r3, [pc, #32] @ (8001524 ) 8001504: 2200 movs r2, #0 8001506: 615a str r2, [r3, #20] htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 8001508: 4b06 ldr r3, [pc, #24] @ (8001524 ) 800150a: 2200 movs r2, #0 800150c: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim16) != HAL_OK) 800150e: 4b05 ldr r3, [pc, #20] @ (8001524 ) 8001510: 0018 movs r0, r3 8001512: f003 ff9f bl 8005454 8001516: 1e03 subs r3, r0, #0 8001518: d001 beq.n 800151e { Error_Handler(); 800151a: f002 fa97 bl 8003a4c } /* USER CODE BEGIN TIM16_Init 2 */ /* USER CODE END TIM16_Init 2 */ } 800151e: 46c0 nop @ (mov r8, r8) 8001520: 46bd mov sp, r7 8001522: bd80 pop {r7, pc} 8001524: 20000130 .word 0x20000130 8001528: 40014400 .word 0x40014400 800152c: 0000bb7f .word 0x0000bb7f 8001530: 0000ffff .word 0x0000ffff 08001534 : * @brief TIM17 Initialization Function * @param None * @retval None */ static void MX_TIM17_Init(void) { 8001534: b580 push {r7, lr} 8001536: af00 add r7, sp, #0 /* USER CODE END TIM17_Init 0 */ /* USER CODE BEGIN TIM17_Init 1 */ /* USER CODE END TIM17_Init 1 */ htim17.Instance = TIM17; 8001538: 4b0f ldr r3, [pc, #60] @ (8001578 ) 800153a: 4a10 ldr r2, [pc, #64] @ (800157c ) 800153c: 601a str r2, [r3, #0] htim17.Init.Prescaler = 48000-1; 800153e: 4b0e ldr r3, [pc, #56] @ (8001578 ) 8001540: 4a0f ldr r2, [pc, #60] @ (8001580 ) 8001542: 605a str r2, [r3, #4] htim17.Init.CounterMode = TIM_COUNTERMODE_UP; 8001544: 4b0c ldr r3, [pc, #48] @ (8001578 ) 8001546: 2200 movs r2, #0 8001548: 609a str r2, [r3, #8] htim17.Init.Period = 65535; 800154a: 4b0b ldr r3, [pc, #44] @ (8001578 ) 800154c: 4a0d ldr r2, [pc, #52] @ (8001584 ) 800154e: 60da str r2, [r3, #12] htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1; 8001550: 4b09 ldr r3, [pc, #36] @ (8001578 ) 8001552: 2200 movs r2, #0 8001554: 611a str r2, [r3, #16] htim17.Init.RepetitionCounter = 0; 8001556: 4b08 ldr r3, [pc, #32] @ (8001578 ) 8001558: 2200 movs r2, #0 800155a: 615a str r2, [r3, #20] htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; 800155c: 4b06 ldr r3, [pc, #24] @ (8001578 ) 800155e: 2200 movs r2, #0 8001560: 619a str r2, [r3, #24] if (HAL_TIM_Base_Init(&htim17) != HAL_OK) 8001562: 4b05 ldr r3, [pc, #20] @ (8001578 ) 8001564: 0018 movs r0, r3 8001566: f003 ff75 bl 8005454 800156a: 1e03 subs r3, r0, #0 800156c: d001 beq.n 8001572 { Error_Handler(); 800156e: f002 fa6d bl 8003a4c } /* USER CODE BEGIN TIM17_Init 2 */ /* USER CODE END TIM17_Init 2 */ } 8001572: 46c0 nop @ (mov r8, r8) 8001574: 46bd mov sp, r7 8001576: bd80 pop {r7, pc} 8001578: 2000017c .word 0x2000017c 800157c: 40014800 .word 0x40014800 8001580: 0000bb7f .word 0x0000bb7f 8001584: 0000ffff .word 0x0000ffff 08001588 : * @brief USART1 Initialization Function * @param None * @retval None */ static void MX_USART1_UART_Init(void) { 8001588: b580 push {r7, lr} 800158a: af00 add r7, sp, #0 /* USER CODE END USART1_Init 0 */ /* USER CODE BEGIN USART1_Init 1 */ /* USER CODE END USART1_Init 1 */ huart1.Instance = USART1; 800158c: 4b23 ldr r3, [pc, #140] @ (800161c ) 800158e: 4a24 ldr r2, [pc, #144] @ (8001620 ) 8001590: 601a str r2, [r3, #0] huart1.Init.BaudRate = 115200; 8001592: 4b22 ldr r3, [pc, #136] @ (800161c ) 8001594: 22e1 movs r2, #225 @ 0xe1 8001596: 0252 lsls r2, r2, #9 8001598: 605a str r2, [r3, #4] huart1.Init.WordLength = UART_WORDLENGTH_8B; 800159a: 4b20 ldr r3, [pc, #128] @ (800161c ) 800159c: 2200 movs r2, #0 800159e: 609a str r2, [r3, #8] huart1.Init.StopBits = UART_STOPBITS_1; 80015a0: 4b1e ldr r3, [pc, #120] @ (800161c ) 80015a2: 2200 movs r2, #0 80015a4: 60da str r2, [r3, #12] huart1.Init.Parity = UART_PARITY_NONE; 80015a6: 4b1d ldr r3, [pc, #116] @ (800161c ) 80015a8: 2200 movs r2, #0 80015aa: 611a str r2, [r3, #16] huart1.Init.Mode = UART_MODE_TX_RX; 80015ac: 4b1b ldr r3, [pc, #108] @ (800161c ) 80015ae: 220c movs r2, #12 80015b0: 615a str r2, [r3, #20] huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; 80015b2: 4b1a ldr r3, [pc, #104] @ (800161c ) 80015b4: 2200 movs r2, #0 80015b6: 619a str r2, [r3, #24] huart1.Init.OverSampling = UART_OVERSAMPLING_16; 80015b8: 4b18 ldr r3, [pc, #96] @ (800161c ) 80015ba: 2200 movs r2, #0 80015bc: 61da str r2, [r3, #28] huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 80015be: 4b17 ldr r3, [pc, #92] @ (800161c ) 80015c0: 2200 movs r2, #0 80015c2: 621a str r2, [r3, #32] huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; 80015c4: 4b15 ldr r3, [pc, #84] @ (800161c ) 80015c6: 2200 movs r2, #0 80015c8: 625a str r2, [r3, #36] @ 0x24 huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 80015ca: 4b14 ldr r3, [pc, #80] @ (800161c ) 80015cc: 2200 movs r2, #0 80015ce: 629a str r2, [r3, #40] @ 0x28 if (HAL_UART_Init(&huart1) != HAL_OK) 80015d0: 4b12 ldr r3, [pc, #72] @ (800161c ) 80015d2: 0018 movs r0, r3 80015d4: f005 fa8c bl 8006af0 80015d8: 1e03 subs r3, r0, #0 80015da: d001 beq.n 80015e0 { Error_Handler(); 80015dc: f002 fa36 bl 8003a4c } if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) 80015e0: 4b0e ldr r3, [pc, #56] @ (800161c ) 80015e2: 2100 movs r1, #0 80015e4: 0018 movs r0, r3 80015e6: f006 fa0f bl 8007a08 80015ea: 1e03 subs r3, r0, #0 80015ec: d001 beq.n 80015f2 { Error_Handler(); 80015ee: f002 fa2d bl 8003a4c } if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) 80015f2: 4b0a ldr r3, [pc, #40] @ (800161c ) 80015f4: 2100 movs r1, #0 80015f6: 0018 movs r0, r3 80015f8: f006 fa46 bl 8007a88 80015fc: 1e03 subs r3, r0, #0 80015fe: d001 beq.n 8001604 { Error_Handler(); 8001600: f002 fa24 bl 8003a4c } if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) 8001604: 4b05 ldr r3, [pc, #20] @ (800161c ) 8001606: 0018 movs r0, r3 8001608: f006 f9c4 bl 8007994 800160c: 1e03 subs r3, r0, #0 800160e: d001 beq.n 8001614 { Error_Handler(); 8001610: f002 fa1c bl 8003a4c } /* USER CODE BEGIN USART1_Init 2 */ /* USER CODE END USART1_Init 2 */ } 8001614: 46c0 nop @ (mov r8, r8) 8001616: 46bd mov sp, r7 8001618: bd80 pop {r7, pc} 800161a: 46c0 nop @ (mov r8, r8) 800161c: 200001c8 .word 0x200001c8 8001620: 40013800 .word 0x40013800 08001624 : * @brief USART2 Initialization Function * @param None * @retval None */ static void MX_USART2_UART_Init(void) { 8001624: b580 push {r7, lr} 8001626: af00 add r7, sp, #0 /* USER CODE END USART2_Init 0 */ /* USER CODE BEGIN USART2_Init 1 */ /* USER CODE END USART2_Init 1 */ huart2.Instance = USART2; 8001628: 4b26 ldr r3, [pc, #152] @ (80016c4 ) 800162a: 4a27 ldr r2, [pc, #156] @ (80016c8 ) 800162c: 601a str r2, [r3, #0] huart2.Init.BaudRate = 57600; 800162e: 4b25 ldr r3, [pc, #148] @ (80016c4 ) 8001630: 22e1 movs r2, #225 @ 0xe1 8001632: 0212 lsls r2, r2, #8 8001634: 605a str r2, [r3, #4] huart2.Init.WordLength = UART_WORDLENGTH_8B; 8001636: 4b23 ldr r3, [pc, #140] @ (80016c4 ) 8001638: 2200 movs r2, #0 800163a: 609a str r2, [r3, #8] huart2.Init.StopBits = UART_STOPBITS_1; 800163c: 4b21 ldr r3, [pc, #132] @ (80016c4 ) 800163e: 2200 movs r2, #0 8001640: 60da str r2, [r3, #12] huart2.Init.Parity = UART_PARITY_NONE; 8001642: 4b20 ldr r3, [pc, #128] @ (80016c4 ) 8001644: 2200 movs r2, #0 8001646: 611a str r2, [r3, #16] huart2.Init.Mode = UART_MODE_TX_RX; 8001648: 4b1e ldr r3, [pc, #120] @ (80016c4 ) 800164a: 220c movs r2, #12 800164c: 615a str r2, [r3, #20] huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE; 800164e: 4b1d ldr r3, [pc, #116] @ (80016c4 ) 8001650: 2200 movs r2, #0 8001652: 619a str r2, [r3, #24] huart2.Init.OverSampling = UART_OVERSAMPLING_16; 8001654: 4b1b ldr r3, [pc, #108] @ (80016c4 ) 8001656: 2200 movs r2, #0 8001658: 61da str r2, [r3, #28] huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; 800165a: 4b1a ldr r3, [pc, #104] @ (80016c4 ) 800165c: 2200 movs r2, #0 800165e: 621a str r2, [r3, #32] huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1; 8001660: 4b18 ldr r3, [pc, #96] @ (80016c4 ) 8001662: 2200 movs r2, #0 8001664: 625a str r2, [r3, #36] @ 0x24 huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; 8001666: 4b17 ldr r3, [pc, #92] @ (80016c4 ) 8001668: 2200 movs r2, #0 800166a: 629a str r2, [r3, #40] @ 0x28 if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 0, 0) != HAL_OK) 800166c: 4815 ldr r0, [pc, #84] @ (80016c4 ) 800166e: 2300 movs r3, #0 8001670: 2200 movs r2, #0 8001672: 2100 movs r1, #0 8001674: f006 f91c bl 80078b0 8001678: 1e03 subs r3, r0, #0 800167a: d001 beq.n 8001680 { Error_Handler(); 800167c: f002 f9e6 bl 8003a4c } if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_2) != HAL_OK) 8001680: 2380 movs r3, #128 @ 0x80 8001682: 05da lsls r2, r3, #23 8001684: 4b0f ldr r3, [pc, #60] @ (80016c4 ) 8001686: 0011 movs r1, r2 8001688: 0018 movs r0, r3 800168a: f006 f9bd bl 8007a08 800168e: 1e03 subs r3, r0, #0 8001690: d001 beq.n 8001696 { Error_Handler(); 8001692: f002 f9db bl 8003a4c } if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_2) != HAL_OK) 8001696: 2380 movs r3, #128 @ 0x80 8001698: 04da lsls r2, r3, #19 800169a: 4b0a ldr r3, [pc, #40] @ (80016c4 ) 800169c: 0011 movs r1, r2 800169e: 0018 movs r0, r3 80016a0: f006 f9f2 bl 8007a88 80016a4: 1e03 subs r3, r0, #0 80016a6: d001 beq.n 80016ac { Error_Handler(); 80016a8: f002 f9d0 bl 8003a4c } if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK) 80016ac: 4b05 ldr r3, [pc, #20] @ (80016c4 ) 80016ae: 0018 movs r0, r3 80016b0: f006 f970 bl 8007994 80016b4: 1e03 subs r3, r0, #0 80016b6: d001 beq.n 80016bc { Error_Handler(); 80016b8: f002 f9c8 bl 8003a4c } /* USER CODE BEGIN USART2_Init 2 */ /* USER CODE END USART2_Init 2 */ } 80016bc: 46c0 nop @ (mov r8, r8) 80016be: 46bd mov sp, r7 80016c0: bd80 pop {r7, pc} 80016c2: 46c0 nop @ (mov r8, r8) 80016c4: 2000025c .word 0x2000025c 80016c8: 40004400 .word 0x40004400 080016cc : /** * Enable DMA controller clock */ static void MX_DMA_Init(void) { 80016cc: b580 push {r7, lr} 80016ce: b082 sub sp, #8 80016d0: af00 add r7, sp, #0 /* DMA controller clock enable */ __HAL_RCC_DMA1_CLK_ENABLE(); 80016d2: 4b10 ldr r3, [pc, #64] @ (8001714 ) 80016d4: 6b9a ldr r2, [r3, #56] @ 0x38 80016d6: 4b0f ldr r3, [pc, #60] @ (8001714 ) 80016d8: 2101 movs r1, #1 80016da: 430a orrs r2, r1 80016dc: 639a str r2, [r3, #56] @ 0x38 80016de: 4b0d ldr r3, [pc, #52] @ (8001714 ) 80016e0: 6b9b ldr r3, [r3, #56] @ 0x38 80016e2: 2201 movs r2, #1 80016e4: 4013 ands r3, r2 80016e6: 607b str r3, [r7, #4] 80016e8: 687b ldr r3, [r7, #4] /* DMA interrupt init */ /* DMA1_Channel1_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); 80016ea: 2200 movs r2, #0 80016ec: 2100 movs r1, #0 80016ee: 2009 movs r0, #9 80016f0: f002 fdea bl 80042c8 HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); 80016f4: 2009 movs r0, #9 80016f6: f002 fdfc bl 80042f2 /* DMA1_Channel2_3_IRQn interrupt configuration */ HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0); 80016fa: 2200 movs r2, #0 80016fc: 2100 movs r1, #0 80016fe: 200a movs r0, #10 8001700: f002 fde2 bl 80042c8 HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn); 8001704: 200a movs r0, #10 8001706: f002 fdf4 bl 80042f2 } 800170a: 46c0 nop @ (mov r8, r8) 800170c: 46bd mov sp, r7 800170e: b002 add sp, #8 8001710: bd80 pop {r7, pc} 8001712: 46c0 nop @ (mov r8, r8) 8001714: 40021000 .word 0x40021000 08001718 : * @brief GPIO Initialization Function * @param None * @retval None */ static void MX_GPIO_Init(void) { 8001718: b590 push {r4, r7, lr} 800171a: b08b sub sp, #44 @ 0x2c 800171c: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800171e: 2414 movs r4, #20 8001720: 193b adds r3, r7, r4 8001722: 0018 movs r0, r3 8001724: 2314 movs r3, #20 8001726: 001a movs r2, r3 8001728: 2100 movs r1, #0 800172a: f006 fac3 bl 8007cb4 /* USER CODE BEGIN MX_GPIO_Init_1 */ /* USER CODE END MX_GPIO_Init_1 */ /* GPIO Ports Clock Enable */ __HAL_RCC_GPIOF_CLK_ENABLE(); 800172e: 4b3f ldr r3, [pc, #252] @ (800182c ) 8001730: 6b5a ldr r2, [r3, #52] @ 0x34 8001732: 4b3e ldr r3, [pc, #248] @ (800182c ) 8001734: 2120 movs r1, #32 8001736: 430a orrs r2, r1 8001738: 635a str r2, [r3, #52] @ 0x34 800173a: 4b3c ldr r3, [pc, #240] @ (800182c ) 800173c: 6b5b ldr r3, [r3, #52] @ 0x34 800173e: 2220 movs r2, #32 8001740: 4013 ands r3, r2 8001742: 613b str r3, [r7, #16] 8001744: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOA_CLK_ENABLE(); 8001746: 4b39 ldr r3, [pc, #228] @ (800182c ) 8001748: 6b5a ldr r2, [r3, #52] @ 0x34 800174a: 4b38 ldr r3, [pc, #224] @ (800182c ) 800174c: 2101 movs r1, #1 800174e: 430a orrs r2, r1 8001750: 635a str r2, [r3, #52] @ 0x34 8001752: 4b36 ldr r3, [pc, #216] @ (800182c ) 8001754: 6b5b ldr r3, [r3, #52] @ 0x34 8001756: 2201 movs r2, #1 8001758: 4013 ands r3, r2 800175a: 60fb str r3, [r7, #12] 800175c: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOC_CLK_ENABLE(); 800175e: 4b33 ldr r3, [pc, #204] @ (800182c ) 8001760: 6b5a ldr r2, [r3, #52] @ 0x34 8001762: 4b32 ldr r3, [pc, #200] @ (800182c ) 8001764: 2104 movs r1, #4 8001766: 430a orrs r2, r1 8001768: 635a str r2, [r3, #52] @ 0x34 800176a: 4b30 ldr r3, [pc, #192] @ (800182c ) 800176c: 6b5b ldr r3, [r3, #52] @ 0x34 800176e: 2204 movs r2, #4 8001770: 4013 ands r3, r2 8001772: 60bb str r3, [r7, #8] 8001774: 68bb ldr r3, [r7, #8] __HAL_RCC_GPIOB_CLK_ENABLE(); 8001776: 4b2d ldr r3, [pc, #180] @ (800182c ) 8001778: 6b5a ldr r2, [r3, #52] @ 0x34 800177a: 4b2c ldr r3, [pc, #176] @ (800182c ) 800177c: 2102 movs r1, #2 800177e: 430a orrs r2, r1 8001780: 635a str r2, [r3, #52] @ 0x34 8001782: 4b2a ldr r3, [pc, #168] @ (800182c ) 8001784: 6b5b ldr r3, [r3, #52] @ 0x34 8001786: 2202 movs r2, #2 8001788: 4013 ands r3, r2 800178a: 607b str r3, [r7, #4] 800178c: 687b ldr r3, [r7, #4] /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET); 800178e: 4928 ldr r1, [pc, #160] @ (8001830 ) 8001790: 23a0 movs r3, #160 @ 0xa0 8001792: 05db lsls r3, r3, #23 8001794: 2200 movs r2, #0 8001796: 0018 movs r0, r3 8001798: f003 f9ab bl 8004af2 /*Configure GPIO pin Output Level */ HAL_GPIO_WritePin(GPIOB, LED_R_Pin|LED_B_Pin|LED_G_Pin, GPIO_PIN_RESET); 800179c: 4b25 ldr r3, [pc, #148] @ (8001834 ) 800179e: 2200 movs r2, #0 80017a0: 2138 movs r1, #56 @ 0x38 80017a2: 0018 movs r0, r3 80017a4: f003 f9a5 bl 8004af2 /*Configure GPIO pins : USART2_NRE_Pin ONEWIRE_Pin */ GPIO_InitStruct.Pin = USART2_NRE_Pin|ONEWIRE_Pin; 80017a8: 193b adds r3, r7, r4 80017aa: 4a21 ldr r2, [pc, #132] @ (8001830 ) 80017ac: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80017ae: 193b adds r3, r7, r4 80017b0: 2201 movs r2, #1 80017b2: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 80017b4: 193b adds r3, r7, r4 80017b6: 2200 movs r2, #0 80017b8: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80017ba: 193b adds r3, r7, r4 80017bc: 2200 movs r2, #0 80017be: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 80017c0: 193a adds r2, r7, r4 80017c2: 23a0 movs r3, #160 @ 0xa0 80017c4: 05db lsls r3, r3, #23 80017c6: 0011 movs r1, r2 80017c8: 0018 movs r0, r3 80017ca: f003 f803 bl 80047d4 /*Configure GPIO pins : LED_R_Pin LED_B_Pin LED_G_Pin */ GPIO_InitStruct.Pin = LED_R_Pin|LED_B_Pin|LED_G_Pin; 80017ce: 193b adds r3, r7, r4 80017d0: 2238 movs r2, #56 @ 0x38 80017d2: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; 80017d4: 193b adds r3, r7, r4 80017d6: 2201 movs r2, #1 80017d8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 80017da: 193b adds r3, r7, r4 80017dc: 2200 movs r2, #0 80017de: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 80017e0: 193b adds r3, r7, r4 80017e2: 2200 movs r2, #0 80017e4: 60da str r2, [r3, #12] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 80017e6: 193b adds r3, r7, r4 80017e8: 4a12 ldr r2, [pc, #72] @ (8001834 ) 80017ea: 0019 movs r1, r3 80017ec: 0010 movs r0, r2 80017ee: f002 fff1 bl 80047d4 /*Configure GPIO pins : SW2_Pin SW1_Pin */ GPIO_InitStruct.Pin = SW2_Pin|SW1_Pin; 80017f2: 0021 movs r1, r4 80017f4: 187b adds r3, r7, r1 80017f6: 22c0 movs r2, #192 @ 0xc0 80017f8: 0092 lsls r2, r2, #2 80017fa: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING; 80017fc: 187b adds r3, r7, r1 80017fe: 4a0e ldr r2, [pc, #56] @ (8001838 ) 8001800: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8001802: 187b adds r3, r7, r1 8001804: 2200 movs r2, #0 8001806: 609a str r2, [r3, #8] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8001808: 187b adds r3, r7, r1 800180a: 4a0a ldr r2, [pc, #40] @ (8001834 ) 800180c: 0019 movs r1, r3 800180e: 0010 movs r0, r2 8001810: f002 ffe0 bl 80047d4 /* EXTI interrupt init*/ HAL_NVIC_SetPriority(EXTI4_15_IRQn, 0, 0); 8001814: 2200 movs r2, #0 8001816: 2100 movs r1, #0 8001818: 2007 movs r0, #7 800181a: f002 fd55 bl 80042c8 HAL_NVIC_EnableIRQ(EXTI4_15_IRQn); 800181e: 2007 movs r0, #7 8001820: f002 fd67 bl 80042f2 /* USER CODE BEGIN MX_GPIO_Init_2 */ // PEEL1/PEEL2 (PA2/PA3) are TIM1_CH3/CH4 - configured by MX_TIM1_Init /* USER CODE END MX_GPIO_Init_2 */ } 8001824: 46c0 nop @ (mov r8, r8) 8001826: 46bd mov sp, r7 8001828: b00b add sp, #44 @ 0x2c 800182a: bd90 pop {r4, r7, pc} 800182c: 40021000 .word 0x40021000 8001830: 00000401 .word 0x00000401 8001834: 50000400 .word 0x50000400 8001838: 10210000 .word 0x10210000 0800183c : /* USER CODE BEGIN 4 */ void HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef * htim) { 800183c: b580 push {r7, lr} 800183e: b088 sub sp, #32 8001840: af00 add r7, sp, #0 8001842: 6078 str r0, [r7, #4] if (htim == &htim14) // encoder check timer (runs at 20khz) 8001844: 687a ldr r2, [r7, #4] 8001846: 4b6e ldr r3, [pc, #440] @ (8001a00 ) 8001848: 429a cmp r2, r3 800184a: d000 beq.n 800184e 800184c: e0bf b.n 80019ce { uint16_t count = htim3.Instance->CNT; 800184e: 4b6d ldr r3, [pc, #436] @ (8001a04 ) 8001850: 681b ldr r3, [r3, #0] 8001852: 6a5a ldr r2, [r3, #36] @ 0x24 8001854: 211e movs r1, #30 8001856: 187b adds r3, r7, r1 8001858: 801a strh r2, [r3, #0] if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround 800185a: 4b6b ldr r3, [pc, #428] @ (8001a08 ) 800185c: 881b ldrh r3, [r3, #0] 800185e: 4a6b ldr r2, [pc, #428] @ (8001a0c ) 8001860: 4293 cmp r3, r2 8001862: d90b bls.n 800187c 8001864: 187b adds r3, r7, r1 8001866: 881a ldrh r2, [r3, #0] 8001868: 23fa movs r3, #250 @ 0xfa 800186a: 009b lsls r3, r3, #2 800186c: 429a cmp r2, r3 800186e: d205 bcs.n 800187c { encoder_count_extra ++; 8001870: 4b67 ldr r3, [pc, #412] @ (8001a10 ) 8001872: 681b ldr r3, [r3, #0] 8001874: 1c5a adds r2, r3, #1 8001876: 4b66 ldr r3, [pc, #408] @ (8001a10 ) 8001878: 601a str r2, [r3, #0] 800187a: e010 b.n 800189e } else if ((encoder_previous < CNT_LIMIT_ZONE) && (count > CNT_MAX-CNT_LIMIT_ZONE)) // negative turnaround 800187c: 4b62 ldr r3, [pc, #392] @ (8001a08 ) 800187e: 881a ldrh r2, [r3, #0] 8001880: 23fa movs r3, #250 @ 0xfa 8001882: 009b lsls r3, r3, #2 8001884: 429a cmp r2, r3 8001886: d20a bcs.n 800189e 8001888: 231e movs r3, #30 800188a: 18fb adds r3, r7, r3 800188c: 881b ldrh r3, [r3, #0] 800188e: 4a5f ldr r2, [pc, #380] @ (8001a0c ) 8001890: 4293 cmp r3, r2 8001892: d904 bls.n 800189e { encoder_count_extra --; 8001894: 4b5e ldr r3, [pc, #376] @ (8001a10 ) 8001896: 681b ldr r3, [r3, #0] 8001898: 1e5a subs r2, r3, #1 800189a: 4b5d ldr r3, [pc, #372] @ (8001a10 ) 800189c: 601a str r2, [r3, #0] } encoder_previous = count; // update previous for next cycle 800189e: 4b5a ldr r3, [pc, #360] @ (8001a08 ) 80018a0: 211e movs r1, #30 80018a2: 187a adds r2, r7, r1 80018a4: 8812 ldrh r2, [r2, #0] 80018a6: 801a strh r2, [r3, #0] total_count = (encoder_count_extra * 65536) + count; 80018a8: 4b59 ldr r3, [pc, #356] @ (8001a10 ) 80018aa: 681b ldr r3, [r3, #0] 80018ac: 041a lsls r2, r3, #16 80018ae: 187b adds r3, r7, r1 80018b0: 881b ldrh r3, [r3, #0] 80018b2: 18d2 adds r2, r2, r3 80018b4: 4b57 ldr r3, [pc, #348] @ (8001a14 ) 80018b6: 601a str r2, [r3, #0] // Position overflow prevention - reset counts when they get too large if (total_count > POSITION_OVERFLOW_THRESHOLD) 80018b8: 4b56 ldr r3, [pc, #344] @ (8001a14 ) 80018ba: 681a ldr r2, [r3, #0] 80018bc: 2380 movs r3, #128 @ 0x80 80018be: 05db lsls r3, r3, #23 80018c0: 429a cmp r2, r3 80018c2: db25 blt.n 8001910 { int32_t adjustment = POSITION_RESET_AMOUNT; 80018c4: 4b54 ldr r3, [pc, #336] @ (8001a18 ) 80018c6: 617b str r3, [r7, #20] total_count -= adjustment; 80018c8: 4b52 ldr r3, [pc, #328] @ (8001a14 ) 80018ca: 681a ldr r2, [r3, #0] 80018cc: 697b ldr r3, [r7, #20] 80018ce: 1ad2 subs r2, r2, r3 80018d0: 4b50 ldr r3, [pc, #320] @ (8001a14 ) 80018d2: 601a str r2, [r3, #0] target_count -= adjustment; 80018d4: 4b51 ldr r3, [pc, #324] @ (8001a1c ) 80018d6: 681a ldr r2, [r3, #0] 80018d8: 697b ldr r3, [r7, #20] 80018da: 1ad2 subs r2, r2, r3 80018dc: 4b4f ldr r3, [pc, #316] @ (8001a1c ) 80018de: 601a str r2, [r3, #0] feed_target_position -= adjustment; 80018e0: 4b4f ldr r3, [pc, #316] @ (8001a20 ) 80018e2: 681a ldr r2, [r3, #0] 80018e4: 697b ldr r3, [r7, #20] 80018e6: 1ad2 subs r2, r2, r3 80018e8: 4b4d ldr r3, [pc, #308] @ (8001a20 ) 80018ea: 601a str r2, [r3, #0] encoder_count_extra -= (adjustment / 65536); 80018ec: 697b ldr r3, [r7, #20] 80018ee: 2b00 cmp r3, #0 80018f0: da02 bge.n 80018f8 80018f2: 4a4c ldr r2, [pc, #304] @ (8001a24 ) 80018f4: 4694 mov ip, r2 80018f6: 4463 add r3, ip 80018f8: 141b asrs r3, r3, #16 80018fa: 425b negs r3, r3 80018fc: 001a movs r2, r3 80018fe: 4b44 ldr r3, [pc, #272] @ (8001a10 ) 8001900: 681b ldr r3, [r3, #0] 8001902: 18d2 adds r2, r2, r3 8001904: 4b42 ldr r3, [pc, #264] @ (8001a10 ) 8001906: 601a str r2, [r3, #0] mm_position = 0; // Reset mm tracking too 8001908: 4b47 ldr r3, [pc, #284] @ (8001a28 ) 800190a: 2200 movs r2, #0 800190c: 601a str r2, [r3, #0] 800190e: e029 b.n 8001964 } else if (total_count < -POSITION_OVERFLOW_THRESHOLD) 8001910: 4b40 ldr r3, [pc, #256] @ (8001a14 ) 8001912: 681a ldr r2, [r3, #0] 8001914: 23c0 movs r3, #192 @ 0xc0 8001916: 061b lsls r3, r3, #24 8001918: 429a cmp r2, r3 800191a: dc23 bgt.n 8001964 { int32_t adjustment = POSITION_RESET_AMOUNT; 800191c: 4b3e ldr r3, [pc, #248] @ (8001a18 ) 800191e: 61bb str r3, [r7, #24] total_count += adjustment; 8001920: 4b3c ldr r3, [pc, #240] @ (8001a14 ) 8001922: 681a ldr r2, [r3, #0] 8001924: 69bb ldr r3, [r7, #24] 8001926: 18d2 adds r2, r2, r3 8001928: 4b3a ldr r3, [pc, #232] @ (8001a14 ) 800192a: 601a str r2, [r3, #0] target_count += adjustment; 800192c: 4b3b ldr r3, [pc, #236] @ (8001a1c ) 800192e: 681a ldr r2, [r3, #0] 8001930: 69bb ldr r3, [r7, #24] 8001932: 18d2 adds r2, r2, r3 8001934: 4b39 ldr r3, [pc, #228] @ (8001a1c ) 8001936: 601a str r2, [r3, #0] feed_target_position += adjustment; 8001938: 4b39 ldr r3, [pc, #228] @ (8001a20 ) 800193a: 681a ldr r2, [r3, #0] 800193c: 69bb ldr r3, [r7, #24] 800193e: 18d2 adds r2, r2, r3 8001940: 4b37 ldr r3, [pc, #220] @ (8001a20 ) 8001942: 601a str r2, [r3, #0] encoder_count_extra += (adjustment / 65536); 8001944: 69bb ldr r3, [r7, #24] 8001946: 2b00 cmp r3, #0 8001948: da02 bge.n 8001950 800194a: 4a36 ldr r2, [pc, #216] @ (8001a24 ) 800194c: 4694 mov ip, r2 800194e: 4463 add r3, ip 8001950: 141b asrs r3, r3, #16 8001952: 001a movs r2, r3 8001954: 4b2e ldr r3, [pc, #184] @ (8001a10 ) 8001956: 681b ldr r3, [r3, #0] 8001958: 18d2 adds r2, r2, r3 800195a: 4b2d ldr r3, [pc, #180] @ (8001a10 ) 800195c: 601a str r2, [r3, #0] mm_position = 0; 800195e: 4b32 ldr r3, [pc, #200] @ (8001a28 ) 8001960: 2200 movs r2, #0 8001962: 601a str r2, [r3, #0] } if (pid_add!=0) 8001964: 4b31 ldr r3, [pc, #196] @ (8001a2c ) 8001966: 681b ldr r3, [r3, #0] 8001968: 2b00 cmp r3, #0 800196a: d00d beq.n 8001988 { int64_t temp = target_count + pid_add; 800196c: 4b2b ldr r3, [pc, #172] @ (8001a1c ) 800196e: 681a ldr r2, [r3, #0] 8001970: 4b2e ldr r3, [pc, #184] @ (8001a2c ) 8001972: 681b ldr r3, [r3, #0] 8001974: 18d3 adds r3, r2, r3 8001976: 60bb str r3, [r7, #8] 8001978: 17db asrs r3, r3, #31 800197a: 60fb str r3, [r7, #12] pid_add = 0; 800197c: 4b2b ldr r3, [pc, #172] @ (8001a2c ) 800197e: 2200 movs r2, #0 8001980: 601a str r2, [r3, #0] } else if(temp > (INT32_MAX-10000)) { //todo throw error } target_count = temp; 8001982: 68ba ldr r2, [r7, #8] 8001984: 4b25 ldr r3, [pc, #148] @ (8001a1c ) 8001986: 601a str r2, [r3, #0] } motor_cmd = pid_update_motor(&motor_pid,target_count,total_count); 8001988: 4b24 ldr r3, [pc, #144] @ (8001a1c ) 800198a: 6819 ldr r1, [r3, #0] 800198c: 4b21 ldr r3, [pc, #132] @ (8001a14 ) 800198e: 681a ldr r2, [r3, #0] 8001990: 4b27 ldr r3, [pc, #156] @ (8001a30 ) 8001992: 0018 movs r0, r3 8001994: f7fe ff53 bl 800083e 8001998: 0003 movs r3, r0 800199a: 001a movs r2, r3 800199c: 4b25 ldr r3, [pc, #148] @ (8001a34 ) 800199e: 601a str r2, [r3, #0] debug_pid_output = motor_cmd.dir ? motor_cmd.pwm : -motor_cmd.pwm; // Capture for debug 80019a0: 4b24 ldr r3, [pc, #144] @ (8001a34 ) 80019a2: 789b ldrb r3, [r3, #2] 80019a4: 2b00 cmp r3, #0 80019a6: d003 beq.n 80019b0 80019a8: 4b22 ldr r3, [pc, #136] @ (8001a34 ) 80019aa: 881b ldrh r3, [r3, #0] 80019ac: b21b sxth r3, r3 80019ae: e004 b.n 80019ba 80019b0: 4b20 ldr r3, [pc, #128] @ (8001a34 ) 80019b2: 881b ldrh r3, [r3, #0] 80019b4: 425b negs r3, r3 80019b6: b29b uxth r3, r3 80019b8: b21b sxth r3, r3 80019ba: 4a1f ldr r2, [pc, #124] @ (8001a38 ) 80019bc: 8013 strh r3, [r2, #0] set_Feeder_PWM(motor_cmd.pwm,motor_cmd.dir); 80019be: 4b1d ldr r3, [pc, #116] @ (8001a34 ) 80019c0: 881a ldrh r2, [r3, #0] 80019c2: 4b1c ldr r3, [pc, #112] @ (8001a34 ) 80019c4: 789b ldrb r3, [r3, #2] 80019c6: 0019 movs r1, r3 80019c8: 0010 movs r0, r2 80019ca: f000 fde7 bl 800259c // Note: Feed completion is now handled by feed_state_machine_update() in main loop } if (htim == &htim1) return; // PWM timer 80019ce: 687a ldr r2, [r7, #4] 80019d0: 4b1a ldr r3, [pc, #104] @ (8001a3c ) 80019d2: 429a cmp r2, r3 80019d4: d00f beq.n 80019f6 else if (htim == &htim3) // encoder overflow { // will fire upon wraparound if update IT is enabled } if (htim == &htim16) //SW1 timer 80019d6: 687a ldr r2, [r7, #4] 80019d8: 4b19 ldr r3, [pc, #100] @ (8001a40 ) 80019da: 429a cmp r2, r3 80019dc: d103 bne.n 80019e6 { sw1_pressed = 0; 80019de: 4b19 ldr r3, [pc, #100] @ (8001a44 ) 80019e0: 2200 movs r2, #0 80019e2: 701a strb r2, [r3, #0] 80019e4: e008 b.n 80019f8 //todo handle overflow after ~65seconds (48MHz / 48000) * } else if (htim == &htim17) //SW2 timer 80019e6: 687a ldr r2, [r7, #4] 80019e8: 4b17 ldr r3, [pc, #92] @ (8001a48 ) 80019ea: 429a cmp r2, r3 80019ec: d104 bne.n 80019f8 { //todo sw2_pressed = 0; 80019ee: 4b17 ldr r3, [pc, #92] @ (8001a4c ) 80019f0: 2200 movs r2, #0 80019f2: 701a strb r2, [r3, #0] 80019f4: e000 b.n 80019f8 if (htim == &htim1) return; // PWM timer 80019f6: 46c0 nop @ (mov r8, r8) } } 80019f8: 46bd mov sp, r7 80019fa: b008 add sp, #32 80019fc: bd80 pop {r7, pc} 80019fe: 46c0 nop @ (mov r8, r8) 8001a00: 200000e4 .word 0x200000e4 8001a04: 20000098 .word 0x20000098 8001a08: 200003b0 .word 0x200003b0 8001a0c: 0000fc17 .word 0x0000fc17 8001a10: 200003ac .word 0x200003ac 8001a14: 20000484 .word 0x20000484 8001a18: 1fffffff .word 0x1fffffff 8001a1c: 20000488 .word 0x20000488 8001a20: 200004d0 .word 0x200004d0 8001a24: 0000ffff .word 0x0000ffff 8001a28: 20000550 .word 0x20000550 8001a2c: 200004b8 .word 0x200004b8 8001a30: 2000048c .word 0x2000048c 8001a34: 200004b4 .word 0x200004b4 8001a38: 200005a8 .word 0x200005a8 8001a3c: 2000004c .word 0x2000004c 8001a40: 20000130 .word 0x20000130 8001a44: 200003a8 .word 0x200003a8 8001a48: 2000017c .word 0x2000017c 8001a4c: 200003a9 .word 0x200003a9 08001a50 : void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) { 8001a50: b580 push {r7, lr} 8001a52: b082 sub sp, #8 8001a54: af00 add r7, sp, #0 8001a56: 0002 movs r2, r0 8001a58: 1dbb adds r3, r7, #6 8001a5a: 801a strh r2, [r3, #0] if(GPIO_Pin == SW1_Pin) // SW1 (lower button) 8001a5c: 1dbb adds r3, r7, #6 8001a5e: 881a ldrh r2, [r3, #0] 8001a60: 2380 movs r3, #128 @ 0x80 8001a62: 009b lsls r3, r3, #2 8001a64: 429a cmp r2, r3 8001a66: d10f bne.n 8001a88 { if (!sw1_pressed) 8001a68: 4b14 ldr r3, [pc, #80] @ (8001abc ) 8001a6a: 781b ldrb r3, [r3, #0] 8001a6c: 2b00 cmp r3, #0 8001a6e: d120 bne.n 8001ab2 { htim16.Instance->CNT = 0; 8001a70: 4b13 ldr r3, [pc, #76] @ (8001ac0 ) 8001a72: 681b ldr r3, [r3, #0] 8001a74: 2200 movs r2, #0 8001a76: 625a str r2, [r3, #36] @ 0x24 HAL_TIM_Base_Start_IT(&htim16); 8001a78: 4b11 ldr r3, [pc, #68] @ (8001ac0 ) 8001a7a: 0018 movs r0, r3 8001a7c: f003 fd68 bl 8005550 sw1_pressed = 1; 8001a80: 4b0e ldr r3, [pc, #56] @ (8001abc ) 8001a82: 2201 movs r2, #1 8001a84: 701a strb r2, [r3, #0] htim17.Instance->CNT = 0; HAL_TIM_Base_Start_IT(&htim17); sw2_pressed = 1; } } } 8001a86: e014 b.n 8001ab2 else if (GPIO_Pin == SW2_Pin) // SW2 (upper button) 8001a88: 1dbb adds r3, r7, #6 8001a8a: 881a ldrh r2, [r3, #0] 8001a8c: 2380 movs r3, #128 @ 0x80 8001a8e: 005b lsls r3, r3, #1 8001a90: 429a cmp r2, r3 8001a92: d10e bne.n 8001ab2 if (!sw2_pressed) 8001a94: 4b0b ldr r3, [pc, #44] @ (8001ac4 ) 8001a96: 781b ldrb r3, [r3, #0] 8001a98: 2b00 cmp r3, #0 8001a9a: d10a bne.n 8001ab2 htim17.Instance->CNT = 0; 8001a9c: 4b0a ldr r3, [pc, #40] @ (8001ac8 ) 8001a9e: 681b ldr r3, [r3, #0] 8001aa0: 2200 movs r2, #0 8001aa2: 625a str r2, [r3, #36] @ 0x24 HAL_TIM_Base_Start_IT(&htim17); 8001aa4: 4b08 ldr r3, [pc, #32] @ (8001ac8 ) 8001aa6: 0018 movs r0, r3 8001aa8: f003 fd52 bl 8005550 sw2_pressed = 1; 8001aac: 4b05 ldr r3, [pc, #20] @ (8001ac4 ) 8001aae: 2201 movs r2, #1 8001ab0: 701a strb r2, [r3, #0] } 8001ab2: 46c0 nop @ (mov r8, r8) 8001ab4: 46bd mov sp, r7 8001ab6: b002 add sp, #8 8001ab8: bd80 pop {r7, pc} 8001aba: 46c0 nop @ (mov r8, r8) 8001abc: 200003a8 .word 0x200003a8 8001ac0: 20000130 .word 0x20000130 8001ac4: 200003a9 .word 0x200003a9 8001ac8: 2000017c .word 0x2000017c 08001acc : void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) { 8001acc: b580 push {r7, lr} 8001ace: b082 sub sp, #8 8001ad0: af00 add r7, sp, #0 8001ad2: 6078 str r0, [r7, #4] 8001ad4: 000a movs r2, r1 8001ad6: 1cbb adds r3, r7, #2 8001ad8: 801a strh r2, [r3, #0] if (Size > 64) return; // todo error handling 8001ada: 1cbb adds r3, r7, #2 8001adc: 881b ldrh r3, [r3, #0] 8001ade: 2b40 cmp r3, #64 @ 0x40 8001ae0: d82d bhi.n 8001b3e if (msg_buffer1_empty) 8001ae2: 4b1a ldr r3, [pc, #104] @ (8001b4c ) 8001ae4: 781b ldrb r3, [r3, #0] 8001ae6: 2b00 cmp r3, #0 8001ae8: d00f beq.n 8001b0a { memcpy(msg_buffer1, DMA_buffer, Size); 8001aea: 1cbb adds r3, r7, #2 8001aec: 881a ldrh r2, [r3, #0] 8001aee: 4918 ldr r1, [pc, #96] @ (8001b50 ) 8001af0: 4b18 ldr r3, [pc, #96] @ (8001b54 ) 8001af2: 0018 movs r0, r3 8001af4: f006 f90a bl 8007d0c msg_buffer1_empty = 0; 8001af8: 4b14 ldr r3, [pc, #80] @ (8001b4c ) 8001afa: 2200 movs r2, #0 8001afc: 701a strb r2, [r3, #0] msg_buffer1_size = Size; 8001afe: 1cbb adds r3, r7, #2 8001b00: 881b ldrh r3, [r3, #0] 8001b02: b2da uxtb r2, r3 8001b04: 4b14 ldr r3, [pc, #80] @ (8001b58 ) 8001b06: 701a strb r2, [r3, #0] 8001b08: e012 b.n 8001b30 } else if (msg_buffer2_empty) 8001b0a: 4b14 ldr r3, [pc, #80] @ (8001b5c ) 8001b0c: 781b ldrb r3, [r3, #0] 8001b0e: 2b00 cmp r3, #0 8001b10: d017 beq.n 8001b42 { memcpy(msg_buffer2, DMA_buffer, Size); 8001b12: 1cbb adds r3, r7, #2 8001b14: 881a ldrh r2, [r3, #0] 8001b16: 490e ldr r1, [pc, #56] @ (8001b50 ) 8001b18: 4b11 ldr r3, [pc, #68] @ (8001b60 ) 8001b1a: 0018 movs r0, r3 8001b1c: f006 f8f6 bl 8007d0c msg_buffer2_empty = 0; 8001b20: 4b0e ldr r3, [pc, #56] @ (8001b5c ) 8001b22: 2200 movs r2, #0 8001b24: 701a strb r2, [r3, #0] msg_buffer2_size = Size; 8001b26: 1cbb adds r3, r7, #2 8001b28: 881b ldrh r3, [r3, #0] 8001b2a: b2da uxtb r2, r3 8001b2c: 4b0d ldr r3, [pc, #52] @ (8001b64 ) 8001b2e: 701a strb r2, [r3, #0] } else // no free buffer available todo error handling { return; } HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64); 8001b30: 4907 ldr r1, [pc, #28] @ (8001b50 ) 8001b32: 4b0d ldr r3, [pc, #52] @ (8001b68 ) 8001b34: 2240 movs r2, #64 @ 0x40 8001b36: 0018 movs r0, r3 8001b38: f005 ffe8 bl 8007b0c 8001b3c: e002 b.n 8001b44 if (Size > 64) return; // todo error handling 8001b3e: 46c0 nop @ (mov r8, r8) 8001b40: e000 b.n 8001b44 return; 8001b42: 46c0 nop @ (mov r8, r8) } 8001b44: 46bd mov sp, r7 8001b46: b002 add sp, #8 8001b48: bd80 pop {r7, pc} 8001b4a: 46c0 nop @ (mov r8, r8) 8001b4c: 20000000 .word 0x20000000 8001b50: 20000444 .word 0x20000444 8001b54: 200003c4 .word 0x200003c4 8001b58: 200003c1 .word 0x200003c1 8001b5c: 20000001 .word 0x20000001 8001b60: 20000404 .word 0x20000404 8001b64: 200003c2 .word 0x200003c2 8001b68: 2000025c .word 0x2000025c 08001b6c : void set_LED (uint8_t R, uint8_t G, uint8_t B) { 8001b6c: b590 push {r4, r7, lr} 8001b6e: b083 sub sp, #12 8001b70: af00 add r7, sp, #0 8001b72: 0004 movs r4, r0 8001b74: 0008 movs r0, r1 8001b76: 0011 movs r1, r2 8001b78: 1dfb adds r3, r7, #7 8001b7a: 1c22 adds r2, r4, #0 8001b7c: 701a strb r2, [r3, #0] 8001b7e: 1dbb adds r3, r7, #6 8001b80: 1c02 adds r2, r0, #0 8001b82: 701a strb r2, [r3, #0] 8001b84: 1d7b adds r3, r7, #5 8001b86: 1c0a adds r2, r1, #0 8001b88: 701a strb r2, [r3, #0] if (R) R = GPIO_PIN_SET; 8001b8a: 1dfb adds r3, r7, #7 8001b8c: 781b ldrb r3, [r3, #0] 8001b8e: 2b00 cmp r3, #0 8001b90: d002 beq.n 8001b98 8001b92: 1dfb adds r3, r7, #7 8001b94: 2201 movs r2, #1 8001b96: 701a strb r2, [r3, #0] if (G) G = GPIO_PIN_SET; 8001b98: 1dbb adds r3, r7, #6 8001b9a: 781b ldrb r3, [r3, #0] 8001b9c: 2b00 cmp r3, #0 8001b9e: d002 beq.n 8001ba6 8001ba0: 1dbb adds r3, r7, #6 8001ba2: 2201 movs r2, #1 8001ba4: 701a strb r2, [r3, #0] if (B) B = GPIO_PIN_SET; 8001ba6: 1d7b adds r3, r7, #5 8001ba8: 781b ldrb r3, [r3, #0] 8001baa: 2b00 cmp r3, #0 8001bac: d002 beq.n 8001bb4 8001bae: 1d7b adds r3, r7, #5 8001bb0: 2201 movs r2, #1 8001bb2: 701a strb r2, [r3, #0] HAL_GPIO_WritePin(LED_R_GPIO_Port,LED_R_Pin,R); 8001bb4: 1dfb adds r3, r7, #7 8001bb6: 781b ldrb r3, [r3, #0] 8001bb8: 480b ldr r0, [pc, #44] @ (8001be8 ) 8001bba: 001a movs r2, r3 8001bbc: 2108 movs r1, #8 8001bbe: f002 ff98 bl 8004af2 HAL_GPIO_WritePin(LED_G_GPIO_Port,LED_G_Pin,G); 8001bc2: 1dbb adds r3, r7, #6 8001bc4: 781b ldrb r3, [r3, #0] 8001bc6: 4808 ldr r0, [pc, #32] @ (8001be8 ) 8001bc8: 001a movs r2, r3 8001bca: 2120 movs r1, #32 8001bcc: f002 ff91 bl 8004af2 HAL_GPIO_WritePin(LED_B_GPIO_Port,LED_B_Pin,B); 8001bd0: 1d7b adds r3, r7, #5 8001bd2: 781b ldrb r3, [r3, #0] 8001bd4: 4804 ldr r0, [pc, #16] @ (8001be8 ) 8001bd6: 001a movs r2, r3 8001bd8: 2110 movs r1, #16 8001bda: f002 ff8a bl 8004af2 } 8001bde: 46c0 nop @ (mov r8, r8) 8001be0: 46bd mov sp, r7 8001be2: b003 add sp, #12 8001be4: bd90 pop {r4, r7, pc} 8001be6: 46c0 nop @ (mov r8, r8) 8001be8: 50000400 .word 0x50000400 08001bec : void comp_crc_header(CRC8_107 *lcrc, PhotonResponse *lresponse) { 8001bec: b580 push {r7, lr} 8001bee: b082 sub sp, #8 8001bf0: af00 add r7, sp, #0 8001bf2: 6078 str r0, [r7, #4] 8001bf4: 6039 str r1, [r7, #0] CRC8_107_add(lcrc,lresponse->header.toAddress); 8001bf6: 683b ldr r3, [r7, #0] 8001bf8: 781a ldrb r2, [r3, #0] 8001bfa: 687b ldr r3, [r7, #4] 8001bfc: 0011 movs r1, r2 8001bfe: 0018 movs r0, r3 8001c00: f7fe fd7e bl 8000700 CRC8_107_add(lcrc,lresponse->header.fromAddress); 8001c04: 683b ldr r3, [r7, #0] 8001c06: 785a ldrb r2, [r3, #1] 8001c08: 687b ldr r3, [r7, #4] 8001c0a: 0011 movs r1, r2 8001c0c: 0018 movs r0, r3 8001c0e: f7fe fd77 bl 8000700 CRC8_107_add(lcrc,lresponse->header.packetId); 8001c12: 683b ldr r3, [r7, #0] 8001c14: 789a ldrb r2, [r3, #2] 8001c16: 687b ldr r3, [r7, #4] 8001c18: 0011 movs r1, r2 8001c1a: 0018 movs r0, r3 8001c1c: f7fe fd70 bl 8000700 CRC8_107_add(lcrc,lresponse->header.payloadLength); 8001c20: 683b ldr r3, [r7, #0] 8001c22: 78da ldrb r2, [r3, #3] 8001c24: 687b ldr r3, [r7, #4] 8001c26: 0011 movs r1, r2 8001c28: 0018 movs r0, r3 8001c2a: f7fe fd69 bl 8000700 } 8001c2e: 46c0 nop @ (mov r8, r8) 8001c30: 46bd mov sp, r7 8001c32: b002 add sp, #8 8001c34: bd80 pop {r7, pc} ... 08001c38 : void handleRS485Message(uint8_t *buffer, uint8_t size) { 8001c38: b5f0 push {r4, r5, r6, r7, lr} 8001c3a: b09f sub sp, #124 @ 0x7c 8001c3c: af00 add r7, sp, #0 8001c3e: 6078 str r0, [r7, #4] 8001c40: 000a movs r2, r1 8001c42: 1cfb adds r3, r7, #3 8001c44: 701a strb r2, [r3, #0] PhotonPacketHeader *header = (PhotonPacketHeader *) buffer; 8001c46: 687b ldr r3, [r7, #4] 8001c48: 64bb str r3, [r7, #72] @ 0x48 // Validate minimum packet size if (size < sizeof(PhotonPacketHeader) + 1) // header + at least commandId 8001c4a: 1cfb adds r3, r7, #3 8001c4c: 781b ldrb r3, [r3, #0] 8001c4e: 2b05 cmp r3, #5 8001c50: d801 bhi.n 8001c56 8001c52: f000 fc87 bl 8002564 return; // packet too small } // Validate CRC CRC8_107 rx_crc; CRC8_107_init(&rx_crc); 8001c56: 242c movs r4, #44 @ 0x2c 8001c58: 193b adds r3, r7, r4 8001c5a: 0018 movs r0, r3 8001c5c: f7fe feb6 bl 80009cc CRC8_107_add(&rx_crc, header->toAddress); 8001c60: 6cbb ldr r3, [r7, #72] @ 0x48 8001c62: 781a ldrb r2, [r3, #0] 8001c64: 193b adds r3, r7, r4 8001c66: 0011 movs r1, r2 8001c68: 0018 movs r0, r3 8001c6a: f7fe fd49 bl 8000700 CRC8_107_add(&rx_crc, header->fromAddress); 8001c6e: 6cbb ldr r3, [r7, #72] @ 0x48 8001c70: 785a ldrb r2, [r3, #1] 8001c72: 193b adds r3, r7, r4 8001c74: 0011 movs r1, r2 8001c76: 0018 movs r0, r3 8001c78: f7fe fd42 bl 8000700 CRC8_107_add(&rx_crc, header->packetId); 8001c7c: 6cbb ldr r3, [r7, #72] @ 0x48 8001c7e: 789a ldrb r2, [r3, #2] 8001c80: 193b adds r3, r7, r4 8001c82: 0011 movs r1, r2 8001c84: 0018 movs r0, r3 8001c86: f7fe fd3b bl 8000700 CRC8_107_add(&rx_crc, header->payloadLength); 8001c8a: 6cbb ldr r3, [r7, #72] @ 0x48 8001c8c: 78da ldrb r2, [r3, #3] 8001c8e: 193b adds r3, r7, r4 8001c90: 0011 movs r1, r2 8001c92: 0018 movs r0, r3 8001c94: f7fe fd34 bl 8000700 // Add payload bytes to CRC (everything after header) for (uint8_t i = 0; i < header->payloadLength; i++) 8001c98: 2377 movs r3, #119 @ 0x77 8001c9a: 18fb adds r3, r7, r3 8001c9c: 2200 movs r2, #0 8001c9e: 701a strb r2, [r3, #0] 8001ca0: e011 b.n 8001cc6 { CRC8_107_add(&rx_crc, buffer[sizeof(PhotonPacketHeader) + i]); 8001ca2: 2477 movs r4, #119 @ 0x77 8001ca4: 193b adds r3, r7, r4 8001ca6: 781b ldrb r3, [r3, #0] 8001ca8: 3305 adds r3, #5 8001caa: 687a ldr r2, [r7, #4] 8001cac: 18d3 adds r3, r2, r3 8001cae: 781a ldrb r2, [r3, #0] 8001cb0: 232c movs r3, #44 @ 0x2c 8001cb2: 18fb adds r3, r7, r3 8001cb4: 0011 movs r1, r2 8001cb6: 0018 movs r0, r3 8001cb8: f7fe fd22 bl 8000700 for (uint8_t i = 0; i < header->payloadLength; i++) 8001cbc: 193b adds r3, r7, r4 8001cbe: 781a ldrb r2, [r3, #0] 8001cc0: 193b adds r3, r7, r4 8001cc2: 3201 adds r2, #1 8001cc4: 701a strb r2, [r3, #0] 8001cc6: 6cbb ldr r3, [r7, #72] @ 0x48 8001cc8: 78db ldrb r3, [r3, #3] 8001cca: 2277 movs r2, #119 @ 0x77 8001ccc: 18ba adds r2, r7, r2 8001cce: 7812 ldrb r2, [r2, #0] 8001cd0: 429a cmp r2, r3 8001cd2: d3e6 bcc.n 8001ca2 } if (CRC8_107_getChecksum(&rx_crc) != header->crc) 8001cd4: 232c movs r3, #44 @ 0x2c 8001cd6: 18fb adds r3, r7, r3 8001cd8: 0018 movs r0, r3 8001cda: f7fe fd41 bl 8000760 8001cde: 0003 movs r3, r0 8001ce0: 001a movs r2, r3 8001ce2: 6cbb ldr r3, [r7, #72] @ 0x48 8001ce4: 791b ldrb r3, [r3, #4] 8001ce6: 429a cmp r2, r3 8001ce8: d001 beq.n 8001cee 8001cea: f000 fc3d bl 8002568 { return; // CRC mismatch, discard packet } // check if message is for this device or is broadcast if ((header->toAddress != PHOTON_NETWORK_BROADCAST_ADDRESS) && 8001cee: 6cbb ldr r3, [r7, #72] @ 0x48 8001cf0: 781b ldrb r3, [r3, #0] 8001cf2: 2bff cmp r3, #255 @ 0xff 8001cf4: d007 beq.n 8001d06 (header->toAddress != my_address)) 8001cf6: 6cbb ldr r3, [r7, #72] @ 0x48 8001cf8: 781a ldrb r2, [r3, #0] 8001cfa: 4bde ldr r3, [pc, #888] @ (8002074 ) 8001cfc: 781b ldrb r3, [r3, #0] if ((header->toAddress != PHOTON_NETWORK_BROADCAST_ADDRESS) && 8001cfe: 429a cmp r2, r3 8001d00: d001 beq.n 8001d06 8001d02: f000 fc33 bl 800256c return; // message not for us } // this message is relevant to this device (unicast to us or broadcast) { PhotonCommand *command = (PhotonCommand *) buffer; 8001d06: 687b ldr r3, [r7, #4] 8001d08: 647b str r3, [r7, #68] @ 0x44 PhotonResponse response; CRC8_107 crc; CRC8_107_init(&crc); 8001d0a: 230c movs r3, #12 8001d0c: 18fb adds r3, r7, r3 8001d0e: 0018 movs r0, r3 8001d10: f7fe fe5c bl 80009cc response.header.fromAddress = my_address; 8001d14: 4bd7 ldr r3, [pc, #860] @ (8002074 ) 8001d16: 781a ldrb r2, [r3, #0] 8001d18: 2110 movs r1, #16 8001d1a: 187b adds r3, r7, r1 8001d1c: 705a strb r2, [r3, #1] response.header.packetId = command->header.packetId; 8001d1e: 6c7b ldr r3, [r7, #68] @ 0x44 8001d20: 789a ldrb r2, [r3, #2] 8001d22: 187b adds r3, r7, r1 8001d24: 709a strb r2, [r3, #2] response.header.toAddress = command->header.fromAddress; 8001d26: 6c7b ldr r3, [r7, #68] @ 0x44 8001d28: 785a ldrb r2, [r3, #1] 8001d2a: 187b adds r3, r7, r1 8001d2c: 701a strb r2, [r3, #0] uint8_t *payload_ptr; size_t packet_len; switch (command->commandId) 8001d2e: 6c7b ldr r3, [r7, #68] @ 0x44 8001d30: 795b ldrb r3, [r3, #5] 8001d32: 2b06 cmp r3, #6 8001d34: dc16 bgt.n 8001d64 8001d36: 2b00 cmp r3, #0 8001d38: dc0b bgt.n 8001d52 packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100); break; default: // todo error handling return; 8001d3a: f000 fc19 bl 8002570 switch (command->commandId) 8001d3e: 3bbf subs r3, #191 @ 0xbf 8001d40: 2b04 cmp r3, #4 8001d42: d901 bls.n 8001d48 8001d44: f000 fc14 bl 8002570 8001d48: 009a lsls r2, r3, #2 8001d4a: 4bcb ldr r3, [pc, #812] @ (8002078 ) 8001d4c: 18d3 adds r3, r2, r3 8001d4e: 681b ldr r3, [r3, #0] 8001d50: 469f mov pc, r3 8001d52: 2b06 cmp r3, #6 8001d54: d901 bls.n 8001d5a 8001d56: f000 fc0b bl 8002570 8001d5a: 009a lsls r2, r3, #2 8001d5c: 4bc7 ldr r3, [pc, #796] @ (800207c ) 8001d5e: 18d3 adds r3, r2, r3 8001d60: 681b ldr r3, [r3, #0] 8001d62: 469f mov pc, r3 8001d64: 2bc3 cmp r3, #195 @ 0xc3 8001d66: dd01 ble.n 8001d6c 8001d68: f000 fc02 bl 8002570 8001d6c: 2bbf cmp r3, #191 @ 0xbf 8001d6e: dae6 bge.n 8001d3e return; 8001d70: f000 fbfe bl 8002570 memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH); 8001d74: 2410 movs r4, #16 8001d76: 193b adds r3, r7, r4 8001d78: 2206 movs r2, #6 8001d7a: 49c1 ldr r1, [pc, #772] @ (8002080 ) 8001d7c: 189b adds r3, r3, r2 8001d7e: 220c movs r2, #12 8001d80: 0018 movs r0, r3 8001d82: f005 ffc3 bl 8007d0c response.status = STATUS_OK; 8001d86: 193b adds r3, r7, r4 8001d88: 2200 movs r2, #0 8001d8a: 715a strb r2, [r3, #5] comp_crc_header(&crc,&response); 8001d8c: 193a adds r2, r7, r4 8001d8e: 230c movs r3, #12 8001d90: 18fb adds r3, r7, r3 8001d92: 0011 movs r1, r2 8001d94: 0018 movs r0, r3 8001d96: f7ff ff29 bl 8001bec payload_ptr =(uint8_t*) &response.payload; 8001d9a: 193b adds r3, r7, r4 8001d9c: 3306 adds r3, #6 8001d9e: 643b str r3, [r7, #64] @ 0x40 for (uint32_t i = 0; i CRC8_107_add(&crc,*(payload_ptr+i)); 8001da6: 6c3a ldr r2, [r7, #64] @ 0x40 8001da8: 6f3b ldr r3, [r7, #112] @ 0x70 8001daa: 18d3 adds r3, r2, r3 8001dac: 781a ldrb r2, [r3, #0] 8001dae: 230c movs r3, #12 8001db0: 18fb adds r3, r7, r3 8001db2: 0011 movs r1, r2 8001db4: 0018 movs r0, r3 8001db6: f7fe fca3 bl 8000700 for (uint32_t i = 0; i response.header.crc = CRC8_107_getChecksum(&crc); 8001dc6: 230c movs r3, #12 8001dc8: 18fb adds r3, r7, r3 8001dca: 0018 movs r0, r3 8001dcc: f7fe fcc8 bl 8000760 8001dd0: 0003 movs r3, r0 8001dd2: 001a movs r2, r3 8001dd4: 2110 movs r1, #16 8001dd6: 187b adds r3, r7, r1 8001dd8: 711a strb r2, [r3, #4] response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for the length byte 8001dda: 187b adds r3, r7, r1 8001ddc: 220d movs r2, #13 8001dde: 70da strb r2, [r3, #3] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 8001de0: 187b adds r3, r7, r1 8001de2: 78db ldrb r3, [r3, #3] 8001de4: 3305 adds r3, #5 8001de6: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100); 8001de8: 6bfb ldr r3, [r7, #60] @ 0x3c 8001dea: b29a uxth r2, r3 8001dec: 1879 adds r1, r7, r1 8001dee: 48a5 ldr r0, [pc, #660] @ (8002084 ) 8001df0: 2364 movs r3, #100 @ 0x64 8001df2: f004 fed3 bl 8006b9c break; 8001df6: f000 fbc2 bl 800257e memcpy(response.payload.initializeFeeder.uuid,UUID,UUID_LENGTH); 8001dfa: 2410 movs r4, #16 8001dfc: 193b adds r3, r7, r4 8001dfe: 2206 movs r2, #6 8001e00: 499f ldr r1, [pc, #636] @ (8002080 ) 8001e02: 189b adds r3, r3, r2 8001e04: 220c movs r2, #12 8001e06: 0018 movs r0, r3 8001e08: f005 ff80 bl 8007d0c if(memcmp(UUID,command->payload.initializeFeeder.uuid,UUID_LENGTH) == 0) 8001e0c: 6c7b ldr r3, [r7, #68] @ 0x44 8001e0e: 1d99 adds r1, r3, #6 8001e10: 4b9b ldr r3, [pc, #620] @ (8002080 ) 8001e12: 220c movs r2, #12 8001e14: 0018 movs r0, r3 8001e16: f005 ff3f bl 8007c98 8001e1a: 1e03 subs r3, r0, #0 8001e1c: d106 bne.n 8001e2c is_initialized = 1; 8001e1e: 4b9a ldr r3, [pc, #616] @ (8002088 ) 8001e20: 2201 movs r2, #1 8001e22: 701a strb r2, [r3, #0] response.status = STATUS_OK; 8001e24: 193b adds r3, r7, r4 8001e26: 2200 movs r2, #0 8001e28: 715a strb r2, [r3, #5] 8001e2a: e003 b.n 8001e34 response.status = STATUS_WRONG_FEEDER_ID; 8001e2c: 2310 movs r3, #16 8001e2e: 18fb adds r3, r7, r3 8001e30: 2201 movs r2, #1 8001e32: 715a strb r2, [r3, #5] comp_crc_header(&crc,&response); 8001e34: 2410 movs r4, #16 8001e36: 193a adds r2, r7, r4 8001e38: 230c movs r3, #12 8001e3a: 18fb adds r3, r7, r3 8001e3c: 0011 movs r1, r2 8001e3e: 0018 movs r0, r3 8001e40: f7ff fed4 bl 8001bec payload_ptr =(uint8_t*) &response.payload; 8001e44: 193b adds r3, r7, r4 8001e46: 3306 adds r3, #6 8001e48: 643b str r3, [r7, #64] @ 0x40 for (uint32_t i = 0; i CRC8_107_add(&crc,*(payload_ptr+i)); 8001e50: 6c3a ldr r2, [r7, #64] @ 0x40 8001e52: 6efb ldr r3, [r7, #108] @ 0x6c 8001e54: 18d3 adds r3, r2, r3 8001e56: 781a ldrb r2, [r3, #0] 8001e58: 230c movs r3, #12 8001e5a: 18fb adds r3, r7, r3 8001e5c: 0011 movs r1, r2 8001e5e: 0018 movs r0, r3 8001e60: f7fe fc4e bl 8000700 for (uint32_t i = 0; i response.header.crc = CRC8_107_getChecksum(&crc); 8001e70: 230c movs r3, #12 8001e72: 18fb adds r3, r7, r3 8001e74: 0018 movs r0, r3 8001e76: f7fe fc73 bl 8000760 8001e7a: 0003 movs r3, r0 8001e7c: 001a movs r2, r3 8001e7e: 2110 movs r1, #16 8001e80: 187b adds r3, r7, r1 8001e82: 711a strb r2, [r3, #4] response.header.payloadLength = sizeof(response.payload.initializeFeeder)+1; // +1 for the length byte 8001e84: 187b adds r3, r7, r1 8001e86: 220d movs r2, #13 8001e88: 70da strb r2, [r3, #3] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 8001e8a: 187b adds r3, r7, r1 8001e8c: 78db ldrb r3, [r3, #3] 8001e8e: 3305 adds r3, #5 8001e90: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100); 8001e92: 6bfb ldr r3, [r7, #60] @ 0x3c 8001e94: b29a uxth r2, r3 8001e96: 1879 adds r1, r7, r1 8001e98: 487a ldr r0, [pc, #488] @ (8002084 ) 8001e9a: 2364 movs r3, #100 @ 0x64 8001e9c: f004 fe7e bl 8006b9c break; 8001ea0: e36d b.n 800257e response.status = STATUS_OK; 8001ea2: 2410 movs r4, #16 8001ea4: 193b adds r3, r7, r4 8001ea6: 2200 movs r2, #0 8001ea8: 715a strb r2, [r3, #5] response.payload.protocolVersion.version = PROTOCOL_VERSION; 8001eaa: 193b adds r3, r7, r4 8001eac: 2201 movs r2, #1 8001eae: 719a strb r2, [r3, #6] comp_crc_header(&crc,&response); 8001eb0: 193a adds r2, r7, r4 8001eb2: 230c movs r3, #12 8001eb4: 18fb adds r3, r7, r3 8001eb6: 0011 movs r1, r2 8001eb8: 0018 movs r0, r3 8001eba: f7ff fe97 bl 8001bec payload_ptr =(uint8_t*) &response.payload; 8001ebe: 193b adds r3, r7, r4 8001ec0: 3306 adds r3, #6 8001ec2: 643b str r3, [r7, #64] @ 0x40 for (uint32_t i = 0; i CRC8_107_add(&crc,*(payload_ptr+i)); 8001eca: 6c3a ldr r2, [r7, #64] @ 0x40 8001ecc: 6ebb ldr r3, [r7, #104] @ 0x68 8001ece: 18d3 adds r3, r2, r3 8001ed0: 781a ldrb r2, [r3, #0] 8001ed2: 230c movs r3, #12 8001ed4: 18fb adds r3, r7, r3 8001ed6: 0011 movs r1, r2 8001ed8: 0018 movs r0, r3 8001eda: f7fe fc11 bl 8000700 for (uint32_t i = 0; i response.header.crc = CRC8_107_getChecksum(&crc); 8001eea: 230c movs r3, #12 8001eec: 18fb adds r3, r7, r3 8001eee: 0018 movs r0, r3 8001ef0: f7fe fc36 bl 8000760 8001ef4: 0003 movs r3, r0 8001ef6: 001a movs r2, r3 8001ef8: 2110 movs r1, #16 8001efa: 187b adds r3, r7, r1 8001efc: 711a strb r2, [r3, #4] response.header.payloadLength = sizeof(response.payload.protocolVersion)+1; // +1 for the length byte 8001efe: 187b adds r3, r7, r1 8001f00: 2202 movs r2, #2 8001f02: 70da strb r2, [r3, #3] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 8001f04: 187b adds r3, r7, r1 8001f06: 78db ldrb r3, [r3, #3] 8001f08: 3305 adds r3, #5 8001f0a: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100); 8001f0c: 6bfb ldr r3, [r7, #60] @ 0x3c 8001f0e: b29a uxth r2, r3 8001f10: 1879 adds r1, r7, r1 8001f12: 485c ldr r0, [pc, #368] @ (8002084 ) 8001f14: 2364 movs r3, #100 @ 0x64 8001f16: f004 fe41 bl 8006b9c break; 8001f1a: e330 b.n 800257e if (!is_initialized) 8001f1c: 4b5a ldr r3, [pc, #360] @ (8002088 ) 8001f1e: 781b ldrb r3, [r3, #0] 8001f20: 2b00 cmp r3, #0 8001f22: d144 bne.n 8001fae response.status = STATUS_UNINITIALIZED_FEEDER; 8001f24: 2410 movs r4, #16 8001f26: 193b adds r3, r7, r4 8001f28: 2203 movs r2, #3 8001f2a: 715a strb r2, [r3, #5] memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH); 8001f2c: 193b adds r3, r7, r4 8001f2e: 2206 movs r2, #6 8001f30: 4953 ldr r1, [pc, #332] @ (8002080 ) 8001f32: 189b adds r3, r3, r2 8001f34: 220c movs r2, #12 8001f36: 0018 movs r0, r3 8001f38: f005 fee8 bl 8007d0c response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1; 8001f3c: 193b adds r3, r7, r4 8001f3e: 220d movs r2, #13 8001f40: 70da strb r2, [r3, #3] comp_crc_header(&crc, &response); 8001f42: 193a adds r2, r7, r4 8001f44: 230c movs r3, #12 8001f46: 18fb adds r3, r7, r3 8001f48: 0011 movs r1, r2 8001f4a: 0018 movs r0, r3 8001f4c: f7ff fe4e bl 8001bec payload_ptr = (uint8_t*)&response.status; 8001f50: 193b adds r3, r7, r4 8001f52: 3305 adds r3, #5 8001f54: 643b str r3, [r7, #64] @ 0x40 for (uint32_t i = 0; i < response.header.payloadLength; i++) 8001f56: 2300 movs r3, #0 8001f58: 667b str r3, [r7, #100] @ 0x64 8001f5a: e00c b.n 8001f76 CRC8_107_add(&crc, *(payload_ptr + i)); 8001f5c: 6c3a ldr r2, [r7, #64] @ 0x40 8001f5e: 6e7b ldr r3, [r7, #100] @ 0x64 8001f60: 18d3 adds r3, r2, r3 8001f62: 781a ldrb r2, [r3, #0] 8001f64: 230c movs r3, #12 8001f66: 18fb adds r3, r7, r3 8001f68: 0011 movs r1, r2 8001f6a: 0018 movs r0, r3 8001f6c: f7fe fbc8 bl 8000700 for (uint32_t i = 0; i < response.header.payloadLength; i++) 8001f70: 6e7b ldr r3, [r7, #100] @ 0x64 8001f72: 3301 adds r3, #1 8001f74: 667b str r3, [r7, #100] @ 0x64 8001f76: 2410 movs r4, #16 8001f78: 193b adds r3, r7, r4 8001f7a: 78db ldrb r3, [r3, #3] 8001f7c: 001a movs r2, r3 8001f7e: 6e7b ldr r3, [r7, #100] @ 0x64 8001f80: 4293 cmp r3, r2 8001f82: d3eb bcc.n 8001f5c response.header.crc = CRC8_107_getChecksum(&crc); 8001f84: 230c movs r3, #12 8001f86: 18fb adds r3, r7, r3 8001f88: 0018 movs r0, r3 8001f8a: f7fe fbe9 bl 8000760 8001f8e: 0003 movs r3, r0 8001f90: 001a movs r2, r3 8001f92: 193b adds r3, r7, r4 8001f94: 711a strb r2, [r3, #4] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 8001f96: 193b adds r3, r7, r4 8001f98: 78db ldrb r3, [r3, #3] 8001f9a: 3305 adds r3, #5 8001f9c: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100); 8001f9e: 6bfb ldr r3, [r7, #60] @ 0x3c 8001fa0: b29a uxth r2, r3 8001fa2: 1939 adds r1, r7, r4 8001fa4: 4837 ldr r0, [pc, #220] @ (8002084 ) 8001fa6: 2364 movs r3, #100 @ 0x64 8001fa8: f004 fdf8 bl 8006b9c break; 8001fac: e2e7 b.n 800257e uint16_t exp_time = calculate_expected_feed_time(command->payload.move.distance, 1); 8001fae: 6c7b ldr r3, [r7, #68] @ 0x44 8001fb0: 799b ldrb r3, [r3, #6] 8001fb2: 2534 movs r5, #52 @ 0x34 8001fb4: 197c adds r4, r7, r5 8001fb6: 2101 movs r1, #1 8001fb8: 0018 movs r0, r3 8001fba: f000 fcb1 bl 8002920 8001fbe: 0003 movs r3, r0 8001fc0: 8023 strh r3, [r4, #0] uint16_t exp_time_be = (exp_time >> 8) | (exp_time << 8); // byte swap for network order 8001fc2: 0029 movs r1, r5 8001fc4: 187b adds r3, r7, r1 8001fc6: 881b ldrh r3, [r3, #0] 8001fc8: 0a1b lsrs r3, r3, #8 8001fca: b29b uxth r3, r3 8001fcc: b21a sxth r2, r3 8001fce: 187b adds r3, r7, r1 8001fd0: 2100 movs r1, #0 8001fd2: 5e5b ldrsh r3, [r3, r1] 8001fd4: 021b lsls r3, r3, #8 8001fd6: b21b sxth r3, r3 8001fd8: 4313 orrs r3, r2 8001fda: b21a sxth r2, r3 8001fdc: 2032 movs r0, #50 @ 0x32 8001fde: 183b adds r3, r7, r0 8001fe0: 801a strh r2, [r3, #0] response.status = STATUS_OK; 8001fe2: 2110 movs r1, #16 8001fe4: 187b adds r3, r7, r1 8001fe6: 2200 movs r2, #0 8001fe8: 715a strb r2, [r3, #5] response.payload.expectedTimeToFeed.expectedFeedTime = exp_time_be; 8001fea: 187b adds r3, r7, r1 8001fec: 183a adds r2, r7, r0 8001fee: 8812 ldrh r2, [r2, #0] 8001ff0: 80da strh r2, [r3, #6] response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1; 8001ff2: 187b adds r3, r7, r1 8001ff4: 2203 movs r2, #3 8001ff6: 70da strb r2, [r3, #3] comp_crc_header(&crc, &response); 8001ff8: 000c movs r4, r1 8001ffa: 187a adds r2, r7, r1 8001ffc: 230c movs r3, #12 8001ffe: 18fb adds r3, r7, r3 8002000: 0011 movs r1, r2 8002002: 0018 movs r0, r3 8002004: f7ff fdf2 bl 8001bec payload_ptr = (uint8_t*)&response.status; 8002008: 193b adds r3, r7, r4 800200a: 3305 adds r3, #5 800200c: 643b str r3, [r7, #64] @ 0x40 for (uint32_t i = 0; i < response.header.payloadLength; i++) 800200e: 2300 movs r3, #0 8002010: 663b str r3, [r7, #96] @ 0x60 8002012: e00c b.n 800202e CRC8_107_add(&crc, *(payload_ptr + i)); 8002014: 6c3a ldr r2, [r7, #64] @ 0x40 8002016: 6e3b ldr r3, [r7, #96] @ 0x60 8002018: 18d3 adds r3, r2, r3 800201a: 781a ldrb r2, [r3, #0] 800201c: 230c movs r3, #12 800201e: 18fb adds r3, r7, r3 8002020: 0011 movs r1, r2 8002022: 0018 movs r0, r3 8002024: f7fe fb6c bl 8000700 for (uint32_t i = 0; i < response.header.payloadLength; i++) 8002028: 6e3b ldr r3, [r7, #96] @ 0x60 800202a: 3301 adds r3, #1 800202c: 663b str r3, [r7, #96] @ 0x60 800202e: 2410 movs r4, #16 8002030: 193b adds r3, r7, r4 8002032: 78db ldrb r3, [r3, #3] 8002034: 001a movs r2, r3 8002036: 6e3b ldr r3, [r7, #96] @ 0x60 8002038: 4293 cmp r3, r2 800203a: d3eb bcc.n 8002014 response.header.crc = CRC8_107_getChecksum(&crc); 800203c: 230c movs r3, #12 800203e: 18fb adds r3, r7, r3 8002040: 0018 movs r0, r3 8002042: f7fe fb8d bl 8000760 8002046: 0003 movs r3, r0 8002048: 001a movs r2, r3 800204a: 193b adds r3, r7, r4 800204c: 711a strb r2, [r3, #4] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 800204e: 193b adds r3, r7, r4 8002050: 78db ldrb r3, [r3, #3] 8002052: 3305 adds r3, #5 8002054: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100); 8002056: 6bfb ldr r3, [r7, #60] @ 0x3c 8002058: b29a uxth r2, r3 800205a: 1939 adds r1, r7, r4 800205c: 4809 ldr r0, [pc, #36] @ (8002084 ) 800205e: 2364 movs r3, #100 @ 0x64 8002060: f004 fd9c bl 8006b9c start_feed(command->payload.move.distance, 1); 8002064: 6c7b ldr r3, [r7, #68] @ 0x44 8002066: 799b ldrb r3, [r3, #6] 8002068: b21b sxth r3, r3 800206a: 2101 movs r1, #1 800206c: 0018 movs r0, r3 800206e: f000 fc9f bl 80029b0 break; 8002072: e284 b.n 800257e 8002074: 20000002 .word 0x20000002 8002078: 08007d58 .word 0x08007d58 800207c: 08007d6c .word 0x08007d6c 8002080: 200003b4 .word 0x200003b4 8002084: 2000025c .word 0x2000025c 8002088: 200003c0 .word 0x200003c0 if (!is_initialized) 800208c: 4be9 ldr r3, [pc, #932] @ (8002434 ) 800208e: 781b ldrb r3, [r3, #0] 8002090: 2b00 cmp r3, #0 8002092: d144 bne.n 800211e response.status = STATUS_UNINITIALIZED_FEEDER; 8002094: 2410 movs r4, #16 8002096: 193b adds r3, r7, r4 8002098: 2203 movs r2, #3 800209a: 715a strb r2, [r3, #5] memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH); 800209c: 193b adds r3, r7, r4 800209e: 2206 movs r2, #6 80020a0: 49e5 ldr r1, [pc, #916] @ (8002438 ) 80020a2: 189b adds r3, r3, r2 80020a4: 220c movs r2, #12 80020a6: 0018 movs r0, r3 80020a8: f005 fe30 bl 8007d0c response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1; 80020ac: 193b adds r3, r7, r4 80020ae: 220d movs r2, #13 80020b0: 70da strb r2, [r3, #3] comp_crc_header(&crc, &response); 80020b2: 193a adds r2, r7, r4 80020b4: 230c movs r3, #12 80020b6: 18fb adds r3, r7, r3 80020b8: 0011 movs r1, r2 80020ba: 0018 movs r0, r3 80020bc: f7ff fd96 bl 8001bec payload_ptr = (uint8_t*)&response.status; 80020c0: 193b adds r3, r7, r4 80020c2: 3305 adds r3, #5 80020c4: 643b str r3, [r7, #64] @ 0x40 for (uint32_t i = 0; i < response.header.payloadLength; i++) 80020c6: 2300 movs r3, #0 80020c8: 65fb str r3, [r7, #92] @ 0x5c 80020ca: e00c b.n 80020e6 CRC8_107_add(&crc, *(payload_ptr + i)); 80020cc: 6c3a ldr r2, [r7, #64] @ 0x40 80020ce: 6dfb ldr r3, [r7, #92] @ 0x5c 80020d0: 18d3 adds r3, r2, r3 80020d2: 781a ldrb r2, [r3, #0] 80020d4: 230c movs r3, #12 80020d6: 18fb adds r3, r7, r3 80020d8: 0011 movs r1, r2 80020da: 0018 movs r0, r3 80020dc: f7fe fb10 bl 8000700 for (uint32_t i = 0; i < response.header.payloadLength; i++) 80020e0: 6dfb ldr r3, [r7, #92] @ 0x5c 80020e2: 3301 adds r3, #1 80020e4: 65fb str r3, [r7, #92] @ 0x5c 80020e6: 2410 movs r4, #16 80020e8: 193b adds r3, r7, r4 80020ea: 78db ldrb r3, [r3, #3] 80020ec: 001a movs r2, r3 80020ee: 6dfb ldr r3, [r7, #92] @ 0x5c 80020f0: 4293 cmp r3, r2 80020f2: d3eb bcc.n 80020cc response.header.crc = CRC8_107_getChecksum(&crc); 80020f4: 230c movs r3, #12 80020f6: 18fb adds r3, r7, r3 80020f8: 0018 movs r0, r3 80020fa: f7fe fb31 bl 8000760 80020fe: 0003 movs r3, r0 8002100: 001a movs r2, r3 8002102: 193b adds r3, r7, r4 8002104: 711a strb r2, [r3, #4] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 8002106: 193b adds r3, r7, r4 8002108: 78db ldrb r3, [r3, #3] 800210a: 3305 adds r3, #5 800210c: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100); 800210e: 6bfb ldr r3, [r7, #60] @ 0x3c 8002110: b29a uxth r2, r3 8002112: 1939 adds r1, r7, r4 8002114: 48c9 ldr r0, [pc, #804] @ (800243c ) 8002116: 2364 movs r3, #100 @ 0x64 8002118: f004 fd40 bl 8006b9c break; 800211c: e22f b.n 800257e uint16_t exp_time = calculate_expected_feed_time(command->payload.move.distance, 0); 800211e: 6c7b ldr r3, [r7, #68] @ 0x44 8002120: 799b ldrb r3, [r3, #6] 8002122: 2538 movs r5, #56 @ 0x38 8002124: 197c adds r4, r7, r5 8002126: 2100 movs r1, #0 8002128: 0018 movs r0, r3 800212a: f000 fbf9 bl 8002920 800212e: 0003 movs r3, r0 8002130: 8023 strh r3, [r4, #0] uint16_t exp_time_be = (exp_time >> 8) | (exp_time << 8); // byte swap for network order 8002132: 0029 movs r1, r5 8002134: 187b adds r3, r7, r1 8002136: 881b ldrh r3, [r3, #0] 8002138: 0a1b lsrs r3, r3, #8 800213a: b29b uxth r3, r3 800213c: b21a sxth r2, r3 800213e: 187b adds r3, r7, r1 8002140: 2100 movs r1, #0 8002142: 5e5b ldrsh r3, [r3, r1] 8002144: 021b lsls r3, r3, #8 8002146: b21b sxth r3, r3 8002148: 4313 orrs r3, r2 800214a: b21a sxth r2, r3 800214c: 2036 movs r0, #54 @ 0x36 800214e: 183b adds r3, r7, r0 8002150: 801a strh r2, [r3, #0] response.status = STATUS_OK; 8002152: 2110 movs r1, #16 8002154: 187b adds r3, r7, r1 8002156: 2200 movs r2, #0 8002158: 715a strb r2, [r3, #5] response.payload.expectedTimeToFeed.expectedFeedTime = exp_time_be; 800215a: 187b adds r3, r7, r1 800215c: 183a adds r2, r7, r0 800215e: 8812 ldrh r2, [r2, #0] 8002160: 80da strh r2, [r3, #6] response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1; 8002162: 187b adds r3, r7, r1 8002164: 2203 movs r2, #3 8002166: 70da strb r2, [r3, #3] comp_crc_header(&crc, &response); 8002168: 000c movs r4, r1 800216a: 187a adds r2, r7, r1 800216c: 230c movs r3, #12 800216e: 18fb adds r3, r7, r3 8002170: 0011 movs r1, r2 8002172: 0018 movs r0, r3 8002174: f7ff fd3a bl 8001bec payload_ptr = (uint8_t*)&response.status; 8002178: 193b adds r3, r7, r4 800217a: 3305 adds r3, #5 800217c: 643b str r3, [r7, #64] @ 0x40 for (uint32_t i = 0; i < response.header.payloadLength; i++) 800217e: 2300 movs r3, #0 8002180: 65bb str r3, [r7, #88] @ 0x58 8002182: e00c b.n 800219e CRC8_107_add(&crc, *(payload_ptr + i)); 8002184: 6c3a ldr r2, [r7, #64] @ 0x40 8002186: 6dbb ldr r3, [r7, #88] @ 0x58 8002188: 18d3 adds r3, r2, r3 800218a: 781a ldrb r2, [r3, #0] 800218c: 230c movs r3, #12 800218e: 18fb adds r3, r7, r3 8002190: 0011 movs r1, r2 8002192: 0018 movs r0, r3 8002194: f7fe fab4 bl 8000700 for (uint32_t i = 0; i < response.header.payloadLength; i++) 8002198: 6dbb ldr r3, [r7, #88] @ 0x58 800219a: 3301 adds r3, #1 800219c: 65bb str r3, [r7, #88] @ 0x58 800219e: 2410 movs r4, #16 80021a0: 193b adds r3, r7, r4 80021a2: 78db ldrb r3, [r3, #3] 80021a4: 001a movs r2, r3 80021a6: 6dbb ldr r3, [r7, #88] @ 0x58 80021a8: 4293 cmp r3, r2 80021aa: d3eb bcc.n 8002184 response.header.crc = CRC8_107_getChecksum(&crc); 80021ac: 230c movs r3, #12 80021ae: 18fb adds r3, r7, r3 80021b0: 0018 movs r0, r3 80021b2: f7fe fad5 bl 8000760 80021b6: 0003 movs r3, r0 80021b8: 001a movs r2, r3 80021ba: 193b adds r3, r7, r4 80021bc: 711a strb r2, [r3, #4] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 80021be: 193b adds r3, r7, r4 80021c0: 78db ldrb r3, [r3, #3] 80021c2: 3305 adds r3, #5 80021c4: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100); 80021c6: 6bfb ldr r3, [r7, #60] @ 0x3c 80021c8: b29a uxth r2, r3 80021ca: 1939 adds r1, r7, r4 80021cc: 489b ldr r0, [pc, #620] @ (800243c ) 80021ce: 2364 movs r3, #100 @ 0x64 80021d0: f004 fce4 bl 8006b9c start_feed(command->payload.move.distance, 0); 80021d4: 6c7b ldr r3, [r7, #68] @ 0x44 80021d6: 799b ldrb r3, [r3, #6] 80021d8: b21b sxth r3, r3 80021da: 2100 movs r1, #0 80021dc: 0018 movs r0, r3 80021de: f000 fbe7 bl 80029b0 break; 80021e2: e1cc b.n 800257e if (feed_in_progress) 80021e4: 4b96 ldr r3, [pc, #600] @ (8002440 ) 80021e6: 781b ldrb r3, [r3, #0] 80021e8: b2db uxtb r3, r3 80021ea: 2b00 cmp r3, #0 80021ec: d004 beq.n 80021f8 response.status = STATUS_FEEDING_IN_PROGRESS; 80021ee: 2310 movs r3, #16 80021f0: 18fb adds r3, r7, r3 80021f2: 2204 movs r2, #4 80021f4: 715a strb r2, [r3, #5] 80021f6: e004 b.n 8002202 response.status = last_feed_status; 80021f8: 4b92 ldr r3, [pc, #584] @ (8002444 ) 80021fa: 781a ldrb r2, [r3, #0] 80021fc: 2310 movs r3, #16 80021fe: 18fb adds r3, r7, r3 8002200: 715a strb r2, [r3, #5] response.header.payloadLength = 1; // only status byte 8002202: 2410 movs r4, #16 8002204: 193b adds r3, r7, r4 8002206: 2201 movs r2, #1 8002208: 70da strb r2, [r3, #3] comp_crc_header(&crc,&response); 800220a: 193a adds r2, r7, r4 800220c: 250c movs r5, #12 800220e: 197b adds r3, r7, r5 8002210: 0011 movs r1, r2 8002212: 0018 movs r0, r3 8002214: f7ff fcea bl 8001bec CRC8_107_add(&crc, response.status); 8002218: 193b adds r3, r7, r4 800221a: 795a ldrb r2, [r3, #5] 800221c: 197b adds r3, r7, r5 800221e: 0011 movs r1, r2 8002220: 0018 movs r0, r3 8002222: f7fe fa6d bl 8000700 response.header.crc = CRC8_107_getChecksum(&crc); 8002226: 197b adds r3, r7, r5 8002228: 0018 movs r0, r3 800222a: f7fe fa99 bl 8000760 800222e: 0003 movs r3, r0 8002230: 001a movs r2, r3 8002232: 193b adds r3, r7, r4 8002234: 711a strb r2, [r3, #4] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 8002236: 193b adds r3, r7, r4 8002238: 78db ldrb r3, [r3, #3] 800223a: 3305 adds r3, #5 800223c: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100); 800223e: 6bfb ldr r3, [r7, #60] @ 0x3c 8002240: b29a uxth r2, r3 8002242: 1939 adds r1, r7, r4 8002244: 487d ldr r0, [pc, #500] @ (800243c ) 8002246: 2364 movs r3, #100 @ 0x64 8002248: f004 fca8 bl 8006b9c break; 800224c: e197 b.n 800257e if (!is_initialized) 800224e: 4b79 ldr r3, [pc, #484] @ (8002434 ) 8002250: 781b ldrb r3, [r3, #0] 8002252: 2b00 cmp r3, #0 8002254: d144 bne.n 80022e0 response.status = STATUS_UNINITIALIZED_FEEDER; 8002256: 2410 movs r4, #16 8002258: 193b adds r3, r7, r4 800225a: 2203 movs r2, #3 800225c: 715a strb r2, [r3, #5] memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH); 800225e: 193b adds r3, r7, r4 8002260: 2206 movs r2, #6 8002262: 4975 ldr r1, [pc, #468] @ (8002438 ) 8002264: 189b adds r3, r3, r2 8002266: 220c movs r2, #12 8002268: 0018 movs r0, r3 800226a: f005 fd4f bl 8007d0c response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1; 800226e: 193b adds r3, r7, r4 8002270: 220d movs r2, #13 8002272: 70da strb r2, [r3, #3] comp_crc_header(&crc, &response); 8002274: 193a adds r2, r7, r4 8002276: 230c movs r3, #12 8002278: 18fb adds r3, r7, r3 800227a: 0011 movs r1, r2 800227c: 0018 movs r0, r3 800227e: f7ff fcb5 bl 8001bec payload_ptr = (uint8_t*)&response.status; 8002282: 193b adds r3, r7, r4 8002284: 3305 adds r3, #5 8002286: 643b str r3, [r7, #64] @ 0x40 for (uint32_t i = 0; i < response.header.payloadLength; i++) 8002288: 2300 movs r3, #0 800228a: 657b str r3, [r7, #84] @ 0x54 800228c: e00c b.n 80022a8 CRC8_107_add(&crc, *(payload_ptr + i)); 800228e: 6c3a ldr r2, [r7, #64] @ 0x40 8002290: 6d7b ldr r3, [r7, #84] @ 0x54 8002292: 18d3 adds r3, r2, r3 8002294: 781a ldrb r2, [r3, #0] 8002296: 230c movs r3, #12 8002298: 18fb adds r3, r7, r3 800229a: 0011 movs r1, r2 800229c: 0018 movs r0, r3 800229e: f7fe fa2f bl 8000700 for (uint32_t i = 0; i < response.header.payloadLength; i++) 80022a2: 6d7b ldr r3, [r7, #84] @ 0x54 80022a4: 3301 adds r3, #1 80022a6: 657b str r3, [r7, #84] @ 0x54 80022a8: 2410 movs r4, #16 80022aa: 193b adds r3, r7, r4 80022ac: 78db ldrb r3, [r3, #3] 80022ae: 001a movs r2, r3 80022b0: 6d7b ldr r3, [r7, #84] @ 0x54 80022b2: 4293 cmp r3, r2 80022b4: d3eb bcc.n 800228e response.header.crc = CRC8_107_getChecksum(&crc); 80022b6: 230c movs r3, #12 80022b8: 18fb adds r3, r7, r3 80022ba: 0018 movs r0, r3 80022bc: f7fe fa50 bl 8000760 80022c0: 0003 movs r3, r0 80022c2: 001a movs r2, r3 80022c4: 193b adds r3, r7, r4 80022c6: 711a strb r2, [r3, #4] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 80022c8: 193b adds r3, r7, r4 80022ca: 78db ldrb r3, [r3, #3] 80022cc: 3305 adds r3, #5 80022ce: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100); 80022d0: 6bfb ldr r3, [r7, #60] @ 0x3c 80022d2: b29a uxth r2, r3 80022d4: 1939 adds r1, r7, r4 80022d6: 4859 ldr r0, [pc, #356] @ (800243c ) 80022d8: 2364 movs r3, #100 @ 0x64 80022da: f004 fc5f bl 8006b9c break; 80022de: e14e b.n 800257e handle_vendor_options(command->payload.vendorOptions.options, response.payload.vendorOptions.options); 80022e0: 6c7b ldr r3, [r7, #68] @ 0x44 80022e2: 1d9a adds r2, r3, #6 80022e4: 2410 movs r4, #16 80022e6: 193b adds r3, r7, r4 80022e8: 3306 adds r3, #6 80022ea: 0019 movs r1, r3 80022ec: 0010 movs r0, r2 80022ee: f000 fe15 bl 8002f1c response.status = STATUS_OK; 80022f2: 193b adds r3, r7, r4 80022f4: 2200 movs r2, #0 80022f6: 715a strb r2, [r3, #5] comp_crc_header(&crc,&response); 80022f8: 193a adds r2, r7, r4 80022fa: 230c movs r3, #12 80022fc: 18fb adds r3, r7, r3 80022fe: 0011 movs r1, r2 8002300: 0018 movs r0, r3 8002302: f7ff fc73 bl 8001bec payload_ptr =(uint8_t*) &response.status; 8002306: 193b adds r3, r7, r4 8002308: 3305 adds r3, #5 800230a: 643b str r3, [r7, #64] @ 0x40 for (uint32_t i = 0; i CRC8_107_add(&crc,*(payload_ptr+i)); 8002312: 6c3a ldr r2, [r7, #64] @ 0x40 8002314: 6d3b ldr r3, [r7, #80] @ 0x50 8002316: 18d3 adds r3, r2, r3 8002318: 781a ldrb r2, [r3, #0] 800231a: 230c movs r3, #12 800231c: 18fb adds r3, r7, r3 800231e: 0011 movs r1, r2 8002320: 0018 movs r0, r3 8002322: f7fe f9ed bl 8000700 for (uint32_t i = 0; i response.header.crc = CRC8_107_getChecksum(&crc); 8002332: 230c movs r3, #12 8002334: 18fb adds r3, r7, r3 8002336: 0018 movs r0, r3 8002338: f7fe fa12 bl 8000760 800233c: 0003 movs r3, r0 800233e: 001a movs r2, r3 8002340: 2110 movs r1, #16 8002342: 187b adds r3, r7, r1 8002344: 711a strb r2, [r3, #4] response.header.payloadLength = sizeof(response.payload.vendorOptions)+1; // +1 for the status byte 8002346: 187b adds r3, r7, r1 8002348: 2215 movs r2, #21 800234a: 70da strb r2, [r3, #3] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 800234c: 187b adds r3, r7, r1 800234e: 78db ldrb r3, [r3, #3] 8002350: 3305 adds r3, #5 8002352: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100); 8002354: 6bfb ldr r3, [r7, #60] @ 0x3c 8002356: b29a uxth r2, r3 8002358: 1879 adds r1, r7, r1 800235a: 4838 ldr r0, [pc, #224] @ (800243c ) 800235c: 2364 movs r3, #100 @ 0x64 800235e: f004 fc1d bl 8006b9c break; 8002362: e10c b.n 800257e if(memcmp(UUID,command->payload.getFeederAddress.uuid,UUID_LENGTH) == 0) 8002364: 6c7b ldr r3, [r7, #68] @ 0x44 8002366: 1d99 adds r1, r3, #6 8002368: 4b33 ldr r3, [pc, #204] @ (8002438 ) 800236a: 220c movs r2, #12 800236c: 0018 movs r0, r3 800236e: f005 fc93 bl 8007c98 8002372: 1e03 subs r3, r0, #0 8002374: d000 beq.n 8002378 8002376: e0fd b.n 8002574 response.status = STATUS_OK; 8002378: 2410 movs r4, #16 800237a: 193b adds r3, r7, r4 800237c: 2200 movs r2, #0 800237e: 715a strb r2, [r3, #5] response.header.payloadLength = 1; // only status byte 8002380: 193b adds r3, r7, r4 8002382: 2201 movs r2, #1 8002384: 70da strb r2, [r3, #3] comp_crc_header(&crc,&response); 8002386: 193a adds r2, r7, r4 8002388: 250c movs r5, #12 800238a: 197b adds r3, r7, r5 800238c: 0011 movs r1, r2 800238e: 0018 movs r0, r3 8002390: f7ff fc2c bl 8001bec CRC8_107_add(&crc,response.status); 8002394: 193b adds r3, r7, r4 8002396: 795a ldrb r2, [r3, #5] 8002398: 197b adds r3, r7, r5 800239a: 0011 movs r1, r2 800239c: 0018 movs r0, r3 800239e: f7fe f9af bl 8000700 response.header.crc = CRC8_107_getChecksum(&crc); 80023a2: 197b adds r3, r7, r5 80023a4: 0018 movs r0, r3 80023a6: f7fe f9db bl 8000760 80023aa: 0003 movs r3, r0 80023ac: 001a movs r2, r3 80023ae: 193b adds r3, r7, r4 80023b0: 711a strb r2, [r3, #4] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 80023b2: 193b adds r3, r7, r4 80023b4: 78db ldrb r3, [r3, #3] 80023b6: 3305 adds r3, #5 80023b8: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100); 80023ba: 6bfb ldr r3, [r7, #60] @ 0x3c 80023bc: b29a uxth r2, r3 80023be: 1939 adds r1, r7, r4 80023c0: 481e ldr r0, [pc, #120] @ (800243c ) 80023c2: 2364 movs r3, #100 @ 0x64 80023c4: f004 fbea bl 8006b9c break; 80023c8: e0d9 b.n 800257e if(memcmp(UUID,command->payload.identifyFeeder.uuid,UUID_LENGTH) == 0) 80023ca: 6c7b ldr r3, [r7, #68] @ 0x44 80023cc: 1d99 adds r1, r3, #6 80023ce: 4b1a ldr r3, [pc, #104] @ (8002438 ) 80023d0: 220c movs r2, #12 80023d2: 0018 movs r0, r3 80023d4: f005 fc60 bl 8007c98 80023d8: 1e03 subs r3, r0, #0 80023da: d000 beq.n 80023de 80023dc: e0cc b.n 8002578 response.status = STATUS_OK; 80023de: 2410 movs r4, #16 80023e0: 193b adds r3, r7, r4 80023e2: 2200 movs r2, #0 80023e4: 715a strb r2, [r3, #5] response.header.payloadLength = 1; // only status byte 80023e6: 193b adds r3, r7, r4 80023e8: 2201 movs r2, #1 80023ea: 70da strb r2, [r3, #3] comp_crc_header(&crc,&response); 80023ec: 193a adds r2, r7, r4 80023ee: 250c movs r5, #12 80023f0: 197b adds r3, r7, r5 80023f2: 0011 movs r1, r2 80023f4: 0018 movs r0, r3 80023f6: f7ff fbf9 bl 8001bec CRC8_107_add(&crc,response.status); 80023fa: 193b adds r3, r7, r4 80023fc: 795a ldrb r2, [r3, #5] 80023fe: 197b adds r3, r7, r5 8002400: 0011 movs r1, r2 8002402: 0018 movs r0, r3 8002404: f7fe f97c bl 8000700 response.header.crc = CRC8_107_getChecksum(&crc); 8002408: 197b adds r3, r7, r5 800240a: 0018 movs r0, r3 800240c: f7fe f9a8 bl 8000760 8002410: 0003 movs r3, r0 8002412: 001a movs r2, r3 8002414: 193b adds r3, r7, r4 8002416: 711a strb r2, [r3, #4] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 8002418: 193b adds r3, r7, r4 800241a: 78db ldrb r3, [r3, #3] 800241c: 3305 adds r3, #5 800241e: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100); 8002420: 6bfb ldr r3, [r7, #60] @ 0x3c 8002422: b29a uxth r2, r3 8002424: 1939 adds r1, r7, r4 8002426: 4805 ldr r0, [pc, #20] @ (800243c ) 8002428: 2364 movs r3, #100 @ 0x64 800242a: f004 fbb7 bl 8006b9c identify_feeder(); 800242e: f000 fa15 bl 800285c break; 8002432: e0a4 b.n 800257e 8002434: 200003c0 .word 0x200003c0 8002438: 200003b4 .word 0x200003b4 800243c: 2000025c .word 0x2000025c 8002440: 200004bd .word 0x200004bd 8002444: 200004bc .word 0x200004bc uint8_t new_address = command->payload.programFeederFloorAddress.address; 8002448: 253b movs r5, #59 @ 0x3b 800244a: 197b adds r3, r7, r5 800244c: 6c7a ldr r2, [r7, #68] @ 0x44 800244e: 7c92 ldrb r2, [r2, #18] 8002450: 701a strb r2, [r3, #0] uint8_t write_success = write_floor_address(new_address); 8002452: 263a movs r6, #58 @ 0x3a 8002454: 19bc adds r4, r7, r6 8002456: 197b adds r3, r7, r5 8002458: 781b ldrb r3, [r3, #0] 800245a: 0018 movs r0, r3 800245c: f000 ffcf bl 80033fe 8002460: 0003 movs r3, r0 8002462: 7023 strb r3, [r4, #0] if (write_success) 8002464: 19bb adds r3, r7, r6 8002466: 781b ldrb r3, [r3, #0] 8002468: 2b00 cmp r3, #0 800246a: d00f beq.n 800248c my_address = new_address; 800246c: 4b45 ldr r3, [pc, #276] @ (8002584 ) 800246e: 197a adds r2, r7, r5 8002470: 7812 ldrb r2, [r2, #0] 8002472: 701a strb r2, [r3, #0] floor_address = new_address; 8002474: 4b44 ldr r3, [pc, #272] @ (8002588 ) 8002476: 197a adds r2, r7, r5 8002478: 7812 ldrb r2, [r2, #0] 800247a: 701a strb r2, [r3, #0] floor_address_status = 2; 800247c: 4b43 ldr r3, [pc, #268] @ (800258c ) 800247e: 2202 movs r2, #2 8002480: 701a strb r2, [r3, #0] response.status = STATUS_OK; 8002482: 2310 movs r3, #16 8002484: 18fb adds r3, r7, r3 8002486: 2200 movs r2, #0 8002488: 715a strb r2, [r3, #5] 800248a: e003 b.n 8002494 response.status = STATUS_FAIL; 800248c: 2310 movs r3, #16 800248e: 18fb adds r3, r7, r3 8002490: 2205 movs r2, #5 8002492: 715a strb r2, [r3, #5] response.header.payloadLength = 1; // only status byte 8002494: 2410 movs r4, #16 8002496: 193b adds r3, r7, r4 8002498: 2201 movs r2, #1 800249a: 70da strb r2, [r3, #3] comp_crc_header(&crc, &response); 800249c: 193a adds r2, r7, r4 800249e: 250c movs r5, #12 80024a0: 197b adds r3, r7, r5 80024a2: 0011 movs r1, r2 80024a4: 0018 movs r0, r3 80024a6: f7ff fba1 bl 8001bec CRC8_107_add(&crc, response.status); 80024aa: 193b adds r3, r7, r4 80024ac: 795a ldrb r2, [r3, #5] 80024ae: 197b adds r3, r7, r5 80024b0: 0011 movs r1, r2 80024b2: 0018 movs r0, r3 80024b4: f7fe f924 bl 8000700 response.header.crc = CRC8_107_getChecksum(&crc); 80024b8: 197b adds r3, r7, r5 80024ba: 0018 movs r0, r3 80024bc: f7fe f950 bl 8000760 80024c0: 0003 movs r3, r0 80024c2: 001a movs r2, r3 80024c4: 193b adds r3, r7, r4 80024c6: 711a strb r2, [r3, #4] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 80024c8: 193b adds r3, r7, r4 80024ca: 78db ldrb r3, [r3, #3] 80024cc: 3305 adds r3, #5 80024ce: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100); 80024d0: 6bfb ldr r3, [r7, #60] @ 0x3c 80024d2: b29a uxth r2, r3 80024d4: 1939 adds r1, r7, r4 80024d6: 482e ldr r0, [pc, #184] @ (8002590 ) 80024d8: 2364 movs r3, #100 @ 0x64 80024da: f004 fb5f bl 8006b9c break; 80024de: e04e b.n 800257e if (is_initialized) return; 80024e0: 4b2c ldr r3, [pc, #176] @ (8002594 ) 80024e2: 781b ldrb r3, [r3, #0] 80024e4: 2b00 cmp r3, #0 80024e6: d149 bne.n 800257c memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH); 80024e8: 2410 movs r4, #16 80024ea: 193b adds r3, r7, r4 80024ec: 2206 movs r2, #6 80024ee: 492a ldr r1, [pc, #168] @ (8002598 ) 80024f0: 189b adds r3, r3, r2 80024f2: 220c movs r2, #12 80024f4: 0018 movs r0, r3 80024f6: f005 fc09 bl 8007d0c response.header.payloadLength=sizeof(response.payload)+1; 80024fa: 193b adds r3, r7, r4 80024fc: 2215 movs r2, #21 80024fe: 70da strb r2, [r3, #3] response.status=STATUS_OK; 8002500: 193b adds r3, r7, r4 8002502: 2200 movs r2, #0 8002504: 715a strb r2, [r3, #5] payload_ptr =(uint8_t*) &response.payload; 8002506: 193b adds r3, r7, r4 8002508: 3306 adds r3, #6 800250a: 643b str r3, [r7, #64] @ 0x40 for (uint32_t i = 0; i CRC8_107_add(&crc,*(payload_ptr+i)); 8002512: 6c3a ldr r2, [r7, #64] @ 0x40 8002514: 6cfb ldr r3, [r7, #76] @ 0x4c 8002516: 18d3 adds r3, r2, r3 8002518: 781a ldrb r2, [r3, #0] 800251a: 230c movs r3, #12 800251c: 18fb adds r3, r7, r3 800251e: 0011 movs r1, r2 8002520: 0018 movs r0, r3 8002522: f7fe f8ed bl 8000700 for (uint32_t i = 0; i response.header.crc = CRC8_107_getChecksum(&crc); 8002532: 230c movs r3, #12 8002534: 18fb adds r3, r7, r3 8002536: 0018 movs r0, r3 8002538: f7fe f912 bl 8000760 800253c: 0003 movs r3, r0 800253e: 001a movs r2, r3 8002540: 2110 movs r1, #16 8002542: 187b adds r3, r7, r1 8002544: 711a strb r2, [r3, #4] response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for the length byte 8002546: 187b adds r3, r7, r1 8002548: 220d movs r2, #13 800254a: 70da strb r2, [r3, #3] packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength; 800254c: 187b adds r3, r7, r1 800254e: 78db ldrb r3, [r3, #3] 8002550: 3305 adds r3, #5 8002552: 63fb str r3, [r7, #60] @ 0x3c HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100); 8002554: 6bfb ldr r3, [r7, #60] @ 0x3c 8002556: b29a uxth r2, r3 8002558: 1879 adds r1, r7, r1 800255a: 480d ldr r0, [pc, #52] @ (8002590 ) 800255c: 2364 movs r3, #100 @ 0x64 800255e: f004 fb1d bl 8006b9c break; 8002562: e00c b.n 800257e return; // packet too small 8002564: 46c0 nop @ (mov r8, r8) 8002566: e00a b.n 800257e return; // CRC mismatch, discard packet 8002568: 46c0 nop @ (mov r8, r8) 800256a: e008 b.n 800257e return; // message not for us 800256c: 46c0 nop @ (mov r8, r8) 800256e: e006 b.n 800257e return; 8002570: 46c0 nop @ (mov r8, r8) 8002572: e004 b.n 800257e return; // this makes no sense, but original code behaves like this 8002574: 46c0 nop @ (mov r8, r8) 8002576: e002 b.n 800257e return; // UUID doesn't match, ignore 8002578: 46c0 nop @ (mov r8, r8) 800257a: e000 b.n 800257e if (is_initialized) return; 800257c: 46c0 nop @ (mov r8, r8) break; } } } 800257e: 46bd mov sp, r7 8002580: b01f add sp, #124 @ 0x7c 8002582: bdf0 pop {r4, r5, r6, r7, pc} 8002584: 20000002 .word 0x20000002 8002588: 2000001f .word 0x2000001f 800258c: 2000054c .word 0x2000054c 8002590: 2000025c .word 0x2000025c 8002594: 200003c0 .word 0x200003c0 8002598: 200003b4 .word 0x200003b4 0800259c : #define FEED_PWM_MIN_THRESHOLD 840 // 35% of 2400 - below this, don't drive void set_Feeder_PWM(uint16_t PWM, uint8_t direction) { 800259c: b580 push {r7, lr} 800259e: b082 sub sp, #8 80025a0: af00 add r7, sp, #0 80025a2: 0002 movs r2, r0 80025a4: 1dbb adds r3, r7, #6 80025a6: 801a strh r2, [r3, #0] 80025a8: 1d7b adds r3, r7, #5 80025aa: 1c0a adds r2, r1, #0 80025ac: 701a strb r2, [r3, #0] if (PWM > 0 && PWM < FEED_PWM_MIN_THRESHOLD) PWM = 0; 80025ae: 1dbb adds r3, r7, #6 80025b0: 881b ldrh r3, [r3, #0] 80025b2: 2b00 cmp r3, #0 80025b4: d008 beq.n 80025c8 80025b6: 1dbb adds r3, r7, #6 80025b8: 881a ldrh r2, [r3, #0] 80025ba: 23d2 movs r3, #210 @ 0xd2 80025bc: 009b lsls r3, r3, #2 80025be: 429a cmp r2, r3 80025c0: d202 bcs.n 80025c8 80025c2: 1dbb adds r3, r7, #6 80025c4: 2200 movs r2, #0 80025c6: 801a strh r2, [r3, #0] if (direction) 80025c8: 1d7b adds r3, r7, #5 80025ca: 781b ldrb r3, [r3, #0] 80025cc: 2b00 cmp r3, #0 80025ce: d009 beq.n 80025e4 { htim1.Instance->CCR1 = PWM; 80025d0: 4b0b ldr r3, [pc, #44] @ (8002600 ) 80025d2: 681b ldr r3, [r3, #0] 80025d4: 1dba adds r2, r7, #6 80025d6: 8812 ldrh r2, [r2, #0] 80025d8: 635a str r2, [r3, #52] @ 0x34 htim1.Instance->CCR2 = 0; 80025da: 4b09 ldr r3, [pc, #36] @ (8002600 ) 80025dc: 681b ldr r3, [r3, #0] 80025de: 2200 movs r2, #0 80025e0: 639a str r2, [r3, #56] @ 0x38 else { htim1.Instance->CCR1 = 0; htim1.Instance->CCR2 = PWM; } } 80025e2: e008 b.n 80025f6 htim1.Instance->CCR1 = 0; 80025e4: 4b06 ldr r3, [pc, #24] @ (8002600 ) 80025e6: 681b ldr r3, [r3, #0] 80025e8: 2200 movs r2, #0 80025ea: 635a str r2, [r3, #52] @ 0x34 htim1.Instance->CCR2 = PWM; 80025ec: 4b04 ldr r3, [pc, #16] @ (8002600 ) 80025ee: 681b ldr r3, [r3, #0] 80025f0: 1dba adds r2, r7, #6 80025f2: 8812 ldrh r2, [r2, #0] 80025f4: 639a str r2, [r3, #56] @ 0x38 } 80025f6: 46c0 nop @ (mov r8, r8) 80025f8: 46bd mov sp, r7 80025fa: b002 add sp, #8 80025fc: bd80 pop {r7, pc} 80025fe: 46c0 nop @ (mov r8, r8) 8002600: 2000004c .word 0x2000004c 08002604 : void peel_motor(uint8_t forward) { 8002604: b580 push {r7, lr} 8002606: b082 sub sp, #8 8002608: af00 add r7, sp, #0 800260a: 0002 movs r2, r0 800260c: 1dfb adds r3, r7, #7 800260e: 701a strb r2, [r3, #0] peel_target_pwm = forward ? PWM_MAX : -PWM_MAX; 8002610: 1dfb adds r3, r7, #7 8002612: 781b ldrb r3, [r3, #0] 8002614: 2b00 cmp r3, #0 8002616: d002 beq.n 800261e 8002618: 2396 movs r3, #150 @ 0x96 800261a: 011a lsls r2, r3, #4 800261c: e000 b.n 8002620 800261e: 4a03 ldr r2, [pc, #12] @ (800262c ) 8002620: 4b03 ldr r3, [pc, #12] @ (8002630 ) 8002622: 801a strh r2, [r3, #0] } 8002624: 46c0 nop @ (mov r8, r8) 8002626: 46bd mov sp, r7 8002628: b002 add sp, #8 800262a: bd80 pop {r7, pc} 800262c: fffff6a0 .word 0xfffff6a0 8002630: 200004d6 .word 0x200004d6 08002634 : void peel_brake(void) { 8002634: b580 push {r7, lr} 8002636: af00 add r7, sp, #0 peel_target_pwm = 0; 8002638: 4b02 ldr r3, [pc, #8] @ (8002644 ) 800263a: 2200 movs r2, #0 800263c: 801a strh r2, [r3, #0] } 800263e: 46c0 nop @ (mov r8, r8) 8002640: 46bd mov sp, r7 8002642: bd80 pop {r7, pc} 8002644: 200004d6 .word 0x200004d6 08002648 : void peel_ramp_update(void) { 8002648: b580 push {r7, lr} 800264a: b084 sub sp, #16 800264c: af00 add r7, sp, #0 uint32_t now = HAL_GetTick(); 800264e: f001 fd43 bl 80040d8 8002652: 0003 movs r3, r0 8002654: 60bb str r3, [r7, #8] uint32_t dt = now - peel_last_ramp_time; 8002656: 4b4d ldr r3, [pc, #308] @ (800278c ) 8002658: 681b ldr r3, [r3, #0] 800265a: 68ba ldr r2, [r7, #8] 800265c: 1ad3 subs r3, r2, r3 800265e: 607b str r3, [r7, #4] if (dt == 0) return; 8002660: 687b ldr r3, [r7, #4] 8002662: 2b00 cmp r3, #0 8002664: d100 bne.n 8002668 8002666: e08b b.n 8002780 peel_last_ramp_time = now; 8002668: 4b48 ldr r3, [pc, #288] @ (800278c ) 800266a: 68ba ldr r2, [r7, #8] 800266c: 601a str r2, [r3, #0] if (peel_current_pwm == peel_target_pwm) return; 800266e: 4b48 ldr r3, [pc, #288] @ (8002790 ) 8002670: 2200 movs r2, #0 8002672: 5e9a ldrsh r2, [r3, r2] 8002674: 4b47 ldr r3, [pc, #284] @ (8002794 ) 8002676: 2100 movs r1, #0 8002678: 5e5b ldrsh r3, [r3, r1] 800267a: 429a cmp r2, r3 800267c: d100 bne.n 8002680 800267e: e081 b.n 8002784 // Step size: full range (PWM_MAX) in PEEL_RAMP_TIME_MS int16_t step = (int16_t)((int32_t)PWM_MAX * dt / PEEL_RAMP_TIME_MS); 8002680: 687a ldr r2, [r7, #4] 8002682: 0013 movs r3, r2 8002684: 009b lsls r3, r3, #2 8002686: 189b adds r3, r3, r2 8002688: 011a lsls r2, r3, #4 800268a: 1ad2 subs r2, r2, r3 800268c: 0153 lsls r3, r2, #5 800268e: 001a movs r2, r3 8002690: 0013 movs r3, r2 8002692: 2164 movs r1, #100 @ 0x64 8002694: 0018 movs r0, r3 8002696: f7fd fd37 bl 8000108 <__udivsi3> 800269a: 0003 movs r3, r0 800269c: 001a movs r2, r3 800269e: 210e movs r1, #14 80026a0: 187b adds r3, r7, r1 80026a2: 801a strh r2, [r3, #0] if (step < 1) step = 1; 80026a4: 000a movs r2, r1 80026a6: 18bb adds r3, r7, r2 80026a8: 2100 movs r1, #0 80026aa: 5e5b ldrsh r3, [r3, r1] 80026ac: 2b00 cmp r3, #0 80026ae: dc02 bgt.n 80026b6 80026b0: 18bb adds r3, r7, r2 80026b2: 2201 movs r2, #1 80026b4: 801a strh r2, [r3, #0] if (peel_target_pwm > peel_current_pwm) 80026b6: 4b37 ldr r3, [pc, #220] @ (8002794 ) 80026b8: 2200 movs r2, #0 80026ba: 5e9a ldrsh r2, [r3, r2] 80026bc: 4b34 ldr r3, [pc, #208] @ (8002790 ) 80026be: 2100 movs r1, #0 80026c0: 5e5b ldrsh r3, [r3, r1] 80026c2: 429a cmp r2, r3 80026c4: dd19 ble.n 80026fa { peel_current_pwm += step; 80026c6: 4b32 ldr r3, [pc, #200] @ (8002790 ) 80026c8: 2200 movs r2, #0 80026ca: 5e9b ldrsh r3, [r3, r2] 80026cc: b29a uxth r2, r3 80026ce: 230e movs r3, #14 80026d0: 18fb adds r3, r7, r3 80026d2: 881b ldrh r3, [r3, #0] 80026d4: 18d3 adds r3, r2, r3 80026d6: b29b uxth r3, r3 80026d8: b21a sxth r2, r3 80026da: 4b2d ldr r3, [pc, #180] @ (8002790 ) 80026dc: 801a strh r2, [r3, #0] if (peel_current_pwm > peel_target_pwm) 80026de: 4b2c ldr r3, [pc, #176] @ (8002790 ) 80026e0: 2200 movs r2, #0 80026e2: 5e9a ldrsh r2, [r3, r2] 80026e4: 4b2b ldr r3, [pc, #172] @ (8002794 ) 80026e6: 2100 movs r1, #0 80026e8: 5e5b ldrsh r3, [r3, r1] 80026ea: 429a cmp r2, r3 80026ec: dd1e ble.n 800272c peel_current_pwm = peel_target_pwm; 80026ee: 4b29 ldr r3, [pc, #164] @ (8002794 ) 80026f0: 2200 movs r2, #0 80026f2: 5e9a ldrsh r2, [r3, r2] 80026f4: 4b26 ldr r3, [pc, #152] @ (8002790 ) 80026f6: 801a strh r2, [r3, #0] 80026f8: e018 b.n 800272c } else { peel_current_pwm -= step; 80026fa: 4b25 ldr r3, [pc, #148] @ (8002790 ) 80026fc: 2200 movs r2, #0 80026fe: 5e9b ldrsh r3, [r3, r2] 8002700: b29a uxth r2, r3 8002702: 230e movs r3, #14 8002704: 18fb adds r3, r7, r3 8002706: 881b ldrh r3, [r3, #0] 8002708: 1ad3 subs r3, r2, r3 800270a: b29b uxth r3, r3 800270c: b21a sxth r2, r3 800270e: 4b20 ldr r3, [pc, #128] @ (8002790 ) 8002710: 801a strh r2, [r3, #0] if (peel_current_pwm < peel_target_pwm) 8002712: 4b1f ldr r3, [pc, #124] @ (8002790 ) 8002714: 2200 movs r2, #0 8002716: 5e9a ldrsh r2, [r3, r2] 8002718: 4b1e ldr r3, [pc, #120] @ (8002794 ) 800271a: 2100 movs r1, #0 800271c: 5e5b ldrsh r3, [r3, r1] 800271e: 429a cmp r2, r3 8002720: da04 bge.n 800272c peel_current_pwm = peel_target_pwm; 8002722: 4b1c ldr r3, [pc, #112] @ (8002794 ) 8002724: 2200 movs r2, #0 8002726: 5e9a ldrsh r2, [r3, r2] 8002728: 4b19 ldr r3, [pc, #100] @ (8002790 ) 800272a: 801a strh r2, [r3, #0] } // Apply to TIM1 CH3/CH4 if (peel_current_pwm > 0) 800272c: 4b18 ldr r3, [pc, #96] @ (8002790 ) 800272e: 2200 movs r2, #0 8002730: 5e9b ldrsh r3, [r3, r2] 8002732: 2b00 cmp r3, #0 8002734: dd0a ble.n 800274c { htim1.Instance->CCR3 = peel_current_pwm; 8002736: 4b16 ldr r3, [pc, #88] @ (8002790 ) 8002738: 2200 movs r2, #0 800273a: 5e9a ldrsh r2, [r3, r2] 800273c: 4b16 ldr r3, [pc, #88] @ (8002798 ) 800273e: 681b ldr r3, [r3, #0] 8002740: 63da str r2, [r3, #60] @ 0x3c htim1.Instance->CCR4 = 0; 8002742: 4b15 ldr r3, [pc, #84] @ (8002798 ) 8002744: 681b ldr r3, [r3, #0] 8002746: 2200 movs r2, #0 8002748: 641a str r2, [r3, #64] @ 0x40 800274a: e01c b.n 8002786 } else if (peel_current_pwm < 0) 800274c: 4b10 ldr r3, [pc, #64] @ (8002790 ) 800274e: 2200 movs r2, #0 8002750: 5e9b ldrsh r3, [r3, r2] 8002752: 2b00 cmp r3, #0 8002754: da0b bge.n 800276e { htim1.Instance->CCR3 = 0; 8002756: 4b10 ldr r3, [pc, #64] @ (8002798 ) 8002758: 681b ldr r3, [r3, #0] 800275a: 2200 movs r2, #0 800275c: 63da str r2, [r3, #60] @ 0x3c htim1.Instance->CCR4 = -peel_current_pwm; 800275e: 4b0c ldr r3, [pc, #48] @ (8002790 ) 8002760: 2200 movs r2, #0 8002762: 5e9b ldrsh r3, [r3, r2] 8002764: 425a negs r2, r3 8002766: 4b0c ldr r3, [pc, #48] @ (8002798 ) 8002768: 681b ldr r3, [r3, #0] 800276a: 641a str r2, [r3, #64] @ 0x40 800276c: e00b b.n 8002786 } else { htim1.Instance->CCR3 = 0; 800276e: 4b0a ldr r3, [pc, #40] @ (8002798 ) 8002770: 681b ldr r3, [r3, #0] 8002772: 2200 movs r2, #0 8002774: 63da str r2, [r3, #60] @ 0x3c htim1.Instance->CCR4 = 0; 8002776: 4b08 ldr r3, [pc, #32] @ (8002798 ) 8002778: 681b ldr r3, [r3, #0] 800277a: 2200 movs r2, #0 800277c: 641a str r2, [r3, #64] @ 0x40 800277e: e002 b.n 8002786 if (dt == 0) return; 8002780: 46c0 nop @ (mov r8, r8) 8002782: e000 b.n 8002786 if (peel_current_pwm == peel_target_pwm) return; 8002784: 46c0 nop @ (mov r8, r8) } } 8002786: 46bd mov sp, r7 8002788: b004 add sp, #16 800278a: bd80 pop {r7, pc} 800278c: 200004dc .word 0x200004dc 8002790: 200004d8 .word 0x200004d8 8002794: 200004d6 .word 0x200004d6 8002798: 2000004c .word 0x2000004c 0800279c : void drive_continuous(uint8_t forward) { 800279c: b580 push {r7, lr} 800279e: b082 sub sp, #8 80027a0: af00 add r7, sp, #0 80027a2: 0002 movs r2, r0 80027a4: 1dfb adds r3, r7, #7 80027a6: 701a strb r2, [r3, #0] // Bypass PID - set target far away in the desired direction so PID drives at max pid_reset(&motor_pid); 80027a8: 4b0c ldr r3, [pc, #48] @ (80027dc ) 80027aa: 0018 movs r0, r3 80027ac: f7fe f836 bl 800081c if (forward) 80027b0: 1dfb adds r3, r7, #7 80027b2: 781b ldrb r3, [r3, #0] 80027b4: 2b00 cmp r3, #0 80027b6: d006 beq.n 80027c6 { target_count = total_count + 10000; 80027b8: 4b09 ldr r3, [pc, #36] @ (80027e0 ) 80027ba: 681b ldr r3, [r3, #0] 80027bc: 4a09 ldr r2, [pc, #36] @ (80027e4 ) 80027be: 189a adds r2, r3, r2 80027c0: 4b09 ldr r3, [pc, #36] @ (80027e8 ) 80027c2: 601a str r2, [r3, #0] } else { target_count = total_count - 10000; } } 80027c4: e005 b.n 80027d2 target_count = total_count - 10000; 80027c6: 4b06 ldr r3, [pc, #24] @ (80027e0 ) 80027c8: 681b ldr r3, [r3, #0] 80027ca: 4a08 ldr r2, [pc, #32] @ (80027ec ) 80027cc: 189a adds r2, r3, r2 80027ce: 4b06 ldr r3, [pc, #24] @ (80027e8 ) 80027d0: 601a str r2, [r3, #0] } 80027d2: 46c0 nop @ (mov r8, r8) 80027d4: 46bd mov sp, r7 80027d6: b002 add sp, #8 80027d8: bd80 pop {r7, pc} 80027da: 46c0 nop @ (mov r8, r8) 80027dc: 2000048c .word 0x2000048c 80027e0: 20000484 .word 0x20000484 80027e4: 00002710 .word 0x00002710 80027e8: 20000488 .word 0x20000488 80027ec: ffffd8f0 .word 0xffffd8f0 080027f0 : void halt_all(void) { 80027f0: b580 push {r7, lr} 80027f2: af00 add r7, sp, #0 // Stop drive motor (brake) htim1.Instance->CCR1 = PWM_MAX; 80027f4: 4b12 ldr r3, [pc, #72] @ (8002840 ) 80027f6: 681b ldr r3, [r3, #0] 80027f8: 2296 movs r2, #150 @ 0x96 80027fa: 0112 lsls r2, r2, #4 80027fc: 635a str r2, [r3, #52] @ 0x34 htim1.Instance->CCR2 = PWM_MAX; 80027fe: 4b10 ldr r3, [pc, #64] @ (8002840 ) 8002800: 681b ldr r3, [r3, #0] 8002802: 2296 movs r2, #150 @ 0x96 8002804: 0112 lsls r2, r2, #4 8002806: 639a str r2, [r3, #56] @ 0x38 // Stop peel motor immediately peel_target_pwm = 0; 8002808: 4b0e ldr r3, [pc, #56] @ (8002844 ) 800280a: 2200 movs r2, #0 800280c: 801a strh r2, [r3, #0] peel_current_pwm = 0; 800280e: 4b0e ldr r3, [pc, #56] @ (8002848 ) 8002810: 2200 movs r2, #0 8002812: 801a strh r2, [r3, #0] htim1.Instance->CCR3 = 0; 8002814: 4b0a ldr r3, [pc, #40] @ (8002840 ) 8002816: 681b ldr r3, [r3, #0] 8002818: 2200 movs r2, #0 800281a: 63da str r2, [r3, #60] @ 0x3c htim1.Instance->CCR4 = 0; 800281c: 4b08 ldr r3, [pc, #32] @ (8002840 ) 800281e: 681b ldr r3, [r3, #0] 8002820: 2200 movs r2, #0 8002822: 641a str r2, [r3, #64] @ 0x40 // Reset PID state to prevent sudden movement pid_reset(&motor_pid); 8002824: 4b09 ldr r3, [pc, #36] @ (800284c ) 8002826: 0018 movs r0, r3 8002828: f7fd fff8 bl 800081c target_count = total_count; // Set target to current position 800282c: 4b08 ldr r3, [pc, #32] @ (8002850 ) 800282e: 681a ldr r2, [r3, #0] 8002830: 4b08 ldr r3, [pc, #32] @ (8002854 ) 8002832: 601a str r2, [r3, #0] pid_add = 0; 8002834: 4b08 ldr r3, [pc, #32] @ (8002858 ) 8002836: 2200 movs r2, #0 8002838: 601a str r2, [r3, #0] } 800283a: 46c0 nop @ (mov r8, r8) 800283c: 46bd mov sp, r7 800283e: bd80 pop {r7, pc} 8002840: 2000004c .word 0x2000004c 8002844: 200004d6 .word 0x200004d6 8002848: 200004d8 .word 0x200004d8 800284c: 2000048c .word 0x2000048c 8002850: 20000484 .word 0x20000484 8002854: 20000488 .word 0x20000488 8002858: 200004b8 .word 0x200004b8 0800285c : void identify_feeder(void) { 800285c: b580 push {r7, lr} 800285e: b082 sub sp, #8 8002860: af00 add r7, sp, #0 // Flash LED white 3 times for (int i = 0; i < 3; i++) 8002862: 2300 movs r3, #0 8002864: 607b str r3, [r7, #4] 8002866: e016 b.n 8002896 { set_LED(1, 1, 1); 8002868: 2201 movs r2, #1 800286a: 2101 movs r1, #1 800286c: 2001 movs r0, #1 800286e: f7ff f97d bl 8001b6c HAL_Delay(300); 8002872: 2396 movs r3, #150 @ 0x96 8002874: 005b lsls r3, r3, #1 8002876: 0018 movs r0, r3 8002878: f001 fc38 bl 80040ec set_LED(0, 0, 0); 800287c: 2200 movs r2, #0 800287e: 2100 movs r1, #0 8002880: 2000 movs r0, #0 8002882: f7ff f973 bl 8001b6c HAL_Delay(300); 8002886: 2396 movs r3, #150 @ 0x96 8002888: 005b lsls r3, r3, #1 800288a: 0018 movs r0, r3 800288c: f001 fc2e bl 80040ec for (int i = 0; i < 3; i++) 8002890: 687b ldr r3, [r7, #4] 8002892: 3301 adds r3, #1 8002894: 607b str r3, [r7, #4] 8002896: 687b ldr r3, [r7, #4] 8002898: 2b02 cmp r3, #2 800289a: dde5 ble.n 8002868 } } 800289c: 46c0 nop @ (mov r8, r8) 800289e: 46c0 nop @ (mov r8, r8) 80028a0: 46bd mov sp, r7 80028a2: b002 add sp, #8 80028a4: bd80 pop {r7, pc} 080028a6 : void show_version(void) { 80028a6: b580 push {r7, lr} 80028a8: af00 add r7, sp, #0 // Flash green for release version set_LED(0, 1, 0); 80028aa: 2200 movs r2, #0 80028ac: 2101 movs r1, #1 80028ae: 2000 movs r0, #0 80028b0: f7ff f95c bl 8001b6c HAL_Delay(250); 80028b4: 20fa movs r0, #250 @ 0xfa 80028b6: f001 fc19 bl 80040ec set_LED(0, 0, 0); 80028ba: 2200 movs r2, #0 80028bc: 2100 movs r1, #0 80028be: 2000 movs r0, #0 80028c0: f7ff f954 bl 8001b6c HAL_Delay(250); 80028c4: 20fa movs r0, #250 @ 0xfa 80028c6: f001 fc11 bl 80040ec } 80028ca: 46c0 nop @ (mov r8, r8) 80028cc: 46bd mov sp, r7 80028ce: bd80 pop {r7, pc} 080028d0 : // Convert distance in tenths of mm to encoder counts int32_t tenths_to_counts(int16_t tenths) { 80028d0: b5b0 push {r4, r5, r7, lr} 80028d2: b084 sub sp, #16 80028d4: af00 add r7, sp, #0 80028d6: 0002 movs r2, r0 80028d8: 1dbb adds r3, r7, #6 80028da: 801a strh r2, [r3, #0] // counts = (tenths * 1000 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV int64_t temp = ((int64_t)tenths * 1000 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV; 80028dc: 1dbb adds r3, r7, #6 80028de: 881b ldrh r3, [r3, #0] 80028e0: b21b sxth r3, r3 80028e2: 001c movs r4, r3 80028e4: 17db asrs r3, r3, #31 80028e6: 001d movs r5, r3 80028e8: 4a0b ldr r2, [pc, #44] @ (8002918 ) 80028ea: 2300 movs r3, #0 80028ec: 0020 movs r0, r4 80028ee: 0029 movs r1, r5 80028f0: f7fd fda4 bl 800043c <__aeabi_lmul> 80028f4: 0002 movs r2, r0 80028f6: 000b movs r3, r1 80028f8: 0010 movs r0, r2 80028fa: 0019 movs r1, r3 80028fc: 4a07 ldr r2, [pc, #28] @ (800291c ) 80028fe: 2300 movs r3, #0 8002900: f7fd fd78 bl 80003f4 <__aeabi_ldivmod> 8002904: 0002 movs r2, r0 8002906: 000b movs r3, r1 8002908: 60ba str r2, [r7, #8] 800290a: 60fb str r3, [r7, #12] return (int32_t)temp; 800290c: 68bb ldr r3, [r7, #8] } 800290e: 0018 movs r0, r3 8002910: 46bd mov sp, r7 8002912: b004 add sp, #16 8002914: bdb0 pop {r4, r5, r7, pc} 8002916: 46c0 nop @ (mov r8, r8) 8002918: 01b81040 .word 0x01b81040 800291c: 0001f377 .word 0x0001f377 08002920 : // Calculate expected feed time in milliseconds uint16_t calculate_expected_feed_time(uint8_t distance, uint8_t forward) { 8002920: b580 push {r7, lr} 8002922: b084 sub sp, #16 8002924: af00 add r7, sp, #0 8002926: 0002 movs r2, r0 8002928: 1dfb adds r3, r7, #7 800292a: 701a strb r2, [r3, #0] 800292c: 1dbb adds r3, r7, #6 800292e: 1c0a adds r2, r1, #0 8002930: 701a strb r2, [r3, #0] if (forward) 8002932: 1dbb adds r3, r7, #6 8002934: 781b ldrb r3, [r3, #0] 8002936: 2b00 cmp r3, #0 8002938: d020 beq.n 800297c { // Forward: peel time + peel backoff + drive time + extra for first feed uint16_t time = (distance * PEEL_TIME_PER_TENTH_MM) + PEEL_BACKOFF_TIME + 800293a: 1dfb adds r3, r7, #7 800293c: 781b ldrb r3, [r3, #0] 800293e: b29b uxth r3, r3 8002940: 223a movs r2, #58 @ 0x3a 8002942: 4353 muls r3, r2 8002944: b29a uxth r2, r3 uint16_t time = (distance * PEEL_TIME_PER_TENTH_MM) + 8002946: 210e movs r1, #14 8002948: 187b adds r3, r7, r1 800294a: 321e adds r2, #30 800294c: 801a strh r2, [r3, #0] (distance * TIMEOUT_TIME_PER_TENTH_MM); if (first_feed_since_load) 800294e: 4b17 ldr r3, [pc, #92] @ (80029ac ) 8002950: 781b ldrb r3, [r3, #0] 8002952: 2b00 cmp r3, #0 8002954: d008 beq.n 8002968 { time += 1000; // Extra time for tape detection 8002956: 187a adds r2, r7, r1 8002958: 187b adds r3, r7, r1 800295a: 881b ldrh r3, [r3, #0] 800295c: 21fa movs r1, #250 @ 0xfa 800295e: 0089 lsls r1, r1, #2 8002960: 468c mov ip, r1 8002962: 4463 add r3, ip 8002964: 8013 strh r3, [r2, #0] 8002966: e005 b.n 8002974 } else { time += 200; 8002968: 220e movs r2, #14 800296a: 18bb adds r3, r7, r2 800296c: 18ba adds r2, r7, r2 800296e: 8812 ldrh r2, [r2, #0] 8002970: 32c8 adds r2, #200 @ 0xc8 8002972: 801a strh r2, [r3, #0] } return time; 8002974: 230e movs r3, #14 8002976: 18fb adds r3, r7, r3 8002978: 881b ldrh r3, [r3, #0] 800297a: e013 b.n 80029a4 } else { // Backward: unpeel + drive (with backlash) + slack removal return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) + 800297c: 1dfb adds r3, r7, #7 800297e: 781b ldrb r3, [r3, #0] 8002980: b29b uxth r3, r3 8002982: 1c1a adds r2, r3, #0 8002984: 0112 lsls r2, r2, #4 8002986: 1ad3 subs r3, r2, r3 8002988: 18db adds r3, r3, r3 800298a: b29a uxth r2, r3 ((distance + (BACKLASH_COMP_TENTH_MM * 2)) * TIMEOUT_TIME_PER_TENTH_MM) + 800298c: 1dfb adds r3, r7, #7 800298e: 781b ldrb r3, [r3, #0] 8002990: 3314 adds r3, #20 return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) + 8002992: b29b uxth r3, r3 8002994: 2128 movs r1, #40 @ 0x28 8002996: 434b muls r3, r1 8002998: b29b uxth r3, r3 800299a: 18d3 adds r3, r2, r3 800299c: b29b uxth r3, r3 BACKWARDS_FEED_FILM_SLACK_REMOVAL_TIME + 50; 800299e: 3391 adds r3, #145 @ 0x91 80029a0: 33ff adds r3, #255 @ 0xff 80029a2: b29b uxth r3, r3 } } 80029a4: 0018 movs r0, r3 80029a6: 46bd mov sp, r7 80029a8: b004 add sp, #16 80029aa: bd80 pop {r7, pc} 80029ac: 2000001d .word 0x2000001d 080029b0 : // Start a feed operation void start_feed(int16_t distance_tenths, uint8_t forward) { 80029b0: b580 push {r7, lr} 80029b2: b082 sub sp, #8 80029b4: af00 add r7, sp, #0 80029b6: 0002 movs r2, r0 80029b8: 1dbb adds r3, r7, #6 80029ba: 801a strh r2, [r3, #0] 80029bc: 1d7b adds r3, r7, #5 80029be: 1c0a adds r2, r1, #0 80029c0: 701a strb r2, [r3, #0] if (feed_state != FEED_STATE_IDLE) 80029c2: 4b3c ldr r3, [pc, #240] @ (8002ab4 ) 80029c4: 781b ldrb r3, [r3, #0] 80029c6: b2db uxtb r3, r3 80029c8: 2b00 cmp r3, #0 80029ca: d16e bne.n 8002aaa { return; // Already feeding } // Check for first feed calibration if (first_feed_since_load) 80029cc: 4b3a ldr r3, [pc, #232] @ (8002ab8 ) 80029ce: 781b ldrb r3, [r3, #0] 80029d0: 2b00 cmp r3, #0 80029d2: d004 beq.n 80029de { check_tape_loaded(); 80029d4: f000 fa3c bl 8002e50 first_feed_since_load = 0; 80029d8: 4b37 ldr r3, [pc, #220] @ (8002ab8 ) 80029da: 2200 movs r2, #0 80029dc: 701a strb r2, [r3, #0] } feed_distance_tenths = distance_tenths; 80029de: 4b37 ldr r3, [pc, #220] @ (8002abc ) 80029e0: 1dba adds r2, r7, #6 80029e2: 8812 ldrh r2, [r2, #0] 80029e4: 801a strh r2, [r3, #0] feed_direction = forward; 80029e6: 4b36 ldr r3, [pc, #216] @ (8002ac0 ) 80029e8: 1d7a adds r2, r7, #5 80029ea: 7812 ldrb r2, [r2, #0] 80029ec: 701a strb r2, [r3, #0] feed_retry_count = 0; 80029ee: 4b35 ldr r3, [pc, #212] @ (8002ac4 ) 80029f0: 2200 movs r2, #0 80029f2: 701a strb r2, [r3, #0] feed_in_progress = 1; 80029f4: 4b34 ldr r3, [pc, #208] @ (8002ac8 ) 80029f6: 2201 movs r2, #1 80029f8: 701a strb r2, [r3, #0] last_feed_status = STATUS_OK; 80029fa: 4b34 ldr r3, [pc, #208] @ (8002acc ) 80029fc: 2200 movs r2, #0 80029fe: 701a strb r2, [r3, #0] set_LED(1, 1, 1); // White during feed 8002a00: 2201 movs r2, #1 8002a02: 2101 movs r1, #1 8002a04: 2001 movs r0, #1 8002a06: f7ff f8b1 bl 8001b6c if (forward) 8002a0a: 1d7b adds r3, r7, #5 8002a0c: 781b ldrb r3, [r3, #0] 8002a0e: 2b00 cmp r3, #0 8002a10: d035 beq.n 8002a7e { // Forward feed: drive both motors simultaneously feed_state = FEED_STATE_PEEL_FORWARD; 8002a12: 4b28 ldr r3, [pc, #160] @ (8002ab4 ) 8002a14: 2201 movs r2, #1 8002a16: 701a strb r2, [r3, #0] feed_state_start_time = HAL_GetTick(); 8002a18: f001 fb5e bl 80040d8 8002a1c: 0002 movs r2, r0 8002a1e: 4b2c ldr r3, [pc, #176] @ (8002ad0 ) 8002a20: 601a str r2, [r3, #0] feed_state_duration = distance_tenths * PEEL_TIME_PER_TENTH_MM; 8002a22: 1dbb adds r3, r7, #6 8002a24: 2200 movs r2, #0 8002a26: 5e9a ldrsh r2, [r3, r2] 8002a28: 0013 movs r3, r2 8002a2a: 00db lsls r3, r3, #3 8002a2c: 189b adds r3, r3, r2 8002a2e: 005b lsls r3, r3, #1 8002a30: 001a movs r2, r3 8002a32: 4b28 ldr r3, [pc, #160] @ (8002ad4 ) 8002a34: 601a str r2, [r3, #0] peel_motor(1); // Peel forward 8002a36: 2001 movs r0, #1 8002a38: f7ff fde4 bl 8002604 // Start feed motor at the same time feed_timeout_time = HAL_GetTick() + (distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500; 8002a3c: f001 fb4c bl 80040d8 8002a40: 0001 movs r1, r0 8002a42: 1dbb adds r3, r7, #6 8002a44: 2200 movs r2, #0 8002a46: 5e9a ldrsh r2, [r3, r2] 8002a48: 0013 movs r3, r2 8002a4a: 009b lsls r3, r3, #2 8002a4c: 189b adds r3, r3, r2 8002a4e: 00db lsls r3, r3, #3 8002a50: 18cb adds r3, r1, r3 8002a52: 33f5 adds r3, #245 @ 0xf5 8002a54: 33ff adds r3, #255 @ 0xff 8002a56: 001a movs r2, r3 8002a58: 4b1f ldr r3, [pc, #124] @ (8002ad8 ) 8002a5a: 601a str r2, [r3, #0] feed_target_position = total_count + tenths_to_counts(distance_tenths); 8002a5c: 1dbb adds r3, r7, #6 8002a5e: 2200 movs r2, #0 8002a60: 5e9b ldrsh r3, [r3, r2] 8002a62: 0018 movs r0, r3 8002a64: f7ff ff34 bl 80028d0 8002a68: 0002 movs r2, r0 8002a6a: 4b1c ldr r3, [pc, #112] @ (8002adc ) 8002a6c: 681b ldr r3, [r3, #0] 8002a6e: 18d2 adds r2, r2, r3 8002a70: 4b1b ldr r3, [pc, #108] @ (8002ae0 ) 8002a72: 601a str r2, [r3, #0] target_count = feed_target_position; 8002a74: 4b1a ldr r3, [pc, #104] @ (8002ae0 ) 8002a76: 681a ldr r2, [r3, #0] 8002a78: 4b1a ldr r3, [pc, #104] @ (8002ae4 ) 8002a7a: 601a str r2, [r3, #0] 8002a7c: e016 b.n 8002aac } else { // Backward feed: start with unpeeling to give slack feed_state = FEED_STATE_UNPEEL; 8002a7e: 4b0d ldr r3, [pc, #52] @ (8002ab4 ) 8002a80: 2203 movs r2, #3 8002a82: 701a strb r2, [r3, #0] feed_state_start_time = HAL_GetTick(); 8002a84: f001 fb28 bl 80040d8 8002a88: 0002 movs r2, r0 8002a8a: 4b11 ldr r3, [pc, #68] @ (8002ad0 ) 8002a8c: 601a str r2, [r3, #0] feed_state_duration = distance_tenths * BACKWARDS_PEEL_TIME_PER_TENTH_MM; 8002a8e: 1dbb adds r3, r7, #6 8002a90: 2200 movs r2, #0 8002a92: 5e9a ldrsh r2, [r3, r2] 8002a94: 0013 movs r3, r2 8002a96: 011b lsls r3, r3, #4 8002a98: 1a9b subs r3, r3, r2 8002a9a: 005b lsls r3, r3, #1 8002a9c: 001a movs r2, r3 8002a9e: 4b0d ldr r3, [pc, #52] @ (8002ad4 ) 8002aa0: 601a str r2, [r3, #0] peel_motor(0); // Peel backward (unpeel) 8002aa2: 2000 movs r0, #0 8002aa4: f7ff fdae bl 8002604 8002aa8: e000 b.n 8002aac return; // Already feeding 8002aaa: 46c0 nop @ (mov r8, r8) } } 8002aac: 46bd mov sp, r7 8002aae: b002 add sp, #8 8002ab0: bd80 pop {r7, pc} 8002ab2: 46c0 nop @ (mov r8, r8) 8002ab4: 200004bf .word 0x200004bf 8002ab8: 2000001d .word 0x2000001d 8002abc: 200004cc .word 0x200004cc 8002ac0: 2000001c .word 0x2000001c 8002ac4: 200004d4 .word 0x200004d4 8002ac8: 200004bd .word 0x200004bd 8002acc: 200004bc .word 0x200004bc 8002ad0: 200004c0 .word 0x200004c0 8002ad4: 200004c4 .word 0x200004c4 8002ad8: 200004c8 .word 0x200004c8 8002adc: 20000484 .word 0x20000484 8002ae0: 200004d0 .word 0x200004d0 8002ae4: 20000488 .word 0x20000488 08002ae8 : // Update feed state machine - called from main loop void feed_state_machine_update(void) { 8002ae8: b590 push {r4, r7, lr} 8002aea: b087 sub sp, #28 8002aec: af00 add r7, sp, #0 if (feed_state == FEED_STATE_IDLE) 8002aee: 4bc6 ldr r3, [pc, #792] @ (8002e08 ) 8002af0: 781b ldrb r3, [r3, #0] 8002af2: b2db uxtb r3, r3 8002af4: 2b00 cmp r3, #0 8002af6: d100 bne.n 8002afa 8002af8: e176 b.n 8002de8 { return; } uint32_t now = HAL_GetTick(); 8002afa: f001 faed bl 80040d8 8002afe: 0003 movs r3, r0 8002b00: 60fb str r3, [r7, #12] uint32_t elapsed = now - feed_state_start_time; 8002b02: 4bc2 ldr r3, [pc, #776] @ (8002e0c ) 8002b04: 681b ldr r3, [r3, #0] 8002b06: 68fa ldr r2, [r7, #12] 8002b08: 1ad3 subs r3, r2, r3 8002b0a: 60bb str r3, [r7, #8] switch (feed_state) 8002b0c: 4bbe ldr r3, [pc, #760] @ (8002e08 ) 8002b0e: 781b ldrb r3, [r3, #0] 8002b10: b2db uxtb r3, r3 8002b12: 2b09 cmp r3, #9 8002b14: d900 bls.n 8002b18 8002b16: e163 b.n 8002de0 8002b18: 009a lsls r2, r3, #2 8002b1a: 4bbd ldr r3, [pc, #756] @ (8002e10 ) 8002b1c: 18d3 adds r3, r2, r3 8002b1e: 681b ldr r3, [r3, #0] 8002b20: 469f mov pc, r3 { case FEED_STATE_PEEL_FORWARD: // Peeling film while feed motor drives simultaneously if (elapsed >= feed_state_duration) 8002b22: 4bbc ldr r3, [pc, #752] @ (8002e14 ) 8002b24: 681b ldr r3, [r3, #0] 8002b26: 68ba ldr r2, [r7, #8] 8002b28: 429a cmp r2, r3 8002b2a: d200 bcs.n 8002b2e 8002b2c: e15e b.n 8002dec { peel_brake(); // Peel done, feed motor continues via PID 8002b2e: f7ff fd81 bl 8002634 feed_state = FEED_STATE_DRIVING; 8002b32: 4bb5 ldr r3, [pc, #724] @ (8002e08 ) 8002b34: 2204 movs r2, #4 8002b36: 701a strb r2, [r3, #0] feed_state_start_time = now; 8002b38: 4bb4 ldr r3, [pc, #720] @ (8002e0c ) 8002b3a: 68fa ldr r2, [r7, #12] 8002b3c: 601a str r2, [r3, #0] // feed_target_position and feed_timeout_time already set in start_feed } break; 8002b3e: e155 b.n 8002dec case FEED_STATE_UNPEEL: // Unpeeling film before backward drive if (elapsed >= feed_state_duration) 8002b40: 4bb4 ldr r3, [pc, #720] @ (8002e14 ) 8002b42: 681b ldr r3, [r3, #0] 8002b44: 68ba ldr r2, [r7, #8] 8002b46: 429a cmp r2, r3 8002b48: d200 bcs.n 8002b4c 8002b4a: e151 b.n 8002df0 { peel_brake(); 8002b4c: f7ff fd72 bl 8002634 // Start driving backward with backlash overshoot feed_state = FEED_STATE_DRIVING; 8002b50: 4bad ldr r3, [pc, #692] @ (8002e08 ) 8002b52: 2204 movs r2, #4 8002b54: 701a strb r2, [r3, #0] feed_state_start_time = now; 8002b56: 4bad ldr r3, [pc, #692] @ (8002e0c ) 8002b58: 68fa ldr r2, [r7, #12] 8002b5a: 601a str r2, [r3, #0] int16_t total_backward = feed_distance_tenths + BACKLASH_COMP_TENTH_MM; 8002b5c: 4bae ldr r3, [pc, #696] @ (8002e18 ) 8002b5e: 2200 movs r2, #0 8002b60: 5e9b ldrsh r3, [r3, r2] 8002b62: b29b uxth r3, r3 8002b64: 330a adds r3, #10 8002b66: b29a uxth r2, r3 8002b68: 1dbb adds r3, r7, #6 8002b6a: 801a strh r2, [r3, #0] feed_timeout_time = now + (total_backward * TIMEOUT_TIME_PER_TENTH_MM) + 500; 8002b6c: 1dbb adds r3, r7, #6 8002b6e: 2200 movs r2, #0 8002b70: 5e9a ldrsh r2, [r3, r2] 8002b72: 0013 movs r3, r2 8002b74: 009b lsls r3, r3, #2 8002b76: 189b adds r3, r3, r2 8002b78: 00db lsls r3, r3, #3 8002b7a: 001a movs r2, r3 8002b7c: 68fb ldr r3, [r7, #12] 8002b7e: 18d3 adds r3, r2, r3 8002b80: 33f5 adds r3, #245 @ 0xf5 8002b82: 33ff adds r3, #255 @ 0xff 8002b84: 001a movs r2, r3 8002b86: 4ba5 ldr r3, [pc, #660] @ (8002e1c ) 8002b88: 601a str r2, [r3, #0] feed_target_position = total_count - tenths_to_counts(total_backward); 8002b8a: 4ba5 ldr r3, [pc, #660] @ (8002e20 ) 8002b8c: 681c ldr r4, [r3, #0] 8002b8e: 1dbb adds r3, r7, #6 8002b90: 2200 movs r2, #0 8002b92: 5e9b ldrsh r3, [r3, r2] 8002b94: 0018 movs r0, r3 8002b96: f7ff fe9b bl 80028d0 8002b9a: 0003 movs r3, r0 8002b9c: 1ae2 subs r2, r4, r3 8002b9e: 4ba1 ldr r3, [pc, #644] @ (8002e24 ) 8002ba0: 601a str r2, [r3, #0] target_count = feed_target_position; 8002ba2: 4ba0 ldr r3, [pc, #640] @ (8002e24 ) 8002ba4: 681a ldr r2, [r3, #0] 8002ba6: 4ba0 ldr r3, [pc, #640] @ (8002e28 ) 8002ba8: 601a str r2, [r3, #0] } break; 8002baa: e121 b.n 8002df0 case FEED_STATE_DRIVING: // Check for position reached and stall detection { int32_t error = feed_target_position - total_count; 8002bac: 4b9d ldr r3, [pc, #628] @ (8002e24 ) 8002bae: 681a ldr r2, [r3, #0] 8002bb0: 4b9b ldr r3, [pc, #620] @ (8002e20 ) 8002bb2: 681b ldr r3, [r3, #0] 8002bb4: 1ad3 subs r3, r2, r3 8002bb6: 617b str r3, [r7, #20] if (error < 0) error = -error; 8002bb8: 697b ldr r3, [r7, #20] 8002bba: 2b00 cmp r3, #0 8002bbc: da02 bge.n 8002bc4 8002bbe: 697b ldr r3, [r7, #20] 8002bc0: 425b negs r3, r3 8002bc2: 617b str r3, [r7, #20] // Update stall detection stall_detection_update(total_count); 8002bc4: 4b96 ldr r3, [pc, #600] @ (8002e20 ) 8002bc6: 681b ldr r3, [r3, #0] 8002bc8: 0018 movs r0, r3 8002bca: f000 fa5b bl 8003084 // Check for stall and increase power if needed if (check_stall(total_count) && !stall_cooldown) 8002bce: 4b94 ldr r3, [pc, #592] @ (8002e20 ) 8002bd0: 681b ldr r3, [r3, #0] 8002bd2: 0018 movs r0, r3 8002bd4: f000 fa84 bl 80030e0 8002bd8: 1e03 subs r3, r0, #0 8002bda: d016 beq.n 8002c0a 8002bdc: 4b93 ldr r3, [pc, #588] @ (8002e2c ) 8002bde: 781b ldrb r3, [r3, #0] 8002be0: 2b00 cmp r3, #0 8002be2: d112 bne.n 8002c0a { current_drive_value += 3; 8002be4: 4b92 ldr r3, [pc, #584] @ (8002e30 ) 8002be6: 781b ldrb r3, [r3, #0] 8002be8: 3303 adds r3, #3 8002bea: b2da uxtb r2, r3 8002bec: 4b90 ldr r3, [pc, #576] @ (8002e30 ) 8002bee: 701a strb r2, [r3, #0] if (current_drive_value > 255) current_drive_value = 255; stall_cooldown = 1; 8002bf0: 4b8e ldr r3, [pc, #568] @ (8002e2c ) 8002bf2: 2201 movs r2, #1 8002bf4: 701a strb r2, [r3, #0] stall_cooldown_time = now; 8002bf6: 4b8f ldr r3, [pc, #572] @ (8002e34 ) 8002bf8: 68fa ldr r2, [r7, #12] 8002bfa: 601a str r2, [r3, #0] // If we're stalling a lot, mark as beefy tape if (current_drive_value > 200) 8002bfc: 4b8c ldr r3, [pc, #560] @ (8002e30 ) 8002bfe: 781b ldrb r3, [r3, #0] 8002c00: 2bc8 cmp r3, #200 @ 0xc8 8002c02: d902 bls.n 8002c0a { beefy_tape = 1; 8002c04: 4b8c ldr r3, [pc, #560] @ (8002e38 ) 8002c06: 2201 movs r2, #1 8002c08: 701a strb r2, [r3, #0] } } // Reset stall cooldown after 5ms if (stall_cooldown && (now - stall_cooldown_time) > 5) 8002c0a: 4b88 ldr r3, [pc, #544] @ (8002e2c ) 8002c0c: 781b ldrb r3, [r3, #0] 8002c0e: 2b00 cmp r3, #0 8002c10: d008 beq.n 8002c24 8002c12: 4b88 ldr r3, [pc, #544] @ (8002e34 ) 8002c14: 681b ldr r3, [r3, #0] 8002c16: 68fa ldr r2, [r7, #12] 8002c18: 1ad3 subs r3, r2, r3 8002c1a: 2b05 cmp r3, #5 8002c1c: d902 bls.n 8002c24 { stall_cooldown = 0; 8002c1e: 4b83 ldr r3, [pc, #524] @ (8002e2c ) 8002c20: 2200 movs r2, #0 8002c22: 701a strb r2, [r3, #0] } if (error < FEED_POSITION_TOLERANCE) 8002c24: 697b ldr r3, [r7, #20] 8002c26: 2b04 cmp r3, #4 8002c28: dc1d bgt.n 8002c66 { // Position reached stall_detection_init(); // Reset stall detection 8002c2a: f000 f9f7 bl 800301c if (!feed_direction) 8002c2e: 4b83 ldr r3, [pc, #524] @ (8002e3c ) 8002c30: 781b ldrb r3, [r3, #0] 8002c32: 2b00 cmp r3, #0 8002c34: d10d bne.n 8002c52 { // Backward feed: take up slack then do final approach feed_state = FEED_STATE_SLACK_REMOVAL; 8002c36: 4b74 ldr r3, [pc, #464] @ (8002e08 ) 8002c38: 2205 movs r2, #5 8002c3a: 701a strb r2, [r3, #0] feed_state_start_time = now; 8002c3c: 4b73 ldr r3, [pc, #460] @ (8002e0c ) 8002c3e: 68fa ldr r2, [r7, #12] 8002c40: 601a str r2, [r3, #0] feed_state_duration = BACKWARDS_FEED_FILM_SLACK_REMOVAL_TIME; 8002c42: 4b74 ldr r3, [pc, #464] @ (8002e14 ) 8002c44: 22af movs r2, #175 @ 0xaf 8002c46: 0052 lsls r2, r2, #1 8002c48: 601a str r2, [r3, #0] peel_motor(1); // Peel forward to take up slack 8002c4a: 2001 movs r0, #1 8002c4c: f7ff fcda bl 8002604 { // Timeout feed_state = FEED_STATE_TIMEOUT; } } break; 8002c50: e0d0 b.n 8002df4 feed_state = FEED_STATE_SETTLING; 8002c52: 4b6d ldr r3, [pc, #436] @ (8002e08 ) 8002c54: 2207 movs r2, #7 8002c56: 701a strb r2, [r3, #0] feed_state_start_time = now; 8002c58: 4b6c ldr r3, [pc, #432] @ (8002e0c ) 8002c5a: 68fa ldr r2, [r7, #12] 8002c5c: 601a str r2, [r3, #0] feed_state_duration = FEED_SETTLE_TIME; 8002c5e: 4b6d ldr r3, [pc, #436] @ (8002e14 ) 8002c60: 2232 movs r2, #50 @ 0x32 8002c62: 601a str r2, [r3, #0] break; 8002c64: e0c6 b.n 8002df4 else if (now > feed_timeout_time) 8002c66: 4b6d ldr r3, [pc, #436] @ (8002e1c ) 8002c68: 681b ldr r3, [r3, #0] 8002c6a: 68fa ldr r2, [r7, #12] 8002c6c: 429a cmp r2, r3 8002c6e: d800 bhi.n 8002c72 8002c70: e0c0 b.n 8002df4 feed_state = FEED_STATE_TIMEOUT; 8002c72: 4b65 ldr r3, [pc, #404] @ (8002e08 ) 8002c74: 2209 movs r2, #9 8002c76: 701a strb r2, [r3, #0] break; 8002c78: e0bc b.n 8002df4 case FEED_STATE_SLACK_REMOVAL: // Taking up film slack after backward movement if (elapsed >= feed_state_duration) 8002c7a: 4b66 ldr r3, [pc, #408] @ (8002e14 ) 8002c7c: 681b ldr r3, [r3, #0] 8002c7e: 68ba ldr r2, [r7, #8] 8002c80: 429a cmp r2, r3 8002c82: d200 bcs.n 8002c86 8002c84: e0b8 b.n 8002df8 { peel_brake(); 8002c86: f7ff fcd5 bl 8002634 // Final forward approach for backlash compensation feed_state = FEED_STATE_DRIVING_BACKLASH; 8002c8a: 4b5f ldr r3, [pc, #380] @ (8002e08 ) 8002c8c: 2206 movs r2, #6 8002c8e: 701a strb r2, [r3, #0] feed_state_start_time = now; 8002c90: 4b5e ldr r3, [pc, #376] @ (8002e0c ) 8002c92: 68fa ldr r2, [r7, #12] 8002c94: 601a str r2, [r3, #0] feed_timeout_time = now + (BACKLASH_COMP_TENTH_MM * TIMEOUT_TIME_PER_TENTH_MM) + 200; 8002c96: 68fb ldr r3, [r7, #12] 8002c98: 2296 movs r2, #150 @ 0x96 8002c9a: 0092 lsls r2, r2, #2 8002c9c: 189a adds r2, r3, r2 8002c9e: 4b5f ldr r3, [pc, #380] @ (8002e1c ) 8002ca0: 601a str r2, [r3, #0] // Move forward by backlash amount to final position feed_target_position = total_count + tenths_to_counts(BACKLASH_COMP_TENTH_MM); 8002ca2: 200a movs r0, #10 8002ca4: f7ff fe14 bl 80028d0 8002ca8: 0002 movs r2, r0 8002caa: 4b5d ldr r3, [pc, #372] @ (8002e20 ) 8002cac: 681b ldr r3, [r3, #0] 8002cae: 18d2 adds r2, r2, r3 8002cb0: 4b5c ldr r3, [pc, #368] @ (8002e24 ) 8002cb2: 601a str r2, [r3, #0] target_count = feed_target_position; 8002cb4: 4b5b ldr r3, [pc, #364] @ (8002e24 ) 8002cb6: 681a ldr r2, [r3, #0] 8002cb8: 4b5b ldr r3, [pc, #364] @ (8002e28 ) 8002cba: 601a str r2, [r3, #0] } break; 8002cbc: e09c b.n 8002df8 case FEED_STATE_DRIVING_BACKLASH: // Final forward approach after backward feed { int32_t error = feed_target_position - total_count; 8002cbe: 4b59 ldr r3, [pc, #356] @ (8002e24 ) 8002cc0: 681a ldr r2, [r3, #0] 8002cc2: 4b57 ldr r3, [pc, #348] @ (8002e20 ) 8002cc4: 681b ldr r3, [r3, #0] 8002cc6: 1ad3 subs r3, r2, r3 8002cc8: 613b str r3, [r7, #16] if (error < 0) error = -error; 8002cca: 693b ldr r3, [r7, #16] 8002ccc: 2b00 cmp r3, #0 8002cce: da02 bge.n 8002cd6 8002cd0: 693b ldr r3, [r7, #16] 8002cd2: 425b negs r3, r3 8002cd4: 613b str r3, [r7, #16] if (error < FEED_POSITION_TOLERANCE) 8002cd6: 693b ldr r3, [r7, #16] 8002cd8: 2b04 cmp r3, #4 8002cda: dc09 bgt.n 8002cf0 { feed_state = FEED_STATE_SETTLING; 8002cdc: 4b4a ldr r3, [pc, #296] @ (8002e08 ) 8002cde: 2207 movs r2, #7 8002ce0: 701a strb r2, [r3, #0] feed_state_start_time = now; 8002ce2: 4b4a ldr r3, [pc, #296] @ (8002e0c ) 8002ce4: 68fa ldr r2, [r7, #12] 8002ce6: 601a str r2, [r3, #0] feed_state_duration = FEED_SETTLE_TIME; 8002ce8: 4b4a ldr r3, [pc, #296] @ (8002e14 ) 8002cea: 2232 movs r2, #50 @ 0x32 8002cec: 601a str r2, [r3, #0] else if (now > feed_timeout_time) { feed_state = FEED_STATE_TIMEOUT; } } break; 8002cee: e085 b.n 8002dfc else if (now > feed_timeout_time) 8002cf0: 4b4a ldr r3, [pc, #296] @ (8002e1c ) 8002cf2: 681b ldr r3, [r3, #0] 8002cf4: 68fa ldr r2, [r7, #12] 8002cf6: 429a cmp r2, r3 8002cf8: d800 bhi.n 8002cfc 8002cfa: e07f b.n 8002dfc feed_state = FEED_STATE_TIMEOUT; 8002cfc: 4b42 ldr r3, [pc, #264] @ (8002e08 ) 8002cfe: 2209 movs r2, #9 8002d00: 701a strb r2, [r3, #0] break; 8002d02: e07b b.n 8002dfc case FEED_STATE_SETTLING: // Wait for position to settle if (elapsed >= feed_state_duration) 8002d04: 4b43 ldr r3, [pc, #268] @ (8002e14 ) 8002d06: 681b ldr r3, [r3, #0] 8002d08: 68ba ldr r2, [r7, #8] 8002d0a: 429a cmp r2, r3 8002d0c: d200 bcs.n 8002d10 8002d0e: e077 b.n 8002e00 { feed_state = FEED_STATE_COMPLETE; 8002d10: 4b3d ldr r3, [pc, #244] @ (8002e08 ) 8002d12: 2208 movs r2, #8 8002d14: 701a strb r2, [r3, #0] } break; 8002d16: e073 b.n 8002e00 case FEED_STATE_COMPLETE: feed_state = FEED_STATE_IDLE; 8002d18: 4b3b ldr r3, [pc, #236] @ (8002e08 ) 8002d1a: 2200 movs r2, #0 8002d1c: 701a strb r2, [r3, #0] feed_in_progress = 0; 8002d1e: 4b48 ldr r3, [pc, #288] @ (8002e40 ) 8002d20: 2200 movs r2, #0 8002d22: 701a strb r2, [r3, #0] last_feed_status = STATUS_OK; 8002d24: 4b47 ldr r3, [pc, #284] @ (8002e44 ) 8002d26: 2200 movs r2, #0 8002d28: 701a strb r2, [r3, #0] feed_just_completed = 1; 8002d2a: 4b47 ldr r3, [pc, #284] @ (8002e48 ) 8002d2c: 2201 movs r2, #1 8002d2e: 701a strb r2, [r3, #0] break; 8002d30: e067 b.n 8002e02 case FEED_STATE_TIMEOUT: // Handle timeout - could retry or fail if (feed_retry_count < FEED_RETRY_LIMIT) 8002d32: 4b46 ldr r3, [pc, #280] @ (8002e4c ) 8002d34: 781b ldrb r3, [r3, #0] 8002d36: 2b02 cmp r3, #2 8002d38: d843 bhi.n 8002dc2 { feed_retry_count++; 8002d3a: 4b44 ldr r3, [pc, #272] @ (8002e4c ) 8002d3c: 781b ldrb r3, [r3, #0] 8002d3e: 3301 adds r3, #1 8002d40: b2da uxtb r2, r3 8002d42: 4b42 ldr r3, [pc, #264] @ (8002e4c ) 8002d44: 701a strb r2, [r3, #0] // Move back slightly and retry target_count = total_count - tenths_to_counts(5); // Back up 0.5mm 8002d46: 4b36 ldr r3, [pc, #216] @ (8002e20 ) 8002d48: 681c ldr r4, [r3, #0] 8002d4a: 2005 movs r0, #5 8002d4c: f7ff fdc0 bl 80028d0 8002d50: 0003 movs r3, r0 8002d52: 1ae2 subs r2, r4, r3 8002d54: 4b34 ldr r3, [pc, #208] @ (8002e28 ) 8002d56: 601a str r2, [r3, #0] HAL_Delay(50); 8002d58: 2032 movs r0, #50 @ 0x32 8002d5a: f001 f9c7 bl 80040ec // Restart the feed if (feed_direction) 8002d5e: 4b37 ldr r3, [pc, #220] @ (8002e3c ) 8002d60: 781b ldrb r3, [r3, #0] 8002d62: 2b00 cmp r3, #0 8002d64: d016 beq.n 8002d94 { feed_state = FEED_STATE_PEEL_FORWARD; 8002d66: 4b28 ldr r3, [pc, #160] @ (8002e08 ) 8002d68: 2201 movs r2, #1 8002d6a: 701a strb r2, [r3, #0] feed_state_start_time = HAL_GetTick(); 8002d6c: f001 f9b4 bl 80040d8 8002d70: 0002 movs r2, r0 8002d72: 4b26 ldr r3, [pc, #152] @ (8002e0c ) 8002d74: 601a str r2, [r3, #0] feed_state_duration = feed_distance_tenths * PEEL_TIME_PER_TENTH_MM; 8002d76: 4b28 ldr r3, [pc, #160] @ (8002e18 ) 8002d78: 2200 movs r2, #0 8002d7a: 5e9b ldrsh r3, [r3, r2] 8002d7c: 001a movs r2, r3 8002d7e: 0013 movs r3, r2 8002d80: 00db lsls r3, r3, #3 8002d82: 189b adds r3, r3, r2 8002d84: 005b lsls r3, r3, #1 8002d86: 001a movs r2, r3 8002d88: 4b22 ldr r3, [pc, #136] @ (8002e14 ) 8002d8a: 601a str r2, [r3, #0] peel_motor(1); 8002d8c: 2001 movs r0, #1 8002d8e: f7ff fc39 bl 8002604 feed_in_progress = 0; last_feed_status = STATUS_COULDNT_REACH; feed_just_completed = 1; halt_all(); } break; 8002d92: e036 b.n 8002e02 feed_state = FEED_STATE_UNPEEL; 8002d94: 4b1c ldr r3, [pc, #112] @ (8002e08 ) 8002d96: 2203 movs r2, #3 8002d98: 701a strb r2, [r3, #0] feed_state_start_time = HAL_GetTick(); 8002d9a: f001 f99d bl 80040d8 8002d9e: 0002 movs r2, r0 8002da0: 4b1a ldr r3, [pc, #104] @ (8002e0c ) 8002da2: 601a str r2, [r3, #0] feed_state_duration = feed_distance_tenths * BACKWARDS_PEEL_TIME_PER_TENTH_MM; 8002da4: 4b1c ldr r3, [pc, #112] @ (8002e18 ) 8002da6: 2200 movs r2, #0 8002da8: 5e9b ldrsh r3, [r3, r2] 8002daa: 001a movs r2, r3 8002dac: 0013 movs r3, r2 8002dae: 011b lsls r3, r3, #4 8002db0: 1a9b subs r3, r3, r2 8002db2: 005b lsls r3, r3, #1 8002db4: 001a movs r2, r3 8002db6: 4b17 ldr r3, [pc, #92] @ (8002e14 ) 8002db8: 601a str r2, [r3, #0] peel_motor(0); 8002dba: 2000 movs r0, #0 8002dbc: f7ff fc22 bl 8002604 break; 8002dc0: e01f b.n 8002e02 feed_state = FEED_STATE_IDLE; 8002dc2: 4b11 ldr r3, [pc, #68] @ (8002e08 ) 8002dc4: 2200 movs r2, #0 8002dc6: 701a strb r2, [r3, #0] feed_in_progress = 0; 8002dc8: 4b1d ldr r3, [pc, #116] @ (8002e40 ) 8002dca: 2200 movs r2, #0 8002dcc: 701a strb r2, [r3, #0] last_feed_status = STATUS_COULDNT_REACH; 8002dce: 4b1d ldr r3, [pc, #116] @ (8002e44 ) 8002dd0: 2202 movs r2, #2 8002dd2: 701a strb r2, [r3, #0] feed_just_completed = 1; 8002dd4: 4b1c ldr r3, [pc, #112] @ (8002e48 ) 8002dd6: 2201 movs r2, #1 8002dd8: 701a strb r2, [r3, #0] halt_all(); 8002dda: f7ff fd09 bl 80027f0 break; 8002dde: e010 b.n 8002e02 default: feed_state = FEED_STATE_IDLE; 8002de0: 4b09 ldr r3, [pc, #36] @ (8002e08 ) 8002de2: 2200 movs r2, #0 8002de4: 701a strb r2, [r3, #0] break; 8002de6: e00c b.n 8002e02 return; 8002de8: 46c0 nop @ (mov r8, r8) 8002dea: e00a b.n 8002e02 break; 8002dec: 46c0 nop @ (mov r8, r8) 8002dee: e008 b.n 8002e02 break; 8002df0: 46c0 nop @ (mov r8, r8) 8002df2: e006 b.n 8002e02 break; 8002df4: 46c0 nop @ (mov r8, r8) 8002df6: e004 b.n 8002e02 break; 8002df8: 46c0 nop @ (mov r8, r8) 8002dfa: e002 b.n 8002e02 break; 8002dfc: 46c0 nop @ (mov r8, r8) 8002dfe: e000 b.n 8002e02 break; 8002e00: 46c0 nop @ (mov r8, r8) } } 8002e02: 46bd mov sp, r7 8002e04: b007 add sp, #28 8002e06: bd90 pop {r4, r7, pc} 8002e08: 200004bf .word 0x200004bf 8002e0c: 200004c0 .word 0x200004c0 8002e10: 08007d88 .word 0x08007d88 8002e14: 200004c4 .word 0x200004c4 8002e18: 200004cc .word 0x200004cc 8002e1c: 200004c8 .word 0x200004c8 8002e20: 20000484 .word 0x20000484 8002e24: 200004d0 .word 0x200004d0 8002e28: 20000488 .word 0x20000488 8002e2c: 20000544 .word 0x20000544 8002e30: 2000001e .word 0x2000001e 8002e34: 20000548 .word 0x20000548 8002e38: 200004d5 .word 0x200004d5 8002e3c: 2000001c .word 0x2000001c 8002e40: 200004bd .word 0x200004bd 8002e44: 200004bc .word 0x200004bc 8002e48: 200004be .word 0x200004be 8002e4c: 200004d4 .word 0x200004d4 08002e50 : // Check what type of tape is loaded (thick vs thin) void check_tape_loaded(void) { 8002e50: b580 push {r7, lr} 8002e52: b084 sub sp, #16 8002e54: af00 add r7, sp, #0 // Take up any backlash slack set_Feeder_PWM(250, 0); // Brief reverse 8002e56: 2100 movs r1, #0 8002e58: 20fa movs r0, #250 @ 0xfa 8002e5a: f7ff fb9f bl 800259c HAL_Delay(2); 8002e5e: 2002 movs r0, #2 8002e60: f001 f944 bl 80040ec set_Feeder_PWM(20, 0); 8002e64: 2100 movs r1, #0 8002e66: 2014 movs r0, #20 8002e68: f7ff fb98 bl 800259c HAL_Delay(100); 8002e6c: 2064 movs r0, #100 @ 0x64 8002e6e: f001 f93d bl 80040ec set_Feeder_PWM(0, 0); 8002e72: 2100 movs r1, #0 8002e74: 2000 movs r0, #0 8002e76: f7ff fb91 bl 800259c HAL_Delay(10); 8002e7a: 200a movs r0, #10 8002e7c: f001 f936 bl 80040ec // Find starting threshold of movement int32_t starting_count = total_count; 8002e80: 4b22 ldr r3, [pc, #136] @ (8002f0c ) 8002e82: 681b ldr r3, [r3, #0] 8002e84: 603b str r3, [r7, #0] int moved_at = 256; 8002e86: 2380 movs r3, #128 @ 0x80 8002e88: 005b lsls r3, r3, #1 8002e8a: 60fb str r3, [r7, #12] for (int pwm = 20; pwm < 255; pwm += 5) 8002e8c: 2314 movs r3, #20 8002e8e: 60bb str r3, [r7, #8] 8002e90: e01c b.n 8002ecc { set_Feeder_PWM(pwm, 0); // Drive backward 8002e92: 68bb ldr r3, [r7, #8] 8002e94: b29b uxth r3, r3 8002e96: 2100 movs r1, #0 8002e98: 0018 movs r0, r3 8002e9a: f7ff fb7f bl 800259c HAL_Delay(75); 8002e9e: 204b movs r0, #75 @ 0x4b 8002ea0: f001 f924 bl 80040ec int32_t diff = total_count - starting_count; 8002ea4: 4b19 ldr r3, [pc, #100] @ (8002f0c ) 8002ea6: 681a ldr r2, [r3, #0] 8002ea8: 683b ldr r3, [r7, #0] 8002eaa: 1ad3 subs r3, r2, r3 8002eac: 607b str r3, [r7, #4] if (diff < 0) diff = -diff; 8002eae: 687b ldr r3, [r7, #4] 8002eb0: 2b00 cmp r3, #0 8002eb2: da02 bge.n 8002eba 8002eb4: 687b ldr r3, [r7, #4] 8002eb6: 425b negs r3, r3 8002eb8: 607b str r3, [r7, #4] if (diff > 3) // Movement detected 8002eba: 687b ldr r3, [r7, #4] 8002ebc: 2b03 cmp r3, #3 8002ebe: dd02 ble.n 8002ec6 { moved_at = pwm; 8002ec0: 68bb ldr r3, [r7, #8] 8002ec2: 60fb str r3, [r7, #12] break; 8002ec4: e005 b.n 8002ed2 for (int pwm = 20; pwm < 255; pwm += 5) 8002ec6: 68bb ldr r3, [r7, #8] 8002ec8: 3305 adds r3, #5 8002eca: 60bb str r3, [r7, #8] 8002ecc: 68bb ldr r3, [r7, #8] 8002ece: 2bfe cmp r3, #254 @ 0xfe 8002ed0: dddf ble.n 8002e92 } } set_Feeder_PWM(0, 0); 8002ed2: 2100 movs r1, #0 8002ed4: 2000 movs r0, #0 8002ed6: f7ff fb61 bl 800259c HAL_Delay(10); 8002eda: 200a movs r0, #10 8002edc: f001 f906 bl 80040ec // Reset position pid_reset(&motor_pid); 8002ee0: 4b0b ldr r3, [pc, #44] @ (8002f10 ) 8002ee2: 0018 movs r0, r3 8002ee4: f7fd fc9a bl 800081c target_count = total_count; 8002ee8: 4b08 ldr r3, [pc, #32] @ (8002f0c ) 8002eea: 681a ldr r2, [r3, #0] 8002eec: 4b09 ldr r3, [pc, #36] @ (8002f14 ) 8002eee: 601a str r2, [r3, #0] if (moved_at > 140) 8002ef0: 68fb ldr r3, [r7, #12] 8002ef2: 2b8c cmp r3, #140 @ 0x8c 8002ef4: dd03 ble.n 8002efe { beefy_tape = 1; // Thick tape detected 8002ef6: 4b08 ldr r3, [pc, #32] @ (8002f18 ) 8002ef8: 2201 movs r2, #1 8002efa: 701a strb r2, [r3, #0] } else { beefy_tape = 0; } } 8002efc: e002 b.n 8002f04 beefy_tape = 0; 8002efe: 4b06 ldr r3, [pc, #24] @ (8002f18 ) 8002f00: 2200 movs r2, #0 8002f02: 701a strb r2, [r3, #0] } 8002f04: 46c0 nop @ (mov r8, r8) 8002f06: 46bd mov sp, r7 8002f08: b004 add sp, #16 8002f0a: bd80 pop {r7, pc} 8002f0c: 20000484 .word 0x20000484 8002f10: 2000048c .word 0x2000048c 8002f14: 20000488 .word 0x20000488 8002f18: 200004d5 .word 0x200004d5 08002f1c : // Handle vendor-specific options void handle_vendor_options(uint8_t *options, uint8_t *response) { 8002f1c: b580 push {r7, lr} 8002f1e: b08c sub sp, #48 @ 0x30 8002f20: af00 add r7, sp, #0 8002f22: 6078 str r0, [r7, #4] 8002f24: 6039 str r1, [r7, #0] uint8_t command = options[0]; 8002f26: 212f movs r1, #47 @ 0x2f 8002f28: 187b adds r3, r7, r1 8002f2a: 687a ldr r2, [r7, #4] 8002f2c: 7812 ldrb r2, [r2, #0] 8002f2e: 701a strb r2, [r3, #0] // Commands 0x00-0x0F: Get firmware version string in chunks if (command <= 0x0F) 8002f30: 000a movs r2, r1 8002f32: 18bb adds r3, r7, r2 8002f34: 781b ldrb r3, [r3, #0] 8002f36: 2b0f cmp r3, #15 8002f38: d82d bhi.n 8002f96 { size_t version_len = strlen(VERSION_STRING); 8002f3a: 2309 movs r3, #9 8002f3c: 61bb str r3, [r7, #24] size_t start_index = command * VENDOR_SPECIFIC_OPTIONS_LENGTH; 8002f3e: 18bb adds r3, r7, r2 8002f40: 781a ldrb r2, [r3, #0] 8002f42: 0013 movs r3, r2 8002f44: 009b lsls r3, r3, #2 8002f46: 189b adds r3, r3, r2 8002f48: 009b lsls r3, r3, #2 8002f4a: 617b str r3, [r7, #20] if (start_index < version_len) 8002f4c: 697a ldr r2, [r7, #20] 8002f4e: 69bb ldr r3, [r7, #24] 8002f50: 429a cmp r2, r3 8002f52: d219 bcs.n 8002f88 { size_t remaining = version_len - start_index; 8002f54: 69ba ldr r2, [r7, #24] 8002f56: 697b ldr r3, [r7, #20] 8002f58: 1ad3 subs r3, r2, r3 8002f5a: 613b str r3, [r7, #16] size_t copy_len = (remaining < VENDOR_SPECIFIC_OPTIONS_LENGTH) ? remaining : VENDOR_SPECIFIC_OPTIONS_LENGTH; 8002f5c: 693b ldr r3, [r7, #16] 8002f5e: 2b14 cmp r3, #20 8002f60: d900 bls.n 8002f64 8002f62: 2314 movs r3, #20 8002f64: 60fb str r3, [r7, #12] memcpy(response, VERSION_STRING + start_index, copy_len); 8002f66: 697a ldr r2, [r7, #20] 8002f68: 4b2b ldr r3, [pc, #172] @ (8003018 ) 8002f6a: 18d1 adds r1, r2, r3 8002f6c: 68fa ldr r2, [r7, #12] 8002f6e: 683b ldr r3, [r7, #0] 8002f70: 0018 movs r0, r3 8002f72: f004 fecb bl 8007d0c // Null-terminate if there's room if (copy_len < VENDOR_SPECIFIC_OPTIONS_LENGTH) 8002f76: 68fb ldr r3, [r7, #12] 8002f78: 2b13 cmp r3, #19 8002f7a: d847 bhi.n 800300c { response[copy_len] = '\0'; 8002f7c: 683a ldr r2, [r7, #0] 8002f7e: 68fb ldr r3, [r7, #12] 8002f80: 18d3 adds r3, r2, r3 8002f82: 2200 movs r2, #0 8002f84: 701a strb r2, [r3, #0] } else { memset(response, 0, VENDOR_SPECIFIC_OPTIONS_LENGTH); } return; 8002f86: e041 b.n 800300c memset(response, 0, VENDOR_SPECIFIC_OPTIONS_LENGTH); 8002f88: 683b ldr r3, [r7, #0] 8002f8a: 2214 movs r2, #20 8002f8c: 2100 movs r1, #0 8002f8e: 0018 movs r0, r3 8002f90: f004 fe90 bl 8007cb4 return; 8002f94: e03a b.n 800300c } switch (command) 8002f96: 232f movs r3, #47 @ 0x2f 8002f98: 18fb adds r3, r7, r3 8002f9a: 781b ldrb r3, [r3, #0] 8002f9c: 2b10 cmp r3, #16 8002f9e: d12e bne.n 8002ffe { case 0x10: { // LED control uint8_t led_mask = options[1]; 8002fa0: 212e movs r1, #46 @ 0x2e 8002fa2: 187b adds r3, r7, r1 8002fa4: 687a ldr r2, [r7, #4] 8002fa6: 7852 ldrb r2, [r2, #1] 8002fa8: 701a strb r2, [r3, #0] int blue = led_mask & 1; 8002faa: 187b adds r3, r7, r1 8002fac: 781b ldrb r3, [r3, #0] 8002fae: 2201 movs r2, #1 8002fb0: 4013 ands r3, r2 8002fb2: 62bb str r3, [r7, #40] @ 0x28 int green = (led_mask >> 1) & 1; 8002fb4: 187b adds r3, r7, r1 8002fb6: 781b ldrb r3, [r3, #0] 8002fb8: 085b lsrs r3, r3, #1 8002fba: b2db uxtb r3, r3 8002fbc: 001a movs r2, r3 8002fbe: 2301 movs r3, #1 8002fc0: 4013 ands r3, r2 8002fc2: 627b str r3, [r7, #36] @ 0x24 int red = (led_mask >> 2) & 1; 8002fc4: 187b adds r3, r7, r1 8002fc6: 781b ldrb r3, [r3, #0] 8002fc8: 089b lsrs r3, r3, #2 8002fca: b2db uxtb r3, r3 8002fcc: 001a movs r2, r3 8002fce: 2301 movs r3, #1 8002fd0: 4013 ands r3, r2 8002fd2: 623b str r3, [r7, #32] int set = (led_mask >> 3) & 1; 8002fd4: 187b adds r3, r7, r1 8002fd6: 781b ldrb r3, [r3, #0] 8002fd8: 08db lsrs r3, r3, #3 8002fda: b2db uxtb r3, r3 8002fdc: 001a movs r2, r3 8002fde: 2301 movs r3, #1 8002fe0: 4013 ands r3, r2 8002fe2: 61fb str r3, [r7, #28] if (set) 8002fe4: 69fb ldr r3, [r7, #28] 8002fe6: 2b00 cmp r3, #0 8002fe8: d012 beq.n 8003010 { set_LED(red, green, blue); 8002fea: 6a3b ldr r3, [r7, #32] 8002fec: b2db uxtb r3, r3 8002fee: 6a7a ldr r2, [r7, #36] @ 0x24 8002ff0: b2d1 uxtb r1, r2 8002ff2: 6aba ldr r2, [r7, #40] @ 0x28 8002ff4: b2d2 uxtb r2, r2 8002ff6: 0018 movs r0, r3 8002ff8: f7fe fdb8 bl 8001b6c } break; 8002ffc: e008 b.n 8003010 } default: // Unknown command, return zeros memset(response, 0, VENDOR_SPECIFIC_OPTIONS_LENGTH); 8002ffe: 683b ldr r3, [r7, #0] 8003000: 2214 movs r2, #20 8003002: 2100 movs r1, #0 8003004: 0018 movs r0, r3 8003006: f004 fe55 bl 8007cb4 break; 800300a: e002 b.n 8003012 return; 800300c: 46c0 nop @ (mov r8, r8) 800300e: e000 b.n 8003012 break; 8003010: 46c0 nop @ (mov r8, r8) } } 8003012: 46bd mov sp, r7 8003014: b00c add sp, #48 @ 0x30 8003016: bd80 pop {r7, pc} 8003018: 08007d4c .word 0x08007d4c 0800301c : // ============================================================================ // Stall Detection Functions // ============================================================================ void stall_detection_init(void) { 800301c: b580 push {r7, lr} 800301e: b082 sub sp, #8 8003020: af00 add r7, sp, #0 for (int i = 0; i < STALL_HISTORY_SIZE; i++) 8003022: 2300 movs r3, #0 8003024: 607b str r3, [r7, #4] 8003026: e007 b.n 8003038 { stall_history[i] = 0; 8003028: 4b10 ldr r3, [pc, #64] @ (800306c ) 800302a: 687a ldr r2, [r7, #4] 800302c: 0092 lsls r2, r2, #2 800302e: 2100 movs r1, #0 8003030: 50d1 str r1, [r2, r3] for (int i = 0; i < STALL_HISTORY_SIZE; i++) 8003032: 687b ldr r3, [r7, #4] 8003034: 3301 adds r3, #1 8003036: 607b str r3, [r7, #4] 8003038: 687b ldr r3, [r7, #4] 800303a: 2b13 cmp r3, #19 800303c: ddf4 ble.n 8003028 } stall_history_index = 0; 800303e: 4b0c ldr r3, [pc, #48] @ (8003070 ) 8003040: 2200 movs r2, #0 8003042: 701a strb r2, [r3, #0] last_stall_sample_time = 0; 8003044: 4b0b ldr r3, [pc, #44] @ (8003074 ) 8003046: 2200 movs r2, #0 8003048: 601a str r2, [r3, #0] stall_cooldown = 0; 800304a: 4b0b ldr r3, [pc, #44] @ (8003078 ) 800304c: 2200 movs r2, #0 800304e: 701a strb r2, [r3, #0] current_drive_value = beefy_tape ? 255 : 30; 8003050: 4b0a ldr r3, [pc, #40] @ (800307c ) 8003052: 781b ldrb r3, [r3, #0] 8003054: 2b00 cmp r3, #0 8003056: d001 beq.n 800305c 8003058: 22ff movs r2, #255 @ 0xff 800305a: e000 b.n 800305e 800305c: 221e movs r2, #30 800305e: 4b08 ldr r3, [pc, #32] @ (8003080 ) 8003060: 701a strb r2, [r3, #0] } 8003062: 46c0 nop @ (mov r8, r8) 8003064: 46bd mov sp, r7 8003066: b002 add sp, #8 8003068: bd80 pop {r7, pc} 800306a: 46c0 nop @ (mov r8, r8) 800306c: 200004ec .word 0x200004ec 8003070: 2000053c .word 0x2000053c 8003074: 20000540 .word 0x20000540 8003078: 20000544 .word 0x20000544 800307c: 200004d5 .word 0x200004d5 8003080: 2000001e .word 0x2000001e 08003084 : void stall_detection_update(int32_t current_tick) { 8003084: b580 push {r7, lr} 8003086: b084 sub sp, #16 8003088: af00 add r7, sp, #0 800308a: 6078 str r0, [r7, #4] uint32_t now = HAL_GetTick(); 800308c: f001 f824 bl 80040d8 8003090: 0003 movs r3, r0 8003092: 60fb str r3, [r7, #12] if ((now - last_stall_sample_time) >= STALL_SAMPLE_INTERVAL_MS) 8003094: 4b0f ldr r3, [pc, #60] @ (80030d4 ) 8003096: 681b ldr r3, [r3, #0] 8003098: 68fa ldr r2, [r7, #12] 800309a: 429a cmp r2, r3 800309c: d016 beq.n 80030cc { last_stall_sample_time = now; 800309e: 4b0d ldr r3, [pc, #52] @ (80030d4 ) 80030a0: 68fa ldr r2, [r7, #12] 80030a2: 601a str r2, [r3, #0] stall_history[stall_history_index] = current_tick; 80030a4: 4b0c ldr r3, [pc, #48] @ (80030d8 ) 80030a6: 781b ldrb r3, [r3, #0] 80030a8: 001a movs r2, r3 80030aa: 4b0c ldr r3, [pc, #48] @ (80030dc ) 80030ac: 0092 lsls r2, r2, #2 80030ae: 6879 ldr r1, [r7, #4] 80030b0: 50d1 str r1, [r2, r3] stall_history_index++; 80030b2: 4b09 ldr r3, [pc, #36] @ (80030d8 ) 80030b4: 781b ldrb r3, [r3, #0] 80030b6: 3301 adds r3, #1 80030b8: b2da uxtb r2, r3 80030ba: 4b07 ldr r3, [pc, #28] @ (80030d8 ) 80030bc: 701a strb r2, [r3, #0] if (stall_history_index >= STALL_HISTORY_SIZE) 80030be: 4b06 ldr r3, [pc, #24] @ (80030d8 ) 80030c0: 781b ldrb r3, [r3, #0] 80030c2: 2b13 cmp r3, #19 80030c4: d902 bls.n 80030cc { stall_history_index = 0; 80030c6: 4b04 ldr r3, [pc, #16] @ (80030d8 ) 80030c8: 2200 movs r2, #0 80030ca: 701a strb r2, [r3, #0] } } } 80030cc: 46c0 nop @ (mov r8, r8) 80030ce: 46bd mov sp, r7 80030d0: b004 add sp, #16 80030d2: bd80 pop {r7, pc} 80030d4: 20000540 .word 0x20000540 80030d8: 2000053c .word 0x2000053c 80030dc: 200004ec .word 0x200004ec 080030e0 : uint8_t check_stall(int32_t current_tick) { 80030e0: b580 push {r7, lr} 80030e2: b086 sub sp, #24 80030e4: af00 add r7, sp, #0 80030e6: 6078 str r0, [r7, #4] // Find min and max in history int32_t min_val = stall_history[0]; 80030e8: 4b1b ldr r3, [pc, #108] @ (8003158 ) 80030ea: 681b ldr r3, [r3, #0] 80030ec: 617b str r3, [r7, #20] int32_t max_val = stall_history[0]; 80030ee: 4b1a ldr r3, [pc, #104] @ (8003158 ) 80030f0: 681b ldr r3, [r3, #0] 80030f2: 613b str r3, [r7, #16] for (int i = 1; i < STALL_HISTORY_SIZE; i++) 80030f4: 2301 movs r3, #1 80030f6: 60fb str r3, [r7, #12] 80030f8: e01a b.n 8003130 { if (stall_history[i] < min_val) min_val = stall_history[i]; 80030fa: 4b17 ldr r3, [pc, #92] @ (8003158 ) 80030fc: 68fa ldr r2, [r7, #12] 80030fe: 0092 lsls r2, r2, #2 8003100: 58d3 ldr r3, [r2, r3] 8003102: 697a ldr r2, [r7, #20] 8003104: 429a cmp r2, r3 8003106: dd04 ble.n 8003112 8003108: 4b13 ldr r3, [pc, #76] @ (8003158 ) 800310a: 68fa ldr r2, [r7, #12] 800310c: 0092 lsls r2, r2, #2 800310e: 58d3 ldr r3, [r2, r3] 8003110: 617b str r3, [r7, #20] if (stall_history[i] > max_val) max_val = stall_history[i]; 8003112: 4b11 ldr r3, [pc, #68] @ (8003158 ) 8003114: 68fa ldr r2, [r7, #12] 8003116: 0092 lsls r2, r2, #2 8003118: 58d3 ldr r3, [r2, r3] 800311a: 693a ldr r2, [r7, #16] 800311c: 429a cmp r2, r3 800311e: da04 bge.n 800312a 8003120: 4b0d ldr r3, [pc, #52] @ (8003158 ) 8003122: 68fa ldr r2, [r7, #12] 8003124: 0092 lsls r2, r2, #2 8003126: 58d3 ldr r3, [r2, r3] 8003128: 613b str r3, [r7, #16] for (int i = 1; i < STALL_HISTORY_SIZE; i++) 800312a: 68fb ldr r3, [r7, #12] 800312c: 3301 adds r3, #1 800312e: 60fb str r3, [r7, #12] 8003130: 68fb ldr r3, [r7, #12] 8003132: 2b13 cmp r3, #19 8003134: dde1 ble.n 80030fa } int32_t delta = max_val - min_val; 8003136: 693a ldr r2, [r7, #16] 8003138: 697b ldr r3, [r7, #20] 800313a: 1ad3 subs r3, r2, r3 800313c: 60bb str r3, [r7, #8] return (delta <= STALL_THRESHOLD); 800313e: 68bb ldr r3, [r7, #8] 8003140: 2205 movs r2, #5 8003142: 0fd8 lsrs r0, r3, #31 8003144: 17d1 asrs r1, r2, #31 8003146: 429a cmp r2, r3 8003148: 4148 adcs r0, r1 800314a: 0003 movs r3, r0 800314c: b2db uxtb r3, r3 } 800314e: 0018 movs r0, r3 8003150: 46bd mov sp, r7 8003152: b006 add sp, #24 8003154: bd80 pop {r7, pc} 8003156: 46c0 nop @ (mov r8, r8) 8003158: 200004ec .word 0x200004ec 0800315c : // OneWire Functions (Bit-banging for DS2431 EEPROM) // ============================================================================ // Microsecond delay using DWT cycle counter or busy loop void onewire_delay_us(uint32_t us) { 800315c: b580 push {r7, lr} 800315e: b084 sub sp, #16 8003160: af00 add r7, sp, #0 8003162: 6078 str r0, [r7, #4] // Simple busy-wait delay - approximately calibrated for 48MHz volatile uint32_t count = us * 12; // Adjust multiplier as needed 8003164: 687a ldr r2, [r7, #4] 8003166: 0013 movs r3, r2 8003168: 005b lsls r3, r3, #1 800316a: 189b adds r3, r3, r2 800316c: 009b lsls r3, r3, #2 800316e: 60fb str r3, [r7, #12] while (count--) { __NOP(); } 8003170: e000 b.n 8003174 8003172: 46c0 nop @ (mov r8, r8) 8003174: 68fb ldr r3, [r7, #12] 8003176: 1e5a subs r2, r3, #1 8003178: 60fa str r2, [r7, #12] 800317a: 2b00 cmp r3, #0 800317c: d1f9 bne.n 8003172 } 800317e: 46c0 nop @ (mov r8, r8) 8003180: 46c0 nop @ (mov r8, r8) 8003182: 46bd mov sp, r7 8003184: b004 add sp, #16 8003186: bd80 pop {r7, pc} 08003188 : void onewire_set_output(void) { 8003188: b580 push {r7, lr} 800318a: b086 sub sp, #24 800318c: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 800318e: 1d3b adds r3, r7, #4 8003190: 0018 movs r0, r3 8003192: 2314 movs r3, #20 8003194: 001a movs r2, r3 8003196: 2100 movs r1, #0 8003198: f004 fd8c bl 8007cb4 GPIO_InitStruct.Pin = ONEWIRE_Pin; 800319c: 1d3b adds r3, r7, #4 800319e: 2280 movs r2, #128 @ 0x80 80031a0: 00d2 lsls r2, r2, #3 80031a2: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; // Open-drain for OneWire 80031a4: 1d3b adds r3, r7, #4 80031a6: 2211 movs r2, #17 80031a8: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 80031aa: 1d3b adds r3, r7, #4 80031ac: 2200 movs r2, #0 80031ae: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH; 80031b0: 1d3b adds r3, r7, #4 80031b2: 2202 movs r2, #2 80031b4: 60da str r2, [r3, #12] HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct); 80031b6: 1d3a adds r2, r7, #4 80031b8: 23a0 movs r3, #160 @ 0xa0 80031ba: 05db lsls r3, r3, #23 80031bc: 0011 movs r1, r2 80031be: 0018 movs r0, r3 80031c0: f001 fb08 bl 80047d4 } 80031c4: 46c0 nop @ (mov r8, r8) 80031c6: 46bd mov sp, r7 80031c8: b006 add sp, #24 80031ca: bd80 pop {r7, pc} 080031cc : void onewire_set_input(void) { 80031cc: b580 push {r7, lr} 80031ce: b086 sub sp, #24 80031d0: af00 add r7, sp, #0 GPIO_InitTypeDef GPIO_InitStruct = {0}; 80031d2: 1d3b adds r3, r7, #4 80031d4: 0018 movs r0, r3 80031d6: 2314 movs r3, #20 80031d8: 001a movs r2, r3 80031da: 2100 movs r1, #0 80031dc: f004 fd6a bl 8007cb4 GPIO_InitStruct.Pin = ONEWIRE_Pin; 80031e0: 1d3b adds r3, r7, #4 80031e2: 2280 movs r2, #128 @ 0x80 80031e4: 00d2 lsls r2, r2, #3 80031e6: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_INPUT; 80031e8: 1d3b adds r3, r7, #4 80031ea: 2200 movs r2, #0 80031ec: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_PULLUP; 80031ee: 1d3b adds r3, r7, #4 80031f0: 2201 movs r2, #1 80031f2: 609a str r2, [r3, #8] HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct); 80031f4: 1d3a adds r2, r7, #4 80031f6: 23a0 movs r3, #160 @ 0xa0 80031f8: 05db lsls r3, r3, #23 80031fa: 0011 movs r1, r2 80031fc: 0018 movs r0, r3 80031fe: f001 fae9 bl 80047d4 } 8003202: 46c0 nop @ (mov r8, r8) 8003204: 46bd mov sp, r7 8003206: b006 add sp, #24 8003208: bd80 pop {r7, pc} 0800320a : void onewire_write_low(void) { 800320a: b580 push {r7, lr} 800320c: af00 add r7, sp, #0 HAL_GPIO_WritePin(ONEWIRE_GPIO_Port, ONEWIRE_Pin, GPIO_PIN_RESET); 800320e: 2380 movs r3, #128 @ 0x80 8003210: 00d9 lsls r1, r3, #3 8003212: 23a0 movs r3, #160 @ 0xa0 8003214: 05db lsls r3, r3, #23 8003216: 2200 movs r2, #0 8003218: 0018 movs r0, r3 800321a: f001 fc6a bl 8004af2 } 800321e: 46c0 nop @ (mov r8, r8) 8003220: 46bd mov sp, r7 8003222: bd80 pop {r7, pc} 08003224 : void onewire_write_high(void) { 8003224: b580 push {r7, lr} 8003226: af00 add r7, sp, #0 HAL_GPIO_WritePin(ONEWIRE_GPIO_Port, ONEWIRE_Pin, GPIO_PIN_SET); 8003228: 2380 movs r3, #128 @ 0x80 800322a: 00d9 lsls r1, r3, #3 800322c: 23a0 movs r3, #160 @ 0xa0 800322e: 05db lsls r3, r3, #23 8003230: 2201 movs r2, #1 8003232: 0018 movs r0, r3 8003234: f001 fc5d bl 8004af2 } 8003238: 46c0 nop @ (mov r8, r8) 800323a: 46bd mov sp, r7 800323c: bd80 pop {r7, pc} 0800323e : uint8_t onewire_read_bit(void) { 800323e: b580 push {r7, lr} 8003240: af00 add r7, sp, #0 return HAL_GPIO_ReadPin(ONEWIRE_GPIO_Port, ONEWIRE_Pin); 8003242: 2380 movs r3, #128 @ 0x80 8003244: 00da lsls r2, r3, #3 8003246: 23a0 movs r3, #160 @ 0xa0 8003248: 05db lsls r3, r3, #23 800324a: 0011 movs r1, r2 800324c: 0018 movs r0, r3 800324e: f001 fc33 bl 8004ab8 8003252: 0003 movs r3, r0 } 8003254: 0018 movs r0, r3 8003256: 46bd mov sp, r7 8003258: bd80 pop {r7, pc} 0800325a : // Reset pulse - returns 1 if device present, 0 if not uint8_t onewire_reset(void) { 800325a: b580 push {r7, lr} 800325c: b082 sub sp, #8 800325e: af00 add r7, sp, #0 uint8_t presence; onewire_set_output(); 8003260: f7ff ff92 bl 8003188 onewire_write_low(); 8003264: f7ff ffd1 bl 800320a onewire_delay_us(ONEWIRE_DELAY_H); // 480us 8003268: 23f0 movs r3, #240 @ 0xf0 800326a: 005b lsls r3, r3, #1 800326c: 0018 movs r0, r3 800326e: f7ff ff75 bl 800315c onewire_set_input(); 8003272: f7ff ffab bl 80031cc onewire_delay_us(ONEWIRE_DELAY_I); // 70us 8003276: 2046 movs r0, #70 @ 0x46 8003278: f7ff ff70 bl 800315c presence = !onewire_read_bit(); // Device pulls low if present 800327c: f7ff ffdf bl 800323e 8003280: 0003 movs r3, r0 8003282: 425a negs r2, r3 8003284: 4153 adcs r3, r2 8003286: b2da uxtb r2, r3 8003288: 1dfb adds r3, r7, #7 800328a: 701a strb r2, [r3, #0] onewire_delay_us(ONEWIRE_DELAY_J); // 410us 800328c: 23cd movs r3, #205 @ 0xcd 800328e: 005b lsls r3, r3, #1 8003290: 0018 movs r0, r3 8003292: f7ff ff63 bl 800315c return presence; 8003296: 1dfb adds r3, r7, #7 8003298: 781b ldrb r3, [r3, #0] } 800329a: 0018 movs r0, r3 800329c: 46bd mov sp, r7 800329e: b002 add sp, #8 80032a0: bd80 pop {r7, pc} 080032a2 : void onewire_write_bit(uint8_t bit) { 80032a2: b580 push {r7, lr} 80032a4: b082 sub sp, #8 80032a6: af00 add r7, sp, #0 80032a8: 0002 movs r2, r0 80032aa: 1dfb adds r3, r7, #7 80032ac: 701a strb r2, [r3, #0] onewire_set_output(); 80032ae: f7ff ff6b bl 8003188 if (bit) 80032b2: 1dfb adds r3, r7, #7 80032b4: 781b ldrb r3, [r3, #0] 80032b6: 2b00 cmp r3, #0 80032b8: d00a beq.n 80032d0 { // Write 1: pull low briefly, then release onewire_write_low(); 80032ba: f7ff ffa6 bl 800320a onewire_delay_us(ONEWIRE_DELAY_A); // 6us 80032be: 2006 movs r0, #6 80032c0: f7ff ff4c bl 800315c onewire_write_high(); 80032c4: f7ff ffae bl 8003224 onewire_delay_us(ONEWIRE_DELAY_B); // 64us 80032c8: 2040 movs r0, #64 @ 0x40 80032ca: f7ff ff47 bl 800315c onewire_write_low(); onewire_delay_us(ONEWIRE_DELAY_C); // 60us onewire_write_high(); onewire_delay_us(ONEWIRE_DELAY_D); // 10us } } 80032ce: e009 b.n 80032e4 onewire_write_low(); 80032d0: f7ff ff9b bl 800320a onewire_delay_us(ONEWIRE_DELAY_C); // 60us 80032d4: 203c movs r0, #60 @ 0x3c 80032d6: f7ff ff41 bl 800315c onewire_write_high(); 80032da: f7ff ffa3 bl 8003224 onewire_delay_us(ONEWIRE_DELAY_D); // 10us 80032de: 200a movs r0, #10 80032e0: f7ff ff3c bl 800315c } 80032e4: 46c0 nop @ (mov r8, r8) 80032e6: 46bd mov sp, r7 80032e8: b002 add sp, #8 80032ea: bd80 pop {r7, pc} 080032ec : uint8_t onewire_read_bit_slot(void) { 80032ec: b590 push {r4, r7, lr} 80032ee: b083 sub sp, #12 80032f0: af00 add r7, sp, #0 uint8_t bit; onewire_set_output(); 80032f2: f7ff ff49 bl 8003188 onewire_write_low(); 80032f6: f7ff ff88 bl 800320a onewire_delay_us(ONEWIRE_DELAY_A); // 6us 80032fa: 2006 movs r0, #6 80032fc: f7ff ff2e bl 800315c onewire_set_input(); 8003300: f7ff ff64 bl 80031cc onewire_delay_us(ONEWIRE_DELAY_E); // 9us 8003304: 2009 movs r0, #9 8003306: f7ff ff29 bl 800315c bit = onewire_read_bit(); 800330a: 1dfc adds r4, r7, #7 800330c: f7ff ff97 bl 800323e 8003310: 0003 movs r3, r0 8003312: 7023 strb r3, [r4, #0] onewire_delay_us(ONEWIRE_DELAY_F); // 55us 8003314: 2037 movs r0, #55 @ 0x37 8003316: f7ff ff21 bl 800315c return bit; 800331a: 1dfb adds r3, r7, #7 800331c: 781b ldrb r3, [r3, #0] } 800331e: 0018 movs r0, r3 8003320: 46bd mov sp, r7 8003322: b003 add sp, #12 8003324: bd90 pop {r4, r7, pc} 08003326 : void onewire_write_byte(uint8_t byte) { 8003326: b580 push {r7, lr} 8003328: b084 sub sp, #16 800332a: af00 add r7, sp, #0 800332c: 0002 movs r2, r0 800332e: 1dfb adds r3, r7, #7 8003330: 701a strb r2, [r3, #0] for (int i = 0; i < 8; i++) 8003332: 2300 movs r3, #0 8003334: 60fb str r3, [r7, #12] 8003336: e00f b.n 8003358 { onewire_write_bit(byte & 0x01); 8003338: 1dfb adds r3, r7, #7 800333a: 781b ldrb r3, [r3, #0] 800333c: 2201 movs r2, #1 800333e: 4013 ands r3, r2 8003340: b2db uxtb r3, r3 8003342: 0018 movs r0, r3 8003344: f7ff ffad bl 80032a2 byte >>= 1; 8003348: 1dfb adds r3, r7, #7 800334a: 1dfa adds r2, r7, #7 800334c: 7812 ldrb r2, [r2, #0] 800334e: 0852 lsrs r2, r2, #1 8003350: 701a strb r2, [r3, #0] for (int i = 0; i < 8; i++) 8003352: 68fb ldr r3, [r7, #12] 8003354: 3301 adds r3, #1 8003356: 60fb str r3, [r7, #12] 8003358: 68fb ldr r3, [r7, #12] 800335a: 2b07 cmp r3, #7 800335c: ddec ble.n 8003338 } } 800335e: 46c0 nop @ (mov r8, r8) 8003360: 46c0 nop @ (mov r8, r8) 8003362: 46bd mov sp, r7 8003364: b004 add sp, #16 8003366: bd80 pop {r7, pc} 08003368 : uint8_t onewire_read_byte(void) { 8003368: b580 push {r7, lr} 800336a: b082 sub sp, #8 800336c: af00 add r7, sp, #0 uint8_t byte = 0; 800336e: 1dfb adds r3, r7, #7 8003370: 2200 movs r2, #0 8003372: 701a strb r2, [r3, #0] for (int i = 0; i < 8; i++) 8003374: 2300 movs r3, #0 8003376: 603b str r3, [r7, #0] 8003378: e012 b.n 80033a0 { byte >>= 1; 800337a: 1dfb adds r3, r7, #7 800337c: 1dfa adds r2, r7, #7 800337e: 7812 ldrb r2, [r2, #0] 8003380: 0852 lsrs r2, r2, #1 8003382: 701a strb r2, [r3, #0] if (onewire_read_bit_slot()) 8003384: f7ff ffb2 bl 80032ec 8003388: 1e03 subs r3, r0, #0 800338a: d006 beq.n 800339a { byte |= 0x80; 800338c: 1dfb adds r3, r7, #7 800338e: 1dfa adds r2, r7, #7 8003390: 7812 ldrb r2, [r2, #0] 8003392: 2180 movs r1, #128 @ 0x80 8003394: 4249 negs r1, r1 8003396: 430a orrs r2, r1 8003398: 701a strb r2, [r3, #0] for (int i = 0; i < 8; i++) 800339a: 683b ldr r3, [r7, #0] 800339c: 3301 adds r3, #1 800339e: 603b str r3, [r7, #0] 80033a0: 683b ldr r3, [r7, #0] 80033a2: 2b07 cmp r3, #7 80033a4: dde9 ble.n 800337a } } return byte; 80033a6: 1dfb adds r3, r7, #7 80033a8: 781b ldrb r3, [r3, #0] } 80033aa: 0018 movs r0, r3 80033ac: 46bd mov sp, r7 80033ae: b002 add sp, #8 80033b0: bd80 pop {r7, pc} 080033b2 : // Read floor address from DS2431 EEPROM uint8_t read_floor_address(void) { 80033b2: b590 push {r4, r7, lr} 80033b4: b083 sub sp, #12 80033b6: af00 add r7, sp, #0 \details Disables IRQ interrupts by setting special-purpose register PRIMASK. Can only be executed in Privileged modes. */ __STATIC_FORCEINLINE void __disable_irq(void) { __ASM volatile ("cpsid i" : : : "memory"); 80033b8: b672 cpsid i } 80033ba: 46c0 nop @ (mov r8, r8) // Disable interrupts for timing-critical OneWire __disable_irq(); if (!onewire_reset()) 80033bc: f7ff ff4d bl 800325a 80033c0: 1e03 subs r3, r0, #0 80033c2: d103 bne.n 80033cc __ASM volatile ("cpsie i" : : : "memory"); 80033c4: b662 cpsie i } 80033c6: 46c0 nop @ (mov r8, r8) { __enable_irq(); return FLOOR_ADDRESS_NOT_DETECTED; 80033c8: 23ff movs r3, #255 @ 0xff 80033ca: e014 b.n 80033f6 } // Skip ROM (only one device on bus) onewire_write_byte(DS2431_SKIP_ROM); 80033cc: 20cc movs r0, #204 @ 0xcc 80033ce: f7ff ffaa bl 8003326 // Read Memory command onewire_write_byte(DS2431_READ_MEMORY); 80033d2: 20f0 movs r0, #240 @ 0xf0 80033d4: f7ff ffa7 bl 8003326 // Address (2 bytes, LSB first) onewire_write_byte(FLOOR_ADDRESS_LOCATION & 0xFF); 80033d8: 2000 movs r0, #0 80033da: f7ff ffa4 bl 8003326 onewire_write_byte((FLOOR_ADDRESS_LOCATION >> 8) & 0xFF); 80033de: 2000 movs r0, #0 80033e0: f7ff ffa1 bl 8003326 // Read the data byte uint8_t address = onewire_read_byte(); 80033e4: 1dfc adds r4, r7, #7 80033e6: f7ff ffbf bl 8003368 80033ea: 0003 movs r3, r0 80033ec: 7023 strb r3, [r4, #0] __ASM volatile ("cpsie i" : : : "memory"); 80033ee: b662 cpsie i } 80033f0: 46c0 nop @ (mov r8, r8) __enable_irq(); return address; 80033f2: 1dfb adds r3, r7, #7 80033f4: 781b ldrb r3, [r3, #0] } 80033f6: 0018 movs r0, r3 80033f8: 46bd mov sp, r7 80033fa: b003 add sp, #12 80033fc: bd90 pop {r4, r7, pc} 080033fe : // Write floor address to DS2431 EEPROM uint8_t write_floor_address(uint8_t address) { 80033fe: b5b0 push {r4, r5, r7, lr} 8003400: b086 sub sp, #24 8003402: af00 add r7, sp, #0 8003404: 0002 movs r2, r0 8003406: 1dfb adds r3, r7, #7 8003408: 701a strb r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 800340a: b672 cpsid i } 800340c: 46c0 nop @ (mov r8, r8) // Disable interrupts for timing-critical OneWire __disable_irq(); if (!onewire_reset()) 800340e: f7ff ff24 bl 800325a 8003412: 1e03 subs r3, r0, #0 8003414: d103 bne.n 800341e __ASM volatile ("cpsie i" : : : "memory"); 8003416: b662 cpsie i } 8003418: 46c0 nop @ (mov r8, r8) { __enable_irq(); return 0; // Device not present 800341a: 2300 movs r3, #0 800341c: e08d b.n 800353a } // Skip ROM onewire_write_byte(DS2431_SKIP_ROM); 800341e: 20cc movs r0, #204 @ 0xcc 8003420: f7ff ff81 bl 8003326 // Write Scratchpad command onewire_write_byte(DS2431_WRITE_SCRATCHPAD); 8003424: 200f movs r0, #15 8003426: f7ff ff7e bl 8003326 // Address (2 bytes, LSB first) onewire_write_byte(FLOOR_ADDRESS_LOCATION & 0xFF); 800342a: 2000 movs r0, #0 800342c: f7ff ff7b bl 8003326 onewire_write_byte((FLOOR_ADDRESS_LOCATION >> 8) & 0xFF); 8003430: 2000 movs r0, #0 8003432: f7ff ff78 bl 8003326 // Write the data (8 bytes for DS2431, we only need 1) onewire_write_byte(address); 8003436: 1dfb adds r3, r7, #7 8003438: 781b ldrb r3, [r3, #0] 800343a: 0018 movs r0, r3 800343c: f7ff ff73 bl 8003326 for (int i = 1; i < 8; i++) 8003440: 2301 movs r3, #1 8003442: 617b str r3, [r7, #20] 8003444: e005 b.n 8003452 { onewire_write_byte(0xFF); // Pad with 0xFF 8003446: 20ff movs r0, #255 @ 0xff 8003448: f7ff ff6d bl 8003326 for (int i = 1; i < 8; i++) 800344c: 697b ldr r3, [r7, #20] 800344e: 3301 adds r3, #1 8003450: 617b str r3, [r7, #20] 8003452: 697b ldr r3, [r7, #20] 8003454: 2b07 cmp r3, #7 8003456: ddf6 ble.n 8003446 } // Small delay onewire_delay_us(100); 8003458: 2064 movs r0, #100 @ 0x64 800345a: f7ff fe7f bl 800315c // Reset for next command if (!onewire_reset()) 800345e: f7ff fefc bl 800325a 8003462: 1e03 subs r3, r0, #0 8003464: d103 bne.n 800346e __ASM volatile ("cpsie i" : : : "memory"); 8003466: b662 cpsie i } 8003468: 46c0 nop @ (mov r8, r8) { __enable_irq(); return 0; 800346a: 2300 movs r3, #0 800346c: e065 b.n 800353a } // Skip ROM onewire_write_byte(DS2431_SKIP_ROM); 800346e: 20cc movs r0, #204 @ 0xcc 8003470: f7ff ff59 bl 8003326 // Read Scratchpad to get authorization bytes onewire_write_byte(DS2431_READ_SCRATCHPAD); 8003474: 20aa movs r0, #170 @ 0xaa 8003476: f7ff ff56 bl 8003326 uint8_t ta1 = onewire_read_byte(); // Target address 1 800347a: 230f movs r3, #15 800347c: 18fc adds r4, r7, r3 800347e: f7ff ff73 bl 8003368 8003482: 0003 movs r3, r0 8003484: 7023 strb r3, [r4, #0] uint8_t ta2 = onewire_read_byte(); // Target address 2 8003486: 230e movs r3, #14 8003488: 18fc adds r4, r7, r3 800348a: f7ff ff6d bl 8003368 800348e: 0003 movs r3, r0 8003490: 7023 strb r3, [r4, #0] uint8_t es = onewire_read_byte(); // E/S register 8003492: 230d movs r3, #13 8003494: 18fc adds r4, r7, r3 8003496: f7ff ff67 bl 8003368 800349a: 0003 movs r3, r0 800349c: 7023 strb r3, [r4, #0] // Read back data to verify (8 bytes) uint8_t verify = onewire_read_byte(); 800349e: 250c movs r5, #12 80034a0: 197c adds r4, r7, r5 80034a2: f7ff ff61 bl 8003368 80034a6: 0003 movs r3, r0 80034a8: 7023 strb r3, [r4, #0] if (verify != address) 80034aa: 197a adds r2, r7, r5 80034ac: 1dfb adds r3, r7, #7 80034ae: 7812 ldrb r2, [r2, #0] 80034b0: 781b ldrb r3, [r3, #0] 80034b2: 429a cmp r2, r3 80034b4: d003 beq.n 80034be __ASM volatile ("cpsie i" : : : "memory"); 80034b6: b662 cpsie i } 80034b8: 46c0 nop @ (mov r8, r8) { __enable_irq(); return 0; // Scratchpad write failed 80034ba: 2300 movs r3, #0 80034bc: e03d b.n 800353a } // Skip remaining bytes for (int i = 1; i < 8; i++) 80034be: 2301 movs r3, #1 80034c0: 613b str r3, [r7, #16] 80034c2: e004 b.n 80034ce { onewire_read_byte(); 80034c4: f7ff ff50 bl 8003368 for (int i = 1; i < 8; i++) 80034c8: 693b ldr r3, [r7, #16] 80034ca: 3301 adds r3, #1 80034cc: 613b str r3, [r7, #16] 80034ce: 693b ldr r3, [r7, #16] 80034d0: 2b07 cmp r3, #7 80034d2: ddf7 ble.n 80034c4 } // Reset for copy command if (!onewire_reset()) 80034d4: f7ff fec1 bl 800325a 80034d8: 1e03 subs r3, r0, #0 80034da: d103 bne.n 80034e4 __ASM volatile ("cpsie i" : : : "memory"); 80034dc: b662 cpsie i } 80034de: 46c0 nop @ (mov r8, r8) { __enable_irq(); return 0; 80034e0: 2300 movs r3, #0 80034e2: e02a b.n 800353a } // Skip ROM onewire_write_byte(DS2431_SKIP_ROM); 80034e4: 20cc movs r0, #204 @ 0xcc 80034e6: f7ff ff1e bl 8003326 // Copy Scratchpad command onewire_write_byte(DS2431_COPY_SCRATCHPAD); 80034ea: 2055 movs r0, #85 @ 0x55 80034ec: f7ff ff1b bl 8003326 // Send authorization bytes onewire_write_byte(ta1); 80034f0: 230f movs r3, #15 80034f2: 18fb adds r3, r7, r3 80034f4: 781b ldrb r3, [r3, #0] 80034f6: 0018 movs r0, r3 80034f8: f7ff ff15 bl 8003326 onewire_write_byte(ta2); 80034fc: 230e movs r3, #14 80034fe: 18fb adds r3, r7, r3 8003500: 781b ldrb r3, [r3, #0] 8003502: 0018 movs r0, r3 8003504: f7ff ff0f bl 8003326 onewire_write_byte(es); 8003508: 230d movs r3, #13 800350a: 18fb adds r3, r7, r3 800350c: 781b ldrb r3, [r3, #0] 800350e: 0018 movs r0, r3 8003510: f7ff ff09 bl 8003326 __ASM volatile ("cpsie i" : : : "memory"); 8003514: b662 cpsie i } 8003516: 46c0 nop @ (mov r8, r8) __enable_irq(); // Wait for copy to complete (10ms typical for EEPROM) HAL_Delay(15); 8003518: 200f movs r0, #15 800351a: f000 fde7 bl 80040ec // Verify by reading back uint8_t read_back = read_floor_address(); 800351e: 250b movs r5, #11 8003520: 197c adds r4, r7, r5 8003522: f7ff ff46 bl 80033b2 8003526: 0003 movs r3, r0 8003528: 7023 strb r3, [r4, #0] return (read_back == address) ? 1 : 0; 800352a: 197a adds r2, r7, r5 800352c: 1dfb adds r3, r7, #7 800352e: 7812 ldrb r2, [r2, #0] 8003530: 781b ldrb r3, [r3, #0] 8003532: 1ad3 subs r3, r2, r3 8003534: 425a negs r2, r3 8003536: 4153 adcs r3, r2 8003538: b2db uxtb r3, r3 } 800353a: 0018 movs r0, r3 800353c: 46bd mov sp, r7 800353e: b006 add sp, #24 8003540: bdb0 pop {r4, r5, r7, pc} 08003542 : // Debug Output Functions (lightweight, no printf/snprintf) // ============================================================================ // Convert int32 to decimal string, returns length written uint8_t debug_itoa(int32_t val, char *buf) { 8003542: b580 push {r7, lr} 8003544: b086 sub sp, #24 8003546: af00 add r7, sp, #0 8003548: 6078 str r0, [r7, #4] 800354a: 6039 str r1, [r7, #0] char tmp[12]; uint8_t i = 0, len = 0; 800354c: 2317 movs r3, #23 800354e: 18fb adds r3, r7, r3 8003550: 2200 movs r2, #0 8003552: 701a strb r2, [r3, #0] 8003554: 2316 movs r3, #22 8003556: 18fb adds r3, r7, r3 8003558: 2200 movs r2, #0 800355a: 701a strb r2, [r3, #0] uint8_t neg = 0; 800355c: 2115 movs r1, #21 800355e: 187b adds r3, r7, r1 8003560: 2200 movs r2, #0 8003562: 701a strb r2, [r3, #0] if (val < 0) { neg = 1; val = -val; } 8003564: 687b ldr r3, [r7, #4] 8003566: 2b00 cmp r3, #0 8003568: da05 bge.n 8003576 800356a: 187b adds r3, r7, r1 800356c: 2201 movs r2, #1 800356e: 701a strb r2, [r3, #0] 8003570: 687b ldr r3, [r7, #4] 8003572: 425b negs r3, r3 8003574: 607b str r3, [r7, #4] if (val == 0) { tmp[i++] = '0'; } 8003576: 687b ldr r3, [r7, #4] 8003578: 2b00 cmp r3, #0 800357a: d126 bne.n 80035ca 800357c: 2217 movs r2, #23 800357e: 18bb adds r3, r7, r2 8003580: 781b ldrb r3, [r3, #0] 8003582: 18ba adds r2, r7, r2 8003584: 1c59 adds r1, r3, #1 8003586: 7011 strb r1, [r2, #0] 8003588: 001a movs r2, r3 800358a: 2308 movs r3, #8 800358c: 18fb adds r3, r7, r3 800358e: 2130 movs r1, #48 @ 0x30 8003590: 5499 strb r1, [r3, r2] 8003592: e01d b.n 80035d0 else { while (val > 0) { tmp[i++] = '0' + (val % 10); val /= 10; } } 8003594: 687b ldr r3, [r7, #4] 8003596: 210a movs r1, #10 8003598: 0018 movs r0, r3 800359a: f7fc ff25 bl 80003e8 <__aeabi_idivmod> 800359e: 000b movs r3, r1 80035a0: b2da uxtb r2, r3 80035a2: 2117 movs r1, #23 80035a4: 187b adds r3, r7, r1 80035a6: 781b ldrb r3, [r3, #0] 80035a8: 1879 adds r1, r7, r1 80035aa: 1c58 adds r0, r3, #1 80035ac: 7008 strb r0, [r1, #0] 80035ae: 0019 movs r1, r3 80035b0: 0013 movs r3, r2 80035b2: 3330 adds r3, #48 @ 0x30 80035b4: b2da uxtb r2, r3 80035b6: 2308 movs r3, #8 80035b8: 18fb adds r3, r7, r3 80035ba: 545a strb r2, [r3, r1] 80035bc: 687b ldr r3, [r7, #4] 80035be: 210a movs r1, #10 80035c0: 0018 movs r0, r3 80035c2: f7fc fe2b bl 800021c <__divsi3> 80035c6: 0003 movs r3, r0 80035c8: 607b str r3, [r7, #4] 80035ca: 687b ldr r3, [r7, #4] 80035cc: 2b00 cmp r3, #0 80035ce: dce1 bgt.n 8003594 if (neg) { *buf++ = '-'; len++; } 80035d0: 2315 movs r3, #21 80035d2: 18fb adds r3, r7, r3 80035d4: 781b ldrb r3, [r3, #0] 80035d6: 2b00 cmp r3, #0 80035d8: d020 beq.n 800361c 80035da: 683b ldr r3, [r7, #0] 80035dc: 1c5a adds r2, r3, #1 80035de: 603a str r2, [r7, #0] 80035e0: 222d movs r2, #45 @ 0x2d 80035e2: 701a strb r2, [r3, #0] 80035e4: 2116 movs r1, #22 80035e6: 187b adds r3, r7, r1 80035e8: 781a ldrb r2, [r3, #0] 80035ea: 187b adds r3, r7, r1 80035ec: 3201 adds r2, #1 80035ee: 701a strb r2, [r3, #0] while (i > 0) { *buf++ = tmp[--i]; len++; } 80035f0: e014 b.n 800361c 80035f2: 2117 movs r1, #23 80035f4: 187b adds r3, r7, r1 80035f6: 187a adds r2, r7, r1 80035f8: 7812 ldrb r2, [r2, #0] 80035fa: 3a01 subs r2, #1 80035fc: 701a strb r2, [r3, #0] 80035fe: 187b adds r3, r7, r1 8003600: 781a ldrb r2, [r3, #0] 8003602: 683b ldr r3, [r7, #0] 8003604: 1c59 adds r1, r3, #1 8003606: 6039 str r1, [r7, #0] 8003608: 2108 movs r1, #8 800360a: 1879 adds r1, r7, r1 800360c: 5c8a ldrb r2, [r1, r2] 800360e: 701a strb r2, [r3, #0] 8003610: 2116 movs r1, #22 8003612: 187b adds r3, r7, r1 8003614: 781a ldrb r2, [r3, #0] 8003616: 187b adds r3, r7, r1 8003618: 3201 adds r2, #1 800361a: 701a strb r2, [r3, #0] 800361c: 2317 movs r3, #23 800361e: 18fb adds r3, r7, r3 8003620: 781b ldrb r3, [r3, #0] 8003622: 2b00 cmp r3, #0 8003624: d1e5 bne.n 80035f2 return len; 8003626: 2316 movs r3, #22 8003628: 18fb adds r3, r7, r3 800362a: 781b ldrb r3, [r3, #0] } 800362c: 0018 movs r0, r3 800362e: 46bd mov sp, r7 8003630: b006 add sp, #24 8003632: bd80 pop {r7, pc} 08003634 : // Convert uint8 to 2-digit hex, returns 2 uint8_t debug_hex8(uint8_t val, char *buf) { 8003634: b5b0 push {r4, r5, r7, lr} 8003636: b088 sub sp, #32 8003638: af00 add r7, sp, #0 800363a: 0002 movs r2, r0 800363c: 6039 str r1, [r7, #0] 800363e: 1dfb adds r3, r7, #7 8003640: 701a strb r2, [r3, #0] const char hex[] = "0123456789ABCDEF"; 8003642: 250c movs r5, #12 8003644: 197b adds r3, r7, r5 8003646: 4a10 ldr r2, [pc, #64] @ (8003688 ) 8003648: ca13 ldmia r2!, {r0, r1, r4} 800364a: c313 stmia r3!, {r0, r1, r4} 800364c: 6811 ldr r1, [r2, #0] 800364e: 6019 str r1, [r3, #0] 8003650: 7912 ldrb r2, [r2, #4] 8003652: 711a strb r2, [r3, #4] buf[0] = hex[(val >> 4) & 0x0F]; 8003654: 1dfb adds r3, r7, #7 8003656: 781b ldrb r3, [r3, #0] 8003658: 091b lsrs r3, r3, #4 800365a: b2db uxtb r3, r3 800365c: 001a movs r2, r3 800365e: 230f movs r3, #15 8003660: 4013 ands r3, r2 8003662: 197a adds r2, r7, r5 8003664: 5cd2 ldrb r2, [r2, r3] 8003666: 683b ldr r3, [r7, #0] 8003668: 701a strb r2, [r3, #0] buf[1] = hex[val & 0x0F]; 800366a: 1dfb adds r3, r7, #7 800366c: 781b ldrb r3, [r3, #0] 800366e: 220f movs r2, #15 8003670: 401a ands r2, r3 8003672: 683b ldr r3, [r7, #0] 8003674: 3301 adds r3, #1 8003676: 1979 adds r1, r7, r5 8003678: 5c8a ldrb r2, [r1, r2] 800367a: 701a strb r2, [r3, #0] return 2; 800367c: 2302 movs r3, #2 } 800367e: 0018 movs r0, r3 8003680: 46bd mov sp, r7 8003682: b008 add sp, #32 8003684: bdb0 pop {r4, r5, r7, pc} 8003686: 46c0 nop @ (mov r8, r8) 8003688: 08007d38 .word 0x08007d38 0800368c : void debug_output(void) { 800368c: b580 push {r7, lr} 800368e: b082 sub sp, #8 8003690: af00 add r7, sp, #0 if (!debug_enabled) return; 8003692: 4bb6 ldr r3, [pc, #728] @ (800396c ) 8003694: 781b ldrb r3, [r3, #0] 8003696: 2b00 cmp r3, #0 8003698: d100 bne.n 800369c 800369a: e161 b.n 8003960 uint32_t now = HAL_GetTick(); 800369c: f000 fd1c bl 80040d8 80036a0: 0003 movs r3, r0 80036a2: 607b str r3, [r7, #4] if ((now - last_debug_output_time) < DEBUG_OUTPUT_INTERVAL_MS) return; 80036a4: 4bb2 ldr r3, [pc, #712] @ (8003970 ) 80036a6: 681b ldr r3, [r3, #0] 80036a8: 687a ldr r2, [r7, #4] 80036aa: 1ad3 subs r3, r2, r3 80036ac: 2b63 cmp r3, #99 @ 0x63 80036ae: d800 bhi.n 80036b2 80036b0: e158 b.n 8003964 last_debug_output_time = now; 80036b2: 4baf ldr r3, [pc, #700] @ (8003970 ) 80036b4: 687a ldr r2, [r7, #4] 80036b6: 601a str r2, [r3, #0] // Format: $P:pos:tgt:err,I:pid,S:state,F:flags,A:addr,D:drv*\r\n char *p = debug_tx_buffer; 80036b8: 4bae ldr r3, [pc, #696] @ (8003974 ) 80036ba: 603b str r3, [r7, #0] *p++ = '$'; *p++ = 'P'; *p++ = ':'; 80036bc: 683b ldr r3, [r7, #0] 80036be: 1c5a adds r2, r3, #1 80036c0: 603a str r2, [r7, #0] 80036c2: 2224 movs r2, #36 @ 0x24 80036c4: 701a strb r2, [r3, #0] 80036c6: 683b ldr r3, [r7, #0] 80036c8: 1c5a adds r2, r3, #1 80036ca: 603a str r2, [r7, #0] 80036cc: 2250 movs r2, #80 @ 0x50 80036ce: 701a strb r2, [r3, #0] 80036d0: 683b ldr r3, [r7, #0] 80036d2: 1c5a adds r2, r3, #1 80036d4: 603a str r2, [r7, #0] 80036d6: 223a movs r2, #58 @ 0x3a 80036d8: 701a strb r2, [r3, #0] p += debug_itoa(total_count, p); 80036da: 4ba7 ldr r3, [pc, #668] @ (8003978 ) 80036dc: 681b ldr r3, [r3, #0] 80036de: 683a ldr r2, [r7, #0] 80036e0: 0011 movs r1, r2 80036e2: 0018 movs r0, r3 80036e4: f7ff ff2d bl 8003542 80036e8: 0003 movs r3, r0 80036ea: 001a movs r2, r3 80036ec: 683b ldr r3, [r7, #0] 80036ee: 189b adds r3, r3, r2 80036f0: 603b str r3, [r7, #0] *p++ = ':'; 80036f2: 683b ldr r3, [r7, #0] 80036f4: 1c5a adds r2, r3, #1 80036f6: 603a str r2, [r7, #0] 80036f8: 223a movs r2, #58 @ 0x3a 80036fa: 701a strb r2, [r3, #0] p += debug_itoa(target_count, p); 80036fc: 4b9f ldr r3, [pc, #636] @ (800397c ) 80036fe: 681b ldr r3, [r3, #0] 8003700: 683a ldr r2, [r7, #0] 8003702: 0011 movs r1, r2 8003704: 0018 movs r0, r3 8003706: f7ff ff1c bl 8003542 800370a: 0003 movs r3, r0 800370c: 001a movs r2, r3 800370e: 683b ldr r3, [r7, #0] 8003710: 189b adds r3, r3, r2 8003712: 603b str r3, [r7, #0] *p++ = ':'; 8003714: 683b ldr r3, [r7, #0] 8003716: 1c5a adds r2, r3, #1 8003718: 603a str r2, [r7, #0] 800371a: 223a movs r2, #58 @ 0x3a 800371c: 701a strb r2, [r3, #0] p += debug_itoa(target_count - total_count, p); 800371e: 4b97 ldr r3, [pc, #604] @ (800397c ) 8003720: 681a ldr r2, [r3, #0] 8003722: 4b95 ldr r3, [pc, #596] @ (8003978 ) 8003724: 681b ldr r3, [r3, #0] 8003726: 1ad3 subs r3, r2, r3 8003728: 683a ldr r2, [r7, #0] 800372a: 0011 movs r1, r2 800372c: 0018 movs r0, r3 800372e: f7ff ff08 bl 8003542 8003732: 0003 movs r3, r0 8003734: 001a movs r2, r3 8003736: 683b ldr r3, [r7, #0] 8003738: 189b adds r3, r3, r2 800373a: 603b str r3, [r7, #0] *p++ = ','; *p++ = 'I'; *p++ = ':'; 800373c: 683b ldr r3, [r7, #0] 800373e: 1c5a adds r2, r3, #1 8003740: 603a str r2, [r7, #0] 8003742: 222c movs r2, #44 @ 0x2c 8003744: 701a strb r2, [r3, #0] 8003746: 683b ldr r3, [r7, #0] 8003748: 1c5a adds r2, r3, #1 800374a: 603a str r2, [r7, #0] 800374c: 2249 movs r2, #73 @ 0x49 800374e: 701a strb r2, [r3, #0] 8003750: 683b ldr r3, [r7, #0] 8003752: 1c5a adds r2, r3, #1 8003754: 603a str r2, [r7, #0] 8003756: 223a movs r2, #58 @ 0x3a 8003758: 701a strb r2, [r3, #0] p += debug_itoa(debug_pid_output, p); 800375a: 4b89 ldr r3, [pc, #548] @ (8003980 ) 800375c: 881b ldrh r3, [r3, #0] 800375e: b21b sxth r3, r3 8003760: 001a movs r2, r3 8003762: 683b ldr r3, [r7, #0] 8003764: 0019 movs r1, r3 8003766: 0010 movs r0, r2 8003768: f7ff feeb bl 8003542 800376c: 0003 movs r3, r0 800376e: 001a movs r2, r3 8003770: 683b ldr r3, [r7, #0] 8003772: 189b adds r3, r3, r2 8003774: 603b str r3, [r7, #0] *p++ = ','; *p++ = 'S'; *p++ = ':'; 8003776: 683b ldr r3, [r7, #0] 8003778: 1c5a adds r2, r3, #1 800377a: 603a str r2, [r7, #0] 800377c: 222c movs r2, #44 @ 0x2c 800377e: 701a strb r2, [r3, #0] 8003780: 683b ldr r3, [r7, #0] 8003782: 1c5a adds r2, r3, #1 8003784: 603a str r2, [r7, #0] 8003786: 2253 movs r2, #83 @ 0x53 8003788: 701a strb r2, [r3, #0] 800378a: 683b ldr r3, [r7, #0] 800378c: 1c5a adds r2, r3, #1 800378e: 603a str r2, [r7, #0] 8003790: 223a movs r2, #58 @ 0x3a 8003792: 701a strb r2, [r3, #0] *p++ = '0' + feed_state; // State as single digit 0-9 8003794: 4b7b ldr r3, [pc, #492] @ (8003984 ) 8003796: 781b ldrb r3, [r3, #0] 8003798: b2da uxtb r2, r3 800379a: 683b ldr r3, [r7, #0] 800379c: 1c59 adds r1, r3, #1 800379e: 6039 str r1, [r7, #0] 80037a0: 3230 adds r2, #48 @ 0x30 80037a2: b2d2 uxtb r2, r2 80037a4: 701a strb r2, [r3, #0] *p++ = ','; *p++ = 'F'; *p++ = ':'; 80037a6: 683b ldr r3, [r7, #0] 80037a8: 1c5a adds r2, r3, #1 80037aa: 603a str r2, [r7, #0] 80037ac: 222c movs r2, #44 @ 0x2c 80037ae: 701a strb r2, [r3, #0] 80037b0: 683b ldr r3, [r7, #0] 80037b2: 1c5a adds r2, r3, #1 80037b4: 603a str r2, [r7, #0] 80037b6: 2246 movs r2, #70 @ 0x46 80037b8: 701a strb r2, [r3, #0] 80037ba: 683b ldr r3, [r7, #0] 80037bc: 1c5a adds r2, r3, #1 80037be: 603a str r2, [r7, #0] 80037c0: 223a movs r2, #58 @ 0x3a 80037c2: 701a strb r2, [r3, #0] *p++ = '0' + is_initialized; 80037c4: 4b70 ldr r3, [pc, #448] @ (8003988 ) 80037c6: 781a ldrb r2, [r3, #0] 80037c8: 683b ldr r3, [r7, #0] 80037ca: 1c59 adds r1, r3, #1 80037cc: 6039 str r1, [r7, #0] 80037ce: 3230 adds r2, #48 @ 0x30 80037d0: b2d2 uxtb r2, r2 80037d2: 701a strb r2, [r3, #0] *p++ = '0' + feed_in_progress; 80037d4: 4b6d ldr r3, [pc, #436] @ (800398c ) 80037d6: 781b ldrb r3, [r3, #0] 80037d8: b2da uxtb r2, r3 80037da: 683b ldr r3, [r7, #0] 80037dc: 1c59 adds r1, r3, #1 80037de: 6039 str r1, [r7, #0] 80037e0: 3230 adds r2, #48 @ 0x30 80037e2: b2d2 uxtb r2, r2 80037e4: 701a strb r2, [r3, #0] *p++ = '0' + beefy_tape; 80037e6: 4b6a ldr r3, [pc, #424] @ (8003990 ) 80037e8: 781a ldrb r2, [r3, #0] 80037ea: 683b ldr r3, [r7, #0] 80037ec: 1c59 adds r1, r3, #1 80037ee: 6039 str r1, [r7, #0] 80037f0: 3230 adds r2, #48 @ 0x30 80037f2: b2d2 uxtb r2, r2 80037f4: 701a strb r2, [r3, #0] *p++ = ','; *p++ = 'A'; *p++ = ':'; 80037f6: 683b ldr r3, [r7, #0] 80037f8: 1c5a adds r2, r3, #1 80037fa: 603a str r2, [r7, #0] 80037fc: 222c movs r2, #44 @ 0x2c 80037fe: 701a strb r2, [r3, #0] 8003800: 683b ldr r3, [r7, #0] 8003802: 1c5a adds r2, r3, #1 8003804: 603a str r2, [r7, #0] 8003806: 2241 movs r2, #65 @ 0x41 8003808: 701a strb r2, [r3, #0] 800380a: 683b ldr r3, [r7, #0] 800380c: 1c5a adds r2, r3, #1 800380e: 603a str r2, [r7, #0] 8003810: 223a movs r2, #58 @ 0x3a 8003812: 701a strb r2, [r3, #0] p += debug_hex8(my_address, p); 8003814: 4b5f ldr r3, [pc, #380] @ (8003994 ) 8003816: 781b ldrb r3, [r3, #0] 8003818: 683a ldr r2, [r7, #0] 800381a: 0011 movs r1, r2 800381c: 0018 movs r0, r3 800381e: f7ff ff09 bl 8003634 8003822: 0003 movs r3, r0 8003824: 001a movs r2, r3 8003826: 683b ldr r3, [r7, #0] 8003828: 189b adds r3, r3, r2 800382a: 603b str r3, [r7, #0] *p++ = ','; *p++ = 'B'; *p++ = ':'; 800382c: 683b ldr r3, [r7, #0] 800382e: 1c5a adds r2, r3, #1 8003830: 603a str r2, [r7, #0] 8003832: 222c movs r2, #44 @ 0x2c 8003834: 701a strb r2, [r3, #0] 8003836: 683b ldr r3, [r7, #0] 8003838: 1c5a adds r2, r3, #1 800383a: 603a str r2, [r7, #0] 800383c: 2242 movs r2, #66 @ 0x42 800383e: 701a strb r2, [r3, #0] 8003840: 683b ldr r3, [r7, #0] 8003842: 1c5a adds r2, r3, #1 8003844: 603a str r2, [r7, #0] 8003846: 223a movs r2, #58 @ 0x3a 8003848: 701a strb r2, [r3, #0] *p++ = '0' + sw1_pressed; 800384a: 4b53 ldr r3, [pc, #332] @ (8003998 ) 800384c: 781a ldrb r2, [r3, #0] 800384e: 683b ldr r3, [r7, #0] 8003850: 1c59 adds r1, r3, #1 8003852: 6039 str r1, [r7, #0] 8003854: 3230 adds r2, #48 @ 0x30 8003856: b2d2 uxtb r2, r2 8003858: 701a strb r2, [r3, #0] *p++ = '0' + sw2_pressed; 800385a: 4b50 ldr r3, [pc, #320] @ (800399c ) 800385c: 781a ldrb r2, [r3, #0] 800385e: 683b ldr r3, [r7, #0] 8003860: 1c59 adds r1, r3, #1 8003862: 6039 str r1, [r7, #0] 8003864: 3230 adds r2, #48 @ 0x30 8003866: b2d2 uxtb r2, r2 8003868: 701a strb r2, [r3, #0] // Raw GPIO pin state: 1=high(released), 0=low(pressed) *p++ = ','; *p++ = 'G'; *p++ = ':'; 800386a: 683b ldr r3, [r7, #0] 800386c: 1c5a adds r2, r3, #1 800386e: 603a str r2, [r7, #0] 8003870: 222c movs r2, #44 @ 0x2c 8003872: 701a strb r2, [r3, #0] 8003874: 683b ldr r3, [r7, #0] 8003876: 1c5a adds r2, r3, #1 8003878: 603a str r2, [r7, #0] 800387a: 2247 movs r2, #71 @ 0x47 800387c: 701a strb r2, [r3, #0] 800387e: 683b ldr r3, [r7, #0] 8003880: 1c5a adds r2, r3, #1 8003882: 603a str r2, [r7, #0] 8003884: 223a movs r2, #58 @ 0x3a 8003886: 701a strb r2, [r3, #0] *p++ = '0' + (uint8_t)HAL_GPIO_ReadPin(SW1_GPIO_Port, SW1_Pin); 8003888: 2380 movs r3, #128 @ 0x80 800388a: 009b lsls r3, r3, #2 800388c: 4a44 ldr r2, [pc, #272] @ (80039a0 ) 800388e: 0019 movs r1, r3 8003890: 0010 movs r0, r2 8003892: f001 f911 bl 8004ab8 8003896: 0003 movs r3, r0 8003898: 0019 movs r1, r3 800389a: 683b ldr r3, [r7, #0] 800389c: 1c5a adds r2, r3, #1 800389e: 603a str r2, [r7, #0] 80038a0: 000a movs r2, r1 80038a2: 3230 adds r2, #48 @ 0x30 80038a4: b2d2 uxtb r2, r2 80038a6: 701a strb r2, [r3, #0] *p++ = '0' + (uint8_t)HAL_GPIO_ReadPin(SW2_GPIO_Port, SW2_Pin); 80038a8: 2380 movs r3, #128 @ 0x80 80038aa: 005b lsls r3, r3, #1 80038ac: 4a3c ldr r2, [pc, #240] @ (80039a0 ) 80038ae: 0019 movs r1, r3 80038b0: 0010 movs r0, r2 80038b2: f001 f901 bl 8004ab8 80038b6: 0003 movs r3, r0 80038b8: 0019 movs r1, r3 80038ba: 683b ldr r3, [r7, #0] 80038bc: 1c5a adds r2, r3, #1 80038be: 603a str r2, [r7, #0] 80038c0: 000a movs r2, r1 80038c2: 3230 adds r2, #48 @ 0x30 80038c4: b2d2 uxtb r2, r2 80038c6: 701a strb r2, [r3, #0] *p++ = ','; *p++ = 'D'; *p++ = ':'; 80038c8: 683b ldr r3, [r7, #0] 80038ca: 1c5a adds r2, r3, #1 80038cc: 603a str r2, [r7, #0] 80038ce: 222c movs r2, #44 @ 0x2c 80038d0: 701a strb r2, [r3, #0] 80038d2: 683b ldr r3, [r7, #0] 80038d4: 1c5a adds r2, r3, #1 80038d6: 603a str r2, [r7, #0] 80038d8: 2244 movs r2, #68 @ 0x44 80038da: 701a strb r2, [r3, #0] 80038dc: 683b ldr r3, [r7, #0] 80038de: 1c5a adds r2, r3, #1 80038e0: 603a str r2, [r7, #0] 80038e2: 223a movs r2, #58 @ 0x3a 80038e4: 701a strb r2, [r3, #0] p += debug_itoa(current_drive_value, p); 80038e6: 4b2f ldr r3, [pc, #188] @ (80039a4 ) 80038e8: 781b ldrb r3, [r3, #0] 80038ea: 001a movs r2, r3 80038ec: 683b ldr r3, [r7, #0] 80038ee: 0019 movs r1, r3 80038f0: 0010 movs r0, r2 80038f2: f7ff fe26 bl 8003542 80038f6: 0003 movs r3, r0 80038f8: 001a movs r2, r3 80038fa: 683b ldr r3, [r7, #0] 80038fc: 189b adds r3, r3, r2 80038fe: 603b str r3, [r7, #0] *p++ = ','; *p++ = 'M'; *p++ = ':'; 8003900: 683b ldr r3, [r7, #0] 8003902: 1c5a adds r2, r3, #1 8003904: 603a str r2, [r7, #0] 8003906: 222c movs r2, #44 @ 0x2c 8003908: 701a strb r2, [r3, #0] 800390a: 683b ldr r3, [r7, #0] 800390c: 1c5a adds r2, r3, #1 800390e: 603a str r2, [r7, #0] 8003910: 224d movs r2, #77 @ 0x4d 8003912: 701a strb r2, [r3, #0] 8003914: 683b ldr r3, [r7, #0] 8003916: 1c5a adds r2, r3, #1 8003918: 603a str r2, [r7, #0] 800391a: 223a movs r2, #58 @ 0x3a 800391c: 701a strb r2, [r3, #0] *p++ = '0' + drive_mode; 800391e: 4b22 ldr r3, [pc, #136] @ (80039a8 ) 8003920: 781a ldrb r2, [r3, #0] 8003922: 683b ldr r3, [r7, #0] 8003924: 1c59 adds r1, r3, #1 8003926: 6039 str r1, [r7, #0] 8003928: 3230 adds r2, #48 @ 0x30 800392a: b2d2 uxtb r2, r2 800392c: 701a strb r2, [r3, #0] *p++ = '*'; *p++ = '\r'; *p++ = '\n'; 800392e: 683b ldr r3, [r7, #0] 8003930: 1c5a adds r2, r3, #1 8003932: 603a str r2, [r7, #0] 8003934: 222a movs r2, #42 @ 0x2a 8003936: 701a strb r2, [r3, #0] 8003938: 683b ldr r3, [r7, #0] 800393a: 1c5a adds r2, r3, #1 800393c: 603a str r2, [r7, #0] 800393e: 220d movs r2, #13 8003940: 701a strb r2, [r3, #0] 8003942: 683b ldr r3, [r7, #0] 8003944: 1c5a adds r2, r3, #1 8003946: 603a str r2, [r7, #0] 8003948: 220a movs r2, #10 800394a: 701a strb r2, [r3, #0] HAL_UART_Transmit(&huart1, (uint8_t*)debug_tx_buffer, p - debug_tx_buffer, 10); 800394c: 683a ldr r2, [r7, #0] 800394e: 4b09 ldr r3, [pc, #36] @ (8003974 ) 8003950: 1ad3 subs r3, r2, r3 8003952: b29a uxth r2, r3 8003954: 4907 ldr r1, [pc, #28] @ (8003974 ) 8003956: 4815 ldr r0, [pc, #84] @ (80039ac ) 8003958: 230a movs r3, #10 800395a: f003 f91f bl 8006b9c 800395e: e002 b.n 8003966 if (!debug_enabled) return; 8003960: 46c0 nop @ (mov r8, r8) 8003962: e000 b.n 8003966 if ((now - last_debug_output_time) < DEBUG_OUTPUT_INTERVAL_MS) return; 8003964: 46c0 nop @ (mov r8, r8) } 8003966: 46bd mov sp, r7 8003968: b002 add sp, #8 800396a: bd80 pop {r7, pc} 800396c: 20000020 .word 0x20000020 8003970: 20000554 .word 0x20000554 8003974: 20000558 .word 0x20000558 8003978: 20000484 .word 0x20000484 800397c: 20000488 .word 0x20000488 8003980: 200005a8 .word 0x200005a8 8003984: 200004bf .word 0x200004bf 8003988: 200003c0 .word 0x200003c0 800398c: 200004bd .word 0x200004bd 8003990: 200004d5 .word 0x200004d5 8003994: 20000002 .word 0x20000002 8003998: 200003a8 .word 0x200003a8 800399c: 200003a9 .word 0x200003a9 80039a0: 50000400 .word 0x50000400 80039a4: 2000001e .word 0x2000001e 80039a8: 200004e0 .word 0x200004e0 80039ac: 200001c8 .word 0x200001c8 080039b0 : // ============================================================================ // Position Management // ============================================================================ void reset_position_if_needed(void) { 80039b0: b580 push {r7, lr} 80039b2: b082 sub sp, #8 80039b4: af00 add r7, sp, #0 // This is called from main loop periodically or after feed completes // to reset position tracking and prevent overflow // Only reset when position is at a "round" value to avoid drift int32_t counts_per_mm = tenths_to_counts(10); // counts per 1mm 80039b6: 200a movs r0, #10 80039b8: f7fe ff8a bl 80028d0 80039bc: 0003 movs r3, r0 80039be: 607b str r3, [r7, #4] // Check if we're at a position that's a multiple of 1mm if ((total_count % counts_per_mm) == 0 && feed_state == FEED_STATE_IDLE) 80039c0: 4b1a ldr r3, [pc, #104] @ (8003a2c ) 80039c2: 681b ldr r3, [r3, #0] 80039c4: 6879 ldr r1, [r7, #4] 80039c6: 0018 movs r0, r3 80039c8: f7fc fd0e bl 80003e8 <__aeabi_idivmod> 80039cc: 1e0b subs r3, r1, #0 80039ce: d129 bne.n 8003a24 80039d0: 4b17 ldr r3, [pc, #92] @ (8003a30 ) 80039d2: 781b ldrb r3, [r3, #0] 80039d4: b2db uxtb r3, r3 80039d6: 2b00 cmp r3, #0 80039d8: d124 bne.n 8003a24 { // Calculate how many mm we've moved int32_t mm_moved = total_count / counts_per_mm; 80039da: 4b14 ldr r3, [pc, #80] @ (8003a2c ) 80039dc: 681b ldr r3, [r3, #0] 80039de: 6879 ldr r1, [r7, #4] 80039e0: 0018 movs r0, r3 80039e2: f7fc fc1b bl 800021c <__divsi3> 80039e6: 0003 movs r3, r0 80039e8: 603b str r3, [r7, #0] mm_position += mm_moved; 80039ea: 4b12 ldr r3, [pc, #72] @ (8003a34 ) 80039ec: 681a ldr r2, [r3, #0] 80039ee: 683b ldr r3, [r7, #0] 80039f0: 18d2 adds r2, r2, r3 80039f2: 4b10 ldr r3, [pc, #64] @ (8003a34 ) 80039f4: 601a str r2, [r3, #0] __ASM volatile ("cpsid i" : : : "memory"); 80039f6: b672 cpsid i } 80039f8: 46c0 nop @ (mov r8, r8) // Reset encoder tracking __disable_irq(); encoder_count_extra = 0; 80039fa: 4b0f ldr r3, [pc, #60] @ (8003a38 ) 80039fc: 2200 movs r2, #0 80039fe: 601a str r2, [r3, #0] htim3.Instance->CNT = 0; 8003a00: 4b0e ldr r3, [pc, #56] @ (8003a3c ) 8003a02: 681b ldr r3, [r3, #0] 8003a04: 2200 movs r2, #0 8003a06: 625a str r2, [r3, #36] @ 0x24 encoder_previous = 0; 8003a08: 4b0d ldr r3, [pc, #52] @ (8003a40 ) 8003a0a: 2200 movs r2, #0 8003a0c: 801a strh r2, [r3, #0] total_count = 0; 8003a0e: 4b07 ldr r3, [pc, #28] @ (8003a2c ) 8003a10: 2200 movs r2, #0 8003a12: 601a str r2, [r3, #0] target_count = 0; 8003a14: 4b0b ldr r3, [pc, #44] @ (8003a44 ) 8003a16: 2200 movs r2, #0 8003a18: 601a str r2, [r3, #0] feed_target_position = 0; 8003a1a: 4b0b ldr r3, [pc, #44] @ (8003a48 ) 8003a1c: 2200 movs r2, #0 8003a1e: 601a str r2, [r3, #0] __ASM volatile ("cpsie i" : : : "memory"); 8003a20: b662 cpsie i } 8003a22: 46c0 nop @ (mov r8, r8) __enable_irq(); } } 8003a24: 46c0 nop @ (mov r8, r8) 8003a26: 46bd mov sp, r7 8003a28: b002 add sp, #8 8003a2a: bd80 pop {r7, pc} 8003a2c: 20000484 .word 0x20000484 8003a30: 200004bf .word 0x200004bf 8003a34: 20000550 .word 0x20000550 8003a38: 200003ac .word 0x200003ac 8003a3c: 20000098 .word 0x20000098 8003a40: 200003b0 .word 0x200003b0 8003a44: 20000488 .word 0x20000488 8003a48: 200004d0 .word 0x200004d0 08003a4c : /** * @brief This function is executed in case of error occurrence. * @retval None */ void Error_Handler(void) { 8003a4c: b580 push {r7, lr} 8003a4e: af00 add r7, sp, #0 __ASM volatile ("cpsid i" : : : "memory"); 8003a50: b672 cpsid i } 8003a52: 46c0 nop @ (mov r8, r8) /* USER CODE BEGIN Error_Handler_Debug */ /* User can add his own implementation to report the HAL error return state */ __disable_irq(); while (1) 8003a54: 46c0 nop @ (mov r8, r8) 8003a56: e7fd b.n 8003a54 08003a58 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim); /** * Initializes the Global MSP. */ void HAL_MspInit(void) { 8003a58: b580 push {r7, lr} 8003a5a: b082 sub sp, #8 8003a5c: af00 add r7, sp, #0 /* USER CODE BEGIN MspInit 0 */ /* USER CODE END MspInit 0 */ __HAL_RCC_SYSCFG_CLK_ENABLE(); 8003a5e: 4b0f ldr r3, [pc, #60] @ (8003a9c ) 8003a60: 6c1a ldr r2, [r3, #64] @ 0x40 8003a62: 4b0e ldr r3, [pc, #56] @ (8003a9c ) 8003a64: 2101 movs r1, #1 8003a66: 430a orrs r2, r1 8003a68: 641a str r2, [r3, #64] @ 0x40 8003a6a: 4b0c ldr r3, [pc, #48] @ (8003a9c ) 8003a6c: 6c1b ldr r3, [r3, #64] @ 0x40 8003a6e: 2201 movs r2, #1 8003a70: 4013 ands r3, r2 8003a72: 607b str r3, [r7, #4] 8003a74: 687b ldr r3, [r7, #4] __HAL_RCC_PWR_CLK_ENABLE(); 8003a76: 4b09 ldr r3, [pc, #36] @ (8003a9c ) 8003a78: 6bda ldr r2, [r3, #60] @ 0x3c 8003a7a: 4b08 ldr r3, [pc, #32] @ (8003a9c ) 8003a7c: 2180 movs r1, #128 @ 0x80 8003a7e: 0549 lsls r1, r1, #21 8003a80: 430a orrs r2, r1 8003a82: 63da str r2, [r3, #60] @ 0x3c 8003a84: 4b05 ldr r3, [pc, #20] @ (8003a9c ) 8003a86: 6bda ldr r2, [r3, #60] @ 0x3c 8003a88: 2380 movs r3, #128 @ 0x80 8003a8a: 055b lsls r3, r3, #21 8003a8c: 4013 ands r3, r2 8003a8e: 603b str r3, [r7, #0] 8003a90: 683b ldr r3, [r7, #0] /* System interrupt init*/ /* USER CODE BEGIN MspInit 1 */ /* USER CODE END MspInit 1 */ } 8003a92: 46c0 nop @ (mov r8, r8) 8003a94: 46bd mov sp, r7 8003a96: b002 add sp, #8 8003a98: bd80 pop {r7, pc} 8003a9a: 46c0 nop @ (mov r8, r8) 8003a9c: 40021000 .word 0x40021000 08003aa0 : * This function configures the hardware resources used in this example * @param htim_base: TIM_Base handle pointer * @retval None */ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base) { 8003aa0: b580 push {r7, lr} 8003aa2: b086 sub sp, #24 8003aa4: af00 add r7, sp, #0 8003aa6: 6078 str r0, [r7, #4] if(htim_base->Instance==TIM1) 8003aa8: 687b ldr r3, [r7, #4] 8003aaa: 681b ldr r3, [r3, #0] 8003aac: 4a34 ldr r2, [pc, #208] @ (8003b80 ) 8003aae: 4293 cmp r3, r2 8003ab0: d10e bne.n 8003ad0 { /* USER CODE BEGIN TIM1_MspInit 0 */ /* USER CODE END TIM1_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM1_CLK_ENABLE(); 8003ab2: 4b34 ldr r3, [pc, #208] @ (8003b84 ) 8003ab4: 6c1a ldr r2, [r3, #64] @ 0x40 8003ab6: 4b33 ldr r3, [pc, #204] @ (8003b84 ) 8003ab8: 2180 movs r1, #128 @ 0x80 8003aba: 0109 lsls r1, r1, #4 8003abc: 430a orrs r2, r1 8003abe: 641a str r2, [r3, #64] @ 0x40 8003ac0: 4b30 ldr r3, [pc, #192] @ (8003b84 ) 8003ac2: 6c1a ldr r2, [r3, #64] @ 0x40 8003ac4: 2380 movs r3, #128 @ 0x80 8003ac6: 011b lsls r3, r3, #4 8003ac8: 4013 ands r3, r2 8003aca: 617b str r3, [r7, #20] 8003acc: 697b ldr r3, [r7, #20] /* USER CODE BEGIN TIM17_MspInit 1 */ /* USER CODE END TIM17_MspInit 1 */ } } 8003ace: e052 b.n 8003b76 else if(htim_base->Instance==TIM14) 8003ad0: 687b ldr r3, [r7, #4] 8003ad2: 681b ldr r3, [r3, #0] 8003ad4: 4a2c ldr r2, [pc, #176] @ (8003b88 ) 8003ad6: 4293 cmp r3, r2 8003ad8: d116 bne.n 8003b08 __HAL_RCC_TIM14_CLK_ENABLE(); 8003ada: 4b2a ldr r3, [pc, #168] @ (8003b84 ) 8003adc: 6c1a ldr r2, [r3, #64] @ 0x40 8003ade: 4b29 ldr r3, [pc, #164] @ (8003b84 ) 8003ae0: 2180 movs r1, #128 @ 0x80 8003ae2: 0209 lsls r1, r1, #8 8003ae4: 430a orrs r2, r1 8003ae6: 641a str r2, [r3, #64] @ 0x40 8003ae8: 4b26 ldr r3, [pc, #152] @ (8003b84 ) 8003aea: 6c1a ldr r2, [r3, #64] @ 0x40 8003aec: 2380 movs r3, #128 @ 0x80 8003aee: 021b lsls r3, r3, #8 8003af0: 4013 ands r3, r2 8003af2: 613b str r3, [r7, #16] 8003af4: 693b ldr r3, [r7, #16] HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0); 8003af6: 2200 movs r2, #0 8003af8: 2100 movs r1, #0 8003afa: 2013 movs r0, #19 8003afc: f000 fbe4 bl 80042c8 HAL_NVIC_EnableIRQ(TIM14_IRQn); 8003b00: 2013 movs r0, #19 8003b02: f000 fbf6 bl 80042f2 } 8003b06: e036 b.n 8003b76 else if(htim_base->Instance==TIM16) 8003b08: 687b ldr r3, [r7, #4] 8003b0a: 681b ldr r3, [r3, #0] 8003b0c: 4a1f ldr r2, [pc, #124] @ (8003b8c ) 8003b0e: 4293 cmp r3, r2 8003b10: d116 bne.n 8003b40 __HAL_RCC_TIM16_CLK_ENABLE(); 8003b12: 4b1c ldr r3, [pc, #112] @ (8003b84 ) 8003b14: 6c1a ldr r2, [r3, #64] @ 0x40 8003b16: 4b1b ldr r3, [pc, #108] @ (8003b84 ) 8003b18: 2180 movs r1, #128 @ 0x80 8003b1a: 0289 lsls r1, r1, #10 8003b1c: 430a orrs r2, r1 8003b1e: 641a str r2, [r3, #64] @ 0x40 8003b20: 4b18 ldr r3, [pc, #96] @ (8003b84 ) 8003b22: 6c1a ldr r2, [r3, #64] @ 0x40 8003b24: 2380 movs r3, #128 @ 0x80 8003b26: 029b lsls r3, r3, #10 8003b28: 4013 ands r3, r2 8003b2a: 60fb str r3, [r7, #12] 8003b2c: 68fb ldr r3, [r7, #12] HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0); 8003b2e: 2200 movs r2, #0 8003b30: 2100 movs r1, #0 8003b32: 2015 movs r0, #21 8003b34: f000 fbc8 bl 80042c8 HAL_NVIC_EnableIRQ(TIM16_IRQn); 8003b38: 2015 movs r0, #21 8003b3a: f000 fbda bl 80042f2 } 8003b3e: e01a b.n 8003b76 else if(htim_base->Instance==TIM17) 8003b40: 687b ldr r3, [r7, #4] 8003b42: 681b ldr r3, [r3, #0] 8003b44: 4a12 ldr r2, [pc, #72] @ (8003b90 ) 8003b46: 4293 cmp r3, r2 8003b48: d115 bne.n 8003b76 __HAL_RCC_TIM17_CLK_ENABLE(); 8003b4a: 4b0e ldr r3, [pc, #56] @ (8003b84 ) 8003b4c: 6c1a ldr r2, [r3, #64] @ 0x40 8003b4e: 4b0d ldr r3, [pc, #52] @ (8003b84 ) 8003b50: 2180 movs r1, #128 @ 0x80 8003b52: 02c9 lsls r1, r1, #11 8003b54: 430a orrs r2, r1 8003b56: 641a str r2, [r3, #64] @ 0x40 8003b58: 4b0a ldr r3, [pc, #40] @ (8003b84 ) 8003b5a: 6c1a ldr r2, [r3, #64] @ 0x40 8003b5c: 2380 movs r3, #128 @ 0x80 8003b5e: 02db lsls r3, r3, #11 8003b60: 4013 ands r3, r2 8003b62: 60bb str r3, [r7, #8] 8003b64: 68bb ldr r3, [r7, #8] HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0); 8003b66: 2200 movs r2, #0 8003b68: 2100 movs r1, #0 8003b6a: 2016 movs r0, #22 8003b6c: f000 fbac bl 80042c8 HAL_NVIC_EnableIRQ(TIM17_IRQn); 8003b70: 2016 movs r0, #22 8003b72: f000 fbbe bl 80042f2 } 8003b76: 46c0 nop @ (mov r8, r8) 8003b78: 46bd mov sp, r7 8003b7a: b006 add sp, #24 8003b7c: bd80 pop {r7, pc} 8003b7e: 46c0 nop @ (mov r8, r8) 8003b80: 40012c00 .word 0x40012c00 8003b84: 40021000 .word 0x40021000 8003b88: 40002000 .word 0x40002000 8003b8c: 40014400 .word 0x40014400 8003b90: 40014800 .word 0x40014800 08003b94 : * This function configures the hardware resources used in this example * @param htim_encoder: TIM_Encoder handle pointer * @retval None */ void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder) { 8003b94: b590 push {r4, r7, lr} 8003b96: b08b sub sp, #44 @ 0x2c 8003b98: af00 add r7, sp, #0 8003b9a: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003b9c: 2414 movs r4, #20 8003b9e: 193b adds r3, r7, r4 8003ba0: 0018 movs r0, r3 8003ba2: 2314 movs r3, #20 8003ba4: 001a movs r2, r3 8003ba6: 2100 movs r1, #0 8003ba8: f004 f884 bl 8007cb4 if(htim_encoder->Instance==TIM3) 8003bac: 687b ldr r3, [r7, #4] 8003bae: 681b ldr r3, [r3, #0] 8003bb0: 4a1a ldr r2, [pc, #104] @ (8003c1c ) 8003bb2: 4293 cmp r3, r2 8003bb4: d12d bne.n 8003c12 { /* USER CODE BEGIN TIM3_MspInit 0 */ /* USER CODE END TIM3_MspInit 0 */ /* Peripheral clock enable */ __HAL_RCC_TIM3_CLK_ENABLE(); 8003bb6: 4b1a ldr r3, [pc, #104] @ (8003c20 ) 8003bb8: 6bda ldr r2, [r3, #60] @ 0x3c 8003bba: 4b19 ldr r3, [pc, #100] @ (8003c20 ) 8003bbc: 2102 movs r1, #2 8003bbe: 430a orrs r2, r1 8003bc0: 63da str r2, [r3, #60] @ 0x3c 8003bc2: 4b17 ldr r3, [pc, #92] @ (8003c20 ) 8003bc4: 6bdb ldr r3, [r3, #60] @ 0x3c 8003bc6: 2202 movs r2, #2 8003bc8: 4013 ands r3, r2 8003bca: 613b str r3, [r7, #16] 8003bcc: 693b ldr r3, [r7, #16] __HAL_RCC_GPIOC_CLK_ENABLE(); 8003bce: 4b14 ldr r3, [pc, #80] @ (8003c20 ) 8003bd0: 6b5a ldr r2, [r3, #52] @ 0x34 8003bd2: 4b13 ldr r3, [pc, #76] @ (8003c20 ) 8003bd4: 2104 movs r1, #4 8003bd6: 430a orrs r2, r1 8003bd8: 635a str r2, [r3, #52] @ 0x34 8003bda: 4b11 ldr r3, [pc, #68] @ (8003c20 ) 8003bdc: 6b5b ldr r3, [r3, #52] @ 0x34 8003bde: 2204 movs r2, #4 8003be0: 4013 ands r3, r2 8003be2: 60fb str r3, [r7, #12] 8003be4: 68fb ldr r3, [r7, #12] /**TIM3 GPIO Configuration PC6 ------> TIM3_CH1 PC7 ------> TIM3_CH2 */ GPIO_InitStruct.Pin = QUAD_A_Pin|QUAD_B_Pin; 8003be6: 0021 movs r1, r4 8003be8: 187b adds r3, r7, r1 8003bea: 22c0 movs r2, #192 @ 0xc0 8003bec: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003bee: 187b adds r3, r7, r1 8003bf0: 2202 movs r2, #2 8003bf2: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003bf4: 187b adds r3, r7, r1 8003bf6: 2200 movs r2, #0 8003bf8: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003bfa: 187b adds r3, r7, r1 8003bfc: 2200 movs r2, #0 8003bfe: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_TIM3; 8003c00: 187b adds r3, r7, r1 8003c02: 2201 movs r2, #1 8003c04: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); 8003c06: 187b adds r3, r7, r1 8003c08: 4a06 ldr r2, [pc, #24] @ (8003c24 ) 8003c0a: 0019 movs r1, r3 8003c0c: 0010 movs r0, r2 8003c0e: f000 fde1 bl 80047d4 /* USER CODE END TIM3_MspInit 1 */ } } 8003c12: 46c0 nop @ (mov r8, r8) 8003c14: 46bd mov sp, r7 8003c16: b00b add sp, #44 @ 0x2c 8003c18: bd90 pop {r4, r7, pc} 8003c1a: 46c0 nop @ (mov r8, r8) 8003c1c: 40000400 .word 0x40000400 8003c20: 40021000 .word 0x40021000 8003c24: 50000800 .word 0x50000800 08003c28 : void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim) { 8003c28: b590 push {r4, r7, lr} 8003c2a: b089 sub sp, #36 @ 0x24 8003c2c: af00 add r7, sp, #0 8003c2e: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003c30: 240c movs r4, #12 8003c32: 193b adds r3, r7, r4 8003c34: 0018 movs r0, r3 8003c36: 2314 movs r3, #20 8003c38: 001a movs r2, r3 8003c3a: 2100 movs r1, #0 8003c3c: f004 f83a bl 8007cb4 if(htim->Instance==TIM1) 8003c40: 687b ldr r3, [r7, #4] 8003c42: 681b ldr r3, [r3, #0] 8003c44: 4a20 ldr r2, [pc, #128] @ (8003cc8 ) 8003c46: 4293 cmp r3, r2 8003c48: d139 bne.n 8003cbe { /* USER CODE BEGIN TIM1_MspPostInit 0 */ /* USER CODE END TIM1_MspPostInit 0 */ __HAL_RCC_GPIOA_CLK_ENABLE(); 8003c4a: 4b20 ldr r3, [pc, #128] @ (8003ccc ) 8003c4c: 6b5a ldr r2, [r3, #52] @ 0x34 8003c4e: 4b1f ldr r3, [pc, #124] @ (8003ccc ) 8003c50: 2101 movs r1, #1 8003c52: 430a orrs r2, r1 8003c54: 635a str r2, [r3, #52] @ 0x34 8003c56: 4b1d ldr r3, [pc, #116] @ (8003ccc ) 8003c58: 6b5b ldr r3, [r3, #52] @ 0x34 8003c5a: 2201 movs r2, #1 8003c5c: 4013 ands r3, r2 8003c5e: 60bb str r3, [r7, #8] 8003c60: 68bb ldr r3, [r7, #8] PA2 ------> TIM1_CH3 PA3 ------> TIM1_CH4 PA8 ------> TIM1_CH1 PA9 ------> TIM1_CH2 */ GPIO_InitStruct.Pin = PEEL1_Pin|PEEL2_Pin; 8003c62: 193b adds r3, r7, r4 8003c64: 220c movs r2, #12 8003c66: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003c68: 193b adds r3, r7, r4 8003c6a: 2202 movs r2, #2 8003c6c: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003c6e: 193b adds r3, r7, r4 8003c70: 2200 movs r2, #0 8003c72: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003c74: 193b adds r3, r7, r4 8003c76: 2200 movs r2, #0 8003c78: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF5_TIM1; 8003c7a: 193b adds r3, r7, r4 8003c7c: 2205 movs r2, #5 8003c7e: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003c80: 193a adds r2, r7, r4 8003c82: 23a0 movs r3, #160 @ 0xa0 8003c84: 05db lsls r3, r3, #23 8003c86: 0011 movs r1, r2 8003c88: 0018 movs r0, r3 8003c8a: f000 fda3 bl 80047d4 GPIO_InitStruct.Pin = DRIVE1_Pin|DRIVE2_Pin; 8003c8e: 0021 movs r1, r4 8003c90: 187b adds r3, r7, r1 8003c92: 22c0 movs r2, #192 @ 0xc0 8003c94: 0092 lsls r2, r2, #2 8003c96: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003c98: 187b adds r3, r7, r1 8003c9a: 2202 movs r2, #2 8003c9c: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003c9e: 187b adds r3, r7, r1 8003ca0: 2200 movs r2, #0 8003ca2: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003ca4: 187b adds r3, r7, r1 8003ca6: 2200 movs r2, #0 8003ca8: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF2_TIM1; 8003caa: 187b adds r3, r7, r1 8003cac: 2202 movs r2, #2 8003cae: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003cb0: 187a adds r2, r7, r1 8003cb2: 23a0 movs r3, #160 @ 0xa0 8003cb4: 05db lsls r3, r3, #23 8003cb6: 0011 movs r1, r2 8003cb8: 0018 movs r0, r3 8003cba: f000 fd8b bl 80047d4 /* USER CODE BEGIN TIM1_MspPostInit 1 */ /* USER CODE END TIM1_MspPostInit 1 */ } } 8003cbe: 46c0 nop @ (mov r8, r8) 8003cc0: 46bd mov sp, r7 8003cc2: b009 add sp, #36 @ 0x24 8003cc4: bd90 pop {r4, r7, pc} 8003cc6: 46c0 nop @ (mov r8, r8) 8003cc8: 40012c00 .word 0x40012c00 8003ccc: 40021000 .word 0x40021000 08003cd0 : * This function configures the hardware resources used in this example * @param huart: UART handle pointer * @retval None */ void HAL_UART_MspInit(UART_HandleTypeDef* huart) { 8003cd0: b590 push {r4, r7, lr} 8003cd2: b093 sub sp, #76 @ 0x4c 8003cd4: af00 add r7, sp, #0 8003cd6: 6078 str r0, [r7, #4] GPIO_InitTypeDef GPIO_InitStruct = {0}; 8003cd8: 2334 movs r3, #52 @ 0x34 8003cda: 18fb adds r3, r7, r3 8003cdc: 0018 movs r0, r3 8003cde: 2314 movs r3, #20 8003ce0: 001a movs r2, r3 8003ce2: 2100 movs r1, #0 8003ce4: f003 ffe6 bl 8007cb4 RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; 8003ce8: 2418 movs r4, #24 8003cea: 193b adds r3, r7, r4 8003cec: 0018 movs r0, r3 8003cee: 231c movs r3, #28 8003cf0: 001a movs r2, r3 8003cf2: 2100 movs r1, #0 8003cf4: f003 ffde bl 8007cb4 if(huart->Instance==USART1) 8003cf8: 687b ldr r3, [r7, #4] 8003cfa: 681b ldr r3, [r3, #0] 8003cfc: 4a68 ldr r2, [pc, #416] @ (8003ea0 ) 8003cfe: 4293 cmp r3, r2 8003d00: d13e bne.n 8003d80 /* USER CODE END USART1_MspInit 0 */ /** Initializes the peripherals clocks */ PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; 8003d02: 193b adds r3, r7, r4 8003d04: 2201 movs r2, #1 8003d06: 601a str r2, [r3, #0] PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1; 8003d08: 193b adds r3, r7, r4 8003d0a: 2200 movs r2, #0 8003d0c: 609a str r2, [r3, #8] if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) 8003d0e: 193b adds r3, r7, r4 8003d10: 0018 movs r0, r3 8003d12: f001 fab3 bl 800527c 8003d16: 1e03 subs r3, r0, #0 8003d18: d001 beq.n 8003d1e { Error_Handler(); 8003d1a: f7ff fe97 bl 8003a4c } /* Peripheral clock enable */ __HAL_RCC_USART1_CLK_ENABLE(); 8003d1e: 4b61 ldr r3, [pc, #388] @ (8003ea4 ) 8003d20: 6c1a ldr r2, [r3, #64] @ 0x40 8003d22: 4b60 ldr r3, [pc, #384] @ (8003ea4 ) 8003d24: 2180 movs r1, #128 @ 0x80 8003d26: 01c9 lsls r1, r1, #7 8003d28: 430a orrs r2, r1 8003d2a: 641a str r2, [r3, #64] @ 0x40 8003d2c: 4b5d ldr r3, [pc, #372] @ (8003ea4 ) 8003d2e: 6c1a ldr r2, [r3, #64] @ 0x40 8003d30: 2380 movs r3, #128 @ 0x80 8003d32: 01db lsls r3, r3, #7 8003d34: 4013 ands r3, r2 8003d36: 617b str r3, [r7, #20] 8003d38: 697b ldr r3, [r7, #20] __HAL_RCC_GPIOB_CLK_ENABLE(); 8003d3a: 4b5a ldr r3, [pc, #360] @ (8003ea4 ) 8003d3c: 6b5a ldr r2, [r3, #52] @ 0x34 8003d3e: 4b59 ldr r3, [pc, #356] @ (8003ea4 ) 8003d40: 2102 movs r1, #2 8003d42: 430a orrs r2, r1 8003d44: 635a str r2, [r3, #52] @ 0x34 8003d46: 4b57 ldr r3, [pc, #348] @ (8003ea4 ) 8003d48: 6b5b ldr r3, [r3, #52] @ 0x34 8003d4a: 2202 movs r2, #2 8003d4c: 4013 ands r3, r2 8003d4e: 613b str r3, [r7, #16] 8003d50: 693b ldr r3, [r7, #16] /**USART1 GPIO Configuration PB6 ------> USART1_TX PB7 ------> USART1_RX */ GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7; 8003d52: 2134 movs r1, #52 @ 0x34 8003d54: 187b adds r3, r7, r1 8003d56: 22c0 movs r2, #192 @ 0xc0 8003d58: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003d5a: 187b adds r3, r7, r1 8003d5c: 2202 movs r2, #2 8003d5e: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003d60: 187b adds r3, r7, r1 8003d62: 2200 movs r2, #0 8003d64: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003d66: 187b adds r3, r7, r1 8003d68: 2200 movs r2, #0 8003d6a: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF0_USART1; 8003d6c: 187b adds r3, r7, r1 8003d6e: 2200 movs r2, #0 8003d70: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); 8003d72: 187b adds r3, r7, r1 8003d74: 4a4c ldr r2, [pc, #304] @ (8003ea8 ) 8003d76: 0019 movs r1, r3 8003d78: 0010 movs r0, r2 8003d7a: f000 fd2b bl 80047d4 /* USER CODE BEGIN USART2_MspInit 1 */ /* USER CODE END USART2_MspInit 1 */ } } 8003d7e: e08b b.n 8003e98 else if(huart->Instance==USART2) 8003d80: 687b ldr r3, [r7, #4] 8003d82: 681b ldr r3, [r3, #0] 8003d84: 4a49 ldr r2, [pc, #292] @ (8003eac ) 8003d86: 4293 cmp r3, r2 8003d88: d000 beq.n 8003d8c 8003d8a: e085 b.n 8003e98 __HAL_RCC_USART2_CLK_ENABLE(); 8003d8c: 4b45 ldr r3, [pc, #276] @ (8003ea4 ) 8003d8e: 6bda ldr r2, [r3, #60] @ 0x3c 8003d90: 4b44 ldr r3, [pc, #272] @ (8003ea4 ) 8003d92: 2180 movs r1, #128 @ 0x80 8003d94: 0289 lsls r1, r1, #10 8003d96: 430a orrs r2, r1 8003d98: 63da str r2, [r3, #60] @ 0x3c 8003d9a: 4b42 ldr r3, [pc, #264] @ (8003ea4 ) 8003d9c: 6bda ldr r2, [r3, #60] @ 0x3c 8003d9e: 2380 movs r3, #128 @ 0x80 8003da0: 029b lsls r3, r3, #10 8003da2: 4013 ands r3, r2 8003da4: 60fb str r3, [r7, #12] 8003da6: 68fb ldr r3, [r7, #12] __HAL_RCC_GPIOA_CLK_ENABLE(); 8003da8: 4b3e ldr r3, [pc, #248] @ (8003ea4 ) 8003daa: 6b5a ldr r2, [r3, #52] @ 0x34 8003dac: 4b3d ldr r3, [pc, #244] @ (8003ea4 ) 8003dae: 2101 movs r1, #1 8003db0: 430a orrs r2, r1 8003db2: 635a str r2, [r3, #52] @ 0x34 8003db4: 4b3b ldr r3, [pc, #236] @ (8003ea4 ) 8003db6: 6b5b ldr r3, [r3, #52] @ 0x34 8003db8: 2201 movs r2, #1 8003dba: 4013 ands r3, r2 8003dbc: 60bb str r3, [r7, #8] 8003dbe: 68bb ldr r3, [r7, #8] GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5; 8003dc0: 2134 movs r1, #52 @ 0x34 8003dc2: 187b adds r3, r7, r1 8003dc4: 2232 movs r2, #50 @ 0x32 8003dc6: 601a str r2, [r3, #0] GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; 8003dc8: 187b adds r3, r7, r1 8003dca: 2202 movs r2, #2 8003dcc: 605a str r2, [r3, #4] GPIO_InitStruct.Pull = GPIO_NOPULL; 8003dce: 187b adds r3, r7, r1 8003dd0: 2200 movs r2, #0 8003dd2: 609a str r2, [r3, #8] GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; 8003dd4: 187b adds r3, r7, r1 8003dd6: 2200 movs r2, #0 8003dd8: 60da str r2, [r3, #12] GPIO_InitStruct.Alternate = GPIO_AF1_USART2; 8003dda: 187b adds r3, r7, r1 8003ddc: 2201 movs r2, #1 8003dde: 611a str r2, [r3, #16] HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); 8003de0: 187a adds r2, r7, r1 8003de2: 23a0 movs r3, #160 @ 0xa0 8003de4: 05db lsls r3, r3, #23 8003de6: 0011 movs r1, r2 8003de8: 0018 movs r0, r3 8003dea: f000 fcf3 bl 80047d4 hdma_usart2_rx.Instance = DMA1_Channel2; 8003dee: 4b30 ldr r3, [pc, #192] @ (8003eb0 ) 8003df0: 4a30 ldr r2, [pc, #192] @ (8003eb4 ) 8003df2: 601a str r2, [r3, #0] hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX; 8003df4: 4b2e ldr r3, [pc, #184] @ (8003eb0 ) 8003df6: 2234 movs r2, #52 @ 0x34 8003df8: 605a str r2, [r3, #4] hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; 8003dfa: 4b2d ldr r3, [pc, #180] @ (8003eb0 ) 8003dfc: 2200 movs r2, #0 8003dfe: 609a str r2, [r3, #8] hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE; 8003e00: 4b2b ldr r3, [pc, #172] @ (8003eb0 ) 8003e02: 2200 movs r2, #0 8003e04: 60da str r2, [r3, #12] hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE; 8003e06: 4b2a ldr r3, [pc, #168] @ (8003eb0 ) 8003e08: 2280 movs r2, #128 @ 0x80 8003e0a: 611a str r2, [r3, #16] hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8003e0c: 4b28 ldr r3, [pc, #160] @ (8003eb0 ) 8003e0e: 2200 movs r2, #0 8003e10: 615a str r2, [r3, #20] hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8003e12: 4b27 ldr r3, [pc, #156] @ (8003eb0 ) 8003e14: 2200 movs r2, #0 8003e16: 619a str r2, [r3, #24] hdma_usart2_rx.Init.Mode = DMA_NORMAL; 8003e18: 4b25 ldr r3, [pc, #148] @ (8003eb0 ) 8003e1a: 2200 movs r2, #0 8003e1c: 61da str r2, [r3, #28] hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM; 8003e1e: 4b24 ldr r3, [pc, #144] @ (8003eb0 ) 8003e20: 2280 movs r2, #128 @ 0x80 8003e22: 0152 lsls r2, r2, #5 8003e24: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK) 8003e26: 4b22 ldr r3, [pc, #136] @ (8003eb0 ) 8003e28: 0018 movs r0, r3 8003e2a: f000 fa7f bl 800432c 8003e2e: 1e03 subs r3, r0, #0 8003e30: d001 beq.n 8003e36 Error_Handler(); 8003e32: f7ff fe0b bl 8003a4c __HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx); 8003e36: 687b ldr r3, [r7, #4] 8003e38: 2180 movs r1, #128 @ 0x80 8003e3a: 4a1d ldr r2, [pc, #116] @ (8003eb0 ) 8003e3c: 505a str r2, [r3, r1] 8003e3e: 4b1c ldr r3, [pc, #112] @ (8003eb0 ) 8003e40: 687a ldr r2, [r7, #4] 8003e42: 629a str r2, [r3, #40] @ 0x28 hdma_usart2_tx.Instance = DMA1_Channel1; 8003e44: 4b1c ldr r3, [pc, #112] @ (8003eb8 ) 8003e46: 4a1d ldr r2, [pc, #116] @ (8003ebc ) 8003e48: 601a str r2, [r3, #0] hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX; 8003e4a: 4b1b ldr r3, [pc, #108] @ (8003eb8 ) 8003e4c: 2235 movs r2, #53 @ 0x35 8003e4e: 605a str r2, [r3, #4] hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; 8003e50: 4b19 ldr r3, [pc, #100] @ (8003eb8 ) 8003e52: 2210 movs r2, #16 8003e54: 609a str r2, [r3, #8] hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE; 8003e56: 4b18 ldr r3, [pc, #96] @ (8003eb8 ) 8003e58: 2200 movs r2, #0 8003e5a: 60da str r2, [r3, #12] hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE; 8003e5c: 4b16 ldr r3, [pc, #88] @ (8003eb8 ) 8003e5e: 2280 movs r2, #128 @ 0x80 8003e60: 611a str r2, [r3, #16] hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; 8003e62: 4b15 ldr r3, [pc, #84] @ (8003eb8 ) 8003e64: 2200 movs r2, #0 8003e66: 615a str r2, [r3, #20] hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; 8003e68: 4b13 ldr r3, [pc, #76] @ (8003eb8 ) 8003e6a: 2200 movs r2, #0 8003e6c: 619a str r2, [r3, #24] hdma_usart2_tx.Init.Mode = DMA_NORMAL; 8003e6e: 4b12 ldr r3, [pc, #72] @ (8003eb8 ) 8003e70: 2200 movs r2, #0 8003e72: 61da str r2, [r3, #28] hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH; 8003e74: 4b10 ldr r3, [pc, #64] @ (8003eb8 ) 8003e76: 2280 movs r2, #128 @ 0x80 8003e78: 0192 lsls r2, r2, #6 8003e7a: 621a str r2, [r3, #32] if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK) 8003e7c: 4b0e ldr r3, [pc, #56] @ (8003eb8 ) 8003e7e: 0018 movs r0, r3 8003e80: f000 fa54 bl 800432c 8003e84: 1e03 subs r3, r0, #0 8003e86: d001 beq.n 8003e8c Error_Handler(); 8003e88: f7ff fde0 bl 8003a4c __HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx); 8003e8c: 687b ldr r3, [r7, #4] 8003e8e: 4a0a ldr r2, [pc, #40] @ (8003eb8 ) 8003e90: 67da str r2, [r3, #124] @ 0x7c 8003e92: 4b09 ldr r3, [pc, #36] @ (8003eb8 ) 8003e94: 687a ldr r2, [r7, #4] 8003e96: 629a str r2, [r3, #40] @ 0x28 } 8003e98: 46c0 nop @ (mov r8, r8) 8003e9a: 46bd mov sp, r7 8003e9c: b013 add sp, #76 @ 0x4c 8003e9e: bd90 pop {r4, r7, pc} 8003ea0: 40013800 .word 0x40013800 8003ea4: 40021000 .word 0x40021000 8003ea8: 50000400 .word 0x50000400 8003eac: 40004400 .word 0x40004400 8003eb0: 200002f0 .word 0x200002f0 8003eb4: 4002001c .word 0x4002001c 8003eb8: 2000034c .word 0x2000034c 8003ebc: 40020008 .word 0x40020008 08003ec0 : /******************************************************************************/ /** * @brief This function handles Non maskable interrupt. */ void NMI_Handler(void) { 8003ec0: b580 push {r7, lr} 8003ec2: af00 add r7, sp, #0 /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ /* USER CODE END NonMaskableInt_IRQn 0 */ /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ while (1) 8003ec4: 46c0 nop @ (mov r8, r8) 8003ec6: e7fd b.n 8003ec4 08003ec8 : /** * @brief This function handles Hard fault interrupt. */ void HardFault_Handler(void) { 8003ec8: b580 push {r7, lr} 8003eca: af00 add r7, sp, #0 /* USER CODE BEGIN HardFault_IRQn 0 */ /* USER CODE END HardFault_IRQn 0 */ while (1) 8003ecc: 46c0 nop @ (mov r8, r8) 8003ece: e7fd b.n 8003ecc 08003ed0 : /** * @brief This function handles System service call via SWI instruction. */ void SVC_Handler(void) { 8003ed0: b580 push {r7, lr} 8003ed2: af00 add r7, sp, #0 /* USER CODE END SVCall_IRQn 0 */ /* USER CODE BEGIN SVCall_IRQn 1 */ /* USER CODE END SVCall_IRQn 1 */ } 8003ed4: 46c0 nop @ (mov r8, r8) 8003ed6: 46bd mov sp, r7 8003ed8: bd80 pop {r7, pc} 08003eda : /** * @brief This function handles Pendable request for system service. */ void PendSV_Handler(void) { 8003eda: b580 push {r7, lr} 8003edc: af00 add r7, sp, #0 /* USER CODE END PendSV_IRQn 0 */ /* USER CODE BEGIN PendSV_IRQn 1 */ /* USER CODE END PendSV_IRQn 1 */ } 8003ede: 46c0 nop @ (mov r8, r8) 8003ee0: 46bd mov sp, r7 8003ee2: bd80 pop {r7, pc} 08003ee4 : /** * @brief This function handles System tick timer. */ void SysTick_Handler(void) { 8003ee4: b580 push {r7, lr} 8003ee6: af00 add r7, sp, #0 /* USER CODE BEGIN SysTick_IRQn 0 */ /* USER CODE END SysTick_IRQn 0 */ HAL_IncTick(); 8003ee8: f000 f8e4 bl 80040b4 /* USER CODE BEGIN SysTick_IRQn 1 */ /* USER CODE END SysTick_IRQn 1 */ } 8003eec: 46c0 nop @ (mov r8, r8) 8003eee: 46bd mov sp, r7 8003ef0: bd80 pop {r7, pc} 08003ef2 : /** * @brief This function handles EXTI line 4 to 15 interrupts. */ void EXTI4_15_IRQHandler(void) { 8003ef2: b580 push {r7, lr} 8003ef4: af00 add r7, sp, #0 /* USER CODE BEGIN EXTI4_15_IRQn 0 */ /* USER CODE END EXTI4_15_IRQn 0 */ HAL_GPIO_EXTI_IRQHandler(SW2_Pin); 8003ef6: 2380 movs r3, #128 @ 0x80 8003ef8: 005b lsls r3, r3, #1 8003efa: 0018 movs r0, r3 8003efc: f000 fe16 bl 8004b2c HAL_GPIO_EXTI_IRQHandler(SW1_Pin); 8003f00: 2380 movs r3, #128 @ 0x80 8003f02: 009b lsls r3, r3, #2 8003f04: 0018 movs r0, r3 8003f06: f000 fe11 bl 8004b2c /* USER CODE BEGIN EXTI4_15_IRQn 1 */ /* USER CODE END EXTI4_15_IRQn 1 */ } 8003f0a: 46c0 nop @ (mov r8, r8) 8003f0c: 46bd mov sp, r7 8003f0e: bd80 pop {r7, pc} 08003f10 : /** * @brief This function handles DMA1 channel 1 interrupt. */ void DMA1_Channel1_IRQHandler(void) { 8003f10: b580 push {r7, lr} 8003f12: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ /* USER CODE END DMA1_Channel1_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_tx); 8003f14: 4b03 ldr r3, [pc, #12] @ (8003f24 ) 8003f16: 0018 movs r0, r3 8003f18: f000 fb1a bl 8004550 /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ /* USER CODE END DMA1_Channel1_IRQn 1 */ } 8003f1c: 46c0 nop @ (mov r8, r8) 8003f1e: 46bd mov sp, r7 8003f20: bd80 pop {r7, pc} 8003f22: 46c0 nop @ (mov r8, r8) 8003f24: 2000034c .word 0x2000034c 08003f28 : /** * @brief This function handles DMA1 channel 2 and channel 3 interrupts. */ void DMA1_Channel2_3_IRQHandler(void) { 8003f28: b580 push {r7, lr} 8003f2a: af00 add r7, sp, #0 /* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */ /* USER CODE END DMA1_Channel2_3_IRQn 0 */ HAL_DMA_IRQHandler(&hdma_usart2_rx); 8003f2c: 4b03 ldr r3, [pc, #12] @ (8003f3c ) 8003f2e: 0018 movs r0, r3 8003f30: f000 fb0e bl 8004550 /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */ /* USER CODE END DMA1_Channel2_3_IRQn 1 */ } 8003f34: 46c0 nop @ (mov r8, r8) 8003f36: 46bd mov sp, r7 8003f38: bd80 pop {r7, pc} 8003f3a: 46c0 nop @ (mov r8, r8) 8003f3c: 200002f0 .word 0x200002f0 08003f40 : /** * @brief This function handles TIM14 global interrupt. */ void TIM14_IRQHandler(void) { 8003f40: b580 push {r7, lr} 8003f42: af00 add r7, sp, #0 /* USER CODE BEGIN TIM14_IRQn 0 */ /* USER CODE END TIM14_IRQn 0 */ HAL_TIM_IRQHandler(&htim14); 8003f44: 4b03 ldr r3, [pc, #12] @ (8003f54 ) 8003f46: 0018 movs r0, r3 8003f48: f001 fde0 bl 8005b0c /* USER CODE BEGIN TIM14_IRQn 1 */ /* USER CODE END TIM14_IRQn 1 */ } 8003f4c: 46c0 nop @ (mov r8, r8) 8003f4e: 46bd mov sp, r7 8003f50: bd80 pop {r7, pc} 8003f52: 46c0 nop @ (mov r8, r8) 8003f54: 200000e4 .word 0x200000e4 08003f58 : /** * @brief This function handles TIM16 global interrupt. */ void TIM16_IRQHandler(void) { 8003f58: b580 push {r7, lr} 8003f5a: af00 add r7, sp, #0 /* USER CODE BEGIN TIM16_IRQn 0 */ /* USER CODE END TIM16_IRQn 0 */ HAL_TIM_IRQHandler(&htim16); 8003f5c: 4b03 ldr r3, [pc, #12] @ (8003f6c ) 8003f5e: 0018 movs r0, r3 8003f60: f001 fdd4 bl 8005b0c /* USER CODE BEGIN TIM16_IRQn 1 */ /* USER CODE END TIM16_IRQn 1 */ } 8003f64: 46c0 nop @ (mov r8, r8) 8003f66: 46bd mov sp, r7 8003f68: bd80 pop {r7, pc} 8003f6a: 46c0 nop @ (mov r8, r8) 8003f6c: 20000130 .word 0x20000130 08003f70 : /** * @brief This function handles TIM17 global interrupt. */ void TIM17_IRQHandler(void) { 8003f70: b580 push {r7, lr} 8003f72: af00 add r7, sp, #0 /* USER CODE BEGIN TIM17_IRQn 0 */ /* USER CODE END TIM17_IRQn 0 */ HAL_TIM_IRQHandler(&htim17); 8003f74: 4b03 ldr r3, [pc, #12] @ (8003f84 ) 8003f76: 0018 movs r0, r3 8003f78: f001 fdc8 bl 8005b0c /* USER CODE BEGIN TIM17_IRQn 1 */ /* USER CODE END TIM17_IRQn 1 */ } 8003f7c: 46c0 nop @ (mov r8, r8) 8003f7e: 46bd mov sp, r7 8003f80: bd80 pop {r7, pc} 8003f82: 46c0 nop @ (mov r8, r8) 8003f84: 2000017c .word 0x2000017c 08003f88 : * @brief Setup the microcontroller system. * @param None * @retval None */ void SystemInit(void) { 8003f88: b580 push {r7, lr} 8003f8a: af00 add r7, sp, #0 /* Configure the Vector Table location add offset address ------------------*/ #ifdef VECT_TAB_SRAM SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ #else SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ 8003f8c: 4b03 ldr r3, [pc, #12] @ (8003f9c ) 8003f8e: 2280 movs r2, #128 @ 0x80 8003f90: 0512 lsls r2, r2, #20 8003f92: 609a str r2, [r3, #8] #endif } 8003f94: 46c0 nop @ (mov r8, r8) 8003f96: 46bd mov sp, r7 8003f98: bd80 pop {r7, pc} 8003f9a: 46c0 nop @ (mov r8, r8) 8003f9c: e000ed00 .word 0xe000ed00 08003fa0 : .section .text.Reset_Handler .weak Reset_Handler .type Reset_Handler, %function Reset_Handler: ldr r0, =_estack 8003fa0: 480d ldr r0, [pc, #52] @ (8003fd8 ) mov sp, r0 /* set stack pointer */ 8003fa2: 4685 mov sp, r0 /* Call the clock system initialization function.*/ bl SystemInit 8003fa4: f7ff fff0 bl 8003f88 /* Copy the data segment initializers from flash to SRAM */ movs r1, #0 8003fa8: 2100 movs r1, #0 b LoopCopyDataInit 8003faa: e003 b.n 8003fb4 08003fac : CopyDataInit: ldr r3, =_sidata 8003fac: 4b0b ldr r3, [pc, #44] @ (8003fdc ) ldr r3, [r3, r1] 8003fae: 585b ldr r3, [r3, r1] str r3, [r0, r1] 8003fb0: 5043 str r3, [r0, r1] adds r1, r1, #4 8003fb2: 3104 adds r1, #4 08003fb4 : LoopCopyDataInit: ldr r0, =_sdata 8003fb4: 480a ldr r0, [pc, #40] @ (8003fe0 ) ldr r3, =_edata 8003fb6: 4b0b ldr r3, [pc, #44] @ (8003fe4 ) adds r2, r0, r1 8003fb8: 1842 adds r2, r0, r1 cmp r2, r3 8003fba: 429a cmp r2, r3 bcc CopyDataInit 8003fbc: d3f6 bcc.n 8003fac ldr r2, =_sbss 8003fbe: 4a0a ldr r2, [pc, #40] @ (8003fe8 ) b LoopFillZerobss 8003fc0: e002 b.n 8003fc8 08003fc2 : /* Zero fill the bss segment. */ FillZerobss: movs r3, #0 8003fc2: 2300 movs r3, #0 str r3, [r2] 8003fc4: 6013 str r3, [r2, #0] adds r2, r2, #4 8003fc6: 3204 adds r2, #4 08003fc8 : LoopFillZerobss: ldr r3, = _ebss 8003fc8: 4b08 ldr r3, [pc, #32] @ (8003fec ) cmp r2, r3 8003fca: 429a cmp r2, r3 bcc FillZerobss 8003fcc: d3f9 bcc.n 8003fc2 /* Call static constructors */ bl __libc_init_array 8003fce: f003 fe79 bl 8007cc4 <__libc_init_array> /* Call the application's entry point.*/ bl main 8003fd2: f7fc fd07 bl 80009e4
08003fd6 : LoopForever: b LoopForever 8003fd6: e7fe b.n 8003fd6 ldr r0, =_estack 8003fd8: 20003000 .word 0x20003000 ldr r3, =_sidata 8003fdc: 08007e9c .word 0x08007e9c ldr r0, =_sdata 8003fe0: 20000000 .word 0x20000000 ldr r3, =_edata 8003fe4: 20000030 .word 0x20000030 ldr r2, =_sbss 8003fe8: 20000030 .word 0x20000030 ldr r3, = _ebss 8003fec: 200005b0 .word 0x200005b0 08003ff0 : * @retval : None */ .section .text.Default_Handler,"ax",%progbits Default_Handler: Infinite_Loop: b Infinite_Loop 8003ff0: e7fe b.n 8003ff0 08003ff2 : * each 1ms in the SysTick_Handler() interrupt handler. * * @retval HAL status */ HAL_StatusTypeDef HAL_Init(void) { 8003ff2: b580 push {r7, lr} 8003ff4: b082 sub sp, #8 8003ff6: af00 add r7, sp, #0 HAL_StatusTypeDef status = HAL_OK; 8003ff8: 1dfb adds r3, r7, #7 8003ffa: 2200 movs r2, #0 8003ffc: 701a strb r2, [r3, #0] #if (PREFETCH_ENABLE != 0U) __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); #endif /* PREFETCH_ENABLE */ /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */ if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) 8003ffe: 2003 movs r0, #3 8004000: f000 f80e bl 8004020 8004004: 1e03 subs r3, r0, #0 8004006: d003 beq.n 8004010 { status = HAL_ERROR; 8004008: 1dfb adds r3, r7, #7 800400a: 2201 movs r2, #1 800400c: 701a strb r2, [r3, #0] 800400e: e001 b.n 8004014 } else { /* Init the low level hardware */ HAL_MspInit(); 8004010: f7ff fd22 bl 8003a58 } /* Return function status */ return status; 8004014: 1dfb adds r3, r7, #7 8004016: 781b ldrb r3, [r3, #0] } 8004018: 0018 movs r0, r3 800401a: 46bd mov sp, r7 800401c: b002 add sp, #8 800401e: bd80 pop {r7, pc} 08004020 : * implementation in user file. * @param TickPriority Tick interrupt priority. * @retval HAL status */ __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) { 8004020: b590 push {r4, r7, lr} 8004022: b085 sub sp, #20 8004024: af00 add r7, sp, #0 8004026: 6078 str r0, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8004028: 230f movs r3, #15 800402a: 18fb adds r3, r7, r3 800402c: 2200 movs r2, #0 800402e: 701a strb r2, [r3, #0] if ((uint32_t)uwTickFreq != 0UL) 8004030: 4b1d ldr r3, [pc, #116] @ (80040a8 ) 8004032: 781b ldrb r3, [r3, #0] 8004034: 2b00 cmp r3, #0 8004036: d02b beq.n 8004090 { /*Configure the SysTick to have interrupt in 1ms time basis*/ if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) == 0U) 8004038: 4b1c ldr r3, [pc, #112] @ (80040ac ) 800403a: 681c ldr r4, [r3, #0] 800403c: 4b1a ldr r3, [pc, #104] @ (80040a8 ) 800403e: 781b ldrb r3, [r3, #0] 8004040: 0019 movs r1, r3 8004042: 23fa movs r3, #250 @ 0xfa 8004044: 0098 lsls r0, r3, #2 8004046: f7fc f85f bl 8000108 <__udivsi3> 800404a: 0003 movs r3, r0 800404c: 0019 movs r1, r3 800404e: 0020 movs r0, r4 8004050: f7fc f85a bl 8000108 <__udivsi3> 8004054: 0003 movs r3, r0 8004056: 0018 movs r0, r3 8004058: f000 f95b bl 8004312 800405c: 1e03 subs r3, r0, #0 800405e: d112 bne.n 8004086 { /* Configure the SysTick IRQ priority */ if (TickPriority < (1UL << __NVIC_PRIO_BITS)) 8004060: 687b ldr r3, [r7, #4] 8004062: 2b03 cmp r3, #3 8004064: d80a bhi.n 800407c { HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); 8004066: 6879 ldr r1, [r7, #4] 8004068: 2301 movs r3, #1 800406a: 425b negs r3, r3 800406c: 2200 movs r2, #0 800406e: 0018 movs r0, r3 8004070: f000 f92a bl 80042c8 uwTickPrio = TickPriority; 8004074: 4b0e ldr r3, [pc, #56] @ (80040b0 ) 8004076: 687a ldr r2, [r7, #4] 8004078: 601a str r2, [r3, #0] 800407a: e00d b.n 8004098 } else { status = HAL_ERROR; 800407c: 230f movs r3, #15 800407e: 18fb adds r3, r7, r3 8004080: 2201 movs r2, #1 8004082: 701a strb r2, [r3, #0] 8004084: e008 b.n 8004098 } } else { status = HAL_ERROR; 8004086: 230f movs r3, #15 8004088: 18fb adds r3, r7, r3 800408a: 2201 movs r2, #1 800408c: 701a strb r2, [r3, #0] 800408e: e003 b.n 8004098 } } else { status = HAL_ERROR; 8004090: 230f movs r3, #15 8004092: 18fb adds r3, r7, r3 8004094: 2201 movs r2, #1 8004096: 701a strb r2, [r3, #0] } /* Return function status */ return status; 8004098: 230f movs r3, #15 800409a: 18fb adds r3, r7, r3 800409c: 781b ldrb r3, [r3, #0] } 800409e: 0018 movs r0, r3 80040a0: 46bd mov sp, r7 80040a2: b005 add sp, #20 80040a4: bd90 pop {r4, r7, pc} 80040a6: 46c0 nop @ (mov r8, r8) 80040a8: 2000002c .word 0x2000002c 80040ac: 20000024 .word 0x20000024 80040b0: 20000028 .word 0x20000028 080040b4 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval None */ __weak void HAL_IncTick(void) { 80040b4: b580 push {r7, lr} 80040b6: af00 add r7, sp, #0 uwTick += (uint32_t)uwTickFreq; 80040b8: 4b05 ldr r3, [pc, #20] @ (80040d0 ) 80040ba: 781b ldrb r3, [r3, #0] 80040bc: 001a movs r2, r3 80040be: 4b05 ldr r3, [pc, #20] @ (80040d4 ) 80040c0: 681b ldr r3, [r3, #0] 80040c2: 18d2 adds r2, r2, r3 80040c4: 4b03 ldr r3, [pc, #12] @ (80040d4 ) 80040c6: 601a str r2, [r3, #0] } 80040c8: 46c0 nop @ (mov r8, r8) 80040ca: 46bd mov sp, r7 80040cc: bd80 pop {r7, pc} 80040ce: 46c0 nop @ (mov r8, r8) 80040d0: 2000002c .word 0x2000002c 80040d4: 200005ac .word 0x200005ac 080040d8 : * @note This function is declared as __weak to be overwritten in case of other * implementations in user file. * @retval tick value */ __weak uint32_t HAL_GetTick(void) { 80040d8: b580 push {r7, lr} 80040da: af00 add r7, sp, #0 return uwTick; 80040dc: 4b02 ldr r3, [pc, #8] @ (80040e8 ) 80040de: 681b ldr r3, [r3, #0] } 80040e0: 0018 movs r0, r3 80040e2: 46bd mov sp, r7 80040e4: bd80 pop {r7, pc} 80040e6: 46c0 nop @ (mov r8, r8) 80040e8: 200005ac .word 0x200005ac 080040ec : * implementations in user file. * @param Delay specifies the delay time length, in milliseconds. * @retval None */ __weak void HAL_Delay(uint32_t Delay) { 80040ec: b580 push {r7, lr} 80040ee: b084 sub sp, #16 80040f0: af00 add r7, sp, #0 80040f2: 6078 str r0, [r7, #4] uint32_t tickstart = HAL_GetTick(); 80040f4: f7ff fff0 bl 80040d8 80040f8: 0003 movs r3, r0 80040fa: 60bb str r3, [r7, #8] uint32_t wait = Delay; 80040fc: 687b ldr r3, [r7, #4] 80040fe: 60fb str r3, [r7, #12] /* Add a freq to guarantee minimum wait */ if (wait < HAL_MAX_DELAY) 8004100: 68fb ldr r3, [r7, #12] 8004102: 3301 adds r3, #1 8004104: d005 beq.n 8004112 { wait += (uint32_t)(uwTickFreq); 8004106: 4b0a ldr r3, [pc, #40] @ (8004130 ) 8004108: 781b ldrb r3, [r3, #0] 800410a: 001a movs r2, r3 800410c: 68fb ldr r3, [r7, #12] 800410e: 189b adds r3, r3, r2 8004110: 60fb str r3, [r7, #12] } while ((HAL_GetTick() - tickstart) < wait) 8004112: 46c0 nop @ (mov r8, r8) 8004114: f7ff ffe0 bl 80040d8 8004118: 0002 movs r2, r0 800411a: 68bb ldr r3, [r7, #8] 800411c: 1ad3 subs r3, r2, r3 800411e: 68fa ldr r2, [r7, #12] 8004120: 429a cmp r2, r3 8004122: d8f7 bhi.n 8004114 { } } 8004124: 46c0 nop @ (mov r8, r8) 8004126: 46c0 nop @ (mov r8, r8) 8004128: 46bd mov sp, r7 800412a: b004 add sp, #16 800412c: bd80 pop {r7, pc} 800412e: 46c0 nop @ (mov r8, r8) 8004130: 2000002c .word 0x2000002c 08004134 : /** * @brief Returns first word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw0(void) { 8004134: b580 push {r7, lr} 8004136: af00 add r7, sp, #0 return (READ_REG(*((uint32_t *)UID_BASE))); 8004138: 4b02 ldr r3, [pc, #8] @ (8004144 ) 800413a: 681b ldr r3, [r3, #0] } 800413c: 0018 movs r0, r3 800413e: 46bd mov sp, r7 8004140: bd80 pop {r7, pc} 8004142: 46c0 nop @ (mov r8, r8) 8004144: 1fff7550 .word 0x1fff7550 08004148 : /** * @brief Returns second word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw1(void) { 8004148: b580 push {r7, lr} 800414a: af00 add r7, sp, #0 return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); 800414c: 4b02 ldr r3, [pc, #8] @ (8004158 ) 800414e: 681b ldr r3, [r3, #0] } 8004150: 0018 movs r0, r3 8004152: 46bd mov sp, r7 8004154: bd80 pop {r7, pc} 8004156: 46c0 nop @ (mov r8, r8) 8004158: 1fff7554 .word 0x1fff7554 0800415c : /** * @brief Returns third word of the unique device identifier (UID based on 96 bits) * @retval Device identifier */ uint32_t HAL_GetUIDw2(void) { 800415c: b580 push {r7, lr} 800415e: af00 add r7, sp, #0 return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); 8004160: 4b02 ldr r3, [pc, #8] @ (800416c ) 8004162: 681b ldr r3, [r3, #0] } 8004164: 0018 movs r0, r3 8004166: 46bd mov sp, r7 8004168: bd80 pop {r7, pc} 800416a: 46c0 nop @ (mov r8, r8) 800416c: 1fff7558 .word 0x1fff7558 08004170 <__NVIC_EnableIRQ>: { 8004170: b580 push {r7, lr} 8004172: b082 sub sp, #8 8004174: af00 add r7, sp, #0 8004176: 0002 movs r2, r0 8004178: 1dfb adds r3, r7, #7 800417a: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 800417c: 1dfb adds r3, r7, #7 800417e: 781b ldrb r3, [r3, #0] 8004180: 2b7f cmp r3, #127 @ 0x7f 8004182: d809 bhi.n 8004198 <__NVIC_EnableIRQ+0x28> NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); 8004184: 1dfb adds r3, r7, #7 8004186: 781b ldrb r3, [r3, #0] 8004188: 001a movs r2, r3 800418a: 231f movs r3, #31 800418c: 401a ands r2, r3 800418e: 4b04 ldr r3, [pc, #16] @ (80041a0 <__NVIC_EnableIRQ+0x30>) 8004190: 2101 movs r1, #1 8004192: 4091 lsls r1, r2 8004194: 000a movs r2, r1 8004196: 601a str r2, [r3, #0] } 8004198: 46c0 nop @ (mov r8, r8) 800419a: 46bd mov sp, r7 800419c: b002 add sp, #8 800419e: bd80 pop {r7, pc} 80041a0: e000e100 .word 0xe000e100 080041a4 <__NVIC_SetPriority>: { 80041a4: b590 push {r4, r7, lr} 80041a6: b083 sub sp, #12 80041a8: af00 add r7, sp, #0 80041aa: 0002 movs r2, r0 80041ac: 6039 str r1, [r7, #0] 80041ae: 1dfb adds r3, r7, #7 80041b0: 701a strb r2, [r3, #0] if ((int32_t)(IRQn) >= 0) 80041b2: 1dfb adds r3, r7, #7 80041b4: 781b ldrb r3, [r3, #0] 80041b6: 2b7f cmp r3, #127 @ 0x7f 80041b8: d828 bhi.n 800420c <__NVIC_SetPriority+0x68> NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80041ba: 4a2f ldr r2, [pc, #188] @ (8004278 <__NVIC_SetPriority+0xd4>) 80041bc: 1dfb adds r3, r7, #7 80041be: 781b ldrb r3, [r3, #0] 80041c0: b25b sxtb r3, r3 80041c2: 089b lsrs r3, r3, #2 80041c4: 33c0 adds r3, #192 @ 0xc0 80041c6: 009b lsls r3, r3, #2 80041c8: 589b ldr r3, [r3, r2] 80041ca: 1dfa adds r2, r7, #7 80041cc: 7812 ldrb r2, [r2, #0] 80041ce: 0011 movs r1, r2 80041d0: 2203 movs r2, #3 80041d2: 400a ands r2, r1 80041d4: 00d2 lsls r2, r2, #3 80041d6: 21ff movs r1, #255 @ 0xff 80041d8: 4091 lsls r1, r2 80041da: 000a movs r2, r1 80041dc: 43d2 mvns r2, r2 80041de: 401a ands r2, r3 80041e0: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 80041e2: 683b ldr r3, [r7, #0] 80041e4: 019b lsls r3, r3, #6 80041e6: 22ff movs r2, #255 @ 0xff 80041e8: 401a ands r2, r3 80041ea: 1dfb adds r3, r7, #7 80041ec: 781b ldrb r3, [r3, #0] 80041ee: 0018 movs r0, r3 80041f0: 2303 movs r3, #3 80041f2: 4003 ands r3, r0 80041f4: 00db lsls r3, r3, #3 80041f6: 409a lsls r2, r3 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 80041f8: 481f ldr r0, [pc, #124] @ (8004278 <__NVIC_SetPriority+0xd4>) 80041fa: 1dfb adds r3, r7, #7 80041fc: 781b ldrb r3, [r3, #0] 80041fe: b25b sxtb r3, r3 8004200: 089b lsrs r3, r3, #2 8004202: 430a orrs r2, r1 8004204: 33c0 adds r3, #192 @ 0xc0 8004206: 009b lsls r3, r3, #2 8004208: 501a str r2, [r3, r0] } 800420a: e031 b.n 8004270 <__NVIC_SetPriority+0xcc> SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 800420c: 4a1b ldr r2, [pc, #108] @ (800427c <__NVIC_SetPriority+0xd8>) 800420e: 1dfb adds r3, r7, #7 8004210: 781b ldrb r3, [r3, #0] 8004212: 0019 movs r1, r3 8004214: 230f movs r3, #15 8004216: 400b ands r3, r1 8004218: 3b08 subs r3, #8 800421a: 089b lsrs r3, r3, #2 800421c: 3306 adds r3, #6 800421e: 009b lsls r3, r3, #2 8004220: 18d3 adds r3, r2, r3 8004222: 3304 adds r3, #4 8004224: 681b ldr r3, [r3, #0] 8004226: 1dfa adds r2, r7, #7 8004228: 7812 ldrb r2, [r2, #0] 800422a: 0011 movs r1, r2 800422c: 2203 movs r2, #3 800422e: 400a ands r2, r1 8004230: 00d2 lsls r2, r2, #3 8004232: 21ff movs r1, #255 @ 0xff 8004234: 4091 lsls r1, r2 8004236: 000a movs r2, r1 8004238: 43d2 mvns r2, r2 800423a: 401a ands r2, r3 800423c: 0011 movs r1, r2 (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); 800423e: 683b ldr r3, [r7, #0] 8004240: 019b lsls r3, r3, #6 8004242: 22ff movs r2, #255 @ 0xff 8004244: 401a ands r2, r3 8004246: 1dfb adds r3, r7, #7 8004248: 781b ldrb r3, [r3, #0] 800424a: 0018 movs r0, r3 800424c: 2303 movs r3, #3 800424e: 4003 ands r3, r0 8004250: 00db lsls r3, r3, #3 8004252: 409a lsls r2, r3 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | 8004254: 4809 ldr r0, [pc, #36] @ (800427c <__NVIC_SetPriority+0xd8>) 8004256: 1dfb adds r3, r7, #7 8004258: 781b ldrb r3, [r3, #0] 800425a: 001c movs r4, r3 800425c: 230f movs r3, #15 800425e: 4023 ands r3, r4 8004260: 3b08 subs r3, #8 8004262: 089b lsrs r3, r3, #2 8004264: 430a orrs r2, r1 8004266: 3306 adds r3, #6 8004268: 009b lsls r3, r3, #2 800426a: 18c3 adds r3, r0, r3 800426c: 3304 adds r3, #4 800426e: 601a str r2, [r3, #0] } 8004270: 46c0 nop @ (mov r8, r8) 8004272: 46bd mov sp, r7 8004274: b003 add sp, #12 8004276: bd90 pop {r4, r7, pc} 8004278: e000e100 .word 0xe000e100 800427c: e000ed00 .word 0xe000ed00 08004280 : \note When the variable __Vendor_SysTickConfig is set to 1, then the function SysTick_Config is not included. In this case, the file device.h must contain a vendor-specific implementation of this function. */ __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) { 8004280: b580 push {r7, lr} 8004282: b082 sub sp, #8 8004284: af00 add r7, sp, #0 8004286: 6078 str r0, [r7, #4] if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) 8004288: 687b ldr r3, [r7, #4] 800428a: 1e5a subs r2, r3, #1 800428c: 2380 movs r3, #128 @ 0x80 800428e: 045b lsls r3, r3, #17 8004290: 429a cmp r2, r3 8004292: d301 bcc.n 8004298 { return (1UL); /* Reload value impossible */ 8004294: 2301 movs r3, #1 8004296: e010 b.n 80042ba } SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ 8004298: 4b0a ldr r3, [pc, #40] @ (80042c4 ) 800429a: 687a ldr r2, [r7, #4] 800429c: 3a01 subs r2, #1 800429e: 605a str r2, [r3, #4] NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ 80042a0: 2301 movs r3, #1 80042a2: 425b negs r3, r3 80042a4: 2103 movs r1, #3 80042a6: 0018 movs r0, r3 80042a8: f7ff ff7c bl 80041a4 <__NVIC_SetPriority> SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ 80042ac: 4b05 ldr r3, [pc, #20] @ (80042c4 ) 80042ae: 2200 movs r2, #0 80042b0: 609a str r2, [r3, #8] SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 80042b2: 4b04 ldr r3, [pc, #16] @ (80042c4 ) 80042b4: 2207 movs r2, #7 80042b6: 601a str r2, [r3, #0] SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ return (0UL); /* Function successful */ 80042b8: 2300 movs r3, #0 } 80042ba: 0018 movs r0, r3 80042bc: 46bd mov sp, r7 80042be: b002 add sp, #8 80042c0: bd80 pop {r7, pc} 80042c2: 46c0 nop @ (mov r8, r8) 80042c4: e000e010 .word 0xe000e010 080042c8 : * with stm32c0xx devices, this parameter is a dummy value and it is ignored, because * no subpriority supported in Cortex M0+ based products. * @retval None */ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) { 80042c8: b580 push {r7, lr} 80042ca: b084 sub sp, #16 80042cc: af00 add r7, sp, #0 80042ce: 60b9 str r1, [r7, #8] 80042d0: 607a str r2, [r7, #4] 80042d2: 210f movs r1, #15 80042d4: 187b adds r3, r7, r1 80042d6: 1c02 adds r2, r0, #0 80042d8: 701a strb r2, [r3, #0] /* Prevent unused argument(s) compilation warning */ UNUSED(SubPriority); /* Check the parameters */ assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); NVIC_SetPriority(IRQn, PreemptPriority); 80042da: 68ba ldr r2, [r7, #8] 80042dc: 187b adds r3, r7, r1 80042de: 781b ldrb r3, [r3, #0] 80042e0: b25b sxtb r3, r3 80042e2: 0011 movs r1, r2 80042e4: 0018 movs r0, r3 80042e6: f7ff ff5d bl 80041a4 <__NVIC_SetPriority> } 80042ea: 46c0 nop @ (mov r8, r8) 80042ec: 46bd mov sp, r7 80042ee: b004 add sp, #16 80042f0: bd80 pop {r7, pc} 080042f2 : * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate * CMSIS device file (stm32c0xxxx.h)) * @retval None */ void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) { 80042f2: b580 push {r7, lr} 80042f4: b082 sub sp, #8 80042f6: af00 add r7, sp, #0 80042f8: 0002 movs r2, r0 80042fa: 1dfb adds r3, r7, #7 80042fc: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); /* Enable interrupt */ NVIC_EnableIRQ(IRQn); 80042fe: 1dfb adds r3, r7, #7 8004300: 781b ldrb r3, [r3, #0] 8004302: b25b sxtb r3, r3 8004304: 0018 movs r0, r3 8004306: f7ff ff33 bl 8004170 <__NVIC_EnableIRQ> } 800430a: 46c0 nop @ (mov r8, r8) 800430c: 46bd mov sp, r7 800430e: b002 add sp, #8 8004310: bd80 pop {r7, pc} 08004312 : * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) { 8004312: b580 push {r7, lr} 8004314: b082 sub sp, #8 8004316: af00 add r7, sp, #0 8004318: 6078 str r0, [r7, #4] return SysTick_Config(TicksNumb); 800431a: 687b ldr r3, [r7, #4] 800431c: 0018 movs r0, r3 800431e: f7ff ffaf bl 8004280 8004322: 0003 movs r3, r0 } 8004324: 0018 movs r0, r3 8004326: 46bd mov sp, r7 8004328: b002 add sp, #8 800432a: bd80 pop {r7, pc} 0800432c : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) { 800432c: b580 push {r7, lr} 800432e: b082 sub sp, #8 8004330: af00 add r7, sp, #0 8004332: 6078 str r0, [r7, #4] /* Check the DMA handle allocation */ if (hdma == NULL) 8004334: 687b ldr r3, [r7, #4] 8004336: 2b00 cmp r3, #0 8004338: d101 bne.n 800433e { return HAL_ERROR; 800433a: 2301 movs r3, #1 800433c: e077 b.n 800442e assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); assert_param(IS_DMA_MODE(hdma->Init.Mode)); assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); /* calculation of the channel index */ hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \ 800433e: 687b ldr r3, [r7, #4] 8004340: 681b ldr r3, [r3, #0] 8004342: 4a3d ldr r2, [pc, #244] @ (8004438 ) 8004344: 4694 mov ip, r2 8004346: 4463 add r3, ip 8004348: 2114 movs r1, #20 800434a: 0018 movs r0, r3 800434c: f7fb fedc bl 8000108 <__udivsi3> 8004350: 0003 movs r3, r0 (uint32_t)DMA1_Channel1)) << 2U; 8004352: 009a lsls r2, r3, #2 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \ 8004354: 687b ldr r3, [r7, #4] 8004356: 641a str r2, [r3, #64] @ 0x40 /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8004358: 687b ldr r3, [r7, #4] 800435a: 2225 movs r2, #37 @ 0x25 800435c: 2102 movs r1, #2 800435e: 5499 strb r1, [r3, r2] /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ 8004360: 687b ldr r3, [r7, #4] 8004362: 681b ldr r3, [r3, #0] 8004364: 681a ldr r2, [r3, #0] 8004366: 687b ldr r3, [r7, #4] 8004368: 681b ldr r3, [r3, #0] 800436a: 4934 ldr r1, [pc, #208] @ (800443c ) 800436c: 400a ands r2, r1 800436e: 601a str r2, [r3, #0] DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ DMA_CCR_DIR | DMA_CCR_MEM2MEM)); /* Set the DMA Channel configuration */ SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ 8004370: 687b ldr r3, [r7, #4] 8004372: 681b ldr r3, [r3, #0] 8004374: 6819 ldr r1, [r3, #0] 8004376: 687b ldr r3, [r7, #4] 8004378: 689a ldr r2, [r3, #8] 800437a: 687b ldr r3, [r7, #4] 800437c: 68db ldr r3, [r3, #12] 800437e: 431a orrs r2, r3 8004380: 687b ldr r3, [r7, #4] 8004382: 691b ldr r3, [r3, #16] 8004384: 431a orrs r2, r3 8004386: 687b ldr r3, [r7, #4] 8004388: 695b ldr r3, [r3, #20] 800438a: 431a orrs r2, r3 800438c: 687b ldr r3, [r7, #4] 800438e: 699b ldr r3, [r3, #24] 8004390: 431a orrs r2, r3 8004392: 687b ldr r3, [r7, #4] 8004394: 69db ldr r3, [r3, #28] 8004396: 431a orrs r2, r3 8004398: 687b ldr r3, [r7, #4] 800439a: 6a1b ldr r3, [r3, #32] 800439c: 431a orrs r2, r3 800439e: 687b ldr r3, [r7, #4] 80043a0: 681b ldr r3, [r3, #0] 80043a2: 430a orrs r2, r1 80043a4: 601a str r2, [r3, #0] hdma->Init.Mode | hdma->Init.Priority)); /* Initialize parameters for DMAMUX channel : DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ DMA_CalcDMAMUXChannelBaseAndMask(hdma); 80043a6: 687b ldr r3, [r7, #4] 80043a8: 0018 movs r0, r3 80043aa: f000 f9c3 bl 8004734 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 80043ae: 687b ldr r3, [r7, #4] 80043b0: 689a ldr r2, [r3, #8] 80043b2: 2380 movs r3, #128 @ 0x80 80043b4: 01db lsls r3, r3, #7 80043b6: 429a cmp r2, r3 80043b8: d102 bne.n 80043c0 { /* if memory to memory force the request to 0*/ hdma->Init.Request = DMA_REQUEST_MEM2MEM; 80043ba: 687b ldr r3, [r7, #4] 80043bc: 2200 movs r2, #0 80043be: 605a str r2, [r3, #4] } /* Set peripheral request to DMAMUX channel */ hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 80043c0: 687b ldr r3, [r7, #4] 80043c2: 685a ldr r2, [r3, #4] 80043c4: 687b ldr r3, [r7, #4] 80043c6: 6c5b ldr r3, [r3, #68] @ 0x44 80043c8: 21ff movs r1, #255 @ 0xff 80043ca: 400a ands r2, r1 80043cc: 601a str r2, [r3, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80043ce: 687b ldr r3, [r7, #4] 80043d0: 6c9b ldr r3, [r3, #72] @ 0x48 80043d2: 687a ldr r2, [r7, #4] 80043d4: 6cd2 ldr r2, [r2, #76] @ 0x4c 80043d6: 605a str r2, [r3, #4] if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 80043d8: 687b ldr r3, [r7, #4] 80043da: 685b ldr r3, [r3, #4] 80043dc: 2b00 cmp r3, #0 80043de: d011 beq.n 8004404 80043e0: 687b ldr r3, [r7, #4] 80043e2: 685b ldr r3, [r3, #4] 80043e4: 2b04 cmp r3, #4 80043e6: d80d bhi.n 8004404 { /* Initialize parameters for DMAMUX request generator : DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask */ DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 80043e8: 687b ldr r3, [r7, #4] 80043ea: 0018 movs r0, r3 80043ec: f000 f9ce bl 800478c /* Reset the DMAMUX request generator register*/ hdma->DMAmuxRequestGen->RGCR = 0U; 80043f0: 687b ldr r3, [r7, #4] 80043f2: 6d1b ldr r3, [r3, #80] @ 0x50 80043f4: 2200 movs r2, #0 80043f6: 601a str r2, [r3, #0] /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80043f8: 687b ldr r3, [r7, #4] 80043fa: 6d5b ldr r3, [r3, #84] @ 0x54 80043fc: 687a ldr r2, [r7, #4] 80043fe: 6d92 ldr r2, [r2, #88] @ 0x58 8004400: 605a str r2, [r3, #4] 8004402: e008 b.n 8004416 } else { hdma->DMAmuxRequestGen = 0U; 8004404: 687b ldr r3, [r7, #4] 8004406: 2200 movs r2, #0 8004408: 651a str r2, [r3, #80] @ 0x50 hdma->DMAmuxRequestGenStatus = 0U; 800440a: 687b ldr r3, [r7, #4] 800440c: 2200 movs r2, #0 800440e: 655a str r2, [r3, #84] @ 0x54 hdma->DMAmuxRequestGenStatusMask = 0U; 8004410: 687b ldr r3, [r7, #4] 8004412: 2200 movs r2, #0 8004414: 659a str r2, [r3, #88] @ 0x58 } /* Initialize the error code */ hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8004416: 687b ldr r3, [r7, #4] 8004418: 2200 movs r2, #0 800441a: 63da str r2, [r3, #60] @ 0x3c /* Initialize the DMA state*/ hdma->State = HAL_DMA_STATE_READY; 800441c: 687b ldr r3, [r7, #4] 800441e: 2225 movs r2, #37 @ 0x25 8004420: 2101 movs r1, #1 8004422: 5499 strb r1, [r3, r2] /* Release Lock */ __HAL_UNLOCK(hdma); 8004424: 687b ldr r3, [r7, #4] 8004426: 2224 movs r2, #36 @ 0x24 8004428: 2100 movs r1, #0 800442a: 5499 strb r1, [r3, r2] return HAL_OK; 800442c: 2300 movs r3, #0 } 800442e: 0018 movs r0, r3 8004430: 46bd mov sp, r7 8004432: b002 add sp, #8 8004434: bd80 pop {r7, pc} 8004436: 46c0 nop @ (mov r8, r8) 8004438: bffdfff8 .word 0xbffdfff8 800443c: ffff800f .word 0xffff800f 08004440 : * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 8004440: b580 push {r7, lr} 8004442: b086 sub sp, #24 8004444: af00 add r7, sp, #0 8004446: 60f8 str r0, [r7, #12] 8004448: 60b9 str r1, [r7, #8] 800444a: 607a str r2, [r7, #4] 800444c: 603b str r3, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 800444e: 2317 movs r3, #23 8004450: 18fb adds r3, r7, r3 8004452: 2200 movs r2, #0 8004454: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_DMA_BUFFER_SIZE(DataLength)); /* Process locked */ __HAL_LOCK(hdma); 8004456: 68fb ldr r3, [r7, #12] 8004458: 2224 movs r2, #36 @ 0x24 800445a: 5c9b ldrb r3, [r3, r2] 800445c: 2b01 cmp r3, #1 800445e: d101 bne.n 8004464 8004460: 2302 movs r3, #2 8004462: e070 b.n 8004546 8004464: 68fb ldr r3, [r7, #12] 8004466: 2224 movs r2, #36 @ 0x24 8004468: 2101 movs r1, #1 800446a: 5499 strb r1, [r3, r2] if (HAL_DMA_STATE_READY == hdma->State) 800446c: 68fb ldr r3, [r7, #12] 800446e: 2225 movs r2, #37 @ 0x25 8004470: 5c9b ldrb r3, [r3, r2] 8004472: b2db uxtb r3, r3 8004474: 2b01 cmp r3, #1 8004476: d157 bne.n 8004528 { /* Change DMA peripheral state */ hdma->State = HAL_DMA_STATE_BUSY; 8004478: 68fb ldr r3, [r7, #12] 800447a: 2225 movs r2, #37 @ 0x25 800447c: 2102 movs r1, #2 800447e: 5499 strb r1, [r3, r2] hdma->ErrorCode = HAL_DMA_ERROR_NONE; 8004480: 68fb ldr r3, [r7, #12] 8004482: 2200 movs r2, #0 8004484: 63da str r2, [r3, #60] @ 0x3c /* Disable the peripheral */ __HAL_DMA_DISABLE(hdma); 8004486: 68fb ldr r3, [r7, #12] 8004488: 681b ldr r3, [r3, #0] 800448a: 681a ldr r2, [r3, #0] 800448c: 68fb ldr r3, [r7, #12] 800448e: 681b ldr r3, [r3, #0] 8004490: 2101 movs r1, #1 8004492: 438a bics r2, r1 8004494: 601a str r2, [r3, #0] /* Configure the source, destination address and the data length & clear flags*/ DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 8004496: 683b ldr r3, [r7, #0] 8004498: 687a ldr r2, [r7, #4] 800449a: 68b9 ldr r1, [r7, #8] 800449c: 68f8 ldr r0, [r7, #12] 800449e: f000 f909 bl 80046b4 /* Enable the transfer complete interrupt */ /* Enable the transfer Error interrupt */ if (NULL != hdma->XferHalfCpltCallback) 80044a2: 68fb ldr r3, [r7, #12] 80044a4: 6b1b ldr r3, [r3, #48] @ 0x30 80044a6: 2b00 cmp r3, #0 80044a8: d008 beq.n 80044bc { /* Enable the Half transfer complete interrupt as well */ __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 80044aa: 68fb ldr r3, [r7, #12] 80044ac: 681b ldr r3, [r3, #0] 80044ae: 681a ldr r2, [r3, #0] 80044b0: 68fb ldr r3, [r7, #12] 80044b2: 681b ldr r3, [r3, #0] 80044b4: 210e movs r1, #14 80044b6: 430a orrs r2, r1 80044b8: 601a str r2, [r3, #0] 80044ba: e00f b.n 80044dc } else { __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 80044bc: 68fb ldr r3, [r7, #12] 80044be: 681b ldr r3, [r3, #0] 80044c0: 681a ldr r2, [r3, #0] 80044c2: 68fb ldr r3, [r7, #12] 80044c4: 681b ldr r3, [r3, #0] 80044c6: 2104 movs r1, #4 80044c8: 438a bics r2, r1 80044ca: 601a str r2, [r3, #0] __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 80044cc: 68fb ldr r3, [r7, #12] 80044ce: 681b ldr r3, [r3, #0] 80044d0: 681a ldr r2, [r3, #0] 80044d2: 68fb ldr r3, [r7, #12] 80044d4: 681b ldr r3, [r3, #0] 80044d6: 210a movs r1, #10 80044d8: 430a orrs r2, r1 80044da: 601a str r2, [r3, #0] } /* Check if DMAMUX Synchronization is enabled*/ if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 80044dc: 68fb ldr r3, [r7, #12] 80044de: 6c5b ldr r3, [r3, #68] @ 0x44 80044e0: 681a ldr r2, [r3, #0] 80044e2: 2380 movs r3, #128 @ 0x80 80044e4: 025b lsls r3, r3, #9 80044e6: 4013 ands r3, r2 80044e8: d008 beq.n 80044fc { /* Enable DMAMUX sync overrun IT*/ hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 80044ea: 68fb ldr r3, [r7, #12] 80044ec: 6c5b ldr r3, [r3, #68] @ 0x44 80044ee: 681a ldr r2, [r3, #0] 80044f0: 68fb ldr r3, [r7, #12] 80044f2: 6c5b ldr r3, [r3, #68] @ 0x44 80044f4: 2180 movs r1, #128 @ 0x80 80044f6: 0049 lsls r1, r1, #1 80044f8: 430a orrs r2, r1 80044fa: 601a str r2, [r3, #0] } if (hdma->DMAmuxRequestGen != 0U) 80044fc: 68fb ldr r3, [r7, #12] 80044fe: 6d1b ldr r3, [r3, #80] @ 0x50 8004500: 2b00 cmp r3, #0 8004502: d008 beq.n 8004516 { /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ /* enable the request gen overrun IT*/ hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 8004504: 68fb ldr r3, [r7, #12] 8004506: 6d1b ldr r3, [r3, #80] @ 0x50 8004508: 681a ldr r2, [r3, #0] 800450a: 68fb ldr r3, [r7, #12] 800450c: 6d1b ldr r3, [r3, #80] @ 0x50 800450e: 2180 movs r1, #128 @ 0x80 8004510: 0049 lsls r1, r1, #1 8004512: 430a orrs r2, r1 8004514: 601a str r2, [r3, #0] } /* Enable the Peripheral */ __HAL_DMA_ENABLE(hdma); 8004516: 68fb ldr r3, [r7, #12] 8004518: 681b ldr r3, [r3, #0] 800451a: 681a ldr r2, [r3, #0] 800451c: 68fb ldr r3, [r7, #12] 800451e: 681b ldr r3, [r3, #0] 8004520: 2101 movs r1, #1 8004522: 430a orrs r2, r1 8004524: 601a str r2, [r3, #0] 8004526: e007 b.n 8004538 } else { /* Process Unlocked */ __HAL_UNLOCK(hdma); 8004528: 68fb ldr r3, [r7, #12] 800452a: 2224 movs r2, #36 @ 0x24 800452c: 2100 movs r1, #0 800452e: 5499 strb r1, [r3, r2] /* Remain BUSY */ status = HAL_BUSY; 8004530: 2317 movs r3, #23 8004532: 18fb adds r3, r7, r3 8004534: 2202 movs r2, #2 8004536: 701a strb r2, [r3, #0] } /* Process unlocked */ __HAL_UNLOCK(hdma); 8004538: 68fb ldr r3, [r7, #12] 800453a: 2224 movs r2, #36 @ 0x24 800453c: 2100 movs r1, #0 800453e: 5499 strb r1, [r3, r2] return status; 8004540: 2317 movs r3, #23 8004542: 18fb adds r3, r7, r3 8004544: 781b ldrb r3, [r3, #0] } 8004546: 0018 movs r0, r3 8004548: 46bd mov sp, r7 800454a: b006 add sp, #24 800454c: bd80 pop {r7, pc} ... 08004550 : * @param hdma: pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Channel. * @retval None */ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) { 8004550: b580 push {r7, lr} 8004552: b084 sub sp, #16 8004554: af00 add r7, sp, #0 8004556: 6078 str r0, [r7, #4] uint32_t flag_it = DMA1->ISR; 8004558: 4b55 ldr r3, [pc, #340] @ (80046b0 ) 800455a: 681b ldr r3, [r3, #0] 800455c: 60fb str r3, [r7, #12] uint32_t source_it = hdma->Instance->CCR; 800455e: 687b ldr r3, [r7, #4] 8004560: 681b ldr r3, [r3, #0] 8004562: 681b ldr r3, [r3, #0] 8004564: 60bb str r3, [r7, #8] /* Half Transfer Complete Interrupt management ******************************/ if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) 8004566: 687b ldr r3, [r7, #4] 8004568: 6c1b ldr r3, [r3, #64] @ 0x40 800456a: 221c movs r2, #28 800456c: 4013 ands r3, r2 800456e: 2204 movs r2, #4 8004570: 409a lsls r2, r3 8004572: 0013 movs r3, r2 8004574: 68fa ldr r2, [r7, #12] 8004576: 4013 ands r3, r2 8004578: d027 beq.n 80045ca 800457a: 68bb ldr r3, [r7, #8] 800457c: 2204 movs r2, #4 800457e: 4013 ands r3, r2 8004580: d023 beq.n 80045ca { /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 8004582: 687b ldr r3, [r7, #4] 8004584: 681b ldr r3, [r3, #0] 8004586: 681b ldr r3, [r3, #0] 8004588: 2220 movs r2, #32 800458a: 4013 ands r3, r2 800458c: d107 bne.n 800459e { /* Disable the half transfer interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 800458e: 687b ldr r3, [r7, #4] 8004590: 681b ldr r3, [r3, #0] 8004592: 681a ldr r2, [r3, #0] 8004594: 687b ldr r3, [r7, #4] 8004596: 681b ldr r3, [r3, #0] 8004598: 2104 movs r1, #4 800459a: 438a bics r2, r1 800459c: 601a str r2, [r3, #0] } /* Clear the half transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))); 800459e: 4b44 ldr r3, [pc, #272] @ (80046b0 ) 80045a0: 6859 ldr r1, [r3, #4] 80045a2: 687b ldr r3, [r7, #4] 80045a4: 6c1b ldr r3, [r3, #64] @ 0x40 80045a6: 221c movs r2, #28 80045a8: 4013 ands r3, r2 80045aa: 2204 movs r2, #4 80045ac: 409a lsls r2, r3 80045ae: 4b40 ldr r3, [pc, #256] @ (80046b0 ) 80045b0: 430a orrs r2, r1 80045b2: 605a str r2, [r3, #4] /* DMA peripheral state is not updated in Half Transfer */ /* but in Transfer Complete case */ if (hdma->XferHalfCpltCallback != NULL) 80045b4: 687b ldr r3, [r7, #4] 80045b6: 6b1b ldr r3, [r3, #48] @ 0x30 80045b8: 2b00 cmp r3, #0 80045ba: d100 bne.n 80045be 80045bc: e073 b.n 80046a6 { /* Half transfer callback */ hdma->XferHalfCpltCallback(hdma); 80045be: 687b ldr r3, [r7, #4] 80045c0: 6b1b ldr r3, [r3, #48] @ 0x30 80045c2: 687a ldr r2, [r7, #4] 80045c4: 0010 movs r0, r2 80045c6: 4798 blx r3 if (hdma->XferHalfCpltCallback != NULL) 80045c8: e06d b.n 80046a6 } } /* Transfer Complete Interrupt management ***********************************/ else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC))) 80045ca: 687b ldr r3, [r7, #4] 80045cc: 6c1b ldr r3, [r3, #64] @ 0x40 80045ce: 221c movs r2, #28 80045d0: 4013 ands r3, r2 80045d2: 2202 movs r2, #2 80045d4: 409a lsls r2, r3 80045d6: 0013 movs r3, r2 80045d8: 68fa ldr r2, [r7, #12] 80045da: 4013 ands r3, r2 80045dc: d02e beq.n 800463c 80045de: 68bb ldr r3, [r7, #8] 80045e0: 2202 movs r2, #2 80045e2: 4013 ands r3, r2 80045e4: d02a beq.n 800463c { if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 80045e6: 687b ldr r3, [r7, #4] 80045e8: 681b ldr r3, [r3, #0] 80045ea: 681b ldr r3, [r3, #0] 80045ec: 2220 movs r2, #32 80045ee: 4013 ands r3, r2 80045f0: d10b bne.n 800460a { /* Disable the transfer complete and error interrupt */ __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 80045f2: 687b ldr r3, [r7, #4] 80045f4: 681b ldr r3, [r3, #0] 80045f6: 681a ldr r2, [r3, #0] 80045f8: 687b ldr r3, [r7, #4] 80045fa: 681b ldr r3, [r3, #0] 80045fc: 210a movs r1, #10 80045fe: 438a bics r2, r1 8004600: 601a str r2, [r3, #0] /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8004602: 687b ldr r3, [r7, #4] 8004604: 2225 movs r2, #37 @ 0x25 8004606: 2101 movs r1, #1 8004608: 5499 strb r1, [r3, r2] } /* Clear the transfer complete flag */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))); 800460a: 4b29 ldr r3, [pc, #164] @ (80046b0 ) 800460c: 6859 ldr r1, [r3, #4] 800460e: 687b ldr r3, [r7, #4] 8004610: 6c1b ldr r3, [r3, #64] @ 0x40 8004612: 221c movs r2, #28 8004614: 4013 ands r3, r2 8004616: 2202 movs r2, #2 8004618: 409a lsls r2, r3 800461a: 4b25 ldr r3, [pc, #148] @ (80046b0 ) 800461c: 430a orrs r2, r1 800461e: 605a str r2, [r3, #4] /* Process Unlocked */ __HAL_UNLOCK(hdma); 8004620: 687b ldr r3, [r7, #4] 8004622: 2224 movs r2, #36 @ 0x24 8004624: 2100 movs r1, #0 8004626: 5499 strb r1, [r3, r2] if (hdma->XferCpltCallback != NULL) 8004628: 687b ldr r3, [r7, #4] 800462a: 6adb ldr r3, [r3, #44] @ 0x2c 800462c: 2b00 cmp r3, #0 800462e: d03a beq.n 80046a6 { /* Transfer complete callback */ hdma->XferCpltCallback(hdma); 8004630: 687b ldr r3, [r7, #4] 8004632: 6adb ldr r3, [r3, #44] @ 0x2c 8004634: 687a ldr r2, [r7, #4] 8004636: 0010 movs r0, r2 8004638: 4798 blx r3 if (hdma->XferCpltCallback != NULL) 800463a: e034 b.n 80046a6 } } /* Transfer Error Interrupt management **************************************/ else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) 800463c: 687b ldr r3, [r7, #4] 800463e: 6c1b ldr r3, [r3, #64] @ 0x40 8004640: 221c movs r2, #28 8004642: 4013 ands r3, r2 8004644: 2208 movs r2, #8 8004646: 409a lsls r2, r3 8004648: 0013 movs r3, r2 800464a: 68fa ldr r2, [r7, #12] 800464c: 4013 ands r3, r2 800464e: d02b beq.n 80046a8 8004650: 68bb ldr r3, [r7, #8] 8004652: 2208 movs r2, #8 8004654: 4013 ands r3, r2 8004656: d027 beq.n 80046a8 { /* When a DMA transfer error occurs */ /* A hardware clear of its EN bits is performed */ /* Disable ALL DMA IT */ __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 8004658: 687b ldr r3, [r7, #4] 800465a: 681b ldr r3, [r3, #0] 800465c: 681a ldr r2, [r3, #0] 800465e: 687b ldr r3, [r7, #4] 8004660: 681b ldr r3, [r3, #0] 8004662: 210e movs r1, #14 8004664: 438a bics r2, r1 8004666: 601a str r2, [r3, #0] /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU))); 8004668: 4b11 ldr r3, [pc, #68] @ (80046b0 ) 800466a: 6859 ldr r1, [r3, #4] 800466c: 687b ldr r3, [r7, #4] 800466e: 6c1b ldr r3, [r3, #64] @ 0x40 8004670: 221c movs r2, #28 8004672: 4013 ands r3, r2 8004674: 2201 movs r2, #1 8004676: 409a lsls r2, r3 8004678: 4b0d ldr r3, [pc, #52] @ (80046b0 ) 800467a: 430a orrs r2, r1 800467c: 605a str r2, [r3, #4] /* Update error code */ hdma->ErrorCode = HAL_DMA_ERROR_TE; 800467e: 687b ldr r3, [r7, #4] 8004680: 2201 movs r2, #1 8004682: 63da str r2, [r3, #60] @ 0x3c /* Change the DMA state */ hdma->State = HAL_DMA_STATE_READY; 8004684: 687b ldr r3, [r7, #4] 8004686: 2225 movs r2, #37 @ 0x25 8004688: 2101 movs r1, #1 800468a: 5499 strb r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(hdma); 800468c: 687b ldr r3, [r7, #4] 800468e: 2224 movs r2, #36 @ 0x24 8004690: 2100 movs r1, #0 8004692: 5499 strb r1, [r3, r2] if (hdma->XferErrorCallback != NULL) 8004694: 687b ldr r3, [r7, #4] 8004696: 6b5b ldr r3, [r3, #52] @ 0x34 8004698: 2b00 cmp r3, #0 800469a: d005 beq.n 80046a8 { /* Transfer error callback */ hdma->XferErrorCallback(hdma); 800469c: 687b ldr r3, [r7, #4] 800469e: 6b5b ldr r3, [r3, #52] @ 0x34 80046a0: 687a ldr r2, [r7, #4] 80046a2: 0010 movs r0, r2 80046a4: 4798 blx r3 } else { /* Nothing To Do */ } return; 80046a6: 46c0 nop @ (mov r8, r8) 80046a8: 46c0 nop @ (mov r8, r8) } 80046aa: 46bd mov sp, r7 80046ac: b004 add sp, #16 80046ae: bd80 pop {r7, pc} 80046b0: 40020000 .word 0x40020000 080046b4 : * @param DstAddress The destination memory Buffer address * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) { 80046b4: b580 push {r7, lr} 80046b6: b084 sub sp, #16 80046b8: af00 add r7, sp, #0 80046ba: 60f8 str r0, [r7, #12] 80046bc: 60b9 str r1, [r7, #8] 80046be: 607a str r2, [r7, #4] 80046c0: 603b str r3, [r7, #0] /* Clear the DMAMUX synchro overrun flag */ hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 80046c2: 68fb ldr r3, [r7, #12] 80046c4: 6c9b ldr r3, [r3, #72] @ 0x48 80046c6: 68fa ldr r2, [r7, #12] 80046c8: 6cd2 ldr r2, [r2, #76] @ 0x4c 80046ca: 605a str r2, [r3, #4] if (hdma->DMAmuxRequestGen != 0U) 80046cc: 68fb ldr r3, [r7, #12] 80046ce: 6d1b ldr r3, [r3, #80] @ 0x50 80046d0: 2b00 cmp r3, #0 80046d2: d004 beq.n 80046de { /* Clear the DMAMUX request generator overrun flag */ hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 80046d4: 68fb ldr r3, [r7, #12] 80046d6: 6d5b ldr r3, [r3, #84] @ 0x54 80046d8: 68fa ldr r2, [r7, #12] 80046da: 6d92 ldr r2, [r2, #88] @ 0x58 80046dc: 605a str r2, [r3, #4] } /* Clear all flags */ __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU))); 80046de: 4b14 ldr r3, [pc, #80] @ (8004730 ) 80046e0: 6859 ldr r1, [r3, #4] 80046e2: 68fb ldr r3, [r7, #12] 80046e4: 6c1b ldr r3, [r3, #64] @ 0x40 80046e6: 221c movs r2, #28 80046e8: 4013 ands r3, r2 80046ea: 2201 movs r2, #1 80046ec: 409a lsls r2, r3 80046ee: 4b10 ldr r3, [pc, #64] @ (8004730 ) 80046f0: 430a orrs r2, r1 80046f2: 605a str r2, [r3, #4] /* Configure DMA Channel data length */ hdma->Instance->CNDTR = DataLength; 80046f4: 68fb ldr r3, [r7, #12] 80046f6: 681b ldr r3, [r3, #0] 80046f8: 683a ldr r2, [r7, #0] 80046fa: 605a str r2, [r3, #4] /* Peripheral to Memory */ if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 80046fc: 68fb ldr r3, [r7, #12] 80046fe: 689b ldr r3, [r3, #8] 8004700: 2b10 cmp r3, #16 8004702: d108 bne.n 8004716 { /* Configure DMA Channel destination address */ hdma->Instance->CPAR = DstAddress; 8004704: 68fb ldr r3, [r7, #12] 8004706: 681b ldr r3, [r3, #0] 8004708: 687a ldr r2, [r7, #4] 800470a: 609a str r2, [r3, #8] /* Configure DMA Channel source address */ hdma->Instance->CMAR = SrcAddress; 800470c: 68fb ldr r3, [r7, #12] 800470e: 681b ldr r3, [r3, #0] 8004710: 68ba ldr r2, [r7, #8] 8004712: 60da str r2, [r3, #12] hdma->Instance->CPAR = SrcAddress; /* Configure DMA Channel destination address */ hdma->Instance->CMAR = DstAddress; } } 8004714: e007 b.n 8004726 hdma->Instance->CPAR = SrcAddress; 8004716: 68fb ldr r3, [r7, #12] 8004718: 681b ldr r3, [r3, #0] 800471a: 68ba ldr r2, [r7, #8] 800471c: 609a str r2, [r3, #8] hdma->Instance->CMAR = DstAddress; 800471e: 68fb ldr r3, [r7, #12] 8004720: 681b ldr r3, [r3, #0] 8004722: 687a ldr r2, [r7, #4] 8004724: 60da str r2, [r3, #12] } 8004726: 46c0 nop @ (mov r8, r8) 8004728: 46bd mov sp, r7 800472a: b004 add sp, #16 800472c: bd80 pop {r7, pc} 800472e: 46c0 nop @ (mov r8, r8) 8004730: 40020000 .word 0x40020000 08004734 : * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) { 8004734: b580 push {r7, lr} 8004736: b084 sub sp, #16 8004738: af00 add r7, sp, #0 800473a: 6078 str r0, [r7, #4] uint32_t channel_number; channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; 800473c: 687b ldr r3, [r7, #4] 800473e: 681b ldr r3, [r3, #0] 8004740: 001a movs r2, r3 8004742: 23ff movs r3, #255 @ 0xff 8004744: 4013 ands r3, r2 8004746: 3b08 subs r3, #8 8004748: 2114 movs r1, #20 800474a: 0018 movs r0, r3 800474c: f7fb fcdc bl 8000108 <__udivsi3> 8004750: 0003 movs r3, r0 8004752: 60fb str r3, [r7, #12] hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \ ((hdma->ChannelIndex >> 2U) * \ 8004754: 687b ldr r3, [r7, #4] 8004756: 6c1b ldr r3, [r3, #64] @ 0x40 8004758: 089b lsrs r3, r3, #2 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \ 800475a: 4a0a ldr r2, [pc, #40] @ (8004784 ) 800475c: 4694 mov ip, r2 800475e: 4463 add r3, ip 8004760: 009b lsls r3, r3, #2 8004762: 001a movs r2, r3 8004764: 687b ldr r3, [r7, #4] 8004766: 645a str r2, [r3, #68] @ 0x44 ((uint32_t)DMAMUX1_Channel1 - \ (uint32_t)DMAMUX1_Channel0))); hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 8004768: 687b ldr r3, [r7, #4] 800476a: 4a07 ldr r2, [pc, #28] @ (8004788 ) 800476c: 649a str r2, [r3, #72] @ 0x48 hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU); 800476e: 68fb ldr r3, [r7, #12] 8004770: 221c movs r2, #28 8004772: 4013 ands r3, r2 8004774: 2201 movs r2, #1 8004776: 409a lsls r2, r3 8004778: 687b ldr r3, [r7, #4] 800477a: 64da str r2, [r3, #76] @ 0x4c } 800477c: 46c0 nop @ (mov r8, r8) 800477e: 46bd mov sp, r7 8004780: b004 add sp, #16 8004782: bd80 pop {r7, pc} 8004784: 10008200 .word 0x10008200 8004788: 40020880 .word 0x40020880 0800478c : * the configuration information for the specified DMA Stream. * @retval None */ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) { 800478c: b580 push {r7, lr} 800478e: b084 sub sp, #16 8004790: af00 add r7, sp, #0 8004792: 6078 str r0, [r7, #4] uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 8004794: 687b ldr r3, [r7, #4] 8004796: 685b ldr r3, [r3, #4] 8004798: 22ff movs r2, #255 @ 0xff 800479a: 4013 ands r3, r2 800479c: 60fb str r3, [r7, #12] /* DMA Channels are connected to DMAMUX1 request generator blocks*/ hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \ 800479e: 68fb ldr r3, [r7, #12] 80047a0: 4a0a ldr r2, [pc, #40] @ (80047cc ) 80047a2: 4694 mov ip, r2 80047a4: 4463 add r3, ip 80047a6: 009b lsls r3, r3, #2 80047a8: 001a movs r2, r3 80047aa: 687b ldr r3, [r7, #4] 80047ac: 651a str r2, [r3, #80] @ 0x50 ((request - 1U) * 4U))); hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 80047ae: 687b ldr r3, [r7, #4] 80047b0: 4a07 ldr r2, [pc, #28] @ (80047d0 ) 80047b2: 655a str r2, [r3, #84] @ 0x54 /* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/ hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); 80047b4: 68fb ldr r3, [r7, #12] 80047b6: 3b01 subs r3, #1 80047b8: 2203 movs r2, #3 80047ba: 4013 ands r3, r2 80047bc: 2201 movs r2, #1 80047be: 409a lsls r2, r3 80047c0: 687b ldr r3, [r7, #4] 80047c2: 659a str r2, [r3, #88] @ 0x58 } 80047c4: 46c0 nop @ (mov r8, r8) 80047c6: 46bd mov sp, r7 80047c8: b004 add sp, #16 80047ca: bd80 pop {r7, pc} 80047cc: 1000823f .word 0x1000823f 80047d0: 40020940 .word 0x40020940 080047d4 : * @param pGPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) { 80047d4: b580 push {r7, lr} 80047d6: b086 sub sp, #24 80047d8: af00 add r7, sp, #0 80047da: 6078 str r0, [r7, #4] 80047dc: 6039 str r1, [r7, #0] uint32_t tmp; uint32_t iocurrent; uint32_t position = 0U; 80047de: 2300 movs r3, #0 80047e0: 613b str r3, [r7, #16] assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); assert_param(IS_GPIO_PIN(pGPIO_Init->Pin)); assert_param(IS_GPIO_MODE(pGPIO_Init->Mode)); /* Configure the port pins */ while (((pGPIO_Init->Pin) >> position) != 0U) 80047e2: e153 b.n 8004a8c { /* Get current io position */ iocurrent = (pGPIO_Init->Pin) & (1UL << position); 80047e4: 683b ldr r3, [r7, #0] 80047e6: 681b ldr r3, [r3, #0] 80047e8: 2101 movs r1, #1 80047ea: 693a ldr r2, [r7, #16] 80047ec: 4091 lsls r1, r2 80047ee: 000a movs r2, r1 80047f0: 4013 ands r3, r2 80047f2: 60fb str r3, [r7, #12] if (iocurrent != 0U) 80047f4: 68fb ldr r3, [r7, #12] 80047f6: 2b00 cmp r3, #0 80047f8: d100 bne.n 80047fc 80047fa: e144 b.n 8004a86 { /*--------------------- GPIO Mode Configuration ------------------------*/ /* In case of Alternate function mode selection */ if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) 80047fc: 683b ldr r3, [r7, #0] 80047fe: 685b ldr r3, [r3, #4] 8004800: 2b02 cmp r3, #2 8004802: d003 beq.n 800480c 8004804: 683b ldr r3, [r7, #0] 8004806: 685b ldr r3, [r3, #4] 8004808: 2b12 cmp r3, #18 800480a: d125 bne.n 8004858 /* Check the Alternate function parameters */ assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); assert_param(IS_GPIO_AF(pGPIO_Init->Alternate)); /* Configure Alternate function mapped with the current IO */ tmp = GPIOx->AFR[position >> 3U]; 800480c: 693b ldr r3, [r7, #16] 800480e: 08da lsrs r2, r3, #3 8004810: 687b ldr r3, [r7, #4] 8004812: 3208 adds r2, #8 8004814: 0092 lsls r2, r2, #2 8004816: 58d3 ldr r3, [r2, r3] 8004818: 617b str r3, [r7, #20] tmp &= ~(0xFUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ; 800481a: 693b ldr r3, [r7, #16] 800481c: 2207 movs r2, #7 800481e: 4013 ands r3, r2 8004820: 009b lsls r3, r3, #2 8004822: 220f movs r2, #15 8004824: 409a lsls r2, r3 8004826: 0013 movs r3, r2 8004828: 43da mvns r2, r3 800482a: 697b ldr r3, [r7, #20] 800482c: 4013 ands r3, r2 800482e: 617b str r3, [r7, #20] tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); 8004830: 683b ldr r3, [r7, #0] 8004832: 691b ldr r3, [r3, #16] 8004834: 220f movs r2, #15 8004836: 401a ands r2, r3 8004838: 693b ldr r3, [r7, #16] 800483a: 2107 movs r1, #7 800483c: 400b ands r3, r1 800483e: 009b lsls r3, r3, #2 8004840: 409a lsls r2, r3 8004842: 0013 movs r3, r2 8004844: 697a ldr r2, [r7, #20] 8004846: 4313 orrs r3, r2 8004848: 617b str r3, [r7, #20] GPIOx->AFR[position >> 3U] = tmp; 800484a: 693b ldr r3, [r7, #16] 800484c: 08da lsrs r2, r3, #3 800484e: 687b ldr r3, [r7, #4] 8004850: 3208 adds r2, #8 8004852: 0092 lsls r2, r2, #2 8004854: 6979 ldr r1, [r7, #20] 8004856: 50d1 str r1, [r2, r3] } /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ tmp = GPIOx->MODER; 8004858: 687b ldr r3, [r7, #4] 800485a: 681b ldr r3, [r3, #0] 800485c: 617b str r3, [r7, #20] tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos)); 800485e: 693b ldr r3, [r7, #16] 8004860: 005b lsls r3, r3, #1 8004862: 2203 movs r2, #3 8004864: 409a lsls r2, r3 8004866: 0013 movs r3, r2 8004868: 43da mvns r2, r3 800486a: 697b ldr r3, [r7, #20] 800486c: 4013 ands r3, r2 800486e: 617b str r3, [r7, #20] tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos)); 8004870: 683b ldr r3, [r7, #0] 8004872: 685b ldr r3, [r3, #4] 8004874: 2203 movs r2, #3 8004876: 401a ands r2, r3 8004878: 693b ldr r3, [r7, #16] 800487a: 005b lsls r3, r3, #1 800487c: 409a lsls r2, r3 800487e: 0013 movs r3, r2 8004880: 697a ldr r2, [r7, #20] 8004882: 4313 orrs r3, r2 8004884: 617b str r3, [r7, #20] GPIOx->MODER = tmp; 8004886: 687b ldr r3, [r7, #4] 8004888: 697a ldr r2, [r7, #20] 800488a: 601a str r2, [r3, #0] /* In case of Output or Alternate function mode selection */ if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) || 800488c: 683b ldr r3, [r7, #0] 800488e: 685b ldr r3, [r3, #4] 8004890: 2b01 cmp r3, #1 8004892: d00b beq.n 80048ac 8004894: 683b ldr r3, [r7, #0] 8004896: 685b ldr r3, [r3, #4] 8004898: 2b02 cmp r3, #2 800489a: d007 beq.n 80048ac (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) 800489c: 683b ldr r3, [r7, #0] 800489e: 685b ldr r3, [r3, #4] if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) || 80048a0: 2b11 cmp r3, #17 80048a2: d003 beq.n 80048ac (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) 80048a4: 683b ldr r3, [r7, #0] 80048a6: 685b ldr r3, [r3, #4] 80048a8: 2b12 cmp r3, #18 80048aa: d130 bne.n 800490e { /* Check the Speed parameter */ assert_param(IS_GPIO_SPEED(pGPIO_Init->Speed)); /* Configure the IO Speed */ tmp = GPIOx->OSPEEDR; 80048ac: 687b ldr r3, [r7, #4] 80048ae: 689b ldr r3, [r3, #8] 80048b0: 617b str r3, [r7, #20] tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos)); 80048b2: 693b ldr r3, [r7, #16] 80048b4: 005b lsls r3, r3, #1 80048b6: 2203 movs r2, #3 80048b8: 409a lsls r2, r3 80048ba: 0013 movs r3, r2 80048bc: 43da mvns r2, r3 80048be: 697b ldr r3, [r7, #20] 80048c0: 4013 ands r3, r2 80048c2: 617b str r3, [r7, #20] tmp |= (pGPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos)); 80048c4: 683b ldr r3, [r7, #0] 80048c6: 68da ldr r2, [r3, #12] 80048c8: 693b ldr r3, [r7, #16] 80048ca: 005b lsls r3, r3, #1 80048cc: 409a lsls r2, r3 80048ce: 0013 movs r3, r2 80048d0: 697a ldr r2, [r7, #20] 80048d2: 4313 orrs r3, r2 80048d4: 617b str r3, [r7, #20] GPIOx->OSPEEDR = tmp; 80048d6: 687b ldr r3, [r7, #4] 80048d8: 697a ldr r2, [r7, #20] 80048da: 609a str r2, [r3, #8] /* Configure the IO Output Type */ tmp = GPIOx->OTYPER; 80048dc: 687b ldr r3, [r7, #4] 80048de: 685b ldr r3, [r3, #4] 80048e0: 617b str r3, [r7, #20] tmp &= ~(GPIO_OTYPER_OT0 << position) ; 80048e2: 2201 movs r2, #1 80048e4: 693b ldr r3, [r7, #16] 80048e6: 409a lsls r2, r3 80048e8: 0013 movs r3, r2 80048ea: 43da mvns r2, r3 80048ec: 697b ldr r3, [r7, #20] 80048ee: 4013 ands r3, r2 80048f0: 617b str r3, [r7, #20] tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position); 80048f2: 683b ldr r3, [r7, #0] 80048f4: 685b ldr r3, [r3, #4] 80048f6: 091b lsrs r3, r3, #4 80048f8: 2201 movs r2, #1 80048fa: 401a ands r2, r3 80048fc: 693b ldr r3, [r7, #16] 80048fe: 409a lsls r2, r3 8004900: 0013 movs r3, r2 8004902: 697a ldr r2, [r7, #20] 8004904: 4313 orrs r3, r2 8004906: 617b str r3, [r7, #20] GPIOx->OTYPER = tmp; 8004908: 687b ldr r3, [r7, #4] 800490a: 697a ldr r2, [r7, #20] 800490c: 605a str r2, [r3, #4] } if (pGPIO_Init->Mode != GPIO_MODE_ANALOG) 800490e: 683b ldr r3, [r7, #0] 8004910: 685b ldr r3, [r3, #4] 8004912: 2b03 cmp r3, #3 8004914: d017 beq.n 8004946 { /* Check the Pull parameters */ assert_param(IS_GPIO_PULL(pGPIO_Init->Pull)); /* Activate the Pull-up or Pull down resistor for the current IO */ tmp = GPIOx->PUPDR; 8004916: 687b ldr r3, [r7, #4] 8004918: 68db ldr r3, [r3, #12] 800491a: 617b str r3, [r7, #20] tmp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos)); 800491c: 693b ldr r3, [r7, #16] 800491e: 005b lsls r3, r3, #1 8004920: 2203 movs r2, #3 8004922: 409a lsls r2, r3 8004924: 0013 movs r3, r2 8004926: 43da mvns r2, r3 8004928: 697b ldr r3, [r7, #20] 800492a: 4013 ands r3, r2 800492c: 617b str r3, [r7, #20] tmp |= ((pGPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos)); 800492e: 683b ldr r3, [r7, #0] 8004930: 689a ldr r2, [r3, #8] 8004932: 693b ldr r3, [r7, #16] 8004934: 005b lsls r3, r3, #1 8004936: 409a lsls r2, r3 8004938: 0013 movs r3, r2 800493a: 697a ldr r2, [r7, #20] 800493c: 4313 orrs r3, r2 800493e: 617b str r3, [r7, #20] GPIOx->PUPDR = tmp; 8004940: 687b ldr r3, [r7, #4] 8004942: 697a ldr r2, [r7, #20] 8004944: 60da str r2, [r3, #12] } /*--------------------- EXTI Mode Configuration ------------------------*/ /* Configure the External Interrupt or event for the current IO */ if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 8004946: 683b ldr r3, [r7, #0] 8004948: 685a ldr r2, [r3, #4] 800494a: 2380 movs r3, #128 @ 0x80 800494c: 055b lsls r3, r3, #21 800494e: 4013 ands r3, r2 8004950: d100 bne.n 8004954 8004952: e098 b.n 8004a86 { tmp = EXTI->EXTICR[position >> 2U]; 8004954: 4a53 ldr r2, [pc, #332] @ (8004aa4 ) 8004956: 693b ldr r3, [r7, #16] 8004958: 089b lsrs r3, r3, #2 800495a: 3318 adds r3, #24 800495c: 009b lsls r3, r3, #2 800495e: 589b ldr r3, [r3, r2] 8004960: 617b str r3, [r7, #20] tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); 8004962: 693b ldr r3, [r7, #16] 8004964: 2203 movs r2, #3 8004966: 4013 ands r3, r2 8004968: 00db lsls r3, r3, #3 800496a: 220f movs r2, #15 800496c: 409a lsls r2, r3 800496e: 0013 movs r3, r2 8004970: 43da mvns r2, r3 8004972: 697b ldr r3, [r7, #20] 8004974: 4013 ands r3, r2 8004976: 617b str r3, [r7, #20] tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos)); 8004978: 687a ldr r2, [r7, #4] 800497a: 23a0 movs r3, #160 @ 0xa0 800497c: 05db lsls r3, r3, #23 800497e: 429a cmp r2, r3 8004980: d019 beq.n 80049b6 8004982: 687b ldr r3, [r7, #4] 8004984: 4a48 ldr r2, [pc, #288] @ (8004aa8 ) 8004986: 4293 cmp r3, r2 8004988: d013 beq.n 80049b2 800498a: 687b ldr r3, [r7, #4] 800498c: 4a47 ldr r2, [pc, #284] @ (8004aac ) 800498e: 4293 cmp r3, r2 8004990: d00d beq.n 80049ae 8004992: 687b ldr r3, [r7, #4] 8004994: 4a46 ldr r2, [pc, #280] @ (8004ab0 ) 8004996: 4293 cmp r3, r2 8004998: d007 beq.n 80049aa 800499a: 687b ldr r3, [r7, #4] 800499c: 4a45 ldr r2, [pc, #276] @ (8004ab4 ) 800499e: 4293 cmp r3, r2 80049a0: d101 bne.n 80049a6 80049a2: 2305 movs r3, #5 80049a4: e008 b.n 80049b8 80049a6: 2306 movs r3, #6 80049a8: e006 b.n 80049b8 80049aa: 2303 movs r3, #3 80049ac: e004 b.n 80049b8 80049ae: 2302 movs r3, #2 80049b0: e002 b.n 80049b8 80049b2: 2301 movs r3, #1 80049b4: e000 b.n 80049b8 80049b6: 2300 movs r3, #0 80049b8: 693a ldr r2, [r7, #16] 80049ba: 2103 movs r1, #3 80049bc: 400a ands r2, r1 80049be: 00d2 lsls r2, r2, #3 80049c0: 4093 lsls r3, r2 80049c2: 697a ldr r2, [r7, #20] 80049c4: 4313 orrs r3, r2 80049c6: 617b str r3, [r7, #20] EXTI->EXTICR[position >> 2U] = tmp; 80049c8: 4936 ldr r1, [pc, #216] @ (8004aa4 ) 80049ca: 693b ldr r3, [r7, #16] 80049cc: 089b lsrs r3, r3, #2 80049ce: 3318 adds r3, #24 80049d0: 009b lsls r3, r3, #2 80049d2: 697a ldr r2, [r7, #20] 80049d4: 505a str r2, [r3, r1] /* Clear EXTI line configuration */ tmp = EXTI->IMR1; 80049d6: 4a33 ldr r2, [pc, #204] @ (8004aa4 ) 80049d8: 2380 movs r3, #128 @ 0x80 80049da: 58d3 ldr r3, [r2, r3] 80049dc: 617b str r3, [r7, #20] tmp &= ~((uint32_t)iocurrent); 80049de: 68fb ldr r3, [r7, #12] 80049e0: 43da mvns r2, r3 80049e2: 697b ldr r3, [r7, #20] 80049e4: 4013 ands r3, r2 80049e6: 617b str r3, [r7, #20] if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) 80049e8: 683b ldr r3, [r7, #0] 80049ea: 685a ldr r2, [r3, #4] 80049ec: 2380 movs r3, #128 @ 0x80 80049ee: 025b lsls r3, r3, #9 80049f0: 4013 ands r3, r2 80049f2: d003 beq.n 80049fc { tmp |= iocurrent; 80049f4: 697a ldr r2, [r7, #20] 80049f6: 68fb ldr r3, [r7, #12] 80049f8: 4313 orrs r3, r2 80049fa: 617b str r3, [r7, #20] } EXTI->IMR1 = tmp; 80049fc: 4929 ldr r1, [pc, #164] @ (8004aa4 ) 80049fe: 2280 movs r2, #128 @ 0x80 8004a00: 697b ldr r3, [r7, #20] 8004a02: 508b str r3, [r1, r2] tmp = EXTI->EMR1; 8004a04: 4a27 ldr r2, [pc, #156] @ (8004aa4 ) 8004a06: 2384 movs r3, #132 @ 0x84 8004a08: 58d3 ldr r3, [r2, r3] 8004a0a: 617b str r3, [r7, #20] tmp &= ~((uint32_t)iocurrent); 8004a0c: 68fb ldr r3, [r7, #12] 8004a0e: 43da mvns r2, r3 8004a10: 697b ldr r3, [r7, #20] 8004a12: 4013 ands r3, r2 8004a14: 617b str r3, [r7, #20] if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) 8004a16: 683b ldr r3, [r7, #0] 8004a18: 685a ldr r2, [r3, #4] 8004a1a: 2380 movs r3, #128 @ 0x80 8004a1c: 029b lsls r3, r3, #10 8004a1e: 4013 ands r3, r2 8004a20: d003 beq.n 8004a2a { tmp |= iocurrent; 8004a22: 697a ldr r2, [r7, #20] 8004a24: 68fb ldr r3, [r7, #12] 8004a26: 4313 orrs r3, r2 8004a28: 617b str r3, [r7, #20] } EXTI->EMR1 = tmp; 8004a2a: 491e ldr r1, [pc, #120] @ (8004aa4 ) 8004a2c: 2284 movs r2, #132 @ 0x84 8004a2e: 697b ldr r3, [r7, #20] 8004a30: 508b str r3, [r1, r2] /* Clear Rising Falling edge configuration */ tmp = EXTI->RTSR1; 8004a32: 4b1c ldr r3, [pc, #112] @ (8004aa4 ) 8004a34: 681b ldr r3, [r3, #0] 8004a36: 617b str r3, [r7, #20] tmp &= ~((uint32_t)iocurrent); 8004a38: 68fb ldr r3, [r7, #12] 8004a3a: 43da mvns r2, r3 8004a3c: 697b ldr r3, [r7, #20] 8004a3e: 4013 ands r3, r2 8004a40: 617b str r3, [r7, #20] if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) 8004a42: 683b ldr r3, [r7, #0] 8004a44: 685a ldr r2, [r3, #4] 8004a46: 2380 movs r3, #128 @ 0x80 8004a48: 035b lsls r3, r3, #13 8004a4a: 4013 ands r3, r2 8004a4c: d003 beq.n 8004a56 { tmp |= iocurrent; 8004a4e: 697a ldr r2, [r7, #20] 8004a50: 68fb ldr r3, [r7, #12] 8004a52: 4313 orrs r3, r2 8004a54: 617b str r3, [r7, #20] } EXTI->RTSR1 = tmp; 8004a56: 4b13 ldr r3, [pc, #76] @ (8004aa4 ) 8004a58: 697a ldr r2, [r7, #20] 8004a5a: 601a str r2, [r3, #0] tmp = EXTI->FTSR1; 8004a5c: 4b11 ldr r3, [pc, #68] @ (8004aa4 ) 8004a5e: 685b ldr r3, [r3, #4] 8004a60: 617b str r3, [r7, #20] tmp &= ~((uint32_t)iocurrent); 8004a62: 68fb ldr r3, [r7, #12] 8004a64: 43da mvns r2, r3 8004a66: 697b ldr r3, [r7, #20] 8004a68: 4013 ands r3, r2 8004a6a: 617b str r3, [r7, #20] if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) 8004a6c: 683b ldr r3, [r7, #0] 8004a6e: 685a ldr r2, [r3, #4] 8004a70: 2380 movs r3, #128 @ 0x80 8004a72: 039b lsls r3, r3, #14 8004a74: 4013 ands r3, r2 8004a76: d003 beq.n 8004a80 { tmp |= iocurrent; 8004a78: 697a ldr r2, [r7, #20] 8004a7a: 68fb ldr r3, [r7, #12] 8004a7c: 4313 orrs r3, r2 8004a7e: 617b str r3, [r7, #20] } EXTI->FTSR1 = tmp; 8004a80: 4b08 ldr r3, [pc, #32] @ (8004aa4 ) 8004a82: 697a ldr r2, [r7, #20] 8004a84: 605a str r2, [r3, #4] } } position++; 8004a86: 693b ldr r3, [r7, #16] 8004a88: 3301 adds r3, #1 8004a8a: 613b str r3, [r7, #16] while (((pGPIO_Init->Pin) >> position) != 0U) 8004a8c: 683b ldr r3, [r7, #0] 8004a8e: 681a ldr r2, [r3, #0] 8004a90: 693b ldr r3, [r7, #16] 8004a92: 40da lsrs r2, r3 8004a94: 1e13 subs r3, r2, #0 8004a96: d000 beq.n 8004a9a 8004a98: e6a4 b.n 80047e4 } } 8004a9a: 46c0 nop @ (mov r8, r8) 8004a9c: 46c0 nop @ (mov r8, r8) 8004a9e: 46bd mov sp, r7 8004aa0: b006 add sp, #24 8004aa2: bd80 pop {r7, pc} 8004aa4: 40021800 .word 0x40021800 8004aa8: 50000400 .word 0x50000400 8004aac: 50000800 .word 0x50000800 8004ab0: 50000c00 .word 0x50000c00 8004ab4: 50001400 .word 0x50001400 08004ab8 : * @param GPIO_Pin specifies the port bit to read. * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). * @retval The input port pin value. */ GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { 8004ab8: b580 push {r7, lr} 8004aba: b084 sub sp, #16 8004abc: af00 add r7, sp, #0 8004abe: 6078 str r0, [r7, #4] 8004ac0: 000a movs r2, r1 8004ac2: 1cbb adds r3, r7, #2 8004ac4: 801a strh r2, [r3, #0] GPIO_PinState bitstatus; /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); if ((GPIOx->IDR & GPIO_Pin) != 0U) 8004ac6: 687b ldr r3, [r7, #4] 8004ac8: 691b ldr r3, [r3, #16] 8004aca: 1cba adds r2, r7, #2 8004acc: 8812 ldrh r2, [r2, #0] 8004ace: 4013 ands r3, r2 8004ad0: d004 beq.n 8004adc { bitstatus = GPIO_PIN_SET; 8004ad2: 230f movs r3, #15 8004ad4: 18fb adds r3, r7, r3 8004ad6: 2201 movs r2, #1 8004ad8: 701a strb r2, [r3, #0] 8004ada: e003 b.n 8004ae4 } else { bitstatus = GPIO_PIN_RESET; 8004adc: 230f movs r3, #15 8004ade: 18fb adds r3, r7, r3 8004ae0: 2200 movs r2, #0 8004ae2: 701a strb r2, [r3, #0] } return bitstatus; 8004ae4: 230f movs r3, #15 8004ae6: 18fb adds r3, r7, r3 8004ae8: 781b ldrb r3, [r3, #0] } 8004aea: 0018 movs r0, r3 8004aec: 46bd mov sp, r7 8004aee: b004 add sp, #16 8004af0: bd80 pop {r7, pc} 08004af2 : * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin * @retval None */ void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) { 8004af2: b580 push {r7, lr} 8004af4: b082 sub sp, #8 8004af6: af00 add r7, sp, #0 8004af8: 6078 str r0, [r7, #4] 8004afa: 0008 movs r0, r1 8004afc: 0011 movs r1, r2 8004afe: 1cbb adds r3, r7, #2 8004b00: 1c02 adds r2, r0, #0 8004b02: 801a strh r2, [r3, #0] 8004b04: 1c7b adds r3, r7, #1 8004b06: 1c0a adds r2, r1, #0 8004b08: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN_ACTION(PinState)); if (PinState != GPIO_PIN_RESET) 8004b0a: 1c7b adds r3, r7, #1 8004b0c: 781b ldrb r3, [r3, #0] 8004b0e: 2b00 cmp r3, #0 8004b10: d004 beq.n 8004b1c { GPIOx->BSRR = (uint32_t)GPIO_Pin; 8004b12: 1cbb adds r3, r7, #2 8004b14: 881a ldrh r2, [r3, #0] 8004b16: 687b ldr r3, [r7, #4] 8004b18: 619a str r2, [r3, #24] } else { GPIOx->BRR = (uint32_t)GPIO_Pin; } } 8004b1a: e003 b.n 8004b24 GPIOx->BRR = (uint32_t)GPIO_Pin; 8004b1c: 1cbb adds r3, r7, #2 8004b1e: 881a ldrh r2, [r3, #0] 8004b20: 687b ldr r3, [r7, #4] 8004b22: 629a str r2, [r3, #40] @ 0x28 } 8004b24: 46c0 nop @ (mov r8, r8) 8004b26: 46bd mov sp, r7 8004b28: b002 add sp, #8 8004b2a: bd80 pop {r7, pc} 08004b2c : * @brief Handle EXTI interrupt request. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) { 8004b2c: b580 push {r7, lr} 8004b2e: b082 sub sp, #8 8004b30: af00 add r7, sp, #0 8004b32: 0002 movs r2, r0 8004b34: 1dbb adds r3, r7, #6 8004b36: 801a strh r2, [r3, #0] /* EXTI line interrupt detected */ if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U) 8004b38: 4b10 ldr r3, [pc, #64] @ (8004b7c ) 8004b3a: 68db ldr r3, [r3, #12] 8004b3c: 1dba adds r2, r7, #6 8004b3e: 8812 ldrh r2, [r2, #0] 8004b40: 4013 ands r3, r2 8004b42: d008 beq.n 8004b56 { __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); 8004b44: 4b0d ldr r3, [pc, #52] @ (8004b7c ) 8004b46: 1dba adds r2, r7, #6 8004b48: 8812 ldrh r2, [r2, #0] 8004b4a: 60da str r2, [r3, #12] HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); 8004b4c: 1dbb adds r3, r7, #6 8004b4e: 881b ldrh r3, [r3, #0] 8004b50: 0018 movs r0, r3 8004b52: f000 f815 bl 8004b80 } if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U) 8004b56: 4b09 ldr r3, [pc, #36] @ (8004b7c ) 8004b58: 691b ldr r3, [r3, #16] 8004b5a: 1dba adds r2, r7, #6 8004b5c: 8812 ldrh r2, [r2, #0] 8004b5e: 4013 ands r3, r2 8004b60: d008 beq.n 8004b74 { __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); 8004b62: 4b06 ldr r3, [pc, #24] @ (8004b7c ) 8004b64: 1dba adds r2, r7, #6 8004b66: 8812 ldrh r2, [r2, #0] 8004b68: 611a str r2, [r3, #16] HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); 8004b6a: 1dbb adds r3, r7, #6 8004b6c: 881b ldrh r3, [r3, #0] 8004b6e: 0018 movs r0, r3 8004b70: f7fc ff6e bl 8001a50 } } 8004b74: 46c0 nop @ (mov r8, r8) 8004b76: 46bd mov sp, r7 8004b78: b002 add sp, #8 8004b7a: bd80 pop {r7, pc} 8004b7c: 40021800 .word 0x40021800 08004b80 : * @brief EXTI line detection callback. * @param GPIO_Pin Specifies the port pin connected to corresponding EXTI line. * @retval None */ __weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) { 8004b80: b580 push {r7, lr} 8004b82: b082 sub sp, #8 8004b84: af00 add r7, sp, #0 8004b86: 0002 movs r2, r0 8004b88: 1dbb adds r3, r7, #6 8004b8a: 801a strh r2, [r3, #0] UNUSED(GPIO_Pin); /* NOTE: This function should not be modified, when the callback is needed, the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file */ } 8004b8c: 46c0 nop @ (mov r8, r8) 8004b8e: 46bd mov sp, r7 8004b90: b002 add sp, #8 8004b92: bd80 pop {r7, pc} 08004b94 : must adjust the number of CPU wait states in their application (SystemClock_Config() API) before calling the HAL_RCC_OscConfig() API to update the HSI48 clock division factor. * @retval HAL status */ HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *RCC_OscInitStruct) { 8004b94: b580 push {r7, lr} 8004b96: b086 sub sp, #24 8004b98: af00 add r7, sp, #0 8004b9a: 6078 str r0, [r7, #4] uint32_t tickstart; uint32_t temp_sysclksrc; /* Check Null pointer */ if (RCC_OscInitStruct == NULL) 8004b9c: 687b ldr r3, [r7, #4] 8004b9e: 2b00 cmp r3, #0 8004ba0: d101 bne.n 8004ba6 { return HAL_ERROR; 8004ba2: 2301 movs r3, #1 8004ba4: e1d0 b.n 8004f48 /* Check the parameters */ assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); /*------------------------------- HSE Configuration ------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) 8004ba6: 687b ldr r3, [r7, #4] 8004ba8: 681b ldr r3, [r3, #0] 8004baa: 2201 movs r2, #1 8004bac: 4013 ands r3, r2 8004bae: d100 bne.n 8004bb2 8004bb0: e069 b.n 8004c86 { /* Check the parameters */ assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8004bb2: 4bc8 ldr r3, [pc, #800] @ (8004ed4 ) 8004bb4: 689b ldr r3, [r3, #8] 8004bb6: 2238 movs r2, #56 @ 0x38 8004bb8: 4013 ands r3, r2 8004bba: 617b str r3, [r7, #20] /* When the HSE is used as system clock in these cases it is not allowed to be disabled */ if (temp_sysclksrc == RCC_CFGR_SWS_HSE) 8004bbc: 697b ldr r3, [r7, #20] 8004bbe: 2b08 cmp r3, #8 8004bc0: d105 bne.n 8004bce { if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) 8004bc2: 687b ldr r3, [r7, #4] 8004bc4: 685b ldr r3, [r3, #4] 8004bc6: 2b00 cmp r3, #0 8004bc8: d15d bne.n 8004c86 { return HAL_ERROR; 8004bca: 2301 movs r3, #1 8004bcc: e1bc b.n 8004f48 } } else { /* Set the new HSE configuration ---------------------------------------*/ __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); 8004bce: 687b ldr r3, [r7, #4] 8004bd0: 685a ldr r2, [r3, #4] 8004bd2: 2380 movs r3, #128 @ 0x80 8004bd4: 025b lsls r3, r3, #9 8004bd6: 429a cmp r2, r3 8004bd8: d107 bne.n 8004bea 8004bda: 4bbe ldr r3, [pc, #760] @ (8004ed4 ) 8004bdc: 681a ldr r2, [r3, #0] 8004bde: 4bbd ldr r3, [pc, #756] @ (8004ed4 ) 8004be0: 2180 movs r1, #128 @ 0x80 8004be2: 0249 lsls r1, r1, #9 8004be4: 430a orrs r2, r1 8004be6: 601a str r2, [r3, #0] 8004be8: e020 b.n 8004c2c 8004bea: 687b ldr r3, [r7, #4] 8004bec: 685a ldr r2, [r3, #4] 8004bee: 23a0 movs r3, #160 @ 0xa0 8004bf0: 02db lsls r3, r3, #11 8004bf2: 429a cmp r2, r3 8004bf4: d10e bne.n 8004c14 8004bf6: 4bb7 ldr r3, [pc, #732] @ (8004ed4 ) 8004bf8: 681a ldr r2, [r3, #0] 8004bfa: 4bb6 ldr r3, [pc, #728] @ (8004ed4 ) 8004bfc: 2180 movs r1, #128 @ 0x80 8004bfe: 02c9 lsls r1, r1, #11 8004c00: 430a orrs r2, r1 8004c02: 601a str r2, [r3, #0] 8004c04: 4bb3 ldr r3, [pc, #716] @ (8004ed4 ) 8004c06: 681a ldr r2, [r3, #0] 8004c08: 4bb2 ldr r3, [pc, #712] @ (8004ed4 ) 8004c0a: 2180 movs r1, #128 @ 0x80 8004c0c: 0249 lsls r1, r1, #9 8004c0e: 430a orrs r2, r1 8004c10: 601a str r2, [r3, #0] 8004c12: e00b b.n 8004c2c 8004c14: 4baf ldr r3, [pc, #700] @ (8004ed4 ) 8004c16: 681a ldr r2, [r3, #0] 8004c18: 4bae ldr r3, [pc, #696] @ (8004ed4 ) 8004c1a: 49af ldr r1, [pc, #700] @ (8004ed8 ) 8004c1c: 400a ands r2, r1 8004c1e: 601a str r2, [r3, #0] 8004c20: 4bac ldr r3, [pc, #688] @ (8004ed4 ) 8004c22: 681a ldr r2, [r3, #0] 8004c24: 4bab ldr r3, [pc, #684] @ (8004ed4 ) 8004c26: 49ad ldr r1, [pc, #692] @ (8004edc ) 8004c28: 400a ands r2, r1 8004c2a: 601a str r2, [r3, #0] /* Check the HSE State */ if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) 8004c2c: 687b ldr r3, [r7, #4] 8004c2e: 685b ldr r3, [r3, #4] 8004c30: 2b00 cmp r3, #0 8004c32: d014 beq.n 8004c5e { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004c34: f7ff fa50 bl 80040d8 8004c38: 0003 movs r3, r0 8004c3a: 613b str r3, [r7, #16] /* Wait till HSE is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8004c3c: e008 b.n 8004c50 { if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) 8004c3e: f7ff fa4b bl 80040d8 8004c42: 0002 movs r2, r0 8004c44: 693b ldr r3, [r7, #16] 8004c46: 1ad3 subs r3, r2, r3 8004c48: 2b64 cmp r3, #100 @ 0x64 8004c4a: d901 bls.n 8004c50 { return HAL_TIMEOUT; 8004c4c: 2303 movs r3, #3 8004c4e: e17b b.n 8004f48 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 8004c50: 4ba0 ldr r3, [pc, #640] @ (8004ed4 ) 8004c52: 681a ldr r2, [r3, #0] 8004c54: 2380 movs r3, #128 @ 0x80 8004c56: 029b lsls r3, r3, #10 8004c58: 4013 ands r3, r2 8004c5a: d0f0 beq.n 8004c3e 8004c5c: e013 b.n 8004c86 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004c5e: f7ff fa3b bl 80040d8 8004c62: 0003 movs r3, r0 8004c64: 613b str r3, [r7, #16] /* Wait till HSE is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8004c66: e008 b.n 8004c7a { if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE) 8004c68: f7ff fa36 bl 80040d8 8004c6c: 0002 movs r2, r0 8004c6e: 693b ldr r3, [r7, #16] 8004c70: 1ad3 subs r3, r2, r3 8004c72: 2b64 cmp r3, #100 @ 0x64 8004c74: d901 bls.n 8004c7a { return HAL_TIMEOUT; 8004c76: 2303 movs r3, #3 8004c78: e166 b.n 8004f48 while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) 8004c7a: 4b96 ldr r3, [pc, #600] @ (8004ed4 ) 8004c7c: 681a ldr r2, [r3, #0] 8004c7e: 2380 movs r3, #128 @ 0x80 8004c80: 029b lsls r3, r3, #10 8004c82: 4013 ands r3, r2 8004c84: d1f0 bne.n 8004c68 } } } } /*----------------------------- HSI Configuration --------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) 8004c86: 687b ldr r3, [r7, #4] 8004c88: 681b ldr r3, [r3, #0] 8004c8a: 2202 movs r2, #2 8004c8c: 4013 ands r3, r2 8004c8e: d100 bne.n 8004c92 8004c90: e086 b.n 8004da0 assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv)); /* Check if HSI48 is used as system clock */ temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); 8004c92: 4b90 ldr r3, [pc, #576] @ (8004ed4 ) 8004c94: 689b ldr r3, [r3, #8] 8004c96: 2238 movs r2, #56 @ 0x38 8004c98: 4013 ands r3, r2 8004c9a: 617b str r3, [r7, #20] if (temp_sysclksrc == RCC_CFGR_SWS_HSI) 8004c9c: 697b ldr r3, [r7, #20] 8004c9e: 2b00 cmp r3, #0 8004ca0: d12f bne.n 8004d02 { /* When HSI is used as system clock it can not be disabled */ if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) 8004ca2: 687b ldr r3, [r7, #4] 8004ca4: 68db ldr r3, [r3, #12] 8004ca6: 2b00 cmp r3, #0 8004ca8: d101 bne.n 8004cae { return HAL_ERROR; 8004caa: 2301 movs r3, #1 8004cac: e14c b.n 8004f48 } /* Otherwise, just the calibration is allowed */ else { /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004cae: 4b89 ldr r3, [pc, #548] @ (8004ed4 ) 8004cb0: 685b ldr r3, [r3, #4] 8004cb2: 4a8b ldr r2, [pc, #556] @ (8004ee0 ) 8004cb4: 4013 ands r3, r2 8004cb6: 0019 movs r1, r3 8004cb8: 687b ldr r3, [r7, #4] 8004cba: 695b ldr r3, [r3, #20] 8004cbc: 021a lsls r2, r3, #8 8004cbe: 4b85 ldr r3, [pc, #532] @ (8004ed4 ) 8004cc0: 430a orrs r2, r1 8004cc2: 605a str r2, [r3, #4] if (temp_sysclksrc == RCC_CFGR_SWS_HSI) 8004cc4: 697b ldr r3, [r7, #20] 8004cc6: 2b00 cmp r3, #0 8004cc8: d112 bne.n 8004cf0 { /* Adjust the HSI48 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); 8004cca: 4b82 ldr r3, [pc, #520] @ (8004ed4 ) 8004ccc: 681b ldr r3, [r3, #0] 8004cce: 4a85 ldr r2, [pc, #532] @ (8004ee4 ) 8004cd0: 4013 ands r3, r2 8004cd2: 0019 movs r1, r3 8004cd4: 687b ldr r3, [r7, #4] 8004cd6: 691a ldr r2, [r3, #16] 8004cd8: 4b7e ldr r3, [pc, #504] @ (8004ed4 ) 8004cda: 430a orrs r2, r1 8004cdc: 601a str r2, [r3, #0] /* Update the SystemCoreClock global variable with HSISYS value */ SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos))); 8004cde: 4b7d ldr r3, [pc, #500] @ (8004ed4 ) 8004ce0: 681b ldr r3, [r3, #0] 8004ce2: 0adb lsrs r3, r3, #11 8004ce4: 2207 movs r2, #7 8004ce6: 4013 ands r3, r2 8004ce8: 4a7f ldr r2, [pc, #508] @ (8004ee8 ) 8004cea: 40da lsrs r2, r3 8004cec: 4b7f ldr r3, [pc, #508] @ (8004eec ) 8004cee: 601a str r2, [r3, #0] } /* Adapt Systick interrupt period */ if (HAL_InitTick(uwTickPrio) != HAL_OK) 8004cf0: 4b7f ldr r3, [pc, #508] @ (8004ef0 ) 8004cf2: 681b ldr r3, [r3, #0] 8004cf4: 0018 movs r0, r3 8004cf6: f7ff f993 bl 8004020 8004cfa: 1e03 subs r3, r0, #0 8004cfc: d050 beq.n 8004da0 { return HAL_ERROR; 8004cfe: 2301 movs r3, #1 8004d00: e122 b.n 8004f48 } } else { /* Check the HSI State */ if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) 8004d02: 687b ldr r3, [r7, #4] 8004d04: 68db ldr r3, [r3, #12] 8004d06: 2b00 cmp r3, #0 8004d08: d030 beq.n 8004d6c { /* Configure the HSI48 division factor */ __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv); 8004d0a: 4b72 ldr r3, [pc, #456] @ (8004ed4 ) 8004d0c: 681b ldr r3, [r3, #0] 8004d0e: 4a75 ldr r2, [pc, #468] @ (8004ee4 ) 8004d10: 4013 ands r3, r2 8004d12: 0019 movs r1, r3 8004d14: 687b ldr r3, [r7, #4] 8004d16: 691a ldr r2, [r3, #16] 8004d18: 4b6e ldr r3, [pc, #440] @ (8004ed4 ) 8004d1a: 430a orrs r2, r1 8004d1c: 601a str r2, [r3, #0] /* Enable the Internal High Speed oscillator (HSI48). */ __HAL_RCC_HSI_ENABLE(); 8004d1e: 4b6d ldr r3, [pc, #436] @ (8004ed4 ) 8004d20: 681a ldr r2, [r3, #0] 8004d22: 4b6c ldr r3, [pc, #432] @ (8004ed4 ) 8004d24: 2180 movs r1, #128 @ 0x80 8004d26: 0049 lsls r1, r1, #1 8004d28: 430a orrs r2, r1 8004d2a: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004d2c: f7ff f9d4 bl 80040d8 8004d30: 0003 movs r3, r0 8004d32: 613b str r3, [r7, #16] /* Wait till HSI is ready */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8004d34: e008 b.n 8004d48 { if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) 8004d36: f7ff f9cf bl 80040d8 8004d3a: 0002 movs r2, r0 8004d3c: 693b ldr r3, [r7, #16] 8004d3e: 1ad3 subs r3, r2, r3 8004d40: 2b02 cmp r3, #2 8004d42: d901 bls.n 8004d48 { return HAL_TIMEOUT; 8004d44: 2303 movs r3, #3 8004d46: e0ff b.n 8004f48 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8004d48: 4b62 ldr r3, [pc, #392] @ (8004ed4 ) 8004d4a: 681a ldr r2, [r3, #0] 8004d4c: 2380 movs r3, #128 @ 0x80 8004d4e: 00db lsls r3, r3, #3 8004d50: 4013 ands r3, r2 8004d52: d0f0 beq.n 8004d36 } } /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/ __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); 8004d54: 4b5f ldr r3, [pc, #380] @ (8004ed4 ) 8004d56: 685b ldr r3, [r3, #4] 8004d58: 4a61 ldr r2, [pc, #388] @ (8004ee0 ) 8004d5a: 4013 ands r3, r2 8004d5c: 0019 movs r1, r3 8004d5e: 687b ldr r3, [r7, #4] 8004d60: 695b ldr r3, [r3, #20] 8004d62: 021a lsls r2, r3, #8 8004d64: 4b5b ldr r3, [pc, #364] @ (8004ed4 ) 8004d66: 430a orrs r2, r1 8004d68: 605a str r2, [r3, #4] 8004d6a: e019 b.n 8004da0 } else { /* Disable the Internal High Speed oscillator (HSI48). */ __HAL_RCC_HSI_DISABLE(); 8004d6c: 4b59 ldr r3, [pc, #356] @ (8004ed4 ) 8004d6e: 681a ldr r2, [r3, #0] 8004d70: 4b58 ldr r3, [pc, #352] @ (8004ed4 ) 8004d72: 4960 ldr r1, [pc, #384] @ (8004ef4 ) 8004d74: 400a ands r2, r1 8004d76: 601a str r2, [r3, #0] /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004d78: f7ff f9ae bl 80040d8 8004d7c: 0003 movs r3, r0 8004d7e: 613b str r3, [r7, #16] /* Wait till HSI is disabled */ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8004d80: e008 b.n 8004d94 { if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE) 8004d82: f7ff f9a9 bl 80040d8 8004d86: 0002 movs r2, r0 8004d88: 693b ldr r3, [r7, #16] 8004d8a: 1ad3 subs r3, r2, r3 8004d8c: 2b02 cmp r3, #2 8004d8e: d901 bls.n 8004d94 { return HAL_TIMEOUT; 8004d90: 2303 movs r3, #3 8004d92: e0d9 b.n 8004f48 while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) 8004d94: 4b4f ldr r3, [pc, #316] @ (8004ed4 ) 8004d96: 681a ldr r2, [r3, #0] 8004d98: 2380 movs r3, #128 @ 0x80 8004d9a: 00db lsls r3, r3, #3 8004d9c: 4013 ands r3, r2 8004d9e: d1f0 bne.n 8004d82 } } } } /*------------------------------ LSI Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) 8004da0: 687b ldr r3, [r7, #4] 8004da2: 681b ldr r3, [r3, #0] 8004da4: 2208 movs r2, #8 8004da6: 4013 ands r3, r2 8004da8: d042 beq.n 8004e30 { /* Check the parameters */ assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); /* Check if LSI is used as system clock */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI) 8004daa: 4b4a ldr r3, [pc, #296] @ (8004ed4 ) 8004dac: 689b ldr r3, [r3, #8] 8004dae: 2238 movs r2, #56 @ 0x38 8004db0: 4013 ands r3, r2 8004db2: 2b18 cmp r3, #24 8004db4: d105 bne.n 8004dc2 { /* When LSI is used as system clock it will not be disabled */ if (RCC_OscInitStruct->LSIState == RCC_LSI_OFF) 8004db6: 687b ldr r3, [r7, #4] 8004db8: 699b ldr r3, [r3, #24] 8004dba: 2b00 cmp r3, #0 8004dbc: d138 bne.n 8004e30 { return HAL_ERROR; 8004dbe: 2301 movs r3, #1 8004dc0: e0c2 b.n 8004f48 } } else { /* Check the LSI State */ if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) 8004dc2: 687b ldr r3, [r7, #4] 8004dc4: 699b ldr r3, [r3, #24] 8004dc6: 2b00 cmp r3, #0 8004dc8: d019 beq.n 8004dfe { /* Enable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_ENABLE(); 8004dca: 4b42 ldr r3, [pc, #264] @ (8004ed4 ) 8004dcc: 6e1a ldr r2, [r3, #96] @ 0x60 8004dce: 4b41 ldr r3, [pc, #260] @ (8004ed4 ) 8004dd0: 2101 movs r1, #1 8004dd2: 430a orrs r2, r1 8004dd4: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004dd6: f7ff f97f bl 80040d8 8004dda: 0003 movs r3, r0 8004ddc: 613b str r3, [r7, #16] /* Wait till LSI is ready */ while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) 8004dde: e008 b.n 8004df2 { if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) 8004de0: f7ff f97a bl 80040d8 8004de4: 0002 movs r2, r0 8004de6: 693b ldr r3, [r7, #16] 8004de8: 1ad3 subs r3, r2, r3 8004dea: 2b02 cmp r3, #2 8004dec: d901 bls.n 8004df2 { return HAL_TIMEOUT; 8004dee: 2303 movs r3, #3 8004df0: e0aa b.n 8004f48 while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) 8004df2: 4b38 ldr r3, [pc, #224] @ (8004ed4 ) 8004df4: 6e1b ldr r3, [r3, #96] @ 0x60 8004df6: 2202 movs r2, #2 8004df8: 4013 ands r3, r2 8004dfa: d0f1 beq.n 8004de0 8004dfc: e018 b.n 8004e30 } } else { /* Disable the Internal Low Speed oscillator (LSI). */ __HAL_RCC_LSI_DISABLE(); 8004dfe: 4b35 ldr r3, [pc, #212] @ (8004ed4 ) 8004e00: 6e1a ldr r2, [r3, #96] @ 0x60 8004e02: 4b34 ldr r3, [pc, #208] @ (8004ed4 ) 8004e04: 2101 movs r1, #1 8004e06: 438a bics r2, r1 8004e08: 661a str r2, [r3, #96] @ 0x60 /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004e0a: f7ff f965 bl 80040d8 8004e0e: 0003 movs r3, r0 8004e10: 613b str r3, [r7, #16] /* Wait till LSI is disabled */ while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U) 8004e12: e008 b.n 8004e26 { if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE) 8004e14: f7ff f960 bl 80040d8 8004e18: 0002 movs r2, r0 8004e1a: 693b ldr r3, [r7, #16] 8004e1c: 1ad3 subs r3, r2, r3 8004e1e: 2b02 cmp r3, #2 8004e20: d901 bls.n 8004e26 { return HAL_TIMEOUT; 8004e22: 2303 movs r3, #3 8004e24: e090 b.n 8004f48 while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U) 8004e26: 4b2b ldr r3, [pc, #172] @ (8004ed4 ) 8004e28: 6e1b ldr r3, [r3, #96] @ 0x60 8004e2a: 2202 movs r2, #2 8004e2c: 4013 ands r3, r2 8004e2e: d1f1 bne.n 8004e14 } } } } /*------------------------------ LSE Configuration -------------------------*/ if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) 8004e30: 687b ldr r3, [r7, #4] 8004e32: 681b ldr r3, [r3, #0] 8004e34: 2204 movs r2, #4 8004e36: 4013 ands r3, r2 8004e38: d100 bne.n 8004e3c 8004e3a: e084 b.n 8004f46 { FlagStatus pwrclkchanged = RESET; 8004e3c: 230f movs r3, #15 8004e3e: 18fb adds r3, r7, r3 8004e40: 2200 movs r2, #0 8004e42: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); /* When the LSE is used as system clock, it is not allowed disable it */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE) 8004e44: 4b23 ldr r3, [pc, #140] @ (8004ed4 ) 8004e46: 689b ldr r3, [r3, #8] 8004e48: 2238 movs r2, #56 @ 0x38 8004e4a: 4013 ands r3, r2 8004e4c: 2b20 cmp r3, #32 8004e4e: d106 bne.n 8004e5e { if (RCC_OscInitStruct->LSEState == RCC_LSE_OFF) 8004e50: 687b ldr r3, [r7, #4] 8004e52: 689b ldr r3, [r3, #8] 8004e54: 2b00 cmp r3, #0 8004e56: d000 beq.n 8004e5a 8004e58: e075 b.n 8004f46 { return HAL_ERROR; 8004e5a: 2301 movs r3, #1 8004e5c: e074 b.n 8004f48 } else { /* Update LSE configuration in RTC Domain control register */ /* Set the new LSE configuration -----------------------------------------*/ __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState); 8004e5e: 687b ldr r3, [r7, #4] 8004e60: 689b ldr r3, [r3, #8] 8004e62: 2b01 cmp r3, #1 8004e64: d106 bne.n 8004e74 8004e66: 4b1b ldr r3, [pc, #108] @ (8004ed4 ) 8004e68: 6dda ldr r2, [r3, #92] @ 0x5c 8004e6a: 4b1a ldr r3, [pc, #104] @ (8004ed4 ) 8004e6c: 2101 movs r1, #1 8004e6e: 430a orrs r2, r1 8004e70: 65da str r2, [r3, #92] @ 0x5c 8004e72: e01c b.n 8004eae 8004e74: 687b ldr r3, [r7, #4] 8004e76: 689b ldr r3, [r3, #8] 8004e78: 2b05 cmp r3, #5 8004e7a: d10c bne.n 8004e96 8004e7c: 4b15 ldr r3, [pc, #84] @ (8004ed4 ) 8004e7e: 6dda ldr r2, [r3, #92] @ 0x5c 8004e80: 4b14 ldr r3, [pc, #80] @ (8004ed4 ) 8004e82: 2104 movs r1, #4 8004e84: 430a orrs r2, r1 8004e86: 65da str r2, [r3, #92] @ 0x5c 8004e88: 4b12 ldr r3, [pc, #72] @ (8004ed4 ) 8004e8a: 6dda ldr r2, [r3, #92] @ 0x5c 8004e8c: 4b11 ldr r3, [pc, #68] @ (8004ed4 ) 8004e8e: 2101 movs r1, #1 8004e90: 430a orrs r2, r1 8004e92: 65da str r2, [r3, #92] @ 0x5c 8004e94: e00b b.n 8004eae 8004e96: 4b0f ldr r3, [pc, #60] @ (8004ed4 ) 8004e98: 6dda ldr r2, [r3, #92] @ 0x5c 8004e9a: 4b0e ldr r3, [pc, #56] @ (8004ed4 ) 8004e9c: 2101 movs r1, #1 8004e9e: 438a bics r2, r1 8004ea0: 65da str r2, [r3, #92] @ 0x5c 8004ea2: 4b0c ldr r3, [pc, #48] @ (8004ed4 ) 8004ea4: 6dda ldr r2, [r3, #92] @ 0x5c 8004ea6: 4b0b ldr r3, [pc, #44] @ (8004ed4 ) 8004ea8: 2104 movs r1, #4 8004eaa: 438a bics r2, r1 8004eac: 65da str r2, [r3, #92] @ 0x5c /* Check the LSE State */ if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) 8004eae: 687b ldr r3, [r7, #4] 8004eb0: 689b ldr r3, [r3, #8] 8004eb2: 2b00 cmp r3, #0 8004eb4: d028 beq.n 8004f08 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004eb6: f7ff f90f bl 80040d8 8004eba: 0003 movs r3, r0 8004ebc: 613b str r3, [r7, #16] /* Wait till LSE is ready */ while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) 8004ebe: e01d b.n 8004efc { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004ec0: f7ff f90a bl 80040d8 8004ec4: 0002 movs r2, r0 8004ec6: 693b ldr r3, [r7, #16] 8004ec8: 1ad3 subs r3, r2, r3 8004eca: 4a0b ldr r2, [pc, #44] @ (8004ef8 ) 8004ecc: 4293 cmp r3, r2 8004ece: d915 bls.n 8004efc { return HAL_TIMEOUT; 8004ed0: 2303 movs r3, #3 8004ed2: e039 b.n 8004f48 8004ed4: 40021000 .word 0x40021000 8004ed8: fffeffff .word 0xfffeffff 8004edc: fffbffff .word 0xfffbffff 8004ee0: ffff80ff .word 0xffff80ff 8004ee4: ffffc7ff .word 0xffffc7ff 8004ee8: 02dc6c00 .word 0x02dc6c00 8004eec: 20000024 .word 0x20000024 8004ef0: 20000028 .word 0x20000028 8004ef4: fffffeff .word 0xfffffeff 8004ef8: 00001388 .word 0x00001388 while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) 8004efc: 4b14 ldr r3, [pc, #80] @ (8004f50 ) 8004efe: 6ddb ldr r3, [r3, #92] @ 0x5c 8004f00: 2202 movs r2, #2 8004f02: 4013 ands r3, r2 8004f04: d0dc beq.n 8004ec0 8004f06: e013 b.n 8004f30 } } else { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8004f08: f7ff f8e6 bl 80040d8 8004f0c: 0003 movs r3, r0 8004f0e: 613b str r3, [r7, #16] /* Wait till LSE is disabled */ while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U) 8004f10: e009 b.n 8004f26 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 8004f12: f7ff f8e1 bl 80040d8 8004f16: 0002 movs r2, r0 8004f18: 693b ldr r3, [r7, #16] 8004f1a: 1ad3 subs r3, r2, r3 8004f1c: 4a0d ldr r2, [pc, #52] @ (8004f54 ) 8004f1e: 4293 cmp r3, r2 8004f20: d901 bls.n 8004f26 { return HAL_TIMEOUT; 8004f22: 2303 movs r3, #3 8004f24: e010 b.n 8004f48 while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U) 8004f26: 4b0a ldr r3, [pc, #40] @ (8004f50 ) 8004f28: 6ddb ldr r3, [r3, #92] @ 0x5c 8004f2a: 2202 movs r2, #2 8004f2c: 4013 ands r3, r2 8004f2e: d1f0 bne.n 8004f12 } } } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 8004f30: 230f movs r3, #15 8004f32: 18fb adds r3, r7, r3 8004f34: 781b ldrb r3, [r3, #0] 8004f36: 2b01 cmp r3, #1 8004f38: d105 bne.n 8004f46 { __HAL_RCC_PWR_CLK_DISABLE(); 8004f3a: 4b05 ldr r3, [pc, #20] @ (8004f50 ) 8004f3c: 6bda ldr r2, [r3, #60] @ 0x3c 8004f3e: 4b04 ldr r3, [pc, #16] @ (8004f50 ) 8004f40: 4905 ldr r1, [pc, #20] @ (8004f58 ) 8004f42: 400a ands r2, r1 8004f44: 63da str r2, [r3, #60] @ 0x3c } } } } #endif /* RCC_CR_HSIUSB48ON */ return HAL_OK; 8004f46: 2300 movs r3, #0 } 8004f48: 0018 movs r0, r3 8004f4a: 46bd mov sp, r7 8004f4c: b006 add sp, #24 8004f4e: bd80 pop {r7, pc} 8004f50: 40021000 .word 0x40021000 8004f54: 00001388 .word 0x00001388 8004f58: efffffff .word 0xefffffff 08004f5c : * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { 8004f5c: b580 push {r7, lr} 8004f5e: b084 sub sp, #16 8004f60: af00 add r7, sp, #0 8004f62: 6078 str r0, [r7, #4] 8004f64: 6039 str r1, [r7, #0] uint32_t tickstart; /* Check Null pointer */ if (RCC_ClkInitStruct == NULL) 8004f66: 687b ldr r3, [r7, #4] 8004f68: 2b00 cmp r3, #0 8004f6a: d101 bne.n 8004f70 { return HAL_ERROR; 8004f6c: 2301 movs r3, #1 8004f6e: e0e9 b.n 8005144 /* To correctly read data from FLASH memory, the number of wait states (LATENCY) must be correctly programmed according to the frequency of the FLASH clock (HCLK) and the supply voltage of the device. */ /* Increasing the number of wait states because of higher CPU frequency */ if (FLatency > __HAL_FLASH_GET_LATENCY()) 8004f70: 4b76 ldr r3, [pc, #472] @ (800514c ) 8004f72: 681b ldr r3, [r3, #0] 8004f74: 2207 movs r2, #7 8004f76: 4013 ands r3, r2 8004f78: 683a ldr r2, [r7, #0] 8004f7a: 429a cmp r2, r3 8004f7c: d91e bls.n 8004fbc { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 8004f7e: 4b73 ldr r3, [pc, #460] @ (800514c ) 8004f80: 681b ldr r3, [r3, #0] 8004f82: 2207 movs r2, #7 8004f84: 4393 bics r3, r2 8004f86: 0019 movs r1, r3 8004f88: 4b70 ldr r3, [pc, #448] @ (800514c ) 8004f8a: 683a ldr r2, [r7, #0] 8004f8c: 430a orrs r2, r1 8004f8e: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 8004f90: f7ff f8a2 bl 80040d8 8004f94: 0003 movs r3, r0 8004f96: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8004f98: e009 b.n 8004fae { if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) 8004f9a: f7ff f89d bl 80040d8 8004f9e: 0002 movs r2, r0 8004fa0: 68fb ldr r3, [r7, #12] 8004fa2: 1ad3 subs r3, r2, r3 8004fa4: 4a6a ldr r2, [pc, #424] @ (8005150 ) 8004fa6: 4293 cmp r3, r2 8004fa8: d901 bls.n 8004fae { return HAL_TIMEOUT; 8004faa: 2303 movs r3, #3 8004fac: e0ca b.n 8005144 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 8004fae: 4b67 ldr r3, [pc, #412] @ (800514c ) 8004fb0: 681b ldr r3, [r3, #0] 8004fb2: 2207 movs r2, #7 8004fb4: 4013 ands r3, r2 8004fb6: 683a ldr r2, [r7, #0] 8004fb8: 429a cmp r2, r3 8004fba: d1ee bne.n 8004f9a } } } /*-------------------------- HCLK Configuration --------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) 8004fbc: 687b ldr r3, [r7, #4] 8004fbe: 681b ldr r3, [r3, #0] 8004fc0: 2202 movs r2, #2 8004fc2: 4013 ands r3, r2 8004fc4: d017 beq.n 8004ff6 { /* Set the highest APB divider in order to ensure that we do not go through a non-spec phase whatever we decrease or increase HCLK. */ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 8004fc6: 687b ldr r3, [r7, #4] 8004fc8: 681b ldr r3, [r3, #0] 8004fca: 2204 movs r2, #4 8004fcc: 4013 ands r3, r2 8004fce: d008 beq.n 8004fe2 { MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16); 8004fd0: 4b60 ldr r3, [pc, #384] @ (8005154 ) 8004fd2: 689b ldr r3, [r3, #8] 8004fd4: 4a60 ldr r2, [pc, #384] @ (8005158 ) 8004fd6: 401a ands r2, r3 8004fd8: 4b5e ldr r3, [pc, #376] @ (8005154 ) 8004fda: 21b0 movs r1, #176 @ 0xb0 8004fdc: 0109 lsls r1, r1, #4 8004fde: 430a orrs r2, r1 8004fe0: 609a str r2, [r3, #8] } /* Set the new HCLK clock divider */ assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider); 8004fe2: 4b5c ldr r3, [pc, #368] @ (8005154 ) 8004fe4: 689b ldr r3, [r3, #8] 8004fe6: 4a5d ldr r2, [pc, #372] @ (800515c ) 8004fe8: 4013 ands r3, r2 8004fea: 0019 movs r1, r3 8004fec: 687b ldr r3, [r7, #4] 8004fee: 68da ldr r2, [r3, #12] 8004ff0: 4b58 ldr r3, [pc, #352] @ (8005154 ) 8004ff2: 430a orrs r2, r1 8004ff4: 609a str r2, [r3, #8] } /*------------------------- SYSCLK Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) 8004ff6: 687b ldr r3, [r7, #4] 8004ff8: 681b ldr r3, [r3, #0] 8004ffa: 2201 movs r2, #1 8004ffc: 4013 ands r3, r2 8004ffe: d055 beq.n 80050ac { assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider)); assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); #if defined(RCC_CR_SYSDIV) MODIFY_REG(RCC->CR, RCC_CR_SYSDIV, RCC_ClkInitStruct->SYSCLKDivider); 8005000: 4b54 ldr r3, [pc, #336] @ (8005154 ) 8005002: 681b ldr r3, [r3, #0] 8005004: 221c movs r2, #28 8005006: 4393 bics r3, r2 8005008: 0019 movs r1, r3 800500a: 687b ldr r3, [r7, #4] 800500c: 689a ldr r2, [r3, #8] 800500e: 4b51 ldr r3, [pc, #324] @ (8005154 ) 8005010: 430a orrs r2, r1 8005012: 601a str r2, [r3, #0] #endif /* RCC_CR_SYSDIV */ /* HSE is selected as System Clock Source */ if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) 8005014: 687b ldr r3, [r7, #4] 8005016: 685b ldr r3, [r3, #4] 8005018: 2b01 cmp r3, #1 800501a: d107 bne.n 800502c { /* Check the HSE ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) 800501c: 4b4d ldr r3, [pc, #308] @ (8005154 ) 800501e: 681a ldr r2, [r3, #0] 8005020: 2380 movs r3, #128 @ 0x80 8005022: 029b lsls r3, r3, #10 8005024: 4013 ands r3, r2 8005026: d11f bne.n 8005068 { return HAL_ERROR; 8005028: 2301 movs r3, #1 800502a: e08b b.n 8005144 } } /* HSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI) 800502c: 687b ldr r3, [r7, #4] 800502e: 685b ldr r3, [r3, #4] 8005030: 2b00 cmp r3, #0 8005032: d107 bne.n 8005044 { /* Check the HSI ready flag */ if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) 8005034: 4b47 ldr r3, [pc, #284] @ (8005154 ) 8005036: 681a ldr r2, [r3, #0] 8005038: 2380 movs r3, #128 @ 0x80 800503a: 00db lsls r3, r3, #3 800503c: 4013 ands r3, r2 800503e: d113 bne.n 8005068 { return HAL_ERROR; 8005040: 2301 movs r3, #1 8005042: e07f b.n 8005144 return HAL_ERROR; } } #endif /* RCC_HSI48_SUPPORT */ /* LSI is selected as System Clock Source */ else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI) 8005044: 687b ldr r3, [r7, #4] 8005046: 685b ldr r3, [r3, #4] 8005048: 2b03 cmp r3, #3 800504a: d106 bne.n 800505a { /* Check the LSI ready flag */ if (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U) 800504c: 4b41 ldr r3, [pc, #260] @ (8005154 ) 800504e: 6e1b ldr r3, [r3, #96] @ 0x60 8005050: 2202 movs r2, #2 8005052: 4013 ands r3, r2 8005054: d108 bne.n 8005068 { return HAL_ERROR; 8005056: 2301 movs r3, #1 8005058: e074 b.n 8005144 } /* LSE is selected as System Clock Source */ else { /* Check the LSE ready flag */ if (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) 800505a: 4b3e ldr r3, [pc, #248] @ (8005154 ) 800505c: 6ddb ldr r3, [r3, #92] @ 0x5c 800505e: 2202 movs r2, #2 8005060: 4013 ands r3, r2 8005062: d101 bne.n 8005068 { return HAL_ERROR; 8005064: 2301 movs r3, #1 8005066: e06d b.n 8005144 } } MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource); 8005068: 4b3a ldr r3, [pc, #232] @ (8005154 ) 800506a: 689b ldr r3, [r3, #8] 800506c: 2207 movs r2, #7 800506e: 4393 bics r3, r2 8005070: 0019 movs r1, r3 8005072: 687b ldr r3, [r7, #4] 8005074: 685a ldr r2, [r3, #4] 8005076: 4b37 ldr r3, [pc, #220] @ (8005154 ) 8005078: 430a orrs r2, r1 800507a: 609a str r2, [r3, #8] /* Get Start Tick*/ tickstart = HAL_GetTick(); 800507c: f7ff f82c bl 80040d8 8005080: 0003 movs r3, r0 8005082: 60fb str r3, [r7, #12] while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 8005084: e009 b.n 800509a { if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) 8005086: f7ff f827 bl 80040d8 800508a: 0002 movs r2, r0 800508c: 68fb ldr r3, [r7, #12] 800508e: 1ad3 subs r3, r2, r3 8005090: 4a2f ldr r2, [pc, #188] @ (8005150 ) 8005092: 4293 cmp r3, r2 8005094: d901 bls.n 800509a { return HAL_TIMEOUT; 8005096: 2303 movs r3, #3 8005098: e054 b.n 8005144 while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) 800509a: 4b2e ldr r3, [pc, #184] @ (8005154 ) 800509c: 689b ldr r3, [r3, #8] 800509e: 2238 movs r2, #56 @ 0x38 80050a0: 401a ands r2, r3 80050a2: 687b ldr r3, [r7, #4] 80050a4: 685b ldr r3, [r3, #4] 80050a6: 00db lsls r3, r3, #3 80050a8: 429a cmp r2, r3 80050aa: d1ec bne.n 8005086 } } } /* Decreasing the number of wait states because of lower CPU frequency */ if (FLatency < __HAL_FLASH_GET_LATENCY()) 80050ac: 4b27 ldr r3, [pc, #156] @ (800514c ) 80050ae: 681b ldr r3, [r3, #0] 80050b0: 2207 movs r2, #7 80050b2: 4013 ands r3, r2 80050b4: 683a ldr r2, [r7, #0] 80050b6: 429a cmp r2, r3 80050b8: d21e bcs.n 80050f8 { /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ __HAL_FLASH_SET_LATENCY(FLatency); 80050ba: 4b24 ldr r3, [pc, #144] @ (800514c ) 80050bc: 681b ldr r3, [r3, #0] 80050be: 2207 movs r2, #7 80050c0: 4393 bics r3, r2 80050c2: 0019 movs r1, r3 80050c4: 4b21 ldr r3, [pc, #132] @ (800514c ) 80050c6: 683a ldr r2, [r7, #0] 80050c8: 430a orrs r2, r1 80050ca: 601a str r2, [r3, #0] /* Check that the new number of wait states is taken into account to access the Flash memory by polling the FLASH_ACR register */ tickstart = HAL_GetTick(); 80050cc: f7ff f804 bl 80040d8 80050d0: 0003 movs r3, r0 80050d2: 60fb str r3, [r7, #12] while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 80050d4: e009 b.n 80050ea { if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE) 80050d6: f7fe ffff bl 80040d8 80050da: 0002 movs r2, r0 80050dc: 68fb ldr r3, [r7, #12] 80050de: 1ad3 subs r3, r2, r3 80050e0: 4a1b ldr r2, [pc, #108] @ (8005150 ) 80050e2: 4293 cmp r3, r2 80050e4: d901 bls.n 80050ea { return HAL_TIMEOUT; 80050e6: 2303 movs r3, #3 80050e8: e02c b.n 8005144 while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency) 80050ea: 4b18 ldr r3, [pc, #96] @ (800514c ) 80050ec: 681b ldr r3, [r3, #0] 80050ee: 2207 movs r2, #7 80050f0: 4013 ands r3, r2 80050f2: 683a ldr r2, [r7, #0] 80050f4: 429a cmp r2, r3 80050f6: d1ee bne.n 80050d6 } } } /*-------------------------- PCLK1 Configuration ---------------------------*/ if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) 80050f8: 687b ldr r3, [r7, #4] 80050fa: 681b ldr r3, [r3, #0] 80050fc: 2204 movs r2, #4 80050fe: 4013 ands r3, r2 8005100: d009 beq.n 8005116 { assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider)); MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider); 8005102: 4b14 ldr r3, [pc, #80] @ (8005154 ) 8005104: 689b ldr r3, [r3, #8] 8005106: 4a16 ldr r2, [pc, #88] @ (8005160 ) 8005108: 4013 ands r3, r2 800510a: 0019 movs r1, r3 800510c: 687b ldr r3, [r7, #4] 800510e: 691a ldr r2, [r3, #16] 8005110: 4b10 ldr r3, [pc, #64] @ (8005154 ) 8005112: 430a orrs r2, r1 8005114: 609a str r2, [r3, #8] } /* Update the SystemCoreClock global variable */ SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ 8005116: f000 f82b bl 8005170 800511a: 0001 movs r1, r0 800511c: 4b0d ldr r3, [pc, #52] @ (8005154 ) 800511e: 689b ldr r3, [r3, #8] >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); 8005120: 0a1b lsrs r3, r3, #8 8005122: 220f movs r2, #15 8005124: 401a ands r2, r3 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ 8005126: 4b0f ldr r3, [pc, #60] @ (8005164 ) 8005128: 0092 lsls r2, r2, #2 800512a: 58d3 ldr r3, [r2, r3] >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); 800512c: 221f movs r2, #31 800512e: 4013 ands r3, r2 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ 8005130: 000a movs r2, r1 8005132: 40da lsrs r2, r3 8005134: 4b0c ldr r3, [pc, #48] @ (8005168 ) 8005136: 601a str r2, [r3, #0] /* Configure the source of time base considering new system clocks settings*/ return HAL_InitTick(uwTickPrio); 8005138: 4b0c ldr r3, [pc, #48] @ (800516c ) 800513a: 681b ldr r3, [r3, #0] 800513c: 0018 movs r0, r3 800513e: f7fe ff6f bl 8004020 8005142: 0003 movs r3, r0 } 8005144: 0018 movs r0, r3 8005146: 46bd mov sp, r7 8005148: b004 add sp, #16 800514a: bd80 pop {r7, pc} 800514c: 40022000 .word 0x40022000 8005150: 00001388 .word 0x00001388 8005154: 40021000 .word 0x40021000 8005158: ffff84ff .word 0xffff84ff 800515c: fffff0ff .word 0xfffff0ff 8005160: ffff8fff .word 0xffff8fff 8005164: 08007db0 .word 0x08007db0 8005168: 20000024 .word 0x20000024 800516c: 20000028 .word 0x20000028 08005170 : * * * @retval SYSCLK frequency */ uint32_t HAL_RCC_GetSysClockFreq(void) { 8005170: b580 push {r7, lr} 8005172: b084 sub sp, #16 8005174: af00 add r7, sp, #0 uint32_t hsidiv; uint32_t sysclockfreq; #if defined(RCC_CR_SYSDIV) uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U); 8005176: 4b23 ldr r3, [pc, #140] @ (8005204 ) 8005178: 681b ldr r3, [r3, #0] 800517a: 089b lsrs r3, r3, #2 800517c: 2207 movs r2, #7 800517e: 4013 ands r3, r2 8005180: 3301 adds r3, #1 8005182: 60bb str r3, [r7, #8] #endif /* RCC_CR_SYSDIV */ if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 8005184: 4b1f ldr r3, [pc, #124] @ (8005204 ) 8005186: 689b ldr r3, [r3, #8] 8005188: 2238 movs r2, #56 @ 0x38 800518a: 4013 ands r3, r2 800518c: d10f bne.n 80051ae { /* HSISYS can be derived for HSI48 */ hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)); 800518e: 4b1d ldr r3, [pc, #116] @ (8005204 ) 8005190: 681b ldr r3, [r3, #0] 8005192: 0adb lsrs r3, r3, #11 8005194: 2207 movs r2, #7 8005196: 4013 ands r3, r2 8005198: 2201 movs r2, #1 800519a: 409a lsls r2, r3 800519c: 0013 movs r3, r2 800519e: 607b str r3, [r7, #4] /* HSI used as system clock source */ sysclockfreq = (HSI_VALUE / hsidiv); 80051a0: 6879 ldr r1, [r7, #4] 80051a2: 4819 ldr r0, [pc, #100] @ (8005208 ) 80051a4: f7fa ffb0 bl 8000108 <__udivsi3> 80051a8: 0003 movs r3, r0 80051aa: 60fb str r3, [r7, #12] 80051ac: e01e b.n 80051ec } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 80051ae: 4b15 ldr r3, [pc, #84] @ (8005204 ) 80051b0: 689b ldr r3, [r3, #8] 80051b2: 2238 movs r2, #56 @ 0x38 80051b4: 4013 ands r3, r2 80051b6: 2b08 cmp r3, #8 80051b8: d102 bne.n 80051c0 { /* HSE used as system clock source */ sysclockfreq = HSE_VALUE; 80051ba: 4b14 ldr r3, [pc, #80] @ (800520c ) 80051bc: 60fb str r3, [r7, #12] 80051be: e015 b.n 80051ec } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE) 80051c0: 4b10 ldr r3, [pc, #64] @ (8005204 ) 80051c2: 689b ldr r3, [r3, #8] 80051c4: 2238 movs r2, #56 @ 0x38 80051c6: 4013 ands r3, r2 80051c8: 2b20 cmp r3, #32 80051ca: d103 bne.n 80051d4 { /* LSE used as system clock source */ sysclockfreq = LSE_VALUE; 80051cc: 2380 movs r3, #128 @ 0x80 80051ce: 021b lsls r3, r3, #8 80051d0: 60fb str r3, [r7, #12] 80051d2: e00b b.n 80051ec } else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI) 80051d4: 4b0b ldr r3, [pc, #44] @ (8005204 ) 80051d6: 689b ldr r3, [r3, #8] 80051d8: 2238 movs r2, #56 @ 0x38 80051da: 4013 ands r3, r2 80051dc: 2b18 cmp r3, #24 80051de: d103 bne.n 80051e8 { /* LSI used as system clock source */ sysclockfreq = LSI_VALUE; 80051e0: 23fa movs r3, #250 @ 0xfa 80051e2: 01db lsls r3, r3, #7 80051e4: 60fb str r3, [r7, #12] 80051e6: e001 b.n 80051ec sysclockfreq = HSI48_VALUE; } #endif /* RCC_HSI48_SUPPORT */ else { sysclockfreq = 0U; 80051e8: 2300 movs r3, #0 80051ea: 60fb str r3, [r7, #12] } #if defined(RCC_CR_SYSDIV) sysclockfreq = sysclockfreq / sysclockdiv; 80051ec: 68b9 ldr r1, [r7, #8] 80051ee: 68f8 ldr r0, [r7, #12] 80051f0: f7fa ff8a bl 8000108 <__udivsi3> 80051f4: 0003 movs r3, r0 80051f6: 60fb str r3, [r7, #12] #endif /* RCC_CR_SYSDIV */ return sysclockfreq; 80051f8: 68fb ldr r3, [r7, #12] } 80051fa: 0018 movs r0, r3 80051fc: 46bd mov sp, r7 80051fe: b004 add sp, #16 8005200: bd80 pop {r7, pc} 8005202: 46c0 nop @ (mov r8, r8) 8005204: 40021000 .word 0x40021000 8005208: 02dc6c00 .word 0x02dc6c00 800520c: 007a1200 .word 0x007a1200 08005210 : * * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. * @retval HCLK frequency in Hz */ uint32_t HAL_RCC_GetHCLKFreq(void) { 8005210: b580 push {r7, lr} 8005212: af00 add r7, sp, #0 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ 8005214: f7ff ffac bl 8005170 8005218: 0001 movs r1, r0 800521a: 4b09 ldr r3, [pc, #36] @ (8005240 ) 800521c: 689b ldr r3, [r3, #8] >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); 800521e: 0a1b lsrs r3, r3, #8 8005220: 220f movs r2, #15 8005222: 401a ands r2, r3 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ 8005224: 4b07 ldr r3, [pc, #28] @ (8005244 ) 8005226: 0092 lsls r2, r2, #2 8005228: 58d3 ldr r3, [r2, r3] >> RCC_CFGR_HPRE_Pos]) & 0x1FU)); 800522a: 221f movs r2, #31 800522c: 4013 ands r3, r2 SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \ 800522e: 000a movs r2, r1 8005230: 40da lsrs r2, r3 8005232: 4b05 ldr r3, [pc, #20] @ (8005248 ) 8005234: 601a str r2, [r3, #0] return SystemCoreClock; 8005236: 4b04 ldr r3, [pc, #16] @ (8005248 ) 8005238: 681b ldr r3, [r3, #0] } 800523a: 0018 movs r0, r3 800523c: 46bd mov sp, r7 800523e: bd80 pop {r7, pc} 8005240: 40021000 .word 0x40021000 8005244: 08007db0 .word 0x08007db0 8005248: 20000024 .word 0x20000024 0800524c : * @note Each time PCLK1 changes, this function must be called to update the * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. * @retval PCLK1 frequency in Hz */ uint32_t HAL_RCC_GetPCLK1Freq(void) { 800524c: b580 push {r7, lr} 800524e: af00 add r7, sp, #0 /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_Pos]) & 0x1FU)); 8005250: f7ff ffde bl 8005210 8005254: 0001 movs r1, r0 8005256: 4b07 ldr r3, [pc, #28] @ (8005274 ) 8005258: 689b ldr r3, [r3, #8] 800525a: 0b1b lsrs r3, r3, #12 800525c: 2207 movs r2, #7 800525e: 401a ands r2, r3 8005260: 4b05 ldr r3, [pc, #20] @ (8005278 ) 8005262: 0092 lsls r2, r2, #2 8005264: 58d3 ldr r3, [r2, r3] 8005266: 221f movs r2, #31 8005268: 4013 ands r3, r2 800526a: 40d9 lsrs r1, r3 800526c: 000b movs r3, r1 } 800526e: 0018 movs r0, r3 8005270: 46bd mov sp, r7 8005272: bd80 pop {r7, pc} 8005274: 40021000 .word 0x40021000 8005278: 08007df0 .word 0x08007df0 0800527c : * @note (*) not available on all devices * * @retval HAL status */ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *PeriphClkInit) { 800527c: b580 push {r7, lr} 800527e: b086 sub sp, #24 8005280: af00 add r7, sp, #0 8005282: 6078 str r0, [r7, #4] uint32_t tmpregister; uint32_t tickstart; HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ 8005284: 2313 movs r3, #19 8005286: 18fb adds r3, r7, r3 8005288: 2200 movs r2, #0 800528a: 701a strb r2, [r3, #0] HAL_StatusTypeDef status = HAL_OK; /* Final status */ 800528c: 2312 movs r3, #18 800528e: 18fb adds r3, r7, r3 8005290: 2200 movs r2, #0 8005292: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); /*-------------------------- RTC clock source configuration ----------------------*/ if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 8005294: 687b ldr r3, [r7, #4] 8005296: 681b ldr r3, [r3, #0] 8005298: 2240 movs r2, #64 @ 0x40 800529a: 4013 ands r3, r2 800529c: d100 bne.n 80052a0 800529e: e079 b.n 8005394 { FlagStatus pwrclkchanged = RESET; 80052a0: 2011 movs r0, #17 80052a2: 183b adds r3, r7, r0 80052a4: 2200 movs r2, #0 80052a6: 701a strb r2, [r3, #0] /* Check for RTC Parameters used to output RTCCLK */ assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); /* Enable Power Clock */ if (__HAL_RCC_PWR_IS_CLK_DISABLED()) 80052a8: 4b63 ldr r3, [pc, #396] @ (8005438 ) 80052aa: 6bda ldr r2, [r3, #60] @ 0x3c 80052ac: 2380 movs r3, #128 @ 0x80 80052ae: 055b lsls r3, r3, #21 80052b0: 4013 ands r3, r2 80052b2: d110 bne.n 80052d6 { __HAL_RCC_PWR_CLK_ENABLE(); 80052b4: 4b60 ldr r3, [pc, #384] @ (8005438 ) 80052b6: 6bda ldr r2, [r3, #60] @ 0x3c 80052b8: 4b5f ldr r3, [pc, #380] @ (8005438 ) 80052ba: 2180 movs r1, #128 @ 0x80 80052bc: 0549 lsls r1, r1, #21 80052be: 430a orrs r2, r1 80052c0: 63da str r2, [r3, #60] @ 0x3c 80052c2: 4b5d ldr r3, [pc, #372] @ (8005438 ) 80052c4: 6bda ldr r2, [r3, #60] @ 0x3c 80052c6: 2380 movs r3, #128 @ 0x80 80052c8: 055b lsls r3, r3, #21 80052ca: 4013 ands r3, r2 80052cc: 60bb str r3, [r7, #8] 80052ce: 68bb ldr r3, [r7, #8] pwrclkchanged = SET; 80052d0: 183b adds r3, r7, r0 80052d2: 2201 movs r2, #1 80052d4: 701a strb r2, [r3, #0] } /* Reset the RTC domain only if the RTC Clock source selection is modified from default */ tmpregister = READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL); 80052d6: 4b58 ldr r3, [pc, #352] @ (8005438 ) 80052d8: 6dda ldr r2, [r3, #92] @ 0x5c 80052da: 23c0 movs r3, #192 @ 0xc0 80052dc: 009b lsls r3, r3, #2 80052de: 4013 ands r3, r2 80052e0: 617b str r3, [r7, #20] /* Reset the RTC domain only if the RTC Clock source selection is modified */ if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection)) 80052e2: 697b ldr r3, [r7, #20] 80052e4: 2b00 cmp r3, #0 80052e6: d019 beq.n 800531c 80052e8: 687b ldr r3, [r7, #4] 80052ea: 699b ldr r3, [r3, #24] 80052ec: 697a ldr r2, [r7, #20] 80052ee: 429a cmp r2, r3 80052f0: d014 beq.n 800531c { /* Store the content of CSR1 register before the reset of RTC Domain */ tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL)); 80052f2: 4b51 ldr r3, [pc, #324] @ (8005438 ) 80052f4: 6ddb ldr r3, [r3, #92] @ 0x5c 80052f6: 4a51 ldr r2, [pc, #324] @ (800543c ) 80052f8: 4013 ands r3, r2 80052fa: 617b str r3, [r7, #20] /* RTC Clock selection can be changed only if the RTC Domain is reset */ __HAL_RCC_BACKUPRESET_FORCE(); 80052fc: 4b4e ldr r3, [pc, #312] @ (8005438 ) 80052fe: 6dda ldr r2, [r3, #92] @ 0x5c 8005300: 4b4d ldr r3, [pc, #308] @ (8005438 ) 8005302: 2180 movs r1, #128 @ 0x80 8005304: 0249 lsls r1, r1, #9 8005306: 430a orrs r2, r1 8005308: 65da str r2, [r3, #92] @ 0x5c __HAL_RCC_BACKUPRESET_RELEASE(); 800530a: 4b4b ldr r3, [pc, #300] @ (8005438 ) 800530c: 6dda ldr r2, [r3, #92] @ 0x5c 800530e: 4b4a ldr r3, [pc, #296] @ (8005438 ) 8005310: 494b ldr r1, [pc, #300] @ (8005440 ) 8005312: 400a ands r2, r1 8005314: 65da str r2, [r3, #92] @ 0x5c /* Restore the Content of CSR1 register */ RCC->CSR1 = tmpregister; 8005316: 4b48 ldr r3, [pc, #288] @ (8005438 ) 8005318: 697a ldr r2, [r7, #20] 800531a: 65da str r2, [r3, #92] @ 0x5c } /* Wait for LSE reactivation if LSE was enable prior to RTC Domain reset */ if (HAL_IS_BIT_SET(tmpregister, RCC_CSR1_LSEON)) 800531c: 697b ldr r3, [r7, #20] 800531e: 2201 movs r2, #1 8005320: 4013 ands r3, r2 8005322: d016 beq.n 8005352 { /* Get Start Tick*/ tickstart = HAL_GetTick(); 8005324: f7fe fed8 bl 80040d8 8005328: 0003 movs r3, r0 800532a: 60fb str r3, [r7, #12] /* Wait till LSE is ready */ while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) 800532c: e00c b.n 8005348 { if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) 800532e: f7fe fed3 bl 80040d8 8005332: 0002 movs r2, r0 8005334: 68fb ldr r3, [r7, #12] 8005336: 1ad3 subs r3, r2, r3 8005338: 4a42 ldr r2, [pc, #264] @ (8005444 ) 800533a: 4293 cmp r3, r2 800533c: d904 bls.n 8005348 { ret = HAL_TIMEOUT; 800533e: 2313 movs r3, #19 8005340: 18fb adds r3, r7, r3 8005342: 2203 movs r2, #3 8005344: 701a strb r2, [r3, #0] break; 8005346: e004 b.n 8005352 while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U) 8005348: 4b3b ldr r3, [pc, #236] @ (8005438 ) 800534a: 6ddb ldr r3, [r3, #92] @ 0x5c 800534c: 2202 movs r2, #2 800534e: 4013 ands r3, r2 8005350: d0ed beq.n 800532e } } } if (ret == HAL_OK) 8005352: 2313 movs r3, #19 8005354: 18fb adds r3, r7, r3 8005356: 781b ldrb r3, [r3, #0] 8005358: 2b00 cmp r3, #0 800535a: d10a bne.n 8005372 { /* Apply new RTC clock source selection */ __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); 800535c: 4b36 ldr r3, [pc, #216] @ (8005438 ) 800535e: 6ddb ldr r3, [r3, #92] @ 0x5c 8005360: 4a36 ldr r2, [pc, #216] @ (800543c ) 8005362: 4013 ands r3, r2 8005364: 0019 movs r1, r3 8005366: 687b ldr r3, [r7, #4] 8005368: 699a ldr r2, [r3, #24] 800536a: 4b33 ldr r3, [pc, #204] @ (8005438 ) 800536c: 430a orrs r2, r1 800536e: 65da str r2, [r3, #92] @ 0x5c 8005370: e005 b.n 800537e } else { /* set overall return value */ status = ret; 8005372: 2312 movs r3, #18 8005374: 18fb adds r3, r7, r3 8005376: 2213 movs r2, #19 8005378: 18ba adds r2, r7, r2 800537a: 7812 ldrb r2, [r2, #0] 800537c: 701a strb r2, [r3, #0] } /* Restore clock configuration if changed */ if (pwrclkchanged == SET) 800537e: 2311 movs r3, #17 8005380: 18fb adds r3, r7, r3 8005382: 781b ldrb r3, [r3, #0] 8005384: 2b01 cmp r3, #1 8005386: d105 bne.n 8005394 { __HAL_RCC_PWR_CLK_DISABLE(); 8005388: 4b2b ldr r3, [pc, #172] @ (8005438 ) 800538a: 6bda ldr r2, [r3, #60] @ 0x3c 800538c: 4b2a ldr r3, [pc, #168] @ (8005438 ) 800538e: 492e ldr r1, [pc, #184] @ (8005448 ) 8005390: 400a ands r2, r1 8005392: 63da str r2, [r3, #60] @ 0x3c } } /*-------------------------- USART1 clock source configuration -------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) 8005394: 687b ldr r3, [r7, #4] 8005396: 681b ldr r3, [r3, #0] 8005398: 2201 movs r2, #1 800539a: 4013 ands r3, r2 800539c: d009 beq.n 80053b2 { /* Check the parameters */ assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); /* Configure the USART1 clock source */ __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); 800539e: 4b26 ldr r3, [pc, #152] @ (8005438 ) 80053a0: 6d5b ldr r3, [r3, #84] @ 0x54 80053a2: 2203 movs r2, #3 80053a4: 4393 bics r3, r2 80053a6: 0019 movs r1, r3 80053a8: 687b ldr r3, [r7, #4] 80053aa: 689a ldr r2, [r3, #8] 80053ac: 4b22 ldr r3, [pc, #136] @ (8005438 ) 80053ae: 430a orrs r2, r1 80053b0: 655a str r2, [r3, #84] @ 0x54 } /*-------------------------- I2C1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) 80053b2: 687b ldr r3, [r7, #4] 80053b4: 681b ldr r3, [r3, #0] 80053b6: 2202 movs r2, #2 80053b8: 4013 ands r3, r2 80053ba: d009 beq.n 80053d0 { /* Check the parameters */ assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); /* Configure the I2C1 clock source */ __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); 80053bc: 4b1e ldr r3, [pc, #120] @ (8005438 ) 80053be: 6d5b ldr r3, [r3, #84] @ 0x54 80053c0: 4a22 ldr r2, [pc, #136] @ (800544c ) 80053c2: 4013 ands r3, r2 80053c4: 0019 movs r1, r3 80053c6: 687b ldr r3, [r7, #4] 80053c8: 68da ldr r2, [r3, #12] 80053ca: 4b1b ldr r3, [pc, #108] @ (8005438 ) 80053cc: 430a orrs r2, r1 80053ce: 655a str r2, [r3, #84] @ 0x54 } /*-------------------------- ADC clock source configuration ----------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) 80053d0: 687b ldr r3, [r7, #4] 80053d2: 681b ldr r3, [r3, #0] 80053d4: 2220 movs r2, #32 80053d6: 4013 ands r3, r2 80053d8: d008 beq.n 80053ec { /* Check the parameters */ assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); /* Configure the ADC interface clock source */ __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); 80053da: 4b17 ldr r3, [pc, #92] @ (8005438 ) 80053dc: 6d5b ldr r3, [r3, #84] @ 0x54 80053de: 009b lsls r3, r3, #2 80053e0: 0899 lsrs r1, r3, #2 80053e2: 687b ldr r3, [r7, #4] 80053e4: 695a ldr r2, [r3, #20] 80053e6: 4b14 ldr r3, [pc, #80] @ (8005438 ) 80053e8: 430a orrs r2, r1 80053ea: 655a str r2, [r3, #84] @ 0x54 __HAL_RCC_FDCAN1_CONFIG(PeriphClkInit->Fdcan1ClockSelection); } #endif /* FDCAN1 */ /*-------------------------- I2S1 clock source configuration ---------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1) 80053ec: 687b ldr r3, [r7, #4] 80053ee: 681b ldr r3, [r3, #0] 80053f0: 2204 movs r2, #4 80053f2: 4013 ands r3, r2 80053f4: d009 beq.n 800540a { /* Check the parameters */ assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection)); /* Configure the I2S1 clock source */ __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection); 80053f6: 4b10 ldr r3, [pc, #64] @ (8005438 ) 80053f8: 6d5b ldr r3, [r3, #84] @ 0x54 80053fa: 4a15 ldr r2, [pc, #84] @ (8005450 ) 80053fc: 4013 ands r3, r2 80053fe: 0019 movs r1, r3 8005400: 687b ldr r3, [r7, #4] 8005402: 691a ldr r2, [r3, #16] 8005404: 4b0c ldr r3, [pc, #48] @ (8005438 ) 8005406: 430a orrs r2, r1 8005408: 655a str r2, [r3, #84] @ 0x54 } /*------------------------------------ HSI Kernel clock source configuration --------------------------------------*/ if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER) 800540a: 687b ldr r3, [r7, #4] 800540c: 681b ldr r3, [r3, #0] 800540e: 2280 movs r2, #128 @ 0x80 8005410: 4013 ands r3, r2 8005412: d009 beq.n 8005428 { /* Check the parameters */ assert_param(IS_RCC_HSIKERDIV(PeriphClkInit->HSIKerClockDivider)); /* Configure the HSI Kernel clock source Divider */ __HAL_RCC_HSIKER_CONFIG(PeriphClkInit->HSIKerClockDivider); 8005414: 4b08 ldr r3, [pc, #32] @ (8005438 ) 8005416: 681b ldr r3, [r3, #0] 8005418: 22e0 movs r2, #224 @ 0xe0 800541a: 4393 bics r3, r2 800541c: 0019 movs r1, r3 800541e: 687b ldr r3, [r7, #4] 8005420: 685a ldr r2, [r3, #4] 8005422: 4b05 ldr r3, [pc, #20] @ (8005438 ) 8005424: 430a orrs r2, r1 8005426: 601a str r2, [r3, #0] } return status; 8005428: 2312 movs r3, #18 800542a: 18fb adds r3, r7, r3 800542c: 781b ldrb r3, [r3, #0] } 800542e: 0018 movs r0, r3 8005430: 46bd mov sp, r7 8005432: b006 add sp, #24 8005434: bd80 pop {r7, pc} 8005436: 46c0 nop @ (mov r8, r8) 8005438: 40021000 .word 0x40021000 800543c: fffffcff .word 0xfffffcff 8005440: fffeffff .word 0xfffeffff 8005444: 00001388 .word 0x00001388 8005448: efffffff .word 0xefffffff 800544c: ffffcfff .word 0xffffcfff 8005450: ffff3fff .word 0xffff3fff 08005454 : * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) { 8005454: b580 push {r7, lr} 8005456: b082 sub sp, #8 8005458: af00 add r7, sp, #0 800545a: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 800545c: 687b ldr r3, [r7, #4] 800545e: 2b00 cmp r3, #0 8005460: d101 bne.n 8005466 { return HAL_ERROR; 8005462: 2301 movs r3, #1 8005464: e04a b.n 80054fc assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 8005466: 687b ldr r3, [r7, #4] 8005468: 223d movs r2, #61 @ 0x3d 800546a: 5c9b ldrb r3, [r3, r2] 800546c: b2db uxtb r3, r3 800546e: 2b00 cmp r3, #0 8005470: d107 bne.n 8005482 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005472: 687b ldr r3, [r7, #4] 8005474: 223c movs r2, #60 @ 0x3c 8005476: 2100 movs r1, #0 8005478: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Base_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC */ HAL_TIM_Base_MspInit(htim); 800547a: 687b ldr r3, [r7, #4] 800547c: 0018 movs r0, r3 800547e: f7fe fb0f bl 8003aa0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005482: 687b ldr r3, [r7, #4] 8005484: 223d movs r2, #61 @ 0x3d 8005486: 2102 movs r1, #2 8005488: 5499 strb r1, [r3, r2] /* Set the Time Base configuration */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800548a: 687b ldr r3, [r7, #4] 800548c: 681a ldr r2, [r3, #0] 800548e: 687b ldr r3, [r7, #4] 8005490: 3304 adds r3, #4 8005492: 0019 movs r1, r3 8005494: 0010 movs r0, r2 8005496: f000 fe37 bl 8006108 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800549a: 687b ldr r3, [r7, #4] 800549c: 2248 movs r2, #72 @ 0x48 800549e: 2101 movs r1, #1 80054a0: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80054a2: 687b ldr r3, [r7, #4] 80054a4: 223e movs r2, #62 @ 0x3e 80054a6: 2101 movs r1, #1 80054a8: 5499 strb r1, [r3, r2] 80054aa: 687b ldr r3, [r7, #4] 80054ac: 223f movs r2, #63 @ 0x3f 80054ae: 2101 movs r1, #1 80054b0: 5499 strb r1, [r3, r2] 80054b2: 687b ldr r3, [r7, #4] 80054b4: 2240 movs r2, #64 @ 0x40 80054b6: 2101 movs r1, #1 80054b8: 5499 strb r1, [r3, r2] 80054ba: 687b ldr r3, [r7, #4] 80054bc: 2241 movs r2, #65 @ 0x41 80054be: 2101 movs r1, #1 80054c0: 5499 strb r1, [r3, r2] 80054c2: 687b ldr r3, [r7, #4] 80054c4: 2242 movs r2, #66 @ 0x42 80054c6: 2101 movs r1, #1 80054c8: 5499 strb r1, [r3, r2] 80054ca: 687b ldr r3, [r7, #4] 80054cc: 2243 movs r2, #67 @ 0x43 80054ce: 2101 movs r1, #1 80054d0: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 80054d2: 687b ldr r3, [r7, #4] 80054d4: 2244 movs r2, #68 @ 0x44 80054d6: 2101 movs r1, #1 80054d8: 5499 strb r1, [r3, r2] 80054da: 687b ldr r3, [r7, #4] 80054dc: 2245 movs r2, #69 @ 0x45 80054de: 2101 movs r1, #1 80054e0: 5499 strb r1, [r3, r2] 80054e2: 687b ldr r3, [r7, #4] 80054e4: 2246 movs r2, #70 @ 0x46 80054e6: 2101 movs r1, #1 80054e8: 5499 strb r1, [r3, r2] 80054ea: 687b ldr r3, [r7, #4] 80054ec: 2247 movs r2, #71 @ 0x47 80054ee: 2101 movs r1, #1 80054f0: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80054f2: 687b ldr r3, [r7, #4] 80054f4: 223d movs r2, #61 @ 0x3d 80054f6: 2101 movs r1, #1 80054f8: 5499 strb r1, [r3, r2] return HAL_OK; 80054fa: 2300 movs r3, #0 } 80054fc: 0018 movs r0, r3 80054fe: 46bd mov sp, r7 8005500: b002 add sp, #8 8005502: bd80 pop {r7, pc} 08005504 : * @brief Stops the TIM Base generation. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) { 8005504: b580 push {r7, lr} 8005506: b082 sub sp, #8 8005508: af00 add r7, sp, #0 800550a: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Disable the Peripheral */ __HAL_TIM_DISABLE(htim); 800550c: 687b ldr r3, [r7, #4] 800550e: 681b ldr r3, [r3, #0] 8005510: 6a1b ldr r3, [r3, #32] 8005512: 4a0d ldr r2, [pc, #52] @ (8005548 ) 8005514: 4013 ands r3, r2 8005516: d10d bne.n 8005534 8005518: 687b ldr r3, [r7, #4] 800551a: 681b ldr r3, [r3, #0] 800551c: 6a1b ldr r3, [r3, #32] 800551e: 4a0b ldr r2, [pc, #44] @ (800554c ) 8005520: 4013 ands r3, r2 8005522: d107 bne.n 8005534 8005524: 687b ldr r3, [r7, #4] 8005526: 681b ldr r3, [r3, #0] 8005528: 681a ldr r2, [r3, #0] 800552a: 687b ldr r3, [r7, #4] 800552c: 681b ldr r3, [r3, #0] 800552e: 2101 movs r1, #1 8005530: 438a bics r2, r1 8005532: 601a str r2, [r3, #0] /* Set the TIM state */ htim->State = HAL_TIM_STATE_READY; 8005534: 687b ldr r3, [r7, #4] 8005536: 223d movs r2, #61 @ 0x3d 8005538: 2101 movs r1, #1 800553a: 5499 strb r1, [r3, r2] /* Return function status */ return HAL_OK; 800553c: 2300 movs r3, #0 } 800553e: 0018 movs r0, r3 8005540: 46bd mov sp, r7 8005542: b002 add sp, #8 8005544: bd80 pop {r7, pc} 8005546: 46c0 nop @ (mov r8, r8) 8005548: 00001111 .word 0x00001111 800554c: 00000444 .word 0x00000444 08005550 : * @brief Starts the TIM Base generation in interrupt mode. * @param htim TIM Base handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) { 8005550: b580 push {r7, lr} 8005552: b084 sub sp, #16 8005554: af00 add r7, sp, #0 8005556: 6078 str r0, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_INSTANCE(htim->Instance)); /* Check the TIM state */ if (htim->State != HAL_TIM_STATE_READY) 8005558: 687b ldr r3, [r7, #4] 800555a: 223d movs r2, #61 @ 0x3d 800555c: 5c9b ldrb r3, [r3, r2] 800555e: b2db uxtb r3, r3 8005560: 2b01 cmp r3, #1 8005562: d001 beq.n 8005568 { return HAL_ERROR; 8005564: 2301 movs r3, #1 8005566: e03d b.n 80055e4 } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005568: 687b ldr r3, [r7, #4] 800556a: 223d movs r2, #61 @ 0x3d 800556c: 2102 movs r1, #2 800556e: 5499 strb r1, [r3, r2] /* Enable the TIM Update interrupt */ __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); 8005570: 687b ldr r3, [r7, #4] 8005572: 681b ldr r3, [r3, #0] 8005574: 68da ldr r2, [r3, #12] 8005576: 687b ldr r3, [r7, #4] 8005578: 681b ldr r3, [r3, #0] 800557a: 2101 movs r1, #1 800557c: 430a orrs r2, r1 800557e: 60da str r2, [r3, #12] /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8005580: 687b ldr r3, [r7, #4] 8005582: 681b ldr r3, [r3, #0] 8005584: 4a19 ldr r2, [pc, #100] @ (80055ec ) 8005586: 4293 cmp r3, r2 8005588: d00a beq.n 80055a0 800558a: 687b ldr r3, [r7, #4] 800558c: 681a ldr r2, [r3, #0] 800558e: 2380 movs r3, #128 @ 0x80 8005590: 05db lsls r3, r3, #23 8005592: 429a cmp r2, r3 8005594: d004 beq.n 80055a0 8005596: 687b ldr r3, [r7, #4] 8005598: 681b ldr r3, [r3, #0] 800559a: 4a15 ldr r2, [pc, #84] @ (80055f0 ) 800559c: 4293 cmp r3, r2 800559e: d116 bne.n 80055ce { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 80055a0: 687b ldr r3, [r7, #4] 80055a2: 681b ldr r3, [r3, #0] 80055a4: 689b ldr r3, [r3, #8] 80055a6: 4a13 ldr r2, [pc, #76] @ (80055f4 ) 80055a8: 4013 ands r3, r2 80055aa: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80055ac: 68fb ldr r3, [r7, #12] 80055ae: 2b06 cmp r3, #6 80055b0: d016 beq.n 80055e0 80055b2: 68fa ldr r2, [r7, #12] 80055b4: 2380 movs r3, #128 @ 0x80 80055b6: 025b lsls r3, r3, #9 80055b8: 429a cmp r2, r3 80055ba: d011 beq.n 80055e0 { __HAL_TIM_ENABLE(htim); 80055bc: 687b ldr r3, [r7, #4] 80055be: 681b ldr r3, [r3, #0] 80055c0: 681a ldr r2, [r3, #0] 80055c2: 687b ldr r3, [r7, #4] 80055c4: 681b ldr r3, [r3, #0] 80055c6: 2101 movs r1, #1 80055c8: 430a orrs r2, r1 80055ca: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80055cc: e008 b.n 80055e0 } } else { __HAL_TIM_ENABLE(htim); 80055ce: 687b ldr r3, [r7, #4] 80055d0: 681b ldr r3, [r3, #0] 80055d2: 681a ldr r2, [r3, #0] 80055d4: 687b ldr r3, [r7, #4] 80055d6: 681b ldr r3, [r3, #0] 80055d8: 2101 movs r1, #1 80055da: 430a orrs r2, r1 80055dc: 601a str r2, [r3, #0] 80055de: e000 b.n 80055e2 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 80055e0: 46c0 nop @ (mov r8, r8) } /* Return function status */ return HAL_OK; 80055e2: 2300 movs r3, #0 } 80055e4: 0018 movs r0, r3 80055e6: 46bd mov sp, r7 80055e8: b004 add sp, #16 80055ea: bd80 pop {r7, pc} 80055ec: 40012c00 .word 0x40012c00 80055f0: 40000400 .word 0x40000400 80055f4: 00010007 .word 0x00010007 080055f8 : * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() * @param htim TIM PWM handle * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) { 80055f8: b580 push {r7, lr} 80055fa: b082 sub sp, #8 80055fc: af00 add r7, sp, #0 80055fe: 6078 str r0, [r7, #4] /* Check the TIM handle allocation */ if (htim == NULL) 8005600: 687b ldr r3, [r7, #4] 8005602: 2b00 cmp r3, #0 8005604: d101 bne.n 800560a { return HAL_ERROR; 8005606: 2301 movs r3, #1 8005608: e04a b.n 80056a0 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); if (htim->State == HAL_TIM_STATE_RESET) 800560a: 687b ldr r3, [r7, #4] 800560c: 223d movs r2, #61 @ 0x3d 800560e: 5c9b ldrb r3, [r3, r2] 8005610: b2db uxtb r3, r3 8005612: 2b00 cmp r3, #0 8005614: d107 bne.n 8005626 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005616: 687b ldr r3, [r7, #4] 8005618: 223c movs r2, #60 @ 0x3c 800561a: 2100 movs r1, #0 800561c: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->PWM_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_PWM_MspInit(htim); 800561e: 687b ldr r3, [r7, #4] 8005620: 0018 movs r0, r3 8005622: f000 f841 bl 80056a8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 8005626: 687b ldr r3, [r7, #4] 8005628: 223d movs r2, #61 @ 0x3d 800562a: 2102 movs r1, #2 800562c: 5499 strb r1, [r3, r2] /* Init the base time for the PWM */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 800562e: 687b ldr r3, [r7, #4] 8005630: 681a ldr r2, [r3, #0] 8005632: 687b ldr r3, [r7, #4] 8005634: 3304 adds r3, #4 8005636: 0019 movs r1, r3 8005638: 0010 movs r0, r2 800563a: f000 fd65 bl 8006108 /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 800563e: 687b ldr r3, [r7, #4] 8005640: 2248 movs r2, #72 @ 0x48 8005642: 2101 movs r1, #1 8005644: 5499 strb r1, [r3, r2] /* Initialize the TIM channels state */ TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005646: 687b ldr r3, [r7, #4] 8005648: 223e movs r2, #62 @ 0x3e 800564a: 2101 movs r1, #1 800564c: 5499 strb r1, [r3, r2] 800564e: 687b ldr r3, [r7, #4] 8005650: 223f movs r2, #63 @ 0x3f 8005652: 2101 movs r1, #1 8005654: 5499 strb r1, [r3, r2] 8005656: 687b ldr r3, [r7, #4] 8005658: 2240 movs r2, #64 @ 0x40 800565a: 2101 movs r1, #1 800565c: 5499 strb r1, [r3, r2] 800565e: 687b ldr r3, [r7, #4] 8005660: 2241 movs r2, #65 @ 0x41 8005662: 2101 movs r1, #1 8005664: 5499 strb r1, [r3, r2] 8005666: 687b ldr r3, [r7, #4] 8005668: 2242 movs r2, #66 @ 0x42 800566a: 2101 movs r1, #1 800566c: 5499 strb r1, [r3, r2] 800566e: 687b ldr r3, [r7, #4] 8005670: 2243 movs r2, #67 @ 0x43 8005672: 2101 movs r1, #1 8005674: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); 8005676: 687b ldr r3, [r7, #4] 8005678: 2244 movs r2, #68 @ 0x44 800567a: 2101 movs r1, #1 800567c: 5499 strb r1, [r3, r2] 800567e: 687b ldr r3, [r7, #4] 8005680: 2245 movs r2, #69 @ 0x45 8005682: 2101 movs r1, #1 8005684: 5499 strb r1, [r3, r2] 8005686: 687b ldr r3, [r7, #4] 8005688: 2246 movs r2, #70 @ 0x46 800568a: 2101 movs r1, #1 800568c: 5499 strb r1, [r3, r2] 800568e: 687b ldr r3, [r7, #4] 8005690: 2247 movs r2, #71 @ 0x47 8005692: 2101 movs r1, #1 8005694: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 8005696: 687b ldr r3, [r7, #4] 8005698: 223d movs r2, #61 @ 0x3d 800569a: 2101 movs r1, #1 800569c: 5499 strb r1, [r3, r2] return HAL_OK; 800569e: 2300 movs r3, #0 } 80056a0: 0018 movs r0, r3 80056a2: 46bd mov sp, r7 80056a4: b002 add sp, #8 80056a6: bd80 pop {r7, pc} 080056a8 : * @brief Initializes the TIM PWM MSP. * @param htim TIM PWM handle * @retval None */ __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) { 80056a8: b580 push {r7, lr} 80056aa: b082 sub sp, #8 80056ac: af00 add r7, sp, #0 80056ae: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_MspInit could be implemented in the user file */ } 80056b0: 46c0 nop @ (mov r8, r8) 80056b2: 46bd mov sp, r7 80056b4: b002 add sp, #8 80056b6: bd80 pop {r7, pc} 080056b8 : * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 80056b8: b580 push {r7, lr} 80056ba: b084 sub sp, #16 80056bc: af00 add r7, sp, #0 80056be: 6078 str r0, [r7, #4] 80056c0: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); /* Check the TIM channel state */ if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) 80056c2: 683b ldr r3, [r7, #0] 80056c4: 2b00 cmp r3, #0 80056c6: d108 bne.n 80056da 80056c8: 687b ldr r3, [r7, #4] 80056ca: 223e movs r2, #62 @ 0x3e 80056cc: 5c9b ldrb r3, [r3, r2] 80056ce: b2db uxtb r3, r3 80056d0: 3b01 subs r3, #1 80056d2: 1e5a subs r2, r3, #1 80056d4: 4193 sbcs r3, r2 80056d6: b2db uxtb r3, r3 80056d8: e037 b.n 800574a 80056da: 683b ldr r3, [r7, #0] 80056dc: 2b04 cmp r3, #4 80056de: d108 bne.n 80056f2 80056e0: 687b ldr r3, [r7, #4] 80056e2: 223f movs r2, #63 @ 0x3f 80056e4: 5c9b ldrb r3, [r3, r2] 80056e6: b2db uxtb r3, r3 80056e8: 3b01 subs r3, #1 80056ea: 1e5a subs r2, r3, #1 80056ec: 4193 sbcs r3, r2 80056ee: b2db uxtb r3, r3 80056f0: e02b b.n 800574a 80056f2: 683b ldr r3, [r7, #0] 80056f4: 2b08 cmp r3, #8 80056f6: d108 bne.n 800570a 80056f8: 687b ldr r3, [r7, #4] 80056fa: 2240 movs r2, #64 @ 0x40 80056fc: 5c9b ldrb r3, [r3, r2] 80056fe: b2db uxtb r3, r3 8005700: 3b01 subs r3, #1 8005702: 1e5a subs r2, r3, #1 8005704: 4193 sbcs r3, r2 8005706: b2db uxtb r3, r3 8005708: e01f b.n 800574a 800570a: 683b ldr r3, [r7, #0] 800570c: 2b0c cmp r3, #12 800570e: d108 bne.n 8005722 8005710: 687b ldr r3, [r7, #4] 8005712: 2241 movs r2, #65 @ 0x41 8005714: 5c9b ldrb r3, [r3, r2] 8005716: b2db uxtb r3, r3 8005718: 3b01 subs r3, #1 800571a: 1e5a subs r2, r3, #1 800571c: 4193 sbcs r3, r2 800571e: b2db uxtb r3, r3 8005720: e013 b.n 800574a 8005722: 683b ldr r3, [r7, #0] 8005724: 2b10 cmp r3, #16 8005726: d108 bne.n 800573a 8005728: 687b ldr r3, [r7, #4] 800572a: 2242 movs r2, #66 @ 0x42 800572c: 5c9b ldrb r3, [r3, r2] 800572e: b2db uxtb r3, r3 8005730: 3b01 subs r3, #1 8005732: 1e5a subs r2, r3, #1 8005734: 4193 sbcs r3, r2 8005736: b2db uxtb r3, r3 8005738: e007 b.n 800574a 800573a: 687b ldr r3, [r7, #4] 800573c: 2243 movs r2, #67 @ 0x43 800573e: 5c9b ldrb r3, [r3, r2] 8005740: b2db uxtb r3, r3 8005742: 3b01 subs r3, #1 8005744: 1e5a subs r2, r3, #1 8005746: 4193 sbcs r3, r2 8005748: b2db uxtb r3, r3 800574a: 2b00 cmp r3, #0 800574c: d001 beq.n 8005752 { return HAL_ERROR; 800574e: 2301 movs r3, #1 8005750: e081 b.n 8005856 } /* Set the TIM channel state */ TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); 8005752: 683b ldr r3, [r7, #0] 8005754: 2b00 cmp r3, #0 8005756: d104 bne.n 8005762 8005758: 687b ldr r3, [r7, #4] 800575a: 223e movs r2, #62 @ 0x3e 800575c: 2102 movs r1, #2 800575e: 5499 strb r1, [r3, r2] 8005760: e023 b.n 80057aa 8005762: 683b ldr r3, [r7, #0] 8005764: 2b04 cmp r3, #4 8005766: d104 bne.n 8005772 8005768: 687b ldr r3, [r7, #4] 800576a: 223f movs r2, #63 @ 0x3f 800576c: 2102 movs r1, #2 800576e: 5499 strb r1, [r3, r2] 8005770: e01b b.n 80057aa 8005772: 683b ldr r3, [r7, #0] 8005774: 2b08 cmp r3, #8 8005776: d104 bne.n 8005782 8005778: 687b ldr r3, [r7, #4] 800577a: 2240 movs r2, #64 @ 0x40 800577c: 2102 movs r1, #2 800577e: 5499 strb r1, [r3, r2] 8005780: e013 b.n 80057aa 8005782: 683b ldr r3, [r7, #0] 8005784: 2b0c cmp r3, #12 8005786: d104 bne.n 8005792 8005788: 687b ldr r3, [r7, #4] 800578a: 2241 movs r2, #65 @ 0x41 800578c: 2102 movs r1, #2 800578e: 5499 strb r1, [r3, r2] 8005790: e00b b.n 80057aa 8005792: 683b ldr r3, [r7, #0] 8005794: 2b10 cmp r3, #16 8005796: d104 bne.n 80057a2 8005798: 687b ldr r3, [r7, #4] 800579a: 2242 movs r2, #66 @ 0x42 800579c: 2102 movs r1, #2 800579e: 5499 strb r1, [r3, r2] 80057a0: e003 b.n 80057aa 80057a2: 687b ldr r3, [r7, #4] 80057a4: 2243 movs r2, #67 @ 0x43 80057a6: 2102 movs r1, #2 80057a8: 5499 strb r1, [r3, r2] /* Enable the Capture compare channel */ TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); 80057aa: 687b ldr r3, [r7, #4] 80057ac: 681b ldr r3, [r3, #0] 80057ae: 6839 ldr r1, [r7, #0] 80057b0: 2201 movs r2, #1 80057b2: 0018 movs r0, r3 80057b4: f001 f85c bl 8006870 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) 80057b8: 687b ldr r3, [r7, #4] 80057ba: 681b ldr r3, [r3, #0] 80057bc: 4a28 ldr r2, [pc, #160] @ (8005860 ) 80057be: 4293 cmp r3, r2 80057c0: d009 beq.n 80057d6 80057c2: 687b ldr r3, [r7, #4] 80057c4: 681b ldr r3, [r3, #0] 80057c6: 4a27 ldr r2, [pc, #156] @ (8005864 ) 80057c8: 4293 cmp r3, r2 80057ca: d004 beq.n 80057d6 80057cc: 687b ldr r3, [r7, #4] 80057ce: 681b ldr r3, [r3, #0] 80057d0: 4a25 ldr r2, [pc, #148] @ (8005868 ) 80057d2: 4293 cmp r3, r2 80057d4: d101 bne.n 80057da 80057d6: 2301 movs r3, #1 80057d8: e000 b.n 80057dc 80057da: 2300 movs r3, #0 80057dc: 2b00 cmp r3, #0 80057de: d008 beq.n 80057f2 { /* Enable the main output */ __HAL_TIM_MOE_ENABLE(htim); 80057e0: 687b ldr r3, [r7, #4] 80057e2: 681b ldr r3, [r3, #0] 80057e4: 6c5a ldr r2, [r3, #68] @ 0x44 80057e6: 687b ldr r3, [r7, #4] 80057e8: 681b ldr r3, [r3, #0] 80057ea: 2180 movs r1, #128 @ 0x80 80057ec: 0209 lsls r1, r1, #8 80057ee: 430a orrs r2, r1 80057f0: 645a str r2, [r3, #68] @ 0x44 } /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 80057f2: 687b ldr r3, [r7, #4] 80057f4: 681b ldr r3, [r3, #0] 80057f6: 4a1a ldr r2, [pc, #104] @ (8005860 ) 80057f8: 4293 cmp r3, r2 80057fa: d00a beq.n 8005812 80057fc: 687b ldr r3, [r7, #4] 80057fe: 681a ldr r2, [r3, #0] 8005800: 2380 movs r3, #128 @ 0x80 8005802: 05db lsls r3, r3, #23 8005804: 429a cmp r2, r3 8005806: d004 beq.n 8005812 8005808: 687b ldr r3, [r7, #4] 800580a: 681b ldr r3, [r3, #0] 800580c: 4a17 ldr r2, [pc, #92] @ (800586c ) 800580e: 4293 cmp r3, r2 8005810: d116 bne.n 8005840 { tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; 8005812: 687b ldr r3, [r7, #4] 8005814: 681b ldr r3, [r3, #0] 8005816: 689b ldr r3, [r3, #8] 8005818: 4a15 ldr r2, [pc, #84] @ (8005870 ) 800581a: 4013 ands r3, r2 800581c: 60fb str r3, [r7, #12] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800581e: 68fb ldr r3, [r7, #12] 8005820: 2b06 cmp r3, #6 8005822: d016 beq.n 8005852 8005824: 68fa ldr r2, [r7, #12] 8005826: 2380 movs r3, #128 @ 0x80 8005828: 025b lsls r3, r3, #9 800582a: 429a cmp r2, r3 800582c: d011 beq.n 8005852 { __HAL_TIM_ENABLE(htim); 800582e: 687b ldr r3, [r7, #4] 8005830: 681b ldr r3, [r3, #0] 8005832: 681a ldr r2, [r3, #0] 8005834: 687b ldr r3, [r7, #4] 8005836: 681b ldr r3, [r3, #0] 8005838: 2101 movs r1, #1 800583a: 430a orrs r2, r1 800583c: 601a str r2, [r3, #0] if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 800583e: e008 b.n 8005852 } } else { __HAL_TIM_ENABLE(htim); 8005840: 687b ldr r3, [r7, #4] 8005842: 681b ldr r3, [r3, #0] 8005844: 681a ldr r2, [r3, #0] 8005846: 687b ldr r3, [r7, #4] 8005848: 681b ldr r3, [r3, #0] 800584a: 2101 movs r1, #1 800584c: 430a orrs r2, r1 800584e: 601a str r2, [r3, #0] 8005850: e000 b.n 8005854 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) 8005852: 46c0 nop @ (mov r8, r8) } /* Return function status */ return HAL_OK; 8005854: 2300 movs r3, #0 } 8005856: 0018 movs r0, r3 8005858: 46bd mov sp, r7 800585a: b004 add sp, #16 800585c: bd80 pop {r7, pc} 800585e: 46c0 nop @ (mov r8, r8) 8005860: 40012c00 .word 0x40012c00 8005864: 40014400 .word 0x40014400 8005868: 40014800 .word 0x40014800 800586c: 40000400 .word 0x40000400 8005870: 00010007 .word 0x00010007 08005874 : * @param htim TIM Encoder Interface handle * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) { 8005874: b580 push {r7, lr} 8005876: b086 sub sp, #24 8005878: af00 add r7, sp, #0 800587a: 6078 str r0, [r7, #4] 800587c: 6039 str r1, [r7, #0] uint32_t tmpsmcr; uint32_t tmpccmr1; uint32_t tmpccer; /* Check the TIM handle allocation */ if (htim == NULL) 800587e: 687b ldr r3, [r7, #4] 8005880: 2b00 cmp r3, #0 8005882: d101 bne.n 8005888 { return HAL_ERROR; 8005884: 2301 movs r3, #1 8005886: e090 b.n 80059aa assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); if (htim->State == HAL_TIM_STATE_RESET) 8005888: 687b ldr r3, [r7, #4] 800588a: 223d movs r2, #61 @ 0x3d 800588c: 5c9b ldrb r3, [r3, r2] 800588e: b2db uxtb r3, r3 8005890: 2b00 cmp r3, #0 8005892: d107 bne.n 80058a4 { /* Allocate lock resource and initialize it */ htim->Lock = HAL_UNLOCKED; 8005894: 687b ldr r3, [r7, #4] 8005896: 223c movs r2, #60 @ 0x3c 8005898: 2100 movs r1, #0 800589a: 5499 strb r1, [r3, r2] } /* Init the low level hardware : GPIO, CLOCK, NVIC */ htim->Encoder_MspInitCallback(htim); #else /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ HAL_TIM_Encoder_MspInit(htim); 800589c: 687b ldr r3, [r7, #4] 800589e: 0018 movs r0, r3 80058a0: f7fe f978 bl 8003b94 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } /* Set the TIM state */ htim->State = HAL_TIM_STATE_BUSY; 80058a4: 687b ldr r3, [r7, #4] 80058a6: 223d movs r2, #61 @ 0x3d 80058a8: 2102 movs r1, #2 80058aa: 5499 strb r1, [r3, r2] /* Reset the SMS and ECE bits */ htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); 80058ac: 687b ldr r3, [r7, #4] 80058ae: 681b ldr r3, [r3, #0] 80058b0: 689a ldr r2, [r3, #8] 80058b2: 687b ldr r3, [r7, #4] 80058b4: 681b ldr r3, [r3, #0] 80058b6: 493f ldr r1, [pc, #252] @ (80059b4 ) 80058b8: 400a ands r2, r1 80058ba: 609a str r2, [r3, #8] /* Configure the Time base in the Encoder Mode */ TIM_Base_SetConfig(htim->Instance, &htim->Init); 80058bc: 687b ldr r3, [r7, #4] 80058be: 681a ldr r2, [r3, #0] 80058c0: 687b ldr r3, [r7, #4] 80058c2: 3304 adds r3, #4 80058c4: 0019 movs r1, r3 80058c6: 0010 movs r0, r2 80058c8: f000 fc1e bl 8006108 /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80058cc: 687b ldr r3, [r7, #4] 80058ce: 681b ldr r3, [r3, #0] 80058d0: 689b ldr r3, [r3, #8] 80058d2: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmr1 = htim->Instance->CCMR1; 80058d4: 687b ldr r3, [r7, #4] 80058d6: 681b ldr r3, [r3, #0] 80058d8: 699b ldr r3, [r3, #24] 80058da: 613b str r3, [r7, #16] /* Get the TIMx CCER register value */ tmpccer = htim->Instance->CCER; 80058dc: 687b ldr r3, [r7, #4] 80058de: 681b ldr r3, [r3, #0] 80058e0: 6a1b ldr r3, [r3, #32] 80058e2: 60fb str r3, [r7, #12] /* Set the encoder Mode */ tmpsmcr |= sConfig->EncoderMode; 80058e4: 683b ldr r3, [r7, #0] 80058e6: 681b ldr r3, [r3, #0] 80058e8: 697a ldr r2, [r7, #20] 80058ea: 4313 orrs r3, r2 80058ec: 617b str r3, [r7, #20] /* Select the Capture Compare 1 and the Capture Compare 2 as input */ tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); 80058ee: 693b ldr r3, [r7, #16] 80058f0: 4a31 ldr r2, [pc, #196] @ (80059b8 ) 80058f2: 4013 ands r3, r2 80058f4: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); 80058f6: 683b ldr r3, [r7, #0] 80058f8: 689a ldr r2, [r3, #8] 80058fa: 683b ldr r3, [r7, #0] 80058fc: 699b ldr r3, [r3, #24] 80058fe: 021b lsls r3, r3, #8 8005900: 4313 orrs r3, r2 8005902: 693a ldr r2, [r7, #16] 8005904: 4313 orrs r3, r2 8005906: 613b str r3, [r7, #16] /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); 8005908: 693b ldr r3, [r7, #16] 800590a: 4a2c ldr r2, [pc, #176] @ (80059bc ) 800590c: 4013 ands r3, r2 800590e: 613b str r3, [r7, #16] tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); 8005910: 693b ldr r3, [r7, #16] 8005912: 4a2b ldr r2, [pc, #172] @ (80059c0 ) 8005914: 4013 ands r3, r2 8005916: 613b str r3, [r7, #16] tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); 8005918: 683b ldr r3, [r7, #0] 800591a: 68da ldr r2, [r3, #12] 800591c: 683b ldr r3, [r7, #0] 800591e: 69db ldr r3, [r3, #28] 8005920: 021b lsls r3, r3, #8 8005922: 4313 orrs r3, r2 8005924: 693a ldr r2, [r7, #16] 8005926: 4313 orrs r3, r2 8005928: 613b str r3, [r7, #16] tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); 800592a: 683b ldr r3, [r7, #0] 800592c: 691b ldr r3, [r3, #16] 800592e: 011a lsls r2, r3, #4 8005930: 683b ldr r3, [r7, #0] 8005932: 6a1b ldr r3, [r3, #32] 8005934: 031b lsls r3, r3, #12 8005936: 4313 orrs r3, r2 8005938: 693a ldr r2, [r7, #16] 800593a: 4313 orrs r3, r2 800593c: 613b str r3, [r7, #16] /* Set the TI1 and the TI2 Polarities */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); 800593e: 68fb ldr r3, [r7, #12] 8005940: 2222 movs r2, #34 @ 0x22 8005942: 4393 bics r3, r2 8005944: 60fb str r3, [r7, #12] tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); 8005946: 68fb ldr r3, [r7, #12] 8005948: 2288 movs r2, #136 @ 0x88 800594a: 4393 bics r3, r2 800594c: 60fb str r3, [r7, #12] tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); 800594e: 683b ldr r3, [r7, #0] 8005950: 685a ldr r2, [r3, #4] 8005952: 683b ldr r3, [r7, #0] 8005954: 695b ldr r3, [r3, #20] 8005956: 011b lsls r3, r3, #4 8005958: 4313 orrs r3, r2 800595a: 68fa ldr r2, [r7, #12] 800595c: 4313 orrs r3, r2 800595e: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005960: 687b ldr r3, [r7, #4] 8005962: 681b ldr r3, [r3, #0] 8005964: 697a ldr r2, [r7, #20] 8005966: 609a str r2, [r3, #8] /* Write to TIMx CCMR1 */ htim->Instance->CCMR1 = tmpccmr1; 8005968: 687b ldr r3, [r7, #4] 800596a: 681b ldr r3, [r3, #0] 800596c: 693a ldr r2, [r7, #16] 800596e: 619a str r2, [r3, #24] /* Write to TIMx CCER */ htim->Instance->CCER = tmpccer; 8005970: 687b ldr r3, [r7, #4] 8005972: 681b ldr r3, [r3, #0] 8005974: 68fa ldr r2, [r7, #12] 8005976: 621a str r2, [r3, #32] /* Initialize the DMA burst operation state */ htim->DMABurstState = HAL_DMA_BURST_STATE_READY; 8005978: 687b ldr r3, [r7, #4] 800597a: 2248 movs r2, #72 @ 0x48 800597c: 2101 movs r1, #1 800597e: 5499 strb r1, [r3, r2] /* Set the TIM channels state */ TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005980: 687b ldr r3, [r7, #4] 8005982: 223e movs r2, #62 @ 0x3e 8005984: 2101 movs r1, #1 8005986: 5499 strb r1, [r3, r2] TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005988: 687b ldr r3, [r7, #4] 800598a: 223f movs r2, #63 @ 0x3f 800598c: 2101 movs r1, #1 800598e: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); 8005990: 687b ldr r3, [r7, #4] 8005992: 2244 movs r2, #68 @ 0x44 8005994: 2101 movs r1, #1 8005996: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); 8005998: 687b ldr r3, [r7, #4] 800599a: 2245 movs r2, #69 @ 0x45 800599c: 2101 movs r1, #1 800599e: 5499 strb r1, [r3, r2] /* Initialize the TIM state*/ htim->State = HAL_TIM_STATE_READY; 80059a0: 687b ldr r3, [r7, #4] 80059a2: 223d movs r2, #61 @ 0x3d 80059a4: 2101 movs r1, #1 80059a6: 5499 strb r1, [r3, r2] return HAL_OK; 80059a8: 2300 movs r3, #0 } 80059aa: 0018 movs r0, r3 80059ac: 46bd mov sp, r7 80059ae: b006 add sp, #24 80059b0: bd80 pop {r7, pc} 80059b2: 46c0 nop @ (mov r8, r8) 80059b4: fffebff8 .word 0xfffebff8 80059b8: fffffcfc .word 0xfffffcfc 80059bc: fffff3f3 .word 0xfffff3f3 80059c0: ffff0f0f .word 0xffff0f0f 080059c4 : * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) { 80059c4: b590 push {r4, r7, lr} 80059c6: b085 sub sp, #20 80059c8: af00 add r7, sp, #0 80059ca: 6078 str r0, [r7, #4] 80059cc: 6039 str r1, [r7, #0] HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); 80059ce: 200f movs r0, #15 80059d0: 183b adds r3, r7, r0 80059d2: 687a ldr r2, [r7, #4] 80059d4: 213e movs r1, #62 @ 0x3e 80059d6: 5c52 ldrb r2, [r2, r1] 80059d8: 701a strb r2, [r3, #0] HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); 80059da: 230e movs r3, #14 80059dc: 18fb adds r3, r7, r3 80059de: 687a ldr r2, [r7, #4] 80059e0: 213f movs r1, #63 @ 0x3f 80059e2: 5c52 ldrb r2, [r2, r1] 80059e4: 701a strb r2, [r3, #0] HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); 80059e6: 240d movs r4, #13 80059e8: 193b adds r3, r7, r4 80059ea: 687a ldr r2, [r7, #4] 80059ec: 2144 movs r1, #68 @ 0x44 80059ee: 5c52 ldrb r2, [r2, r1] 80059f0: 701a strb r2, [r3, #0] HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); 80059f2: 230c movs r3, #12 80059f4: 18fb adds r3, r7, r3 80059f6: 687a ldr r2, [r7, #4] 80059f8: 2145 movs r1, #69 @ 0x45 80059fa: 5c52 ldrb r2, [r2, r1] 80059fc: 701a strb r2, [r3, #0] /* Check the parameters */ assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); /* Set the TIM channel(s) state */ if (Channel == TIM_CHANNEL_1) 80059fe: 683b ldr r3, [r7, #0] 8005a00: 2b00 cmp r3, #0 8005a02: d112 bne.n 8005a2a { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005a04: 183b adds r3, r7, r0 8005a06: 781b ldrb r3, [r3, #0] 8005a08: 2b01 cmp r3, #1 8005a0a: d103 bne.n 8005a14 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) 8005a0c: 193b adds r3, r7, r4 8005a0e: 781b ldrb r3, [r3, #0] 8005a10: 2b01 cmp r3, #1 8005a12: d001 beq.n 8005a18 { return HAL_ERROR; 8005a14: 2301 movs r3, #1 8005a16: e075 b.n 8005b04 } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005a18: 687b ldr r3, [r7, #4] 8005a1a: 223e movs r2, #62 @ 0x3e 8005a1c: 2102 movs r1, #2 8005a1e: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005a20: 687b ldr r3, [r7, #4] 8005a22: 2244 movs r2, #68 @ 0x44 8005a24: 2102 movs r1, #2 8005a26: 5499 strb r1, [r3, r2] 8005a28: e03d b.n 8005aa6 } } else if (Channel == TIM_CHANNEL_2) 8005a2a: 683b ldr r3, [r7, #0] 8005a2c: 2b04 cmp r3, #4 8005a2e: d114 bne.n 8005a5a { if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) 8005a30: 230e movs r3, #14 8005a32: 18fb adds r3, r7, r3 8005a34: 781b ldrb r3, [r3, #0] 8005a36: 2b01 cmp r3, #1 8005a38: d104 bne.n 8005a44 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) 8005a3a: 230c movs r3, #12 8005a3c: 18fb adds r3, r7, r3 8005a3e: 781b ldrb r3, [r3, #0] 8005a40: 2b01 cmp r3, #1 8005a42: d001 beq.n 8005a48 { return HAL_ERROR; 8005a44: 2301 movs r3, #1 8005a46: e05d b.n 8005b04 } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005a48: 687b ldr r3, [r7, #4] 8005a4a: 223f movs r2, #63 @ 0x3f 8005a4c: 2102 movs r1, #2 8005a4e: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005a50: 687b ldr r3, [r7, #4] 8005a52: 2245 movs r2, #69 @ 0x45 8005a54: 2102 movs r1, #2 8005a56: 5499 strb r1, [r3, r2] 8005a58: e025 b.n 8005aa6 } } else { if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005a5a: 230f movs r3, #15 8005a5c: 18fb adds r3, r7, r3 8005a5e: 781b ldrb r3, [r3, #0] 8005a60: 2b01 cmp r3, #1 8005a62: d10e bne.n 8005a82 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) 8005a64: 230e movs r3, #14 8005a66: 18fb adds r3, r7, r3 8005a68: 781b ldrb r3, [r3, #0] 8005a6a: 2b01 cmp r3, #1 8005a6c: d109 bne.n 8005a82 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) 8005a6e: 230d movs r3, #13 8005a70: 18fb adds r3, r7, r3 8005a72: 781b ldrb r3, [r3, #0] 8005a74: 2b01 cmp r3, #1 8005a76: d104 bne.n 8005a82 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) 8005a78: 230c movs r3, #12 8005a7a: 18fb adds r3, r7, r3 8005a7c: 781b ldrb r3, [r3, #0] 8005a7e: 2b01 cmp r3, #1 8005a80: d001 beq.n 8005a86 { return HAL_ERROR; 8005a82: 2301 movs r3, #1 8005a84: e03e b.n 8005b04 } else { TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005a86: 687b ldr r3, [r7, #4] 8005a88: 223e movs r2, #62 @ 0x3e 8005a8a: 2102 movs r1, #2 8005a8c: 5499 strb r1, [r3, r2] TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005a8e: 687b ldr r3, [r7, #4] 8005a90: 223f movs r2, #63 @ 0x3f 8005a92: 2102 movs r1, #2 8005a94: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); 8005a96: 687b ldr r3, [r7, #4] 8005a98: 2244 movs r2, #68 @ 0x44 8005a9a: 2102 movs r1, #2 8005a9c: 5499 strb r1, [r3, r2] TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); 8005a9e: 687b ldr r3, [r7, #4] 8005aa0: 2245 movs r2, #69 @ 0x45 8005aa2: 2102 movs r1, #2 8005aa4: 5499 strb r1, [r3, r2] } } /* Enable the encoder interface channels */ switch (Channel) 8005aa6: 683b ldr r3, [r7, #0] 8005aa8: 2b00 cmp r3, #0 8005aaa: d003 beq.n 8005ab4 8005aac: 683b ldr r3, [r7, #0] 8005aae: 2b04 cmp r3, #4 8005ab0: d008 beq.n 8005ac4 8005ab2: e00f b.n 8005ad4 { case TIM_CHANNEL_1: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 8005ab4: 687b ldr r3, [r7, #4] 8005ab6: 681b ldr r3, [r3, #0] 8005ab8: 2201 movs r2, #1 8005aba: 2100 movs r1, #0 8005abc: 0018 movs r0, r3 8005abe: f000 fed7 bl 8006870 break; 8005ac2: e016 b.n 8005af2 } case TIM_CHANNEL_2: { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 8005ac4: 687b ldr r3, [r7, #4] 8005ac6: 681b ldr r3, [r3, #0] 8005ac8: 2201 movs r2, #1 8005aca: 2104 movs r1, #4 8005acc: 0018 movs r0, r3 8005ace: f000 fecf bl 8006870 break; 8005ad2: e00e b.n 8005af2 } default : { TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); 8005ad4: 687b ldr r3, [r7, #4] 8005ad6: 681b ldr r3, [r3, #0] 8005ad8: 2201 movs r2, #1 8005ada: 2100 movs r1, #0 8005adc: 0018 movs r0, r3 8005ade: f000 fec7 bl 8006870 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); 8005ae2: 687b ldr r3, [r7, #4] 8005ae4: 681b ldr r3, [r3, #0] 8005ae6: 2201 movs r2, #1 8005ae8: 2104 movs r1, #4 8005aea: 0018 movs r0, r3 8005aec: f000 fec0 bl 8006870 break; 8005af0: 46c0 nop @ (mov r8, r8) } } /* Enable the Peripheral */ __HAL_TIM_ENABLE(htim); 8005af2: 687b ldr r3, [r7, #4] 8005af4: 681b ldr r3, [r3, #0] 8005af6: 681a ldr r2, [r3, #0] 8005af8: 687b ldr r3, [r7, #4] 8005afa: 681b ldr r3, [r3, #0] 8005afc: 2101 movs r1, #1 8005afe: 430a orrs r2, r1 8005b00: 601a str r2, [r3, #0] /* Return function status */ return HAL_OK; 8005b02: 2300 movs r3, #0 } 8005b04: 0018 movs r0, r3 8005b06: 46bd mov sp, r7 8005b08: b005 add sp, #20 8005b0a: bd90 pop {r4, r7, pc} 08005b0c : * @brief This function handles TIM interrupts requests. * @param htim TIM handle * @retval None */ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) { 8005b0c: b580 push {r7, lr} 8005b0e: b084 sub sp, #16 8005b10: af00 add r7, sp, #0 8005b12: 6078 str r0, [r7, #4] uint32_t itsource = htim->Instance->DIER; 8005b14: 687b ldr r3, [r7, #4] 8005b16: 681b ldr r3, [r3, #0] 8005b18: 68db ldr r3, [r3, #12] 8005b1a: 60fb str r3, [r7, #12] uint32_t itflag = htim->Instance->SR; 8005b1c: 687b ldr r3, [r7, #4] 8005b1e: 681b ldr r3, [r3, #0] 8005b20: 691b ldr r3, [r3, #16] 8005b22: 60bb str r3, [r7, #8] /* Capture compare 1 event */ if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) 8005b24: 68bb ldr r3, [r7, #8] 8005b26: 2202 movs r2, #2 8005b28: 4013 ands r3, r2 8005b2a: d021 beq.n 8005b70 { if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) 8005b2c: 68fb ldr r3, [r7, #12] 8005b2e: 2202 movs r2, #2 8005b30: 4013 ands r3, r2 8005b32: d01d beq.n 8005b70 { { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); 8005b34: 687b ldr r3, [r7, #4] 8005b36: 681b ldr r3, [r3, #0] 8005b38: 2203 movs r2, #3 8005b3a: 4252 negs r2, r2 8005b3c: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; 8005b3e: 687b ldr r3, [r7, #4] 8005b40: 2201 movs r2, #1 8005b42: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) 8005b44: 687b ldr r3, [r7, #4] 8005b46: 681b ldr r3, [r3, #0] 8005b48: 699b ldr r3, [r3, #24] 8005b4a: 2203 movs r2, #3 8005b4c: 4013 ands r3, r2 8005b4e: d004 beq.n 8005b5a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8005b50: 687b ldr r3, [r7, #4] 8005b52: 0018 movs r0, r3 8005b54: f000 fac0 bl 80060d8 8005b58: e007 b.n 8005b6a { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005b5a: 687b ldr r3, [r7, #4] 8005b5c: 0018 movs r0, r3 8005b5e: f000 fab3 bl 80060c8 HAL_TIM_PWM_PulseFinishedCallback(htim); 8005b62: 687b ldr r3, [r7, #4] 8005b64: 0018 movs r0, r3 8005b66: f000 fabf bl 80060e8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005b6a: 687b ldr r3, [r7, #4] 8005b6c: 2200 movs r2, #0 8005b6e: 771a strb r2, [r3, #28] } } } /* Capture compare 2 event */ if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) 8005b70: 68bb ldr r3, [r7, #8] 8005b72: 2204 movs r2, #4 8005b74: 4013 ands r3, r2 8005b76: d022 beq.n 8005bbe { if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) 8005b78: 68fb ldr r3, [r7, #12] 8005b7a: 2204 movs r2, #4 8005b7c: 4013 ands r3, r2 8005b7e: d01e beq.n 8005bbe { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); 8005b80: 687b ldr r3, [r7, #4] 8005b82: 681b ldr r3, [r3, #0] 8005b84: 2205 movs r2, #5 8005b86: 4252 negs r2, r2 8005b88: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; 8005b8a: 687b ldr r3, [r7, #4] 8005b8c: 2202 movs r2, #2 8005b8e: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) 8005b90: 687b ldr r3, [r7, #4] 8005b92: 681b ldr r3, [r3, #0] 8005b94: 699a ldr r2, [r3, #24] 8005b96: 23c0 movs r3, #192 @ 0xc0 8005b98: 009b lsls r3, r3, #2 8005b9a: 4013 ands r3, r2 8005b9c: d004 beq.n 8005ba8 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8005b9e: 687b ldr r3, [r7, #4] 8005ba0: 0018 movs r0, r3 8005ba2: f000 fa99 bl 80060d8 8005ba6: e007 b.n 8005bb8 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005ba8: 687b ldr r3, [r7, #4] 8005baa: 0018 movs r0, r3 8005bac: f000 fa8c bl 80060c8 HAL_TIM_PWM_PulseFinishedCallback(htim); 8005bb0: 687b ldr r3, [r7, #4] 8005bb2: 0018 movs r0, r3 8005bb4: f000 fa98 bl 80060e8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005bb8: 687b ldr r3, [r7, #4] 8005bba: 2200 movs r2, #0 8005bbc: 771a strb r2, [r3, #28] } } /* Capture compare 3 event */ if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) 8005bbe: 68bb ldr r3, [r7, #8] 8005bc0: 2208 movs r2, #8 8005bc2: 4013 ands r3, r2 8005bc4: d021 beq.n 8005c0a { if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) 8005bc6: 68fb ldr r3, [r7, #12] 8005bc8: 2208 movs r2, #8 8005bca: 4013 ands r3, r2 8005bcc: d01d beq.n 8005c0a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); 8005bce: 687b ldr r3, [r7, #4] 8005bd0: 681b ldr r3, [r3, #0] 8005bd2: 2209 movs r2, #9 8005bd4: 4252 negs r2, r2 8005bd6: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; 8005bd8: 687b ldr r3, [r7, #4] 8005bda: 2204 movs r2, #4 8005bdc: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) 8005bde: 687b ldr r3, [r7, #4] 8005be0: 681b ldr r3, [r3, #0] 8005be2: 69db ldr r3, [r3, #28] 8005be4: 2203 movs r2, #3 8005be6: 4013 ands r3, r2 8005be8: d004 beq.n 8005bf4 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8005bea: 687b ldr r3, [r7, #4] 8005bec: 0018 movs r0, r3 8005bee: f000 fa73 bl 80060d8 8005bf2: e007 b.n 8005c04 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005bf4: 687b ldr r3, [r7, #4] 8005bf6: 0018 movs r0, r3 8005bf8: f000 fa66 bl 80060c8 HAL_TIM_PWM_PulseFinishedCallback(htim); 8005bfc: 687b ldr r3, [r7, #4] 8005bfe: 0018 movs r0, r3 8005c00: f000 fa72 bl 80060e8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005c04: 687b ldr r3, [r7, #4] 8005c06: 2200 movs r2, #0 8005c08: 771a strb r2, [r3, #28] } } /* Capture compare 4 event */ if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) 8005c0a: 68bb ldr r3, [r7, #8] 8005c0c: 2210 movs r2, #16 8005c0e: 4013 ands r3, r2 8005c10: d022 beq.n 8005c58 { if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) 8005c12: 68fb ldr r3, [r7, #12] 8005c14: 2210 movs r2, #16 8005c16: 4013 ands r3, r2 8005c18: d01e beq.n 8005c58 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); 8005c1a: 687b ldr r3, [r7, #4] 8005c1c: 681b ldr r3, [r3, #0] 8005c1e: 2211 movs r2, #17 8005c20: 4252 negs r2, r2 8005c22: 611a str r2, [r3, #16] htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; 8005c24: 687b ldr r3, [r7, #4] 8005c26: 2208 movs r2, #8 8005c28: 771a strb r2, [r3, #28] /* Input capture event */ if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) 8005c2a: 687b ldr r3, [r7, #4] 8005c2c: 681b ldr r3, [r3, #0] 8005c2e: 69da ldr r2, [r3, #28] 8005c30: 23c0 movs r3, #192 @ 0xc0 8005c32: 009b lsls r3, r3, #2 8005c34: 4013 ands r3, r2 8005c36: d004 beq.n 8005c42 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->IC_CaptureCallback(htim); #else HAL_TIM_IC_CaptureCallback(htim); 8005c38: 687b ldr r3, [r7, #4] 8005c3a: 0018 movs r0, r3 8005c3c: f000 fa4c bl 80060d8 8005c40: e007 b.n 8005c52 { #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->OC_DelayElapsedCallback(htim); htim->PWM_PulseFinishedCallback(htim); #else HAL_TIM_OC_DelayElapsedCallback(htim); 8005c42: 687b ldr r3, [r7, #4] 8005c44: 0018 movs r0, r3 8005c46: f000 fa3f bl 80060c8 HAL_TIM_PWM_PulseFinishedCallback(htim); 8005c4a: 687b ldr r3, [r7, #4] 8005c4c: 0018 movs r0, r3 8005c4e: f000 fa4b bl 80060e8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; 8005c52: 687b ldr r3, [r7, #4] 8005c54: 2200 movs r2, #0 8005c56: 771a strb r2, [r3, #28] } } /* TIM Update event */ if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) 8005c58: 68bb ldr r3, [r7, #8] 8005c5a: 2201 movs r2, #1 8005c5c: 4013 ands r3, r2 8005c5e: d00c beq.n 8005c7a { if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) 8005c60: 68fb ldr r3, [r7, #12] 8005c62: 2201 movs r2, #1 8005c64: 4013 ands r3, r2 8005c66: d008 beq.n 8005c7a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); 8005c68: 687b ldr r3, [r7, #4] 8005c6a: 681b ldr r3, [r3, #0] 8005c6c: 2202 movs r2, #2 8005c6e: 4252 negs r2, r2 8005c70: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->PeriodElapsedCallback(htim); #else HAL_TIM_PeriodElapsedCallback(htim); 8005c72: 687b ldr r3, [r7, #4] 8005c74: 0018 movs r0, r3 8005c76: f7fb fde1 bl 800183c #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break input event */ if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 8005c7a: 68bb ldr r3, [r7, #8] 8005c7c: 2280 movs r2, #128 @ 0x80 8005c7e: 4013 ands r3, r2 8005c80: d104 bne.n 8005c8c ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) 8005c82: 68ba ldr r2, [r7, #8] 8005c84: 2380 movs r3, #128 @ 0x80 8005c86: 019b lsls r3, r3, #6 8005c88: 4013 ands r3, r2 if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ 8005c8a: d00b beq.n 8005ca4 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8005c8c: 68fb ldr r3, [r7, #12] 8005c8e: 2280 movs r2, #128 @ 0x80 8005c90: 4013 ands r3, r2 8005c92: d007 beq.n 8005ca4 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); 8005c94: 687b ldr r3, [r7, #4] 8005c96: 681b ldr r3, [r3, #0] 8005c98: 4a1e ldr r2, [pc, #120] @ (8005d14 ) 8005c9a: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->BreakCallback(htim); #else HAL_TIMEx_BreakCallback(htim); 8005c9c: 687b ldr r3, [r7, #4] 8005c9e: 0018 movs r0, r3 8005ca0: f000 ff16 bl 8006ad0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Break2 input event */ if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) 8005ca4: 68ba ldr r2, [r7, #8] 8005ca6: 2380 movs r3, #128 @ 0x80 8005ca8: 005b lsls r3, r3, #1 8005caa: 4013 ands r3, r2 8005cac: d00b beq.n 8005cc6 { if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) 8005cae: 68fb ldr r3, [r7, #12] 8005cb0: 2280 movs r2, #128 @ 0x80 8005cb2: 4013 ands r3, r2 8005cb4: d007 beq.n 8005cc6 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); 8005cb6: 687b ldr r3, [r7, #4] 8005cb8: 681b ldr r3, [r3, #0] 8005cba: 4a17 ldr r2, [pc, #92] @ (8005d18 ) 8005cbc: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->Break2Callback(htim); #else HAL_TIMEx_Break2Callback(htim); 8005cbe: 687b ldr r3, [r7, #4] 8005cc0: 0018 movs r0, r3 8005cc2: f000 ff0d bl 8006ae0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM Trigger detection event */ if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) 8005cc6: 68bb ldr r3, [r7, #8] 8005cc8: 2240 movs r2, #64 @ 0x40 8005cca: 4013 ands r3, r2 8005ccc: d00c beq.n 8005ce8 { if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) 8005cce: 68fb ldr r3, [r7, #12] 8005cd0: 2240 movs r2, #64 @ 0x40 8005cd2: 4013 ands r3, r2 8005cd4: d008 beq.n 8005ce8 { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); 8005cd6: 687b ldr r3, [r7, #4] 8005cd8: 681b ldr r3, [r3, #0] 8005cda: 2241 movs r2, #65 @ 0x41 8005cdc: 4252 negs r2, r2 8005cde: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->TriggerCallback(htim); #else HAL_TIM_TriggerCallback(htim); 8005ce0: 687b ldr r3, [r7, #4] 8005ce2: 0018 movs r0, r3 8005ce4: f000 fa08 bl 80060f8 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } /* TIM commutation event */ if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) 8005ce8: 68bb ldr r3, [r7, #8] 8005cea: 2220 movs r2, #32 8005cec: 4013 ands r3, r2 8005cee: d00c beq.n 8005d0a { if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) 8005cf0: 68fb ldr r3, [r7, #12] 8005cf2: 2220 movs r2, #32 8005cf4: 4013 ands r3, r2 8005cf6: d008 beq.n 8005d0a { __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); 8005cf8: 687b ldr r3, [r7, #4] 8005cfa: 681b ldr r3, [r3, #0] 8005cfc: 2221 movs r2, #33 @ 0x21 8005cfe: 4252 negs r2, r2 8005d00: 611a str r2, [r3, #16] #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) htim->CommutationCallback(htim); #else HAL_TIMEx_CommutCallback(htim); 8005d02: 687b ldr r3, [r7, #4] 8005d04: 0018 movs r0, r3 8005d06: f000 fedb bl 8006ac0 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ } } } 8005d0a: 46c0 nop @ (mov r8, r8) 8005d0c: 46bd mov sp, r7 8005d0e: b004 add sp, #16 8005d10: bd80 pop {r7, pc} 8005d12: 46c0 nop @ (mov r8, r8) 8005d14: ffffdf7f .word 0xffffdf7f 8005d18: fffffeff .word 0xfffffeff 08005d1c : * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, uint32_t Channel) { 8005d1c: b580 push {r7, lr} 8005d1e: b086 sub sp, #24 8005d20: af00 add r7, sp, #0 8005d22: 60f8 str r0, [r7, #12] 8005d24: 60b9 str r1, [r7, #8] 8005d26: 607a str r2, [r7, #4] HAL_StatusTypeDef status = HAL_OK; 8005d28: 2317 movs r3, #23 8005d2a: 18fb adds r3, r7, r3 8005d2c: 2200 movs r2, #0 8005d2e: 701a strb r2, [r3, #0] assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); /* Process Locked */ __HAL_LOCK(htim); 8005d30: 68fb ldr r3, [r7, #12] 8005d32: 223c movs r2, #60 @ 0x3c 8005d34: 5c9b ldrb r3, [r3, r2] 8005d36: 2b01 cmp r3, #1 8005d38: d101 bne.n 8005d3e 8005d3a: 2302 movs r3, #2 8005d3c: e0e5 b.n 8005f0a 8005d3e: 68fb ldr r3, [r7, #12] 8005d40: 223c movs r2, #60 @ 0x3c 8005d42: 2101 movs r1, #1 8005d44: 5499 strb r1, [r3, r2] switch (Channel) 8005d46: 687b ldr r3, [r7, #4] 8005d48: 2b14 cmp r3, #20 8005d4a: d900 bls.n 8005d4e 8005d4c: e0d1 b.n 8005ef2 8005d4e: 687b ldr r3, [r7, #4] 8005d50: 009a lsls r2, r3, #2 8005d52: 4b70 ldr r3, [pc, #448] @ (8005f14 ) 8005d54: 18d3 adds r3, r2, r3 8005d56: 681b ldr r3, [r3, #0] 8005d58: 469f mov pc, r3 { /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); /* Configure the Channel 1 in PWM mode */ TIM_OC1_SetConfig(htim->Instance, sConfig); 8005d5a: 68fb ldr r3, [r7, #12] 8005d5c: 681b ldr r3, [r3, #0] 8005d5e: 68ba ldr r2, [r7, #8] 8005d60: 0011 movs r1, r2 8005d62: 0018 movs r0, r3 8005d64: f000 fa4c bl 8006200 /* Set the Preload enable bit for channel1 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; 8005d68: 68fb ldr r3, [r7, #12] 8005d6a: 681b ldr r3, [r3, #0] 8005d6c: 699a ldr r2, [r3, #24] 8005d6e: 68fb ldr r3, [r7, #12] 8005d70: 681b ldr r3, [r3, #0] 8005d72: 2108 movs r1, #8 8005d74: 430a orrs r2, r1 8005d76: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; 8005d78: 68fb ldr r3, [r7, #12] 8005d7a: 681b ldr r3, [r3, #0] 8005d7c: 699a ldr r2, [r3, #24] 8005d7e: 68fb ldr r3, [r7, #12] 8005d80: 681b ldr r3, [r3, #0] 8005d82: 2104 movs r1, #4 8005d84: 438a bics r2, r1 8005d86: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode; 8005d88: 68fb ldr r3, [r7, #12] 8005d8a: 681b ldr r3, [r3, #0] 8005d8c: 6999 ldr r1, [r3, #24] 8005d8e: 68bb ldr r3, [r7, #8] 8005d90: 691a ldr r2, [r3, #16] 8005d92: 68fb ldr r3, [r7, #12] 8005d94: 681b ldr r3, [r3, #0] 8005d96: 430a orrs r2, r1 8005d98: 619a str r2, [r3, #24] break; 8005d9a: e0af b.n 8005efc { /* Check the parameters */ assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); /* Configure the Channel 2 in PWM mode */ TIM_OC2_SetConfig(htim->Instance, sConfig); 8005d9c: 68fb ldr r3, [r7, #12] 8005d9e: 681b ldr r3, [r3, #0] 8005da0: 68ba ldr r2, [r7, #8] 8005da2: 0011 movs r1, r2 8005da4: 0018 movs r0, r3 8005da6: f000 faab bl 8006300 /* Set the Preload enable bit for channel2 */ htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; 8005daa: 68fb ldr r3, [r7, #12] 8005dac: 681b ldr r3, [r3, #0] 8005dae: 699a ldr r2, [r3, #24] 8005db0: 68fb ldr r3, [r7, #12] 8005db2: 681b ldr r3, [r3, #0] 8005db4: 2180 movs r1, #128 @ 0x80 8005db6: 0109 lsls r1, r1, #4 8005db8: 430a orrs r2, r1 8005dba: 619a str r2, [r3, #24] /* Configure the Output Fast mode */ htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; 8005dbc: 68fb ldr r3, [r7, #12] 8005dbe: 681b ldr r3, [r3, #0] 8005dc0: 699a ldr r2, [r3, #24] 8005dc2: 68fb ldr r3, [r7, #12] 8005dc4: 681b ldr r3, [r3, #0] 8005dc6: 4954 ldr r1, [pc, #336] @ (8005f18 ) 8005dc8: 400a ands r2, r1 8005dca: 619a str r2, [r3, #24] htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; 8005dcc: 68fb ldr r3, [r7, #12] 8005dce: 681b ldr r3, [r3, #0] 8005dd0: 6999 ldr r1, [r3, #24] 8005dd2: 68bb ldr r3, [r7, #8] 8005dd4: 691b ldr r3, [r3, #16] 8005dd6: 021a lsls r2, r3, #8 8005dd8: 68fb ldr r3, [r7, #12] 8005dda: 681b ldr r3, [r3, #0] 8005ddc: 430a orrs r2, r1 8005dde: 619a str r2, [r3, #24] break; 8005de0: e08c b.n 8005efc { /* Check the parameters */ assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); /* Configure the Channel 3 in PWM mode */ TIM_OC3_SetConfig(htim->Instance, sConfig); 8005de2: 68fb ldr r3, [r7, #12] 8005de4: 681b ldr r3, [r3, #0] 8005de6: 68ba ldr r2, [r7, #8] 8005de8: 0011 movs r1, r2 8005dea: 0018 movs r0, r3 8005dec: f000 fb06 bl 80063fc /* Set the Preload enable bit for channel3 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; 8005df0: 68fb ldr r3, [r7, #12] 8005df2: 681b ldr r3, [r3, #0] 8005df4: 69da ldr r2, [r3, #28] 8005df6: 68fb ldr r3, [r7, #12] 8005df8: 681b ldr r3, [r3, #0] 8005dfa: 2108 movs r1, #8 8005dfc: 430a orrs r2, r1 8005dfe: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; 8005e00: 68fb ldr r3, [r7, #12] 8005e02: 681b ldr r3, [r3, #0] 8005e04: 69da ldr r2, [r3, #28] 8005e06: 68fb ldr r3, [r7, #12] 8005e08: 681b ldr r3, [r3, #0] 8005e0a: 2104 movs r1, #4 8005e0c: 438a bics r2, r1 8005e0e: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode; 8005e10: 68fb ldr r3, [r7, #12] 8005e12: 681b ldr r3, [r3, #0] 8005e14: 69d9 ldr r1, [r3, #28] 8005e16: 68bb ldr r3, [r7, #8] 8005e18: 691a ldr r2, [r3, #16] 8005e1a: 68fb ldr r3, [r7, #12] 8005e1c: 681b ldr r3, [r3, #0] 8005e1e: 430a orrs r2, r1 8005e20: 61da str r2, [r3, #28] break; 8005e22: e06b b.n 8005efc { /* Check the parameters */ assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); /* Configure the Channel 4 in PWM mode */ TIM_OC4_SetConfig(htim->Instance, sConfig); 8005e24: 68fb ldr r3, [r7, #12] 8005e26: 681b ldr r3, [r3, #0] 8005e28: 68ba ldr r2, [r7, #8] 8005e2a: 0011 movs r1, r2 8005e2c: 0018 movs r0, r3 8005e2e: f000 fb67 bl 8006500 /* Set the Preload enable bit for channel4 */ htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; 8005e32: 68fb ldr r3, [r7, #12] 8005e34: 681b ldr r3, [r3, #0] 8005e36: 69da ldr r2, [r3, #28] 8005e38: 68fb ldr r3, [r7, #12] 8005e3a: 681b ldr r3, [r3, #0] 8005e3c: 2180 movs r1, #128 @ 0x80 8005e3e: 0109 lsls r1, r1, #4 8005e40: 430a orrs r2, r1 8005e42: 61da str r2, [r3, #28] /* Configure the Output Fast mode */ htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; 8005e44: 68fb ldr r3, [r7, #12] 8005e46: 681b ldr r3, [r3, #0] 8005e48: 69da ldr r2, [r3, #28] 8005e4a: 68fb ldr r3, [r7, #12] 8005e4c: 681b ldr r3, [r3, #0] 8005e4e: 4932 ldr r1, [pc, #200] @ (8005f18 ) 8005e50: 400a ands r2, r1 8005e52: 61da str r2, [r3, #28] htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; 8005e54: 68fb ldr r3, [r7, #12] 8005e56: 681b ldr r3, [r3, #0] 8005e58: 69d9 ldr r1, [r3, #28] 8005e5a: 68bb ldr r3, [r7, #8] 8005e5c: 691b ldr r3, [r3, #16] 8005e5e: 021a lsls r2, r3, #8 8005e60: 68fb ldr r3, [r7, #12] 8005e62: 681b ldr r3, [r3, #0] 8005e64: 430a orrs r2, r1 8005e66: 61da str r2, [r3, #28] break; 8005e68: e048 b.n 8005efc { /* Check the parameters */ assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); /* Configure the Channel 5 in PWM mode */ TIM_OC5_SetConfig(htim->Instance, sConfig); 8005e6a: 68fb ldr r3, [r7, #12] 8005e6c: 681b ldr r3, [r3, #0] 8005e6e: 68ba ldr r2, [r7, #8] 8005e70: 0011 movs r1, r2 8005e72: 0018 movs r0, r3 8005e74: f000 fba8 bl 80065c8 /* Set the Preload enable bit for channel5*/ htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; 8005e78: 68fb ldr r3, [r7, #12] 8005e7a: 681b ldr r3, [r3, #0] 8005e7c: 6d5a ldr r2, [r3, #84] @ 0x54 8005e7e: 68fb ldr r3, [r7, #12] 8005e80: 681b ldr r3, [r3, #0] 8005e82: 2108 movs r1, #8 8005e84: 430a orrs r2, r1 8005e86: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; 8005e88: 68fb ldr r3, [r7, #12] 8005e8a: 681b ldr r3, [r3, #0] 8005e8c: 6d5a ldr r2, [r3, #84] @ 0x54 8005e8e: 68fb ldr r3, [r7, #12] 8005e90: 681b ldr r3, [r3, #0] 8005e92: 2104 movs r1, #4 8005e94: 438a bics r2, r1 8005e96: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode; 8005e98: 68fb ldr r3, [r7, #12] 8005e9a: 681b ldr r3, [r3, #0] 8005e9c: 6d59 ldr r1, [r3, #84] @ 0x54 8005e9e: 68bb ldr r3, [r7, #8] 8005ea0: 691a ldr r2, [r3, #16] 8005ea2: 68fb ldr r3, [r7, #12] 8005ea4: 681b ldr r3, [r3, #0] 8005ea6: 430a orrs r2, r1 8005ea8: 655a str r2, [r3, #84] @ 0x54 break; 8005eaa: e027 b.n 8005efc { /* Check the parameters */ assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); /* Configure the Channel 6 in PWM mode */ TIM_OC6_SetConfig(htim->Instance, sConfig); 8005eac: 68fb ldr r3, [r7, #12] 8005eae: 681b ldr r3, [r3, #0] 8005eb0: 68ba ldr r2, [r7, #8] 8005eb2: 0011 movs r1, r2 8005eb4: 0018 movs r0, r3 8005eb6: f000 fbe1 bl 800667c /* Set the Preload enable bit for channel6 */ htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; 8005eba: 68fb ldr r3, [r7, #12] 8005ebc: 681b ldr r3, [r3, #0] 8005ebe: 6d5a ldr r2, [r3, #84] @ 0x54 8005ec0: 68fb ldr r3, [r7, #12] 8005ec2: 681b ldr r3, [r3, #0] 8005ec4: 2180 movs r1, #128 @ 0x80 8005ec6: 0109 lsls r1, r1, #4 8005ec8: 430a orrs r2, r1 8005eca: 655a str r2, [r3, #84] @ 0x54 /* Configure the Output Fast mode */ htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; 8005ecc: 68fb ldr r3, [r7, #12] 8005ece: 681b ldr r3, [r3, #0] 8005ed0: 6d5a ldr r2, [r3, #84] @ 0x54 8005ed2: 68fb ldr r3, [r7, #12] 8005ed4: 681b ldr r3, [r3, #0] 8005ed6: 4910 ldr r1, [pc, #64] @ (8005f18 ) 8005ed8: 400a ands r2, r1 8005eda: 655a str r2, [r3, #84] @ 0x54 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; 8005edc: 68fb ldr r3, [r7, #12] 8005ede: 681b ldr r3, [r3, #0] 8005ee0: 6d59 ldr r1, [r3, #84] @ 0x54 8005ee2: 68bb ldr r3, [r7, #8] 8005ee4: 691b ldr r3, [r3, #16] 8005ee6: 021a lsls r2, r3, #8 8005ee8: 68fb ldr r3, [r7, #12] 8005eea: 681b ldr r3, [r3, #0] 8005eec: 430a orrs r2, r1 8005eee: 655a str r2, [r3, #84] @ 0x54 break; 8005ef0: e004 b.n 8005efc } default: status = HAL_ERROR; 8005ef2: 2317 movs r3, #23 8005ef4: 18fb adds r3, r7, r3 8005ef6: 2201 movs r2, #1 8005ef8: 701a strb r2, [r3, #0] break; 8005efa: 46c0 nop @ (mov r8, r8) } __HAL_UNLOCK(htim); 8005efc: 68fb ldr r3, [r7, #12] 8005efe: 223c movs r2, #60 @ 0x3c 8005f00: 2100 movs r1, #0 8005f02: 5499 strb r1, [r3, r2] return status; 8005f04: 2317 movs r3, #23 8005f06: 18fb adds r3, r7, r3 8005f08: 781b ldrb r3, [r3, #0] } 8005f0a: 0018 movs r0, r3 8005f0c: 46bd mov sp, r7 8005f0e: b006 add sp, #24 8005f10: bd80 pop {r7, pc} 8005f12: 46c0 nop @ (mov r8, r8) 8005f14: 08007e10 .word 0x08007e10 8005f18: fffffbff .word 0xfffffbff 08005f1c : * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) { 8005f1c: b580 push {r7, lr} 8005f1e: b084 sub sp, #16 8005f20: af00 add r7, sp, #0 8005f22: 6078 str r0, [r7, #4] 8005f24: 6039 str r1, [r7, #0] HAL_StatusTypeDef status = HAL_OK; 8005f26: 230f movs r3, #15 8005f28: 18fb adds r3, r7, r3 8005f2a: 2200 movs r2, #0 8005f2c: 701a strb r2, [r3, #0] uint32_t tmpsmcr; /* Process Locked */ __HAL_LOCK(htim); 8005f2e: 687b ldr r3, [r7, #4] 8005f30: 223c movs r2, #60 @ 0x3c 8005f32: 5c9b ldrb r3, [r3, r2] 8005f34: 2b01 cmp r3, #1 8005f36: d101 bne.n 8005f3c 8005f38: 2302 movs r3, #2 8005f3a: e0bc b.n 80060b6 8005f3c: 687b ldr r3, [r7, #4] 8005f3e: 223c movs r2, #60 @ 0x3c 8005f40: 2101 movs r1, #1 8005f42: 5499 strb r1, [r3, r2] htim->State = HAL_TIM_STATE_BUSY; 8005f44: 687b ldr r3, [r7, #4] 8005f46: 223d movs r2, #61 @ 0x3d 8005f48: 2102 movs r1, #2 8005f4a: 5499 strb r1, [r3, r2] /* Check the parameters */ assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ tmpsmcr = htim->Instance->SMCR; 8005f4c: 687b ldr r3, [r7, #4] 8005f4e: 681b ldr r3, [r3, #0] 8005f50: 689b ldr r3, [r3, #8] 8005f52: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); 8005f54: 68bb ldr r3, [r7, #8] 8005f56: 4a5a ldr r2, [pc, #360] @ (80060c0 ) 8005f58: 4013 ands r3, r2 8005f5a: 60bb str r3, [r7, #8] tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8005f5c: 68bb ldr r3, [r7, #8] 8005f5e: 4a59 ldr r2, [pc, #356] @ (80060c4 ) 8005f60: 4013 ands r3, r2 8005f62: 60bb str r3, [r7, #8] htim->Instance->SMCR = tmpsmcr; 8005f64: 687b ldr r3, [r7, #4] 8005f66: 681b ldr r3, [r3, #0] 8005f68: 68ba ldr r2, [r7, #8] 8005f6a: 609a str r2, [r3, #8] switch (sClockSourceConfig->ClockSource) 8005f6c: 683b ldr r3, [r7, #0] 8005f6e: 681b ldr r3, [r3, #0] 8005f70: 2280 movs r2, #128 @ 0x80 8005f72: 0192 lsls r2, r2, #6 8005f74: 4293 cmp r3, r2 8005f76: d040 beq.n 8005ffa 8005f78: 2280 movs r2, #128 @ 0x80 8005f7a: 0192 lsls r2, r2, #6 8005f7c: 4293 cmp r3, r2 8005f7e: d900 bls.n 8005f82 8005f80: e088 b.n 8006094 8005f82: 2280 movs r2, #128 @ 0x80 8005f84: 0152 lsls r2, r2, #5 8005f86: 4293 cmp r3, r2 8005f88: d100 bne.n 8005f8c 8005f8a: e088 b.n 800609e 8005f8c: 2280 movs r2, #128 @ 0x80 8005f8e: 0152 lsls r2, r2, #5 8005f90: 4293 cmp r3, r2 8005f92: d900 bls.n 8005f96 8005f94: e07e b.n 8006094 8005f96: 2b70 cmp r3, #112 @ 0x70 8005f98: d018 beq.n 8005fcc 8005f9a: d900 bls.n 8005f9e 8005f9c: e07a b.n 8006094 8005f9e: 2b60 cmp r3, #96 @ 0x60 8005fa0: d04f beq.n 8006042 8005fa2: d900 bls.n 8005fa6 8005fa4: e076 b.n 8006094 8005fa6: 2b50 cmp r3, #80 @ 0x50 8005fa8: d03b beq.n 8006022 8005faa: d900 bls.n 8005fae 8005fac: e072 b.n 8006094 8005fae: 2b40 cmp r3, #64 @ 0x40 8005fb0: d057 beq.n 8006062 8005fb2: d900 bls.n 8005fb6 8005fb4: e06e b.n 8006094 8005fb6: 2b30 cmp r3, #48 @ 0x30 8005fb8: d063 beq.n 8006082 8005fba: d86b bhi.n 8006094 8005fbc: 2b20 cmp r3, #32 8005fbe: d060 beq.n 8006082 8005fc0: d868 bhi.n 8006094 8005fc2: 2b00 cmp r3, #0 8005fc4: d05d beq.n 8006082 8005fc6: 2b10 cmp r3, #16 8005fc8: d05b beq.n 8006082 8005fca: e063 b.n 8006094 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8005fcc: 687b ldr r3, [r7, #4] 8005fce: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8005fd0: 683b ldr r3, [r7, #0] 8005fd2: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8005fd4: 683b ldr r3, [r7, #0] 8005fd6: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8005fd8: 683b ldr r3, [r7, #0] 8005fda: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 8005fdc: f000 fc28 bl 8006830 /* Select the External clock mode1 and the ETRF trigger */ tmpsmcr = htim->Instance->SMCR; 8005fe0: 687b ldr r3, [r7, #4] 8005fe2: 681b ldr r3, [r3, #0] 8005fe4: 689b ldr r3, [r3, #8] 8005fe6: 60bb str r3, [r7, #8] tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); 8005fe8: 68bb ldr r3, [r7, #8] 8005fea: 2277 movs r2, #119 @ 0x77 8005fec: 4313 orrs r3, r2 8005fee: 60bb str r3, [r7, #8] /* Write to TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8005ff0: 687b ldr r3, [r7, #4] 8005ff2: 681b ldr r3, [r3, #0] 8005ff4: 68ba ldr r2, [r7, #8] 8005ff6: 609a str r2, [r3, #8] break; 8005ff8: e052 b.n 80060a0 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); /* Configure the ETR Clock source */ TIM_ETR_SetConfig(htim->Instance, 8005ffa: 687b ldr r3, [r7, #4] 8005ffc: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPrescaler, 8005ffe: 683b ldr r3, [r7, #0] 8006000: 6899 ldr r1, [r3, #8] sClockSourceConfig->ClockPolarity, 8006002: 683b ldr r3, [r7, #0] 8006004: 685a ldr r2, [r3, #4] sClockSourceConfig->ClockFilter); 8006006: 683b ldr r3, [r7, #0] 8006008: 68db ldr r3, [r3, #12] TIM_ETR_SetConfig(htim->Instance, 800600a: f000 fc11 bl 8006830 /* Enable the External clock mode2 */ htim->Instance->SMCR |= TIM_SMCR_ECE; 800600e: 687b ldr r3, [r7, #4] 8006010: 681b ldr r3, [r3, #0] 8006012: 689a ldr r2, [r3, #8] 8006014: 687b ldr r3, [r7, #4] 8006016: 681b ldr r3, [r3, #0] 8006018: 2180 movs r1, #128 @ 0x80 800601a: 01c9 lsls r1, r1, #7 800601c: 430a orrs r2, r1 800601e: 609a str r2, [r3, #8] break; 8006020: e03e b.n 80060a0 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8006022: 687b ldr r3, [r7, #4] 8006024: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8006026: 683b ldr r3, [r7, #0] 8006028: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800602a: 683b ldr r3, [r7, #0] 800602c: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800602e: 001a movs r2, r3 8006030: f000 fb82 bl 8006738 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); 8006034: 687b ldr r3, [r7, #4] 8006036: 681b ldr r3, [r3, #0] 8006038: 2150 movs r1, #80 @ 0x50 800603a: 0018 movs r0, r3 800603c: f000 fbdc bl 80067f8 break; 8006040: e02e b.n 80060a0 /* Check TI2 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI2_ConfigInputStage(htim->Instance, 8006042: 687b ldr r3, [r7, #4] 8006044: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8006046: 683b ldr r3, [r7, #0] 8006048: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800604a: 683b ldr r3, [r7, #0] 800604c: 68db ldr r3, [r3, #12] TIM_TI2_ConfigInputStage(htim->Instance, 800604e: 001a movs r2, r3 8006050: f000 fba0 bl 8006794 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); 8006054: 687b ldr r3, [r7, #4] 8006056: 681b ldr r3, [r3, #0] 8006058: 2160 movs r1, #96 @ 0x60 800605a: 0018 movs r0, r3 800605c: f000 fbcc bl 80067f8 break; 8006060: e01e b.n 80060a0 /* Check TI1 input conditioning related parameters */ assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); TIM_TI1_ConfigInputStage(htim->Instance, 8006062: 687b ldr r3, [r7, #4] 8006064: 6818 ldr r0, [r3, #0] sClockSourceConfig->ClockPolarity, 8006066: 683b ldr r3, [r7, #0] 8006068: 6859 ldr r1, [r3, #4] sClockSourceConfig->ClockFilter); 800606a: 683b ldr r3, [r7, #0] 800606c: 68db ldr r3, [r3, #12] TIM_TI1_ConfigInputStage(htim->Instance, 800606e: 001a movs r2, r3 8006070: f000 fb62 bl 8006738 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); 8006074: 687b ldr r3, [r7, #4] 8006076: 681b ldr r3, [r3, #0] 8006078: 2140 movs r1, #64 @ 0x40 800607a: 0018 movs r0, r3 800607c: f000 fbbc bl 80067f8 break; 8006080: e00e b.n 80060a0 case TIM_CLOCKSOURCE_ITR3: { /* Check whether or not the timer instance supports internal trigger input */ assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance)); TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); 8006082: 687b ldr r3, [r7, #4] 8006084: 681a ldr r2, [r3, #0] 8006086: 683b ldr r3, [r7, #0] 8006088: 681b ldr r3, [r3, #0] 800608a: 0019 movs r1, r3 800608c: 0010 movs r0, r2 800608e: f000 fbb3 bl 80067f8 break; 8006092: e005 b.n 80060a0 } default: status = HAL_ERROR; 8006094: 230f movs r3, #15 8006096: 18fb adds r3, r7, r3 8006098: 2201 movs r2, #1 800609a: 701a strb r2, [r3, #0] break; 800609c: e000 b.n 80060a0 break; 800609e: 46c0 nop @ (mov r8, r8) } htim->State = HAL_TIM_STATE_READY; 80060a0: 687b ldr r3, [r7, #4] 80060a2: 223d movs r2, #61 @ 0x3d 80060a4: 2101 movs r1, #1 80060a6: 5499 strb r1, [r3, r2] __HAL_UNLOCK(htim); 80060a8: 687b ldr r3, [r7, #4] 80060aa: 223c movs r2, #60 @ 0x3c 80060ac: 2100 movs r1, #0 80060ae: 5499 strb r1, [r3, r2] return status; 80060b0: 230f movs r3, #15 80060b2: 18fb adds r3, r7, r3 80060b4: 781b ldrb r3, [r3, #0] } 80060b6: 0018 movs r0, r3 80060b8: 46bd mov sp, r7 80060ba: b004 add sp, #16 80060bc: bd80 pop {r7, pc} 80060be: 46c0 nop @ (mov r8, r8) 80060c0: ffceff88 .word 0xffceff88 80060c4: ffff00ff .word 0xffff00ff 080060c8 : * @brief Output Compare callback in non-blocking mode * @param htim TIM OC handle * @retval None */ __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) { 80060c8: b580 push {r7, lr} 80060ca: b082 sub sp, #8 80060cc: af00 add r7, sp, #0 80060ce: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file */ } 80060d0: 46c0 nop @ (mov r8, r8) 80060d2: 46bd mov sp, r7 80060d4: b002 add sp, #8 80060d6: bd80 pop {r7, pc} 080060d8 : * @brief Input Capture callback in non-blocking mode * @param htim TIM IC handle * @retval None */ __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) { 80060d8: b580 push {r7, lr} 80060da: b082 sub sp, #8 80060dc: af00 add r7, sp, #0 80060de: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_IC_CaptureCallback could be implemented in the user file */ } 80060e0: 46c0 nop @ (mov r8, r8) 80060e2: 46bd mov sp, r7 80060e4: b002 add sp, #8 80060e6: bd80 pop {r7, pc} 080060e8 : * @brief PWM Pulse finished callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) { 80060e8: b580 push {r7, lr} 80060ea: b082 sub sp, #8 80060ec: af00 add r7, sp, #0 80060ee: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file */ } 80060f0: 46c0 nop @ (mov r8, r8) 80060f2: 46bd mov sp, r7 80060f4: b002 add sp, #8 80060f6: bd80 pop {r7, pc} 080060f8 : * @brief Hall Trigger detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) { 80060f8: b580 push {r7, lr} 80060fa: b082 sub sp, #8 80060fc: af00 add r7, sp, #0 80060fe: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIM_TriggerCallback could be implemented in the user file */ } 8006100: 46c0 nop @ (mov r8, r8) 8006102: 46bd mov sp, r7 8006104: b002 add sp, #8 8006106: bd80 pop {r7, pc} 08006108 : * @param TIMx TIM peripheral * @param Structure TIM Base configuration structure * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) { 8006108: b580 push {r7, lr} 800610a: b084 sub sp, #16 800610c: af00 add r7, sp, #0 800610e: 6078 str r0, [r7, #4] 8006110: 6039 str r1, [r7, #0] uint32_t tmpcr1; tmpcr1 = TIMx->CR1; 8006112: 687b ldr r3, [r7, #4] 8006114: 681b ldr r3, [r3, #0] 8006116: 60fb str r3, [r7, #12] /* Set TIM Time Base Unit parameters ---------------------------------------*/ if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 8006118: 687b ldr r3, [r7, #4] 800611a: 4a33 ldr r2, [pc, #204] @ (80061e8 ) 800611c: 4293 cmp r3, r2 800611e: d008 beq.n 8006132 8006120: 687a ldr r2, [r7, #4] 8006122: 2380 movs r3, #128 @ 0x80 8006124: 05db lsls r3, r3, #23 8006126: 429a cmp r2, r3 8006128: d003 beq.n 8006132 800612a: 687b ldr r3, [r7, #4] 800612c: 4a2f ldr r2, [pc, #188] @ (80061ec ) 800612e: 4293 cmp r3, r2 8006130: d108 bne.n 8006144 { /* Select the Counter Mode */ tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); 8006132: 68fb ldr r3, [r7, #12] 8006134: 2270 movs r2, #112 @ 0x70 8006136: 4393 bics r3, r2 8006138: 60fb str r3, [r7, #12] tmpcr1 |= Structure->CounterMode; 800613a: 683b ldr r3, [r7, #0] 800613c: 685b ldr r3, [r3, #4] 800613e: 68fa ldr r2, [r7, #12] 8006140: 4313 orrs r3, r2 8006142: 60fb str r3, [r7, #12] } if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 8006144: 687b ldr r3, [r7, #4] 8006146: 4a28 ldr r2, [pc, #160] @ (80061e8 ) 8006148: 4293 cmp r3, r2 800614a: d014 beq.n 8006176 800614c: 687a ldr r2, [r7, #4] 800614e: 2380 movs r3, #128 @ 0x80 8006150: 05db lsls r3, r3, #23 8006152: 429a cmp r2, r3 8006154: d00f beq.n 8006176 8006156: 687b ldr r3, [r7, #4] 8006158: 4a24 ldr r2, [pc, #144] @ (80061ec ) 800615a: 4293 cmp r3, r2 800615c: d00b beq.n 8006176 800615e: 687b ldr r3, [r7, #4] 8006160: 4a23 ldr r2, [pc, #140] @ (80061f0 ) 8006162: 4293 cmp r3, r2 8006164: d007 beq.n 8006176 8006166: 687b ldr r3, [r7, #4] 8006168: 4a22 ldr r2, [pc, #136] @ (80061f4 ) 800616a: 4293 cmp r3, r2 800616c: d003 beq.n 8006176 800616e: 687b ldr r3, [r7, #4] 8006170: 4a21 ldr r2, [pc, #132] @ (80061f8 ) 8006172: 4293 cmp r3, r2 8006174: d108 bne.n 8006188 { /* Set the clock division */ tmpcr1 &= ~TIM_CR1_CKD; 8006176: 68fb ldr r3, [r7, #12] 8006178: 4a20 ldr r2, [pc, #128] @ (80061fc ) 800617a: 4013 ands r3, r2 800617c: 60fb str r3, [r7, #12] tmpcr1 |= (uint32_t)Structure->ClockDivision; 800617e: 683b ldr r3, [r7, #0] 8006180: 68db ldr r3, [r3, #12] 8006182: 68fa ldr r2, [r7, #12] 8006184: 4313 orrs r3, r2 8006186: 60fb str r3, [r7, #12] } /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); 8006188: 68fb ldr r3, [r7, #12] 800618a: 2280 movs r2, #128 @ 0x80 800618c: 4393 bics r3, r2 800618e: 001a movs r2, r3 8006190: 683b ldr r3, [r7, #0] 8006192: 695b ldr r3, [r3, #20] 8006194: 4313 orrs r3, r2 8006196: 60fb str r3, [r7, #12] /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; 8006198: 683b ldr r3, [r7, #0] 800619a: 689a ldr r2, [r3, #8] 800619c: 687b ldr r3, [r7, #4] 800619e: 62da str r2, [r3, #44] @ 0x2c /* Set the Prescaler value */ TIMx->PSC = Structure->Prescaler; 80061a0: 683b ldr r3, [r7, #0] 80061a2: 681a ldr r2, [r3, #0] 80061a4: 687b ldr r3, [r7, #4] 80061a6: 629a str r2, [r3, #40] @ 0x28 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 80061a8: 687b ldr r3, [r7, #4] 80061aa: 4a0f ldr r2, [pc, #60] @ (80061e8 ) 80061ac: 4293 cmp r3, r2 80061ae: d007 beq.n 80061c0 80061b0: 687b ldr r3, [r7, #4] 80061b2: 4a10 ldr r2, [pc, #64] @ (80061f4 ) 80061b4: 4293 cmp r3, r2 80061b6: d003 beq.n 80061c0 80061b8: 687b ldr r3, [r7, #4] 80061ba: 4a0f ldr r2, [pc, #60] @ (80061f8 ) 80061bc: 4293 cmp r3, r2 80061be: d103 bne.n 80061c8 { /* Set the Repetition Counter value */ TIMx->RCR = Structure->RepetitionCounter; 80061c0: 683b ldr r3, [r7, #0] 80061c2: 691a ldr r2, [r3, #16] 80061c4: 687b ldr r3, [r7, #4] 80061c6: 631a str r2, [r3, #48] @ 0x30 } /* Disable Update Event (UEV) with Update Generation (UG) by changing Update Request Source (URS) to avoid Update flag (UIF) */ SET_BIT(TIMx->CR1, TIM_CR1_URS); 80061c8: 687b ldr r3, [r7, #4] 80061ca: 681b ldr r3, [r3, #0] 80061cc: 2204 movs r2, #4 80061ce: 431a orrs r2, r3 80061d0: 687b ldr r3, [r7, #4] 80061d2: 601a str r2, [r3, #0] /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; 80061d4: 687b ldr r3, [r7, #4] 80061d6: 2201 movs r2, #1 80061d8: 615a str r2, [r3, #20] TIMx->CR1 = tmpcr1; 80061da: 687b ldr r3, [r7, #4] 80061dc: 68fa ldr r2, [r7, #12] 80061de: 601a str r2, [r3, #0] } 80061e0: 46c0 nop @ (mov r8, r8) 80061e2: 46bd mov sp, r7 80061e4: b004 add sp, #16 80061e6: bd80 pop {r7, pc} 80061e8: 40012c00 .word 0x40012c00 80061ec: 40000400 .word 0x40000400 80061f0: 40002000 .word 0x40002000 80061f4: 40014400 .word 0x40014400 80061f8: 40014800 .word 0x40014800 80061fc: fffffcff .word 0xfffffcff 08006200 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8006200: b580 push {r7, lr} 8006202: b086 sub sp, #24 8006204: af00 add r7, sp, #0 8006206: 6078 str r0, [r7, #4] 8006208: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800620a: 687b ldr r3, [r7, #4] 800620c: 6a1b ldr r3, [r3, #32] 800620e: 617b str r3, [r7, #20] /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; 8006210: 687b ldr r3, [r7, #4] 8006212: 6a1b ldr r3, [r3, #32] 8006214: 2201 movs r2, #1 8006216: 4393 bics r3, r2 8006218: 001a movs r2, r3 800621a: 687b ldr r3, [r7, #4] 800621c: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800621e: 687b ldr r3, [r7, #4] 8006220: 685b ldr r3, [r3, #4] 8006222: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8006224: 687b ldr r3, [r7, #4] 8006226: 699b ldr r3, [r3, #24] 8006228: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~TIM_CCMR1_OC1M; 800622a: 68fb ldr r3, [r7, #12] 800622c: 4a2e ldr r2, [pc, #184] @ (80062e8 ) 800622e: 4013 ands r3, r2 8006230: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC1S; 8006232: 68fb ldr r3, [r7, #12] 8006234: 2203 movs r2, #3 8006236: 4393 bics r3, r2 8006238: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 800623a: 683b ldr r3, [r7, #0] 800623c: 681b ldr r3, [r3, #0] 800623e: 68fa ldr r2, [r7, #12] 8006240: 4313 orrs r3, r2 8006242: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC1P; 8006244: 697b ldr r3, [r7, #20] 8006246: 2202 movs r2, #2 8006248: 4393 bics r3, r2 800624a: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= OC_Config->OCPolarity; 800624c: 683b ldr r3, [r7, #0] 800624e: 689b ldr r3, [r3, #8] 8006250: 697a ldr r2, [r7, #20] 8006252: 4313 orrs r3, r2 8006254: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) 8006256: 687b ldr r3, [r7, #4] 8006258: 4a24 ldr r2, [pc, #144] @ (80062ec ) 800625a: 4293 cmp r3, r2 800625c: d007 beq.n 800626e 800625e: 687b ldr r3, [r7, #4] 8006260: 4a23 ldr r2, [pc, #140] @ (80062f0 ) 8006262: 4293 cmp r3, r2 8006264: d003 beq.n 800626e 8006266: 687b ldr r3, [r7, #4] 8006268: 4a22 ldr r2, [pc, #136] @ (80062f4 ) 800626a: 4293 cmp r3, r2 800626c: d10c bne.n 8006288 { /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; 800626e: 697b ldr r3, [r7, #20] 8006270: 2208 movs r2, #8 8006272: 4393 bics r3, r2 8006274: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; 8006276: 683b ldr r3, [r7, #0] 8006278: 68db ldr r3, [r3, #12] 800627a: 697a ldr r2, [r7, #20] 800627c: 4313 orrs r3, r2 800627e: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC1NE; 8006280: 697b ldr r3, [r7, #20] 8006282: 2204 movs r2, #4 8006284: 4393 bics r3, r2 8006286: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006288: 687b ldr r3, [r7, #4] 800628a: 4a18 ldr r2, [pc, #96] @ (80062ec ) 800628c: 4293 cmp r3, r2 800628e: d007 beq.n 80062a0 8006290: 687b ldr r3, [r7, #4] 8006292: 4a17 ldr r2, [pc, #92] @ (80062f0 ) 8006294: 4293 cmp r3, r2 8006296: d003 beq.n 80062a0 8006298: 687b ldr r3, [r7, #4] 800629a: 4a16 ldr r2, [pc, #88] @ (80062f4 ) 800629c: 4293 cmp r3, r2 800629e: d111 bne.n 80062c4 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS1; 80062a0: 693b ldr r3, [r7, #16] 80062a2: 4a15 ldr r2, [pc, #84] @ (80062f8 ) 80062a4: 4013 ands r3, r2 80062a6: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS1N; 80062a8: 693b ldr r3, [r7, #16] 80062aa: 4a14 ldr r2, [pc, #80] @ (80062fc ) 80062ac: 4013 ands r3, r2 80062ae: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= OC_Config->OCIdleState; 80062b0: 683b ldr r3, [r7, #0] 80062b2: 695b ldr r3, [r3, #20] 80062b4: 693a ldr r2, [r7, #16] 80062b6: 4313 orrs r3, r2 80062b8: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= OC_Config->OCNIdleState; 80062ba: 683b ldr r3, [r7, #0] 80062bc: 699b ldr r3, [r3, #24] 80062be: 693a ldr r2, [r7, #16] 80062c0: 4313 orrs r3, r2 80062c2: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80062c4: 687b ldr r3, [r7, #4] 80062c6: 693a ldr r2, [r7, #16] 80062c8: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80062ca: 687b ldr r3, [r7, #4] 80062cc: 68fa ldr r2, [r7, #12] 80062ce: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR1 = OC_Config->Pulse; 80062d0: 683b ldr r3, [r7, #0] 80062d2: 685a ldr r2, [r3, #4] 80062d4: 687b ldr r3, [r7, #4] 80062d6: 635a str r2, [r3, #52] @ 0x34 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80062d8: 687b ldr r3, [r7, #4] 80062da: 697a ldr r2, [r7, #20] 80062dc: 621a str r2, [r3, #32] } 80062de: 46c0 nop @ (mov r8, r8) 80062e0: 46bd mov sp, r7 80062e2: b006 add sp, #24 80062e4: bd80 pop {r7, pc} 80062e6: 46c0 nop @ (mov r8, r8) 80062e8: fffeff8f .word 0xfffeff8f 80062ec: 40012c00 .word 0x40012c00 80062f0: 40014400 .word 0x40014400 80062f4: 40014800 .word 0x40014800 80062f8: fffffeff .word 0xfffffeff 80062fc: fffffdff .word 0xfffffdff 08006300 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8006300: b580 push {r7, lr} 8006302: b086 sub sp, #24 8006304: af00 add r7, sp, #0 8006306: 6078 str r0, [r7, #4] 8006308: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800630a: 687b ldr r3, [r7, #4] 800630c: 6a1b ldr r3, [r3, #32] 800630e: 617b str r3, [r7, #20] /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; 8006310: 687b ldr r3, [r7, #4] 8006312: 6a1b ldr r3, [r3, #32] 8006314: 2210 movs r2, #16 8006316: 4393 bics r3, r2 8006318: 001a movs r2, r3 800631a: 687b ldr r3, [r7, #4] 800631c: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800631e: 687b ldr r3, [r7, #4] 8006320: 685b ldr r3, [r3, #4] 8006322: 613b str r3, [r7, #16] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR1; 8006324: 687b ldr r3, [r7, #4] 8006326: 699b ldr r3, [r3, #24] 8006328: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR1_OC2M; 800632a: 68fb ldr r3, [r7, #12] 800632c: 4a2c ldr r2, [pc, #176] @ (80063e0 ) 800632e: 4013 ands r3, r2 8006330: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR1_CC2S; 8006332: 68fb ldr r3, [r7, #12] 8006334: 4a2b ldr r2, [pc, #172] @ (80063e4 ) 8006336: 4013 ands r3, r2 8006338: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 800633a: 683b ldr r3, [r7, #0] 800633c: 681b ldr r3, [r3, #0] 800633e: 021b lsls r3, r3, #8 8006340: 68fa ldr r2, [r7, #12] 8006342: 4313 orrs r3, r2 8006344: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC2P; 8006346: 697b ldr r3, [r7, #20] 8006348: 2220 movs r2, #32 800634a: 4393 bics r3, r2 800634c: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 4U); 800634e: 683b ldr r3, [r7, #0] 8006350: 689b ldr r3, [r3, #8] 8006352: 011b lsls r3, r3, #4 8006354: 697a ldr r2, [r7, #20] 8006356: 4313 orrs r3, r2 8006358: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) 800635a: 687b ldr r3, [r7, #4] 800635c: 4a22 ldr r2, [pc, #136] @ (80063e8 ) 800635e: 4293 cmp r3, r2 8006360: d10d bne.n 800637e { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; 8006362: 697b ldr r3, [r7, #20] 8006364: 2280 movs r2, #128 @ 0x80 8006366: 4393 bics r3, r2 8006368: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); 800636a: 683b ldr r3, [r7, #0] 800636c: 68db ldr r3, [r3, #12] 800636e: 011b lsls r3, r3, #4 8006370: 697a ldr r2, [r7, #20] 8006372: 4313 orrs r3, r2 8006374: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC2NE; 8006376: 697b ldr r3, [r7, #20] 8006378: 2240 movs r2, #64 @ 0x40 800637a: 4393 bics r3, r2 800637c: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 800637e: 687b ldr r3, [r7, #4] 8006380: 4a19 ldr r2, [pc, #100] @ (80063e8 ) 8006382: 4293 cmp r3, r2 8006384: d007 beq.n 8006396 8006386: 687b ldr r3, [r7, #4] 8006388: 4a18 ldr r2, [pc, #96] @ (80063ec ) 800638a: 4293 cmp r3, r2 800638c: d003 beq.n 8006396 800638e: 687b ldr r3, [r7, #4] 8006390: 4a17 ldr r2, [pc, #92] @ (80063f0 ) 8006392: 4293 cmp r3, r2 8006394: d113 bne.n 80063be /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS2; 8006396: 693b ldr r3, [r7, #16] 8006398: 4a16 ldr r2, [pc, #88] @ (80063f4 ) 800639a: 4013 ands r3, r2 800639c: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS2N; 800639e: 693b ldr r3, [r7, #16] 80063a0: 4a15 ldr r2, [pc, #84] @ (80063f8 ) 80063a2: 4013 ands r3, r2 80063a4: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 2U); 80063a6: 683b ldr r3, [r7, #0] 80063a8: 695b ldr r3, [r3, #20] 80063aa: 009b lsls r3, r3, #2 80063ac: 693a ldr r2, [r7, #16] 80063ae: 4313 orrs r3, r2 80063b0: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 2U); 80063b2: 683b ldr r3, [r7, #0] 80063b4: 699b ldr r3, [r3, #24] 80063b6: 009b lsls r3, r3, #2 80063b8: 693a ldr r2, [r7, #16] 80063ba: 4313 orrs r3, r2 80063bc: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80063be: 687b ldr r3, [r7, #4] 80063c0: 693a ldr r2, [r7, #16] 80063c2: 605a str r2, [r3, #4] /* Write to TIMx CCMR1 */ TIMx->CCMR1 = tmpccmrx; 80063c4: 687b ldr r3, [r7, #4] 80063c6: 68fa ldr r2, [r7, #12] 80063c8: 619a str r2, [r3, #24] /* Set the Capture Compare Register value */ TIMx->CCR2 = OC_Config->Pulse; 80063ca: 683b ldr r3, [r7, #0] 80063cc: 685a ldr r2, [r3, #4] 80063ce: 687b ldr r3, [r7, #4] 80063d0: 639a str r2, [r3, #56] @ 0x38 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80063d2: 687b ldr r3, [r7, #4] 80063d4: 697a ldr r2, [r7, #20] 80063d6: 621a str r2, [r3, #32] } 80063d8: 46c0 nop @ (mov r8, r8) 80063da: 46bd mov sp, r7 80063dc: b006 add sp, #24 80063de: bd80 pop {r7, pc} 80063e0: feff8fff .word 0xfeff8fff 80063e4: fffffcff .word 0xfffffcff 80063e8: 40012c00 .word 0x40012c00 80063ec: 40014400 .word 0x40014400 80063f0: 40014800 .word 0x40014800 80063f4: fffffbff .word 0xfffffbff 80063f8: fffff7ff .word 0xfffff7ff 080063fc : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80063fc: b580 push {r7, lr} 80063fe: b086 sub sp, #24 8006400: af00 add r7, sp, #0 8006402: 6078 str r0, [r7, #4] 8006404: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8006406: 687b ldr r3, [r7, #4] 8006408: 6a1b ldr r3, [r3, #32] 800640a: 617b str r3, [r7, #20] /* Disable the Channel 3: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; 800640c: 687b ldr r3, [r7, #4] 800640e: 6a1b ldr r3, [r3, #32] 8006410: 4a31 ldr r2, [pc, #196] @ (80064d8 ) 8006412: 401a ands r2, r3 8006414: 687b ldr r3, [r7, #4] 8006416: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8006418: 687b ldr r3, [r7, #4] 800641a: 685b ldr r3, [r3, #4] 800641c: 613b str r3, [r7, #16] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 800641e: 687b ldr r3, [r7, #4] 8006420: 69db ldr r3, [r3, #28] 8006422: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC3M; 8006424: 68fb ldr r3, [r7, #12] 8006426: 4a2d ldr r2, [pc, #180] @ (80064dc ) 8006428: 4013 ands r3, r2 800642a: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC3S; 800642c: 68fb ldr r3, [r7, #12] 800642e: 2203 movs r2, #3 8006430: 4393 bics r3, r2 8006432: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 8006434: 683b ldr r3, [r7, #0] 8006436: 681b ldr r3, [r3, #0] 8006438: 68fa ldr r2, [r7, #12] 800643a: 4313 orrs r3, r2 800643c: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC3P; 800643e: 697b ldr r3, [r7, #20] 8006440: 4a27 ldr r2, [pc, #156] @ (80064e0 ) 8006442: 4013 ands r3, r2 8006444: 617b str r3, [r7, #20] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 8U); 8006446: 683b ldr r3, [r7, #0] 8006448: 689b ldr r3, [r3, #8] 800644a: 021b lsls r3, r3, #8 800644c: 697a ldr r2, [r7, #20] 800644e: 4313 orrs r3, r2 8006450: 617b str r3, [r7, #20] if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) 8006452: 687b ldr r3, [r7, #4] 8006454: 4a23 ldr r2, [pc, #140] @ (80064e4 ) 8006456: 4293 cmp r3, r2 8006458: d10d bne.n 8006476 { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; 800645a: 697b ldr r3, [r7, #20] 800645c: 4a22 ldr r2, [pc, #136] @ (80064e8 ) 800645e: 4013 ands r3, r2 8006460: 617b str r3, [r7, #20] /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); 8006462: 683b ldr r3, [r7, #0] 8006464: 68db ldr r3, [r3, #12] 8006466: 021b lsls r3, r3, #8 8006468: 697a ldr r2, [r7, #20] 800646a: 4313 orrs r3, r2 800646c: 617b str r3, [r7, #20] /* Reset the Output N State */ tmpccer &= ~TIM_CCER_CC3NE; 800646e: 697b ldr r3, [r7, #20] 8006470: 4a1e ldr r2, [pc, #120] @ (80064ec ) 8006472: 4013 ands r3, r2 8006474: 617b str r3, [r7, #20] } if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006476: 687b ldr r3, [r7, #4] 8006478: 4a1a ldr r2, [pc, #104] @ (80064e4 ) 800647a: 4293 cmp r3, r2 800647c: d007 beq.n 800648e 800647e: 687b ldr r3, [r7, #4] 8006480: 4a1b ldr r2, [pc, #108] @ (80064f0 ) 8006482: 4293 cmp r3, r2 8006484: d003 beq.n 800648e 8006486: 687b ldr r3, [r7, #4] 8006488: 4a1a ldr r2, [pc, #104] @ (80064f4 ) 800648a: 4293 cmp r3, r2 800648c: d113 bne.n 80064b6 /* Check parameters */ assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare and Output Compare N IDLE State */ tmpcr2 &= ~TIM_CR2_OIS3; 800648e: 693b ldr r3, [r7, #16] 8006490: 4a19 ldr r2, [pc, #100] @ (80064f8 ) 8006492: 4013 ands r3, r2 8006494: 613b str r3, [r7, #16] tmpcr2 &= ~TIM_CR2_OIS3N; 8006496: 693b ldr r3, [r7, #16] 8006498: 4a18 ldr r2, [pc, #96] @ (80064fc ) 800649a: 4013 ands r3, r2 800649c: 613b str r3, [r7, #16] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 4U); 800649e: 683b ldr r3, [r7, #0] 80064a0: 695b ldr r3, [r3, #20] 80064a2: 011b lsls r3, r3, #4 80064a4: 693a ldr r2, [r7, #16] 80064a6: 4313 orrs r3, r2 80064a8: 613b str r3, [r7, #16] /* Set the Output N Idle state */ tmpcr2 |= (OC_Config->OCNIdleState << 4U); 80064aa: 683b ldr r3, [r7, #0] 80064ac: 699b ldr r3, [r3, #24] 80064ae: 011b lsls r3, r3, #4 80064b0: 693a ldr r2, [r7, #16] 80064b2: 4313 orrs r3, r2 80064b4: 613b str r3, [r7, #16] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80064b6: 687b ldr r3, [r7, #4] 80064b8: 693a ldr r2, [r7, #16] 80064ba: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 80064bc: 687b ldr r3, [r7, #4] 80064be: 68fa ldr r2, [r7, #12] 80064c0: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR3 = OC_Config->Pulse; 80064c2: 683b ldr r3, [r7, #0] 80064c4: 685a ldr r2, [r3, #4] 80064c6: 687b ldr r3, [r7, #4] 80064c8: 63da str r2, [r3, #60] @ 0x3c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 80064ca: 687b ldr r3, [r7, #4] 80064cc: 697a ldr r2, [r7, #20] 80064ce: 621a str r2, [r3, #32] } 80064d0: 46c0 nop @ (mov r8, r8) 80064d2: 46bd mov sp, r7 80064d4: b006 add sp, #24 80064d6: bd80 pop {r7, pc} 80064d8: fffffeff .word 0xfffffeff 80064dc: fffeff8f .word 0xfffeff8f 80064e0: fffffdff .word 0xfffffdff 80064e4: 40012c00 .word 0x40012c00 80064e8: fffff7ff .word 0xfffff7ff 80064ec: fffffbff .word 0xfffffbff 80064f0: 40014400 .word 0x40014400 80064f4: 40014800 .word 0x40014800 80064f8: ffffefff .word 0xffffefff 80064fc: ffffdfff .word 0xffffdfff 08006500 : * @param TIMx to select the TIM peripheral * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 8006500: b580 push {r7, lr} 8006502: b086 sub sp, #24 8006504: af00 add r7, sp, #0 8006506: 6078 str r0, [r7, #4] 8006508: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 800650a: 687b ldr r3, [r7, #4] 800650c: 6a1b ldr r3, [r3, #32] 800650e: 613b str r3, [r7, #16] /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; 8006510: 687b ldr r3, [r7, #4] 8006512: 6a1b ldr r3, [r3, #32] 8006514: 4a24 ldr r2, [pc, #144] @ (80065a8 ) 8006516: 401a ands r2, r3 8006518: 687b ldr r3, [r7, #4] 800651a: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 800651c: 687b ldr r3, [r7, #4] 800651e: 685b ldr r3, [r3, #4] 8006520: 617b str r3, [r7, #20] /* Get the TIMx CCMR2 register value */ tmpccmrx = TIMx->CCMR2; 8006522: 687b ldr r3, [r7, #4] 8006524: 69db ldr r3, [r3, #28] 8006526: 60fb str r3, [r7, #12] /* Reset the Output Compare mode and Capture/Compare selection Bits */ tmpccmrx &= ~TIM_CCMR2_OC4M; 8006528: 68fb ldr r3, [r7, #12] 800652a: 4a20 ldr r2, [pc, #128] @ (80065ac ) 800652c: 4013 ands r3, r2 800652e: 60fb str r3, [r7, #12] tmpccmrx &= ~TIM_CCMR2_CC4S; 8006530: 68fb ldr r3, [r7, #12] 8006532: 4a1f ldr r2, [pc, #124] @ (80065b0 ) 8006534: 4013 ands r3, r2 8006536: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 8006538: 683b ldr r3, [r7, #0] 800653a: 681b ldr r3, [r3, #0] 800653c: 021b lsls r3, r3, #8 800653e: 68fa ldr r2, [r7, #12] 8006540: 4313 orrs r3, r2 8006542: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC4P; 8006544: 693b ldr r3, [r7, #16] 8006546: 4a1b ldr r2, [pc, #108] @ (80065b4 ) 8006548: 4013 ands r3, r2 800654a: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 12U); 800654c: 683b ldr r3, [r7, #0] 800654e: 689b ldr r3, [r3, #8] 8006550: 031b lsls r3, r3, #12 8006552: 693a ldr r2, [r7, #16] 8006554: 4313 orrs r3, r2 8006556: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006558: 687b ldr r3, [r7, #4] 800655a: 4a17 ldr r2, [pc, #92] @ (80065b8 ) 800655c: 4293 cmp r3, r2 800655e: d007 beq.n 8006570 8006560: 687b ldr r3, [r7, #4] 8006562: 4a16 ldr r2, [pc, #88] @ (80065bc ) 8006564: 4293 cmp r3, r2 8006566: d003 beq.n 8006570 8006568: 687b ldr r3, [r7, #4] 800656a: 4a15 ldr r2, [pc, #84] @ (80065c0 ) 800656c: 4293 cmp r3, r2 800656e: d109 bne.n 8006584 { /* Check parameters */ assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS4; 8006570: 697b ldr r3, [r7, #20] 8006572: 4a14 ldr r2, [pc, #80] @ (80065c4 ) 8006574: 4013 ands r3, r2 8006576: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 6U); 8006578: 683b ldr r3, [r7, #0] 800657a: 695b ldr r3, [r3, #20] 800657c: 019b lsls r3, r3, #6 800657e: 697a ldr r2, [r7, #20] 8006580: 4313 orrs r3, r2 8006582: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8006584: 687b ldr r3, [r7, #4] 8006586: 697a ldr r2, [r7, #20] 8006588: 605a str r2, [r3, #4] /* Write to TIMx CCMR2 */ TIMx->CCMR2 = tmpccmrx; 800658a: 687b ldr r3, [r7, #4] 800658c: 68fa ldr r2, [r7, #12] 800658e: 61da str r2, [r3, #28] /* Set the Capture Compare Register value */ TIMx->CCR4 = OC_Config->Pulse; 8006590: 683b ldr r3, [r7, #0] 8006592: 685a ldr r2, [r3, #4] 8006594: 687b ldr r3, [r7, #4] 8006596: 641a str r2, [r3, #64] @ 0x40 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8006598: 687b ldr r3, [r7, #4] 800659a: 693a ldr r2, [r7, #16] 800659c: 621a str r2, [r3, #32] } 800659e: 46c0 nop @ (mov r8, r8) 80065a0: 46bd mov sp, r7 80065a2: b006 add sp, #24 80065a4: bd80 pop {r7, pc} 80065a6: 46c0 nop @ (mov r8, r8) 80065a8: ffffefff .word 0xffffefff 80065ac: feff8fff .word 0xfeff8fff 80065b0: fffffcff .word 0xfffffcff 80065b4: ffffdfff .word 0xffffdfff 80065b8: 40012c00 .word 0x40012c00 80065bc: 40014400 .word 0x40014400 80065c0: 40014800 .word 0x40014800 80065c4: ffffbfff .word 0xffffbfff 080065c8 : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 80065c8: b580 push {r7, lr} 80065ca: b086 sub sp, #24 80065cc: af00 add r7, sp, #0 80065ce: 6078 str r0, [r7, #4] 80065d0: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 80065d2: 687b ldr r3, [r7, #4] 80065d4: 6a1b ldr r3, [r3, #32] 80065d6: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC5E; 80065d8: 687b ldr r3, [r7, #4] 80065da: 6a1b ldr r3, [r3, #32] 80065dc: 4a21 ldr r2, [pc, #132] @ (8006664 ) 80065de: 401a ands r2, r3 80065e0: 687b ldr r3, [r7, #4] 80065e2: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 80065e4: 687b ldr r3, [r7, #4] 80065e6: 685b ldr r3, [r3, #4] 80065e8: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 80065ea: 687b ldr r3, [r7, #4] 80065ec: 6d5b ldr r3, [r3, #84] @ 0x54 80065ee: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC5M); 80065f0: 68fb ldr r3, [r7, #12] 80065f2: 4a1d ldr r2, [pc, #116] @ (8006668 ) 80065f4: 4013 ands r3, r2 80065f6: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= OC_Config->OCMode; 80065f8: 683b ldr r3, [r7, #0] 80065fa: 681b ldr r3, [r3, #0] 80065fc: 68fa ldr r2, [r7, #12] 80065fe: 4313 orrs r3, r2 8006600: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= ~TIM_CCER_CC5P; 8006602: 693b ldr r3, [r7, #16] 8006604: 4a19 ldr r2, [pc, #100] @ (800666c ) 8006606: 4013 ands r3, r2 8006608: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 16U); 800660a: 683b ldr r3, [r7, #0] 800660c: 689b ldr r3, [r3, #8] 800660e: 041b lsls r3, r3, #16 8006610: 693a ldr r2, [r7, #16] 8006612: 4313 orrs r3, r2 8006614: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 8006616: 687b ldr r3, [r7, #4] 8006618: 4a15 ldr r2, [pc, #84] @ (8006670 ) 800661a: 4293 cmp r3, r2 800661c: d007 beq.n 800662e 800661e: 687b ldr r3, [r7, #4] 8006620: 4a14 ldr r2, [pc, #80] @ (8006674 ) 8006622: 4293 cmp r3, r2 8006624: d003 beq.n 800662e 8006626: 687b ldr r3, [r7, #4] 8006628: 4a13 ldr r2, [pc, #76] @ (8006678 ) 800662a: 4293 cmp r3, r2 800662c: d109 bne.n 8006642 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS5; 800662e: 697b ldr r3, [r7, #20] 8006630: 4a0c ldr r2, [pc, #48] @ (8006664 ) 8006632: 4013 ands r3, r2 8006634: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 8U); 8006636: 683b ldr r3, [r7, #0] 8006638: 695b ldr r3, [r3, #20] 800663a: 021b lsls r3, r3, #8 800663c: 697a ldr r2, [r7, #20] 800663e: 4313 orrs r3, r2 8006640: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 8006642: 687b ldr r3, [r7, #4] 8006644: 697a ldr r2, [r7, #20] 8006646: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 8006648: 687b ldr r3, [r7, #4] 800664a: 68fa ldr r2, [r7, #12] 800664c: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR5 = OC_Config->Pulse; 800664e: 683b ldr r3, [r7, #0] 8006650: 685a ldr r2, [r3, #4] 8006652: 687b ldr r3, [r7, #4] 8006654: 659a str r2, [r3, #88] @ 0x58 /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 8006656: 687b ldr r3, [r7, #4] 8006658: 693a ldr r2, [r7, #16] 800665a: 621a str r2, [r3, #32] } 800665c: 46c0 nop @ (mov r8, r8) 800665e: 46bd mov sp, r7 8006660: b006 add sp, #24 8006662: bd80 pop {r7, pc} 8006664: fffeffff .word 0xfffeffff 8006668: fffeff8f .word 0xfffeff8f 800666c: fffdffff .word 0xfffdffff 8006670: 40012c00 .word 0x40012c00 8006674: 40014400 .word 0x40014400 8006678: 40014800 .word 0x40014800 0800667c : * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { 800667c: b580 push {r7, lr} 800667e: b086 sub sp, #24 8006680: af00 add r7, sp, #0 8006682: 6078 str r0, [r7, #4] 8006684: 6039 str r1, [r7, #0] uint32_t tmpccmrx; uint32_t tmpccer; uint32_t tmpcr2; /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; 8006686: 687b ldr r3, [r7, #4] 8006688: 6a1b ldr r3, [r3, #32] 800668a: 613b str r3, [r7, #16] /* Disable the output: Reset the CCxE Bit */ TIMx->CCER &= ~TIM_CCER_CC6E; 800668c: 687b ldr r3, [r7, #4] 800668e: 6a1b ldr r3, [r3, #32] 8006690: 4a22 ldr r2, [pc, #136] @ (800671c ) 8006692: 401a ands r2, r3 8006694: 687b ldr r3, [r7, #4] 8006696: 621a str r2, [r3, #32] /* Get the TIMx CR2 register value */ tmpcr2 = TIMx->CR2; 8006698: 687b ldr r3, [r7, #4] 800669a: 685b ldr r3, [r3, #4] 800669c: 617b str r3, [r7, #20] /* Get the TIMx CCMR1 register value */ tmpccmrx = TIMx->CCMR3; 800669e: 687b ldr r3, [r7, #4] 80066a0: 6d5b ldr r3, [r3, #84] @ 0x54 80066a2: 60fb str r3, [r7, #12] /* Reset the Output Compare Mode Bits */ tmpccmrx &= ~(TIM_CCMR3_OC6M); 80066a4: 68fb ldr r3, [r7, #12] 80066a6: 4a1e ldr r2, [pc, #120] @ (8006720 ) 80066a8: 4013 ands r3, r2 80066aa: 60fb str r3, [r7, #12] /* Select the Output Compare Mode */ tmpccmrx |= (OC_Config->OCMode << 8U); 80066ac: 683b ldr r3, [r7, #0] 80066ae: 681b ldr r3, [r3, #0] 80066b0: 021b lsls r3, r3, #8 80066b2: 68fa ldr r2, [r7, #12] 80066b4: 4313 orrs r3, r2 80066b6: 60fb str r3, [r7, #12] /* Reset the Output Polarity level */ tmpccer &= (uint32_t)~TIM_CCER_CC6P; 80066b8: 693b ldr r3, [r7, #16] 80066ba: 4a1a ldr r2, [pc, #104] @ (8006724 ) 80066bc: 4013 ands r3, r2 80066be: 613b str r3, [r7, #16] /* Set the Output Compare Polarity */ tmpccer |= (OC_Config->OCPolarity << 20U); 80066c0: 683b ldr r3, [r7, #0] 80066c2: 689b ldr r3, [r3, #8] 80066c4: 051b lsls r3, r3, #20 80066c6: 693a ldr r2, [r7, #16] 80066c8: 4313 orrs r3, r2 80066ca: 613b str r3, [r7, #16] if (IS_TIM_BREAK_INSTANCE(TIMx)) 80066cc: 687b ldr r3, [r7, #4] 80066ce: 4a16 ldr r2, [pc, #88] @ (8006728 ) 80066d0: 4293 cmp r3, r2 80066d2: d007 beq.n 80066e4 80066d4: 687b ldr r3, [r7, #4] 80066d6: 4a15 ldr r2, [pc, #84] @ (800672c ) 80066d8: 4293 cmp r3, r2 80066da: d003 beq.n 80066e4 80066dc: 687b ldr r3, [r7, #4] 80066de: 4a14 ldr r2, [pc, #80] @ (8006730 ) 80066e0: 4293 cmp r3, r2 80066e2: d109 bne.n 80066f8 { /* Reset the Output Compare IDLE State */ tmpcr2 &= ~TIM_CR2_OIS6; 80066e4: 697b ldr r3, [r7, #20] 80066e6: 4a13 ldr r2, [pc, #76] @ (8006734 ) 80066e8: 4013 ands r3, r2 80066ea: 617b str r3, [r7, #20] /* Set the Output Idle state */ tmpcr2 |= (OC_Config->OCIdleState << 10U); 80066ec: 683b ldr r3, [r7, #0] 80066ee: 695b ldr r3, [r3, #20] 80066f0: 029b lsls r3, r3, #10 80066f2: 697a ldr r2, [r7, #20] 80066f4: 4313 orrs r3, r2 80066f6: 617b str r3, [r7, #20] } /* Write to TIMx CR2 */ TIMx->CR2 = tmpcr2; 80066f8: 687b ldr r3, [r7, #4] 80066fa: 697a ldr r2, [r7, #20] 80066fc: 605a str r2, [r3, #4] /* Write to TIMx CCMR3 */ TIMx->CCMR3 = tmpccmrx; 80066fe: 687b ldr r3, [r7, #4] 8006700: 68fa ldr r2, [r7, #12] 8006702: 655a str r2, [r3, #84] @ 0x54 /* Set the Capture Compare Register value */ TIMx->CCR6 = OC_Config->Pulse; 8006704: 683b ldr r3, [r7, #0] 8006706: 685a ldr r2, [r3, #4] 8006708: 687b ldr r3, [r7, #4] 800670a: 65da str r2, [r3, #92] @ 0x5c /* Write to TIMx CCER */ TIMx->CCER = tmpccer; 800670c: 687b ldr r3, [r7, #4] 800670e: 693a ldr r2, [r7, #16] 8006710: 621a str r2, [r3, #32] } 8006712: 46c0 nop @ (mov r8, r8) 8006714: 46bd mov sp, r7 8006716: b006 add sp, #24 8006718: bd80 pop {r7, pc} 800671a: 46c0 nop @ (mov r8, r8) 800671c: ffefffff .word 0xffefffff 8006720: feff8fff .word 0xfeff8fff 8006724: ffdfffff .word 0xffdfffff 8006728: 40012c00 .word 0x40012c00 800672c: 40014400 .word 0x40014400 8006730: 40014800 .word 0x40014800 8006734: fffbffff .word 0xfffbffff 08006738 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8006738: b580 push {r7, lr} 800673a: b086 sub sp, #24 800673c: af00 add r7, sp, #0 800673e: 60f8 str r0, [r7, #12] 8006740: 60b9 str r1, [r7, #8] 8006742: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 1: Reset the CC1E Bit */ tmpccer = TIMx->CCER; 8006744: 68fb ldr r3, [r7, #12] 8006746: 6a1b ldr r3, [r3, #32] 8006748: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC1E; 800674a: 68fb ldr r3, [r7, #12] 800674c: 6a1b ldr r3, [r3, #32] 800674e: 2201 movs r2, #1 8006750: 4393 bics r3, r2 8006752: 001a movs r2, r3 8006754: 68fb ldr r3, [r7, #12] 8006756: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 8006758: 68fb ldr r3, [r7, #12] 800675a: 699b ldr r3, [r3, #24] 800675c: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC1F; 800675e: 693b ldr r3, [r7, #16] 8006760: 22f0 movs r2, #240 @ 0xf0 8006762: 4393 bics r3, r2 8006764: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 4U); 8006766: 687b ldr r3, [r7, #4] 8006768: 011b lsls r3, r3, #4 800676a: 693a ldr r2, [r7, #16] 800676c: 4313 orrs r3, r2 800676e: 613b str r3, [r7, #16] /* Select the Polarity and set the CC1E Bit */ tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); 8006770: 697b ldr r3, [r7, #20] 8006772: 220a movs r2, #10 8006774: 4393 bics r3, r2 8006776: 617b str r3, [r7, #20] tmpccer |= TIM_ICPolarity; 8006778: 697a ldr r2, [r7, #20] 800677a: 68bb ldr r3, [r7, #8] 800677c: 4313 orrs r3, r2 800677e: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1; 8006780: 68fb ldr r3, [r7, #12] 8006782: 693a ldr r2, [r7, #16] 8006784: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 8006786: 68fb ldr r3, [r7, #12] 8006788: 697a ldr r2, [r7, #20] 800678a: 621a str r2, [r3, #32] } 800678c: 46c0 nop @ (mov r8, r8) 800678e: 46bd mov sp, r7 8006790: b006 add sp, #24 8006792: bd80 pop {r7, pc} 08006794 : * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) { 8006794: b580 push {r7, lr} 8006796: b086 sub sp, #24 8006798: af00 add r7, sp, #0 800679a: 60f8 str r0, [r7, #12] 800679c: 60b9 str r1, [r7, #8] 800679e: 607a str r2, [r7, #4] uint32_t tmpccmr1; uint32_t tmpccer; /* Disable the Channel 2: Reset the CC2E Bit */ tmpccer = TIMx->CCER; 80067a0: 68fb ldr r3, [r7, #12] 80067a2: 6a1b ldr r3, [r3, #32] 80067a4: 617b str r3, [r7, #20] TIMx->CCER &= ~TIM_CCER_CC2E; 80067a6: 68fb ldr r3, [r7, #12] 80067a8: 6a1b ldr r3, [r3, #32] 80067aa: 2210 movs r2, #16 80067ac: 4393 bics r3, r2 80067ae: 001a movs r2, r3 80067b0: 68fb ldr r3, [r7, #12] 80067b2: 621a str r2, [r3, #32] tmpccmr1 = TIMx->CCMR1; 80067b4: 68fb ldr r3, [r7, #12] 80067b6: 699b ldr r3, [r3, #24] 80067b8: 613b str r3, [r7, #16] /* Set the filter */ tmpccmr1 &= ~TIM_CCMR1_IC2F; 80067ba: 693b ldr r3, [r7, #16] 80067bc: 4a0d ldr r2, [pc, #52] @ (80067f4 ) 80067be: 4013 ands r3, r2 80067c0: 613b str r3, [r7, #16] tmpccmr1 |= (TIM_ICFilter << 12U); 80067c2: 687b ldr r3, [r7, #4] 80067c4: 031b lsls r3, r3, #12 80067c6: 693a ldr r2, [r7, #16] 80067c8: 4313 orrs r3, r2 80067ca: 613b str r3, [r7, #16] /* Select the Polarity and set the CC2E Bit */ tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); 80067cc: 697b ldr r3, [r7, #20] 80067ce: 22a0 movs r2, #160 @ 0xa0 80067d0: 4393 bics r3, r2 80067d2: 617b str r3, [r7, #20] tmpccer |= (TIM_ICPolarity << 4U); 80067d4: 68bb ldr r3, [r7, #8] 80067d6: 011b lsls r3, r3, #4 80067d8: 697a ldr r2, [r7, #20] 80067da: 4313 orrs r3, r2 80067dc: 617b str r3, [r7, #20] /* Write to TIMx CCMR1 and CCER registers */ TIMx->CCMR1 = tmpccmr1 ; 80067de: 68fb ldr r3, [r7, #12] 80067e0: 693a ldr r2, [r7, #16] 80067e2: 619a str r2, [r3, #24] TIMx->CCER = tmpccer; 80067e4: 68fb ldr r3, [r7, #12] 80067e6: 697a ldr r2, [r7, #20] 80067e8: 621a str r2, [r3, #32] } 80067ea: 46c0 nop @ (mov r8, r8) 80067ec: 46bd mov sp, r7 80067ee: b006 add sp, #24 80067f0: bd80 pop {r7, pc} 80067f2: 46c0 nop @ (mov r8, r8) 80067f4: ffff0fff .word 0xffff0fff 080067f8 : * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 * @arg TIM_TS_ETRF: External Trigger input * @retval None */ static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) { 80067f8: b580 push {r7, lr} 80067fa: b084 sub sp, #16 80067fc: af00 add r7, sp, #0 80067fe: 6078 str r0, [r7, #4] 8006800: 6039 str r1, [r7, #0] uint32_t tmpsmcr; /* Get the TIMx SMCR register value */ tmpsmcr = TIMx->SMCR; 8006802: 687b ldr r3, [r7, #4] 8006804: 689b ldr r3, [r3, #8] 8006806: 60fb str r3, [r7, #12] /* Reset the TS Bits */ tmpsmcr &= ~TIM_SMCR_TS; 8006808: 68fb ldr r3, [r7, #12] 800680a: 4a08 ldr r2, [pc, #32] @ (800682c ) 800680c: 4013 ands r3, r2 800680e: 60fb str r3, [r7, #12] /* Set the Input Trigger source and the slave mode*/ tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); 8006810: 683a ldr r2, [r7, #0] 8006812: 68fb ldr r3, [r7, #12] 8006814: 4313 orrs r3, r2 8006816: 2207 movs r2, #7 8006818: 4313 orrs r3, r2 800681a: 60fb str r3, [r7, #12] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 800681c: 687b ldr r3, [r7, #4] 800681e: 68fa ldr r2, [r7, #12] 8006820: 609a str r2, [r3, #8] } 8006822: 46c0 nop @ (mov r8, r8) 8006824: 46bd mov sp, r7 8006826: b004 add sp, #16 8006828: bd80 pop {r7, pc} 800682a: 46c0 nop @ (mov r8, r8) 800682c: ffcfff8f .word 0xffcfff8f 08006830 : * This parameter must be a value between 0x00 and 0x0F * @retval None */ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) { 8006830: b580 push {r7, lr} 8006832: b086 sub sp, #24 8006834: af00 add r7, sp, #0 8006836: 60f8 str r0, [r7, #12] 8006838: 60b9 str r1, [r7, #8] 800683a: 607a str r2, [r7, #4] 800683c: 603b str r3, [r7, #0] uint32_t tmpsmcr; tmpsmcr = TIMx->SMCR; 800683e: 68fb ldr r3, [r7, #12] 8006840: 689b ldr r3, [r3, #8] 8006842: 617b str r3, [r7, #20] /* Reset the ETR Bits */ tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); 8006844: 697b ldr r3, [r7, #20] 8006846: 4a09 ldr r2, [pc, #36] @ (800686c ) 8006848: 4013 ands r3, r2 800684a: 617b str r3, [r7, #20] /* Set the Prescaler, the Filter value and the Polarity */ tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); 800684c: 683b ldr r3, [r7, #0] 800684e: 021a lsls r2, r3, #8 8006850: 687b ldr r3, [r7, #4] 8006852: 431a orrs r2, r3 8006854: 68bb ldr r3, [r7, #8] 8006856: 4313 orrs r3, r2 8006858: 697a ldr r2, [r7, #20] 800685a: 4313 orrs r3, r2 800685c: 617b str r3, [r7, #20] /* Write to TIMx SMCR */ TIMx->SMCR = tmpsmcr; 800685e: 68fb ldr r3, [r7, #12] 8006860: 697a ldr r2, [r7, #20] 8006862: 609a str r2, [r3, #8] } 8006864: 46c0 nop @ (mov r8, r8) 8006866: 46bd mov sp, r7 8006868: b006 add sp, #24 800686a: bd80 pop {r7, pc} 800686c: ffff00ff .word 0xffff00ff 08006870 : * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. * @retval None */ void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) { 8006870: b580 push {r7, lr} 8006872: b086 sub sp, #24 8006874: af00 add r7, sp, #0 8006876: 60f8 str r0, [r7, #12] 8006878: 60b9 str r1, [r7, #8] 800687a: 607a str r2, [r7, #4] /* Check the parameters */ assert_param(IS_TIM_CC1_INSTANCE(TIMx)); assert_param(IS_TIM_CHANNELS(Channel)); tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ 800687c: 68bb ldr r3, [r7, #8] 800687e: 221f movs r2, #31 8006880: 4013 ands r3, r2 8006882: 2201 movs r2, #1 8006884: 409a lsls r2, r3 8006886: 0013 movs r3, r2 8006888: 617b str r3, [r7, #20] /* Reset the CCxE Bit */ TIMx->CCER &= ~tmp; 800688a: 68fb ldr r3, [r7, #12] 800688c: 6a1b ldr r3, [r3, #32] 800688e: 697a ldr r2, [r7, #20] 8006890: 43d2 mvns r2, r2 8006892: 401a ands r2, r3 8006894: 68fb ldr r3, [r7, #12] 8006896: 621a str r2, [r3, #32] /* Set or reset the CCxE Bit */ TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ 8006898: 68fb ldr r3, [r7, #12] 800689a: 6a1a ldr r2, [r3, #32] 800689c: 68bb ldr r3, [r7, #8] 800689e: 211f movs r1, #31 80068a0: 400b ands r3, r1 80068a2: 6879 ldr r1, [r7, #4] 80068a4: 4099 lsls r1, r3 80068a6: 000b movs r3, r1 80068a8: 431a orrs r2, r3 80068aa: 68fb ldr r3, [r7, #12] 80068ac: 621a str r2, [r3, #32] } 80068ae: 46c0 nop @ (mov r8, r8) 80068b0: 46bd mov sp, r7 80068b2: b006 add sp, #24 80068b4: bd80 pop {r7, pc} ... 080068b8 : * mode. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, const TIM_MasterConfigTypeDef *sMasterConfig) { 80068b8: b580 push {r7, lr} 80068ba: b084 sub sp, #16 80068bc: af00 add r7, sp, #0 80068be: 6078 str r0, [r7, #4] 80068c0: 6039 str r1, [r7, #0] assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); /* Check input state */ __HAL_LOCK(htim); 80068c2: 687b ldr r3, [r7, #4] 80068c4: 223c movs r2, #60 @ 0x3c 80068c6: 5c9b ldrb r3, [r3, r2] 80068c8: 2b01 cmp r3, #1 80068ca: d101 bne.n 80068d0 80068cc: 2302 movs r3, #2 80068ce: e050 b.n 8006972 80068d0: 687b ldr r3, [r7, #4] 80068d2: 223c movs r2, #60 @ 0x3c 80068d4: 2101 movs r1, #1 80068d6: 5499 strb r1, [r3, r2] /* Change the handler state */ htim->State = HAL_TIM_STATE_BUSY; 80068d8: 687b ldr r3, [r7, #4] 80068da: 223d movs r2, #61 @ 0x3d 80068dc: 2102 movs r1, #2 80068de: 5499 strb r1, [r3, r2] /* Get the TIMx CR2 register value */ tmpcr2 = htim->Instance->CR2; 80068e0: 687b ldr r3, [r7, #4] 80068e2: 681b ldr r3, [r3, #0] 80068e4: 685b ldr r3, [r3, #4] 80068e6: 60fb str r3, [r7, #12] /* Get the TIMx SMCR register value */ tmpsmcr = htim->Instance->SMCR; 80068e8: 687b ldr r3, [r7, #4] 80068ea: 681b ldr r3, [r3, #0] 80068ec: 689b ldr r3, [r3, #8] 80068ee: 60bb str r3, [r7, #8] /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) 80068f0: 687b ldr r3, [r7, #4] 80068f2: 681b ldr r3, [r3, #0] 80068f4: 4a21 ldr r2, [pc, #132] @ (800697c ) 80068f6: 4293 cmp r3, r2 80068f8: d108 bne.n 800690c { /* Check the parameters */ assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); /* Clear the MMS2 bits */ tmpcr2 &= ~TIM_CR2_MMS2; 80068fa: 68fb ldr r3, [r7, #12] 80068fc: 4a20 ldr r2, [pc, #128] @ (8006980 ) 80068fe: 4013 ands r3, r2 8006900: 60fb str r3, [r7, #12] /* Select the TRGO2 source*/ tmpcr2 |= sMasterConfig->MasterOutputTrigger2; 8006902: 683b ldr r3, [r7, #0] 8006904: 685b ldr r3, [r3, #4] 8006906: 68fa ldr r2, [r7, #12] 8006908: 4313 orrs r3, r2 800690a: 60fb str r3, [r7, #12] } /* Reset the MMS Bits */ tmpcr2 &= ~TIM_CR2_MMS; 800690c: 68fb ldr r3, [r7, #12] 800690e: 2270 movs r2, #112 @ 0x70 8006910: 4393 bics r3, r2 8006912: 60fb str r3, [r7, #12] /* Select the TRGO source */ tmpcr2 |= sMasterConfig->MasterOutputTrigger; 8006914: 683b ldr r3, [r7, #0] 8006916: 681b ldr r3, [r3, #0] 8006918: 68fa ldr r2, [r7, #12] 800691a: 4313 orrs r3, r2 800691c: 60fb str r3, [r7, #12] /* Update TIMx CR2 */ htim->Instance->CR2 = tmpcr2; 800691e: 687b ldr r3, [r7, #4] 8006920: 681b ldr r3, [r3, #0] 8006922: 68fa ldr r2, [r7, #12] 8006924: 605a str r2, [r3, #4] if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) 8006926: 687b ldr r3, [r7, #4] 8006928: 681b ldr r3, [r3, #0] 800692a: 4a14 ldr r2, [pc, #80] @ (800697c ) 800692c: 4293 cmp r3, r2 800692e: d00a beq.n 8006946 8006930: 687b ldr r3, [r7, #4] 8006932: 681a ldr r2, [r3, #0] 8006934: 2380 movs r3, #128 @ 0x80 8006936: 05db lsls r3, r3, #23 8006938: 429a cmp r2, r3 800693a: d004 beq.n 8006946 800693c: 687b ldr r3, [r7, #4] 800693e: 681b ldr r3, [r3, #0] 8006940: 4a10 ldr r2, [pc, #64] @ (8006984 ) 8006942: 4293 cmp r3, r2 8006944: d10c bne.n 8006960 { /* Reset the MSM Bit */ tmpsmcr &= ~TIM_SMCR_MSM; 8006946: 68bb ldr r3, [r7, #8] 8006948: 2280 movs r2, #128 @ 0x80 800694a: 4393 bics r3, r2 800694c: 60bb str r3, [r7, #8] /* Set master mode */ tmpsmcr |= sMasterConfig->MasterSlaveMode; 800694e: 683b ldr r3, [r7, #0] 8006950: 689b ldr r3, [r3, #8] 8006952: 68ba ldr r2, [r7, #8] 8006954: 4313 orrs r3, r2 8006956: 60bb str r3, [r7, #8] /* Update TIMx SMCR */ htim->Instance->SMCR = tmpsmcr; 8006958: 687b ldr r3, [r7, #4] 800695a: 681b ldr r3, [r3, #0] 800695c: 68ba ldr r2, [r7, #8] 800695e: 609a str r2, [r3, #8] } /* Change the htim state */ htim->State = HAL_TIM_STATE_READY; 8006960: 687b ldr r3, [r7, #4] 8006962: 223d movs r2, #61 @ 0x3d 8006964: 2101 movs r1, #1 8006966: 5499 strb r1, [r3, r2] __HAL_UNLOCK(htim); 8006968: 687b ldr r3, [r7, #4] 800696a: 223c movs r2, #60 @ 0x3c 800696c: 2100 movs r1, #0 800696e: 5499 strb r1, [r3, r2] return HAL_OK; 8006970: 2300 movs r3, #0 } 8006972: 0018 movs r0, r3 8006974: 46bd mov sp, r7 8006976: b004 add sp, #16 8006978: bd80 pop {r7, pc} 800697a: 46c0 nop @ (mov r8, r8) 800697c: 40012c00 .word 0x40012c00 8006980: ff0fffff .word 0xff0fffff 8006984: 40000400 .word 0x40000400 08006988 : * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) { 8006988: b580 push {r7, lr} 800698a: b084 sub sp, #16 800698c: af00 add r7, sp, #0 800698e: 6078 str r0, [r7, #4] 8006990: 6039 str r1, [r7, #0] /* Keep this variable initialized to 0 as it is used to configure BDTR register */ uint32_t tmpbdtr = 0U; 8006992: 2300 movs r3, #0 8006994: 60fb str r3, [r7, #12] assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); /* Check input state */ __HAL_LOCK(htim); 8006996: 687b ldr r3, [r7, #4] 8006998: 223c movs r2, #60 @ 0x3c 800699a: 5c9b ldrb r3, [r3, r2] 800699c: 2b01 cmp r3, #1 800699e: d101 bne.n 80069a4 80069a0: 2302 movs r3, #2 80069a2: e06f b.n 8006a84 80069a4: 687b ldr r3, [r7, #4] 80069a6: 223c movs r2, #60 @ 0x3c 80069a8: 2101 movs r1, #1 80069aa: 5499 strb r1, [r3, r2] /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, the OSSI State, the dead time value and the Automatic Output Enable Bit */ /* Set the BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); 80069ac: 68fb ldr r3, [r7, #12] 80069ae: 22ff movs r2, #255 @ 0xff 80069b0: 4393 bics r3, r2 80069b2: 001a movs r2, r3 80069b4: 683b ldr r3, [r7, #0] 80069b6: 68db ldr r3, [r3, #12] 80069b8: 4313 orrs r3, r2 80069ba: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); 80069bc: 68fb ldr r3, [r7, #12] 80069be: 4a33 ldr r2, [pc, #204] @ (8006a8c ) 80069c0: 401a ands r2, r3 80069c2: 683b ldr r3, [r7, #0] 80069c4: 689b ldr r3, [r3, #8] 80069c6: 4313 orrs r3, r2 80069c8: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); 80069ca: 68fb ldr r3, [r7, #12] 80069cc: 4a30 ldr r2, [pc, #192] @ (8006a90 ) 80069ce: 401a ands r2, r3 80069d0: 683b ldr r3, [r7, #0] 80069d2: 685b ldr r3, [r3, #4] 80069d4: 4313 orrs r3, r2 80069d6: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); 80069d8: 68fb ldr r3, [r7, #12] 80069da: 4a2e ldr r2, [pc, #184] @ (8006a94 ) 80069dc: 401a ands r2, r3 80069de: 683b ldr r3, [r7, #0] 80069e0: 681b ldr r3, [r3, #0] 80069e2: 4313 orrs r3, r2 80069e4: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); 80069e6: 68fb ldr r3, [r7, #12] 80069e8: 4a2b ldr r2, [pc, #172] @ (8006a98 ) 80069ea: 401a ands r2, r3 80069ec: 683b ldr r3, [r7, #0] 80069ee: 691b ldr r3, [r3, #16] 80069f0: 4313 orrs r3, r2 80069f2: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); 80069f4: 68fb ldr r3, [r7, #12] 80069f6: 4a29 ldr r2, [pc, #164] @ (8006a9c ) 80069f8: 401a ands r2, r3 80069fa: 683b ldr r3, [r7, #0] 80069fc: 695b ldr r3, [r3, #20] 80069fe: 4313 orrs r3, r2 8006a00: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); 8006a02: 68fb ldr r3, [r7, #12] 8006a04: 4a26 ldr r2, [pc, #152] @ (8006aa0 ) 8006a06: 401a ands r2, r3 8006a08: 683b ldr r3, [r7, #0] 8006a0a: 6b1b ldr r3, [r3, #48] @ 0x30 8006a0c: 4313 orrs r3, r2 8006a0e: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); 8006a10: 68fb ldr r3, [r7, #12] 8006a12: 4a24 ldr r2, [pc, #144] @ (8006aa4 ) 8006a14: 401a ands r2, r3 8006a16: 683b ldr r3, [r7, #0] 8006a18: 699b ldr r3, [r3, #24] 8006a1a: 041b lsls r3, r3, #16 8006a1c: 4313 orrs r3, r2 8006a1e: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); 8006a20: 68fb ldr r3, [r7, #12] 8006a22: 4a21 ldr r2, [pc, #132] @ (8006aa8 ) 8006a24: 401a ands r2, r3 8006a26: 683b ldr r3, [r7, #0] 8006a28: 69db ldr r3, [r3, #28] 8006a2a: 4313 orrs r3, r2 8006a2c: 60fb str r3, [r7, #12] if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) 8006a2e: 687b ldr r3, [r7, #4] 8006a30: 681b ldr r3, [r3, #0] 8006a32: 4a1e ldr r2, [pc, #120] @ (8006aac ) 8006a34: 4293 cmp r3, r2 8006a36: d11c bne.n 8006a72 assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); /* Set the BREAK2 input related BDTR bits */ MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); 8006a38: 68fb ldr r3, [r7, #12] 8006a3a: 4a1d ldr r2, [pc, #116] @ (8006ab0 ) 8006a3c: 401a ands r2, r3 8006a3e: 683b ldr r3, [r7, #0] 8006a40: 6a9b ldr r3, [r3, #40] @ 0x28 8006a42: 051b lsls r3, r3, #20 8006a44: 4313 orrs r3, r2 8006a46: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); 8006a48: 68fb ldr r3, [r7, #12] 8006a4a: 4a1a ldr r2, [pc, #104] @ (8006ab4 ) 8006a4c: 401a ands r2, r3 8006a4e: 683b ldr r3, [r7, #0] 8006a50: 6a1b ldr r3, [r3, #32] 8006a52: 4313 orrs r3, r2 8006a54: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); 8006a56: 68fb ldr r3, [r7, #12] 8006a58: 4a17 ldr r2, [pc, #92] @ (8006ab8 ) 8006a5a: 401a ands r2, r3 8006a5c: 683b ldr r3, [r7, #0] 8006a5e: 6a5b ldr r3, [r3, #36] @ 0x24 8006a60: 4313 orrs r3, r2 8006a62: 60fb str r3, [r7, #12] MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); 8006a64: 68fb ldr r3, [r7, #12] 8006a66: 4a15 ldr r2, [pc, #84] @ (8006abc ) 8006a68: 401a ands r2, r3 8006a6a: 683b ldr r3, [r7, #0] 8006a6c: 6adb ldr r3, [r3, #44] @ 0x2c 8006a6e: 4313 orrs r3, r2 8006a70: 60fb str r3, [r7, #12] } /* Set TIMx_BDTR */ htim->Instance->BDTR = tmpbdtr; 8006a72: 687b ldr r3, [r7, #4] 8006a74: 681b ldr r3, [r3, #0] 8006a76: 68fa ldr r2, [r7, #12] 8006a78: 645a str r2, [r3, #68] @ 0x44 __HAL_UNLOCK(htim); 8006a7a: 687b ldr r3, [r7, #4] 8006a7c: 223c movs r2, #60 @ 0x3c 8006a7e: 2100 movs r1, #0 8006a80: 5499 strb r1, [r3, r2] return HAL_OK; 8006a82: 2300 movs r3, #0 } 8006a84: 0018 movs r0, r3 8006a86: 46bd mov sp, r7 8006a88: b004 add sp, #16 8006a8a: bd80 pop {r7, pc} 8006a8c: fffffcff .word 0xfffffcff 8006a90: fffffbff .word 0xfffffbff 8006a94: fffff7ff .word 0xfffff7ff 8006a98: ffffefff .word 0xffffefff 8006a9c: ffffdfff .word 0xffffdfff 8006aa0: ffffbfff .word 0xffffbfff 8006aa4: fff0ffff .word 0xfff0ffff 8006aa8: efffffff .word 0xefffffff 8006aac: 40012c00 .word 0x40012c00 8006ab0: ff0fffff .word 0xff0fffff 8006ab4: feffffff .word 0xfeffffff 8006ab8: fdffffff .word 0xfdffffff 8006abc: dfffffff .word 0xdfffffff 08006ac0 : * @brief Commutation callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) { 8006ac0: b580 push {r7, lr} 8006ac2: b082 sub sp, #8 8006ac4: af00 add r7, sp, #0 8006ac6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_CommutCallback could be implemented in the user file */ } 8006ac8: 46c0 nop @ (mov r8, r8) 8006aca: 46bd mov sp, r7 8006acc: b002 add sp, #8 8006ace: bd80 pop {r7, pc} 08006ad0 : * @brief Break detection callback in non-blocking mode * @param htim TIM handle * @retval None */ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) { 8006ad0: b580 push {r7, lr} 8006ad2: b082 sub sp, #8 8006ad4: af00 add r7, sp, #0 8006ad6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function should not be modified, when the callback is needed, the HAL_TIMEx_BreakCallback could be implemented in the user file */ } 8006ad8: 46c0 nop @ (mov r8, r8) 8006ada: 46bd mov sp, r7 8006adc: b002 add sp, #8 8006ade: bd80 pop {r7, pc} 08006ae0 : * @brief Break2 detection callback in non blocking mode * @param htim: TIM handle * @retval None */ __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) { 8006ae0: b580 push {r7, lr} 8006ae2: b082 sub sp, #8 8006ae4: af00 add r7, sp, #0 8006ae6: 6078 str r0, [r7, #4] UNUSED(htim); /* NOTE : This function Should not be modified, when the callback is needed, the HAL_TIMEx_Break2Callback could be implemented in the user file */ } 8006ae8: 46c0 nop @ (mov r8, r8) 8006aea: 46bd mov sp, r7 8006aec: b002 add sp, #8 8006aee: bd80 pop {r7, pc} 08006af0 : * parameters in the UART_InitTypeDef and initialize the associated handle. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) { 8006af0: b580 push {r7, lr} 8006af2: b082 sub sp, #8 8006af4: af00 add r7, sp, #0 8006af6: 6078 str r0, [r7, #4] /* Check the UART handle allocation */ if (huart == NULL) 8006af8: 687b ldr r3, [r7, #4] 8006afa: 2b00 cmp r3, #0 8006afc: d101 bne.n 8006b02 { return HAL_ERROR; 8006afe: 2301 movs r3, #1 8006b00: e046 b.n 8006b90 { /* Check the parameters */ assert_param(IS_UART_INSTANCE(huart->Instance)); } if (huart->gState == HAL_UART_STATE_RESET) 8006b02: 687b ldr r3, [r7, #4] 8006b04: 2288 movs r2, #136 @ 0x88 8006b06: 589b ldr r3, [r3, r2] 8006b08: 2b00 cmp r3, #0 8006b0a: d107 bne.n 8006b1c { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 8006b0c: 687b ldr r3, [r7, #4] 8006b0e: 2284 movs r2, #132 @ 0x84 8006b10: 2100 movs r1, #0 8006b12: 5499 strb r1, [r3, r2] /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK */ HAL_UART_MspInit(huart); 8006b14: 687b ldr r3, [r7, #4] 8006b16: 0018 movs r0, r3 8006b18: f7fd f8da bl 8003cd0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 8006b1c: 687b ldr r3, [r7, #4] 8006b1e: 2288 movs r2, #136 @ 0x88 8006b20: 2124 movs r1, #36 @ 0x24 8006b22: 5099 str r1, [r3, r2] __HAL_UART_DISABLE(huart); 8006b24: 687b ldr r3, [r7, #4] 8006b26: 681b ldr r3, [r3, #0] 8006b28: 681a ldr r2, [r3, #0] 8006b2a: 687b ldr r3, [r7, #4] 8006b2c: 681b ldr r3, [r3, #0] 8006b2e: 2101 movs r1, #1 8006b30: 438a bics r2, r1 8006b32: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 8006b34: 687b ldr r3, [r7, #4] 8006b36: 6a9b ldr r3, [r3, #40] @ 0x28 8006b38: 2b00 cmp r3, #0 8006b3a: d003 beq.n 8006b44 { UART_AdvFeatureConfig(huart); 8006b3c: 687b ldr r3, [r7, #4] 8006b3e: 0018 movs r0, r3 8006b40: f000 fa66 bl 8007010 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 8006b44: 687b ldr r3, [r7, #4] 8006b46: 0018 movs r0, r3 8006b48: f000 f8e4 bl 8006d14 8006b4c: 0003 movs r3, r0 8006b4e: 2b01 cmp r3, #1 8006b50: d101 bne.n 8006b56 { return HAL_ERROR; 8006b52: 2301 movs r3, #1 8006b54: e01c b.n 8006b90 } /* In asynchronous mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); 8006b56: 687b ldr r3, [r7, #4] 8006b58: 681b ldr r3, [r3, #0] 8006b5a: 685a ldr r2, [r3, #4] 8006b5c: 687b ldr r3, [r7, #4] 8006b5e: 681b ldr r3, [r3, #0] 8006b60: 490d ldr r1, [pc, #52] @ (8006b98 ) 8006b62: 400a ands r2, r1 8006b64: 605a str r2, [r3, #4] CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); 8006b66: 687b ldr r3, [r7, #4] 8006b68: 681b ldr r3, [r3, #0] 8006b6a: 689a ldr r2, [r3, #8] 8006b6c: 687b ldr r3, [r7, #4] 8006b6e: 681b ldr r3, [r3, #0] 8006b70: 212a movs r1, #42 @ 0x2a 8006b72: 438a bics r2, r1 8006b74: 609a str r2, [r3, #8] __HAL_UART_ENABLE(huart); 8006b76: 687b ldr r3, [r7, #4] 8006b78: 681b ldr r3, [r3, #0] 8006b7a: 681a ldr r2, [r3, #0] 8006b7c: 687b ldr r3, [r7, #4] 8006b7e: 681b ldr r3, [r3, #0] 8006b80: 2101 movs r1, #1 8006b82: 430a orrs r2, r1 8006b84: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 8006b86: 687b ldr r3, [r7, #4] 8006b88: 0018 movs r0, r3 8006b8a: f000 faf5 bl 8007178 8006b8e: 0003 movs r3, r0 } 8006b90: 0018 movs r0, r3 8006b92: 46bd mov sp, r7 8006b94: b002 add sp, #8 8006b96: bd80 pop {r7, pc} 8006b98: ffffb7ff .word 0xffffb7ff 08006b9c : * @param Size Amount of data elements (u8 or u16) to be sent. * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { 8006b9c: b580 push {r7, lr} 8006b9e: b08a sub sp, #40 @ 0x28 8006ba0: af02 add r7, sp, #8 8006ba2: 60f8 str r0, [r7, #12] 8006ba4: 60b9 str r1, [r7, #8] 8006ba6: 603b str r3, [r7, #0] 8006ba8: 1dbb adds r3, r7, #6 8006baa: 801a strh r2, [r3, #0] const uint8_t *pdata8bits; const uint16_t *pdata16bits; uint32_t tickstart; /* Check that a Tx process is not already ongoing */ if (huart->gState == HAL_UART_STATE_READY) 8006bac: 68fb ldr r3, [r7, #12] 8006bae: 2288 movs r2, #136 @ 0x88 8006bb0: 589b ldr r3, [r3, r2] 8006bb2: 2b20 cmp r3, #32 8006bb4: d000 beq.n 8006bb8 8006bb6: e090 b.n 8006cda { if ((pData == NULL) || (Size == 0U)) 8006bb8: 68bb ldr r3, [r7, #8] 8006bba: 2b00 cmp r3, #0 8006bbc: d003 beq.n 8006bc6 8006bbe: 1dbb adds r3, r7, #6 8006bc0: 881b ldrh r3, [r3, #0] 8006bc2: 2b00 cmp r3, #0 8006bc4: d101 bne.n 8006bca { return HAL_ERROR; 8006bc6: 2301 movs r3, #1 8006bc8: e088 b.n 8006cdc } /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter should be aligned on a u16 frontier, as data to be filled into TDR will be handled through a u16 cast. */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006bca: 68fb ldr r3, [r7, #12] 8006bcc: 689a ldr r2, [r3, #8] 8006bce: 2380 movs r3, #128 @ 0x80 8006bd0: 015b lsls r3, r3, #5 8006bd2: 429a cmp r2, r3 8006bd4: d109 bne.n 8006bea 8006bd6: 68fb ldr r3, [r7, #12] 8006bd8: 691b ldr r3, [r3, #16] 8006bda: 2b00 cmp r3, #0 8006bdc: d105 bne.n 8006bea { if ((((uint32_t)pData) & 1U) != 0U) 8006bde: 68bb ldr r3, [r7, #8] 8006be0: 2201 movs r2, #1 8006be2: 4013 ands r3, r2 8006be4: d001 beq.n 8006bea { return HAL_ERROR; 8006be6: 2301 movs r3, #1 8006be8: e078 b.n 8006cdc } } huart->ErrorCode = HAL_UART_ERROR_NONE; 8006bea: 68fb ldr r3, [r7, #12] 8006bec: 2290 movs r2, #144 @ 0x90 8006bee: 2100 movs r1, #0 8006bf0: 5099 str r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY_TX; 8006bf2: 68fb ldr r3, [r7, #12] 8006bf4: 2288 movs r2, #136 @ 0x88 8006bf6: 2121 movs r1, #33 @ 0x21 8006bf8: 5099 str r1, [r3, r2] /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8006bfa: f7fd fa6d bl 80040d8 8006bfe: 0003 movs r3, r0 8006c00: 617b str r3, [r7, #20] huart->TxXferSize = Size; 8006c02: 68fb ldr r3, [r7, #12] 8006c04: 1dba adds r2, r7, #6 8006c06: 2154 movs r1, #84 @ 0x54 8006c08: 8812 ldrh r2, [r2, #0] 8006c0a: 525a strh r2, [r3, r1] huart->TxXferCount = Size; 8006c0c: 68fb ldr r3, [r7, #12] 8006c0e: 1dba adds r2, r7, #6 8006c10: 2156 movs r1, #86 @ 0x56 8006c12: 8812 ldrh r2, [r2, #0] 8006c14: 525a strh r2, [r3, r1] /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8006c16: 68fb ldr r3, [r7, #12] 8006c18: 689a ldr r2, [r3, #8] 8006c1a: 2380 movs r3, #128 @ 0x80 8006c1c: 015b lsls r3, r3, #5 8006c1e: 429a cmp r2, r3 8006c20: d108 bne.n 8006c34 8006c22: 68fb ldr r3, [r7, #12] 8006c24: 691b ldr r3, [r3, #16] 8006c26: 2b00 cmp r3, #0 8006c28: d104 bne.n 8006c34 { pdata8bits = NULL; 8006c2a: 2300 movs r3, #0 8006c2c: 61fb str r3, [r7, #28] pdata16bits = (const uint16_t *) pData; 8006c2e: 68bb ldr r3, [r7, #8] 8006c30: 61bb str r3, [r7, #24] 8006c32: e003 b.n 8006c3c } else { pdata8bits = pData; 8006c34: 68bb ldr r3, [r7, #8] 8006c36: 61fb str r3, [r7, #28] pdata16bits = NULL; 8006c38: 2300 movs r3, #0 8006c3a: 61bb str r3, [r7, #24] } while (huart->TxXferCount > 0U) 8006c3c: e030 b.n 8006ca0 { if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) 8006c3e: 697a ldr r2, [r7, #20] 8006c40: 68f8 ldr r0, [r7, #12] 8006c42: 683b ldr r3, [r7, #0] 8006c44: 9300 str r3, [sp, #0] 8006c46: 0013 movs r3, r2 8006c48: 2200 movs r2, #0 8006c4a: 2180 movs r1, #128 @ 0x80 8006c4c: f000 fb3e bl 80072cc 8006c50: 1e03 subs r3, r0, #0 8006c52: d005 beq.n 8006c60 { huart->gState = HAL_UART_STATE_READY; 8006c54: 68fb ldr r3, [r7, #12] 8006c56: 2288 movs r2, #136 @ 0x88 8006c58: 2120 movs r1, #32 8006c5a: 5099 str r1, [r3, r2] return HAL_TIMEOUT; 8006c5c: 2303 movs r3, #3 8006c5e: e03d b.n 8006cdc } if (pdata8bits == NULL) 8006c60: 69fb ldr r3, [r7, #28] 8006c62: 2b00 cmp r3, #0 8006c64: d10b bne.n 8006c7e { huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); 8006c66: 69bb ldr r3, [r7, #24] 8006c68: 881b ldrh r3, [r3, #0] 8006c6a: 001a movs r2, r3 8006c6c: 68fb ldr r3, [r7, #12] 8006c6e: 681b ldr r3, [r3, #0] 8006c70: 05d2 lsls r2, r2, #23 8006c72: 0dd2 lsrs r2, r2, #23 8006c74: 629a str r2, [r3, #40] @ 0x28 pdata16bits++; 8006c76: 69bb ldr r3, [r7, #24] 8006c78: 3302 adds r3, #2 8006c7a: 61bb str r3, [r7, #24] 8006c7c: e007 b.n 8006c8e } else { huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); 8006c7e: 69fb ldr r3, [r7, #28] 8006c80: 781a ldrb r2, [r3, #0] 8006c82: 68fb ldr r3, [r7, #12] 8006c84: 681b ldr r3, [r3, #0] 8006c86: 629a str r2, [r3, #40] @ 0x28 pdata8bits++; 8006c88: 69fb ldr r3, [r7, #28] 8006c8a: 3301 adds r3, #1 8006c8c: 61fb str r3, [r7, #28] } huart->TxXferCount--; 8006c8e: 68fb ldr r3, [r7, #12] 8006c90: 2256 movs r2, #86 @ 0x56 8006c92: 5a9b ldrh r3, [r3, r2] 8006c94: b29b uxth r3, r3 8006c96: 3b01 subs r3, #1 8006c98: b299 uxth r1, r3 8006c9a: 68fb ldr r3, [r7, #12] 8006c9c: 2256 movs r2, #86 @ 0x56 8006c9e: 5299 strh r1, [r3, r2] while (huart->TxXferCount > 0U) 8006ca0: 68fb ldr r3, [r7, #12] 8006ca2: 2256 movs r2, #86 @ 0x56 8006ca4: 5a9b ldrh r3, [r3, r2] 8006ca6: b29b uxth r3, r3 8006ca8: 2b00 cmp r3, #0 8006caa: d1c8 bne.n 8006c3e } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) 8006cac: 697a ldr r2, [r7, #20] 8006cae: 68f8 ldr r0, [r7, #12] 8006cb0: 683b ldr r3, [r7, #0] 8006cb2: 9300 str r3, [sp, #0] 8006cb4: 0013 movs r3, r2 8006cb6: 2200 movs r2, #0 8006cb8: 2140 movs r1, #64 @ 0x40 8006cba: f000 fb07 bl 80072cc 8006cbe: 1e03 subs r3, r0, #0 8006cc0: d005 beq.n 8006cce { huart->gState = HAL_UART_STATE_READY; 8006cc2: 68fb ldr r3, [r7, #12] 8006cc4: 2288 movs r2, #136 @ 0x88 8006cc6: 2120 movs r1, #32 8006cc8: 5099 str r1, [r3, r2] return HAL_TIMEOUT; 8006cca: 2303 movs r3, #3 8006ccc: e006 b.n 8006cdc } /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8006cce: 68fb ldr r3, [r7, #12] 8006cd0: 2288 movs r2, #136 @ 0x88 8006cd2: 2120 movs r1, #32 8006cd4: 5099 str r1, [r3, r2] return HAL_OK; 8006cd6: 2300 movs r3, #0 8006cd8: e000 b.n 8006cdc } else { return HAL_BUSY; 8006cda: 2302 movs r3, #2 } } 8006cdc: 0018 movs r0, r3 8006cde: 46bd mov sp, r7 8006ce0: b008 add sp, #32 8006ce2: bd80 pop {r7, pc} 08006ce4 : * @brief Rx Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) { 8006ce4: b580 push {r7, lr} 8006ce6: b082 sub sp, #8 8006ce8: af00 add r7, sp, #0 8006cea: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_RxCpltCallback can be implemented in the user file. */ } 8006cec: 46c0 nop @ (mov r8, r8) 8006cee: 46bd mov sp, r7 8006cf0: b002 add sp, #8 8006cf2: bd80 pop {r7, pc} 08006cf4 : * @brief Rx Half Transfer completed callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) { 8006cf4: b580 push {r7, lr} 8006cf6: b082 sub sp, #8 8006cf8: af00 add r7, sp, #0 8006cfa: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE: This function should not be modified, when the callback is needed, the HAL_UART_RxHalfCpltCallback can be implemented in the user file. */ } 8006cfc: 46c0 nop @ (mov r8, r8) 8006cfe: 46bd mov sp, r7 8006d00: b002 add sp, #8 8006d02: bd80 pop {r7, pc} 08006d04 : * @brief UART error callback. * @param huart UART handle. * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) { 8006d04: b580 push {r7, lr} 8006d06: b082 sub sp, #8 8006d08: af00 add r7, sp, #0 8006d0a: 6078 str r0, [r7, #4] UNUSED(huart); /* NOTE : This function should not be modified, when the callback is needed, the HAL_UART_ErrorCallback can be implemented in the user file. */ } 8006d0c: 46c0 nop @ (mov r8, r8) 8006d0e: 46bd mov sp, r7 8006d10: b002 add sp, #8 8006d12: bd80 pop {r7, pc} 08006d14 : * @brief Configure the UART peripheral. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) { 8006d14: b580 push {r7, lr} 8006d16: b088 sub sp, #32 8006d18: af00 add r7, sp, #0 8006d1a: 6078 str r0, [r7, #4] uint32_t tmpreg; uint16_t brrtemp; UART_ClockSourceTypeDef clocksource; uint32_t usartdiv; HAL_StatusTypeDef ret = HAL_OK; 8006d1c: 231e movs r3, #30 8006d1e: 18fb adds r3, r7, r3 8006d20: 2200 movs r2, #0 8006d22: 701a strb r2, [r3, #0] * the UART Word Length, Parity, Mode and oversampling: * set the M bits according to huart->Init.WordLength value * set PCE and PS bits according to huart->Init.Parity value * set TE and RE bits according to huart->Init.Mode value * set OVER8 bit according to huart->Init.OverSampling value */ tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; 8006d24: 687b ldr r3, [r7, #4] 8006d26: 689a ldr r2, [r3, #8] 8006d28: 687b ldr r3, [r7, #4] 8006d2a: 691b ldr r3, [r3, #16] 8006d2c: 431a orrs r2, r3 8006d2e: 687b ldr r3, [r7, #4] 8006d30: 695b ldr r3, [r3, #20] 8006d32: 431a orrs r2, r3 8006d34: 687b ldr r3, [r7, #4] 8006d36: 69db ldr r3, [r3, #28] 8006d38: 4313 orrs r3, r2 8006d3a: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); 8006d3c: 687b ldr r3, [r7, #4] 8006d3e: 681b ldr r3, [r3, #0] 8006d40: 681b ldr r3, [r3, #0] 8006d42: 4aab ldr r2, [pc, #684] @ (8006ff0 ) 8006d44: 4013 ands r3, r2 8006d46: 0019 movs r1, r3 8006d48: 687b ldr r3, [r7, #4] 8006d4a: 681b ldr r3, [r3, #0] 8006d4c: 697a ldr r2, [r7, #20] 8006d4e: 430a orrs r2, r1 8006d50: 601a str r2, [r3, #0] /*-------------------------- USART CR2 Configuration -----------------------*/ /* Configure the UART Stop Bits: Set STOP[13:12] bits according * to huart->Init.StopBits value */ MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); 8006d52: 687b ldr r3, [r7, #4] 8006d54: 681b ldr r3, [r3, #0] 8006d56: 685b ldr r3, [r3, #4] 8006d58: 4aa6 ldr r2, [pc, #664] @ (8006ff4 ) 8006d5a: 4013 ands r3, r2 8006d5c: 0019 movs r1, r3 8006d5e: 687b ldr r3, [r7, #4] 8006d60: 68da ldr r2, [r3, #12] 8006d62: 687b ldr r3, [r7, #4] 8006d64: 681b ldr r3, [r3, #0] 8006d66: 430a orrs r2, r1 8006d68: 605a str r2, [r3, #4] /* Configure * - UART HardWare Flow Control: set CTSE and RTSE bits according * to huart->Init.HwFlowCtl value * - one-bit sampling method versus three samples' majority rule according * to huart->Init.OneBitSampling (not applicable to LPUART) */ tmpreg = (uint32_t)huart->Init.HwFlowCtl; 8006d6a: 687b ldr r3, [r7, #4] 8006d6c: 699b ldr r3, [r3, #24] 8006d6e: 617b str r3, [r7, #20] tmpreg |= huart->Init.OneBitSampling; 8006d70: 687b ldr r3, [r7, #4] 8006d72: 6a1b ldr r3, [r3, #32] 8006d74: 697a ldr r2, [r7, #20] 8006d76: 4313 orrs r3, r2 8006d78: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); 8006d7a: 687b ldr r3, [r7, #4] 8006d7c: 681b ldr r3, [r3, #0] 8006d7e: 689b ldr r3, [r3, #8] 8006d80: 4a9d ldr r2, [pc, #628] @ (8006ff8 ) 8006d82: 4013 ands r3, r2 8006d84: 0019 movs r1, r3 8006d86: 687b ldr r3, [r7, #4] 8006d88: 681b ldr r3, [r3, #0] 8006d8a: 697a ldr r2, [r7, #20] 8006d8c: 430a orrs r2, r1 8006d8e: 609a str r2, [r3, #8] /*-------------------------- USART PRESC Configuration -----------------------*/ /* Configure * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); 8006d90: 687b ldr r3, [r7, #4] 8006d92: 681b ldr r3, [r3, #0] 8006d94: 6adb ldr r3, [r3, #44] @ 0x2c 8006d96: 220f movs r2, #15 8006d98: 4393 bics r3, r2 8006d9a: 0019 movs r1, r3 8006d9c: 687b ldr r3, [r7, #4] 8006d9e: 6a5a ldr r2, [r3, #36] @ 0x24 8006da0: 687b ldr r3, [r7, #4] 8006da2: 681b ldr r3, [r3, #0] 8006da4: 430a orrs r2, r1 8006da6: 62da str r2, [r3, #44] @ 0x2c /*-------------------------- USART BRR Configuration -----------------------*/ UART_GETCLOCKSOURCE(huart, clocksource); 8006da8: 687b ldr r3, [r7, #4] 8006daa: 681b ldr r3, [r3, #0] 8006dac: 4a93 ldr r2, [pc, #588] @ (8006ffc ) 8006dae: 4293 cmp r3, r2 8006db0: d127 bne.n 8006e02 8006db2: 4b93 ldr r3, [pc, #588] @ (8007000 ) 8006db4: 6d5b ldr r3, [r3, #84] @ 0x54 8006db6: 2203 movs r2, #3 8006db8: 4013 ands r3, r2 8006dba: 2b03 cmp r3, #3 8006dbc: d017 beq.n 8006dee 8006dbe: d81b bhi.n 8006df8 8006dc0: 2b02 cmp r3, #2 8006dc2: d00a beq.n 8006dda 8006dc4: d818 bhi.n 8006df8 8006dc6: 2b00 cmp r3, #0 8006dc8: d002 beq.n 8006dd0 8006dca: 2b01 cmp r3, #1 8006dcc: d00a beq.n 8006de4 8006dce: e013 b.n 8006df8 8006dd0: 231f movs r3, #31 8006dd2: 18fb adds r3, r7, r3 8006dd4: 2200 movs r2, #0 8006dd6: 701a strb r2, [r3, #0] 8006dd8: e021 b.n 8006e1e 8006dda: 231f movs r3, #31 8006ddc: 18fb adds r3, r7, r3 8006dde: 2202 movs r2, #2 8006de0: 701a strb r2, [r3, #0] 8006de2: e01c b.n 8006e1e 8006de4: 231f movs r3, #31 8006de6: 18fb adds r3, r7, r3 8006de8: 2204 movs r2, #4 8006dea: 701a strb r2, [r3, #0] 8006dec: e017 b.n 8006e1e 8006dee: 231f movs r3, #31 8006df0: 18fb adds r3, r7, r3 8006df2: 2208 movs r2, #8 8006df4: 701a strb r2, [r3, #0] 8006df6: e012 b.n 8006e1e 8006df8: 231f movs r3, #31 8006dfa: 18fb adds r3, r7, r3 8006dfc: 2210 movs r2, #16 8006dfe: 701a strb r2, [r3, #0] 8006e00: e00d b.n 8006e1e 8006e02: 687b ldr r3, [r7, #4] 8006e04: 681b ldr r3, [r3, #0] 8006e06: 4a7f ldr r2, [pc, #508] @ (8007004 ) 8006e08: 4293 cmp r3, r2 8006e0a: d104 bne.n 8006e16 8006e0c: 231f movs r3, #31 8006e0e: 18fb adds r3, r7, r3 8006e10: 2200 movs r2, #0 8006e12: 701a strb r2, [r3, #0] 8006e14: e003 b.n 8006e1e 8006e16: 231f movs r3, #31 8006e18: 18fb adds r3, r7, r3 8006e1a: 2210 movs r2, #16 8006e1c: 701a strb r2, [r3, #0] if (huart->Init.OverSampling == UART_OVERSAMPLING_8) 8006e1e: 687b ldr r3, [r7, #4] 8006e20: 69da ldr r2, [r3, #28] 8006e22: 2380 movs r3, #128 @ 0x80 8006e24: 021b lsls r3, r3, #8 8006e26: 429a cmp r2, r3 8006e28: d000 beq.n 8006e2c 8006e2a: e06f b.n 8006f0c { switch (clocksource) 8006e2c: 231f movs r3, #31 8006e2e: 18fb adds r3, r7, r3 8006e30: 781b ldrb r3, [r3, #0] 8006e32: 2b08 cmp r3, #8 8006e34: d01f beq.n 8006e76 8006e36: dc22 bgt.n 8006e7e 8006e38: 2b04 cmp r3, #4 8006e3a: d017 beq.n 8006e6c 8006e3c: dc1f bgt.n 8006e7e 8006e3e: 2b00 cmp r3, #0 8006e40: d002 beq.n 8006e48 8006e42: 2b02 cmp r3, #2 8006e44: d005 beq.n 8006e52 8006e46: e01a b.n 8006e7e { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8006e48: f7fe fa00 bl 800524c 8006e4c: 0003 movs r3, r0 8006e4e: 61bb str r3, [r7, #24] break; 8006e50: e01c b.n 8006e8c case UART_CLOCKSOURCE_HSI: pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); 8006e52: 4b6b ldr r3, [pc, #428] @ (8007000 ) 8006e54: 681b ldr r3, [r3, #0] 8006e56: 095b lsrs r3, r3, #5 8006e58: 2207 movs r2, #7 8006e5a: 4013 ands r3, r2 8006e5c: 3301 adds r3, #1 8006e5e: 0019 movs r1, r3 8006e60: 4869 ldr r0, [pc, #420] @ (8007008 ) 8006e62: f7f9 f951 bl 8000108 <__udivsi3> 8006e66: 0003 movs r3, r0 8006e68: 61bb str r3, [r7, #24] break; 8006e6a: e00f b.n 8006e8c case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8006e6c: f7fe f980 bl 8005170 8006e70: 0003 movs r3, r0 8006e72: 61bb str r3, [r7, #24] break; 8006e74: e00a b.n 8006e8c case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8006e76: 2380 movs r3, #128 @ 0x80 8006e78: 021b lsls r3, r3, #8 8006e7a: 61bb str r3, [r7, #24] break; 8006e7c: e006 b.n 8006e8c default: pclk = 0U; 8006e7e: 2300 movs r3, #0 8006e80: 61bb str r3, [r7, #24] ret = HAL_ERROR; 8006e82: 231e movs r3, #30 8006e84: 18fb adds r3, r7, r3 8006e86: 2201 movs r2, #1 8006e88: 701a strb r2, [r3, #0] break; 8006e8a: 46c0 nop @ (mov r8, r8) } /* USARTDIV must be greater than or equal to 0d16 */ if (pclk != 0U) 8006e8c: 69bb ldr r3, [r7, #24] 8006e8e: 2b00 cmp r3, #0 8006e90: d100 bne.n 8006e94 8006e92: e097 b.n 8006fc4 { usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8006e94: 687b ldr r3, [r7, #4] 8006e96: 6a5a ldr r2, [r3, #36] @ 0x24 8006e98: 4b5c ldr r3, [pc, #368] @ (800700c ) 8006e9a: 0052 lsls r2, r2, #1 8006e9c: 5ad3 ldrh r3, [r2, r3] 8006e9e: 0019 movs r1, r3 8006ea0: 69b8 ldr r0, [r7, #24] 8006ea2: f7f9 f931 bl 8000108 <__udivsi3> 8006ea6: 0003 movs r3, r0 8006ea8: 005a lsls r2, r3, #1 8006eaa: 687b ldr r3, [r7, #4] 8006eac: 685b ldr r3, [r3, #4] 8006eae: 085b lsrs r3, r3, #1 8006eb0: 18d2 adds r2, r2, r3 8006eb2: 687b ldr r3, [r7, #4] 8006eb4: 685b ldr r3, [r3, #4] 8006eb6: 0019 movs r1, r3 8006eb8: 0010 movs r0, r2 8006eba: f7f9 f925 bl 8000108 <__udivsi3> 8006ebe: 0003 movs r3, r0 8006ec0: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8006ec2: 693b ldr r3, [r7, #16] 8006ec4: 2b0f cmp r3, #15 8006ec6: d91c bls.n 8006f02 8006ec8: 693a ldr r2, [r7, #16] 8006eca: 2380 movs r3, #128 @ 0x80 8006ecc: 025b lsls r3, r3, #9 8006ece: 429a cmp r2, r3 8006ed0: d217 bcs.n 8006f02 { brrtemp = (uint16_t)(usartdiv & 0xFFF0U); 8006ed2: 693b ldr r3, [r7, #16] 8006ed4: b29a uxth r2, r3 8006ed6: 200e movs r0, #14 8006ed8: 183b adds r3, r7, r0 8006eda: 210f movs r1, #15 8006edc: 438a bics r2, r1 8006ede: 801a strh r2, [r3, #0] brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); 8006ee0: 693b ldr r3, [r7, #16] 8006ee2: 085b lsrs r3, r3, #1 8006ee4: b29b uxth r3, r3 8006ee6: 2207 movs r2, #7 8006ee8: 4013 ands r3, r2 8006eea: b299 uxth r1, r3 8006eec: 183b adds r3, r7, r0 8006eee: 183a adds r2, r7, r0 8006ef0: 8812 ldrh r2, [r2, #0] 8006ef2: 430a orrs r2, r1 8006ef4: 801a strh r2, [r3, #0] huart->Instance->BRR = brrtemp; 8006ef6: 687b ldr r3, [r7, #4] 8006ef8: 681b ldr r3, [r3, #0] 8006efa: 183a adds r2, r7, r0 8006efc: 8812 ldrh r2, [r2, #0] 8006efe: 60da str r2, [r3, #12] 8006f00: e060 b.n 8006fc4 } else { ret = HAL_ERROR; 8006f02: 231e movs r3, #30 8006f04: 18fb adds r3, r7, r3 8006f06: 2201 movs r2, #1 8006f08: 701a strb r2, [r3, #0] 8006f0a: e05b b.n 8006fc4 } } } else { switch (clocksource) 8006f0c: 231f movs r3, #31 8006f0e: 18fb adds r3, r7, r3 8006f10: 781b ldrb r3, [r3, #0] 8006f12: 2b08 cmp r3, #8 8006f14: d01f beq.n 8006f56 8006f16: dc22 bgt.n 8006f5e 8006f18: 2b04 cmp r3, #4 8006f1a: d017 beq.n 8006f4c 8006f1c: dc1f bgt.n 8006f5e 8006f1e: 2b00 cmp r3, #0 8006f20: d002 beq.n 8006f28 8006f22: 2b02 cmp r3, #2 8006f24: d005 beq.n 8006f32 8006f26: e01a b.n 8006f5e { case UART_CLOCKSOURCE_PCLK1: pclk = HAL_RCC_GetPCLK1Freq(); 8006f28: f7fe f990 bl 800524c 8006f2c: 0003 movs r3, r0 8006f2e: 61bb str r3, [r7, #24] break; 8006f30: e01c b.n 8006f6c case UART_CLOCKSOURCE_HSI: pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U)); 8006f32: 4b33 ldr r3, [pc, #204] @ (8007000 ) 8006f34: 681b ldr r3, [r3, #0] 8006f36: 095b lsrs r3, r3, #5 8006f38: 2207 movs r2, #7 8006f3a: 4013 ands r3, r2 8006f3c: 3301 adds r3, #1 8006f3e: 0019 movs r1, r3 8006f40: 4831 ldr r0, [pc, #196] @ (8007008 ) 8006f42: f7f9 f8e1 bl 8000108 <__udivsi3> 8006f46: 0003 movs r3, r0 8006f48: 61bb str r3, [r7, #24] break; 8006f4a: e00f b.n 8006f6c case UART_CLOCKSOURCE_SYSCLK: pclk = HAL_RCC_GetSysClockFreq(); 8006f4c: f7fe f910 bl 8005170 8006f50: 0003 movs r3, r0 8006f52: 61bb str r3, [r7, #24] break; 8006f54: e00a b.n 8006f6c case UART_CLOCKSOURCE_LSE: pclk = (uint32_t) LSE_VALUE; 8006f56: 2380 movs r3, #128 @ 0x80 8006f58: 021b lsls r3, r3, #8 8006f5a: 61bb str r3, [r7, #24] break; 8006f5c: e006 b.n 8006f6c default: pclk = 0U; 8006f5e: 2300 movs r3, #0 8006f60: 61bb str r3, [r7, #24] ret = HAL_ERROR; 8006f62: 231e movs r3, #30 8006f64: 18fb adds r3, r7, r3 8006f66: 2201 movs r2, #1 8006f68: 701a strb r2, [r3, #0] break; 8006f6a: 46c0 nop @ (mov r8, r8) } if (pclk != 0U) 8006f6c: 69bb ldr r3, [r7, #24] 8006f6e: 2b00 cmp r3, #0 8006f70: d028 beq.n 8006fc4 { /* USARTDIV must be greater than or equal to 0d16 */ usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); 8006f72: 687b ldr r3, [r7, #4] 8006f74: 6a5a ldr r2, [r3, #36] @ 0x24 8006f76: 4b25 ldr r3, [pc, #148] @ (800700c ) 8006f78: 0052 lsls r2, r2, #1 8006f7a: 5ad3 ldrh r3, [r2, r3] 8006f7c: 0019 movs r1, r3 8006f7e: 69b8 ldr r0, [r7, #24] 8006f80: f7f9 f8c2 bl 8000108 <__udivsi3> 8006f84: 0003 movs r3, r0 8006f86: 001a movs r2, r3 8006f88: 687b ldr r3, [r7, #4] 8006f8a: 685b ldr r3, [r3, #4] 8006f8c: 085b lsrs r3, r3, #1 8006f8e: 18d2 adds r2, r2, r3 8006f90: 687b ldr r3, [r7, #4] 8006f92: 685b ldr r3, [r3, #4] 8006f94: 0019 movs r1, r3 8006f96: 0010 movs r0, r2 8006f98: f7f9 f8b6 bl 8000108 <__udivsi3> 8006f9c: 0003 movs r3, r0 8006f9e: 613b str r3, [r7, #16] if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) 8006fa0: 693b ldr r3, [r7, #16] 8006fa2: 2b0f cmp r3, #15 8006fa4: d90a bls.n 8006fbc 8006fa6: 693a ldr r2, [r7, #16] 8006fa8: 2380 movs r3, #128 @ 0x80 8006faa: 025b lsls r3, r3, #9 8006fac: 429a cmp r2, r3 8006fae: d205 bcs.n 8006fbc { huart->Instance->BRR = (uint16_t)usartdiv; 8006fb0: 693b ldr r3, [r7, #16] 8006fb2: b29a uxth r2, r3 8006fb4: 687b ldr r3, [r7, #4] 8006fb6: 681b ldr r3, [r3, #0] 8006fb8: 60da str r2, [r3, #12] 8006fba: e003 b.n 8006fc4 } else { ret = HAL_ERROR; 8006fbc: 231e movs r3, #30 8006fbe: 18fb adds r3, r7, r3 8006fc0: 2201 movs r2, #1 8006fc2: 701a strb r2, [r3, #0] } } } /* Initialize the number of data to process during RX/TX ISR execution */ huart->NbTxDataToProcess = 1; 8006fc4: 687b ldr r3, [r7, #4] 8006fc6: 226a movs r2, #106 @ 0x6a 8006fc8: 2101 movs r1, #1 8006fca: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = 1; 8006fcc: 687b ldr r3, [r7, #4] 8006fce: 2268 movs r2, #104 @ 0x68 8006fd0: 2101 movs r1, #1 8006fd2: 5299 strh r1, [r3, r2] /* Clear ISR function pointers */ huart->RxISR = NULL; 8006fd4: 687b ldr r3, [r7, #4] 8006fd6: 2200 movs r2, #0 8006fd8: 675a str r2, [r3, #116] @ 0x74 huart->TxISR = NULL; 8006fda: 687b ldr r3, [r7, #4] 8006fdc: 2200 movs r2, #0 8006fde: 679a str r2, [r3, #120] @ 0x78 return ret; 8006fe0: 231e movs r3, #30 8006fe2: 18fb adds r3, r7, r3 8006fe4: 781b ldrb r3, [r3, #0] } 8006fe6: 0018 movs r0, r3 8006fe8: 46bd mov sp, r7 8006fea: b008 add sp, #32 8006fec: bd80 pop {r7, pc} 8006fee: 46c0 nop @ (mov r8, r8) 8006ff0: cfff69f3 .word 0xcfff69f3 8006ff4: ffffcfff .word 0xffffcfff 8006ff8: 11fff4ff .word 0x11fff4ff 8006ffc: 40013800 .word 0x40013800 8007000: 40021000 .word 0x40021000 8007004: 40004400 .word 0x40004400 8007008: 02dc6c00 .word 0x02dc6c00 800700c: 08007e64 .word 0x08007e64 08007010 : * @brief Configure the UART peripheral advanced features. * @param huart UART handle. * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) { 8007010: b580 push {r7, lr} 8007012: b082 sub sp, #8 8007014: af00 add r7, sp, #0 8007016: 6078 str r0, [r7, #4] /* Check whether the set of advanced features to configure is properly set */ assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); /* if required, configure RX/TX pins swap */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) 8007018: 687b ldr r3, [r7, #4] 800701a: 6a9b ldr r3, [r3, #40] @ 0x28 800701c: 2208 movs r2, #8 800701e: 4013 ands r3, r2 8007020: d00b beq.n 800703a { assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); 8007022: 687b ldr r3, [r7, #4] 8007024: 681b ldr r3, [r3, #0] 8007026: 685b ldr r3, [r3, #4] 8007028: 4a4a ldr r2, [pc, #296] @ (8007154 ) 800702a: 4013 ands r3, r2 800702c: 0019 movs r1, r3 800702e: 687b ldr r3, [r7, #4] 8007030: 6b9a ldr r2, [r3, #56] @ 0x38 8007032: 687b ldr r3, [r7, #4] 8007034: 681b ldr r3, [r3, #0] 8007036: 430a orrs r2, r1 8007038: 605a str r2, [r3, #4] } /* if required, configure TX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) 800703a: 687b ldr r3, [r7, #4] 800703c: 6a9b ldr r3, [r3, #40] @ 0x28 800703e: 2201 movs r2, #1 8007040: 4013 ands r3, r2 8007042: d00b beq.n 800705c { assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); 8007044: 687b ldr r3, [r7, #4] 8007046: 681b ldr r3, [r3, #0] 8007048: 685b ldr r3, [r3, #4] 800704a: 4a43 ldr r2, [pc, #268] @ (8007158 ) 800704c: 4013 ands r3, r2 800704e: 0019 movs r1, r3 8007050: 687b ldr r3, [r7, #4] 8007052: 6ada ldr r2, [r3, #44] @ 0x2c 8007054: 687b ldr r3, [r7, #4] 8007056: 681b ldr r3, [r3, #0] 8007058: 430a orrs r2, r1 800705a: 605a str r2, [r3, #4] } /* if required, configure RX pin active level inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) 800705c: 687b ldr r3, [r7, #4] 800705e: 6a9b ldr r3, [r3, #40] @ 0x28 8007060: 2202 movs r2, #2 8007062: 4013 ands r3, r2 8007064: d00b beq.n 800707e { assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); 8007066: 687b ldr r3, [r7, #4] 8007068: 681b ldr r3, [r3, #0] 800706a: 685b ldr r3, [r3, #4] 800706c: 4a3b ldr r2, [pc, #236] @ (800715c ) 800706e: 4013 ands r3, r2 8007070: 0019 movs r1, r3 8007072: 687b ldr r3, [r7, #4] 8007074: 6b1a ldr r2, [r3, #48] @ 0x30 8007076: 687b ldr r3, [r7, #4] 8007078: 681b ldr r3, [r3, #0] 800707a: 430a orrs r2, r1 800707c: 605a str r2, [r3, #4] } /* if required, configure data inversion */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) 800707e: 687b ldr r3, [r7, #4] 8007080: 6a9b ldr r3, [r3, #40] @ 0x28 8007082: 2204 movs r2, #4 8007084: 4013 ands r3, r2 8007086: d00b beq.n 80070a0 { assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); 8007088: 687b ldr r3, [r7, #4] 800708a: 681b ldr r3, [r3, #0] 800708c: 685b ldr r3, [r3, #4] 800708e: 4a34 ldr r2, [pc, #208] @ (8007160 ) 8007090: 4013 ands r3, r2 8007092: 0019 movs r1, r3 8007094: 687b ldr r3, [r7, #4] 8007096: 6b5a ldr r2, [r3, #52] @ 0x34 8007098: 687b ldr r3, [r7, #4] 800709a: 681b ldr r3, [r3, #0] 800709c: 430a orrs r2, r1 800709e: 605a str r2, [r3, #4] } /* if required, configure RX overrun detection disabling */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) 80070a0: 687b ldr r3, [r7, #4] 80070a2: 6a9b ldr r3, [r3, #40] @ 0x28 80070a4: 2210 movs r2, #16 80070a6: 4013 ands r3, r2 80070a8: d00b beq.n 80070c2 { assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); 80070aa: 687b ldr r3, [r7, #4] 80070ac: 681b ldr r3, [r3, #0] 80070ae: 689b ldr r3, [r3, #8] 80070b0: 4a2c ldr r2, [pc, #176] @ (8007164 ) 80070b2: 4013 ands r3, r2 80070b4: 0019 movs r1, r3 80070b6: 687b ldr r3, [r7, #4] 80070b8: 6bda ldr r2, [r3, #60] @ 0x3c 80070ba: 687b ldr r3, [r7, #4] 80070bc: 681b ldr r3, [r3, #0] 80070be: 430a orrs r2, r1 80070c0: 609a str r2, [r3, #8] } #if defined(HAL_DMA_MODULE_ENABLED) /* if required, configure DMA disabling on reception error */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) 80070c2: 687b ldr r3, [r7, #4] 80070c4: 6a9b ldr r3, [r3, #40] @ 0x28 80070c6: 2220 movs r2, #32 80070c8: 4013 ands r3, r2 80070ca: d00b beq.n 80070e4 { assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); 80070cc: 687b ldr r3, [r7, #4] 80070ce: 681b ldr r3, [r3, #0] 80070d0: 689b ldr r3, [r3, #8] 80070d2: 4a25 ldr r2, [pc, #148] @ (8007168 ) 80070d4: 4013 ands r3, r2 80070d6: 0019 movs r1, r3 80070d8: 687b ldr r3, [r7, #4] 80070da: 6c1a ldr r2, [r3, #64] @ 0x40 80070dc: 687b ldr r3, [r7, #4] 80070de: 681b ldr r3, [r3, #0] 80070e0: 430a orrs r2, r1 80070e2: 609a str r2, [r3, #8] } #endif /* HAL_DMA_MODULE_ENABLED */ /* if required, configure auto Baud rate detection scheme */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) 80070e4: 687b ldr r3, [r7, #4] 80070e6: 6a9b ldr r3, [r3, #40] @ 0x28 80070e8: 2240 movs r2, #64 @ 0x40 80070ea: 4013 ands r3, r2 80070ec: d01d beq.n 800712a { assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); 80070ee: 687b ldr r3, [r7, #4] 80070f0: 681b ldr r3, [r3, #0] 80070f2: 685b ldr r3, [r3, #4] 80070f4: 4a1d ldr r2, [pc, #116] @ (800716c ) 80070f6: 4013 ands r3, r2 80070f8: 0019 movs r1, r3 80070fa: 687b ldr r3, [r7, #4] 80070fc: 6c5a ldr r2, [r3, #68] @ 0x44 80070fe: 687b ldr r3, [r7, #4] 8007100: 681b ldr r3, [r3, #0] 8007102: 430a orrs r2, r1 8007104: 605a str r2, [r3, #4] /* set auto Baudrate detection parameters if detection is enabled */ if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) 8007106: 687b ldr r3, [r7, #4] 8007108: 6c5a ldr r2, [r3, #68] @ 0x44 800710a: 2380 movs r3, #128 @ 0x80 800710c: 035b lsls r3, r3, #13 800710e: 429a cmp r2, r3 8007110: d10b bne.n 800712a { assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); 8007112: 687b ldr r3, [r7, #4] 8007114: 681b ldr r3, [r3, #0] 8007116: 685b ldr r3, [r3, #4] 8007118: 4a15 ldr r2, [pc, #84] @ (8007170 ) 800711a: 4013 ands r3, r2 800711c: 0019 movs r1, r3 800711e: 687b ldr r3, [r7, #4] 8007120: 6c9a ldr r2, [r3, #72] @ 0x48 8007122: 687b ldr r3, [r7, #4] 8007124: 681b ldr r3, [r3, #0] 8007126: 430a orrs r2, r1 8007128: 605a str r2, [r3, #4] } } /* if required, configure MSB first on communication line */ if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) 800712a: 687b ldr r3, [r7, #4] 800712c: 6a9b ldr r3, [r3, #40] @ 0x28 800712e: 2280 movs r2, #128 @ 0x80 8007130: 4013 ands r3, r2 8007132: d00b beq.n 800714c { assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); 8007134: 687b ldr r3, [r7, #4] 8007136: 681b ldr r3, [r3, #0] 8007138: 685b ldr r3, [r3, #4] 800713a: 4a0e ldr r2, [pc, #56] @ (8007174 ) 800713c: 4013 ands r3, r2 800713e: 0019 movs r1, r3 8007140: 687b ldr r3, [r7, #4] 8007142: 6cda ldr r2, [r3, #76] @ 0x4c 8007144: 687b ldr r3, [r7, #4] 8007146: 681b ldr r3, [r3, #0] 8007148: 430a orrs r2, r1 800714a: 605a str r2, [r3, #4] } } 800714c: 46c0 nop @ (mov r8, r8) 800714e: 46bd mov sp, r7 8007150: b002 add sp, #8 8007152: bd80 pop {r7, pc} 8007154: ffff7fff .word 0xffff7fff 8007158: fffdffff .word 0xfffdffff 800715c: fffeffff .word 0xfffeffff 8007160: fffbffff .word 0xfffbffff 8007164: ffffefff .word 0xffffefff 8007168: ffffdfff .word 0xffffdfff 800716c: ffefffff .word 0xffefffff 8007170: ff9fffff .word 0xff9fffff 8007174: fff7ffff .word 0xfff7ffff 08007178 : * @brief Check the UART Idle State. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) { 8007178: b580 push {r7, lr} 800717a: b092 sub sp, #72 @ 0x48 800717c: af02 add r7, sp, #8 800717e: 6078 str r0, [r7, #4] uint32_t tickstart; /* Initialize the UART ErrorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; 8007180: 687b ldr r3, [r7, #4] 8007182: 2290 movs r2, #144 @ 0x90 8007184: 2100 movs r1, #0 8007186: 5099 str r1, [r3, r2] /* Init tickstart for timeout management */ tickstart = HAL_GetTick(); 8007188: f7fc ffa6 bl 80040d8 800718c: 0003 movs r3, r0 800718e: 63fb str r3, [r7, #60] @ 0x3c /* Check if the Transmitter is enabled */ if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) 8007190: 687b ldr r3, [r7, #4] 8007192: 681b ldr r3, [r3, #0] 8007194: 681b ldr r3, [r3, #0] 8007196: 2208 movs r2, #8 8007198: 4013 ands r3, r2 800719a: 2b08 cmp r3, #8 800719c: d12d bne.n 80071fa { /* Wait until TEACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 800719e: 6bfb ldr r3, [r7, #60] @ 0x3c 80071a0: 2280 movs r2, #128 @ 0x80 80071a2: 0391 lsls r1, r2, #14 80071a4: 6878 ldr r0, [r7, #4] 80071a6: 4a47 ldr r2, [pc, #284] @ (80072c4 ) 80071a8: 9200 str r2, [sp, #0] 80071aa: 2200 movs r2, #0 80071ac: f000 f88e bl 80072cc 80071b0: 1e03 subs r3, r0, #0 80071b2: d022 beq.n 80071fa */ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) { uint32_t result; __ASM volatile ("MRS %0, primask" : "=r" (result) ); 80071b4: f3ef 8310 mrs r3, PRIMASK 80071b8: 627b str r3, [r7, #36] @ 0x24 return(result); 80071ba: 6a7b ldr r3, [r7, #36] @ 0x24 { /* Disable TXE interrupt for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); 80071bc: 63bb str r3, [r7, #56] @ 0x38 80071be: 2301 movs r3, #1 80071c0: 62bb str r3, [r7, #40] @ 0x28 \details Assigns the given value to the Priority Mask Register. \param [in] priMask Priority Mask */ __STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) { __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80071c2: 6abb ldr r3, [r7, #40] @ 0x28 80071c4: f383 8810 msr PRIMASK, r3 } 80071c8: 46c0 nop @ (mov r8, r8) 80071ca: 687b ldr r3, [r7, #4] 80071cc: 681b ldr r3, [r3, #0] 80071ce: 681a ldr r2, [r3, #0] 80071d0: 687b ldr r3, [r7, #4] 80071d2: 681b ldr r3, [r3, #0] 80071d4: 2180 movs r1, #128 @ 0x80 80071d6: 438a bics r2, r1 80071d8: 601a str r2, [r3, #0] 80071da: 6bbb ldr r3, [r7, #56] @ 0x38 80071dc: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80071de: 6afb ldr r3, [r7, #44] @ 0x2c 80071e0: f383 8810 msr PRIMASK, r3 } 80071e4: 46c0 nop @ (mov r8, r8) huart->gState = HAL_UART_STATE_READY; 80071e6: 687b ldr r3, [r7, #4] 80071e8: 2288 movs r2, #136 @ 0x88 80071ea: 2120 movs r1, #32 80071ec: 5099 str r1, [r3, r2] __HAL_UNLOCK(huart); 80071ee: 687b ldr r3, [r7, #4] 80071f0: 2284 movs r2, #132 @ 0x84 80071f2: 2100 movs r1, #0 80071f4: 5499 strb r1, [r3, r2] /* Timeout occurred */ return HAL_TIMEOUT; 80071f6: 2303 movs r3, #3 80071f8: e060 b.n 80072bc } } /* Check if the Receiver is enabled */ if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) 80071fa: 687b ldr r3, [r7, #4] 80071fc: 681b ldr r3, [r3, #0] 80071fe: 681b ldr r3, [r3, #0] 8007200: 2204 movs r2, #4 8007202: 4013 ands r3, r2 8007204: 2b04 cmp r3, #4 8007206: d146 bne.n 8007296 { /* Wait until REACK flag is set */ if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) 8007208: 6bfb ldr r3, [r7, #60] @ 0x3c 800720a: 2280 movs r2, #128 @ 0x80 800720c: 03d1 lsls r1, r2, #15 800720e: 6878 ldr r0, [r7, #4] 8007210: 4a2c ldr r2, [pc, #176] @ (80072c4 ) 8007212: 9200 str r2, [sp, #0] 8007214: 2200 movs r2, #0 8007216: f000 f859 bl 80072cc 800721a: 1e03 subs r3, r0, #0 800721c: d03b beq.n 8007296 __ASM volatile ("MRS %0, primask" : "=r" (result) ); 800721e: f3ef 8310 mrs r3, PRIMASK 8007222: 60fb str r3, [r7, #12] return(result); 8007224: 68fb ldr r3, [r7, #12] { /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8007226: 637b str r3, [r7, #52] @ 0x34 8007228: 2301 movs r3, #1 800722a: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800722c: 693b ldr r3, [r7, #16] 800722e: f383 8810 msr PRIMASK, r3 } 8007232: 46c0 nop @ (mov r8, r8) 8007234: 687b ldr r3, [r7, #4] 8007236: 681b ldr r3, [r3, #0] 8007238: 681a ldr r2, [r3, #0] 800723a: 687b ldr r3, [r7, #4] 800723c: 681b ldr r3, [r3, #0] 800723e: 4922 ldr r1, [pc, #136] @ (80072c8 ) 8007240: 400a ands r2, r1 8007242: 601a str r2, [r3, #0] 8007244: 6b7b ldr r3, [r7, #52] @ 0x34 8007246: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8007248: 697b ldr r3, [r7, #20] 800724a: f383 8810 msr PRIMASK, r3 } 800724e: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); 8007250: f3ef 8310 mrs r3, PRIMASK 8007254: 61bb str r3, [r7, #24] return(result); 8007256: 69bb ldr r3, [r7, #24] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 8007258: 633b str r3, [r7, #48] @ 0x30 800725a: 2301 movs r3, #1 800725c: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800725e: 69fb ldr r3, [r7, #28] 8007260: f383 8810 msr PRIMASK, r3 } 8007264: 46c0 nop @ (mov r8, r8) 8007266: 687b ldr r3, [r7, #4] 8007268: 681b ldr r3, [r3, #0] 800726a: 689a ldr r2, [r3, #8] 800726c: 687b ldr r3, [r7, #4] 800726e: 681b ldr r3, [r3, #0] 8007270: 2101 movs r1, #1 8007272: 438a bics r2, r1 8007274: 609a str r2, [r3, #8] 8007276: 6b3b ldr r3, [r7, #48] @ 0x30 8007278: 623b str r3, [r7, #32] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800727a: 6a3b ldr r3, [r7, #32] 800727c: f383 8810 msr PRIMASK, r3 } 8007280: 46c0 nop @ (mov r8, r8) huart->RxState = HAL_UART_STATE_READY; 8007282: 687b ldr r3, [r7, #4] 8007284: 228c movs r2, #140 @ 0x8c 8007286: 2120 movs r1, #32 8007288: 5099 str r1, [r3, r2] __HAL_UNLOCK(huart); 800728a: 687b ldr r3, [r7, #4] 800728c: 2284 movs r2, #132 @ 0x84 800728e: 2100 movs r1, #0 8007290: 5499 strb r1, [r3, r2] /* Timeout occurred */ return HAL_TIMEOUT; 8007292: 2303 movs r3, #3 8007294: e012 b.n 80072bc } } /* Initialize the UART State */ huart->gState = HAL_UART_STATE_READY; 8007296: 687b ldr r3, [r7, #4] 8007298: 2288 movs r2, #136 @ 0x88 800729a: 2120 movs r1, #32 800729c: 5099 str r1, [r3, r2] huart->RxState = HAL_UART_STATE_READY; 800729e: 687b ldr r3, [r7, #4] 80072a0: 228c movs r2, #140 @ 0x8c 80072a2: 2120 movs r1, #32 80072a4: 5099 str r1, [r3, r2] huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 80072a6: 687b ldr r3, [r7, #4] 80072a8: 2200 movs r2, #0 80072aa: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 80072ac: 687b ldr r3, [r7, #4] 80072ae: 2200 movs r2, #0 80072b0: 671a str r2, [r3, #112] @ 0x70 __HAL_UNLOCK(huart); 80072b2: 687b ldr r3, [r7, #4] 80072b4: 2284 movs r2, #132 @ 0x84 80072b6: 2100 movs r1, #0 80072b8: 5499 strb r1, [r3, r2] return HAL_OK; 80072ba: 2300 movs r3, #0 } 80072bc: 0018 movs r0, r3 80072be: 46bd mov sp, r7 80072c0: b010 add sp, #64 @ 0x40 80072c2: bd80 pop {r7, pc} 80072c4: 01ffffff .word 0x01ffffff 80072c8: fffffedf .word 0xfffffedf 080072cc : * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout) { 80072cc: b580 push {r7, lr} 80072ce: b084 sub sp, #16 80072d0: af00 add r7, sp, #0 80072d2: 60f8 str r0, [r7, #12] 80072d4: 60b9 str r1, [r7, #8] 80072d6: 603b str r3, [r7, #0] 80072d8: 1dfb adds r3, r7, #7 80072da: 701a strb r2, [r3, #0] /* Wait until flag is set */ while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 80072dc: e051 b.n 8007382 { /* Check for the Timeout */ if (Timeout != HAL_MAX_DELAY) 80072de: 69bb ldr r3, [r7, #24] 80072e0: 3301 adds r3, #1 80072e2: d04e beq.n 8007382 { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) 80072e4: f7fc fef8 bl 80040d8 80072e8: 0002 movs r2, r0 80072ea: 683b ldr r3, [r7, #0] 80072ec: 1ad3 subs r3, r2, r3 80072ee: 69ba ldr r2, [r7, #24] 80072f0: 429a cmp r2, r3 80072f2: d302 bcc.n 80072fa 80072f4: 69bb ldr r3, [r7, #24] 80072f6: 2b00 cmp r3, #0 80072f8: d101 bne.n 80072fe { return HAL_TIMEOUT; 80072fa: 2303 movs r3, #3 80072fc: e051 b.n 80073a2 } if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) 80072fe: 68fb ldr r3, [r7, #12] 8007300: 681b ldr r3, [r3, #0] 8007302: 681b ldr r3, [r3, #0] 8007304: 2204 movs r2, #4 8007306: 4013 ands r3, r2 8007308: d03b beq.n 8007382 800730a: 68bb ldr r3, [r7, #8] 800730c: 2b80 cmp r3, #128 @ 0x80 800730e: d038 beq.n 8007382 8007310: 68bb ldr r3, [r7, #8] 8007312: 2b40 cmp r3, #64 @ 0x40 8007314: d035 beq.n 8007382 { if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) 8007316: 68fb ldr r3, [r7, #12] 8007318: 681b ldr r3, [r3, #0] 800731a: 69db ldr r3, [r3, #28] 800731c: 2208 movs r2, #8 800731e: 4013 ands r3, r2 8007320: 2b08 cmp r3, #8 8007322: d111 bne.n 8007348 { /* Clear Overrun Error flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); 8007324: 68fb ldr r3, [r7, #12] 8007326: 681b ldr r3, [r3, #0] 8007328: 2208 movs r2, #8 800732a: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 800732c: 68fb ldr r3, [r7, #12] 800732e: 0018 movs r0, r3 8007330: f000 f922 bl 8007578 huart->ErrorCode = HAL_UART_ERROR_ORE; 8007334: 68fb ldr r3, [r7, #12] 8007336: 2290 movs r2, #144 @ 0x90 8007338: 2108 movs r1, #8 800733a: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 800733c: 68fb ldr r3, [r7, #12] 800733e: 2284 movs r2, #132 @ 0x84 8007340: 2100 movs r1, #0 8007342: 5499 strb r1, [r3, r2] return HAL_ERROR; 8007344: 2301 movs r3, #1 8007346: e02c b.n 80073a2 } if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) 8007348: 68fb ldr r3, [r7, #12] 800734a: 681b ldr r3, [r3, #0] 800734c: 69da ldr r2, [r3, #28] 800734e: 2380 movs r3, #128 @ 0x80 8007350: 011b lsls r3, r3, #4 8007352: 401a ands r2, r3 8007354: 2380 movs r3, #128 @ 0x80 8007356: 011b lsls r3, r3, #4 8007358: 429a cmp r2, r3 800735a: d112 bne.n 8007382 { /* Clear Receiver Timeout flag*/ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); 800735c: 68fb ldr r3, [r7, #12] 800735e: 681b ldr r3, [r3, #0] 8007360: 2280 movs r2, #128 @ 0x80 8007362: 0112 lsls r2, r2, #4 8007364: 621a str r2, [r3, #32] /* Blocking error : transfer is aborted Set the UART state ready to be able to start again the process, Disable Rx Interrupts if ongoing */ UART_EndRxTransfer(huart); 8007366: 68fb ldr r3, [r7, #12] 8007368: 0018 movs r0, r3 800736a: f000 f905 bl 8007578 huart->ErrorCode = HAL_UART_ERROR_RTO; 800736e: 68fb ldr r3, [r7, #12] 8007370: 2290 movs r2, #144 @ 0x90 8007372: 2120 movs r1, #32 8007374: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 8007376: 68fb ldr r3, [r7, #12] 8007378: 2284 movs r2, #132 @ 0x84 800737a: 2100 movs r1, #0 800737c: 5499 strb r1, [r3, r2] return HAL_TIMEOUT; 800737e: 2303 movs r3, #3 8007380: e00f b.n 80073a2 while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) 8007382: 68fb ldr r3, [r7, #12] 8007384: 681b ldr r3, [r3, #0] 8007386: 69db ldr r3, [r3, #28] 8007388: 68ba ldr r2, [r7, #8] 800738a: 4013 ands r3, r2 800738c: 68ba ldr r2, [r7, #8] 800738e: 1ad3 subs r3, r2, r3 8007390: 425a negs r2, r3 8007392: 4153 adcs r3, r2 8007394: b2db uxtb r3, r3 8007396: 001a movs r2, r3 8007398: 1dfb adds r3, r7, #7 800739a: 781b ldrb r3, [r3, #0] 800739c: 429a cmp r2, r3 800739e: d09e beq.n 80072de } } } } return HAL_OK; 80073a0: 2300 movs r3, #0 } 80073a2: 0018 movs r0, r3 80073a4: 46bd mov sp, r7 80073a6: b004 add sp, #16 80073a8: bd80 pop {r7, pc} ... 080073ac : * @param pData Pointer to data buffer (u8 or u16 data elements). * @param Size Amount of data elements (u8 or u16) to be received. * @retval HAL status */ HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 80073ac: b580 push {r7, lr} 80073ae: b090 sub sp, #64 @ 0x40 80073b0: af00 add r7, sp, #0 80073b2: 60f8 str r0, [r7, #12] 80073b4: 60b9 str r1, [r7, #8] 80073b6: 1dbb adds r3, r7, #6 80073b8: 801a strh r2, [r3, #0] huart->pRxBuffPtr = pData; 80073ba: 68fb ldr r3, [r7, #12] 80073bc: 68ba ldr r2, [r7, #8] 80073be: 659a str r2, [r3, #88] @ 0x58 huart->RxXferSize = Size; 80073c0: 68fb ldr r3, [r7, #12] 80073c2: 1dba adds r2, r7, #6 80073c4: 215c movs r1, #92 @ 0x5c 80073c6: 8812 ldrh r2, [r2, #0] 80073c8: 525a strh r2, [r3, r1] huart->ErrorCode = HAL_UART_ERROR_NONE; 80073ca: 68fb ldr r3, [r7, #12] 80073cc: 2290 movs r2, #144 @ 0x90 80073ce: 2100 movs r1, #0 80073d0: 5099 str r1, [r3, r2] huart->RxState = HAL_UART_STATE_BUSY_RX; 80073d2: 68fb ldr r3, [r7, #12] 80073d4: 228c movs r2, #140 @ 0x8c 80073d6: 2122 movs r1, #34 @ 0x22 80073d8: 5099 str r1, [r3, r2] if (huart->hdmarx != NULL) 80073da: 68fb ldr r3, [r7, #12] 80073dc: 2280 movs r2, #128 @ 0x80 80073de: 589b ldr r3, [r3, r2] 80073e0: 2b00 cmp r3, #0 80073e2: d02d beq.n 8007440 { /* Set the UART DMA transfer complete callback */ huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; 80073e4: 68fb ldr r3, [r7, #12] 80073e6: 2280 movs r2, #128 @ 0x80 80073e8: 589b ldr r3, [r3, r2] 80073ea: 4a40 ldr r2, [pc, #256] @ (80074ec ) 80073ec: 62da str r2, [r3, #44] @ 0x2c /* Set the UART DMA Half transfer complete callback */ huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; 80073ee: 68fb ldr r3, [r7, #12] 80073f0: 2280 movs r2, #128 @ 0x80 80073f2: 589b ldr r3, [r3, r2] 80073f4: 4a3e ldr r2, [pc, #248] @ (80074f0 ) 80073f6: 631a str r2, [r3, #48] @ 0x30 /* Set the DMA error callback */ huart->hdmarx->XferErrorCallback = UART_DMAError; 80073f8: 68fb ldr r3, [r7, #12] 80073fa: 2280 movs r2, #128 @ 0x80 80073fc: 589b ldr r3, [r3, r2] 80073fe: 4a3d ldr r2, [pc, #244] @ (80074f4 ) 8007400: 635a str r2, [r3, #52] @ 0x34 /* Set the DMA abort callback */ huart->hdmarx->XferAbortCallback = NULL; 8007402: 68fb ldr r3, [r7, #12] 8007404: 2280 movs r2, #128 @ 0x80 8007406: 589b ldr r3, [r3, r2] 8007408: 2200 movs r2, #0 800740a: 639a str r2, [r3, #56] @ 0x38 /* Enable the DMA channel */ if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK) 800740c: 68fb ldr r3, [r7, #12] 800740e: 2280 movs r2, #128 @ 0x80 8007410: 5898 ldr r0, [r3, r2] 8007412: 68fb ldr r3, [r7, #12] 8007414: 681b ldr r3, [r3, #0] 8007416: 3324 adds r3, #36 @ 0x24 8007418: 0019 movs r1, r3 800741a: 68fb ldr r3, [r7, #12] 800741c: 6d9b ldr r3, [r3, #88] @ 0x58 800741e: 001a movs r2, r3 8007420: 1dbb adds r3, r7, #6 8007422: 881b ldrh r3, [r3, #0] 8007424: f7fd f80c bl 8004440 8007428: 1e03 subs r3, r0, #0 800742a: d009 beq.n 8007440 { /* Set error code to DMA */ huart->ErrorCode = HAL_UART_ERROR_DMA; 800742c: 68fb ldr r3, [r7, #12] 800742e: 2290 movs r2, #144 @ 0x90 8007430: 2110 movs r1, #16 8007432: 5099 str r1, [r3, r2] /* Restore huart->RxState to ready */ huart->RxState = HAL_UART_STATE_READY; 8007434: 68fb ldr r3, [r7, #12] 8007436: 228c movs r2, #140 @ 0x8c 8007438: 2120 movs r1, #32 800743a: 5099 str r1, [r3, r2] return HAL_ERROR; 800743c: 2301 movs r3, #1 800743e: e050 b.n 80074e2 } } /* Enable the UART Parity Error Interrupt */ if (huart->Init.Parity != UART_PARITY_NONE) 8007440: 68fb ldr r3, [r7, #12] 8007442: 691b ldr r3, [r3, #16] 8007444: 2b00 cmp r3, #0 8007446: d019 beq.n 800747c __ASM volatile ("MRS %0, primask" : "=r" (result) ); 8007448: f3ef 8310 mrs r3, PRIMASK 800744c: 62bb str r3, [r7, #40] @ 0x28 return(result); 800744e: 6abb ldr r3, [r7, #40] @ 0x28 { ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); 8007450: 63fb str r3, [r7, #60] @ 0x3c 8007452: 2301 movs r3, #1 8007454: 62fb str r3, [r7, #44] @ 0x2c __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8007456: 6afb ldr r3, [r7, #44] @ 0x2c 8007458: f383 8810 msr PRIMASK, r3 } 800745c: 46c0 nop @ (mov r8, r8) 800745e: 68fb ldr r3, [r7, #12] 8007460: 681b ldr r3, [r3, #0] 8007462: 681a ldr r2, [r3, #0] 8007464: 68fb ldr r3, [r7, #12] 8007466: 681b ldr r3, [r3, #0] 8007468: 2180 movs r1, #128 @ 0x80 800746a: 0049 lsls r1, r1, #1 800746c: 430a orrs r2, r1 800746e: 601a str r2, [r3, #0] 8007470: 6bfb ldr r3, [r7, #60] @ 0x3c 8007472: 633b str r3, [r7, #48] @ 0x30 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8007474: 6b3b ldr r3, [r7, #48] @ 0x30 8007476: f383 8810 msr PRIMASK, r3 } 800747a: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); 800747c: f3ef 8310 mrs r3, PRIMASK 8007480: 613b str r3, [r7, #16] return(result); 8007482: 693b ldr r3, [r7, #16] } /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); 8007484: 63bb str r3, [r7, #56] @ 0x38 8007486: 2301 movs r3, #1 8007488: 617b str r3, [r7, #20] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800748a: 697b ldr r3, [r7, #20] 800748c: f383 8810 msr PRIMASK, r3 } 8007490: 46c0 nop @ (mov r8, r8) 8007492: 68fb ldr r3, [r7, #12] 8007494: 681b ldr r3, [r3, #0] 8007496: 689a ldr r2, [r3, #8] 8007498: 68fb ldr r3, [r7, #12] 800749a: 681b ldr r3, [r3, #0] 800749c: 2101 movs r1, #1 800749e: 430a orrs r2, r1 80074a0: 609a str r2, [r3, #8] 80074a2: 6bbb ldr r3, [r7, #56] @ 0x38 80074a4: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80074a6: 69bb ldr r3, [r7, #24] 80074a8: f383 8810 msr PRIMASK, r3 } 80074ac: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); 80074ae: f3ef 8310 mrs r3, PRIMASK 80074b2: 61fb str r3, [r7, #28] return(result); 80074b4: 69fb ldr r3, [r7, #28] /* Enable the DMA transfer for the receiver request by setting the DMAR bit in the UART CR3 register */ ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80074b6: 637b str r3, [r7, #52] @ 0x34 80074b8: 2301 movs r3, #1 80074ba: 623b str r3, [r7, #32] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80074bc: 6a3b ldr r3, [r7, #32] 80074be: f383 8810 msr PRIMASK, r3 } 80074c2: 46c0 nop @ (mov r8, r8) 80074c4: 68fb ldr r3, [r7, #12] 80074c6: 681b ldr r3, [r3, #0] 80074c8: 689a ldr r2, [r3, #8] 80074ca: 68fb ldr r3, [r7, #12] 80074cc: 681b ldr r3, [r3, #0] 80074ce: 2140 movs r1, #64 @ 0x40 80074d0: 430a orrs r2, r1 80074d2: 609a str r2, [r3, #8] 80074d4: 6b7b ldr r3, [r7, #52] @ 0x34 80074d6: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80074d8: 6a7b ldr r3, [r7, #36] @ 0x24 80074da: f383 8810 msr PRIMASK, r3 } 80074de: 46c0 nop @ (mov r8, r8) return HAL_OK; 80074e0: 2300 movs r3, #0 } 80074e2: 0018 movs r0, r3 80074e4: 46bd mov sp, r7 80074e6: b010 add sp, #64 @ 0x40 80074e8: bd80 pop {r7, pc} 80074ea: 46c0 nop @ (mov r8, r8) 80074ec: 08007645 .word 0x08007645 80074f0: 080077ad .word 0x080077ad 80074f4: 0800782b .word 0x0800782b 080074f8 : * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) { 80074f8: b580 push {r7, lr} 80074fa: b08a sub sp, #40 @ 0x28 80074fc: af00 add r7, sp, #0 80074fe: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) ); 8007500: f3ef 8310 mrs r3, PRIMASK 8007504: 60bb str r3, [r7, #8] return(result); 8007506: 68bb ldr r3, [r7, #8] /* Disable TXEIE, TCIE, TXFT interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); 8007508: 627b str r3, [r7, #36] @ 0x24 800750a: 2301 movs r3, #1 800750c: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800750e: 68fb ldr r3, [r7, #12] 8007510: f383 8810 msr PRIMASK, r3 } 8007514: 46c0 nop @ (mov r8, r8) 8007516: 687b ldr r3, [r7, #4] 8007518: 681b ldr r3, [r3, #0] 800751a: 681a ldr r2, [r3, #0] 800751c: 687b ldr r3, [r7, #4] 800751e: 681b ldr r3, [r3, #0] 8007520: 21c0 movs r1, #192 @ 0xc0 8007522: 438a bics r2, r1 8007524: 601a str r2, [r3, #0] 8007526: 6a7b ldr r3, [r7, #36] @ 0x24 8007528: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800752a: 693b ldr r3, [r7, #16] 800752c: f383 8810 msr PRIMASK, r3 } 8007530: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); 8007532: f3ef 8310 mrs r3, PRIMASK 8007536: 617b str r3, [r7, #20] return(result); 8007538: 697b ldr r3, [r7, #20] ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); 800753a: 623b str r3, [r7, #32] 800753c: 2301 movs r3, #1 800753e: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8007540: 69bb ldr r3, [r7, #24] 8007542: f383 8810 msr PRIMASK, r3 } 8007546: 46c0 nop @ (mov r8, r8) 8007548: 687b ldr r3, [r7, #4] 800754a: 681b ldr r3, [r3, #0] 800754c: 689a ldr r2, [r3, #8] 800754e: 687b ldr r3, [r7, #4] 8007550: 681b ldr r3, [r3, #0] 8007552: 4908 ldr r1, [pc, #32] @ (8007574 ) 8007554: 400a ands r2, r1 8007556: 609a str r2, [r3, #8] 8007558: 6a3b ldr r3, [r7, #32] 800755a: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800755c: 69fb ldr r3, [r7, #28] 800755e: f383 8810 msr PRIMASK, r3 } 8007562: 46c0 nop @ (mov r8, r8) /* At end of Tx process, restore huart->gState to Ready */ huart->gState = HAL_UART_STATE_READY; 8007564: 687b ldr r3, [r7, #4] 8007566: 2288 movs r2, #136 @ 0x88 8007568: 2120 movs r1, #32 800756a: 5099 str r1, [r3, r2] } 800756c: 46c0 nop @ (mov r8, r8) 800756e: 46bd mov sp, r7 8007570: b00a add sp, #40 @ 0x28 8007572: bd80 pop {r7, pc} 8007574: ff7fffff .word 0xff7fffff 08007578 : * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) { 8007578: b580 push {r7, lr} 800757a: b08e sub sp, #56 @ 0x38 800757c: af00 add r7, sp, #0 800757e: 6078 str r0, [r7, #4] __ASM volatile ("MRS %0, primask" : "=r" (result) ); 8007580: f3ef 8310 mrs r3, PRIMASK 8007584: 617b str r3, [r7, #20] return(result); 8007586: 697b ldr r3, [r7, #20] /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); 8007588: 637b str r3, [r7, #52] @ 0x34 800758a: 2301 movs r3, #1 800758c: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800758e: 69bb ldr r3, [r7, #24] 8007590: f383 8810 msr PRIMASK, r3 } 8007594: 46c0 nop @ (mov r8, r8) 8007596: 687b ldr r3, [r7, #4] 8007598: 681b ldr r3, [r3, #0] 800759a: 681a ldr r2, [r3, #0] 800759c: 687b ldr r3, [r7, #4] 800759e: 681b ldr r3, [r3, #0] 80075a0: 4926 ldr r1, [pc, #152] @ (800763c ) 80075a2: 400a ands r2, r1 80075a4: 601a str r2, [r3, #0] 80075a6: 6b7b ldr r3, [r7, #52] @ 0x34 80075a8: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80075aa: 69fb ldr r3, [r7, #28] 80075ac: f383 8810 msr PRIMASK, r3 } 80075b0: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); 80075b2: f3ef 8310 mrs r3, PRIMASK 80075b6: 623b str r3, [r7, #32] return(result); 80075b8: 6a3b ldr r3, [r7, #32] ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); 80075ba: 633b str r3, [r7, #48] @ 0x30 80075bc: 2301 movs r3, #1 80075be: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80075c0: 6a7b ldr r3, [r7, #36] @ 0x24 80075c2: f383 8810 msr PRIMASK, r3 } 80075c6: 46c0 nop @ (mov r8, r8) 80075c8: 687b ldr r3, [r7, #4] 80075ca: 681b ldr r3, [r3, #0] 80075cc: 689a ldr r2, [r3, #8] 80075ce: 687b ldr r3, [r7, #4] 80075d0: 681b ldr r3, [r3, #0] 80075d2: 491b ldr r1, [pc, #108] @ (8007640 ) 80075d4: 400a ands r2, r1 80075d6: 609a str r2, [r3, #8] 80075d8: 6b3b ldr r3, [r7, #48] @ 0x30 80075da: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80075dc: 6abb ldr r3, [r7, #40] @ 0x28 80075de: f383 8810 msr PRIMASK, r3 } 80075e2: 46c0 nop @ (mov r8, r8) /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80075e4: 687b ldr r3, [r7, #4] 80075e6: 6edb ldr r3, [r3, #108] @ 0x6c 80075e8: 2b01 cmp r3, #1 80075ea: d118 bne.n 800761e __ASM volatile ("MRS %0, primask" : "=r" (result) ); 80075ec: f3ef 8310 mrs r3, PRIMASK 80075f0: 60bb str r3, [r7, #8] return(result); 80075f2: 68bb ldr r3, [r7, #8] { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 80075f4: 62fb str r3, [r7, #44] @ 0x2c 80075f6: 2301 movs r3, #1 80075f8: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80075fa: 68fb ldr r3, [r7, #12] 80075fc: f383 8810 msr PRIMASK, r3 } 8007600: 46c0 nop @ (mov r8, r8) 8007602: 687b ldr r3, [r7, #4] 8007604: 681b ldr r3, [r3, #0] 8007606: 681a ldr r2, [r3, #0] 8007608: 687b ldr r3, [r7, #4] 800760a: 681b ldr r3, [r3, #0] 800760c: 2110 movs r1, #16 800760e: 438a bics r2, r1 8007610: 601a str r2, [r3, #0] 8007612: 6afb ldr r3, [r7, #44] @ 0x2c 8007614: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8007616: 693b ldr r3, [r7, #16] 8007618: f383 8810 msr PRIMASK, r3 } 800761c: 46c0 nop @ (mov r8, r8) } /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 800761e: 687b ldr r3, [r7, #4] 8007620: 228c movs r2, #140 @ 0x8c 8007622: 2120 movs r1, #32 8007624: 5099 str r1, [r3, r2] huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; 8007626: 687b ldr r3, [r7, #4] 8007628: 2200 movs r2, #0 800762a: 66da str r2, [r3, #108] @ 0x6c /* Reset RxIsr function pointer */ huart->RxISR = NULL; 800762c: 687b ldr r3, [r7, #4] 800762e: 2200 movs r2, #0 8007630: 675a str r2, [r3, #116] @ 0x74 } 8007632: 46c0 nop @ (mov r8, r8) 8007634: 46bd mov sp, r7 8007636: b00e add sp, #56 @ 0x38 8007638: bd80 pop {r7, pc} 800763a: 46c0 nop @ (mov r8, r8) 800763c: fffffedf .word 0xfffffedf 8007640: effffffe .word 0xeffffffe 08007644 : * @brief DMA UART receive process complete callback. * @param hdma DMA handle. * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { 8007644: b580 push {r7, lr} 8007646: b094 sub sp, #80 @ 0x50 8007648: af00 add r7, sp, #0 800764a: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 800764c: 687b ldr r3, [r7, #4] 800764e: 6a9b ldr r3, [r3, #40] @ 0x28 8007650: 64fb str r3, [r7, #76] @ 0x4c /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) 8007652: 687b ldr r3, [r7, #4] 8007654: 681b ldr r3, [r3, #0] 8007656: 681b ldr r3, [r3, #0] 8007658: 2220 movs r2, #32 800765a: 4013 ands r3, r2 800765c: d16f bne.n 800773e { huart->RxXferCount = 0U; 800765e: 6cfb ldr r3, [r7, #76] @ 0x4c 8007660: 225e movs r2, #94 @ 0x5e 8007662: 2100 movs r1, #0 8007664: 5299 strh r1, [r3, r2] __ASM volatile ("MRS %0, primask" : "=r" (result) ); 8007666: f3ef 8310 mrs r3, PRIMASK 800766a: 617b str r3, [r7, #20] return(result); 800766c: 697b ldr r3, [r7, #20] /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); 800766e: 64bb str r3, [r7, #72] @ 0x48 8007670: 2301 movs r3, #1 8007672: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8007674: 69bb ldr r3, [r7, #24] 8007676: f383 8810 msr PRIMASK, r3 } 800767a: 46c0 nop @ (mov r8, r8) 800767c: 6cfb ldr r3, [r7, #76] @ 0x4c 800767e: 681b ldr r3, [r3, #0] 8007680: 681a ldr r2, [r3, #0] 8007682: 6cfb ldr r3, [r7, #76] @ 0x4c 8007684: 681b ldr r3, [r3, #0] 8007686: 4948 ldr r1, [pc, #288] @ (80077a8 ) 8007688: 400a ands r2, r1 800768a: 601a str r2, [r3, #0] 800768c: 6cbb ldr r3, [r7, #72] @ 0x48 800768e: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8007690: 69fb ldr r3, [r7, #28] 8007692: f383 8810 msr PRIMASK, r3 } 8007696: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); 8007698: f3ef 8310 mrs r3, PRIMASK 800769c: 623b str r3, [r7, #32] return(result); 800769e: 6a3b ldr r3, [r7, #32] ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); 80076a0: 647b str r3, [r7, #68] @ 0x44 80076a2: 2301 movs r3, #1 80076a4: 627b str r3, [r7, #36] @ 0x24 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80076a6: 6a7b ldr r3, [r7, #36] @ 0x24 80076a8: f383 8810 msr PRIMASK, r3 } 80076ac: 46c0 nop @ (mov r8, r8) 80076ae: 6cfb ldr r3, [r7, #76] @ 0x4c 80076b0: 681b ldr r3, [r3, #0] 80076b2: 689a ldr r2, [r3, #8] 80076b4: 6cfb ldr r3, [r7, #76] @ 0x4c 80076b6: 681b ldr r3, [r3, #0] 80076b8: 2101 movs r1, #1 80076ba: 438a bics r2, r1 80076bc: 609a str r2, [r3, #8] 80076be: 6c7b ldr r3, [r7, #68] @ 0x44 80076c0: 62bb str r3, [r7, #40] @ 0x28 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80076c2: 6abb ldr r3, [r7, #40] @ 0x28 80076c4: f383 8810 msr PRIMASK, r3 } 80076c8: 46c0 nop @ (mov r8, r8) __ASM volatile ("MRS %0, primask" : "=r" (result) ); 80076ca: f3ef 8310 mrs r3, PRIMASK 80076ce: 62fb str r3, [r7, #44] @ 0x2c return(result); 80076d0: 6afb ldr r3, [r7, #44] @ 0x2c /* Disable the DMA transfer for the receiver request by resetting the DMAR bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); 80076d2: 643b str r3, [r7, #64] @ 0x40 80076d4: 2301 movs r3, #1 80076d6: 633b str r3, [r7, #48] @ 0x30 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80076d8: 6b3b ldr r3, [r7, #48] @ 0x30 80076da: f383 8810 msr PRIMASK, r3 } 80076de: 46c0 nop @ (mov r8, r8) 80076e0: 6cfb ldr r3, [r7, #76] @ 0x4c 80076e2: 681b ldr r3, [r3, #0] 80076e4: 689a ldr r2, [r3, #8] 80076e6: 6cfb ldr r3, [r7, #76] @ 0x4c 80076e8: 681b ldr r3, [r3, #0] 80076ea: 2140 movs r1, #64 @ 0x40 80076ec: 438a bics r2, r1 80076ee: 609a str r2, [r3, #8] 80076f0: 6c3b ldr r3, [r7, #64] @ 0x40 80076f2: 637b str r3, [r7, #52] @ 0x34 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 80076f4: 6b7b ldr r3, [r7, #52] @ 0x34 80076f6: f383 8810 msr PRIMASK, r3 } 80076fa: 46c0 nop @ (mov r8, r8) /* At end of Rx process, restore huart->RxState to Ready */ huart->RxState = HAL_UART_STATE_READY; 80076fc: 6cfb ldr r3, [r7, #76] @ 0x4c 80076fe: 228c movs r2, #140 @ 0x8c 8007700: 2120 movs r1, #32 8007702: 5099 str r1, [r3, r2] /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8007704: 6cfb ldr r3, [r7, #76] @ 0x4c 8007706: 6edb ldr r3, [r3, #108] @ 0x6c 8007708: 2b01 cmp r3, #1 800770a: d118 bne.n 800773e __ASM volatile ("MRS %0, primask" : "=r" (result) ); 800770c: f3ef 8310 mrs r3, PRIMASK 8007710: 60bb str r3, [r7, #8] return(result); 8007712: 68bb ldr r3, [r7, #8] { ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8007714: 63fb str r3, [r7, #60] @ 0x3c 8007716: 2301 movs r3, #1 8007718: 60fb str r3, [r7, #12] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 800771a: 68fb ldr r3, [r7, #12] 800771c: f383 8810 msr PRIMASK, r3 } 8007720: 46c0 nop @ (mov r8, r8) 8007722: 6cfb ldr r3, [r7, #76] @ 0x4c 8007724: 681b ldr r3, [r3, #0] 8007726: 681a ldr r2, [r3, #0] 8007728: 6cfb ldr r3, [r7, #76] @ 0x4c 800772a: 681b ldr r3, [r3, #0] 800772c: 2110 movs r1, #16 800772e: 438a bics r2, r1 8007730: 601a str r2, [r3, #0] 8007732: 6bfb ldr r3, [r7, #60] @ 0x3c 8007734: 613b str r3, [r7, #16] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8007736: 693b ldr r3, [r7, #16] 8007738: f383 8810 msr PRIMASK, r3 } 800773c: 46c0 nop @ (mov r8, r8) } } /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Transfer Complete */ huart->RxEventType = HAL_UART_RXEVENT_TC; 800773e: 6cfb ldr r3, [r7, #76] @ 0x4c 8007740: 2200 movs r2, #0 8007742: 671a str r2, [r3, #112] @ 0x70 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8007744: 6cfb ldr r3, [r7, #76] @ 0x4c 8007746: 6edb ldr r3, [r3, #108] @ 0x6c 8007748: 2b01 cmp r3, #1 800774a: d124 bne.n 8007796 { huart->RxXferCount = 0; 800774c: 6cfb ldr r3, [r7, #76] @ 0x4c 800774e: 225e movs r2, #94 @ 0x5e 8007750: 2100 movs r1, #0 8007752: 5299 strh r1, [r3, r2] /* Check current nb of data still to be received on DMA side. DMA Normal mode, remaining nb of data will be 0 DMA Circular mode, remaining nb of data is reset to RxXferSize */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); 8007754: 687b ldr r3, [r7, #4] 8007756: 681b ldr r3, [r3, #0] 8007758: 685a ldr r2, [r3, #4] 800775a: 213a movs r1, #58 @ 0x3a 800775c: 187b adds r3, r7, r1 800775e: 801a strh r2, [r3, #0] if (nb_remaining_rx_data < huart->RxXferSize) 8007760: 6cfb ldr r3, [r7, #76] @ 0x4c 8007762: 225c movs r2, #92 @ 0x5c 8007764: 5a9b ldrh r3, [r3, r2] 8007766: 187a adds r2, r7, r1 8007768: 8812 ldrh r2, [r2, #0] 800776a: 429a cmp r2, r3 800776c: d204 bcs.n 8007778 { /* Update nb of remaining data */ huart->RxXferCount = nb_remaining_rx_data; 800776e: 6cfb ldr r3, [r7, #76] @ 0x4c 8007770: 187a adds r2, r7, r1 8007772: 215e movs r1, #94 @ 0x5e 8007774: 8812 ldrh r2, [r2, #0] 8007776: 525a strh r2, [r3, r1] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 8007778: 6cfb ldr r3, [r7, #76] @ 0x4c 800777a: 225c movs r2, #92 @ 0x5c 800777c: 5a9a ldrh r2, [r3, r2] 800777e: 6cfb ldr r3, [r7, #76] @ 0x4c 8007780: 215e movs r1, #94 @ 0x5e 8007782: 5a5b ldrh r3, [r3, r1] 8007784: b29b uxth r3, r3 8007786: 1ad3 subs r3, r2, r3 8007788: b29a uxth r2, r3 800778a: 6cfb ldr r3, [r7, #76] @ 0x4c 800778c: 0011 movs r1, r2 800778e: 0018 movs r0, r3 8007790: f7fa f99c bl 8001acc #else /*Call legacy weak Rx complete callback*/ HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8007794: e003 b.n 800779e HAL_UART_RxCpltCallback(huart); 8007796: 6cfb ldr r3, [r7, #76] @ 0x4c 8007798: 0018 movs r0, r3 800779a: f7ff faa3 bl 8006ce4 } 800779e: 46c0 nop @ (mov r8, r8) 80077a0: 46bd mov sp, r7 80077a2: b014 add sp, #80 @ 0x50 80077a4: bd80 pop {r7, pc} 80077a6: 46c0 nop @ (mov r8, r8) 80077a8: fffffeff .word 0xfffffeff 080077ac : * @brief DMA UART receive process half complete callback. * @param hdma DMA handle. * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) { 80077ac: b580 push {r7, lr} 80077ae: b084 sub sp, #16 80077b0: af00 add r7, sp, #0 80077b2: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 80077b4: 687b ldr r3, [r7, #4] 80077b6: 6a9b ldr r3, [r3, #40] @ 0x28 80077b8: 60fb str r3, [r7, #12] /* Initialize type of RxEvent that correspond to RxEvent callback execution; In this case, Rx Event type is Half Transfer */ huart->RxEventType = HAL_UART_RXEVENT_HT; 80077ba: 68fb ldr r3, [r7, #12] 80077bc: 2201 movs r2, #1 80077be: 671a str r2, [r3, #112] @ 0x70 /* Check current reception Mode : If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 80077c0: 68fb ldr r3, [r7, #12] 80077c2: 6edb ldr r3, [r3, #108] @ 0x6c 80077c4: 2b01 cmp r3, #1 80077c6: d128 bne.n 800781a { huart->RxXferCount = huart->RxXferSize / 2U; 80077c8: 68fb ldr r3, [r7, #12] 80077ca: 225c movs r2, #92 @ 0x5c 80077cc: 5a9b ldrh r3, [r3, r2] 80077ce: 085b lsrs r3, r3, #1 80077d0: b299 uxth r1, r3 80077d2: 68fb ldr r3, [r7, #12] 80077d4: 225e movs r2, #94 @ 0x5e 80077d6: 5299 strh r1, [r3, r2] /* Check current nb of data still to be received on DMA side. */ uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); 80077d8: 687b ldr r3, [r7, #4] 80077da: 681b ldr r3, [r3, #0] 80077dc: 685a ldr r2, [r3, #4] 80077de: 210a movs r1, #10 80077e0: 187b adds r3, r7, r1 80077e2: 801a strh r2, [r3, #0] if (nb_remaining_rx_data <= huart->RxXferSize) 80077e4: 68fb ldr r3, [r7, #12] 80077e6: 225c movs r2, #92 @ 0x5c 80077e8: 5a9b ldrh r3, [r3, r2] 80077ea: 187a adds r2, r7, r1 80077ec: 8812 ldrh r2, [r2, #0] 80077ee: 429a cmp r2, r3 80077f0: d804 bhi.n 80077fc { /* Update nb of remaining data */ huart->RxXferCount = nb_remaining_rx_data; 80077f2: 68fb ldr r3, [r7, #12] 80077f4: 187a adds r2, r7, r1 80077f6: 215e movs r1, #94 @ 0x5e 80077f8: 8812 ldrh r2, [r2, #0] 80077fa: 525a strh r2, [r3, r1] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); 80077fc: 68fb ldr r3, [r7, #12] 80077fe: 225c movs r2, #92 @ 0x5c 8007800: 5a9a ldrh r2, [r3, r2] 8007802: 68fb ldr r3, [r7, #12] 8007804: 215e movs r1, #94 @ 0x5e 8007806: 5a5b ldrh r3, [r3, r1] 8007808: b29b uxth r3, r3 800780a: 1ad3 subs r3, r2, r3 800780c: b29a uxth r2, r3 800780e: 68fb ldr r3, [r7, #12] 8007810: 0011 movs r1, r2 8007812: 0018 movs r0, r3 8007814: f7fa f95a bl 8001acc #else /*Call legacy weak Rx Half complete callback*/ HAL_UART_RxHalfCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } } 8007818: e003 b.n 8007822 HAL_UART_RxHalfCpltCallback(huart); 800781a: 68fb ldr r3, [r7, #12] 800781c: 0018 movs r0, r3 800781e: f7ff fa69 bl 8006cf4 } 8007822: 46c0 nop @ (mov r8, r8) 8007824: 46bd mov sp, r7 8007826: b004 add sp, #16 8007828: bd80 pop {r7, pc} 0800782a : * @brief DMA UART communication error callback. * @param hdma DMA handle. * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) { 800782a: b580 push {r7, lr} 800782c: b086 sub sp, #24 800782e: af00 add r7, sp, #0 8007830: 6078 str r0, [r7, #4] UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); 8007832: 687b ldr r3, [r7, #4] 8007834: 6a9b ldr r3, [r3, #40] @ 0x28 8007836: 617b str r3, [r7, #20] const HAL_UART_StateTypeDef gstate = huart->gState; 8007838: 697b ldr r3, [r7, #20] 800783a: 2288 movs r2, #136 @ 0x88 800783c: 589b ldr r3, [r3, r2] 800783e: 613b str r3, [r7, #16] const HAL_UART_StateTypeDef rxstate = huart->RxState; 8007840: 697b ldr r3, [r7, #20] 8007842: 228c movs r2, #140 @ 0x8c 8007844: 589b ldr r3, [r3, r2] 8007846: 60fb str r3, [r7, #12] /* Stop UART DMA Tx request if ongoing */ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && 8007848: 697b ldr r3, [r7, #20] 800784a: 681b ldr r3, [r3, #0] 800784c: 689b ldr r3, [r3, #8] 800784e: 2280 movs r2, #128 @ 0x80 8007850: 4013 ands r3, r2 8007852: 2b80 cmp r3, #128 @ 0x80 8007854: d10a bne.n 800786c 8007856: 693b ldr r3, [r7, #16] 8007858: 2b21 cmp r3, #33 @ 0x21 800785a: d107 bne.n 800786c (gstate == HAL_UART_STATE_BUSY_TX)) { huart->TxXferCount = 0U; 800785c: 697b ldr r3, [r7, #20] 800785e: 2256 movs r2, #86 @ 0x56 8007860: 2100 movs r1, #0 8007862: 5299 strh r1, [r3, r2] UART_EndTxTransfer(huart); 8007864: 697b ldr r3, [r7, #20] 8007866: 0018 movs r0, r3 8007868: f7ff fe46 bl 80074f8 } /* Stop UART DMA Rx request if ongoing */ if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && 800786c: 697b ldr r3, [r7, #20] 800786e: 681b ldr r3, [r3, #0] 8007870: 689b ldr r3, [r3, #8] 8007872: 2240 movs r2, #64 @ 0x40 8007874: 4013 ands r3, r2 8007876: 2b40 cmp r3, #64 @ 0x40 8007878: d10a bne.n 8007890 800787a: 68fb ldr r3, [r7, #12] 800787c: 2b22 cmp r3, #34 @ 0x22 800787e: d107 bne.n 8007890 (rxstate == HAL_UART_STATE_BUSY_RX)) { huart->RxXferCount = 0U; 8007880: 697b ldr r3, [r7, #20] 8007882: 225e movs r2, #94 @ 0x5e 8007884: 2100 movs r1, #0 8007886: 5299 strh r1, [r3, r2] UART_EndRxTransfer(huart); 8007888: 697b ldr r3, [r7, #20] 800788a: 0018 movs r0, r3 800788c: f7ff fe74 bl 8007578 } huart->ErrorCode |= HAL_UART_ERROR_DMA; 8007890: 697b ldr r3, [r7, #20] 8007892: 2290 movs r2, #144 @ 0x90 8007894: 589b ldr r3, [r3, r2] 8007896: 2210 movs r2, #16 8007898: 431a orrs r2, r3 800789a: 697b ldr r3, [r7, #20] 800789c: 2190 movs r1, #144 @ 0x90 800789e: 505a str r2, [r3, r1] #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ huart->ErrorCallback(huart); #else /*Call legacy weak error callback*/ HAL_UART_ErrorCallback(huart); 80078a0: 697b ldr r3, [r7, #20] 80078a2: 0018 movs r0, r3 80078a4: f7ff fa2e bl 8006d04 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } 80078a8: 46c0 nop @ (mov r8, r8) 80078aa: 46bd mov sp, r7 80078ac: b006 add sp, #24 80078ae: bd80 pop {r7, pc} 080078b0 : * oversampling rate). * @retval HAL status */ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, uint32_t DeassertionTime) { 80078b0: b580 push {r7, lr} 80078b2: b086 sub sp, #24 80078b4: af00 add r7, sp, #0 80078b6: 60f8 str r0, [r7, #12] 80078b8: 60b9 str r1, [r7, #8] 80078ba: 607a str r2, [r7, #4] 80078bc: 603b str r3, [r7, #0] uint32_t temp; /* Check the UART handle allocation */ if (huart == NULL) 80078be: 68fb ldr r3, [r7, #12] 80078c0: 2b00 cmp r3, #0 80078c2: d101 bne.n 80078c8 { return HAL_ERROR; 80078c4: 2301 movs r3, #1 80078c6: e05d b.n 8007984 assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); /* Check the Driver Enable deassertion time */ assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); if (huart->gState == HAL_UART_STATE_RESET) 80078c8: 68fb ldr r3, [r7, #12] 80078ca: 2288 movs r2, #136 @ 0x88 80078cc: 589b ldr r3, [r3, r2] 80078ce: 2b00 cmp r3, #0 80078d0: d107 bne.n 80078e2 { /* Allocate lock resource and initialize it */ huart->Lock = HAL_UNLOCKED; 80078d2: 68fb ldr r3, [r7, #12] 80078d4: 2284 movs r2, #132 @ 0x84 80078d6: 2100 movs r1, #0 80078d8: 5499 strb r1, [r3, r2] /* Init the low level hardware */ huart->MspInitCallback(huart); #else /* Init the low level hardware : GPIO, CLOCK, CORTEX */ HAL_UART_MspInit(huart); 80078da: 68fb ldr r3, [r7, #12] 80078dc: 0018 movs r0, r3 80078de: f7fc f9f7 bl 8003cd0 #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } huart->gState = HAL_UART_STATE_BUSY; 80078e2: 68fb ldr r3, [r7, #12] 80078e4: 2288 movs r2, #136 @ 0x88 80078e6: 2124 movs r1, #36 @ 0x24 80078e8: 5099 str r1, [r3, r2] /* Disable the Peripheral */ __HAL_UART_DISABLE(huart); 80078ea: 68fb ldr r3, [r7, #12] 80078ec: 681b ldr r3, [r3, #0] 80078ee: 681a ldr r2, [r3, #0] 80078f0: 68fb ldr r3, [r7, #12] 80078f2: 681b ldr r3, [r3, #0] 80078f4: 2101 movs r1, #1 80078f6: 438a bics r2, r1 80078f8: 601a str r2, [r3, #0] /* Perform advanced settings configuration */ /* For some items, configuration requires to be done prior TE and RE bits are set */ if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) 80078fa: 68fb ldr r3, [r7, #12] 80078fc: 6a9b ldr r3, [r3, #40] @ 0x28 80078fe: 2b00 cmp r3, #0 8007900: d003 beq.n 800790a { UART_AdvFeatureConfig(huart); 8007902: 68fb ldr r3, [r7, #12] 8007904: 0018 movs r0, r3 8007906: f7ff fb83 bl 8007010 } /* Set the UART Communication parameters */ if (UART_SetConfig(huart) == HAL_ERROR) 800790a: 68fb ldr r3, [r7, #12] 800790c: 0018 movs r0, r3 800790e: f7ff fa01 bl 8006d14 8007912: 0003 movs r3, r0 8007914: 2b01 cmp r3, #1 8007916: d101 bne.n 800791c { return HAL_ERROR; 8007918: 2301 movs r3, #1 800791a: e033 b.n 8007984 } /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ SET_BIT(huart->Instance->CR3, USART_CR3_DEM); 800791c: 68fb ldr r3, [r7, #12] 800791e: 681b ldr r3, [r3, #0] 8007920: 689a ldr r2, [r3, #8] 8007922: 68fb ldr r3, [r7, #12] 8007924: 681b ldr r3, [r3, #0] 8007926: 2180 movs r1, #128 @ 0x80 8007928: 01c9 lsls r1, r1, #7 800792a: 430a orrs r2, r1 800792c: 609a str r2, [r3, #8] /* Set the Driver Enable polarity */ MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); 800792e: 68fb ldr r3, [r7, #12] 8007930: 681b ldr r3, [r3, #0] 8007932: 689b ldr r3, [r3, #8] 8007934: 4a15 ldr r2, [pc, #84] @ (800798c ) 8007936: 4013 ands r3, r2 8007938: 0019 movs r1, r3 800793a: 68fb ldr r3, [r7, #12] 800793c: 681b ldr r3, [r3, #0] 800793e: 68ba ldr r2, [r7, #8] 8007940: 430a orrs r2, r1 8007942: 609a str r2, [r3, #8] /* Set the Driver Enable assertion and deassertion times */ temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); 8007944: 687b ldr r3, [r7, #4] 8007946: 055b lsls r3, r3, #21 8007948: 617b str r3, [r7, #20] temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); 800794a: 683b ldr r3, [r7, #0] 800794c: 041b lsls r3, r3, #16 800794e: 697a ldr r2, [r7, #20] 8007950: 4313 orrs r3, r2 8007952: 617b str r3, [r7, #20] MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); 8007954: 68fb ldr r3, [r7, #12] 8007956: 681b ldr r3, [r3, #0] 8007958: 681b ldr r3, [r3, #0] 800795a: 4a0d ldr r2, [pc, #52] @ (8007990 ) 800795c: 4013 ands r3, r2 800795e: 0019 movs r1, r3 8007960: 68fb ldr r3, [r7, #12] 8007962: 681b ldr r3, [r3, #0] 8007964: 697a ldr r2, [r7, #20] 8007966: 430a orrs r2, r1 8007968: 601a str r2, [r3, #0] /* Enable the Peripheral */ __HAL_UART_ENABLE(huart); 800796a: 68fb ldr r3, [r7, #12] 800796c: 681b ldr r3, [r3, #0] 800796e: 681a ldr r2, [r3, #0] 8007970: 68fb ldr r3, [r7, #12] 8007972: 681b ldr r3, [r3, #0] 8007974: 2101 movs r1, #1 8007976: 430a orrs r2, r1 8007978: 601a str r2, [r3, #0] /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ return (UART_CheckIdleState(huart)); 800797a: 68fb ldr r3, [r7, #12] 800797c: 0018 movs r0, r3 800797e: f7ff fbfb bl 8007178 8007982: 0003 movs r3, r0 } 8007984: 0018 movs r0, r3 8007986: 46bd mov sp, r7 8007988: b006 add sp, #24 800798a: bd80 pop {r7, pc} 800798c: ffff7fff .word 0xffff7fff 8007990: fc00ffff .word 0xfc00ffff 08007994 : * @brief Disable the FIFO mode. * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) { 8007994: b580 push {r7, lr} 8007996: b084 sub sp, #16 8007998: af00 add r7, sp, #0 800799a: 6078 str r0, [r7, #4] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); /* Process Locked */ __HAL_LOCK(huart); 800799c: 687b ldr r3, [r7, #4] 800799e: 2284 movs r2, #132 @ 0x84 80079a0: 5c9b ldrb r3, [r3, r2] 80079a2: 2b01 cmp r3, #1 80079a4: d101 bne.n 80079aa 80079a6: 2302 movs r3, #2 80079a8: e027 b.n 80079fa 80079aa: 687b ldr r3, [r7, #4] 80079ac: 2284 movs r2, #132 @ 0x84 80079ae: 2101 movs r1, #1 80079b0: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; 80079b2: 687b ldr r3, [r7, #4] 80079b4: 2288 movs r2, #136 @ 0x88 80079b6: 2124 movs r1, #36 @ 0x24 80079b8: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 80079ba: 687b ldr r3, [r7, #4] 80079bc: 681b ldr r3, [r3, #0] 80079be: 681b ldr r3, [r3, #0] 80079c0: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 80079c2: 687b ldr r3, [r7, #4] 80079c4: 681b ldr r3, [r3, #0] 80079c6: 681a ldr r2, [r3, #0] 80079c8: 687b ldr r3, [r7, #4] 80079ca: 681b ldr r3, [r3, #0] 80079cc: 2101 movs r1, #1 80079ce: 438a bics r2, r1 80079d0: 601a str r2, [r3, #0] /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); 80079d2: 68fb ldr r3, [r7, #12] 80079d4: 4a0b ldr r2, [pc, #44] @ (8007a04 ) 80079d6: 4013 ands r3, r2 80079d8: 60fb str r3, [r7, #12] huart->FifoMode = UART_FIFOMODE_DISABLE; 80079da: 687b ldr r3, [r7, #4] 80079dc: 2200 movs r2, #0 80079de: 665a str r2, [r3, #100] @ 0x64 /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 80079e0: 687b ldr r3, [r7, #4] 80079e2: 681b ldr r3, [r3, #0] 80079e4: 68fa ldr r2, [r7, #12] 80079e6: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 80079e8: 687b ldr r3, [r7, #4] 80079ea: 2288 movs r2, #136 @ 0x88 80079ec: 2120 movs r1, #32 80079ee: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 80079f0: 687b ldr r3, [r7, #4] 80079f2: 2284 movs r2, #132 @ 0x84 80079f4: 2100 movs r1, #0 80079f6: 5499 strb r1, [r3, r2] return HAL_OK; 80079f8: 2300 movs r3, #0 } 80079fa: 0018 movs r0, r3 80079fc: 46bd mov sp, r7 80079fe: b004 add sp, #16 8007a00: bd80 pop {r7, pc} 8007a02: 46c0 nop @ (mov r8, r8) 8007a04: dfffffff .word 0xdfffffff 08007a08 : * @arg @ref UART_TXFIFO_THRESHOLD_7_8 * @arg @ref UART_TXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8007a08: b580 push {r7, lr} 8007a0a: b084 sub sp, #16 8007a0c: af00 add r7, sp, #0 8007a0e: 6078 str r0, [r7, #4] 8007a10: 6039 str r1, [r7, #0] /* Check parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8007a12: 687b ldr r3, [r7, #4] 8007a14: 2284 movs r2, #132 @ 0x84 8007a16: 5c9b ldrb r3, [r3, r2] 8007a18: 2b01 cmp r3, #1 8007a1a: d101 bne.n 8007a20 8007a1c: 2302 movs r3, #2 8007a1e: e02e b.n 8007a7e 8007a20: 687b ldr r3, [r7, #4] 8007a22: 2284 movs r2, #132 @ 0x84 8007a24: 2101 movs r1, #1 8007a26: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; 8007a28: 687b ldr r3, [r7, #4] 8007a2a: 2288 movs r2, #136 @ 0x88 8007a2c: 2124 movs r1, #36 @ 0x24 8007a2e: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8007a30: 687b ldr r3, [r7, #4] 8007a32: 681b ldr r3, [r3, #0] 8007a34: 681b ldr r3, [r3, #0] 8007a36: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8007a38: 687b ldr r3, [r7, #4] 8007a3a: 681b ldr r3, [r3, #0] 8007a3c: 681a ldr r2, [r3, #0] 8007a3e: 687b ldr r3, [r7, #4] 8007a40: 681b ldr r3, [r3, #0] 8007a42: 2101 movs r1, #1 8007a44: 438a bics r2, r1 8007a46: 601a str r2, [r3, #0] /* Update TX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); 8007a48: 687b ldr r3, [r7, #4] 8007a4a: 681b ldr r3, [r3, #0] 8007a4c: 689b ldr r3, [r3, #8] 8007a4e: 00db lsls r3, r3, #3 8007a50: 08d9 lsrs r1, r3, #3 8007a52: 687b ldr r3, [r7, #4] 8007a54: 681b ldr r3, [r3, #0] 8007a56: 683a ldr r2, [r7, #0] 8007a58: 430a orrs r2, r1 8007a5a: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8007a5c: 687b ldr r3, [r7, #4] 8007a5e: 0018 movs r0, r3 8007a60: f000 f8bc bl 8007bdc /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8007a64: 687b ldr r3, [r7, #4] 8007a66: 681b ldr r3, [r3, #0] 8007a68: 68fa ldr r2, [r7, #12] 8007a6a: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8007a6c: 687b ldr r3, [r7, #4] 8007a6e: 2288 movs r2, #136 @ 0x88 8007a70: 2120 movs r1, #32 8007a72: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 8007a74: 687b ldr r3, [r7, #4] 8007a76: 2284 movs r2, #132 @ 0x84 8007a78: 2100 movs r1, #0 8007a7a: 5499 strb r1, [r3, r2] return HAL_OK; 8007a7c: 2300 movs r3, #0 } 8007a7e: 0018 movs r0, r3 8007a80: 46bd mov sp, r7 8007a82: b004 add sp, #16 8007a84: bd80 pop {r7, pc} ... 08007a88 : * @arg @ref UART_RXFIFO_THRESHOLD_7_8 * @arg @ref UART_RXFIFO_THRESHOLD_8_8 * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) { 8007a88: b580 push {r7, lr} 8007a8a: b084 sub sp, #16 8007a8c: af00 add r7, sp, #0 8007a8e: 6078 str r0, [r7, #4] 8007a90: 6039 str r1, [r7, #0] /* Check the parameters */ assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); /* Process Locked */ __HAL_LOCK(huart); 8007a92: 687b ldr r3, [r7, #4] 8007a94: 2284 movs r2, #132 @ 0x84 8007a96: 5c9b ldrb r3, [r3, r2] 8007a98: 2b01 cmp r3, #1 8007a9a: d101 bne.n 8007aa0 8007a9c: 2302 movs r3, #2 8007a9e: e02f b.n 8007b00 8007aa0: 687b ldr r3, [r7, #4] 8007aa2: 2284 movs r2, #132 @ 0x84 8007aa4: 2101 movs r1, #1 8007aa6: 5499 strb r1, [r3, r2] huart->gState = HAL_UART_STATE_BUSY; 8007aa8: 687b ldr r3, [r7, #4] 8007aaa: 2288 movs r2, #136 @ 0x88 8007aac: 2124 movs r1, #36 @ 0x24 8007aae: 5099 str r1, [r3, r2] /* Save actual UART configuration */ tmpcr1 = READ_REG(huart->Instance->CR1); 8007ab0: 687b ldr r3, [r7, #4] 8007ab2: 681b ldr r3, [r3, #0] 8007ab4: 681b ldr r3, [r3, #0] 8007ab6: 60fb str r3, [r7, #12] /* Disable UART */ __HAL_UART_DISABLE(huart); 8007ab8: 687b ldr r3, [r7, #4] 8007aba: 681b ldr r3, [r3, #0] 8007abc: 681a ldr r2, [r3, #0] 8007abe: 687b ldr r3, [r7, #4] 8007ac0: 681b ldr r3, [r3, #0] 8007ac2: 2101 movs r1, #1 8007ac4: 438a bics r2, r1 8007ac6: 601a str r2, [r3, #0] /* Update RX threshold configuration */ MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); 8007ac8: 687b ldr r3, [r7, #4] 8007aca: 681b ldr r3, [r3, #0] 8007acc: 689b ldr r3, [r3, #8] 8007ace: 4a0e ldr r2, [pc, #56] @ (8007b08 ) 8007ad0: 4013 ands r3, r2 8007ad2: 0019 movs r1, r3 8007ad4: 687b ldr r3, [r7, #4] 8007ad6: 681b ldr r3, [r3, #0] 8007ad8: 683a ldr r2, [r7, #0] 8007ada: 430a orrs r2, r1 8007adc: 609a str r2, [r3, #8] /* Determine the number of data to process during RX/TX ISR execution */ UARTEx_SetNbDataToProcess(huart); 8007ade: 687b ldr r3, [r7, #4] 8007ae0: 0018 movs r0, r3 8007ae2: f000 f87b bl 8007bdc /* Restore UART configuration */ WRITE_REG(huart->Instance->CR1, tmpcr1); 8007ae6: 687b ldr r3, [r7, #4] 8007ae8: 681b ldr r3, [r3, #0] 8007aea: 68fa ldr r2, [r7, #12] 8007aec: 601a str r2, [r3, #0] huart->gState = HAL_UART_STATE_READY; 8007aee: 687b ldr r3, [r7, #4] 8007af0: 2288 movs r2, #136 @ 0x88 8007af2: 2120 movs r1, #32 8007af4: 5099 str r1, [r3, r2] /* Process Unlocked */ __HAL_UNLOCK(huart); 8007af6: 687b ldr r3, [r7, #4] 8007af8: 2284 movs r2, #132 @ 0x84 8007afa: 2100 movs r1, #0 8007afc: 5499 strb r1, [r3, r2] return HAL_OK; 8007afe: 2300 movs r3, #0 } 8007b00: 0018 movs r0, r3 8007b02: 46bd mov sp, r7 8007b04: b004 add sp, #16 8007b06: bd80 pop {r7, pc} 8007b08: f1ffffff .word 0xf1ffffff 08007b0c : * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). * @param Size Amount of data elements (uint8_t or uint16_t) to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) { 8007b0c: b5b0 push {r4, r5, r7, lr} 8007b0e: b08a sub sp, #40 @ 0x28 8007b10: af00 add r7, sp, #0 8007b12: 60f8 str r0, [r7, #12] 8007b14: 60b9 str r1, [r7, #8] 8007b16: 1dbb adds r3, r7, #6 8007b18: 801a strh r2, [r3, #0] HAL_StatusTypeDef status; /* Check that a Rx process is not already ongoing */ if (huart->RxState == HAL_UART_STATE_READY) 8007b1a: 68fb ldr r3, [r7, #12] 8007b1c: 228c movs r2, #140 @ 0x8c 8007b1e: 589b ldr r3, [r3, r2] 8007b20: 2b20 cmp r3, #32 8007b22: d156 bne.n 8007bd2 { if ((pData == NULL) || (Size == 0U)) 8007b24: 68bb ldr r3, [r7, #8] 8007b26: 2b00 cmp r3, #0 8007b28: d003 beq.n 8007b32 8007b2a: 1dbb adds r3, r7, #6 8007b2c: 881b ldrh r3, [r3, #0] 8007b2e: 2b00 cmp r3, #0 8007b30: d101 bne.n 8007b36 { return HAL_ERROR; 8007b32: 2301 movs r3, #1 8007b34: e04e b.n 8007bd4 } /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter should be aligned on a uint16_t frontier, as data copy from RDR will be handled by DMA from a uint16_t frontier. */ if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) 8007b36: 68fb ldr r3, [r7, #12] 8007b38: 689a ldr r2, [r3, #8] 8007b3a: 2380 movs r3, #128 @ 0x80 8007b3c: 015b lsls r3, r3, #5 8007b3e: 429a cmp r2, r3 8007b40: d109 bne.n 8007b56 8007b42: 68fb ldr r3, [r7, #12] 8007b44: 691b ldr r3, [r3, #16] 8007b46: 2b00 cmp r3, #0 8007b48: d105 bne.n 8007b56 { if ((((uint32_t)pData) & 1U) != 0U) 8007b4a: 68bb ldr r3, [r7, #8] 8007b4c: 2201 movs r2, #1 8007b4e: 4013 ands r3, r2 8007b50: d001 beq.n 8007b56 { return HAL_ERROR; 8007b52: 2301 movs r3, #1 8007b54: e03e b.n 8007bd4 } } /* Set Reception type to reception till IDLE Event*/ huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; 8007b56: 68fb ldr r3, [r7, #12] 8007b58: 2201 movs r2, #1 8007b5a: 66da str r2, [r3, #108] @ 0x6c huart->RxEventType = HAL_UART_RXEVENT_TC; 8007b5c: 68fb ldr r3, [r7, #12] 8007b5e: 2200 movs r2, #0 8007b60: 671a str r2, [r3, #112] @ 0x70 status = UART_Start_Receive_DMA(huart, pData, Size); 8007b62: 2527 movs r5, #39 @ 0x27 8007b64: 197c adds r4, r7, r5 8007b66: 1dbb adds r3, r7, #6 8007b68: 881a ldrh r2, [r3, #0] 8007b6a: 68b9 ldr r1, [r7, #8] 8007b6c: 68fb ldr r3, [r7, #12] 8007b6e: 0018 movs r0, r3 8007b70: f7ff fc1c bl 80073ac 8007b74: 0003 movs r3, r0 8007b76: 7023 strb r3, [r4, #0] /* Check Rx process has been successfully started */ if (status == HAL_OK) 8007b78: 197b adds r3, r7, r5 8007b7a: 781b ldrb r3, [r3, #0] 8007b7c: 2b00 cmp r3, #0 8007b7e: d124 bne.n 8007bca { if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) 8007b80: 68fb ldr r3, [r7, #12] 8007b82: 6edb ldr r3, [r3, #108] @ 0x6c 8007b84: 2b01 cmp r3, #1 8007b86: d11c bne.n 8007bc2 { __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); 8007b88: 68fb ldr r3, [r7, #12] 8007b8a: 681b ldr r3, [r3, #0] 8007b8c: 2210 movs r2, #16 8007b8e: 621a str r2, [r3, #32] __ASM volatile ("MRS %0, primask" : "=r" (result) ); 8007b90: f3ef 8310 mrs r3, PRIMASK 8007b94: 617b str r3, [r7, #20] return(result); 8007b96: 697b ldr r3, [r7, #20] ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); 8007b98: 623b str r3, [r7, #32] 8007b9a: 2301 movs r3, #1 8007b9c: 61bb str r3, [r7, #24] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8007b9e: 69bb ldr r3, [r7, #24] 8007ba0: f383 8810 msr PRIMASK, r3 } 8007ba4: 46c0 nop @ (mov r8, r8) 8007ba6: 68fb ldr r3, [r7, #12] 8007ba8: 681b ldr r3, [r3, #0] 8007baa: 681a ldr r2, [r3, #0] 8007bac: 68fb ldr r3, [r7, #12] 8007bae: 681b ldr r3, [r3, #0] 8007bb0: 2110 movs r1, #16 8007bb2: 430a orrs r2, r1 8007bb4: 601a str r2, [r3, #0] 8007bb6: 6a3b ldr r3, [r7, #32] 8007bb8: 61fb str r3, [r7, #28] __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); 8007bba: 69fb ldr r3, [r7, #28] 8007bbc: f383 8810 msr PRIMASK, r3 } 8007bc0: e003 b.n 8007bca { /* In case of errors already pending when reception is started, Interrupts may have already been raised and lead to reception abortion. (Overrun error for instance). In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ status = HAL_ERROR; 8007bc2: 2327 movs r3, #39 @ 0x27 8007bc4: 18fb adds r3, r7, r3 8007bc6: 2201 movs r2, #1 8007bc8: 701a strb r2, [r3, #0] } } return status; 8007bca: 2327 movs r3, #39 @ 0x27 8007bcc: 18fb adds r3, r7, r3 8007bce: 781b ldrb r3, [r3, #0] 8007bd0: e000 b.n 8007bd4 } else { return HAL_BUSY; 8007bd2: 2302 movs r3, #2 } } 8007bd4: 0018 movs r0, r3 8007bd6: 46bd mov sp, r7 8007bd8: b00a add sp, #40 @ 0x28 8007bda: bdb0 pop {r4, r5, r7, pc} 08007bdc : * the UART configuration registers. * @param huart UART handle. * @retval None */ static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) { 8007bdc: b5f0 push {r4, r5, r6, r7, lr} 8007bde: b085 sub sp, #20 8007be0: af00 add r7, sp, #0 8007be2: 6078 str r0, [r7, #4] uint8_t rx_fifo_threshold; uint8_t tx_fifo_threshold; static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; if (huart->FifoMode == UART_FIFOMODE_DISABLE) 8007be4: 687b ldr r3, [r7, #4] 8007be6: 6e5b ldr r3, [r3, #100] @ 0x64 8007be8: 2b00 cmp r3, #0 8007bea: d108 bne.n 8007bfe { huart->NbTxDataToProcess = 1U; 8007bec: 687b ldr r3, [r7, #4] 8007bee: 226a movs r2, #106 @ 0x6a 8007bf0: 2101 movs r1, #1 8007bf2: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = 1U; 8007bf4: 687b ldr r3, [r7, #4] 8007bf6: 2268 movs r2, #104 @ 0x68 8007bf8: 2101 movs r1, #1 8007bfa: 5299 strh r1, [r3, r2] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / (uint16_t)denominator[tx_fifo_threshold]; huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / (uint16_t)denominator[rx_fifo_threshold]; } } 8007bfc: e043 b.n 8007c86 rx_fifo_depth = RX_FIFO_DEPTH; 8007bfe: 260f movs r6, #15 8007c00: 19bb adds r3, r7, r6 8007c02: 2208 movs r2, #8 8007c04: 701a strb r2, [r3, #0] tx_fifo_depth = TX_FIFO_DEPTH; 8007c06: 200e movs r0, #14 8007c08: 183b adds r3, r7, r0 8007c0a: 2208 movs r2, #8 8007c0c: 701a strb r2, [r3, #0] rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 8007c0e: 687b ldr r3, [r7, #4] 8007c10: 681b ldr r3, [r3, #0] 8007c12: 689b ldr r3, [r3, #8] 8007c14: 0e5b lsrs r3, r3, #25 8007c16: b2da uxtb r2, r3 8007c18: 240d movs r4, #13 8007c1a: 193b adds r3, r7, r4 8007c1c: 2107 movs r1, #7 8007c1e: 400a ands r2, r1 8007c20: 701a strb r2, [r3, #0] tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 8007c22: 687b ldr r3, [r7, #4] 8007c24: 681b ldr r3, [r3, #0] 8007c26: 689b ldr r3, [r3, #8] 8007c28: 0f5b lsrs r3, r3, #29 8007c2a: b2da uxtb r2, r3 8007c2c: 250c movs r5, #12 8007c2e: 197b adds r3, r7, r5 8007c30: 2107 movs r1, #7 8007c32: 400a ands r2, r1 8007c34: 701a strb r2, [r3, #0] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8007c36: 183b adds r3, r7, r0 8007c38: 781b ldrb r3, [r3, #0] 8007c3a: 197a adds r2, r7, r5 8007c3c: 7812 ldrb r2, [r2, #0] 8007c3e: 4914 ldr r1, [pc, #80] @ (8007c90 ) 8007c40: 5c8a ldrb r2, [r1, r2] 8007c42: 435a muls r2, r3 8007c44: 0010 movs r0, r2 (uint16_t)denominator[tx_fifo_threshold]; 8007c46: 197b adds r3, r7, r5 8007c48: 781b ldrb r3, [r3, #0] 8007c4a: 4a12 ldr r2, [pc, #72] @ (8007c94 ) 8007c4c: 5cd3 ldrb r3, [r2, r3] huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / 8007c4e: 0019 movs r1, r3 8007c50: f7f8 fae4 bl 800021c <__divsi3> 8007c54: 0003 movs r3, r0 8007c56: b299 uxth r1, r3 8007c58: 687b ldr r3, [r7, #4] 8007c5a: 226a movs r2, #106 @ 0x6a 8007c5c: 5299 strh r1, [r3, r2] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8007c5e: 19bb adds r3, r7, r6 8007c60: 781b ldrb r3, [r3, #0] 8007c62: 193a adds r2, r7, r4 8007c64: 7812 ldrb r2, [r2, #0] 8007c66: 490a ldr r1, [pc, #40] @ (8007c90 ) 8007c68: 5c8a ldrb r2, [r1, r2] 8007c6a: 435a muls r2, r3 8007c6c: 0010 movs r0, r2 (uint16_t)denominator[rx_fifo_threshold]; 8007c6e: 193b adds r3, r7, r4 8007c70: 781b ldrb r3, [r3, #0] 8007c72: 4a08 ldr r2, [pc, #32] @ (8007c94 ) 8007c74: 5cd3 ldrb r3, [r2, r3] huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / 8007c76: 0019 movs r1, r3 8007c78: f7f8 fad0 bl 800021c <__divsi3> 8007c7c: 0003 movs r3, r0 8007c7e: b299 uxth r1, r3 8007c80: 687b ldr r3, [r7, #4] 8007c82: 2268 movs r2, #104 @ 0x68 8007c84: 5299 strh r1, [r3, r2] } 8007c86: 46c0 nop @ (mov r8, r8) 8007c88: 46bd mov sp, r7 8007c8a: b005 add sp, #20 8007c8c: bdf0 pop {r4, r5, r6, r7, pc} 8007c8e: 46c0 nop @ (mov r8, r8) 8007c90: 08007e7c .word 0x08007e7c 8007c94: 08007e84 .word 0x08007e84 08007c98 : 8007c98: b530 push {r4, r5, lr} 8007c9a: 2400 movs r4, #0 8007c9c: 3901 subs r1, #1 8007c9e: 42a2 cmp r2, r4 8007ca0: d101 bne.n 8007ca6 8007ca2: 2000 movs r0, #0 8007ca4: e005 b.n 8007cb2 8007ca6: 5d03 ldrb r3, [r0, r4] 8007ca8: 3401 adds r4, #1 8007caa: 5d0d ldrb r5, [r1, r4] 8007cac: 42ab cmp r3, r5 8007cae: d0f6 beq.n 8007c9e 8007cb0: 1b58 subs r0, r3, r5 8007cb2: bd30 pop {r4, r5, pc} 08007cb4 : 8007cb4: 0003 movs r3, r0 8007cb6: 1882 adds r2, r0, r2 8007cb8: 4293 cmp r3, r2 8007cba: d100 bne.n 8007cbe 8007cbc: 4770 bx lr 8007cbe: 7019 strb r1, [r3, #0] 8007cc0: 3301 adds r3, #1 8007cc2: e7f9 b.n 8007cb8 08007cc4 <__libc_init_array>: 8007cc4: b570 push {r4, r5, r6, lr} 8007cc6: 2600 movs r6, #0 8007cc8: 4c0c ldr r4, [pc, #48] @ (8007cfc <__libc_init_array+0x38>) 8007cca: 4d0d ldr r5, [pc, #52] @ (8007d00 <__libc_init_array+0x3c>) 8007ccc: 1b64 subs r4, r4, r5 8007cce: 10a4 asrs r4, r4, #2 8007cd0: 42a6 cmp r6, r4 8007cd2: d109 bne.n 8007ce8 <__libc_init_array+0x24> 8007cd4: 2600 movs r6, #0 8007cd6: f000 f823 bl 8007d20 <_init> 8007cda: 4c0a ldr r4, [pc, #40] @ (8007d04 <__libc_init_array+0x40>) 8007cdc: 4d0a ldr r5, [pc, #40] @ (8007d08 <__libc_init_array+0x44>) 8007cde: 1b64 subs r4, r4, r5 8007ce0: 10a4 asrs r4, r4, #2 8007ce2: 42a6 cmp r6, r4 8007ce4: d105 bne.n 8007cf2 <__libc_init_array+0x2e> 8007ce6: bd70 pop {r4, r5, r6, pc} 8007ce8: 00b3 lsls r3, r6, #2 8007cea: 58eb ldr r3, [r5, r3] 8007cec: 4798 blx r3 8007cee: 3601 adds r6, #1 8007cf0: e7ee b.n 8007cd0 <__libc_init_array+0xc> 8007cf2: 00b3 lsls r3, r6, #2 8007cf4: 58eb ldr r3, [r5, r3] 8007cf6: 4798 blx r3 8007cf8: 3601 adds r6, #1 8007cfa: e7f2 b.n 8007ce2 <__libc_init_array+0x1e> 8007cfc: 08007e94 .word 0x08007e94 8007d00: 08007e94 .word 0x08007e94 8007d04: 08007e98 .word 0x08007e98 8007d08: 08007e94 .word 0x08007e94 08007d0c : 8007d0c: 2300 movs r3, #0 8007d0e: b510 push {r4, lr} 8007d10: 429a cmp r2, r3 8007d12: d100 bne.n 8007d16 8007d14: bd10 pop {r4, pc} 8007d16: 5ccc ldrb r4, [r1, r3] 8007d18: 54c4 strb r4, [r0, r3] 8007d1a: 3301 adds r3, #1 8007d1c: e7f8 b.n 8007d10 ... 08007d20 <_init>: 8007d20: b5f8 push {r3, r4, r5, r6, r7, lr} 8007d22: 46c0 nop @ (mov r8, r8) 8007d24: bcf8 pop {r3, r4, r5, r6, r7} 8007d26: bc08 pop {r3} 8007d28: 469e mov lr, r3 8007d2a: 4770 bx lr 08007d2c <_fini>: 8007d2c: b5f8 push {r3, r4, r5, r6, r7, lr} 8007d2e: 46c0 nop @ (mov r8, r8) 8007d30: bcf8 pop {r3, r4, r5, r6, r7} 8007d32: bc08 pop {r3} 8007d34: 469e mov lr, r3 8007d36: 4770 bx lr