diff --git a/N30-1812-1030G-8D-7PPR_REV-C(1).pdf b/N30-1812-1030G-8D-7PPR_REV-C(1).pdf
new file mode 100644
index 0000000..d5919f3
Binary files /dev/null and b/N30-1812-1030G-8D-7PPR_REV-C(1).pdf differ
diff --git a/code/.cproject b/code/.cproject
index 1f42a09..46c8023 100644
--- a/code/.cproject
+++ b/code/.cproject
@@ -34,7 +34,7 @@
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.288588021" name="MCU/MPU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
 								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1195911872" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.479801723" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.479801723" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.oz" valueType="enumerated"/>
 								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1746005180" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="DEBUG"/>
 									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
@@ -95,26 +95,26 @@
 				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.749563602" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
 					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.749563602." name="/" resourcePath="">
 						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.1719776956" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.95773864" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32C051C6Tx" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.337106446" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.2104311438" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1932361446" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.282411569" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32C051C6Tx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32C0xx_HAL_Driver/Inc | ../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32C0xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32C051xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32C051C6TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.743590200" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="48" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.95773864" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32C051C6Tx" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.337106446" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.2104311438" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1932361446" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.282411569" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32C051C6Tx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32C0xx_HAL_Driver/Inc | ../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32C0xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32C051xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32C051C6TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.debug.option.cpuclock.743590200" name="Cpu clock frequence" superClass="com.st.stm32cube.ide.mcu.debug.option.cpuclock" useByScannerDiscovery="false" value="48" valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1241986810" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
-							<builder buildPath="${workspace_loc:/feeder_mk2}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.189486637" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
+							<builder buildPath="${workspace_loc:/feeder_mk2}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.189486637" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.469570881" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1409120056" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1409120056" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1350547342" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.833784897" name="MCU/MPU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1950948351" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.60763210" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.2064160852" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1950948351" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.60763210" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.2064160852" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
 									<listOptionValue builtIn="false" value="STM32C051xx"/>
 								</option>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.359433534" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.359433534" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
 									<listOptionValue builtIn="false" value="../Core/Inc"/>
 									<listOptionValue builtIn="false" value="../Drivers/STM32C0xx_HAL_Driver/Inc"/>
 									<listOptionValue builtIn="false" value="../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy"/>
@@ -124,11 +124,11 @@
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.865476332" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.937925286" name="MCU/MPU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1144563673" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.637665107" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1144563673" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.637665107" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.77660645" name="MCU/MPU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1452135767" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32C051C6TX_FLASH.ld}" valueType="string"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1452135767" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32C051C6TX_FLASH.ld}" valueType="string"/>
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.376051529" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
@@ -169,29 +169,29 @@
 				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.debug" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1773838781" name="Debug" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug">
 					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.debug.1773838781." name="/" resourcePath="">
 						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug.534348417" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.debug">
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.849888053" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32C051C6Tx" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.109976386" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1271013541" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1345114919" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1700257373" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32C051C6Tx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32C0xx_HAL_Driver/Inc | ../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32C0xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32C051xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32C051C6TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.849888053" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32C051C6Tx" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.109976386" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.1271013541" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.1345114919" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.1700257373" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Debug || true || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32C051C6Tx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32C0xx_HAL_Driver/Inc | ../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32C0xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32C051xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32C051C6TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.599884550" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
-							<builder buildPath="${workspace_loc:/feeder_mk2}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1109463696" managedBuildOn="true" name="Gnu Make Builder.Debug" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
+							<builder buildPath="${workspace_loc:/feeder_mk2}/Debug" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.1109463696" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.1289664662" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1121963870" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.1100620306" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" valueType="definedSymbols">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.1121963870" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols.1100620306" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.definedsymbols" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="DEBUG"/>
 								</option>
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.16753259" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.897816544" name="MCU/MPU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.2124147385" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.813582153" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level"/>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.209402282" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" valueType="definedSymbols">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.2124147385" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.813582153" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.209402282" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="DEBUG"/>
 									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
 									<listOptionValue builtIn="false" value="STM32C051xx"/>
 								</option>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.80289720" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" valueType="includePath">
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.80289720" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
 									<listOptionValue builtIn="false" value="../Core/Inc"/>
 									<listOptionValue builtIn="false" value="../Drivers/STM32C0xx_HAL_Driver/Inc"/>
 									<listOptionValue builtIn="false" value="../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy"/>
@@ -201,11 +201,11 @@
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.861865851" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.1336897310" name="MCU/MPU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1512288779" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1559001255" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1512288779" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g3" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.1559001255" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false"/>
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.969750042" name="MCU/MPU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1802035541" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32C051C6TX_FLASH.ld}" valueType="string"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.1802035541" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32C051C6TX_FLASH.ld}" valueType="string"/>
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.936374392" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
@@ -246,25 +246,25 @@
 				<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="rm -rf" description="" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1813768786" name="Release" parent="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release">
 					<folderInfo id="com.st.stm32cube.ide.mcu.gnu.managedbuild.config.exe.release.1813768786." name="/" resourcePath="">
 						<toolChain id="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release.594971184" name="MCU ARM GCC" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.toolchain.exe.release">
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.631510249" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" value="STM32C051C6Tx" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1777976030" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.71133310" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" value="0" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.992413084" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" value="genericBoard" valueType="string"/>
-							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.116796964" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32C051C6Tx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32C0xx_HAL_Driver/Inc | ../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32C0xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32C051xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32C051C6TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu.631510249" name="MCU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_mcu" useByScannerDiscovery="true" value="STM32C051C6Tx" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid.1777976030" name="CPU" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_cpuid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid.71133310" name="Core" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_coreid" useByScannerDiscovery="false" value="0" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board.992413084" name="Board" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.target_board" useByScannerDiscovery="false" value="genericBoard" valueType="string"/>
+							<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults.116796964" name="Defaults" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.option.defaults" useByScannerDiscovery="false" value="com.st.stm32cube.ide.common.services.build.inputs.revA.1.0.6 || Release || false || Executable || com.st.stm32cube.ide.mcu.gnu.managedbuild.option.toolchain.value.workspace || STM32C051C6Tx || 0 || 0 || arm-none-eabi- || ${gnu_tools_for_stm32_compiler_path} || ../Core/Inc | ../Drivers/STM32C0xx_HAL_Driver/Inc | ../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy | ../Drivers/CMSIS/Device/ST/STM32C0xx/Include | ../Drivers/CMSIS/Include ||  ||  || USE_HAL_DRIVER | STM32C051xx ||  || Drivers | Core/Startup | Core ||  ||  || ${workspace_loc:/${ProjName}/STM32C051C6TX_FLASH.ld} || true || NonSecure ||  || secure_nsclib.o ||  || None ||  ||  || " valueType="string"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform.1962359373" isAbstract="false" osList="all" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.targetplatform"/>
-							<builder buildPath="${workspace_loc:/feeder_mk2}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.649701287" managedBuildOn="true" name="Gnu Make Builder.Release" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
+							<builder buildPath="${workspace_loc:/feeder_mk2}/Release" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder.649701287" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" parallelBuildOn="true" parallelizationNumber="optimal" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.builder"/>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.121254354" name="MCU/MPU GCC Assembler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.615900473" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.615900473" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.option.debuglevel.value.g0" valueType="enumerated"/>
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input.1576766624" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.assembler.input"/>
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.1690084034" name="MCU/MPU GCC Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1261288323" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.719313019" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1660359632" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" valueType="definedSymbols">
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.1261288323" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.719313019" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols.1660359632" name="Define symbols (-D)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.definedsymbols" useByScannerDiscovery="false" valueType="definedSymbols">
 									<listOptionValue builtIn="false" value="USE_HAL_DRIVER"/>
 									<listOptionValue builtIn="false" value="STM32C051xx"/>
 								</option>
-								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.328209715" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" valueType="includePath">
+								<option IS_BUILTIN_EMPTY="false" IS_VALUE_EMPTY="false" id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths.328209715" name="Include paths (-I)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.option.includepaths" useByScannerDiscovery="false" valueType="includePath">
 									<listOptionValue builtIn="false" value="../Core/Inc"/>
 									<listOptionValue builtIn="false" value="../Drivers/STM32C0xx_HAL_Driver/Inc"/>
 									<listOptionValue builtIn="false" value="../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy"/>
@@ -274,11 +274,11 @@
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c.1727265949" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.compiler.input.c"/>
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.844134411" name="MCU/MPU G++ Compiler" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1314731639" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.743635977" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.1314731639" name="Debug level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.debuglevel.value.g0" valueType="enumerated"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.743635977" name="Optimization level" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level" useByScannerDiscovery="false" value="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.cpp.compiler.option.optimization.level.value.os" valueType="enumerated"/>
 							</tool>
 							<tool id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.1128945908" name="MCU/MPU GCC Linker" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker">
-								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.108416306" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32C051C6TX_FLASH.ld}" valueType="string"/>
+								<option id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script.108416306" name="Linker Script (-T)" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.option.script" value="${workspace_loc:/${ProjName}/STM32C051C6TX_FLASH.ld}" valueType="string"/>
 								<inputType id="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input.1670379260" superClass="com.st.stm32cube.ide.mcu.gnu.managedbuild.tool.c.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
@@ -325,4 +325,5 @@
 			<autodiscovery enabled="false" problemReportingEnabled="true" selectedProfileId=""/>
 		</scannerConfigBuildInfo>
 	</storageModule>
+	<storageModule moduleId="refreshScope"/>
 </cproject>
\ No newline at end of file
diff --git a/code/.mxproject b/code/.mxproject
index 76f15e0..a711598 100644
--- a/code/.mxproject
+++ b/code/.mxproject
@@ -1,8 +1,8 @@
 [PreviousLibFiles]
-LibFiles=Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_utils.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_bus.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ramfunc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_usart.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_dmamux.h;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_utils.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_bus.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ramfunc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_usart.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c051xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
+LibFiles=Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_utils.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_bus.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ramfunc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_usart.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_dmamux.h;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_utils.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_bus.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ramfunc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_usart.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_uart_ex.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c051xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h;
 
 [PreviousUsedCubeIDEFiles]
-SourceFiles=Core\Src\main.c;Core\Src\stm32c0xx_it.c;Core\Src\stm32c0xx_hal_msp.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Core\Src\system_stm32c0xx.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Core\Src\system_stm32c0xx.c;;;
+SourceFiles=Core\Src\main.c;Core\Src\stm32c0xx_it.c;Core\Src\stm32c0xx_hal_msp.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Core\Src\system_stm32c0xx.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_uart_ex.c;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Core\Src\system_stm32c0xx.c;;;
 HeaderPath=Drivers\STM32C0xx_HAL_Driver\Inc;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32C0xx\Include;Drivers\CMSIS\Include;Core\Inc;
 CDefines=USE_HAL_DRIVER;STM32C051xx;USE_HAL_DRIVER;USE_HAL_DRIVER;
 
diff --git a/code/Core/Inc/main.h b/code/Core/Inc/main.h
index 6984f07..70a48b4 100644
--- a/code/Core/Inc/main.h
+++ b/code/Core/Inc/main.h
@@ -65,6 +65,12 @@ void Error_Handler(void);
 #define PEEL1_GPIO_Port GPIOA
 #define PEEL2_Pin GPIO_PIN_3
 #define PEEL2_GPIO_Port GPIOA
+#define ONEWIRE_Pin GPIO_PIN_6
+#define ONEWIRE_GPIO_Port GPIOA
+#define IPROP_PEEL_Pin GPIO_PIN_7
+#define IPROP_PEEL_GPIO_Port GPIOA
+#define IPROP_DRIVE_Pin GPIO_PIN_12
+#define IPROP_DRIVE_GPIO_Port GPIOB
 #define DRIVE1_Pin GPIO_PIN_8
 #define DRIVE1_GPIO_Port GPIOA
 #define DRIVE2_Pin GPIO_PIN_9
@@ -73,8 +79,6 @@ void Error_Handler(void);
 #define QUAD_A_GPIO_Port GPIOC
 #define QUAD_B_Pin GPIO_PIN_7
 #define QUAD_B_GPIO_Port GPIOC
-#define ONEWIRE_Pin GPIO_PIN_10
-#define ONEWIRE_GPIO_Port GPIOA
 #define LED_R_Pin GPIO_PIN_3
 #define LED_R_GPIO_Port GPIOB
 #define LED_B_Pin GPIO_PIN_4
diff --git a/code/Core/Inc/pid.h b/code/Core/Inc/pid.h
index fa72206..1a16b13 100644
--- a/code/Core/Inc/pid.h
+++ b/code/Core/Inc/pid.h
@@ -82,8 +82,8 @@ static inline pid_motor_cmd_t pid_update_motor(pid_i32_t *pid,
 
     int32_t error = setpoint - position;
 
-    // Deadband: if within ±3 counts, hold position and reset integrator
-    if (error >= -3 && error <= 3) {
+    // Deadband: if within ±1 count (~0.005mm), hold position and reset integrator
+    if (error >= -1 && error <= 1) {
         pid->integrator = 0;
         pid->prev_error = 0;
         pid->last_output = 0;
diff --git a/code/Core/Inc/stm32c0xx_hal_conf.h b/code/Core/Inc/stm32c0xx_hal_conf.h
index 881fbee..5d3c356 100644
--- a/code/Core/Inc/stm32c0xx_hal_conf.h
+++ b/code/Core/Inc/stm32c0xx_hal_conf.h
@@ -35,7 +35,7 @@ extern "C" {
   * @brief This is the list of modules to be used in the HAL driver
   */
 #define HAL_MODULE_ENABLED
-/* #define HAL_ADC_MODULE_ENABLED   */
+#define HAL_ADC_MODULE_ENABLED
 /* #define HAL_CRC_MODULE_ENABLED   */
 /* #define HAL_CRYP_MODULE_ENABLED   */
 /* #define HAL_I2C_MODULE_ENABLED   */
diff --git a/code/Core/Inc/stm32c0xx_it.h b/code/Core/Inc/stm32c0xx_it.h
index 6da51f5..dc5a19c 100644
--- a/code/Core/Inc/stm32c0xx_it.h
+++ b/code/Core/Inc/stm32c0xx_it.h
@@ -57,6 +57,7 @@ void DMA1_Channel2_3_IRQHandler(void);
 void TIM14_IRQHandler(void);
 void TIM16_IRQHandler(void);
 void TIM17_IRQHandler(void);
+void USART2_IRQHandler(void);
 /* USER CODE BEGIN EFP */
 
 /* USER CODE END EFP */
diff --git a/code/Core/Src/main.c b/code/Core/Src/main.c
index 145addb..2662d23 100644
--- a/code/Core/Src/main.c
+++ b/code/Core/Src/main.c
@@ -55,16 +55,12 @@
 #define PEEL_TIME_PER_TENTH_MM 18          // ms per 0.1mm for forward peel
 #define BACKWARDS_PEEL_TIME_PER_TENTH_MM 30 // ms per 0.1mm for backward unpeel
 #define PEEL_BACKOFF_TIME 30               // ms to reverse peel after forward peel
-#define TIMEOUT_TIME_PER_TENTH_MM 40       // ms per 0.1mm before timeout
+#define TIMEOUT_TIME_PER_TENTH_MM 100      // ms per 0.1mm before timeout
 #define BACKWARDS_FEED_FILM_SLACK_REMOVAL_TIME 350 // ms to take up slack after backward
 #define BACKLASH_COMP_TENTH_MM 10          // 1mm backlash compensation
 #define FEED_SETTLE_TIME 50                // ms to wait for position to settle
-#define FEED_POSITION_TOLERANCE 5          // encoder counts tolerance for "arrived"
+#define FEED_POSITION_TOLERANCE 10         // encoder counts tolerance (~0.044mm)
 
-// Stall detection
-#define STALL_HISTORY_SIZE 20              // Number of samples for stall detection
-#define STALL_THRESHOLD 5                  // Max tick delta to consider stalled
-#define STALL_SAMPLE_INTERVAL_MS 1         // How often to sample position
 
 // OneWire timing (microseconds)
 #define ONEWIRE_DELAY_A 6
@@ -116,6 +112,7 @@ typedef enum {
 /* USER CODE END PM */
 
 /* Private variables ---------------------------------------------------------*/
+ADC_HandleTypeDef hadc1;
 
 TIM_HandleTypeDef htim1;
 TIM_HandleTypeDef htim3;
@@ -135,30 +132,33 @@ uint16_t encoder_previous=0;
 uint8_t UUID[UUID_LENGTH];
 uint8_t is_initialized=0;
 uint8_t network_buffer_RX[64];
-uint8_t msg_buffer1_empty = 1;
-uint8_t msg_buffer2_empty = 1;
-uint8_t msg_buffer1_size = 0;
-uint8_t msg_buffer2_size = 0;
-uint8_t msg_buffer1 [64];
-uint8_t msg_buffer2 [64];
+#define MSG_BUF_COUNT 54
+volatile uint8_t msg_buf_empty[MSG_BUF_COUNT];  // initialized in code
+volatile uint8_t msg_buf_size[MSG_BUF_COUNT] = {0};
+uint8_t msg_buf[MSG_BUF_COUNT][64];
 uint8_t DMA_buffer[64];
+volatile uint16_t rx_msg_count = 0;
 uint8_t my_address = 0xFF;
 int32_t total_count = 0;
 int32_t target_count = 0;
-int32_t kp = 6;
+int32_t kp = 4;
 int32_t ki = 1;
-int32_t kd = 3;
-int32_t i_min = -800;
-int32_t i_max = 800;
-int32_t pid_max_step = 25;
+int32_t kd = 6;
+int32_t i_min = -400;
+int32_t i_max = 400;
+int32_t pid_max_step = 30;
 pid_i32_t motor_pid;
 pid_motor_cmd_t motor_cmd;
 uint8_t vendor_options[VENDOR_SPECIFIC_OPTIONS_LENGTH];
 uint8_t feed_distance = 4;
 int32_t pid_add = 0;
+volatile int32_t brake_time_tenths = 30; // Adaptive braking in 0.1ms units (3.0ms initial)
 uint8_t last_feed_status = STATUS_OK;
 volatile uint8_t feed_in_progress = 0;
 volatile uint8_t feed_just_completed = 0; // flag set by ISR when feed completes
+volatile uint16_t feed_ok_count = 0;
+volatile uint16_t feed_fail_count = 0;
+volatile uint16_t feed_retry_total = 0;
 
 // Feed state machine
 volatile FeedState feed_state = FEED_STATE_IDLE;
@@ -171,9 +171,6 @@ int32_t feed_target_position = 0;      // target encoder position for current ph
 uint8_t feed_retry_count = 0;          // retry counter
 #define FEED_RETRY_LIMIT 3
 
-// Tape type detection
-uint8_t first_feed_since_load = 1;     // flag for first feed calibration
-uint8_t beefy_tape = 0;                // thick tape detected
 
 // Version string
 const char VERSION_STRING[] = "2.0.0-dev";
@@ -193,13 +190,6 @@ uint8_t sw2_long_handled = 0;
 uint8_t both_pressed_handled = 0;
 uint32_t both_pressed_start = 0; // timestamp for both-button hold timing
 
-// Stall detection
-int32_t stall_history[STALL_HISTORY_SIZE];
-uint8_t stall_history_index = 0;
-uint32_t last_stall_sample_time = 0;
-uint8_t stall_cooldown = 0;
-uint32_t stall_cooldown_time = 0;
-uint8_t current_drive_value = 30;  // Current PWM value during approach
 
 // Floor address (from EEPROM)
 uint8_t floor_address = FLOOR_ADDRESS_NOT_DETECTED;
@@ -212,7 +202,7 @@ int32_t mm_position = 0;  // Position in tenths of mm
 #define DEBUG_OUTPUT_INTERVAL_MS 100
 uint32_t last_debug_output_time = 0;
 uint8_t debug_enabled = 1;
-char debug_tx_buffer[80];
+char debug_tx_buffer[96];
 volatile int16_t debug_pid_output = 0;  // Captured from ISR for debug
 /* USER CODE END PV */
 
@@ -227,6 +217,7 @@ static void MX_USART2_UART_Init(void);
 static void MX_TIM16_Init(void);
 static void MX_TIM17_Init(void);
 static void MX_TIM14_Init(void);
+static void MX_ADC1_Init(void);
 /* USER CODE BEGIN PFP */
 
 void set_LED (uint8_t R, uint8_t G, uint8_t B);
@@ -247,19 +238,13 @@ void feed_state_machine_update(void);
 void set_feed_target_counts(int16_t distance_tenths);
 int32_t tenths_to_counts(int16_t tenths);
 uint16_t calculate_expected_feed_time(uint8_t distance, uint8_t forward);
-void check_tape_loaded(void);
 
 // Stall detection
-void stall_detection_init(void);
-uint8_t check_stall(int32_t current_tick);
-void stall_detection_update(int32_t current_tick);
 
 // OneWire / EEPROM functions
 void onewire_delay_us(uint32_t us);
-void onewire_set_output(void);
-void onewire_set_input(void);
-void onewire_write_low(void);
-void onewire_write_high(void);
+void onewire_drive_low(void);
+void onewire_release(void);
 uint8_t onewire_read_bit(void);
 uint8_t onewire_reset(void);
 void onewire_write_bit(uint8_t bit);
@@ -323,6 +308,7 @@ int main(void)
   MX_TIM16_Init();
   MX_TIM17_Init();
   MX_TIM14_Init();
+  MX_ADC1_Init();
   /* USER CODE BEGIN 2 */
 
   uint32_t * puuid = (uint32_t *)UUID;
@@ -342,9 +328,6 @@ int main(void)
   // Start PID control timer (TIM14) with interrupt
   HAL_TIM_Base_Start_IT(&htim14);
 
-  // Initialize stall detection
-  stall_detection_init();
-
   // Read floor address from EEPROM
   floor_address = read_floor_address();
   if (floor_address == FLOOR_ADDRESS_NOT_DETECTED)
@@ -366,7 +349,11 @@ int main(void)
 	  set_LED(0, 0, 0);
   }
 
+  for (uint8_t i = 0; i < MSG_BUF_COUNT; i++) msg_buf_empty[i] = 1;
+
   HAL_UARTEx_ReceiveToIdle_DMA (&huart2,DMA_buffer,64);
+  __HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT); // Disable half-transfer interrupt
+  __HAL_UART_ENABLE_IT(&huart2, UART_IT_ERR); // Enable error interrupt for overrun recovery
 
   /* USER CODE END 2 */
 
@@ -562,25 +549,14 @@ int main(void)
 		  }
 	  }
 
-	  if (!msg_buffer1_empty) // msg 1 buffer has a message
+	  for (uint8_t bi = 0; bi < MSG_BUF_COUNT; bi++)
 	  {
-		  handleRS485Message(msg_buffer1, msg_buffer1_size);
-		  for (uint8_t i = 0; i<64 ; i++)
+		  if (!msg_buf_empty[bi])
 		  {
-			  msg_buffer1[i]=0;
+			  handleRS485Message(msg_buf[bi], msg_buf_size[bi]);
+			  msg_buf_size[bi] = 0;
+			  msg_buf_empty[bi] = 1;
 		  }
-		  msg_buffer1_size = 0;
-		  msg_buffer1_empty = 1;
-	  }
-	  if (!msg_buffer2_empty) // msg 2 buffer has a message
-	  {
-		  handleRS485Message(msg_buffer2, msg_buffer2_size);
-		  for (uint8_t i = 0; i<64 ; i++)
-		  {
-			  msg_buffer2[i]=0;
-		  }
-		  msg_buffer2_size = 0;
-		  msg_buffer2_empty = 1;
 	  }
 
 
@@ -629,6 +605,71 @@ void SystemClock_Config(void)
   }
 }
 
+/**
+  * @brief ADC1 Initialization Function
+  * @param None
+  * @retval None
+  */
+static void MX_ADC1_Init(void)
+{
+
+  /* USER CODE BEGIN ADC1_Init 0 */
+
+  /* USER CODE END ADC1_Init 0 */
+
+  ADC_ChannelConfTypeDef sConfig = {0};
+
+  /* USER CODE BEGIN ADC1_Init 1 */
+
+  /* USER CODE END ADC1_Init 1 */
+
+  /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion)
+  */
+  hadc1.Instance = ADC1;
+  hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
+  hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+  hadc1.Init.ScanConvMode = ADC_SCAN_SEQ_FIXED;
+  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+  hadc1.Init.LowPowerAutoWait = DISABLE;
+  hadc1.Init.LowPowerAutoPowerOff = DISABLE;
+  hadc1.Init.ContinuousConvMode = DISABLE;
+  hadc1.Init.NbrOfConversion = 1;
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+  hadc1.Init.DMAContinuousRequests = DISABLE;
+  hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+  hadc1.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_1CYCLE_5;
+  hadc1.Init.OversamplingMode = DISABLE;
+  hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_7;
+  sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+
+  /** Configure Regular Channel
+  */
+  sConfig.Channel = ADC_CHANNEL_22;
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+  {
+    Error_Handler();
+  }
+  /* USER CODE BEGIN ADC1_Init 2 */
+
+  /* USER CODE END ADC1_Init 2 */
+
+}
+
 /**
   * @brief TIM1 Initialization Function
   * @param None
@@ -941,7 +982,7 @@ static void MX_USART2_UART_Init(void)
   huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
   huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
   huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
-  if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 0, 0) != HAL_OK)
+  if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 31, 31) != HAL_OK)
   {
     Error_Handler();
   }
@@ -997,8 +1038,8 @@ static void MX_GPIO_Init(void)
   /* GPIO Ports Clock Enable */
   __HAL_RCC_GPIOF_CLK_ENABLE();
   __HAL_RCC_GPIOA_CLK_ENABLE();
-  __HAL_RCC_GPIOC_CLK_ENABLE();
   __HAL_RCC_GPIOB_CLK_ENABLE();
+  __HAL_RCC_GPIOC_CLK_ENABLE();
 
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
@@ -1006,12 +1047,19 @@ static void MX_GPIO_Init(void)
   /*Configure GPIO pin Output Level */
   HAL_GPIO_WritePin(GPIOB, LED_R_Pin|LED_B_Pin|LED_G_Pin, GPIO_PIN_RESET);
 
-  /*Configure GPIO pins : USART2_NRE_Pin ONEWIRE_Pin */
-  GPIO_InitStruct.Pin = USART2_NRE_Pin|ONEWIRE_Pin;
+  /*Configure GPIO pin : USART2_NRE_Pin */
+  GPIO_InitStruct.Pin = USART2_NRE_Pin;
   GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
   GPIO_InitStruct.Pull = GPIO_NOPULL;
   GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+  HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
+
+  /*Configure GPIO pin : ONEWIRE_Pin */
+  GPIO_InitStruct.Pin = ONEWIRE_Pin;
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+  HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
 
   /*Configure GPIO pins : LED_R_Pin LED_B_Pin LED_G_Pin */
   GPIO_InitStruct.Pin = LED_R_Pin|LED_B_Pin|LED_G_Pin;
@@ -1089,9 +1137,59 @@ void HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef * htim)
 			}
 			target_count = temp;
 		}
-		motor_cmd = pid_update_motor(&motor_pid,target_count,total_count);
-		debug_pid_output = motor_cmd.dir ? motor_cmd.pwm : -motor_cmd.pwm; // Capture for debug
-		set_Feeder_PWM(motor_cmd.pwm,motor_cmd.dir);
+
+		// Velocity-based predictive braking
+		{
+			// Measure velocity every 1ms (20 ISR cycles at 20kHz)
+			static int32_t vel_prev_pos = 0;
+			static uint8_t vel_counter = 0;
+			static int32_t velocity = 0; // counts per 1ms
+
+			vel_counter++;
+			if (vel_counter >= 20)
+			{
+				velocity = total_count - vel_prev_pos;
+				vel_prev_pos = total_count;
+				vel_counter = 0;
+			}
+
+			// Detect standstill: position unchanged for 2ms
+			static int32_t last_moved_pos = 0;
+			static uint16_t still_counter = 0;
+			if (total_count != last_moved_pos)
+			{
+				last_moved_pos = total_count;
+				still_counter = 0;
+			}
+			else if (still_counter < 1000)
+			{
+				still_counter++;
+			}
+			uint8_t is_stopped = still_counter > 40; // 40 * 50us = 2ms
+
+			int32_t error = target_count - total_count;
+
+			int32_t brake_distance = velocity * brake_time_tenths / 10;
+
+			if (error > FEED_POSITION_TOLERANCE && (is_stopped || error > brake_distance))
+			{
+				set_Feeder_PWM(PWM_MAX, 1); // Full forward
+				debug_pid_output = PWM_MAX;
+			}
+			else if (error < -FEED_POSITION_TOLERANCE)
+			{
+				// Significantly past target: reverse (retry backup)
+				set_Feeder_PWM(PWM_MAX, 0); // Full reverse
+				debug_pid_output = -PWM_MAX;
+			}
+			else
+			{
+				// Within tolerance: brake
+				htim1.Instance->CCR1 = PWM_MAX;
+				htim1.Instance->CCR2 = PWM_MAX;
+				debug_pid_output = 0;
+			}
+		}
 
 		// Note: Feed completion is now handled by feed_state_machine_update() in main loop
 
@@ -1140,23 +1238,34 @@ void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
 void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
 {
     if (Size > 64) return; // todo error handling
-    if (msg_buffer1_empty)
+    rx_msg_count++;
+    for (uint8_t i = 0; i < MSG_BUF_COUNT; i++)
     {
-    	memcpy(msg_buffer1, DMA_buffer, Size);
-    	msg_buffer1_empty = 0;
-    	msg_buffer1_size = Size;
-    }
-    else if (msg_buffer2_empty)
-    {
-    	memcpy(msg_buffer2, DMA_buffer, Size);
-    	msg_buffer2_empty = 0;
-    	msg_buffer2_size = Size;
-    }
-    else // no free buffer available todo error handling
-    {
-    	return;
+    	if (msg_buf_empty[i])
+    	{
+    		memcpy(msg_buf[i], DMA_buffer, Size);
+    		msg_buf_size[i] = Size;
+    		msg_buf_empty[i] = 0;
+    		break;
+    	}
     }
+    // Always re-arm DMA — even if all buffers full, keep listening
     HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
+    __HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT);
+}
+
+volatile uint16_t uart_error_count = 0;
+
+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
+{
+    if (huart->Instance == USART2)
+    {
+        uart_error_count++;
+        // Clear all error flags and re-arm DMA
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_FEF | UART_CLEAR_NEF | UART_CLEAR_PEF);
+        HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
+        __HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT);
+    }
 }
 
 void set_LED (uint8_t R, uint8_t G, uint8_t B)
@@ -1169,6 +1278,18 @@ void set_LED (uint8_t R, uint8_t G, uint8_t B)
 	HAL_GPIO_WritePin(LED_B_GPIO_Port,LED_B_Pin,B);
 }
 
+void rs485_transmit(uint8_t *data, uint16_t len)
+{
+	// Turnaround delay — let controller switch to RX mode
+	HAL_Delay(1);
+	// Disable receiver, transmit, re-enable receiver, re-arm DMA
+	HAL_GPIO_WritePin(USART2_NRE_GPIO_Port, USART2_NRE_Pin, GPIO_PIN_SET); // NRE high = receiver off
+	HAL_UART_Transmit(&huart2, data, len, 100);
+	HAL_GPIO_WritePin(USART2_NRE_GPIO_Port, USART2_NRE_Pin, GPIO_PIN_RESET); // NRE low = receiver on
+	HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
+	__HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT);
+}
+
 void comp_crc_header(CRC8_107 *lcrc, PhotonResponse *lresponse)
 {
 	CRC8_107_add(lcrc,lresponse->header.toAddress);
@@ -1177,16 +1298,40 @@ void comp_crc_header(CRC8_107 *lcrc, PhotonResponse *lresponse)
 	CRC8_107_add(lcrc,lresponse->header.payloadLength);
 }
 
+volatile uint16_t drop_size = 0;
+volatile uint16_t drop_crc = 0;
+volatile uint16_t drop_addr = 0;
+volatile uint16_t msg_handled = 0;
+volatile uint8_t last_rx_size = 0;
+volatile uint8_t last_rx_to = 0;
+volatile uint8_t last_rx_cmd = 0;
+volatile uint8_t last_rx_bytes[8] = {0};
+volatile uint8_t my_addr_bytes[8] = {0};  // trap: last packet addressed to us
+volatile uint8_t my_addr_size = 0;
+volatile uint8_t my_addr_crc_exp = 0;
+
 void handleRS485Message(uint8_t *buffer, uint8_t size)
 {
 	PhotonPacketHeader *header = (PhotonPacketHeader *) buffer;
+	last_rx_size = size;
+	for (uint8_t i = 0; i < 8 && i < size; i++) last_rx_bytes[i] = buffer[i];
+
+	// Trap packets addressed to us (before any validation)
+	if (size >= 1 && buffer[0] == my_address)
+	{
+		my_addr_size = size;
+		for (uint8_t i = 0; i < 8 && i < size; i++) my_addr_bytes[i] = buffer[i];
+	}
 
 	// Validate minimum packet size
 	if (size < sizeof(PhotonPacketHeader) + 1) // header + at least commandId
 	{
+		drop_size++;
 		return; // packet too small
 	}
 
+	last_rx_to = header->toAddress;
+
 	// Validate CRC
 	CRC8_107 rx_crc;
 	CRC8_107_init(&rx_crc);
@@ -1201,6 +1346,9 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 	}
 	if (CRC8_107_getChecksum(&rx_crc) != header->crc)
 	{
+		drop_crc++;
+		if (header->toAddress == my_address)
+			my_addr_crc_exp = CRC8_107_getChecksum(&rx_crc);
 		return; // CRC mismatch, discard packet
 	}
 
@@ -1208,10 +1356,13 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 	if ((header->toAddress != PHOTON_NETWORK_BROADCAST_ADDRESS) &&
 		(header->toAddress != my_address))
 	{
+		drop_addr++;
 		return; // message not for us
 	}
 
 	// this message is relevant to this device (unicast to us or broadcast)
+	msg_handled++;
+	last_rx_cmd = buffer[sizeof(PhotonPacketHeader)]; // commandId
 	{
 		PhotonCommand *command = (PhotonCommand *) buffer;
 		PhotonResponse response;
@@ -1227,17 +1378,17 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 			case GET_FEEDER_ID:
 				memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH);
 				response.status = STATUS_OK;
+				response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for status byte
 
 				comp_crc_header(&crc,&response);
-				payload_ptr =(uint8_t*) &response.payload;
-				for (uint32_t i = 0; i<sizeof(response.payload.getFeederId)+1; i++)
+				payload_ptr =(uint8_t*) &response.status;
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
 				{
 					CRC8_107_add(&crc,*(payload_ptr+i));
 				}
 				response.header.crc = CRC8_107_getChecksum(&crc);
-				response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for the length byte
 				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
+				rs485_transmit((uint8_t *)&response, packet_len);
 				break;
 			case INITIALIZE_FEEDER:
 				memcpy(response.payload.initializeFeeder.uuid,UUID,UUID_LENGTH);
@@ -1250,31 +1401,31 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 				{
 					response.status = STATUS_WRONG_FEEDER_ID;
 				}
+				response.header.payloadLength = sizeof(response.payload.initializeFeeder)+1;
 
 				comp_crc_header(&crc,&response);
-				payload_ptr =(uint8_t*) &response.payload;
-				for (uint32_t i = 0; i<sizeof(response.payload.initializeFeeder)+1; i++)
+				payload_ptr =(uint8_t*) &response.status;
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
 				{
 					CRC8_107_add(&crc,*(payload_ptr+i));
 				}
 				response.header.crc = CRC8_107_getChecksum(&crc);
-				response.header.payloadLength = sizeof(response.payload.initializeFeeder)+1; // +1 for the length byte
 				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
+				rs485_transmit((uint8_t *)&response, packet_len);
 				break;
 			case GET_VERSION:
 				response.status = STATUS_OK;
 				response.payload.protocolVersion.version = PROTOCOL_VERSION;
+				response.header.payloadLength = sizeof(response.payload.protocolVersion)+1;
 				comp_crc_header(&crc,&response);
-				payload_ptr =(uint8_t*) &response.payload;
-				for (uint32_t i = 0; i<sizeof(response.payload.protocolVersion)+1; i++)
+				payload_ptr =(uint8_t*) &response.status;
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
 				{
 					CRC8_107_add(&crc,*(payload_ptr+i));
 				}
 				response.header.crc = CRC8_107_getChecksum(&crc);
-				response.header.payloadLength = sizeof(response.payload.protocolVersion)+1; // +1 for the length byte
 				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
+				rs485_transmit((uint8_t *)&response, packet_len);
 
 				break;
 			case MOVE_FEED_FORWARD:
@@ -1291,7 +1442,7 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 					}
 					response.header.crc = CRC8_107_getChecksum(&crc);
 					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-					HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100);
+					rs485_transmit((uint8_t *)&response, packet_len);
 					break;
 				}
 				{
@@ -1308,7 +1459,7 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 					}
 					response.header.crc = CRC8_107_getChecksum(&crc);
 					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-					HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100);
+					rs485_transmit((uint8_t *)&response, packet_len);
 					start_feed(command->payload.move.distance, 1);
 				}
 				break;
@@ -1326,7 +1477,7 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 					}
 					response.header.crc = CRC8_107_getChecksum(&crc);
 					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-					HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100);
+					rs485_transmit((uint8_t *)&response, packet_len);
 					break;
 				}
 				{
@@ -1343,7 +1494,7 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 					}
 					response.header.crc = CRC8_107_getChecksum(&crc);
 					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-					HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100);
+					rs485_transmit((uint8_t *)&response, packet_len);
 					start_feed(command->payload.move.distance, 0);
 				}
 				break;
@@ -1361,7 +1512,7 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 				CRC8_107_add(&crc, response.status);
 				response.header.crc = CRC8_107_getChecksum(&crc);
 				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
+				rs485_transmit((uint8_t *)&response, packet_len);
 				break;
 			case VENDOR_OPTIONS:
 				if (!is_initialized)
@@ -1377,7 +1528,7 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 					}
 					response.header.crc = CRC8_107_getChecksum(&crc);
 					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-					HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100);
+					rs485_transmit((uint8_t *)&response, packet_len);
 					break;
 				}
 				handle_vendor_options(command->payload.vendorOptions.options, response.payload.vendorOptions.options);
@@ -1391,7 +1542,7 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 				response.header.crc = CRC8_107_getChecksum(&crc);
 				response.header.payloadLength = sizeof(response.payload.vendorOptions)+1; // +1 for the status byte
 				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
+				rs485_transmit((uint8_t *)&response, packet_len);
 				break;
 			case GET_FEEDER_ADDRESS:
 				if(memcmp(UUID,command->payload.getFeederAddress.uuid,UUID_LENGTH) == 0)
@@ -1408,7 +1559,7 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 				CRC8_107_add(&crc,response.status);
 				response.header.crc = CRC8_107_getChecksum(&crc);
 				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
+				rs485_transmit((uint8_t *)&response, packet_len);
 				break;
 			case IDENTIFY_FEEDER:
 				if(memcmp(UUID,command->payload.identifyFeeder.uuid,UUID_LENGTH) == 0)
@@ -1425,7 +1576,7 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 				CRC8_107_add(&crc,response.status);
 				response.header.crc = CRC8_107_getChecksum(&crc);
 				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
+				rs485_transmit((uint8_t *)&response, packet_len);
 				identify_feeder();
 				break;
 			case PROGRAM_FEEDER_FLOOR:
@@ -1450,24 +1601,24 @@ void handleRS485Message(uint8_t *buffer, uint8_t size)
 					CRC8_107_add(&crc, response.status);
 					response.header.crc = CRC8_107_getChecksum(&crc);
 					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-					HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100);
+					rs485_transmit((uint8_t *)&response, packet_len);
 				}
 				break;
 			case UNINITIALIZED_FEEDERS_RESPOND:
 				if (is_initialized) return;
 				memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH);
-				response.header.payloadLength=sizeof(response.payload)+1;
 				response.status=STATUS_OK;
+				response.header.payloadLength = sizeof(response.payload.getFeederId)+1;
 
-				payload_ptr =(uint8_t*) &response.payload;
-				for (uint32_t i = 0; i<sizeof(response.payload.getFeederId)+1; i++)
+				comp_crc_header(&crc,&response);
+				payload_ptr =(uint8_t*) &response.status;
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
 				{
 					CRC8_107_add(&crc,*(payload_ptr+i));
 				}
 				response.header.crc = CRC8_107_getChecksum(&crc);
-				response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for the length byte
 				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
+				rs485_transmit((uint8_t *)&response, packet_len);
 				break;
 			default:
 				// todo error handling
@@ -1505,11 +1656,8 @@ void update_Feeder_Target(int32_t difference)
 
 
 
-#define FEED_PWM_MIN_THRESHOLD 840  // 35% of 2400 - below this, don't drive
-
 void set_Feeder_PWM(uint16_t PWM, uint8_t direction)
 {
-	if (PWM > 0 && PWM < FEED_PWM_MIN_THRESHOLD) PWM = 0;
 
 	if (direction)
 	{
@@ -1579,16 +1727,11 @@ void peel_ramp_update(void)
 
 void drive_continuous(uint8_t forward)
 {
-	// Bypass PID - set target far away in the desired direction so PID drives at max
-	pid_reset(&motor_pid);
+	// Set target far away so motor drives at full speed
 	if (forward)
-	{
 		target_count = total_count + 10000;
-	}
 	else
-	{
 		target_count = total_count - 10000;
-	}
 }
 
 void halt_all(void)
@@ -1603,9 +1746,8 @@ void halt_all(void)
 	htim1.Instance->CCR3 = 0;
 	htim1.Instance->CCR4 = 0;
 
-	// Reset PID state to prevent sudden movement
-	pid_reset(&motor_pid);
-	target_count = total_count; // Set target to current position
+	// Set target to current position to prevent further movement
+	target_count = total_count;
 	pid_add = 0;
 }
 
@@ -1633,8 +1775,9 @@ void show_version(void)
 // Convert distance in tenths of mm to encoder counts
 int32_t tenths_to_counts(int16_t tenths)
 {
-	// counts = (tenths * 1000 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV
-	int64_t temp = ((int64_t)tenths * 1000 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV;
+	// counts = (tenths * 100 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV
+	// 1 tenth-mm = 100um
+	int64_t temp = ((int64_t)tenths * 100 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV;
 	return (int32_t)temp;
 }
 
@@ -1646,15 +1789,7 @@ uint16_t calculate_expected_feed_time(uint8_t distance, uint8_t forward)
 		// Forward: peel time + peel backoff + drive time + extra for first feed
 		uint16_t time = (distance * PEEL_TIME_PER_TENTH_MM) +
 						PEEL_BACKOFF_TIME +
-						(distance * TIMEOUT_TIME_PER_TENTH_MM);
-		if (first_feed_since_load)
-		{
-			time += 1000; // Extra time for tape detection
-		}
-		else
-		{
-			time += 200;
-		}
+						(distance * TIMEOUT_TIME_PER_TENTH_MM) + 200;
 		return time;
 	}
 	else
@@ -1674,12 +1809,6 @@ void start_feed(int16_t distance_tenths, uint8_t forward)
 		return; // Already feeding
 	}
 
-	// Check for first feed calibration
-	if (first_feed_since_load)
-	{
-		check_tape_loaded();
-		first_feed_since_load = 0;
-	}
 
 	feed_distance_tenths = distance_tenths;
 	feed_direction = forward;
@@ -1750,39 +1879,25 @@ void feed_state_machine_update(void)
 			break;
 
 		case FEED_STATE_DRIVING:
-			// Check for position reached and stall detection
+			// Check for position reached, overshoot, and timeout
 			{
 				int32_t error = feed_target_position - total_count;
-				if (error < 0) error = -error;
+				int32_t abs_error = error < 0 ? -error : error;
 
-				// Update stall detection
-				stall_detection_update(total_count);
+				// Brake time adjustment based on error magnitude
+				// <5: none, >=5: ±5, >=10: ±10, >=20: ±20
+				int32_t brake_adj = abs_error >= 20 ? 20 : abs_error >= 10 ? 10 : abs_error >= 5 ? 5 : 0;
 
-				// Check for stall and increase power if needed
-				if (check_stall(total_count) && !stall_cooldown)
+				if (abs_error < FEED_POSITION_TOLERANCE)
 				{
-					current_drive_value += 3;
-					if (current_drive_value > 255) current_drive_value = 255;
-					stall_cooldown = 1;
-					stall_cooldown_time = now;
+					// Position reached - fine-tune brake time based on where we stopped
+					if (error < 0) // overshot
+						brake_time_tenths += brake_adj;
+					else if (error > 0 && brake_time_tenths > brake_adj) // undershot
+						brake_time_tenths -= brake_adj;
+					else if (error > 0)
+						brake_time_tenths = 1;
 
-					// If we're stalling a lot, mark as beefy tape
-					if (current_drive_value > 200)
-					{
-						beefy_tape = 1;
-					}
-				}
-
-				// Reset stall cooldown after 5ms
-				if (stall_cooldown && (now - stall_cooldown_time) > 5)
-				{
-					stall_cooldown = 0;
-				}
-
-				if (error < FEED_POSITION_TOLERANCE)
-				{
-					// Position reached
-					stall_detection_init(); // Reset stall detection
 					if (!feed_direction)
 					{
 						// Backward feed: take up slack then do final approach
@@ -1799,10 +1914,34 @@ void feed_state_machine_update(void)
 						feed_state_duration = FEED_SETTLE_TIME;
 					}
 				}
+				else if (error < -FEED_POSITION_TOLERANCE)
+				{
+					// Overshot - increase braking time, back up 1mm and re-approach
+					brake_time_tenths += brake_adj;
+					feed_retry_total++;
+					target_count = total_count - tenths_to_counts(10);
+					HAL_Delay(200);
+					htim1.Instance->CCR1 = PWM_MAX;
+					htim1.Instance->CCR2 = PWM_MAX;
+					HAL_Delay(50);
+					target_count = feed_target_position;
+					feed_state_start_time = now;
+					feed_timeout_time = HAL_GetTick() + (feed_distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
+				}
 				else if (now > feed_timeout_time)
 				{
-					// Timeout
-					feed_state = FEED_STATE_TIMEOUT;
+					// Fell short - decrease braking time, back up 1mm and re-approach
+					if (brake_time_tenths > brake_adj) brake_time_tenths -= brake_adj;
+					else brake_time_tenths = 1;
+					feed_retry_total++;
+					target_count = total_count - tenths_to_counts(10);
+					HAL_Delay(200);
+					htim1.Instance->CCR1 = PWM_MAX;
+					htim1.Instance->CCR2 = PWM_MAX;
+					HAL_Delay(50);
+					target_count = feed_target_position;
+					feed_state_start_time = now;
+					feed_timeout_time = HAL_GetTick() + (feed_distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
 				}
 			}
 			break;
@@ -1854,31 +1993,26 @@ void feed_state_machine_update(void)
 			feed_in_progress = 0;
 			last_feed_status = STATUS_OK;
 			feed_just_completed = 1;
+			feed_ok_count++;
 			break;
 
 		case FEED_STATE_TIMEOUT:
-			// Handle timeout - could retry or fail
+			// Handle timeout - back up 1mm to clear backlash, then retry
 			if (feed_retry_count < FEED_RETRY_LIMIT)
 			{
 				feed_retry_count++;
-				// Move back slightly and retry
-				target_count = total_count - tenths_to_counts(5); // Back up 0.5mm
-				HAL_Delay(50);
-				// Restart the feed
-				if (feed_direction)
-				{
-					feed_state = FEED_STATE_PEEL_FORWARD;
-					feed_state_start_time = HAL_GetTick();
-					feed_state_duration = feed_distance_tenths * PEEL_TIME_PER_TENTH_MM;
-					peel_motor(1);
-				}
-				else
-				{
-					feed_state = FEED_STATE_UNPEEL;
-					feed_state_start_time = HAL_GetTick();
-					feed_state_duration = feed_distance_tenths * BACKWARDS_PEEL_TIME_PER_TENTH_MM;
-					peel_motor(0);
-				}
+				feed_retry_total++;
+				// Back up 1mm (10 tenths) to overcome backlash
+				target_count = total_count - tenths_to_counts(10);
+				HAL_Delay(200); // Let motor reverse past backlash
+				// Brake and re-approach original target
+				htim1.Instance->CCR1 = PWM_MAX;
+				htim1.Instance->CCR2 = PWM_MAX;
+				HAL_Delay(50); // Settle
+				target_count = feed_target_position;
+				feed_state = FEED_STATE_DRIVING;
+				feed_state_start_time = now;
+				feed_timeout_time = HAL_GetTick() + (feed_distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
 			}
 			else
 			{
@@ -1887,6 +2021,7 @@ void feed_state_machine_update(void)
 				feed_in_progress = 0;
 				last_feed_status = STATUS_COULDNT_REACH;
 				feed_just_completed = 1;
+				feed_fail_count++;
 				halt_all();
 			}
 			break;
@@ -1897,53 +2032,6 @@ void feed_state_machine_update(void)
 	}
 }
 
-// Check what type of tape is loaded (thick vs thin)
-void check_tape_loaded(void)
-{
-	// Take up any backlash slack
-	set_Feeder_PWM(250, 0); // Brief reverse
-	HAL_Delay(2);
-	set_Feeder_PWM(20, 0);
-	HAL_Delay(100);
-	set_Feeder_PWM(0, 0);
-	HAL_Delay(10);
-
-	// Find starting threshold of movement
-	int32_t starting_count = total_count;
-	int moved_at = 256;
-
-	for (int pwm = 20; pwm < 255; pwm += 5)
-	{
-		set_Feeder_PWM(pwm, 0); // Drive backward
-		HAL_Delay(75);
-
-		int32_t diff = total_count - starting_count;
-		if (diff < 0) diff = -diff;
-
-		if (diff > 3) // Movement detected
-		{
-			moved_at = pwm;
-			break;
-		}
-	}
-
-	set_Feeder_PWM(0, 0);
-	HAL_Delay(10);
-
-	// Reset position
-	pid_reset(&motor_pid);
-	target_count = total_count;
-
-	if (moved_at > 140)
-	{
-		beefy_tape = 1; // Thick tape detected
-	}
-	else
-	{
-		beefy_tape = 0;
-	}
-}
-
 // Handle vendor-specific options
 void handle_vendor_options(uint8_t *options, uint8_t *response)
 {
@@ -1998,97 +2086,44 @@ void handle_vendor_options(uint8_t *options, uint8_t *response)
 	}
 }
 
-// ============================================================================
-// Stall Detection Functions
-// ============================================================================
-
-void stall_detection_init(void)
-{
-	for (int i = 0; i < STALL_HISTORY_SIZE; i++)
-	{
-		stall_history[i] = 0;
-	}
-	stall_history_index = 0;
-	last_stall_sample_time = 0;
-	stall_cooldown = 0;
-	current_drive_value = beefy_tape ? 255 : 30;
-}
-
-void stall_detection_update(int32_t current_tick)
-{
-	uint32_t now = HAL_GetTick();
-	if ((now - last_stall_sample_time) >= STALL_SAMPLE_INTERVAL_MS)
-	{
-		last_stall_sample_time = now;
-		stall_history[stall_history_index] = current_tick;
-		stall_history_index++;
-		if (stall_history_index >= STALL_HISTORY_SIZE)
-		{
-			stall_history_index = 0;
-		}
-	}
-}
-
-uint8_t check_stall(int32_t current_tick)
-{
-	// Find min and max in history
-	int32_t min_val = stall_history[0];
-	int32_t max_val = stall_history[0];
-
-	for (int i = 1; i < STALL_HISTORY_SIZE; i++)
-	{
-		if (stall_history[i] < min_val) min_val = stall_history[i];
-		if (stall_history[i] > max_val) max_val = stall_history[i];
-	}
-
-	int32_t delta = max_val - min_val;
-	return (delta <= STALL_THRESHOLD);
-}
-
 // ============================================================================
 // OneWire Functions (Bit-banging for DS2431 EEPROM)
 // ============================================================================
 
-// Microsecond delay using DWT cycle counter or busy loop
+// Microsecond delay using SysTick (cycle-accurate at 48MHz)
 void onewire_delay_us(uint32_t us)
 {
-	// Simple busy-wait delay - approximately calibrated for 48MHz
-	volatile uint32_t count = us * 12; // Adjust multiplier as needed
-	while (count--) { __NOP(); }
+	uint32_t cycles = us * 48;
+	uint32_t reload = SysTick->LOAD;
+	uint32_t prev = SysTick->VAL;
+	uint32_t elapsed = 0;
+	while (elapsed < cycles)
+	{
+		uint32_t now = SysTick->VAL;
+		if (now <= prev)
+			elapsed += prev - now;
+		else
+			elapsed += prev + reload + 1 - now;
+		prev = now;
+	}
 }
 
-void onewire_set_output(void)
+// Pin is always open-drain: SET = release (high-Z), RESET = drive low
+// Reading IDR works regardless since it's open-drain
+
+void onewire_drive_low(void)
 {
-	GPIO_InitTypeDef GPIO_InitStruct = {0};
-	GPIO_InitStruct.Pin = ONEWIRE_Pin;
-	GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; // Open-drain for OneWire
-	GPIO_InitStruct.Pull = GPIO_NOPULL;
-	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
-	HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
+	ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
 }
 
-void onewire_set_input(void)
+void onewire_release(void)
 {
-	GPIO_InitTypeDef GPIO_InitStruct = {0};
-	GPIO_InitStruct.Pin = ONEWIRE_Pin;
-	GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
-	GPIO_InitStruct.Pull = GPIO_PULLUP;
-	HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
-}
-
-void onewire_write_low(void)
-{
-	HAL_GPIO_WritePin(ONEWIRE_GPIO_Port, ONEWIRE_Pin, GPIO_PIN_RESET);
-}
-
-void onewire_write_high(void)
-{
-	HAL_GPIO_WritePin(ONEWIRE_GPIO_Port, ONEWIRE_Pin, GPIO_PIN_SET);
+	ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
 }
 
 uint8_t onewire_read_bit(void)
 {
-	return HAL_GPIO_ReadPin(ONEWIRE_GPIO_Port, ONEWIRE_Pin);
+	return (ONEWIRE_GPIO_Port->IDR & ONEWIRE_Pin) ? 1 : 0;
 }
 
 // Reset pulse - returns 1 if device present, 0 if not
@@ -2096,11 +2131,10 @@ uint8_t onewire_reset(void)
 {
 	uint8_t presence;
 
-	onewire_set_output();
-	onewire_write_low();
+	onewire_drive_low();
 	onewire_delay_us(ONEWIRE_DELAY_H); // 480us
 
-	onewire_set_input();
+	onewire_release();
 	onewire_delay_us(ONEWIRE_DELAY_I); // 70us
 
 	presence = !onewire_read_bit(); // Device pulls low if present
@@ -2112,22 +2146,20 @@ uint8_t onewire_reset(void)
 
 void onewire_write_bit(uint8_t bit)
 {
-	onewire_set_output();
-
 	if (bit)
 	{
 		// Write 1: pull low briefly, then release
-		onewire_write_low();
+		onewire_drive_low();
 		onewire_delay_us(ONEWIRE_DELAY_A); // 6us
-		onewire_write_high();
+		onewire_release();
 		onewire_delay_us(ONEWIRE_DELAY_B); // 64us
 	}
 	else
 	{
 		// Write 0: pull low for full slot
-		onewire_write_low();
+		onewire_drive_low();
 		onewire_delay_us(ONEWIRE_DELAY_C); // 60us
-		onewire_write_high();
+		onewire_release();
 		onewire_delay_us(ONEWIRE_DELAY_D); // 10us
 	}
 }
@@ -2136,11 +2168,10 @@ uint8_t onewire_read_bit_slot(void)
 {
 	uint8_t bit;
 
-	onewire_set_output();
-	onewire_write_low();
+	onewire_drive_low();
 	onewire_delay_us(ONEWIRE_DELAY_A); // 6us
 
-	onewire_set_input();
+	onewire_release();
 	onewire_delay_us(ONEWIRE_DELAY_E); // 9us
 
 	bit = onewire_read_bit();
@@ -2350,25 +2381,32 @@ void debug_output(void)
 	*p++ = ','; *p++ = 'F'; *p++ = ':';
 	*p++ = '0' + is_initialized;
 	*p++ = '0' + feed_in_progress;
-	*p++ = '0' + beefy_tape;
+
+	*p++ = ','; *p++ = 'C'; *p++ = ':';
+	p += debug_itoa(feed_ok_count, p);
+	*p++ = ':';
+	p += debug_itoa(feed_fail_count, p);
+	*p++ = ':';
+	p += debug_itoa(brake_time_tenths, p);
+	*p++ = ':';
+	p += debug_itoa(feed_retry_total, p);
 
 	*p++ = ','; *p++ = 'A'; *p++ = ':';
 	p += debug_hex8(my_address, p);
 
-	*p++ = ','; *p++ = 'B'; *p++ = ':';
-	*p++ = '0' + sw1_pressed;
-	*p++ = '0' + sw2_pressed;
-
-	// Raw GPIO pin state: 1=high(released), 0=low(pressed)
-	*p++ = ','; *p++ = 'G'; *p++ = ':';
-	*p++ = '0' + (uint8_t)HAL_GPIO_ReadPin(SW1_GPIO_Port, SW1_Pin);
-	*p++ = '0' + (uint8_t)HAL_GPIO_ReadPin(SW2_GPIO_Port, SW2_Pin);
-
-	*p++ = ','; *p++ = 'D'; *p++ = ':';
-	p += debug_itoa(current_drive_value, p);
-
-	*p++ = ','; *p++ = 'M'; *p++ = ':';
-	*p++ = '0' + drive_mode;
+	*p++ = ','; *p++ = 'R'; *p++ = ':';
+	p += debug_itoa(drop_crc, p);
+	*p++ = ':';
+	p += debug_itoa(msg_handled, p);
+	*p++ = ':';
+	p += debug_itoa(uart_error_count, p);
+	*p++ = ','; *p++ = 'T'; *p++ = ':';
+	p += debug_itoa(my_addr_size, p);
+	*p++ = ':';
+	for (uint8_t i = 0; i < 8 && i < my_addr_size; i++)
+		p += debug_hex8(my_addr_bytes[i], p);
+	*p++ = ':';
+	p += debug_hex8(my_addr_crc_exp, p);
 
 	*p++ = '*'; *p++ = '\r'; *p++ = '\n';
 
diff --git a/code/Core/Src/stm32c0xx_hal_msp.c b/code/Core/Src/stm32c0xx_hal_msp.c
index 8fd23f1..bc395f6 100644
--- a/code/Core/Src/stm32c0xx_hal_msp.c
+++ b/code/Core/Src/stm32c0xx_hal_msp.c
@@ -82,6 +82,89 @@ void HAL_MspInit(void)
   /* USER CODE END MspInit 1 */
 }
 
+/**
+  * @brief ADC MSP Initialization
+  * This function configures the hardware resources used in this example
+  * @param hadc: ADC handle pointer
+  * @retval None
+  */
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+  if(hadc->Instance==ADC1)
+  {
+    /* USER CODE BEGIN ADC1_MspInit 0 */
+
+    /* USER CODE END ADC1_MspInit 0 */
+
+  /** Initializes the peripherals clocks
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+    PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+    {
+      Error_Handler();
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC_CLK_ENABLE();
+
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+    /**ADC1 GPIO Configuration
+    PA7     ------> ADC1_IN7
+    PB12     ------> ADC1_IN22
+    */
+    GPIO_InitStruct.Pin = IPROP_PEEL_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
+
+    GPIO_InitStruct.Pin = IPROP_DRIVE_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(IPROP_DRIVE_GPIO_Port, &GPIO_InitStruct);
+
+    /* USER CODE BEGIN ADC1_MspInit 1 */
+
+    /* USER CODE END ADC1_MspInit 1 */
+
+  }
+
+}
+
+/**
+  * @brief ADC MSP De-Initialization
+  * This function freeze the hardware resources used in this example
+  * @param hadc: ADC handle pointer
+  * @retval None
+  */
+void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
+{
+  if(hadc->Instance==ADC1)
+  {
+    /* USER CODE BEGIN ADC1_MspDeInit 0 */
+
+    /* USER CODE END ADC1_MspDeInit 0 */
+    /* Peripheral clock disable */
+    __HAL_RCC_ADC_CLK_DISABLE();
+
+    /**ADC1 GPIO Configuration
+    PA7     ------> ADC1_IN7
+    PB12     ------> ADC1_IN22
+    */
+    HAL_GPIO_DeInit(IPROP_PEEL_GPIO_Port, IPROP_PEEL_Pin);
+
+    HAL_GPIO_DeInit(IPROP_DRIVE_GPIO_Port, IPROP_DRIVE_Pin);
+
+    /* USER CODE BEGIN ADC1_MspDeInit 1 */
+
+    /* USER CODE END ADC1_MspDeInit 1 */
+  }
+
+}
+
 /**
   * @brief TIM_Base MSP Initialization
   * This function configures the hardware resources used in this example
@@ -413,6 +496,9 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
 
     __HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx);
 
+    /* USART2 interrupt Init */
+    HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
+    HAL_NVIC_EnableIRQ(USART2_IRQn);
     /* USER CODE BEGIN USART2_MspInit 1 */
 
     /* USER CODE END USART2_MspInit 1 */
@@ -464,6 +550,9 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
     /* USART2 DMA DeInit */
     HAL_DMA_DeInit(huart->hdmarx);
     HAL_DMA_DeInit(huart->hdmatx);
+
+    /* USART2 interrupt DeInit */
+    HAL_NVIC_DisableIRQ(USART2_IRQn);
     /* USER CODE BEGIN USART2_MspDeInit 1 */
 
     /* USER CODE END USART2_MspDeInit 1 */
diff --git a/code/Core/Src/stm32c0xx_it.c b/code/Core/Src/stm32c0xx_it.c
index bf2500f..0fc9e11 100644
--- a/code/Core/Src/stm32c0xx_it.c
+++ b/code/Core/Src/stm32c0xx_it.c
@@ -60,6 +60,7 @@ extern TIM_HandleTypeDef htim16;
 extern TIM_HandleTypeDef htim17;
 extern DMA_HandleTypeDef hdma_usart2_rx;
 extern DMA_HandleTypeDef hdma_usart2_tx;
+extern UART_HandleTypeDef huart2;
 /* USER CODE BEGIN EV */
 
 /* USER CODE END EV */
@@ -229,6 +230,20 @@ void TIM17_IRQHandler(void)
   /* USER CODE END TIM17_IRQn 1 */
 }
 
+/**
+  * @brief This function handles USART2 interrupt.
+  */
+void USART2_IRQHandler(void)
+{
+  /* USER CODE BEGIN USART2_IRQn 0 */
+
+  /* USER CODE END USART2_IRQn 0 */
+  HAL_UART_IRQHandler(&huart2);
+  /* USER CODE BEGIN USART2_IRQn 1 */
+
+  /* USER CODE END USART2_IRQn 1 */
+}
+
 /* USER CODE BEGIN 1 */
 
 /* USER CODE END 1 */
diff --git a/code/Debug/Core/Src/crc.o b/code/Debug/Core/Src/crc.o
index c7cbf88..2d80f10 100644
Binary files a/code/Debug/Core/Src/crc.o and b/code/Debug/Core/Src/crc.o differ
diff --git a/code/Debug/Core/Src/crc.su b/code/Debug/Core/Src/crc.su
index 9c8295d..b0c4f5e 100644
--- a/code/Debug/Core/Src/crc.su
+++ b/code/Debug/Core/Src/crc.su
@@ -1,2 +1,2 @@
-../Core/Src/crc.c:10:6:CRC8_107_add	24	static
-../Core/Src/crc.c:21:9:CRC8_107_getChecksum	16	static
+../Core/Src/crc.c:10:6:CRC8_107_add	8	static
+../Core/Src/crc.c:21:9:CRC8_107_getChecksum	0	static
diff --git a/code/Debug/Core/Src/main.cyclo b/code/Debug/Core/Src/main.cyclo
index 786187e..32c5c7f 100644
--- a/code/Debug/Core/Src/main.cyclo
+++ b/code/Debug/Core/Src/main.cyclo
@@ -1,59 +1,40 @@
-../Drivers/CMSIS/Include/core_cm0plus.h:987:34:__NVIC_SystemReset	1
-../Core/Inc/pid.h:39:23:clamp_i32	3
-../Core/Inc/pid.h:46:20:pid_init	1
-../Core/Inc/pid.h:70:20:pid_reset	1
-../Core/Inc/pid.h:77:31:pid_update_motor	10
-../Core/Inc/crc.h:18:20:CRC8_107_init	1
-../Core/Src/main.c:291:5:main	58
-../Core/Src/main.c:598:6:SystemClock_Config	3
-../Core/Src/main.c:637:13:MX_TIM1_Init	10
-../Core/Src/main.c:731:13:MX_TIM3_Init	3
-../Core/Src/main.c:780:13:MX_TIM14_Init	2
-../Core/Src/main.c:811:13:MX_TIM16_Init	2
-../Core/Src/main.c:843:13:MX_TIM17_Init	2
-../Core/Src/main.c:875:13:MX_USART1_UART_Init	5
-../Core/Src/main.c:923:13:MX_USART2_UART_Init	5
-../Core/Src/main.c:969:13:MX_DMA_Init	1
-../Core/Src/main.c:990:13:MX_GPIO_Init	1
-../Core/Src/main.c:1040:6:HAL_TIM_PeriodElapsedCallback	15
-../Core/Src/main.c:1116:6:HAL_GPIO_EXTI_Falling_Callback	5
-../Core/Src/main.c:1140:6:HAL_UARTEx_RxEventCallback	4
-../Core/Src/main.c:1162:6:set_LED	4
-../Core/Src/main.c:1172:6:comp_crc_header	1
-../Core/Src/main.c:1180:6:handleRS485Message	41
-../Core/Src/main.c:1481:6:update_Feeder_Target	8
-../Core/Src/main.c:1510:6:set_Feeder_PWM	4
-../Core/Src/main.c:1526:6:peel_motor	2
-../Core/Src/main.c:1531:6:peel_brake	1
-../Core/Src/main.c:1536:6:peel_ramp_update	9
-../Core/Src/main.c:1580:6:drive_continuous	2
-../Core/Src/main.c:1594:6:halt_all	1
-../Core/Src/main.c:1612:6:identify_feeder	2
-../Core/Src/main.c:1624:6:show_version	1
-../Core/Src/main.c:1634:9:tenths_to_counts	1
-../Core/Src/main.c:1642:10:calculate_expected_feed_time	3
-../Core/Src/main.c:1670:6:start_feed	4
-../Core/Src/main.c:1714:6:feed_state_machine_update	29
-../Core/Src/main.c:1901:6:check_tape_loaded	5
-../Core/Src/main.c:1948:6:handle_vendor_options	7
-../Core/Src/main.c:2005:6:stall_detection_init	3
-../Core/Src/main.c:2017:6:stall_detection_update	3
-../Core/Src/main.c:2032:9:check_stall	4
-../Core/Src/main.c:2053:6:onewire_delay_us	2
-../Core/Src/main.c:2060:6:onewire_set_output	1
-../Core/Src/main.c:2070:6:onewire_set_input	1
-../Core/Src/main.c:2079:6:onewire_write_low	1
-../Core/Src/main.c:2084:6:onewire_write_high	1
-../Core/Src/main.c:2089:9:onewire_read_bit	1
-../Core/Src/main.c:2095:9:onewire_reset	1
-../Core/Src/main.c:2113:6:onewire_write_bit	2
-../Core/Src/main.c:2135:9:onewire_read_bit_slot	1
-../Core/Src/main.c:2153:6:onewire_write_byte	2
-../Core/Src/main.c:2162:9:onewire_read_byte	3
-../Core/Src/main.c:2177:9:read_floor_address	2
-../Core/Src/main.c:2207:9:write_floor_address	7
-../Core/Src/main.c:2302:9:debug_itoa	6
-../Core/Src/main.c:2318:9:debug_hex8	1
-../Core/Src/main.c:2326:6:debug_output	3
-../Core/Src/main.c:2382:6:reset_position_if_needed	3
-../Core/Src/main.c:2415:6:Error_Handler	1
+../Core/Src/main.c:574:6:SystemClock_Config	3
+../Core/Src/main.c:1088:6:HAL_TIM_PeriodElapsedCallback	19
+../Core/Src/main.c:1214:6:HAL_GPIO_EXTI_Falling_Callback	5
+../Core/Src/main.c:1238:6:HAL_UARTEx_RxEventCallback	4
+../Core/Src/main.c:1259:6:HAL_UART_ErrorCallback	2
+../Core/Src/main.c:1271:6:set_LED	1
+../Core/Src/main.c:1281:6:rs485_transmit	1
+../Core/Src/main.c:1293:6:comp_crc_header	1
+../Core/Src/main.c:1632:6:update_Feeder_Target	2
+../Core/Src/main.c:1659:6:set_Feeder_PWM	2
+../Core/Src/main.c:1674:6:peel_motor	1
+../Core/Src/main.c:1679:6:peel_brake	1
+../Core/Src/main.c:1684:6:peel_ramp_update	9
+../Core/Src/main.c:1728:6:drive_continuous	2
+../Core/Src/main.c:1737:6:halt_all	1
+../Core/Src/main.c:1754:6:identify_feeder	2
+../Core/Src/main.c:1766:6:show_version	1
+../Core/Src/main.c:1776:9:tenths_to_counts	1
+../Core/Src/main.c:1785:10:calculate_expected_feed_time	2
+../Core/Src/main.c:1805:6:start_feed	3
+../Core/Src/main.c:1843:6:feed_state_machine_update	29
+../Core/Src/main.c:2036:6:handle_vendor_options	5
+../Core/Src/main.c:2094:6:onewire_delay_us	3
+../Core/Src/main.c:2114:6:onewire_drive_low	1
+../Core/Src/main.c:2119:6:onewire_release	1
+../Core/Src/main.c:2124:9:onewire_read_bit	1
+../Core/Src/main.c:2130:9:onewire_reset	1
+../Core/Src/main.c:2147:6:onewire_write_bit	2
+../Core/Src/main.c:2167:9:onewire_read_bit_slot	1
+../Core/Src/main.c:2184:6:onewire_write_byte	2
+../Core/Src/main.c:2193:9:onewire_read_byte	2
+../Core/Src/main.c:2208:9:read_floor_address	2
+../Core/Src/main.c:2238:9:write_floor_address	6
+../Core/Src/main.c:1313:6:handleRS485Message	44
+../Core/Src/main.c:2333:9:debug_itoa	6
+../Core/Src/main.c:2349:9:debug_hex8	1
+../Core/Src/main.c:2357:6:debug_output	5
+../Core/Src/main.c:2420:6:reset_position_if_needed	3
+../Core/Src/main.c:276:5:main	69
+../Core/Src/main.c:2453:6:Error_Handler	1
diff --git a/code/Debug/Core/Src/main.d b/code/Debug/Core/Src/main.d
index 3a54d32..a79b84f 100644
--- a/code/Debug/Core/Src/main.d
+++ b/code/Debug/Core/Src/main.d
@@ -20,6 +20,10 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -52,6 +56,10 @@ Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Core/Src/main.o b/code/Debug/Core/Src/main.o
index ab7d6b4..7d1946f 100644
Binary files a/code/Debug/Core/Src/main.o and b/code/Debug/Core/Src/main.o differ
diff --git a/code/Debug/Core/Src/main.su b/code/Debug/Core/Src/main.su
index f6515f3..e05379c 100644
--- a/code/Debug/Core/Src/main.su
+++ b/code/Debug/Core/Src/main.su
@@ -1,59 +1,40 @@
-../Drivers/CMSIS/Include/core_cm0plus.h:987:34:__NVIC_SystemReset	8	static,ignoring_inline_asm
-../Core/Inc/pid.h:39:23:clamp_i32	24	static
-../Core/Inc/pid.h:46:20:pid_init	24	static
-../Core/Inc/pid.h:70:20:pid_reset	16	static
-../Core/Inc/pid.h:77:31:pid_update_motor	72	static
-../Core/Inc/crc.h:18:20:CRC8_107_init	16	static
-../Core/Src/main.c:291:5:main	64	static
-../Core/Src/main.c:598:6:SystemClock_Config	64	static
-../Core/Src/main.c:637:13:MX_TIM1_Init	120	static
-../Core/Src/main.c:731:13:MX_TIM3_Init	64	static
-../Core/Src/main.c:780:13:MX_TIM14_Init	8	static
-../Core/Src/main.c:811:13:MX_TIM16_Init	8	static
-../Core/Src/main.c:843:13:MX_TIM17_Init	8	static
-../Core/Src/main.c:875:13:MX_USART1_UART_Init	8	static
-../Core/Src/main.c:923:13:MX_USART2_UART_Init	8	static
-../Core/Src/main.c:969:13:MX_DMA_Init	16	static
-../Core/Src/main.c:990:13:MX_GPIO_Init	56	static
-../Core/Src/main.c:1040:6:HAL_TIM_PeriodElapsedCallback	40	static
-../Core/Src/main.c:1116:6:HAL_GPIO_EXTI_Falling_Callback	16	static
-../Core/Src/main.c:1140:6:HAL_UARTEx_RxEventCallback	16	static
-../Core/Src/main.c:1162:6:set_LED	24	static
-../Core/Src/main.c:1172:6:comp_crc_header	16	static
-../Core/Src/main.c:1180:6:handleRS485Message	144	static
-../Core/Src/main.c:1481:6:update_Feeder_Target	24	static
-../Core/Src/main.c:1510:6:set_Feeder_PWM	16	static
-../Core/Src/main.c:1526:6:peel_motor	16	static
-../Core/Src/main.c:1531:6:peel_brake	8	static
-../Core/Src/main.c:1536:6:peel_ramp_update	24	static
-../Core/Src/main.c:1580:6:drive_continuous	16	static
-../Core/Src/main.c:1594:6:halt_all	8	static
-../Core/Src/main.c:1612:6:identify_feeder	16	static
-../Core/Src/main.c:1624:6:show_version	8	static
-../Core/Src/main.c:1634:9:tenths_to_counts	32	static
-../Core/Src/main.c:1642:10:calculate_expected_feed_time	24	static
-../Core/Src/main.c:1670:6:start_feed	16	static
-../Core/Src/main.c:1714:6:feed_state_machine_update	40	static
-../Core/Src/main.c:1901:6:check_tape_loaded	24	static
-../Core/Src/main.c:1948:6:handle_vendor_options	56	static
-../Core/Src/main.c:2005:6:stall_detection_init	16	static
-../Core/Src/main.c:2017:6:stall_detection_update	24	static
-../Core/Src/main.c:2032:9:check_stall	32	static
-../Core/Src/main.c:2053:6:onewire_delay_us	24	static,ignoring_inline_asm
-../Core/Src/main.c:2060:6:onewire_set_output	32	static
-../Core/Src/main.c:2070:6:onewire_set_input	32	static
-../Core/Src/main.c:2079:6:onewire_write_low	8	static
-../Core/Src/main.c:2084:6:onewire_write_high	8	static
-../Core/Src/main.c:2089:9:onewire_read_bit	8	static
-../Core/Src/main.c:2095:9:onewire_reset	16	static
-../Core/Src/main.c:2113:6:onewire_write_bit	16	static
-../Core/Src/main.c:2135:9:onewire_read_bit_slot	24	static
-../Core/Src/main.c:2153:6:onewire_write_byte	24	static
-../Core/Src/main.c:2162:9:onewire_read_byte	16	static
-../Core/Src/main.c:2177:9:read_floor_address	24	static,ignoring_inline_asm
-../Core/Src/main.c:2207:9:write_floor_address	40	static,ignoring_inline_asm
-../Core/Src/main.c:2302:9:debug_itoa	32	static
-../Core/Src/main.c:2318:9:debug_hex8	48	static
-../Core/Src/main.c:2326:6:debug_output	16	static
-../Core/Src/main.c:2382:6:reset_position_if_needed	16	static,ignoring_inline_asm
-../Core/Src/main.c:2415:6:Error_Handler	8	static,ignoring_inline_asm
+../Core/Src/main.c:574:6:SystemClock_Config	64	static,ignoring_inline_asm
+../Core/Src/main.c:1088:6:HAL_TIM_PeriodElapsedCallback	24	static
+../Core/Src/main.c:1214:6:HAL_GPIO_EXTI_Falling_Callback	8	static
+../Core/Src/main.c:1238:6:HAL_UARTEx_RxEventCallback	16	static
+../Core/Src/main.c:1259:6:HAL_UART_ErrorCallback	8	static
+../Core/Src/main.c:1271:6:set_LED	16	static
+../Core/Src/main.c:1281:6:rs485_transmit	16	static
+../Core/Src/main.c:1293:6:comp_crc_header	16	static
+../Core/Src/main.c:1632:6:update_Feeder_Target	8	static
+../Core/Src/main.c:1659:6:set_Feeder_PWM	0	static
+../Core/Src/main.c:1674:6:peel_motor	0	static
+../Core/Src/main.c:1679:6:peel_brake	0	static
+../Core/Src/main.c:1684:6:peel_ramp_update	24	static
+../Core/Src/main.c:1728:6:drive_continuous	0	static
+../Core/Src/main.c:1737:6:halt_all	0	static
+../Core/Src/main.c:1754:6:identify_feeder	8	static
+../Core/Src/main.c:1766:6:show_version	8	static
+../Core/Src/main.c:1776:9:tenths_to_counts	8	static
+../Core/Src/main.c:1785:10:calculate_expected_feed_time	0	static
+../Core/Src/main.c:1805:6:start_feed	40	static
+../Core/Src/main.c:1843:6:feed_state_machine_update	32	static
+../Core/Src/main.c:2036:6:handle_vendor_options	16	static
+../Core/Src/main.c:2094:6:onewire_delay_us	16	static
+../Core/Src/main.c:2114:6:onewire_drive_low	0	static
+../Core/Src/main.c:2119:6:onewire_release	0	static
+../Core/Src/main.c:2124:9:onewire_read_bit	0	static
+../Core/Src/main.c:2130:9:onewire_reset	16	static
+../Core/Src/main.c:2147:6:onewire_write_bit	16	static
+../Core/Src/main.c:2167:9:onewire_read_bit_slot	16	static
+../Core/Src/main.c:2184:6:onewire_write_byte	16	static
+../Core/Src/main.c:2193:9:onewire_read_byte	16	static
+../Core/Src/main.c:2208:9:read_floor_address	8	static,ignoring_inline_asm
+../Core/Src/main.c:2238:9:write_floor_address	24	static,ignoring_inline_asm
+../Core/Src/main.c:1313:6:handleRS485Message	64	static
+../Core/Src/main.c:2333:9:debug_itoa	48	static
+../Core/Src/main.c:2349:9:debug_hex8	40	static
+../Core/Src/main.c:2357:6:debug_output	32	static
+../Core/Src/main.c:2420:6:reset_position_if_needed	16	static,ignoring_inline_asm
+../Core/Src/main.c:276:5:main	160	static,ignoring_inline_asm
+../Core/Src/main.c:2453:6:Error_Handler	0	static,ignoring_inline_asm
diff --git a/code/Debug/Core/Src/stm32c0xx_hal_msp.cyclo b/code/Debug/Core/Src/stm32c0xx_hal_msp.cyclo
index 2af659c..408fd1d 100644
--- a/code/Debug/Core/Src/stm32c0xx_hal_msp.cyclo
+++ b/code/Debug/Core/Src/stm32c0xx_hal_msp.cyclo
@@ -1,8 +1,10 @@
 ../Core/Src/stm32c0xx_hal_msp.c:68:6:HAL_MspInit	1
-../Core/Src/stm32c0xx_hal_msp.c:91:6:HAL_TIM_Base_MspInit	5
-../Core/Src/stm32c0xx_hal_msp.c:155:6:HAL_TIM_Encoder_MspInit	2
-../Core/Src/stm32c0xx_hal_msp.c:186:6:HAL_TIM_MspPostInit	2
-../Core/Src/stm32c0xx_hal_msp.c:228:6:HAL_TIM_Base_MspDeInit	5
-../Core/Src/stm32c0xx_hal_msp.c:292:6:HAL_TIM_Encoder_MspDeInit	2
-../Core/Src/stm32c0xx_hal_msp.c:321:6:HAL_UART_MspInit	6
-../Core/Src/stm32c0xx_hal_msp.c:429:6:HAL_UART_MspDeInit	3
+../Core/Src/stm32c0xx_hal_msp.c:91:6:HAL_ADC_MspInit	3
+../Core/Src/stm32c0xx_hal_msp.c:143:6:HAL_ADC_MspDeInit	2
+../Core/Src/stm32c0xx_hal_msp.c:174:6:HAL_TIM_Base_MspInit	5
+../Core/Src/stm32c0xx_hal_msp.c:238:6:HAL_TIM_Encoder_MspInit	2
+../Core/Src/stm32c0xx_hal_msp.c:269:6:HAL_TIM_MspPostInit	2
+../Core/Src/stm32c0xx_hal_msp.c:311:6:HAL_TIM_Base_MspDeInit	5
+../Core/Src/stm32c0xx_hal_msp.c:375:6:HAL_TIM_Encoder_MspDeInit	2
+../Core/Src/stm32c0xx_hal_msp.c:404:6:HAL_UART_MspInit	6
+../Core/Src/stm32c0xx_hal_msp.c:515:6:HAL_UART_MspDeInit	3
diff --git a/code/Debug/Core/Src/stm32c0xx_hal_msp.d b/code/Debug/Core/Src/stm32c0xx_hal_msp.d
index 9a2208c..40d768b 100644
--- a/code/Debug/Core/Src/stm32c0xx_hal_msp.d
+++ b/code/Debug/Core/Src/stm32c0xx_hal_msp.d
@@ -20,6 +20,10 @@ Core/Src/stm32c0xx_hal_msp.o: ../Core/Src/stm32c0xx_hal_msp.c \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Core/Src/stm32c0xx_hal_msp.o: ../Core/Src/stm32c0xx_hal_msp.c \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Core/Src/stm32c0xx_hal_msp.o b/code/Debug/Core/Src/stm32c0xx_hal_msp.o
index 98fc117..3f53e88 100644
Binary files a/code/Debug/Core/Src/stm32c0xx_hal_msp.o and b/code/Debug/Core/Src/stm32c0xx_hal_msp.o differ
diff --git a/code/Debug/Core/Src/stm32c0xx_hal_msp.su b/code/Debug/Core/Src/stm32c0xx_hal_msp.su
index 1a8c7e1..d263997 100644
--- a/code/Debug/Core/Src/stm32c0xx_hal_msp.su
+++ b/code/Debug/Core/Src/stm32c0xx_hal_msp.su
@@ -1,8 +1,10 @@
-../Core/Src/stm32c0xx_hal_msp.c:68:6:HAL_MspInit	16	static
-../Core/Src/stm32c0xx_hal_msp.c:91:6:HAL_TIM_Base_MspInit	32	static
-../Core/Src/stm32c0xx_hal_msp.c:155:6:HAL_TIM_Encoder_MspInit	56	static
-../Core/Src/stm32c0xx_hal_msp.c:186:6:HAL_TIM_MspPostInit	48	static
-../Core/Src/stm32c0xx_hal_msp.c:228:6:HAL_TIM_Base_MspDeInit	16	static
-../Core/Src/stm32c0xx_hal_msp.c:292:6:HAL_TIM_Encoder_MspDeInit	16	static
-../Core/Src/stm32c0xx_hal_msp.c:321:6:HAL_UART_MspInit	88	static
-../Core/Src/stm32c0xx_hal_msp.c:429:6:HAL_UART_MspDeInit	16	static
+../Core/Src/stm32c0xx_hal_msp.c:68:6:HAL_MspInit	8	static
+../Core/Src/stm32c0xx_hal_msp.c:91:6:HAL_ADC_MspInit	80	static
+../Core/Src/stm32c0xx_hal_msp.c:143:6:HAL_ADC_MspDeInit	8	static
+../Core/Src/stm32c0xx_hal_msp.c:174:6:HAL_TIM_Base_MspInit	24	static
+../Core/Src/stm32c0xx_hal_msp.c:238:6:HAL_TIM_Encoder_MspInit	40	static
+../Core/Src/stm32c0xx_hal_msp.c:269:6:HAL_TIM_MspPostInit	32	static
+../Core/Src/stm32c0xx_hal_msp.c:311:6:HAL_TIM_Base_MspDeInit	8	static
+../Core/Src/stm32c0xx_hal_msp.c:375:6:HAL_TIM_Encoder_MspDeInit	8	static
+../Core/Src/stm32c0xx_hal_msp.c:404:6:HAL_UART_MspInit	80	static
+../Core/Src/stm32c0xx_hal_msp.c:515:6:HAL_UART_MspDeInit	8	static
diff --git a/code/Debug/Core/Src/stm32c0xx_it.cyclo b/code/Debug/Core/Src/stm32c0xx_it.cyclo
index c6d4709..689cf62 100644
--- a/code/Debug/Core/Src/stm32c0xx_it.cyclo
+++ b/code/Debug/Core/Src/stm32c0xx_it.cyclo
@@ -1,11 +1,12 @@
-../Core/Src/stm32c0xx_it.c:73:6:NMI_Handler	1
-../Core/Src/stm32c0xx_it.c:88:6:HardFault_Handler	1
-../Core/Src/stm32c0xx_it.c:103:6:SVC_Handler	1
-../Core/Src/stm32c0xx_it.c:116:6:PendSV_Handler	1
-../Core/Src/stm32c0xx_it.c:129:6:SysTick_Handler	1
-../Core/Src/stm32c0xx_it.c:150:6:EXTI4_15_IRQHandler	1
-../Core/Src/stm32c0xx_it.c:165:6:DMA1_Channel1_IRQHandler	1
-../Core/Src/stm32c0xx_it.c:179:6:DMA1_Channel2_3_IRQHandler	1
-../Core/Src/stm32c0xx_it.c:193:6:TIM14_IRQHandler	1
-../Core/Src/stm32c0xx_it.c:207:6:TIM16_IRQHandler	1
-../Core/Src/stm32c0xx_it.c:221:6:TIM17_IRQHandler	1
+../Core/Src/stm32c0xx_it.c:74:6:NMI_Handler	1
+../Core/Src/stm32c0xx_it.c:89:6:HardFault_Handler	1
+../Core/Src/stm32c0xx_it.c:104:6:SVC_Handler	1
+../Core/Src/stm32c0xx_it.c:117:6:PendSV_Handler	1
+../Core/Src/stm32c0xx_it.c:130:6:SysTick_Handler	1
+../Core/Src/stm32c0xx_it.c:151:6:EXTI4_15_IRQHandler	1
+../Core/Src/stm32c0xx_it.c:166:6:DMA1_Channel1_IRQHandler	1
+../Core/Src/stm32c0xx_it.c:180:6:DMA1_Channel2_3_IRQHandler	1
+../Core/Src/stm32c0xx_it.c:194:6:TIM14_IRQHandler	1
+../Core/Src/stm32c0xx_it.c:208:6:TIM16_IRQHandler	1
+../Core/Src/stm32c0xx_it.c:222:6:TIM17_IRQHandler	1
+../Core/Src/stm32c0xx_it.c:236:6:USART2_IRQHandler	1
diff --git a/code/Debug/Core/Src/stm32c0xx_it.d b/code/Debug/Core/Src/stm32c0xx_it.d
index 0ce4e49..be73c7d 100644
--- a/code/Debug/Core/Src/stm32c0xx_it.d
+++ b/code/Debug/Core/Src/stm32c0xx_it.d
@@ -20,6 +20,10 @@ Core/Src/stm32c0xx_it.o: ../Core/Src/stm32c0xx_it.c ../Core/Inc/main.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -52,6 +56,10 @@ Core/Src/stm32c0xx_it.o: ../Core/Src/stm32c0xx_it.c ../Core/Inc/main.h \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Core/Src/stm32c0xx_it.o b/code/Debug/Core/Src/stm32c0xx_it.o
index 7eb2f0f..d14e157 100644
Binary files a/code/Debug/Core/Src/stm32c0xx_it.o and b/code/Debug/Core/Src/stm32c0xx_it.o differ
diff --git a/code/Debug/Core/Src/stm32c0xx_it.su b/code/Debug/Core/Src/stm32c0xx_it.su
index 4994dfb..ac9f611 100644
--- a/code/Debug/Core/Src/stm32c0xx_it.su
+++ b/code/Debug/Core/Src/stm32c0xx_it.su
@@ -1,11 +1,12 @@
-../Core/Src/stm32c0xx_it.c:73:6:NMI_Handler	8	static
-../Core/Src/stm32c0xx_it.c:88:6:HardFault_Handler	8	static
-../Core/Src/stm32c0xx_it.c:103:6:SVC_Handler	8	static
-../Core/Src/stm32c0xx_it.c:116:6:PendSV_Handler	8	static
-../Core/Src/stm32c0xx_it.c:129:6:SysTick_Handler	8	static
-../Core/Src/stm32c0xx_it.c:150:6:EXTI4_15_IRQHandler	8	static
-../Core/Src/stm32c0xx_it.c:165:6:DMA1_Channel1_IRQHandler	8	static
-../Core/Src/stm32c0xx_it.c:179:6:DMA1_Channel2_3_IRQHandler	8	static
-../Core/Src/stm32c0xx_it.c:193:6:TIM14_IRQHandler	8	static
-../Core/Src/stm32c0xx_it.c:207:6:TIM16_IRQHandler	8	static
-../Core/Src/stm32c0xx_it.c:221:6:TIM17_IRQHandler	8	static
+../Core/Src/stm32c0xx_it.c:74:6:NMI_Handler	0	static
+../Core/Src/stm32c0xx_it.c:89:6:HardFault_Handler	0	static
+../Core/Src/stm32c0xx_it.c:104:6:SVC_Handler	0	static
+../Core/Src/stm32c0xx_it.c:117:6:PendSV_Handler	0	static
+../Core/Src/stm32c0xx_it.c:130:6:SysTick_Handler	8	static
+../Core/Src/stm32c0xx_it.c:151:6:EXTI4_15_IRQHandler	8	static
+../Core/Src/stm32c0xx_it.c:166:6:DMA1_Channel1_IRQHandler	8	static
+../Core/Src/stm32c0xx_it.c:180:6:DMA1_Channel2_3_IRQHandler	8	static
+../Core/Src/stm32c0xx_it.c:194:6:TIM14_IRQHandler	8	static
+../Core/Src/stm32c0xx_it.c:208:6:TIM16_IRQHandler	8	static
+../Core/Src/stm32c0xx_it.c:222:6:TIM17_IRQHandler	8	static
+../Core/Src/stm32c0xx_it.c:236:6:USART2_IRQHandler	8	static
diff --git a/code/Debug/Core/Src/subdir.mk b/code/Debug/Core/Src/subdir.mk
index 1be359e..d4dc2f9 100644
--- a/code/Debug/Core/Src/subdir.mk
+++ b/code/Debug/Core/Src/subdir.mk
@@ -1,6 +1,6 @@
 ################################################################################
 # Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (13.3.rel1)
+# Toolchain: GNU Tools for STM32 (14.3.rel1)
 ################################################################################
 
 # Add inputs and outputs from these tool invocations to the build variables 
@@ -34,7 +34,7 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C051xx -c -I../Core/Inc -I../Drivers/STM32C0xx_HAL_Driver/Inc -I../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C051xx -c -I../Core/Inc -I../Drivers/STM32C0xx_HAL_Driver/Inc -I../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../Drivers/CMSIS/Include -Oz -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
 
 clean: clean-Core-2f-Src
 
diff --git a/code/Debug/Core/Src/syscalls.o b/code/Debug/Core/Src/syscalls.o
index 5bf0dfa..5a30e4f 100644
Binary files a/code/Debug/Core/Src/syscalls.o and b/code/Debug/Core/Src/syscalls.o differ
diff --git a/code/Debug/Core/Src/syscalls.su b/code/Debug/Core/Src/syscalls.su
index 1b5bca2..268646b 100644
--- a/code/Debug/Core/Src/syscalls.su
+++ b/code/Debug/Core/Src/syscalls.su
@@ -1,18 +1,18 @@
-../Core/Src/syscalls.c:44:6:initialise_monitor_handles	8	static
-../Core/Src/syscalls.c:48:5:_getpid	8	static
-../Core/Src/syscalls.c:53:5:_kill	16	static
-../Core/Src/syscalls.c:61:6:_exit	16	static
-../Core/Src/syscalls.c:67:27:_read	32	static
-../Core/Src/syscalls.c:80:27:_write	32	static
-../Core/Src/syscalls.c:92:5:_close	16	static
-../Core/Src/syscalls.c:99:5:_fstat	16	static
-../Core/Src/syscalls.c:106:5:_isatty	16	static
-../Core/Src/syscalls.c:112:5:_lseek	24	static
-../Core/Src/syscalls.c:120:5:_open	20	static
-../Core/Src/syscalls.c:128:5:_wait	16	static
-../Core/Src/syscalls.c:135:5:_unlink	16	static
-../Core/Src/syscalls.c:142:5:_times	16	static
-../Core/Src/syscalls.c:148:5:_stat	16	static
-../Core/Src/syscalls.c:155:5:_link	16	static
+../Core/Src/syscalls.c:44:6:initialise_monitor_handles	0	static
+../Core/Src/syscalls.c:48:5:_getpid	0	static
+../Core/Src/syscalls.c:53:5:_kill	8	static
+../Core/Src/syscalls.c:61:6:_exit	8	static
+../Core/Src/syscalls.c:67:27:_read	16	static
+../Core/Src/syscalls.c:80:27:_write	16	static
+../Core/Src/syscalls.c:92:5:_close	0	static
+../Core/Src/syscalls.c:99:5:_fstat	0	static
+../Core/Src/syscalls.c:106:5:_isatty	0	static
+../Core/Src/syscalls.c:112:5:_lseek	0	static
+../Core/Src/syscalls.c:120:5:_open	0	static
+../Core/Src/syscalls.c:128:5:_wait	8	static
+../Core/Src/syscalls.c:135:5:_unlink	8	static
+../Core/Src/syscalls.c:142:5:_times	0	static
+../Core/Src/syscalls.c:148:5:_stat	0	static
+../Core/Src/syscalls.c:155:5:_link	8	static
 ../Core/Src/syscalls.c:163:5:_fork	8	static
-../Core/Src/syscalls.c:169:5:_execve	24	static
+../Core/Src/syscalls.c:169:5:_execve	8	static
diff --git a/code/Debug/Core/Src/sysmem.o b/code/Debug/Core/Src/sysmem.o
index c8d7546..4a11207 100644
Binary files a/code/Debug/Core/Src/sysmem.o and b/code/Debug/Core/Src/sysmem.o differ
diff --git a/code/Debug/Core/Src/sysmem.su b/code/Debug/Core/Src/sysmem.su
index 12d5f17..43d062a 100644
--- a/code/Debug/Core/Src/sysmem.su
+++ b/code/Debug/Core/Src/sysmem.su
@@ -1 +1 @@
-../Core/Src/sysmem.c:53:7:_sbrk	32	static
+../Core/Src/sysmem.c:53:7:_sbrk	8	static
diff --git a/code/Debug/Core/Src/system_stm32c0xx.cyclo b/code/Debug/Core/Src/system_stm32c0xx.cyclo
index a733bba..f993d47 100644
--- a/code/Debug/Core/Src/system_stm32c0xx.cyclo
+++ b/code/Debug/Core/Src/system_stm32c0xx.cyclo
@@ -1,2 +1,2 @@
 ../Core/Src/system_stm32c0xx.c:142:6:SystemInit	1
-../Core/Src/system_stm32c0xx.c:190:6:SystemCoreClockUpdate	5
+../Core/Src/system_stm32c0xx.c:190:6:SystemCoreClockUpdate	4
diff --git a/code/Debug/Core/Src/system_stm32c0xx.d b/code/Debug/Core/Src/system_stm32c0xx.d
index 8ab5dd5..0b523c6 100644
--- a/code/Debug/Core/Src/system_stm32c0xx.d
+++ b/code/Debug/Core/Src/system_stm32c0xx.d
@@ -20,6 +20,10 @@ Core/Src/system_stm32c0xx.o: ../Core/Src/system_stm32c0xx.c \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -50,6 +54,10 @@ Core/Src/system_stm32c0xx.o: ../Core/Src/system_stm32c0xx.c \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Core/Src/system_stm32c0xx.o b/code/Debug/Core/Src/system_stm32c0xx.o
index 329d430..6b27fc8 100644
Binary files a/code/Debug/Core/Src/system_stm32c0xx.o and b/code/Debug/Core/Src/system_stm32c0xx.o differ
diff --git a/code/Debug/Core/Src/system_stm32c0xx.su b/code/Debug/Core/Src/system_stm32c0xx.su
index 2ac48ad..7f0bc71 100644
--- a/code/Debug/Core/Src/system_stm32c0xx.su
+++ b/code/Debug/Core/Src/system_stm32c0xx.su
@@ -1,2 +1,2 @@
-../Core/Src/system_stm32c0xx.c:142:6:SystemInit	8	static
-../Core/Src/system_stm32c0xx.c:190:6:SystemCoreClockUpdate	24	static
+../Core/Src/system_stm32c0xx.c:142:6:SystemInit	0	static
+../Core/Src/system_stm32c0xx.c:190:6:SystemCoreClockUpdate	16	static
diff --git a/code/Debug/Core/Startup/startup_stm32c051c6tx.o b/code/Debug/Core/Startup/startup_stm32c051c6tx.o
index c20bd5a..a3d1e22 100644
Binary files a/code/Debug/Core/Startup/startup_stm32c051c6tx.o and b/code/Debug/Core/Startup/startup_stm32c051c6tx.o differ
diff --git a/code/Debug/Core/Startup/subdir.mk b/code/Debug/Core/Startup/subdir.mk
index c0e792a..ca36f51 100644
--- a/code/Debug/Core/Startup/subdir.mk
+++ b/code/Debug/Core/Startup/subdir.mk
@@ -1,6 +1,6 @@
 ################################################################################
 # Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (13.3.rel1)
+# Toolchain: GNU Tools for STM32 (14.3.rel1)
 ################################################################################
 
 # Add inputs and outputs from these tool invocations to the build variables 
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.cyclo
index ad4e77b..539e992 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.cyclo
@@ -1,10 +1,8 @@
-../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h:595:22:LL_SYSCFG_ConfigPinMux	1
-../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h:606:26:LL_SYSCFG_GetConfigPinMux	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:139:19:HAL_Init	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:176:19:HAL_DeInit	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:202:13:HAL_MspInit	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:213:13:HAL_MspDeInit	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:176:19:HAL_DeInit	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:236:26:HAL_InitTick	4
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:139:19:HAL_Init	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:303:13:HAL_IncTick	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:314:17:HAL_GetTick	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:323:10:HAL_GetTickPrio	1
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.d
index ddac790..67d7736 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
index 823d98d..7d6cda1 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.su
index c62b57e..4c20e24 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.su
@@ -1,29 +1,27 @@
-../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h:595:22:LL_SYSCFG_ConfigPinMux	16	static
-../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_system.h:606:26:LL_SYSCFG_GetConfigPinMux	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:139:19:HAL_Init	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:202:13:HAL_MspInit	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:213:13:HAL_MspDeInit	0	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:176:19:HAL_DeInit	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:202:13:HAL_MspInit	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:213:13:HAL_MspDeInit	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:236:26:HAL_InitTick	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:303:13:HAL_IncTick	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:314:17:HAL_GetTick	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:323:10:HAL_GetTickPrio	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:332:19:HAL_SetTickFreq	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:357:21:HAL_GetTickFreq	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:373:13:HAL_Delay	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:399:13:HAL_SuspendTick	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:415:13:HAL_ResumeTick	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:425:10:HAL_GetHalVersion	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:434:10:HAL_GetREVID	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:443:10:HAL_GetDEVID	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:452:10:HAL_GetUIDw0	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:461:10:HAL_GetUIDw1	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:470:10:HAL_GetUIDw2	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:498:6:HAL_DBGMCU_EnableDBGStopMode	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:507:6:HAL_DBGMCU_DisableDBGStopMode	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:516:6:HAL_DBGMCU_EnableDBGStandbyMode	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:525:6:HAL_DBGMCU_DisableDBGStandbyMode	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:554:6:HAL_SYSCFG_EnableRemap	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:569:6:HAL_SYSCFG_DisableRemap	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:582:6:HAL_SYSCFG_SetPinBinding	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:595:10:HAL_SYSCFG_GetPinBinding	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:236:26:HAL_InitTick	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:139:19:HAL_Init	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:303:13:HAL_IncTick	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:314:17:HAL_GetTick	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:323:10:HAL_GetTickPrio	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:332:19:HAL_SetTickFreq	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:357:21:HAL_GetTickFreq	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:373:13:HAL_Delay	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:399:13:HAL_SuspendTick	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:415:13:HAL_ResumeTick	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:425:10:HAL_GetHalVersion	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:434:10:HAL_GetREVID	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:443:10:HAL_GetDEVID	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:452:10:HAL_GetUIDw0	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:461:10:HAL_GetUIDw1	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:470:10:HAL_GetUIDw2	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:498:6:HAL_DBGMCU_EnableDBGStopMode	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:507:6:HAL_DBGMCU_DisableDBGStopMode	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:516:6:HAL_DBGMCU_EnableDBGStandbyMode	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:525:6:HAL_DBGMCU_DisableDBGStandbyMode	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:554:6:HAL_SYSCFG_EnableRemap	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:569:6:HAL_SYSCFG_DisableRemap	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:582:6:HAL_SYSCFG_SetPinBinding	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c:595:10:HAL_SYSCFG_GetPinBinding	0	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.cyclo
index 876a40c..9a0da4e 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.cyclo
@@ -1,24 +1,15 @@
-../Drivers/CMSIS/Include/core_cm0plus.h:741:22:__NVIC_EnableIRQ	2
-../Drivers/CMSIS/Include/core_cm0plus.h:779:22:__NVIC_DisableIRQ	2
-../Drivers/CMSIS/Include/core_cm0plus.h:798:26:__NVIC_GetPendingIRQ	2
-../Drivers/CMSIS/Include/core_cm0plus.h:817:22:__NVIC_SetPendingIRQ	2
-../Drivers/CMSIS/Include/core_cm0plus.h:832:22:__NVIC_ClearPendingIRQ	2
-../Drivers/CMSIS/Include/core_cm0plus.h:850:22:__NVIC_SetPriority	2
-../Drivers/CMSIS/Include/core_cm0plus.h:874:26:__NVIC_GetPriority	2
-../Drivers/CMSIS/Include/core_cm0plus.h:987:34:__NVIC_SystemReset	1
-../Drivers/CMSIS/Include/core_cm0plus.h:1058:26:SysTick_Config	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:132:6:HAL_NVIC_SetPriority	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:149:6:HAL_NVIC_EnableIRQ	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:166:6:HAL_NVIC_DisableIRQ	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:179:6:HAL_NVIC_SystemReset	0
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:192:10:HAL_SYSTICK_Config	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:224:10:HAL_NVIC_GetPriority	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:238:6:HAL_NVIC_SetPendingIRQ	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:257:10:HAL_NVIC_GetPendingIRQ	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:274:6:HAL_NVIC_ClearPendingIRQ	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:132:6:HAL_NVIC_SetPriority	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:149:6:HAL_NVIC_EnableIRQ	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:166:6:HAL_NVIC_DisableIRQ	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:179:6:HAL_NVIC_SystemReset	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:192:10:HAL_SYSTICK_Config	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:224:10:HAL_NVIC_GetPriority	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:238:6:HAL_NVIC_SetPendingIRQ	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:257:10:HAL_NVIC_GetPendingIRQ	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:274:6:HAL_NVIC_ClearPendingIRQ	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:291:6:HAL_SYSTICK_CLKSourceConfig	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:309:6:HAL_SYSTICK_IRQHandler	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:318:13:HAL_SYSTICK_Callback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:309:6:HAL_SYSTICK_IRQHandler	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:337:6:HAL_MPU_Enable	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:351:6:HAL_MPU_Disable	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:364:6:HAL_MPU_EnableRegion	1
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.d
index 72167e4..355da17 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
index fd74729..9fc30f3 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.su
index 50a6b00..8561063 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.su
@@ -1,26 +1,17 @@
-../Drivers/CMSIS/Include/core_cm0plus.h:741:22:__NVIC_EnableIRQ	16	static,ignoring_inline_asm
-../Drivers/CMSIS/Include/core_cm0plus.h:779:22:__NVIC_DisableIRQ	16	static,ignoring_inline_asm
-../Drivers/CMSIS/Include/core_cm0plus.h:798:26:__NVIC_GetPendingIRQ	16	static
-../Drivers/CMSIS/Include/core_cm0plus.h:817:22:__NVIC_SetPendingIRQ	16	static
-../Drivers/CMSIS/Include/core_cm0plus.h:832:22:__NVIC_ClearPendingIRQ	16	static
-../Drivers/CMSIS/Include/core_cm0plus.h:850:22:__NVIC_SetPriority	24	static
-../Drivers/CMSIS/Include/core_cm0plus.h:874:26:__NVIC_GetPriority	16	static
-../Drivers/CMSIS/Include/core_cm0plus.h:987:34:__NVIC_SystemReset	8	static,ignoring_inline_asm
-../Drivers/CMSIS/Include/core_cm0plus.h:1058:26:SysTick_Config	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:132:6:HAL_NVIC_SetPriority	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:149:6:HAL_NVIC_EnableIRQ	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:166:6:HAL_NVIC_DisableIRQ	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:179:6:HAL_NVIC_SystemReset	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:192:10:HAL_SYSTICK_Config	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:224:10:HAL_NVIC_GetPriority	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:238:6:HAL_NVIC_SetPendingIRQ	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:257:10:HAL_NVIC_GetPendingIRQ	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:274:6:HAL_NVIC_ClearPendingIRQ	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:291:6:HAL_SYSTICK_CLKSourceConfig	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:132:6:HAL_NVIC_SetPriority	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:149:6:HAL_NVIC_EnableIRQ	0	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:166:6:HAL_NVIC_DisableIRQ	0	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:179:6:HAL_NVIC_SystemReset	0	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:192:10:HAL_SYSTICK_Config	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:224:10:HAL_NVIC_GetPriority	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:238:6:HAL_NVIC_SetPendingIRQ	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:257:10:HAL_NVIC_GetPendingIRQ	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:274:6:HAL_NVIC_ClearPendingIRQ	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:291:6:HAL_SYSTICK_CLKSourceConfig	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:318:13:HAL_SYSTICK_Callback	0	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:309:6:HAL_SYSTICK_IRQHandler	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:318:13:HAL_SYSTICK_Callback	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:337:6:HAL_MPU_Enable	16	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:351:6:HAL_MPU_Disable	8	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:364:6:HAL_MPU_EnableRegion	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:380:6:HAL_MPU_DisableRegion	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:398:6:HAL_MPU_ConfigRegion	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:337:6:HAL_MPU_Enable	0	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:351:6:HAL_MPU_Disable	0	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:364:6:HAL_MPU_EnableRegion	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:380:6:HAL_MPU_DisableRegion	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c:398:6:HAL_MPU_ConfigRegion	0	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.cyclo
index 00eb246..2b38ce3 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.cyclo
@@ -1,15 +1,14 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:151:19:HAL_DMA_Init	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:241:19:HAL_DMA_DeInit	4
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:984:13:DMA_SetConfig	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:1027:13:DMA_CalcDMAMUXChannelBaseAndMask	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:151:19:HAL_DMA_Init	4
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:241:19:HAL_DMA_DeInit	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:345:19:HAL_DMA_Start	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:392:19:HAL_DMA_Start_IT	6
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:466:19:HAL_DMA_Abort	4
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:527:19:HAL_DMA_Abort_IT	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:527:19:HAL_DMA_Abort_IT	4
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:592:19:HAL_DMA_PollForTransfer	13
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:724:6:HAL_DMA_IRQHandler	12
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:818:19:HAL_DMA_RegisterCallback	9
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:818:19:HAL_DMA_RegisterCallback	7
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:870:19:HAL_DMA_UnRegisterCallback	8
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:946:22:HAL_DMA_GetState	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:958:10:HAL_DMA_GetError	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:984:13:DMA_SetConfig	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:1027:13:DMA_CalcDMAMUXChannelBaseAndMask	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:1047:13:DMA_CalcDMAMUXRequestGenBaseAndMask	1
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.d
index 1906e01..ee1dbee 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
index ec21218..f8b036d 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.su
index 85b3949..1aeaaeb 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.su
@@ -1,15 +1,14 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:151:19:HAL_DMA_Init	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:241:19:HAL_DMA_DeInit	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:984:13:DMA_SetConfig	20	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:1027:13:DMA_CalcDMAMUXChannelBaseAndMask	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:151:19:HAL_DMA_Init	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:241:19:HAL_DMA_DeInit	24	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:345:19:HAL_DMA_Start	32	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:392:19:HAL_DMA_Start_IT	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:466:19:HAL_DMA_Abort	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:466:19:HAL_DMA_Abort	20	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:527:19:HAL_DMA_Abort_IT	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:592:19:HAL_DMA_PollForTransfer	32	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:592:19:HAL_DMA_PollForTransfer	40	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:724:6:HAL_DMA_IRQHandler	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:818:19:HAL_DMA_RegisterCallback	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:870:19:HAL_DMA_UnRegisterCallback	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:946:22:HAL_DMA_GetState	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:958:10:HAL_DMA_GetError	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:984:13:DMA_SetConfig	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:1027:13:DMA_CalcDMAMUXChannelBaseAndMask	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:1047:13:DMA_CalcDMAMUXRequestGenBaseAndMask	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:818:19:HAL_DMA_RegisterCallback	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:870:19:HAL_DMA_UnRegisterCallback	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:946:22:HAL_DMA_GetState	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c:958:10:HAL_DMA_GetError	0	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.d
index 0842fa1..a3c86ed 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
index a22905a..ac76769 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.su
index c1e487b..4de793a 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.su
@@ -1,5 +1,5 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:94:19:HAL_DMAEx_ConfigMuxSync	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:142:19:HAL_DMAEx_ConfigMuxRequestGenerator	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:181:19:HAL_DMAEx_EnableMuxRequestGenerator	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:208:19:HAL_DMAEx_DisableMuxRequestGenerator	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:94:19:HAL_DMAEx_ConfigMuxSync	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:142:19:HAL_DMAEx_ConfigMuxRequestGenerator	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:181:19:HAL_DMAEx_EnableMuxRequestGenerator	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:208:19:HAL_DMAEx_DisableMuxRequestGenerator	0	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c:236:6:HAL_DMAEx_MUX_IRQHandler	16	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.cyclo
index 2f43e3b..ef52a50 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.cyclo
@@ -1,7 +1,7 @@
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:136:19:HAL_EXTI_SetConfigLine	9
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:257:19:HAL_EXTI_GetConfigLine	9
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:257:19:HAL_EXTI_GetConfigLine	7
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:350:19:HAL_EXTI_ClearConfigLine	4
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:415:19:HAL_EXTI_RegisterCallback	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:415:19:HAL_EXTI_RegisterCallback	4
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:450:19:HAL_EXTI_GetHandle	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:490:6:HAL_EXTI_IRQHandler	5
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:544:10:HAL_EXTI_GetPending	2
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.d
index 5578a3b..b4a47a5 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
index 56d2c1f..b830d48 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.su
index 4c3145c..ba90c60 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.su
@@ -1,9 +1,9 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:136:19:HAL_EXTI_SetConfigLine	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:257:19:HAL_EXTI_GetConfigLine	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:350:19:HAL_EXTI_ClearConfigLine	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:415:19:HAL_EXTI_RegisterCallback	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:450:19:HAL_EXTI_GetHandle	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:490:6:HAL_EXTI_IRQHandler	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:544:10:HAL_EXTI_GetPending	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:588:6:HAL_EXTI_ClearPending	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:624:6:HAL_EXTI_GenerateSWI	32	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:136:19:HAL_EXTI_SetConfigLine	32	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:257:19:HAL_EXTI_GetConfigLine	20	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:350:19:HAL_EXTI_ClearConfigLine	32	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:415:19:HAL_EXTI_RegisterCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:450:19:HAL_EXTI_GetHandle	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:490:6:HAL_EXTI_IRQHandler	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:544:10:HAL_EXTI_GetPending	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:588:6:HAL_EXTI_ClearPending	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.c:624:6:HAL_EXTI_GenerateSWI	0	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.cyclo
index 4bcdfed..edc394c 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.cyclo
@@ -1,14 +1,13 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:161:19:HAL_FLASH_Program	4
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:222:19:HAL_FLASH_Program_IT	4
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:279:6:HAL_FLASH_IRQHandler	9
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:653:24:FLASH_Program_Fast	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:374:13:HAL_FLASH_EndOfOperationCallback	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:392:13:HAL_FLASH_OperationErrorCallback	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:425:19:HAL_FLASH_Unlock	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:449:19:HAL_FLASH_Lock	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:469:19:HAL_FLASH_OB_Unlock	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:493:19:HAL_FLASH_OB_Lock	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:279:6:HAL_FLASH_IRQHandler	8
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:425:19:HAL_FLASH_Unlock	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:449:19:HAL_FLASH_Lock	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:469:19:HAL_FLASH_OB_Unlock	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:493:19:HAL_FLASH_OB_Lock	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:513:19:HAL_FLASH_OB_Launch	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:556:10:HAL_FLASH_GetError	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:580:19:FLASH_WaitForLastOperation	8
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:631:13:FLASH_Program_DoubleWord	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:653:24:FLASH_Program_Fast	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:580:19:FLASH_WaitForLastOperation	6
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:161:19:HAL_FLASH_Program	4
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:222:19:HAL_FLASH_Program_IT	4
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.d
index 82ee61b..1055b83 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
index 7849a05..3c5f0a4 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.su
index 818371a..5c73211 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.su
@@ -1,14 +1,13 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:161:19:HAL_FLASH_Program	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:222:19:HAL_FLASH_Program_IT	40	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:653:24:FLASH_Program_Fast	12	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:374:13:HAL_FLASH_EndOfOperationCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:392:13:HAL_FLASH_OperationErrorCallback	0	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:279:6:HAL_FLASH_IRQHandler	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:374:13:HAL_FLASH_EndOfOperationCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:392:13:HAL_FLASH_OperationErrorCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:425:19:HAL_FLASH_Unlock	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:449:19:HAL_FLASH_Lock	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:469:19:HAL_FLASH_OB_Unlock	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:493:19:HAL_FLASH_OB_Lock	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:513:19:HAL_FLASH_OB_Launch	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:556:10:HAL_FLASH_GetError	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:425:19:HAL_FLASH_Unlock	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:449:19:HAL_FLASH_Lock	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:469:19:HAL_FLASH_OB_Unlock	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:493:19:HAL_FLASH_OB_Lock	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:513:19:HAL_FLASH_OB_Launch	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:556:10:HAL_FLASH_GetError	0	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:580:19:FLASH_WaitForLastOperation	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:631:13:FLASH_Program_DoubleWord	32	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:653:24:FLASH_Program_Fast	40	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:161:19:HAL_FLASH_Program	32	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.c:222:19:HAL_FLASH_Program_IT	32	static,ignoring_inline_asm
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.cyclo
index 949bf34..6b6ec02 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.cyclo
@@ -1,23 +1,11 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:139:19:HAL_FLASHEx_Erase	6
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:206:19:HAL_FLASHEx_Erase_IT	4
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:270:19:HAL_FLASHEx_OBProgram	11
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:373:6:HAL_FLASHEx_OBGetConfig	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:270:19:HAL_FLASHEx_OBProgram	16
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:373:6:HAL_FLASHEx_OBGetConfig	4
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:401:6:HAL_FLASHEx_EnableDebugger	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:412:6:HAL_FLASHEx_DisableDebugger	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:423:10:HAL_FLASHEx_FlashEmptyCheck	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:437:6:HAL_FLASHEx_ForceFlashEmpty	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:456:6:HAL_FLASHEx_EnableSecMemProtection	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:479:13:FLASH_MassErase	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:491:6:FLASH_PageErase	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:139:19:HAL_FLASHEx_Erase	6
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:206:19:HAL_FLASHEx_Erase_IT	4
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:509:6:FLASH_FlushCaches	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:543:13:FLASH_OB_WRPConfig	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:594:13:FLASH_OB_OptrConfig	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:624:13:FLASH_OB_PCROP1AConfig	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:676:13:FLASH_OB_PCROP1BConfig	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:705:13:FLASH_OB_SecMemConfig	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:730:13:FLASH_OB_GetWRP	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:756:17:FLASH_OB_GetRDP	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:792:17:FLASH_OB_GetUser	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:807:13:FLASH_OB_GetPCROP1A	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:832:13:FLASH_OB_GetPCROP1B	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:852:13:FLASH_OB_GetSecMem	1
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.d
index 9b2e208..a94b8ed 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
index 87de05b..f042a99 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.su
index 42ced77..65bae25 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.su
@@ -1,23 +1,11 @@
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:270:19:HAL_FLASHEx_OBProgram	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:373:6:HAL_FLASHEx_OBGetConfig	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:401:6:HAL_FLASHEx_EnableDebugger	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:412:6:HAL_FLASHEx_DisableDebugger	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:423:10:HAL_FLASHEx_FlashEmptyCheck	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:437:6:HAL_FLASHEx_ForceFlashEmpty	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:456:6:HAL_FLASHEx_EnableSecMemProtection	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:491:6:FLASH_PageErase	0	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:139:19:HAL_FLASHEx_Erase	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:206:19:HAL_FLASHEx_Erase_IT	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:270:19:HAL_FLASHEx_OBProgram	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:373:6:HAL_FLASHEx_OBGetConfig	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:401:6:HAL_FLASHEx_EnableDebugger	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:412:6:HAL_FLASHEx_DisableDebugger	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:423:10:HAL_FLASHEx_FlashEmptyCheck	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:437:6:HAL_FLASHEx_ForceFlashEmpty	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:456:6:HAL_FLASHEx_EnableSecMemProtection	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:479:13:FLASH_MassErase	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:491:6:FLASH_PageErase	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:509:6:FLASH_FlushCaches	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:543:13:FLASH_OB_WRPConfig	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:594:13:FLASH_OB_OptrConfig	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:624:13:FLASH_OB_PCROP1AConfig	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:676:13:FLASH_OB_PCROP1BConfig	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:705:13:FLASH_OB_SecMemConfig	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:730:13:FLASH_OB_GetWRP	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:756:17:FLASH_OB_GetRDP	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:792:17:FLASH_OB_GetUser	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:807:13:FLASH_OB_GetPCROP1A	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:832:13:FLASH_OB_GetPCROP1B	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:852:13:FLASH_OB_GetSecMem	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:206:19:HAL_FLASHEx_Erase_IT	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.c:509:6:FLASH_FlushCaches	0	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.cyclo
index 830c005..ac9955c 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.cyclo
@@ -1,10 +1,10 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:173:6:HAL_GPIO_Init	20
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:301:6:HAL_GPIO_DeInit	9
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:381:15:HAL_GPIO_ReadPin	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:173:6:HAL_GPIO_Init	15
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:301:6:HAL_GPIO_DeInit	8
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:381:15:HAL_GPIO_ReadPin	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:413:6:HAL_GPIO_WritePin	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:443:6:HAL_GPIO_WriteMultipleStatePin	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:462:6:HAL_GPIO_TogglePin	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:487:19:HAL_GPIO_LockPin	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:519:6:HAL_GPIO_EXTI_IRQHandler	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:487:19:HAL_GPIO_LockPin	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:540:13:HAL_GPIO_EXTI_Rising_Callback	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:555:13:HAL_GPIO_EXTI_Falling_Callback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:519:6:HAL_GPIO_EXTI_IRQHandler	3
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.d
index 8b3f54b..8e9032d 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
index d03b9c1..b10a282 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.su
index 515cbf3..d79c3b5 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.su
@@ -1,10 +1,10 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:173:6:HAL_GPIO_Init	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:301:6:HAL_GPIO_DeInit	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:381:15:HAL_GPIO_ReadPin	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:413:6:HAL_GPIO_WritePin	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:443:6:HAL_GPIO_WriteMultipleStatePin	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:462:6:HAL_GPIO_TogglePin	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:487:19:HAL_GPIO_LockPin	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:173:6:HAL_GPIO_Init	40	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:301:6:HAL_GPIO_DeInit	40	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:381:15:HAL_GPIO_ReadPin	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:413:6:HAL_GPIO_WritePin	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:443:6:HAL_GPIO_WriteMultipleStatePin	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:462:6:HAL_GPIO_TogglePin	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:487:19:HAL_GPIO_LockPin	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:540:13:HAL_GPIO_EXTI_Rising_Callback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:555:13:HAL_GPIO_EXTI_Falling_Callback	0	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:519:6:HAL_GPIO_EXTI_IRQHandler	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:540:13:HAL_GPIO_EXTI_Rising_Callback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.c:555:13:HAL_GPIO_EXTI_Falling_Callback	16	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.d
index 359fcb3..4da3df4 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
index c7fc96c..89a7d63 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.su
index 2e55c09..9df4c10 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.su
@@ -1,10 +1,10 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:73:6:HAL_PWR_DeInit	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:207:6:HAL_PWR_EnableWakeUpPin	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:228:6:HAL_PWR_DisableWakeUpPin	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:252:6:HAL_PWR_EnterSLEEPMode	16	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:300:6:HAL_PWR_EnterSTOPMode	16	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:343:6:HAL_PWR_EnterSTANDBYMode	8	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:364:6:HAL_PWR_EnableSleepOnExit	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:377:6:HAL_PWR_DisableSleepOnExit	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:390:6:HAL_PWR_EnableSEVOnPend	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:402:6:HAL_PWR_DisableSEVOnPend	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:73:6:HAL_PWR_DeInit	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:207:6:HAL_PWR_EnableWakeUpPin	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:228:6:HAL_PWR_DisableWakeUpPin	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:252:6:HAL_PWR_EnterSLEEPMode	0	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:300:6:HAL_PWR_EnterSTOPMode	0	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:343:6:HAL_PWR_EnterSTANDBYMode	0	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:364:6:HAL_PWR_EnableSleepOnExit	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:377:6:HAL_PWR_DisableSleepOnExit	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:390:6:HAL_PWR_EnableSEVOnPend	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.c:402:6:HAL_PWR_DisableSEVOnPend	0	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.d
index b76576d..573b4d7 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
index ea12657..06aad34 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.su
index f499377..4907f89 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.su
@@ -1,13 +1,13 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:163:6:HAL_PWREx_EnableInternalWakeUpLine	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:173:6:HAL_PWREx_DisableInternalWakeUpLine	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:198:19:HAL_PWREx_EnableGPIOPullUp	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:254:19:HAL_PWREx_DisableGPIOPullUp	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:311:19:HAL_PWREx_EnableGPIOPullDown	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:367:19:HAL_PWREx_DisableGPIOPullDown	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:415:6:HAL_PWREx_EnablePullUpPullDownConfig	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:426:6:HAL_PWREx_DisablePullUpPullDownConfig	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:440:6:HAL_PWREx_EnableFlashPowerDown	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:456:6:HAL_PWREx_DisableFlashPowerDown	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:481:6:HAL_PWREx_EnterSHUTDOWNMode	8	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:525:6:HAL_PWREx_BKUPWrite	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:546:10:HAL_PWREx_BKUPRead	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:163:6:HAL_PWREx_EnableInternalWakeUpLine	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:173:6:HAL_PWREx_DisableInternalWakeUpLine	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:198:19:HAL_PWREx_EnableGPIOPullUp	4	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:254:19:HAL_PWREx_DisableGPIOPullUp	4	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:311:19:HAL_PWREx_EnableGPIOPullDown	4	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:367:19:HAL_PWREx_DisableGPIOPullDown	4	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:415:6:HAL_PWREx_EnablePullUpPullDownConfig	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:426:6:HAL_PWREx_DisablePullUpPullDownConfig	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:440:6:HAL_PWREx_EnableFlashPowerDown	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:456:6:HAL_PWREx_DisableFlashPowerDown	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:481:6:HAL_PWREx_EnterSHUTDOWNMode	0	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:525:6:HAL_PWREx_BKUPWrite	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.c:546:10:HAL_PWREx_BKUPRead	0	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.cyclo
index 5c77793..8594264 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.cyclo
@@ -1,10 +1,8 @@
-../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h:1365:22:LL_RCC_ConfigMCO	1
-../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h:1406:22:LL_RCC_ConfigMCO2	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:202:19:HAL_RCC_DeInit	8
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:293:19:HAL_RCC_OscConfig	41
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:642:19:HAL_RCC_ClockConfig	21
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:856:6:HAL_RCC_MCOConfig	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:202:19:HAL_RCC_DeInit	7
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:293:19:HAL_RCC_OscConfig	38
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:856:6:HAL_RCC_MCOConfig	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:940:10:HAL_RCC_GetSysClockFreq	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:642:19:HAL_RCC_ClockConfig	21
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:996:10:HAL_RCC_GetHCLKFreq	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1009:10:HAL_RCC_GetPCLK1Freq	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1022:6:HAL_RCC_GetOscConfig	1
@@ -12,6 +10,6 @@
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1122:6:HAL_RCC_EnableCSS	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1138:6:HAL_RCC_EnableLSECSS	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1149:6:HAL_RCC_DisableLSECSS	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1159:6:HAL_RCC_NMI_IRQHandler	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1185:13:HAL_RCC_CSSCallback	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1196:13:HAL_RCC_LSECSSCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1159:6:HAL_RCC_NMI_IRQHandler	3
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.d
index e256fc2..2a5a3f5 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
index f85387e..750f3a9 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.su
index 695134f..9398a77 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.su
@@ -1,17 +1,15 @@
-../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h:1365:22:LL_RCC_ConfigMCO	16	static
-../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_rcc.h:1406:22:LL_RCC_ConfigMCO2	16	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:202:19:HAL_RCC_DeInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:293:19:HAL_RCC_OscConfig	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:642:19:HAL_RCC_ClockConfig	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:856:6:HAL_RCC_MCOConfig	56	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:940:10:HAL_RCC_GetSysClockFreq	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:293:19:HAL_RCC_OscConfig	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:856:6:HAL_RCC_MCOConfig	48	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:940:10:HAL_RCC_GetSysClockFreq	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:642:19:HAL_RCC_ClockConfig	32	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:996:10:HAL_RCC_GetHCLKFreq	8	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1009:10:HAL_RCC_GetPCLK1Freq	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1022:6:HAL_RCC_GetOscConfig	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1082:6:HAL_RCC_GetClockConfig	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1122:6:HAL_RCC_EnableCSS	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1138:6:HAL_RCC_EnableLSECSS	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1149:6:HAL_RCC_DisableLSECSS	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1159:6:HAL_RCC_NMI_IRQHandler	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1185:13:HAL_RCC_CSSCallback	8	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1196:13:HAL_RCC_LSECSSCallback	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1022:6:HAL_RCC_GetOscConfig	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1082:6:HAL_RCC_GetClockConfig	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1122:6:HAL_RCC_EnableCSS	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1138:6:HAL_RCC_EnableLSECSS	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1149:6:HAL_RCC_DisableLSECSS	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1185:13:HAL_RCC_CSSCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1196:13:HAL_RCC_LSECSSCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.c:1159:6:HAL_RCC_NMI_IRQHandler	8	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.cyclo
index 37c8f4d..686cff0 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.cyclo
@@ -1,5 +1,5 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:95:19:HAL_RCCEx_PeriphCLKConfig	15
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:95:19:HAL_RCCEx_PeriphCLKConfig	14
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:253:6:HAL_RCCEx_GetPeriphCLKConfig	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:309:10:HAL_RCCEx_GetPeriphCLKFreq	31
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:309:10:HAL_RCCEx_GetPeriphCLKFreq	27
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:520:6:HAL_RCCEx_EnableLSCO	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:545:6:HAL_RCCEx_DisableLSCO	1
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.d
index a491f7b..86b97c0 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
index 6aed708..cdf9fe2 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.su
index 20a0818..254e700 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.su
@@ -1,5 +1,5 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:95:19:HAL_RCCEx_PeriphCLKConfig	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:253:6:HAL_RCCEx_GetPeriphCLKConfig	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:309:10:HAL_RCCEx_GetPeriphCLKFreq	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:95:19:HAL_RCCEx_PeriphCLKConfig	40	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:253:6:HAL_RCCEx_GetPeriphCLKConfig	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:309:10:HAL_RCCEx_GetPeriphCLKFreq	8	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:520:6:HAL_RCCEx_EnableLSCO	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:545:6:HAL_RCCEx_DisableLSCO	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.c:545:6:HAL_RCCEx_DisableLSCO	0	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.cyclo
index 3ddbfd9..8f02fc3 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.cyclo
@@ -1,89 +1,71 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:277:19:HAL_TIM_Base_Init	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:337:19:HAL_TIM_Base_DeInit	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6988:13:TIM_OC1_SetConfig	4
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7140:13:TIM_OC3_SetConfig	4
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7215:13:TIM_OC4_SetConfig	4
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7276:13:TIM_OC5_SetConfig	4
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7330:13:TIM_OC6_SetConfig	4
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:380:13:HAL_TIM_Base_MspInit	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:395:13:HAL_TIM_Base_MspDeInit	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:337:19:HAL_TIM_Base_DeInit	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:411:19:HAL_TIM_Base_Start	7
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:450:19:HAL_TIM_Base_Stop	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:470:19:HAL_TIM_Base_Start_IT	7
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:512:19:HAL_TIM_Base_Stop_IT	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:537:19:HAL_TIM_Base_Start_DMA	11
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:606:19:HAL_TIM_Base_Stop_DMA	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:661:19:HAL_TIM_OC_Init	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:721:19:HAL_TIM_OC_DeInit	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:764:13:HAL_TIM_OC_MspInit	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:779:13:HAL_TIM_OC_MspDeInit	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:802:19:HAL_TIM_OC_Start	21
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:858:19:HAL_TIM_OC_Stop	14
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:893:19:HAL_TIM_OC_Start_IT	28
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:986:19:HAL_TIM_OC_Stop_IT	21
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1063:19:HAL_TIM_OC_Start_DMA	40
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1227:19:HAL_TIM_OC_Stop_DMA	21
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1330:19:HAL_TIM_PWM_Init	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1390:19:HAL_TIM_PWM_DeInit	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:721:19:HAL_TIM_OC_DeInit	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspInit	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1448:13:HAL_TIM_PWM_MspDeInit	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1471:19:HAL_TIM_PWM_Start	21
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1527:19:HAL_TIM_PWM_Stop	14
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1562:19:HAL_TIM_PWM_Start_IT	28
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1655:19:HAL_TIM_PWM_Stop_IT	21
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1732:19:HAL_TIM_PWM_Start_DMA	40
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1895:19:HAL_TIM_PWM_Stop_DMA	21
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1998:19:HAL_TIM_IC_Init	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2058:19:HAL_TIM_IC_DeInit	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1390:19:HAL_TIM_PWM_DeInit	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2101:13:HAL_TIM_IC_MspInit	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2116:13:HAL_TIM_IC_MspDeInit	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2137:19:HAL_TIM_IC_Start	24
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2189:19:HAL_TIM_IC_Stop	11
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2219:19:HAL_TIM_IC_Start_IT	31
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2311:19:HAL_TIM_IC_Stop_IT	18
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2383:19:HAL_TIM_IC_Start_DMA	38
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2542:19:HAL_TIM_IC_Stop_DMA	18
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2647:19:HAL_TIM_OnePulse_Init	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2716:19:HAL_TIM_OnePulse_DeInit	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2058:19:HAL_TIM_IC_DeInit	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2761:13:HAL_TIM_OnePulse_MspInit	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2776:13:HAL_TIM_OnePulse_MspDeInit	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2796:19:HAL_TIM_OnePulse_Start	9
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2853:19:HAL_TIM_OnePulse_Stop	9
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2896:19:HAL_TIM_OnePulse_Start_IT	9
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2959:19:HAL_TIM_OnePulse_Stop_IT	9
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3038:19:HAL_TIM_Encoder_Init	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3153:19:HAL_TIM_Encoder_DeInit	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2716:19:HAL_TIM_OnePulse_DeInit	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2796:19:HAL_TIM_OnePulse_Start	8
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2853:19:HAL_TIM_OnePulse_Stop	8
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2896:19:HAL_TIM_OnePulse_Start_IT	8
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2959:19:HAL_TIM_OnePulse_Stop_IT	8
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3198:13:HAL_TIM_Encoder_MspInit	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3213:13:HAL_TIM_Encoder_MspDeInit	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3233:19:HAL_TIM_Encoder_Start	13
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3327:19:HAL_TIM_Encoder_Stop	15
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3387:19:HAL_TIM_Encoder_Start_IT	13
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3487:19:HAL_TIM_Encoder_Stop_IT	15
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3552:19:HAL_TIM_Encoder_Start_DMA	32
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3765:19:HAL_TIM_Encoder_Stop_DMA	15
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3842:6:HAL_TIM_IRQHandler	24
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4076:19:HAL_TIM_OC_ConfigChannel	9
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4175:19:HAL_TIM_IC_ConfigChannel	6
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4276:19:HAL_TIM_PWM_ConfigChannel	9
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4424:19:HAL_TIM_OnePulse_ConfigChannel	8
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3153:19:HAL_TIM_Encoder_DeInit	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3233:19:HAL_TIM_Encoder_Start	11
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3327:19:HAL_TIM_Encoder_Stop	7
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3387:19:HAL_TIM_Encoder_Start_IT	11
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3487:19:HAL_TIM_Encoder_Stop_IT	7
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3552:19:HAL_TIM_Encoder_Start_DMA	30
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3765:19:HAL_TIM_Encoder_Stop_DMA	7
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4636:19:HAL_TIM_DMABurst_MultiWriteStart	20
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4578:19:HAL_TIM_DMABurst_WriteStart	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4636:19:HAL_TIM_DMABurst_MultiWriteStart	25
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4820:19:HAL_TIM_DMABurst_WriteStop	14
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4820:19:HAL_TIM_DMABurst_WriteStop	9
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4984:19:HAL_TIM_DMABurst_MultiReadStart	20
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4927:19:HAL_TIM_DMABurst_ReadStart	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4984:19:HAL_TIM_DMABurst_MultiReadStart	25
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5168:19:HAL_TIM_DMABurst_ReadStop	14
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5168:19:HAL_TIM_DMABurst_ReadStop	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5252:19:HAL_TIM_GenerateEvent	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5291:19:HAL_TIM_ConfigOCrefClear	19
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5452:19:HAL_TIM_ConfigClockSource	20
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5606:19:HAL_TIM_ConfigTI1Input	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5638:19:HAL_TIM_SlaveConfigSynchro	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5678:19:HAL_TIM_SlaveConfigSynchro_IT	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5721:10:HAL_TIM_ReadCapturedValue	7
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5721:10:HAL_TIM_ReadCapturedValue	6
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5805:13:HAL_TIM_PeriodElapsedCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6861:13:TIM_DMAPeriodElapsedCplt	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5820:13:HAL_TIM_PeriodElapsedHalfCpltCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6882:13:TIM_DMAPeriodElapsedHalfCplt	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5835:13:HAL_TIM_OC_DelayElapsedCallback	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5850:13:HAL_TIM_IC_CaptureCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6759:6:TIM_DMACaptureCplt	9
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5865:13:HAL_TIM_IC_CaptureHalfCpltCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6822:6:TIM_DMACaptureHalfCplt	5
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5880:13:HAL_TIM_PWM_PulseFinishedCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6661:13:TIM_DMADelayPulseCplt	9
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5895:13:HAL_TIM_PWM_PulseFinishedHalfCpltCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6720:6:TIM_DMADelayPulseHalfCplt	5
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5910:13:HAL_TIM_TriggerCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3842:6:HAL_TIM_IRQHandler	23
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6898:13:TIM_DMATriggerCplt	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5925:13:HAL_TIM_TriggerHalfCpltCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6919:13:TIM_DMATriggerHalfCplt	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5940:13:HAL_TIM_ErrorCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6618:6:TIM_DMAError	5
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6498:22:HAL_TIM_Base_GetState	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6508:22:HAL_TIM_OC_GetState	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6518:22:HAL_TIM_PWM_GetState	1
@@ -91,31 +73,43 @@
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6538:22:HAL_TIM_OnePulse_GetState	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6548:22:HAL_TIM_Encoder_GetState	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6558:23:HAL_TIM_GetActiveChannel	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6576:29:HAL_TIM_GetChannelState	6
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6576:29:HAL_TIM_GetChannelState	7
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6593:30:HAL_TIM_DMABurstState	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6618:6:TIM_DMAError	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6661:13:TIM_DMADelayPulseCplt	9
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6720:6:TIM_DMADelayPulseHalfCplt	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6759:6:TIM_DMACaptureCplt	9
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6822:6:TIM_DMACaptureHalfCplt	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6861:13:TIM_DMAPeriodElapsedCplt	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6882:13:TIM_DMAPeriodElapsedHalfCplt	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6898:13:TIM_DMATriggerCplt	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6919:13:TIM_DMATriggerHalfCplt	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6936:6:TIM_Base_SetConfig	13
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6988:13:TIM_OC1_SetConfig	7
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7064:6:TIM_OC2_SetConfig	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7140:13:TIM_OC3_SetConfig	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7215:13:TIM_OC4_SetConfig	4
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7276:13:TIM_OC5_SetConfig	4
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7330:13:TIM_OC6_SetConfig	4
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7385:26:TIM_SlaveTimer_SetConfig	16
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7519:6:TIM_TI1_SetConfig	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7566:13:TIM_TI1_ConfigInputStage	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7609:13:TIM_TI2_SetConfig	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7649:13:TIM_TI2_ConfigInputStage	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7692:13:TIM_TI3_SetConfig	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7740:13:TIM_TI4_SetConfig	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7783:13:TIM_ITRx_SetConfig	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6936:6:TIM_Base_SetConfig	10
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:277:19:HAL_TIM_Base_Init	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:661:19:HAL_TIM_OC_Init	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1330:19:HAL_TIM_PWM_Init	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1998:19:HAL_TIM_IC_Init	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2647:19:HAL_TIM_OnePulse_Init	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3038:19:HAL_TIM_Encoder_Init	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7064:6:TIM_OC2_SetConfig	4
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4076:19:HAL_TIM_OC_ConfigChannel	9
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4276:19:HAL_TIM_PWM_ConfigChannel	9
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7519:6:TIM_TI1_SetConfig	4
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4175:19:HAL_TIM_IC_ConfigChannel	7
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:4424:19:HAL_TIM_OnePulse_ConfigChannel	7
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7813:6:TIM_ETR_SetConfig	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5291:19:HAL_TIM_ConfigOCrefClear	18
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5452:19:HAL_TIM_ConfigClockSource	14
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7385:26:TIM_SlaveTimer_SetConfig.constprop	10
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5678:19:HAL_TIM_SlaveConfigSynchro_IT	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5638:19:HAL_TIM_SlaveConfigSynchro	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7845:6:TIM_CCxChannelCmd	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:802:19:HAL_TIM_OC_Start	22
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1471:19:HAL_TIM_PWM_Start	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:858:19:HAL_TIM_OC_Stop	14
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1527:19:HAL_TIM_PWM_Stop	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:893:19:HAL_TIM_OC_Start_IT	22
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1562:19:HAL_TIM_PWM_Start_IT	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:986:19:HAL_TIM_OC_Stop_IT	16
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1655:19:HAL_TIM_PWM_Stop_IT	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1063:19:HAL_TIM_OC_Start_DMA	38
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1732:19:HAL_TIM_PWM_Start_DMA	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1227:19:HAL_TIM_OC_Stop_DMA	16
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1895:19:HAL_TIM_PWM_Stop_DMA	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2137:19:HAL_TIM_IC_Start	20
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2189:19:HAL_TIM_IC_Stop	9
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2219:19:HAL_TIM_IC_Start_IT	20
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2311:19:HAL_TIM_IC_Stop_IT	11
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2383:19:HAL_TIM_IC_Start_DMA	33
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2542:19:HAL_TIM_IC_Stop_DMA	11
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.d
index ecea28d..62f839f 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
index 8984e00..0388ce3 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.su
index 22f10d3..6d0a8f3 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.su
@@ -1,121 +1,115 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:277:19:HAL_TIM_Base_Init	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:6988:13:TIM_OC1_SetConfig	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7140:13:TIM_OC3_SetConfig	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7215:13:TIM_OC4_SetConfig	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7276:13:TIM_OC5_SetConfig	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7330:13:TIM_OC6_SetConfig	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:380:13:HAL_TIM_Base_MspInit	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:395:13:HAL_TIM_Base_MspDeInit	0	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:337:19:HAL_TIM_Base_DeInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:380:13:HAL_TIM_Base_MspInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:395:13:HAL_TIM_Base_MspDeInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:411:19:HAL_TIM_Base_Start	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:450:19:HAL_TIM_Base_Stop	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:470:19:HAL_TIM_Base_Start_IT	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:512:19:HAL_TIM_Base_Stop_IT	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:537:19:HAL_TIM_Base_Start_DMA	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:606:19:HAL_TIM_Base_Stop_DMA	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:661:19:HAL_TIM_OC_Init	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:411:19:HAL_TIM_Base_Start	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:450:19:HAL_TIM_Base_Stop	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:470:19:HAL_TIM_Base_Start_IT	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:512:19:HAL_TIM_Base_Stop_IT	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:537:19:HAL_TIM_Base_Start_DMA	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:606:19:HAL_TIM_Base_Stop_DMA	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:764:13:HAL_TIM_OC_MspInit	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:779:13:HAL_TIM_OC_MspDeInit	0	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:721:19:HAL_TIM_OC_DeInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:764:13:HAL_TIM_OC_MspInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:779:13:HAL_TIM_OC_MspDeInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:802:19:HAL_TIM_OC_Start	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:858:19:HAL_TIM_OC_Stop	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:893:19:HAL_TIM_OC_Start_IT	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:986:19:HAL_TIM_OC_Stop_IT	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1063:19:HAL_TIM_OC_Start_DMA	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1227:19:HAL_TIM_OC_Stop_DMA	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1330:19:HAL_TIM_PWM_Init	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspInit	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1448:13:HAL_TIM_PWM_MspDeInit	0	static
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-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1433:13:HAL_TIM_PWM_MspInit	16	static
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-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1998:19:HAL_TIM_IC_Init	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2101:13:HAL_TIM_IC_MspInit	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2116:13:HAL_TIM_IC_MspDeInit	0	static
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-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2647:19:HAL_TIM_OnePulse_Init	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2761:13:HAL_TIM_OnePulse_MspInit	0	static
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+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2796:19:HAL_TIM_OnePulse_Start	32	static
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-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3327:19:HAL_TIM_Encoder_Stop	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3327:19:HAL_TIM_Encoder_Stop	8	static
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-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:3487:19:HAL_TIM_Encoder_Stop_IT	16	static
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-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7649:13:TIM_TI2_ConfigInputStage	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7692:13:TIM_TI3_SetConfig	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7740:13:TIM_TI4_SetConfig	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7783:13:TIM_ITRx_SetConfig	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7813:6:TIM_ETR_SetConfig	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7845:6:TIM_CCxChannelCmd	32	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7385:26:TIM_SlaveTimer_SetConfig.constprop	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5678:19:HAL_TIM_SlaveConfigSynchro_IT	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:5638:19:HAL_TIM_SlaveConfigSynchro	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:7845:6:TIM_CCxChannelCmd	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:802:19:HAL_TIM_OC_Start	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1471:19:HAL_TIM_PWM_Start	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:858:19:HAL_TIM_OC_Stop	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1527:19:HAL_TIM_PWM_Stop	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:893:19:HAL_TIM_OC_Start_IT	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1562:19:HAL_TIM_PWM_Start_IT	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:986:19:HAL_TIM_OC_Stop_IT	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1655:19:HAL_TIM_PWM_Stop_IT	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1063:19:HAL_TIM_OC_Start_DMA	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1732:19:HAL_TIM_PWM_Start_DMA	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1227:19:HAL_TIM_OC_Stop_DMA	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:1895:19:HAL_TIM_PWM_Stop_DMA	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2137:19:HAL_TIM_IC_Start	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2189:19:HAL_TIM_IC_Stop	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2219:19:HAL_TIM_IC_Start_IT	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2311:19:HAL_TIM_IC_Stop_IT	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2383:19:HAL_TIM_IC_Start_DMA	32	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.c:2542:19:HAL_TIM_IC_Stop_DMA	16	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.cyclo
index 6986937..4531c86 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.cyclo
@@ -1,7 +1,10 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:151:19:HAL_TIMEx_HallSensor_Init	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:253:19:HAL_TIMEx_HallSensor_DeInit	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2784:13:TIM_CCxNChannelCmd	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2739:13:TIM_DMAErrorCCxN	4
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2689:13:TIM_DMADelayPulseNCplt	7
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:298:13:HAL_TIMEx_HallSensor_MspInit	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:151:19:HAL_TIMEx_HallSensor_Init	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:313:13:HAL_TIMEx_HallSensor_MspDeInit	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:253:19:HAL_TIMEx_HallSensor_DeInit	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:328:19:HAL_TIMEx_HallSensor_Start	10
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:382:19:HAL_TIMEx_HallSensor_Stop	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:410:19:HAL_TIMEx_HallSensor_Start_IT	10
@@ -10,39 +13,36 @@
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:576:19:HAL_TIMEx_HallSensor_Stop_DMA	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:638:19:HAL_TIMEx_OCN_Start	13
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:689:19:HAL_TIMEx_OCN_Stop	8
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:721:19:HAL_TIMEx_OCN_Start_IT	18
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:808:19:HAL_TIMEx_OCN_Stop_IT	14
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:883:19:HAL_TIMEx_OCN_Start_DMA	27
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1021:19:HAL_TIMEx_OCN_Stop_DMA	13
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1111:19:HAL_TIMEx_PWMN_Start	13
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1161:19:HAL_TIMEx_PWMN_Stop	8
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1193:19:HAL_TIMEx_PWMN_Start_IT	18
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1279:19:HAL_TIMEx_PWMN_Stop_IT	14
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1354:19:HAL_TIMEx_PWMN_Start_DMA	27
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1492:19:HAL_TIMEx_PWMN_Stop_DMA	13
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1583:19:HAL_TIMEx_OnePulseN_Start	6
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1632:19:HAL_TIMEx_OnePulseN_Stop	6
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1671:19:HAL_TIMEx_OnePulseN_Start_IT	6
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1726:19:HAL_TIMEx_OnePulseN_Stop_IT	6
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1811:19:HAL_TIMEx_ConfigCommutEvent	6
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1877:19:HAL_TIMEx_ConfigCommutEvent_IT	6
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1944:19:HAL_TIMEx_ConfigCommutEvent_DMA	6
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:721:19:HAL_TIMEx_OCN_Start_IT	13
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:808:19:HAL_TIMEx_OCN_Stop_IT	11
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:883:19:HAL_TIMEx_OCN_Start_DMA	22
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1021:19:HAL_TIMEx_OCN_Stop_DMA	10
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1111:19:HAL_TIMEx_PWMN_Start	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1161:19:HAL_TIMEx_PWMN_Stop	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1193:19:HAL_TIMEx_PWMN_Start_IT	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1279:19:HAL_TIMEx_PWMN_Stop_IT	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1354:19:HAL_TIMEx_PWMN_Start_DMA	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1492:19:HAL_TIMEx_PWMN_Stop_DMA	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1583:19:HAL_TIMEx_OnePulseN_Start	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1632:19:HAL_TIMEx_OnePulseN_Stop	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1671:19:HAL_TIMEx_OnePulseN_Start_IT	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1726:19:HAL_TIMEx_OnePulseN_Stop_IT	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1811:19:HAL_TIMEx_ConfigCommutEvent	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1877:19:HAL_TIMEx_ConfigCommutEvent_IT	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1944:19:HAL_TIMEx_ConfigCommutEvent_DMA	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1999:19:HAL_TIMEx_MasterConfigSynchronization	6
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2072:19:HAL_TIMEx_ConfigBreakDeadTime	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2140:19:HAL_TIMEx_ConfigBreakInput	5
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2251:19:HAL_TIMEx_RemapConfig	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2306:20:HAL_TIMEx_TISelection	6
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2306:20:HAL_TIMEx_TISelection	5
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2348:19:HAL_TIMEx_GroupChannel5	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2386:19:HAL_TIMEx_DisarmBreakInput	7
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2386:19:HAL_TIMEx_DisarmBreakInput	5
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2440:19:HAL_TIMEx_ReArmBreakInput	11
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2529:13:HAL_TIMEx_CommutCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2650:6:TIMEx_DMACommutationCplt	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2543:13:HAL_TIMEx_CommutHalfCpltCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2669:6:TIMEx_DMACommutationHalfCplt	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2558:13:HAL_TIMEx_BreakCallback	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2573:13:HAL_TIMEx_Break2Callback	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2606:22:HAL_TIMEx_HallSensor_GetState	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2621:29:HAL_TIMEx_GetChannelNState	4
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2650:6:TIMEx_DMACommutationCplt	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2669:6:TIMEx_DMACommutationHalfCplt	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2689:13:TIM_DMADelayPulseNCplt	7
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2739:13:TIM_DMAErrorCCxN	4
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2784:13:TIM_CCxNChannelCmd	1
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.d
index c5bc97f..65fdfab 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
index bd79adf..551fcfe 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.su
index 739581b..0890f6d 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.su
@@ -1,48 +1,48 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:151:19:HAL_TIMEx_HallSensor_Init	48	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2784:13:TIM_CCxNChannelCmd	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2739:13:TIM_DMAErrorCCxN	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2689:13:TIM_DMADelayPulseNCplt	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:298:13:HAL_TIMEx_HallSensor_MspInit	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:151:19:HAL_TIMEx_HallSensor_Init	56	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:313:13:HAL_TIMEx_HallSensor_MspDeInit	0	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:253:19:HAL_TIMEx_HallSensor_DeInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:298:13:HAL_TIMEx_HallSensor_MspInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:313:13:HAL_TIMEx_HallSensor_MspDeInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:328:19:HAL_TIMEx_HallSensor_Start	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:382:19:HAL_TIMEx_HallSensor_Stop	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:410:19:HAL_TIMEx_HallSensor_Start_IT	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:467:19:HAL_TIMEx_HallSensor_Stop_IT	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:500:19:HAL_TIMEx_HallSensor_Start_DMA	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:576:19:HAL_TIMEx_HallSensor_Stop_DMA	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:638:19:HAL_TIMEx_OCN_Start	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:328:19:HAL_TIMEx_HallSensor_Start	32	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:382:19:HAL_TIMEx_HallSensor_Stop	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:410:19:HAL_TIMEx_HallSensor_Start_IT	32	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:467:19:HAL_TIMEx_HallSensor_Stop_IT	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:500:19:HAL_TIMEx_HallSensor_Start_DMA	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:576:19:HAL_TIMEx_HallSensor_Stop_DMA	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:638:19:HAL_TIMEx_OCN_Start	8	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:689:19:HAL_TIMEx_OCN_Stop	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:721:19:HAL_TIMEx_OCN_Start_IT	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:808:19:HAL_TIMEx_OCN_Stop_IT	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:883:19:HAL_TIMEx_OCN_Start_DMA	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1021:19:HAL_TIMEx_OCN_Stop_DMA	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1111:19:HAL_TIMEx_PWMN_Start	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1161:19:HAL_TIMEx_PWMN_Stop	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1193:19:HAL_TIMEx_PWMN_Start_IT	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1279:19:HAL_TIMEx_PWMN_Stop_IT	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1354:19:HAL_TIMEx_PWMN_Start_DMA	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1492:19:HAL_TIMEx_PWMN_Stop_DMA	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:721:19:HAL_TIMEx_OCN_Start_IT	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:808:19:HAL_TIMEx_OCN_Stop_IT	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:883:19:HAL_TIMEx_OCN_Start_DMA	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1021:19:HAL_TIMEx_OCN_Stop_DMA	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1111:19:HAL_TIMEx_PWMN_Start	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1161:19:HAL_TIMEx_PWMN_Stop	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1193:19:HAL_TIMEx_PWMN_Start_IT	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1279:19:HAL_TIMEx_PWMN_Stop_IT	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1354:19:HAL_TIMEx_PWMN_Start_DMA	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1492:19:HAL_TIMEx_PWMN_Stop_DMA	8	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1583:19:HAL_TIMEx_OnePulseN_Start	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1632:19:HAL_TIMEx_OnePulseN_Stop	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1632:19:HAL_TIMEx_OnePulseN_Stop	16	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1671:19:HAL_TIMEx_OnePulseN_Start_IT	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1726:19:HAL_TIMEx_OnePulseN_Stop_IT	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1811:19:HAL_TIMEx_ConfigCommutEvent	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1877:19:HAL_TIMEx_ConfigCommutEvent_IT	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1944:19:HAL_TIMEx_ConfigCommutEvent_DMA	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1999:19:HAL_TIMEx_MasterConfigSynchronization	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2072:19:HAL_TIMEx_ConfigBreakDeadTime	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2140:19:HAL_TIMEx_ConfigBreakInput	48	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2251:19:HAL_TIMEx_RemapConfig	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2306:20:HAL_TIMEx_TISelection	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2348:19:HAL_TIMEx_GroupChannel5	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2386:19:HAL_TIMEx_DisarmBreakInput	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2440:19:HAL_TIMEx_ReArmBreakInput	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2529:13:HAL_TIMEx_CommutCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2543:13:HAL_TIMEx_CommutHalfCpltCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2558:13:HAL_TIMEx_BreakCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2573:13:HAL_TIMEx_Break2Callback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2606:22:HAL_TIMEx_HallSensor_GetState	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2621:29:HAL_TIMEx_GetChannelNState	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2650:6:TIMEx_DMACommutationCplt	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2669:6:TIMEx_DMACommutationHalfCplt	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2689:13:TIM_DMADelayPulseNCplt	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2739:13:TIM_DMAErrorCCxN	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2784:13:TIM_CCxNChannelCmd	32	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1726:19:HAL_TIMEx_OnePulseN_Stop_IT	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1811:19:HAL_TIMEx_ConfigCommutEvent	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1877:19:HAL_TIMEx_ConfigCommutEvent_IT	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1944:19:HAL_TIMEx_ConfigCommutEvent_DMA	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:1999:19:HAL_TIMEx_MasterConfigSynchronization	20	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2072:19:HAL_TIMEx_ConfigBreakDeadTime	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2140:19:HAL_TIMEx_ConfigBreakInput	20	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2251:19:HAL_TIMEx_RemapConfig	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2306:20:HAL_TIMEx_TISelection	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2348:19:HAL_TIMEx_GroupChannel5	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2386:19:HAL_TIMEx_DisarmBreakInput	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2440:19:HAL_TIMEx_ReArmBreakInput	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2529:13:HAL_TIMEx_CommutCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2650:6:TIMEx_DMACommutationCplt	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2543:13:HAL_TIMEx_CommutHalfCpltCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2669:6:TIMEx_DMACommutationHalfCplt	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2558:13:HAL_TIMEx_BreakCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2573:13:HAL_TIMEx_Break2Callback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2606:22:HAL_TIMEx_HallSensor_GetState	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.c:2621:29:HAL_TIMEx_GetChannelNState	0	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.cyclo
index f549558..188da1c 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.cyclo
@@ -1,70 +1,70 @@
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:307:19:HAL_UART_Init	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:382:19:HAL_HalfDuplex_Init	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:457:19:HAL_LIN_Init	7
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:556:19:HAL_MultiProcessor_Init	6
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:632:19:HAL_UART_DeInit	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3612:13:UART_EndTxTransfer	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3629:13:UART_EndRxTransfer	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4065:13:UART_TxISR_8BIT.part.0	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4065:13:UART_TxISR_8BIT	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4094:13:UART_TxISR_16BIT	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4126:13:UART_TxISR_8BIT_FIFOEN	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4166:13:UART_TxISR_16BIT_FIFOEN	5
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:679:13:HAL_UART_MspInit	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:694:13:HAL_UART_MspDeInit	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1126:19:HAL_UART_Transmit	13
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1232:19:HAL_UART_Receive	18
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:632:19:HAL_UART_DeInit	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1332:19:HAL_UART_Transmit_IT	12
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1416:19:HAL_UART_Receive_IT	8
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1471:19:HAL_UART_Transmit_DMA	9
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1557:19:HAL_UART_Receive_DMA	8
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1601:19:HAL_UART_DMAPause	5
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1631:19:HAL_UART_DMAResume	4
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1662:19:HAL_UART_DMAStop	11
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1738:19:HAL_UART_Abort	11
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1843:19:HAL_UART_AbortTransmit	6
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1904:19:HAL_UART_AbortReceive	6
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1974:19:HAL_UART_Abort_IT	14
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2129:19:HAL_UART_AbortTransmit_IT	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2222:19:HAL_UART_AbortReceive_IT	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2317:6:HAL_UART_IRQHandler	53
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2675:13:HAL_UART_TxCpltCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3656:13:UART_DMATransmitCplt	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2690:13:HAL_UART_TxHalfCpltCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3690:13:UART_DMATxHalfCplt	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2705:13:HAL_UART_RxCpltCallback	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2720:13:HAL_UART_RxHalfCpltCallback	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2735:13:HAL_UART_ErrorCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3829:13:UART_DMAError	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3869:13:UART_DMAAbortOnError	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2750:13:HAL_UART_AbortCpltCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1974:19:HAL_UART_Abort_IT	14
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3946:13:UART_DMARxAbortCallback	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3891:13:UART_DMATxAbortCallback	4
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2765:13:HAL_UART_AbortTransmitCpltCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2129:19:HAL_UART_AbortTransmit_IT	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3998:13:UART_DMATxOnlyAbortCallback	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2780:13:HAL_UART_AbortReceiveCpltCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2222:19:HAL_UART_AbortReceive_IT	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4031:13:UART_DMARxOnlyAbortCallback	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2797:13:HAL_UARTEx_RxEventCallback	1
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2317:6:HAL_UART_IRQHandler	46
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4232:13:UART_RxISR_8BIT	6
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4320:13:UART_RxISR_16BIT	6
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4410:13:UART_RxISR_8BIT_FIFOEN	18
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4570:13:UART_RxISR_16BIT_FIFOEN	18
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3781:13:UART_DMARxHalfCplt	3
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3708:13:UART_DMAReceiveCplt	5
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2845:6:HAL_UART_ReceiverTimeout_Config	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2857:19:HAL_UART_EnableReceiverTimeout	3
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2888:19:HAL_UART_DisableReceiverTimeout	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2919:19:HAL_MultiProcessor_EnableMuteMode	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2939:19:HAL_MultiProcessor_DisableMuteMode	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2959:6:HAL_MultiProcessor_EnterMuteMode	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2969:19:HAL_HalfDuplex_EnableTransmitter	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2992:19:HAL_HalfDuplex_EnableReceiver	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3016:19:HAL_LIN_SendBreak	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3061:23:HAL_UART_GetState	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3077:10:HAL_UART_GetError	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3123:19:UART_SetConfig	28
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3123:19:UART_SetConfig	19
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3269:6:UART_AdvFeatureConfig	10
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3414:19:UART_WaitOnFlagUntilTimeout	9
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1126:19:HAL_UART_Transmit	13
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1232:19:HAL_UART_Receive	16
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3345:19:UART_CheckIdleState	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3414:19:UART_WaitOnFlagUntilTimeout	10
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3482:19:UART_Start_Receive_IT	15
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:307:19:HAL_UART_Init	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:382:19:HAL_HalfDuplex_Init	5
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:457:19:HAL_LIN_Init	7
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:556:19:HAL_MultiProcessor_Init	6
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2919:19:HAL_MultiProcessor_EnableMuteMode	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2939:19:HAL_MultiProcessor_DisableMuteMode	2
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3482:19:UART_Start_Receive_IT	14
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1416:19:HAL_UART_Receive_IT	8
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3555:19:UART_Start_Receive_DMA	4
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3612:13:UART_EndTxTransfer	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3629:13:UART_EndRxTransfer	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3656:13:UART_DMATransmitCplt	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3690:13:UART_DMATxHalfCplt	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3708:13:UART_DMAReceiveCplt	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3781:13:UART_DMARxHalfCplt	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3829:13:UART_DMAError	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3869:13:UART_DMAAbortOnError	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3891:13:UART_DMATxAbortCallback	4
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3946:13:UART_DMARxAbortCallback	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3998:13:UART_DMATxOnlyAbortCallback	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4031:13:UART_DMARxOnlyAbortCallback	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4065:13:UART_TxISR_8BIT	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4094:13:UART_TxISR_16BIT	3
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4126:13:UART_TxISR_8BIT_FIFOEN	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4166:13:UART_TxISR_16BIT_FIFOEN	5
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4207:13:UART_EndTransmit_IT	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4232:13:UART_RxISR_8BIT	6
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4320:13:UART_RxISR_16BIT	6
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4410:13:UART_RxISR_8BIT_FIFOEN	18
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4570:13:UART_RxISR_16BIT_FIFOEN	18
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1557:19:HAL_UART_Receive_DMA	8
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.d
index a24248e..b326a22 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
index deb3aed..12cdfda 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.su
index efae6b1..a1c1a89 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.su
@@ -1,70 +1,70 @@
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3612:13:UART_EndTxTransfer	12	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3629:13:UART_EndRxTransfer	12	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4065:13:UART_TxISR_8BIT.part.0	12	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4065:13:UART_TxISR_8BIT	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4094:13:UART_TxISR_16BIT	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4126:13:UART_TxISR_8BIT_FIFOEN	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4166:13:UART_TxISR_16BIT_FIFOEN	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:679:13:HAL_UART_MspInit	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:694:13:HAL_UART_MspDeInit	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:632:19:HAL_UART_DeInit	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1332:19:HAL_UART_Transmit_IT	12	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1471:19:HAL_UART_Transmit_DMA	32	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1601:19:HAL_UART_DMAPause	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1631:19:HAL_UART_DMAResume	8	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1662:19:HAL_UART_DMAStop	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1738:19:HAL_UART_Abort	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1843:19:HAL_UART_AbortTransmit	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1904:19:HAL_UART_AbortReceive	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2675:13:HAL_UART_TxCpltCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3656:13:UART_DMATransmitCplt	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2690:13:HAL_UART_TxHalfCpltCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3690:13:UART_DMATxHalfCplt	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2705:13:HAL_UART_RxCpltCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2720:13:HAL_UART_RxHalfCpltCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2735:13:HAL_UART_ErrorCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3829:13:UART_DMAError	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3869:13:UART_DMAAbortOnError	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2750:13:HAL_UART_AbortCpltCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1974:19:HAL_UART_Abort_IT	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3946:13:UART_DMARxAbortCallback	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3891:13:UART_DMATxAbortCallback	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2765:13:HAL_UART_AbortTransmitCpltCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2129:19:HAL_UART_AbortTransmit_IT	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3998:13:UART_DMATxOnlyAbortCallback	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2780:13:HAL_UART_AbortReceiveCpltCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2222:19:HAL_UART_AbortReceive_IT	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4031:13:UART_DMARxOnlyAbortCallback	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2797:13:HAL_UARTEx_RxEventCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2317:6:HAL_UART_IRQHandler	32	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4232:13:UART_RxISR_8BIT	24	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4320:13:UART_RxISR_16BIT	24	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4410:13:UART_RxISR_8BIT_FIFOEN	40	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4570:13:UART_RxISR_16BIT_FIFOEN	40	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3781:13:UART_DMARxHalfCplt	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3708:13:UART_DMAReceiveCplt	24	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2845:6:HAL_UART_ReceiverTimeout_Config	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2857:19:HAL_UART_EnableReceiverTimeout	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2888:19:HAL_UART_DisableReceiverTimeout	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2959:6:HAL_MultiProcessor_EnterMuteMode	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2969:19:HAL_HalfDuplex_EnableTransmitter	20	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2992:19:HAL_HalfDuplex_EnableReceiver	20	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3016:19:HAL_LIN_SendBreak	8	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3061:23:HAL_UART_GetState	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3077:10:HAL_UART_GetError	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3123:19:UART_SetConfig	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3269:6:UART_AdvFeatureConfig	12	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3414:19:UART_WaitOnFlagUntilTimeout	32	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1126:19:HAL_UART_Transmit	48	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1232:19:HAL_UART_Receive	48	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3345:19:UART_CheckIdleState	24	static,ignoring_inline_asm
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:307:19:HAL_UART_Init	16	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:382:19:HAL_HalfDuplex_Init	16	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:457:19:HAL_LIN_Init	16	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:556:19:HAL_MultiProcessor_Init	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:632:19:HAL_UART_DeInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:679:13:HAL_UART_MspInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:694:13:HAL_UART_MspDeInit	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1126:19:HAL_UART_Transmit	48	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1232:19:HAL_UART_Receive	48	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1332:19:HAL_UART_Transmit_IT	56	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1416:19:HAL_UART_Receive_IT	40	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1471:19:HAL_UART_Transmit_DMA	40	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1557:19:HAL_UART_Receive_DMA	40	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1601:19:HAL_UART_DMAPause	88	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1631:19:HAL_UART_DMAResume	80	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1662:19:HAL_UART_DMAStop	56	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1738:19:HAL_UART_Abort	96	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1843:19:HAL_UART_AbortTransmit	64	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1904:19:HAL_UART_AbortReceive	80	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1974:19:HAL_UART_Abort_IT	104	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2129:19:HAL_UART_AbortTransmit_IT	64	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2222:19:HAL_UART_AbortReceive_IT	80	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2317:6:HAL_UART_IRQHandler	184	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2675:13:HAL_UART_TxCpltCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2690:13:HAL_UART_TxHalfCpltCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2705:13:HAL_UART_RxCpltCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2720:13:HAL_UART_RxHalfCpltCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2735:13:HAL_UART_ErrorCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2750:13:HAL_UART_AbortCpltCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2765:13:HAL_UART_AbortTransmitCpltCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2780:13:HAL_UART_AbortReceiveCpltCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2797:13:HAL_UARTEx_RxEventCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2845:6:HAL_UART_ReceiverTimeout_Config	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2857:19:HAL_UART_EnableReceiverTimeout	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2888:19:HAL_UART_DisableReceiverTimeout	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2919:19:HAL_MultiProcessor_EnableMuteMode	32	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2939:19:HAL_MultiProcessor_DisableMuteMode	32	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2959:6:HAL_MultiProcessor_EnterMuteMode	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2969:19:HAL_HalfDuplex_EnableTransmitter	48	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2992:19:HAL_HalfDuplex_EnableReceiver	48	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3016:19:HAL_LIN_SendBreak	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3061:23:HAL_UART_GetState	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3077:10:HAL_UART_GetError	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3123:19:UART_SetConfig	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3269:6:UART_AdvFeatureConfig	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3345:19:UART_CheckIdleState	80	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3414:19:UART_WaitOnFlagUntilTimeout	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3482:19:UART_Start_Receive_IT	104	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3555:19:UART_Start_Receive_DMA	72	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3612:13:UART_EndTxTransfer	48	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3629:13:UART_EndRxTransfer	64	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3656:13:UART_DMATransmitCplt	56	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3690:13:UART_DMATxHalfCplt	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3708:13:UART_DMAReceiveCplt	88	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3781:13:UART_DMARxHalfCplt	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3829:13:UART_DMAError	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3869:13:UART_DMAAbortOnError	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3891:13:UART_DMATxAbortCallback	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3946:13:UART_DMARxAbortCallback	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3998:13:UART_DMATxOnlyAbortCallback	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4031:13:UART_DMARxOnlyAbortCallback	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4065:13:UART_TxISR_8BIT	48	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4094:13:UART_TxISR_16BIT	56	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4126:13:UART_TxISR_8BIT_FIFOEN	56	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4166:13:UART_TxISR_16BIT_FIFOEN	56	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4207:13:UART_EndTransmit_IT	32	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4232:13:UART_RxISR_8BIT	88	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4320:13:UART_RxISR_16BIT	88	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4410:13:UART_RxISR_8BIT_FIFOEN	136	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:4570:13:UART_RxISR_16BIT_FIFOEN	144	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2919:19:HAL_MultiProcessor_EnableMuteMode	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:2939:19:HAL_MultiProcessor_DisableMuteMode	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3482:19:UART_Start_Receive_IT	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1416:19:HAL_UART_Receive_IT	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:3555:19:UART_Start_Receive_DMA	24	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.c:1557:19:HAL_UART_Receive_DMA	16	static,ignoring_inline_asm
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.cyclo b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.cyclo
index 8cbb2ad..8ffc51f 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.cyclo
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.cyclo
@@ -1,3 +1,4 @@
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1049:13:UARTEx_SetNbDataToProcess	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init	5
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback	1
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback	1
@@ -10,9 +11,7 @@
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:605:19:HAL_UARTEx_SetTxFifoThreshold	2
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:654:19:HAL_UARTEx_SetRxFifoThreshold	2
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:716:19:HAL_UARTEx_ReceiveToIdle	23
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:716:19:HAL_UARTEx_ReceiveToIdle	21
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:855:19:HAL_UARTEx_ReceiveToIdle_IT	8
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:929:19:HAL_UARTEx_ReceiveToIdle_DMA	9
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1007:29:HAL_UARTEx_GetRxEventType	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1031:13:UARTEx_Wakeup_AddressConfig	1
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1049:13:UARTEx_SetNbDataToProcess	2
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.d b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.d
index f211705..ba79ede 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.d
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.d
@@ -21,6 +21,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o: \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
+ ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h \
  ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h \
@@ -51,6 +55,10 @@ Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o: \
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_dma_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_cortex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
+../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_exti.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash.h:
 ../Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_flash_ex.h:
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
index 597aa5b..28544ab 100644
Binary files a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o and b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o differ
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.su b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.su
index c6043a6..d6b80b9 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.su
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.su
@@ -1,18 +1,17 @@
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1049:13:UARTEx_SetNbDataToProcess	32	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init	32	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:302:13:HAL_UARTEx_TxFifoEmptyCallback	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback	0	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:302:13:HAL_UARTEx_TxFifoEmptyCallback	0	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:387:19:HAL_MultiProcessorEx_AddressLength_Set	16	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:425:19:HAL_UARTEx_StopModeWakeUpSourceConfig	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:480:19:HAL_UARTEx_EnableStopMode	32	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:499:19:HAL_UARTEx_DisableStopMode	32	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:518:19:HAL_UARTEx_EnableFifoMode	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode	24	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:480:19:HAL_UARTEx_EnableStopMode	8	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:499:19:HAL_UARTEx_DisableStopMode	8	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:518:19:HAL_UARTEx_EnableFifoMode	16	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode	16	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:605:19:HAL_UARTEx_SetTxFifoThreshold	24	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:654:19:HAL_UARTEx_SetRxFifoThreshold	24	static
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:716:19:HAL_UARTEx_ReceiveToIdle	40	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:855:19:HAL_UARTEx_ReceiveToIdle_IT	48	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:929:19:HAL_UARTEx_ReceiveToIdle_DMA	56	static,ignoring_inline_asm
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1007:29:HAL_UARTEx_GetRxEventType	16	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1031:13:UARTEx_Wakeup_AddressConfig	24	static
-../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1049:13:UARTEx_SetNbDataToProcess	40	static
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:855:19:HAL_UARTEx_ReceiveToIdle_IT	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:929:19:HAL_UARTEx_ReceiveToIdle_DMA	16	static,ignoring_inline_asm
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.c:1007:29:HAL_UARTEx_GetRxEventType	0	static
diff --git a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/subdir.mk b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/subdir.mk
index e2d0874..bda6905 100644
--- a/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/subdir.mk
+++ b/code/Debug/Drivers/STM32C0xx_HAL_Driver/Src/subdir.mk
@@ -1,11 +1,13 @@
 ################################################################################
 # Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (13.3.rel1)
+# Toolchain: GNU Tools for STM32 (14.3.rel1)
 ################################################################################
 
 # Add inputs and outputs from these tool invocations to the build variables 
 C_SRCS += \
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.c \
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c \
+../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c \
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.c \
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.c \
 ../Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.c \
@@ -24,6 +26,8 @@ C_SRCS += \
 
 OBJS += \
 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o \
+./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o \
+./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o \
 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o \
 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o \
 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o \
@@ -42,6 +46,8 @@ OBJS += \
 
 C_DEPS += \
 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.d \
+./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.d \
+./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.d \
 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.d \
 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.d \
 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.d \
@@ -61,12 +67,12 @@ C_DEPS += \
 
 # Each subdirectory must supply rules for building sources it contributes
 Drivers/STM32C0xx_HAL_Driver/Src/%.o Drivers/STM32C0xx_HAL_Driver/Src/%.su Drivers/STM32C0xx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32C0xx_HAL_Driver/Src/%.c Drivers/STM32C0xx_HAL_Driver/Src/subdir.mk
-	arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C051xx -c -I../Core/Inc -I../Drivers/STM32C0xx_HAL_Driver/Inc -I../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../Drivers/CMSIS/Include -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
+	arm-none-eabi-gcc "$<" -mcpu=cortex-m0plus -std=gnu11 -g3 -DDEBUG -DUSE_HAL_DRIVER -DSTM32C051xx -c -I../Core/Inc -I../Drivers/STM32C0xx_HAL_Driver/Inc -I../Drivers/STM32C0xx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32C0xx/Include -I../Drivers/CMSIS/Include -Oz -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@"
 
 clean: clean-Drivers-2f-STM32C0xx_HAL_Driver-2f-Src
 
 clean-Drivers-2f-STM32C0xx_HAL_Driver-2f-Src:
-	-$(RM) ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.su
+	-$(RM) ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.su ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.cyclo ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.su
 
 .PHONY: clean-Drivers-2f-STM32C0xx_HAL_Driver-2f-Src
 
diff --git a/code/Debug/feeder_mk2.elf b/code/Debug/feeder_mk2.elf
index e358b8d..d5e1f57 100644
Binary files a/code/Debug/feeder_mk2.elf and b/code/Debug/feeder_mk2.elf differ
diff --git a/code/Debug/feeder_mk2.list b/code/Debug/feeder_mk2.list
index 356455e..d6010ff 100644
--- a/code/Debug/feeder_mk2.list
+++ b/code/Debug/feeder_mk2.list
@@ -5,47 +5,49 @@ Sections:
 Idx Name          Size      VMA       LMA       File off  Algn
   0 .isr_vector   000000c0  08000000  08000000  00001000  2**0
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  1 .text         00007c78  080000c0  080000c0  000010c0  2**2
+  1 .text         00005150  080000c0  080000c0  000010c0  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, CODE
-  2 .rodata       00000154  08007d38  08007d38  00008d38  2**2
+  2 .rodata       000000a8  08005210  08005210  00006210  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  3 .ARM.extab    00000000  08007e8c  08007e8c  00009030  2**0
+  3 .ARM.extab    00000000  080052b8  080052b8  00007030  2**0
                   CONTENTS, READONLY
-  4 .ARM          00000008  08007e8c  08007e8c  00008e8c  2**2
+  4 .ARM          00000008  080052b8  080052b8  000062b8  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  5 .preinit_array 00000000  08007e94  08007e94  00009030  2**0
+  5 .preinit_array 00000000  080052c0  080052c0  00007030  2**0
                   CONTENTS, ALLOC, LOAD, DATA
-  6 .init_array   00000004  08007e94  08007e94  00008e94  2**2
+  6 .init_array   00000004  080052c0  080052c0  000062c0  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  7 .fini_array   00000004  08007e98  08007e98  00008e98  2**2
+  7 .fini_array   00000004  080052c4  080052c4  000062c4  2**2
                   CONTENTS, ALLOC, LOAD, READONLY, DATA
-  8 .data         00000030  20000000  08007e9c  00009000  2**2
+  8 .data         00000030  20000000  080052c8  00007000  2**2
                   CONTENTS, ALLOC, LOAD, DATA
-  9 .bss          00000580  20000030  08007ecc  00009030  2**2
+  9 .bss          00001334  20000030  080052f8  00007030  2**2
                   ALLOC
- 10 ._user_heap_stack 00000600  200005b0  08007ecc  000095b0  2**0
+ 10 ._user_heap_stack 00000604  20001364  080052f8  00007364  2**0
                   ALLOC
- 11 .ARM.attributes 00000028  00000000  00000000  00009030  2**0
+ 11 .ARM.attributes 00000028  00000000  00000000  00007030  2**0
                   CONTENTS, READONLY
- 12 .debug_info   00011b87  00000000  00000000  00009058  2**0
+ 12 .debug_info   0001b022  00000000  00000000  00007058  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 13 .debug_abbrev 00002372  00000000  00000000  0001abdf  2**0
+ 13 .debug_abbrev 00002ea9  00000000  00000000  0002207a  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 14 .debug_aranges 00000f58  00000000  00000000  0001cf58  2**3
+ 14 .debug_loclists 0000c0a2  00000000  00000000  00024f23  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 15 .debug_rnglists 00000c68  00000000  00000000  0001deb0  2**0
+ 15 .debug_aranges 00000f48  00000000  00000000  00030fc8  2**3
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 16 .debug_macro  00014817  00000000  00000000  0001eb18  2**0
+ 16 .debug_rnglists 000013d0  00000000  00000000  00031f10  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 17 .debug_line   000126c2  00000000  00000000  0003332f  2**0
+ 17 .debug_macro  00015b92  00000000  00000000  000332e0  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 18 .debug_str    00084920  00000000  00000000  000459f1  2**0
+ 18 .debug_line   0001a310  00000000  00000000  00048e72  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 19 .comment      00000043  00000000  00000000  000ca311  2**0
+ 19 .debug_str    0008ebf3  00000000  00000000  00063182  2**0
+                  CONTENTS, READONLY, DEBUGGING, OCTETS
+ 20 .comment      00000043  00000000  00000000  000f1d75  2**0
                   CONTENTS, READONLY
- 20 .debug_frame  000038f8  00000000  00000000  000ca354  2**2
+ 21 .debug_frame  00002bb0  00000000  00000000  000f1db8  2**2
                   CONTENTS, READONLY, DEBUGGING, OCTETS
- 21 .debug_line_str 0000004d  00000000  00000000  000cdc4c  2**0
+ 22 .debug_line_str 0000004d  00000000  00000000  000f4968  2**0
                   CONTENTS, READONLY, DEBUGGING, OCTETS
 
 Disassembly of section .text:
@@ -67,7 +69,7 @@ Disassembly of section .text:
  80000da:	bd10      	pop	{r4, pc}
  80000dc:	20000030 	.word	0x20000030
  80000e0:	00000000 	.word	0x00000000
- 80000e4:	08007d20 	.word	0x08007d20
+ 80000e4:	080051f8 	.word	0x080051f8
 
 080000e8 <frame_dummy>:
  80000e8:	4b04      	ldr	r3, [pc, #16]	@ (80000fc <frame_dummy+0x14>)
@@ -82,21764 +84,14385 @@ Disassembly of section .text:
  80000fa:	46c0      	nop			@ (mov r8, r8)
  80000fc:	00000000 	.word	0x00000000
  8000100:	20000034 	.word	0x20000034
- 8000104:	08007d20 	.word	0x08007d20
+ 8000104:	080051f8 	.word	0x080051f8
 
-08000108 <__udivsi3>:
- 8000108:	2200      	movs	r2, #0
- 800010a:	0843      	lsrs	r3, r0, #1
- 800010c:	428b      	cmp	r3, r1
- 800010e:	d374      	bcc.n	80001fa <__udivsi3+0xf2>
- 8000110:	0903      	lsrs	r3, r0, #4
- 8000112:	428b      	cmp	r3, r1
- 8000114:	d35f      	bcc.n	80001d6 <__udivsi3+0xce>
- 8000116:	0a03      	lsrs	r3, r0, #8
- 8000118:	428b      	cmp	r3, r1
- 800011a:	d344      	bcc.n	80001a6 <__udivsi3+0x9e>
- 800011c:	0b03      	lsrs	r3, r0, #12
- 800011e:	428b      	cmp	r3, r1
- 8000120:	d328      	bcc.n	8000174 <__udivsi3+0x6c>
- 8000122:	0c03      	lsrs	r3, r0, #16
- 8000124:	428b      	cmp	r3, r1
- 8000126:	d30d      	bcc.n	8000144 <__udivsi3+0x3c>
- 8000128:	22ff      	movs	r2, #255	@ 0xff
- 800012a:	0209      	lsls	r1, r1, #8
- 800012c:	ba12      	rev	r2, r2
- 800012e:	0c03      	lsrs	r3, r0, #16
- 8000130:	428b      	cmp	r3, r1
- 8000132:	d302      	bcc.n	800013a <__udivsi3+0x32>
- 8000134:	1212      	asrs	r2, r2, #8
- 8000136:	0209      	lsls	r1, r1, #8
- 8000138:	d065      	beq.n	8000206 <__udivsi3+0xfe>
- 800013a:	0b03      	lsrs	r3, r0, #12
- 800013c:	428b      	cmp	r3, r1
- 800013e:	d319      	bcc.n	8000174 <__udivsi3+0x6c>
- 8000140:	e000      	b.n	8000144 <__udivsi3+0x3c>
- 8000142:	0a09      	lsrs	r1, r1, #8
- 8000144:	0bc3      	lsrs	r3, r0, #15
+08000108 <__gnu_thumb1_case_uqi>:
+ 8000108:	b402      	push	{r1}
+ 800010a:	4671      	mov	r1, lr
+ 800010c:	0849      	lsrs	r1, r1, #1
+ 800010e:	0049      	lsls	r1, r1, #1
+ 8000110:	5c09      	ldrb	r1, [r1, r0]
+ 8000112:	0049      	lsls	r1, r1, #1
+ 8000114:	448e      	add	lr, r1
+ 8000116:	bc02      	pop	{r1}
+ 8000118:	4770      	bx	lr
+ 800011a:	46c0      	nop			@ (mov r8, r8)
+
+0800011c <__gnu_thumb1_case_uhi>:
+ 800011c:	b403      	push	{r0, r1}
+ 800011e:	4671      	mov	r1, lr
+ 8000120:	0849      	lsrs	r1, r1, #1
+ 8000122:	0040      	lsls	r0, r0, #1
+ 8000124:	0049      	lsls	r1, r1, #1
+ 8000126:	5a09      	ldrh	r1, [r1, r0]
+ 8000128:	0049      	lsls	r1, r1, #1
+ 800012a:	448e      	add	lr, r1
+ 800012c:	bc03      	pop	{r0, r1}
+ 800012e:	4770      	bx	lr
+
+08000130 <__udivsi3>:
+ 8000130:	2200      	movs	r2, #0
+ 8000132:	0843      	lsrs	r3, r0, #1
+ 8000134:	428b      	cmp	r3, r1
+ 8000136:	d374      	bcc.n	8000222 <__udivsi3+0xf2>
+ 8000138:	0903      	lsrs	r3, r0, #4
+ 800013a:	428b      	cmp	r3, r1
+ 800013c:	d35f      	bcc.n	80001fe <__udivsi3+0xce>
+ 800013e:	0a03      	lsrs	r3, r0, #8
+ 8000140:	428b      	cmp	r3, r1
+ 8000142:	d344      	bcc.n	80001ce <__udivsi3+0x9e>
+ 8000144:	0b03      	lsrs	r3, r0, #12
  8000146:	428b      	cmp	r3, r1
- 8000148:	d301      	bcc.n	800014e <__udivsi3+0x46>
- 800014a:	03cb      	lsls	r3, r1, #15
- 800014c:	1ac0      	subs	r0, r0, r3
- 800014e:	4152      	adcs	r2, r2
- 8000150:	0b83      	lsrs	r3, r0, #14
- 8000152:	428b      	cmp	r3, r1
- 8000154:	d301      	bcc.n	800015a <__udivsi3+0x52>
- 8000156:	038b      	lsls	r3, r1, #14
- 8000158:	1ac0      	subs	r0, r0, r3
- 800015a:	4152      	adcs	r2, r2
- 800015c:	0b43      	lsrs	r3, r0, #13
- 800015e:	428b      	cmp	r3, r1
- 8000160:	d301      	bcc.n	8000166 <__udivsi3+0x5e>
- 8000162:	034b      	lsls	r3, r1, #13
- 8000164:	1ac0      	subs	r0, r0, r3
- 8000166:	4152      	adcs	r2, r2
- 8000168:	0b03      	lsrs	r3, r0, #12
- 800016a:	428b      	cmp	r3, r1
- 800016c:	d301      	bcc.n	8000172 <__udivsi3+0x6a>
- 800016e:	030b      	lsls	r3, r1, #12
- 8000170:	1ac0      	subs	r0, r0, r3
- 8000172:	4152      	adcs	r2, r2
- 8000174:	0ac3      	lsrs	r3, r0, #11
- 8000176:	428b      	cmp	r3, r1
- 8000178:	d301      	bcc.n	800017e <__udivsi3+0x76>
- 800017a:	02cb      	lsls	r3, r1, #11
- 800017c:	1ac0      	subs	r0, r0, r3
- 800017e:	4152      	adcs	r2, r2
- 8000180:	0a83      	lsrs	r3, r0, #10
- 8000182:	428b      	cmp	r3, r1
- 8000184:	d301      	bcc.n	800018a <__udivsi3+0x82>
- 8000186:	028b      	lsls	r3, r1, #10
- 8000188:	1ac0      	subs	r0, r0, r3
- 800018a:	4152      	adcs	r2, r2
- 800018c:	0a43      	lsrs	r3, r0, #9
- 800018e:	428b      	cmp	r3, r1
- 8000190:	d301      	bcc.n	8000196 <__udivsi3+0x8e>
- 8000192:	024b      	lsls	r3, r1, #9
- 8000194:	1ac0      	subs	r0, r0, r3
- 8000196:	4152      	adcs	r2, r2
- 8000198:	0a03      	lsrs	r3, r0, #8
- 800019a:	428b      	cmp	r3, r1
- 800019c:	d301      	bcc.n	80001a2 <__udivsi3+0x9a>
- 800019e:	020b      	lsls	r3, r1, #8
- 80001a0:	1ac0      	subs	r0, r0, r3
- 80001a2:	4152      	adcs	r2, r2
- 80001a4:	d2cd      	bcs.n	8000142 <__udivsi3+0x3a>
- 80001a6:	09c3      	lsrs	r3, r0, #7
- 80001a8:	428b      	cmp	r3, r1
- 80001aa:	d301      	bcc.n	80001b0 <__udivsi3+0xa8>
- 80001ac:	01cb      	lsls	r3, r1, #7
- 80001ae:	1ac0      	subs	r0, r0, r3
- 80001b0:	4152      	adcs	r2, r2
- 80001b2:	0983      	lsrs	r3, r0, #6
- 80001b4:	428b      	cmp	r3, r1
- 80001b6:	d301      	bcc.n	80001bc <__udivsi3+0xb4>
- 80001b8:	018b      	lsls	r3, r1, #6
- 80001ba:	1ac0      	subs	r0, r0, r3
- 80001bc:	4152      	adcs	r2, r2
- 80001be:	0943      	lsrs	r3, r0, #5
- 80001c0:	428b      	cmp	r3, r1
- 80001c2:	d301      	bcc.n	80001c8 <__udivsi3+0xc0>
- 80001c4:	014b      	lsls	r3, r1, #5
- 80001c6:	1ac0      	subs	r0, r0, r3
- 80001c8:	4152      	adcs	r2, r2
- 80001ca:	0903      	lsrs	r3, r0, #4
- 80001cc:	428b      	cmp	r3, r1
- 80001ce:	d301      	bcc.n	80001d4 <__udivsi3+0xcc>
- 80001d0:	010b      	lsls	r3, r1, #4
- 80001d2:	1ac0      	subs	r0, r0, r3
- 80001d4:	4152      	adcs	r2, r2
- 80001d6:	08c3      	lsrs	r3, r0, #3
- 80001d8:	428b      	cmp	r3, r1
- 80001da:	d301      	bcc.n	80001e0 <__udivsi3+0xd8>
- 80001dc:	00cb      	lsls	r3, r1, #3
- 80001de:	1ac0      	subs	r0, r0, r3
- 80001e0:	4152      	adcs	r2, r2
- 80001e2:	0883      	lsrs	r3, r0, #2
- 80001e4:	428b      	cmp	r3, r1
- 80001e6:	d301      	bcc.n	80001ec <__udivsi3+0xe4>
- 80001e8:	008b      	lsls	r3, r1, #2
- 80001ea:	1ac0      	subs	r0, r0, r3
- 80001ec:	4152      	adcs	r2, r2
- 80001ee:	0843      	lsrs	r3, r0, #1
- 80001f0:	428b      	cmp	r3, r1
- 80001f2:	d301      	bcc.n	80001f8 <__udivsi3+0xf0>
- 80001f4:	004b      	lsls	r3, r1, #1
- 80001f6:	1ac0      	subs	r0, r0, r3
- 80001f8:	4152      	adcs	r2, r2
- 80001fa:	1a41      	subs	r1, r0, r1
- 80001fc:	d200      	bcs.n	8000200 <__udivsi3+0xf8>
- 80001fe:	4601      	mov	r1, r0
- 8000200:	4152      	adcs	r2, r2
- 8000202:	4610      	mov	r0, r2
- 8000204:	4770      	bx	lr
- 8000206:	e7ff      	b.n	8000208 <__udivsi3+0x100>
- 8000208:	b501      	push	{r0, lr}
- 800020a:	2000      	movs	r0, #0
- 800020c:	f000 f8f0 	bl	80003f0 <__aeabi_idiv0>
- 8000210:	bd02      	pop	{r1, pc}
- 8000212:	46c0      	nop			@ (mov r8, r8)
+ 8000148:	d328      	bcc.n	800019c <__udivsi3+0x6c>
+ 800014a:	0c03      	lsrs	r3, r0, #16
+ 800014c:	428b      	cmp	r3, r1
+ 800014e:	d30d      	bcc.n	800016c <__udivsi3+0x3c>
+ 8000150:	22ff      	movs	r2, #255	@ 0xff
+ 8000152:	0209      	lsls	r1, r1, #8
+ 8000154:	ba12      	rev	r2, r2
+ 8000156:	0c03      	lsrs	r3, r0, #16
+ 8000158:	428b      	cmp	r3, r1
+ 800015a:	d302      	bcc.n	8000162 <__udivsi3+0x32>
+ 800015c:	1212      	asrs	r2, r2, #8
+ 800015e:	0209      	lsls	r1, r1, #8
+ 8000160:	d065      	beq.n	800022e <__udivsi3+0xfe>
+ 8000162:	0b03      	lsrs	r3, r0, #12
+ 8000164:	428b      	cmp	r3, r1
+ 8000166:	d319      	bcc.n	800019c <__udivsi3+0x6c>
+ 8000168:	e000      	b.n	800016c <__udivsi3+0x3c>
+ 800016a:	0a09      	lsrs	r1, r1, #8
+ 800016c:	0bc3      	lsrs	r3, r0, #15
+ 800016e:	428b      	cmp	r3, r1
+ 8000170:	d301      	bcc.n	8000176 <__udivsi3+0x46>
+ 8000172:	03cb      	lsls	r3, r1, #15
+ 8000174:	1ac0      	subs	r0, r0, r3
+ 8000176:	4152      	adcs	r2, r2
+ 8000178:	0b83      	lsrs	r3, r0, #14
+ 800017a:	428b      	cmp	r3, r1
+ 800017c:	d301      	bcc.n	8000182 <__udivsi3+0x52>
+ 800017e:	038b      	lsls	r3, r1, #14
+ 8000180:	1ac0      	subs	r0, r0, r3
+ 8000182:	4152      	adcs	r2, r2
+ 8000184:	0b43      	lsrs	r3, r0, #13
+ 8000186:	428b      	cmp	r3, r1
+ 8000188:	d301      	bcc.n	800018e <__udivsi3+0x5e>
+ 800018a:	034b      	lsls	r3, r1, #13
+ 800018c:	1ac0      	subs	r0, r0, r3
+ 800018e:	4152      	adcs	r2, r2
+ 8000190:	0b03      	lsrs	r3, r0, #12
+ 8000192:	428b      	cmp	r3, r1
+ 8000194:	d301      	bcc.n	800019a <__udivsi3+0x6a>
+ 8000196:	030b      	lsls	r3, r1, #12
+ 8000198:	1ac0      	subs	r0, r0, r3
+ 800019a:	4152      	adcs	r2, r2
+ 800019c:	0ac3      	lsrs	r3, r0, #11
+ 800019e:	428b      	cmp	r3, r1
+ 80001a0:	d301      	bcc.n	80001a6 <__udivsi3+0x76>
+ 80001a2:	02cb      	lsls	r3, r1, #11
+ 80001a4:	1ac0      	subs	r0, r0, r3
+ 80001a6:	4152      	adcs	r2, r2
+ 80001a8:	0a83      	lsrs	r3, r0, #10
+ 80001aa:	428b      	cmp	r3, r1
+ 80001ac:	d301      	bcc.n	80001b2 <__udivsi3+0x82>
+ 80001ae:	028b      	lsls	r3, r1, #10
+ 80001b0:	1ac0      	subs	r0, r0, r3
+ 80001b2:	4152      	adcs	r2, r2
+ 80001b4:	0a43      	lsrs	r3, r0, #9
+ 80001b6:	428b      	cmp	r3, r1
+ 80001b8:	d301      	bcc.n	80001be <__udivsi3+0x8e>
+ 80001ba:	024b      	lsls	r3, r1, #9
+ 80001bc:	1ac0      	subs	r0, r0, r3
+ 80001be:	4152      	adcs	r2, r2
+ 80001c0:	0a03      	lsrs	r3, r0, #8
+ 80001c2:	428b      	cmp	r3, r1
+ 80001c4:	d301      	bcc.n	80001ca <__udivsi3+0x9a>
+ 80001c6:	020b      	lsls	r3, r1, #8
+ 80001c8:	1ac0      	subs	r0, r0, r3
+ 80001ca:	4152      	adcs	r2, r2
+ 80001cc:	d2cd      	bcs.n	800016a <__udivsi3+0x3a>
+ 80001ce:	09c3      	lsrs	r3, r0, #7
+ 80001d0:	428b      	cmp	r3, r1
+ 80001d2:	d301      	bcc.n	80001d8 <__udivsi3+0xa8>
+ 80001d4:	01cb      	lsls	r3, r1, #7
+ 80001d6:	1ac0      	subs	r0, r0, r3
+ 80001d8:	4152      	adcs	r2, r2
+ 80001da:	0983      	lsrs	r3, r0, #6
+ 80001dc:	428b      	cmp	r3, r1
+ 80001de:	d301      	bcc.n	80001e4 <__udivsi3+0xb4>
+ 80001e0:	018b      	lsls	r3, r1, #6
+ 80001e2:	1ac0      	subs	r0, r0, r3
+ 80001e4:	4152      	adcs	r2, r2
+ 80001e6:	0943      	lsrs	r3, r0, #5
+ 80001e8:	428b      	cmp	r3, r1
+ 80001ea:	d301      	bcc.n	80001f0 <__udivsi3+0xc0>
+ 80001ec:	014b      	lsls	r3, r1, #5
+ 80001ee:	1ac0      	subs	r0, r0, r3
+ 80001f0:	4152      	adcs	r2, r2
+ 80001f2:	0903      	lsrs	r3, r0, #4
+ 80001f4:	428b      	cmp	r3, r1
+ 80001f6:	d301      	bcc.n	80001fc <__udivsi3+0xcc>
+ 80001f8:	010b      	lsls	r3, r1, #4
+ 80001fa:	1ac0      	subs	r0, r0, r3
+ 80001fc:	4152      	adcs	r2, r2
+ 80001fe:	08c3      	lsrs	r3, r0, #3
+ 8000200:	428b      	cmp	r3, r1
+ 8000202:	d301      	bcc.n	8000208 <__udivsi3+0xd8>
+ 8000204:	00cb      	lsls	r3, r1, #3
+ 8000206:	1ac0      	subs	r0, r0, r3
+ 8000208:	4152      	adcs	r2, r2
+ 800020a:	0883      	lsrs	r3, r0, #2
+ 800020c:	428b      	cmp	r3, r1
+ 800020e:	d301      	bcc.n	8000214 <__udivsi3+0xe4>
+ 8000210:	008b      	lsls	r3, r1, #2
+ 8000212:	1ac0      	subs	r0, r0, r3
+ 8000214:	4152      	adcs	r2, r2
+ 8000216:	0843      	lsrs	r3, r0, #1
+ 8000218:	428b      	cmp	r3, r1
+ 800021a:	d301      	bcc.n	8000220 <__udivsi3+0xf0>
+ 800021c:	004b      	lsls	r3, r1, #1
+ 800021e:	1ac0      	subs	r0, r0, r3
+ 8000220:	4152      	adcs	r2, r2
+ 8000222:	1a41      	subs	r1, r0, r1
+ 8000224:	d200      	bcs.n	8000228 <__udivsi3+0xf8>
+ 8000226:	4601      	mov	r1, r0
+ 8000228:	4152      	adcs	r2, r2
+ 800022a:	4610      	mov	r0, r2
+ 800022c:	4770      	bx	lr
+ 800022e:	e7ff      	b.n	8000230 <__udivsi3+0x100>
+ 8000230:	b501      	push	{r0, lr}
+ 8000232:	2000      	movs	r0, #0
+ 8000234:	f000 f8f0 	bl	8000418 <__aeabi_idiv0>
+ 8000238:	bd02      	pop	{r1, pc}
+ 800023a:	46c0      	nop			@ (mov r8, r8)
 
-08000214 <__aeabi_uidivmod>:
- 8000214:	2900      	cmp	r1, #0
- 8000216:	d0f7      	beq.n	8000208 <__udivsi3+0x100>
- 8000218:	e776      	b.n	8000108 <__udivsi3>
- 800021a:	4770      	bx	lr
+0800023c <__aeabi_uidivmod>:
+ 800023c:	2900      	cmp	r1, #0
+ 800023e:	d0f7      	beq.n	8000230 <__udivsi3+0x100>
+ 8000240:	e776      	b.n	8000130 <__udivsi3>
+ 8000242:	4770      	bx	lr
 
-0800021c <__divsi3>:
- 800021c:	4603      	mov	r3, r0
- 800021e:	430b      	orrs	r3, r1
- 8000220:	d47f      	bmi.n	8000322 <__divsi3+0x106>
- 8000222:	2200      	movs	r2, #0
- 8000224:	0843      	lsrs	r3, r0, #1
- 8000226:	428b      	cmp	r3, r1
- 8000228:	d374      	bcc.n	8000314 <__divsi3+0xf8>
- 800022a:	0903      	lsrs	r3, r0, #4
- 800022c:	428b      	cmp	r3, r1
- 800022e:	d35f      	bcc.n	80002f0 <__divsi3+0xd4>
- 8000230:	0a03      	lsrs	r3, r0, #8
- 8000232:	428b      	cmp	r3, r1
- 8000234:	d344      	bcc.n	80002c0 <__divsi3+0xa4>
- 8000236:	0b03      	lsrs	r3, r0, #12
- 8000238:	428b      	cmp	r3, r1
- 800023a:	d328      	bcc.n	800028e <__divsi3+0x72>
- 800023c:	0c03      	lsrs	r3, r0, #16
- 800023e:	428b      	cmp	r3, r1
- 8000240:	d30d      	bcc.n	800025e <__divsi3+0x42>
- 8000242:	22ff      	movs	r2, #255	@ 0xff
- 8000244:	0209      	lsls	r1, r1, #8
- 8000246:	ba12      	rev	r2, r2
- 8000248:	0c03      	lsrs	r3, r0, #16
- 800024a:	428b      	cmp	r3, r1
- 800024c:	d302      	bcc.n	8000254 <__divsi3+0x38>
- 800024e:	1212      	asrs	r2, r2, #8
- 8000250:	0209      	lsls	r1, r1, #8
- 8000252:	d065      	beq.n	8000320 <__divsi3+0x104>
- 8000254:	0b03      	lsrs	r3, r0, #12
- 8000256:	428b      	cmp	r3, r1
- 8000258:	d319      	bcc.n	800028e <__divsi3+0x72>
- 800025a:	e000      	b.n	800025e <__divsi3+0x42>
- 800025c:	0a09      	lsrs	r1, r1, #8
- 800025e:	0bc3      	lsrs	r3, r0, #15
+08000244 <__divsi3>:
+ 8000244:	4603      	mov	r3, r0
+ 8000246:	430b      	orrs	r3, r1
+ 8000248:	d47f      	bmi.n	800034a <__divsi3+0x106>
+ 800024a:	2200      	movs	r2, #0
+ 800024c:	0843      	lsrs	r3, r0, #1
+ 800024e:	428b      	cmp	r3, r1
+ 8000250:	d374      	bcc.n	800033c <__divsi3+0xf8>
+ 8000252:	0903      	lsrs	r3, r0, #4
+ 8000254:	428b      	cmp	r3, r1
+ 8000256:	d35f      	bcc.n	8000318 <__divsi3+0xd4>
+ 8000258:	0a03      	lsrs	r3, r0, #8
+ 800025a:	428b      	cmp	r3, r1
+ 800025c:	d344      	bcc.n	80002e8 <__divsi3+0xa4>
+ 800025e:	0b03      	lsrs	r3, r0, #12
  8000260:	428b      	cmp	r3, r1
- 8000262:	d301      	bcc.n	8000268 <__divsi3+0x4c>
- 8000264:	03cb      	lsls	r3, r1, #15
- 8000266:	1ac0      	subs	r0, r0, r3
- 8000268:	4152      	adcs	r2, r2
- 800026a:	0b83      	lsrs	r3, r0, #14
- 800026c:	428b      	cmp	r3, r1
- 800026e:	d301      	bcc.n	8000274 <__divsi3+0x58>
- 8000270:	038b      	lsls	r3, r1, #14
- 8000272:	1ac0      	subs	r0, r0, r3
- 8000274:	4152      	adcs	r2, r2
- 8000276:	0b43      	lsrs	r3, r0, #13
- 8000278:	428b      	cmp	r3, r1
- 800027a:	d301      	bcc.n	8000280 <__divsi3+0x64>
- 800027c:	034b      	lsls	r3, r1, #13
- 800027e:	1ac0      	subs	r0, r0, r3
- 8000280:	4152      	adcs	r2, r2
- 8000282:	0b03      	lsrs	r3, r0, #12
- 8000284:	428b      	cmp	r3, r1
- 8000286:	d301      	bcc.n	800028c <__divsi3+0x70>
- 8000288:	030b      	lsls	r3, r1, #12
- 800028a:	1ac0      	subs	r0, r0, r3
- 800028c:	4152      	adcs	r2, r2
- 800028e:	0ac3      	lsrs	r3, r0, #11
- 8000290:	428b      	cmp	r3, r1
- 8000292:	d301      	bcc.n	8000298 <__divsi3+0x7c>
- 8000294:	02cb      	lsls	r3, r1, #11
- 8000296:	1ac0      	subs	r0, r0, r3
- 8000298:	4152      	adcs	r2, r2
- 800029a:	0a83      	lsrs	r3, r0, #10
- 800029c:	428b      	cmp	r3, r1
- 800029e:	d301      	bcc.n	80002a4 <__divsi3+0x88>
- 80002a0:	028b      	lsls	r3, r1, #10
- 80002a2:	1ac0      	subs	r0, r0, r3
- 80002a4:	4152      	adcs	r2, r2
- 80002a6:	0a43      	lsrs	r3, r0, #9
- 80002a8:	428b      	cmp	r3, r1
- 80002aa:	d301      	bcc.n	80002b0 <__divsi3+0x94>
- 80002ac:	024b      	lsls	r3, r1, #9
- 80002ae:	1ac0      	subs	r0, r0, r3
- 80002b0:	4152      	adcs	r2, r2
- 80002b2:	0a03      	lsrs	r3, r0, #8
- 80002b4:	428b      	cmp	r3, r1
- 80002b6:	d301      	bcc.n	80002bc <__divsi3+0xa0>
- 80002b8:	020b      	lsls	r3, r1, #8
- 80002ba:	1ac0      	subs	r0, r0, r3
- 80002bc:	4152      	adcs	r2, r2
- 80002be:	d2cd      	bcs.n	800025c <__divsi3+0x40>
- 80002c0:	09c3      	lsrs	r3, r0, #7
- 80002c2:	428b      	cmp	r3, r1
- 80002c4:	d301      	bcc.n	80002ca <__divsi3+0xae>
- 80002c6:	01cb      	lsls	r3, r1, #7
- 80002c8:	1ac0      	subs	r0, r0, r3
- 80002ca:	4152      	adcs	r2, r2
- 80002cc:	0983      	lsrs	r3, r0, #6
- 80002ce:	428b      	cmp	r3, r1
- 80002d0:	d301      	bcc.n	80002d6 <__divsi3+0xba>
- 80002d2:	018b      	lsls	r3, r1, #6
- 80002d4:	1ac0      	subs	r0, r0, r3
- 80002d6:	4152      	adcs	r2, r2
- 80002d8:	0943      	lsrs	r3, r0, #5
- 80002da:	428b      	cmp	r3, r1
- 80002dc:	d301      	bcc.n	80002e2 <__divsi3+0xc6>
- 80002de:	014b      	lsls	r3, r1, #5
- 80002e0:	1ac0      	subs	r0, r0, r3
- 80002e2:	4152      	adcs	r2, r2
- 80002e4:	0903      	lsrs	r3, r0, #4
- 80002e6:	428b      	cmp	r3, r1
- 80002e8:	d301      	bcc.n	80002ee <__divsi3+0xd2>
- 80002ea:	010b      	lsls	r3, r1, #4
- 80002ec:	1ac0      	subs	r0, r0, r3
- 80002ee:	4152      	adcs	r2, r2
- 80002f0:	08c3      	lsrs	r3, r0, #3
- 80002f2:	428b      	cmp	r3, r1
- 80002f4:	d301      	bcc.n	80002fa <__divsi3+0xde>
- 80002f6:	00cb      	lsls	r3, r1, #3
- 80002f8:	1ac0      	subs	r0, r0, r3
- 80002fa:	4152      	adcs	r2, r2
- 80002fc:	0883      	lsrs	r3, r0, #2
- 80002fe:	428b      	cmp	r3, r1
- 8000300:	d301      	bcc.n	8000306 <__divsi3+0xea>
- 8000302:	008b      	lsls	r3, r1, #2
- 8000304:	1ac0      	subs	r0, r0, r3
- 8000306:	4152      	adcs	r2, r2
- 8000308:	0843      	lsrs	r3, r0, #1
- 800030a:	428b      	cmp	r3, r1
- 800030c:	d301      	bcc.n	8000312 <__divsi3+0xf6>
- 800030e:	004b      	lsls	r3, r1, #1
- 8000310:	1ac0      	subs	r0, r0, r3
- 8000312:	4152      	adcs	r2, r2
- 8000314:	1a41      	subs	r1, r0, r1
- 8000316:	d200      	bcs.n	800031a <__divsi3+0xfe>
- 8000318:	4601      	mov	r1, r0
- 800031a:	4152      	adcs	r2, r2
- 800031c:	4610      	mov	r0, r2
- 800031e:	4770      	bx	lr
- 8000320:	e05d      	b.n	80003de <__divsi3+0x1c2>
- 8000322:	0fca      	lsrs	r2, r1, #31
- 8000324:	d000      	beq.n	8000328 <__divsi3+0x10c>
- 8000326:	4249      	negs	r1, r1
- 8000328:	1003      	asrs	r3, r0, #32
- 800032a:	d300      	bcc.n	800032e <__divsi3+0x112>
- 800032c:	4240      	negs	r0, r0
- 800032e:	4053      	eors	r3, r2
- 8000330:	2200      	movs	r2, #0
- 8000332:	469c      	mov	ip, r3
- 8000334:	0903      	lsrs	r3, r0, #4
- 8000336:	428b      	cmp	r3, r1
- 8000338:	d32d      	bcc.n	8000396 <__divsi3+0x17a>
- 800033a:	0a03      	lsrs	r3, r0, #8
- 800033c:	428b      	cmp	r3, r1
- 800033e:	d312      	bcc.n	8000366 <__divsi3+0x14a>
- 8000340:	22fc      	movs	r2, #252	@ 0xfc
- 8000342:	0189      	lsls	r1, r1, #6
- 8000344:	ba12      	rev	r2, r2
- 8000346:	0a03      	lsrs	r3, r0, #8
- 8000348:	428b      	cmp	r3, r1
- 800034a:	d30c      	bcc.n	8000366 <__divsi3+0x14a>
- 800034c:	0189      	lsls	r1, r1, #6
- 800034e:	1192      	asrs	r2, r2, #6
- 8000350:	428b      	cmp	r3, r1
- 8000352:	d308      	bcc.n	8000366 <__divsi3+0x14a>
- 8000354:	0189      	lsls	r1, r1, #6
- 8000356:	1192      	asrs	r2, r2, #6
- 8000358:	428b      	cmp	r3, r1
- 800035a:	d304      	bcc.n	8000366 <__divsi3+0x14a>
- 800035c:	0189      	lsls	r1, r1, #6
- 800035e:	d03a      	beq.n	80003d6 <__divsi3+0x1ba>
- 8000360:	1192      	asrs	r2, r2, #6
- 8000362:	e000      	b.n	8000366 <__divsi3+0x14a>
- 8000364:	0989      	lsrs	r1, r1, #6
- 8000366:	09c3      	lsrs	r3, r0, #7
- 8000368:	428b      	cmp	r3, r1
- 800036a:	d301      	bcc.n	8000370 <__divsi3+0x154>
- 800036c:	01cb      	lsls	r3, r1, #7
- 800036e:	1ac0      	subs	r0, r0, r3
- 8000370:	4152      	adcs	r2, r2
- 8000372:	0983      	lsrs	r3, r0, #6
- 8000374:	428b      	cmp	r3, r1
- 8000376:	d301      	bcc.n	800037c <__divsi3+0x160>
- 8000378:	018b      	lsls	r3, r1, #6
- 800037a:	1ac0      	subs	r0, r0, r3
- 800037c:	4152      	adcs	r2, r2
- 800037e:	0943      	lsrs	r3, r0, #5
+ 8000262:	d328      	bcc.n	80002b6 <__divsi3+0x72>
+ 8000264:	0c03      	lsrs	r3, r0, #16
+ 8000266:	428b      	cmp	r3, r1
+ 8000268:	d30d      	bcc.n	8000286 <__divsi3+0x42>
+ 800026a:	22ff      	movs	r2, #255	@ 0xff
+ 800026c:	0209      	lsls	r1, r1, #8
+ 800026e:	ba12      	rev	r2, r2
+ 8000270:	0c03      	lsrs	r3, r0, #16
+ 8000272:	428b      	cmp	r3, r1
+ 8000274:	d302      	bcc.n	800027c <__divsi3+0x38>
+ 8000276:	1212      	asrs	r2, r2, #8
+ 8000278:	0209      	lsls	r1, r1, #8
+ 800027a:	d065      	beq.n	8000348 <__divsi3+0x104>
+ 800027c:	0b03      	lsrs	r3, r0, #12
+ 800027e:	428b      	cmp	r3, r1
+ 8000280:	d319      	bcc.n	80002b6 <__divsi3+0x72>
+ 8000282:	e000      	b.n	8000286 <__divsi3+0x42>
+ 8000284:	0a09      	lsrs	r1, r1, #8
+ 8000286:	0bc3      	lsrs	r3, r0, #15
+ 8000288:	428b      	cmp	r3, r1
+ 800028a:	d301      	bcc.n	8000290 <__divsi3+0x4c>
+ 800028c:	03cb      	lsls	r3, r1, #15
+ 800028e:	1ac0      	subs	r0, r0, r3
+ 8000290:	4152      	adcs	r2, r2
+ 8000292:	0b83      	lsrs	r3, r0, #14
+ 8000294:	428b      	cmp	r3, r1
+ 8000296:	d301      	bcc.n	800029c <__divsi3+0x58>
+ 8000298:	038b      	lsls	r3, r1, #14
+ 800029a:	1ac0      	subs	r0, r0, r3
+ 800029c:	4152      	adcs	r2, r2
+ 800029e:	0b43      	lsrs	r3, r0, #13
+ 80002a0:	428b      	cmp	r3, r1
+ 80002a2:	d301      	bcc.n	80002a8 <__divsi3+0x64>
+ 80002a4:	034b      	lsls	r3, r1, #13
+ 80002a6:	1ac0      	subs	r0, r0, r3
+ 80002a8:	4152      	adcs	r2, r2
+ 80002aa:	0b03      	lsrs	r3, r0, #12
+ 80002ac:	428b      	cmp	r3, r1
+ 80002ae:	d301      	bcc.n	80002b4 <__divsi3+0x70>
+ 80002b0:	030b      	lsls	r3, r1, #12
+ 80002b2:	1ac0      	subs	r0, r0, r3
+ 80002b4:	4152      	adcs	r2, r2
+ 80002b6:	0ac3      	lsrs	r3, r0, #11
+ 80002b8:	428b      	cmp	r3, r1
+ 80002ba:	d301      	bcc.n	80002c0 <__divsi3+0x7c>
+ 80002bc:	02cb      	lsls	r3, r1, #11
+ 80002be:	1ac0      	subs	r0, r0, r3
+ 80002c0:	4152      	adcs	r2, r2
+ 80002c2:	0a83      	lsrs	r3, r0, #10
+ 80002c4:	428b      	cmp	r3, r1
+ 80002c6:	d301      	bcc.n	80002cc <__divsi3+0x88>
+ 80002c8:	028b      	lsls	r3, r1, #10
+ 80002ca:	1ac0      	subs	r0, r0, r3
+ 80002cc:	4152      	adcs	r2, r2
+ 80002ce:	0a43      	lsrs	r3, r0, #9
+ 80002d0:	428b      	cmp	r3, r1
+ 80002d2:	d301      	bcc.n	80002d8 <__divsi3+0x94>
+ 80002d4:	024b      	lsls	r3, r1, #9
+ 80002d6:	1ac0      	subs	r0, r0, r3
+ 80002d8:	4152      	adcs	r2, r2
+ 80002da:	0a03      	lsrs	r3, r0, #8
+ 80002dc:	428b      	cmp	r3, r1
+ 80002de:	d301      	bcc.n	80002e4 <__divsi3+0xa0>
+ 80002e0:	020b      	lsls	r3, r1, #8
+ 80002e2:	1ac0      	subs	r0, r0, r3
+ 80002e4:	4152      	adcs	r2, r2
+ 80002e6:	d2cd      	bcs.n	8000284 <__divsi3+0x40>
+ 80002e8:	09c3      	lsrs	r3, r0, #7
+ 80002ea:	428b      	cmp	r3, r1
+ 80002ec:	d301      	bcc.n	80002f2 <__divsi3+0xae>
+ 80002ee:	01cb      	lsls	r3, r1, #7
+ 80002f0:	1ac0      	subs	r0, r0, r3
+ 80002f2:	4152      	adcs	r2, r2
+ 80002f4:	0983      	lsrs	r3, r0, #6
+ 80002f6:	428b      	cmp	r3, r1
+ 80002f8:	d301      	bcc.n	80002fe <__divsi3+0xba>
+ 80002fa:	018b      	lsls	r3, r1, #6
+ 80002fc:	1ac0      	subs	r0, r0, r3
+ 80002fe:	4152      	adcs	r2, r2
+ 8000300:	0943      	lsrs	r3, r0, #5
+ 8000302:	428b      	cmp	r3, r1
+ 8000304:	d301      	bcc.n	800030a <__divsi3+0xc6>
+ 8000306:	014b      	lsls	r3, r1, #5
+ 8000308:	1ac0      	subs	r0, r0, r3
+ 800030a:	4152      	adcs	r2, r2
+ 800030c:	0903      	lsrs	r3, r0, #4
+ 800030e:	428b      	cmp	r3, r1
+ 8000310:	d301      	bcc.n	8000316 <__divsi3+0xd2>
+ 8000312:	010b      	lsls	r3, r1, #4
+ 8000314:	1ac0      	subs	r0, r0, r3
+ 8000316:	4152      	adcs	r2, r2
+ 8000318:	08c3      	lsrs	r3, r0, #3
+ 800031a:	428b      	cmp	r3, r1
+ 800031c:	d301      	bcc.n	8000322 <__divsi3+0xde>
+ 800031e:	00cb      	lsls	r3, r1, #3
+ 8000320:	1ac0      	subs	r0, r0, r3
+ 8000322:	4152      	adcs	r2, r2
+ 8000324:	0883      	lsrs	r3, r0, #2
+ 8000326:	428b      	cmp	r3, r1
+ 8000328:	d301      	bcc.n	800032e <__divsi3+0xea>
+ 800032a:	008b      	lsls	r3, r1, #2
+ 800032c:	1ac0      	subs	r0, r0, r3
+ 800032e:	4152      	adcs	r2, r2
+ 8000330:	0843      	lsrs	r3, r0, #1
+ 8000332:	428b      	cmp	r3, r1
+ 8000334:	d301      	bcc.n	800033a <__divsi3+0xf6>
+ 8000336:	004b      	lsls	r3, r1, #1
+ 8000338:	1ac0      	subs	r0, r0, r3
+ 800033a:	4152      	adcs	r2, r2
+ 800033c:	1a41      	subs	r1, r0, r1
+ 800033e:	d200      	bcs.n	8000342 <__divsi3+0xfe>
+ 8000340:	4601      	mov	r1, r0
+ 8000342:	4152      	adcs	r2, r2
+ 8000344:	4610      	mov	r0, r2
+ 8000346:	4770      	bx	lr
+ 8000348:	e05d      	b.n	8000406 <__divsi3+0x1c2>
+ 800034a:	0fca      	lsrs	r2, r1, #31
+ 800034c:	d000      	beq.n	8000350 <__divsi3+0x10c>
+ 800034e:	4249      	negs	r1, r1
+ 8000350:	1003      	asrs	r3, r0, #32
+ 8000352:	d300      	bcc.n	8000356 <__divsi3+0x112>
+ 8000354:	4240      	negs	r0, r0
+ 8000356:	4053      	eors	r3, r2
+ 8000358:	2200      	movs	r2, #0
+ 800035a:	469c      	mov	ip, r3
+ 800035c:	0903      	lsrs	r3, r0, #4
+ 800035e:	428b      	cmp	r3, r1
+ 8000360:	d32d      	bcc.n	80003be <__divsi3+0x17a>
+ 8000362:	0a03      	lsrs	r3, r0, #8
+ 8000364:	428b      	cmp	r3, r1
+ 8000366:	d312      	bcc.n	800038e <__divsi3+0x14a>
+ 8000368:	22fc      	movs	r2, #252	@ 0xfc
+ 800036a:	0189      	lsls	r1, r1, #6
+ 800036c:	ba12      	rev	r2, r2
+ 800036e:	0a03      	lsrs	r3, r0, #8
+ 8000370:	428b      	cmp	r3, r1
+ 8000372:	d30c      	bcc.n	800038e <__divsi3+0x14a>
+ 8000374:	0189      	lsls	r1, r1, #6
+ 8000376:	1192      	asrs	r2, r2, #6
+ 8000378:	428b      	cmp	r3, r1
+ 800037a:	d308      	bcc.n	800038e <__divsi3+0x14a>
+ 800037c:	0189      	lsls	r1, r1, #6
+ 800037e:	1192      	asrs	r2, r2, #6
  8000380:	428b      	cmp	r3, r1
- 8000382:	d301      	bcc.n	8000388 <__divsi3+0x16c>
- 8000384:	014b      	lsls	r3, r1, #5
- 8000386:	1ac0      	subs	r0, r0, r3
- 8000388:	4152      	adcs	r2, r2
- 800038a:	0903      	lsrs	r3, r0, #4
- 800038c:	428b      	cmp	r3, r1
- 800038e:	d301      	bcc.n	8000394 <__divsi3+0x178>
- 8000390:	010b      	lsls	r3, r1, #4
- 8000392:	1ac0      	subs	r0, r0, r3
- 8000394:	4152      	adcs	r2, r2
- 8000396:	08c3      	lsrs	r3, r0, #3
- 8000398:	428b      	cmp	r3, r1
- 800039a:	d301      	bcc.n	80003a0 <__divsi3+0x184>
- 800039c:	00cb      	lsls	r3, r1, #3
- 800039e:	1ac0      	subs	r0, r0, r3
- 80003a0:	4152      	adcs	r2, r2
- 80003a2:	0883      	lsrs	r3, r0, #2
- 80003a4:	428b      	cmp	r3, r1
- 80003a6:	d301      	bcc.n	80003ac <__divsi3+0x190>
- 80003a8:	008b      	lsls	r3, r1, #2
- 80003aa:	1ac0      	subs	r0, r0, r3
- 80003ac:	4152      	adcs	r2, r2
- 80003ae:	d2d9      	bcs.n	8000364 <__divsi3+0x148>
- 80003b0:	0843      	lsrs	r3, r0, #1
- 80003b2:	428b      	cmp	r3, r1
- 80003b4:	d301      	bcc.n	80003ba <__divsi3+0x19e>
- 80003b6:	004b      	lsls	r3, r1, #1
- 80003b8:	1ac0      	subs	r0, r0, r3
- 80003ba:	4152      	adcs	r2, r2
- 80003bc:	1a41      	subs	r1, r0, r1
- 80003be:	d200      	bcs.n	80003c2 <__divsi3+0x1a6>
- 80003c0:	4601      	mov	r1, r0
- 80003c2:	4663      	mov	r3, ip
- 80003c4:	4152      	adcs	r2, r2
- 80003c6:	105b      	asrs	r3, r3, #1
- 80003c8:	4610      	mov	r0, r2
- 80003ca:	d301      	bcc.n	80003d0 <__divsi3+0x1b4>
- 80003cc:	4240      	negs	r0, r0
- 80003ce:	2b00      	cmp	r3, #0
- 80003d0:	d500      	bpl.n	80003d4 <__divsi3+0x1b8>
- 80003d2:	4249      	negs	r1, r1
- 80003d4:	4770      	bx	lr
- 80003d6:	4663      	mov	r3, ip
- 80003d8:	105b      	asrs	r3, r3, #1
- 80003da:	d300      	bcc.n	80003de <__divsi3+0x1c2>
- 80003dc:	4240      	negs	r0, r0
- 80003de:	b501      	push	{r0, lr}
- 80003e0:	2000      	movs	r0, #0
- 80003e2:	f000 f805 	bl	80003f0 <__aeabi_idiv0>
- 80003e6:	bd02      	pop	{r1, pc}
+ 8000382:	d304      	bcc.n	800038e <__divsi3+0x14a>
+ 8000384:	0189      	lsls	r1, r1, #6
+ 8000386:	d03a      	beq.n	80003fe <__divsi3+0x1ba>
+ 8000388:	1192      	asrs	r2, r2, #6
+ 800038a:	e000      	b.n	800038e <__divsi3+0x14a>
+ 800038c:	0989      	lsrs	r1, r1, #6
+ 800038e:	09c3      	lsrs	r3, r0, #7
+ 8000390:	428b      	cmp	r3, r1
+ 8000392:	d301      	bcc.n	8000398 <__divsi3+0x154>
+ 8000394:	01cb      	lsls	r3, r1, #7
+ 8000396:	1ac0      	subs	r0, r0, r3
+ 8000398:	4152      	adcs	r2, r2
+ 800039a:	0983      	lsrs	r3, r0, #6
+ 800039c:	428b      	cmp	r3, r1
+ 800039e:	d301      	bcc.n	80003a4 <__divsi3+0x160>
+ 80003a0:	018b      	lsls	r3, r1, #6
+ 80003a2:	1ac0      	subs	r0, r0, r3
+ 80003a4:	4152      	adcs	r2, r2
+ 80003a6:	0943      	lsrs	r3, r0, #5
+ 80003a8:	428b      	cmp	r3, r1
+ 80003aa:	d301      	bcc.n	80003b0 <__divsi3+0x16c>
+ 80003ac:	014b      	lsls	r3, r1, #5
+ 80003ae:	1ac0      	subs	r0, r0, r3
+ 80003b0:	4152      	adcs	r2, r2
+ 80003b2:	0903      	lsrs	r3, r0, #4
+ 80003b4:	428b      	cmp	r3, r1
+ 80003b6:	d301      	bcc.n	80003bc <__divsi3+0x178>
+ 80003b8:	010b      	lsls	r3, r1, #4
+ 80003ba:	1ac0      	subs	r0, r0, r3
+ 80003bc:	4152      	adcs	r2, r2
+ 80003be:	08c3      	lsrs	r3, r0, #3
+ 80003c0:	428b      	cmp	r3, r1
+ 80003c2:	d301      	bcc.n	80003c8 <__divsi3+0x184>
+ 80003c4:	00cb      	lsls	r3, r1, #3
+ 80003c6:	1ac0      	subs	r0, r0, r3
+ 80003c8:	4152      	adcs	r2, r2
+ 80003ca:	0883      	lsrs	r3, r0, #2
+ 80003cc:	428b      	cmp	r3, r1
+ 80003ce:	d301      	bcc.n	80003d4 <__divsi3+0x190>
+ 80003d0:	008b      	lsls	r3, r1, #2
+ 80003d2:	1ac0      	subs	r0, r0, r3
+ 80003d4:	4152      	adcs	r2, r2
+ 80003d6:	d2d9      	bcs.n	800038c <__divsi3+0x148>
+ 80003d8:	0843      	lsrs	r3, r0, #1
+ 80003da:	428b      	cmp	r3, r1
+ 80003dc:	d301      	bcc.n	80003e2 <__divsi3+0x19e>
+ 80003de:	004b      	lsls	r3, r1, #1
+ 80003e0:	1ac0      	subs	r0, r0, r3
+ 80003e2:	4152      	adcs	r2, r2
+ 80003e4:	1a41      	subs	r1, r0, r1
+ 80003e6:	d200      	bcs.n	80003ea <__divsi3+0x1a6>
+ 80003e8:	4601      	mov	r1, r0
+ 80003ea:	4663      	mov	r3, ip
+ 80003ec:	4152      	adcs	r2, r2
+ 80003ee:	105b      	asrs	r3, r3, #1
+ 80003f0:	4610      	mov	r0, r2
+ 80003f2:	d301      	bcc.n	80003f8 <__divsi3+0x1b4>
+ 80003f4:	4240      	negs	r0, r0
+ 80003f6:	2b00      	cmp	r3, #0
+ 80003f8:	d500      	bpl.n	80003fc <__divsi3+0x1b8>
+ 80003fa:	4249      	negs	r1, r1
+ 80003fc:	4770      	bx	lr
+ 80003fe:	4663      	mov	r3, ip
+ 8000400:	105b      	asrs	r3, r3, #1
+ 8000402:	d300      	bcc.n	8000406 <__divsi3+0x1c2>
+ 8000404:	4240      	negs	r0, r0
+ 8000406:	b501      	push	{r0, lr}
+ 8000408:	2000      	movs	r0, #0
+ 800040a:	f000 f805 	bl	8000418 <__aeabi_idiv0>
+ 800040e:	bd02      	pop	{r1, pc}
 
-080003e8 <__aeabi_idivmod>:
- 80003e8:	2900      	cmp	r1, #0
- 80003ea:	d0f8      	beq.n	80003de <__divsi3+0x1c2>
- 80003ec:	e716      	b.n	800021c <__divsi3>
- 80003ee:	4770      	bx	lr
+08000410 <__aeabi_idivmod>:
+ 8000410:	2900      	cmp	r1, #0
+ 8000412:	d0f8      	beq.n	8000406 <__divsi3+0x1c2>
+ 8000414:	e716      	b.n	8000244 <__divsi3>
+ 8000416:	4770      	bx	lr
 
-080003f0 <__aeabi_idiv0>:
- 80003f0:	4770      	bx	lr
- 80003f2:	46c0      	nop			@ (mov r8, r8)
+08000418 <__aeabi_idiv0>:
+ 8000418:	4770      	bx	lr
+ 800041a:	46c0      	nop			@ (mov r8, r8)
 
-080003f4 <__aeabi_ldivmod>:
- 80003f4:	2b00      	cmp	r3, #0
- 80003f6:	d115      	bne.n	8000424 <__aeabi_ldivmod+0x30>
- 80003f8:	2a00      	cmp	r2, #0
- 80003fa:	d113      	bne.n	8000424 <__aeabi_ldivmod+0x30>
- 80003fc:	2900      	cmp	r1, #0
- 80003fe:	db06      	blt.n	800040e <__aeabi_ldivmod+0x1a>
- 8000400:	dc01      	bgt.n	8000406 <__aeabi_ldivmod+0x12>
- 8000402:	2800      	cmp	r0, #0
- 8000404:	d006      	beq.n	8000414 <__aeabi_ldivmod+0x20>
- 8000406:	2000      	movs	r0, #0
- 8000408:	43c0      	mvns	r0, r0
- 800040a:	0841      	lsrs	r1, r0, #1
- 800040c:	e002      	b.n	8000414 <__aeabi_ldivmod+0x20>
- 800040e:	2180      	movs	r1, #128	@ 0x80
- 8000410:	0609      	lsls	r1, r1, #24
- 8000412:	2000      	movs	r0, #0
- 8000414:	b407      	push	{r0, r1, r2}
- 8000416:	4802      	ldr	r0, [pc, #8]	@ (8000420 <__aeabi_ldivmod+0x2c>)
- 8000418:	a101      	add	r1, pc, #4	@ (adr r1, 8000420 <__aeabi_ldivmod+0x2c>)
- 800041a:	1840      	adds	r0, r0, r1
- 800041c:	9002      	str	r0, [sp, #8]
- 800041e:	bd03      	pop	{r0, r1, pc}
- 8000420:	ffffffd1 	.word	0xffffffd1
- 8000424:	b403      	push	{r0, r1}
- 8000426:	4668      	mov	r0, sp
- 8000428:	b501      	push	{r0, lr}
- 800042a:	9802      	ldr	r0, [sp, #8]
- 800042c:	f000 f834 	bl	8000498 <__gnu_ldivmod_helper>
- 8000430:	9b01      	ldr	r3, [sp, #4]
- 8000432:	469e      	mov	lr, r3
- 8000434:	b002      	add	sp, #8
- 8000436:	bc0c      	pop	{r2, r3}
- 8000438:	4770      	bx	lr
- 800043a:	46c0      	nop			@ (mov r8, r8)
+0800041c <__aeabi_ldivmod>:
+ 800041c:	2b00      	cmp	r3, #0
+ 800041e:	d115      	bne.n	800044c <__aeabi_ldivmod+0x30>
+ 8000420:	2a00      	cmp	r2, #0
+ 8000422:	d113      	bne.n	800044c <__aeabi_ldivmod+0x30>
+ 8000424:	2900      	cmp	r1, #0
+ 8000426:	db06      	blt.n	8000436 <__aeabi_ldivmod+0x1a>
+ 8000428:	dc01      	bgt.n	800042e <__aeabi_ldivmod+0x12>
+ 800042a:	2800      	cmp	r0, #0
+ 800042c:	d006      	beq.n	800043c <__aeabi_ldivmod+0x20>
+ 800042e:	2000      	movs	r0, #0
+ 8000430:	43c0      	mvns	r0, r0
+ 8000432:	0841      	lsrs	r1, r0, #1
+ 8000434:	e002      	b.n	800043c <__aeabi_ldivmod+0x20>
+ 8000436:	2180      	movs	r1, #128	@ 0x80
+ 8000438:	0609      	lsls	r1, r1, #24
+ 800043a:	2000      	movs	r0, #0
+ 800043c:	b407      	push	{r0, r1, r2}
+ 800043e:	4802      	ldr	r0, [pc, #8]	@ (8000448 <__aeabi_ldivmod+0x2c>)
+ 8000440:	a101      	add	r1, pc, #4	@ (adr r1, 8000448 <__aeabi_ldivmod+0x2c>)
+ 8000442:	1840      	adds	r0, r0, r1
+ 8000444:	9002      	str	r0, [sp, #8]
+ 8000446:	bd03      	pop	{r0, r1, pc}
+ 8000448:	ffffffd1 	.word	0xffffffd1
+ 800044c:	b403      	push	{r0, r1}
+ 800044e:	4668      	mov	r0, sp
+ 8000450:	b501      	push	{r0, lr}
+ 8000452:	9802      	ldr	r0, [sp, #8]
+ 8000454:	f000 f834 	bl	80004c0 <__gnu_ldivmod_helper>
+ 8000458:	9b01      	ldr	r3, [sp, #4]
+ 800045a:	469e      	mov	lr, r3
+ 800045c:	b002      	add	sp, #8
+ 800045e:	bc0c      	pop	{r2, r3}
+ 8000460:	4770      	bx	lr
+ 8000462:	46c0      	nop			@ (mov r8, r8)
 
-0800043c <__aeabi_lmul>:
- 800043c:	b5f0      	push	{r4, r5, r6, r7, lr}
- 800043e:	46ce      	mov	lr, r9
- 8000440:	4699      	mov	r9, r3
- 8000442:	0c03      	lsrs	r3, r0, #16
- 8000444:	469c      	mov	ip, r3
- 8000446:	0413      	lsls	r3, r2, #16
- 8000448:	4647      	mov	r7, r8
- 800044a:	0c1b      	lsrs	r3, r3, #16
- 800044c:	001d      	movs	r5, r3
- 800044e:	000e      	movs	r6, r1
- 8000450:	4661      	mov	r1, ip
- 8000452:	0404      	lsls	r4, r0, #16
- 8000454:	0c24      	lsrs	r4, r4, #16
- 8000456:	b580      	push	{r7, lr}
- 8000458:	0007      	movs	r7, r0
- 800045a:	0c10      	lsrs	r0, r2, #16
- 800045c:	434b      	muls	r3, r1
- 800045e:	4365      	muls	r5, r4
- 8000460:	4341      	muls	r1, r0
- 8000462:	4360      	muls	r0, r4
- 8000464:	0c2c      	lsrs	r4, r5, #16
- 8000466:	18c0      	adds	r0, r0, r3
- 8000468:	1824      	adds	r4, r4, r0
- 800046a:	468c      	mov	ip, r1
- 800046c:	42a3      	cmp	r3, r4
- 800046e:	d903      	bls.n	8000478 <__aeabi_lmul+0x3c>
- 8000470:	2380      	movs	r3, #128	@ 0x80
- 8000472:	025b      	lsls	r3, r3, #9
- 8000474:	4698      	mov	r8, r3
- 8000476:	44c4      	add	ip, r8
- 8000478:	4649      	mov	r1, r9
- 800047a:	4379      	muls	r1, r7
- 800047c:	4356      	muls	r6, r2
- 800047e:	0c23      	lsrs	r3, r4, #16
- 8000480:	042d      	lsls	r5, r5, #16
- 8000482:	0c2d      	lsrs	r5, r5, #16
- 8000484:	1989      	adds	r1, r1, r6
- 8000486:	4463      	add	r3, ip
- 8000488:	0424      	lsls	r4, r4, #16
- 800048a:	1960      	adds	r0, r4, r5
- 800048c:	18c9      	adds	r1, r1, r3
- 800048e:	bcc0      	pop	{r6, r7}
- 8000490:	46b9      	mov	r9, r7
- 8000492:	46b0      	mov	r8, r6
- 8000494:	bdf0      	pop	{r4, r5, r6, r7, pc}
- 8000496:	46c0      	nop			@ (mov r8, r8)
+08000464 <__aeabi_lmul>:
+ 8000464:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 8000466:	46ce      	mov	lr, r9
+ 8000468:	4699      	mov	r9, r3
+ 800046a:	0c03      	lsrs	r3, r0, #16
+ 800046c:	469c      	mov	ip, r3
+ 800046e:	0413      	lsls	r3, r2, #16
+ 8000470:	4647      	mov	r7, r8
+ 8000472:	0c1b      	lsrs	r3, r3, #16
+ 8000474:	001d      	movs	r5, r3
+ 8000476:	000e      	movs	r6, r1
+ 8000478:	4661      	mov	r1, ip
+ 800047a:	0404      	lsls	r4, r0, #16
+ 800047c:	0c24      	lsrs	r4, r4, #16
+ 800047e:	b580      	push	{r7, lr}
+ 8000480:	0007      	movs	r7, r0
+ 8000482:	0c10      	lsrs	r0, r2, #16
+ 8000484:	434b      	muls	r3, r1
+ 8000486:	4365      	muls	r5, r4
+ 8000488:	4341      	muls	r1, r0
+ 800048a:	4360      	muls	r0, r4
+ 800048c:	0c2c      	lsrs	r4, r5, #16
+ 800048e:	18c0      	adds	r0, r0, r3
+ 8000490:	1824      	adds	r4, r4, r0
+ 8000492:	468c      	mov	ip, r1
+ 8000494:	42a3      	cmp	r3, r4
+ 8000496:	d903      	bls.n	80004a0 <__aeabi_lmul+0x3c>
+ 8000498:	2380      	movs	r3, #128	@ 0x80
+ 800049a:	025b      	lsls	r3, r3, #9
+ 800049c:	4698      	mov	r8, r3
+ 800049e:	44c4      	add	ip, r8
+ 80004a0:	4649      	mov	r1, r9
+ 80004a2:	4379      	muls	r1, r7
+ 80004a4:	4356      	muls	r6, r2
+ 80004a6:	0c23      	lsrs	r3, r4, #16
+ 80004a8:	042d      	lsls	r5, r5, #16
+ 80004aa:	0c2d      	lsrs	r5, r5, #16
+ 80004ac:	1989      	adds	r1, r1, r6
+ 80004ae:	4463      	add	r3, ip
+ 80004b0:	0424      	lsls	r4, r4, #16
+ 80004b2:	1960      	adds	r0, r4, r5
+ 80004b4:	18c9      	adds	r1, r1, r3
+ 80004b6:	bcc0      	pop	{r6, r7}
+ 80004b8:	46b9      	mov	r9, r7
+ 80004ba:	46b0      	mov	r8, r6
+ 80004bc:	bdf0      	pop	{r4, r5, r6, r7, pc}
+ 80004be:	46c0      	nop			@ (mov r8, r8)
 
-08000498 <__gnu_ldivmod_helper>:
- 8000498:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 800049a:	46ce      	mov	lr, r9
- 800049c:	4647      	mov	r7, r8
- 800049e:	b580      	push	{r7, lr}
- 80004a0:	4691      	mov	r9, r2
- 80004a2:	4698      	mov	r8, r3
- 80004a4:	0004      	movs	r4, r0
- 80004a6:	000d      	movs	r5, r1
- 80004a8:	f000 f814 	bl	80004d4 <__divdi3>
- 80004ac:	0007      	movs	r7, r0
- 80004ae:	000e      	movs	r6, r1
- 80004b0:	0002      	movs	r2, r0
- 80004b2:	000b      	movs	r3, r1
- 80004b4:	4648      	mov	r0, r9
- 80004b6:	4641      	mov	r1, r8
- 80004b8:	f7ff ffc0 	bl	800043c <__aeabi_lmul>
- 80004bc:	1a24      	subs	r4, r4, r0
- 80004be:	418d      	sbcs	r5, r1
- 80004c0:	9b08      	ldr	r3, [sp, #32]
- 80004c2:	0038      	movs	r0, r7
- 80004c4:	0031      	movs	r1, r6
- 80004c6:	601c      	str	r4, [r3, #0]
- 80004c8:	605d      	str	r5, [r3, #4]
- 80004ca:	bcc0      	pop	{r6, r7}
- 80004cc:	46b9      	mov	r9, r7
- 80004ce:	46b0      	mov	r8, r6
- 80004d0:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
- 80004d2:	46c0      	nop			@ (mov r8, r8)
+080004c0 <__gnu_ldivmod_helper>:
+ 80004c0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 80004c2:	46ce      	mov	lr, r9
+ 80004c4:	4647      	mov	r7, r8
+ 80004c6:	b580      	push	{r7, lr}
+ 80004c8:	4691      	mov	r9, r2
+ 80004ca:	4698      	mov	r8, r3
+ 80004cc:	0004      	movs	r4, r0
+ 80004ce:	000d      	movs	r5, r1
+ 80004d0:	f000 f814 	bl	80004fc <__divdi3>
+ 80004d4:	0007      	movs	r7, r0
+ 80004d6:	000e      	movs	r6, r1
+ 80004d8:	0002      	movs	r2, r0
+ 80004da:	000b      	movs	r3, r1
+ 80004dc:	4648      	mov	r0, r9
+ 80004de:	4641      	mov	r1, r8
+ 80004e0:	f7ff ffc0 	bl	8000464 <__aeabi_lmul>
+ 80004e4:	1a24      	subs	r4, r4, r0
+ 80004e6:	418d      	sbcs	r5, r1
+ 80004e8:	9b08      	ldr	r3, [sp, #32]
+ 80004ea:	0038      	movs	r0, r7
+ 80004ec:	0031      	movs	r1, r6
+ 80004ee:	601c      	str	r4, [r3, #0]
+ 80004f0:	605d      	str	r5, [r3, #4]
+ 80004f2:	bcc0      	pop	{r6, r7}
+ 80004f4:	46b9      	mov	r9, r7
+ 80004f6:	46b0      	mov	r8, r6
+ 80004f8:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 80004fa:	46c0      	nop			@ (mov r8, r8)
 
-080004d4 <__divdi3>:
- 80004d4:	b5f0      	push	{r4, r5, r6, r7, lr}
- 80004d6:	464f      	mov	r7, r9
- 80004d8:	4646      	mov	r6, r8
- 80004da:	46d6      	mov	lr, sl
- 80004dc:	b5c0      	push	{r6, r7, lr}
- 80004de:	0006      	movs	r6, r0
- 80004e0:	000f      	movs	r7, r1
- 80004e2:	0010      	movs	r0, r2
- 80004e4:	0019      	movs	r1, r3
- 80004e6:	b082      	sub	sp, #8
- 80004e8:	2f00      	cmp	r7, #0
- 80004ea:	db5d      	blt.n	80005a8 <__divdi3+0xd4>
- 80004ec:	0034      	movs	r4, r6
- 80004ee:	003d      	movs	r5, r7
- 80004f0:	2b00      	cmp	r3, #0
- 80004f2:	db0b      	blt.n	800050c <__divdi3+0x38>
- 80004f4:	0016      	movs	r6, r2
- 80004f6:	001f      	movs	r7, r3
- 80004f8:	42ab      	cmp	r3, r5
- 80004fa:	d917      	bls.n	800052c <__divdi3+0x58>
- 80004fc:	2000      	movs	r0, #0
- 80004fe:	2100      	movs	r1, #0
- 8000500:	b002      	add	sp, #8
- 8000502:	bce0      	pop	{r5, r6, r7}
- 8000504:	46ba      	mov	sl, r7
- 8000506:	46b1      	mov	r9, r6
- 8000508:	46a8      	mov	r8, r5
- 800050a:	bdf0      	pop	{r4, r5, r6, r7, pc}
- 800050c:	2700      	movs	r7, #0
- 800050e:	4246      	negs	r6, r0
- 8000510:	418f      	sbcs	r7, r1
- 8000512:	42af      	cmp	r7, r5
- 8000514:	d8f2      	bhi.n	80004fc <__divdi3+0x28>
- 8000516:	d100      	bne.n	800051a <__divdi3+0x46>
- 8000518:	e0a0      	b.n	800065c <__divdi3+0x188>
- 800051a:	2301      	movs	r3, #1
- 800051c:	425b      	negs	r3, r3
- 800051e:	4699      	mov	r9, r3
- 8000520:	e009      	b.n	8000536 <__divdi3+0x62>
- 8000522:	2700      	movs	r7, #0
- 8000524:	4246      	negs	r6, r0
- 8000526:	418f      	sbcs	r7, r1
- 8000528:	42af      	cmp	r7, r5
- 800052a:	d8e7      	bhi.n	80004fc <__divdi3+0x28>
- 800052c:	42af      	cmp	r7, r5
- 800052e:	d100      	bne.n	8000532 <__divdi3+0x5e>
- 8000530:	e090      	b.n	8000654 <__divdi3+0x180>
- 8000532:	2300      	movs	r3, #0
- 8000534:	4699      	mov	r9, r3
- 8000536:	0039      	movs	r1, r7
- 8000538:	0030      	movs	r0, r6
- 800053a:	f000 f8b7 	bl	80006ac <__clzdi2>
- 800053e:	4680      	mov	r8, r0
- 8000540:	0029      	movs	r1, r5
- 8000542:	0020      	movs	r0, r4
- 8000544:	f000 f8b2 	bl	80006ac <__clzdi2>
- 8000548:	4643      	mov	r3, r8
- 800054a:	1a1b      	subs	r3, r3, r0
- 800054c:	4698      	mov	r8, r3
- 800054e:	3b20      	subs	r3, #32
- 8000550:	d475      	bmi.n	800063e <__divdi3+0x16a>
- 8000552:	0031      	movs	r1, r6
- 8000554:	4099      	lsls	r1, r3
- 8000556:	469a      	mov	sl, r3
- 8000558:	000b      	movs	r3, r1
- 800055a:	0031      	movs	r1, r6
- 800055c:	4640      	mov	r0, r8
- 800055e:	4081      	lsls	r1, r0
- 8000560:	000a      	movs	r2, r1
- 8000562:	42ab      	cmp	r3, r5
- 8000564:	d82e      	bhi.n	80005c4 <__divdi3+0xf0>
- 8000566:	d02b      	beq.n	80005c0 <__divdi3+0xec>
- 8000568:	4651      	mov	r1, sl
- 800056a:	1aa4      	subs	r4, r4, r2
- 800056c:	419d      	sbcs	r5, r3
- 800056e:	2900      	cmp	r1, #0
- 8000570:	da00      	bge.n	8000574 <__divdi3+0xa0>
- 8000572:	e090      	b.n	8000696 <__divdi3+0x1c2>
- 8000574:	2100      	movs	r1, #0
- 8000576:	2000      	movs	r0, #0
- 8000578:	2601      	movs	r6, #1
- 800057a:	9000      	str	r0, [sp, #0]
- 800057c:	9101      	str	r1, [sp, #4]
- 800057e:	4651      	mov	r1, sl
- 8000580:	408e      	lsls	r6, r1
- 8000582:	9601      	str	r6, [sp, #4]
- 8000584:	4641      	mov	r1, r8
- 8000586:	2601      	movs	r6, #1
- 8000588:	408e      	lsls	r6, r1
- 800058a:	4641      	mov	r1, r8
- 800058c:	9600      	str	r6, [sp, #0]
- 800058e:	2900      	cmp	r1, #0
- 8000590:	d11f      	bne.n	80005d2 <__divdi3+0xfe>
- 8000592:	9800      	ldr	r0, [sp, #0]
- 8000594:	9901      	ldr	r1, [sp, #4]
- 8000596:	464b      	mov	r3, r9
- 8000598:	2b00      	cmp	r3, #0
- 800059a:	d0b1      	beq.n	8000500 <__divdi3+0x2c>
- 800059c:	0003      	movs	r3, r0
- 800059e:	000c      	movs	r4, r1
- 80005a0:	2100      	movs	r1, #0
- 80005a2:	4258      	negs	r0, r3
- 80005a4:	41a1      	sbcs	r1, r4
- 80005a6:	e7ab      	b.n	8000500 <__divdi3+0x2c>
- 80005a8:	2500      	movs	r5, #0
- 80005aa:	4274      	negs	r4, r6
- 80005ac:	41bd      	sbcs	r5, r7
- 80005ae:	2b00      	cmp	r3, #0
- 80005b0:	dbb7      	blt.n	8000522 <__divdi3+0x4e>
- 80005b2:	0016      	movs	r6, r2
- 80005b4:	001f      	movs	r7, r3
- 80005b6:	42ab      	cmp	r3, r5
- 80005b8:	d8a0      	bhi.n	80004fc <__divdi3+0x28>
- 80005ba:	42af      	cmp	r7, r5
- 80005bc:	d1ad      	bne.n	800051a <__divdi3+0x46>
- 80005be:	e04d      	b.n	800065c <__divdi3+0x188>
- 80005c0:	42a1      	cmp	r1, r4
- 80005c2:	d9d1      	bls.n	8000568 <__divdi3+0x94>
- 80005c4:	2100      	movs	r1, #0
- 80005c6:	2000      	movs	r0, #0
- 80005c8:	9000      	str	r0, [sp, #0]
- 80005ca:	9101      	str	r1, [sp, #4]
- 80005cc:	4641      	mov	r1, r8
- 80005ce:	2900      	cmp	r1, #0
- 80005d0:	d0df      	beq.n	8000592 <__divdi3+0xbe>
- 80005d2:	07d9      	lsls	r1, r3, #31
- 80005d4:	0856      	lsrs	r6, r2, #1
- 80005d6:	085f      	lsrs	r7, r3, #1
- 80005d8:	430e      	orrs	r6, r1
- 80005da:	4643      	mov	r3, r8
- 80005dc:	e00e      	b.n	80005fc <__divdi3+0x128>
- 80005de:	42af      	cmp	r7, r5
- 80005e0:	d101      	bne.n	80005e6 <__divdi3+0x112>
- 80005e2:	42a6      	cmp	r6, r4
- 80005e4:	d80c      	bhi.n	8000600 <__divdi3+0x12c>
- 80005e6:	1ba4      	subs	r4, r4, r6
- 80005e8:	41bd      	sbcs	r5, r7
- 80005ea:	2101      	movs	r1, #1
- 80005ec:	1924      	adds	r4, r4, r4
- 80005ee:	416d      	adcs	r5, r5
- 80005f0:	2200      	movs	r2, #0
- 80005f2:	3b01      	subs	r3, #1
- 80005f4:	1864      	adds	r4, r4, r1
- 80005f6:	4155      	adcs	r5, r2
- 80005f8:	2b00      	cmp	r3, #0
- 80005fa:	d006      	beq.n	800060a <__divdi3+0x136>
- 80005fc:	42af      	cmp	r7, r5
- 80005fe:	d9ee      	bls.n	80005de <__divdi3+0x10a>
- 8000600:	3b01      	subs	r3, #1
- 8000602:	1924      	adds	r4, r4, r4
- 8000604:	416d      	adcs	r5, r5
- 8000606:	2b00      	cmp	r3, #0
- 8000608:	d1f8      	bne.n	80005fc <__divdi3+0x128>
- 800060a:	9a00      	ldr	r2, [sp, #0]
- 800060c:	9b01      	ldr	r3, [sp, #4]
- 800060e:	4651      	mov	r1, sl
- 8000610:	1912      	adds	r2, r2, r4
- 8000612:	416b      	adcs	r3, r5
- 8000614:	2900      	cmp	r1, #0
- 8000616:	db25      	blt.n	8000664 <__divdi3+0x190>
- 8000618:	002e      	movs	r6, r5
- 800061a:	002c      	movs	r4, r5
- 800061c:	40ce      	lsrs	r6, r1
- 800061e:	4641      	mov	r1, r8
- 8000620:	40cc      	lsrs	r4, r1
- 8000622:	4651      	mov	r1, sl
- 8000624:	2900      	cmp	r1, #0
- 8000626:	db2d      	blt.n	8000684 <__divdi3+0x1b0>
- 8000628:	0034      	movs	r4, r6
- 800062a:	408c      	lsls	r4, r1
- 800062c:	0021      	movs	r1, r4
- 800062e:	4644      	mov	r4, r8
- 8000630:	40a6      	lsls	r6, r4
- 8000632:	0030      	movs	r0, r6
- 8000634:	1a12      	subs	r2, r2, r0
- 8000636:	418b      	sbcs	r3, r1
- 8000638:	9200      	str	r2, [sp, #0]
- 800063a:	9301      	str	r3, [sp, #4]
- 800063c:	e7a9      	b.n	8000592 <__divdi3+0xbe>
- 800063e:	4642      	mov	r2, r8
- 8000640:	0038      	movs	r0, r7
- 8000642:	469a      	mov	sl, r3
- 8000644:	2320      	movs	r3, #32
- 8000646:	0031      	movs	r1, r6
- 8000648:	4090      	lsls	r0, r2
- 800064a:	1a9b      	subs	r3, r3, r2
- 800064c:	40d9      	lsrs	r1, r3
- 800064e:	0003      	movs	r3, r0
- 8000650:	430b      	orrs	r3, r1
- 8000652:	e782      	b.n	800055a <__divdi3+0x86>
- 8000654:	42a6      	cmp	r6, r4
- 8000656:	d900      	bls.n	800065a <__divdi3+0x186>
- 8000658:	e750      	b.n	80004fc <__divdi3+0x28>
- 800065a:	e76a      	b.n	8000532 <__divdi3+0x5e>
- 800065c:	42a6      	cmp	r6, r4
- 800065e:	d800      	bhi.n	8000662 <__divdi3+0x18e>
- 8000660:	e75b      	b.n	800051a <__divdi3+0x46>
- 8000662:	e74b      	b.n	80004fc <__divdi3+0x28>
- 8000664:	4640      	mov	r0, r8
- 8000666:	2120      	movs	r1, #32
- 8000668:	1a09      	subs	r1, r1, r0
- 800066a:	0028      	movs	r0, r5
- 800066c:	4088      	lsls	r0, r1
- 800066e:	0026      	movs	r6, r4
- 8000670:	0001      	movs	r1, r0
- 8000672:	4640      	mov	r0, r8
- 8000674:	40c6      	lsrs	r6, r0
- 8000676:	002c      	movs	r4, r5
- 8000678:	430e      	orrs	r6, r1
- 800067a:	4641      	mov	r1, r8
- 800067c:	40cc      	lsrs	r4, r1
- 800067e:	4651      	mov	r1, sl
- 8000680:	2900      	cmp	r1, #0
- 8000682:	dad1      	bge.n	8000628 <__divdi3+0x154>
- 8000684:	4640      	mov	r0, r8
- 8000686:	2120      	movs	r1, #32
- 8000688:	0035      	movs	r5, r6
- 800068a:	4084      	lsls	r4, r0
- 800068c:	1a09      	subs	r1, r1, r0
- 800068e:	40cd      	lsrs	r5, r1
- 8000690:	0021      	movs	r1, r4
- 8000692:	4329      	orrs	r1, r5
- 8000694:	e7cb      	b.n	800062e <__divdi3+0x15a>
- 8000696:	4641      	mov	r1, r8
- 8000698:	2620      	movs	r6, #32
- 800069a:	2701      	movs	r7, #1
- 800069c:	1a76      	subs	r6, r6, r1
- 800069e:	2000      	movs	r0, #0
- 80006a0:	2100      	movs	r1, #0
- 80006a2:	40f7      	lsrs	r7, r6
- 80006a4:	9000      	str	r0, [sp, #0]
- 80006a6:	9101      	str	r1, [sp, #4]
- 80006a8:	9701      	str	r7, [sp, #4]
- 80006aa:	e76b      	b.n	8000584 <__divdi3+0xb0>
+080004fc <__divdi3>:
+ 80004fc:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 80004fe:	4645      	mov	r5, r8
+ 8000500:	46de      	mov	lr, fp
+ 8000502:	4657      	mov	r7, sl
+ 8000504:	464e      	mov	r6, r9
+ 8000506:	b5e0      	push	{r5, r6, r7, lr}
+ 8000508:	b083      	sub	sp, #12
+ 800050a:	9200      	str	r2, [sp, #0]
+ 800050c:	9301      	str	r3, [sp, #4]
+ 800050e:	000d      	movs	r5, r1
+ 8000510:	9900      	ldr	r1, [sp, #0]
+ 8000512:	9a01      	ldr	r2, [sp, #4]
+ 8000514:	0004      	movs	r4, r0
+ 8000516:	2d00      	cmp	r5, #0
+ 8000518:	db61      	blt.n	80005de <__divdi3+0xe2>
+ 800051a:	0006      	movs	r6, r0
+ 800051c:	002f      	movs	r7, r5
+ 800051e:	2a00      	cmp	r2, #0
+ 8000520:	db0c      	blt.n	800053c <__divdi3+0x40>
+ 8000522:	9c00      	ldr	r4, [sp, #0]
+ 8000524:	9d01      	ldr	r5, [sp, #4]
+ 8000526:	42bd      	cmp	r5, r7
+ 8000528:	d91a      	bls.n	8000560 <__divdi3+0x64>
+ 800052a:	2000      	movs	r0, #0
+ 800052c:	2100      	movs	r1, #0
+ 800052e:	b003      	add	sp, #12
+ 8000530:	bcf0      	pop	{r4, r5, r6, r7}
+ 8000532:	46bb      	mov	fp, r7
+ 8000534:	46b2      	mov	sl, r6
+ 8000536:	46a9      	mov	r9, r5
+ 8000538:	46a0      	mov	r8, r4
+ 800053a:	bdf0      	pop	{r4, r5, r6, r7, pc}
+ 800053c:	2500      	movs	r5, #0
+ 800053e:	424c      	negs	r4, r1
+ 8000540:	4195      	sbcs	r5, r2
+ 8000542:	42bd      	cmp	r5, r7
+ 8000544:	d8f1      	bhi.n	800052a <__divdi3+0x2e>
+ 8000546:	d100      	bne.n	800054a <__divdi3+0x4e>
+ 8000548:	e0ae      	b.n	80006a8 <__divdi3+0x1ac>
+ 800054a:	2301      	movs	r3, #1
+ 800054c:	425b      	negs	r3, r3
+ 800054e:	4699      	mov	r9, r3
+ 8000550:	e00b      	b.n	800056a <__divdi3+0x6e>
+ 8000552:	9a00      	ldr	r2, [sp, #0]
+ 8000554:	9b01      	ldr	r3, [sp, #4]
+ 8000556:	2500      	movs	r5, #0
+ 8000558:	4254      	negs	r4, r2
+ 800055a:	419d      	sbcs	r5, r3
+ 800055c:	42bd      	cmp	r5, r7
+ 800055e:	d8e4      	bhi.n	800052a <__divdi3+0x2e>
+ 8000560:	42bd      	cmp	r5, r7
+ 8000562:	d100      	bne.n	8000566 <__divdi3+0x6a>
+ 8000564:	e09c      	b.n	80006a0 <__divdi3+0x1a4>
+ 8000566:	2300      	movs	r3, #0
+ 8000568:	4699      	mov	r9, r3
+ 800056a:	0029      	movs	r1, r5
+ 800056c:	0020      	movs	r0, r4
+ 800056e:	f000 f8c3 	bl	80006f8 <__clzdi2>
+ 8000572:	4680      	mov	r8, r0
+ 8000574:	0039      	movs	r1, r7
+ 8000576:	0030      	movs	r0, r6
+ 8000578:	f000 f8be 	bl	80006f8 <__clzdi2>
+ 800057c:	4643      	mov	r3, r8
+ 800057e:	1a1b      	subs	r3, r3, r0
+ 8000580:	4698      	mov	r8, r3
+ 8000582:	3b20      	subs	r3, #32
+ 8000584:	d500      	bpl.n	8000588 <__divdi3+0x8c>
+ 8000586:	e080      	b.n	800068a <__divdi3+0x18e>
+ 8000588:	0021      	movs	r1, r4
+ 800058a:	4099      	lsls	r1, r3
+ 800058c:	469a      	mov	sl, r3
+ 800058e:	000b      	movs	r3, r1
+ 8000590:	0021      	movs	r1, r4
+ 8000592:	4640      	mov	r0, r8
+ 8000594:	4081      	lsls	r1, r0
+ 8000596:	000a      	movs	r2, r1
+ 8000598:	42bb      	cmp	r3, r7
+ 800059a:	d82d      	bhi.n	80005f8 <__divdi3+0xfc>
+ 800059c:	d02a      	beq.n	80005f4 <__divdi3+0xf8>
+ 800059e:	4651      	mov	r1, sl
+ 80005a0:	1ab6      	subs	r6, r6, r2
+ 80005a2:	419f      	sbcs	r7, r3
+ 80005a4:	2900      	cmp	r1, #0
+ 80005a6:	da00      	bge.n	80005aa <__divdi3+0xae>
+ 80005a8:	e09b      	b.n	80006e2 <__divdi3+0x1e6>
+ 80005aa:	2100      	movs	r1, #0
+ 80005ac:	2000      	movs	r0, #0
+ 80005ae:	2401      	movs	r4, #1
+ 80005b0:	9000      	str	r0, [sp, #0]
+ 80005b2:	9101      	str	r1, [sp, #4]
+ 80005b4:	4651      	mov	r1, sl
+ 80005b6:	408c      	lsls	r4, r1
+ 80005b8:	9401      	str	r4, [sp, #4]
+ 80005ba:	2401      	movs	r4, #1
+ 80005bc:	4645      	mov	r5, r8
+ 80005be:	40ac      	lsls	r4, r5
+ 80005c0:	9400      	str	r4, [sp, #0]
+ 80005c2:	4644      	mov	r4, r8
+ 80005c4:	2c00      	cmp	r4, #0
+ 80005c6:	d11e      	bne.n	8000606 <__divdi3+0x10a>
+ 80005c8:	9800      	ldr	r0, [sp, #0]
+ 80005ca:	9901      	ldr	r1, [sp, #4]
+ 80005cc:	464b      	mov	r3, r9
+ 80005ce:	2b00      	cmp	r3, #0
+ 80005d0:	d0ad      	beq.n	800052e <__divdi3+0x32>
+ 80005d2:	0003      	movs	r3, r0
+ 80005d4:	000c      	movs	r4, r1
+ 80005d6:	2100      	movs	r1, #0
+ 80005d8:	4258      	negs	r0, r3
+ 80005da:	41a1      	sbcs	r1, r4
+ 80005dc:	e7a7      	b.n	800052e <__divdi3+0x32>
+ 80005de:	2700      	movs	r7, #0
+ 80005e0:	4266      	negs	r6, r4
+ 80005e2:	41af      	sbcs	r7, r5
+ 80005e4:	2a00      	cmp	r2, #0
+ 80005e6:	dbb4      	blt.n	8000552 <__divdi3+0x56>
+ 80005e8:	9c00      	ldr	r4, [sp, #0]
+ 80005ea:	9d01      	ldr	r5, [sp, #4]
+ 80005ec:	42bd      	cmp	r5, r7
+ 80005ee:	d89c      	bhi.n	800052a <__divdi3+0x2e>
+ 80005f0:	d1ab      	bne.n	800054a <__divdi3+0x4e>
+ 80005f2:	e059      	b.n	80006a8 <__divdi3+0x1ac>
+ 80005f4:	42b1      	cmp	r1, r6
+ 80005f6:	d9d2      	bls.n	800059e <__divdi3+0xa2>
+ 80005f8:	2000      	movs	r0, #0
+ 80005fa:	2100      	movs	r1, #0
+ 80005fc:	4644      	mov	r4, r8
+ 80005fe:	9000      	str	r0, [sp, #0]
+ 8000600:	9101      	str	r1, [sp, #4]
+ 8000602:	2c00      	cmp	r4, #0
+ 8000604:	d0e0      	beq.n	80005c8 <__divdi3+0xcc>
+ 8000606:	07dc      	lsls	r4, r3, #31
+ 8000608:	46a4      	mov	ip, r4
+ 800060a:	4661      	mov	r1, ip
+ 800060c:	0854      	lsrs	r4, r2, #1
+ 800060e:	46c4      	mov	ip, r8
+ 8000610:	430c      	orrs	r4, r1
+ 8000612:	085d      	lsrs	r5, r3, #1
+ 8000614:	e014      	b.n	8000640 <__divdi3+0x144>
+ 8000616:	42bd      	cmp	r5, r7
+ 8000618:	d101      	bne.n	800061e <__divdi3+0x122>
+ 800061a:	42b4      	cmp	r4, r6
+ 800061c:	d812      	bhi.n	8000644 <__divdi3+0x148>
+ 800061e:	0032      	movs	r2, r6
+ 8000620:	003b      	movs	r3, r7
+ 8000622:	1b12      	subs	r2, r2, r4
+ 8000624:	41ab      	sbcs	r3, r5
+ 8000626:	2601      	movs	r6, #1
+ 8000628:	1892      	adds	r2, r2, r2
+ 800062a:	415b      	adcs	r3, r3
+ 800062c:	2700      	movs	r7, #0
+ 800062e:	18b6      	adds	r6, r6, r2
+ 8000630:	415f      	adcs	r7, r3
+ 8000632:	2301      	movs	r3, #1
+ 8000634:	425b      	negs	r3, r3
+ 8000636:	469b      	mov	fp, r3
+ 8000638:	44dc      	add	ip, fp
+ 800063a:	4663      	mov	r3, ip
+ 800063c:	2b00      	cmp	r3, #0
+ 800063e:	d00a      	beq.n	8000656 <__divdi3+0x15a>
+ 8000640:	42bd      	cmp	r5, r7
+ 8000642:	d9e8      	bls.n	8000616 <__divdi3+0x11a>
+ 8000644:	2301      	movs	r3, #1
+ 8000646:	425b      	negs	r3, r3
+ 8000648:	469b      	mov	fp, r3
+ 800064a:	44dc      	add	ip, fp
+ 800064c:	4663      	mov	r3, ip
+ 800064e:	19b6      	adds	r6, r6, r6
+ 8000650:	417f      	adcs	r7, r7
+ 8000652:	2b00      	cmp	r3, #0
+ 8000654:	d1f4      	bne.n	8000640 <__divdi3+0x144>
+ 8000656:	9a00      	ldr	r2, [sp, #0]
+ 8000658:	9b01      	ldr	r3, [sp, #4]
+ 800065a:	4651      	mov	r1, sl
+ 800065c:	1992      	adds	r2, r2, r6
+ 800065e:	417b      	adcs	r3, r7
+ 8000660:	2900      	cmp	r1, #0
+ 8000662:	db25      	blt.n	80006b0 <__divdi3+0x1b4>
+ 8000664:	003c      	movs	r4, r7
+ 8000666:	003d      	movs	r5, r7
+ 8000668:	40cc      	lsrs	r4, r1
+ 800066a:	4641      	mov	r1, r8
+ 800066c:	40cd      	lsrs	r5, r1
+ 800066e:	4651      	mov	r1, sl
+ 8000670:	2900      	cmp	r1, #0
+ 8000672:	db2d      	blt.n	80006d0 <__divdi3+0x1d4>
+ 8000674:	0025      	movs	r5, r4
+ 8000676:	408d      	lsls	r5, r1
+ 8000678:	0029      	movs	r1, r5
+ 800067a:	4645      	mov	r5, r8
+ 800067c:	40ac      	lsls	r4, r5
+ 800067e:	0020      	movs	r0, r4
+ 8000680:	1a12      	subs	r2, r2, r0
+ 8000682:	418b      	sbcs	r3, r1
+ 8000684:	9200      	str	r2, [sp, #0]
+ 8000686:	9301      	str	r3, [sp, #4]
+ 8000688:	e79e      	b.n	80005c8 <__divdi3+0xcc>
+ 800068a:	4642      	mov	r2, r8
+ 800068c:	0028      	movs	r0, r5
+ 800068e:	469a      	mov	sl, r3
+ 8000690:	2320      	movs	r3, #32
+ 8000692:	0021      	movs	r1, r4
+ 8000694:	4090      	lsls	r0, r2
+ 8000696:	1a9b      	subs	r3, r3, r2
+ 8000698:	40d9      	lsrs	r1, r3
+ 800069a:	0003      	movs	r3, r0
+ 800069c:	430b      	orrs	r3, r1
+ 800069e:	e777      	b.n	8000590 <__divdi3+0x94>
+ 80006a0:	42b4      	cmp	r4, r6
+ 80006a2:	d900      	bls.n	80006a6 <__divdi3+0x1aa>
+ 80006a4:	e741      	b.n	800052a <__divdi3+0x2e>
+ 80006a6:	e75e      	b.n	8000566 <__divdi3+0x6a>
+ 80006a8:	42b4      	cmp	r4, r6
+ 80006aa:	d800      	bhi.n	80006ae <__divdi3+0x1b2>
+ 80006ac:	e74d      	b.n	800054a <__divdi3+0x4e>
+ 80006ae:	e73c      	b.n	800052a <__divdi3+0x2e>
+ 80006b0:	4640      	mov	r0, r8
+ 80006b2:	2120      	movs	r1, #32
+ 80006b4:	1a09      	subs	r1, r1, r0
+ 80006b6:	0038      	movs	r0, r7
+ 80006b8:	4088      	lsls	r0, r1
+ 80006ba:	0034      	movs	r4, r6
+ 80006bc:	0001      	movs	r1, r0
+ 80006be:	4640      	mov	r0, r8
+ 80006c0:	40c4      	lsrs	r4, r0
+ 80006c2:	003d      	movs	r5, r7
+ 80006c4:	430c      	orrs	r4, r1
+ 80006c6:	4641      	mov	r1, r8
+ 80006c8:	40cd      	lsrs	r5, r1
+ 80006ca:	4651      	mov	r1, sl
+ 80006cc:	2900      	cmp	r1, #0
+ 80006ce:	dad1      	bge.n	8000674 <__divdi3+0x178>
+ 80006d0:	4640      	mov	r0, r8
+ 80006d2:	2120      	movs	r1, #32
+ 80006d4:	0026      	movs	r6, r4
+ 80006d6:	4085      	lsls	r5, r0
+ 80006d8:	1a09      	subs	r1, r1, r0
+ 80006da:	40ce      	lsrs	r6, r1
+ 80006dc:	0029      	movs	r1, r5
+ 80006de:	4331      	orrs	r1, r6
+ 80006e0:	e7cb      	b.n	800067a <__divdi3+0x17e>
+ 80006e2:	4641      	mov	r1, r8
+ 80006e4:	2420      	movs	r4, #32
+ 80006e6:	2501      	movs	r5, #1
+ 80006e8:	1a64      	subs	r4, r4, r1
+ 80006ea:	2000      	movs	r0, #0
+ 80006ec:	2100      	movs	r1, #0
+ 80006ee:	40e5      	lsrs	r5, r4
+ 80006f0:	9000      	str	r0, [sp, #0]
+ 80006f2:	9101      	str	r1, [sp, #4]
+ 80006f4:	9501      	str	r5, [sp, #4]
+ 80006f6:	e760      	b.n	80005ba <__divdi3+0xbe>
 
-080006ac <__clzdi2>:
- 80006ac:	b510      	push	{r4, lr}
- 80006ae:	2900      	cmp	r1, #0
- 80006b0:	d103      	bne.n	80006ba <__clzdi2+0xe>
- 80006b2:	f000 f807 	bl	80006c4 <__clzsi2>
- 80006b6:	3020      	adds	r0, #32
- 80006b8:	e002      	b.n	80006c0 <__clzdi2+0x14>
- 80006ba:	0008      	movs	r0, r1
- 80006bc:	f000 f802 	bl	80006c4 <__clzsi2>
- 80006c0:	bd10      	pop	{r4, pc}
- 80006c2:	46c0      	nop			@ (mov r8, r8)
+080006f8 <__clzdi2>:
+ 80006f8:	b510      	push	{r4, lr}
+ 80006fa:	2900      	cmp	r1, #0
+ 80006fc:	d103      	bne.n	8000706 <__clzdi2+0xe>
+ 80006fe:	f000 f807 	bl	8000710 <__clzsi2>
+ 8000702:	3020      	adds	r0, #32
+ 8000704:	e002      	b.n	800070c <__clzdi2+0x14>
+ 8000706:	0008      	movs	r0, r1
+ 8000708:	f000 f802 	bl	8000710 <__clzsi2>
+ 800070c:	bd10      	pop	{r4, pc}
+ 800070e:	46c0      	nop			@ (mov r8, r8)
 
-080006c4 <__clzsi2>:
- 80006c4:	211c      	movs	r1, #28
- 80006c6:	2301      	movs	r3, #1
- 80006c8:	041b      	lsls	r3, r3, #16
- 80006ca:	4298      	cmp	r0, r3
- 80006cc:	d301      	bcc.n	80006d2 <__clzsi2+0xe>
- 80006ce:	0c00      	lsrs	r0, r0, #16
- 80006d0:	3910      	subs	r1, #16
- 80006d2:	0a1b      	lsrs	r3, r3, #8
- 80006d4:	4298      	cmp	r0, r3
- 80006d6:	d301      	bcc.n	80006dc <__clzsi2+0x18>
- 80006d8:	0a00      	lsrs	r0, r0, #8
- 80006da:	3908      	subs	r1, #8
- 80006dc:	091b      	lsrs	r3, r3, #4
- 80006de:	4298      	cmp	r0, r3
- 80006e0:	d301      	bcc.n	80006e6 <__clzsi2+0x22>
- 80006e2:	0900      	lsrs	r0, r0, #4
- 80006e4:	3904      	subs	r1, #4
- 80006e6:	a202      	add	r2, pc, #8	@ (adr r2, 80006f0 <__clzsi2+0x2c>)
- 80006e8:	5c10      	ldrb	r0, [r2, r0]
- 80006ea:	1840      	adds	r0, r0, r1
- 80006ec:	4770      	bx	lr
- 80006ee:	46c0      	nop			@ (mov r8, r8)
- 80006f0:	02020304 	.word	0x02020304
- 80006f4:	01010101 	.word	0x01010101
+08000710 <__clzsi2>:
+ 8000710:	211c      	movs	r1, #28
+ 8000712:	2301      	movs	r3, #1
+ 8000714:	041b      	lsls	r3, r3, #16
+ 8000716:	4298      	cmp	r0, r3
+ 8000718:	d301      	bcc.n	800071e <__clzsi2+0xe>
+ 800071a:	0c00      	lsrs	r0, r0, #16
+ 800071c:	3910      	subs	r1, #16
+ 800071e:	0a1b      	lsrs	r3, r3, #8
+ 8000720:	4298      	cmp	r0, r3
+ 8000722:	d301      	bcc.n	8000728 <__clzsi2+0x18>
+ 8000724:	0a00      	lsrs	r0, r0, #8
+ 8000726:	3908      	subs	r1, #8
+ 8000728:	091b      	lsrs	r3, r3, #4
+ 800072a:	4298      	cmp	r0, r3
+ 800072c:	d301      	bcc.n	8000732 <__clzsi2+0x22>
+ 800072e:	0900      	lsrs	r0, r0, #4
+ 8000730:	3904      	subs	r1, #4
+ 8000732:	a202      	add	r2, pc, #8	@ (adr r2, 800073c <__clzsi2+0x2c>)
+ 8000734:	5c10      	ldrb	r0, [r2, r0]
+ 8000736:	1840      	adds	r0, r0, r1
+ 8000738:	4770      	bx	lr
+ 800073a:	46c0      	nop			@ (mov r8, r8)
+ 800073c:	02020304 	.word	0x02020304
+ 8000740:	01010101 	.word	0x01010101
 	...
 
-08000700 <CRC8_107_add>:
- */
+0800074c <CRC8_107_add>:
 
 #include "crc.h"
 
 void CRC8_107_add(CRC8_107 *ctx, uint8_t data)
 {
- 8000700:	b580      	push	{r7, lr}
- 8000702:	b084      	sub	sp, #16
- 8000704:	af00      	add	r7, sp, #0
- 8000706:	6078      	str	r0, [r7, #4]
- 8000708:	000a      	movs	r2, r1
- 800070a:	1cfb      	adds	r3, r7, #3
- 800070c:	701a      	strb	r2, [r3, #0]
     ctx->crc ^= ((uint32_t)data << 8);
- 800070e:	687b      	ldr	r3, [r7, #4]
- 8000710:	681a      	ldr	r2, [r3, #0]
- 8000712:	1cfb      	adds	r3, r7, #3
- 8000714:	781b      	ldrb	r3, [r3, #0]
- 8000716:	021b      	lsls	r3, r3, #8
- 8000718:	405a      	eors	r2, r3
- 800071a:	687b      	ldr	r3, [r7, #4]
- 800071c:	601a      	str	r2, [r3, #0]
+ 800074c:	6803      	ldr	r3, [r0, #0]
     for (size_t bit_n = 0; bit_n < 8; bit_n++) {
- 800071e:	2300      	movs	r3, #0
- 8000720:	60fb      	str	r3, [r7, #12]
- 8000722:	e013      	b.n	800074c <CRC8_107_add+0x4c>
         if (ctx->crc & 0x8000u) {
- 8000724:	687b      	ldr	r3, [r7, #4]
- 8000726:	681a      	ldr	r2, [r3, #0]
- 8000728:	2380      	movs	r3, #128	@ 0x80
- 800072a:	021b      	lsls	r3, r3, #8
- 800072c:	4013      	ands	r3, r2
- 800072e:	d005      	beq.n	800073c <CRC8_107_add+0x3c>
+ 800074e:	2280      	movs	r2, #128	@ 0x80
+    ctx->crc ^= ((uint32_t)data << 8);
+ 8000750:	0209      	lsls	r1, r1, #8
+ 8000752:	4059      	eors	r1, r3
+ 8000754:	2308      	movs	r3, #8
+{
+ 8000756:	b510      	push	{r4, lr}
             ctx->crc ^= ((uint32_t)0x1070u << 3);  // same as 0x8380
- 8000730:	687b      	ldr	r3, [r7, #4]
- 8000732:	681b      	ldr	r3, [r3, #0]
- 8000734:	4a09      	ldr	r2, [pc, #36]	@ (800075c <CRC8_107_add+0x5c>)
- 8000736:	405a      	eors	r2, r3
- 8000738:	687b      	ldr	r3, [r7, #4]
- 800073a:	601a      	str	r2, [r3, #0]
+ 8000758:	4c05      	ldr	r4, [pc, #20]	@ (8000770 <CRC8_107_add+0x24>)
+        if (ctx->crc & 0x8000u) {
+ 800075a:	0212      	lsls	r2, r2, #8
+ 800075c:	4211      	tst	r1, r2
+ 800075e:	d000      	beq.n	8000762 <CRC8_107_add+0x16>
+            ctx->crc ^= ((uint32_t)0x1070u << 3);  // same as 0x8380
+ 8000760:	4061      	eors	r1, r4
+    for (size_t bit_n = 0; bit_n < 8; bit_n++) {
+ 8000762:	3b01      	subs	r3, #1
         }
         ctx->crc <<= 1;
- 800073c:	687b      	ldr	r3, [r7, #4]
- 800073e:	681b      	ldr	r3, [r3, #0]
- 8000740:	005a      	lsls	r2, r3, #1
- 8000742:	687b      	ldr	r3, [r7, #4]
- 8000744:	601a      	str	r2, [r3, #0]
+ 8000764:	0049      	lsls	r1, r1, #1
     for (size_t bit_n = 0; bit_n < 8; bit_n++) {
- 8000746:	68fb      	ldr	r3, [r7, #12]
- 8000748:	3301      	adds	r3, #1
- 800074a:	60fb      	str	r3, [r7, #12]
- 800074c:	68fb      	ldr	r3, [r7, #12]
- 800074e:	2b07      	cmp	r3, #7
- 8000750:	d9e8      	bls.n	8000724 <CRC8_107_add+0x24>
+ 8000766:	2b00      	cmp	r3, #0
+ 8000768:	d1f8      	bne.n	800075c <CRC8_107_add+0x10>
     }
 }
- 8000752:	46c0      	nop			@ (mov r8, r8)
- 8000754:	46c0      	nop			@ (mov r8, r8)
- 8000756:	46bd      	mov	sp, r7
- 8000758:	b004      	add	sp, #16
- 800075a:	bd80      	pop	{r7, pc}
- 800075c:	00008380 	.word	0x00008380
+ 800076a:	6001      	str	r1, [r0, #0]
+ 800076c:	bd10      	pop	{r4, pc}
+ 800076e:	46c0      	nop			@ (mov r8, r8)
+ 8000770:	00008380 	.word	0x00008380
 
-08000760 <CRC8_107_getChecksum>:
+08000774 <CRC8_107_getChecksum>:
 
 uint8_t CRC8_107_getChecksum(const CRC8_107 *ctx)
 {
- 8000760:	b580      	push	{r7, lr}
- 8000762:	b082      	sub	sp, #8
- 8000764:	af00      	add	r7, sp, #0
- 8000766:	6078      	str	r0, [r7, #4]
     return (uint8_t)(ctx->crc >> 8);
- 8000768:	687b      	ldr	r3, [r7, #4]
- 800076a:	681b      	ldr	r3, [r3, #0]
- 800076c:	0a1b      	lsrs	r3, r3, #8
- 800076e:	b2db      	uxtb	r3, r3
+ 8000774:	6800      	ldr	r0, [r0, #0]
+ 8000776:	0a00      	lsrs	r0, r0, #8
+ 8000778:	b2c0      	uxtb	r0, r0
 }
- 8000770:	0018      	movs	r0, r3
- 8000772:	46bd      	mov	sp, r7
- 8000774:	b002      	add	sp, #8
- 8000776:	bd80      	pop	{r7, pc}
+ 800077a:	4770      	bx	lr
 
-08000778 <__NVIC_SystemReset>:
-/**
-  \brief   System Reset
-  \details Initiates a system reset request to reset the MCU.
- */
-__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
-{
- 8000778:	b580      	push	{r7, lr}
- 800077a:	af00      	add	r7, sp, #0
-  \details Acts as a special kind of Data Memory Barrier.
-           It completes when all explicit memory accesses before this instruction complete.
- */
-__STATIC_FORCEINLINE void __DSB(void)
-{
-  __ASM volatile ("dsb 0xF":::"memory");
- 800077c:	f3bf 8f4f 	dsb	sy
-}
- 8000780:	46c0      	nop			@ (mov r8, r8)
-  __DSB();                                                          /* Ensure all outstanding memory accesses included
-                                                                       buffered write are completed before reset */
-  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
- 8000782:	4b04      	ldr	r3, [pc, #16]	@ (8000794 <__NVIC_SystemReset+0x1c>)
- 8000784:	4a04      	ldr	r2, [pc, #16]	@ (8000798 <__NVIC_SystemReset+0x20>)
- 8000786:	60da      	str	r2, [r3, #12]
-  __ASM volatile ("dsb 0xF":::"memory");
- 8000788:	f3bf 8f4f 	dsb	sy
-}
- 800078c:	46c0      	nop			@ (mov r8, r8)
-                 SCB_AIRCR_SYSRESETREQ_Msk);
-  __DSB();                                                          /* Ensure completion of memory access */
-
-  for(;;)                                                           /* wait until reset */
-  {
-    __NOP();
- 800078e:	46c0      	nop			@ (mov r8, r8)
- 8000790:	e7fd      	b.n	800078e <__NVIC_SystemReset+0x16>
- 8000792:	46c0      	nop			@ (mov r8, r8)
- 8000794:	e000ed00 	.word	0xe000ed00
- 8000798:	05fa0004 	.word	0x05fa0004
-
-0800079c <clamp_i32>:
-    uint16_t pwm;  // 0..out_max
-    uint8_t  dir;  // 0 or 1
-} pid_motor_cmd_t;
-
-static inline int32_t clamp_i32(int32_t x, int32_t lo, int32_t hi)
-{
- 800079c:	b580      	push	{r7, lr}
- 800079e:	b084      	sub	sp, #16
- 80007a0:	af00      	add	r7, sp, #0
- 80007a2:	60f8      	str	r0, [r7, #12]
- 80007a4:	60b9      	str	r1, [r7, #8]
- 80007a6:	607a      	str	r2, [r7, #4]
-    if (x < lo) return lo;
- 80007a8:	68fa      	ldr	r2, [r7, #12]
- 80007aa:	68bb      	ldr	r3, [r7, #8]
- 80007ac:	429a      	cmp	r2, r3
- 80007ae:	da01      	bge.n	80007b4 <clamp_i32+0x18>
- 80007b0:	68bb      	ldr	r3, [r7, #8]
- 80007b2:	e006      	b.n	80007c2 <clamp_i32+0x26>
-    if (x > hi) return hi;
- 80007b4:	68fa      	ldr	r2, [r7, #12]
- 80007b6:	687b      	ldr	r3, [r7, #4]
- 80007b8:	429a      	cmp	r2, r3
- 80007ba:	dd01      	ble.n	80007c0 <clamp_i32+0x24>
- 80007bc:	687b      	ldr	r3, [r7, #4]
- 80007be:	e000      	b.n	80007c2 <clamp_i32+0x26>
-    return x;
- 80007c0:	68fb      	ldr	r3, [r7, #12]
-}
- 80007c2:	0018      	movs	r0, r3
- 80007c4:	46bd      	mov	sp, r7
- 80007c6:	b004      	add	sp, #16
- 80007c8:	bd80      	pop	{r7, pc}
-
-080007ca <pid_init>:
-                            int32_t kd,
-                            int32_t integrator_min,
-                            int32_t integrator_max,
-                            int32_t out_max,
-                            int32_t max_output_step)
-{
- 80007ca:	b580      	push	{r7, lr}
- 80007cc:	b084      	sub	sp, #16
- 80007ce:	af00      	add	r7, sp, #0
- 80007d0:	60f8      	str	r0, [r7, #12]
- 80007d2:	60b9      	str	r1, [r7, #8]
- 80007d4:	607a      	str	r2, [r7, #4]
- 80007d6:	603b      	str	r3, [r7, #0]
-    pid->kp = kp;
- 80007d8:	68fb      	ldr	r3, [r7, #12]
- 80007da:	68ba      	ldr	r2, [r7, #8]
- 80007dc:	601a      	str	r2, [r3, #0]
-    pid->ki = ki;
- 80007de:	68fb      	ldr	r3, [r7, #12]
- 80007e0:	687a      	ldr	r2, [r7, #4]
- 80007e2:	605a      	str	r2, [r3, #4]
-    pid->kd = kd;
- 80007e4:	68fb      	ldr	r3, [r7, #12]
- 80007e6:	683a      	ldr	r2, [r7, #0]
- 80007e8:	609a      	str	r2, [r3, #8]
-
-    pid->integrator = 0;
- 80007ea:	68fb      	ldr	r3, [r7, #12]
- 80007ec:	2200      	movs	r2, #0
- 80007ee:	60da      	str	r2, [r3, #12]
-    pid->prev_error = 0;
- 80007f0:	68fb      	ldr	r3, [r7, #12]
- 80007f2:	2200      	movs	r2, #0
- 80007f4:	611a      	str	r2, [r3, #16]
-
-    pid->integrator_min = integrator_min;
- 80007f6:	68fb      	ldr	r3, [r7, #12]
- 80007f8:	69ba      	ldr	r2, [r7, #24]
- 80007fa:	615a      	str	r2, [r3, #20]
-    pid->integrator_max = integrator_max;
- 80007fc:	68fb      	ldr	r3, [r7, #12]
- 80007fe:	69fa      	ldr	r2, [r7, #28]
- 8000800:	619a      	str	r2, [r3, #24]
-    pid->out_max        = out_max;
- 8000802:	68fb      	ldr	r3, [r7, #12]
- 8000804:	6a3a      	ldr	r2, [r7, #32]
- 8000806:	61da      	str	r2, [r3, #28]
-
-    pid->max_output_step = max_output_step;
- 8000808:	68fb      	ldr	r3, [r7, #12]
- 800080a:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
- 800080c:	621a      	str	r2, [r3, #32]
-    pid->last_output     = 0;
- 800080e:	68fb      	ldr	r3, [r7, #12]
- 8000810:	2200      	movs	r2, #0
- 8000812:	625a      	str	r2, [r3, #36]	@ 0x24
-}
- 8000814:	46c0      	nop			@ (mov r8, r8)
- 8000816:	46bd      	mov	sp, r7
- 8000818:	b004      	add	sp, #16
- 800081a:	bd80      	pop	{r7, pc}
-
-0800081c <pid_reset>:
-
-static inline void pid_reset(pid_i32_t *pid)
-{
- 800081c:	b580      	push	{r7, lr}
- 800081e:	b082      	sub	sp, #8
- 8000820:	af00      	add	r7, sp, #0
- 8000822:	6078      	str	r0, [r7, #4]
-    pid->integrator = 0;
- 8000824:	687b      	ldr	r3, [r7, #4]
- 8000826:	2200      	movs	r2, #0
- 8000828:	60da      	str	r2, [r3, #12]
-    pid->prev_error = 0;
- 800082a:	687b      	ldr	r3, [r7, #4]
- 800082c:	2200      	movs	r2, #0
- 800082e:	611a      	str	r2, [r3, #16]
-    pid->last_output = 0;
- 8000830:	687b      	ldr	r3, [r7, #4]
- 8000832:	2200      	movs	r2, #0
- 8000834:	625a      	str	r2, [r3, #36]	@ 0x24
-}
- 8000836:	46c0      	nop			@ (mov r8, r8)
- 8000838:	46bd      	mov	sp, r7
- 800083a:	b002      	add	sp, #8
- 800083c:	bd80      	pop	{r7, pc}
-
-0800083e <pid_update_motor>:
-
-static inline pid_motor_cmd_t pid_update_motor(pid_i32_t *pid,
-                                               int32_t setpoint,
-                                               int32_t position)
-{
- 800083e:	b580      	push	{r7, lr}
- 8000840:	b090      	sub	sp, #64	@ 0x40
- 8000842:	af00      	add	r7, sp, #0
- 8000844:	60f8      	str	r0, [r7, #12]
- 8000846:	60b9      	str	r1, [r7, #8]
- 8000848:	607a      	str	r2, [r7, #4]
-    pid_motor_cmd_t cmd;
-
-    int32_t error = setpoint - position;
- 800084a:	68ba      	ldr	r2, [r7, #8]
- 800084c:	687b      	ldr	r3, [r7, #4]
- 800084e:	1ad3      	subs	r3, r2, r3
- 8000850:	637b      	str	r3, [r7, #52]	@ 0x34
-
-    // Deadband: if within ±3 counts, hold position and reset integrator
-    if (error >= -3 && error <= 3) {
- 8000852:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
- 8000854:	3303      	adds	r3, #3
- 8000856:	db18      	blt.n	800088a <pid_update_motor+0x4c>
- 8000858:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
- 800085a:	2b03      	cmp	r3, #3
- 800085c:	dc15      	bgt.n	800088a <pid_update_motor+0x4c>
-        pid->integrator = 0;
- 800085e:	68fb      	ldr	r3, [r7, #12]
- 8000860:	2200      	movs	r2, #0
- 8000862:	60da      	str	r2, [r3, #12]
-        pid->prev_error = 0;
- 8000864:	68fb      	ldr	r3, [r7, #12]
- 8000866:	2200      	movs	r2, #0
- 8000868:	611a      	str	r2, [r3, #16]
-        pid->last_output = 0;
- 800086a:	68fb      	ldr	r3, [r7, #12]
- 800086c:	2200      	movs	r2, #0
- 800086e:	625a      	str	r2, [r3, #36]	@ 0x24
-        cmd.pwm = 0;
- 8000870:	2110      	movs	r1, #16
- 8000872:	187b      	adds	r3, r7, r1
- 8000874:	2200      	movs	r2, #0
- 8000876:	801a      	strh	r2, [r3, #0]
-        cmd.dir = 1;
- 8000878:	187b      	adds	r3, r7, r1
- 800087a:	2201      	movs	r2, #1
- 800087c:	709a      	strb	r2, [r3, #2]
-        return cmd;
- 800087e:	2314      	movs	r3, #20
- 8000880:	18fb      	adds	r3, r7, r3
- 8000882:	187a      	adds	r2, r7, r1
- 8000884:	6812      	ldr	r2, [r2, #0]
- 8000886:	601a      	str	r2, [r3, #0]
- 8000888:	e08e      	b.n	80009a8 <pid_update_motor+0x16a>
-    }
-
-    int32_t p = pid->kp * error;
- 800088a:	68fb      	ldr	r3, [r7, #12]
- 800088c:	681a      	ldr	r2, [r3, #0]
- 800088e:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
- 8000890:	4353      	muls	r3, r2
- 8000892:	633b      	str	r3, [r7, #48]	@ 0x30
-
-    int32_t i = pid->integrator + pid->ki * error;
- 8000894:	68fb      	ldr	r3, [r7, #12]
- 8000896:	68da      	ldr	r2, [r3, #12]
- 8000898:	68fb      	ldr	r3, [r7, #12]
- 800089a:	685b      	ldr	r3, [r3, #4]
- 800089c:	6b79      	ldr	r1, [r7, #52]	@ 0x34
- 800089e:	434b      	muls	r3, r1
- 80008a0:	18d3      	adds	r3, r2, r3
- 80008a2:	62fb      	str	r3, [r7, #44]	@ 0x2c
-    i = clamp_i32(i, pid->integrator_min, pid->integrator_max);
- 80008a4:	68fb      	ldr	r3, [r7, #12]
- 80008a6:	6959      	ldr	r1, [r3, #20]
- 80008a8:	68fb      	ldr	r3, [r7, #12]
- 80008aa:	699a      	ldr	r2, [r3, #24]
- 80008ac:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
- 80008ae:	0018      	movs	r0, r3
- 80008b0:	f7ff ff74 	bl	800079c <clamp_i32>
- 80008b4:	0003      	movs	r3, r0
- 80008b6:	62fb      	str	r3, [r7, #44]	@ 0x2c
-    pid->integrator = i;
- 80008b8:	68fb      	ldr	r3, [r7, #12]
- 80008ba:	6afa      	ldr	r2, [r7, #44]	@ 0x2c
- 80008bc:	60da      	str	r2, [r3, #12]
-
-    int32_t d_error = error - pid->prev_error;
- 80008be:	68fb      	ldr	r3, [r7, #12]
- 80008c0:	691b      	ldr	r3, [r3, #16]
- 80008c2:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
- 80008c4:	1ad3      	subs	r3, r2, r3
- 80008c6:	62bb      	str	r3, [r7, #40]	@ 0x28
-    int32_t d = pid->kd * d_error;
- 80008c8:	68fb      	ldr	r3, [r7, #12]
- 80008ca:	689a      	ldr	r2, [r3, #8]
- 80008cc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
- 80008ce:	4353      	muls	r3, r2
- 80008d0:	627b      	str	r3, [r7, #36]	@ 0x24
-    pid->prev_error = error;
- 80008d2:	68fb      	ldr	r3, [r7, #12]
- 80008d4:	6b7a      	ldr	r2, [r7, #52]	@ 0x34
- 80008d6:	611a      	str	r2, [r3, #16]
-
-    // Raw control effort
-    int32_t u_raw = p + i + d;
- 80008d8:	6b3a      	ldr	r2, [r7, #48]	@ 0x30
- 80008da:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
- 80008dc:	18d3      	adds	r3, r2, r3
- 80008de:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
- 80008e0:	18d3      	adds	r3, r2, r3
- 80008e2:	63fb      	str	r3, [r7, #60]	@ 0x3c
-
-    // Clamp to [-out_max, +out_max]
-    if (u_raw >  pid->out_max) u_raw =  pid->out_max;
- 80008e4:	68fb      	ldr	r3, [r7, #12]
- 80008e6:	69db      	ldr	r3, [r3, #28]
- 80008e8:	6bfa      	ldr	r2, [r7, #60]	@ 0x3c
- 80008ea:	429a      	cmp	r2, r3
- 80008ec:	dd02      	ble.n	80008f4 <pid_update_motor+0xb6>
- 80008ee:	68fb      	ldr	r3, [r7, #12]
- 80008f0:	69db      	ldr	r3, [r3, #28]
- 80008f2:	63fb      	str	r3, [r7, #60]	@ 0x3c
-    if (u_raw < -pid->out_max) u_raw = -pid->out_max;
- 80008f4:	68fb      	ldr	r3, [r7, #12]
- 80008f6:	69db      	ldr	r3, [r3, #28]
- 80008f8:	425b      	negs	r3, r3
- 80008fa:	6bfa      	ldr	r2, [r7, #60]	@ 0x3c
- 80008fc:	429a      	cmp	r2, r3
- 80008fe:	da03      	bge.n	8000908 <pid_update_motor+0xca>
- 8000900:	68fb      	ldr	r3, [r7, #12]
- 8000902:	69db      	ldr	r3, [r3, #28]
- 8000904:	425b      	negs	r3, r3
- 8000906:	63fb      	str	r3, [r7, #60]	@ 0x3c
-
-    // ---------- Slew limit: avoid instant full reverse ----------
-    int32_t u_prev = pid->last_output;
- 8000908:	68fb      	ldr	r3, [r7, #12]
- 800090a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 800090c:	623b      	str	r3, [r7, #32]
-    int32_t u = u_raw;
- 800090e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8000910:	63bb      	str	r3, [r7, #56]	@ 0x38
-
-    int32_t max_step = pid->max_output_step;
- 8000912:	68fb      	ldr	r3, [r7, #12]
- 8000914:	6a1b      	ldr	r3, [r3, #32]
- 8000916:	61fb      	str	r3, [r7, #28]
-    if (max_step > 0) {
- 8000918:	69fb      	ldr	r3, [r7, #28]
- 800091a:	2b00      	cmp	r3, #0
- 800091c:	dd18      	ble.n	8000950 <pid_update_motor+0x112>
-        int32_t du = u_raw - u_prev;
- 800091e:	6bfa      	ldr	r2, [r7, #60]	@ 0x3c
- 8000920:	6a3b      	ldr	r3, [r7, #32]
- 8000922:	1ad3      	subs	r3, r2, r3
- 8000924:	61bb      	str	r3, [r7, #24]
-
-        if (du > max_step) {
- 8000926:	69ba      	ldr	r2, [r7, #24]
- 8000928:	69fb      	ldr	r3, [r7, #28]
- 800092a:	429a      	cmp	r2, r3
- 800092c:	dd04      	ble.n	8000938 <pid_update_motor+0xfa>
-            u = u_prev + max_step;
- 800092e:	6a3a      	ldr	r2, [r7, #32]
- 8000930:	69fb      	ldr	r3, [r7, #28]
- 8000932:	18d3      	adds	r3, r2, r3
- 8000934:	63bb      	str	r3, [r7, #56]	@ 0x38
- 8000936:	e00b      	b.n	8000950 <pid_update_motor+0x112>
-        } else if (du < -max_step) {
- 8000938:	69fb      	ldr	r3, [r7, #28]
- 800093a:	425b      	negs	r3, r3
- 800093c:	69ba      	ldr	r2, [r7, #24]
- 800093e:	429a      	cmp	r2, r3
- 8000940:	da04      	bge.n	800094c <pid_update_motor+0x10e>
-            u = u_prev - max_step;
- 8000942:	6a3a      	ldr	r2, [r7, #32]
- 8000944:	69fb      	ldr	r3, [r7, #28]
- 8000946:	1ad3      	subs	r3, r2, r3
- 8000948:	63bb      	str	r3, [r7, #56]	@ 0x38
- 800094a:	e001      	b.n	8000950 <pid_update_motor+0x112>
-        } else {
-            u = u_raw;
- 800094c:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 800094e:	63bb      	str	r3, [r7, #56]	@ 0x38
-        }
-    }
-
-    // Save for next time
-    pid->last_output = u;
- 8000950:	68fb      	ldr	r3, [r7, #12]
- 8000952:	6bba      	ldr	r2, [r7, #56]	@ 0x38
- 8000954:	625a      	str	r2, [r3, #36]	@ 0x24
-
-    // Map signed u to dir + pwm
-    if (u >= 0) {
- 8000956:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 8000958:	2b00      	cmp	r3, #0
- 800095a:	db08      	blt.n	800096e <pid_update_motor+0x130>
-        cmd.dir = 1;
- 800095c:	2110      	movs	r1, #16
- 800095e:	187b      	adds	r3, r7, r1
- 8000960:	2201      	movs	r2, #1
- 8000962:	709a      	strb	r2, [r3, #2]
-        cmd.pwm = (uint16_t)u;
- 8000964:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 8000966:	b29a      	uxth	r2, r3
- 8000968:	187b      	adds	r3, r7, r1
- 800096a:	801a      	strh	r2, [r3, #0]
- 800096c:	e009      	b.n	8000982 <pid_update_motor+0x144>
-    } else {
-        cmd.dir = 0;
- 800096e:	2110      	movs	r1, #16
- 8000970:	187b      	adds	r3, r7, r1
- 8000972:	2200      	movs	r2, #0
- 8000974:	709a      	strb	r2, [r3, #2]
-        cmd.pwm = (uint16_t)(-u);
- 8000976:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 8000978:	b29b      	uxth	r3, r3
- 800097a:	425b      	negs	r3, r3
- 800097c:	b29a      	uxth	r2, r3
- 800097e:	187b      	adds	r3, r7, r1
- 8000980:	801a      	strh	r2, [r3, #0]
-    }
-
-    if (cmd.pwm > pid->out_max)
- 8000982:	2110      	movs	r1, #16
- 8000984:	187b      	adds	r3, r7, r1
- 8000986:	881b      	ldrh	r3, [r3, #0]
- 8000988:	001a      	movs	r2, r3
- 800098a:	68fb      	ldr	r3, [r7, #12]
- 800098c:	69db      	ldr	r3, [r3, #28]
- 800098e:	429a      	cmp	r2, r3
- 8000990:	dd04      	ble.n	800099c <pid_update_motor+0x15e>
-        cmd.pwm = (uint16_t)pid->out_max;
- 8000992:	68fb      	ldr	r3, [r7, #12]
- 8000994:	69db      	ldr	r3, [r3, #28]
- 8000996:	b29a      	uxth	r2, r3
- 8000998:	187b      	adds	r3, r7, r1
- 800099a:	801a      	strh	r2, [r3, #0]
-
-    return cmd;
- 800099c:	2314      	movs	r3, #20
- 800099e:	18fb      	adds	r3, r7, r3
- 80009a0:	2210      	movs	r2, #16
- 80009a2:	18ba      	adds	r2, r7, r2
- 80009a4:	6812      	ldr	r2, [r2, #0]
- 80009a6:	601a      	str	r2, [r3, #0]
-}
- 80009a8:	2314      	movs	r3, #20
- 80009aa:	18fa      	adds	r2, r7, r3
- 80009ac:	2300      	movs	r3, #0
- 80009ae:	8811      	ldrh	r1, [r2, #0]
- 80009b0:	0409      	lsls	r1, r1, #16
- 80009b2:	0c09      	lsrs	r1, r1, #16
- 80009b4:	0c1b      	lsrs	r3, r3, #16
- 80009b6:	041b      	lsls	r3, r3, #16
- 80009b8:	430b      	orrs	r3, r1
- 80009ba:	8852      	ldrh	r2, [r2, #2]
- 80009bc:	0412      	lsls	r2, r2, #16
- 80009be:	041b      	lsls	r3, r3, #16
- 80009c0:	0c1b      	lsrs	r3, r3, #16
- 80009c2:	4313      	orrs	r3, r2
- 80009c4:	0018      	movs	r0, r3
- 80009c6:	46bd      	mov	sp, r7
- 80009c8:	b010      	add	sp, #64	@ 0x40
- 80009ca:	bd80      	pop	{r7, pc}
-
-080009cc <CRC8_107_init>:
-typedef struct {
-    uint32_t crc;
-} CRC8_107;
-
-static inline void CRC8_107_init(CRC8_107 *ctx)
-{
- 80009cc:	b580      	push	{r7, lr}
- 80009ce:	b082      	sub	sp, #8
- 80009d0:	af00      	add	r7, sp, #0
- 80009d2:	6078      	str	r0, [r7, #4]
-    ctx->crc = 0x0u;
- 80009d4:	687b      	ldr	r3, [r7, #4]
- 80009d6:	2200      	movs	r2, #0
- 80009d8:	601a      	str	r2, [r3, #0]
-}
- 80009da:	46c0      	nop			@ (mov r8, r8)
- 80009dc:	46bd      	mov	sp, r7
- 80009de:	b002      	add	sp, #8
- 80009e0:	bd80      	pop	{r7, pc}
-	...
-
-080009e4 <main>:
-/**
-  * @brief  The application entry point.
-  * @retval int
-  */
-int main(void)
-{
- 80009e4:	b5f0      	push	{r4, r5, r6, r7, lr}
- 80009e6:	b08b      	sub	sp, #44	@ 0x2c
- 80009e8:	af04      	add	r7, sp, #16
-  /* USER CODE END 1 */
-
-  /* MCU Configuration--------------------------------------------------------*/
-
-  /* Reset of all peripherals, Initializes the Flash interface and the Systick. */
-  HAL_Init();
- 80009ea:	f003 fb02 	bl	8003ff2 <HAL_Init>
-
-  /* USER CODE BEGIN Init */
-
-  pid_init(&motor_pid,kp,ki,kd,i_min,i_max,PWM_MAX,pid_max_step);
- 80009ee:	4bc8      	ldr	r3, [pc, #800]	@ (8000d10 <main+0x32c>)
- 80009f0:	681c      	ldr	r4, [r3, #0]
- 80009f2:	4bc8      	ldr	r3, [pc, #800]	@ (8000d14 <main+0x330>)
- 80009f4:	681d      	ldr	r5, [r3, #0]
- 80009f6:	4bc8      	ldr	r3, [pc, #800]	@ (8000d18 <main+0x334>)
- 80009f8:	681e      	ldr	r6, [r3, #0]
- 80009fa:	4bc8      	ldr	r3, [pc, #800]	@ (8000d1c <main+0x338>)
- 80009fc:	681a      	ldr	r2, [r3, #0]
- 80009fe:	4bc8      	ldr	r3, [pc, #800]	@ (8000d20 <main+0x33c>)
- 8000a00:	6819      	ldr	r1, [r3, #0]
- 8000a02:	4bc8      	ldr	r3, [pc, #800]	@ (8000d24 <main+0x340>)
- 8000a04:	681b      	ldr	r3, [r3, #0]
- 8000a06:	48c8      	ldr	r0, [pc, #800]	@ (8000d28 <main+0x344>)
- 8000a08:	9303      	str	r3, [sp, #12]
- 8000a0a:	2396      	movs	r3, #150	@ 0x96
- 8000a0c:	011b      	lsls	r3, r3, #4
- 8000a0e:	9302      	str	r3, [sp, #8]
- 8000a10:	9101      	str	r1, [sp, #4]
- 8000a12:	9200      	str	r2, [sp, #0]
- 8000a14:	0033      	movs	r3, r6
- 8000a16:	002a      	movs	r2, r5
- 8000a18:	0021      	movs	r1, r4
- 8000a1a:	f7ff fed6 	bl	80007ca <pid_init>
-
-  /* USER CODE END Init */
-
-  /* Configure the system clock */
-  SystemClock_Config();
- 8000a1e:	f000 fb9d 	bl	800115c <SystemClock_Config>
-  /* USER CODE BEGIN SysInit */
-
-  /* USER CODE END SysInit */
-
-  /* Initialize all configured peripherals */
-  MX_GPIO_Init();
- 8000a22:	f000 fe79 	bl	8001718 <MX_GPIO_Init>
-  MX_DMA_Init();
- 8000a26:	f000 fe51 	bl	80016cc <MX_DMA_Init>
-  MX_TIM1_Init();
- 8000a2a:	f000 fbe5 	bl	80011f8 <MX_TIM1_Init>
-  MX_TIM3_Init();
- 8000a2e:	f000 fccf 	bl	80013d0 <MX_TIM3_Init>
-  MX_USART1_UART_Init();
- 8000a32:	f000 fda9 	bl	8001588 <MX_USART1_UART_Init>
-  MX_USART2_UART_Init();
- 8000a36:	f000 fdf5 	bl	8001624 <MX_USART2_UART_Init>
-  MX_TIM16_Init();
- 8000a3a:	f000 fd51 	bl	80014e0 <MX_TIM16_Init>
-  MX_TIM17_Init();
- 8000a3e:	f000 fd79 	bl	8001534 <MX_TIM17_Init>
-  MX_TIM14_Init();
- 8000a42:	f000 fd29 	bl	8001498 <MX_TIM14_Init>
-  /* USER CODE BEGIN 2 */
-
-  uint32_t * puuid = (uint32_t *)UUID;
- 8000a46:	4bb9      	ldr	r3, [pc, #740]	@ (8000d2c <main+0x348>)
- 8000a48:	613b      	str	r3, [r7, #16]
-  *puuid 		= HAL_GetUIDw0();
- 8000a4a:	f003 fb73 	bl	8004134 <HAL_GetUIDw0>
- 8000a4e:	0002      	movs	r2, r0
- 8000a50:	693b      	ldr	r3, [r7, #16]
- 8000a52:	601a      	str	r2, [r3, #0]
-  *(puuid+1)	= HAL_GetUIDw1();
- 8000a54:	693b      	ldr	r3, [r7, #16]
- 8000a56:	1d1c      	adds	r4, r3, #4
- 8000a58:	f003 fb76 	bl	8004148 <HAL_GetUIDw1>
- 8000a5c:	0003      	movs	r3, r0
- 8000a5e:	6023      	str	r3, [r4, #0]
-  *(puuid+2)	= HAL_GetUIDw2();
- 8000a60:	693b      	ldr	r3, [r7, #16]
- 8000a62:	3308      	adds	r3, #8
- 8000a64:	001c      	movs	r4, r3
- 8000a66:	f003 fb79 	bl	800415c <HAL_GetUIDw2>
- 8000a6a:	0003      	movs	r3, r0
- 8000a6c:	6023      	str	r3, [r4, #0]
-
-  // Start encoder timer (TIM3) in encoder mode
-  HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL);
- 8000a6e:	4bb0      	ldr	r3, [pc, #704]	@ (8000d30 <main+0x34c>)
- 8000a70:	213c      	movs	r1, #60	@ 0x3c
- 8000a72:	0018      	movs	r0, r3
- 8000a74:	f004 ffa6 	bl	80059c4 <HAL_TIM_Encoder_Start>
-
-  // Start PWM timer (TIM1) for motor control
-  HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1);  // Feed motor
- 8000a78:	4bae      	ldr	r3, [pc, #696]	@ (8000d34 <main+0x350>)
- 8000a7a:	2100      	movs	r1, #0
- 8000a7c:	0018      	movs	r0, r3
- 8000a7e:	f004 fe1b 	bl	80056b8 <HAL_TIM_PWM_Start>
-  HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_2);  // Feed motor
- 8000a82:	4bac      	ldr	r3, [pc, #688]	@ (8000d34 <main+0x350>)
- 8000a84:	2104      	movs	r1, #4
- 8000a86:	0018      	movs	r0, r3
- 8000a88:	f004 fe16 	bl	80056b8 <HAL_TIM_PWM_Start>
-  HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_3);  // Peel motor
- 8000a8c:	4ba9      	ldr	r3, [pc, #676]	@ (8000d34 <main+0x350>)
- 8000a8e:	2108      	movs	r1, #8
- 8000a90:	0018      	movs	r0, r3
- 8000a92:	f004 fe11 	bl	80056b8 <HAL_TIM_PWM_Start>
-  HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_4);  // Peel motor
- 8000a96:	4ba7      	ldr	r3, [pc, #668]	@ (8000d34 <main+0x350>)
- 8000a98:	210c      	movs	r1, #12
- 8000a9a:	0018      	movs	r0, r3
- 8000a9c:	f004 fe0c 	bl	80056b8 <HAL_TIM_PWM_Start>
-
-  // Start PID control timer (TIM14) with interrupt
-  HAL_TIM_Base_Start_IT(&htim14);
- 8000aa0:	4ba5      	ldr	r3, [pc, #660]	@ (8000d38 <main+0x354>)
- 8000aa2:	0018      	movs	r0, r3
- 8000aa4:	f004 fd54 	bl	8005550 <HAL_TIM_Base_Start_IT>
-
-  // Initialize stall detection
-  stall_detection_init();
- 8000aa8:	f002 fab8 	bl	800301c <stall_detection_init>
-
-  // Read floor address from EEPROM
-  floor_address = read_floor_address();
- 8000aac:	f002 fc81 	bl	80033b2 <read_floor_address>
- 8000ab0:	0003      	movs	r3, r0
- 8000ab2:	001a      	movs	r2, r3
- 8000ab4:	4ba1      	ldr	r3, [pc, #644]	@ (8000d3c <main+0x358>)
- 8000ab6:	701a      	strb	r2, [r3, #0]
-  if (floor_address == FLOOR_ADDRESS_NOT_DETECTED)
- 8000ab8:	4ba0      	ldr	r3, [pc, #640]	@ (8000d3c <main+0x358>)
- 8000aba:	781b      	ldrb	r3, [r3, #0]
- 8000abc:	2bff      	cmp	r3, #255	@ 0xff
- 8000abe:	d108      	bne.n	8000ad2 <main+0xee>
-  {
-	  floor_address_status = 0;
- 8000ac0:	4b9f      	ldr	r3, [pc, #636]	@ (8000d40 <main+0x35c>)
- 8000ac2:	2200      	movs	r2, #0
- 8000ac4:	701a      	strb	r2, [r3, #0]
-	  set_LED(1, 0, 0); // Red = EEPROM not detected
- 8000ac6:	2200      	movs	r2, #0
- 8000ac8:	2100      	movs	r1, #0
- 8000aca:	2001      	movs	r0, #1
- 8000acc:	f001 f84e 	bl	8001b6c <set_LED>
- 8000ad0:	e020      	b.n	8000b14 <main+0x130>
-  }
-  else if (floor_address == FLOOR_ADDRESS_NOT_PROGRAMMED)
- 8000ad2:	4b9a      	ldr	r3, [pc, #616]	@ (8000d3c <main+0x358>)
- 8000ad4:	781b      	ldrb	r3, [r3, #0]
- 8000ad6:	2b00      	cmp	r3, #0
- 8000ad8:	d108      	bne.n	8000aec <main+0x108>
-  {
-	  floor_address_status = 1;
- 8000ada:	4b99      	ldr	r3, [pc, #612]	@ (8000d40 <main+0x35c>)
- 8000adc:	2201      	movs	r2, #1
- 8000ade:	701a      	strb	r2, [r3, #0]
-	  set_LED(0, 0, 1); // Blue = not programmed
- 8000ae0:	2201      	movs	r2, #1
- 8000ae2:	2100      	movs	r1, #0
- 8000ae4:	2000      	movs	r0, #0
- 8000ae6:	f001 f841 	bl	8001b6c <set_LED>
- 8000aea:	e013      	b.n	8000b14 <main+0x130>
-  }
-  else
-  {
-	  floor_address_status = 2;
- 8000aec:	4b94      	ldr	r3, [pc, #592]	@ (8000d40 <main+0x35c>)
- 8000aee:	2202      	movs	r2, #2
- 8000af0:	701a      	strb	r2, [r3, #0]
-	  my_address = floor_address;
- 8000af2:	4b92      	ldr	r3, [pc, #584]	@ (8000d3c <main+0x358>)
- 8000af4:	781a      	ldrb	r2, [r3, #0]
- 8000af6:	4b93      	ldr	r3, [pc, #588]	@ (8000d44 <main+0x360>)
- 8000af8:	701a      	strb	r2, [r3, #0]
-	  set_LED(0, 1, 0); // Green briefly = valid address
- 8000afa:	2200      	movs	r2, #0
- 8000afc:	2101      	movs	r1, #1
- 8000afe:	2000      	movs	r0, #0
- 8000b00:	f001 f834 	bl	8001b6c <set_LED>
-	  HAL_Delay(200);
- 8000b04:	20c8      	movs	r0, #200	@ 0xc8
- 8000b06:	f003 faf1 	bl	80040ec <HAL_Delay>
-	  set_LED(0, 0, 0);
- 8000b0a:	2200      	movs	r2, #0
- 8000b0c:	2100      	movs	r1, #0
- 8000b0e:	2000      	movs	r0, #0
- 8000b10:	f001 f82c 	bl	8001b6c <set_LED>
-  }
-
-  HAL_UARTEx_ReceiveToIdle_DMA (&huart2,DMA_buffer,64);
- 8000b14:	498c      	ldr	r1, [pc, #560]	@ (8000d48 <main+0x364>)
- 8000b16:	4b8d      	ldr	r3, [pc, #564]	@ (8000d4c <main+0x368>)
- 8000b18:	2240      	movs	r2, #64	@ 0x40
- 8000b1a:	0018      	movs	r0, r3
- 8000b1c:	f006 fff6 	bl	8007b0c <HAL_UARTEx_ReceiveToIdle_DMA>
-
-  /* Infinite loop */
-  /* USER CODE BEGIN WHILE */
-  while (1)
-  {
-	  uint8_t sw1_state = HAL_GPIO_ReadPin(SW1_GPIO_Port, SW1_Pin); // 1 = released, 0 = pressed
- 8000b20:	230f      	movs	r3, #15
- 8000b22:	18fc      	adds	r4, r7, r3
- 8000b24:	2380      	movs	r3, #128	@ 0x80
- 8000b26:	009b      	lsls	r3, r3, #2
- 8000b28:	4a89      	ldr	r2, [pc, #548]	@ (8000d50 <main+0x36c>)
- 8000b2a:	0019      	movs	r1, r3
- 8000b2c:	0010      	movs	r0, r2
- 8000b2e:	f003 ffc3 	bl	8004ab8 <HAL_GPIO_ReadPin>
- 8000b32:	0003      	movs	r3, r0
- 8000b34:	7023      	strb	r3, [r4, #0]
-	  uint8_t sw2_state = HAL_GPIO_ReadPin(SW2_GPIO_Port, SW2_Pin);
- 8000b36:	250e      	movs	r5, #14
- 8000b38:	197c      	adds	r4, r7, r5
- 8000b3a:	2380      	movs	r3, #128	@ 0x80
- 8000b3c:	005b      	lsls	r3, r3, #1
- 8000b3e:	4a84      	ldr	r2, [pc, #528]	@ (8000d50 <main+0x36c>)
- 8000b40:	0019      	movs	r1, r3
- 8000b42:	0010      	movs	r0, r2
- 8000b44:	f003 ffb8 	bl	8004ab8 <HAL_GPIO_ReadPin>
- 8000b48:	0003      	movs	r3, r0
- 8000b4a:	7023      	strb	r3, [r4, #0]
-
-	  // Handle ongoing continuous drive - stop when button released
-	  if (driving)
- 8000b4c:	4b81      	ldr	r3, [pc, #516]	@ (8000d54 <main+0x370>)
- 8000b4e:	781b      	ldrb	r3, [r3, #0]
- 8000b50:	2b00      	cmp	r3, #0
- 8000b52:	d046      	beq.n	8000be2 <main+0x1fe>
-	  {
-		  if ((driving_direction && sw2_state) || (!driving_direction && sw1_state))
- 8000b54:	4b80      	ldr	r3, [pc, #512]	@ (8000d58 <main+0x374>)
- 8000b56:	781b      	ldrb	r3, [r3, #0]
- 8000b58:	2b00      	cmp	r3, #0
- 8000b5a:	d003      	beq.n	8000b64 <main+0x180>
- 8000b5c:	197b      	adds	r3, r7, r5
- 8000b5e:	781b      	ldrb	r3, [r3, #0]
- 8000b60:	2b00      	cmp	r3, #0
- 8000b62:	d108      	bne.n	8000b76 <main+0x192>
- 8000b64:	4b7c      	ldr	r3, [pc, #496]	@ (8000d58 <main+0x374>)
- 8000b66:	781b      	ldrb	r3, [r3, #0]
- 8000b68:	2b00      	cmp	r3, #0
- 8000b6a:	d123      	bne.n	8000bb4 <main+0x1d0>
- 8000b6c:	230f      	movs	r3, #15
- 8000b6e:	18fb      	adds	r3, r7, r3
- 8000b70:	781b      	ldrb	r3, [r3, #0]
- 8000b72:	2b00      	cmp	r3, #0
- 8000b74:	d01e      	beq.n	8000bb4 <main+0x1d0>
-		  {
-			  halt_all();
- 8000b76:	f001 fe3b 	bl	80027f0 <halt_all>
-			  driving = 0;
- 8000b7a:	4b76      	ldr	r3, [pc, #472]	@ (8000d54 <main+0x370>)
- 8000b7c:	2200      	movs	r2, #0
- 8000b7e:	701a      	strb	r2, [r3, #0]
-			  HAL_TIM_Base_Stop(&htim16);
- 8000b80:	4b76      	ldr	r3, [pc, #472]	@ (8000d5c <main+0x378>)
- 8000b82:	0018      	movs	r0, r3
- 8000b84:	f004 fcbe 	bl	8005504 <HAL_TIM_Base_Stop>
-			  HAL_TIM_Base_Stop(&htim17);
- 8000b88:	4b75      	ldr	r3, [pc, #468]	@ (8000d60 <main+0x37c>)
- 8000b8a:	0018      	movs	r0, r3
- 8000b8c:	f004 fcba 	bl	8005504 <HAL_TIM_Base_Stop>
-			  sw1_pressed = 0;
- 8000b90:	4b74      	ldr	r3, [pc, #464]	@ (8000d64 <main+0x380>)
- 8000b92:	2200      	movs	r2, #0
- 8000b94:	701a      	strb	r2, [r3, #0]
-			  sw2_pressed = 0;
- 8000b96:	4b74      	ldr	r3, [pc, #464]	@ (8000d68 <main+0x384>)
- 8000b98:	2200      	movs	r2, #0
- 8000b9a:	701a      	strb	r2, [r3, #0]
-			  sw1_long_handled = 0;
- 8000b9c:	4b73      	ldr	r3, [pc, #460]	@ (8000d6c <main+0x388>)
- 8000b9e:	2200      	movs	r2, #0
- 8000ba0:	701a      	strb	r2, [r3, #0]
-			  sw2_long_handled = 0;
- 8000ba2:	4b73      	ldr	r3, [pc, #460]	@ (8000d70 <main+0x38c>)
- 8000ba4:	2200      	movs	r2, #0
- 8000ba6:	701a      	strb	r2, [r3, #0]
-			  set_LED(0, 0, 0);
- 8000ba8:	2200      	movs	r2, #0
- 8000baa:	2100      	movs	r1, #0
- 8000bac:	2000      	movs	r0, #0
- 8000bae:	f000 ffdd 	bl	8001b6c <set_LED>
- 8000bb2:	e240      	b.n	8001036 <main+0x652>
-		  }
-		  else if (!drive_mode)
- 8000bb4:	4b6f      	ldr	r3, [pc, #444]	@ (8000d74 <main+0x390>)
- 8000bb6:	781b      	ldrb	r3, [r3, #0]
- 8000bb8:	2b00      	cmp	r3, #0
- 8000bba:	d000      	beq.n	8000bbe <main+0x1da>
- 8000bbc:	e23b      	b.n	8001036 <main+0x652>
-		  {
-			  // Tape mode: keep target ahead of current position
-			  if (driving_direction)
- 8000bbe:	4b66      	ldr	r3, [pc, #408]	@ (8000d58 <main+0x374>)
- 8000bc0:	781b      	ldrb	r3, [r3, #0]
- 8000bc2:	2b00      	cmp	r3, #0
- 8000bc4:	d006      	beq.n	8000bd4 <main+0x1f0>
-				  target_count = total_count + 10000;
- 8000bc6:	4b6c      	ldr	r3, [pc, #432]	@ (8000d78 <main+0x394>)
- 8000bc8:	681b      	ldr	r3, [r3, #0]
- 8000bca:	4a6c      	ldr	r2, [pc, #432]	@ (8000d7c <main+0x398>)
- 8000bcc:	189a      	adds	r2, r3, r2
- 8000bce:	4b6c      	ldr	r3, [pc, #432]	@ (8000d80 <main+0x39c>)
- 8000bd0:	601a      	str	r2, [r3, #0]
- 8000bd2:	e230      	b.n	8001036 <main+0x652>
-			  else
-				  target_count = total_count - 10000;
- 8000bd4:	4b68      	ldr	r3, [pc, #416]	@ (8000d78 <main+0x394>)
- 8000bd6:	681b      	ldr	r3, [r3, #0]
- 8000bd8:	4a6a      	ldr	r2, [pc, #424]	@ (8000d84 <main+0x3a0>)
- 8000bda:	189a      	adds	r2, r3, r2
- 8000bdc:	4b68      	ldr	r3, [pc, #416]	@ (8000d80 <main+0x39c>)
- 8000bde:	601a      	str	r2, [r3, #0]
- 8000be0:	e229      	b.n	8001036 <main+0x652>
-		  }
-	  }
-	  else if (both_pressed_handled)
- 8000be2:	4b69      	ldr	r3, [pc, #420]	@ (8000d88 <main+0x3a4>)
- 8000be4:	781b      	ldrb	r3, [r3, #0]
- 8000be6:	2b00      	cmp	r3, #0
- 8000be8:	d100      	bne.n	8000bec <main+0x208>
- 8000bea:	e072      	b.n	8000cd2 <main+0x2ee>
-	  {
-		  // Both-press mode: wait for release, handle long-hold actions
-		  if (sw1_state && sw2_state)
- 8000bec:	230f      	movs	r3, #15
- 8000bee:	18fb      	adds	r3, r7, r3
- 8000bf0:	781b      	ldrb	r3, [r3, #0]
- 8000bf2:	2b00      	cmp	r3, #0
- 8000bf4:	d026      	beq.n	8000c44 <main+0x260>
- 8000bf6:	230e      	movs	r3, #14
- 8000bf8:	18fb      	adds	r3, r7, r3
- 8000bfa:	781b      	ldrb	r3, [r3, #0]
- 8000bfc:	2b00      	cmp	r3, #0
- 8000bfe:	d021      	beq.n	8000c44 <main+0x260>
-		  {
-			  // Both released - show mode color briefly then clear
-			  both_pressed_handled = 0;
- 8000c00:	4b61      	ldr	r3, [pc, #388]	@ (8000d88 <main+0x3a4>)
- 8000c02:	2200      	movs	r2, #0
- 8000c04:	701a      	strb	r2, [r3, #0]
-			  HAL_TIM_Base_Stop(&htim16);
- 8000c06:	4b55      	ldr	r3, [pc, #340]	@ (8000d5c <main+0x378>)
- 8000c08:	0018      	movs	r0, r3
- 8000c0a:	f004 fc7b 	bl	8005504 <HAL_TIM_Base_Stop>
-			  HAL_TIM_Base_Stop(&htim17);
- 8000c0e:	4b54      	ldr	r3, [pc, #336]	@ (8000d60 <main+0x37c>)
- 8000c10:	0018      	movs	r0, r3
- 8000c12:	f004 fc77 	bl	8005504 <HAL_TIM_Base_Stop>
-			  sw1_pressed = 0;
- 8000c16:	4b53      	ldr	r3, [pc, #332]	@ (8000d64 <main+0x380>)
- 8000c18:	2200      	movs	r2, #0
- 8000c1a:	701a      	strb	r2, [r3, #0]
-			  sw2_pressed = 0;
- 8000c1c:	4b52      	ldr	r3, [pc, #328]	@ (8000d68 <main+0x384>)
- 8000c1e:	2200      	movs	r2, #0
- 8000c20:	701a      	strb	r2, [r3, #0]
-			  sw1_long_handled = 0;
- 8000c22:	4b52      	ldr	r3, [pc, #328]	@ (8000d6c <main+0x388>)
- 8000c24:	2200      	movs	r2, #0
- 8000c26:	701a      	strb	r2, [r3, #0]
-			  sw2_long_handled = 0;
- 8000c28:	4b51      	ldr	r3, [pc, #324]	@ (8000d70 <main+0x38c>)
- 8000c2a:	2200      	movs	r2, #0
- 8000c2c:	701a      	strb	r2, [r3, #0]
-			  HAL_Delay(400);
- 8000c2e:	23c8      	movs	r3, #200	@ 0xc8
- 8000c30:	005b      	lsls	r3, r3, #1
- 8000c32:	0018      	movs	r0, r3
- 8000c34:	f003 fa5a 	bl	80040ec <HAL_Delay>
-			  set_LED(0, 0, 0);
- 8000c38:	2200      	movs	r2, #0
- 8000c3a:	2100      	movs	r1, #0
- 8000c3c:	2000      	movs	r0, #0
- 8000c3e:	f000 ff95 	bl	8001b6c <set_LED>
- 8000c42:	e1f8      	b.n	8001036 <main+0x652>
-		  }
-		  else
-		  {
-			  // Still holding - check for long-hold actions
-			  uint32_t hold_time = HAL_GetTick() - both_pressed_start;
- 8000c44:	f003 fa48 	bl	80040d8 <HAL_GetTick>
- 8000c48:	0002      	movs	r2, r0
- 8000c4a:	4b50      	ldr	r3, [pc, #320]	@ (8000d8c <main+0x3a8>)
- 8000c4c:	681b      	ldr	r3, [r3, #0]
- 8000c4e:	1ad3      	subs	r3, r2, r3
- 8000c50:	607b      	str	r3, [r7, #4]
-			  if (hold_time > 2000 && hold_time < 2100)
- 8000c52:	687a      	ldr	r2, [r7, #4]
- 8000c54:	23fa      	movs	r3, #250	@ 0xfa
- 8000c56:	00db      	lsls	r3, r3, #3
- 8000c58:	429a      	cmp	r2, r3
- 8000c5a:	d906      	bls.n	8000c6a <main+0x286>
- 8000c5c:	687b      	ldr	r3, [r7, #4]
- 8000c5e:	4a4c      	ldr	r2, [pc, #304]	@ (8000d90 <main+0x3ac>)
- 8000c60:	4293      	cmp	r3, r2
- 8000c62:	d802      	bhi.n	8000c6a <main+0x286>
-			  {
-				  show_version();
- 8000c64:	f001 fe1f 	bl	80028a6 <show_version>
- 8000c68:	e1e5      	b.n	8001036 <main+0x652>
-			  }
-			  else if (hold_time > 4000 && hold_time < 6000)
- 8000c6a:	687a      	ldr	r2, [r7, #4]
- 8000c6c:	23fa      	movs	r3, #250	@ 0xfa
- 8000c6e:	011b      	lsls	r3, r3, #4
- 8000c70:	429a      	cmp	r2, r3
- 8000c72:	d91f      	bls.n	8000cb4 <main+0x2d0>
- 8000c74:	687b      	ldr	r3, [r7, #4]
- 8000c76:	4a47      	ldr	r2, [pc, #284]	@ (8000d94 <main+0x3b0>)
- 8000c78:	4293      	cmp	r3, r2
- 8000c7a:	d81b      	bhi.n	8000cb4 <main+0x2d0>
-			  {
-				  set_LED((hold_time / 100) % 2, 0, !((hold_time / 100) % 2));
- 8000c7c:	687b      	ldr	r3, [r7, #4]
- 8000c7e:	2164      	movs	r1, #100	@ 0x64
- 8000c80:	0018      	movs	r0, r3
- 8000c82:	f7ff fa41 	bl	8000108 <__udivsi3>
- 8000c86:	0003      	movs	r3, r0
- 8000c88:	b2db      	uxtb	r3, r3
- 8000c8a:	2201      	movs	r2, #1
- 8000c8c:	4013      	ands	r3, r2
- 8000c8e:	b2dc      	uxtb	r4, r3
- 8000c90:	687b      	ldr	r3, [r7, #4]
- 8000c92:	2164      	movs	r1, #100	@ 0x64
- 8000c94:	0018      	movs	r0, r3
- 8000c96:	f7ff fa37 	bl	8000108 <__udivsi3>
- 8000c9a:	0003      	movs	r3, r0
- 8000c9c:	001a      	movs	r2, r3
- 8000c9e:	2301      	movs	r3, #1
- 8000ca0:	4013      	ands	r3, r2
- 8000ca2:	425a      	negs	r2, r3
- 8000ca4:	4153      	adcs	r3, r2
- 8000ca6:	b2db      	uxtb	r3, r3
- 8000ca8:	001a      	movs	r2, r3
- 8000caa:	2100      	movs	r1, #0
- 8000cac:	0020      	movs	r0, r4
- 8000cae:	f000 ff5d 	bl	8001b6c <set_LED>
- 8000cb2:	e1c0      	b.n	8001036 <main+0x652>
-			  }
-			  else if (hold_time >= 6000)
- 8000cb4:	687b      	ldr	r3, [r7, #4]
- 8000cb6:	4a37      	ldr	r2, [pc, #220]	@ (8000d94 <main+0x3b0>)
- 8000cb8:	4293      	cmp	r3, r2
- 8000cba:	d800      	bhi.n	8000cbe <main+0x2da>
- 8000cbc:	e1bb      	b.n	8001036 <main+0x652>
-			  {
-				  set_LED(1, 0, 1);
- 8000cbe:	2201      	movs	r2, #1
- 8000cc0:	2100      	movs	r1, #0
- 8000cc2:	2001      	movs	r0, #1
- 8000cc4:	f000 ff52 	bl	8001b6c <set_LED>
-				  HAL_Delay(100);
- 8000cc8:	2064      	movs	r0, #100	@ 0x64
- 8000cca:	f003 fa0f 	bl	80040ec <HAL_Delay>
-				  NVIC_SystemReset();
- 8000cce:	f7ff fd53 	bl	8000778 <__NVIC_SystemReset>
-			  }
-		  }
-	  }
-	  else if (sw1_pressed || sw2_pressed)
- 8000cd2:	4b24      	ldr	r3, [pc, #144]	@ (8000d64 <main+0x380>)
- 8000cd4:	781b      	ldrb	r3, [r3, #0]
- 8000cd6:	2b00      	cmp	r3, #0
- 8000cd8:	d104      	bne.n	8000ce4 <main+0x300>
- 8000cda:	4b23      	ldr	r3, [pc, #140]	@ (8000d68 <main+0x384>)
- 8000cdc:	781b      	ldrb	r3, [r3, #0]
- 8000cde:	2b00      	cmp	r3, #0
- 8000ce0:	d100      	bne.n	8000ce4 <main+0x300>
- 8000ce2:	e1a8      	b.n	8001036 <main+0x652>
-	  {
-		  // At least one button pressed - use decision window
-		  uint16_t time1 = sw1_pressed ? htim16.Instance->CNT : 0;
- 8000ce4:	4b1f      	ldr	r3, [pc, #124]	@ (8000d64 <main+0x380>)
- 8000ce6:	781b      	ldrb	r3, [r3, #0]
- 8000ce8:	2b00      	cmp	r3, #0
- 8000cea:	d004      	beq.n	8000cf6 <main+0x312>
- 8000cec:	4b1b      	ldr	r3, [pc, #108]	@ (8000d5c <main+0x378>)
- 8000cee:	681b      	ldr	r3, [r3, #0]
- 8000cf0:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8000cf2:	b29a      	uxth	r2, r3
- 8000cf4:	e000      	b.n	8000cf8 <main+0x314>
- 8000cf6:	2200      	movs	r2, #0
- 8000cf8:	230c      	movs	r3, #12
- 8000cfa:	18fb      	adds	r3, r7, r3
- 8000cfc:	801a      	strh	r2, [r3, #0]
-		  uint16_t time2 = sw2_pressed ? htim17.Instance->CNT : 0;
- 8000cfe:	4b1a      	ldr	r3, [pc, #104]	@ (8000d68 <main+0x384>)
- 8000d00:	781b      	ldrb	r3, [r3, #0]
- 8000d02:	2b00      	cmp	r3, #0
- 8000d04:	d048      	beq.n	8000d98 <main+0x3b4>
- 8000d06:	4b16      	ldr	r3, [pc, #88]	@ (8000d60 <main+0x37c>)
- 8000d08:	681b      	ldr	r3, [r3, #0]
- 8000d0a:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8000d0c:	b29a      	uxth	r2, r3
- 8000d0e:	e044      	b.n	8000d9a <main+0x3b6>
- 8000d10:	20000004 	.word	0x20000004
- 8000d14:	20000008 	.word	0x20000008
- 8000d18:	2000000c 	.word	0x2000000c
- 8000d1c:	20000010 	.word	0x20000010
- 8000d20:	20000014 	.word	0x20000014
- 8000d24:	20000018 	.word	0x20000018
- 8000d28:	2000048c 	.word	0x2000048c
- 8000d2c:	200003b4 	.word	0x200003b4
- 8000d30:	20000098 	.word	0x20000098
- 8000d34:	2000004c 	.word	0x2000004c
- 8000d38:	200000e4 	.word	0x200000e4
- 8000d3c:	2000001f 	.word	0x2000001f
- 8000d40:	2000054c 	.word	0x2000054c
- 8000d44:	20000002 	.word	0x20000002
- 8000d48:	20000444 	.word	0x20000444
- 8000d4c:	2000025c 	.word	0x2000025c
- 8000d50:	50000400 	.word	0x50000400
- 8000d54:	200004e1 	.word	0x200004e1
- 8000d58:	200004e2 	.word	0x200004e2
- 8000d5c:	20000130 	.word	0x20000130
- 8000d60:	2000017c 	.word	0x2000017c
- 8000d64:	200003a8 	.word	0x200003a8
- 8000d68:	200003a9 	.word	0x200003a9
- 8000d6c:	200004e3 	.word	0x200004e3
- 8000d70:	200004e4 	.word	0x200004e4
- 8000d74:	200004e0 	.word	0x200004e0
- 8000d78:	20000484 	.word	0x20000484
- 8000d7c:	00002710 	.word	0x00002710
- 8000d80:	20000488 	.word	0x20000488
- 8000d84:	ffffd8f0 	.word	0xffffd8f0
- 8000d88:	200004e5 	.word	0x200004e5
- 8000d8c:	200004e8 	.word	0x200004e8
- 8000d90:	00000833 	.word	0x00000833
- 8000d94:	0000176f 	.word	0x0000176f
- 8000d98:	2200      	movs	r2, #0
- 8000d9a:	210a      	movs	r1, #10
- 8000d9c:	187b      	adds	r3, r7, r1
- 8000d9e:	801a      	strh	r2, [r3, #0]
-		  uint16_t max_time = (time1 > time2) ? time1 : time2;
- 8000da0:	2308      	movs	r3, #8
- 8000da2:	18fa      	adds	r2, r7, r3
- 8000da4:	187b      	adds	r3, r7, r1
- 8000da6:	210c      	movs	r1, #12
- 8000da8:	1879      	adds	r1, r7, r1
- 8000daa:	880c      	ldrh	r4, [r1, #0]
- 8000dac:	881b      	ldrh	r3, [r3, #0]
- 8000dae:	b298      	uxth	r0, r3
- 8000db0:	b2a1      	uxth	r1, r4
- 8000db2:	4288      	cmp	r0, r1
- 8000db4:	d200      	bcs.n	8000db8 <main+0x3d4>
- 8000db6:	1c23      	adds	r3, r4, #0
- 8000db8:	8013      	strh	r3, [r2, #0]
-
-		  // Wait 100ms decision window before acting (unless already past it)
-		  if (max_time < 100)
- 8000dba:	2308      	movs	r3, #8
- 8000dbc:	18fb      	adds	r3, r7, r3
- 8000dbe:	881b      	ldrh	r3, [r3, #0]
- 8000dc0:	2b63      	cmp	r3, #99	@ 0x63
- 8000dc2:	d800      	bhi.n	8000dc6 <main+0x3e2>
- 8000dc4:	e137      	b.n	8001036 <main+0x652>
-		  {
-			  // Still in decision window - do nothing yet
-		  }
-		  else if (sw1_pressed && sw2_pressed && !sw1_state && !sw2_state)
- 8000dc6:	4bd2      	ldr	r3, [pc, #840]	@ (8001110 <main+0x72c>)
- 8000dc8:	781b      	ldrb	r3, [r3, #0]
- 8000dca:	2b00      	cmp	r3, #0
- 8000dcc:	d02b      	beq.n	8000e26 <main+0x442>
- 8000dce:	4bd1      	ldr	r3, [pc, #836]	@ (8001114 <main+0x730>)
- 8000dd0:	781b      	ldrb	r3, [r3, #0]
- 8000dd2:	2b00      	cmp	r3, #0
- 8000dd4:	d027      	beq.n	8000e26 <main+0x442>
- 8000dd6:	230f      	movs	r3, #15
- 8000dd8:	18fb      	adds	r3, r7, r3
- 8000dda:	781b      	ldrb	r3, [r3, #0]
- 8000ddc:	2b00      	cmp	r3, #0
- 8000dde:	d122      	bne.n	8000e26 <main+0x442>
- 8000de0:	230e      	movs	r3, #14
- 8000de2:	18fb      	adds	r3, r7, r3
- 8000de4:	781b      	ldrb	r3, [r3, #0]
- 8000de6:	2b00      	cmp	r3, #0
- 8000de8:	d11d      	bne.n	8000e26 <main+0x442>
-		  {
-			  // Both pressed - toggle mode
-			  both_pressed_handled = 1;
- 8000dea:	4bcb      	ldr	r3, [pc, #812]	@ (8001118 <main+0x734>)
- 8000dec:	2201      	movs	r2, #1
- 8000dee:	701a      	strb	r2, [r3, #0]
-			  both_pressed_start = HAL_GetTick();
- 8000df0:	f003 f972 	bl	80040d8 <HAL_GetTick>
- 8000df4:	0002      	movs	r2, r0
- 8000df6:	4bc9      	ldr	r3, [pc, #804]	@ (800111c <main+0x738>)
- 8000df8:	601a      	str	r2, [r3, #0]
-			  if (drive_mode)
- 8000dfa:	4bc9      	ldr	r3, [pc, #804]	@ (8001120 <main+0x73c>)
- 8000dfc:	781b      	ldrb	r3, [r3, #0]
- 8000dfe:	2b00      	cmp	r3, #0
- 8000e00:	d008      	beq.n	8000e14 <main+0x430>
-			  {
-				  drive_mode = 0;
- 8000e02:	4bc7      	ldr	r3, [pc, #796]	@ (8001120 <main+0x73c>)
- 8000e04:	2200      	movs	r2, #0
- 8000e06:	701a      	strb	r2, [r3, #0]
-				  set_LED(0, 0, 1); // Blue = tape mode
- 8000e08:	2201      	movs	r2, #1
- 8000e0a:	2100      	movs	r1, #0
- 8000e0c:	2000      	movs	r0, #0
- 8000e0e:	f000 fead 	bl	8001b6c <set_LED>
-			  if (drive_mode)
- 8000e12:	e110      	b.n	8001036 <main+0x652>
-			  }
-			  else
-			  {
-				  drive_mode = 1;
- 8000e14:	4bc2      	ldr	r3, [pc, #776]	@ (8001120 <main+0x73c>)
- 8000e16:	2201      	movs	r2, #1
- 8000e18:	701a      	strb	r2, [r3, #0]
-				  set_LED(1, 1, 0); // Yellow = peel mode
- 8000e1a:	2200      	movs	r2, #0
- 8000e1c:	2101      	movs	r1, #1
- 8000e1e:	2001      	movs	r0, #1
- 8000e20:	f000 fea4 	bl	8001b6c <set_LED>
-			  if (drive_mode)
- 8000e24:	e107      	b.n	8001036 <main+0x652>
-			  }
-		  }
-		  else if (sw1_pressed && !sw2_pressed)
- 8000e26:	4bba      	ldr	r3, [pc, #744]	@ (8001110 <main+0x72c>)
- 8000e28:	781b      	ldrb	r3, [r3, #0]
- 8000e2a:	2b00      	cmp	r3, #0
- 8000e2c:	d100      	bne.n	8000e30 <main+0x44c>
- 8000e2e:	e06e      	b.n	8000f0e <main+0x52a>
- 8000e30:	4bb8      	ldr	r3, [pc, #736]	@ (8001114 <main+0x730>)
- 8000e32:	781b      	ldrb	r3, [r3, #0]
- 8000e34:	2b00      	cmp	r3, #0
- 8000e36:	d000      	beq.n	8000e3a <main+0x456>
- 8000e38:	e069      	b.n	8000f0e <main+0x52a>
-		  {
-			  // Single SW1 handling
-			  if (!sw1_state && time1 > 2000 && !sw1_long_handled)
- 8000e3a:	230f      	movs	r3, #15
- 8000e3c:	18fb      	adds	r3, r7, r3
- 8000e3e:	781b      	ldrb	r3, [r3, #0]
- 8000e40:	2b00      	cmp	r3, #0
- 8000e42:	d124      	bne.n	8000e8e <main+0x4aa>
- 8000e44:	230c      	movs	r3, #12
- 8000e46:	18fb      	adds	r3, r7, r3
- 8000e48:	881a      	ldrh	r2, [r3, #0]
- 8000e4a:	23fa      	movs	r3, #250	@ 0xfa
- 8000e4c:	00db      	lsls	r3, r3, #3
- 8000e4e:	429a      	cmp	r2, r3
- 8000e50:	d91d      	bls.n	8000e8e <main+0x4aa>
- 8000e52:	4bb4      	ldr	r3, [pc, #720]	@ (8001124 <main+0x740>)
- 8000e54:	781b      	ldrb	r3, [r3, #0]
- 8000e56:	2b00      	cmp	r3, #0
- 8000e58:	d119      	bne.n	8000e8e <main+0x4aa>
-			  {
-				  sw1_long_handled = 1;
- 8000e5a:	4bb2      	ldr	r3, [pc, #712]	@ (8001124 <main+0x740>)
- 8000e5c:	2201      	movs	r2, #1
- 8000e5e:	701a      	strb	r2, [r3, #0]
-				  set_LED(1, 1, 1);
- 8000e60:	2201      	movs	r2, #1
- 8000e62:	2101      	movs	r1, #1
- 8000e64:	2001      	movs	r0, #1
- 8000e66:	f000 fe81 	bl	8001b6c <set_LED>
-				  if (drive_mode)
- 8000e6a:	4bad      	ldr	r3, [pc, #692]	@ (8001120 <main+0x73c>)
- 8000e6c:	781b      	ldrb	r3, [r3, #0]
- 8000e6e:	2b00      	cmp	r3, #0
- 8000e70:	d003      	beq.n	8000e7a <main+0x496>
-					  peel_motor(0);
- 8000e72:	2000      	movs	r0, #0
- 8000e74:	f001 fbc6 	bl	8002604 <peel_motor>
- 8000e78:	e002      	b.n	8000e80 <main+0x49c>
-				  else
-					  drive_continuous(0);
- 8000e7a:	2000      	movs	r0, #0
- 8000e7c:	f001 fc8e 	bl	800279c <drive_continuous>
-				  driving = 1;
- 8000e80:	4ba9      	ldr	r3, [pc, #676]	@ (8001128 <main+0x744>)
- 8000e82:	2201      	movs	r2, #1
- 8000e84:	701a      	strb	r2, [r3, #0]
-				  driving_direction = 0;
- 8000e86:	4ba9      	ldr	r3, [pc, #676]	@ (800112c <main+0x748>)
- 8000e88:	2200      	movs	r2, #0
- 8000e8a:	701a      	strb	r2, [r3, #0]
- 8000e8c:	e03e      	b.n	8000f0c <main+0x528>
-			  }
-			  else if (sw1_state && time1 <= 2000 && time1 > 100)
- 8000e8e:	230f      	movs	r3, #15
- 8000e90:	18fb      	adds	r3, r7, r3
- 8000e92:	781b      	ldrb	r3, [r3, #0]
- 8000e94:	2b00      	cmp	r3, #0
- 8000e96:	d01e      	beq.n	8000ed6 <main+0x4f2>
- 8000e98:	210c      	movs	r1, #12
- 8000e9a:	187b      	adds	r3, r7, r1
- 8000e9c:	881a      	ldrh	r2, [r3, #0]
- 8000e9e:	23fa      	movs	r3, #250	@ 0xfa
- 8000ea0:	00db      	lsls	r3, r3, #3
- 8000ea2:	429a      	cmp	r2, r3
- 8000ea4:	d817      	bhi.n	8000ed6 <main+0x4f2>
- 8000ea6:	187b      	adds	r3, r7, r1
- 8000ea8:	881b      	ldrh	r3, [r3, #0]
- 8000eaa:	2b64      	cmp	r3, #100	@ 0x64
- 8000eac:	d913      	bls.n	8000ed6 <main+0x4f2>
-			  {
-				  set_LED(1, 1, 1);
- 8000eae:	2201      	movs	r2, #1
- 8000eb0:	2101      	movs	r1, #1
- 8000eb2:	2001      	movs	r0, #1
- 8000eb4:	f000 fe5a 	bl	8001b6c <set_LED>
-				  start_feed(20, 0);
- 8000eb8:	2100      	movs	r1, #0
- 8000eba:	2014      	movs	r0, #20
- 8000ebc:	f001 fd78 	bl	80029b0 <start_feed>
-				  HAL_TIM_Base_Stop(&htim16);
- 8000ec0:	4b9b      	ldr	r3, [pc, #620]	@ (8001130 <main+0x74c>)
- 8000ec2:	0018      	movs	r0, r3
- 8000ec4:	f004 fb1e 	bl	8005504 <HAL_TIM_Base_Stop>
-				  sw1_pressed = 0;
- 8000ec8:	4b91      	ldr	r3, [pc, #580]	@ (8001110 <main+0x72c>)
- 8000eca:	2200      	movs	r2, #0
- 8000ecc:	701a      	strb	r2, [r3, #0]
-				  sw1_long_handled = 0;
- 8000ece:	4b95      	ldr	r3, [pc, #596]	@ (8001124 <main+0x740>)
- 8000ed0:	2200      	movs	r2, #0
- 8000ed2:	701a      	strb	r2, [r3, #0]
- 8000ed4:	e01a      	b.n	8000f0c <main+0x528>
-			  }
-			  else if (sw1_state)
- 8000ed6:	230f      	movs	r3, #15
- 8000ed8:	18fb      	adds	r3, r7, r3
- 8000eda:	781b      	ldrb	r3, [r3, #0]
- 8000edc:	2b00      	cmp	r3, #0
- 8000ede:	d100      	bne.n	8000ee2 <main+0x4fe>
- 8000ee0:	e0a6      	b.n	8001030 <main+0x64c>
-			  {
-				  HAL_TIM_Base_Stop(&htim16);
- 8000ee2:	4b93      	ldr	r3, [pc, #588]	@ (8001130 <main+0x74c>)
- 8000ee4:	0018      	movs	r0, r3
- 8000ee6:	f004 fb0d 	bl	8005504 <HAL_TIM_Base_Stop>
-				  sw1_pressed = 0;
- 8000eea:	4b89      	ldr	r3, [pc, #548]	@ (8001110 <main+0x72c>)
- 8000eec:	2200      	movs	r2, #0
- 8000eee:	701a      	strb	r2, [r3, #0]
-				  sw1_long_handled = 0;
- 8000ef0:	4b8c      	ldr	r3, [pc, #560]	@ (8001124 <main+0x740>)
- 8000ef2:	2200      	movs	r2, #0
- 8000ef4:	701a      	strb	r2, [r3, #0]
-				  if (!driving) set_LED(0, 0, 0);
- 8000ef6:	4b8c      	ldr	r3, [pc, #560]	@ (8001128 <main+0x744>)
- 8000ef8:	781b      	ldrb	r3, [r3, #0]
- 8000efa:	2b00      	cmp	r3, #0
- 8000efc:	d000      	beq.n	8000f00 <main+0x51c>
- 8000efe:	e097      	b.n	8001030 <main+0x64c>
- 8000f00:	2200      	movs	r2, #0
- 8000f02:	2100      	movs	r1, #0
- 8000f04:	2000      	movs	r0, #0
- 8000f06:	f000 fe31 	bl	8001b6c <set_LED>
-			  if (!sw1_state && time1 > 2000 && !sw1_long_handled)
- 8000f0a:	e091      	b.n	8001030 <main+0x64c>
- 8000f0c:	e090      	b.n	8001030 <main+0x64c>
-			  }
-		  }
-		  else if (sw2_pressed && !sw1_pressed)
- 8000f0e:	4b81      	ldr	r3, [pc, #516]	@ (8001114 <main+0x730>)
- 8000f10:	781b      	ldrb	r3, [r3, #0]
- 8000f12:	2b00      	cmp	r3, #0
- 8000f14:	d100      	bne.n	8000f18 <main+0x534>
- 8000f16:	e06c      	b.n	8000ff2 <main+0x60e>
- 8000f18:	4b7d      	ldr	r3, [pc, #500]	@ (8001110 <main+0x72c>)
- 8000f1a:	781b      	ldrb	r3, [r3, #0]
- 8000f1c:	2b00      	cmp	r3, #0
- 8000f1e:	d000      	beq.n	8000f22 <main+0x53e>
- 8000f20:	e067      	b.n	8000ff2 <main+0x60e>
-		  {
-			  // Single SW2 handling
-			  if (!sw2_state && time2 > 2000 && !sw2_long_handled)
- 8000f22:	230e      	movs	r3, #14
- 8000f24:	18fb      	adds	r3, r7, r3
- 8000f26:	781b      	ldrb	r3, [r3, #0]
- 8000f28:	2b00      	cmp	r3, #0
- 8000f2a:	d124      	bne.n	8000f76 <main+0x592>
- 8000f2c:	230a      	movs	r3, #10
- 8000f2e:	18fb      	adds	r3, r7, r3
- 8000f30:	881a      	ldrh	r2, [r3, #0]
- 8000f32:	23fa      	movs	r3, #250	@ 0xfa
- 8000f34:	00db      	lsls	r3, r3, #3
- 8000f36:	429a      	cmp	r2, r3
- 8000f38:	d91d      	bls.n	8000f76 <main+0x592>
- 8000f3a:	4b7e      	ldr	r3, [pc, #504]	@ (8001134 <main+0x750>)
- 8000f3c:	781b      	ldrb	r3, [r3, #0]
- 8000f3e:	2b00      	cmp	r3, #0
- 8000f40:	d119      	bne.n	8000f76 <main+0x592>
-			  {
-				  sw2_long_handled = 1;
- 8000f42:	4b7c      	ldr	r3, [pc, #496]	@ (8001134 <main+0x750>)
- 8000f44:	2201      	movs	r2, #1
- 8000f46:	701a      	strb	r2, [r3, #0]
-				  set_LED(1, 1, 1);
- 8000f48:	2201      	movs	r2, #1
- 8000f4a:	2101      	movs	r1, #1
- 8000f4c:	2001      	movs	r0, #1
- 8000f4e:	f000 fe0d 	bl	8001b6c <set_LED>
-				  if (drive_mode)
- 8000f52:	4b73      	ldr	r3, [pc, #460]	@ (8001120 <main+0x73c>)
- 8000f54:	781b      	ldrb	r3, [r3, #0]
- 8000f56:	2b00      	cmp	r3, #0
- 8000f58:	d003      	beq.n	8000f62 <main+0x57e>
-					  peel_motor(1);
- 8000f5a:	2001      	movs	r0, #1
- 8000f5c:	f001 fb52 	bl	8002604 <peel_motor>
- 8000f60:	e002      	b.n	8000f68 <main+0x584>
-				  else
-					  drive_continuous(1);
- 8000f62:	2001      	movs	r0, #1
- 8000f64:	f001 fc1a 	bl	800279c <drive_continuous>
-				  driving = 1;
- 8000f68:	4b6f      	ldr	r3, [pc, #444]	@ (8001128 <main+0x744>)
- 8000f6a:	2201      	movs	r2, #1
- 8000f6c:	701a      	strb	r2, [r3, #0]
-				  driving_direction = 1;
- 8000f6e:	4b6f      	ldr	r3, [pc, #444]	@ (800112c <main+0x748>)
- 8000f70:	2201      	movs	r2, #1
- 8000f72:	701a      	strb	r2, [r3, #0]
- 8000f74:	e03c      	b.n	8000ff0 <main+0x60c>
-			  }
-			  else if (sw2_state && time2 <= 2000 && time2 > 100)
- 8000f76:	230e      	movs	r3, #14
- 8000f78:	18fb      	adds	r3, r7, r3
- 8000f7a:	781b      	ldrb	r3, [r3, #0]
- 8000f7c:	2b00      	cmp	r3, #0
- 8000f7e:	d01e      	beq.n	8000fbe <main+0x5da>
- 8000f80:	210a      	movs	r1, #10
- 8000f82:	187b      	adds	r3, r7, r1
- 8000f84:	881a      	ldrh	r2, [r3, #0]
- 8000f86:	23fa      	movs	r3, #250	@ 0xfa
- 8000f88:	00db      	lsls	r3, r3, #3
- 8000f8a:	429a      	cmp	r2, r3
- 8000f8c:	d817      	bhi.n	8000fbe <main+0x5da>
- 8000f8e:	187b      	adds	r3, r7, r1
- 8000f90:	881b      	ldrh	r3, [r3, #0]
- 8000f92:	2b64      	cmp	r3, #100	@ 0x64
- 8000f94:	d913      	bls.n	8000fbe <main+0x5da>
-			  {
-				  set_LED(1, 1, 1);
- 8000f96:	2201      	movs	r2, #1
- 8000f98:	2101      	movs	r1, #1
- 8000f9a:	2001      	movs	r0, #1
- 8000f9c:	f000 fde6 	bl	8001b6c <set_LED>
-				  start_feed(20, 1);
- 8000fa0:	2101      	movs	r1, #1
- 8000fa2:	2014      	movs	r0, #20
- 8000fa4:	f001 fd04 	bl	80029b0 <start_feed>
-				  HAL_TIM_Base_Stop(&htim17);
- 8000fa8:	4b63      	ldr	r3, [pc, #396]	@ (8001138 <main+0x754>)
- 8000faa:	0018      	movs	r0, r3
- 8000fac:	f004 faaa 	bl	8005504 <HAL_TIM_Base_Stop>
-				  sw2_pressed = 0;
- 8000fb0:	4b58      	ldr	r3, [pc, #352]	@ (8001114 <main+0x730>)
- 8000fb2:	2200      	movs	r2, #0
- 8000fb4:	701a      	strb	r2, [r3, #0]
-				  sw2_long_handled = 0;
- 8000fb6:	4b5f      	ldr	r3, [pc, #380]	@ (8001134 <main+0x750>)
- 8000fb8:	2200      	movs	r2, #0
- 8000fba:	701a      	strb	r2, [r3, #0]
- 8000fbc:	e018      	b.n	8000ff0 <main+0x60c>
-			  }
-			  else if (sw2_state)
- 8000fbe:	230e      	movs	r3, #14
- 8000fc0:	18fb      	adds	r3, r7, r3
- 8000fc2:	781b      	ldrb	r3, [r3, #0]
- 8000fc4:	2b00      	cmp	r3, #0
- 8000fc6:	d035      	beq.n	8001034 <main+0x650>
-			  {
-				  HAL_TIM_Base_Stop(&htim17);
- 8000fc8:	4b5b      	ldr	r3, [pc, #364]	@ (8001138 <main+0x754>)
- 8000fca:	0018      	movs	r0, r3
- 8000fcc:	f004 fa9a 	bl	8005504 <HAL_TIM_Base_Stop>
-				  sw2_pressed = 0;
- 8000fd0:	4b50      	ldr	r3, [pc, #320]	@ (8001114 <main+0x730>)
- 8000fd2:	2200      	movs	r2, #0
- 8000fd4:	701a      	strb	r2, [r3, #0]
-				  sw2_long_handled = 0;
- 8000fd6:	4b57      	ldr	r3, [pc, #348]	@ (8001134 <main+0x750>)
- 8000fd8:	2200      	movs	r2, #0
- 8000fda:	701a      	strb	r2, [r3, #0]
-				  if (!driving) set_LED(0, 0, 0);
- 8000fdc:	4b52      	ldr	r3, [pc, #328]	@ (8001128 <main+0x744>)
- 8000fde:	781b      	ldrb	r3, [r3, #0]
- 8000fe0:	2b00      	cmp	r3, #0
- 8000fe2:	d127      	bne.n	8001034 <main+0x650>
- 8000fe4:	2200      	movs	r2, #0
- 8000fe6:	2100      	movs	r1, #0
- 8000fe8:	2000      	movs	r0, #0
- 8000fea:	f000 fdbf 	bl	8001b6c <set_LED>
-			  if (!sw2_state && time2 > 2000 && !sw2_long_handled)
- 8000fee:	e021      	b.n	8001034 <main+0x650>
- 8000ff0:	e020      	b.n	8001034 <main+0x650>
-			  }
-		  }
-		  else if (sw1_state && sw2_state)
- 8000ff2:	230f      	movs	r3, #15
- 8000ff4:	18fb      	adds	r3, r7, r3
- 8000ff6:	781b      	ldrb	r3, [r3, #0]
- 8000ff8:	2b00      	cmp	r3, #0
- 8000ffa:	d01c      	beq.n	8001036 <main+0x652>
- 8000ffc:	230e      	movs	r3, #14
- 8000ffe:	18fb      	adds	r3, r7, r3
- 8001000:	781b      	ldrb	r3, [r3, #0]
- 8001002:	2b00      	cmp	r3, #0
- 8001004:	d017      	beq.n	8001036 <main+0x652>
-		  {
-			  // Both released without triggering both-press (one was released too fast)
-			  HAL_TIM_Base_Stop(&htim16);
- 8001006:	4b4a      	ldr	r3, [pc, #296]	@ (8001130 <main+0x74c>)
- 8001008:	0018      	movs	r0, r3
- 800100a:	f004 fa7b 	bl	8005504 <HAL_TIM_Base_Stop>
-			  HAL_TIM_Base_Stop(&htim17);
- 800100e:	4b4a      	ldr	r3, [pc, #296]	@ (8001138 <main+0x754>)
- 8001010:	0018      	movs	r0, r3
- 8001012:	f004 fa77 	bl	8005504 <HAL_TIM_Base_Stop>
-			  sw1_pressed = 0;
- 8001016:	4b3e      	ldr	r3, [pc, #248]	@ (8001110 <main+0x72c>)
- 8001018:	2200      	movs	r2, #0
- 800101a:	701a      	strb	r2, [r3, #0]
-			  sw2_pressed = 0;
- 800101c:	4b3d      	ldr	r3, [pc, #244]	@ (8001114 <main+0x730>)
- 800101e:	2200      	movs	r2, #0
- 8001020:	701a      	strb	r2, [r3, #0]
-			  sw1_long_handled = 0;
- 8001022:	4b40      	ldr	r3, [pc, #256]	@ (8001124 <main+0x740>)
- 8001024:	2200      	movs	r2, #0
- 8001026:	701a      	strb	r2, [r3, #0]
-			  sw2_long_handled = 0;
- 8001028:	4b42      	ldr	r3, [pc, #264]	@ (8001134 <main+0x750>)
- 800102a:	2200      	movs	r2, #0
- 800102c:	701a      	strb	r2, [r3, #0]
- 800102e:	e002      	b.n	8001036 <main+0x652>
-			  if (!sw1_state && time1 > 2000 && !sw1_long_handled)
- 8001030:	46c0      	nop			@ (mov r8, r8)
- 8001032:	e000      	b.n	8001036 <main+0x652>
-			  if (!sw2_state && time2 > 2000 && !sw2_long_handled)
- 8001034:	46c0      	nop			@ (mov r8, r8)
-		  }
-	  }
-
-	  // Update feed state machine
-	  feed_state_machine_update();
- 8001036:	f001 fd57 	bl	8002ae8 <feed_state_machine_update>
-
-	  // Ramp peel motor PWM
-	  peel_ramp_update();
- 800103a:	f001 fb05 	bl	8002648 <peel_ramp_update>
-
-	  // Debug output via USART1
-	  debug_output();
- 800103e:	f002 fb25 	bl	800368c <debug_output>
-
-	  // Turn off LED when feed completes
-	  if (feed_just_completed)
- 8001042:	4b3e      	ldr	r3, [pc, #248]	@ (800113c <main+0x758>)
- 8001044:	781b      	ldrb	r3, [r3, #0]
- 8001046:	b2db      	uxtb	r3, r3
- 8001048:	2b00      	cmp	r3, #0
- 800104a:	d013      	beq.n	8001074 <main+0x690>
-	  {
-		  feed_just_completed = 0;
- 800104c:	4b3b      	ldr	r3, [pc, #236]	@ (800113c <main+0x758>)
- 800104e:	2200      	movs	r2, #0
- 8001050:	701a      	strb	r2, [r3, #0]
-		  if (last_feed_status == STATUS_OK)
- 8001052:	4b3b      	ldr	r3, [pc, #236]	@ (8001140 <main+0x75c>)
- 8001054:	781b      	ldrb	r3, [r3, #0]
- 8001056:	2b00      	cmp	r3, #0
- 8001058:	d107      	bne.n	800106a <main+0x686>
-		  {
-			  set_LED(0, 0, 0); // Success - LED off
- 800105a:	2200      	movs	r2, #0
- 800105c:	2100      	movs	r1, #0
- 800105e:	2000      	movs	r0, #0
- 8001060:	f000 fd84 	bl	8001b6c <set_LED>
-			  // Reset position tracking to prevent overflow
-			  reset_position_if_needed();
- 8001064:	f002 fca4 	bl	80039b0 <reset_position_if_needed>
- 8001068:	e004      	b.n	8001074 <main+0x690>
-		  }
-		  else
-		  {
-			  set_LED(1, 0, 0); // Error - LED red
- 800106a:	2200      	movs	r2, #0
- 800106c:	2100      	movs	r1, #0
- 800106e:	2001      	movs	r0, #1
- 8001070:	f000 fd7c 	bl	8001b6c <set_LED>
-		  }
-	  }
-
-	  if (!msg_buffer1_empty) // msg 1 buffer has a message
- 8001074:	4b33      	ldr	r3, [pc, #204]	@ (8001144 <main+0x760>)
- 8001076:	781b      	ldrb	r3, [r3, #0]
- 8001078:	2b00      	cmp	r3, #0
- 800107a:	d121      	bne.n	80010c0 <main+0x6dc>
-	  {
-		  handleRS485Message(msg_buffer1, msg_buffer1_size);
- 800107c:	4b32      	ldr	r3, [pc, #200]	@ (8001148 <main+0x764>)
- 800107e:	781a      	ldrb	r2, [r3, #0]
- 8001080:	4b32      	ldr	r3, [pc, #200]	@ (800114c <main+0x768>)
- 8001082:	0011      	movs	r1, r2
- 8001084:	0018      	movs	r0, r3
- 8001086:	f000 fdd7 	bl	8001c38 <handleRS485Message>
-		  for (uint8_t i = 0; i<64 ; i++)
- 800108a:	2317      	movs	r3, #23
- 800108c:	18fb      	adds	r3, r7, r3
- 800108e:	2200      	movs	r2, #0
- 8001090:	701a      	strb	r2, [r3, #0]
- 8001092:	e00a      	b.n	80010aa <main+0x6c6>
-		  {
-			  msg_buffer1[i]=0;
- 8001094:	2017      	movs	r0, #23
- 8001096:	183b      	adds	r3, r7, r0
- 8001098:	781b      	ldrb	r3, [r3, #0]
- 800109a:	4a2c      	ldr	r2, [pc, #176]	@ (800114c <main+0x768>)
- 800109c:	2100      	movs	r1, #0
- 800109e:	54d1      	strb	r1, [r2, r3]
-		  for (uint8_t i = 0; i<64 ; i++)
- 80010a0:	183b      	adds	r3, r7, r0
- 80010a2:	781a      	ldrb	r2, [r3, #0]
- 80010a4:	183b      	adds	r3, r7, r0
- 80010a6:	3201      	adds	r2, #1
- 80010a8:	701a      	strb	r2, [r3, #0]
- 80010aa:	2317      	movs	r3, #23
- 80010ac:	18fb      	adds	r3, r7, r3
- 80010ae:	781b      	ldrb	r3, [r3, #0]
- 80010b0:	2b3f      	cmp	r3, #63	@ 0x3f
- 80010b2:	d9ef      	bls.n	8001094 <main+0x6b0>
-		  }
-		  msg_buffer1_size = 0;
- 80010b4:	4b24      	ldr	r3, [pc, #144]	@ (8001148 <main+0x764>)
- 80010b6:	2200      	movs	r2, #0
- 80010b8:	701a      	strb	r2, [r3, #0]
-		  msg_buffer1_empty = 1;
- 80010ba:	4b22      	ldr	r3, [pc, #136]	@ (8001144 <main+0x760>)
- 80010bc:	2201      	movs	r2, #1
- 80010be:	701a      	strb	r2, [r3, #0]
-	  }
-	  if (!msg_buffer2_empty) // msg 2 buffer has a message
- 80010c0:	4b23      	ldr	r3, [pc, #140]	@ (8001150 <main+0x76c>)
- 80010c2:	781b      	ldrb	r3, [r3, #0]
- 80010c4:	2b00      	cmp	r3, #0
- 80010c6:	d000      	beq.n	80010ca <main+0x6e6>
- 80010c8:	e52a      	b.n	8000b20 <main+0x13c>
-	  {
-		  handleRS485Message(msg_buffer2, msg_buffer2_size);
- 80010ca:	4b22      	ldr	r3, [pc, #136]	@ (8001154 <main+0x770>)
- 80010cc:	781a      	ldrb	r2, [r3, #0]
- 80010ce:	4b22      	ldr	r3, [pc, #136]	@ (8001158 <main+0x774>)
- 80010d0:	0011      	movs	r1, r2
- 80010d2:	0018      	movs	r0, r3
- 80010d4:	f000 fdb0 	bl	8001c38 <handleRS485Message>
-		  for (uint8_t i = 0; i<64 ; i++)
- 80010d8:	2316      	movs	r3, #22
- 80010da:	18fb      	adds	r3, r7, r3
- 80010dc:	2200      	movs	r2, #0
- 80010de:	701a      	strb	r2, [r3, #0]
- 80010e0:	e00a      	b.n	80010f8 <main+0x714>
-		  {
-			  msg_buffer2[i]=0;
- 80010e2:	2016      	movs	r0, #22
- 80010e4:	183b      	adds	r3, r7, r0
- 80010e6:	781b      	ldrb	r3, [r3, #0]
- 80010e8:	4a1b      	ldr	r2, [pc, #108]	@ (8001158 <main+0x774>)
- 80010ea:	2100      	movs	r1, #0
- 80010ec:	54d1      	strb	r1, [r2, r3]
-		  for (uint8_t i = 0; i<64 ; i++)
- 80010ee:	183b      	adds	r3, r7, r0
- 80010f0:	781a      	ldrb	r2, [r3, #0]
- 80010f2:	183b      	adds	r3, r7, r0
- 80010f4:	3201      	adds	r2, #1
- 80010f6:	701a      	strb	r2, [r3, #0]
- 80010f8:	2316      	movs	r3, #22
- 80010fa:	18fb      	adds	r3, r7, r3
- 80010fc:	781b      	ldrb	r3, [r3, #0]
- 80010fe:	2b3f      	cmp	r3, #63	@ 0x3f
- 8001100:	d9ef      	bls.n	80010e2 <main+0x6fe>
-		  }
-		  msg_buffer2_size = 0;
- 8001102:	4b14      	ldr	r3, [pc, #80]	@ (8001154 <main+0x770>)
- 8001104:	2200      	movs	r2, #0
- 8001106:	701a      	strb	r2, [r3, #0]
-		  msg_buffer2_empty = 1;
- 8001108:	4b11      	ldr	r3, [pc, #68]	@ (8001150 <main+0x76c>)
- 800110a:	2201      	movs	r2, #1
- 800110c:	701a      	strb	r2, [r3, #0]
-  {
- 800110e:	e507      	b.n	8000b20 <main+0x13c>
- 8001110:	200003a8 	.word	0x200003a8
- 8001114:	200003a9 	.word	0x200003a9
- 8001118:	200004e5 	.word	0x200004e5
- 800111c:	200004e8 	.word	0x200004e8
- 8001120:	200004e0 	.word	0x200004e0
- 8001124:	200004e3 	.word	0x200004e3
- 8001128:	200004e1 	.word	0x200004e1
- 800112c:	200004e2 	.word	0x200004e2
- 8001130:	20000130 	.word	0x20000130
- 8001134:	200004e4 	.word	0x200004e4
- 8001138:	2000017c 	.word	0x2000017c
- 800113c:	200004be 	.word	0x200004be
- 8001140:	200004bc 	.word	0x200004bc
- 8001144:	20000000 	.word	0x20000000
- 8001148:	200003c1 	.word	0x200003c1
- 800114c:	200003c4 	.word	0x200003c4
- 8001150:	20000001 	.word	0x20000001
- 8001154:	200003c2 	.word	0x200003c2
- 8001158:	20000404 	.word	0x20000404
-
-0800115c <SystemClock_Config>:
+0800077c <SystemClock_Config>:
 /**
   * @brief System Clock Configuration
   * @retval None
   */
 void SystemClock_Config(void)
 {
- 800115c:	b590      	push	{r4, r7, lr}
- 800115e:	b08d      	sub	sp, #52	@ 0x34
- 8001160:	af00      	add	r7, sp, #0
+ 800077c:	b570      	push	{r4, r5, r6, lr}
   RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- 8001162:	2414      	movs	r4, #20
- 8001164:	193b      	adds	r3, r7, r4
- 8001166:	0018      	movs	r0, r3
- 8001168:	231c      	movs	r3, #28
- 800116a:	001a      	movs	r2, r3
- 800116c:	2100      	movs	r1, #0
- 800116e:	f006 fda1 	bl	8007cb4 <memset>
   RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
- 8001172:	003b      	movs	r3, r7
- 8001174:	0018      	movs	r0, r3
- 8001176:	2314      	movs	r3, #20
- 8001178:	001a      	movs	r2, r3
- 800117a:	2100      	movs	r1, #0
- 800117c:	f006 fd9a 	bl	8007cb4 <memset>
 
   __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1);
- 8001180:	4b1c      	ldr	r3, [pc, #112]	@ (80011f4 <SystemClock_Config+0x98>)
- 8001182:	681b      	ldr	r3, [r3, #0]
- 8001184:	2207      	movs	r2, #7
- 8001186:	4393      	bics	r3, r2
- 8001188:	001a      	movs	r2, r3
- 800118a:	4b1a      	ldr	r3, [pc, #104]	@ (80011f4 <SystemClock_Config+0x98>)
- 800118c:	2101      	movs	r1, #1
- 800118e:	430a      	orrs	r2, r1
- 8001190:	601a      	str	r2, [r3, #0]
-
-  /** Initializes the RCC Oscillators according to the specified parameters
-  * in the RCC_OscInitTypeDef structure.
+ 800077e:	2607      	movs	r6, #7
+ 8000780:	2501      	movs	r5, #1
+{
+ 8000782:	b08c      	sub	sp, #48	@ 0x30
+  RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+ 8000784:	2218      	movs	r2, #24
+ 8000786:	2100      	movs	r1, #0
+ 8000788:	a806      	add	r0, sp, #24
+ 800078a:	f004 fcff 	bl	800518c <memset>
+  RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+ 800078e:	2214      	movs	r2, #20
+ 8000790:	2100      	movs	r1, #0
+ 8000792:	4668      	mov	r0, sp
+ 8000794:	f004 fcfa 	bl	800518c <memset>
+  __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1);
+ 8000798:	4a11      	ldr	r2, [pc, #68]	@ (80007e0 <SystemClock_Config+0x64>)
   */
   RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
- 8001192:	193b      	adds	r3, r7, r4
- 8001194:	2202      	movs	r2, #2
- 8001196:	601a      	str	r2, [r3, #0]
   RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- 8001198:	193b      	adds	r3, r7, r4
- 800119a:	2280      	movs	r2, #128	@ 0x80
- 800119c:	0052      	lsls	r2, r2, #1
- 800119e:	60da      	str	r2, [r3, #12]
   RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
- 80011a0:	193b      	adds	r3, r7, r4
- 80011a2:	2200      	movs	r2, #0
- 80011a4:	611a      	str	r2, [r3, #16]
   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
- 80011a6:	193b      	adds	r3, r7, r4
- 80011a8:	2240      	movs	r2, #64	@ 0x40
- 80011aa:	615a      	str	r2, [r3, #20]
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
- 80011ac:	193b      	adds	r3, r7, r4
- 80011ae:	0018      	movs	r0, r3
- 80011b0:	f003 fcf0 	bl	8004b94 <HAL_RCC_OscConfig>
- 80011b4:	1e03      	subs	r3, r0, #0
- 80011b6:	d001      	beq.n	80011bc <SystemClock_Config+0x60>
-  {
-    Error_Handler();
- 80011b8:	f002 fc48 	bl	8003a4c <Error_Handler>
-  }
-
-  /** Initializes the CPU, AHB and APB buses clocks
-  */
-  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
- 80011bc:	003b      	movs	r3, r7
- 80011be:	2207      	movs	r2, #7
- 80011c0:	601a      	str	r2, [r3, #0]
-                              |RCC_CLOCKTYPE_PCLK1;
-  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
- 80011c2:	003b      	movs	r3, r7
- 80011c4:	2200      	movs	r2, #0
- 80011c6:	605a      	str	r2, [r3, #4]
-  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
- 80011c8:	003b      	movs	r3, r7
- 80011ca:	2200      	movs	r2, #0
- 80011cc:	609a      	str	r2, [r3, #8]
-  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
- 80011ce:	003b      	movs	r3, r7
- 80011d0:	2200      	movs	r2, #0
- 80011d2:	60da      	str	r2, [r3, #12]
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
- 80011d4:	003b      	movs	r3, r7
- 80011d6:	2200      	movs	r2, #0
- 80011d8:	611a      	str	r2, [r3, #16]
-
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
- 80011da:	003b      	movs	r3, r7
- 80011dc:	2101      	movs	r1, #1
- 80011de:	0018      	movs	r0, r3
- 80011e0:	f003 febc 	bl	8004f5c <HAL_RCC_ClockConfig>
- 80011e4:	1e03      	subs	r3, r0, #0
- 80011e6:	d001      	beq.n	80011ec <SystemClock_Config+0x90>
-  {
-    Error_Handler();
- 80011e8:	f002 fc30 	bl	8003a4c <Error_Handler>
-  }
-}
- 80011ec:	46c0      	nop			@ (mov r8, r8)
- 80011ee:	46bd      	mov	sp, r7
- 80011f0:	b00d      	add	sp, #52	@ 0x34
- 80011f2:	bd90      	pop	{r4, r7, pc}
- 80011f4:	40022000 	.word	0x40022000
-
-080011f8 <MX_TIM1_Init>:
-  * @brief TIM1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_TIM1_Init(void)
-{
- 80011f8:	b580      	push	{r7, lr}
- 80011fa:	b09c      	sub	sp, #112	@ 0x70
- 80011fc:	af00      	add	r7, sp, #0
-
-  /* USER CODE BEGIN TIM1_Init 0 */
-
-  /* USER CODE END TIM1_Init 0 */
-
-  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
- 80011fe:	2360      	movs	r3, #96	@ 0x60
- 8001200:	18fb      	adds	r3, r7, r3
- 8001202:	0018      	movs	r0, r3
- 8001204:	2310      	movs	r3, #16
- 8001206:	001a      	movs	r2, r3
- 8001208:	2100      	movs	r1, #0
- 800120a:	f006 fd53 	bl	8007cb4 <memset>
-  TIM_MasterConfigTypeDef sMasterConfig = {0};
- 800120e:	2354      	movs	r3, #84	@ 0x54
- 8001210:	18fb      	adds	r3, r7, r3
- 8001212:	0018      	movs	r0, r3
- 8001214:	230c      	movs	r3, #12
- 8001216:	001a      	movs	r2, r3
- 8001218:	2100      	movs	r1, #0
- 800121a:	f006 fd4b 	bl	8007cb4 <memset>
-  TIM_OC_InitTypeDef sConfigOC = {0};
- 800121e:	2338      	movs	r3, #56	@ 0x38
- 8001220:	18fb      	adds	r3, r7, r3
- 8001222:	0018      	movs	r0, r3
- 8001224:	231c      	movs	r3, #28
- 8001226:	001a      	movs	r2, r3
- 8001228:	2100      	movs	r1, #0
- 800122a:	f006 fd43 	bl	8007cb4 <memset>
-  TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
- 800122e:	1d3b      	adds	r3, r7, #4
- 8001230:	0018      	movs	r0, r3
- 8001232:	2334      	movs	r3, #52	@ 0x34
- 8001234:	001a      	movs	r2, r3
- 8001236:	2100      	movs	r1, #0
- 8001238:	f006 fd3c 	bl	8007cb4 <memset>
-
-  /* USER CODE BEGIN TIM1_Init 1 */
-
-  /* USER CODE END TIM1_Init 1 */
-  htim1.Instance = TIM1;
- 800123c:	4b62      	ldr	r3, [pc, #392]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 800123e:	4a63      	ldr	r2, [pc, #396]	@ (80013cc <MX_TIM1_Init+0x1d4>)
- 8001240:	601a      	str	r2, [r3, #0]
-  htim1.Init.Prescaler = 0;
- 8001242:	4b61      	ldr	r3, [pc, #388]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 8001244:	2200      	movs	r2, #0
- 8001246:	605a      	str	r2, [r3, #4]
-  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8001248:	4b5f      	ldr	r3, [pc, #380]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 800124a:	2200      	movs	r2, #0
- 800124c:	609a      	str	r2, [r3, #8]
-  htim1.Init.Period = 2400;
- 800124e:	4b5e      	ldr	r3, [pc, #376]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 8001250:	2296      	movs	r2, #150	@ 0x96
- 8001252:	0112      	lsls	r2, r2, #4
- 8001254:	60da      	str	r2, [r3, #12]
-  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8001256:	4b5c      	ldr	r3, [pc, #368]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 8001258:	2200      	movs	r2, #0
- 800125a:	611a      	str	r2, [r3, #16]
-  htim1.Init.RepetitionCounter = 0;
- 800125c:	4b5a      	ldr	r3, [pc, #360]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 800125e:	2200      	movs	r2, #0
- 8001260:	615a      	str	r2, [r3, #20]
-  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8001262:	4b59      	ldr	r3, [pc, #356]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 8001264:	2200      	movs	r2, #0
- 8001266:	619a      	str	r2, [r3, #24]
-  if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
- 8001268:	4b57      	ldr	r3, [pc, #348]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 800126a:	0018      	movs	r0, r3
- 800126c:	f004 f8f2 	bl	8005454 <HAL_TIM_Base_Init>
- 8001270:	1e03      	subs	r3, r0, #0
- 8001272:	d001      	beq.n	8001278 <MX_TIM1_Init+0x80>
-  {
-    Error_Handler();
- 8001274:	f002 fbea 	bl	8003a4c <Error_Handler>
-  }
-  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
- 8001278:	2160      	movs	r1, #96	@ 0x60
- 800127a:	187b      	adds	r3, r7, r1
- 800127c:	2280      	movs	r2, #128	@ 0x80
- 800127e:	0152      	lsls	r2, r2, #5
- 8001280:	601a      	str	r2, [r3, #0]
-  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
- 8001282:	187a      	adds	r2, r7, r1
- 8001284:	4b50      	ldr	r3, [pc, #320]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 8001286:	0011      	movs	r1, r2
- 8001288:	0018      	movs	r0, r3
- 800128a:	f004 fe47 	bl	8005f1c <HAL_TIM_ConfigClockSource>
- 800128e:	1e03      	subs	r3, r0, #0
- 8001290:	d001      	beq.n	8001296 <MX_TIM1_Init+0x9e>
-  {
-    Error_Handler();
- 8001292:	f002 fbdb 	bl	8003a4c <Error_Handler>
-  }
-  if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
- 8001296:	4b4c      	ldr	r3, [pc, #304]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 8001298:	0018      	movs	r0, r3
- 800129a:	f004 f9ad 	bl	80055f8 <HAL_TIM_PWM_Init>
- 800129e:	1e03      	subs	r3, r0, #0
- 80012a0:	d001      	beq.n	80012a6 <MX_TIM1_Init+0xae>
-  {
-    Error_Handler();
- 80012a2:	f002 fbd3 	bl	8003a4c <Error_Handler>
-  }
-  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 80012a6:	2154      	movs	r1, #84	@ 0x54
- 80012a8:	187b      	adds	r3, r7, r1
- 80012aa:	2200      	movs	r2, #0
- 80012ac:	601a      	str	r2, [r3, #0]
-  sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
- 80012ae:	187b      	adds	r3, r7, r1
- 80012b0:	2200      	movs	r2, #0
- 80012b2:	605a      	str	r2, [r3, #4]
-  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 80012b4:	187b      	adds	r3, r7, r1
- 80012b6:	2200      	movs	r2, #0
- 80012b8:	609a      	str	r2, [r3, #8]
-  if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
- 80012ba:	187a      	adds	r2, r7, r1
- 80012bc:	4b42      	ldr	r3, [pc, #264]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 80012be:	0011      	movs	r1, r2
- 80012c0:	0018      	movs	r0, r3
- 80012c2:	f005 faf9 	bl	80068b8 <HAL_TIMEx_MasterConfigSynchronization>
- 80012c6:	1e03      	subs	r3, r0, #0
- 80012c8:	d001      	beq.n	80012ce <MX_TIM1_Init+0xd6>
-  {
-    Error_Handler();
- 80012ca:	f002 fbbf 	bl	8003a4c <Error_Handler>
-  }
-  sConfigOC.OCMode = TIM_OCMODE_PWM1;
- 80012ce:	2138      	movs	r1, #56	@ 0x38
- 80012d0:	187b      	adds	r3, r7, r1
- 80012d2:	2260      	movs	r2, #96	@ 0x60
- 80012d4:	601a      	str	r2, [r3, #0]
-  sConfigOC.Pulse = 0;
- 80012d6:	187b      	adds	r3, r7, r1
- 80012d8:	2200      	movs	r2, #0
- 80012da:	605a      	str	r2, [r3, #4]
-  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
- 80012dc:	187b      	adds	r3, r7, r1
- 80012de:	2200      	movs	r2, #0
- 80012e0:	609a      	str	r2, [r3, #8]
-  sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
- 80012e2:	187b      	adds	r3, r7, r1
- 80012e4:	2200      	movs	r2, #0
- 80012e6:	60da      	str	r2, [r3, #12]
-  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
- 80012e8:	187b      	adds	r3, r7, r1
- 80012ea:	2200      	movs	r2, #0
- 80012ec:	611a      	str	r2, [r3, #16]
-  sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
- 80012ee:	187b      	adds	r3, r7, r1
- 80012f0:	2200      	movs	r2, #0
- 80012f2:	615a      	str	r2, [r3, #20]
-  sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
- 80012f4:	187b      	adds	r3, r7, r1
- 80012f6:	2200      	movs	r2, #0
- 80012f8:	619a      	str	r2, [r3, #24]
-  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
- 80012fa:	1879      	adds	r1, r7, r1
- 80012fc:	4b32      	ldr	r3, [pc, #200]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 80012fe:	2200      	movs	r2, #0
- 8001300:	0018      	movs	r0, r3
- 8001302:	f004 fd0b 	bl	8005d1c <HAL_TIM_PWM_ConfigChannel>
- 8001306:	1e03      	subs	r3, r0, #0
- 8001308:	d001      	beq.n	800130e <MX_TIM1_Init+0x116>
-  {
-    Error_Handler();
- 800130a:	f002 fb9f 	bl	8003a4c <Error_Handler>
-  }
-  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
- 800130e:	2338      	movs	r3, #56	@ 0x38
- 8001310:	18f9      	adds	r1, r7, r3
- 8001312:	4b2d      	ldr	r3, [pc, #180]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 8001314:	2204      	movs	r2, #4
- 8001316:	0018      	movs	r0, r3
- 8001318:	f004 fd00 	bl	8005d1c <HAL_TIM_PWM_ConfigChannel>
- 800131c:	1e03      	subs	r3, r0, #0
- 800131e:	d001      	beq.n	8001324 <MX_TIM1_Init+0x12c>
-  {
-    Error_Handler();
- 8001320:	f002 fb94 	bl	8003a4c <Error_Handler>
-  }
-  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
- 8001324:	2338      	movs	r3, #56	@ 0x38
- 8001326:	18f9      	adds	r1, r7, r3
- 8001328:	4b27      	ldr	r3, [pc, #156]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 800132a:	2208      	movs	r2, #8
- 800132c:	0018      	movs	r0, r3
- 800132e:	f004 fcf5 	bl	8005d1c <HAL_TIM_PWM_ConfigChannel>
- 8001332:	1e03      	subs	r3, r0, #0
- 8001334:	d001      	beq.n	800133a <MX_TIM1_Init+0x142>
-  {
-    Error_Handler();
- 8001336:	f002 fb89 	bl	8003a4c <Error_Handler>
-  }
-  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
- 800133a:	2338      	movs	r3, #56	@ 0x38
- 800133c:	18f9      	adds	r1, r7, r3
- 800133e:	4b22      	ldr	r3, [pc, #136]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 8001340:	220c      	movs	r2, #12
- 8001342:	0018      	movs	r0, r3
- 8001344:	f004 fcea 	bl	8005d1c <HAL_TIM_PWM_ConfigChannel>
- 8001348:	1e03      	subs	r3, r0, #0
- 800134a:	d001      	beq.n	8001350 <MX_TIM1_Init+0x158>
-  {
-    Error_Handler();
- 800134c:	f002 fb7e 	bl	8003a4c <Error_Handler>
-  }
-  sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
- 8001350:	1d3b      	adds	r3, r7, #4
- 8001352:	2200      	movs	r2, #0
- 8001354:	601a      	str	r2, [r3, #0]
-  sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
- 8001356:	1d3b      	adds	r3, r7, #4
- 8001358:	2200      	movs	r2, #0
- 800135a:	605a      	str	r2, [r3, #4]
-  sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
- 800135c:	1d3b      	adds	r3, r7, #4
- 800135e:	2200      	movs	r2, #0
- 8001360:	609a      	str	r2, [r3, #8]
-  sBreakDeadTimeConfig.DeadTime = 0;
- 8001362:	1d3b      	adds	r3, r7, #4
- 8001364:	2200      	movs	r2, #0
- 8001366:	60da      	str	r2, [r3, #12]
-  sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
- 8001368:	1d3b      	adds	r3, r7, #4
- 800136a:	2200      	movs	r2, #0
- 800136c:	611a      	str	r2, [r3, #16]
-  sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
- 800136e:	1d3b      	adds	r3, r7, #4
- 8001370:	2280      	movs	r2, #128	@ 0x80
- 8001372:	0192      	lsls	r2, r2, #6
- 8001374:	615a      	str	r2, [r3, #20]
-  sBreakDeadTimeConfig.BreakFilter = 0;
- 8001376:	1d3b      	adds	r3, r7, #4
- 8001378:	2200      	movs	r2, #0
- 800137a:	619a      	str	r2, [r3, #24]
-  sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT;
- 800137c:	1d3b      	adds	r3, r7, #4
- 800137e:	2200      	movs	r2, #0
- 8001380:	61da      	str	r2, [r3, #28]
-  sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
- 8001382:	1d3b      	adds	r3, r7, #4
- 8001384:	2200      	movs	r2, #0
- 8001386:	621a      	str	r2, [r3, #32]
-  sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
- 8001388:	1d3b      	adds	r3, r7, #4
- 800138a:	2280      	movs	r2, #128	@ 0x80
- 800138c:	0492      	lsls	r2, r2, #18
- 800138e:	625a      	str	r2, [r3, #36]	@ 0x24
-  sBreakDeadTimeConfig.Break2Filter = 0;
- 8001390:	1d3b      	adds	r3, r7, #4
- 8001392:	2200      	movs	r2, #0
- 8001394:	629a      	str	r2, [r3, #40]	@ 0x28
-  sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT;
- 8001396:	1d3b      	adds	r3, r7, #4
- 8001398:	2200      	movs	r2, #0
- 800139a:	62da      	str	r2, [r3, #44]	@ 0x2c
-  sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
- 800139c:	1d3b      	adds	r3, r7, #4
- 800139e:	2200      	movs	r2, #0
- 80013a0:	631a      	str	r2, [r3, #48]	@ 0x30
-  if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
- 80013a2:	1d3a      	adds	r2, r7, #4
- 80013a4:	4b08      	ldr	r3, [pc, #32]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 80013a6:	0011      	movs	r1, r2
- 80013a8:	0018      	movs	r0, r3
- 80013aa:	f005 faed 	bl	8006988 <HAL_TIMEx_ConfigBreakDeadTime>
- 80013ae:	1e03      	subs	r3, r0, #0
- 80013b0:	d001      	beq.n	80013b6 <MX_TIM1_Init+0x1be>
-  {
-    Error_Handler();
- 80013b2:	f002 fb4b 	bl	8003a4c <Error_Handler>
-  }
-  /* USER CODE BEGIN TIM1_Init 2 */
-
-  /* USER CODE END TIM1_Init 2 */
-  HAL_TIM_MspPostInit(&htim1);
- 80013b6:	4b04      	ldr	r3, [pc, #16]	@ (80013c8 <MX_TIM1_Init+0x1d0>)
- 80013b8:	0018      	movs	r0, r3
- 80013ba:	f002 fc35 	bl	8003c28 <HAL_TIM_MspPostInit>
-
-}
- 80013be:	46c0      	nop			@ (mov r8, r8)
- 80013c0:	46bd      	mov	sp, r7
- 80013c2:	b01c      	add	sp, #112	@ 0x70
- 80013c4:	bd80      	pop	{r7, pc}
- 80013c6:	46c0      	nop			@ (mov r8, r8)
- 80013c8:	2000004c 	.word	0x2000004c
- 80013cc:	40012c00 	.word	0x40012c00
-
-080013d0 <MX_TIM3_Init>:
-  * @brief TIM3 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_TIM3_Init(void)
-{
- 80013d0:	b590      	push	{r4, r7, lr}
- 80013d2:	b08d      	sub	sp, #52	@ 0x34
- 80013d4:	af00      	add	r7, sp, #0
-
-  /* USER CODE BEGIN TIM3_Init 0 */
-
-  /* USER CODE END TIM3_Init 0 */
-
-  TIM_Encoder_InitTypeDef sConfig = {0};
- 80013d6:	240c      	movs	r4, #12
- 80013d8:	193b      	adds	r3, r7, r4
- 80013da:	0018      	movs	r0, r3
- 80013dc:	2324      	movs	r3, #36	@ 0x24
- 80013de:	001a      	movs	r2, r3
- 80013e0:	2100      	movs	r1, #0
- 80013e2:	f006 fc67 	bl	8007cb4 <memset>
-  TIM_MasterConfigTypeDef sMasterConfig = {0};
- 80013e6:	003b      	movs	r3, r7
- 80013e8:	0018      	movs	r0, r3
- 80013ea:	230c      	movs	r3, #12
- 80013ec:	001a      	movs	r2, r3
- 80013ee:	2100      	movs	r1, #0
- 80013f0:	f006 fc60 	bl	8007cb4 <memset>
-
-  /* USER CODE BEGIN TIM3_Init 1 */
-
-  /* USER CODE END TIM3_Init 1 */
-  htim3.Instance = TIM3;
- 80013f4:	4b25      	ldr	r3, [pc, #148]	@ (800148c <MX_TIM3_Init+0xbc>)
- 80013f6:	4a26      	ldr	r2, [pc, #152]	@ (8001490 <MX_TIM3_Init+0xc0>)
- 80013f8:	601a      	str	r2, [r3, #0]
-  htim3.Init.Prescaler = 0;
- 80013fa:	4b24      	ldr	r3, [pc, #144]	@ (800148c <MX_TIM3_Init+0xbc>)
- 80013fc:	2200      	movs	r2, #0
- 80013fe:	605a      	str	r2, [r3, #4]
-  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8001400:	4b22      	ldr	r3, [pc, #136]	@ (800148c <MX_TIM3_Init+0xbc>)
- 8001402:	2200      	movs	r2, #0
- 8001404:	609a      	str	r2, [r3, #8]
-  htim3.Init.Period = 65535;
- 8001406:	4b21      	ldr	r3, [pc, #132]	@ (800148c <MX_TIM3_Init+0xbc>)
- 8001408:	4a22      	ldr	r2, [pc, #136]	@ (8001494 <MX_TIM3_Init+0xc4>)
- 800140a:	60da      	str	r2, [r3, #12]
-  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 800140c:	4b1f      	ldr	r3, [pc, #124]	@ (800148c <MX_TIM3_Init+0xbc>)
- 800140e:	2200      	movs	r2, #0
- 8001410:	611a      	str	r2, [r3, #16]
-  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8001412:	4b1e      	ldr	r3, [pc, #120]	@ (800148c <MX_TIM3_Init+0xbc>)
- 8001414:	2200      	movs	r2, #0
- 8001416:	619a      	str	r2, [r3, #24]
-  sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
- 8001418:	0021      	movs	r1, r4
- 800141a:	187b      	adds	r3, r7, r1
- 800141c:	2203      	movs	r2, #3
- 800141e:	601a      	str	r2, [r3, #0]
-  sConfig.IC1Polarity = TIM_ICPOLARITY_RISING;
- 8001420:	187b      	adds	r3, r7, r1
- 8001422:	2200      	movs	r2, #0
- 8001424:	605a      	str	r2, [r3, #4]
-  sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
- 8001426:	187b      	adds	r3, r7, r1
- 8001428:	2201      	movs	r2, #1
- 800142a:	609a      	str	r2, [r3, #8]
-  sConfig.IC1Prescaler = TIM_ICPSC_DIV1;
- 800142c:	187b      	adds	r3, r7, r1
- 800142e:	2200      	movs	r2, #0
- 8001430:	60da      	str	r2, [r3, #12]
-  sConfig.IC1Filter = 0;
- 8001432:	187b      	adds	r3, r7, r1
- 8001434:	2200      	movs	r2, #0
- 8001436:	611a      	str	r2, [r3, #16]
-  sConfig.IC2Polarity = TIM_ICPOLARITY_RISING;
- 8001438:	187b      	adds	r3, r7, r1
- 800143a:	2200      	movs	r2, #0
- 800143c:	615a      	str	r2, [r3, #20]
-  sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
- 800143e:	187b      	adds	r3, r7, r1
- 8001440:	2201      	movs	r2, #1
- 8001442:	619a      	str	r2, [r3, #24]
-  sConfig.IC2Prescaler = TIM_ICPSC_DIV1;
- 8001444:	187b      	adds	r3, r7, r1
- 8001446:	2200      	movs	r2, #0
- 8001448:	61da      	str	r2, [r3, #28]
-  sConfig.IC2Filter = 0;
- 800144a:	187b      	adds	r3, r7, r1
- 800144c:	2200      	movs	r2, #0
- 800144e:	621a      	str	r2, [r3, #32]
-  if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
- 8001450:	187a      	adds	r2, r7, r1
- 8001452:	4b0e      	ldr	r3, [pc, #56]	@ (800148c <MX_TIM3_Init+0xbc>)
- 8001454:	0011      	movs	r1, r2
- 8001456:	0018      	movs	r0, r3
- 8001458:	f004 fa0c 	bl	8005874 <HAL_TIM_Encoder_Init>
- 800145c:	1e03      	subs	r3, r0, #0
- 800145e:	d001      	beq.n	8001464 <MX_TIM3_Init+0x94>
-  {
-    Error_Handler();
- 8001460:	f002 faf4 	bl	8003a4c <Error_Handler>
-  }
-  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
- 8001464:	003b      	movs	r3, r7
- 8001466:	2200      	movs	r2, #0
- 8001468:	601a      	str	r2, [r3, #0]
-  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
- 800146a:	003b      	movs	r3, r7
- 800146c:	2200      	movs	r2, #0
- 800146e:	609a      	str	r2, [r3, #8]
-  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
- 8001470:	003a      	movs	r2, r7
- 8001472:	4b06      	ldr	r3, [pc, #24]	@ (800148c <MX_TIM3_Init+0xbc>)
- 8001474:	0011      	movs	r1, r2
- 8001476:	0018      	movs	r0, r3
- 8001478:	f005 fa1e 	bl	80068b8 <HAL_TIMEx_MasterConfigSynchronization>
- 800147c:	1e03      	subs	r3, r0, #0
- 800147e:	d001      	beq.n	8001484 <MX_TIM3_Init+0xb4>
-  {
-    Error_Handler();
- 8001480:	f002 fae4 	bl	8003a4c <Error_Handler>
-  }
-  /* USER CODE BEGIN TIM3_Init 2 */
-
-  /* USER CODE END TIM3_Init 2 */
-
-}
- 8001484:	46c0      	nop			@ (mov r8, r8)
- 8001486:	46bd      	mov	sp, r7
- 8001488:	b00d      	add	sp, #52	@ 0x34
- 800148a:	bd90      	pop	{r4, r7, pc}
- 800148c:	20000098 	.word	0x20000098
- 8001490:	40000400 	.word	0x40000400
- 8001494:	0000ffff 	.word	0x0000ffff
-
-08001498 <MX_TIM14_Init>:
-  * @brief TIM14 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_TIM14_Init(void)
-{
- 8001498:	b580      	push	{r7, lr}
- 800149a:	af00      	add	r7, sp, #0
-  /* USER CODE END TIM14_Init 0 */
-
-  /* USER CODE BEGIN TIM14_Init 1 */
-
-  /* USER CODE END TIM14_Init 1 */
-  htim14.Instance = TIM14;
- 800149c:	4b0e      	ldr	r3, [pc, #56]	@ (80014d8 <MX_TIM14_Init+0x40>)
- 800149e:	4a0f      	ldr	r2, [pc, #60]	@ (80014dc <MX_TIM14_Init+0x44>)
- 80014a0:	601a      	str	r2, [r3, #0]
-  htim14.Init.Prescaler = 480-1;
- 80014a2:	4b0d      	ldr	r3, [pc, #52]	@ (80014d8 <MX_TIM14_Init+0x40>)
- 80014a4:	22e0      	movs	r2, #224	@ 0xe0
- 80014a6:	32ff      	adds	r2, #255	@ 0xff
- 80014a8:	605a      	str	r2, [r3, #4]
-  htim14.Init.CounterMode = TIM_COUNTERMODE_UP;
- 80014aa:	4b0b      	ldr	r3, [pc, #44]	@ (80014d8 <MX_TIM14_Init+0x40>)
- 80014ac:	2200      	movs	r2, #0
- 80014ae:	609a      	str	r2, [r3, #8]
-  htim14.Init.Period = 50;
- 80014b0:	4b09      	ldr	r3, [pc, #36]	@ (80014d8 <MX_TIM14_Init+0x40>)
- 80014b2:	2232      	movs	r2, #50	@ 0x32
- 80014b4:	60da      	str	r2, [r3, #12]
-  htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 80014b6:	4b08      	ldr	r3, [pc, #32]	@ (80014d8 <MX_TIM14_Init+0x40>)
- 80014b8:	2200      	movs	r2, #0
- 80014ba:	611a      	str	r2, [r3, #16]
-  htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 80014bc:	4b06      	ldr	r3, [pc, #24]	@ (80014d8 <MX_TIM14_Init+0x40>)
- 80014be:	2200      	movs	r2, #0
- 80014c0:	619a      	str	r2, [r3, #24]
-  if (HAL_TIM_Base_Init(&htim14) != HAL_OK)
- 80014c2:	4b05      	ldr	r3, [pc, #20]	@ (80014d8 <MX_TIM14_Init+0x40>)
- 80014c4:	0018      	movs	r0, r3
- 80014c6:	f003 ffc5 	bl	8005454 <HAL_TIM_Base_Init>
- 80014ca:	1e03      	subs	r3, r0, #0
- 80014cc:	d001      	beq.n	80014d2 <MX_TIM14_Init+0x3a>
-  {
-    Error_Handler();
- 80014ce:	f002 fabd 	bl	8003a4c <Error_Handler>
-  }
-  /* USER CODE BEGIN TIM14_Init 2 */
-
-  /* USER CODE END TIM14_Init 2 */
-
-}
- 80014d2:	46c0      	nop			@ (mov r8, r8)
- 80014d4:	46bd      	mov	sp, r7
- 80014d6:	bd80      	pop	{r7, pc}
- 80014d8:	200000e4 	.word	0x200000e4
- 80014dc:	40002000 	.word	0x40002000
-
-080014e0 <MX_TIM16_Init>:
-  * @brief TIM16 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_TIM16_Init(void)
-{
- 80014e0:	b580      	push	{r7, lr}
- 80014e2:	af00      	add	r7, sp, #0
-  /* USER CODE END TIM16_Init 0 */
-
-  /* USER CODE BEGIN TIM16_Init 1 */
-
-  /* USER CODE END TIM16_Init 1 */
-  htim16.Instance = TIM16;
- 80014e4:	4b0f      	ldr	r3, [pc, #60]	@ (8001524 <MX_TIM16_Init+0x44>)
- 80014e6:	4a10      	ldr	r2, [pc, #64]	@ (8001528 <MX_TIM16_Init+0x48>)
- 80014e8:	601a      	str	r2, [r3, #0]
-  htim16.Init.Prescaler = 48000-1;
- 80014ea:	4b0e      	ldr	r3, [pc, #56]	@ (8001524 <MX_TIM16_Init+0x44>)
- 80014ec:	4a0f      	ldr	r2, [pc, #60]	@ (800152c <MX_TIM16_Init+0x4c>)
- 80014ee:	605a      	str	r2, [r3, #4]
-  htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
- 80014f0:	4b0c      	ldr	r3, [pc, #48]	@ (8001524 <MX_TIM16_Init+0x44>)
- 80014f2:	2200      	movs	r2, #0
- 80014f4:	609a      	str	r2, [r3, #8]
-  htim16.Init.Period = 65535;
- 80014f6:	4b0b      	ldr	r3, [pc, #44]	@ (8001524 <MX_TIM16_Init+0x44>)
- 80014f8:	4a0d      	ldr	r2, [pc, #52]	@ (8001530 <MX_TIM16_Init+0x50>)
- 80014fa:	60da      	str	r2, [r3, #12]
-  htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 80014fc:	4b09      	ldr	r3, [pc, #36]	@ (8001524 <MX_TIM16_Init+0x44>)
- 80014fe:	2200      	movs	r2, #0
- 8001500:	611a      	str	r2, [r3, #16]
-  htim16.Init.RepetitionCounter = 0;
- 8001502:	4b08      	ldr	r3, [pc, #32]	@ (8001524 <MX_TIM16_Init+0x44>)
- 8001504:	2200      	movs	r2, #0
- 8001506:	615a      	str	r2, [r3, #20]
-  htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 8001508:	4b06      	ldr	r3, [pc, #24]	@ (8001524 <MX_TIM16_Init+0x44>)
- 800150a:	2200      	movs	r2, #0
- 800150c:	619a      	str	r2, [r3, #24]
-  if (HAL_TIM_Base_Init(&htim16) != HAL_OK)
- 800150e:	4b05      	ldr	r3, [pc, #20]	@ (8001524 <MX_TIM16_Init+0x44>)
- 8001510:	0018      	movs	r0, r3
- 8001512:	f003 ff9f 	bl	8005454 <HAL_TIM_Base_Init>
- 8001516:	1e03      	subs	r3, r0, #0
- 8001518:	d001      	beq.n	800151e <MX_TIM16_Init+0x3e>
-  {
-    Error_Handler();
- 800151a:	f002 fa97 	bl	8003a4c <Error_Handler>
-  }
-  /* USER CODE BEGIN TIM16_Init 2 */
-
-  /* USER CODE END TIM16_Init 2 */
-
-}
- 800151e:	46c0      	nop			@ (mov r8, r8)
- 8001520:	46bd      	mov	sp, r7
- 8001522:	bd80      	pop	{r7, pc}
- 8001524:	20000130 	.word	0x20000130
- 8001528:	40014400 	.word	0x40014400
- 800152c:	0000bb7f 	.word	0x0000bb7f
- 8001530:	0000ffff 	.word	0x0000ffff
-
-08001534 <MX_TIM17_Init>:
-  * @brief TIM17 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_TIM17_Init(void)
-{
- 8001534:	b580      	push	{r7, lr}
- 8001536:	af00      	add	r7, sp, #0
-  /* USER CODE END TIM17_Init 0 */
-
-  /* USER CODE BEGIN TIM17_Init 1 */
-
-  /* USER CODE END TIM17_Init 1 */
-  htim17.Instance = TIM17;
- 8001538:	4b0f      	ldr	r3, [pc, #60]	@ (8001578 <MX_TIM17_Init+0x44>)
- 800153a:	4a10      	ldr	r2, [pc, #64]	@ (800157c <MX_TIM17_Init+0x48>)
- 800153c:	601a      	str	r2, [r3, #0]
-  htim17.Init.Prescaler = 48000-1;
- 800153e:	4b0e      	ldr	r3, [pc, #56]	@ (8001578 <MX_TIM17_Init+0x44>)
- 8001540:	4a0f      	ldr	r2, [pc, #60]	@ (8001580 <MX_TIM17_Init+0x4c>)
- 8001542:	605a      	str	r2, [r3, #4]
-  htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
- 8001544:	4b0c      	ldr	r3, [pc, #48]	@ (8001578 <MX_TIM17_Init+0x44>)
- 8001546:	2200      	movs	r2, #0
- 8001548:	609a      	str	r2, [r3, #8]
-  htim17.Init.Period = 65535;
- 800154a:	4b0b      	ldr	r3, [pc, #44]	@ (8001578 <MX_TIM17_Init+0x44>)
- 800154c:	4a0d      	ldr	r2, [pc, #52]	@ (8001584 <MX_TIM17_Init+0x50>)
- 800154e:	60da      	str	r2, [r3, #12]
-  htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
- 8001550:	4b09      	ldr	r3, [pc, #36]	@ (8001578 <MX_TIM17_Init+0x44>)
- 8001552:	2200      	movs	r2, #0
- 8001554:	611a      	str	r2, [r3, #16]
-  htim17.Init.RepetitionCounter = 0;
- 8001556:	4b08      	ldr	r3, [pc, #32]	@ (8001578 <MX_TIM17_Init+0x44>)
- 8001558:	2200      	movs	r2, #0
- 800155a:	615a      	str	r2, [r3, #20]
-  htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
- 800155c:	4b06      	ldr	r3, [pc, #24]	@ (8001578 <MX_TIM17_Init+0x44>)
- 800155e:	2200      	movs	r2, #0
- 8001560:	619a      	str	r2, [r3, #24]
-  if (HAL_TIM_Base_Init(&htim17) != HAL_OK)
- 8001562:	4b05      	ldr	r3, [pc, #20]	@ (8001578 <MX_TIM17_Init+0x44>)
- 8001564:	0018      	movs	r0, r3
- 8001566:	f003 ff75 	bl	8005454 <HAL_TIM_Base_Init>
- 800156a:	1e03      	subs	r3, r0, #0
- 800156c:	d001      	beq.n	8001572 <MX_TIM17_Init+0x3e>
-  {
-    Error_Handler();
- 800156e:	f002 fa6d 	bl	8003a4c <Error_Handler>
-  }
-  /* USER CODE BEGIN TIM17_Init 2 */
-
-  /* USER CODE END TIM17_Init 2 */
-
-}
- 8001572:	46c0      	nop			@ (mov r8, r8)
- 8001574:	46bd      	mov	sp, r7
- 8001576:	bd80      	pop	{r7, pc}
- 8001578:	2000017c 	.word	0x2000017c
- 800157c:	40014800 	.word	0x40014800
- 8001580:	0000bb7f 	.word	0x0000bb7f
- 8001584:	0000ffff 	.word	0x0000ffff
-
-08001588 <MX_USART1_UART_Init>:
-  * @brief USART1 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_USART1_UART_Init(void)
-{
- 8001588:	b580      	push	{r7, lr}
- 800158a:	af00      	add	r7, sp, #0
-  /* USER CODE END USART1_Init 0 */
-
-  /* USER CODE BEGIN USART1_Init 1 */
-
-  /* USER CODE END USART1_Init 1 */
-  huart1.Instance = USART1;
- 800158c:	4b23      	ldr	r3, [pc, #140]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 800158e:	4a24      	ldr	r2, [pc, #144]	@ (8001620 <MX_USART1_UART_Init+0x98>)
- 8001590:	601a      	str	r2, [r3, #0]
-  huart1.Init.BaudRate = 115200;
- 8001592:	4b22      	ldr	r3, [pc, #136]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 8001594:	22e1      	movs	r2, #225	@ 0xe1
- 8001596:	0252      	lsls	r2, r2, #9
- 8001598:	605a      	str	r2, [r3, #4]
-  huart1.Init.WordLength = UART_WORDLENGTH_8B;
- 800159a:	4b20      	ldr	r3, [pc, #128]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 800159c:	2200      	movs	r2, #0
- 800159e:	609a      	str	r2, [r3, #8]
-  huart1.Init.StopBits = UART_STOPBITS_1;
- 80015a0:	4b1e      	ldr	r3, [pc, #120]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 80015a2:	2200      	movs	r2, #0
- 80015a4:	60da      	str	r2, [r3, #12]
-  huart1.Init.Parity = UART_PARITY_NONE;
- 80015a6:	4b1d      	ldr	r3, [pc, #116]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 80015a8:	2200      	movs	r2, #0
- 80015aa:	611a      	str	r2, [r3, #16]
-  huart1.Init.Mode = UART_MODE_TX_RX;
- 80015ac:	4b1b      	ldr	r3, [pc, #108]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 80015ae:	220c      	movs	r2, #12
- 80015b0:	615a      	str	r2, [r3, #20]
-  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 80015b2:	4b1a      	ldr	r3, [pc, #104]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 80015b4:	2200      	movs	r2, #0
- 80015b6:	619a      	str	r2, [r3, #24]
-  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
- 80015b8:	4b18      	ldr	r3, [pc, #96]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 80015ba:	2200      	movs	r2, #0
- 80015bc:	61da      	str	r2, [r3, #28]
-  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
- 80015be:	4b17      	ldr	r3, [pc, #92]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 80015c0:	2200      	movs	r2, #0
- 80015c2:	621a      	str	r2, [r3, #32]
-  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
- 80015c4:	4b15      	ldr	r3, [pc, #84]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 80015c6:	2200      	movs	r2, #0
- 80015c8:	625a      	str	r2, [r3, #36]	@ 0x24
-  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
- 80015ca:	4b14      	ldr	r3, [pc, #80]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 80015cc:	2200      	movs	r2, #0
- 80015ce:	629a      	str	r2, [r3, #40]	@ 0x28
-  if (HAL_UART_Init(&huart1) != HAL_OK)
- 80015d0:	4b12      	ldr	r3, [pc, #72]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 80015d2:	0018      	movs	r0, r3
- 80015d4:	f005 fa8c 	bl	8006af0 <HAL_UART_Init>
- 80015d8:	1e03      	subs	r3, r0, #0
- 80015da:	d001      	beq.n	80015e0 <MX_USART1_UART_Init+0x58>
-  {
-    Error_Handler();
- 80015dc:	f002 fa36 	bl	8003a4c <Error_Handler>
-  }
-  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
- 80015e0:	4b0e      	ldr	r3, [pc, #56]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 80015e2:	2100      	movs	r1, #0
- 80015e4:	0018      	movs	r0, r3
- 80015e6:	f006 fa0f 	bl	8007a08 <HAL_UARTEx_SetTxFifoThreshold>
- 80015ea:	1e03      	subs	r3, r0, #0
- 80015ec:	d001      	beq.n	80015f2 <MX_USART1_UART_Init+0x6a>
-  {
-    Error_Handler();
- 80015ee:	f002 fa2d 	bl	8003a4c <Error_Handler>
-  }
-  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
- 80015f2:	4b0a      	ldr	r3, [pc, #40]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 80015f4:	2100      	movs	r1, #0
- 80015f6:	0018      	movs	r0, r3
- 80015f8:	f006 fa46 	bl	8007a88 <HAL_UARTEx_SetRxFifoThreshold>
- 80015fc:	1e03      	subs	r3, r0, #0
- 80015fe:	d001      	beq.n	8001604 <MX_USART1_UART_Init+0x7c>
-  {
-    Error_Handler();
- 8001600:	f002 fa24 	bl	8003a4c <Error_Handler>
-  }
-  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
- 8001604:	4b05      	ldr	r3, [pc, #20]	@ (800161c <MX_USART1_UART_Init+0x94>)
- 8001606:	0018      	movs	r0, r3
- 8001608:	f006 f9c4 	bl	8007994 <HAL_UARTEx_DisableFifoMode>
- 800160c:	1e03      	subs	r3, r0, #0
- 800160e:	d001      	beq.n	8001614 <MX_USART1_UART_Init+0x8c>
-  {
-    Error_Handler();
- 8001610:	f002 fa1c 	bl	8003a4c <Error_Handler>
-  }
-  /* USER CODE BEGIN USART1_Init 2 */
-
-  /* USER CODE END USART1_Init 2 */
-
-}
- 8001614:	46c0      	nop			@ (mov r8, r8)
- 8001616:	46bd      	mov	sp, r7
- 8001618:	bd80      	pop	{r7, pc}
- 800161a:	46c0      	nop			@ (mov r8, r8)
- 800161c:	200001c8 	.word	0x200001c8
- 8001620:	40013800 	.word	0x40013800
-
-08001624 <MX_USART2_UART_Init>:
-  * @brief USART2 Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_USART2_UART_Init(void)
-{
- 8001624:	b580      	push	{r7, lr}
- 8001626:	af00      	add	r7, sp, #0
-  /* USER CODE END USART2_Init 0 */
-
-  /* USER CODE BEGIN USART2_Init 1 */
-
-  /* USER CODE END USART2_Init 1 */
-  huart2.Instance = USART2;
- 8001628:	4b26      	ldr	r3, [pc, #152]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 800162a:	4a27      	ldr	r2, [pc, #156]	@ (80016c8 <MX_USART2_UART_Init+0xa4>)
- 800162c:	601a      	str	r2, [r3, #0]
-  huart2.Init.BaudRate = 57600;
- 800162e:	4b25      	ldr	r3, [pc, #148]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 8001630:	22e1      	movs	r2, #225	@ 0xe1
- 8001632:	0212      	lsls	r2, r2, #8
- 8001634:	605a      	str	r2, [r3, #4]
-  huart2.Init.WordLength = UART_WORDLENGTH_8B;
- 8001636:	4b23      	ldr	r3, [pc, #140]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 8001638:	2200      	movs	r2, #0
- 800163a:	609a      	str	r2, [r3, #8]
-  huart2.Init.StopBits = UART_STOPBITS_1;
- 800163c:	4b21      	ldr	r3, [pc, #132]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 800163e:	2200      	movs	r2, #0
- 8001640:	60da      	str	r2, [r3, #12]
-  huart2.Init.Parity = UART_PARITY_NONE;
- 8001642:	4b20      	ldr	r3, [pc, #128]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 8001644:	2200      	movs	r2, #0
- 8001646:	611a      	str	r2, [r3, #16]
-  huart2.Init.Mode = UART_MODE_TX_RX;
- 8001648:	4b1e      	ldr	r3, [pc, #120]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 800164a:	220c      	movs	r2, #12
- 800164c:	615a      	str	r2, [r3, #20]
-  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
- 800164e:	4b1d      	ldr	r3, [pc, #116]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 8001650:	2200      	movs	r2, #0
- 8001652:	619a      	str	r2, [r3, #24]
-  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
- 8001654:	4b1b      	ldr	r3, [pc, #108]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 8001656:	2200      	movs	r2, #0
- 8001658:	61da      	str	r2, [r3, #28]
-  huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
- 800165a:	4b1a      	ldr	r3, [pc, #104]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 800165c:	2200      	movs	r2, #0
- 800165e:	621a      	str	r2, [r3, #32]
-  huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
- 8001660:	4b18      	ldr	r3, [pc, #96]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 8001662:	2200      	movs	r2, #0
- 8001664:	625a      	str	r2, [r3, #36]	@ 0x24
-  huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
- 8001666:	4b17      	ldr	r3, [pc, #92]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 8001668:	2200      	movs	r2, #0
- 800166a:	629a      	str	r2, [r3, #40]	@ 0x28
-  if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 0, 0) != HAL_OK)
- 800166c:	4815      	ldr	r0, [pc, #84]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 800166e:	2300      	movs	r3, #0
- 8001670:	2200      	movs	r2, #0
- 8001672:	2100      	movs	r1, #0
- 8001674:	f006 f91c 	bl	80078b0 <HAL_RS485Ex_Init>
- 8001678:	1e03      	subs	r3, r0, #0
- 800167a:	d001      	beq.n	8001680 <MX_USART2_UART_Init+0x5c>
-  {
-    Error_Handler();
- 800167c:	f002 f9e6 	bl	8003a4c <Error_Handler>
-  }
-  if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_2) != HAL_OK)
- 8001680:	2380      	movs	r3, #128	@ 0x80
- 8001682:	05da      	lsls	r2, r3, #23
- 8001684:	4b0f      	ldr	r3, [pc, #60]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 8001686:	0011      	movs	r1, r2
- 8001688:	0018      	movs	r0, r3
- 800168a:	f006 f9bd 	bl	8007a08 <HAL_UARTEx_SetTxFifoThreshold>
- 800168e:	1e03      	subs	r3, r0, #0
- 8001690:	d001      	beq.n	8001696 <MX_USART2_UART_Init+0x72>
-  {
-    Error_Handler();
- 8001692:	f002 f9db 	bl	8003a4c <Error_Handler>
-  }
-  if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_2) != HAL_OK)
- 8001696:	2380      	movs	r3, #128	@ 0x80
- 8001698:	04da      	lsls	r2, r3, #19
- 800169a:	4b0a      	ldr	r3, [pc, #40]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 800169c:	0011      	movs	r1, r2
- 800169e:	0018      	movs	r0, r3
- 80016a0:	f006 f9f2 	bl	8007a88 <HAL_UARTEx_SetRxFifoThreshold>
- 80016a4:	1e03      	subs	r3, r0, #0
- 80016a6:	d001      	beq.n	80016ac <MX_USART2_UART_Init+0x88>
-  {
-    Error_Handler();
- 80016a8:	f002 f9d0 	bl	8003a4c <Error_Handler>
-  }
-  if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK)
- 80016ac:	4b05      	ldr	r3, [pc, #20]	@ (80016c4 <MX_USART2_UART_Init+0xa0>)
- 80016ae:	0018      	movs	r0, r3
- 80016b0:	f006 f970 	bl	8007994 <HAL_UARTEx_DisableFifoMode>
- 80016b4:	1e03      	subs	r3, r0, #0
- 80016b6:	d001      	beq.n	80016bc <MX_USART2_UART_Init+0x98>
-  {
-    Error_Handler();
- 80016b8:	f002 f9c8 	bl	8003a4c <Error_Handler>
-  }
-  /* USER CODE BEGIN USART2_Init 2 */
-
-  /* USER CODE END USART2_Init 2 */
-
-}
- 80016bc:	46c0      	nop			@ (mov r8, r8)
- 80016be:	46bd      	mov	sp, r7
- 80016c0:	bd80      	pop	{r7, pc}
- 80016c2:	46c0      	nop			@ (mov r8, r8)
- 80016c4:	2000025c 	.word	0x2000025c
- 80016c8:	40004400 	.word	0x40004400
-
-080016cc <MX_DMA_Init>:
-
-/**
-  * Enable DMA controller clock
-  */
-static void MX_DMA_Init(void)
-{
- 80016cc:	b580      	push	{r7, lr}
- 80016ce:	b082      	sub	sp, #8
- 80016d0:	af00      	add	r7, sp, #0
-
-  /* DMA controller clock enable */
-  __HAL_RCC_DMA1_CLK_ENABLE();
- 80016d2:	4b10      	ldr	r3, [pc, #64]	@ (8001714 <MX_DMA_Init+0x48>)
- 80016d4:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
- 80016d6:	4b0f      	ldr	r3, [pc, #60]	@ (8001714 <MX_DMA_Init+0x48>)
- 80016d8:	2101      	movs	r1, #1
- 80016da:	430a      	orrs	r2, r1
- 80016dc:	639a      	str	r2, [r3, #56]	@ 0x38
- 80016de:	4b0d      	ldr	r3, [pc, #52]	@ (8001714 <MX_DMA_Init+0x48>)
- 80016e0:	6b9b      	ldr	r3, [r3, #56]	@ 0x38
- 80016e2:	2201      	movs	r2, #1
- 80016e4:	4013      	ands	r3, r2
- 80016e6:	607b      	str	r3, [r7, #4]
- 80016e8:	687b      	ldr	r3, [r7, #4]
-
-  /* DMA interrupt init */
-  /* DMA1_Channel1_IRQn interrupt configuration */
-  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
- 80016ea:	2200      	movs	r2, #0
- 80016ec:	2100      	movs	r1, #0
- 80016ee:	2009      	movs	r0, #9
- 80016f0:	f002 fdea 	bl	80042c8 <HAL_NVIC_SetPriority>
-  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
- 80016f4:	2009      	movs	r0, #9
- 80016f6:	f002 fdfc 	bl	80042f2 <HAL_NVIC_EnableIRQ>
-  /* DMA1_Channel2_3_IRQn interrupt configuration */
-  HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0);
- 80016fa:	2200      	movs	r2, #0
- 80016fc:	2100      	movs	r1, #0
- 80016fe:	200a      	movs	r0, #10
- 8001700:	f002 fde2 	bl	80042c8 <HAL_NVIC_SetPriority>
-  HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
- 8001704:	200a      	movs	r0, #10
- 8001706:	f002 fdf4 	bl	80042f2 <HAL_NVIC_EnableIRQ>
-
-}
- 800170a:	46c0      	nop			@ (mov r8, r8)
- 800170c:	46bd      	mov	sp, r7
- 800170e:	b002      	add	sp, #8
- 8001710:	bd80      	pop	{r7, pc}
- 8001712:	46c0      	nop			@ (mov r8, r8)
- 8001714:	40021000 	.word	0x40021000
-
-08001718 <MX_GPIO_Init>:
-  * @brief GPIO Initialization Function
-  * @param None
-  * @retval None
-  */
-static void MX_GPIO_Init(void)
-{
- 8001718:	b590      	push	{r4, r7, lr}
- 800171a:	b08b      	sub	sp, #44	@ 0x2c
- 800171c:	af00      	add	r7, sp, #0
-  GPIO_InitTypeDef GPIO_InitStruct = {0};
- 800171e:	2414      	movs	r4, #20
- 8001720:	193b      	adds	r3, r7, r4
- 8001722:	0018      	movs	r0, r3
- 8001724:	2314      	movs	r3, #20
- 8001726:	001a      	movs	r2, r3
- 8001728:	2100      	movs	r1, #0
- 800172a:	f006 fac3 	bl	8007cb4 <memset>
-  /* USER CODE BEGIN MX_GPIO_Init_1 */
-
-  /* USER CODE END MX_GPIO_Init_1 */
-
-  /* GPIO Ports Clock Enable */
-  __HAL_RCC_GPIOF_CLK_ENABLE();
- 800172e:	4b3f      	ldr	r3, [pc, #252]	@ (800182c <MX_GPIO_Init+0x114>)
- 8001730:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
- 8001732:	4b3e      	ldr	r3, [pc, #248]	@ (800182c <MX_GPIO_Init+0x114>)
- 8001734:	2120      	movs	r1, #32
- 8001736:	430a      	orrs	r2, r1
- 8001738:	635a      	str	r2, [r3, #52]	@ 0x34
- 800173a:	4b3c      	ldr	r3, [pc, #240]	@ (800182c <MX_GPIO_Init+0x114>)
- 800173c:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 800173e:	2220      	movs	r2, #32
- 8001740:	4013      	ands	r3, r2
- 8001742:	613b      	str	r3, [r7, #16]
- 8001744:	693b      	ldr	r3, [r7, #16]
-  __HAL_RCC_GPIOA_CLK_ENABLE();
- 8001746:	4b39      	ldr	r3, [pc, #228]	@ (800182c <MX_GPIO_Init+0x114>)
- 8001748:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
- 800174a:	4b38      	ldr	r3, [pc, #224]	@ (800182c <MX_GPIO_Init+0x114>)
- 800174c:	2101      	movs	r1, #1
- 800174e:	430a      	orrs	r2, r1
- 8001750:	635a      	str	r2, [r3, #52]	@ 0x34
- 8001752:	4b36      	ldr	r3, [pc, #216]	@ (800182c <MX_GPIO_Init+0x114>)
- 8001754:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8001756:	2201      	movs	r2, #1
- 8001758:	4013      	ands	r3, r2
- 800175a:	60fb      	str	r3, [r7, #12]
- 800175c:	68fb      	ldr	r3, [r7, #12]
-  __HAL_RCC_GPIOC_CLK_ENABLE();
- 800175e:	4b33      	ldr	r3, [pc, #204]	@ (800182c <MX_GPIO_Init+0x114>)
- 8001760:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
- 8001762:	4b32      	ldr	r3, [pc, #200]	@ (800182c <MX_GPIO_Init+0x114>)
- 8001764:	2104      	movs	r1, #4
- 8001766:	430a      	orrs	r2, r1
- 8001768:	635a      	str	r2, [r3, #52]	@ 0x34
- 800176a:	4b30      	ldr	r3, [pc, #192]	@ (800182c <MX_GPIO_Init+0x114>)
- 800176c:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 800176e:	2204      	movs	r2, #4
- 8001770:	4013      	ands	r3, r2
- 8001772:	60bb      	str	r3, [r7, #8]
- 8001774:	68bb      	ldr	r3, [r7, #8]
-  __HAL_RCC_GPIOB_CLK_ENABLE();
- 8001776:	4b2d      	ldr	r3, [pc, #180]	@ (800182c <MX_GPIO_Init+0x114>)
- 8001778:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
- 800177a:	4b2c      	ldr	r3, [pc, #176]	@ (800182c <MX_GPIO_Init+0x114>)
- 800177c:	2102      	movs	r1, #2
- 800177e:	430a      	orrs	r2, r1
- 8001780:	635a      	str	r2, [r3, #52]	@ 0x34
- 8001782:	4b2a      	ldr	r3, [pc, #168]	@ (800182c <MX_GPIO_Init+0x114>)
- 8001784:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8001786:	2202      	movs	r2, #2
- 8001788:	4013      	ands	r3, r2
- 800178a:	607b      	str	r3, [r7, #4]
- 800178c:	687b      	ldr	r3, [r7, #4]
-
-  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
- 800178e:	4928      	ldr	r1, [pc, #160]	@ (8001830 <MX_GPIO_Init+0x118>)
- 8001790:	23a0      	movs	r3, #160	@ 0xa0
- 8001792:	05db      	lsls	r3, r3, #23
- 8001794:	2200      	movs	r2, #0
- 8001796:	0018      	movs	r0, r3
- 8001798:	f003 f9ab 	bl	8004af2 <HAL_GPIO_WritePin>
-
-  /*Configure GPIO pin Output Level */
-  HAL_GPIO_WritePin(GPIOB, LED_R_Pin|LED_B_Pin|LED_G_Pin, GPIO_PIN_RESET);
- 800179c:	4b25      	ldr	r3, [pc, #148]	@ (8001834 <MX_GPIO_Init+0x11c>)
- 800179e:	2200      	movs	r2, #0
- 80017a0:	2138      	movs	r1, #56	@ 0x38
- 80017a2:	0018      	movs	r0, r3
- 80017a4:	f003 f9a5 	bl	8004af2 <HAL_GPIO_WritePin>
-
-  /*Configure GPIO pins : USART2_NRE_Pin ONEWIRE_Pin */
-  GPIO_InitStruct.Pin = USART2_NRE_Pin|ONEWIRE_Pin;
- 80017a8:	193b      	adds	r3, r7, r4
- 80017aa:	4a21      	ldr	r2, [pc, #132]	@ (8001830 <MX_GPIO_Init+0x118>)
- 80017ac:	601a      	str	r2, [r3, #0]
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 80017ae:	193b      	adds	r3, r7, r4
- 80017b0:	2201      	movs	r2, #1
- 80017b2:	605a      	str	r2, [r3, #4]
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80017b4:	193b      	adds	r3, r7, r4
- 80017b6:	2200      	movs	r2, #0
- 80017b8:	609a      	str	r2, [r3, #8]
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 80017ba:	193b      	adds	r3, r7, r4
- 80017bc:	2200      	movs	r2, #0
- 80017be:	60da      	str	r2, [r3, #12]
-  HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 80017c0:	193a      	adds	r2, r7, r4
- 80017c2:	23a0      	movs	r3, #160	@ 0xa0
- 80017c4:	05db      	lsls	r3, r3, #23
- 80017c6:	0011      	movs	r1, r2
- 80017c8:	0018      	movs	r0, r3
- 80017ca:	f003 f803 	bl	80047d4 <HAL_GPIO_Init>
-
-  /*Configure GPIO pins : LED_R_Pin LED_B_Pin LED_G_Pin */
-  GPIO_InitStruct.Pin = LED_R_Pin|LED_B_Pin|LED_G_Pin;
- 80017ce:	193b      	adds	r3, r7, r4
- 80017d0:	2238      	movs	r2, #56	@ 0x38
- 80017d2:	601a      	str	r2, [r3, #0]
-  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
- 80017d4:	193b      	adds	r3, r7, r4
- 80017d6:	2201      	movs	r2, #1
- 80017d8:	605a      	str	r2, [r3, #4]
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80017da:	193b      	adds	r3, r7, r4
- 80017dc:	2200      	movs	r2, #0
- 80017de:	609a      	str	r2, [r3, #8]
-  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 80017e0:	193b      	adds	r3, r7, r4
- 80017e2:	2200      	movs	r2, #0
- 80017e4:	60da      	str	r2, [r3, #12]
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
- 80017e6:	193b      	adds	r3, r7, r4
- 80017e8:	4a12      	ldr	r2, [pc, #72]	@ (8001834 <MX_GPIO_Init+0x11c>)
- 80017ea:	0019      	movs	r1, r3
- 80017ec:	0010      	movs	r0, r2
- 80017ee:	f002 fff1 	bl	80047d4 <HAL_GPIO_Init>
-
-  /*Configure GPIO pins : SW2_Pin SW1_Pin */
-  GPIO_InitStruct.Pin = SW2_Pin|SW1_Pin;
- 80017f2:	0021      	movs	r1, r4
- 80017f4:	187b      	adds	r3, r7, r1
- 80017f6:	22c0      	movs	r2, #192	@ 0xc0
- 80017f8:	0092      	lsls	r2, r2, #2
- 80017fa:	601a      	str	r2, [r3, #0]
-  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
- 80017fc:	187b      	adds	r3, r7, r1
- 80017fe:	4a0e      	ldr	r2, [pc, #56]	@ (8001838 <MX_GPIO_Init+0x120>)
- 8001800:	605a      	str	r2, [r3, #4]
-  GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8001802:	187b      	adds	r3, r7, r1
- 8001804:	2200      	movs	r2, #0
- 8001806:	609a      	str	r2, [r3, #8]
-  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
- 8001808:	187b      	adds	r3, r7, r1
- 800180a:	4a0a      	ldr	r2, [pc, #40]	@ (8001834 <MX_GPIO_Init+0x11c>)
- 800180c:	0019      	movs	r1, r3
- 800180e:	0010      	movs	r0, r2
- 8001810:	f002 ffe0 	bl	80047d4 <HAL_GPIO_Init>
-
-  /* EXTI interrupt init*/
-  HAL_NVIC_SetPriority(EXTI4_15_IRQn, 0, 0);
- 8001814:	2200      	movs	r2, #0
- 8001816:	2100      	movs	r1, #0
- 8001818:	2007      	movs	r0, #7
- 800181a:	f002 fd55 	bl	80042c8 <HAL_NVIC_SetPriority>
-  HAL_NVIC_EnableIRQ(EXTI4_15_IRQn);
- 800181e:	2007      	movs	r0, #7
- 8001820:	f002 fd67 	bl	80042f2 <HAL_NVIC_EnableIRQ>
-
-  /* USER CODE BEGIN MX_GPIO_Init_2 */
-  // PEEL1/PEEL2 (PA2/PA3) are TIM1_CH3/CH4 - configured by MX_TIM1_Init
-  /* USER CODE END MX_GPIO_Init_2 */
-}
- 8001824:	46c0      	nop			@ (mov r8, r8)
- 8001826:	46bd      	mov	sp, r7
- 8001828:	b00b      	add	sp, #44	@ 0x2c
- 800182a:	bd90      	pop	{r4, r7, pc}
- 800182c:	40021000 	.word	0x40021000
- 8001830:	00000401 	.word	0x00000401
- 8001834:	50000400 	.word	0x50000400
- 8001838:	10210000 	.word	0x10210000
-
-0800183c <HAL_TIM_PeriodElapsedCallback>:
-
-/* USER CODE BEGIN 4 */
-
-void HAL_TIM_PeriodElapsedCallback (TIM_HandleTypeDef * htim)
-{
- 800183c:	b580      	push	{r7, lr}
- 800183e:	b088      	sub	sp, #32
- 8001840:	af00      	add	r7, sp, #0
- 8001842:	6078      	str	r0, [r7, #4]
-	if (htim == &htim14) // encoder check timer (runs at 20khz)
- 8001844:	687a      	ldr	r2, [r7, #4]
- 8001846:	4b6e      	ldr	r3, [pc, #440]	@ (8001a00 <HAL_TIM_PeriodElapsedCallback+0x1c4>)
- 8001848:	429a      	cmp	r2, r3
- 800184a:	d000      	beq.n	800184e <HAL_TIM_PeriodElapsedCallback+0x12>
- 800184c:	e0bf      	b.n	80019ce <HAL_TIM_PeriodElapsedCallback+0x192>
-	{
-		uint16_t count = htim3.Instance->CNT;
- 800184e:	4b6d      	ldr	r3, [pc, #436]	@ (8001a04 <HAL_TIM_PeriodElapsedCallback+0x1c8>)
- 8001850:	681b      	ldr	r3, [r3, #0]
- 8001852:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
- 8001854:	211e      	movs	r1, #30
- 8001856:	187b      	adds	r3, r7, r1
- 8001858:	801a      	strh	r2, [r3, #0]
-		if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
- 800185a:	4b6b      	ldr	r3, [pc, #428]	@ (8001a08 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 800185c:	881b      	ldrh	r3, [r3, #0]
- 800185e:	4a6b      	ldr	r2, [pc, #428]	@ (8001a0c <HAL_TIM_PeriodElapsedCallback+0x1d0>)
- 8001860:	4293      	cmp	r3, r2
- 8001862:	d90b      	bls.n	800187c <HAL_TIM_PeriodElapsedCallback+0x40>
- 8001864:	187b      	adds	r3, r7, r1
- 8001866:	881a      	ldrh	r2, [r3, #0]
- 8001868:	23fa      	movs	r3, #250	@ 0xfa
- 800186a:	009b      	lsls	r3, r3, #2
- 800186c:	429a      	cmp	r2, r3
- 800186e:	d205      	bcs.n	800187c <HAL_TIM_PeriodElapsedCallback+0x40>
-		{
-			encoder_count_extra ++;
- 8001870:	4b67      	ldr	r3, [pc, #412]	@ (8001a10 <HAL_TIM_PeriodElapsedCallback+0x1d4>)
- 8001872:	681b      	ldr	r3, [r3, #0]
- 8001874:	1c5a      	adds	r2, r3, #1
- 8001876:	4b66      	ldr	r3, [pc, #408]	@ (8001a10 <HAL_TIM_PeriodElapsedCallback+0x1d4>)
- 8001878:	601a      	str	r2, [r3, #0]
- 800187a:	e010      	b.n	800189e <HAL_TIM_PeriodElapsedCallback+0x62>
-		}
-		else if ((encoder_previous < CNT_LIMIT_ZONE) && (count > CNT_MAX-CNT_LIMIT_ZONE)) // negative turnaround
- 800187c:	4b62      	ldr	r3, [pc, #392]	@ (8001a08 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 800187e:	881a      	ldrh	r2, [r3, #0]
- 8001880:	23fa      	movs	r3, #250	@ 0xfa
- 8001882:	009b      	lsls	r3, r3, #2
- 8001884:	429a      	cmp	r2, r3
- 8001886:	d20a      	bcs.n	800189e <HAL_TIM_PeriodElapsedCallback+0x62>
- 8001888:	231e      	movs	r3, #30
- 800188a:	18fb      	adds	r3, r7, r3
- 800188c:	881b      	ldrh	r3, [r3, #0]
- 800188e:	4a5f      	ldr	r2, [pc, #380]	@ (8001a0c <HAL_TIM_PeriodElapsedCallback+0x1d0>)
- 8001890:	4293      	cmp	r3, r2
- 8001892:	d904      	bls.n	800189e <HAL_TIM_PeriodElapsedCallback+0x62>
-		{
-			encoder_count_extra --;
- 8001894:	4b5e      	ldr	r3, [pc, #376]	@ (8001a10 <HAL_TIM_PeriodElapsedCallback+0x1d4>)
- 8001896:	681b      	ldr	r3, [r3, #0]
- 8001898:	1e5a      	subs	r2, r3, #1
- 800189a:	4b5d      	ldr	r3, [pc, #372]	@ (8001a10 <HAL_TIM_PeriodElapsedCallback+0x1d4>)
- 800189c:	601a      	str	r2, [r3, #0]
-		}
-		encoder_previous = count; // update previous for next cycle
- 800189e:	4b5a      	ldr	r3, [pc, #360]	@ (8001a08 <HAL_TIM_PeriodElapsedCallback+0x1cc>)
- 80018a0:	211e      	movs	r1, #30
- 80018a2:	187a      	adds	r2, r7, r1
- 80018a4:	8812      	ldrh	r2, [r2, #0]
- 80018a6:	801a      	strh	r2, [r3, #0]
-
-		total_count = (encoder_count_extra * 65536) + count;
- 80018a8:	4b59      	ldr	r3, [pc, #356]	@ (8001a10 <HAL_TIM_PeriodElapsedCallback+0x1d4>)
- 80018aa:	681b      	ldr	r3, [r3, #0]
- 80018ac:	041a      	lsls	r2, r3, #16
- 80018ae:	187b      	adds	r3, r7, r1
- 80018b0:	881b      	ldrh	r3, [r3, #0]
- 80018b2:	18d2      	adds	r2, r2, r3
- 80018b4:	4b57      	ldr	r3, [pc, #348]	@ (8001a14 <HAL_TIM_PeriodElapsedCallback+0x1d8>)
- 80018b6:	601a      	str	r2, [r3, #0]
-
-		// Position overflow prevention - reset counts when they get too large
-		if (total_count > POSITION_OVERFLOW_THRESHOLD)
- 80018b8:	4b56      	ldr	r3, [pc, #344]	@ (8001a14 <HAL_TIM_PeriodElapsedCallback+0x1d8>)
- 80018ba:	681a      	ldr	r2, [r3, #0]
- 80018bc:	2380      	movs	r3, #128	@ 0x80
- 80018be:	05db      	lsls	r3, r3, #23
- 80018c0:	429a      	cmp	r2, r3
- 80018c2:	db25      	blt.n	8001910 <HAL_TIM_PeriodElapsedCallback+0xd4>
-		{
-			int32_t adjustment = POSITION_RESET_AMOUNT;
- 80018c4:	4b54      	ldr	r3, [pc, #336]	@ (8001a18 <HAL_TIM_PeriodElapsedCallback+0x1dc>)
- 80018c6:	617b      	str	r3, [r7, #20]
-			total_count -= adjustment;
- 80018c8:	4b52      	ldr	r3, [pc, #328]	@ (8001a14 <HAL_TIM_PeriodElapsedCallback+0x1d8>)
- 80018ca:	681a      	ldr	r2, [r3, #0]
- 80018cc:	697b      	ldr	r3, [r7, #20]
- 80018ce:	1ad2      	subs	r2, r2, r3
- 80018d0:	4b50      	ldr	r3, [pc, #320]	@ (8001a14 <HAL_TIM_PeriodElapsedCallback+0x1d8>)
- 80018d2:	601a      	str	r2, [r3, #0]
-			target_count -= adjustment;
- 80018d4:	4b51      	ldr	r3, [pc, #324]	@ (8001a1c <HAL_TIM_PeriodElapsedCallback+0x1e0>)
- 80018d6:	681a      	ldr	r2, [r3, #0]
- 80018d8:	697b      	ldr	r3, [r7, #20]
- 80018da:	1ad2      	subs	r2, r2, r3
- 80018dc:	4b4f      	ldr	r3, [pc, #316]	@ (8001a1c <HAL_TIM_PeriodElapsedCallback+0x1e0>)
- 80018de:	601a      	str	r2, [r3, #0]
-			feed_target_position -= adjustment;
- 80018e0:	4b4f      	ldr	r3, [pc, #316]	@ (8001a20 <HAL_TIM_PeriodElapsedCallback+0x1e4>)
- 80018e2:	681a      	ldr	r2, [r3, #0]
- 80018e4:	697b      	ldr	r3, [r7, #20]
- 80018e6:	1ad2      	subs	r2, r2, r3
- 80018e8:	4b4d      	ldr	r3, [pc, #308]	@ (8001a20 <HAL_TIM_PeriodElapsedCallback+0x1e4>)
- 80018ea:	601a      	str	r2, [r3, #0]
-			encoder_count_extra -= (adjustment / 65536);
- 80018ec:	697b      	ldr	r3, [r7, #20]
- 80018ee:	2b00      	cmp	r3, #0
- 80018f0:	da02      	bge.n	80018f8 <HAL_TIM_PeriodElapsedCallback+0xbc>
- 80018f2:	4a4c      	ldr	r2, [pc, #304]	@ (8001a24 <HAL_TIM_PeriodElapsedCallback+0x1e8>)
- 80018f4:	4694      	mov	ip, r2
- 80018f6:	4463      	add	r3, ip
- 80018f8:	141b      	asrs	r3, r3, #16
- 80018fa:	425b      	negs	r3, r3
- 80018fc:	001a      	movs	r2, r3
- 80018fe:	4b44      	ldr	r3, [pc, #272]	@ (8001a10 <HAL_TIM_PeriodElapsedCallback+0x1d4>)
- 8001900:	681b      	ldr	r3, [r3, #0]
- 8001902:	18d2      	adds	r2, r2, r3
- 8001904:	4b42      	ldr	r3, [pc, #264]	@ (8001a10 <HAL_TIM_PeriodElapsedCallback+0x1d4>)
- 8001906:	601a      	str	r2, [r3, #0]
-			mm_position = 0; // Reset mm tracking too
- 8001908:	4b47      	ldr	r3, [pc, #284]	@ (8001a28 <HAL_TIM_PeriodElapsedCallback+0x1ec>)
- 800190a:	2200      	movs	r2, #0
- 800190c:	601a      	str	r2, [r3, #0]
- 800190e:	e029      	b.n	8001964 <HAL_TIM_PeriodElapsedCallback+0x128>
-		}
-		else if (total_count < -POSITION_OVERFLOW_THRESHOLD)
- 8001910:	4b40      	ldr	r3, [pc, #256]	@ (8001a14 <HAL_TIM_PeriodElapsedCallback+0x1d8>)
- 8001912:	681a      	ldr	r2, [r3, #0]
- 8001914:	23c0      	movs	r3, #192	@ 0xc0
- 8001916:	061b      	lsls	r3, r3, #24
- 8001918:	429a      	cmp	r2, r3
- 800191a:	dc23      	bgt.n	8001964 <HAL_TIM_PeriodElapsedCallback+0x128>
-		{
-			int32_t adjustment = POSITION_RESET_AMOUNT;
- 800191c:	4b3e      	ldr	r3, [pc, #248]	@ (8001a18 <HAL_TIM_PeriodElapsedCallback+0x1dc>)
- 800191e:	61bb      	str	r3, [r7, #24]
-			total_count += adjustment;
- 8001920:	4b3c      	ldr	r3, [pc, #240]	@ (8001a14 <HAL_TIM_PeriodElapsedCallback+0x1d8>)
- 8001922:	681a      	ldr	r2, [r3, #0]
- 8001924:	69bb      	ldr	r3, [r7, #24]
- 8001926:	18d2      	adds	r2, r2, r3
- 8001928:	4b3a      	ldr	r3, [pc, #232]	@ (8001a14 <HAL_TIM_PeriodElapsedCallback+0x1d8>)
- 800192a:	601a      	str	r2, [r3, #0]
-			target_count += adjustment;
- 800192c:	4b3b      	ldr	r3, [pc, #236]	@ (8001a1c <HAL_TIM_PeriodElapsedCallback+0x1e0>)
- 800192e:	681a      	ldr	r2, [r3, #0]
- 8001930:	69bb      	ldr	r3, [r7, #24]
- 8001932:	18d2      	adds	r2, r2, r3
- 8001934:	4b39      	ldr	r3, [pc, #228]	@ (8001a1c <HAL_TIM_PeriodElapsedCallback+0x1e0>)
- 8001936:	601a      	str	r2, [r3, #0]
-			feed_target_position += adjustment;
- 8001938:	4b39      	ldr	r3, [pc, #228]	@ (8001a20 <HAL_TIM_PeriodElapsedCallback+0x1e4>)
- 800193a:	681a      	ldr	r2, [r3, #0]
- 800193c:	69bb      	ldr	r3, [r7, #24]
- 800193e:	18d2      	adds	r2, r2, r3
- 8001940:	4b37      	ldr	r3, [pc, #220]	@ (8001a20 <HAL_TIM_PeriodElapsedCallback+0x1e4>)
- 8001942:	601a      	str	r2, [r3, #0]
-			encoder_count_extra += (adjustment / 65536);
- 8001944:	69bb      	ldr	r3, [r7, #24]
- 8001946:	2b00      	cmp	r3, #0
- 8001948:	da02      	bge.n	8001950 <HAL_TIM_PeriodElapsedCallback+0x114>
- 800194a:	4a36      	ldr	r2, [pc, #216]	@ (8001a24 <HAL_TIM_PeriodElapsedCallback+0x1e8>)
- 800194c:	4694      	mov	ip, r2
- 800194e:	4463      	add	r3, ip
- 8001950:	141b      	asrs	r3, r3, #16
- 8001952:	001a      	movs	r2, r3
- 8001954:	4b2e      	ldr	r3, [pc, #184]	@ (8001a10 <HAL_TIM_PeriodElapsedCallback+0x1d4>)
- 8001956:	681b      	ldr	r3, [r3, #0]
- 8001958:	18d2      	adds	r2, r2, r3
- 800195a:	4b2d      	ldr	r3, [pc, #180]	@ (8001a10 <HAL_TIM_PeriodElapsedCallback+0x1d4>)
- 800195c:	601a      	str	r2, [r3, #0]
-			mm_position = 0;
- 800195e:	4b32      	ldr	r3, [pc, #200]	@ (8001a28 <HAL_TIM_PeriodElapsedCallback+0x1ec>)
- 8001960:	2200      	movs	r2, #0
- 8001962:	601a      	str	r2, [r3, #0]
-		}
-
-
-		if (pid_add!=0)
- 8001964:	4b31      	ldr	r3, [pc, #196]	@ (8001a2c <HAL_TIM_PeriodElapsedCallback+0x1f0>)
- 8001966:	681b      	ldr	r3, [r3, #0]
- 8001968:	2b00      	cmp	r3, #0
- 800196a:	d00d      	beq.n	8001988 <HAL_TIM_PeriodElapsedCallback+0x14c>
-		{
-			int64_t temp = target_count + pid_add;
- 800196c:	4b2b      	ldr	r3, [pc, #172]	@ (8001a1c <HAL_TIM_PeriodElapsedCallback+0x1e0>)
- 800196e:	681a      	ldr	r2, [r3, #0]
- 8001970:	4b2e      	ldr	r3, [pc, #184]	@ (8001a2c <HAL_TIM_PeriodElapsedCallback+0x1f0>)
- 8001972:	681b      	ldr	r3, [r3, #0]
- 8001974:	18d3      	adds	r3, r2, r3
- 8001976:	60bb      	str	r3, [r7, #8]
- 8001978:	17db      	asrs	r3, r3, #31
- 800197a:	60fb      	str	r3, [r7, #12]
-			pid_add = 0;
- 800197c:	4b2b      	ldr	r3, [pc, #172]	@ (8001a2c <HAL_TIM_PeriodElapsedCallback+0x1f0>)
- 800197e:	2200      	movs	r2, #0
- 8001980:	601a      	str	r2, [r3, #0]
-			}
-			else if(temp > (INT32_MAX-10000))
-			{
-				//todo throw error
-			}
-			target_count = temp;
- 8001982:	68ba      	ldr	r2, [r7, #8]
- 8001984:	4b25      	ldr	r3, [pc, #148]	@ (8001a1c <HAL_TIM_PeriodElapsedCallback+0x1e0>)
- 8001986:	601a      	str	r2, [r3, #0]
-		}
-		motor_cmd = pid_update_motor(&motor_pid,target_count,total_count);
- 8001988:	4b24      	ldr	r3, [pc, #144]	@ (8001a1c <HAL_TIM_PeriodElapsedCallback+0x1e0>)
- 800198a:	6819      	ldr	r1, [r3, #0]
- 800198c:	4b21      	ldr	r3, [pc, #132]	@ (8001a14 <HAL_TIM_PeriodElapsedCallback+0x1d8>)
- 800198e:	681a      	ldr	r2, [r3, #0]
- 8001990:	4b27      	ldr	r3, [pc, #156]	@ (8001a30 <HAL_TIM_PeriodElapsedCallback+0x1f4>)
- 8001992:	0018      	movs	r0, r3
- 8001994:	f7fe ff53 	bl	800083e <pid_update_motor>
- 8001998:	0003      	movs	r3, r0
- 800199a:	001a      	movs	r2, r3
- 800199c:	4b25      	ldr	r3, [pc, #148]	@ (8001a34 <HAL_TIM_PeriodElapsedCallback+0x1f8>)
- 800199e:	601a      	str	r2, [r3, #0]
-		debug_pid_output = motor_cmd.dir ? motor_cmd.pwm : -motor_cmd.pwm; // Capture for debug
- 80019a0:	4b24      	ldr	r3, [pc, #144]	@ (8001a34 <HAL_TIM_PeriodElapsedCallback+0x1f8>)
- 80019a2:	789b      	ldrb	r3, [r3, #2]
- 80019a4:	2b00      	cmp	r3, #0
- 80019a6:	d003      	beq.n	80019b0 <HAL_TIM_PeriodElapsedCallback+0x174>
- 80019a8:	4b22      	ldr	r3, [pc, #136]	@ (8001a34 <HAL_TIM_PeriodElapsedCallback+0x1f8>)
- 80019aa:	881b      	ldrh	r3, [r3, #0]
- 80019ac:	b21b      	sxth	r3, r3
- 80019ae:	e004      	b.n	80019ba <HAL_TIM_PeriodElapsedCallback+0x17e>
- 80019b0:	4b20      	ldr	r3, [pc, #128]	@ (8001a34 <HAL_TIM_PeriodElapsedCallback+0x1f8>)
- 80019b2:	881b      	ldrh	r3, [r3, #0]
- 80019b4:	425b      	negs	r3, r3
- 80019b6:	b29b      	uxth	r3, r3
- 80019b8:	b21b      	sxth	r3, r3
- 80019ba:	4a1f      	ldr	r2, [pc, #124]	@ (8001a38 <HAL_TIM_PeriodElapsedCallback+0x1fc>)
- 80019bc:	8013      	strh	r3, [r2, #0]
-		set_Feeder_PWM(motor_cmd.pwm,motor_cmd.dir);
- 80019be:	4b1d      	ldr	r3, [pc, #116]	@ (8001a34 <HAL_TIM_PeriodElapsedCallback+0x1f8>)
- 80019c0:	881a      	ldrh	r2, [r3, #0]
- 80019c2:	4b1c      	ldr	r3, [pc, #112]	@ (8001a34 <HAL_TIM_PeriodElapsedCallback+0x1f8>)
- 80019c4:	789b      	ldrb	r3, [r3, #2]
- 80019c6:	0019      	movs	r1, r3
- 80019c8:	0010      	movs	r0, r2
- 80019ca:	f000 fde7 	bl	800259c <set_Feeder_PWM>
-
-		// Note: Feed completion is now handled by feed_state_machine_update() in main loop
-
-	}
-	if (htim == &htim1) return; // PWM timer
- 80019ce:	687a      	ldr	r2, [r7, #4]
- 80019d0:	4b1a      	ldr	r3, [pc, #104]	@ (8001a3c <HAL_TIM_PeriodElapsedCallback+0x200>)
- 80019d2:	429a      	cmp	r2, r3
- 80019d4:	d00f      	beq.n	80019f6 <HAL_TIM_PeriodElapsedCallback+0x1ba>
-	else if (htim == &htim3) // encoder overflow
-	{
-		// will fire upon wraparound if update IT is enabled
-	}
-	if (htim == &htim16) //SW1 timer
- 80019d6:	687a      	ldr	r2, [r7, #4]
- 80019d8:	4b19      	ldr	r3, [pc, #100]	@ (8001a40 <HAL_TIM_PeriodElapsedCallback+0x204>)
- 80019da:	429a      	cmp	r2, r3
- 80019dc:	d103      	bne.n	80019e6 <HAL_TIM_PeriodElapsedCallback+0x1aa>
-	{
-		sw1_pressed = 0;
- 80019de:	4b19      	ldr	r3, [pc, #100]	@ (8001a44 <HAL_TIM_PeriodElapsedCallback+0x208>)
- 80019e0:	2200      	movs	r2, #0
- 80019e2:	701a      	strb	r2, [r3, #0]
- 80019e4:	e008      	b.n	80019f8 <HAL_TIM_PeriodElapsedCallback+0x1bc>
-		//todo handle overflow after ~65seconds (48MHz / 48000) *
-	}
-	else if (htim == &htim17) //SW2 timer
- 80019e6:	687a      	ldr	r2, [r7, #4]
- 80019e8:	4b17      	ldr	r3, [pc, #92]	@ (8001a48 <HAL_TIM_PeriodElapsedCallback+0x20c>)
- 80019ea:	429a      	cmp	r2, r3
- 80019ec:	d104      	bne.n	80019f8 <HAL_TIM_PeriodElapsedCallback+0x1bc>
-	{
-		//todo
-		sw2_pressed = 0;
- 80019ee:	4b17      	ldr	r3, [pc, #92]	@ (8001a4c <HAL_TIM_PeriodElapsedCallback+0x210>)
- 80019f0:	2200      	movs	r2, #0
- 80019f2:	701a      	strb	r2, [r3, #0]
- 80019f4:	e000      	b.n	80019f8 <HAL_TIM_PeriodElapsedCallback+0x1bc>
-	if (htim == &htim1) return; // PWM timer
- 80019f6:	46c0      	nop			@ (mov r8, r8)
-	}
-}
- 80019f8:	46bd      	mov	sp, r7
- 80019fa:	b008      	add	sp, #32
- 80019fc:	bd80      	pop	{r7, pc}
- 80019fe:	46c0      	nop			@ (mov r8, r8)
- 8001a00:	200000e4 	.word	0x200000e4
- 8001a04:	20000098 	.word	0x20000098
- 8001a08:	200003b0 	.word	0x200003b0
- 8001a0c:	0000fc17 	.word	0x0000fc17
- 8001a10:	200003ac 	.word	0x200003ac
- 8001a14:	20000484 	.word	0x20000484
- 8001a18:	1fffffff 	.word	0x1fffffff
- 8001a1c:	20000488 	.word	0x20000488
- 8001a20:	200004d0 	.word	0x200004d0
- 8001a24:	0000ffff 	.word	0x0000ffff
- 8001a28:	20000550 	.word	0x20000550
- 8001a2c:	200004b8 	.word	0x200004b8
- 8001a30:	2000048c 	.word	0x2000048c
- 8001a34:	200004b4 	.word	0x200004b4
- 8001a38:	200005a8 	.word	0x200005a8
- 8001a3c:	2000004c 	.word	0x2000004c
- 8001a40:	20000130 	.word	0x20000130
- 8001a44:	200003a8 	.word	0x200003a8
- 8001a48:	2000017c 	.word	0x2000017c
- 8001a4c:	200003a9 	.word	0x200003a9
-
-08001a50 <HAL_GPIO_EXTI_Falling_Callback>:
-
-void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin)
-{
- 8001a50:	b580      	push	{r7, lr}
- 8001a52:	b082      	sub	sp, #8
- 8001a54:	af00      	add	r7, sp, #0
- 8001a56:	0002      	movs	r2, r0
- 8001a58:	1dbb      	adds	r3, r7, #6
- 8001a5a:	801a      	strh	r2, [r3, #0]
-    if(GPIO_Pin == SW1_Pin) // SW1 (lower button)
- 8001a5c:	1dbb      	adds	r3, r7, #6
- 8001a5e:	881a      	ldrh	r2, [r3, #0]
- 8001a60:	2380      	movs	r3, #128	@ 0x80
- 8001a62:	009b      	lsls	r3, r3, #2
- 8001a64:	429a      	cmp	r2, r3
- 8001a66:	d10f      	bne.n	8001a88 <HAL_GPIO_EXTI_Falling_Callback+0x38>
-    {
-    	if (!sw1_pressed)
- 8001a68:	4b14      	ldr	r3, [pc, #80]	@ (8001abc <HAL_GPIO_EXTI_Falling_Callback+0x6c>)
- 8001a6a:	781b      	ldrb	r3, [r3, #0]
- 8001a6c:	2b00      	cmp	r3, #0
- 8001a6e:	d120      	bne.n	8001ab2 <HAL_GPIO_EXTI_Falling_Callback+0x62>
-		{
-    		htim16.Instance->CNT = 0;
- 8001a70:	4b13      	ldr	r3, [pc, #76]	@ (8001ac0 <HAL_GPIO_EXTI_Falling_Callback+0x70>)
- 8001a72:	681b      	ldr	r3, [r3, #0]
- 8001a74:	2200      	movs	r2, #0
- 8001a76:	625a      	str	r2, [r3, #36]	@ 0x24
-    		HAL_TIM_Base_Start_IT(&htim16);
- 8001a78:	4b11      	ldr	r3, [pc, #68]	@ (8001ac0 <HAL_GPIO_EXTI_Falling_Callback+0x70>)
- 8001a7a:	0018      	movs	r0, r3
- 8001a7c:	f003 fd68 	bl	8005550 <HAL_TIM_Base_Start_IT>
-    		sw1_pressed = 1;
- 8001a80:	4b0e      	ldr	r3, [pc, #56]	@ (8001abc <HAL_GPIO_EXTI_Falling_Callback+0x6c>)
- 8001a82:	2201      	movs	r2, #1
- 8001a84:	701a      	strb	r2, [r3, #0]
-    		htim17.Instance->CNT = 0;
-    		HAL_TIM_Base_Start_IT(&htim17);
-    		sw2_pressed = 1;
-    	}
-    }
-}
- 8001a86:	e014      	b.n	8001ab2 <HAL_GPIO_EXTI_Falling_Callback+0x62>
-    else if (GPIO_Pin == SW2_Pin) // SW2 (upper button)
- 8001a88:	1dbb      	adds	r3, r7, #6
- 8001a8a:	881a      	ldrh	r2, [r3, #0]
- 8001a8c:	2380      	movs	r3, #128	@ 0x80
- 8001a8e:	005b      	lsls	r3, r3, #1
- 8001a90:	429a      	cmp	r2, r3
- 8001a92:	d10e      	bne.n	8001ab2 <HAL_GPIO_EXTI_Falling_Callback+0x62>
-    	if (!sw2_pressed)
- 8001a94:	4b0b      	ldr	r3, [pc, #44]	@ (8001ac4 <HAL_GPIO_EXTI_Falling_Callback+0x74>)
- 8001a96:	781b      	ldrb	r3, [r3, #0]
- 8001a98:	2b00      	cmp	r3, #0
- 8001a9a:	d10a      	bne.n	8001ab2 <HAL_GPIO_EXTI_Falling_Callback+0x62>
-    		htim17.Instance->CNT = 0;
- 8001a9c:	4b0a      	ldr	r3, [pc, #40]	@ (8001ac8 <HAL_GPIO_EXTI_Falling_Callback+0x78>)
- 8001a9e:	681b      	ldr	r3, [r3, #0]
- 8001aa0:	2200      	movs	r2, #0
- 8001aa2:	625a      	str	r2, [r3, #36]	@ 0x24
-    		HAL_TIM_Base_Start_IT(&htim17);
- 8001aa4:	4b08      	ldr	r3, [pc, #32]	@ (8001ac8 <HAL_GPIO_EXTI_Falling_Callback+0x78>)
- 8001aa6:	0018      	movs	r0, r3
- 8001aa8:	f003 fd52 	bl	8005550 <HAL_TIM_Base_Start_IT>
-    		sw2_pressed = 1;
- 8001aac:	4b05      	ldr	r3, [pc, #20]	@ (8001ac4 <HAL_GPIO_EXTI_Falling_Callback+0x74>)
- 8001aae:	2201      	movs	r2, #1
- 8001ab0:	701a      	strb	r2, [r3, #0]
-}
- 8001ab2:	46c0      	nop			@ (mov r8, r8)
- 8001ab4:	46bd      	mov	sp, r7
- 8001ab6:	b002      	add	sp, #8
- 8001ab8:	bd80      	pop	{r7, pc}
- 8001aba:	46c0      	nop			@ (mov r8, r8)
- 8001abc:	200003a8 	.word	0x200003a8
- 8001ac0:	20000130 	.word	0x20000130
- 8001ac4:	200003a9 	.word	0x200003a9
- 8001ac8:	2000017c 	.word	0x2000017c
-
-08001acc <HAL_UARTEx_RxEventCallback>:
-
-void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size)
-{
- 8001acc:	b580      	push	{r7, lr}
- 8001ace:	b082      	sub	sp, #8
- 8001ad0:	af00      	add	r7, sp, #0
- 8001ad2:	6078      	str	r0, [r7, #4]
- 8001ad4:	000a      	movs	r2, r1
- 8001ad6:	1cbb      	adds	r3, r7, #2
- 8001ad8:	801a      	strh	r2, [r3, #0]
-    if (Size > 64) return; // todo error handling
- 8001ada:	1cbb      	adds	r3, r7, #2
- 8001adc:	881b      	ldrh	r3, [r3, #0]
- 8001ade:	2b40      	cmp	r3, #64	@ 0x40
- 8001ae0:	d82d      	bhi.n	8001b3e <HAL_UARTEx_RxEventCallback+0x72>
-    if (msg_buffer1_empty)
- 8001ae2:	4b1a      	ldr	r3, [pc, #104]	@ (8001b4c <HAL_UARTEx_RxEventCallback+0x80>)
- 8001ae4:	781b      	ldrb	r3, [r3, #0]
- 8001ae6:	2b00      	cmp	r3, #0
- 8001ae8:	d00f      	beq.n	8001b0a <HAL_UARTEx_RxEventCallback+0x3e>
-    {
-    	memcpy(msg_buffer1, DMA_buffer, Size);
- 8001aea:	1cbb      	adds	r3, r7, #2
- 8001aec:	881a      	ldrh	r2, [r3, #0]
- 8001aee:	4918      	ldr	r1, [pc, #96]	@ (8001b50 <HAL_UARTEx_RxEventCallback+0x84>)
- 8001af0:	4b18      	ldr	r3, [pc, #96]	@ (8001b54 <HAL_UARTEx_RxEventCallback+0x88>)
- 8001af2:	0018      	movs	r0, r3
- 8001af4:	f006 f90a 	bl	8007d0c <memcpy>
-    	msg_buffer1_empty = 0;
- 8001af8:	4b14      	ldr	r3, [pc, #80]	@ (8001b4c <HAL_UARTEx_RxEventCallback+0x80>)
- 8001afa:	2200      	movs	r2, #0
- 8001afc:	701a      	strb	r2, [r3, #0]
-    	msg_buffer1_size = Size;
- 8001afe:	1cbb      	adds	r3, r7, #2
- 8001b00:	881b      	ldrh	r3, [r3, #0]
- 8001b02:	b2da      	uxtb	r2, r3
- 8001b04:	4b14      	ldr	r3, [pc, #80]	@ (8001b58 <HAL_UARTEx_RxEventCallback+0x8c>)
- 8001b06:	701a      	strb	r2, [r3, #0]
- 8001b08:	e012      	b.n	8001b30 <HAL_UARTEx_RxEventCallback+0x64>
-    }
-    else if (msg_buffer2_empty)
- 8001b0a:	4b14      	ldr	r3, [pc, #80]	@ (8001b5c <HAL_UARTEx_RxEventCallback+0x90>)
- 8001b0c:	781b      	ldrb	r3, [r3, #0]
- 8001b0e:	2b00      	cmp	r3, #0
- 8001b10:	d017      	beq.n	8001b42 <HAL_UARTEx_RxEventCallback+0x76>
-    {
-    	memcpy(msg_buffer2, DMA_buffer, Size);
- 8001b12:	1cbb      	adds	r3, r7, #2
- 8001b14:	881a      	ldrh	r2, [r3, #0]
- 8001b16:	490e      	ldr	r1, [pc, #56]	@ (8001b50 <HAL_UARTEx_RxEventCallback+0x84>)
- 8001b18:	4b11      	ldr	r3, [pc, #68]	@ (8001b60 <HAL_UARTEx_RxEventCallback+0x94>)
- 8001b1a:	0018      	movs	r0, r3
- 8001b1c:	f006 f8f6 	bl	8007d0c <memcpy>
-    	msg_buffer2_empty = 0;
- 8001b20:	4b0e      	ldr	r3, [pc, #56]	@ (8001b5c <HAL_UARTEx_RxEventCallback+0x90>)
- 8001b22:	2200      	movs	r2, #0
- 8001b24:	701a      	strb	r2, [r3, #0]
-    	msg_buffer2_size = Size;
- 8001b26:	1cbb      	adds	r3, r7, #2
- 8001b28:	881b      	ldrh	r3, [r3, #0]
- 8001b2a:	b2da      	uxtb	r2, r3
- 8001b2c:	4b0d      	ldr	r3, [pc, #52]	@ (8001b64 <HAL_UARTEx_RxEventCallback+0x98>)
- 8001b2e:	701a      	strb	r2, [r3, #0]
-    }
-    else // no free buffer available todo error handling
-    {
-    	return;
-    }
-    HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
- 8001b30:	4907      	ldr	r1, [pc, #28]	@ (8001b50 <HAL_UARTEx_RxEventCallback+0x84>)
- 8001b32:	4b0d      	ldr	r3, [pc, #52]	@ (8001b68 <HAL_UARTEx_RxEventCallback+0x9c>)
- 8001b34:	2240      	movs	r2, #64	@ 0x40
- 8001b36:	0018      	movs	r0, r3
- 8001b38:	f005 ffe8 	bl	8007b0c <HAL_UARTEx_ReceiveToIdle_DMA>
- 8001b3c:	e002      	b.n	8001b44 <HAL_UARTEx_RxEventCallback+0x78>
-    if (Size > 64) return; // todo error handling
- 8001b3e:	46c0      	nop			@ (mov r8, r8)
- 8001b40:	e000      	b.n	8001b44 <HAL_UARTEx_RxEventCallback+0x78>
-    	return;
- 8001b42:	46c0      	nop			@ (mov r8, r8)
-}
- 8001b44:	46bd      	mov	sp, r7
- 8001b46:	b002      	add	sp, #8
- 8001b48:	bd80      	pop	{r7, pc}
- 8001b4a:	46c0      	nop			@ (mov r8, r8)
- 8001b4c:	20000000 	.word	0x20000000
- 8001b50:	20000444 	.word	0x20000444
- 8001b54:	200003c4 	.word	0x200003c4
- 8001b58:	200003c1 	.word	0x200003c1
- 8001b5c:	20000001 	.word	0x20000001
- 8001b60:	20000404 	.word	0x20000404
- 8001b64:	200003c2 	.word	0x200003c2
- 8001b68:	2000025c 	.word	0x2000025c
-
-08001b6c <set_LED>:
-
-void set_LED (uint8_t R, uint8_t G, uint8_t B)
-{
- 8001b6c:	b590      	push	{r4, r7, lr}
- 8001b6e:	b083      	sub	sp, #12
- 8001b70:	af00      	add	r7, sp, #0
- 8001b72:	0004      	movs	r4, r0
- 8001b74:	0008      	movs	r0, r1
- 8001b76:	0011      	movs	r1, r2
- 8001b78:	1dfb      	adds	r3, r7, #7
- 8001b7a:	1c22      	adds	r2, r4, #0
- 8001b7c:	701a      	strb	r2, [r3, #0]
- 8001b7e:	1dbb      	adds	r3, r7, #6
- 8001b80:	1c02      	adds	r2, r0, #0
- 8001b82:	701a      	strb	r2, [r3, #0]
- 8001b84:	1d7b      	adds	r3, r7, #5
- 8001b86:	1c0a      	adds	r2, r1, #0
- 8001b88:	701a      	strb	r2, [r3, #0]
-	if (R) R = GPIO_PIN_SET;
- 8001b8a:	1dfb      	adds	r3, r7, #7
- 8001b8c:	781b      	ldrb	r3, [r3, #0]
- 8001b8e:	2b00      	cmp	r3, #0
- 8001b90:	d002      	beq.n	8001b98 <set_LED+0x2c>
- 8001b92:	1dfb      	adds	r3, r7, #7
- 8001b94:	2201      	movs	r2, #1
- 8001b96:	701a      	strb	r2, [r3, #0]
-	if (G) G = GPIO_PIN_SET;
- 8001b98:	1dbb      	adds	r3, r7, #6
- 8001b9a:	781b      	ldrb	r3, [r3, #0]
- 8001b9c:	2b00      	cmp	r3, #0
- 8001b9e:	d002      	beq.n	8001ba6 <set_LED+0x3a>
- 8001ba0:	1dbb      	adds	r3, r7, #6
- 8001ba2:	2201      	movs	r2, #1
- 8001ba4:	701a      	strb	r2, [r3, #0]
-	if (B) B = GPIO_PIN_SET;
- 8001ba6:	1d7b      	adds	r3, r7, #5
- 8001ba8:	781b      	ldrb	r3, [r3, #0]
- 8001baa:	2b00      	cmp	r3, #0
- 8001bac:	d002      	beq.n	8001bb4 <set_LED+0x48>
- 8001bae:	1d7b      	adds	r3, r7, #5
- 8001bb0:	2201      	movs	r2, #1
- 8001bb2:	701a      	strb	r2, [r3, #0]
-	HAL_GPIO_WritePin(LED_R_GPIO_Port,LED_R_Pin,R);
- 8001bb4:	1dfb      	adds	r3, r7, #7
- 8001bb6:	781b      	ldrb	r3, [r3, #0]
- 8001bb8:	480b      	ldr	r0, [pc, #44]	@ (8001be8 <set_LED+0x7c>)
- 8001bba:	001a      	movs	r2, r3
- 8001bbc:	2108      	movs	r1, #8
- 8001bbe:	f002 ff98 	bl	8004af2 <HAL_GPIO_WritePin>
-	HAL_GPIO_WritePin(LED_G_GPIO_Port,LED_G_Pin,G);
- 8001bc2:	1dbb      	adds	r3, r7, #6
- 8001bc4:	781b      	ldrb	r3, [r3, #0]
- 8001bc6:	4808      	ldr	r0, [pc, #32]	@ (8001be8 <set_LED+0x7c>)
- 8001bc8:	001a      	movs	r2, r3
- 8001bca:	2120      	movs	r1, #32
- 8001bcc:	f002 ff91 	bl	8004af2 <HAL_GPIO_WritePin>
-	HAL_GPIO_WritePin(LED_B_GPIO_Port,LED_B_Pin,B);
- 8001bd0:	1d7b      	adds	r3, r7, #5
- 8001bd2:	781b      	ldrb	r3, [r3, #0]
- 8001bd4:	4804      	ldr	r0, [pc, #16]	@ (8001be8 <set_LED+0x7c>)
- 8001bd6:	001a      	movs	r2, r3
- 8001bd8:	2110      	movs	r1, #16
- 8001bda:	f002 ff8a 	bl	8004af2 <HAL_GPIO_WritePin>
-}
- 8001bde:	46c0      	nop			@ (mov r8, r8)
- 8001be0:	46bd      	mov	sp, r7
- 8001be2:	b003      	add	sp, #12
- 8001be4:	bd90      	pop	{r4, r7, pc}
- 8001be6:	46c0      	nop			@ (mov r8, r8)
- 8001be8:	50000400 	.word	0x50000400
-
-08001bec <comp_crc_header>:
-
-void comp_crc_header(CRC8_107 *lcrc, PhotonResponse *lresponse)
-{
- 8001bec:	b580      	push	{r7, lr}
- 8001bee:	b082      	sub	sp, #8
- 8001bf0:	af00      	add	r7, sp, #0
- 8001bf2:	6078      	str	r0, [r7, #4]
- 8001bf4:	6039      	str	r1, [r7, #0]
-	CRC8_107_add(lcrc,lresponse->header.toAddress);
- 8001bf6:	683b      	ldr	r3, [r7, #0]
- 8001bf8:	781a      	ldrb	r2, [r3, #0]
- 8001bfa:	687b      	ldr	r3, [r7, #4]
- 8001bfc:	0011      	movs	r1, r2
- 8001bfe:	0018      	movs	r0, r3
- 8001c00:	f7fe fd7e 	bl	8000700 <CRC8_107_add>
-	CRC8_107_add(lcrc,lresponse->header.fromAddress);
- 8001c04:	683b      	ldr	r3, [r7, #0]
- 8001c06:	785a      	ldrb	r2, [r3, #1]
- 8001c08:	687b      	ldr	r3, [r7, #4]
- 8001c0a:	0011      	movs	r1, r2
- 8001c0c:	0018      	movs	r0, r3
- 8001c0e:	f7fe fd77 	bl	8000700 <CRC8_107_add>
-	CRC8_107_add(lcrc,lresponse->header.packetId);
- 8001c12:	683b      	ldr	r3, [r7, #0]
- 8001c14:	789a      	ldrb	r2, [r3, #2]
- 8001c16:	687b      	ldr	r3, [r7, #4]
- 8001c18:	0011      	movs	r1, r2
- 8001c1a:	0018      	movs	r0, r3
- 8001c1c:	f7fe fd70 	bl	8000700 <CRC8_107_add>
-	CRC8_107_add(lcrc,lresponse->header.payloadLength);
- 8001c20:	683b      	ldr	r3, [r7, #0]
- 8001c22:	78da      	ldrb	r2, [r3, #3]
- 8001c24:	687b      	ldr	r3, [r7, #4]
- 8001c26:	0011      	movs	r1, r2
- 8001c28:	0018      	movs	r0, r3
- 8001c2a:	f7fe fd69 	bl	8000700 <CRC8_107_add>
-}
- 8001c2e:	46c0      	nop			@ (mov r8, r8)
- 8001c30:	46bd      	mov	sp, r7
- 8001c32:	b002      	add	sp, #8
- 8001c34:	bd80      	pop	{r7, pc}
-	...
-
-08001c38 <handleRS485Message>:
-
-void handleRS485Message(uint8_t *buffer, uint8_t size)
-{
- 8001c38:	b5f0      	push	{r4, r5, r6, r7, lr}
- 8001c3a:	b09f      	sub	sp, #124	@ 0x7c
- 8001c3c:	af00      	add	r7, sp, #0
- 8001c3e:	6078      	str	r0, [r7, #4]
- 8001c40:	000a      	movs	r2, r1
- 8001c42:	1cfb      	adds	r3, r7, #3
- 8001c44:	701a      	strb	r2, [r3, #0]
-	PhotonPacketHeader *header = (PhotonPacketHeader *) buffer;
- 8001c46:	687b      	ldr	r3, [r7, #4]
- 8001c48:	64bb      	str	r3, [r7, #72]	@ 0x48
-
-	// Validate minimum packet size
-	if (size < sizeof(PhotonPacketHeader) + 1) // header + at least commandId
- 8001c4a:	1cfb      	adds	r3, r7, #3
- 8001c4c:	781b      	ldrb	r3, [r3, #0]
- 8001c4e:	2b05      	cmp	r3, #5
- 8001c50:	d801      	bhi.n	8001c56 <handleRS485Message+0x1e>
- 8001c52:	f000 fc87 	bl	8002564 <handleRS485Message+0x92c>
-		return; // packet too small
-	}
-
-	// Validate CRC
-	CRC8_107 rx_crc;
-	CRC8_107_init(&rx_crc);
- 8001c56:	242c      	movs	r4, #44	@ 0x2c
- 8001c58:	193b      	adds	r3, r7, r4
- 8001c5a:	0018      	movs	r0, r3
- 8001c5c:	f7fe feb6 	bl	80009cc <CRC8_107_init>
-	CRC8_107_add(&rx_crc, header->toAddress);
- 8001c60:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
- 8001c62:	781a      	ldrb	r2, [r3, #0]
- 8001c64:	193b      	adds	r3, r7, r4
- 8001c66:	0011      	movs	r1, r2
- 8001c68:	0018      	movs	r0, r3
- 8001c6a:	f7fe fd49 	bl	8000700 <CRC8_107_add>
-	CRC8_107_add(&rx_crc, header->fromAddress);
- 8001c6e:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
- 8001c70:	785a      	ldrb	r2, [r3, #1]
- 8001c72:	193b      	adds	r3, r7, r4
- 8001c74:	0011      	movs	r1, r2
- 8001c76:	0018      	movs	r0, r3
- 8001c78:	f7fe fd42 	bl	8000700 <CRC8_107_add>
-	CRC8_107_add(&rx_crc, header->packetId);
- 8001c7c:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
- 8001c7e:	789a      	ldrb	r2, [r3, #2]
- 8001c80:	193b      	adds	r3, r7, r4
- 8001c82:	0011      	movs	r1, r2
- 8001c84:	0018      	movs	r0, r3
- 8001c86:	f7fe fd3b 	bl	8000700 <CRC8_107_add>
-	CRC8_107_add(&rx_crc, header->payloadLength);
- 8001c8a:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
- 8001c8c:	78da      	ldrb	r2, [r3, #3]
- 8001c8e:	193b      	adds	r3, r7, r4
- 8001c90:	0011      	movs	r1, r2
- 8001c92:	0018      	movs	r0, r3
- 8001c94:	f7fe fd34 	bl	8000700 <CRC8_107_add>
-	// Add payload bytes to CRC (everything after header)
-	for (uint8_t i = 0; i < header->payloadLength; i++)
- 8001c98:	2377      	movs	r3, #119	@ 0x77
- 8001c9a:	18fb      	adds	r3, r7, r3
- 8001c9c:	2200      	movs	r2, #0
- 8001c9e:	701a      	strb	r2, [r3, #0]
- 8001ca0:	e011      	b.n	8001cc6 <handleRS485Message+0x8e>
-	{
-		CRC8_107_add(&rx_crc, buffer[sizeof(PhotonPacketHeader) + i]);
- 8001ca2:	2477      	movs	r4, #119	@ 0x77
- 8001ca4:	193b      	adds	r3, r7, r4
- 8001ca6:	781b      	ldrb	r3, [r3, #0]
- 8001ca8:	3305      	adds	r3, #5
- 8001caa:	687a      	ldr	r2, [r7, #4]
- 8001cac:	18d3      	adds	r3, r2, r3
- 8001cae:	781a      	ldrb	r2, [r3, #0]
- 8001cb0:	232c      	movs	r3, #44	@ 0x2c
- 8001cb2:	18fb      	adds	r3, r7, r3
- 8001cb4:	0011      	movs	r1, r2
- 8001cb6:	0018      	movs	r0, r3
- 8001cb8:	f7fe fd22 	bl	8000700 <CRC8_107_add>
-	for (uint8_t i = 0; i < header->payloadLength; i++)
- 8001cbc:	193b      	adds	r3, r7, r4
- 8001cbe:	781a      	ldrb	r2, [r3, #0]
- 8001cc0:	193b      	adds	r3, r7, r4
- 8001cc2:	3201      	adds	r2, #1
- 8001cc4:	701a      	strb	r2, [r3, #0]
- 8001cc6:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
- 8001cc8:	78db      	ldrb	r3, [r3, #3]
- 8001cca:	2277      	movs	r2, #119	@ 0x77
- 8001ccc:	18ba      	adds	r2, r7, r2
- 8001cce:	7812      	ldrb	r2, [r2, #0]
- 8001cd0:	429a      	cmp	r2, r3
- 8001cd2:	d3e6      	bcc.n	8001ca2 <handleRS485Message+0x6a>
-	}
-	if (CRC8_107_getChecksum(&rx_crc) != header->crc)
- 8001cd4:	232c      	movs	r3, #44	@ 0x2c
- 8001cd6:	18fb      	adds	r3, r7, r3
- 8001cd8:	0018      	movs	r0, r3
- 8001cda:	f7fe fd41 	bl	8000760 <CRC8_107_getChecksum>
- 8001cde:	0003      	movs	r3, r0
- 8001ce0:	001a      	movs	r2, r3
- 8001ce2:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
- 8001ce4:	791b      	ldrb	r3, [r3, #4]
- 8001ce6:	429a      	cmp	r2, r3
- 8001ce8:	d001      	beq.n	8001cee <handleRS485Message+0xb6>
- 8001cea:	f000 fc3d 	bl	8002568 <handleRS485Message+0x930>
-	{
-		return; // CRC mismatch, discard packet
-	}
-
-	// check if message is for this device or is broadcast
-	if ((header->toAddress != PHOTON_NETWORK_BROADCAST_ADDRESS) &&
- 8001cee:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
- 8001cf0:	781b      	ldrb	r3, [r3, #0]
- 8001cf2:	2bff      	cmp	r3, #255	@ 0xff
- 8001cf4:	d007      	beq.n	8001d06 <handleRS485Message+0xce>
-		(header->toAddress != my_address))
- 8001cf6:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
- 8001cf8:	781a      	ldrb	r2, [r3, #0]
- 8001cfa:	4bde      	ldr	r3, [pc, #888]	@ (8002074 <handleRS485Message+0x43c>)
- 8001cfc:	781b      	ldrb	r3, [r3, #0]
-	if ((header->toAddress != PHOTON_NETWORK_BROADCAST_ADDRESS) &&
- 8001cfe:	429a      	cmp	r2, r3
- 8001d00:	d001      	beq.n	8001d06 <handleRS485Message+0xce>
- 8001d02:	f000 fc33 	bl	800256c <handleRS485Message+0x934>
-		return; // message not for us
-	}
-
-	// this message is relevant to this device (unicast to us or broadcast)
-	{
-		PhotonCommand *command = (PhotonCommand *) buffer;
- 8001d06:	687b      	ldr	r3, [r7, #4]
- 8001d08:	647b      	str	r3, [r7, #68]	@ 0x44
-		PhotonResponse response;
-		CRC8_107 crc;
-		CRC8_107_init(&crc);
- 8001d0a:	230c      	movs	r3, #12
- 8001d0c:	18fb      	adds	r3, r7, r3
- 8001d0e:	0018      	movs	r0, r3
- 8001d10:	f7fe fe5c 	bl	80009cc <CRC8_107_init>
-		response.header.fromAddress = my_address;
- 8001d14:	4bd7      	ldr	r3, [pc, #860]	@ (8002074 <handleRS485Message+0x43c>)
- 8001d16:	781a      	ldrb	r2, [r3, #0]
- 8001d18:	2110      	movs	r1, #16
- 8001d1a:	187b      	adds	r3, r7, r1
- 8001d1c:	705a      	strb	r2, [r3, #1]
-		response.header.packetId = command->header.packetId;
- 8001d1e:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 8001d20:	789a      	ldrb	r2, [r3, #2]
- 8001d22:	187b      	adds	r3, r7, r1
- 8001d24:	709a      	strb	r2, [r3, #2]
-		response.header.toAddress = command->header.fromAddress;
- 8001d26:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 8001d28:	785a      	ldrb	r2, [r3, #1]
- 8001d2a:	187b      	adds	r3, r7, r1
- 8001d2c:	701a      	strb	r2, [r3, #0]
-		uint8_t *payload_ptr;
-		size_t packet_len;
-		switch (command->commandId)
- 8001d2e:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 8001d30:	795b      	ldrb	r3, [r3, #5]
- 8001d32:	2b06      	cmp	r3, #6
- 8001d34:	dc16      	bgt.n	8001d64 <handleRS485Message+0x12c>
- 8001d36:	2b00      	cmp	r3, #0
- 8001d38:	dc0b      	bgt.n	8001d52 <handleRS485Message+0x11a>
-				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
-				break;
-			default:
-				// todo error handling
-				return;
- 8001d3a:	f000 fc19 	bl	8002570 <handleRS485Message+0x938>
-		switch (command->commandId)
- 8001d3e:	3bbf      	subs	r3, #191	@ 0xbf
- 8001d40:	2b04      	cmp	r3, #4
- 8001d42:	d901      	bls.n	8001d48 <handleRS485Message+0x110>
- 8001d44:	f000 fc14 	bl	8002570 <handleRS485Message+0x938>
- 8001d48:	009a      	lsls	r2, r3, #2
- 8001d4a:	4bcb      	ldr	r3, [pc, #812]	@ (8002078 <handleRS485Message+0x440>)
- 8001d4c:	18d3      	adds	r3, r2, r3
- 8001d4e:	681b      	ldr	r3, [r3, #0]
- 8001d50:	469f      	mov	pc, r3
- 8001d52:	2b06      	cmp	r3, #6
- 8001d54:	d901      	bls.n	8001d5a <handleRS485Message+0x122>
- 8001d56:	f000 fc0b 	bl	8002570 <handleRS485Message+0x938>
- 8001d5a:	009a      	lsls	r2, r3, #2
- 8001d5c:	4bc7      	ldr	r3, [pc, #796]	@ (800207c <handleRS485Message+0x444>)
- 8001d5e:	18d3      	adds	r3, r2, r3
- 8001d60:	681b      	ldr	r3, [r3, #0]
- 8001d62:	469f      	mov	pc, r3
- 8001d64:	2bc3      	cmp	r3, #195	@ 0xc3
- 8001d66:	dd01      	ble.n	8001d6c <handleRS485Message+0x134>
- 8001d68:	f000 fc02 	bl	8002570 <handleRS485Message+0x938>
- 8001d6c:	2bbf      	cmp	r3, #191	@ 0xbf
- 8001d6e:	dae6      	bge.n	8001d3e <handleRS485Message+0x106>
-				return;
- 8001d70:	f000 fbfe 	bl	8002570 <handleRS485Message+0x938>
-				memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH);
- 8001d74:	2410      	movs	r4, #16
- 8001d76:	193b      	adds	r3, r7, r4
- 8001d78:	2206      	movs	r2, #6
- 8001d7a:	49c1      	ldr	r1, [pc, #772]	@ (8002080 <handleRS485Message+0x448>)
- 8001d7c:	189b      	adds	r3, r3, r2
- 8001d7e:	220c      	movs	r2, #12
- 8001d80:	0018      	movs	r0, r3
- 8001d82:	f005 ffc3 	bl	8007d0c <memcpy>
-				response.status = STATUS_OK;
- 8001d86:	193b      	adds	r3, r7, r4
- 8001d88:	2200      	movs	r2, #0
- 8001d8a:	715a      	strb	r2, [r3, #5]
-				comp_crc_header(&crc,&response);
- 8001d8c:	193a      	adds	r2, r7, r4
- 8001d8e:	230c      	movs	r3, #12
- 8001d90:	18fb      	adds	r3, r7, r3
- 8001d92:	0011      	movs	r1, r2
- 8001d94:	0018      	movs	r0, r3
- 8001d96:	f7ff ff29 	bl	8001bec <comp_crc_header>
-				payload_ptr =(uint8_t*) &response.payload;
- 8001d9a:	193b      	adds	r3, r7, r4
- 8001d9c:	3306      	adds	r3, #6
- 8001d9e:	643b      	str	r3, [r7, #64]	@ 0x40
-				for (uint32_t i = 0; i<sizeof(response.payload.getFeederId)+1; i++)
- 8001da0:	2300      	movs	r3, #0
- 8001da2:	673b      	str	r3, [r7, #112]	@ 0x70
- 8001da4:	e00c      	b.n	8001dc0 <handleRS485Message+0x188>
-					CRC8_107_add(&crc,*(payload_ptr+i));
- 8001da6:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
- 8001da8:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
- 8001daa:	18d3      	adds	r3, r2, r3
- 8001dac:	781a      	ldrb	r2, [r3, #0]
- 8001dae:	230c      	movs	r3, #12
- 8001db0:	18fb      	adds	r3, r7, r3
- 8001db2:	0011      	movs	r1, r2
- 8001db4:	0018      	movs	r0, r3
- 8001db6:	f7fe fca3 	bl	8000700 <CRC8_107_add>
-				for (uint32_t i = 0; i<sizeof(response.payload.getFeederId)+1; i++)
- 8001dba:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
- 8001dbc:	3301      	adds	r3, #1
- 8001dbe:	673b      	str	r3, [r7, #112]	@ 0x70
- 8001dc0:	6f3b      	ldr	r3, [r7, #112]	@ 0x70
- 8001dc2:	2b0c      	cmp	r3, #12
- 8001dc4:	d9ef      	bls.n	8001da6 <handleRS485Message+0x16e>
-				response.header.crc = CRC8_107_getChecksum(&crc);
- 8001dc6:	230c      	movs	r3, #12
- 8001dc8:	18fb      	adds	r3, r7, r3
- 8001dca:	0018      	movs	r0, r3
- 8001dcc:	f7fe fcc8 	bl	8000760 <CRC8_107_getChecksum>
- 8001dd0:	0003      	movs	r3, r0
- 8001dd2:	001a      	movs	r2, r3
- 8001dd4:	2110      	movs	r1, #16
- 8001dd6:	187b      	adds	r3, r7, r1
- 8001dd8:	711a      	strb	r2, [r3, #4]
-				response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for the length byte
- 8001dda:	187b      	adds	r3, r7, r1
- 8001ddc:	220d      	movs	r2, #13
- 8001dde:	70da      	strb	r2, [r3, #3]
-				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 8001de0:	187b      	adds	r3, r7, r1
- 8001de2:	78db      	ldrb	r3, [r3, #3]
- 8001de4:	3305      	adds	r3, #5
- 8001de6:	63fb      	str	r3, [r7, #60]	@ 0x3c
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
- 8001de8:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8001dea:	b29a      	uxth	r2, r3
- 8001dec:	1879      	adds	r1, r7, r1
- 8001dee:	48a5      	ldr	r0, [pc, #660]	@ (8002084 <handleRS485Message+0x44c>)
- 8001df0:	2364      	movs	r3, #100	@ 0x64
- 8001df2:	f004 fed3 	bl	8006b9c <HAL_UART_Transmit>
-				break;
- 8001df6:	f000 fbc2 	bl	800257e <handleRS485Message+0x946>
-				memcpy(response.payload.initializeFeeder.uuid,UUID,UUID_LENGTH);
- 8001dfa:	2410      	movs	r4, #16
- 8001dfc:	193b      	adds	r3, r7, r4
- 8001dfe:	2206      	movs	r2, #6
- 8001e00:	499f      	ldr	r1, [pc, #636]	@ (8002080 <handleRS485Message+0x448>)
- 8001e02:	189b      	adds	r3, r3, r2
- 8001e04:	220c      	movs	r2, #12
- 8001e06:	0018      	movs	r0, r3
- 8001e08:	f005 ff80 	bl	8007d0c <memcpy>
-				if(memcmp(UUID,command->payload.initializeFeeder.uuid,UUID_LENGTH) == 0)
- 8001e0c:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 8001e0e:	1d99      	adds	r1, r3, #6
- 8001e10:	4b9b      	ldr	r3, [pc, #620]	@ (8002080 <handleRS485Message+0x448>)
- 8001e12:	220c      	movs	r2, #12
- 8001e14:	0018      	movs	r0, r3
- 8001e16:	f005 ff3f 	bl	8007c98 <memcmp>
- 8001e1a:	1e03      	subs	r3, r0, #0
- 8001e1c:	d106      	bne.n	8001e2c <handleRS485Message+0x1f4>
-					is_initialized = 1;
- 8001e1e:	4b9a      	ldr	r3, [pc, #616]	@ (8002088 <handleRS485Message+0x450>)
- 8001e20:	2201      	movs	r2, #1
- 8001e22:	701a      	strb	r2, [r3, #0]
-					response.status = STATUS_OK;
- 8001e24:	193b      	adds	r3, r7, r4
- 8001e26:	2200      	movs	r2, #0
- 8001e28:	715a      	strb	r2, [r3, #5]
- 8001e2a:	e003      	b.n	8001e34 <handleRS485Message+0x1fc>
-					response.status = STATUS_WRONG_FEEDER_ID;
- 8001e2c:	2310      	movs	r3, #16
- 8001e2e:	18fb      	adds	r3, r7, r3
- 8001e30:	2201      	movs	r2, #1
- 8001e32:	715a      	strb	r2, [r3, #5]
-				comp_crc_header(&crc,&response);
- 8001e34:	2410      	movs	r4, #16
- 8001e36:	193a      	adds	r2, r7, r4
- 8001e38:	230c      	movs	r3, #12
- 8001e3a:	18fb      	adds	r3, r7, r3
- 8001e3c:	0011      	movs	r1, r2
- 8001e3e:	0018      	movs	r0, r3
- 8001e40:	f7ff fed4 	bl	8001bec <comp_crc_header>
-				payload_ptr =(uint8_t*) &response.payload;
- 8001e44:	193b      	adds	r3, r7, r4
- 8001e46:	3306      	adds	r3, #6
- 8001e48:	643b      	str	r3, [r7, #64]	@ 0x40
-				for (uint32_t i = 0; i<sizeof(response.payload.initializeFeeder)+1; i++)
- 8001e4a:	2300      	movs	r3, #0
- 8001e4c:	66fb      	str	r3, [r7, #108]	@ 0x6c
- 8001e4e:	e00c      	b.n	8001e6a <handleRS485Message+0x232>
-					CRC8_107_add(&crc,*(payload_ptr+i));
- 8001e50:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
- 8001e52:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
- 8001e54:	18d3      	adds	r3, r2, r3
- 8001e56:	781a      	ldrb	r2, [r3, #0]
- 8001e58:	230c      	movs	r3, #12
- 8001e5a:	18fb      	adds	r3, r7, r3
- 8001e5c:	0011      	movs	r1, r2
- 8001e5e:	0018      	movs	r0, r3
- 8001e60:	f7fe fc4e 	bl	8000700 <CRC8_107_add>
-				for (uint32_t i = 0; i<sizeof(response.payload.initializeFeeder)+1; i++)
- 8001e64:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
- 8001e66:	3301      	adds	r3, #1
- 8001e68:	66fb      	str	r3, [r7, #108]	@ 0x6c
- 8001e6a:	6efb      	ldr	r3, [r7, #108]	@ 0x6c
- 8001e6c:	2b0c      	cmp	r3, #12
- 8001e6e:	d9ef      	bls.n	8001e50 <handleRS485Message+0x218>
-				response.header.crc = CRC8_107_getChecksum(&crc);
- 8001e70:	230c      	movs	r3, #12
- 8001e72:	18fb      	adds	r3, r7, r3
- 8001e74:	0018      	movs	r0, r3
- 8001e76:	f7fe fc73 	bl	8000760 <CRC8_107_getChecksum>
- 8001e7a:	0003      	movs	r3, r0
- 8001e7c:	001a      	movs	r2, r3
- 8001e7e:	2110      	movs	r1, #16
- 8001e80:	187b      	adds	r3, r7, r1
- 8001e82:	711a      	strb	r2, [r3, #4]
-				response.header.payloadLength = sizeof(response.payload.initializeFeeder)+1; // +1 for the length byte
- 8001e84:	187b      	adds	r3, r7, r1
- 8001e86:	220d      	movs	r2, #13
- 8001e88:	70da      	strb	r2, [r3, #3]
-				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 8001e8a:	187b      	adds	r3, r7, r1
- 8001e8c:	78db      	ldrb	r3, [r3, #3]
- 8001e8e:	3305      	adds	r3, #5
- 8001e90:	63fb      	str	r3, [r7, #60]	@ 0x3c
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
- 8001e92:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8001e94:	b29a      	uxth	r2, r3
- 8001e96:	1879      	adds	r1, r7, r1
- 8001e98:	487a      	ldr	r0, [pc, #488]	@ (8002084 <handleRS485Message+0x44c>)
- 8001e9a:	2364      	movs	r3, #100	@ 0x64
- 8001e9c:	f004 fe7e 	bl	8006b9c <HAL_UART_Transmit>
-				break;
- 8001ea0:	e36d      	b.n	800257e <handleRS485Message+0x946>
-				response.status = STATUS_OK;
- 8001ea2:	2410      	movs	r4, #16
- 8001ea4:	193b      	adds	r3, r7, r4
- 8001ea6:	2200      	movs	r2, #0
- 8001ea8:	715a      	strb	r2, [r3, #5]
-				response.payload.protocolVersion.version = PROTOCOL_VERSION;
- 8001eaa:	193b      	adds	r3, r7, r4
- 8001eac:	2201      	movs	r2, #1
- 8001eae:	719a      	strb	r2, [r3, #6]
-				comp_crc_header(&crc,&response);
- 8001eb0:	193a      	adds	r2, r7, r4
- 8001eb2:	230c      	movs	r3, #12
- 8001eb4:	18fb      	adds	r3, r7, r3
- 8001eb6:	0011      	movs	r1, r2
- 8001eb8:	0018      	movs	r0, r3
- 8001eba:	f7ff fe97 	bl	8001bec <comp_crc_header>
-				payload_ptr =(uint8_t*) &response.payload;
- 8001ebe:	193b      	adds	r3, r7, r4
- 8001ec0:	3306      	adds	r3, #6
- 8001ec2:	643b      	str	r3, [r7, #64]	@ 0x40
-				for (uint32_t i = 0; i<sizeof(response.payload.protocolVersion)+1; i++)
- 8001ec4:	2300      	movs	r3, #0
- 8001ec6:	66bb      	str	r3, [r7, #104]	@ 0x68
- 8001ec8:	e00c      	b.n	8001ee4 <handleRS485Message+0x2ac>
-					CRC8_107_add(&crc,*(payload_ptr+i));
- 8001eca:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
- 8001ecc:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
- 8001ece:	18d3      	adds	r3, r2, r3
- 8001ed0:	781a      	ldrb	r2, [r3, #0]
- 8001ed2:	230c      	movs	r3, #12
- 8001ed4:	18fb      	adds	r3, r7, r3
- 8001ed6:	0011      	movs	r1, r2
- 8001ed8:	0018      	movs	r0, r3
- 8001eda:	f7fe fc11 	bl	8000700 <CRC8_107_add>
-				for (uint32_t i = 0; i<sizeof(response.payload.protocolVersion)+1; i++)
- 8001ede:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
- 8001ee0:	3301      	adds	r3, #1
- 8001ee2:	66bb      	str	r3, [r7, #104]	@ 0x68
- 8001ee4:	6ebb      	ldr	r3, [r7, #104]	@ 0x68
- 8001ee6:	2b01      	cmp	r3, #1
- 8001ee8:	d9ef      	bls.n	8001eca <handleRS485Message+0x292>
-				response.header.crc = CRC8_107_getChecksum(&crc);
- 8001eea:	230c      	movs	r3, #12
- 8001eec:	18fb      	adds	r3, r7, r3
- 8001eee:	0018      	movs	r0, r3
- 8001ef0:	f7fe fc36 	bl	8000760 <CRC8_107_getChecksum>
- 8001ef4:	0003      	movs	r3, r0
- 8001ef6:	001a      	movs	r2, r3
- 8001ef8:	2110      	movs	r1, #16
- 8001efa:	187b      	adds	r3, r7, r1
- 8001efc:	711a      	strb	r2, [r3, #4]
-				response.header.payloadLength = sizeof(response.payload.protocolVersion)+1; // +1 for the length byte
- 8001efe:	187b      	adds	r3, r7, r1
- 8001f00:	2202      	movs	r2, #2
- 8001f02:	70da      	strb	r2, [r3, #3]
-				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 8001f04:	187b      	adds	r3, r7, r1
- 8001f06:	78db      	ldrb	r3, [r3, #3]
- 8001f08:	3305      	adds	r3, #5
- 8001f0a:	63fb      	str	r3, [r7, #60]	@ 0x3c
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
- 8001f0c:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8001f0e:	b29a      	uxth	r2, r3
- 8001f10:	1879      	adds	r1, r7, r1
- 8001f12:	485c      	ldr	r0, [pc, #368]	@ (8002084 <handleRS485Message+0x44c>)
- 8001f14:	2364      	movs	r3, #100	@ 0x64
- 8001f16:	f004 fe41 	bl	8006b9c <HAL_UART_Transmit>
-				break;
- 8001f1a:	e330      	b.n	800257e <handleRS485Message+0x946>
-				if (!is_initialized)
- 8001f1c:	4b5a      	ldr	r3, [pc, #360]	@ (8002088 <handleRS485Message+0x450>)
- 8001f1e:	781b      	ldrb	r3, [r3, #0]
- 8001f20:	2b00      	cmp	r3, #0
- 8001f22:	d144      	bne.n	8001fae <handleRS485Message+0x376>
-					response.status = STATUS_UNINITIALIZED_FEEDER;
- 8001f24:	2410      	movs	r4, #16
- 8001f26:	193b      	adds	r3, r7, r4
- 8001f28:	2203      	movs	r2, #3
- 8001f2a:	715a      	strb	r2, [r3, #5]
-					memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
- 8001f2c:	193b      	adds	r3, r7, r4
- 8001f2e:	2206      	movs	r2, #6
- 8001f30:	4953      	ldr	r1, [pc, #332]	@ (8002080 <handleRS485Message+0x448>)
- 8001f32:	189b      	adds	r3, r3, r2
- 8001f34:	220c      	movs	r2, #12
- 8001f36:	0018      	movs	r0, r3
- 8001f38:	f005 fee8 	bl	8007d0c <memcpy>
-					response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
- 8001f3c:	193b      	adds	r3, r7, r4
- 8001f3e:	220d      	movs	r2, #13
- 8001f40:	70da      	strb	r2, [r3, #3]
-					comp_crc_header(&crc, &response);
- 8001f42:	193a      	adds	r2, r7, r4
- 8001f44:	230c      	movs	r3, #12
- 8001f46:	18fb      	adds	r3, r7, r3
- 8001f48:	0011      	movs	r1, r2
- 8001f4a:	0018      	movs	r0, r3
- 8001f4c:	f7ff fe4e 	bl	8001bec <comp_crc_header>
-					payload_ptr = (uint8_t*)&response.status;
- 8001f50:	193b      	adds	r3, r7, r4
- 8001f52:	3305      	adds	r3, #5
- 8001f54:	643b      	str	r3, [r7, #64]	@ 0x40
-					for (uint32_t i = 0; i < response.header.payloadLength; i++)
- 8001f56:	2300      	movs	r3, #0
- 8001f58:	667b      	str	r3, [r7, #100]	@ 0x64
- 8001f5a:	e00c      	b.n	8001f76 <handleRS485Message+0x33e>
-						CRC8_107_add(&crc, *(payload_ptr + i));
- 8001f5c:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
- 8001f5e:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
- 8001f60:	18d3      	adds	r3, r2, r3
- 8001f62:	781a      	ldrb	r2, [r3, #0]
- 8001f64:	230c      	movs	r3, #12
- 8001f66:	18fb      	adds	r3, r7, r3
- 8001f68:	0011      	movs	r1, r2
- 8001f6a:	0018      	movs	r0, r3
- 8001f6c:	f7fe fbc8 	bl	8000700 <CRC8_107_add>
-					for (uint32_t i = 0; i < response.header.payloadLength; i++)
- 8001f70:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
- 8001f72:	3301      	adds	r3, #1
- 8001f74:	667b      	str	r3, [r7, #100]	@ 0x64
- 8001f76:	2410      	movs	r4, #16
- 8001f78:	193b      	adds	r3, r7, r4
- 8001f7a:	78db      	ldrb	r3, [r3, #3]
- 8001f7c:	001a      	movs	r2, r3
- 8001f7e:	6e7b      	ldr	r3, [r7, #100]	@ 0x64
- 8001f80:	4293      	cmp	r3, r2
- 8001f82:	d3eb      	bcc.n	8001f5c <handleRS485Message+0x324>
-					response.header.crc = CRC8_107_getChecksum(&crc);
- 8001f84:	230c      	movs	r3, #12
- 8001f86:	18fb      	adds	r3, r7, r3
- 8001f88:	0018      	movs	r0, r3
- 8001f8a:	f7fe fbe9 	bl	8000760 <CRC8_107_getChecksum>
- 8001f8e:	0003      	movs	r3, r0
- 8001f90:	001a      	movs	r2, r3
- 8001f92:	193b      	adds	r3, r7, r4
- 8001f94:	711a      	strb	r2, [r3, #4]
-					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 8001f96:	193b      	adds	r3, r7, r4
- 8001f98:	78db      	ldrb	r3, [r3, #3]
- 8001f9a:	3305      	adds	r3, #5
- 8001f9c:	63fb      	str	r3, [r7, #60]	@ 0x3c
-					HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100);
- 8001f9e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8001fa0:	b29a      	uxth	r2, r3
- 8001fa2:	1939      	adds	r1, r7, r4
- 8001fa4:	4837      	ldr	r0, [pc, #220]	@ (8002084 <handleRS485Message+0x44c>)
- 8001fa6:	2364      	movs	r3, #100	@ 0x64
- 8001fa8:	f004 fdf8 	bl	8006b9c <HAL_UART_Transmit>
-					break;
- 8001fac:	e2e7      	b.n	800257e <handleRS485Message+0x946>
-					uint16_t exp_time = calculate_expected_feed_time(command->payload.move.distance, 1);
- 8001fae:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 8001fb0:	799b      	ldrb	r3, [r3, #6]
- 8001fb2:	2534      	movs	r5, #52	@ 0x34
- 8001fb4:	197c      	adds	r4, r7, r5
- 8001fb6:	2101      	movs	r1, #1
- 8001fb8:	0018      	movs	r0, r3
- 8001fba:	f000 fcb1 	bl	8002920 <calculate_expected_feed_time>
- 8001fbe:	0003      	movs	r3, r0
- 8001fc0:	8023      	strh	r3, [r4, #0]
-					uint16_t exp_time_be = (exp_time >> 8) | (exp_time << 8); // byte swap for network order
- 8001fc2:	0029      	movs	r1, r5
- 8001fc4:	187b      	adds	r3, r7, r1
- 8001fc6:	881b      	ldrh	r3, [r3, #0]
- 8001fc8:	0a1b      	lsrs	r3, r3, #8
- 8001fca:	b29b      	uxth	r3, r3
- 8001fcc:	b21a      	sxth	r2, r3
- 8001fce:	187b      	adds	r3, r7, r1
- 8001fd0:	2100      	movs	r1, #0
- 8001fd2:	5e5b      	ldrsh	r3, [r3, r1]
- 8001fd4:	021b      	lsls	r3, r3, #8
- 8001fd6:	b21b      	sxth	r3, r3
- 8001fd8:	4313      	orrs	r3, r2
- 8001fda:	b21a      	sxth	r2, r3
- 8001fdc:	2032      	movs	r0, #50	@ 0x32
- 8001fde:	183b      	adds	r3, r7, r0
- 8001fe0:	801a      	strh	r2, [r3, #0]
-					response.status = STATUS_OK;
- 8001fe2:	2110      	movs	r1, #16
- 8001fe4:	187b      	adds	r3, r7, r1
- 8001fe6:	2200      	movs	r2, #0
- 8001fe8:	715a      	strb	r2, [r3, #5]
-					response.payload.expectedTimeToFeed.expectedFeedTime = exp_time_be;
- 8001fea:	187b      	adds	r3, r7, r1
- 8001fec:	183a      	adds	r2, r7, r0
- 8001fee:	8812      	ldrh	r2, [r2, #0]
- 8001ff0:	80da      	strh	r2, [r3, #6]
-					response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
- 8001ff2:	187b      	adds	r3, r7, r1
- 8001ff4:	2203      	movs	r2, #3
- 8001ff6:	70da      	strb	r2, [r3, #3]
-					comp_crc_header(&crc, &response);
- 8001ff8:	000c      	movs	r4, r1
- 8001ffa:	187a      	adds	r2, r7, r1
- 8001ffc:	230c      	movs	r3, #12
- 8001ffe:	18fb      	adds	r3, r7, r3
- 8002000:	0011      	movs	r1, r2
- 8002002:	0018      	movs	r0, r3
- 8002004:	f7ff fdf2 	bl	8001bec <comp_crc_header>
-					payload_ptr = (uint8_t*)&response.status;
- 8002008:	193b      	adds	r3, r7, r4
- 800200a:	3305      	adds	r3, #5
- 800200c:	643b      	str	r3, [r7, #64]	@ 0x40
-					for (uint32_t i = 0; i < response.header.payloadLength; i++)
- 800200e:	2300      	movs	r3, #0
- 8002010:	663b      	str	r3, [r7, #96]	@ 0x60
- 8002012:	e00c      	b.n	800202e <handleRS485Message+0x3f6>
-						CRC8_107_add(&crc, *(payload_ptr + i));
- 8002014:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
- 8002016:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
- 8002018:	18d3      	adds	r3, r2, r3
- 800201a:	781a      	ldrb	r2, [r3, #0]
- 800201c:	230c      	movs	r3, #12
- 800201e:	18fb      	adds	r3, r7, r3
- 8002020:	0011      	movs	r1, r2
- 8002022:	0018      	movs	r0, r3
- 8002024:	f7fe fb6c 	bl	8000700 <CRC8_107_add>
-					for (uint32_t i = 0; i < response.header.payloadLength; i++)
- 8002028:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
- 800202a:	3301      	adds	r3, #1
- 800202c:	663b      	str	r3, [r7, #96]	@ 0x60
- 800202e:	2410      	movs	r4, #16
- 8002030:	193b      	adds	r3, r7, r4
- 8002032:	78db      	ldrb	r3, [r3, #3]
- 8002034:	001a      	movs	r2, r3
- 8002036:	6e3b      	ldr	r3, [r7, #96]	@ 0x60
- 8002038:	4293      	cmp	r3, r2
- 800203a:	d3eb      	bcc.n	8002014 <handleRS485Message+0x3dc>
-					response.header.crc = CRC8_107_getChecksum(&crc);
- 800203c:	230c      	movs	r3, #12
- 800203e:	18fb      	adds	r3, r7, r3
- 8002040:	0018      	movs	r0, r3
- 8002042:	f7fe fb8d 	bl	8000760 <CRC8_107_getChecksum>
- 8002046:	0003      	movs	r3, r0
- 8002048:	001a      	movs	r2, r3
- 800204a:	193b      	adds	r3, r7, r4
- 800204c:	711a      	strb	r2, [r3, #4]
-					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 800204e:	193b      	adds	r3, r7, r4
- 8002050:	78db      	ldrb	r3, [r3, #3]
- 8002052:	3305      	adds	r3, #5
- 8002054:	63fb      	str	r3, [r7, #60]	@ 0x3c
-					HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100);
- 8002056:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8002058:	b29a      	uxth	r2, r3
- 800205a:	1939      	adds	r1, r7, r4
- 800205c:	4809      	ldr	r0, [pc, #36]	@ (8002084 <handleRS485Message+0x44c>)
- 800205e:	2364      	movs	r3, #100	@ 0x64
- 8002060:	f004 fd9c 	bl	8006b9c <HAL_UART_Transmit>
-					start_feed(command->payload.move.distance, 1);
- 8002064:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 8002066:	799b      	ldrb	r3, [r3, #6]
- 8002068:	b21b      	sxth	r3, r3
- 800206a:	2101      	movs	r1, #1
- 800206c:	0018      	movs	r0, r3
- 800206e:	f000 fc9f 	bl	80029b0 <start_feed>
-				break;
- 8002072:	e284      	b.n	800257e <handleRS485Message+0x946>
- 8002074:	20000002 	.word	0x20000002
- 8002078:	08007d58 	.word	0x08007d58
- 800207c:	08007d6c 	.word	0x08007d6c
- 8002080:	200003b4 	.word	0x200003b4
- 8002084:	2000025c 	.word	0x2000025c
- 8002088:	200003c0 	.word	0x200003c0
-				if (!is_initialized)
- 800208c:	4be9      	ldr	r3, [pc, #932]	@ (8002434 <handleRS485Message+0x7fc>)
- 800208e:	781b      	ldrb	r3, [r3, #0]
- 8002090:	2b00      	cmp	r3, #0
- 8002092:	d144      	bne.n	800211e <handleRS485Message+0x4e6>
-					response.status = STATUS_UNINITIALIZED_FEEDER;
- 8002094:	2410      	movs	r4, #16
- 8002096:	193b      	adds	r3, r7, r4
- 8002098:	2203      	movs	r2, #3
- 800209a:	715a      	strb	r2, [r3, #5]
-					memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
- 800209c:	193b      	adds	r3, r7, r4
- 800209e:	2206      	movs	r2, #6
- 80020a0:	49e5      	ldr	r1, [pc, #916]	@ (8002438 <handleRS485Message+0x800>)
- 80020a2:	189b      	adds	r3, r3, r2
- 80020a4:	220c      	movs	r2, #12
- 80020a6:	0018      	movs	r0, r3
- 80020a8:	f005 fe30 	bl	8007d0c <memcpy>
-					response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
- 80020ac:	193b      	adds	r3, r7, r4
- 80020ae:	220d      	movs	r2, #13
- 80020b0:	70da      	strb	r2, [r3, #3]
-					comp_crc_header(&crc, &response);
- 80020b2:	193a      	adds	r2, r7, r4
- 80020b4:	230c      	movs	r3, #12
- 80020b6:	18fb      	adds	r3, r7, r3
- 80020b8:	0011      	movs	r1, r2
- 80020ba:	0018      	movs	r0, r3
- 80020bc:	f7ff fd96 	bl	8001bec <comp_crc_header>
-					payload_ptr = (uint8_t*)&response.status;
- 80020c0:	193b      	adds	r3, r7, r4
- 80020c2:	3305      	adds	r3, #5
- 80020c4:	643b      	str	r3, [r7, #64]	@ 0x40
-					for (uint32_t i = 0; i < response.header.payloadLength; i++)
- 80020c6:	2300      	movs	r3, #0
- 80020c8:	65fb      	str	r3, [r7, #92]	@ 0x5c
- 80020ca:	e00c      	b.n	80020e6 <handleRS485Message+0x4ae>
-						CRC8_107_add(&crc, *(payload_ptr + i));
- 80020cc:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
- 80020ce:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
- 80020d0:	18d3      	adds	r3, r2, r3
- 80020d2:	781a      	ldrb	r2, [r3, #0]
- 80020d4:	230c      	movs	r3, #12
- 80020d6:	18fb      	adds	r3, r7, r3
- 80020d8:	0011      	movs	r1, r2
- 80020da:	0018      	movs	r0, r3
- 80020dc:	f7fe fb10 	bl	8000700 <CRC8_107_add>
-					for (uint32_t i = 0; i < response.header.payloadLength; i++)
- 80020e0:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
- 80020e2:	3301      	adds	r3, #1
- 80020e4:	65fb      	str	r3, [r7, #92]	@ 0x5c
- 80020e6:	2410      	movs	r4, #16
- 80020e8:	193b      	adds	r3, r7, r4
- 80020ea:	78db      	ldrb	r3, [r3, #3]
- 80020ec:	001a      	movs	r2, r3
- 80020ee:	6dfb      	ldr	r3, [r7, #92]	@ 0x5c
- 80020f0:	4293      	cmp	r3, r2
- 80020f2:	d3eb      	bcc.n	80020cc <handleRS485Message+0x494>
-					response.header.crc = CRC8_107_getChecksum(&crc);
- 80020f4:	230c      	movs	r3, #12
- 80020f6:	18fb      	adds	r3, r7, r3
- 80020f8:	0018      	movs	r0, r3
- 80020fa:	f7fe fb31 	bl	8000760 <CRC8_107_getChecksum>
- 80020fe:	0003      	movs	r3, r0
- 8002100:	001a      	movs	r2, r3
- 8002102:	193b      	adds	r3, r7, r4
- 8002104:	711a      	strb	r2, [r3, #4]
-					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 8002106:	193b      	adds	r3, r7, r4
- 8002108:	78db      	ldrb	r3, [r3, #3]
- 800210a:	3305      	adds	r3, #5
- 800210c:	63fb      	str	r3, [r7, #60]	@ 0x3c
-					HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100);
- 800210e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8002110:	b29a      	uxth	r2, r3
- 8002112:	1939      	adds	r1, r7, r4
- 8002114:	48c9      	ldr	r0, [pc, #804]	@ (800243c <handleRS485Message+0x804>)
- 8002116:	2364      	movs	r3, #100	@ 0x64
- 8002118:	f004 fd40 	bl	8006b9c <HAL_UART_Transmit>
-					break;
- 800211c:	e22f      	b.n	800257e <handleRS485Message+0x946>
-					uint16_t exp_time = calculate_expected_feed_time(command->payload.move.distance, 0);
- 800211e:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 8002120:	799b      	ldrb	r3, [r3, #6]
- 8002122:	2538      	movs	r5, #56	@ 0x38
- 8002124:	197c      	adds	r4, r7, r5
- 8002126:	2100      	movs	r1, #0
- 8002128:	0018      	movs	r0, r3
- 800212a:	f000 fbf9 	bl	8002920 <calculate_expected_feed_time>
- 800212e:	0003      	movs	r3, r0
- 8002130:	8023      	strh	r3, [r4, #0]
-					uint16_t exp_time_be = (exp_time >> 8) | (exp_time << 8); // byte swap for network order
- 8002132:	0029      	movs	r1, r5
- 8002134:	187b      	adds	r3, r7, r1
- 8002136:	881b      	ldrh	r3, [r3, #0]
- 8002138:	0a1b      	lsrs	r3, r3, #8
- 800213a:	b29b      	uxth	r3, r3
- 800213c:	b21a      	sxth	r2, r3
- 800213e:	187b      	adds	r3, r7, r1
- 8002140:	2100      	movs	r1, #0
- 8002142:	5e5b      	ldrsh	r3, [r3, r1]
- 8002144:	021b      	lsls	r3, r3, #8
- 8002146:	b21b      	sxth	r3, r3
- 8002148:	4313      	orrs	r3, r2
- 800214a:	b21a      	sxth	r2, r3
- 800214c:	2036      	movs	r0, #54	@ 0x36
- 800214e:	183b      	adds	r3, r7, r0
- 8002150:	801a      	strh	r2, [r3, #0]
-					response.status = STATUS_OK;
- 8002152:	2110      	movs	r1, #16
- 8002154:	187b      	adds	r3, r7, r1
- 8002156:	2200      	movs	r2, #0
- 8002158:	715a      	strb	r2, [r3, #5]
-					response.payload.expectedTimeToFeed.expectedFeedTime = exp_time_be;
- 800215a:	187b      	adds	r3, r7, r1
- 800215c:	183a      	adds	r2, r7, r0
- 800215e:	8812      	ldrh	r2, [r2, #0]
- 8002160:	80da      	strh	r2, [r3, #6]
-					response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
- 8002162:	187b      	adds	r3, r7, r1
- 8002164:	2203      	movs	r2, #3
- 8002166:	70da      	strb	r2, [r3, #3]
-					comp_crc_header(&crc, &response);
- 8002168:	000c      	movs	r4, r1
- 800216a:	187a      	adds	r2, r7, r1
- 800216c:	230c      	movs	r3, #12
- 800216e:	18fb      	adds	r3, r7, r3
- 8002170:	0011      	movs	r1, r2
- 8002172:	0018      	movs	r0, r3
- 8002174:	f7ff fd3a 	bl	8001bec <comp_crc_header>
-					payload_ptr = (uint8_t*)&response.status;
- 8002178:	193b      	adds	r3, r7, r4
- 800217a:	3305      	adds	r3, #5
- 800217c:	643b      	str	r3, [r7, #64]	@ 0x40
-					for (uint32_t i = 0; i < response.header.payloadLength; i++)
- 800217e:	2300      	movs	r3, #0
- 8002180:	65bb      	str	r3, [r7, #88]	@ 0x58
- 8002182:	e00c      	b.n	800219e <handleRS485Message+0x566>
-						CRC8_107_add(&crc, *(payload_ptr + i));
- 8002184:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
- 8002186:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
- 8002188:	18d3      	adds	r3, r2, r3
- 800218a:	781a      	ldrb	r2, [r3, #0]
- 800218c:	230c      	movs	r3, #12
- 800218e:	18fb      	adds	r3, r7, r3
- 8002190:	0011      	movs	r1, r2
- 8002192:	0018      	movs	r0, r3
- 8002194:	f7fe fab4 	bl	8000700 <CRC8_107_add>
-					for (uint32_t i = 0; i < response.header.payloadLength; i++)
- 8002198:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
- 800219a:	3301      	adds	r3, #1
- 800219c:	65bb      	str	r3, [r7, #88]	@ 0x58
- 800219e:	2410      	movs	r4, #16
- 80021a0:	193b      	adds	r3, r7, r4
- 80021a2:	78db      	ldrb	r3, [r3, #3]
- 80021a4:	001a      	movs	r2, r3
- 80021a6:	6dbb      	ldr	r3, [r7, #88]	@ 0x58
- 80021a8:	4293      	cmp	r3, r2
- 80021aa:	d3eb      	bcc.n	8002184 <handleRS485Message+0x54c>
-					response.header.crc = CRC8_107_getChecksum(&crc);
- 80021ac:	230c      	movs	r3, #12
- 80021ae:	18fb      	adds	r3, r7, r3
- 80021b0:	0018      	movs	r0, r3
- 80021b2:	f7fe fad5 	bl	8000760 <CRC8_107_getChecksum>
- 80021b6:	0003      	movs	r3, r0
- 80021b8:	001a      	movs	r2, r3
- 80021ba:	193b      	adds	r3, r7, r4
- 80021bc:	711a      	strb	r2, [r3, #4]
-					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 80021be:	193b      	adds	r3, r7, r4
- 80021c0:	78db      	ldrb	r3, [r3, #3]
- 80021c2:	3305      	adds	r3, #5
- 80021c4:	63fb      	str	r3, [r7, #60]	@ 0x3c
-					HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100);
- 80021c6:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 80021c8:	b29a      	uxth	r2, r3
- 80021ca:	1939      	adds	r1, r7, r4
- 80021cc:	489b      	ldr	r0, [pc, #620]	@ (800243c <handleRS485Message+0x804>)
- 80021ce:	2364      	movs	r3, #100	@ 0x64
- 80021d0:	f004 fce4 	bl	8006b9c <HAL_UART_Transmit>
-					start_feed(command->payload.move.distance, 0);
- 80021d4:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 80021d6:	799b      	ldrb	r3, [r3, #6]
- 80021d8:	b21b      	sxth	r3, r3
- 80021da:	2100      	movs	r1, #0
- 80021dc:	0018      	movs	r0, r3
- 80021de:	f000 fbe7 	bl	80029b0 <start_feed>
-				break;
- 80021e2:	e1cc      	b.n	800257e <handleRS485Message+0x946>
-				if (feed_in_progress)
- 80021e4:	4b96      	ldr	r3, [pc, #600]	@ (8002440 <handleRS485Message+0x808>)
- 80021e6:	781b      	ldrb	r3, [r3, #0]
- 80021e8:	b2db      	uxtb	r3, r3
- 80021ea:	2b00      	cmp	r3, #0
- 80021ec:	d004      	beq.n	80021f8 <handleRS485Message+0x5c0>
-					response.status = STATUS_FEEDING_IN_PROGRESS;
- 80021ee:	2310      	movs	r3, #16
- 80021f0:	18fb      	adds	r3, r7, r3
- 80021f2:	2204      	movs	r2, #4
- 80021f4:	715a      	strb	r2, [r3, #5]
- 80021f6:	e004      	b.n	8002202 <handleRS485Message+0x5ca>
-					response.status = last_feed_status;
- 80021f8:	4b92      	ldr	r3, [pc, #584]	@ (8002444 <handleRS485Message+0x80c>)
- 80021fa:	781a      	ldrb	r2, [r3, #0]
- 80021fc:	2310      	movs	r3, #16
- 80021fe:	18fb      	adds	r3, r7, r3
- 8002200:	715a      	strb	r2, [r3, #5]
-				response.header.payloadLength = 1; // only status byte
- 8002202:	2410      	movs	r4, #16
- 8002204:	193b      	adds	r3, r7, r4
- 8002206:	2201      	movs	r2, #1
- 8002208:	70da      	strb	r2, [r3, #3]
-				comp_crc_header(&crc,&response);
- 800220a:	193a      	adds	r2, r7, r4
- 800220c:	250c      	movs	r5, #12
- 800220e:	197b      	adds	r3, r7, r5
- 8002210:	0011      	movs	r1, r2
- 8002212:	0018      	movs	r0, r3
- 8002214:	f7ff fcea 	bl	8001bec <comp_crc_header>
-				CRC8_107_add(&crc, response.status);
- 8002218:	193b      	adds	r3, r7, r4
- 800221a:	795a      	ldrb	r2, [r3, #5]
- 800221c:	197b      	adds	r3, r7, r5
- 800221e:	0011      	movs	r1, r2
- 8002220:	0018      	movs	r0, r3
- 8002222:	f7fe fa6d 	bl	8000700 <CRC8_107_add>
-				response.header.crc = CRC8_107_getChecksum(&crc);
- 8002226:	197b      	adds	r3, r7, r5
- 8002228:	0018      	movs	r0, r3
- 800222a:	f7fe fa99 	bl	8000760 <CRC8_107_getChecksum>
- 800222e:	0003      	movs	r3, r0
- 8002230:	001a      	movs	r2, r3
- 8002232:	193b      	adds	r3, r7, r4
- 8002234:	711a      	strb	r2, [r3, #4]
-				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 8002236:	193b      	adds	r3, r7, r4
- 8002238:	78db      	ldrb	r3, [r3, #3]
- 800223a:	3305      	adds	r3, #5
- 800223c:	63fb      	str	r3, [r7, #60]	@ 0x3c
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
- 800223e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8002240:	b29a      	uxth	r2, r3
- 8002242:	1939      	adds	r1, r7, r4
- 8002244:	487d      	ldr	r0, [pc, #500]	@ (800243c <handleRS485Message+0x804>)
- 8002246:	2364      	movs	r3, #100	@ 0x64
- 8002248:	f004 fca8 	bl	8006b9c <HAL_UART_Transmit>
-				break;
- 800224c:	e197      	b.n	800257e <handleRS485Message+0x946>
-				if (!is_initialized)
- 800224e:	4b79      	ldr	r3, [pc, #484]	@ (8002434 <handleRS485Message+0x7fc>)
- 8002250:	781b      	ldrb	r3, [r3, #0]
- 8002252:	2b00      	cmp	r3, #0
- 8002254:	d144      	bne.n	80022e0 <handleRS485Message+0x6a8>
-					response.status = STATUS_UNINITIALIZED_FEEDER;
- 8002256:	2410      	movs	r4, #16
- 8002258:	193b      	adds	r3, r7, r4
- 800225a:	2203      	movs	r2, #3
- 800225c:	715a      	strb	r2, [r3, #5]
-					memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
- 800225e:	193b      	adds	r3, r7, r4
- 8002260:	2206      	movs	r2, #6
- 8002262:	4975      	ldr	r1, [pc, #468]	@ (8002438 <handleRS485Message+0x800>)
- 8002264:	189b      	adds	r3, r3, r2
- 8002266:	220c      	movs	r2, #12
- 8002268:	0018      	movs	r0, r3
- 800226a:	f005 fd4f 	bl	8007d0c <memcpy>
-					response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
- 800226e:	193b      	adds	r3, r7, r4
- 8002270:	220d      	movs	r2, #13
- 8002272:	70da      	strb	r2, [r3, #3]
-					comp_crc_header(&crc, &response);
- 8002274:	193a      	adds	r2, r7, r4
- 8002276:	230c      	movs	r3, #12
- 8002278:	18fb      	adds	r3, r7, r3
- 800227a:	0011      	movs	r1, r2
- 800227c:	0018      	movs	r0, r3
- 800227e:	f7ff fcb5 	bl	8001bec <comp_crc_header>
-					payload_ptr = (uint8_t*)&response.status;
- 8002282:	193b      	adds	r3, r7, r4
- 8002284:	3305      	adds	r3, #5
- 8002286:	643b      	str	r3, [r7, #64]	@ 0x40
-					for (uint32_t i = 0; i < response.header.payloadLength; i++)
- 8002288:	2300      	movs	r3, #0
- 800228a:	657b      	str	r3, [r7, #84]	@ 0x54
- 800228c:	e00c      	b.n	80022a8 <handleRS485Message+0x670>
-						CRC8_107_add(&crc, *(payload_ptr + i));
- 800228e:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
- 8002290:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
- 8002292:	18d3      	adds	r3, r2, r3
- 8002294:	781a      	ldrb	r2, [r3, #0]
- 8002296:	230c      	movs	r3, #12
- 8002298:	18fb      	adds	r3, r7, r3
- 800229a:	0011      	movs	r1, r2
- 800229c:	0018      	movs	r0, r3
- 800229e:	f7fe fa2f 	bl	8000700 <CRC8_107_add>
-					for (uint32_t i = 0; i < response.header.payloadLength; i++)
- 80022a2:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
- 80022a4:	3301      	adds	r3, #1
- 80022a6:	657b      	str	r3, [r7, #84]	@ 0x54
- 80022a8:	2410      	movs	r4, #16
- 80022aa:	193b      	adds	r3, r7, r4
- 80022ac:	78db      	ldrb	r3, [r3, #3]
- 80022ae:	001a      	movs	r2, r3
- 80022b0:	6d7b      	ldr	r3, [r7, #84]	@ 0x54
- 80022b2:	4293      	cmp	r3, r2
- 80022b4:	d3eb      	bcc.n	800228e <handleRS485Message+0x656>
-					response.header.crc = CRC8_107_getChecksum(&crc);
- 80022b6:	230c      	movs	r3, #12
- 80022b8:	18fb      	adds	r3, r7, r3
- 80022ba:	0018      	movs	r0, r3
- 80022bc:	f7fe fa50 	bl	8000760 <CRC8_107_getChecksum>
- 80022c0:	0003      	movs	r3, r0
- 80022c2:	001a      	movs	r2, r3
- 80022c4:	193b      	adds	r3, r7, r4
- 80022c6:	711a      	strb	r2, [r3, #4]
-					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 80022c8:	193b      	adds	r3, r7, r4
- 80022ca:	78db      	ldrb	r3, [r3, #3]
- 80022cc:	3305      	adds	r3, #5
- 80022ce:	63fb      	str	r3, [r7, #60]	@ 0x3c
-					HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100);
- 80022d0:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 80022d2:	b29a      	uxth	r2, r3
- 80022d4:	1939      	adds	r1, r7, r4
- 80022d6:	4859      	ldr	r0, [pc, #356]	@ (800243c <handleRS485Message+0x804>)
- 80022d8:	2364      	movs	r3, #100	@ 0x64
- 80022da:	f004 fc5f 	bl	8006b9c <HAL_UART_Transmit>
-					break;
- 80022de:	e14e      	b.n	800257e <handleRS485Message+0x946>
-				handle_vendor_options(command->payload.vendorOptions.options, response.payload.vendorOptions.options);
- 80022e0:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 80022e2:	1d9a      	adds	r2, r3, #6
- 80022e4:	2410      	movs	r4, #16
- 80022e6:	193b      	adds	r3, r7, r4
- 80022e8:	3306      	adds	r3, #6
- 80022ea:	0019      	movs	r1, r3
- 80022ec:	0010      	movs	r0, r2
- 80022ee:	f000 fe15 	bl	8002f1c <handle_vendor_options>
-				response.status = STATUS_OK;
- 80022f2:	193b      	adds	r3, r7, r4
- 80022f4:	2200      	movs	r2, #0
- 80022f6:	715a      	strb	r2, [r3, #5]
-				comp_crc_header(&crc,&response);
- 80022f8:	193a      	adds	r2, r7, r4
- 80022fa:	230c      	movs	r3, #12
- 80022fc:	18fb      	adds	r3, r7, r3
- 80022fe:	0011      	movs	r1, r2
- 8002300:	0018      	movs	r0, r3
- 8002302:	f7ff fc73 	bl	8001bec <comp_crc_header>
-				payload_ptr =(uint8_t*) &response.status;
- 8002306:	193b      	adds	r3, r7, r4
- 8002308:	3305      	adds	r3, #5
- 800230a:	643b      	str	r3, [r7, #64]	@ 0x40
-				for (uint32_t i = 0; i<sizeof(response.payload.vendorOptions)+1; i++)
- 800230c:	2300      	movs	r3, #0
- 800230e:	653b      	str	r3, [r7, #80]	@ 0x50
- 8002310:	e00c      	b.n	800232c <handleRS485Message+0x6f4>
-					CRC8_107_add(&crc,*(payload_ptr+i));
- 8002312:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
- 8002314:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
- 8002316:	18d3      	adds	r3, r2, r3
- 8002318:	781a      	ldrb	r2, [r3, #0]
- 800231a:	230c      	movs	r3, #12
- 800231c:	18fb      	adds	r3, r7, r3
- 800231e:	0011      	movs	r1, r2
- 8002320:	0018      	movs	r0, r3
- 8002322:	f7fe f9ed 	bl	8000700 <CRC8_107_add>
-				for (uint32_t i = 0; i<sizeof(response.payload.vendorOptions)+1; i++)
- 8002326:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
- 8002328:	3301      	adds	r3, #1
- 800232a:	653b      	str	r3, [r7, #80]	@ 0x50
- 800232c:	6d3b      	ldr	r3, [r7, #80]	@ 0x50
- 800232e:	2b14      	cmp	r3, #20
- 8002330:	d9ef      	bls.n	8002312 <handleRS485Message+0x6da>
-				response.header.crc = CRC8_107_getChecksum(&crc);
- 8002332:	230c      	movs	r3, #12
- 8002334:	18fb      	adds	r3, r7, r3
- 8002336:	0018      	movs	r0, r3
- 8002338:	f7fe fa12 	bl	8000760 <CRC8_107_getChecksum>
- 800233c:	0003      	movs	r3, r0
- 800233e:	001a      	movs	r2, r3
- 8002340:	2110      	movs	r1, #16
- 8002342:	187b      	adds	r3, r7, r1
- 8002344:	711a      	strb	r2, [r3, #4]
-				response.header.payloadLength = sizeof(response.payload.vendorOptions)+1; // +1 for the status byte
- 8002346:	187b      	adds	r3, r7, r1
- 8002348:	2215      	movs	r2, #21
- 800234a:	70da      	strb	r2, [r3, #3]
-				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 800234c:	187b      	adds	r3, r7, r1
- 800234e:	78db      	ldrb	r3, [r3, #3]
- 8002350:	3305      	adds	r3, #5
- 8002352:	63fb      	str	r3, [r7, #60]	@ 0x3c
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
- 8002354:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8002356:	b29a      	uxth	r2, r3
- 8002358:	1879      	adds	r1, r7, r1
- 800235a:	4838      	ldr	r0, [pc, #224]	@ (800243c <handleRS485Message+0x804>)
- 800235c:	2364      	movs	r3, #100	@ 0x64
- 800235e:	f004 fc1d 	bl	8006b9c <HAL_UART_Transmit>
-				break;
- 8002362:	e10c      	b.n	800257e <handleRS485Message+0x946>
-				if(memcmp(UUID,command->payload.getFeederAddress.uuid,UUID_LENGTH) == 0)
- 8002364:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 8002366:	1d99      	adds	r1, r3, #6
- 8002368:	4b33      	ldr	r3, [pc, #204]	@ (8002438 <handleRS485Message+0x800>)
- 800236a:	220c      	movs	r2, #12
- 800236c:	0018      	movs	r0, r3
- 800236e:	f005 fc93 	bl	8007c98 <memcmp>
- 8002372:	1e03      	subs	r3, r0, #0
- 8002374:	d000      	beq.n	8002378 <handleRS485Message+0x740>
- 8002376:	e0fd      	b.n	8002574 <handleRS485Message+0x93c>
-					response.status = STATUS_OK;
- 8002378:	2410      	movs	r4, #16
- 800237a:	193b      	adds	r3, r7, r4
- 800237c:	2200      	movs	r2, #0
- 800237e:	715a      	strb	r2, [r3, #5]
-				response.header.payloadLength = 1; // only status byte
- 8002380:	193b      	adds	r3, r7, r4
- 8002382:	2201      	movs	r2, #1
- 8002384:	70da      	strb	r2, [r3, #3]
-				comp_crc_header(&crc,&response);
- 8002386:	193a      	adds	r2, r7, r4
- 8002388:	250c      	movs	r5, #12
- 800238a:	197b      	adds	r3, r7, r5
- 800238c:	0011      	movs	r1, r2
- 800238e:	0018      	movs	r0, r3
- 8002390:	f7ff fc2c 	bl	8001bec <comp_crc_header>
-				CRC8_107_add(&crc,response.status);
- 8002394:	193b      	adds	r3, r7, r4
- 8002396:	795a      	ldrb	r2, [r3, #5]
- 8002398:	197b      	adds	r3, r7, r5
- 800239a:	0011      	movs	r1, r2
- 800239c:	0018      	movs	r0, r3
- 800239e:	f7fe f9af 	bl	8000700 <CRC8_107_add>
-				response.header.crc = CRC8_107_getChecksum(&crc);
- 80023a2:	197b      	adds	r3, r7, r5
- 80023a4:	0018      	movs	r0, r3
- 80023a6:	f7fe f9db 	bl	8000760 <CRC8_107_getChecksum>
- 80023aa:	0003      	movs	r3, r0
- 80023ac:	001a      	movs	r2, r3
- 80023ae:	193b      	adds	r3, r7, r4
- 80023b0:	711a      	strb	r2, [r3, #4]
-				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 80023b2:	193b      	adds	r3, r7, r4
- 80023b4:	78db      	ldrb	r3, [r3, #3]
- 80023b6:	3305      	adds	r3, #5
- 80023b8:	63fb      	str	r3, [r7, #60]	@ 0x3c
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
- 80023ba:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 80023bc:	b29a      	uxth	r2, r3
- 80023be:	1939      	adds	r1, r7, r4
- 80023c0:	481e      	ldr	r0, [pc, #120]	@ (800243c <handleRS485Message+0x804>)
- 80023c2:	2364      	movs	r3, #100	@ 0x64
- 80023c4:	f004 fbea 	bl	8006b9c <HAL_UART_Transmit>
-				break;
- 80023c8:	e0d9      	b.n	800257e <handleRS485Message+0x946>
-				if(memcmp(UUID,command->payload.identifyFeeder.uuid,UUID_LENGTH) == 0)
- 80023ca:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 80023cc:	1d99      	adds	r1, r3, #6
- 80023ce:	4b1a      	ldr	r3, [pc, #104]	@ (8002438 <handleRS485Message+0x800>)
- 80023d0:	220c      	movs	r2, #12
- 80023d2:	0018      	movs	r0, r3
- 80023d4:	f005 fc60 	bl	8007c98 <memcmp>
- 80023d8:	1e03      	subs	r3, r0, #0
- 80023da:	d000      	beq.n	80023de <handleRS485Message+0x7a6>
- 80023dc:	e0cc      	b.n	8002578 <handleRS485Message+0x940>
-					response.status = STATUS_OK;
- 80023de:	2410      	movs	r4, #16
- 80023e0:	193b      	adds	r3, r7, r4
- 80023e2:	2200      	movs	r2, #0
- 80023e4:	715a      	strb	r2, [r3, #5]
-				response.header.payloadLength = 1; // only status byte
- 80023e6:	193b      	adds	r3, r7, r4
- 80023e8:	2201      	movs	r2, #1
- 80023ea:	70da      	strb	r2, [r3, #3]
-				comp_crc_header(&crc,&response);
- 80023ec:	193a      	adds	r2, r7, r4
- 80023ee:	250c      	movs	r5, #12
- 80023f0:	197b      	adds	r3, r7, r5
- 80023f2:	0011      	movs	r1, r2
- 80023f4:	0018      	movs	r0, r3
- 80023f6:	f7ff fbf9 	bl	8001bec <comp_crc_header>
-				CRC8_107_add(&crc,response.status);
- 80023fa:	193b      	adds	r3, r7, r4
- 80023fc:	795a      	ldrb	r2, [r3, #5]
- 80023fe:	197b      	adds	r3, r7, r5
- 8002400:	0011      	movs	r1, r2
- 8002402:	0018      	movs	r0, r3
- 8002404:	f7fe f97c 	bl	8000700 <CRC8_107_add>
-				response.header.crc = CRC8_107_getChecksum(&crc);
- 8002408:	197b      	adds	r3, r7, r5
- 800240a:	0018      	movs	r0, r3
- 800240c:	f7fe f9a8 	bl	8000760 <CRC8_107_getChecksum>
- 8002410:	0003      	movs	r3, r0
- 8002412:	001a      	movs	r2, r3
- 8002414:	193b      	adds	r3, r7, r4
- 8002416:	711a      	strb	r2, [r3, #4]
-				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 8002418:	193b      	adds	r3, r7, r4
- 800241a:	78db      	ldrb	r3, [r3, #3]
- 800241c:	3305      	adds	r3, #5
- 800241e:	63fb      	str	r3, [r7, #60]	@ 0x3c
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
- 8002420:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8002422:	b29a      	uxth	r2, r3
- 8002424:	1939      	adds	r1, r7, r4
- 8002426:	4805      	ldr	r0, [pc, #20]	@ (800243c <handleRS485Message+0x804>)
- 8002428:	2364      	movs	r3, #100	@ 0x64
- 800242a:	f004 fbb7 	bl	8006b9c <HAL_UART_Transmit>
-				identify_feeder();
- 800242e:	f000 fa15 	bl	800285c <identify_feeder>
-				break;
- 8002432:	e0a4      	b.n	800257e <handleRS485Message+0x946>
- 8002434:	200003c0 	.word	0x200003c0
- 8002438:	200003b4 	.word	0x200003b4
- 800243c:	2000025c 	.word	0x2000025c
- 8002440:	200004bd 	.word	0x200004bd
- 8002444:	200004bc 	.word	0x200004bc
-					uint8_t new_address = command->payload.programFeederFloorAddress.address;
- 8002448:	253b      	movs	r5, #59	@ 0x3b
- 800244a:	197b      	adds	r3, r7, r5
- 800244c:	6c7a      	ldr	r2, [r7, #68]	@ 0x44
- 800244e:	7c92      	ldrb	r2, [r2, #18]
- 8002450:	701a      	strb	r2, [r3, #0]
-					uint8_t write_success = write_floor_address(new_address);
- 8002452:	263a      	movs	r6, #58	@ 0x3a
- 8002454:	19bc      	adds	r4, r7, r6
- 8002456:	197b      	adds	r3, r7, r5
- 8002458:	781b      	ldrb	r3, [r3, #0]
- 800245a:	0018      	movs	r0, r3
- 800245c:	f000 ffcf 	bl	80033fe <write_floor_address>
- 8002460:	0003      	movs	r3, r0
- 8002462:	7023      	strb	r3, [r4, #0]
-					if (write_success)
- 8002464:	19bb      	adds	r3, r7, r6
- 8002466:	781b      	ldrb	r3, [r3, #0]
- 8002468:	2b00      	cmp	r3, #0
- 800246a:	d00f      	beq.n	800248c <handleRS485Message+0x854>
-						my_address = new_address;
- 800246c:	4b45      	ldr	r3, [pc, #276]	@ (8002584 <handleRS485Message+0x94c>)
- 800246e:	197a      	adds	r2, r7, r5
- 8002470:	7812      	ldrb	r2, [r2, #0]
- 8002472:	701a      	strb	r2, [r3, #0]
-						floor_address = new_address;
- 8002474:	4b44      	ldr	r3, [pc, #272]	@ (8002588 <handleRS485Message+0x950>)
- 8002476:	197a      	adds	r2, r7, r5
- 8002478:	7812      	ldrb	r2, [r2, #0]
- 800247a:	701a      	strb	r2, [r3, #0]
-						floor_address_status = 2;
- 800247c:	4b43      	ldr	r3, [pc, #268]	@ (800258c <handleRS485Message+0x954>)
- 800247e:	2202      	movs	r2, #2
- 8002480:	701a      	strb	r2, [r3, #0]
-						response.status = STATUS_OK;
- 8002482:	2310      	movs	r3, #16
- 8002484:	18fb      	adds	r3, r7, r3
- 8002486:	2200      	movs	r2, #0
- 8002488:	715a      	strb	r2, [r3, #5]
- 800248a:	e003      	b.n	8002494 <handleRS485Message+0x85c>
-						response.status = STATUS_FAIL;
- 800248c:	2310      	movs	r3, #16
- 800248e:	18fb      	adds	r3, r7, r3
- 8002490:	2205      	movs	r2, #5
- 8002492:	715a      	strb	r2, [r3, #5]
-					response.header.payloadLength = 1; // only status byte
- 8002494:	2410      	movs	r4, #16
- 8002496:	193b      	adds	r3, r7, r4
- 8002498:	2201      	movs	r2, #1
- 800249a:	70da      	strb	r2, [r3, #3]
-					comp_crc_header(&crc, &response);
- 800249c:	193a      	adds	r2, r7, r4
- 800249e:	250c      	movs	r5, #12
- 80024a0:	197b      	adds	r3, r7, r5
- 80024a2:	0011      	movs	r1, r2
- 80024a4:	0018      	movs	r0, r3
- 80024a6:	f7ff fba1 	bl	8001bec <comp_crc_header>
-					CRC8_107_add(&crc, response.status);
- 80024aa:	193b      	adds	r3, r7, r4
- 80024ac:	795a      	ldrb	r2, [r3, #5]
- 80024ae:	197b      	adds	r3, r7, r5
- 80024b0:	0011      	movs	r1, r2
- 80024b2:	0018      	movs	r0, r3
- 80024b4:	f7fe f924 	bl	8000700 <CRC8_107_add>
-					response.header.crc = CRC8_107_getChecksum(&crc);
- 80024b8:	197b      	adds	r3, r7, r5
- 80024ba:	0018      	movs	r0, r3
- 80024bc:	f7fe f950 	bl	8000760 <CRC8_107_getChecksum>
- 80024c0:	0003      	movs	r3, r0
- 80024c2:	001a      	movs	r2, r3
- 80024c4:	193b      	adds	r3, r7, r4
- 80024c6:	711a      	strb	r2, [r3, #4]
-					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 80024c8:	193b      	adds	r3, r7, r4
- 80024ca:	78db      	ldrb	r3, [r3, #3]
- 80024cc:	3305      	adds	r3, #5
- 80024ce:	63fb      	str	r3, [r7, #60]	@ 0x3c
-					HAL_UART_Transmit(&huart2, (uint8_t *)&response, packet_len, 100);
- 80024d0:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 80024d2:	b29a      	uxth	r2, r3
- 80024d4:	1939      	adds	r1, r7, r4
- 80024d6:	482e      	ldr	r0, [pc, #184]	@ (8002590 <handleRS485Message+0x958>)
- 80024d8:	2364      	movs	r3, #100	@ 0x64
- 80024da:	f004 fb5f 	bl	8006b9c <HAL_UART_Transmit>
-				break;
- 80024de:	e04e      	b.n	800257e <handleRS485Message+0x946>
-				if (is_initialized) return;
- 80024e0:	4b2c      	ldr	r3, [pc, #176]	@ (8002594 <handleRS485Message+0x95c>)
- 80024e2:	781b      	ldrb	r3, [r3, #0]
- 80024e4:	2b00      	cmp	r3, #0
- 80024e6:	d149      	bne.n	800257c <handleRS485Message+0x944>
-				memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH);
- 80024e8:	2410      	movs	r4, #16
- 80024ea:	193b      	adds	r3, r7, r4
- 80024ec:	2206      	movs	r2, #6
- 80024ee:	492a      	ldr	r1, [pc, #168]	@ (8002598 <handleRS485Message+0x960>)
- 80024f0:	189b      	adds	r3, r3, r2
- 80024f2:	220c      	movs	r2, #12
- 80024f4:	0018      	movs	r0, r3
- 80024f6:	f005 fc09 	bl	8007d0c <memcpy>
-				response.header.payloadLength=sizeof(response.payload)+1;
- 80024fa:	193b      	adds	r3, r7, r4
- 80024fc:	2215      	movs	r2, #21
- 80024fe:	70da      	strb	r2, [r3, #3]
-				response.status=STATUS_OK;
- 8002500:	193b      	adds	r3, r7, r4
- 8002502:	2200      	movs	r2, #0
- 8002504:	715a      	strb	r2, [r3, #5]
-				payload_ptr =(uint8_t*) &response.payload;
- 8002506:	193b      	adds	r3, r7, r4
- 8002508:	3306      	adds	r3, #6
- 800250a:	643b      	str	r3, [r7, #64]	@ 0x40
-				for (uint32_t i = 0; i<sizeof(response.payload.getFeederId)+1; i++)
- 800250c:	2300      	movs	r3, #0
- 800250e:	64fb      	str	r3, [r7, #76]	@ 0x4c
- 8002510:	e00c      	b.n	800252c <handleRS485Message+0x8f4>
-					CRC8_107_add(&crc,*(payload_ptr+i));
- 8002512:	6c3a      	ldr	r2, [r7, #64]	@ 0x40
- 8002514:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8002516:	18d3      	adds	r3, r2, r3
- 8002518:	781a      	ldrb	r2, [r3, #0]
- 800251a:	230c      	movs	r3, #12
- 800251c:	18fb      	adds	r3, r7, r3
- 800251e:	0011      	movs	r1, r2
- 8002520:	0018      	movs	r0, r3
- 8002522:	f7fe f8ed 	bl	8000700 <CRC8_107_add>
-				for (uint32_t i = 0; i<sizeof(response.payload.getFeederId)+1; i++)
- 8002526:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8002528:	3301      	adds	r3, #1
- 800252a:	64fb      	str	r3, [r7, #76]	@ 0x4c
- 800252c:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 800252e:	2b0c      	cmp	r3, #12
- 8002530:	d9ef      	bls.n	8002512 <handleRS485Message+0x8da>
-				response.header.crc = CRC8_107_getChecksum(&crc);
- 8002532:	230c      	movs	r3, #12
- 8002534:	18fb      	adds	r3, r7, r3
- 8002536:	0018      	movs	r0, r3
- 8002538:	f7fe f912 	bl	8000760 <CRC8_107_getChecksum>
- 800253c:	0003      	movs	r3, r0
- 800253e:	001a      	movs	r2, r3
- 8002540:	2110      	movs	r1, #16
- 8002542:	187b      	adds	r3, r7, r1
- 8002544:	711a      	strb	r2, [r3, #4]
-				response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for the length byte
- 8002546:	187b      	adds	r3, r7, r1
- 8002548:	220d      	movs	r2, #13
- 800254a:	70da      	strb	r2, [r3, #3]
-				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
- 800254c:	187b      	adds	r3, r7, r1
- 800254e:	78db      	ldrb	r3, [r3, #3]
- 8002550:	3305      	adds	r3, #5
- 8002552:	63fb      	str	r3, [r7, #60]	@ 0x3c
-				HAL_UART_Transmit(&huart2,(uint8_t *)&response,packet_len,100);
- 8002554:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8002556:	b29a      	uxth	r2, r3
- 8002558:	1879      	adds	r1, r7, r1
- 800255a:	480d      	ldr	r0, [pc, #52]	@ (8002590 <handleRS485Message+0x958>)
- 800255c:	2364      	movs	r3, #100	@ 0x64
- 800255e:	f004 fb1d 	bl	8006b9c <HAL_UART_Transmit>
-				break;
- 8002562:	e00c      	b.n	800257e <handleRS485Message+0x946>
-		return; // packet too small
- 8002564:	46c0      	nop			@ (mov r8, r8)
- 8002566:	e00a      	b.n	800257e <handleRS485Message+0x946>
-		return; // CRC mismatch, discard packet
- 8002568:	46c0      	nop			@ (mov r8, r8)
- 800256a:	e008      	b.n	800257e <handleRS485Message+0x946>
-		return; // message not for us
- 800256c:	46c0      	nop			@ (mov r8, r8)
- 800256e:	e006      	b.n	800257e <handleRS485Message+0x946>
-				return;
- 8002570:	46c0      	nop			@ (mov r8, r8)
- 8002572:	e004      	b.n	800257e <handleRS485Message+0x946>
-					return; // this makes no sense, but original code behaves like this
- 8002574:	46c0      	nop			@ (mov r8, r8)
- 8002576:	e002      	b.n	800257e <handleRS485Message+0x946>
-					return; // UUID doesn't match, ignore
- 8002578:	46c0      	nop			@ (mov r8, r8)
- 800257a:	e000      	b.n	800257e <handleRS485Message+0x946>
-				if (is_initialized) return;
- 800257c:	46c0      	nop			@ (mov r8, r8)
-				break;
-		}
-
-	}
-}
- 800257e:	46bd      	mov	sp, r7
- 8002580:	b01f      	add	sp, #124	@ 0x7c
- 8002582:	bdf0      	pop	{r4, r5, r6, r7, pc}
- 8002584:	20000002 	.word	0x20000002
- 8002588:	2000001f 	.word	0x2000001f
- 800258c:	2000054c 	.word	0x2000054c
- 8002590:	2000025c 	.word	0x2000025c
- 8002594:	200003c0 	.word	0x200003c0
- 8002598:	200003b4 	.word	0x200003b4
-
-0800259c <set_Feeder_PWM>:
-
-
-#define FEED_PWM_MIN_THRESHOLD 840  // 35% of 2400 - below this, don't drive
-
-void set_Feeder_PWM(uint16_t PWM, uint8_t direction)
-{
- 800259c:	b580      	push	{r7, lr}
- 800259e:	b082      	sub	sp, #8
- 80025a0:	af00      	add	r7, sp, #0
- 80025a2:	0002      	movs	r2, r0
- 80025a4:	1dbb      	adds	r3, r7, #6
- 80025a6:	801a      	strh	r2, [r3, #0]
- 80025a8:	1d7b      	adds	r3, r7, #5
- 80025aa:	1c0a      	adds	r2, r1, #0
- 80025ac:	701a      	strb	r2, [r3, #0]
-	if (PWM > 0 && PWM < FEED_PWM_MIN_THRESHOLD) PWM = 0;
- 80025ae:	1dbb      	adds	r3, r7, #6
- 80025b0:	881b      	ldrh	r3, [r3, #0]
- 80025b2:	2b00      	cmp	r3, #0
- 80025b4:	d008      	beq.n	80025c8 <set_Feeder_PWM+0x2c>
- 80025b6:	1dbb      	adds	r3, r7, #6
- 80025b8:	881a      	ldrh	r2, [r3, #0]
- 80025ba:	23d2      	movs	r3, #210	@ 0xd2
- 80025bc:	009b      	lsls	r3, r3, #2
- 80025be:	429a      	cmp	r2, r3
- 80025c0:	d202      	bcs.n	80025c8 <set_Feeder_PWM+0x2c>
- 80025c2:	1dbb      	adds	r3, r7, #6
- 80025c4:	2200      	movs	r2, #0
- 80025c6:	801a      	strh	r2, [r3, #0]
-
-	if (direction)
- 80025c8:	1d7b      	adds	r3, r7, #5
- 80025ca:	781b      	ldrb	r3, [r3, #0]
- 80025cc:	2b00      	cmp	r3, #0
- 80025ce:	d009      	beq.n	80025e4 <set_Feeder_PWM+0x48>
-	{
-		htim1.Instance->CCR1 = PWM;
- 80025d0:	4b0b      	ldr	r3, [pc, #44]	@ (8002600 <set_Feeder_PWM+0x64>)
- 80025d2:	681b      	ldr	r3, [r3, #0]
- 80025d4:	1dba      	adds	r2, r7, #6
- 80025d6:	8812      	ldrh	r2, [r2, #0]
- 80025d8:	635a      	str	r2, [r3, #52]	@ 0x34
-		htim1.Instance->CCR2 = 0;
- 80025da:	4b09      	ldr	r3, [pc, #36]	@ (8002600 <set_Feeder_PWM+0x64>)
- 80025dc:	681b      	ldr	r3, [r3, #0]
- 80025de:	2200      	movs	r2, #0
- 80025e0:	639a      	str	r2, [r3, #56]	@ 0x38
-	else
-	{
-		htim1.Instance->CCR1 = 0;
-		htim1.Instance->CCR2 = PWM;
-	}
-}
- 80025e2:	e008      	b.n	80025f6 <set_Feeder_PWM+0x5a>
-		htim1.Instance->CCR1 = 0;
- 80025e4:	4b06      	ldr	r3, [pc, #24]	@ (8002600 <set_Feeder_PWM+0x64>)
- 80025e6:	681b      	ldr	r3, [r3, #0]
- 80025e8:	2200      	movs	r2, #0
- 80025ea:	635a      	str	r2, [r3, #52]	@ 0x34
-		htim1.Instance->CCR2 = PWM;
- 80025ec:	4b04      	ldr	r3, [pc, #16]	@ (8002600 <set_Feeder_PWM+0x64>)
- 80025ee:	681b      	ldr	r3, [r3, #0]
- 80025f0:	1dba      	adds	r2, r7, #6
- 80025f2:	8812      	ldrh	r2, [r2, #0]
- 80025f4:	639a      	str	r2, [r3, #56]	@ 0x38
-}
- 80025f6:	46c0      	nop			@ (mov r8, r8)
- 80025f8:	46bd      	mov	sp, r7
- 80025fa:	b002      	add	sp, #8
- 80025fc:	bd80      	pop	{r7, pc}
- 80025fe:	46c0      	nop			@ (mov r8, r8)
- 8002600:	2000004c 	.word	0x2000004c
-
-08002604 <peel_motor>:
-
-void peel_motor(uint8_t forward)
-{
- 8002604:	b580      	push	{r7, lr}
- 8002606:	b082      	sub	sp, #8
- 8002608:	af00      	add	r7, sp, #0
- 800260a:	0002      	movs	r2, r0
- 800260c:	1dfb      	adds	r3, r7, #7
- 800260e:	701a      	strb	r2, [r3, #0]
-	peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
- 8002610:	1dfb      	adds	r3, r7, #7
- 8002612:	781b      	ldrb	r3, [r3, #0]
- 8002614:	2b00      	cmp	r3, #0
- 8002616:	d002      	beq.n	800261e <peel_motor+0x1a>
- 8002618:	2396      	movs	r3, #150	@ 0x96
- 800261a:	011a      	lsls	r2, r3, #4
- 800261c:	e000      	b.n	8002620 <peel_motor+0x1c>
- 800261e:	4a03      	ldr	r2, [pc, #12]	@ (800262c <peel_motor+0x28>)
- 8002620:	4b03      	ldr	r3, [pc, #12]	@ (8002630 <peel_motor+0x2c>)
- 8002622:	801a      	strh	r2, [r3, #0]
-}
- 8002624:	46c0      	nop			@ (mov r8, r8)
- 8002626:	46bd      	mov	sp, r7
- 8002628:	b002      	add	sp, #8
- 800262a:	bd80      	pop	{r7, pc}
- 800262c:	fffff6a0 	.word	0xfffff6a0
- 8002630:	200004d6 	.word	0x200004d6
-
-08002634 <peel_brake>:
-
-void peel_brake(void)
-{
- 8002634:	b580      	push	{r7, lr}
- 8002636:	af00      	add	r7, sp, #0
-	peel_target_pwm = 0;
- 8002638:	4b02      	ldr	r3, [pc, #8]	@ (8002644 <peel_brake+0x10>)
- 800263a:	2200      	movs	r2, #0
- 800263c:	801a      	strh	r2, [r3, #0]
-}
- 800263e:	46c0      	nop			@ (mov r8, r8)
- 8002640:	46bd      	mov	sp, r7
- 8002642:	bd80      	pop	{r7, pc}
- 8002644:	200004d6 	.word	0x200004d6
-
-08002648 <peel_ramp_update>:
-
-void peel_ramp_update(void)
-{
- 8002648:	b580      	push	{r7, lr}
- 800264a:	b084      	sub	sp, #16
- 800264c:	af00      	add	r7, sp, #0
-	uint32_t now = HAL_GetTick();
- 800264e:	f001 fd43 	bl	80040d8 <HAL_GetTick>
- 8002652:	0003      	movs	r3, r0
- 8002654:	60bb      	str	r3, [r7, #8]
-	uint32_t dt = now - peel_last_ramp_time;
- 8002656:	4b4d      	ldr	r3, [pc, #308]	@ (800278c <peel_ramp_update+0x144>)
- 8002658:	681b      	ldr	r3, [r3, #0]
- 800265a:	68ba      	ldr	r2, [r7, #8]
- 800265c:	1ad3      	subs	r3, r2, r3
- 800265e:	607b      	str	r3, [r7, #4]
-	if (dt == 0) return;
- 8002660:	687b      	ldr	r3, [r7, #4]
- 8002662:	2b00      	cmp	r3, #0
- 8002664:	d100      	bne.n	8002668 <peel_ramp_update+0x20>
- 8002666:	e08b      	b.n	8002780 <peel_ramp_update+0x138>
-	peel_last_ramp_time = now;
- 8002668:	4b48      	ldr	r3, [pc, #288]	@ (800278c <peel_ramp_update+0x144>)
- 800266a:	68ba      	ldr	r2, [r7, #8]
- 800266c:	601a      	str	r2, [r3, #0]
-
-	if (peel_current_pwm == peel_target_pwm) return;
- 800266e:	4b48      	ldr	r3, [pc, #288]	@ (8002790 <peel_ramp_update+0x148>)
- 8002670:	2200      	movs	r2, #0
- 8002672:	5e9a      	ldrsh	r2, [r3, r2]
- 8002674:	4b47      	ldr	r3, [pc, #284]	@ (8002794 <peel_ramp_update+0x14c>)
- 8002676:	2100      	movs	r1, #0
- 8002678:	5e5b      	ldrsh	r3, [r3, r1]
- 800267a:	429a      	cmp	r2, r3
- 800267c:	d100      	bne.n	8002680 <peel_ramp_update+0x38>
- 800267e:	e081      	b.n	8002784 <peel_ramp_update+0x13c>
-
-	// Step size: full range (PWM_MAX) in PEEL_RAMP_TIME_MS
-	int16_t step = (int16_t)((int32_t)PWM_MAX * dt / PEEL_RAMP_TIME_MS);
- 8002680:	687a      	ldr	r2, [r7, #4]
- 8002682:	0013      	movs	r3, r2
- 8002684:	009b      	lsls	r3, r3, #2
- 8002686:	189b      	adds	r3, r3, r2
- 8002688:	011a      	lsls	r2, r3, #4
- 800268a:	1ad2      	subs	r2, r2, r3
- 800268c:	0153      	lsls	r3, r2, #5
- 800268e:	001a      	movs	r2, r3
- 8002690:	0013      	movs	r3, r2
- 8002692:	2164      	movs	r1, #100	@ 0x64
- 8002694:	0018      	movs	r0, r3
- 8002696:	f7fd fd37 	bl	8000108 <__udivsi3>
- 800269a:	0003      	movs	r3, r0
- 800269c:	001a      	movs	r2, r3
- 800269e:	210e      	movs	r1, #14
- 80026a0:	187b      	adds	r3, r7, r1
- 80026a2:	801a      	strh	r2, [r3, #0]
-	if (step < 1) step = 1;
- 80026a4:	000a      	movs	r2, r1
- 80026a6:	18bb      	adds	r3, r7, r2
- 80026a8:	2100      	movs	r1, #0
- 80026aa:	5e5b      	ldrsh	r3, [r3, r1]
- 80026ac:	2b00      	cmp	r3, #0
- 80026ae:	dc02      	bgt.n	80026b6 <peel_ramp_update+0x6e>
- 80026b0:	18bb      	adds	r3, r7, r2
- 80026b2:	2201      	movs	r2, #1
- 80026b4:	801a      	strh	r2, [r3, #0]
-
-	if (peel_target_pwm > peel_current_pwm)
- 80026b6:	4b37      	ldr	r3, [pc, #220]	@ (8002794 <peel_ramp_update+0x14c>)
- 80026b8:	2200      	movs	r2, #0
- 80026ba:	5e9a      	ldrsh	r2, [r3, r2]
- 80026bc:	4b34      	ldr	r3, [pc, #208]	@ (8002790 <peel_ramp_update+0x148>)
- 80026be:	2100      	movs	r1, #0
- 80026c0:	5e5b      	ldrsh	r3, [r3, r1]
- 80026c2:	429a      	cmp	r2, r3
- 80026c4:	dd19      	ble.n	80026fa <peel_ramp_update+0xb2>
-	{
-		peel_current_pwm += step;
- 80026c6:	4b32      	ldr	r3, [pc, #200]	@ (8002790 <peel_ramp_update+0x148>)
- 80026c8:	2200      	movs	r2, #0
- 80026ca:	5e9b      	ldrsh	r3, [r3, r2]
- 80026cc:	b29a      	uxth	r2, r3
- 80026ce:	230e      	movs	r3, #14
- 80026d0:	18fb      	adds	r3, r7, r3
- 80026d2:	881b      	ldrh	r3, [r3, #0]
- 80026d4:	18d3      	adds	r3, r2, r3
- 80026d6:	b29b      	uxth	r3, r3
- 80026d8:	b21a      	sxth	r2, r3
- 80026da:	4b2d      	ldr	r3, [pc, #180]	@ (8002790 <peel_ramp_update+0x148>)
- 80026dc:	801a      	strh	r2, [r3, #0]
-		if (peel_current_pwm > peel_target_pwm)
- 80026de:	4b2c      	ldr	r3, [pc, #176]	@ (8002790 <peel_ramp_update+0x148>)
- 80026e0:	2200      	movs	r2, #0
- 80026e2:	5e9a      	ldrsh	r2, [r3, r2]
- 80026e4:	4b2b      	ldr	r3, [pc, #172]	@ (8002794 <peel_ramp_update+0x14c>)
- 80026e6:	2100      	movs	r1, #0
- 80026e8:	5e5b      	ldrsh	r3, [r3, r1]
- 80026ea:	429a      	cmp	r2, r3
- 80026ec:	dd1e      	ble.n	800272c <peel_ramp_update+0xe4>
-			peel_current_pwm = peel_target_pwm;
- 80026ee:	4b29      	ldr	r3, [pc, #164]	@ (8002794 <peel_ramp_update+0x14c>)
- 80026f0:	2200      	movs	r2, #0
- 80026f2:	5e9a      	ldrsh	r2, [r3, r2]
- 80026f4:	4b26      	ldr	r3, [pc, #152]	@ (8002790 <peel_ramp_update+0x148>)
- 80026f6:	801a      	strh	r2, [r3, #0]
- 80026f8:	e018      	b.n	800272c <peel_ramp_update+0xe4>
-	}
-	else
-	{
-		peel_current_pwm -= step;
- 80026fa:	4b25      	ldr	r3, [pc, #148]	@ (8002790 <peel_ramp_update+0x148>)
- 80026fc:	2200      	movs	r2, #0
- 80026fe:	5e9b      	ldrsh	r3, [r3, r2]
- 8002700:	b29a      	uxth	r2, r3
- 8002702:	230e      	movs	r3, #14
- 8002704:	18fb      	adds	r3, r7, r3
- 8002706:	881b      	ldrh	r3, [r3, #0]
- 8002708:	1ad3      	subs	r3, r2, r3
- 800270a:	b29b      	uxth	r3, r3
- 800270c:	b21a      	sxth	r2, r3
- 800270e:	4b20      	ldr	r3, [pc, #128]	@ (8002790 <peel_ramp_update+0x148>)
- 8002710:	801a      	strh	r2, [r3, #0]
-		if (peel_current_pwm < peel_target_pwm)
- 8002712:	4b1f      	ldr	r3, [pc, #124]	@ (8002790 <peel_ramp_update+0x148>)
- 8002714:	2200      	movs	r2, #0
- 8002716:	5e9a      	ldrsh	r2, [r3, r2]
- 8002718:	4b1e      	ldr	r3, [pc, #120]	@ (8002794 <peel_ramp_update+0x14c>)
- 800271a:	2100      	movs	r1, #0
- 800271c:	5e5b      	ldrsh	r3, [r3, r1]
- 800271e:	429a      	cmp	r2, r3
- 8002720:	da04      	bge.n	800272c <peel_ramp_update+0xe4>
-			peel_current_pwm = peel_target_pwm;
- 8002722:	4b1c      	ldr	r3, [pc, #112]	@ (8002794 <peel_ramp_update+0x14c>)
- 8002724:	2200      	movs	r2, #0
- 8002726:	5e9a      	ldrsh	r2, [r3, r2]
- 8002728:	4b19      	ldr	r3, [pc, #100]	@ (8002790 <peel_ramp_update+0x148>)
- 800272a:	801a      	strh	r2, [r3, #0]
-	}
-
-	// Apply to TIM1 CH3/CH4
-	if (peel_current_pwm > 0)
- 800272c:	4b18      	ldr	r3, [pc, #96]	@ (8002790 <peel_ramp_update+0x148>)
- 800272e:	2200      	movs	r2, #0
- 8002730:	5e9b      	ldrsh	r3, [r3, r2]
- 8002732:	2b00      	cmp	r3, #0
- 8002734:	dd0a      	ble.n	800274c <peel_ramp_update+0x104>
-	{
-		htim1.Instance->CCR3 = peel_current_pwm;
- 8002736:	4b16      	ldr	r3, [pc, #88]	@ (8002790 <peel_ramp_update+0x148>)
- 8002738:	2200      	movs	r2, #0
- 800273a:	5e9a      	ldrsh	r2, [r3, r2]
- 800273c:	4b16      	ldr	r3, [pc, #88]	@ (8002798 <peel_ramp_update+0x150>)
- 800273e:	681b      	ldr	r3, [r3, #0]
- 8002740:	63da      	str	r2, [r3, #60]	@ 0x3c
-		htim1.Instance->CCR4 = 0;
- 8002742:	4b15      	ldr	r3, [pc, #84]	@ (8002798 <peel_ramp_update+0x150>)
- 8002744:	681b      	ldr	r3, [r3, #0]
- 8002746:	2200      	movs	r2, #0
- 8002748:	641a      	str	r2, [r3, #64]	@ 0x40
- 800274a:	e01c      	b.n	8002786 <peel_ramp_update+0x13e>
-	}
-	else if (peel_current_pwm < 0)
- 800274c:	4b10      	ldr	r3, [pc, #64]	@ (8002790 <peel_ramp_update+0x148>)
- 800274e:	2200      	movs	r2, #0
- 8002750:	5e9b      	ldrsh	r3, [r3, r2]
- 8002752:	2b00      	cmp	r3, #0
- 8002754:	da0b      	bge.n	800276e <peel_ramp_update+0x126>
-	{
-		htim1.Instance->CCR3 = 0;
- 8002756:	4b10      	ldr	r3, [pc, #64]	@ (8002798 <peel_ramp_update+0x150>)
- 8002758:	681b      	ldr	r3, [r3, #0]
- 800275a:	2200      	movs	r2, #0
- 800275c:	63da      	str	r2, [r3, #60]	@ 0x3c
-		htim1.Instance->CCR4 = -peel_current_pwm;
- 800275e:	4b0c      	ldr	r3, [pc, #48]	@ (8002790 <peel_ramp_update+0x148>)
- 8002760:	2200      	movs	r2, #0
- 8002762:	5e9b      	ldrsh	r3, [r3, r2]
- 8002764:	425a      	negs	r2, r3
- 8002766:	4b0c      	ldr	r3, [pc, #48]	@ (8002798 <peel_ramp_update+0x150>)
- 8002768:	681b      	ldr	r3, [r3, #0]
- 800276a:	641a      	str	r2, [r3, #64]	@ 0x40
- 800276c:	e00b      	b.n	8002786 <peel_ramp_update+0x13e>
-	}
-	else
-	{
-		htim1.Instance->CCR3 = 0;
- 800276e:	4b0a      	ldr	r3, [pc, #40]	@ (8002798 <peel_ramp_update+0x150>)
- 8002770:	681b      	ldr	r3, [r3, #0]
- 8002772:	2200      	movs	r2, #0
- 8002774:	63da      	str	r2, [r3, #60]	@ 0x3c
-		htim1.Instance->CCR4 = 0;
- 8002776:	4b08      	ldr	r3, [pc, #32]	@ (8002798 <peel_ramp_update+0x150>)
- 8002778:	681b      	ldr	r3, [r3, #0]
- 800277a:	2200      	movs	r2, #0
- 800277c:	641a      	str	r2, [r3, #64]	@ 0x40
- 800277e:	e002      	b.n	8002786 <peel_ramp_update+0x13e>
-	if (dt == 0) return;
- 8002780:	46c0      	nop			@ (mov r8, r8)
- 8002782:	e000      	b.n	8002786 <peel_ramp_update+0x13e>
-	if (peel_current_pwm == peel_target_pwm) return;
- 8002784:	46c0      	nop			@ (mov r8, r8)
-	}
-}
- 8002786:	46bd      	mov	sp, r7
- 8002788:	b004      	add	sp, #16
- 800278a:	bd80      	pop	{r7, pc}
- 800278c:	200004dc 	.word	0x200004dc
- 8002790:	200004d8 	.word	0x200004d8
- 8002794:	200004d6 	.word	0x200004d6
- 8002798:	2000004c 	.word	0x2000004c
-
-0800279c <drive_continuous>:
-
-void drive_continuous(uint8_t forward)
-{
- 800279c:	b580      	push	{r7, lr}
- 800279e:	b082      	sub	sp, #8
- 80027a0:	af00      	add	r7, sp, #0
- 80027a2:	0002      	movs	r2, r0
- 80027a4:	1dfb      	adds	r3, r7, #7
- 80027a6:	701a      	strb	r2, [r3, #0]
-	// Bypass PID - set target far away in the desired direction so PID drives at max
-	pid_reset(&motor_pid);
- 80027a8:	4b0c      	ldr	r3, [pc, #48]	@ (80027dc <drive_continuous+0x40>)
- 80027aa:	0018      	movs	r0, r3
- 80027ac:	f7fe f836 	bl	800081c <pid_reset>
-	if (forward)
- 80027b0:	1dfb      	adds	r3, r7, #7
- 80027b2:	781b      	ldrb	r3, [r3, #0]
- 80027b4:	2b00      	cmp	r3, #0
- 80027b6:	d006      	beq.n	80027c6 <drive_continuous+0x2a>
-	{
-		target_count = total_count + 10000;
- 80027b8:	4b09      	ldr	r3, [pc, #36]	@ (80027e0 <drive_continuous+0x44>)
- 80027ba:	681b      	ldr	r3, [r3, #0]
- 80027bc:	4a09      	ldr	r2, [pc, #36]	@ (80027e4 <drive_continuous+0x48>)
- 80027be:	189a      	adds	r2, r3, r2
- 80027c0:	4b09      	ldr	r3, [pc, #36]	@ (80027e8 <drive_continuous+0x4c>)
- 80027c2:	601a      	str	r2, [r3, #0]
-	}
-	else
-	{
-		target_count = total_count - 10000;
-	}
-}
- 80027c4:	e005      	b.n	80027d2 <drive_continuous+0x36>
-		target_count = total_count - 10000;
- 80027c6:	4b06      	ldr	r3, [pc, #24]	@ (80027e0 <drive_continuous+0x44>)
- 80027c8:	681b      	ldr	r3, [r3, #0]
- 80027ca:	4a08      	ldr	r2, [pc, #32]	@ (80027ec <drive_continuous+0x50>)
- 80027cc:	189a      	adds	r2, r3, r2
- 80027ce:	4b06      	ldr	r3, [pc, #24]	@ (80027e8 <drive_continuous+0x4c>)
- 80027d0:	601a      	str	r2, [r3, #0]
-}
- 80027d2:	46c0      	nop			@ (mov r8, r8)
- 80027d4:	46bd      	mov	sp, r7
- 80027d6:	b002      	add	sp, #8
- 80027d8:	bd80      	pop	{r7, pc}
- 80027da:	46c0      	nop			@ (mov r8, r8)
- 80027dc:	2000048c 	.word	0x2000048c
- 80027e0:	20000484 	.word	0x20000484
- 80027e4:	00002710 	.word	0x00002710
- 80027e8:	20000488 	.word	0x20000488
- 80027ec:	ffffd8f0 	.word	0xffffd8f0
-
-080027f0 <halt_all>:
-
-void halt_all(void)
-{
- 80027f0:	b580      	push	{r7, lr}
- 80027f2:	af00      	add	r7, sp, #0
-	// Stop drive motor (brake)
-	htim1.Instance->CCR1 = PWM_MAX;
- 80027f4:	4b12      	ldr	r3, [pc, #72]	@ (8002840 <halt_all+0x50>)
- 80027f6:	681b      	ldr	r3, [r3, #0]
- 80027f8:	2296      	movs	r2, #150	@ 0x96
- 80027fa:	0112      	lsls	r2, r2, #4
- 80027fc:	635a      	str	r2, [r3, #52]	@ 0x34
-	htim1.Instance->CCR2 = PWM_MAX;
- 80027fe:	4b10      	ldr	r3, [pc, #64]	@ (8002840 <halt_all+0x50>)
- 8002800:	681b      	ldr	r3, [r3, #0]
- 8002802:	2296      	movs	r2, #150	@ 0x96
- 8002804:	0112      	lsls	r2, r2, #4
- 8002806:	639a      	str	r2, [r3, #56]	@ 0x38
-
-	// Stop peel motor immediately
-	peel_target_pwm = 0;
- 8002808:	4b0e      	ldr	r3, [pc, #56]	@ (8002844 <halt_all+0x54>)
- 800280a:	2200      	movs	r2, #0
- 800280c:	801a      	strh	r2, [r3, #0]
-	peel_current_pwm = 0;
- 800280e:	4b0e      	ldr	r3, [pc, #56]	@ (8002848 <halt_all+0x58>)
- 8002810:	2200      	movs	r2, #0
- 8002812:	801a      	strh	r2, [r3, #0]
-	htim1.Instance->CCR3 = 0;
- 8002814:	4b0a      	ldr	r3, [pc, #40]	@ (8002840 <halt_all+0x50>)
- 8002816:	681b      	ldr	r3, [r3, #0]
- 8002818:	2200      	movs	r2, #0
- 800281a:	63da      	str	r2, [r3, #60]	@ 0x3c
-	htim1.Instance->CCR4 = 0;
- 800281c:	4b08      	ldr	r3, [pc, #32]	@ (8002840 <halt_all+0x50>)
- 800281e:	681b      	ldr	r3, [r3, #0]
- 8002820:	2200      	movs	r2, #0
- 8002822:	641a      	str	r2, [r3, #64]	@ 0x40
-
-	// Reset PID state to prevent sudden movement
-	pid_reset(&motor_pid);
- 8002824:	4b09      	ldr	r3, [pc, #36]	@ (800284c <halt_all+0x5c>)
- 8002826:	0018      	movs	r0, r3
- 8002828:	f7fd fff8 	bl	800081c <pid_reset>
-	target_count = total_count; // Set target to current position
- 800282c:	4b08      	ldr	r3, [pc, #32]	@ (8002850 <halt_all+0x60>)
- 800282e:	681a      	ldr	r2, [r3, #0]
- 8002830:	4b08      	ldr	r3, [pc, #32]	@ (8002854 <halt_all+0x64>)
- 8002832:	601a      	str	r2, [r3, #0]
-	pid_add = 0;
- 8002834:	4b08      	ldr	r3, [pc, #32]	@ (8002858 <halt_all+0x68>)
- 8002836:	2200      	movs	r2, #0
- 8002838:	601a      	str	r2, [r3, #0]
-}
- 800283a:	46c0      	nop			@ (mov r8, r8)
- 800283c:	46bd      	mov	sp, r7
- 800283e:	bd80      	pop	{r7, pc}
- 8002840:	2000004c 	.word	0x2000004c
- 8002844:	200004d6 	.word	0x200004d6
- 8002848:	200004d8 	.word	0x200004d8
- 800284c:	2000048c 	.word	0x2000048c
- 8002850:	20000484 	.word	0x20000484
- 8002854:	20000488 	.word	0x20000488
- 8002858:	200004b8 	.word	0x200004b8
-
-0800285c <identify_feeder>:
-
-void identify_feeder(void)
-{
- 800285c:	b580      	push	{r7, lr}
- 800285e:	b082      	sub	sp, #8
- 8002860:	af00      	add	r7, sp, #0
-	// Flash LED white 3 times
-	for (int i = 0; i < 3; i++)
- 8002862:	2300      	movs	r3, #0
- 8002864:	607b      	str	r3, [r7, #4]
- 8002866:	e016      	b.n	8002896 <identify_feeder+0x3a>
-	{
-		set_LED(1, 1, 1);
- 8002868:	2201      	movs	r2, #1
- 800286a:	2101      	movs	r1, #1
- 800286c:	2001      	movs	r0, #1
- 800286e:	f7ff f97d 	bl	8001b6c <set_LED>
-		HAL_Delay(300);
- 8002872:	2396      	movs	r3, #150	@ 0x96
- 8002874:	005b      	lsls	r3, r3, #1
- 8002876:	0018      	movs	r0, r3
- 8002878:	f001 fc38 	bl	80040ec <HAL_Delay>
-		set_LED(0, 0, 0);
- 800287c:	2200      	movs	r2, #0
- 800287e:	2100      	movs	r1, #0
- 8002880:	2000      	movs	r0, #0
- 8002882:	f7ff f973 	bl	8001b6c <set_LED>
-		HAL_Delay(300);
- 8002886:	2396      	movs	r3, #150	@ 0x96
- 8002888:	005b      	lsls	r3, r3, #1
- 800288a:	0018      	movs	r0, r3
- 800288c:	f001 fc2e 	bl	80040ec <HAL_Delay>
-	for (int i = 0; i < 3; i++)
- 8002890:	687b      	ldr	r3, [r7, #4]
- 8002892:	3301      	adds	r3, #1
- 8002894:	607b      	str	r3, [r7, #4]
- 8002896:	687b      	ldr	r3, [r7, #4]
- 8002898:	2b02      	cmp	r3, #2
- 800289a:	dde5      	ble.n	8002868 <identify_feeder+0xc>
-	}
-}
- 800289c:	46c0      	nop			@ (mov r8, r8)
- 800289e:	46c0      	nop			@ (mov r8, r8)
- 80028a0:	46bd      	mov	sp, r7
- 80028a2:	b002      	add	sp, #8
- 80028a4:	bd80      	pop	{r7, pc}
-
-080028a6 <show_version>:
-
-void show_version(void)
-{
- 80028a6:	b580      	push	{r7, lr}
- 80028a8:	af00      	add	r7, sp, #0
-	// Flash green for release version
-	set_LED(0, 1, 0);
- 80028aa:	2200      	movs	r2, #0
- 80028ac:	2101      	movs	r1, #1
- 80028ae:	2000      	movs	r0, #0
- 80028b0:	f7ff f95c 	bl	8001b6c <set_LED>
-	HAL_Delay(250);
- 80028b4:	20fa      	movs	r0, #250	@ 0xfa
- 80028b6:	f001 fc19 	bl	80040ec <HAL_Delay>
-	set_LED(0, 0, 0);
- 80028ba:	2200      	movs	r2, #0
- 80028bc:	2100      	movs	r1, #0
- 80028be:	2000      	movs	r0, #0
- 80028c0:	f7ff f954 	bl	8001b6c <set_LED>
-	HAL_Delay(250);
- 80028c4:	20fa      	movs	r0, #250	@ 0xfa
- 80028c6:	f001 fc11 	bl	80040ec <HAL_Delay>
-}
- 80028ca:	46c0      	nop			@ (mov r8, r8)
- 80028cc:	46bd      	mov	sp, r7
- 80028ce:	bd80      	pop	{r7, pc}
-
-080028d0 <tenths_to_counts>:
-
-// Convert distance in tenths of mm to encoder counts
-int32_t tenths_to_counts(int16_t tenths)
-{
- 80028d0:	b5b0      	push	{r4, r5, r7, lr}
- 80028d2:	b084      	sub	sp, #16
- 80028d4:	af00      	add	r7, sp, #0
- 80028d6:	0002      	movs	r2, r0
- 80028d8:	1dbb      	adds	r3, r7, #6
- 80028da:	801a      	strh	r2, [r3, #0]
-	// counts = (tenths * 1000 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV
-	int64_t temp = ((int64_t)tenths * 1000 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV;
- 80028dc:	1dbb      	adds	r3, r7, #6
- 80028de:	881b      	ldrh	r3, [r3, #0]
- 80028e0:	b21b      	sxth	r3, r3
- 80028e2:	001c      	movs	r4, r3
- 80028e4:	17db      	asrs	r3, r3, #31
- 80028e6:	001d      	movs	r5, r3
- 80028e8:	4a0b      	ldr	r2, [pc, #44]	@ (8002918 <tenths_to_counts+0x48>)
- 80028ea:	2300      	movs	r3, #0
- 80028ec:	0020      	movs	r0, r4
- 80028ee:	0029      	movs	r1, r5
- 80028f0:	f7fd fda4 	bl	800043c <__aeabi_lmul>
- 80028f4:	0002      	movs	r2, r0
- 80028f6:	000b      	movs	r3, r1
- 80028f8:	0010      	movs	r0, r2
- 80028fa:	0019      	movs	r1, r3
- 80028fc:	4a07      	ldr	r2, [pc, #28]	@ (800291c <tenths_to_counts+0x4c>)
- 80028fe:	2300      	movs	r3, #0
- 8002900:	f7fd fd78 	bl	80003f4 <__aeabi_ldivmod>
- 8002904:	0002      	movs	r2, r0
- 8002906:	000b      	movs	r3, r1
- 8002908:	60ba      	str	r2, [r7, #8]
- 800290a:	60fb      	str	r3, [r7, #12]
-	return (int32_t)temp;
- 800290c:	68bb      	ldr	r3, [r7, #8]
-}
- 800290e:	0018      	movs	r0, r3
- 8002910:	46bd      	mov	sp, r7
- 8002912:	b004      	add	sp, #16
- 8002914:	bdb0      	pop	{r4, r5, r7, pc}
- 8002916:	46c0      	nop			@ (mov r8, r8)
- 8002918:	01b81040 	.word	0x01b81040
- 800291c:	0001f377 	.word	0x0001f377
-
-08002920 <calculate_expected_feed_time>:
-
-// Calculate expected feed time in milliseconds
-uint16_t calculate_expected_feed_time(uint8_t distance, uint8_t forward)
-{
- 8002920:	b580      	push	{r7, lr}
- 8002922:	b084      	sub	sp, #16
- 8002924:	af00      	add	r7, sp, #0
- 8002926:	0002      	movs	r2, r0
- 8002928:	1dfb      	adds	r3, r7, #7
- 800292a:	701a      	strb	r2, [r3, #0]
- 800292c:	1dbb      	adds	r3, r7, #6
- 800292e:	1c0a      	adds	r2, r1, #0
- 8002930:	701a      	strb	r2, [r3, #0]
-	if (forward)
- 8002932:	1dbb      	adds	r3, r7, #6
- 8002934:	781b      	ldrb	r3, [r3, #0]
- 8002936:	2b00      	cmp	r3, #0
- 8002938:	d020      	beq.n	800297c <calculate_expected_feed_time+0x5c>
-	{
-		// Forward: peel time + peel backoff + drive time + extra for first feed
-		uint16_t time = (distance * PEEL_TIME_PER_TENTH_MM) +
-						PEEL_BACKOFF_TIME +
- 800293a:	1dfb      	adds	r3, r7, #7
- 800293c:	781b      	ldrb	r3, [r3, #0]
- 800293e:	b29b      	uxth	r3, r3
- 8002940:	223a      	movs	r2, #58	@ 0x3a
- 8002942:	4353      	muls	r3, r2
- 8002944:	b29a      	uxth	r2, r3
-		uint16_t time = (distance * PEEL_TIME_PER_TENTH_MM) +
- 8002946:	210e      	movs	r1, #14
- 8002948:	187b      	adds	r3, r7, r1
- 800294a:	321e      	adds	r2, #30
- 800294c:	801a      	strh	r2, [r3, #0]
-						(distance * TIMEOUT_TIME_PER_TENTH_MM);
-		if (first_feed_since_load)
- 800294e:	4b17      	ldr	r3, [pc, #92]	@ (80029ac <calculate_expected_feed_time+0x8c>)
- 8002950:	781b      	ldrb	r3, [r3, #0]
- 8002952:	2b00      	cmp	r3, #0
- 8002954:	d008      	beq.n	8002968 <calculate_expected_feed_time+0x48>
-		{
-			time += 1000; // Extra time for tape detection
- 8002956:	187a      	adds	r2, r7, r1
- 8002958:	187b      	adds	r3, r7, r1
- 800295a:	881b      	ldrh	r3, [r3, #0]
- 800295c:	21fa      	movs	r1, #250	@ 0xfa
- 800295e:	0089      	lsls	r1, r1, #2
- 8002960:	468c      	mov	ip, r1
- 8002962:	4463      	add	r3, ip
- 8002964:	8013      	strh	r3, [r2, #0]
- 8002966:	e005      	b.n	8002974 <calculate_expected_feed_time+0x54>
-		}
-		else
-		{
-			time += 200;
- 8002968:	220e      	movs	r2, #14
- 800296a:	18bb      	adds	r3, r7, r2
- 800296c:	18ba      	adds	r2, r7, r2
- 800296e:	8812      	ldrh	r2, [r2, #0]
- 8002970:	32c8      	adds	r2, #200	@ 0xc8
- 8002972:	801a      	strh	r2, [r3, #0]
-		}
-		return time;
- 8002974:	230e      	movs	r3, #14
- 8002976:	18fb      	adds	r3, r7, r3
- 8002978:	881b      	ldrh	r3, [r3, #0]
- 800297a:	e013      	b.n	80029a4 <calculate_expected_feed_time+0x84>
-	}
-	else
-	{
-		// Backward: unpeel + drive (with backlash) + slack removal
-		return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) +
- 800297c:	1dfb      	adds	r3, r7, #7
- 800297e:	781b      	ldrb	r3, [r3, #0]
- 8002980:	b29b      	uxth	r3, r3
- 8002982:	1c1a      	adds	r2, r3, #0
- 8002984:	0112      	lsls	r2, r2, #4
- 8002986:	1ad3      	subs	r3, r2, r3
- 8002988:	18db      	adds	r3, r3, r3
- 800298a:	b29a      	uxth	r2, r3
-			   ((distance + (BACKLASH_COMP_TENTH_MM * 2)) * TIMEOUT_TIME_PER_TENTH_MM) +
- 800298c:	1dfb      	adds	r3, r7, #7
- 800298e:	781b      	ldrb	r3, [r3, #0]
- 8002990:	3314      	adds	r3, #20
-		return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) +
- 8002992:	b29b      	uxth	r3, r3
- 8002994:	2128      	movs	r1, #40	@ 0x28
- 8002996:	434b      	muls	r3, r1
- 8002998:	b29b      	uxth	r3, r3
- 800299a:	18d3      	adds	r3, r2, r3
- 800299c:	b29b      	uxth	r3, r3
-			   BACKWARDS_FEED_FILM_SLACK_REMOVAL_TIME + 50;
- 800299e:	3391      	adds	r3, #145	@ 0x91
- 80029a0:	33ff      	adds	r3, #255	@ 0xff
- 80029a2:	b29b      	uxth	r3, r3
-	}
-}
- 80029a4:	0018      	movs	r0, r3
- 80029a6:	46bd      	mov	sp, r7
- 80029a8:	b004      	add	sp, #16
- 80029aa:	bd80      	pop	{r7, pc}
- 80029ac:	2000001d 	.word	0x2000001d
-
-080029b0 <start_feed>:
-
-// Start a feed operation
-void start_feed(int16_t distance_tenths, uint8_t forward)
-{
- 80029b0:	b580      	push	{r7, lr}
- 80029b2:	b082      	sub	sp, #8
- 80029b4:	af00      	add	r7, sp, #0
- 80029b6:	0002      	movs	r2, r0
- 80029b8:	1dbb      	adds	r3, r7, #6
- 80029ba:	801a      	strh	r2, [r3, #0]
- 80029bc:	1d7b      	adds	r3, r7, #5
- 80029be:	1c0a      	adds	r2, r1, #0
- 80029c0:	701a      	strb	r2, [r3, #0]
-	if (feed_state != FEED_STATE_IDLE)
- 80029c2:	4b3c      	ldr	r3, [pc, #240]	@ (8002ab4 <start_feed+0x104>)
- 80029c4:	781b      	ldrb	r3, [r3, #0]
- 80029c6:	b2db      	uxtb	r3, r3
- 80029c8:	2b00      	cmp	r3, #0
- 80029ca:	d16e      	bne.n	8002aaa <start_feed+0xfa>
-	{
-		return; // Already feeding
-	}
-
-	// Check for first feed calibration
-	if (first_feed_since_load)
- 80029cc:	4b3a      	ldr	r3, [pc, #232]	@ (8002ab8 <start_feed+0x108>)
- 80029ce:	781b      	ldrb	r3, [r3, #0]
- 80029d0:	2b00      	cmp	r3, #0
- 80029d2:	d004      	beq.n	80029de <start_feed+0x2e>
-	{
-		check_tape_loaded();
- 80029d4:	f000 fa3c 	bl	8002e50 <check_tape_loaded>
-		first_feed_since_load = 0;
- 80029d8:	4b37      	ldr	r3, [pc, #220]	@ (8002ab8 <start_feed+0x108>)
- 80029da:	2200      	movs	r2, #0
- 80029dc:	701a      	strb	r2, [r3, #0]
-	}
-
-	feed_distance_tenths = distance_tenths;
- 80029de:	4b37      	ldr	r3, [pc, #220]	@ (8002abc <start_feed+0x10c>)
- 80029e0:	1dba      	adds	r2, r7, #6
- 80029e2:	8812      	ldrh	r2, [r2, #0]
- 80029e4:	801a      	strh	r2, [r3, #0]
-	feed_direction = forward;
- 80029e6:	4b36      	ldr	r3, [pc, #216]	@ (8002ac0 <start_feed+0x110>)
- 80029e8:	1d7a      	adds	r2, r7, #5
- 80029ea:	7812      	ldrb	r2, [r2, #0]
- 80029ec:	701a      	strb	r2, [r3, #0]
-	feed_retry_count = 0;
- 80029ee:	4b35      	ldr	r3, [pc, #212]	@ (8002ac4 <start_feed+0x114>)
- 80029f0:	2200      	movs	r2, #0
- 80029f2:	701a      	strb	r2, [r3, #0]
-	feed_in_progress = 1;
- 80029f4:	4b34      	ldr	r3, [pc, #208]	@ (8002ac8 <start_feed+0x118>)
- 80029f6:	2201      	movs	r2, #1
- 80029f8:	701a      	strb	r2, [r3, #0]
-	last_feed_status = STATUS_OK;
- 80029fa:	4b34      	ldr	r3, [pc, #208]	@ (8002acc <start_feed+0x11c>)
- 80029fc:	2200      	movs	r2, #0
- 80029fe:	701a      	strb	r2, [r3, #0]
-	set_LED(1, 1, 1); // White during feed
- 8002a00:	2201      	movs	r2, #1
- 8002a02:	2101      	movs	r1, #1
- 8002a04:	2001      	movs	r0, #1
- 8002a06:	f7ff f8b1 	bl	8001b6c <set_LED>
-
-	if (forward)
- 8002a0a:	1d7b      	adds	r3, r7, #5
- 8002a0c:	781b      	ldrb	r3, [r3, #0]
- 8002a0e:	2b00      	cmp	r3, #0
- 8002a10:	d035      	beq.n	8002a7e <start_feed+0xce>
-	{
-		// Forward feed: drive both motors simultaneously
-		feed_state = FEED_STATE_PEEL_FORWARD;
- 8002a12:	4b28      	ldr	r3, [pc, #160]	@ (8002ab4 <start_feed+0x104>)
- 8002a14:	2201      	movs	r2, #1
- 8002a16:	701a      	strb	r2, [r3, #0]
-		feed_state_start_time = HAL_GetTick();
- 8002a18:	f001 fb5e 	bl	80040d8 <HAL_GetTick>
- 8002a1c:	0002      	movs	r2, r0
- 8002a1e:	4b2c      	ldr	r3, [pc, #176]	@ (8002ad0 <start_feed+0x120>)
- 8002a20:	601a      	str	r2, [r3, #0]
-		feed_state_duration = distance_tenths * PEEL_TIME_PER_TENTH_MM;
- 8002a22:	1dbb      	adds	r3, r7, #6
- 8002a24:	2200      	movs	r2, #0
- 8002a26:	5e9a      	ldrsh	r2, [r3, r2]
- 8002a28:	0013      	movs	r3, r2
- 8002a2a:	00db      	lsls	r3, r3, #3
- 8002a2c:	189b      	adds	r3, r3, r2
- 8002a2e:	005b      	lsls	r3, r3, #1
- 8002a30:	001a      	movs	r2, r3
- 8002a32:	4b28      	ldr	r3, [pc, #160]	@ (8002ad4 <start_feed+0x124>)
- 8002a34:	601a      	str	r2, [r3, #0]
-		peel_motor(1); // Peel forward
- 8002a36:	2001      	movs	r0, #1
- 8002a38:	f7ff fde4 	bl	8002604 <peel_motor>
-		// Start feed motor at the same time
-		feed_timeout_time = HAL_GetTick() + (distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
- 8002a3c:	f001 fb4c 	bl	80040d8 <HAL_GetTick>
- 8002a40:	0001      	movs	r1, r0
- 8002a42:	1dbb      	adds	r3, r7, #6
- 8002a44:	2200      	movs	r2, #0
- 8002a46:	5e9a      	ldrsh	r2, [r3, r2]
- 8002a48:	0013      	movs	r3, r2
- 8002a4a:	009b      	lsls	r3, r3, #2
- 8002a4c:	189b      	adds	r3, r3, r2
- 8002a4e:	00db      	lsls	r3, r3, #3
- 8002a50:	18cb      	adds	r3, r1, r3
- 8002a52:	33f5      	adds	r3, #245	@ 0xf5
- 8002a54:	33ff      	adds	r3, #255	@ 0xff
- 8002a56:	001a      	movs	r2, r3
- 8002a58:	4b1f      	ldr	r3, [pc, #124]	@ (8002ad8 <start_feed+0x128>)
- 8002a5a:	601a      	str	r2, [r3, #0]
-		feed_target_position = total_count + tenths_to_counts(distance_tenths);
- 8002a5c:	1dbb      	adds	r3, r7, #6
- 8002a5e:	2200      	movs	r2, #0
- 8002a60:	5e9b      	ldrsh	r3, [r3, r2]
- 8002a62:	0018      	movs	r0, r3
- 8002a64:	f7ff ff34 	bl	80028d0 <tenths_to_counts>
- 8002a68:	0002      	movs	r2, r0
- 8002a6a:	4b1c      	ldr	r3, [pc, #112]	@ (8002adc <start_feed+0x12c>)
- 8002a6c:	681b      	ldr	r3, [r3, #0]
- 8002a6e:	18d2      	adds	r2, r2, r3
- 8002a70:	4b1b      	ldr	r3, [pc, #108]	@ (8002ae0 <start_feed+0x130>)
- 8002a72:	601a      	str	r2, [r3, #0]
-		target_count = feed_target_position;
- 8002a74:	4b1a      	ldr	r3, [pc, #104]	@ (8002ae0 <start_feed+0x130>)
- 8002a76:	681a      	ldr	r2, [r3, #0]
- 8002a78:	4b1a      	ldr	r3, [pc, #104]	@ (8002ae4 <start_feed+0x134>)
- 8002a7a:	601a      	str	r2, [r3, #0]
- 8002a7c:	e016      	b.n	8002aac <start_feed+0xfc>
-	}
-	else
-	{
-		// Backward feed: start with unpeeling to give slack
-		feed_state = FEED_STATE_UNPEEL;
- 8002a7e:	4b0d      	ldr	r3, [pc, #52]	@ (8002ab4 <start_feed+0x104>)
- 8002a80:	2203      	movs	r2, #3
- 8002a82:	701a      	strb	r2, [r3, #0]
-		feed_state_start_time = HAL_GetTick();
- 8002a84:	f001 fb28 	bl	80040d8 <HAL_GetTick>
- 8002a88:	0002      	movs	r2, r0
- 8002a8a:	4b11      	ldr	r3, [pc, #68]	@ (8002ad0 <start_feed+0x120>)
- 8002a8c:	601a      	str	r2, [r3, #0]
-		feed_state_duration = distance_tenths * BACKWARDS_PEEL_TIME_PER_TENTH_MM;
- 8002a8e:	1dbb      	adds	r3, r7, #6
- 8002a90:	2200      	movs	r2, #0
- 8002a92:	5e9a      	ldrsh	r2, [r3, r2]
- 8002a94:	0013      	movs	r3, r2
- 8002a96:	011b      	lsls	r3, r3, #4
- 8002a98:	1a9b      	subs	r3, r3, r2
- 8002a9a:	005b      	lsls	r3, r3, #1
- 8002a9c:	001a      	movs	r2, r3
- 8002a9e:	4b0d      	ldr	r3, [pc, #52]	@ (8002ad4 <start_feed+0x124>)
- 8002aa0:	601a      	str	r2, [r3, #0]
-		peel_motor(0); // Peel backward (unpeel)
- 8002aa2:	2000      	movs	r0, #0
- 8002aa4:	f7ff fdae 	bl	8002604 <peel_motor>
- 8002aa8:	e000      	b.n	8002aac <start_feed+0xfc>
-		return; // Already feeding
- 8002aaa:	46c0      	nop			@ (mov r8, r8)
-	}
-}
- 8002aac:	46bd      	mov	sp, r7
- 8002aae:	b002      	add	sp, #8
- 8002ab0:	bd80      	pop	{r7, pc}
- 8002ab2:	46c0      	nop			@ (mov r8, r8)
- 8002ab4:	200004bf 	.word	0x200004bf
- 8002ab8:	2000001d 	.word	0x2000001d
- 8002abc:	200004cc 	.word	0x200004cc
- 8002ac0:	2000001c 	.word	0x2000001c
- 8002ac4:	200004d4 	.word	0x200004d4
- 8002ac8:	200004bd 	.word	0x200004bd
- 8002acc:	200004bc 	.word	0x200004bc
- 8002ad0:	200004c0 	.word	0x200004c0
- 8002ad4:	200004c4 	.word	0x200004c4
- 8002ad8:	200004c8 	.word	0x200004c8
- 8002adc:	20000484 	.word	0x20000484
- 8002ae0:	200004d0 	.word	0x200004d0
- 8002ae4:	20000488 	.word	0x20000488
-
-08002ae8 <feed_state_machine_update>:
-
-// Update feed state machine - called from main loop
-void feed_state_machine_update(void)
-{
- 8002ae8:	b590      	push	{r4, r7, lr}
- 8002aea:	b087      	sub	sp, #28
- 8002aec:	af00      	add	r7, sp, #0
-	if (feed_state == FEED_STATE_IDLE)
- 8002aee:	4bc6      	ldr	r3, [pc, #792]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002af0:	781b      	ldrb	r3, [r3, #0]
- 8002af2:	b2db      	uxtb	r3, r3
- 8002af4:	2b00      	cmp	r3, #0
- 8002af6:	d100      	bne.n	8002afa <feed_state_machine_update+0x12>
- 8002af8:	e176      	b.n	8002de8 <feed_state_machine_update+0x300>
-	{
-		return;
-	}
-
-	uint32_t now = HAL_GetTick();
- 8002afa:	f001 faed 	bl	80040d8 <HAL_GetTick>
- 8002afe:	0003      	movs	r3, r0
- 8002b00:	60fb      	str	r3, [r7, #12]
-	uint32_t elapsed = now - feed_state_start_time;
- 8002b02:	4bc2      	ldr	r3, [pc, #776]	@ (8002e0c <feed_state_machine_update+0x324>)
- 8002b04:	681b      	ldr	r3, [r3, #0]
- 8002b06:	68fa      	ldr	r2, [r7, #12]
- 8002b08:	1ad3      	subs	r3, r2, r3
- 8002b0a:	60bb      	str	r3, [r7, #8]
-
-	switch (feed_state)
- 8002b0c:	4bbe      	ldr	r3, [pc, #760]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002b0e:	781b      	ldrb	r3, [r3, #0]
- 8002b10:	b2db      	uxtb	r3, r3
- 8002b12:	2b09      	cmp	r3, #9
- 8002b14:	d900      	bls.n	8002b18 <feed_state_machine_update+0x30>
- 8002b16:	e163      	b.n	8002de0 <feed_state_machine_update+0x2f8>
- 8002b18:	009a      	lsls	r2, r3, #2
- 8002b1a:	4bbd      	ldr	r3, [pc, #756]	@ (8002e10 <feed_state_machine_update+0x328>)
- 8002b1c:	18d3      	adds	r3, r2, r3
- 8002b1e:	681b      	ldr	r3, [r3, #0]
- 8002b20:	469f      	mov	pc, r3
-	{
-		case FEED_STATE_PEEL_FORWARD:
-			// Peeling film while feed motor drives simultaneously
-			if (elapsed >= feed_state_duration)
- 8002b22:	4bbc      	ldr	r3, [pc, #752]	@ (8002e14 <feed_state_machine_update+0x32c>)
- 8002b24:	681b      	ldr	r3, [r3, #0]
- 8002b26:	68ba      	ldr	r2, [r7, #8]
- 8002b28:	429a      	cmp	r2, r3
- 8002b2a:	d200      	bcs.n	8002b2e <feed_state_machine_update+0x46>
- 8002b2c:	e15e      	b.n	8002dec <feed_state_machine_update+0x304>
-			{
-				peel_brake(); // Peel done, feed motor continues via PID
- 8002b2e:	f7ff fd81 	bl	8002634 <peel_brake>
-				feed_state = FEED_STATE_DRIVING;
- 8002b32:	4bb5      	ldr	r3, [pc, #724]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002b34:	2204      	movs	r2, #4
- 8002b36:	701a      	strb	r2, [r3, #0]
-				feed_state_start_time = now;
- 8002b38:	4bb4      	ldr	r3, [pc, #720]	@ (8002e0c <feed_state_machine_update+0x324>)
- 8002b3a:	68fa      	ldr	r2, [r7, #12]
- 8002b3c:	601a      	str	r2, [r3, #0]
-				// feed_target_position and feed_timeout_time already set in start_feed
-			}
-			break;
- 8002b3e:	e155      	b.n	8002dec <feed_state_machine_update+0x304>
-
-		case FEED_STATE_UNPEEL:
-			// Unpeeling film before backward drive
-			if (elapsed >= feed_state_duration)
- 8002b40:	4bb4      	ldr	r3, [pc, #720]	@ (8002e14 <feed_state_machine_update+0x32c>)
- 8002b42:	681b      	ldr	r3, [r3, #0]
- 8002b44:	68ba      	ldr	r2, [r7, #8]
- 8002b46:	429a      	cmp	r2, r3
- 8002b48:	d200      	bcs.n	8002b4c <feed_state_machine_update+0x64>
- 8002b4a:	e151      	b.n	8002df0 <feed_state_machine_update+0x308>
-			{
-				peel_brake();
- 8002b4c:	f7ff fd72 	bl	8002634 <peel_brake>
-				// Start driving backward with backlash overshoot
-				feed_state = FEED_STATE_DRIVING;
- 8002b50:	4bad      	ldr	r3, [pc, #692]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002b52:	2204      	movs	r2, #4
- 8002b54:	701a      	strb	r2, [r3, #0]
-				feed_state_start_time = now;
- 8002b56:	4bad      	ldr	r3, [pc, #692]	@ (8002e0c <feed_state_machine_update+0x324>)
- 8002b58:	68fa      	ldr	r2, [r7, #12]
- 8002b5a:	601a      	str	r2, [r3, #0]
-				int16_t total_backward = feed_distance_tenths + BACKLASH_COMP_TENTH_MM;
- 8002b5c:	4bae      	ldr	r3, [pc, #696]	@ (8002e18 <feed_state_machine_update+0x330>)
- 8002b5e:	2200      	movs	r2, #0
- 8002b60:	5e9b      	ldrsh	r3, [r3, r2]
- 8002b62:	b29b      	uxth	r3, r3
- 8002b64:	330a      	adds	r3, #10
- 8002b66:	b29a      	uxth	r2, r3
- 8002b68:	1dbb      	adds	r3, r7, #6
- 8002b6a:	801a      	strh	r2, [r3, #0]
-				feed_timeout_time = now + (total_backward * TIMEOUT_TIME_PER_TENTH_MM) + 500;
- 8002b6c:	1dbb      	adds	r3, r7, #6
- 8002b6e:	2200      	movs	r2, #0
- 8002b70:	5e9a      	ldrsh	r2, [r3, r2]
- 8002b72:	0013      	movs	r3, r2
- 8002b74:	009b      	lsls	r3, r3, #2
- 8002b76:	189b      	adds	r3, r3, r2
- 8002b78:	00db      	lsls	r3, r3, #3
- 8002b7a:	001a      	movs	r2, r3
- 8002b7c:	68fb      	ldr	r3, [r7, #12]
- 8002b7e:	18d3      	adds	r3, r2, r3
- 8002b80:	33f5      	adds	r3, #245	@ 0xf5
- 8002b82:	33ff      	adds	r3, #255	@ 0xff
- 8002b84:	001a      	movs	r2, r3
- 8002b86:	4ba5      	ldr	r3, [pc, #660]	@ (8002e1c <feed_state_machine_update+0x334>)
- 8002b88:	601a      	str	r2, [r3, #0]
-				feed_target_position = total_count - tenths_to_counts(total_backward);
- 8002b8a:	4ba5      	ldr	r3, [pc, #660]	@ (8002e20 <feed_state_machine_update+0x338>)
- 8002b8c:	681c      	ldr	r4, [r3, #0]
- 8002b8e:	1dbb      	adds	r3, r7, #6
- 8002b90:	2200      	movs	r2, #0
- 8002b92:	5e9b      	ldrsh	r3, [r3, r2]
- 8002b94:	0018      	movs	r0, r3
- 8002b96:	f7ff fe9b 	bl	80028d0 <tenths_to_counts>
- 8002b9a:	0003      	movs	r3, r0
- 8002b9c:	1ae2      	subs	r2, r4, r3
- 8002b9e:	4ba1      	ldr	r3, [pc, #644]	@ (8002e24 <feed_state_machine_update+0x33c>)
- 8002ba0:	601a      	str	r2, [r3, #0]
-				target_count = feed_target_position;
- 8002ba2:	4ba0      	ldr	r3, [pc, #640]	@ (8002e24 <feed_state_machine_update+0x33c>)
- 8002ba4:	681a      	ldr	r2, [r3, #0]
- 8002ba6:	4ba0      	ldr	r3, [pc, #640]	@ (8002e28 <feed_state_machine_update+0x340>)
- 8002ba8:	601a      	str	r2, [r3, #0]
-			}
-			break;
- 8002baa:	e121      	b.n	8002df0 <feed_state_machine_update+0x308>
-
-		case FEED_STATE_DRIVING:
-			// Check for position reached and stall detection
-			{
-				int32_t error = feed_target_position - total_count;
- 8002bac:	4b9d      	ldr	r3, [pc, #628]	@ (8002e24 <feed_state_machine_update+0x33c>)
- 8002bae:	681a      	ldr	r2, [r3, #0]
- 8002bb0:	4b9b      	ldr	r3, [pc, #620]	@ (8002e20 <feed_state_machine_update+0x338>)
- 8002bb2:	681b      	ldr	r3, [r3, #0]
- 8002bb4:	1ad3      	subs	r3, r2, r3
- 8002bb6:	617b      	str	r3, [r7, #20]
-				if (error < 0) error = -error;
- 8002bb8:	697b      	ldr	r3, [r7, #20]
- 8002bba:	2b00      	cmp	r3, #0
- 8002bbc:	da02      	bge.n	8002bc4 <feed_state_machine_update+0xdc>
- 8002bbe:	697b      	ldr	r3, [r7, #20]
- 8002bc0:	425b      	negs	r3, r3
- 8002bc2:	617b      	str	r3, [r7, #20]
-
-				// Update stall detection
-				stall_detection_update(total_count);
- 8002bc4:	4b96      	ldr	r3, [pc, #600]	@ (8002e20 <feed_state_machine_update+0x338>)
- 8002bc6:	681b      	ldr	r3, [r3, #0]
- 8002bc8:	0018      	movs	r0, r3
- 8002bca:	f000 fa5b 	bl	8003084 <stall_detection_update>
-
-				// Check for stall and increase power if needed
-				if (check_stall(total_count) && !stall_cooldown)
- 8002bce:	4b94      	ldr	r3, [pc, #592]	@ (8002e20 <feed_state_machine_update+0x338>)
- 8002bd0:	681b      	ldr	r3, [r3, #0]
- 8002bd2:	0018      	movs	r0, r3
- 8002bd4:	f000 fa84 	bl	80030e0 <check_stall>
- 8002bd8:	1e03      	subs	r3, r0, #0
- 8002bda:	d016      	beq.n	8002c0a <feed_state_machine_update+0x122>
- 8002bdc:	4b93      	ldr	r3, [pc, #588]	@ (8002e2c <feed_state_machine_update+0x344>)
- 8002bde:	781b      	ldrb	r3, [r3, #0]
- 8002be0:	2b00      	cmp	r3, #0
- 8002be2:	d112      	bne.n	8002c0a <feed_state_machine_update+0x122>
-				{
-					current_drive_value += 3;
- 8002be4:	4b92      	ldr	r3, [pc, #584]	@ (8002e30 <feed_state_machine_update+0x348>)
- 8002be6:	781b      	ldrb	r3, [r3, #0]
- 8002be8:	3303      	adds	r3, #3
- 8002bea:	b2da      	uxtb	r2, r3
- 8002bec:	4b90      	ldr	r3, [pc, #576]	@ (8002e30 <feed_state_machine_update+0x348>)
- 8002bee:	701a      	strb	r2, [r3, #0]
-					if (current_drive_value > 255) current_drive_value = 255;
-					stall_cooldown = 1;
- 8002bf0:	4b8e      	ldr	r3, [pc, #568]	@ (8002e2c <feed_state_machine_update+0x344>)
- 8002bf2:	2201      	movs	r2, #1
- 8002bf4:	701a      	strb	r2, [r3, #0]
-					stall_cooldown_time = now;
- 8002bf6:	4b8f      	ldr	r3, [pc, #572]	@ (8002e34 <feed_state_machine_update+0x34c>)
- 8002bf8:	68fa      	ldr	r2, [r7, #12]
- 8002bfa:	601a      	str	r2, [r3, #0]
-
-					// If we're stalling a lot, mark as beefy tape
-					if (current_drive_value > 200)
- 8002bfc:	4b8c      	ldr	r3, [pc, #560]	@ (8002e30 <feed_state_machine_update+0x348>)
- 8002bfe:	781b      	ldrb	r3, [r3, #0]
- 8002c00:	2bc8      	cmp	r3, #200	@ 0xc8
- 8002c02:	d902      	bls.n	8002c0a <feed_state_machine_update+0x122>
-					{
-						beefy_tape = 1;
- 8002c04:	4b8c      	ldr	r3, [pc, #560]	@ (8002e38 <feed_state_machine_update+0x350>)
- 8002c06:	2201      	movs	r2, #1
- 8002c08:	701a      	strb	r2, [r3, #0]
-					}
-				}
-
-				// Reset stall cooldown after 5ms
-				if (stall_cooldown && (now - stall_cooldown_time) > 5)
- 8002c0a:	4b88      	ldr	r3, [pc, #544]	@ (8002e2c <feed_state_machine_update+0x344>)
- 8002c0c:	781b      	ldrb	r3, [r3, #0]
- 8002c0e:	2b00      	cmp	r3, #0
- 8002c10:	d008      	beq.n	8002c24 <feed_state_machine_update+0x13c>
- 8002c12:	4b88      	ldr	r3, [pc, #544]	@ (8002e34 <feed_state_machine_update+0x34c>)
- 8002c14:	681b      	ldr	r3, [r3, #0]
- 8002c16:	68fa      	ldr	r2, [r7, #12]
- 8002c18:	1ad3      	subs	r3, r2, r3
- 8002c1a:	2b05      	cmp	r3, #5
- 8002c1c:	d902      	bls.n	8002c24 <feed_state_machine_update+0x13c>
-				{
-					stall_cooldown = 0;
- 8002c1e:	4b83      	ldr	r3, [pc, #524]	@ (8002e2c <feed_state_machine_update+0x344>)
- 8002c20:	2200      	movs	r2, #0
- 8002c22:	701a      	strb	r2, [r3, #0]
-				}
-
-				if (error < FEED_POSITION_TOLERANCE)
- 8002c24:	697b      	ldr	r3, [r7, #20]
- 8002c26:	2b04      	cmp	r3, #4
- 8002c28:	dc1d      	bgt.n	8002c66 <feed_state_machine_update+0x17e>
-				{
-					// Position reached
-					stall_detection_init(); // Reset stall detection
- 8002c2a:	f000 f9f7 	bl	800301c <stall_detection_init>
-					if (!feed_direction)
- 8002c2e:	4b83      	ldr	r3, [pc, #524]	@ (8002e3c <feed_state_machine_update+0x354>)
- 8002c30:	781b      	ldrb	r3, [r3, #0]
- 8002c32:	2b00      	cmp	r3, #0
- 8002c34:	d10d      	bne.n	8002c52 <feed_state_machine_update+0x16a>
-					{
-						// Backward feed: take up slack then do final approach
-						feed_state = FEED_STATE_SLACK_REMOVAL;
- 8002c36:	4b74      	ldr	r3, [pc, #464]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002c38:	2205      	movs	r2, #5
- 8002c3a:	701a      	strb	r2, [r3, #0]
-						feed_state_start_time = now;
- 8002c3c:	4b73      	ldr	r3, [pc, #460]	@ (8002e0c <feed_state_machine_update+0x324>)
- 8002c3e:	68fa      	ldr	r2, [r7, #12]
- 8002c40:	601a      	str	r2, [r3, #0]
-						feed_state_duration = BACKWARDS_FEED_FILM_SLACK_REMOVAL_TIME;
- 8002c42:	4b74      	ldr	r3, [pc, #464]	@ (8002e14 <feed_state_machine_update+0x32c>)
- 8002c44:	22af      	movs	r2, #175	@ 0xaf
- 8002c46:	0052      	lsls	r2, r2, #1
- 8002c48:	601a      	str	r2, [r3, #0]
-						peel_motor(1); // Peel forward to take up slack
- 8002c4a:	2001      	movs	r0, #1
- 8002c4c:	f7ff fcda 	bl	8002604 <peel_motor>
-				{
-					// Timeout
-					feed_state = FEED_STATE_TIMEOUT;
-				}
-			}
-			break;
- 8002c50:	e0d0      	b.n	8002df4 <feed_state_machine_update+0x30c>
-						feed_state = FEED_STATE_SETTLING;
- 8002c52:	4b6d      	ldr	r3, [pc, #436]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002c54:	2207      	movs	r2, #7
- 8002c56:	701a      	strb	r2, [r3, #0]
-						feed_state_start_time = now;
- 8002c58:	4b6c      	ldr	r3, [pc, #432]	@ (8002e0c <feed_state_machine_update+0x324>)
- 8002c5a:	68fa      	ldr	r2, [r7, #12]
- 8002c5c:	601a      	str	r2, [r3, #0]
-						feed_state_duration = FEED_SETTLE_TIME;
- 8002c5e:	4b6d      	ldr	r3, [pc, #436]	@ (8002e14 <feed_state_machine_update+0x32c>)
- 8002c60:	2232      	movs	r2, #50	@ 0x32
- 8002c62:	601a      	str	r2, [r3, #0]
-			break;
- 8002c64:	e0c6      	b.n	8002df4 <feed_state_machine_update+0x30c>
-				else if (now > feed_timeout_time)
- 8002c66:	4b6d      	ldr	r3, [pc, #436]	@ (8002e1c <feed_state_machine_update+0x334>)
- 8002c68:	681b      	ldr	r3, [r3, #0]
- 8002c6a:	68fa      	ldr	r2, [r7, #12]
- 8002c6c:	429a      	cmp	r2, r3
- 8002c6e:	d800      	bhi.n	8002c72 <feed_state_machine_update+0x18a>
- 8002c70:	e0c0      	b.n	8002df4 <feed_state_machine_update+0x30c>
-					feed_state = FEED_STATE_TIMEOUT;
- 8002c72:	4b65      	ldr	r3, [pc, #404]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002c74:	2209      	movs	r2, #9
- 8002c76:	701a      	strb	r2, [r3, #0]
-			break;
- 8002c78:	e0bc      	b.n	8002df4 <feed_state_machine_update+0x30c>
-
-		case FEED_STATE_SLACK_REMOVAL:
-			// Taking up film slack after backward movement
-			if (elapsed >= feed_state_duration)
- 8002c7a:	4b66      	ldr	r3, [pc, #408]	@ (8002e14 <feed_state_machine_update+0x32c>)
- 8002c7c:	681b      	ldr	r3, [r3, #0]
- 8002c7e:	68ba      	ldr	r2, [r7, #8]
- 8002c80:	429a      	cmp	r2, r3
- 8002c82:	d200      	bcs.n	8002c86 <feed_state_machine_update+0x19e>
- 8002c84:	e0b8      	b.n	8002df8 <feed_state_machine_update+0x310>
-			{
-				peel_brake();
- 8002c86:	f7ff fcd5 	bl	8002634 <peel_brake>
-				// Final forward approach for backlash compensation
-				feed_state = FEED_STATE_DRIVING_BACKLASH;
- 8002c8a:	4b5f      	ldr	r3, [pc, #380]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002c8c:	2206      	movs	r2, #6
- 8002c8e:	701a      	strb	r2, [r3, #0]
-				feed_state_start_time = now;
- 8002c90:	4b5e      	ldr	r3, [pc, #376]	@ (8002e0c <feed_state_machine_update+0x324>)
- 8002c92:	68fa      	ldr	r2, [r7, #12]
- 8002c94:	601a      	str	r2, [r3, #0]
-				feed_timeout_time = now + (BACKLASH_COMP_TENTH_MM * TIMEOUT_TIME_PER_TENTH_MM) + 200;
- 8002c96:	68fb      	ldr	r3, [r7, #12]
- 8002c98:	2296      	movs	r2, #150	@ 0x96
- 8002c9a:	0092      	lsls	r2, r2, #2
- 8002c9c:	189a      	adds	r2, r3, r2
- 8002c9e:	4b5f      	ldr	r3, [pc, #380]	@ (8002e1c <feed_state_machine_update+0x334>)
- 8002ca0:	601a      	str	r2, [r3, #0]
-				// Move forward by backlash amount to final position
-				feed_target_position = total_count + tenths_to_counts(BACKLASH_COMP_TENTH_MM);
- 8002ca2:	200a      	movs	r0, #10
- 8002ca4:	f7ff fe14 	bl	80028d0 <tenths_to_counts>
- 8002ca8:	0002      	movs	r2, r0
- 8002caa:	4b5d      	ldr	r3, [pc, #372]	@ (8002e20 <feed_state_machine_update+0x338>)
- 8002cac:	681b      	ldr	r3, [r3, #0]
- 8002cae:	18d2      	adds	r2, r2, r3
- 8002cb0:	4b5c      	ldr	r3, [pc, #368]	@ (8002e24 <feed_state_machine_update+0x33c>)
- 8002cb2:	601a      	str	r2, [r3, #0]
-				target_count = feed_target_position;
- 8002cb4:	4b5b      	ldr	r3, [pc, #364]	@ (8002e24 <feed_state_machine_update+0x33c>)
- 8002cb6:	681a      	ldr	r2, [r3, #0]
- 8002cb8:	4b5b      	ldr	r3, [pc, #364]	@ (8002e28 <feed_state_machine_update+0x340>)
- 8002cba:	601a      	str	r2, [r3, #0]
-			}
-			break;
- 8002cbc:	e09c      	b.n	8002df8 <feed_state_machine_update+0x310>
-
-		case FEED_STATE_DRIVING_BACKLASH:
-			// Final forward approach after backward feed
-			{
-				int32_t error = feed_target_position - total_count;
- 8002cbe:	4b59      	ldr	r3, [pc, #356]	@ (8002e24 <feed_state_machine_update+0x33c>)
- 8002cc0:	681a      	ldr	r2, [r3, #0]
- 8002cc2:	4b57      	ldr	r3, [pc, #348]	@ (8002e20 <feed_state_machine_update+0x338>)
- 8002cc4:	681b      	ldr	r3, [r3, #0]
- 8002cc6:	1ad3      	subs	r3, r2, r3
- 8002cc8:	613b      	str	r3, [r7, #16]
-				if (error < 0) error = -error;
- 8002cca:	693b      	ldr	r3, [r7, #16]
- 8002ccc:	2b00      	cmp	r3, #0
- 8002cce:	da02      	bge.n	8002cd6 <feed_state_machine_update+0x1ee>
- 8002cd0:	693b      	ldr	r3, [r7, #16]
- 8002cd2:	425b      	negs	r3, r3
- 8002cd4:	613b      	str	r3, [r7, #16]
-
-				if (error < FEED_POSITION_TOLERANCE)
- 8002cd6:	693b      	ldr	r3, [r7, #16]
- 8002cd8:	2b04      	cmp	r3, #4
- 8002cda:	dc09      	bgt.n	8002cf0 <feed_state_machine_update+0x208>
-				{
-					feed_state = FEED_STATE_SETTLING;
- 8002cdc:	4b4a      	ldr	r3, [pc, #296]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002cde:	2207      	movs	r2, #7
- 8002ce0:	701a      	strb	r2, [r3, #0]
-					feed_state_start_time = now;
- 8002ce2:	4b4a      	ldr	r3, [pc, #296]	@ (8002e0c <feed_state_machine_update+0x324>)
- 8002ce4:	68fa      	ldr	r2, [r7, #12]
- 8002ce6:	601a      	str	r2, [r3, #0]
-					feed_state_duration = FEED_SETTLE_TIME;
- 8002ce8:	4b4a      	ldr	r3, [pc, #296]	@ (8002e14 <feed_state_machine_update+0x32c>)
- 8002cea:	2232      	movs	r2, #50	@ 0x32
- 8002cec:	601a      	str	r2, [r3, #0]
-				else if (now > feed_timeout_time)
-				{
-					feed_state = FEED_STATE_TIMEOUT;
-				}
-			}
-			break;
- 8002cee:	e085      	b.n	8002dfc <feed_state_machine_update+0x314>
-				else if (now > feed_timeout_time)
- 8002cf0:	4b4a      	ldr	r3, [pc, #296]	@ (8002e1c <feed_state_machine_update+0x334>)
- 8002cf2:	681b      	ldr	r3, [r3, #0]
- 8002cf4:	68fa      	ldr	r2, [r7, #12]
- 8002cf6:	429a      	cmp	r2, r3
- 8002cf8:	d800      	bhi.n	8002cfc <feed_state_machine_update+0x214>
- 8002cfa:	e07f      	b.n	8002dfc <feed_state_machine_update+0x314>
-					feed_state = FEED_STATE_TIMEOUT;
- 8002cfc:	4b42      	ldr	r3, [pc, #264]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002cfe:	2209      	movs	r2, #9
- 8002d00:	701a      	strb	r2, [r3, #0]
-			break;
- 8002d02:	e07b      	b.n	8002dfc <feed_state_machine_update+0x314>
-
-		case FEED_STATE_SETTLING:
-			// Wait for position to settle
-			if (elapsed >= feed_state_duration)
- 8002d04:	4b43      	ldr	r3, [pc, #268]	@ (8002e14 <feed_state_machine_update+0x32c>)
- 8002d06:	681b      	ldr	r3, [r3, #0]
- 8002d08:	68ba      	ldr	r2, [r7, #8]
- 8002d0a:	429a      	cmp	r2, r3
- 8002d0c:	d200      	bcs.n	8002d10 <feed_state_machine_update+0x228>
- 8002d0e:	e077      	b.n	8002e00 <feed_state_machine_update+0x318>
-			{
-				feed_state = FEED_STATE_COMPLETE;
- 8002d10:	4b3d      	ldr	r3, [pc, #244]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002d12:	2208      	movs	r2, #8
- 8002d14:	701a      	strb	r2, [r3, #0]
-			}
-			break;
- 8002d16:	e073      	b.n	8002e00 <feed_state_machine_update+0x318>
-
-		case FEED_STATE_COMPLETE:
-			feed_state = FEED_STATE_IDLE;
- 8002d18:	4b3b      	ldr	r3, [pc, #236]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002d1a:	2200      	movs	r2, #0
- 8002d1c:	701a      	strb	r2, [r3, #0]
-			feed_in_progress = 0;
- 8002d1e:	4b48      	ldr	r3, [pc, #288]	@ (8002e40 <feed_state_machine_update+0x358>)
- 8002d20:	2200      	movs	r2, #0
- 8002d22:	701a      	strb	r2, [r3, #0]
-			last_feed_status = STATUS_OK;
- 8002d24:	4b47      	ldr	r3, [pc, #284]	@ (8002e44 <feed_state_machine_update+0x35c>)
- 8002d26:	2200      	movs	r2, #0
- 8002d28:	701a      	strb	r2, [r3, #0]
-			feed_just_completed = 1;
- 8002d2a:	4b47      	ldr	r3, [pc, #284]	@ (8002e48 <feed_state_machine_update+0x360>)
- 8002d2c:	2201      	movs	r2, #1
- 8002d2e:	701a      	strb	r2, [r3, #0]
-			break;
- 8002d30:	e067      	b.n	8002e02 <feed_state_machine_update+0x31a>
-
-		case FEED_STATE_TIMEOUT:
-			// Handle timeout - could retry or fail
-			if (feed_retry_count < FEED_RETRY_LIMIT)
- 8002d32:	4b46      	ldr	r3, [pc, #280]	@ (8002e4c <feed_state_machine_update+0x364>)
- 8002d34:	781b      	ldrb	r3, [r3, #0]
- 8002d36:	2b02      	cmp	r3, #2
- 8002d38:	d843      	bhi.n	8002dc2 <feed_state_machine_update+0x2da>
-			{
-				feed_retry_count++;
- 8002d3a:	4b44      	ldr	r3, [pc, #272]	@ (8002e4c <feed_state_machine_update+0x364>)
- 8002d3c:	781b      	ldrb	r3, [r3, #0]
- 8002d3e:	3301      	adds	r3, #1
- 8002d40:	b2da      	uxtb	r2, r3
- 8002d42:	4b42      	ldr	r3, [pc, #264]	@ (8002e4c <feed_state_machine_update+0x364>)
- 8002d44:	701a      	strb	r2, [r3, #0]
-				// Move back slightly and retry
-				target_count = total_count - tenths_to_counts(5); // Back up 0.5mm
- 8002d46:	4b36      	ldr	r3, [pc, #216]	@ (8002e20 <feed_state_machine_update+0x338>)
- 8002d48:	681c      	ldr	r4, [r3, #0]
- 8002d4a:	2005      	movs	r0, #5
- 8002d4c:	f7ff fdc0 	bl	80028d0 <tenths_to_counts>
- 8002d50:	0003      	movs	r3, r0
- 8002d52:	1ae2      	subs	r2, r4, r3
- 8002d54:	4b34      	ldr	r3, [pc, #208]	@ (8002e28 <feed_state_machine_update+0x340>)
- 8002d56:	601a      	str	r2, [r3, #0]
-				HAL_Delay(50);
- 8002d58:	2032      	movs	r0, #50	@ 0x32
- 8002d5a:	f001 f9c7 	bl	80040ec <HAL_Delay>
-				// Restart the feed
-				if (feed_direction)
- 8002d5e:	4b37      	ldr	r3, [pc, #220]	@ (8002e3c <feed_state_machine_update+0x354>)
- 8002d60:	781b      	ldrb	r3, [r3, #0]
- 8002d62:	2b00      	cmp	r3, #0
- 8002d64:	d016      	beq.n	8002d94 <feed_state_machine_update+0x2ac>
-				{
-					feed_state = FEED_STATE_PEEL_FORWARD;
- 8002d66:	4b28      	ldr	r3, [pc, #160]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002d68:	2201      	movs	r2, #1
- 8002d6a:	701a      	strb	r2, [r3, #0]
-					feed_state_start_time = HAL_GetTick();
- 8002d6c:	f001 f9b4 	bl	80040d8 <HAL_GetTick>
- 8002d70:	0002      	movs	r2, r0
- 8002d72:	4b26      	ldr	r3, [pc, #152]	@ (8002e0c <feed_state_machine_update+0x324>)
- 8002d74:	601a      	str	r2, [r3, #0]
-					feed_state_duration = feed_distance_tenths * PEEL_TIME_PER_TENTH_MM;
- 8002d76:	4b28      	ldr	r3, [pc, #160]	@ (8002e18 <feed_state_machine_update+0x330>)
- 8002d78:	2200      	movs	r2, #0
- 8002d7a:	5e9b      	ldrsh	r3, [r3, r2]
- 8002d7c:	001a      	movs	r2, r3
- 8002d7e:	0013      	movs	r3, r2
- 8002d80:	00db      	lsls	r3, r3, #3
- 8002d82:	189b      	adds	r3, r3, r2
- 8002d84:	005b      	lsls	r3, r3, #1
- 8002d86:	001a      	movs	r2, r3
- 8002d88:	4b22      	ldr	r3, [pc, #136]	@ (8002e14 <feed_state_machine_update+0x32c>)
- 8002d8a:	601a      	str	r2, [r3, #0]
-					peel_motor(1);
- 8002d8c:	2001      	movs	r0, #1
- 8002d8e:	f7ff fc39 	bl	8002604 <peel_motor>
-				feed_in_progress = 0;
-				last_feed_status = STATUS_COULDNT_REACH;
-				feed_just_completed = 1;
-				halt_all();
-			}
-			break;
- 8002d92:	e036      	b.n	8002e02 <feed_state_machine_update+0x31a>
-					feed_state = FEED_STATE_UNPEEL;
- 8002d94:	4b1c      	ldr	r3, [pc, #112]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002d96:	2203      	movs	r2, #3
- 8002d98:	701a      	strb	r2, [r3, #0]
-					feed_state_start_time = HAL_GetTick();
- 8002d9a:	f001 f99d 	bl	80040d8 <HAL_GetTick>
- 8002d9e:	0002      	movs	r2, r0
- 8002da0:	4b1a      	ldr	r3, [pc, #104]	@ (8002e0c <feed_state_machine_update+0x324>)
- 8002da2:	601a      	str	r2, [r3, #0]
-					feed_state_duration = feed_distance_tenths * BACKWARDS_PEEL_TIME_PER_TENTH_MM;
- 8002da4:	4b1c      	ldr	r3, [pc, #112]	@ (8002e18 <feed_state_machine_update+0x330>)
- 8002da6:	2200      	movs	r2, #0
- 8002da8:	5e9b      	ldrsh	r3, [r3, r2]
- 8002daa:	001a      	movs	r2, r3
- 8002dac:	0013      	movs	r3, r2
- 8002dae:	011b      	lsls	r3, r3, #4
- 8002db0:	1a9b      	subs	r3, r3, r2
- 8002db2:	005b      	lsls	r3, r3, #1
- 8002db4:	001a      	movs	r2, r3
- 8002db6:	4b17      	ldr	r3, [pc, #92]	@ (8002e14 <feed_state_machine_update+0x32c>)
- 8002db8:	601a      	str	r2, [r3, #0]
-					peel_motor(0);
- 8002dba:	2000      	movs	r0, #0
- 8002dbc:	f7ff fc22 	bl	8002604 <peel_motor>
-			break;
- 8002dc0:	e01f      	b.n	8002e02 <feed_state_machine_update+0x31a>
-				feed_state = FEED_STATE_IDLE;
- 8002dc2:	4b11      	ldr	r3, [pc, #68]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002dc4:	2200      	movs	r2, #0
- 8002dc6:	701a      	strb	r2, [r3, #0]
-				feed_in_progress = 0;
- 8002dc8:	4b1d      	ldr	r3, [pc, #116]	@ (8002e40 <feed_state_machine_update+0x358>)
- 8002dca:	2200      	movs	r2, #0
- 8002dcc:	701a      	strb	r2, [r3, #0]
-				last_feed_status = STATUS_COULDNT_REACH;
- 8002dce:	4b1d      	ldr	r3, [pc, #116]	@ (8002e44 <feed_state_machine_update+0x35c>)
- 8002dd0:	2202      	movs	r2, #2
- 8002dd2:	701a      	strb	r2, [r3, #0]
-				feed_just_completed = 1;
- 8002dd4:	4b1c      	ldr	r3, [pc, #112]	@ (8002e48 <feed_state_machine_update+0x360>)
- 8002dd6:	2201      	movs	r2, #1
- 8002dd8:	701a      	strb	r2, [r3, #0]
-				halt_all();
- 8002dda:	f7ff fd09 	bl	80027f0 <halt_all>
-			break;
- 8002dde:	e010      	b.n	8002e02 <feed_state_machine_update+0x31a>
-
-		default:
-			feed_state = FEED_STATE_IDLE;
- 8002de0:	4b09      	ldr	r3, [pc, #36]	@ (8002e08 <feed_state_machine_update+0x320>)
- 8002de2:	2200      	movs	r2, #0
- 8002de4:	701a      	strb	r2, [r3, #0]
-			break;
- 8002de6:	e00c      	b.n	8002e02 <feed_state_machine_update+0x31a>
-		return;
- 8002de8:	46c0      	nop			@ (mov r8, r8)
- 8002dea:	e00a      	b.n	8002e02 <feed_state_machine_update+0x31a>
-			break;
- 8002dec:	46c0      	nop			@ (mov r8, r8)
- 8002dee:	e008      	b.n	8002e02 <feed_state_machine_update+0x31a>
-			break;
- 8002df0:	46c0      	nop			@ (mov r8, r8)
- 8002df2:	e006      	b.n	8002e02 <feed_state_machine_update+0x31a>
-			break;
- 8002df4:	46c0      	nop			@ (mov r8, r8)
- 8002df6:	e004      	b.n	8002e02 <feed_state_machine_update+0x31a>
-			break;
- 8002df8:	46c0      	nop			@ (mov r8, r8)
- 8002dfa:	e002      	b.n	8002e02 <feed_state_machine_update+0x31a>
-			break;
- 8002dfc:	46c0      	nop			@ (mov r8, r8)
- 8002dfe:	e000      	b.n	8002e02 <feed_state_machine_update+0x31a>
-			break;
- 8002e00:	46c0      	nop			@ (mov r8, r8)
-	}
-}
- 8002e02:	46bd      	mov	sp, r7
- 8002e04:	b007      	add	sp, #28
- 8002e06:	bd90      	pop	{r4, r7, pc}
- 8002e08:	200004bf 	.word	0x200004bf
- 8002e0c:	200004c0 	.word	0x200004c0
- 8002e10:	08007d88 	.word	0x08007d88
- 8002e14:	200004c4 	.word	0x200004c4
- 8002e18:	200004cc 	.word	0x200004cc
- 8002e1c:	200004c8 	.word	0x200004c8
- 8002e20:	20000484 	.word	0x20000484
- 8002e24:	200004d0 	.word	0x200004d0
- 8002e28:	20000488 	.word	0x20000488
- 8002e2c:	20000544 	.word	0x20000544
- 8002e30:	2000001e 	.word	0x2000001e
- 8002e34:	20000548 	.word	0x20000548
- 8002e38:	200004d5 	.word	0x200004d5
- 8002e3c:	2000001c 	.word	0x2000001c
- 8002e40:	200004bd 	.word	0x200004bd
- 8002e44:	200004bc 	.word	0x200004bc
- 8002e48:	200004be 	.word	0x200004be
- 8002e4c:	200004d4 	.word	0x200004d4
-
-08002e50 <check_tape_loaded>:
-
-// Check what type of tape is loaded (thick vs thin)
-void check_tape_loaded(void)
-{
- 8002e50:	b580      	push	{r7, lr}
- 8002e52:	b084      	sub	sp, #16
- 8002e54:	af00      	add	r7, sp, #0
-	// Take up any backlash slack
-	set_Feeder_PWM(250, 0); // Brief reverse
- 8002e56:	2100      	movs	r1, #0
- 8002e58:	20fa      	movs	r0, #250	@ 0xfa
- 8002e5a:	f7ff fb9f 	bl	800259c <set_Feeder_PWM>
-	HAL_Delay(2);
- 8002e5e:	2002      	movs	r0, #2
- 8002e60:	f001 f944 	bl	80040ec <HAL_Delay>
-	set_Feeder_PWM(20, 0);
- 8002e64:	2100      	movs	r1, #0
- 8002e66:	2014      	movs	r0, #20
- 8002e68:	f7ff fb98 	bl	800259c <set_Feeder_PWM>
-	HAL_Delay(100);
- 8002e6c:	2064      	movs	r0, #100	@ 0x64
- 8002e6e:	f001 f93d 	bl	80040ec <HAL_Delay>
-	set_Feeder_PWM(0, 0);
- 8002e72:	2100      	movs	r1, #0
- 8002e74:	2000      	movs	r0, #0
- 8002e76:	f7ff fb91 	bl	800259c <set_Feeder_PWM>
-	HAL_Delay(10);
- 8002e7a:	200a      	movs	r0, #10
- 8002e7c:	f001 f936 	bl	80040ec <HAL_Delay>
-
-	// Find starting threshold of movement
-	int32_t starting_count = total_count;
- 8002e80:	4b22      	ldr	r3, [pc, #136]	@ (8002f0c <check_tape_loaded+0xbc>)
- 8002e82:	681b      	ldr	r3, [r3, #0]
- 8002e84:	603b      	str	r3, [r7, #0]
-	int moved_at = 256;
- 8002e86:	2380      	movs	r3, #128	@ 0x80
- 8002e88:	005b      	lsls	r3, r3, #1
- 8002e8a:	60fb      	str	r3, [r7, #12]
-
-	for (int pwm = 20; pwm < 255; pwm += 5)
- 8002e8c:	2314      	movs	r3, #20
- 8002e8e:	60bb      	str	r3, [r7, #8]
- 8002e90:	e01c      	b.n	8002ecc <check_tape_loaded+0x7c>
-	{
-		set_Feeder_PWM(pwm, 0); // Drive backward
- 8002e92:	68bb      	ldr	r3, [r7, #8]
- 8002e94:	b29b      	uxth	r3, r3
- 8002e96:	2100      	movs	r1, #0
- 8002e98:	0018      	movs	r0, r3
- 8002e9a:	f7ff fb7f 	bl	800259c <set_Feeder_PWM>
-		HAL_Delay(75);
- 8002e9e:	204b      	movs	r0, #75	@ 0x4b
- 8002ea0:	f001 f924 	bl	80040ec <HAL_Delay>
-
-		int32_t diff = total_count - starting_count;
- 8002ea4:	4b19      	ldr	r3, [pc, #100]	@ (8002f0c <check_tape_loaded+0xbc>)
- 8002ea6:	681a      	ldr	r2, [r3, #0]
- 8002ea8:	683b      	ldr	r3, [r7, #0]
- 8002eaa:	1ad3      	subs	r3, r2, r3
- 8002eac:	607b      	str	r3, [r7, #4]
-		if (diff < 0) diff = -diff;
- 8002eae:	687b      	ldr	r3, [r7, #4]
- 8002eb0:	2b00      	cmp	r3, #0
- 8002eb2:	da02      	bge.n	8002eba <check_tape_loaded+0x6a>
- 8002eb4:	687b      	ldr	r3, [r7, #4]
- 8002eb6:	425b      	negs	r3, r3
- 8002eb8:	607b      	str	r3, [r7, #4]
-
-		if (diff > 3) // Movement detected
- 8002eba:	687b      	ldr	r3, [r7, #4]
- 8002ebc:	2b03      	cmp	r3, #3
- 8002ebe:	dd02      	ble.n	8002ec6 <check_tape_loaded+0x76>
-		{
-			moved_at = pwm;
- 8002ec0:	68bb      	ldr	r3, [r7, #8]
- 8002ec2:	60fb      	str	r3, [r7, #12]
-			break;
- 8002ec4:	e005      	b.n	8002ed2 <check_tape_loaded+0x82>
-	for (int pwm = 20; pwm < 255; pwm += 5)
- 8002ec6:	68bb      	ldr	r3, [r7, #8]
- 8002ec8:	3305      	adds	r3, #5
- 8002eca:	60bb      	str	r3, [r7, #8]
- 8002ecc:	68bb      	ldr	r3, [r7, #8]
- 8002ece:	2bfe      	cmp	r3, #254	@ 0xfe
- 8002ed0:	dddf      	ble.n	8002e92 <check_tape_loaded+0x42>
-		}
-	}
-
-	set_Feeder_PWM(0, 0);
- 8002ed2:	2100      	movs	r1, #0
- 8002ed4:	2000      	movs	r0, #0
- 8002ed6:	f7ff fb61 	bl	800259c <set_Feeder_PWM>
-	HAL_Delay(10);
- 8002eda:	200a      	movs	r0, #10
- 8002edc:	f001 f906 	bl	80040ec <HAL_Delay>
-
-	// Reset position
-	pid_reset(&motor_pid);
- 8002ee0:	4b0b      	ldr	r3, [pc, #44]	@ (8002f10 <check_tape_loaded+0xc0>)
- 8002ee2:	0018      	movs	r0, r3
- 8002ee4:	f7fd fc9a 	bl	800081c <pid_reset>
-	target_count = total_count;
- 8002ee8:	4b08      	ldr	r3, [pc, #32]	@ (8002f0c <check_tape_loaded+0xbc>)
- 8002eea:	681a      	ldr	r2, [r3, #0]
- 8002eec:	4b09      	ldr	r3, [pc, #36]	@ (8002f14 <check_tape_loaded+0xc4>)
- 8002eee:	601a      	str	r2, [r3, #0]
-
-	if (moved_at > 140)
- 8002ef0:	68fb      	ldr	r3, [r7, #12]
- 8002ef2:	2b8c      	cmp	r3, #140	@ 0x8c
- 8002ef4:	dd03      	ble.n	8002efe <check_tape_loaded+0xae>
-	{
-		beefy_tape = 1; // Thick tape detected
- 8002ef6:	4b08      	ldr	r3, [pc, #32]	@ (8002f18 <check_tape_loaded+0xc8>)
- 8002ef8:	2201      	movs	r2, #1
- 8002efa:	701a      	strb	r2, [r3, #0]
-	}
-	else
-	{
-		beefy_tape = 0;
-	}
-}
- 8002efc:	e002      	b.n	8002f04 <check_tape_loaded+0xb4>
-		beefy_tape = 0;
- 8002efe:	4b06      	ldr	r3, [pc, #24]	@ (8002f18 <check_tape_loaded+0xc8>)
- 8002f00:	2200      	movs	r2, #0
- 8002f02:	701a      	strb	r2, [r3, #0]
-}
- 8002f04:	46c0      	nop			@ (mov r8, r8)
- 8002f06:	46bd      	mov	sp, r7
- 8002f08:	b004      	add	sp, #16
- 8002f0a:	bd80      	pop	{r7, pc}
- 8002f0c:	20000484 	.word	0x20000484
- 8002f10:	2000048c 	.word	0x2000048c
- 8002f14:	20000488 	.word	0x20000488
- 8002f18:	200004d5 	.word	0x200004d5
-
-08002f1c <handle_vendor_options>:
-
-// Handle vendor-specific options
-void handle_vendor_options(uint8_t *options, uint8_t *response)
-{
- 8002f1c:	b580      	push	{r7, lr}
- 8002f1e:	b08c      	sub	sp, #48	@ 0x30
- 8002f20:	af00      	add	r7, sp, #0
- 8002f22:	6078      	str	r0, [r7, #4]
- 8002f24:	6039      	str	r1, [r7, #0]
-	uint8_t command = options[0];
- 8002f26:	212f      	movs	r1, #47	@ 0x2f
- 8002f28:	187b      	adds	r3, r7, r1
- 8002f2a:	687a      	ldr	r2, [r7, #4]
- 8002f2c:	7812      	ldrb	r2, [r2, #0]
- 8002f2e:	701a      	strb	r2, [r3, #0]
-
-	// Commands 0x00-0x0F: Get firmware version string in chunks
-	if (command <= 0x0F)
- 8002f30:	000a      	movs	r2, r1
- 8002f32:	18bb      	adds	r3, r7, r2
- 8002f34:	781b      	ldrb	r3, [r3, #0]
- 8002f36:	2b0f      	cmp	r3, #15
- 8002f38:	d82d      	bhi.n	8002f96 <handle_vendor_options+0x7a>
-	{
-		size_t version_len = strlen(VERSION_STRING);
- 8002f3a:	2309      	movs	r3, #9
- 8002f3c:	61bb      	str	r3, [r7, #24]
-		size_t start_index = command * VENDOR_SPECIFIC_OPTIONS_LENGTH;
- 8002f3e:	18bb      	adds	r3, r7, r2
- 8002f40:	781a      	ldrb	r2, [r3, #0]
- 8002f42:	0013      	movs	r3, r2
- 8002f44:	009b      	lsls	r3, r3, #2
- 8002f46:	189b      	adds	r3, r3, r2
- 8002f48:	009b      	lsls	r3, r3, #2
- 8002f4a:	617b      	str	r3, [r7, #20]
-
-		if (start_index < version_len)
- 8002f4c:	697a      	ldr	r2, [r7, #20]
- 8002f4e:	69bb      	ldr	r3, [r7, #24]
- 8002f50:	429a      	cmp	r2, r3
- 8002f52:	d219      	bcs.n	8002f88 <handle_vendor_options+0x6c>
-		{
-			size_t remaining = version_len - start_index;
- 8002f54:	69ba      	ldr	r2, [r7, #24]
- 8002f56:	697b      	ldr	r3, [r7, #20]
- 8002f58:	1ad3      	subs	r3, r2, r3
- 8002f5a:	613b      	str	r3, [r7, #16]
-			size_t copy_len = (remaining < VENDOR_SPECIFIC_OPTIONS_LENGTH) ? remaining : VENDOR_SPECIFIC_OPTIONS_LENGTH;
- 8002f5c:	693b      	ldr	r3, [r7, #16]
- 8002f5e:	2b14      	cmp	r3, #20
- 8002f60:	d900      	bls.n	8002f64 <handle_vendor_options+0x48>
- 8002f62:	2314      	movs	r3, #20
- 8002f64:	60fb      	str	r3, [r7, #12]
-			memcpy(response, VERSION_STRING + start_index, copy_len);
- 8002f66:	697a      	ldr	r2, [r7, #20]
- 8002f68:	4b2b      	ldr	r3, [pc, #172]	@ (8003018 <handle_vendor_options+0xfc>)
- 8002f6a:	18d1      	adds	r1, r2, r3
- 8002f6c:	68fa      	ldr	r2, [r7, #12]
- 8002f6e:	683b      	ldr	r3, [r7, #0]
- 8002f70:	0018      	movs	r0, r3
- 8002f72:	f004 fecb 	bl	8007d0c <memcpy>
-			// Null-terminate if there's room
-			if (copy_len < VENDOR_SPECIFIC_OPTIONS_LENGTH)
- 8002f76:	68fb      	ldr	r3, [r7, #12]
- 8002f78:	2b13      	cmp	r3, #19
- 8002f7a:	d847      	bhi.n	800300c <handle_vendor_options+0xf0>
-			{
-				response[copy_len] = '\0';
- 8002f7c:	683a      	ldr	r2, [r7, #0]
- 8002f7e:	68fb      	ldr	r3, [r7, #12]
- 8002f80:	18d3      	adds	r3, r2, r3
- 8002f82:	2200      	movs	r2, #0
- 8002f84:	701a      	strb	r2, [r3, #0]
-		}
-		else
-		{
-			memset(response, 0, VENDOR_SPECIFIC_OPTIONS_LENGTH);
-		}
-		return;
- 8002f86:	e041      	b.n	800300c <handle_vendor_options+0xf0>
-			memset(response, 0, VENDOR_SPECIFIC_OPTIONS_LENGTH);
- 8002f88:	683b      	ldr	r3, [r7, #0]
- 8002f8a:	2214      	movs	r2, #20
- 8002f8c:	2100      	movs	r1, #0
- 8002f8e:	0018      	movs	r0, r3
- 8002f90:	f004 fe90 	bl	8007cb4 <memset>
-		return;
- 8002f94:	e03a      	b.n	800300c <handle_vendor_options+0xf0>
-	}
-
-	switch (command)
- 8002f96:	232f      	movs	r3, #47	@ 0x2f
- 8002f98:	18fb      	adds	r3, r7, r3
- 8002f9a:	781b      	ldrb	r3, [r3, #0]
- 8002f9c:	2b10      	cmp	r3, #16
- 8002f9e:	d12e      	bne.n	8002ffe <handle_vendor_options+0xe2>
-	{
-		case 0x10:
-		{
-			// LED control
-			uint8_t led_mask = options[1];
- 8002fa0:	212e      	movs	r1, #46	@ 0x2e
- 8002fa2:	187b      	adds	r3, r7, r1
- 8002fa4:	687a      	ldr	r2, [r7, #4]
- 8002fa6:	7852      	ldrb	r2, [r2, #1]
- 8002fa8:	701a      	strb	r2, [r3, #0]
-			int blue = led_mask & 1;
- 8002faa:	187b      	adds	r3, r7, r1
- 8002fac:	781b      	ldrb	r3, [r3, #0]
- 8002fae:	2201      	movs	r2, #1
- 8002fb0:	4013      	ands	r3, r2
- 8002fb2:	62bb      	str	r3, [r7, #40]	@ 0x28
-			int green = (led_mask >> 1) & 1;
- 8002fb4:	187b      	adds	r3, r7, r1
- 8002fb6:	781b      	ldrb	r3, [r3, #0]
- 8002fb8:	085b      	lsrs	r3, r3, #1
- 8002fba:	b2db      	uxtb	r3, r3
- 8002fbc:	001a      	movs	r2, r3
- 8002fbe:	2301      	movs	r3, #1
- 8002fc0:	4013      	ands	r3, r2
- 8002fc2:	627b      	str	r3, [r7, #36]	@ 0x24
-			int red = (led_mask >> 2) & 1;
- 8002fc4:	187b      	adds	r3, r7, r1
- 8002fc6:	781b      	ldrb	r3, [r3, #0]
- 8002fc8:	089b      	lsrs	r3, r3, #2
- 8002fca:	b2db      	uxtb	r3, r3
- 8002fcc:	001a      	movs	r2, r3
- 8002fce:	2301      	movs	r3, #1
- 8002fd0:	4013      	ands	r3, r2
- 8002fd2:	623b      	str	r3, [r7, #32]
-			int set = (led_mask >> 3) & 1;
- 8002fd4:	187b      	adds	r3, r7, r1
- 8002fd6:	781b      	ldrb	r3, [r3, #0]
- 8002fd8:	08db      	lsrs	r3, r3, #3
- 8002fda:	b2db      	uxtb	r3, r3
- 8002fdc:	001a      	movs	r2, r3
- 8002fde:	2301      	movs	r3, #1
- 8002fe0:	4013      	ands	r3, r2
- 8002fe2:	61fb      	str	r3, [r7, #28]
-
-			if (set)
- 8002fe4:	69fb      	ldr	r3, [r7, #28]
- 8002fe6:	2b00      	cmp	r3, #0
- 8002fe8:	d012      	beq.n	8003010 <handle_vendor_options+0xf4>
-			{
-				set_LED(red, green, blue);
- 8002fea:	6a3b      	ldr	r3, [r7, #32]
- 8002fec:	b2db      	uxtb	r3, r3
- 8002fee:	6a7a      	ldr	r2, [r7, #36]	@ 0x24
- 8002ff0:	b2d1      	uxtb	r1, r2
- 8002ff2:	6aba      	ldr	r2, [r7, #40]	@ 0x28
- 8002ff4:	b2d2      	uxtb	r2, r2
- 8002ff6:	0018      	movs	r0, r3
- 8002ff8:	f7fe fdb8 	bl	8001b6c <set_LED>
-			}
-			break;
- 8002ffc:	e008      	b.n	8003010 <handle_vendor_options+0xf4>
-		}
-
-		default:
-			// Unknown command, return zeros
-			memset(response, 0, VENDOR_SPECIFIC_OPTIONS_LENGTH);
- 8002ffe:	683b      	ldr	r3, [r7, #0]
- 8003000:	2214      	movs	r2, #20
- 8003002:	2100      	movs	r1, #0
- 8003004:	0018      	movs	r0, r3
- 8003006:	f004 fe55 	bl	8007cb4 <memset>
-			break;
- 800300a:	e002      	b.n	8003012 <handle_vendor_options+0xf6>
-		return;
- 800300c:	46c0      	nop			@ (mov r8, r8)
- 800300e:	e000      	b.n	8003012 <handle_vendor_options+0xf6>
-			break;
- 8003010:	46c0      	nop			@ (mov r8, r8)
-	}
-}
- 8003012:	46bd      	mov	sp, r7
- 8003014:	b00c      	add	sp, #48	@ 0x30
- 8003016:	bd80      	pop	{r7, pc}
- 8003018:	08007d4c 	.word	0x08007d4c
-
-0800301c <stall_detection_init>:
-// ============================================================================
-// Stall Detection Functions
-// ============================================================================
-
-void stall_detection_init(void)
-{
- 800301c:	b580      	push	{r7, lr}
- 800301e:	b082      	sub	sp, #8
- 8003020:	af00      	add	r7, sp, #0
-	for (int i = 0; i < STALL_HISTORY_SIZE; i++)
- 8003022:	2300      	movs	r3, #0
- 8003024:	607b      	str	r3, [r7, #4]
- 8003026:	e007      	b.n	8003038 <stall_detection_init+0x1c>
-	{
-		stall_history[i] = 0;
- 8003028:	4b10      	ldr	r3, [pc, #64]	@ (800306c <stall_detection_init+0x50>)
- 800302a:	687a      	ldr	r2, [r7, #4]
- 800302c:	0092      	lsls	r2, r2, #2
- 800302e:	2100      	movs	r1, #0
- 8003030:	50d1      	str	r1, [r2, r3]
-	for (int i = 0; i < STALL_HISTORY_SIZE; i++)
- 8003032:	687b      	ldr	r3, [r7, #4]
- 8003034:	3301      	adds	r3, #1
- 8003036:	607b      	str	r3, [r7, #4]
- 8003038:	687b      	ldr	r3, [r7, #4]
- 800303a:	2b13      	cmp	r3, #19
- 800303c:	ddf4      	ble.n	8003028 <stall_detection_init+0xc>
-	}
-	stall_history_index = 0;
- 800303e:	4b0c      	ldr	r3, [pc, #48]	@ (8003070 <stall_detection_init+0x54>)
- 8003040:	2200      	movs	r2, #0
- 8003042:	701a      	strb	r2, [r3, #0]
-	last_stall_sample_time = 0;
- 8003044:	4b0b      	ldr	r3, [pc, #44]	@ (8003074 <stall_detection_init+0x58>)
- 8003046:	2200      	movs	r2, #0
- 8003048:	601a      	str	r2, [r3, #0]
-	stall_cooldown = 0;
- 800304a:	4b0b      	ldr	r3, [pc, #44]	@ (8003078 <stall_detection_init+0x5c>)
- 800304c:	2200      	movs	r2, #0
- 800304e:	701a      	strb	r2, [r3, #0]
-	current_drive_value = beefy_tape ? 255 : 30;
- 8003050:	4b0a      	ldr	r3, [pc, #40]	@ (800307c <stall_detection_init+0x60>)
- 8003052:	781b      	ldrb	r3, [r3, #0]
- 8003054:	2b00      	cmp	r3, #0
- 8003056:	d001      	beq.n	800305c <stall_detection_init+0x40>
- 8003058:	22ff      	movs	r2, #255	@ 0xff
- 800305a:	e000      	b.n	800305e <stall_detection_init+0x42>
- 800305c:	221e      	movs	r2, #30
- 800305e:	4b08      	ldr	r3, [pc, #32]	@ (8003080 <stall_detection_init+0x64>)
- 8003060:	701a      	strb	r2, [r3, #0]
-}
- 8003062:	46c0      	nop			@ (mov r8, r8)
- 8003064:	46bd      	mov	sp, r7
- 8003066:	b002      	add	sp, #8
- 8003068:	bd80      	pop	{r7, pc}
- 800306a:	46c0      	nop			@ (mov r8, r8)
- 800306c:	200004ec 	.word	0x200004ec
- 8003070:	2000053c 	.word	0x2000053c
- 8003074:	20000540 	.word	0x20000540
- 8003078:	20000544 	.word	0x20000544
- 800307c:	200004d5 	.word	0x200004d5
- 8003080:	2000001e 	.word	0x2000001e
-
-08003084 <stall_detection_update>:
-
-void stall_detection_update(int32_t current_tick)
-{
- 8003084:	b580      	push	{r7, lr}
- 8003086:	b084      	sub	sp, #16
- 8003088:	af00      	add	r7, sp, #0
- 800308a:	6078      	str	r0, [r7, #4]
-	uint32_t now = HAL_GetTick();
- 800308c:	f001 f824 	bl	80040d8 <HAL_GetTick>
- 8003090:	0003      	movs	r3, r0
- 8003092:	60fb      	str	r3, [r7, #12]
-	if ((now - last_stall_sample_time) >= STALL_SAMPLE_INTERVAL_MS)
- 8003094:	4b0f      	ldr	r3, [pc, #60]	@ (80030d4 <stall_detection_update+0x50>)
- 8003096:	681b      	ldr	r3, [r3, #0]
- 8003098:	68fa      	ldr	r2, [r7, #12]
- 800309a:	429a      	cmp	r2, r3
- 800309c:	d016      	beq.n	80030cc <stall_detection_update+0x48>
-	{
-		last_stall_sample_time = now;
- 800309e:	4b0d      	ldr	r3, [pc, #52]	@ (80030d4 <stall_detection_update+0x50>)
- 80030a0:	68fa      	ldr	r2, [r7, #12]
- 80030a2:	601a      	str	r2, [r3, #0]
-		stall_history[stall_history_index] = current_tick;
- 80030a4:	4b0c      	ldr	r3, [pc, #48]	@ (80030d8 <stall_detection_update+0x54>)
- 80030a6:	781b      	ldrb	r3, [r3, #0]
- 80030a8:	001a      	movs	r2, r3
- 80030aa:	4b0c      	ldr	r3, [pc, #48]	@ (80030dc <stall_detection_update+0x58>)
- 80030ac:	0092      	lsls	r2, r2, #2
- 80030ae:	6879      	ldr	r1, [r7, #4]
- 80030b0:	50d1      	str	r1, [r2, r3]
-		stall_history_index++;
- 80030b2:	4b09      	ldr	r3, [pc, #36]	@ (80030d8 <stall_detection_update+0x54>)
- 80030b4:	781b      	ldrb	r3, [r3, #0]
- 80030b6:	3301      	adds	r3, #1
- 80030b8:	b2da      	uxtb	r2, r3
- 80030ba:	4b07      	ldr	r3, [pc, #28]	@ (80030d8 <stall_detection_update+0x54>)
- 80030bc:	701a      	strb	r2, [r3, #0]
-		if (stall_history_index >= STALL_HISTORY_SIZE)
- 80030be:	4b06      	ldr	r3, [pc, #24]	@ (80030d8 <stall_detection_update+0x54>)
- 80030c0:	781b      	ldrb	r3, [r3, #0]
- 80030c2:	2b13      	cmp	r3, #19
- 80030c4:	d902      	bls.n	80030cc <stall_detection_update+0x48>
-		{
-			stall_history_index = 0;
- 80030c6:	4b04      	ldr	r3, [pc, #16]	@ (80030d8 <stall_detection_update+0x54>)
- 80030c8:	2200      	movs	r2, #0
- 80030ca:	701a      	strb	r2, [r3, #0]
-		}
-	}
-}
- 80030cc:	46c0      	nop			@ (mov r8, r8)
- 80030ce:	46bd      	mov	sp, r7
- 80030d0:	b004      	add	sp, #16
- 80030d2:	bd80      	pop	{r7, pc}
- 80030d4:	20000540 	.word	0x20000540
- 80030d8:	2000053c 	.word	0x2000053c
- 80030dc:	200004ec 	.word	0x200004ec
-
-080030e0 <check_stall>:
-
-uint8_t check_stall(int32_t current_tick)
-{
- 80030e0:	b580      	push	{r7, lr}
- 80030e2:	b086      	sub	sp, #24
- 80030e4:	af00      	add	r7, sp, #0
- 80030e6:	6078      	str	r0, [r7, #4]
-	// Find min and max in history
-	int32_t min_val = stall_history[0];
- 80030e8:	4b1b      	ldr	r3, [pc, #108]	@ (8003158 <check_stall+0x78>)
- 80030ea:	681b      	ldr	r3, [r3, #0]
- 80030ec:	617b      	str	r3, [r7, #20]
-	int32_t max_val = stall_history[0];
- 80030ee:	4b1a      	ldr	r3, [pc, #104]	@ (8003158 <check_stall+0x78>)
- 80030f0:	681b      	ldr	r3, [r3, #0]
- 80030f2:	613b      	str	r3, [r7, #16]
-
-	for (int i = 1; i < STALL_HISTORY_SIZE; i++)
- 80030f4:	2301      	movs	r3, #1
- 80030f6:	60fb      	str	r3, [r7, #12]
- 80030f8:	e01a      	b.n	8003130 <check_stall+0x50>
-	{
-		if (stall_history[i] < min_val) min_val = stall_history[i];
- 80030fa:	4b17      	ldr	r3, [pc, #92]	@ (8003158 <check_stall+0x78>)
- 80030fc:	68fa      	ldr	r2, [r7, #12]
- 80030fe:	0092      	lsls	r2, r2, #2
- 8003100:	58d3      	ldr	r3, [r2, r3]
- 8003102:	697a      	ldr	r2, [r7, #20]
- 8003104:	429a      	cmp	r2, r3
- 8003106:	dd04      	ble.n	8003112 <check_stall+0x32>
- 8003108:	4b13      	ldr	r3, [pc, #76]	@ (8003158 <check_stall+0x78>)
- 800310a:	68fa      	ldr	r2, [r7, #12]
- 800310c:	0092      	lsls	r2, r2, #2
- 800310e:	58d3      	ldr	r3, [r2, r3]
- 8003110:	617b      	str	r3, [r7, #20]
-		if (stall_history[i] > max_val) max_val = stall_history[i];
- 8003112:	4b11      	ldr	r3, [pc, #68]	@ (8003158 <check_stall+0x78>)
- 8003114:	68fa      	ldr	r2, [r7, #12]
- 8003116:	0092      	lsls	r2, r2, #2
- 8003118:	58d3      	ldr	r3, [r2, r3]
- 800311a:	693a      	ldr	r2, [r7, #16]
- 800311c:	429a      	cmp	r2, r3
- 800311e:	da04      	bge.n	800312a <check_stall+0x4a>
- 8003120:	4b0d      	ldr	r3, [pc, #52]	@ (8003158 <check_stall+0x78>)
- 8003122:	68fa      	ldr	r2, [r7, #12]
- 8003124:	0092      	lsls	r2, r2, #2
- 8003126:	58d3      	ldr	r3, [r2, r3]
- 8003128:	613b      	str	r3, [r7, #16]
-	for (int i = 1; i < STALL_HISTORY_SIZE; i++)
- 800312a:	68fb      	ldr	r3, [r7, #12]
- 800312c:	3301      	adds	r3, #1
- 800312e:	60fb      	str	r3, [r7, #12]
- 8003130:	68fb      	ldr	r3, [r7, #12]
- 8003132:	2b13      	cmp	r3, #19
- 8003134:	dde1      	ble.n	80030fa <check_stall+0x1a>
-	}
-
-	int32_t delta = max_val - min_val;
- 8003136:	693a      	ldr	r2, [r7, #16]
- 8003138:	697b      	ldr	r3, [r7, #20]
- 800313a:	1ad3      	subs	r3, r2, r3
- 800313c:	60bb      	str	r3, [r7, #8]
-	return (delta <= STALL_THRESHOLD);
- 800313e:	68bb      	ldr	r3, [r7, #8]
- 8003140:	2205      	movs	r2, #5
- 8003142:	0fd8      	lsrs	r0, r3, #31
- 8003144:	17d1      	asrs	r1, r2, #31
- 8003146:	429a      	cmp	r2, r3
- 8003148:	4148      	adcs	r0, r1
- 800314a:	0003      	movs	r3, r0
- 800314c:	b2db      	uxtb	r3, r3
-}
- 800314e:	0018      	movs	r0, r3
- 8003150:	46bd      	mov	sp, r7
- 8003152:	b006      	add	sp, #24
- 8003154:	bd80      	pop	{r7, pc}
- 8003156:	46c0      	nop			@ (mov r8, r8)
- 8003158:	200004ec 	.word	0x200004ec
-
-0800315c <onewire_delay_us>:
-// OneWire Functions (Bit-banging for DS2431 EEPROM)
-// ============================================================================
-
-// Microsecond delay using DWT cycle counter or busy loop
-void onewire_delay_us(uint32_t us)
-{
- 800315c:	b580      	push	{r7, lr}
- 800315e:	b084      	sub	sp, #16
- 8003160:	af00      	add	r7, sp, #0
- 8003162:	6078      	str	r0, [r7, #4]
-	// Simple busy-wait delay - approximately calibrated for 48MHz
-	volatile uint32_t count = us * 12; // Adjust multiplier as needed
- 8003164:	687a      	ldr	r2, [r7, #4]
- 8003166:	0013      	movs	r3, r2
- 8003168:	005b      	lsls	r3, r3, #1
- 800316a:	189b      	adds	r3, r3, r2
- 800316c:	009b      	lsls	r3, r3, #2
- 800316e:	60fb      	str	r3, [r7, #12]
-	while (count--) { __NOP(); }
- 8003170:	e000      	b.n	8003174 <onewire_delay_us+0x18>
- 8003172:	46c0      	nop			@ (mov r8, r8)
- 8003174:	68fb      	ldr	r3, [r7, #12]
- 8003176:	1e5a      	subs	r2, r3, #1
- 8003178:	60fa      	str	r2, [r7, #12]
- 800317a:	2b00      	cmp	r3, #0
- 800317c:	d1f9      	bne.n	8003172 <onewire_delay_us+0x16>
-}
- 800317e:	46c0      	nop			@ (mov r8, r8)
- 8003180:	46c0      	nop			@ (mov r8, r8)
- 8003182:	46bd      	mov	sp, r7
- 8003184:	b004      	add	sp, #16
- 8003186:	bd80      	pop	{r7, pc}
-
-08003188 <onewire_set_output>:
-
-void onewire_set_output(void)
-{
- 8003188:	b580      	push	{r7, lr}
- 800318a:	b086      	sub	sp, #24
- 800318c:	af00      	add	r7, sp, #0
-	GPIO_InitTypeDef GPIO_InitStruct = {0};
- 800318e:	1d3b      	adds	r3, r7, #4
- 8003190:	0018      	movs	r0, r3
- 8003192:	2314      	movs	r3, #20
- 8003194:	001a      	movs	r2, r3
- 8003196:	2100      	movs	r1, #0
- 8003198:	f004 fd8c 	bl	8007cb4 <memset>
-	GPIO_InitStruct.Pin = ONEWIRE_Pin;
- 800319c:	1d3b      	adds	r3, r7, #4
- 800319e:	2280      	movs	r2, #128	@ 0x80
- 80031a0:	00d2      	lsls	r2, r2, #3
- 80031a2:	601a      	str	r2, [r3, #0]
-	GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD; // Open-drain for OneWire
- 80031a4:	1d3b      	adds	r3, r7, #4
- 80031a6:	2211      	movs	r2, #17
- 80031a8:	605a      	str	r2, [r3, #4]
-	GPIO_InitStruct.Pull = GPIO_NOPULL;
- 80031aa:	1d3b      	adds	r3, r7, #4
- 80031ac:	2200      	movs	r2, #0
- 80031ae:	609a      	str	r2, [r3, #8]
-	GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_HIGH;
- 80031b0:	1d3b      	adds	r3, r7, #4
- 80031b2:	2202      	movs	r2, #2
- 80031b4:	60da      	str	r2, [r3, #12]
-	HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
- 80031b6:	1d3a      	adds	r2, r7, #4
- 80031b8:	23a0      	movs	r3, #160	@ 0xa0
- 80031ba:	05db      	lsls	r3, r3, #23
- 80031bc:	0011      	movs	r1, r2
- 80031be:	0018      	movs	r0, r3
- 80031c0:	f001 fb08 	bl	80047d4 <HAL_GPIO_Init>
-}
- 80031c4:	46c0      	nop			@ (mov r8, r8)
- 80031c6:	46bd      	mov	sp, r7
- 80031c8:	b006      	add	sp, #24
- 80031ca:	bd80      	pop	{r7, pc}
-
-080031cc <onewire_set_input>:
-
-void onewire_set_input(void)
-{
- 80031cc:	b580      	push	{r7, lr}
- 80031ce:	b086      	sub	sp, #24
- 80031d0:	af00      	add	r7, sp, #0
-	GPIO_InitTypeDef GPIO_InitStruct = {0};
- 80031d2:	1d3b      	adds	r3, r7, #4
- 80031d4:	0018      	movs	r0, r3
- 80031d6:	2314      	movs	r3, #20
- 80031d8:	001a      	movs	r2, r3
- 80031da:	2100      	movs	r1, #0
- 80031dc:	f004 fd6a 	bl	8007cb4 <memset>
-	GPIO_InitStruct.Pin = ONEWIRE_Pin;
- 80031e0:	1d3b      	adds	r3, r7, #4
- 80031e2:	2280      	movs	r2, #128	@ 0x80
- 80031e4:	00d2      	lsls	r2, r2, #3
- 80031e6:	601a      	str	r2, [r3, #0]
-	GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
- 80031e8:	1d3b      	adds	r3, r7, #4
- 80031ea:	2200      	movs	r2, #0
- 80031ec:	605a      	str	r2, [r3, #4]
-	GPIO_InitStruct.Pull = GPIO_PULLUP;
- 80031ee:	1d3b      	adds	r3, r7, #4
- 80031f0:	2201      	movs	r2, #1
- 80031f2:	609a      	str	r2, [r3, #8]
-	HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
- 80031f4:	1d3a      	adds	r2, r7, #4
- 80031f6:	23a0      	movs	r3, #160	@ 0xa0
- 80031f8:	05db      	lsls	r3, r3, #23
- 80031fa:	0011      	movs	r1, r2
- 80031fc:	0018      	movs	r0, r3
- 80031fe:	f001 fae9 	bl	80047d4 <HAL_GPIO_Init>
-}
- 8003202:	46c0      	nop			@ (mov r8, r8)
- 8003204:	46bd      	mov	sp, r7
- 8003206:	b006      	add	sp, #24
- 8003208:	bd80      	pop	{r7, pc}
-
-0800320a <onewire_write_low>:
-
-void onewire_write_low(void)
-{
- 800320a:	b580      	push	{r7, lr}
- 800320c:	af00      	add	r7, sp, #0
-	HAL_GPIO_WritePin(ONEWIRE_GPIO_Port, ONEWIRE_Pin, GPIO_PIN_RESET);
- 800320e:	2380      	movs	r3, #128	@ 0x80
- 8003210:	00d9      	lsls	r1, r3, #3
- 8003212:	23a0      	movs	r3, #160	@ 0xa0
- 8003214:	05db      	lsls	r3, r3, #23
- 8003216:	2200      	movs	r2, #0
- 8003218:	0018      	movs	r0, r3
- 800321a:	f001 fc6a 	bl	8004af2 <HAL_GPIO_WritePin>
-}
- 800321e:	46c0      	nop			@ (mov r8, r8)
- 8003220:	46bd      	mov	sp, r7
- 8003222:	bd80      	pop	{r7, pc}
-
-08003224 <onewire_write_high>:
-
-void onewire_write_high(void)
-{
- 8003224:	b580      	push	{r7, lr}
- 8003226:	af00      	add	r7, sp, #0
-	HAL_GPIO_WritePin(ONEWIRE_GPIO_Port, ONEWIRE_Pin, GPIO_PIN_SET);
- 8003228:	2380      	movs	r3, #128	@ 0x80
- 800322a:	00d9      	lsls	r1, r3, #3
- 800322c:	23a0      	movs	r3, #160	@ 0xa0
- 800322e:	05db      	lsls	r3, r3, #23
- 8003230:	2201      	movs	r2, #1
- 8003232:	0018      	movs	r0, r3
- 8003234:	f001 fc5d 	bl	8004af2 <HAL_GPIO_WritePin>
-}
- 8003238:	46c0      	nop			@ (mov r8, r8)
- 800323a:	46bd      	mov	sp, r7
- 800323c:	bd80      	pop	{r7, pc}
-
-0800323e <onewire_read_bit>:
-
-uint8_t onewire_read_bit(void)
-{
- 800323e:	b580      	push	{r7, lr}
- 8003240:	af00      	add	r7, sp, #0
-	return HAL_GPIO_ReadPin(ONEWIRE_GPIO_Port, ONEWIRE_Pin);
- 8003242:	2380      	movs	r3, #128	@ 0x80
- 8003244:	00da      	lsls	r2, r3, #3
- 8003246:	23a0      	movs	r3, #160	@ 0xa0
- 8003248:	05db      	lsls	r3, r3, #23
- 800324a:	0011      	movs	r1, r2
- 800324c:	0018      	movs	r0, r3
- 800324e:	f001 fc33 	bl	8004ab8 <HAL_GPIO_ReadPin>
- 8003252:	0003      	movs	r3, r0
-}
- 8003254:	0018      	movs	r0, r3
- 8003256:	46bd      	mov	sp, r7
- 8003258:	bd80      	pop	{r7, pc}
-
-0800325a <onewire_reset>:
-
-// Reset pulse - returns 1 if device present, 0 if not
-uint8_t onewire_reset(void)
-{
- 800325a:	b580      	push	{r7, lr}
- 800325c:	b082      	sub	sp, #8
- 800325e:	af00      	add	r7, sp, #0
-	uint8_t presence;
-
-	onewire_set_output();
- 8003260:	f7ff ff92 	bl	8003188 <onewire_set_output>
-	onewire_write_low();
- 8003264:	f7ff ffd1 	bl	800320a <onewire_write_low>
-	onewire_delay_us(ONEWIRE_DELAY_H); // 480us
- 8003268:	23f0      	movs	r3, #240	@ 0xf0
- 800326a:	005b      	lsls	r3, r3, #1
- 800326c:	0018      	movs	r0, r3
- 800326e:	f7ff ff75 	bl	800315c <onewire_delay_us>
-
-	onewire_set_input();
- 8003272:	f7ff ffab 	bl	80031cc <onewire_set_input>
-	onewire_delay_us(ONEWIRE_DELAY_I); // 70us
- 8003276:	2046      	movs	r0, #70	@ 0x46
- 8003278:	f7ff ff70 	bl	800315c <onewire_delay_us>
-
-	presence = !onewire_read_bit(); // Device pulls low if present
- 800327c:	f7ff ffdf 	bl	800323e <onewire_read_bit>
- 8003280:	0003      	movs	r3, r0
- 8003282:	425a      	negs	r2, r3
- 8003284:	4153      	adcs	r3, r2
- 8003286:	b2da      	uxtb	r2, r3
- 8003288:	1dfb      	adds	r3, r7, #7
- 800328a:	701a      	strb	r2, [r3, #0]
-
-	onewire_delay_us(ONEWIRE_DELAY_J); // 410us
- 800328c:	23cd      	movs	r3, #205	@ 0xcd
- 800328e:	005b      	lsls	r3, r3, #1
- 8003290:	0018      	movs	r0, r3
- 8003292:	f7ff ff63 	bl	800315c <onewire_delay_us>
-
-	return presence;
- 8003296:	1dfb      	adds	r3, r7, #7
- 8003298:	781b      	ldrb	r3, [r3, #0]
-}
- 800329a:	0018      	movs	r0, r3
- 800329c:	46bd      	mov	sp, r7
- 800329e:	b002      	add	sp, #8
- 80032a0:	bd80      	pop	{r7, pc}
-
-080032a2 <onewire_write_bit>:
-
-void onewire_write_bit(uint8_t bit)
-{
- 80032a2:	b580      	push	{r7, lr}
- 80032a4:	b082      	sub	sp, #8
- 80032a6:	af00      	add	r7, sp, #0
- 80032a8:	0002      	movs	r2, r0
- 80032aa:	1dfb      	adds	r3, r7, #7
- 80032ac:	701a      	strb	r2, [r3, #0]
-	onewire_set_output();
- 80032ae:	f7ff ff6b 	bl	8003188 <onewire_set_output>
-
-	if (bit)
- 80032b2:	1dfb      	adds	r3, r7, #7
- 80032b4:	781b      	ldrb	r3, [r3, #0]
- 80032b6:	2b00      	cmp	r3, #0
- 80032b8:	d00a      	beq.n	80032d0 <onewire_write_bit+0x2e>
-	{
-		// Write 1: pull low briefly, then release
-		onewire_write_low();
- 80032ba:	f7ff ffa6 	bl	800320a <onewire_write_low>
-		onewire_delay_us(ONEWIRE_DELAY_A); // 6us
- 80032be:	2006      	movs	r0, #6
- 80032c0:	f7ff ff4c 	bl	800315c <onewire_delay_us>
-		onewire_write_high();
- 80032c4:	f7ff ffae 	bl	8003224 <onewire_write_high>
-		onewire_delay_us(ONEWIRE_DELAY_B); // 64us
- 80032c8:	2040      	movs	r0, #64	@ 0x40
- 80032ca:	f7ff ff47 	bl	800315c <onewire_delay_us>
-		onewire_write_low();
-		onewire_delay_us(ONEWIRE_DELAY_C); // 60us
-		onewire_write_high();
-		onewire_delay_us(ONEWIRE_DELAY_D); // 10us
-	}
-}
- 80032ce:	e009      	b.n	80032e4 <onewire_write_bit+0x42>
-		onewire_write_low();
- 80032d0:	f7ff ff9b 	bl	800320a <onewire_write_low>
-		onewire_delay_us(ONEWIRE_DELAY_C); // 60us
- 80032d4:	203c      	movs	r0, #60	@ 0x3c
- 80032d6:	f7ff ff41 	bl	800315c <onewire_delay_us>
-		onewire_write_high();
- 80032da:	f7ff ffa3 	bl	8003224 <onewire_write_high>
-		onewire_delay_us(ONEWIRE_DELAY_D); // 10us
- 80032de:	200a      	movs	r0, #10
- 80032e0:	f7ff ff3c 	bl	800315c <onewire_delay_us>
-}
- 80032e4:	46c0      	nop			@ (mov r8, r8)
- 80032e6:	46bd      	mov	sp, r7
- 80032e8:	b002      	add	sp, #8
- 80032ea:	bd80      	pop	{r7, pc}
-
-080032ec <onewire_read_bit_slot>:
-
-uint8_t onewire_read_bit_slot(void)
-{
- 80032ec:	b590      	push	{r4, r7, lr}
- 80032ee:	b083      	sub	sp, #12
- 80032f0:	af00      	add	r7, sp, #0
-	uint8_t bit;
-
-	onewire_set_output();
- 80032f2:	f7ff ff49 	bl	8003188 <onewire_set_output>
-	onewire_write_low();
- 80032f6:	f7ff ff88 	bl	800320a <onewire_write_low>
-	onewire_delay_us(ONEWIRE_DELAY_A); // 6us
- 80032fa:	2006      	movs	r0, #6
- 80032fc:	f7ff ff2e 	bl	800315c <onewire_delay_us>
-
-	onewire_set_input();
- 8003300:	f7ff ff64 	bl	80031cc <onewire_set_input>
-	onewire_delay_us(ONEWIRE_DELAY_E); // 9us
- 8003304:	2009      	movs	r0, #9
- 8003306:	f7ff ff29 	bl	800315c <onewire_delay_us>
-
-	bit = onewire_read_bit();
- 800330a:	1dfc      	adds	r4, r7, #7
- 800330c:	f7ff ff97 	bl	800323e <onewire_read_bit>
- 8003310:	0003      	movs	r3, r0
- 8003312:	7023      	strb	r3, [r4, #0]
-
-	onewire_delay_us(ONEWIRE_DELAY_F); // 55us
- 8003314:	2037      	movs	r0, #55	@ 0x37
- 8003316:	f7ff ff21 	bl	800315c <onewire_delay_us>
-
-	return bit;
- 800331a:	1dfb      	adds	r3, r7, #7
- 800331c:	781b      	ldrb	r3, [r3, #0]
-}
- 800331e:	0018      	movs	r0, r3
- 8003320:	46bd      	mov	sp, r7
- 8003322:	b003      	add	sp, #12
- 8003324:	bd90      	pop	{r4, r7, pc}
-
-08003326 <onewire_write_byte>:
-
-void onewire_write_byte(uint8_t byte)
-{
- 8003326:	b580      	push	{r7, lr}
- 8003328:	b084      	sub	sp, #16
- 800332a:	af00      	add	r7, sp, #0
- 800332c:	0002      	movs	r2, r0
- 800332e:	1dfb      	adds	r3, r7, #7
- 8003330:	701a      	strb	r2, [r3, #0]
-	for (int i = 0; i < 8; i++)
- 8003332:	2300      	movs	r3, #0
- 8003334:	60fb      	str	r3, [r7, #12]
- 8003336:	e00f      	b.n	8003358 <onewire_write_byte+0x32>
-	{
-		onewire_write_bit(byte & 0x01);
- 8003338:	1dfb      	adds	r3, r7, #7
- 800333a:	781b      	ldrb	r3, [r3, #0]
- 800333c:	2201      	movs	r2, #1
- 800333e:	4013      	ands	r3, r2
- 8003340:	b2db      	uxtb	r3, r3
- 8003342:	0018      	movs	r0, r3
- 8003344:	f7ff ffad 	bl	80032a2 <onewire_write_bit>
-		byte >>= 1;
- 8003348:	1dfb      	adds	r3, r7, #7
- 800334a:	1dfa      	adds	r2, r7, #7
- 800334c:	7812      	ldrb	r2, [r2, #0]
- 800334e:	0852      	lsrs	r2, r2, #1
- 8003350:	701a      	strb	r2, [r3, #0]
-	for (int i = 0; i < 8; i++)
- 8003352:	68fb      	ldr	r3, [r7, #12]
- 8003354:	3301      	adds	r3, #1
- 8003356:	60fb      	str	r3, [r7, #12]
- 8003358:	68fb      	ldr	r3, [r7, #12]
- 800335a:	2b07      	cmp	r3, #7
- 800335c:	ddec      	ble.n	8003338 <onewire_write_byte+0x12>
-	}
-}
- 800335e:	46c0      	nop			@ (mov r8, r8)
- 8003360:	46c0      	nop			@ (mov r8, r8)
- 8003362:	46bd      	mov	sp, r7
- 8003364:	b004      	add	sp, #16
- 8003366:	bd80      	pop	{r7, pc}
-
-08003368 <onewire_read_byte>:
-
-uint8_t onewire_read_byte(void)
-{
- 8003368:	b580      	push	{r7, lr}
- 800336a:	b082      	sub	sp, #8
- 800336c:	af00      	add	r7, sp, #0
-	uint8_t byte = 0;
- 800336e:	1dfb      	adds	r3, r7, #7
- 8003370:	2200      	movs	r2, #0
- 8003372:	701a      	strb	r2, [r3, #0]
-	for (int i = 0; i < 8; i++)
- 8003374:	2300      	movs	r3, #0
- 8003376:	603b      	str	r3, [r7, #0]
- 8003378:	e012      	b.n	80033a0 <onewire_read_byte+0x38>
-	{
-		byte >>= 1;
- 800337a:	1dfb      	adds	r3, r7, #7
- 800337c:	1dfa      	adds	r2, r7, #7
- 800337e:	7812      	ldrb	r2, [r2, #0]
- 8003380:	0852      	lsrs	r2, r2, #1
- 8003382:	701a      	strb	r2, [r3, #0]
-		if (onewire_read_bit_slot())
- 8003384:	f7ff ffb2 	bl	80032ec <onewire_read_bit_slot>
- 8003388:	1e03      	subs	r3, r0, #0
- 800338a:	d006      	beq.n	800339a <onewire_read_byte+0x32>
-		{
-			byte |= 0x80;
- 800338c:	1dfb      	adds	r3, r7, #7
- 800338e:	1dfa      	adds	r2, r7, #7
- 8003390:	7812      	ldrb	r2, [r2, #0]
- 8003392:	2180      	movs	r1, #128	@ 0x80
- 8003394:	4249      	negs	r1, r1
- 8003396:	430a      	orrs	r2, r1
- 8003398:	701a      	strb	r2, [r3, #0]
-	for (int i = 0; i < 8; i++)
- 800339a:	683b      	ldr	r3, [r7, #0]
- 800339c:	3301      	adds	r3, #1
- 800339e:	603b      	str	r3, [r7, #0]
- 80033a0:	683b      	ldr	r3, [r7, #0]
- 80033a2:	2b07      	cmp	r3, #7
- 80033a4:	dde9      	ble.n	800337a <onewire_read_byte+0x12>
-		}
-	}
-	return byte;
- 80033a6:	1dfb      	adds	r3, r7, #7
- 80033a8:	781b      	ldrb	r3, [r3, #0]
-}
- 80033aa:	0018      	movs	r0, r3
- 80033ac:	46bd      	mov	sp, r7
- 80033ae:	b002      	add	sp, #8
- 80033b0:	bd80      	pop	{r7, pc}
-
-080033b2 <read_floor_address>:
-
-// Read floor address from DS2431 EEPROM
-uint8_t read_floor_address(void)
-{
- 80033b2:	b590      	push	{r4, r7, lr}
- 80033b4:	b083      	sub	sp, #12
- 80033b6:	af00      	add	r7, sp, #0
+ 800079a:	a805      	add	r0, sp, #20
+  __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_1);
+ 800079c:	6813      	ldr	r3, [r2, #0]
+ 800079e:	43b3      	bics	r3, r6
+ 80007a0:	432b      	orrs	r3, r5
+ 80007a2:	6013      	str	r3, [r2, #0]
+  RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
+ 80007a4:	2302      	movs	r3, #2
+ 80007a6:	9305      	str	r3, [sp, #20]
+  RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ 80007a8:	33fe      	adds	r3, #254	@ 0xfe
+ 80007aa:	9308      	str	r3, [sp, #32]
+  RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1;
+ 80007ac:	2300      	movs	r3, #0
+ 80007ae:	9309      	str	r3, [sp, #36]	@ 0x24
+  RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ 80007b0:	3340      	adds	r3, #64	@ 0x40
+ 80007b2:	930a      	str	r3, [sp, #40]	@ 0x28
+  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
+ 80007b4:	f002 fdca 	bl	800334c <HAL_RCC_OscConfig>
+ 80007b8:	2800      	cmp	r0, #0
+ 80007ba:	d001      	beq.n	80007c0 <SystemClock_Config+0x44>
   \details Disables IRQ interrupts by setting special-purpose register PRIMASK.
            Can only be executed in Privileged modes.
  */
 __STATIC_FORCEINLINE void __disable_irq(void)
 {
   __ASM volatile ("cpsid i" : : : "memory");
- 80033b8:	b672      	cpsid	i
-}
- 80033ba:	46c0      	nop			@ (mov r8, r8)
-	// Disable interrupts for timing-critical OneWire
-	__disable_irq();
-
-	if (!onewire_reset())
- 80033bc:	f7ff ff4d 	bl	800325a <onewire_reset>
- 80033c0:	1e03      	subs	r3, r0, #0
- 80033c2:	d103      	bne.n	80033cc <read_floor_address+0x1a>
-  __ASM volatile ("cpsie i" : : : "memory");
- 80033c4:	b662      	cpsie	i
-}
- 80033c6:	46c0      	nop			@ (mov r8, r8)
-	{
-		__enable_irq();
-		return FLOOR_ADDRESS_NOT_DETECTED;
- 80033c8:	23ff      	movs	r3, #255	@ 0xff
- 80033ca:	e014      	b.n	80033f6 <read_floor_address+0x44>
-	}
-
-	// Skip ROM (only one device on bus)
-	onewire_write_byte(DS2431_SKIP_ROM);
- 80033cc:	20cc      	movs	r0, #204	@ 0xcc
- 80033ce:	f7ff ffaa 	bl	8003326 <onewire_write_byte>
-
-	// Read Memory command
-	onewire_write_byte(DS2431_READ_MEMORY);
- 80033d2:	20f0      	movs	r0, #240	@ 0xf0
- 80033d4:	f7ff ffa7 	bl	8003326 <onewire_write_byte>
-
-	// Address (2 bytes, LSB first)
-	onewire_write_byte(FLOOR_ADDRESS_LOCATION & 0xFF);
- 80033d8:	2000      	movs	r0, #0
- 80033da:	f7ff ffa4 	bl	8003326 <onewire_write_byte>
-	onewire_write_byte((FLOOR_ADDRESS_LOCATION >> 8) & 0xFF);
- 80033de:	2000      	movs	r0, #0
- 80033e0:	f7ff ffa1 	bl	8003326 <onewire_write_byte>
-
-	// Read the data byte
-	uint8_t address = onewire_read_byte();
- 80033e4:	1dfc      	adds	r4, r7, #7
- 80033e6:	f7ff ffbf 	bl	8003368 <onewire_read_byte>
- 80033ea:	0003      	movs	r3, r0
- 80033ec:	7023      	strb	r3, [r4, #0]
-  __ASM volatile ("cpsie i" : : : "memory");
- 80033ee:	b662      	cpsie	i
-}
- 80033f0:	46c0      	nop			@ (mov r8, r8)
-
-	__enable_irq();
-
-	return address;
- 80033f2:	1dfb      	adds	r3, r7, #7
- 80033f4:	781b      	ldrb	r3, [r3, #0]
-}
- 80033f6:	0018      	movs	r0, r3
- 80033f8:	46bd      	mov	sp, r7
- 80033fa:	b003      	add	sp, #12
- 80033fc:	bd90      	pop	{r4, r7, pc}
-
-080033fe <write_floor_address>:
-
-// Write floor address to DS2431 EEPROM
-uint8_t write_floor_address(uint8_t address)
-{
- 80033fe:	b5b0      	push	{r4, r5, r7, lr}
- 8003400:	b086      	sub	sp, #24
- 8003402:	af00      	add	r7, sp, #0
- 8003404:	0002      	movs	r2, r0
- 8003406:	1dfb      	adds	r3, r7, #7
- 8003408:	701a      	strb	r2, [r3, #0]
-  __ASM volatile ("cpsid i" : : : "memory");
- 800340a:	b672      	cpsid	i
-}
- 800340c:	46c0      	nop			@ (mov r8, r8)
-	// Disable interrupts for timing-critical OneWire
-	__disable_irq();
-
-	if (!onewire_reset())
- 800340e:	f7ff ff24 	bl	800325a <onewire_reset>
- 8003412:	1e03      	subs	r3, r0, #0
- 8003414:	d103      	bne.n	800341e <write_floor_address+0x20>
-  __ASM volatile ("cpsie i" : : : "memory");
- 8003416:	b662      	cpsie	i
-}
- 8003418:	46c0      	nop			@ (mov r8, r8)
-	{
-		__enable_irq();
-		return 0; // Device not present
- 800341a:	2300      	movs	r3, #0
- 800341c:	e08d      	b.n	800353a <write_floor_address+0x13c>
-	}
-
-	// Skip ROM
-	onewire_write_byte(DS2431_SKIP_ROM);
- 800341e:	20cc      	movs	r0, #204	@ 0xcc
- 8003420:	f7ff ff81 	bl	8003326 <onewire_write_byte>
-
-	// Write Scratchpad command
-	onewire_write_byte(DS2431_WRITE_SCRATCHPAD);
- 8003424:	200f      	movs	r0, #15
- 8003426:	f7ff ff7e 	bl	8003326 <onewire_write_byte>
-
-	// Address (2 bytes, LSB first)
-	onewire_write_byte(FLOOR_ADDRESS_LOCATION & 0xFF);
- 800342a:	2000      	movs	r0, #0
- 800342c:	f7ff ff7b 	bl	8003326 <onewire_write_byte>
-	onewire_write_byte((FLOOR_ADDRESS_LOCATION >> 8) & 0xFF);
- 8003430:	2000      	movs	r0, #0
- 8003432:	f7ff ff78 	bl	8003326 <onewire_write_byte>
-
-	// Write the data (8 bytes for DS2431, we only need 1)
-	onewire_write_byte(address);
- 8003436:	1dfb      	adds	r3, r7, #7
- 8003438:	781b      	ldrb	r3, [r3, #0]
- 800343a:	0018      	movs	r0, r3
- 800343c:	f7ff ff73 	bl	8003326 <onewire_write_byte>
-	for (int i = 1; i < 8; i++)
- 8003440:	2301      	movs	r3, #1
- 8003442:	617b      	str	r3, [r7, #20]
- 8003444:	e005      	b.n	8003452 <write_floor_address+0x54>
-	{
-		onewire_write_byte(0xFF); // Pad with 0xFF
- 8003446:	20ff      	movs	r0, #255	@ 0xff
- 8003448:	f7ff ff6d 	bl	8003326 <onewire_write_byte>
-	for (int i = 1; i < 8; i++)
- 800344c:	697b      	ldr	r3, [r7, #20]
- 800344e:	3301      	adds	r3, #1
- 8003450:	617b      	str	r3, [r7, #20]
- 8003452:	697b      	ldr	r3, [r7, #20]
- 8003454:	2b07      	cmp	r3, #7
- 8003456:	ddf6      	ble.n	8003446 <write_floor_address+0x48>
-	}
-
-	// Small delay
-	onewire_delay_us(100);
- 8003458:	2064      	movs	r0, #100	@ 0x64
- 800345a:	f7ff fe7f 	bl	800315c <onewire_delay_us>
-
-	// Reset for next command
-	if (!onewire_reset())
- 800345e:	f7ff fefc 	bl	800325a <onewire_reset>
- 8003462:	1e03      	subs	r3, r0, #0
- 8003464:	d103      	bne.n	800346e <write_floor_address+0x70>
-  __ASM volatile ("cpsie i" : : : "memory");
- 8003466:	b662      	cpsie	i
-}
- 8003468:	46c0      	nop			@ (mov r8, r8)
-	{
-		__enable_irq();
-		return 0;
- 800346a:	2300      	movs	r3, #0
- 800346c:	e065      	b.n	800353a <write_floor_address+0x13c>
-	}
-
-	// Skip ROM
-	onewire_write_byte(DS2431_SKIP_ROM);
- 800346e:	20cc      	movs	r0, #204	@ 0xcc
- 8003470:	f7ff ff59 	bl	8003326 <onewire_write_byte>
-
-	// Read Scratchpad to get authorization bytes
-	onewire_write_byte(DS2431_READ_SCRATCHPAD);
- 8003474:	20aa      	movs	r0, #170	@ 0xaa
- 8003476:	f7ff ff56 	bl	8003326 <onewire_write_byte>
-
-	uint8_t ta1 = onewire_read_byte(); // Target address 1
- 800347a:	230f      	movs	r3, #15
- 800347c:	18fc      	adds	r4, r7, r3
- 800347e:	f7ff ff73 	bl	8003368 <onewire_read_byte>
- 8003482:	0003      	movs	r3, r0
- 8003484:	7023      	strb	r3, [r4, #0]
-	uint8_t ta2 = onewire_read_byte(); // Target address 2
- 8003486:	230e      	movs	r3, #14
- 8003488:	18fc      	adds	r4, r7, r3
- 800348a:	f7ff ff6d 	bl	8003368 <onewire_read_byte>
- 800348e:	0003      	movs	r3, r0
- 8003490:	7023      	strb	r3, [r4, #0]
-	uint8_t es = onewire_read_byte();  // E/S register
- 8003492:	230d      	movs	r3, #13
- 8003494:	18fc      	adds	r4, r7, r3
- 8003496:	f7ff ff67 	bl	8003368 <onewire_read_byte>
- 800349a:	0003      	movs	r3, r0
- 800349c:	7023      	strb	r3, [r4, #0]
-
-	// Read back data to verify (8 bytes)
-	uint8_t verify = onewire_read_byte();
- 800349e:	250c      	movs	r5, #12
- 80034a0:	197c      	adds	r4, r7, r5
- 80034a2:	f7ff ff61 	bl	8003368 <onewire_read_byte>
- 80034a6:	0003      	movs	r3, r0
- 80034a8:	7023      	strb	r3, [r4, #0]
-	if (verify != address)
- 80034aa:	197a      	adds	r2, r7, r5
- 80034ac:	1dfb      	adds	r3, r7, #7
- 80034ae:	7812      	ldrb	r2, [r2, #0]
- 80034b0:	781b      	ldrb	r3, [r3, #0]
- 80034b2:	429a      	cmp	r2, r3
- 80034b4:	d003      	beq.n	80034be <write_floor_address+0xc0>
-  __ASM volatile ("cpsie i" : : : "memory");
- 80034b6:	b662      	cpsie	i
-}
- 80034b8:	46c0      	nop			@ (mov r8, r8)
-	{
-		__enable_irq();
-		return 0; // Scratchpad write failed
- 80034ba:	2300      	movs	r3, #0
- 80034bc:	e03d      	b.n	800353a <write_floor_address+0x13c>
-	}
-
-	// Skip remaining bytes
-	for (int i = 1; i < 8; i++)
- 80034be:	2301      	movs	r3, #1
- 80034c0:	613b      	str	r3, [r7, #16]
- 80034c2:	e004      	b.n	80034ce <write_floor_address+0xd0>
-	{
-		onewire_read_byte();
- 80034c4:	f7ff ff50 	bl	8003368 <onewire_read_byte>
-	for (int i = 1; i < 8; i++)
- 80034c8:	693b      	ldr	r3, [r7, #16]
- 80034ca:	3301      	adds	r3, #1
- 80034cc:	613b      	str	r3, [r7, #16]
- 80034ce:	693b      	ldr	r3, [r7, #16]
- 80034d0:	2b07      	cmp	r3, #7
- 80034d2:	ddf7      	ble.n	80034c4 <write_floor_address+0xc6>
-	}
-
-	// Reset for copy command
-	if (!onewire_reset())
- 80034d4:	f7ff fec1 	bl	800325a <onewire_reset>
- 80034d8:	1e03      	subs	r3, r0, #0
- 80034da:	d103      	bne.n	80034e4 <write_floor_address+0xe6>
-  __ASM volatile ("cpsie i" : : : "memory");
- 80034dc:	b662      	cpsie	i
-}
- 80034de:	46c0      	nop			@ (mov r8, r8)
-	{
-		__enable_irq();
-		return 0;
- 80034e0:	2300      	movs	r3, #0
- 80034e2:	e02a      	b.n	800353a <write_floor_address+0x13c>
-	}
-
-	// Skip ROM
-	onewire_write_byte(DS2431_SKIP_ROM);
- 80034e4:	20cc      	movs	r0, #204	@ 0xcc
- 80034e6:	f7ff ff1e 	bl	8003326 <onewire_write_byte>
-
-	// Copy Scratchpad command
-	onewire_write_byte(DS2431_COPY_SCRATCHPAD);
- 80034ea:	2055      	movs	r0, #85	@ 0x55
- 80034ec:	f7ff ff1b 	bl	8003326 <onewire_write_byte>
-
-	// Send authorization bytes
-	onewire_write_byte(ta1);
- 80034f0:	230f      	movs	r3, #15
- 80034f2:	18fb      	adds	r3, r7, r3
- 80034f4:	781b      	ldrb	r3, [r3, #0]
- 80034f6:	0018      	movs	r0, r3
- 80034f8:	f7ff ff15 	bl	8003326 <onewire_write_byte>
-	onewire_write_byte(ta2);
- 80034fc:	230e      	movs	r3, #14
- 80034fe:	18fb      	adds	r3, r7, r3
- 8003500:	781b      	ldrb	r3, [r3, #0]
- 8003502:	0018      	movs	r0, r3
- 8003504:	f7ff ff0f 	bl	8003326 <onewire_write_byte>
-	onewire_write_byte(es);
- 8003508:	230d      	movs	r3, #13
- 800350a:	18fb      	adds	r3, r7, r3
- 800350c:	781b      	ldrb	r3, [r3, #0]
- 800350e:	0018      	movs	r0, r3
- 8003510:	f7ff ff09 	bl	8003326 <onewire_write_byte>
-  __ASM volatile ("cpsie i" : : : "memory");
- 8003514:	b662      	cpsie	i
-}
- 8003516:	46c0      	nop			@ (mov r8, r8)
-
-	__enable_irq();
-
-	// Wait for copy to complete (10ms typical for EEPROM)
-	HAL_Delay(15);
- 8003518:	200f      	movs	r0, #15
- 800351a:	f000 fde7 	bl	80040ec <HAL_Delay>
-
-	// Verify by reading back
-	uint8_t read_back = read_floor_address();
- 800351e:	250b      	movs	r5, #11
- 8003520:	197c      	adds	r4, r7, r5
- 8003522:	f7ff ff46 	bl	80033b2 <read_floor_address>
- 8003526:	0003      	movs	r3, r0
- 8003528:	7023      	strb	r3, [r4, #0]
-	return (read_back == address) ? 1 : 0;
- 800352a:	197a      	adds	r2, r7, r5
- 800352c:	1dfb      	adds	r3, r7, #7
- 800352e:	7812      	ldrb	r2, [r2, #0]
- 8003530:	781b      	ldrb	r3, [r3, #0]
- 8003532:	1ad3      	subs	r3, r2, r3
- 8003534:	425a      	negs	r2, r3
- 8003536:	4153      	adcs	r3, r2
- 8003538:	b2db      	uxtb	r3, r3
-}
- 800353a:	0018      	movs	r0, r3
- 800353c:	46bd      	mov	sp, r7
- 800353e:	b006      	add	sp, #24
- 8003540:	bdb0      	pop	{r4, r5, r7, pc}
-
-08003542 <debug_itoa>:
-// Debug Output Functions (lightweight, no printf/snprintf)
-// ============================================================================
-
-// Convert int32 to decimal string, returns length written
-uint8_t debug_itoa(int32_t val, char *buf)
-{
- 8003542:	b580      	push	{r7, lr}
- 8003544:	b086      	sub	sp, #24
- 8003546:	af00      	add	r7, sp, #0
- 8003548:	6078      	str	r0, [r7, #4]
- 800354a:	6039      	str	r1, [r7, #0]
-	char tmp[12];
-	uint8_t i = 0, len = 0;
- 800354c:	2317      	movs	r3, #23
- 800354e:	18fb      	adds	r3, r7, r3
- 8003550:	2200      	movs	r2, #0
- 8003552:	701a      	strb	r2, [r3, #0]
- 8003554:	2316      	movs	r3, #22
- 8003556:	18fb      	adds	r3, r7, r3
- 8003558:	2200      	movs	r2, #0
- 800355a:	701a      	strb	r2, [r3, #0]
-	uint8_t neg = 0;
- 800355c:	2115      	movs	r1, #21
- 800355e:	187b      	adds	r3, r7, r1
- 8003560:	2200      	movs	r2, #0
- 8003562:	701a      	strb	r2, [r3, #0]
-
-	if (val < 0) { neg = 1; val = -val; }
- 8003564:	687b      	ldr	r3, [r7, #4]
- 8003566:	2b00      	cmp	r3, #0
- 8003568:	da05      	bge.n	8003576 <debug_itoa+0x34>
- 800356a:	187b      	adds	r3, r7, r1
- 800356c:	2201      	movs	r2, #1
- 800356e:	701a      	strb	r2, [r3, #0]
- 8003570:	687b      	ldr	r3, [r7, #4]
- 8003572:	425b      	negs	r3, r3
- 8003574:	607b      	str	r3, [r7, #4]
-	if (val == 0) { tmp[i++] = '0'; }
- 8003576:	687b      	ldr	r3, [r7, #4]
- 8003578:	2b00      	cmp	r3, #0
- 800357a:	d126      	bne.n	80035ca <debug_itoa+0x88>
- 800357c:	2217      	movs	r2, #23
- 800357e:	18bb      	adds	r3, r7, r2
- 8003580:	781b      	ldrb	r3, [r3, #0]
- 8003582:	18ba      	adds	r2, r7, r2
- 8003584:	1c59      	adds	r1, r3, #1
- 8003586:	7011      	strb	r1, [r2, #0]
- 8003588:	001a      	movs	r2, r3
- 800358a:	2308      	movs	r3, #8
- 800358c:	18fb      	adds	r3, r7, r3
- 800358e:	2130      	movs	r1, #48	@ 0x30
- 8003590:	5499      	strb	r1, [r3, r2]
- 8003592:	e01d      	b.n	80035d0 <debug_itoa+0x8e>
-	else { while (val > 0) { tmp[i++] = '0' + (val % 10); val /= 10; } }
- 8003594:	687b      	ldr	r3, [r7, #4]
- 8003596:	210a      	movs	r1, #10
- 8003598:	0018      	movs	r0, r3
- 800359a:	f7fc ff25 	bl	80003e8 <__aeabi_idivmod>
- 800359e:	000b      	movs	r3, r1
- 80035a0:	b2da      	uxtb	r2, r3
- 80035a2:	2117      	movs	r1, #23
- 80035a4:	187b      	adds	r3, r7, r1
- 80035a6:	781b      	ldrb	r3, [r3, #0]
- 80035a8:	1879      	adds	r1, r7, r1
- 80035aa:	1c58      	adds	r0, r3, #1
- 80035ac:	7008      	strb	r0, [r1, #0]
- 80035ae:	0019      	movs	r1, r3
- 80035b0:	0013      	movs	r3, r2
- 80035b2:	3330      	adds	r3, #48	@ 0x30
- 80035b4:	b2da      	uxtb	r2, r3
- 80035b6:	2308      	movs	r3, #8
- 80035b8:	18fb      	adds	r3, r7, r3
- 80035ba:	545a      	strb	r2, [r3, r1]
- 80035bc:	687b      	ldr	r3, [r7, #4]
- 80035be:	210a      	movs	r1, #10
- 80035c0:	0018      	movs	r0, r3
- 80035c2:	f7fc fe2b 	bl	800021c <__divsi3>
- 80035c6:	0003      	movs	r3, r0
- 80035c8:	607b      	str	r3, [r7, #4]
- 80035ca:	687b      	ldr	r3, [r7, #4]
- 80035cc:	2b00      	cmp	r3, #0
- 80035ce:	dce1      	bgt.n	8003594 <debug_itoa+0x52>
-
-	if (neg) { *buf++ = '-'; len++; }
- 80035d0:	2315      	movs	r3, #21
- 80035d2:	18fb      	adds	r3, r7, r3
- 80035d4:	781b      	ldrb	r3, [r3, #0]
- 80035d6:	2b00      	cmp	r3, #0
- 80035d8:	d020      	beq.n	800361c <debug_itoa+0xda>
- 80035da:	683b      	ldr	r3, [r7, #0]
- 80035dc:	1c5a      	adds	r2, r3, #1
- 80035de:	603a      	str	r2, [r7, #0]
- 80035e0:	222d      	movs	r2, #45	@ 0x2d
- 80035e2:	701a      	strb	r2, [r3, #0]
- 80035e4:	2116      	movs	r1, #22
- 80035e6:	187b      	adds	r3, r7, r1
- 80035e8:	781a      	ldrb	r2, [r3, #0]
- 80035ea:	187b      	adds	r3, r7, r1
- 80035ec:	3201      	adds	r2, #1
- 80035ee:	701a      	strb	r2, [r3, #0]
-	while (i > 0) { *buf++ = tmp[--i]; len++; }
- 80035f0:	e014      	b.n	800361c <debug_itoa+0xda>
- 80035f2:	2117      	movs	r1, #23
- 80035f4:	187b      	adds	r3, r7, r1
- 80035f6:	187a      	adds	r2, r7, r1
- 80035f8:	7812      	ldrb	r2, [r2, #0]
- 80035fa:	3a01      	subs	r2, #1
- 80035fc:	701a      	strb	r2, [r3, #0]
- 80035fe:	187b      	adds	r3, r7, r1
- 8003600:	781a      	ldrb	r2, [r3, #0]
- 8003602:	683b      	ldr	r3, [r7, #0]
- 8003604:	1c59      	adds	r1, r3, #1
- 8003606:	6039      	str	r1, [r7, #0]
- 8003608:	2108      	movs	r1, #8
- 800360a:	1879      	adds	r1, r7, r1
- 800360c:	5c8a      	ldrb	r2, [r1, r2]
- 800360e:	701a      	strb	r2, [r3, #0]
- 8003610:	2116      	movs	r1, #22
- 8003612:	187b      	adds	r3, r7, r1
- 8003614:	781a      	ldrb	r2, [r3, #0]
- 8003616:	187b      	adds	r3, r7, r1
- 8003618:	3201      	adds	r2, #1
- 800361a:	701a      	strb	r2, [r3, #0]
- 800361c:	2317      	movs	r3, #23
- 800361e:	18fb      	adds	r3, r7, r3
- 8003620:	781b      	ldrb	r3, [r3, #0]
- 8003622:	2b00      	cmp	r3, #0
- 8003624:	d1e5      	bne.n	80035f2 <debug_itoa+0xb0>
-	return len;
- 8003626:	2316      	movs	r3, #22
- 8003628:	18fb      	adds	r3, r7, r3
- 800362a:	781b      	ldrb	r3, [r3, #0]
-}
- 800362c:	0018      	movs	r0, r3
- 800362e:	46bd      	mov	sp, r7
- 8003630:	b006      	add	sp, #24
- 8003632:	bd80      	pop	{r7, pc}
-
-08003634 <debug_hex8>:
-
-// Convert uint8 to 2-digit hex, returns 2
-uint8_t debug_hex8(uint8_t val, char *buf)
-{
- 8003634:	b5b0      	push	{r4, r5, r7, lr}
- 8003636:	b088      	sub	sp, #32
- 8003638:	af00      	add	r7, sp, #0
- 800363a:	0002      	movs	r2, r0
- 800363c:	6039      	str	r1, [r7, #0]
- 800363e:	1dfb      	adds	r3, r7, #7
- 8003640:	701a      	strb	r2, [r3, #0]
-	const char hex[] = "0123456789ABCDEF";
- 8003642:	250c      	movs	r5, #12
- 8003644:	197b      	adds	r3, r7, r5
- 8003646:	4a10      	ldr	r2, [pc, #64]	@ (8003688 <debug_hex8+0x54>)
- 8003648:	ca13      	ldmia	r2!, {r0, r1, r4}
- 800364a:	c313      	stmia	r3!, {r0, r1, r4}
- 800364c:	6811      	ldr	r1, [r2, #0]
- 800364e:	6019      	str	r1, [r3, #0]
- 8003650:	7912      	ldrb	r2, [r2, #4]
- 8003652:	711a      	strb	r2, [r3, #4]
-	buf[0] = hex[(val >> 4) & 0x0F];
- 8003654:	1dfb      	adds	r3, r7, #7
- 8003656:	781b      	ldrb	r3, [r3, #0]
- 8003658:	091b      	lsrs	r3, r3, #4
- 800365a:	b2db      	uxtb	r3, r3
- 800365c:	001a      	movs	r2, r3
- 800365e:	230f      	movs	r3, #15
- 8003660:	4013      	ands	r3, r2
- 8003662:	197a      	adds	r2, r7, r5
- 8003664:	5cd2      	ldrb	r2, [r2, r3]
- 8003666:	683b      	ldr	r3, [r7, #0]
- 8003668:	701a      	strb	r2, [r3, #0]
-	buf[1] = hex[val & 0x0F];
- 800366a:	1dfb      	adds	r3, r7, #7
- 800366c:	781b      	ldrb	r3, [r3, #0]
- 800366e:	220f      	movs	r2, #15
- 8003670:	401a      	ands	r2, r3
- 8003672:	683b      	ldr	r3, [r7, #0]
- 8003674:	3301      	adds	r3, #1
- 8003676:	1979      	adds	r1, r7, r5
- 8003678:	5c8a      	ldrb	r2, [r1, r2]
- 800367a:	701a      	strb	r2, [r3, #0]
-	return 2;
- 800367c:	2302      	movs	r3, #2
-}
- 800367e:	0018      	movs	r0, r3
- 8003680:	46bd      	mov	sp, r7
- 8003682:	b008      	add	sp, #32
- 8003684:	bdb0      	pop	{r4, r5, r7, pc}
- 8003686:	46c0      	nop			@ (mov r8, r8)
- 8003688:	08007d38 	.word	0x08007d38
-
-0800368c <debug_output>:
-
-void debug_output(void)
-{
- 800368c:	b580      	push	{r7, lr}
- 800368e:	b082      	sub	sp, #8
- 8003690:	af00      	add	r7, sp, #0
-	if (!debug_enabled) return;
- 8003692:	4bb6      	ldr	r3, [pc, #728]	@ (800396c <debug_output+0x2e0>)
- 8003694:	781b      	ldrb	r3, [r3, #0]
- 8003696:	2b00      	cmp	r3, #0
- 8003698:	d100      	bne.n	800369c <debug_output+0x10>
- 800369a:	e161      	b.n	8003960 <debug_output+0x2d4>
-
-	uint32_t now = HAL_GetTick();
- 800369c:	f000 fd1c 	bl	80040d8 <HAL_GetTick>
- 80036a0:	0003      	movs	r3, r0
- 80036a2:	607b      	str	r3, [r7, #4]
-	if ((now - last_debug_output_time) < DEBUG_OUTPUT_INTERVAL_MS) return;
- 80036a4:	4bb2      	ldr	r3, [pc, #712]	@ (8003970 <debug_output+0x2e4>)
- 80036a6:	681b      	ldr	r3, [r3, #0]
- 80036a8:	687a      	ldr	r2, [r7, #4]
- 80036aa:	1ad3      	subs	r3, r2, r3
- 80036ac:	2b63      	cmp	r3, #99	@ 0x63
- 80036ae:	d800      	bhi.n	80036b2 <debug_output+0x26>
- 80036b0:	e158      	b.n	8003964 <debug_output+0x2d8>
-	last_debug_output_time = now;
- 80036b2:	4baf      	ldr	r3, [pc, #700]	@ (8003970 <debug_output+0x2e4>)
- 80036b4:	687a      	ldr	r2, [r7, #4]
- 80036b6:	601a      	str	r2, [r3, #0]
-
-	// Format: $P:pos:tgt:err,I:pid,S:state,F:flags,A:addr,D:drv*\r\n
-	char *p = debug_tx_buffer;
- 80036b8:	4bae      	ldr	r3, [pc, #696]	@ (8003974 <debug_output+0x2e8>)
- 80036ba:	603b      	str	r3, [r7, #0]
-
-	*p++ = '$'; *p++ = 'P'; *p++ = ':';
- 80036bc:	683b      	ldr	r3, [r7, #0]
- 80036be:	1c5a      	adds	r2, r3, #1
- 80036c0:	603a      	str	r2, [r7, #0]
- 80036c2:	2224      	movs	r2, #36	@ 0x24
- 80036c4:	701a      	strb	r2, [r3, #0]
- 80036c6:	683b      	ldr	r3, [r7, #0]
- 80036c8:	1c5a      	adds	r2, r3, #1
- 80036ca:	603a      	str	r2, [r7, #0]
- 80036cc:	2250      	movs	r2, #80	@ 0x50
- 80036ce:	701a      	strb	r2, [r3, #0]
- 80036d0:	683b      	ldr	r3, [r7, #0]
- 80036d2:	1c5a      	adds	r2, r3, #1
- 80036d4:	603a      	str	r2, [r7, #0]
- 80036d6:	223a      	movs	r2, #58	@ 0x3a
- 80036d8:	701a      	strb	r2, [r3, #0]
-	p += debug_itoa(total_count, p);
- 80036da:	4ba7      	ldr	r3, [pc, #668]	@ (8003978 <debug_output+0x2ec>)
- 80036dc:	681b      	ldr	r3, [r3, #0]
- 80036de:	683a      	ldr	r2, [r7, #0]
- 80036e0:	0011      	movs	r1, r2
- 80036e2:	0018      	movs	r0, r3
- 80036e4:	f7ff ff2d 	bl	8003542 <debug_itoa>
- 80036e8:	0003      	movs	r3, r0
- 80036ea:	001a      	movs	r2, r3
- 80036ec:	683b      	ldr	r3, [r7, #0]
- 80036ee:	189b      	adds	r3, r3, r2
- 80036f0:	603b      	str	r3, [r7, #0]
-	*p++ = ':';
- 80036f2:	683b      	ldr	r3, [r7, #0]
- 80036f4:	1c5a      	adds	r2, r3, #1
- 80036f6:	603a      	str	r2, [r7, #0]
- 80036f8:	223a      	movs	r2, #58	@ 0x3a
- 80036fa:	701a      	strb	r2, [r3, #0]
-	p += debug_itoa(target_count, p);
- 80036fc:	4b9f      	ldr	r3, [pc, #636]	@ (800397c <debug_output+0x2f0>)
- 80036fe:	681b      	ldr	r3, [r3, #0]
- 8003700:	683a      	ldr	r2, [r7, #0]
- 8003702:	0011      	movs	r1, r2
- 8003704:	0018      	movs	r0, r3
- 8003706:	f7ff ff1c 	bl	8003542 <debug_itoa>
- 800370a:	0003      	movs	r3, r0
- 800370c:	001a      	movs	r2, r3
- 800370e:	683b      	ldr	r3, [r7, #0]
- 8003710:	189b      	adds	r3, r3, r2
- 8003712:	603b      	str	r3, [r7, #0]
-	*p++ = ':';
- 8003714:	683b      	ldr	r3, [r7, #0]
- 8003716:	1c5a      	adds	r2, r3, #1
- 8003718:	603a      	str	r2, [r7, #0]
- 800371a:	223a      	movs	r2, #58	@ 0x3a
- 800371c:	701a      	strb	r2, [r3, #0]
-	p += debug_itoa(target_count - total_count, p);
- 800371e:	4b97      	ldr	r3, [pc, #604]	@ (800397c <debug_output+0x2f0>)
- 8003720:	681a      	ldr	r2, [r3, #0]
- 8003722:	4b95      	ldr	r3, [pc, #596]	@ (8003978 <debug_output+0x2ec>)
- 8003724:	681b      	ldr	r3, [r3, #0]
- 8003726:	1ad3      	subs	r3, r2, r3
- 8003728:	683a      	ldr	r2, [r7, #0]
- 800372a:	0011      	movs	r1, r2
- 800372c:	0018      	movs	r0, r3
- 800372e:	f7ff ff08 	bl	8003542 <debug_itoa>
- 8003732:	0003      	movs	r3, r0
- 8003734:	001a      	movs	r2, r3
- 8003736:	683b      	ldr	r3, [r7, #0]
- 8003738:	189b      	adds	r3, r3, r2
- 800373a:	603b      	str	r3, [r7, #0]
-
-	*p++ = ','; *p++ = 'I'; *p++ = ':';
- 800373c:	683b      	ldr	r3, [r7, #0]
- 800373e:	1c5a      	adds	r2, r3, #1
- 8003740:	603a      	str	r2, [r7, #0]
- 8003742:	222c      	movs	r2, #44	@ 0x2c
- 8003744:	701a      	strb	r2, [r3, #0]
- 8003746:	683b      	ldr	r3, [r7, #0]
- 8003748:	1c5a      	adds	r2, r3, #1
- 800374a:	603a      	str	r2, [r7, #0]
- 800374c:	2249      	movs	r2, #73	@ 0x49
- 800374e:	701a      	strb	r2, [r3, #0]
- 8003750:	683b      	ldr	r3, [r7, #0]
- 8003752:	1c5a      	adds	r2, r3, #1
- 8003754:	603a      	str	r2, [r7, #0]
- 8003756:	223a      	movs	r2, #58	@ 0x3a
- 8003758:	701a      	strb	r2, [r3, #0]
-	p += debug_itoa(debug_pid_output, p);
- 800375a:	4b89      	ldr	r3, [pc, #548]	@ (8003980 <debug_output+0x2f4>)
- 800375c:	881b      	ldrh	r3, [r3, #0]
- 800375e:	b21b      	sxth	r3, r3
- 8003760:	001a      	movs	r2, r3
- 8003762:	683b      	ldr	r3, [r7, #0]
- 8003764:	0019      	movs	r1, r3
- 8003766:	0010      	movs	r0, r2
- 8003768:	f7ff feeb 	bl	8003542 <debug_itoa>
- 800376c:	0003      	movs	r3, r0
- 800376e:	001a      	movs	r2, r3
- 8003770:	683b      	ldr	r3, [r7, #0]
- 8003772:	189b      	adds	r3, r3, r2
- 8003774:	603b      	str	r3, [r7, #0]
-
-	*p++ = ','; *p++ = 'S'; *p++ = ':';
- 8003776:	683b      	ldr	r3, [r7, #0]
- 8003778:	1c5a      	adds	r2, r3, #1
- 800377a:	603a      	str	r2, [r7, #0]
- 800377c:	222c      	movs	r2, #44	@ 0x2c
- 800377e:	701a      	strb	r2, [r3, #0]
- 8003780:	683b      	ldr	r3, [r7, #0]
- 8003782:	1c5a      	adds	r2, r3, #1
- 8003784:	603a      	str	r2, [r7, #0]
- 8003786:	2253      	movs	r2, #83	@ 0x53
- 8003788:	701a      	strb	r2, [r3, #0]
- 800378a:	683b      	ldr	r3, [r7, #0]
- 800378c:	1c5a      	adds	r2, r3, #1
- 800378e:	603a      	str	r2, [r7, #0]
- 8003790:	223a      	movs	r2, #58	@ 0x3a
- 8003792:	701a      	strb	r2, [r3, #0]
-	*p++ = '0' + feed_state; // State as single digit 0-9
- 8003794:	4b7b      	ldr	r3, [pc, #492]	@ (8003984 <debug_output+0x2f8>)
- 8003796:	781b      	ldrb	r3, [r3, #0]
- 8003798:	b2da      	uxtb	r2, r3
- 800379a:	683b      	ldr	r3, [r7, #0]
- 800379c:	1c59      	adds	r1, r3, #1
- 800379e:	6039      	str	r1, [r7, #0]
- 80037a0:	3230      	adds	r2, #48	@ 0x30
- 80037a2:	b2d2      	uxtb	r2, r2
- 80037a4:	701a      	strb	r2, [r3, #0]
-
-	*p++ = ','; *p++ = 'F'; *p++ = ':';
- 80037a6:	683b      	ldr	r3, [r7, #0]
- 80037a8:	1c5a      	adds	r2, r3, #1
- 80037aa:	603a      	str	r2, [r7, #0]
- 80037ac:	222c      	movs	r2, #44	@ 0x2c
- 80037ae:	701a      	strb	r2, [r3, #0]
- 80037b0:	683b      	ldr	r3, [r7, #0]
- 80037b2:	1c5a      	adds	r2, r3, #1
- 80037b4:	603a      	str	r2, [r7, #0]
- 80037b6:	2246      	movs	r2, #70	@ 0x46
- 80037b8:	701a      	strb	r2, [r3, #0]
- 80037ba:	683b      	ldr	r3, [r7, #0]
- 80037bc:	1c5a      	adds	r2, r3, #1
- 80037be:	603a      	str	r2, [r7, #0]
- 80037c0:	223a      	movs	r2, #58	@ 0x3a
- 80037c2:	701a      	strb	r2, [r3, #0]
-	*p++ = '0' + is_initialized;
- 80037c4:	4b70      	ldr	r3, [pc, #448]	@ (8003988 <debug_output+0x2fc>)
- 80037c6:	781a      	ldrb	r2, [r3, #0]
- 80037c8:	683b      	ldr	r3, [r7, #0]
- 80037ca:	1c59      	adds	r1, r3, #1
- 80037cc:	6039      	str	r1, [r7, #0]
- 80037ce:	3230      	adds	r2, #48	@ 0x30
- 80037d0:	b2d2      	uxtb	r2, r2
- 80037d2:	701a      	strb	r2, [r3, #0]
-	*p++ = '0' + feed_in_progress;
- 80037d4:	4b6d      	ldr	r3, [pc, #436]	@ (800398c <debug_output+0x300>)
- 80037d6:	781b      	ldrb	r3, [r3, #0]
- 80037d8:	b2da      	uxtb	r2, r3
- 80037da:	683b      	ldr	r3, [r7, #0]
- 80037dc:	1c59      	adds	r1, r3, #1
- 80037de:	6039      	str	r1, [r7, #0]
- 80037e0:	3230      	adds	r2, #48	@ 0x30
- 80037e2:	b2d2      	uxtb	r2, r2
- 80037e4:	701a      	strb	r2, [r3, #0]
-	*p++ = '0' + beefy_tape;
- 80037e6:	4b6a      	ldr	r3, [pc, #424]	@ (8003990 <debug_output+0x304>)
- 80037e8:	781a      	ldrb	r2, [r3, #0]
- 80037ea:	683b      	ldr	r3, [r7, #0]
- 80037ec:	1c59      	adds	r1, r3, #1
- 80037ee:	6039      	str	r1, [r7, #0]
- 80037f0:	3230      	adds	r2, #48	@ 0x30
- 80037f2:	b2d2      	uxtb	r2, r2
- 80037f4:	701a      	strb	r2, [r3, #0]
-
-	*p++ = ','; *p++ = 'A'; *p++ = ':';
- 80037f6:	683b      	ldr	r3, [r7, #0]
- 80037f8:	1c5a      	adds	r2, r3, #1
- 80037fa:	603a      	str	r2, [r7, #0]
- 80037fc:	222c      	movs	r2, #44	@ 0x2c
- 80037fe:	701a      	strb	r2, [r3, #0]
- 8003800:	683b      	ldr	r3, [r7, #0]
- 8003802:	1c5a      	adds	r2, r3, #1
- 8003804:	603a      	str	r2, [r7, #0]
- 8003806:	2241      	movs	r2, #65	@ 0x41
- 8003808:	701a      	strb	r2, [r3, #0]
- 800380a:	683b      	ldr	r3, [r7, #0]
- 800380c:	1c5a      	adds	r2, r3, #1
- 800380e:	603a      	str	r2, [r7, #0]
- 8003810:	223a      	movs	r2, #58	@ 0x3a
- 8003812:	701a      	strb	r2, [r3, #0]
-	p += debug_hex8(my_address, p);
- 8003814:	4b5f      	ldr	r3, [pc, #380]	@ (8003994 <debug_output+0x308>)
- 8003816:	781b      	ldrb	r3, [r3, #0]
- 8003818:	683a      	ldr	r2, [r7, #0]
- 800381a:	0011      	movs	r1, r2
- 800381c:	0018      	movs	r0, r3
- 800381e:	f7ff ff09 	bl	8003634 <debug_hex8>
- 8003822:	0003      	movs	r3, r0
- 8003824:	001a      	movs	r2, r3
- 8003826:	683b      	ldr	r3, [r7, #0]
- 8003828:	189b      	adds	r3, r3, r2
- 800382a:	603b      	str	r3, [r7, #0]
-
-	*p++ = ','; *p++ = 'B'; *p++ = ':';
- 800382c:	683b      	ldr	r3, [r7, #0]
- 800382e:	1c5a      	adds	r2, r3, #1
- 8003830:	603a      	str	r2, [r7, #0]
- 8003832:	222c      	movs	r2, #44	@ 0x2c
- 8003834:	701a      	strb	r2, [r3, #0]
- 8003836:	683b      	ldr	r3, [r7, #0]
- 8003838:	1c5a      	adds	r2, r3, #1
- 800383a:	603a      	str	r2, [r7, #0]
- 800383c:	2242      	movs	r2, #66	@ 0x42
- 800383e:	701a      	strb	r2, [r3, #0]
- 8003840:	683b      	ldr	r3, [r7, #0]
- 8003842:	1c5a      	adds	r2, r3, #1
- 8003844:	603a      	str	r2, [r7, #0]
- 8003846:	223a      	movs	r2, #58	@ 0x3a
- 8003848:	701a      	strb	r2, [r3, #0]
-	*p++ = '0' + sw1_pressed;
- 800384a:	4b53      	ldr	r3, [pc, #332]	@ (8003998 <debug_output+0x30c>)
- 800384c:	781a      	ldrb	r2, [r3, #0]
- 800384e:	683b      	ldr	r3, [r7, #0]
- 8003850:	1c59      	adds	r1, r3, #1
- 8003852:	6039      	str	r1, [r7, #0]
- 8003854:	3230      	adds	r2, #48	@ 0x30
- 8003856:	b2d2      	uxtb	r2, r2
- 8003858:	701a      	strb	r2, [r3, #0]
-	*p++ = '0' + sw2_pressed;
- 800385a:	4b50      	ldr	r3, [pc, #320]	@ (800399c <debug_output+0x310>)
- 800385c:	781a      	ldrb	r2, [r3, #0]
- 800385e:	683b      	ldr	r3, [r7, #0]
- 8003860:	1c59      	adds	r1, r3, #1
- 8003862:	6039      	str	r1, [r7, #0]
- 8003864:	3230      	adds	r2, #48	@ 0x30
- 8003866:	b2d2      	uxtb	r2, r2
- 8003868:	701a      	strb	r2, [r3, #0]
-
-	// Raw GPIO pin state: 1=high(released), 0=low(pressed)
-	*p++ = ','; *p++ = 'G'; *p++ = ':';
- 800386a:	683b      	ldr	r3, [r7, #0]
- 800386c:	1c5a      	adds	r2, r3, #1
- 800386e:	603a      	str	r2, [r7, #0]
- 8003870:	222c      	movs	r2, #44	@ 0x2c
- 8003872:	701a      	strb	r2, [r3, #0]
- 8003874:	683b      	ldr	r3, [r7, #0]
- 8003876:	1c5a      	adds	r2, r3, #1
- 8003878:	603a      	str	r2, [r7, #0]
- 800387a:	2247      	movs	r2, #71	@ 0x47
- 800387c:	701a      	strb	r2, [r3, #0]
- 800387e:	683b      	ldr	r3, [r7, #0]
- 8003880:	1c5a      	adds	r2, r3, #1
- 8003882:	603a      	str	r2, [r7, #0]
- 8003884:	223a      	movs	r2, #58	@ 0x3a
- 8003886:	701a      	strb	r2, [r3, #0]
-	*p++ = '0' + (uint8_t)HAL_GPIO_ReadPin(SW1_GPIO_Port, SW1_Pin);
- 8003888:	2380      	movs	r3, #128	@ 0x80
- 800388a:	009b      	lsls	r3, r3, #2
- 800388c:	4a44      	ldr	r2, [pc, #272]	@ (80039a0 <debug_output+0x314>)
- 800388e:	0019      	movs	r1, r3
- 8003890:	0010      	movs	r0, r2
- 8003892:	f001 f911 	bl	8004ab8 <HAL_GPIO_ReadPin>
- 8003896:	0003      	movs	r3, r0
- 8003898:	0019      	movs	r1, r3
- 800389a:	683b      	ldr	r3, [r7, #0]
- 800389c:	1c5a      	adds	r2, r3, #1
- 800389e:	603a      	str	r2, [r7, #0]
- 80038a0:	000a      	movs	r2, r1
- 80038a2:	3230      	adds	r2, #48	@ 0x30
- 80038a4:	b2d2      	uxtb	r2, r2
- 80038a6:	701a      	strb	r2, [r3, #0]
-	*p++ = '0' + (uint8_t)HAL_GPIO_ReadPin(SW2_GPIO_Port, SW2_Pin);
- 80038a8:	2380      	movs	r3, #128	@ 0x80
- 80038aa:	005b      	lsls	r3, r3, #1
- 80038ac:	4a3c      	ldr	r2, [pc, #240]	@ (80039a0 <debug_output+0x314>)
- 80038ae:	0019      	movs	r1, r3
- 80038b0:	0010      	movs	r0, r2
- 80038b2:	f001 f901 	bl	8004ab8 <HAL_GPIO_ReadPin>
- 80038b6:	0003      	movs	r3, r0
- 80038b8:	0019      	movs	r1, r3
- 80038ba:	683b      	ldr	r3, [r7, #0]
- 80038bc:	1c5a      	adds	r2, r3, #1
- 80038be:	603a      	str	r2, [r7, #0]
- 80038c0:	000a      	movs	r2, r1
- 80038c2:	3230      	adds	r2, #48	@ 0x30
- 80038c4:	b2d2      	uxtb	r2, r2
- 80038c6:	701a      	strb	r2, [r3, #0]
-
-	*p++ = ','; *p++ = 'D'; *p++ = ':';
- 80038c8:	683b      	ldr	r3, [r7, #0]
- 80038ca:	1c5a      	adds	r2, r3, #1
- 80038cc:	603a      	str	r2, [r7, #0]
- 80038ce:	222c      	movs	r2, #44	@ 0x2c
- 80038d0:	701a      	strb	r2, [r3, #0]
- 80038d2:	683b      	ldr	r3, [r7, #0]
- 80038d4:	1c5a      	adds	r2, r3, #1
- 80038d6:	603a      	str	r2, [r7, #0]
- 80038d8:	2244      	movs	r2, #68	@ 0x44
- 80038da:	701a      	strb	r2, [r3, #0]
- 80038dc:	683b      	ldr	r3, [r7, #0]
- 80038de:	1c5a      	adds	r2, r3, #1
- 80038e0:	603a      	str	r2, [r7, #0]
- 80038e2:	223a      	movs	r2, #58	@ 0x3a
- 80038e4:	701a      	strb	r2, [r3, #0]
-	p += debug_itoa(current_drive_value, p);
- 80038e6:	4b2f      	ldr	r3, [pc, #188]	@ (80039a4 <debug_output+0x318>)
- 80038e8:	781b      	ldrb	r3, [r3, #0]
- 80038ea:	001a      	movs	r2, r3
- 80038ec:	683b      	ldr	r3, [r7, #0]
- 80038ee:	0019      	movs	r1, r3
- 80038f0:	0010      	movs	r0, r2
- 80038f2:	f7ff fe26 	bl	8003542 <debug_itoa>
- 80038f6:	0003      	movs	r3, r0
- 80038f8:	001a      	movs	r2, r3
- 80038fa:	683b      	ldr	r3, [r7, #0]
- 80038fc:	189b      	adds	r3, r3, r2
- 80038fe:	603b      	str	r3, [r7, #0]
-
-	*p++ = ','; *p++ = 'M'; *p++ = ':';
- 8003900:	683b      	ldr	r3, [r7, #0]
- 8003902:	1c5a      	adds	r2, r3, #1
- 8003904:	603a      	str	r2, [r7, #0]
- 8003906:	222c      	movs	r2, #44	@ 0x2c
- 8003908:	701a      	strb	r2, [r3, #0]
- 800390a:	683b      	ldr	r3, [r7, #0]
- 800390c:	1c5a      	adds	r2, r3, #1
- 800390e:	603a      	str	r2, [r7, #0]
- 8003910:	224d      	movs	r2, #77	@ 0x4d
- 8003912:	701a      	strb	r2, [r3, #0]
- 8003914:	683b      	ldr	r3, [r7, #0]
- 8003916:	1c5a      	adds	r2, r3, #1
- 8003918:	603a      	str	r2, [r7, #0]
- 800391a:	223a      	movs	r2, #58	@ 0x3a
- 800391c:	701a      	strb	r2, [r3, #0]
-	*p++ = '0' + drive_mode;
- 800391e:	4b22      	ldr	r3, [pc, #136]	@ (80039a8 <debug_output+0x31c>)
- 8003920:	781a      	ldrb	r2, [r3, #0]
- 8003922:	683b      	ldr	r3, [r7, #0]
- 8003924:	1c59      	adds	r1, r3, #1
- 8003926:	6039      	str	r1, [r7, #0]
- 8003928:	3230      	adds	r2, #48	@ 0x30
- 800392a:	b2d2      	uxtb	r2, r2
- 800392c:	701a      	strb	r2, [r3, #0]
-
-	*p++ = '*'; *p++ = '\r'; *p++ = '\n';
- 800392e:	683b      	ldr	r3, [r7, #0]
- 8003930:	1c5a      	adds	r2, r3, #1
- 8003932:	603a      	str	r2, [r7, #0]
- 8003934:	222a      	movs	r2, #42	@ 0x2a
- 8003936:	701a      	strb	r2, [r3, #0]
- 8003938:	683b      	ldr	r3, [r7, #0]
- 800393a:	1c5a      	adds	r2, r3, #1
- 800393c:	603a      	str	r2, [r7, #0]
- 800393e:	220d      	movs	r2, #13
- 8003940:	701a      	strb	r2, [r3, #0]
- 8003942:	683b      	ldr	r3, [r7, #0]
- 8003944:	1c5a      	adds	r2, r3, #1
- 8003946:	603a      	str	r2, [r7, #0]
- 8003948:	220a      	movs	r2, #10
- 800394a:	701a      	strb	r2, [r3, #0]
-
-	HAL_UART_Transmit(&huart1, (uint8_t*)debug_tx_buffer, p - debug_tx_buffer, 10);
- 800394c:	683a      	ldr	r2, [r7, #0]
- 800394e:	4b09      	ldr	r3, [pc, #36]	@ (8003974 <debug_output+0x2e8>)
- 8003950:	1ad3      	subs	r3, r2, r3
- 8003952:	b29a      	uxth	r2, r3
- 8003954:	4907      	ldr	r1, [pc, #28]	@ (8003974 <debug_output+0x2e8>)
- 8003956:	4815      	ldr	r0, [pc, #84]	@ (80039ac <debug_output+0x320>)
- 8003958:	230a      	movs	r3, #10
- 800395a:	f003 f91f 	bl	8006b9c <HAL_UART_Transmit>
- 800395e:	e002      	b.n	8003966 <debug_output+0x2da>
-	if (!debug_enabled) return;
- 8003960:	46c0      	nop			@ (mov r8, r8)
- 8003962:	e000      	b.n	8003966 <debug_output+0x2da>
-	if ((now - last_debug_output_time) < DEBUG_OUTPUT_INTERVAL_MS) return;
- 8003964:	46c0      	nop			@ (mov r8, r8)
-}
- 8003966:	46bd      	mov	sp, r7
- 8003968:	b002      	add	sp, #8
- 800396a:	bd80      	pop	{r7, pc}
- 800396c:	20000020 	.word	0x20000020
- 8003970:	20000554 	.word	0x20000554
- 8003974:	20000558 	.word	0x20000558
- 8003978:	20000484 	.word	0x20000484
- 800397c:	20000488 	.word	0x20000488
- 8003980:	200005a8 	.word	0x200005a8
- 8003984:	200004bf 	.word	0x200004bf
- 8003988:	200003c0 	.word	0x200003c0
- 800398c:	200004bd 	.word	0x200004bd
- 8003990:	200004d5 	.word	0x200004d5
- 8003994:	20000002 	.word	0x20000002
- 8003998:	200003a8 	.word	0x200003a8
- 800399c:	200003a9 	.word	0x200003a9
- 80039a0:	50000400 	.word	0x50000400
- 80039a4:	2000001e 	.word	0x2000001e
- 80039a8:	200004e0 	.word	0x200004e0
- 80039ac:	200001c8 	.word	0x200001c8
-
-080039b0 <reset_position_if_needed>:
-// ============================================================================
-// Position Management
-// ============================================================================
-
-void reset_position_if_needed(void)
-{
- 80039b0:	b580      	push	{r7, lr}
- 80039b2:	b082      	sub	sp, #8
- 80039b4:	af00      	add	r7, sp, #0
-	// This is called from main loop periodically or after feed completes
-	// to reset position tracking and prevent overflow
-
-	// Only reset when position is at a "round" value to avoid drift
-	int32_t counts_per_mm = tenths_to_counts(10); // counts per 1mm
- 80039b6:	200a      	movs	r0, #10
- 80039b8:	f7fe ff8a 	bl	80028d0 <tenths_to_counts>
- 80039bc:	0003      	movs	r3, r0
- 80039be:	607b      	str	r3, [r7, #4]
-
-	// Check if we're at a position that's a multiple of 1mm
-	if ((total_count % counts_per_mm) == 0 && feed_state == FEED_STATE_IDLE)
- 80039c0:	4b1a      	ldr	r3, [pc, #104]	@ (8003a2c <reset_position_if_needed+0x7c>)
- 80039c2:	681b      	ldr	r3, [r3, #0]
- 80039c4:	6879      	ldr	r1, [r7, #4]
- 80039c6:	0018      	movs	r0, r3
- 80039c8:	f7fc fd0e 	bl	80003e8 <__aeabi_idivmod>
- 80039cc:	1e0b      	subs	r3, r1, #0
- 80039ce:	d129      	bne.n	8003a24 <reset_position_if_needed+0x74>
- 80039d0:	4b17      	ldr	r3, [pc, #92]	@ (8003a30 <reset_position_if_needed+0x80>)
- 80039d2:	781b      	ldrb	r3, [r3, #0]
- 80039d4:	b2db      	uxtb	r3, r3
- 80039d6:	2b00      	cmp	r3, #0
- 80039d8:	d124      	bne.n	8003a24 <reset_position_if_needed+0x74>
-	{
-		// Calculate how many mm we've moved
-		int32_t mm_moved = total_count / counts_per_mm;
- 80039da:	4b14      	ldr	r3, [pc, #80]	@ (8003a2c <reset_position_if_needed+0x7c>)
- 80039dc:	681b      	ldr	r3, [r3, #0]
- 80039de:	6879      	ldr	r1, [r7, #4]
- 80039e0:	0018      	movs	r0, r3
- 80039e2:	f7fc fc1b 	bl	800021c <__divsi3>
- 80039e6:	0003      	movs	r3, r0
- 80039e8:	603b      	str	r3, [r7, #0]
-		mm_position += mm_moved;
- 80039ea:	4b12      	ldr	r3, [pc, #72]	@ (8003a34 <reset_position_if_needed+0x84>)
- 80039ec:	681a      	ldr	r2, [r3, #0]
- 80039ee:	683b      	ldr	r3, [r7, #0]
- 80039f0:	18d2      	adds	r2, r2, r3
- 80039f2:	4b10      	ldr	r3, [pc, #64]	@ (8003a34 <reset_position_if_needed+0x84>)
- 80039f4:	601a      	str	r2, [r3, #0]
-  __ASM volatile ("cpsid i" : : : "memory");
- 80039f6:	b672      	cpsid	i
-}
- 80039f8:	46c0      	nop			@ (mov r8, r8)
-
-		// Reset encoder tracking
-		__disable_irq();
-		encoder_count_extra = 0;
- 80039fa:	4b0f      	ldr	r3, [pc, #60]	@ (8003a38 <reset_position_if_needed+0x88>)
- 80039fc:	2200      	movs	r2, #0
- 80039fe:	601a      	str	r2, [r3, #0]
-		htim3.Instance->CNT = 0;
- 8003a00:	4b0e      	ldr	r3, [pc, #56]	@ (8003a3c <reset_position_if_needed+0x8c>)
- 8003a02:	681b      	ldr	r3, [r3, #0]
- 8003a04:	2200      	movs	r2, #0
- 8003a06:	625a      	str	r2, [r3, #36]	@ 0x24
-		encoder_previous = 0;
- 8003a08:	4b0d      	ldr	r3, [pc, #52]	@ (8003a40 <reset_position_if_needed+0x90>)
- 8003a0a:	2200      	movs	r2, #0
- 8003a0c:	801a      	strh	r2, [r3, #0]
-		total_count = 0;
- 8003a0e:	4b07      	ldr	r3, [pc, #28]	@ (8003a2c <reset_position_if_needed+0x7c>)
- 8003a10:	2200      	movs	r2, #0
- 8003a12:	601a      	str	r2, [r3, #0]
-		target_count = 0;
- 8003a14:	4b0b      	ldr	r3, [pc, #44]	@ (8003a44 <reset_position_if_needed+0x94>)
- 8003a16:	2200      	movs	r2, #0
- 8003a18:	601a      	str	r2, [r3, #0]
-		feed_target_position = 0;
- 8003a1a:	4b0b      	ldr	r3, [pc, #44]	@ (8003a48 <reset_position_if_needed+0x98>)
- 8003a1c:	2200      	movs	r2, #0
- 8003a1e:	601a      	str	r2, [r3, #0]
-  __ASM volatile ("cpsie i" : : : "memory");
- 8003a20:	b662      	cpsie	i
-}
- 8003a22:	46c0      	nop			@ (mov r8, r8)
-		__enable_irq();
-	}
-}
- 8003a24:	46c0      	nop			@ (mov r8, r8)
- 8003a26:	46bd      	mov	sp, r7
- 8003a28:	b002      	add	sp, #8
- 8003a2a:	bd80      	pop	{r7, pc}
- 8003a2c:	20000484 	.word	0x20000484
- 8003a30:	200004bf 	.word	0x200004bf
- 8003a34:	20000550 	.word	0x20000550
- 8003a38:	200003ac 	.word	0x200003ac
- 8003a3c:	20000098 	.word	0x20000098
- 8003a40:	200003b0 	.word	0x200003b0
- 8003a44:	20000488 	.word	0x20000488
- 8003a48:	200004d0 	.word	0x200004d0
-
-08003a4c <Error_Handler>:
-/**
-  * @brief  This function is executed in case of error occurrence.
-  * @retval None
-  */
+ 80007bc:	b672      	cpsid	i
 void Error_Handler(void)
 {
- 8003a4c:	b580      	push	{r7, lr}
- 8003a4e:	af00      	add	r7, sp, #0
-  __ASM volatile ("cpsid i" : : : "memory");
- 8003a50:	b672      	cpsid	i
-}
- 8003a52:	46c0      	nop			@ (mov r8, r8)
   /* USER CODE BEGIN Error_Handler_Debug */
   /* User can add his own implementation to report the HAL error return state */
   __disable_irq();
   while (1)
- 8003a54:	46c0      	nop			@ (mov r8, r8)
- 8003a56:	e7fd      	b.n	8003a54 <Error_Handler+0x8>
+ 80007be:	e7fe      	b.n	80007be <SystemClock_Config+0x42>
+  RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
+ 80007c0:	9001      	str	r0, [sp, #4]
+  RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+ 80007c2:	9002      	str	r0, [sp, #8]
+  RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV1;
+ 80007c4:	9003      	str	r0, [sp, #12]
+  RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV1;
+ 80007c6:	9004      	str	r0, [sp, #16]
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+ 80007c8:	0029      	movs	r1, r5
+ 80007ca:	4668      	mov	r0, sp
+  RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK
+ 80007cc:	9600      	str	r6, [sp, #0]
+  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
+ 80007ce:	f002 ff21 	bl	8003614 <HAL_RCC_ClockConfig>
+ 80007d2:	2800      	cmp	r0, #0
+ 80007d4:	d001      	beq.n	80007da <SystemClock_Config+0x5e>
+ 80007d6:	b672      	cpsid	i
+  while (1)
+ 80007d8:	e7fe      	b.n	80007d8 <SystemClock_Config+0x5c>
+}
+ 80007da:	b00c      	add	sp, #48	@ 0x30
+ 80007dc:	bd70      	pop	{r4, r5, r6, pc}
+ 80007de:	46c0      	nop			@ (mov r8, r8)
+ 80007e0:	40022000 	.word	0x40022000
 
-08003a58 <HAL_MspInit>:
-void HAL_TIM_MspPostInit(TIM_HandleTypeDef *htim);
-                    /**
-  * Initializes the Global MSP.
-  */
-void HAL_MspInit(void)
+080007e4 <HAL_TIM_PeriodElapsedCallback>:
 {
- 8003a58:	b580      	push	{r7, lr}
- 8003a5a:	b082      	sub	sp, #8
- 8003a5c:	af00      	add	r7, sp, #0
+ 80007e4:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+	if (htim == &htim14) // encoder check timer (runs at 20khz)
+ 80007e6:	4b53      	ldr	r3, [pc, #332]	@ (8000934 <HAL_TIM_PeriodElapsedCallback+0x150>)
+ 80007e8:	4c53      	ldr	r4, [pc, #332]	@ (8000938 <HAL_TIM_PeriodElapsedCallback+0x154>)
+ 80007ea:	4298      	cmp	r0, r3
+ 80007ec:	d000      	beq.n	80007f0 <HAL_TIM_PeriodElapsedCallback+0xc>
+ 80007ee:	e093      	b.n	8000918 <HAL_TIM_PeriodElapsedCallback+0x134>
+		uint16_t count = htim3.Instance->CNT;
+ 80007f0:	4b52      	ldr	r3, [pc, #328]	@ (800093c <HAL_TIM_PeriodElapsedCallback+0x158>)
+		if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
+ 80007f2:	4d53      	ldr	r5, [pc, #332]	@ (8000940 <HAL_TIM_PeriodElapsedCallback+0x15c>)
+		uint16_t count = htim3.Instance->CNT;
+ 80007f4:	681b      	ldr	r3, [r3, #0]
+ 80007f6:	27fa      	movs	r7, #250	@ 0xfa
+ 80007f8:	6a59      	ldr	r1, [r3, #36]	@ 0x24
+		if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
+ 80007fa:	882b      	ldrh	r3, [r5, #0]
+			encoder_count_extra ++;
+ 80007fc:	4851      	ldr	r0, [pc, #324]	@ (8000944 <HAL_TIM_PeriodElapsedCallback+0x160>)
+		if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
+ 80007fe:	469c      	mov	ip, r3
+ 8000800:	4e51      	ldr	r6, [pc, #324]	@ (8000948 <HAL_TIM_PeriodElapsedCallback+0x164>)
+			encoder_count_extra ++;
+ 8000802:	6803      	ldr	r3, [r0, #0]
+		uint16_t count = htim3.Instance->CNT;
+ 8000804:	b28a      	uxth	r2, r1
+		if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
+ 8000806:	00bf      	lsls	r7, r7, #2
+ 8000808:	45b4      	cmp	ip, r6
+ 800080a:	d958      	bls.n	80008be <HAL_TIM_PeriodElapsedCallback+0xda>
+			encoder_count_extra ++;
+ 800080c:	3301      	adds	r3, #1
+		if ((encoder_previous > (CNT_MAX-CNT_LIMIT_ZONE)) && (count < CNT_LIMIT_ZONE)) // positive turnaround
+ 800080e:	42ba      	cmp	r2, r7
+ 8000810:	d35a      	bcc.n	80008c8 <HAL_TIM_PeriodElapsedCallback+0xe4>
+		if (total_count > POSITION_OVERFLOW_THRESHOLD)
+ 8000812:	2780      	movs	r7, #128	@ 0x80
+		encoder_previous = count; // update previous for next cycle
+ 8000814:	802a      	strh	r2, [r5, #0]
+		total_count = (encoder_count_extra * 65536) + count;
+ 8000816:	4d4b      	ldr	r5, [pc, #300]	@ (8000944 <HAL_TIM_PeriodElapsedCallback+0x160>)
+ 8000818:	b289      	uxth	r1, r1
+ 800081a:	682a      	ldr	r2, [r5, #0]
+ 800081c:	4e4b      	ldr	r6, [pc, #300]	@ (800094c <HAL_TIM_PeriodElapsedCallback+0x168>)
+ 800081e:	0413      	lsls	r3, r2, #16
+ 8000820:	185b      	adds	r3, r3, r1
+			target_count -= adjustment;
+ 8000822:	494b      	ldr	r1, [pc, #300]	@ (8000950 <HAL_TIM_PeriodElapsedCallback+0x16c>)
+		total_count = (encoder_count_extra * 65536) + count;
+ 8000824:	6033      	str	r3, [r6, #0]
+			target_count -= adjustment;
+ 8000826:	6808      	ldr	r0, [r1, #0]
+		if (total_count > POSITION_OVERFLOW_THRESHOLD)
+ 8000828:	05ff      	lsls	r7, r7, #23
+ 800082a:	42bb      	cmp	r3, r7
+ 800082c:	db4e      	blt.n	80008cc <HAL_TIM_PeriodElapsedCallback+0xe8>
+			total_count -= adjustment;
+ 800082e:	4f49      	ldr	r7, [pc, #292]	@ (8000954 <HAL_TIM_PeriodElapsedCallback+0x170>)
+ 8000830:	19db      	adds	r3, r3, r7
+ 8000832:	6033      	str	r3, [r6, #0]
+			feed_target_position -= adjustment;
+ 8000834:	4e48      	ldr	r6, [pc, #288]	@ (8000958 <HAL_TIM_PeriodElapsedCallback+0x174>)
+			target_count -= adjustment;
+ 8000836:	19c0      	adds	r0, r0, r7
+ 8000838:	6008      	str	r0, [r1, #0]
+			feed_target_position -= adjustment;
+ 800083a:	6830      	ldr	r0, [r6, #0]
+ 800083c:	19c0      	adds	r0, r0, r7
+ 800083e:	6030      	str	r0, [r6, #0]
+			encoder_count_extra -= (adjustment / 65536);
+ 8000840:	4846      	ldr	r0, [pc, #280]	@ (800095c <HAL_TIM_PeriodElapsedCallback+0x178>)
+			encoder_count_extra += (adjustment / 65536);
+ 8000842:	1812      	adds	r2, r2, r0
+			mm_position = 0;
+ 8000844:	2000      	movs	r0, #0
+			encoder_count_extra += (adjustment / 65536);
+ 8000846:	602a      	str	r2, [r5, #0]
+			mm_position = 0;
+ 8000848:	4a45      	ldr	r2, [pc, #276]	@ (8000960 <HAL_TIM_PeriodElapsedCallback+0x17c>)
+ 800084a:	6010      	str	r0, [r2, #0]
+		if (pid_add!=0)
+ 800084c:	4845      	ldr	r0, [pc, #276]	@ (8000964 <HAL_TIM_PeriodElapsedCallback+0x180>)
+ 800084e:	6802      	ldr	r2, [r0, #0]
+ 8000850:	2a00      	cmp	r2, #0
+ 8000852:	d004      	beq.n	800085e <HAL_TIM_PeriodElapsedCallback+0x7a>
+			int64_t temp = target_count + pid_add;
+ 8000854:	680d      	ldr	r5, [r1, #0]
+ 8000856:	1952      	adds	r2, r2, r5
+			pid_add = 0;
+ 8000858:	2500      	movs	r5, #0
+			target_count = temp;
+ 800085a:	600a      	str	r2, [r1, #0]
+			pid_add = 0;
+ 800085c:	6005      	str	r5, [r0, #0]
+			vel_counter++;
+ 800085e:	4842      	ldr	r0, [pc, #264]	@ (8000968 <HAL_TIM_PeriodElapsedCallback+0x184>)
+ 8000860:	7802      	ldrb	r2, [r0, #0]
+ 8000862:	3201      	adds	r2, #1
+ 8000864:	b2d2      	uxtb	r2, r2
+ 8000866:	7002      	strb	r2, [r0, #0]
+			if (vel_counter >= 20)
+ 8000868:	2a13      	cmp	r2, #19
+ 800086a:	d907      	bls.n	800087c <HAL_TIM_PeriodElapsedCallback+0x98>
+				velocity = total_count - vel_prev_pos;
+ 800086c:	4d3f      	ldr	r5, [pc, #252]	@ (800096c <HAL_TIM_PeriodElapsedCallback+0x188>)
+ 800086e:	4e40      	ldr	r6, [pc, #256]	@ (8000970 <HAL_TIM_PeriodElapsedCallback+0x18c>)
+ 8000870:	682a      	ldr	r2, [r5, #0]
+				vel_prev_pos = total_count;
+ 8000872:	602b      	str	r3, [r5, #0]
+				velocity = total_count - vel_prev_pos;
+ 8000874:	1a9a      	subs	r2, r3, r2
+ 8000876:	6032      	str	r2, [r6, #0]
+				vel_counter = 0;
+ 8000878:	2200      	movs	r2, #0
+ 800087a:	7002      	strb	r2, [r0, #0]
+			if (total_count != last_moved_pos)
+ 800087c:	4a3d      	ldr	r2, [pc, #244]	@ (8000974 <HAL_TIM_PeriodElapsedCallback+0x190>)
+ 800087e:	483e      	ldr	r0, [pc, #248]	@ (8000978 <HAL_TIM_PeriodElapsedCallback+0x194>)
+ 8000880:	6815      	ldr	r5, [r2, #0]
+ 8000882:	429d      	cmp	r5, r3
+ 8000884:	d031      	beq.n	80008ea <HAL_TIM_PeriodElapsedCallback+0x106>
+				last_moved_pos = total_count;
+ 8000886:	6013      	str	r3, [r2, #0]
+				still_counter = 0;
+ 8000888:	2200      	movs	r2, #0
+				still_counter++;
+ 800088a:	8002      	strh	r2, [r0, #0]
+			int32_t error = target_count - total_count;
+ 800088c:	680d      	ldr	r5, [r1, #0]
+		htim1.Instance->CCR1 = PWM;
+ 800088e:	6824      	ldr	r4, [r4, #0]
+			int32_t error = target_count - total_count;
+ 8000890:	1aed      	subs	r5, r5, r3
+			int32_t brake_distance = velocity * brake_time_tenths / 10;
+ 8000892:	4b3a      	ldr	r3, [pc, #232]	@ (800097c <HAL_TIM_PeriodElapsedCallback+0x198>)
+ 8000894:	4e3a      	ldr	r6, [pc, #232]	@ (8000980 <HAL_TIM_PeriodElapsedCallback+0x19c>)
+ 8000896:	681b      	ldr	r3, [r3, #0]
+			if (error > FEED_POSITION_TOLERANCE && (is_stopped || error > brake_distance))
+ 8000898:	2d0a      	cmp	r5, #10
+ 800089a:	dd2e      	ble.n	80008fa <HAL_TIM_PeriodElapsedCallback+0x116>
+ 800089c:	2a28      	cmp	r2, #40	@ 0x28
+ 800089e:	d807      	bhi.n	80008b0 <HAL_TIM_PeriodElapsedCallback+0xcc>
+			int32_t brake_distance = velocity * brake_time_tenths / 10;
+ 80008a0:	4a33      	ldr	r2, [pc, #204]	@ (8000970 <HAL_TIM_PeriodElapsedCallback+0x18c>)
+ 80008a2:	210a      	movs	r1, #10
+ 80008a4:	6810      	ldr	r0, [r2, #0]
+ 80008a6:	4358      	muls	r0, r3
+ 80008a8:	f7ff fccc 	bl	8000244 <__divsi3>
+			if (error > FEED_POSITION_TOLERANCE && (is_stopped || error > brake_distance))
+ 80008ac:	4285      	cmp	r5, r0
+ 80008ae:	dd2d      	ble.n	800090c <HAL_TIM_PeriodElapsedCallback+0x128>
+		htim1.Instance->CCR1 = PWM;
+ 80008b0:	2396      	movs	r3, #150	@ 0x96
+		htim1.Instance->CCR2 = 0;
+ 80008b2:	2200      	movs	r2, #0
+		htim1.Instance->CCR1 = PWM;
+ 80008b4:	011b      	lsls	r3, r3, #4
+ 80008b6:	6363      	str	r3, [r4, #52]	@ 0x34
+		htim1.Instance->CCR2 = 0;
+ 80008b8:	63a2      	str	r2, [r4, #56]	@ 0x38
+				debug_pid_output = -PWM_MAX;
+ 80008ba:	8033      	strh	r3, [r6, #0]
+}
+ 80008bc:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+		else if ((encoder_previous < CNT_LIMIT_ZONE) && (count > CNT_MAX-CNT_LIMIT_ZONE)) // negative turnaround
+ 80008be:	45bc      	cmp	ip, r7
+ 80008c0:	d2a7      	bcs.n	8000812 <HAL_TIM_PeriodElapsedCallback+0x2e>
+ 80008c2:	42b2      	cmp	r2, r6
+ 80008c4:	d9a5      	bls.n	8000812 <HAL_TIM_PeriodElapsedCallback+0x2e>
+			encoder_count_extra --;
+ 80008c6:	3b01      	subs	r3, #1
+ 80008c8:	6003      	str	r3, [r0, #0]
+ 80008ca:	e7a2      	b.n	8000812 <HAL_TIM_PeriodElapsedCallback+0x2e>
+		else if (total_count < -POSITION_OVERFLOW_THRESHOLD)
+ 80008cc:	27c0      	movs	r7, #192	@ 0xc0
+ 80008ce:	063f      	lsls	r7, r7, #24
+ 80008d0:	42bb      	cmp	r3, r7
+ 80008d2:	dcbb      	bgt.n	800084c <HAL_TIM_PeriodElapsedCallback+0x68>
+			total_count += adjustment;
+ 80008d4:	4f2b      	ldr	r7, [pc, #172]	@ (8000984 <HAL_TIM_PeriodElapsedCallback+0x1a0>)
+ 80008d6:	19db      	adds	r3, r3, r7
+ 80008d8:	6033      	str	r3, [r6, #0]
+			feed_target_position += adjustment;
+ 80008da:	4e1f      	ldr	r6, [pc, #124]	@ (8000958 <HAL_TIM_PeriodElapsedCallback+0x174>)
+			target_count += adjustment;
+ 80008dc:	19c0      	adds	r0, r0, r7
+ 80008de:	6008      	str	r0, [r1, #0]
+			feed_target_position += adjustment;
+ 80008e0:	6830      	ldr	r0, [r6, #0]
+ 80008e2:	19c0      	adds	r0, r0, r7
+ 80008e4:	6030      	str	r0, [r6, #0]
+			encoder_count_extra += (adjustment / 65536);
+ 80008e6:	4828      	ldr	r0, [pc, #160]	@ (8000988 <HAL_TIM_PeriodElapsedCallback+0x1a4>)
+ 80008e8:	e7ab      	b.n	8000842 <HAL_TIM_PeriodElapsedCallback+0x5e>
+			else if (still_counter < 1000)
+ 80008ea:	25fa      	movs	r5, #250	@ 0xfa
+ 80008ec:	8802      	ldrh	r2, [r0, #0]
+ 80008ee:	00ad      	lsls	r5, r5, #2
+ 80008f0:	42aa      	cmp	r2, r5
+ 80008f2:	d2cb      	bcs.n	800088c <HAL_TIM_PeriodElapsedCallback+0xa8>
+				still_counter++;
+ 80008f4:	3201      	adds	r2, #1
+ 80008f6:	b292      	uxth	r2, r2
+ 80008f8:	e7c7      	b.n	800088a <HAL_TIM_PeriodElapsedCallback+0xa6>
+			else if (error < -FEED_POSITION_TOLERANCE)
+ 80008fa:	350a      	adds	r5, #10
+ 80008fc:	da06      	bge.n	800090c <HAL_TIM_PeriodElapsedCallback+0x128>
+		htim1.Instance->CCR1 = 0;
+ 80008fe:	2300      	movs	r3, #0
+ 8000900:	6363      	str	r3, [r4, #52]	@ 0x34
+		htim1.Instance->CCR2 = PWM;
+ 8000902:	2396      	movs	r3, #150	@ 0x96
+ 8000904:	011b      	lsls	r3, r3, #4
+ 8000906:	63a3      	str	r3, [r4, #56]	@ 0x38
+				debug_pid_output = -PWM_MAX;
+ 8000908:	4b20      	ldr	r3, [pc, #128]	@ (800098c <HAL_TIM_PeriodElapsedCallback+0x1a8>)
+ 800090a:	e7d6      	b.n	80008ba <HAL_TIM_PeriodElapsedCallback+0xd6>
+				htim1.Instance->CCR1 = PWM_MAX;
+ 800090c:	2396      	movs	r3, #150	@ 0x96
+ 800090e:	011b      	lsls	r3, r3, #4
+ 8000910:	6363      	str	r3, [r4, #52]	@ 0x34
+				htim1.Instance->CCR2 = PWM_MAX;
+ 8000912:	63a3      	str	r3, [r4, #56]	@ 0x38
+				debug_pid_output = 0;
+ 8000914:	2300      	movs	r3, #0
+ 8000916:	e7d0      	b.n	80008ba <HAL_TIM_PeriodElapsedCallback+0xd6>
+	if (htim == &htim1) return; // PWM timer
+ 8000918:	42a0      	cmp	r0, r4
+ 800091a:	d0cf      	beq.n	80008bc <HAL_TIM_PeriodElapsedCallback+0xd8>
+	if (htim == &htim16) //SW1 timer
+ 800091c:	4b1c      	ldr	r3, [pc, #112]	@ (8000990 <HAL_TIM_PeriodElapsedCallback+0x1ac>)
+ 800091e:	4298      	cmp	r0, r3
+ 8000920:	d103      	bne.n	800092a <HAL_TIM_PeriodElapsedCallback+0x146>
+		sw1_pressed = 0;
+ 8000922:	4b1c      	ldr	r3, [pc, #112]	@ (8000994 <HAL_TIM_PeriodElapsedCallback+0x1b0>)
+		sw2_pressed = 0;
+ 8000924:	2200      	movs	r2, #0
+ 8000926:	701a      	strb	r2, [r3, #0]
+ 8000928:	e7c8      	b.n	80008bc <HAL_TIM_PeriodElapsedCallback+0xd8>
+	else if (htim == &htim17) //SW2 timer
+ 800092a:	4b1b      	ldr	r3, [pc, #108]	@ (8000998 <HAL_TIM_PeriodElapsedCallback+0x1b4>)
+ 800092c:	4298      	cmp	r0, r3
+ 800092e:	d1c5      	bne.n	80008bc <HAL_TIM_PeriodElapsedCallback+0xd8>
+		sw2_pressed = 0;
+ 8000930:	4b1a      	ldr	r3, [pc, #104]	@ (800099c <HAL_TIM_PeriodElapsedCallback+0x1b8>)
+ 8000932:	e7f7      	b.n	8000924 <HAL_TIM_PeriodElapsedCallback+0x140>
+ 8000934:	20001218 	.word	0x20001218
+ 8000938:	200012b0 	.word	0x200012b0
+ 800093c:	20001264 	.word	0x20001264
+ 8000940:	20000f94 	.word	0x20000f94
+ 8000944:	20000f98 	.word	0x20000f98
+ 8000948:	0000fc17 	.word	0x0000fc17
+ 800094c:	20000154 	.word	0x20000154
+ 8000950:	20000150 	.word	0x20000150
+ 8000954:	e0000001 	.word	0xe0000001
+ 8000958:	20000104 	.word	0x20000104
+ 800095c:	ffffe001 	.word	0xffffe001
+ 8000960:	200000e4 	.word	0x200000e4
+ 8000964:	20000124 	.word	0x20000124
+ 8000968:	2000005c 	.word	0x2000005c
+ 800096c:	20000058 	.word	0x20000058
+ 8000970:	20000054 	.word	0x20000054
+ 8000974:	20000050 	.word	0x20000050
+ 8000978:	2000004c 	.word	0x2000004c
+ 800097c:	20000004 	.word	0x20000004
+ 8000980:	2000007c 	.word	0x2000007c
+ 8000984:	1fffffff 	.word	0x1fffffff
+ 8000988:	00001fff 	.word	0x00001fff
+ 800098c:	fffff6a0 	.word	0xfffff6a0
+ 8000990:	200011cc 	.word	0x200011cc
+ 8000994:	20000f9d 	.word	0x20000f9d
+ 8000998:	20001180 	.word	0x20001180
+ 800099c:	20000f9c 	.word	0x20000f9c
+
+080009a0 <HAL_GPIO_EXTI_Falling_Callback>:
+    if(GPIO_Pin == SW1_Pin) // SW1 (lower button)
+ 80009a0:	2380      	movs	r3, #128	@ 0x80
+{
+ 80009a2:	b510      	push	{r4, lr}
+    if(GPIO_Pin == SW1_Pin) // SW1 (lower button)
+ 80009a4:	009b      	lsls	r3, r3, #2
+ 80009a6:	4298      	cmp	r0, r3
+ 80009a8:	d105      	bne.n	80009b6 <HAL_GPIO_EXTI_Falling_Callback+0x16>
+    	if (!sw1_pressed)
+ 80009aa:	4c0b      	ldr	r4, [pc, #44]	@ (80009d8 <HAL_GPIO_EXTI_Falling_Callback+0x38>)
+    		htim16.Instance->CNT = 0;
+ 80009ac:	480b      	ldr	r0, [pc, #44]	@ (80009dc <HAL_GPIO_EXTI_Falling_Callback+0x3c>)
+    	if (!sw1_pressed)
+ 80009ae:	7823      	ldrb	r3, [r4, #0]
+ 80009b0:	2b00      	cmp	r3, #0
+ 80009b2:	d009      	beq.n	80009c8 <HAL_GPIO_EXTI_Falling_Callback+0x28>
+}
+ 80009b4:	bd10      	pop	{r4, pc}
+    else if (GPIO_Pin == SW2_Pin) // SW2 (upper button)
+ 80009b6:	2380      	movs	r3, #128	@ 0x80
+ 80009b8:	005b      	lsls	r3, r3, #1
+ 80009ba:	4298      	cmp	r0, r3
+ 80009bc:	d1fa      	bne.n	80009b4 <HAL_GPIO_EXTI_Falling_Callback+0x14>
+    	if (!sw2_pressed)
+ 80009be:	4c08      	ldr	r4, [pc, #32]	@ (80009e0 <HAL_GPIO_EXTI_Falling_Callback+0x40>)
+ 80009c0:	7823      	ldrb	r3, [r4, #0]
+ 80009c2:	2b00      	cmp	r3, #0
+ 80009c4:	d1f6      	bne.n	80009b4 <HAL_GPIO_EXTI_Falling_Callback+0x14>
+    		htim17.Instance->CNT = 0;
+ 80009c6:	4807      	ldr	r0, [pc, #28]	@ (80009e4 <HAL_GPIO_EXTI_Falling_Callback+0x44>)
+ 80009c8:	6802      	ldr	r2, [r0, #0]
+ 80009ca:	6253      	str	r3, [r2, #36]	@ 0x24
+    		HAL_TIM_Base_Start_IT(&htim17);
+ 80009cc:	f003 f8ac 	bl	8003b28 <HAL_TIM_Base_Start_IT>
+    		sw2_pressed = 1;
+ 80009d0:	2301      	movs	r3, #1
+ 80009d2:	7023      	strb	r3, [r4, #0]
+}
+ 80009d4:	e7ee      	b.n	80009b4 <HAL_GPIO_EXTI_Falling_Callback+0x14>
+ 80009d6:	46c0      	nop			@ (mov r8, r8)
+ 80009d8:	20000f9d 	.word	0x20000f9d
+ 80009dc:	200011cc 	.word	0x200011cc
+ 80009e0:	20000f9c 	.word	0x20000f9c
+ 80009e4:	20001180 	.word	0x20001180
+
+080009e8 <HAL_UARTEx_RxEventCallback>:
+{
+ 80009e8:	b570      	push	{r4, r5, r6, lr}
+ 80009ea:	000d      	movs	r5, r1
+    if (Size > 64) return; // todo error handling
+ 80009ec:	2940      	cmp	r1, #64	@ 0x40
+ 80009ee:	d822      	bhi.n	8000a36 <HAL_UARTEx_RxEventCallback+0x4e>
+    rx_msg_count++;
+ 80009f0:	2400      	movs	r4, #0
+ 80009f2:	4a13      	ldr	r2, [pc, #76]	@ (8000a40 <HAL_UARTEx_RxEventCallback+0x58>)
+    	if (msg_buf_empty[i])
+ 80009f4:	4e13      	ldr	r6, [pc, #76]	@ (8000a44 <HAL_UARTEx_RxEventCallback+0x5c>)
+    rx_msg_count++;
+ 80009f6:	8813      	ldrh	r3, [r2, #0]
+ 80009f8:	3301      	adds	r3, #1
+ 80009fa:	b29b      	uxth	r3, r3
+ 80009fc:	8013      	strh	r3, [r2, #0]
+    	if (msg_buf_empty[i])
+ 80009fe:	5d33      	ldrb	r3, [r6, r4]
+ 8000a00:	2b00      	cmp	r3, #0
+ 8000a02:	d019      	beq.n	8000a38 <HAL_UARTEx_RxEventCallback+0x50>
+    		memcpy(msg_buf[i], DMA_buffer, Size);
+ 8000a04:	4b10      	ldr	r3, [pc, #64]	@ (8000a48 <HAL_UARTEx_RxEventCallback+0x60>)
+ 8000a06:	01a0      	lsls	r0, r4, #6
+ 8000a08:	002a      	movs	r2, r5
+ 8000a0a:	18c0      	adds	r0, r0, r3
+ 8000a0c:	490f      	ldr	r1, [pc, #60]	@ (8000a4c <HAL_UARTEx_RxEventCallback+0x64>)
+ 8000a0e:	f004 fbe9 	bl	80051e4 <memcpy>
+    		msg_buf_size[i] = Size;
+ 8000a12:	4b0f      	ldr	r3, [pc, #60]	@ (8000a50 <HAL_UARTEx_RxEventCallback+0x68>)
+ 8000a14:	b2ed      	uxtb	r5, r5
+ 8000a16:	551d      	strb	r5, [r3, r4]
+    		msg_buf_empty[i] = 0;
+ 8000a18:	2300      	movs	r3, #0
+ 8000a1a:	5533      	strb	r3, [r6, r4]
+    HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
+ 8000a1c:	4c0d      	ldr	r4, [pc, #52]	@ (8000a54 <HAL_UARTEx_RxEventCallback+0x6c>)
+ 8000a1e:	2240      	movs	r2, #64	@ 0x40
+ 8000a20:	0020      	movs	r0, r4
+ 8000a22:	490a      	ldr	r1, [pc, #40]	@ (8000a4c <HAL_UARTEx_RxEventCallback+0x64>)
+ 8000a24:	f004 fb72 	bl	800510c <HAL_UARTEx_ReceiveToIdle_DMA>
+    __HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT);
+ 8000a28:	2104      	movs	r1, #4
+ 8000a2a:	3404      	adds	r4, #4
+ 8000a2c:	6fe3      	ldr	r3, [r4, #124]	@ 0x7c
+ 8000a2e:	681a      	ldr	r2, [r3, #0]
+ 8000a30:	6813      	ldr	r3, [r2, #0]
+ 8000a32:	438b      	bics	r3, r1
+ 8000a34:	6013      	str	r3, [r2, #0]
+}
+ 8000a36:	bd70      	pop	{r4, r5, r6, pc}
+    for (uint8_t i = 0; i < MSG_BUF_COUNT; i++)
+ 8000a38:	3401      	adds	r4, #1
+ 8000a3a:	2c36      	cmp	r4, #54	@ 0x36
+ 8000a3c:	d1df      	bne.n	80009fe <HAL_UARTEx_RxEventCallback+0x16>
+ 8000a3e:	e7ed      	b.n	8000a1c <HAL_UARTEx_RxEventCallback+0x34>
+ 8000a40:	20000158 	.word	0x20000158
+ 8000a44:	20000f50 	.word	0x20000f50
+ 8000a48:	2000019a 	.word	0x2000019a
+ 8000a4c:	2000015a 	.word	0x2000015a
+ 8000a50:	20000f1a 	.word	0x20000f1a
+ 8000a54:	20001058 	.word	0x20001058
+
+08000a58 <HAL_UART_ErrorCallback>:
+    if (huart->Instance == USART2)
+ 8000a58:	4b0c      	ldr	r3, [pc, #48]	@ (8000a8c <HAL_UART_ErrorCallback+0x34>)
+ 8000a5a:	6802      	ldr	r2, [r0, #0]
+{
+ 8000a5c:	b510      	push	{r4, lr}
+    if (huart->Instance == USART2)
+ 8000a5e:	429a      	cmp	r2, r3
+ 8000a60:	d113      	bne.n	8000a8a <HAL_UART_ErrorCallback+0x32>
+        uart_error_count++;
+ 8000a62:	490b      	ldr	r1, [pc, #44]	@ (8000a90 <HAL_UART_ErrorCallback+0x38>)
+        HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
+ 8000a64:	4c0b      	ldr	r4, [pc, #44]	@ (8000a94 <HAL_UART_ErrorCallback+0x3c>)
+        uart_error_count++;
+ 8000a66:	880b      	ldrh	r3, [r1, #0]
+        HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
+ 8000a68:	0020      	movs	r0, r4
+        uart_error_count++;
+ 8000a6a:	3301      	adds	r3, #1
+ 8000a6c:	b29b      	uxth	r3, r3
+ 8000a6e:	800b      	strh	r3, [r1, #0]
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_FEF | UART_CLEAR_NEF | UART_CLEAR_PEF);
+ 8000a70:	230f      	movs	r3, #15
+        HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
+ 8000a72:	4909      	ldr	r1, [pc, #36]	@ (8000a98 <HAL_UART_ErrorCallback+0x40>)
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_FEF | UART_CLEAR_NEF | UART_CLEAR_PEF);
+ 8000a74:	6213      	str	r3, [r2, #32]
+        HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
+ 8000a76:	2240      	movs	r2, #64	@ 0x40
+ 8000a78:	f004 fb48 	bl	800510c <HAL_UARTEx_ReceiveToIdle_DMA>
+        __HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT);
+ 8000a7c:	2104      	movs	r1, #4
+ 8000a7e:	3404      	adds	r4, #4
+ 8000a80:	6fe3      	ldr	r3, [r4, #124]	@ 0x7c
+ 8000a82:	681a      	ldr	r2, [r3, #0]
+ 8000a84:	6813      	ldr	r3, [r2, #0]
+ 8000a86:	438b      	bics	r3, r1
+ 8000a88:	6013      	str	r3, [r2, #0]
+}
+ 8000a8a:	bd10      	pop	{r4, pc}
+ 8000a8c:	40004400 	.word	0x40004400
+ 8000a90:	2000007a 	.word	0x2000007a
+ 8000a94:	20001058 	.word	0x20001058
+ 8000a98:	2000015a 	.word	0x2000015a
+
+08000a9c <set_LED>:
+{
+ 8000a9c:	b570      	push	{r4, r5, r6, lr}
+ 8000a9e:	000d      	movs	r5, r1
+ 8000aa0:	0014      	movs	r4, r2
+	if (R) R = GPIO_PIN_SET;
+ 8000aa2:	1e43      	subs	r3, r0, #1
+ 8000aa4:	4198      	sbcs	r0, r3
+	if (G) G = GPIO_PIN_SET;
+ 8000aa6:	1e6b      	subs	r3, r5, #1
+ 8000aa8:	419d      	sbcs	r5, r3
+	if (B) B = GPIO_PIN_SET;
+ 8000aaa:	1e63      	subs	r3, r4, #1
+ 8000aac:	419c      	sbcs	r4, r3
+	HAL_GPIO_WritePin(LED_R_GPIO_Port,LED_R_Pin,R);
+ 8000aae:	b2c2      	uxtb	r2, r0
+ 8000ab0:	2108      	movs	r1, #8
+ 8000ab2:	4807      	ldr	r0, [pc, #28]	@ (8000ad0 <set_LED+0x34>)
+ 8000ab4:	f002 fc2e 	bl	8003314 <HAL_GPIO_WritePin>
+	HAL_GPIO_WritePin(LED_G_GPIO_Port,LED_G_Pin,G);
+ 8000ab8:	b2ea      	uxtb	r2, r5
+ 8000aba:	2120      	movs	r1, #32
+ 8000abc:	4804      	ldr	r0, [pc, #16]	@ (8000ad0 <set_LED+0x34>)
+ 8000abe:	f002 fc29 	bl	8003314 <HAL_GPIO_WritePin>
+	HAL_GPIO_WritePin(LED_B_GPIO_Port,LED_B_Pin,B);
+ 8000ac2:	2110      	movs	r1, #16
+ 8000ac4:	4802      	ldr	r0, [pc, #8]	@ (8000ad0 <set_LED+0x34>)
+ 8000ac6:	b2e2      	uxtb	r2, r4
+ 8000ac8:	f002 fc24 	bl	8003314 <HAL_GPIO_WritePin>
+}
+ 8000acc:	bd70      	pop	{r4, r5, r6, pc}
+ 8000ace:	46c0      	nop			@ (mov r8, r8)
+ 8000ad0:	50000400 	.word	0x50000400
+
+08000ad4 <rs485_transmit>:
+{
+ 8000ad4:	b570      	push	{r4, r5, r6, lr}
+ 8000ad6:	0005      	movs	r5, r0
+	HAL_Delay(1);
+ 8000ad8:	2001      	movs	r0, #1
+{
+ 8000ada:	000e      	movs	r6, r1
+	HAL_Delay(1);
+ 8000adc:	f001 ff06 	bl	80028ec <HAL_Delay>
+	HAL_GPIO_WritePin(USART2_NRE_GPIO_Port, USART2_NRE_Pin, GPIO_PIN_SET); // NRE high = receiver off
+ 8000ae0:	2201      	movs	r2, #1
+ 8000ae2:	20a0      	movs	r0, #160	@ 0xa0
+ 8000ae4:	0011      	movs	r1, r2
+ 8000ae6:	05c0      	lsls	r0, r0, #23
+ 8000ae8:	f002 fc14 	bl	8003314 <HAL_GPIO_WritePin>
+	HAL_UART_Transmit(&huart2, data, len, 100);
+ 8000aec:	4c0c      	ldr	r4, [pc, #48]	@ (8000b20 <rs485_transmit+0x4c>)
+ 8000aee:	2364      	movs	r3, #100	@ 0x64
+ 8000af0:	0032      	movs	r2, r6
+ 8000af2:	0029      	movs	r1, r5
+ 8000af4:	0020      	movs	r0, r4
+ 8000af6:	f004 f8de 	bl	8004cb6 <HAL_UART_Transmit>
+	HAL_GPIO_WritePin(USART2_NRE_GPIO_Port, USART2_NRE_Pin, GPIO_PIN_RESET); // NRE low = receiver on
+ 8000afa:	20a0      	movs	r0, #160	@ 0xa0
+ 8000afc:	2200      	movs	r2, #0
+ 8000afe:	2101      	movs	r1, #1
+ 8000b00:	05c0      	lsls	r0, r0, #23
+ 8000b02:	f002 fc07 	bl	8003314 <HAL_GPIO_WritePin>
+	HAL_UARTEx_ReceiveToIdle_DMA(&huart2, DMA_buffer, 64);
+ 8000b06:	2240      	movs	r2, #64	@ 0x40
+ 8000b08:	0020      	movs	r0, r4
+ 8000b0a:	4906      	ldr	r1, [pc, #24]	@ (8000b24 <rs485_transmit+0x50>)
+ 8000b0c:	f004 fafe 	bl	800510c <HAL_UARTEx_ReceiveToIdle_DMA>
+	__HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT);
+ 8000b10:	2104      	movs	r1, #4
+ 8000b12:	3404      	adds	r4, #4
+ 8000b14:	6fe3      	ldr	r3, [r4, #124]	@ 0x7c
+ 8000b16:	681a      	ldr	r2, [r3, #0]
+ 8000b18:	6813      	ldr	r3, [r2, #0]
+ 8000b1a:	438b      	bics	r3, r1
+ 8000b1c:	6013      	str	r3, [r2, #0]
+}
+ 8000b1e:	bd70      	pop	{r4, r5, r6, pc}
+ 8000b20:	20001058 	.word	0x20001058
+ 8000b24:	2000015a 	.word	0x2000015a
+
+08000b28 <comp_crc_header>:
+{
+ 8000b28:	b570      	push	{r4, r5, r6, lr}
+ 8000b2a:	000d      	movs	r5, r1
+ 8000b2c:	0004      	movs	r4, r0
+	CRC8_107_add(lcrc,lresponse->header.toAddress);
+ 8000b2e:	7809      	ldrb	r1, [r1, #0]
+ 8000b30:	f7ff fe0c 	bl	800074c <CRC8_107_add>
+	CRC8_107_add(lcrc,lresponse->header.fromAddress);
+ 8000b34:	7869      	ldrb	r1, [r5, #1]
+ 8000b36:	0020      	movs	r0, r4
+ 8000b38:	f7ff fe08 	bl	800074c <CRC8_107_add>
+	CRC8_107_add(lcrc,lresponse->header.packetId);
+ 8000b3c:	78a9      	ldrb	r1, [r5, #2]
+ 8000b3e:	0020      	movs	r0, r4
+ 8000b40:	f7ff fe04 	bl	800074c <CRC8_107_add>
+	CRC8_107_add(lcrc,lresponse->header.payloadLength);
+ 8000b44:	78e9      	ldrb	r1, [r5, #3]
+ 8000b46:	0020      	movs	r0, r4
+ 8000b48:	f7ff fe00 	bl	800074c <CRC8_107_add>
+}
+ 8000b4c:	bd70      	pop	{r4, r5, r6, pc}
+	...
+
+08000b50 <peel_ramp_update>:
+{
+ 8000b50:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+	uint32_t now = HAL_GetTick();
+ 8000b52:	f001 fec5 	bl	80028e0 <HAL_GetTick>
+	uint32_t dt = now - peel_last_ramp_time;
+ 8000b56:	4b1d      	ldr	r3, [pc, #116]	@ (8000bcc <peel_ramp_update+0x7c>)
+ 8000b58:	681a      	ldr	r2, [r3, #0]
+ 8000b5a:	1a81      	subs	r1, r0, r2
+	if (dt == 0) return;
+ 8000b5c:	4290      	cmp	r0, r2
+ 8000b5e:	d024      	beq.n	8000baa <peel_ramp_update+0x5a>
+	if (peel_current_pwm == peel_target_pwm) return;
+ 8000b60:	4e1b      	ldr	r6, [pc, #108]	@ (8000bd0 <peel_ramp_update+0x80>)
+	peel_last_ramp_time = now;
+ 8000b62:	6018      	str	r0, [r3, #0]
+	if (peel_current_pwm == peel_target_pwm) return;
+ 8000b64:	2300      	movs	r3, #0
+ 8000b66:	5ef7      	ldrsh	r7, [r6, r3]
+ 8000b68:	4b1a      	ldr	r3, [pc, #104]	@ (8000bd4 <peel_ramp_update+0x84>)
+ 8000b6a:	2400      	movs	r4, #0
+ 8000b6c:	5f1c      	ldrsh	r4, [r3, r4]
+ 8000b6e:	42a7      	cmp	r7, r4
+ 8000b70:	d01b      	beq.n	8000baa <peel_ramp_update+0x5a>
+	int16_t step = (int16_t)((int32_t)PWM_MAX * dt / PEEL_RAMP_TIME_MS);
+ 8000b72:	2096      	movs	r0, #150	@ 0x96
+ 8000b74:	0100      	lsls	r0, r0, #4
+ 8000b76:	4348      	muls	r0, r1
+ 8000b78:	2164      	movs	r1, #100	@ 0x64
+ 8000b7a:	f7ff fad9 	bl	8000130 <__udivsi3>
+ 8000b7e:	1c03      	adds	r3, r0, #0
+	if (step < 1) step = 1;
+ 8000b80:	b200      	sxth	r0, r0
+		peel_current_pwm += step;
+ 8000b82:	b2bd      	uxth	r5, r7
+	if (step < 1) step = 1;
+ 8000b84:	2800      	cmp	r0, #0
+ 8000b86:	dc00      	bgt.n	8000b8a <peel_ramp_update+0x3a>
+ 8000b88:	2301      	movs	r3, #1
+		peel_current_pwm += step;
+ 8000b8a:	b29b      	uxth	r3, r3
+	if (peel_target_pwm > peel_current_pwm)
+ 8000b8c:	42a7      	cmp	r7, r4
+ 8000b8e:	da0d      	bge.n	8000bac <peel_ramp_update+0x5c>
+		peel_current_pwm += step;
+ 8000b90:	18eb      	adds	r3, r5, r3
+ 8000b92:	b21b      	sxth	r3, r3
+		if (peel_current_pwm > peel_target_pwm)
+ 8000b94:	429c      	cmp	r4, r3
+ 8000b96:	db0d      	blt.n	8000bb4 <peel_ramp_update+0x64>
+		if (peel_current_pwm < peel_target_pwm)
+ 8000b98:	001c      	movs	r4, r3
+			peel_current_pwm = peel_target_pwm;
+ 8000b9a:	8033      	strh	r3, [r6, #0]
+		htim1.Instance->CCR3 = peel_current_pwm;
+ 8000b9c:	4b0e      	ldr	r3, [pc, #56]	@ (8000bd8 <peel_ramp_update+0x88>)
+ 8000b9e:	681b      	ldr	r3, [r3, #0]
+	if (peel_current_pwm > 0)
+ 8000ba0:	2c00      	cmp	r4, #0
+ 8000ba2:	dd09      	ble.n	8000bb8 <peel_ramp_update+0x68>
+		htim1.Instance->CCR4 = 0;
+ 8000ba4:	2200      	movs	r2, #0
+		htim1.Instance->CCR3 = peel_current_pwm;
+ 8000ba6:	63dc      	str	r4, [r3, #60]	@ 0x3c
+		htim1.Instance->CCR4 = 0;
+ 8000ba8:	641a      	str	r2, [r3, #64]	@ 0x40
+}
+ 8000baa:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+		peel_current_pwm -= step;
+ 8000bac:	1aeb      	subs	r3, r5, r3
+ 8000bae:	b21b      	sxth	r3, r3
+		if (peel_current_pwm < peel_target_pwm)
+ 8000bb0:	429c      	cmp	r4, r3
+ 8000bb2:	ddf1      	ble.n	8000b98 <peel_ramp_update+0x48>
+ 8000bb4:	0023      	movs	r3, r4
+ 8000bb6:	e7f0      	b.n	8000b9a <peel_ramp_update+0x4a>
+	else if (peel_current_pwm < 0)
+ 8000bb8:	2c00      	cmp	r4, #0
+ 8000bba:	d004      	beq.n	8000bc6 <peel_ramp_update+0x76>
+		htim1.Instance->CCR3 = 0;
+ 8000bbc:	2200      	movs	r2, #0
+		htim1.Instance->CCR4 = -peel_current_pwm;
+ 8000bbe:	4264      	negs	r4, r4
+		htim1.Instance->CCR3 = 0;
+ 8000bc0:	63da      	str	r2, [r3, #60]	@ 0x3c
+		htim1.Instance->CCR4 = 0;
+ 8000bc2:	641c      	str	r4, [r3, #64]	@ 0x40
+ 8000bc4:	e7f1      	b.n	8000baa <peel_ramp_update+0x5a>
+		htim1.Instance->CCR3 = 0;
+ 8000bc6:	63dc      	str	r4, [r3, #60]	@ 0x3c
+ 8000bc8:	e7fb      	b.n	8000bc2 <peel_ramp_update+0x72>
+ 8000bca:	46c0      	nop			@ (mov r8, r8)
+ 8000bcc:	200000f8 	.word	0x200000f8
+ 8000bd0:	200000fc 	.word	0x200000fc
+ 8000bd4:	200000fe 	.word	0x200000fe
+ 8000bd8:	200012b0 	.word	0x200012b0
+
+08000bdc <drive_continuous>:
+		target_count = total_count + 10000;
+ 8000bdc:	4b05      	ldr	r3, [pc, #20]	@ (8000bf4 <drive_continuous+0x18>)
+ 8000bde:	681a      	ldr	r2, [r3, #0]
+		target_count = total_count - 10000;
+ 8000be0:	4b05      	ldr	r3, [pc, #20]	@ (8000bf8 <drive_continuous+0x1c>)
+ 8000be2:	18d3      	adds	r3, r2, r3
+	if (forward)
+ 8000be4:	2800      	cmp	r0, #0
+ 8000be6:	d001      	beq.n	8000bec <drive_continuous+0x10>
+		target_count = total_count + 10000;
+ 8000be8:	4b04      	ldr	r3, [pc, #16]	@ (8000bfc <drive_continuous+0x20>)
+ 8000bea:	18d3      	adds	r3, r2, r3
+ 8000bec:	4a04      	ldr	r2, [pc, #16]	@ (8000c00 <drive_continuous+0x24>)
+}
+ 8000bee:	6013      	str	r3, [r2, #0]
+ 8000bf0:	4770      	bx	lr
+ 8000bf2:	46c0      	nop			@ (mov r8, r8)
+ 8000bf4:	20000154 	.word	0x20000154
+ 8000bf8:	ffffd8f0 	.word	0xffffd8f0
+ 8000bfc:	00002710 	.word	0x00002710
+ 8000c00:	20000150 	.word	0x20000150
+
+08000c04 <halt_all>:
+	htim1.Instance->CCR1 = PWM_MAX;
+ 8000c04:	4b09      	ldr	r3, [pc, #36]	@ (8000c2c <halt_all+0x28>)
+	peel_target_pwm = 0;
+ 8000c06:	490a      	ldr	r1, [pc, #40]	@ (8000c30 <halt_all+0x2c>)
+	htim1.Instance->CCR1 = PWM_MAX;
+ 8000c08:	681a      	ldr	r2, [r3, #0]
+ 8000c0a:	2396      	movs	r3, #150	@ 0x96
+ 8000c0c:	011b      	lsls	r3, r3, #4
+ 8000c0e:	6353      	str	r3, [r2, #52]	@ 0x34
+	htim1.Instance->CCR2 = PWM_MAX;
+ 8000c10:	6393      	str	r3, [r2, #56]	@ 0x38
+	peel_target_pwm = 0;
+ 8000c12:	2300      	movs	r3, #0
+ 8000c14:	800b      	strh	r3, [r1, #0]
+	peel_current_pwm = 0;
+ 8000c16:	4907      	ldr	r1, [pc, #28]	@ (8000c34 <halt_all+0x30>)
+	htim1.Instance->CCR3 = 0;
+ 8000c18:	63d3      	str	r3, [r2, #60]	@ 0x3c
+	peel_current_pwm = 0;
+ 8000c1a:	800b      	strh	r3, [r1, #0]
+	target_count = total_count;
+ 8000c1c:	4906      	ldr	r1, [pc, #24]	@ (8000c38 <halt_all+0x34>)
+	htim1.Instance->CCR4 = 0;
+ 8000c1e:	6413      	str	r3, [r2, #64]	@ 0x40
+	target_count = total_count;
+ 8000c20:	6809      	ldr	r1, [r1, #0]
+ 8000c22:	4a06      	ldr	r2, [pc, #24]	@ (8000c3c <halt_all+0x38>)
+ 8000c24:	6011      	str	r1, [r2, #0]
+	pid_add = 0;
+ 8000c26:	4a06      	ldr	r2, [pc, #24]	@ (8000c40 <halt_all+0x3c>)
+ 8000c28:	6013      	str	r3, [r2, #0]
+}
+ 8000c2a:	4770      	bx	lr
+ 8000c2c:	200012b0 	.word	0x200012b0
+ 8000c30:	200000fe 	.word	0x200000fe
+ 8000c34:	200000fc 	.word	0x200000fc
+ 8000c38:	20000154 	.word	0x20000154
+ 8000c3c:	20000150 	.word	0x20000150
+ 8000c40:	20000124 	.word	0x20000124
+
+08000c44 <identify_feeder>:
+{
+ 8000c44:	b510      	push	{r4, lr}
+ 8000c46:	2403      	movs	r4, #3
+		set_LED(1, 1, 1);
+ 8000c48:	2201      	movs	r2, #1
+ 8000c4a:	0011      	movs	r1, r2
+ 8000c4c:	0010      	movs	r0, r2
+ 8000c4e:	f7ff ff25 	bl	8000a9c <set_LED>
+		HAL_Delay(300);
+ 8000c52:	2096      	movs	r0, #150	@ 0x96
+ 8000c54:	0040      	lsls	r0, r0, #1
+ 8000c56:	f001 fe49 	bl	80028ec <HAL_Delay>
+		set_LED(0, 0, 0);
+ 8000c5a:	2200      	movs	r2, #0
+ 8000c5c:	0010      	movs	r0, r2
+ 8000c5e:	0011      	movs	r1, r2
+ 8000c60:	f7ff ff1c 	bl	8000a9c <set_LED>
+		HAL_Delay(300);
+ 8000c64:	2096      	movs	r0, #150	@ 0x96
+	for (int i = 0; i < 3; i++)
+ 8000c66:	3c01      	subs	r4, #1
+		HAL_Delay(300);
+ 8000c68:	0040      	lsls	r0, r0, #1
+ 8000c6a:	f001 fe3f 	bl	80028ec <HAL_Delay>
+	for (int i = 0; i < 3; i++)
+ 8000c6e:	2c00      	cmp	r4, #0
+ 8000c70:	d1ea      	bne.n	8000c48 <identify_feeder+0x4>
+}
+ 8000c72:	bd10      	pop	{r4, pc}
+
+08000c74 <show_version>:
+	set_LED(0, 1, 0);
+ 8000c74:	2200      	movs	r2, #0
+{
+ 8000c76:	b510      	push	{r4, lr}
+	set_LED(0, 1, 0);
+ 8000c78:	0010      	movs	r0, r2
+ 8000c7a:	2101      	movs	r1, #1
+ 8000c7c:	f7ff ff0e 	bl	8000a9c <set_LED>
+	HAL_Delay(250);
+ 8000c80:	20fa      	movs	r0, #250	@ 0xfa
+ 8000c82:	f001 fe33 	bl	80028ec <HAL_Delay>
+	set_LED(0, 0, 0);
+ 8000c86:	2200      	movs	r2, #0
+ 8000c88:	0010      	movs	r0, r2
+ 8000c8a:	0011      	movs	r1, r2
+ 8000c8c:	f7ff ff06 	bl	8000a9c <set_LED>
+	HAL_Delay(250);
+ 8000c90:	20fa      	movs	r0, #250	@ 0xfa
+ 8000c92:	f001 fe2b 	bl	80028ec <HAL_Delay>
+}
+ 8000c96:	bd10      	pop	{r4, pc}
+
+08000c98 <start_feed>:
+{
+ 8000c98:	b5f0      	push	{r4, r5, r6, r7, lr}
+	if (feed_state != FEED_STATE_IDLE)
+ 8000c9a:	4b2a      	ldr	r3, [pc, #168]	@ (8000d44 <start_feed+0xac>)
+{
+ 8000c9c:	b085      	sub	sp, #20
+	if (feed_state != FEED_STATE_IDLE)
+ 8000c9e:	9301      	str	r3, [sp, #4]
+ 8000ca0:	781b      	ldrb	r3, [r3, #0]
+{
+ 8000ca2:	0004      	movs	r4, r0
+ 8000ca4:	9102      	str	r1, [sp, #8]
+	if (feed_state != FEED_STATE_IDLE)
+ 8000ca6:	b2da      	uxtb	r2, r3
+ 8000ca8:	2b00      	cmp	r3, #0
+ 8000caa:	d13c      	bne.n	8000d26 <start_feed+0x8e>
+	feed_in_progress = 1;
+ 8000cac:	2501      	movs	r5, #1
+	feed_distance_tenths = distance_tenths;
+ 8000cae:	4b26      	ldr	r3, [pc, #152]	@ (8000d48 <start_feed+0xb0>)
+ 8000cb0:	8018      	strh	r0, [r3, #0]
+	feed_direction = forward;
+ 8000cb2:	4b26      	ldr	r3, [pc, #152]	@ (8000d4c <start_feed+0xb4>)
+	set_LED(1, 1, 1); // White during feed
+ 8000cb4:	0028      	movs	r0, r5
+	feed_direction = forward;
+ 8000cb6:	7019      	strb	r1, [r3, #0]
+	feed_retry_count = 0;
+ 8000cb8:	4b25      	ldr	r3, [pc, #148]	@ (8000d50 <start_feed+0xb8>)
+	set_LED(1, 1, 1); // White during feed
+ 8000cba:	0029      	movs	r1, r5
+	feed_retry_count = 0;
+ 8000cbc:	701a      	strb	r2, [r3, #0]
+	feed_in_progress = 1;
+ 8000cbe:	4b25      	ldr	r3, [pc, #148]	@ (8000d54 <start_feed+0xbc>)
+ 8000cc0:	701d      	strb	r5, [r3, #0]
+	last_feed_status = STATUS_OK;
+ 8000cc2:	4b25      	ldr	r3, [pc, #148]	@ (8000d58 <start_feed+0xc0>)
+ 8000cc4:	701a      	strb	r2, [r3, #0]
+	set_LED(1, 1, 1); // White during feed
+ 8000cc6:	002a      	movs	r2, r5
+ 8000cc8:	f7ff fee8 	bl	8000a9c <set_LED>
+	if (forward)
+ 8000ccc:	4b23      	ldr	r3, [pc, #140]	@ (8000d5c <start_feed+0xc4>)
+ 8000cce:	4f24      	ldr	r7, [pc, #144]	@ (8000d60 <start_feed+0xc8>)
+ 8000cd0:	9303      	str	r3, [sp, #12]
+ 8000cd2:	9b02      	ldr	r3, [sp, #8]
+ 8000cd4:	4e23      	ldr	r6, [pc, #140]	@ (8000d64 <start_feed+0xcc>)
+ 8000cd6:	2b00      	cmp	r3, #0
+ 8000cd8:	d027      	beq.n	8000d2a <start_feed+0x92>
+		feed_state = FEED_STATE_PEEL_FORWARD;
+ 8000cda:	9b01      	ldr	r3, [sp, #4]
+ 8000cdc:	701d      	strb	r5, [r3, #0]
+		feed_state_start_time = HAL_GetTick();
+ 8000cde:	f001 fdff 	bl	80028e0 <HAL_GetTick>
+		feed_state_duration = distance_tenths * PEEL_TIME_PER_TENTH_MM;
+ 8000ce2:	2312      	movs	r3, #18
+ 8000ce4:	4363      	muls	r3, r4
+ 8000ce6:	6033      	str	r3, [r6, #0]
+	peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
+ 8000ce8:	2396      	movs	r3, #150	@ 0x96
+ 8000cea:	9a03      	ldr	r2, [sp, #12]
+ 8000cec:	011b      	lsls	r3, r3, #4
+ 8000cee:	8013      	strh	r3, [r2, #0]
+		feed_state_start_time = HAL_GetTick();
+ 8000cf0:	6038      	str	r0, [r7, #0]
+		feed_timeout_time = HAL_GetTick() + (distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
+ 8000cf2:	f001 fdf5 	bl	80028e0 <HAL_GetTick>
+ 8000cf6:	2364      	movs	r3, #100	@ 0x64
+ 8000cf8:	4363      	muls	r3, r4
+ 8000cfa:	33f5      	adds	r3, #245	@ 0xf5
+ 8000cfc:	4a1a      	ldr	r2, [pc, #104]	@ (8000d68 <start_feed+0xd0>)
+ 8000cfe:	33ff      	adds	r3, #255	@ 0xff
+ 8000d00:	181b      	adds	r3, r3, r0
+ 8000d02:	6013      	str	r3, [r2, #0]
+	int64_t temp = ((int64_t)tenths * 100 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV;
+ 8000d04:	0020      	movs	r0, r4
+ 8000d06:	2300      	movs	r3, #0
+ 8000d08:	4a18      	ldr	r2, [pc, #96]	@ (8000d6c <start_feed+0xd4>)
+ 8000d0a:	17e1      	asrs	r1, r4, #31
+ 8000d0c:	f7ff fbaa 	bl	8000464 <__aeabi_lmul>
+ 8000d10:	2300      	movs	r3, #0
+ 8000d12:	4a17      	ldr	r2, [pc, #92]	@ (8000d70 <start_feed+0xd8>)
+ 8000d14:	f7ff fb82 	bl	800041c <__aeabi_ldivmod>
+		feed_target_position = total_count + tenths_to_counts(distance_tenths);
+ 8000d18:	4b16      	ldr	r3, [pc, #88]	@ (8000d74 <start_feed+0xdc>)
+ 8000d1a:	681b      	ldr	r3, [r3, #0]
+ 8000d1c:	1818      	adds	r0, r3, r0
+ 8000d1e:	4b16      	ldr	r3, [pc, #88]	@ (8000d78 <start_feed+0xe0>)
+ 8000d20:	6018      	str	r0, [r3, #0]
+		target_count = feed_target_position;
+ 8000d22:	4b16      	ldr	r3, [pc, #88]	@ (8000d7c <start_feed+0xe4>)
+ 8000d24:	6018      	str	r0, [r3, #0]
+}
+ 8000d26:	b005      	add	sp, #20
+ 8000d28:	bdf0      	pop	{r4, r5, r6, r7, pc}
+		feed_state = FEED_STATE_UNPEEL;
+ 8000d2a:	2303      	movs	r3, #3
+ 8000d2c:	9a01      	ldr	r2, [sp, #4]
+ 8000d2e:	7013      	strb	r3, [r2, #0]
+		feed_state_start_time = HAL_GetTick();
+ 8000d30:	f001 fdd6 	bl	80028e0 <HAL_GetTick>
+		feed_state_duration = distance_tenths * BACKWARDS_PEEL_TIME_PER_TENTH_MM;
+ 8000d34:	231e      	movs	r3, #30
+ 8000d36:	4363      	muls	r3, r4
+	peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
+ 8000d38:	9a03      	ldr	r2, [sp, #12]
+		feed_state_duration = distance_tenths * BACKWARDS_PEEL_TIME_PER_TENTH_MM;
+ 8000d3a:	6033      	str	r3, [r6, #0]
+	peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
+ 8000d3c:	4b10      	ldr	r3, [pc, #64]	@ (8000d80 <start_feed+0xe8>)
+		feed_state_start_time = HAL_GetTick();
+ 8000d3e:	6038      	str	r0, [r7, #0]
+	peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
+ 8000d40:	8013      	strh	r3, [r2, #0]
+}
+ 8000d42:	e7f0      	b.n	8000d26 <start_feed+0x8e>
+ 8000d44:	20000118 	.word	0x20000118
+ 8000d48:	20000108 	.word	0x20000108
+ 8000d4c:	20000002 	.word	0x20000002
+ 8000d50:	20000100 	.word	0x20000100
+ 8000d54:	20000121 	.word	0x20000121
+ 8000d58:	20000122 	.word	0x20000122
+ 8000d5c:	200000fe 	.word	0x200000fe
+ 8000d60:	20000114 	.word	0x20000114
+ 8000d64:	20000110 	.word	0x20000110
+ 8000d68:	2000010c 	.word	0x2000010c
+ 8000d6c:	002c01a0 	.word	0x002c01a0
+ 8000d70:	0001f377 	.word	0x0001f377
+ 8000d74:	20000154 	.word	0x20000154
+ 8000d78:	20000104 	.word	0x20000104
+ 8000d7c:	20000150 	.word	0x20000150
+ 8000d80:	fffff6a0 	.word	0xfffff6a0
+
+08000d84 <feed_state_machine_update>:
+{
+ 8000d84:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+	if (feed_state == FEED_STATE_IDLE)
+ 8000d86:	4ea6      	ldr	r6, [pc, #664]	@ (8001020 <feed_state_machine_update+0x29c>)
+ 8000d88:	7833      	ldrb	r3, [r6, #0]
+ 8000d8a:	2b00      	cmp	r3, #0
+ 8000d8c:	d01f      	beq.n	8000dce <feed_state_machine_update+0x4a>
+	uint32_t now = HAL_GetTick();
+ 8000d8e:	f001 fda7 	bl	80028e0 <HAL_GetTick>
+	uint32_t elapsed = now - feed_state_start_time;
+ 8000d92:	4da4      	ldr	r5, [pc, #656]	@ (8001024 <feed_state_machine_update+0x2a0>)
+	uint32_t now = HAL_GetTick();
+ 8000d94:	0004      	movs	r4, r0
+	uint32_t elapsed = now - feed_state_start_time;
+ 8000d96:	682b      	ldr	r3, [r5, #0]
+ 8000d98:	1ac3      	subs	r3, r0, r3
+	switch (feed_state)
+ 8000d9a:	7830      	ldrb	r0, [r6, #0]
+ 8000d9c:	3801      	subs	r0, #1
+ 8000d9e:	2808      	cmp	r0, #8
+ 8000da0:	d900      	bls.n	8000da4 <feed_state_machine_update+0x20>
+ 8000da2:	e135      	b.n	8001010 <feed_state_machine_update+0x28c>
+ 8000da4:	f7ff f9ba 	bl	800011c <__gnu_thumb1_case_uhi>
+ 8000da8:	01340009 	.word	0x01340009
+ 8000dac:	003a0014 	.word	0x003a0014
+ 8000db0:	00c700af 	.word	0x00c700af
+ 8000db4:	00e500de 	.word	0x00e500de
+ 8000db8:	00f4      	.short	0x00f4
+			if (elapsed >= feed_state_duration)
+ 8000dba:	4a9b      	ldr	r2, [pc, #620]	@ (8001028 <feed_state_machine_update+0x2a4>)
+ 8000dbc:	6812      	ldr	r2, [r2, #0]
+ 8000dbe:	4293      	cmp	r3, r2
+ 8000dc0:	d305      	bcc.n	8000dce <feed_state_machine_update+0x4a>
+	peel_target_pwm = 0;
+ 8000dc2:	2200      	movs	r2, #0
+ 8000dc4:	4b99      	ldr	r3, [pc, #612]	@ (800102c <feed_state_machine_update+0x2a8>)
+				feed_state_start_time = now;
+ 8000dc6:	602c      	str	r4, [r5, #0]
+	peel_target_pwm = 0;
+ 8000dc8:	801a      	strh	r2, [r3, #0]
+				feed_state = FEED_STATE_DRIVING;
+ 8000dca:	2304      	movs	r3, #4
+ 8000dcc:	7033      	strb	r3, [r6, #0]
+}
+ 8000dce:	bdf7      	pop	{r0, r1, r2, r4, r5, r6, r7, pc}
+			if (elapsed >= feed_state_duration)
+ 8000dd0:	4a95      	ldr	r2, [pc, #596]	@ (8001028 <feed_state_machine_update+0x2a4>)
+ 8000dd2:	6812      	ldr	r2, [r2, #0]
+ 8000dd4:	4293      	cmp	r3, r2
+ 8000dd6:	d3fa      	bcc.n	8000dce <feed_state_machine_update+0x4a>
+	peel_target_pwm = 0;
+ 8000dd8:	2200      	movs	r2, #0
+ 8000dda:	4b94      	ldr	r3, [pc, #592]	@ (800102c <feed_state_machine_update+0x2a8>)
+				feed_state_start_time = now;
+ 8000ddc:	602c      	str	r4, [r5, #0]
+	peel_target_pwm = 0;
+ 8000dde:	801a      	strh	r2, [r3, #0]
+				feed_state = FEED_STATE_DRIVING;
+ 8000de0:	2304      	movs	r3, #4
+ 8000de2:	7033      	strb	r3, [r6, #0]
+				int16_t total_backward = feed_distance_tenths + BACKLASH_COMP_TENTH_MM;
+ 8000de4:	4b92      	ldr	r3, [pc, #584]	@ (8001030 <feed_state_machine_update+0x2ac>)
+				feed_timeout_time = now + (total_backward * TIMEOUT_TIME_PER_TENTH_MM) + 500;
+ 8000de6:	4a93      	ldr	r2, [pc, #588]	@ (8001034 <feed_state_machine_update+0x2b0>)
+				int16_t total_backward = feed_distance_tenths + BACKLASH_COMP_TENTH_MM;
+ 8000de8:	8818      	ldrh	r0, [r3, #0]
+				feed_timeout_time = now + (total_backward * TIMEOUT_TIME_PER_TENTH_MM) + 500;
+ 8000dea:	2364      	movs	r3, #100	@ 0x64
+				int16_t total_backward = feed_distance_tenths + BACKLASH_COMP_TENTH_MM;
+ 8000dec:	300a      	adds	r0, #10
+ 8000dee:	b200      	sxth	r0, r0
+				feed_timeout_time = now + (total_backward * TIMEOUT_TIME_PER_TENTH_MM) + 500;
+ 8000df0:	4343      	muls	r3, r0
+ 8000df2:	33f5      	adds	r3, #245	@ 0xf5
+ 8000df4:	33ff      	adds	r3, #255	@ 0xff
+ 8000df6:	191b      	adds	r3, r3, r4
+ 8000df8:	6013      	str	r3, [r2, #0]
+	int64_t temp = ((int64_t)tenths * 100 * GEAR_RATIO * ENCODER_CPR) / UM_PER_REV;
+ 8000dfa:	17c1      	asrs	r1, r0, #31
+ 8000dfc:	2300      	movs	r3, #0
+ 8000dfe:	4a8e      	ldr	r2, [pc, #568]	@ (8001038 <feed_state_machine_update+0x2b4>)
+ 8000e00:	f7ff fb30 	bl	8000464 <__aeabi_lmul>
+ 8000e04:	2300      	movs	r3, #0
+ 8000e06:	4a8d      	ldr	r2, [pc, #564]	@ (800103c <feed_state_machine_update+0x2b8>)
+ 8000e08:	f7ff fb08 	bl	800041c <__aeabi_ldivmod>
+				feed_target_position = total_count - tenths_to_counts(total_backward);
+ 8000e0c:	4c8c      	ldr	r4, [pc, #560]	@ (8001040 <feed_state_machine_update+0x2bc>)
+ 8000e0e:	6823      	ldr	r3, [r4, #0]
+ 8000e10:	1a18      	subs	r0, r3, r0
+ 8000e12:	4b8c      	ldr	r3, [pc, #560]	@ (8001044 <feed_state_machine_update+0x2c0>)
+ 8000e14:	6018      	str	r0, [r3, #0]
+				target_count = feed_target_position;
+ 8000e16:	4b8c      	ldr	r3, [pc, #560]	@ (8001048 <feed_state_machine_update+0x2c4>)
+ 8000e18:	6018      	str	r0, [r3, #0]
+ 8000e1a:	e7d8      	b.n	8000dce <feed_state_machine_update+0x4a>
+				int32_t error = feed_target_position - total_count;
+ 8000e1c:	4b88      	ldr	r3, [pc, #544]	@ (8001040 <feed_state_machine_update+0x2bc>)
+ 8000e1e:	4f89      	ldr	r7, [pc, #548]	@ (8001044 <feed_state_machine_update+0x2c0>)
+ 8000e20:	681a      	ldr	r2, [r3, #0]
+ 8000e22:	683b      	ldr	r3, [r7, #0]
+ 8000e24:	1a9b      	subs	r3, r3, r2
+				int32_t abs_error = error < 0 ? -error : error;
+ 8000e26:	17d8      	asrs	r0, r3, #31
+ 8000e28:	1819      	adds	r1, r3, r0
+ 8000e2a:	4041      	eors	r1, r0
+				int32_t brake_adj = abs_error >= 20 ? 20 : abs_error >= 10 ? 10 : abs_error >= 5 ? 5 : 0;
+ 8000e2c:	2913      	cmp	r1, #19
+ 8000e2e:	dc2e      	bgt.n	8000e8e <feed_state_machine_update+0x10a>
+ 8000e30:	2909      	cmp	r1, #9
+ 8000e32:	dc59      	bgt.n	8000ee8 <feed_state_machine_update+0x164>
+ 8000e34:	2904      	cmp	r1, #4
+ 8000e36:	dd00      	ble.n	8000e3a <feed_state_machine_update+0xb6>
+ 8000e38:	e0ec      	b.n	8001014 <feed_state_machine_update+0x290>
+					if (error < 0) // overshot
+ 8000e3a:	2b00      	cmp	r3, #0
+ 8000e3c:	da14      	bge.n	8000e68 <feed_state_machine_update+0xe4>
+ 8000e3e:	2300      	movs	r3, #0
+						brake_time_tenths += brake_adj;
+ 8000e40:	4a82      	ldr	r2, [pc, #520]	@ (800104c <feed_state_machine_update+0x2c8>)
+ 8000e42:	6811      	ldr	r1, [r2, #0]
+ 8000e44:	185b      	adds	r3, r3, r1
+ 8000e46:	6013      	str	r3, [r2, #0]
+					if (!feed_direction)
+ 8000e48:	4b81      	ldr	r3, [pc, #516]	@ (8001050 <feed_state_machine_update+0x2cc>)
+ 8000e4a:	781a      	ldrb	r2, [r3, #0]
+ 8000e4c:	4b76      	ldr	r3, [pc, #472]	@ (8001028 <feed_state_machine_update+0x2a4>)
+ 8000e4e:	2a00      	cmp	r2, #0
+ 8000e50:	d117      	bne.n	8000e82 <feed_state_machine_update+0xfe>
+						feed_state = FEED_STATE_SLACK_REMOVAL;
+ 8000e52:	3205      	adds	r2, #5
+ 8000e54:	7032      	strb	r2, [r6, #0]
+						feed_state_duration = BACKWARDS_FEED_FILM_SLACK_REMOVAL_TIME;
+ 8000e56:	325a      	adds	r2, #90	@ 0x5a
+ 8000e58:	32ff      	adds	r2, #255	@ 0xff
+ 8000e5a:	601a      	str	r2, [r3, #0]
+	peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
+ 8000e5c:	2296      	movs	r2, #150	@ 0x96
+ 8000e5e:	4b73      	ldr	r3, [pc, #460]	@ (800102c <feed_state_machine_update+0x2a8>)
+ 8000e60:	0112      	lsls	r2, r2, #4
+						feed_state_start_time = now;
+ 8000e62:	602c      	str	r4, [r5, #0]
+	peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
+ 8000e64:	801a      	strh	r2, [r3, #0]
+}
+ 8000e66:	e7b2      	b.n	8000dce <feed_state_machine_update+0x4a>
+					else if (error > 0 && brake_time_tenths > brake_adj) // undershot
+ 8000e68:	2b00      	cmp	r3, #0
+ 8000e6a:	d0ed      	beq.n	8000e48 <feed_state_machine_update+0xc4>
+ 8000e6c:	2200      	movs	r2, #0
+ 8000e6e:	4b77      	ldr	r3, [pc, #476]	@ (800104c <feed_state_machine_update+0x2c8>)
+ 8000e70:	6819      	ldr	r1, [r3, #0]
+ 8000e72:	4291      	cmp	r1, r2
+ 8000e74:	dd03      	ble.n	8000e7e <feed_state_machine_update+0xfa>
+						brake_time_tenths -= brake_adj;
+ 8000e76:	6819      	ldr	r1, [r3, #0]
+ 8000e78:	1a8a      	subs	r2, r1, r2
+						brake_time_tenths = 1;
+ 8000e7a:	601a      	str	r2, [r3, #0]
+ 8000e7c:	e7e4      	b.n	8000e48 <feed_state_machine_update+0xc4>
+ 8000e7e:	2201      	movs	r2, #1
+ 8000e80:	e7fb      	b.n	8000e7a <feed_state_machine_update+0xf6>
+						feed_state = FEED_STATE_SETTLING;
+ 8000e82:	2207      	movs	r2, #7
+						feed_state_start_time = now;
+ 8000e84:	602c      	str	r4, [r5, #0]
+						feed_state = FEED_STATE_SETTLING;
+ 8000e86:	7032      	strb	r2, [r6, #0]
+					feed_state_duration = FEED_SETTLE_TIME;
+ 8000e88:	2232      	movs	r2, #50	@ 0x32
+ 8000e8a:	601a      	str	r2, [r3, #0]
+ 8000e8c:	e79f      	b.n	8000dce <feed_state_machine_update+0x4a>
+				int32_t brake_adj = abs_error >= 20 ? 20 : abs_error >= 10 ? 10 : abs_error >= 5 ? 5 : 0;
+ 8000e8e:	2114      	movs	r1, #20
+				else if (error < -FEED_POSITION_TOLERANCE)
+ 8000e90:	4e68      	ldr	r6, [pc, #416]	@ (8001034 <feed_state_machine_update+0x2b0>)
+ 8000e92:	330a      	adds	r3, #10
+ 8000e94:	da2a      	bge.n	8000eec <feed_state_machine_update+0x168>
+					brake_time_tenths += brake_adj;
+ 8000e96:	486d      	ldr	r0, [pc, #436]	@ (800104c <feed_state_machine_update+0x2c8>)
+ 8000e98:	6803      	ldr	r3, [r0, #0]
+ 8000e9a:	185b      	adds	r3, r3, r1
+					feed_retry_total++;
+ 8000e9c:	496d      	ldr	r1, [pc, #436]	@ (8001054 <feed_state_machine_update+0x2d0>)
+					else brake_time_tenths = 1;
+ 8000e9e:	6003      	str	r3, [r0, #0]
+					feed_retry_total++;
+ 8000ea0:	880b      	ldrh	r3, [r1, #0]
+					target_count = total_count - tenths_to_counts(10);
+ 8000ea2:	3ae1      	subs	r2, #225	@ 0xe1
+					feed_retry_total++;
+ 8000ea4:	3301      	adds	r3, #1
+ 8000ea6:	b29b      	uxth	r3, r3
+ 8000ea8:	800b      	strh	r3, [r1, #0]
+					target_count = total_count - tenths_to_counts(10);
+ 8000eaa:	4b67      	ldr	r3, [pc, #412]	@ (8001048 <feed_state_machine_update+0x2c4>)
+					HAL_Delay(200);
+ 8000eac:	20c8      	movs	r0, #200	@ 0xc8
+					target_count = total_count - tenths_to_counts(10);
+ 8000eae:	601a      	str	r2, [r3, #0]
+ 8000eb0:	9301      	str	r3, [sp, #4]
+					HAL_Delay(200);
+ 8000eb2:	f001 fd1b 	bl	80028ec <HAL_Delay>
+					htim1.Instance->CCR1 = PWM_MAX;
+ 8000eb6:	2296      	movs	r2, #150	@ 0x96
+ 8000eb8:	4b67      	ldr	r3, [pc, #412]	@ (8001058 <feed_state_machine_update+0x2d4>)
+ 8000eba:	0112      	lsls	r2, r2, #4
+ 8000ebc:	681b      	ldr	r3, [r3, #0]
+					HAL_Delay(50);
+ 8000ebe:	2032      	movs	r0, #50	@ 0x32
+					htim1.Instance->CCR1 = PWM_MAX;
+ 8000ec0:	635a      	str	r2, [r3, #52]	@ 0x34
+					htim1.Instance->CCR2 = PWM_MAX;
+ 8000ec2:	639a      	str	r2, [r3, #56]	@ 0x38
+					HAL_Delay(50);
+ 8000ec4:	f001 fd12 	bl	80028ec <HAL_Delay>
+					target_count = feed_target_position;
+ 8000ec8:	683b      	ldr	r3, [r7, #0]
+ 8000eca:	9a01      	ldr	r2, [sp, #4]
+					feed_state_start_time = now;
+ 8000ecc:	602c      	str	r4, [r5, #0]
+					target_count = feed_target_position;
+ 8000ece:	6013      	str	r3, [r2, #0]
+					feed_timeout_time = HAL_GetTick() + (feed_distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
+ 8000ed0:	f001 fd06 	bl	80028e0 <HAL_GetTick>
+ 8000ed4:	4b56      	ldr	r3, [pc, #344]	@ (8001030 <feed_state_machine_update+0x2ac>)
+ 8000ed6:	2200      	movs	r2, #0
+ 8000ed8:	5e9a      	ldrsh	r2, [r3, r2]
+ 8000eda:	2364      	movs	r3, #100	@ 0x64
+ 8000edc:	4353      	muls	r3, r2
+ 8000ede:	33f5      	adds	r3, #245	@ 0xf5
+ 8000ee0:	33ff      	adds	r3, #255	@ 0xff
+ 8000ee2:	181b      	adds	r3, r3, r0
+ 8000ee4:	6033      	str	r3, [r6, #0]
+ 8000ee6:	e772      	b.n	8000dce <feed_state_machine_update+0x4a>
+				int32_t brake_adj = abs_error >= 20 ? 20 : abs_error >= 10 ? 10 : abs_error >= 5 ? 5 : 0;
+ 8000ee8:	210a      	movs	r1, #10
+ 8000eea:	e7d1      	b.n	8000e90 <feed_state_machine_update+0x10c>
+				else if (now > feed_timeout_time)
+ 8000eec:	6833      	ldr	r3, [r6, #0]
+ 8000eee:	429c      	cmp	r4, r3
+ 8000ef0:	d800      	bhi.n	8000ef4 <feed_state_machine_update+0x170>
+ 8000ef2:	e76c      	b.n	8000dce <feed_state_machine_update+0x4a>
+					if (brake_time_tenths > brake_adj) brake_time_tenths -= brake_adj;
+ 8000ef4:	4855      	ldr	r0, [pc, #340]	@ (800104c <feed_state_machine_update+0x2c8>)
+ 8000ef6:	6803      	ldr	r3, [r0, #0]
+ 8000ef8:	4299      	cmp	r1, r3
+ 8000efa:	da02      	bge.n	8000f02 <feed_state_machine_update+0x17e>
+ 8000efc:	6803      	ldr	r3, [r0, #0]
+ 8000efe:	1a5b      	subs	r3, r3, r1
+ 8000f00:	e7cc      	b.n	8000e9c <feed_state_machine_update+0x118>
+					else brake_time_tenths = 1;
+ 8000f02:	2301      	movs	r3, #1
+ 8000f04:	e7ca      	b.n	8000e9c <feed_state_machine_update+0x118>
+			if (elapsed >= feed_state_duration)
+ 8000f06:	4a48      	ldr	r2, [pc, #288]	@ (8001028 <feed_state_machine_update+0x2a4>)
+ 8000f08:	6812      	ldr	r2, [r2, #0]
+ 8000f0a:	4293      	cmp	r3, r2
+ 8000f0c:	d200      	bcs.n	8000f10 <feed_state_machine_update+0x18c>
+ 8000f0e:	e75e      	b.n	8000dce <feed_state_machine_update+0x4a>
+	peel_target_pwm = 0;
+ 8000f10:	2200      	movs	r2, #0
+ 8000f12:	4b46      	ldr	r3, [pc, #280]	@ (800102c <feed_state_machine_update+0x2a8>)
+				feed_state_start_time = now;
+ 8000f14:	602c      	str	r4, [r5, #0]
+	peel_target_pwm = 0;
+ 8000f16:	801a      	strh	r2, [r3, #0]
+				feed_state = FEED_STATE_DRIVING_BACKLASH;
+ 8000f18:	2306      	movs	r3, #6
+				feed_timeout_time = now + (BACKLASH_COMP_TENTH_MM * TIMEOUT_TIME_PER_TENTH_MM) + 200;
+ 8000f1a:	2296      	movs	r2, #150	@ 0x96
+				feed_state = FEED_STATE_DRIVING_BACKLASH;
+ 8000f1c:	7033      	strb	r3, [r6, #0]
+				feed_timeout_time = now + (BACKLASH_COMP_TENTH_MM * TIMEOUT_TIME_PER_TENTH_MM) + 200;
+ 8000f1e:	00d2      	lsls	r2, r2, #3
+ 8000f20:	4b44      	ldr	r3, [pc, #272]	@ (8001034 <feed_state_machine_update+0x2b0>)
+ 8000f22:	18a4      	adds	r4, r4, r2
+ 8000f24:	601c      	str	r4, [r3, #0]
+				feed_target_position = total_count + tenths_to_counts(BACKLASH_COMP_TENTH_MM);
+ 8000f26:	4b46      	ldr	r3, [pc, #280]	@ (8001040 <feed_state_machine_update+0x2bc>)
+ 8000f28:	4a46      	ldr	r2, [pc, #280]	@ (8001044 <feed_state_machine_update+0x2c0>)
+ 8000f2a:	681b      	ldr	r3, [r3, #0]
+ 8000f2c:	33e1      	adds	r3, #225	@ 0xe1
+ 8000f2e:	6013      	str	r3, [r2, #0]
+				target_count = feed_target_position;
+ 8000f30:	4a45      	ldr	r2, [pc, #276]	@ (8001048 <feed_state_machine_update+0x2c4>)
+				feed_timeout_time = HAL_GetTick() + (feed_distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
+ 8000f32:	6013      	str	r3, [r2, #0]
+ 8000f34:	e74b      	b.n	8000dce <feed_state_machine_update+0x4a>
+				int32_t error = feed_target_position - total_count;
+ 8000f36:	4b43      	ldr	r3, [pc, #268]	@ (8001044 <feed_state_machine_update+0x2c0>)
+ 8000f38:	4a41      	ldr	r2, [pc, #260]	@ (8001040 <feed_state_machine_update+0x2bc>)
+ 8000f3a:	681b      	ldr	r3, [r3, #0]
+ 8000f3c:	6812      	ldr	r2, [r2, #0]
+ 8000f3e:	1a9b      	subs	r3, r3, r2
+				if (error < 0) error = -error;
+ 8000f40:	17da      	asrs	r2, r3, #31
+ 8000f42:	189b      	adds	r3, r3, r2
+ 8000f44:	4053      	eors	r3, r2
+				if (error < FEED_POSITION_TOLERANCE)
+ 8000f46:	2b09      	cmp	r3, #9
+ 8000f48:	dc04      	bgt.n	8000f54 <feed_state_machine_update+0x1d0>
+					feed_state = FEED_STATE_SETTLING;
+ 8000f4a:	2307      	movs	r3, #7
+					feed_state_start_time = now;
+ 8000f4c:	602c      	str	r4, [r5, #0]
+					feed_state = FEED_STATE_SETTLING;
+ 8000f4e:	7033      	strb	r3, [r6, #0]
+					feed_state_duration = FEED_SETTLE_TIME;
+ 8000f50:	4b35      	ldr	r3, [pc, #212]	@ (8001028 <feed_state_machine_update+0x2a4>)
+ 8000f52:	e799      	b.n	8000e88 <feed_state_machine_update+0x104>
+				else if (now > feed_timeout_time)
+ 8000f54:	4b37      	ldr	r3, [pc, #220]	@ (8001034 <feed_state_machine_update+0x2b0>)
+ 8000f56:	681b      	ldr	r3, [r3, #0]
+ 8000f58:	429c      	cmp	r4, r3
+ 8000f5a:	d800      	bhi.n	8000f5e <feed_state_machine_update+0x1da>
+ 8000f5c:	e737      	b.n	8000dce <feed_state_machine_update+0x4a>
+					feed_state = FEED_STATE_TIMEOUT;
+ 8000f5e:	2309      	movs	r3, #9
+			feed_state = FEED_STATE_IDLE;
+ 8000f60:	7033      	strb	r3, [r6, #0]
+			break;
+ 8000f62:	e734      	b.n	8000dce <feed_state_machine_update+0x4a>
+			if (elapsed >= feed_state_duration)
+ 8000f64:	4a30      	ldr	r2, [pc, #192]	@ (8001028 <feed_state_machine_update+0x2a4>)
+ 8000f66:	6812      	ldr	r2, [r2, #0]
+ 8000f68:	4293      	cmp	r3, r2
+ 8000f6a:	d200      	bcs.n	8000f6e <feed_state_machine_update+0x1ea>
+ 8000f6c:	e72f      	b.n	8000dce <feed_state_machine_update+0x4a>
+				feed_state = FEED_STATE_COMPLETE;
+ 8000f6e:	2308      	movs	r3, #8
+ 8000f70:	e7f6      	b.n	8000f60 <feed_state_machine_update+0x1dc>
+			feed_state = FEED_STATE_IDLE;
+ 8000f72:	2300      	movs	r3, #0
+			feed_in_progress = 0;
+ 8000f74:	4a39      	ldr	r2, [pc, #228]	@ (800105c <feed_state_machine_update+0x2d8>)
+			feed_state = FEED_STATE_IDLE;
+ 8000f76:	7033      	strb	r3, [r6, #0]
+			feed_in_progress = 0;
+ 8000f78:	7013      	strb	r3, [r2, #0]
+			last_feed_status = STATUS_OK;
+ 8000f7a:	4a39      	ldr	r2, [pc, #228]	@ (8001060 <feed_state_machine_update+0x2dc>)
+ 8000f7c:	7013      	strb	r3, [r2, #0]
+			feed_just_completed = 1;
+ 8000f7e:	2201      	movs	r2, #1
+ 8000f80:	4b38      	ldr	r3, [pc, #224]	@ (8001064 <feed_state_machine_update+0x2e0>)
+ 8000f82:	701a      	strb	r2, [r3, #0]
+			feed_ok_count++;
+ 8000f84:	4a38      	ldr	r2, [pc, #224]	@ (8001068 <feed_state_machine_update+0x2e4>)
+ 8000f86:	8813      	ldrh	r3, [r2, #0]
+ 8000f88:	3301      	adds	r3, #1
+ 8000f8a:	b29b      	uxth	r3, r3
+ 8000f8c:	8013      	strh	r3, [r2, #0]
+			break;
+ 8000f8e:	e71e      	b.n	8000dce <feed_state_machine_update+0x4a>
+			if (feed_retry_count < FEED_RETRY_LIMIT)
+ 8000f90:	4a36      	ldr	r2, [pc, #216]	@ (800106c <feed_state_machine_update+0x2e8>)
+ 8000f92:	7813      	ldrb	r3, [r2, #0]
+ 8000f94:	2b02      	cmp	r3, #2
+ 8000f96:	d829      	bhi.n	8000fec <feed_state_machine_update+0x268>
+				feed_retry_count++;
+ 8000f98:	3301      	adds	r3, #1
+ 8000f9a:	7013      	strb	r3, [r2, #0]
+				feed_retry_total++;
+ 8000f9c:	4a2d      	ldr	r2, [pc, #180]	@ (8001054 <feed_state_machine_update+0x2d0>)
+				target_count = total_count - tenths_to_counts(10);
+ 8000f9e:	4f2a      	ldr	r7, [pc, #168]	@ (8001048 <feed_state_machine_update+0x2c4>)
+				feed_retry_total++;
+ 8000fa0:	8813      	ldrh	r3, [r2, #0]
+				HAL_Delay(200); // Let motor reverse past backlash
+ 8000fa2:	20c8      	movs	r0, #200	@ 0xc8
+				feed_retry_total++;
+ 8000fa4:	3301      	adds	r3, #1
+ 8000fa6:	b29b      	uxth	r3, r3
+ 8000fa8:	8013      	strh	r3, [r2, #0]
+				target_count = total_count - tenths_to_counts(10);
+ 8000faa:	4b25      	ldr	r3, [pc, #148]	@ (8001040 <feed_state_machine_update+0x2bc>)
+ 8000fac:	681b      	ldr	r3, [r3, #0]
+ 8000fae:	3be1      	subs	r3, #225	@ 0xe1
+ 8000fb0:	603b      	str	r3, [r7, #0]
+				HAL_Delay(200); // Let motor reverse past backlash
+ 8000fb2:	f001 fc9b 	bl	80028ec <HAL_Delay>
+				htim1.Instance->CCR1 = PWM_MAX;
+ 8000fb6:	2296      	movs	r2, #150	@ 0x96
+ 8000fb8:	4b27      	ldr	r3, [pc, #156]	@ (8001058 <feed_state_machine_update+0x2d4>)
+ 8000fba:	0112      	lsls	r2, r2, #4
+ 8000fbc:	681b      	ldr	r3, [r3, #0]
+				HAL_Delay(50); // Settle
+ 8000fbe:	2032      	movs	r0, #50	@ 0x32
+				htim1.Instance->CCR1 = PWM_MAX;
+ 8000fc0:	635a      	str	r2, [r3, #52]	@ 0x34
+				htim1.Instance->CCR2 = PWM_MAX;
+ 8000fc2:	639a      	str	r2, [r3, #56]	@ 0x38
+				HAL_Delay(50); // Settle
+ 8000fc4:	f001 fc92 	bl	80028ec <HAL_Delay>
+				target_count = feed_target_position;
+ 8000fc8:	4b1e      	ldr	r3, [pc, #120]	@ (8001044 <feed_state_machine_update+0x2c0>)
+				feed_state_start_time = now;
+ 8000fca:	602c      	str	r4, [r5, #0]
+				target_count = feed_target_position;
+ 8000fcc:	681b      	ldr	r3, [r3, #0]
+ 8000fce:	603b      	str	r3, [r7, #0]
+				feed_state = FEED_STATE_DRIVING;
+ 8000fd0:	2304      	movs	r3, #4
+ 8000fd2:	7033      	strb	r3, [r6, #0]
+				feed_timeout_time = HAL_GetTick() + (feed_distance_tenths * TIMEOUT_TIME_PER_TENTH_MM) + 500;
+ 8000fd4:	f001 fc84 	bl	80028e0 <HAL_GetTick>
+ 8000fd8:	4b15      	ldr	r3, [pc, #84]	@ (8001030 <feed_state_machine_update+0x2ac>)
+ 8000fda:	4a16      	ldr	r2, [pc, #88]	@ (8001034 <feed_state_machine_update+0x2b0>)
+ 8000fdc:	2100      	movs	r1, #0
+ 8000fde:	5e59      	ldrsh	r1, [r3, r1]
+ 8000fe0:	2364      	movs	r3, #100	@ 0x64
+ 8000fe2:	434b      	muls	r3, r1
+ 8000fe4:	33f5      	adds	r3, #245	@ 0xf5
+ 8000fe6:	33ff      	adds	r3, #255	@ 0xff
+ 8000fe8:	181b      	adds	r3, r3, r0
+ 8000fea:	e7a2      	b.n	8000f32 <feed_state_machine_update+0x1ae>
+				feed_state = FEED_STATE_IDLE;
+ 8000fec:	2300      	movs	r3, #0
+				feed_in_progress = 0;
+ 8000fee:	4a1b      	ldr	r2, [pc, #108]	@ (800105c <feed_state_machine_update+0x2d8>)
+				feed_state = FEED_STATE_IDLE;
+ 8000ff0:	7033      	strb	r3, [r6, #0]
+				feed_in_progress = 0;
+ 8000ff2:	7013      	strb	r3, [r2, #0]
+				last_feed_status = STATUS_COULDNT_REACH;
+ 8000ff4:	2202      	movs	r2, #2
+ 8000ff6:	4b1a      	ldr	r3, [pc, #104]	@ (8001060 <feed_state_machine_update+0x2dc>)
+ 8000ff8:	701a      	strb	r2, [r3, #0]
+				feed_just_completed = 1;
+ 8000ffa:	4b1a      	ldr	r3, [pc, #104]	@ (8001064 <feed_state_machine_update+0x2e0>)
+ 8000ffc:	3a01      	subs	r2, #1
+ 8000ffe:	701a      	strb	r2, [r3, #0]
+				feed_fail_count++;
+ 8001000:	4a1b      	ldr	r2, [pc, #108]	@ (8001070 <feed_state_machine_update+0x2ec>)
+ 8001002:	8813      	ldrh	r3, [r2, #0]
+ 8001004:	3301      	adds	r3, #1
+ 8001006:	b29b      	uxth	r3, r3
+ 8001008:	8013      	strh	r3, [r2, #0]
+				halt_all();
+ 800100a:	f7ff fdfb 	bl	8000c04 <halt_all>
+ 800100e:	e6de      	b.n	8000dce <feed_state_machine_update+0x4a>
+			feed_state = FEED_STATE_IDLE;
+ 8001010:	2300      	movs	r3, #0
+ 8001012:	e7a5      	b.n	8000f60 <feed_state_machine_update+0x1dc>
+					if (error < 0) // overshot
+ 8001014:	2205      	movs	r2, #5
+ 8001016:	2b00      	cmp	r3, #0
+ 8001018:	db00      	blt.n	800101c <feed_state_machine_update+0x298>
+ 800101a:	e728      	b.n	8000e6e <feed_state_machine_update+0xea>
+ 800101c:	2305      	movs	r3, #5
+ 800101e:	e70f      	b.n	8000e40 <feed_state_machine_update+0xbc>
+ 8001020:	20000118 	.word	0x20000118
+ 8001024:	20000114 	.word	0x20000114
+ 8001028:	20000110 	.word	0x20000110
+ 800102c:	200000fe 	.word	0x200000fe
+ 8001030:	20000108 	.word	0x20000108
+ 8001034:	2000010c 	.word	0x2000010c
+ 8001038:	002c01a0 	.word	0x002c01a0
+ 800103c:	0001f377 	.word	0x0001f377
+ 8001040:	20000154 	.word	0x20000154
+ 8001044:	20000104 	.word	0x20000104
+ 8001048:	20000150 	.word	0x20000150
+ 800104c:	20000004 	.word	0x20000004
+ 8001050:	20000002 	.word	0x20000002
+ 8001054:	2000011a 	.word	0x2000011a
+ 8001058:	200012b0 	.word	0x200012b0
+ 800105c:	20000121 	.word	0x20000121
+ 8001060:	20000122 	.word	0x20000122
+ 8001064:	20000120 	.word	0x20000120
+ 8001068:	2000011e 	.word	0x2000011e
+ 800106c:	20000100 	.word	0x20000100
+ 8001070:	2000011c 	.word	0x2000011c
+
+08001074 <handle_vendor_options>:
+{
+ 8001074:	b570      	push	{r4, r5, r6, lr}
+	uint8_t command = options[0];
+ 8001076:	7803      	ldrb	r3, [r0, #0]
+{
+ 8001078:	000c      	movs	r4, r1
+	if (command <= 0x0F)
+ 800107a:	2b0f      	cmp	r3, #15
+ 800107c:	d80e      	bhi.n	800109c <handle_vendor_options+0x28>
+		size_t start_index = command * VENDOR_SPECIFIC_OPTIONS_LENGTH;
+ 800107e:	2214      	movs	r2, #20
+ 8001080:	4353      	muls	r3, r2
+		if (start_index < version_len)
+ 8001082:	2b08      	cmp	r3, #8
+ 8001084:	dc1a      	bgt.n	80010bc <handle_vendor_options+0x48>
+			size_t remaining = version_len - start_index;
+ 8001086:	2509      	movs	r5, #9
+			memcpy(response, VERSION_STRING + start_index, copy_len);
+ 8001088:	490f      	ldr	r1, [pc, #60]	@ (80010c8 <handle_vendor_options+0x54>)
+			size_t remaining = version_len - start_index;
+ 800108a:	1aed      	subs	r5, r5, r3
+			memcpy(response, VERSION_STRING + start_index, copy_len);
+ 800108c:	1859      	adds	r1, r3, r1
+ 800108e:	002a      	movs	r2, r5
+ 8001090:	0020      	movs	r0, r4
+ 8001092:	f004 f8a7 	bl	80051e4 <memcpy>
+				response[copy_len] = '\0';
+ 8001096:	2300      	movs	r3, #0
+ 8001098:	5563      	strb	r3, [r4, r5]
+}
+ 800109a:	bd70      	pop	{r4, r5, r6, pc}
+	switch (command)
+ 800109c:	2b10      	cmp	r3, #16
+ 800109e:	d10c      	bne.n	80010ba <handle_vendor_options+0x46>
+			uint8_t led_mask = options[1];
+ 80010a0:	7840      	ldrb	r0, [r0, #1]
+			if (set)
+ 80010a2:	0702      	lsls	r2, r0, #28
+ 80010a4:	d5f9      	bpl.n	800109a <handle_vendor_options+0x26>
+				set_LED(red, green, blue);
+ 80010a6:	2401      	movs	r4, #1
+ 80010a8:	0002      	movs	r2, r0
+			int green = (led_mask >> 1) & 1;
+ 80010aa:	0841      	lsrs	r1, r0, #1
+			int red = (led_mask >> 2) & 1;
+ 80010ac:	0880      	lsrs	r0, r0, #2
+				set_LED(red, green, blue);
+ 80010ae:	4022      	ands	r2, r4
+ 80010b0:	4021      	ands	r1, r4
+ 80010b2:	4020      	ands	r0, r4
+ 80010b4:	f7ff fcf2 	bl	8000a9c <set_LED>
+ 80010b8:	e7ef      	b.n	800109a <handle_vendor_options+0x26>
+			memset(response, 0, VENDOR_SPECIFIC_OPTIONS_LENGTH);
+ 80010ba:	2214      	movs	r2, #20
+ 80010bc:	2100      	movs	r1, #0
+ 80010be:	0020      	movs	r0, r4
+ 80010c0:	f004 f864 	bl	800518c <memset>
+			break;
+ 80010c4:	e7e9      	b.n	800109a <handle_vendor_options+0x26>
+ 80010c6:	46c0      	nop			@ (mov r8, r8)
+ 80010c8:	08005221 	.word	0x08005221
+
+080010cc <onewire_delay_us>:
+	uint32_t cycles = us * 48;
+ 80010cc:	2330      	movs	r3, #48	@ 0x30
+ 80010ce:	4358      	muls	r0, r3
+	uint32_t elapsed = 0;
+ 80010d0:	2300      	movs	r3, #0
+{
+ 80010d2:	b570      	push	{r4, r5, r6, lr}
+	uint32_t reload = SysTick->LOAD;
+ 80010d4:	4c08      	ldr	r4, [pc, #32]	@ (80010f8 <onewire_delay_us+0x2c>)
+ 80010d6:	6865      	ldr	r5, [r4, #4]
+	uint32_t prev = SysTick->VAL;
+ 80010d8:	68a2      	ldr	r2, [r4, #8]
+			elapsed += prev + reload + 1 - now;
+ 80010da:	3501      	adds	r5, #1
+	while (elapsed < cycles)
+ 80010dc:	4283      	cmp	r3, r0
+ 80010de:	d300      	bcc.n	80010e2 <onewire_delay_us+0x16>
+}
+ 80010e0:	bd70      	pop	{r4, r5, r6, pc}
+		uint32_t now = SysTick->VAL;
+ 80010e2:	68a1      	ldr	r1, [r4, #8]
+		if (now <= prev)
+ 80010e4:	428a      	cmp	r2, r1
+ 80010e6:	d303      	bcc.n	80010f0 <onewire_delay_us+0x24>
+			elapsed += prev - now;
+ 80010e8:	18d3      	adds	r3, r2, r3
+ 80010ea:	1a5b      	subs	r3, r3, r1
+{
+ 80010ec:	000a      	movs	r2, r1
+ 80010ee:	e7f5      	b.n	80010dc <onewire_delay_us+0x10>
+			elapsed += prev + reload + 1 - now;
+ 80010f0:	1a6e      	subs	r6, r5, r1
+ 80010f2:	18b2      	adds	r2, r6, r2
+ 80010f4:	189b      	adds	r3, r3, r2
+ 80010f6:	e7f9      	b.n	80010ec <onewire_delay_us+0x20>
+ 80010f8:	e000e010 	.word	0xe000e010
+
+080010fc <onewire_read_bit>:
+	return (ONEWIRE_GPIO_Port->IDR & ONEWIRE_Pin) ? 1 : 0;
+ 80010fc:	23a0      	movs	r3, #160	@ 0xa0
+ 80010fe:	05db      	lsls	r3, r3, #23
+ 8001100:	6918      	ldr	r0, [r3, #16]
+ 8001102:	0640      	lsls	r0, r0, #25
+ 8001104:	0fc0      	lsrs	r0, r0, #31
+}
+ 8001106:	4770      	bx	lr
+
+08001108 <onewire_reset>:
+{
+ 8001108:	b570      	push	{r4, r5, r6, lr}
+	ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
+ 800110a:	24a0      	movs	r4, #160	@ 0xa0
+ 800110c:	2540      	movs	r5, #64	@ 0x40
+	onewire_delay_us(ONEWIRE_DELAY_H); // 480us
+ 800110e:	20f0      	movs	r0, #240	@ 0xf0
+	ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
+ 8001110:	05e4      	lsls	r4, r4, #23
+ 8001112:	62a5      	str	r5, [r4, #40]	@ 0x28
+	onewire_delay_us(ONEWIRE_DELAY_H); // 480us
+ 8001114:	0040      	lsls	r0, r0, #1
+ 8001116:	f7ff ffd9 	bl	80010cc <onewire_delay_us>
+	ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
+ 800111a:	61a5      	str	r5, [r4, #24]
+	onewire_delay_us(ONEWIRE_DELAY_I); // 70us
+ 800111c:	2046      	movs	r0, #70	@ 0x46
+ 800111e:	f7ff ffd5 	bl	80010cc <onewire_delay_us>
+	presence = !onewire_read_bit(); // Device pulls low if present
+ 8001122:	f7ff ffeb 	bl	80010fc <onewire_read_bit>
+ 8001126:	0004      	movs	r4, r0
+	onewire_delay_us(ONEWIRE_DELAY_J); // 410us
+ 8001128:	20cd      	movs	r0, #205	@ 0xcd
+ 800112a:	0040      	lsls	r0, r0, #1
+ 800112c:	f7ff ffce 	bl	80010cc <onewire_delay_us>
+	return presence;
+ 8001130:	2001      	movs	r0, #1
+ 8001132:	4060      	eors	r0, r4
+ 8001134:	b2c0      	uxtb	r0, r0
+}
+ 8001136:	bd70      	pop	{r4, r5, r6, pc}
+
+08001138 <onewire_write_bit>:
+{
+ 8001138:	b570      	push	{r4, r5, r6, lr}
+ 800113a:	25a0      	movs	r5, #160	@ 0xa0
+ 800113c:	2440      	movs	r4, #64	@ 0x40
+ 800113e:	05ed      	lsls	r5, r5, #23
+	ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
+ 8001140:	62ac      	str	r4, [r5, #40]	@ 0x28
+	if (bit)
+ 8001142:	2800      	cmp	r0, #0
+ 8001144:	d007      	beq.n	8001156 <onewire_write_bit+0x1e>
+		onewire_delay_us(ONEWIRE_DELAY_A); // 6us
+ 8001146:	2006      	movs	r0, #6
+ 8001148:	f7ff ffc0 	bl	80010cc <onewire_delay_us>
+		onewire_delay_us(ONEWIRE_DELAY_B); // 64us
+ 800114c:	0020      	movs	r0, r4
+	ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
+ 800114e:	61ac      	str	r4, [r5, #24]
+		onewire_delay_us(ONEWIRE_DELAY_D); // 10us
+ 8001150:	f7ff ffbc 	bl	80010cc <onewire_delay_us>
+}
+ 8001154:	bd70      	pop	{r4, r5, r6, pc}
+		onewire_delay_us(ONEWIRE_DELAY_C); // 60us
+ 8001156:	203c      	movs	r0, #60	@ 0x3c
+ 8001158:	f7ff ffb8 	bl	80010cc <onewire_delay_us>
+		onewire_delay_us(ONEWIRE_DELAY_D); // 10us
+ 800115c:	200a      	movs	r0, #10
+	ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
+ 800115e:	61ac      	str	r4, [r5, #24]
+		onewire_delay_us(ONEWIRE_DELAY_D); // 10us
+ 8001160:	e7f6      	b.n	8001150 <onewire_write_bit+0x18>
+
+08001162 <onewire_read_bit_slot>:
+{
+ 8001162:	b570      	push	{r4, r5, r6, lr}
+	ONEWIRE_GPIO_Port->BRR = ONEWIRE_Pin; // Direct register for speed
+ 8001164:	24a0      	movs	r4, #160	@ 0xa0
+ 8001166:	2540      	movs	r5, #64	@ 0x40
+ 8001168:	05e4      	lsls	r4, r4, #23
+ 800116a:	62a5      	str	r5, [r4, #40]	@ 0x28
+	onewire_delay_us(ONEWIRE_DELAY_A); // 6us
+ 800116c:	2006      	movs	r0, #6
+ 800116e:	f7ff ffad 	bl	80010cc <onewire_delay_us>
+	ONEWIRE_GPIO_Port->BSRR = ONEWIRE_Pin; // Direct register for speed
+ 8001172:	61a5      	str	r5, [r4, #24]
+	onewire_delay_us(ONEWIRE_DELAY_E); // 9us
+ 8001174:	2009      	movs	r0, #9
+ 8001176:	f7ff ffa9 	bl	80010cc <onewire_delay_us>
+	bit = onewire_read_bit();
+ 800117a:	f7ff ffbf 	bl	80010fc <onewire_read_bit>
+ 800117e:	0004      	movs	r4, r0
+	onewire_delay_us(ONEWIRE_DELAY_F); // 55us
+ 8001180:	2037      	movs	r0, #55	@ 0x37
+ 8001182:	f7ff ffa3 	bl	80010cc <onewire_delay_us>
+}
+ 8001186:	0020      	movs	r0, r4
+ 8001188:	bd70      	pop	{r4, r5, r6, pc}
+
+0800118a <onewire_write_byte>:
+{
+ 800118a:	b570      	push	{r4, r5, r6, lr}
+ 800118c:	0004      	movs	r4, r0
+ 800118e:	2508      	movs	r5, #8
+		onewire_write_bit(byte & 0x01);
+ 8001190:	2601      	movs	r6, #1
+ 8001192:	0020      	movs	r0, r4
+	for (int i = 0; i < 8; i++)
+ 8001194:	3d01      	subs	r5, #1
+		onewire_write_bit(byte & 0x01);
+ 8001196:	4030      	ands	r0, r6
+ 8001198:	f7ff ffce 	bl	8001138 <onewire_write_bit>
+		byte >>= 1;
+ 800119c:	0864      	lsrs	r4, r4, #1
+	for (int i = 0; i < 8; i++)
+ 800119e:	2d00      	cmp	r5, #0
+ 80011a0:	d1f7      	bne.n	8001192 <onewire_write_byte+0x8>
+}
+ 80011a2:	bd70      	pop	{r4, r5, r6, pc}
+
+080011a4 <onewire_read_byte>:
+{
+ 80011a4:	b570      	push	{r4, r5, r6, lr}
+ 80011a6:	2508      	movs	r5, #8
+	uint8_t byte = 0;
+ 80011a8:	2400      	movs	r4, #0
+		if (onewire_read_bit_slot())
+ 80011aa:	267f      	movs	r6, #127	@ 0x7f
+ 80011ac:	f7ff ffd9 	bl	8001162 <onewire_read_bit_slot>
+ 80011b0:	4240      	negs	r0, r0
+		byte >>= 1;
+ 80011b2:	0864      	lsrs	r4, r4, #1
+		if (onewire_read_bit_slot())
+ 80011b4:	43b0      	bics	r0, r6
+ 80011b6:	4304      	orrs	r4, r0
+	for (int i = 0; i < 8; i++)
+ 80011b8:	3d01      	subs	r5, #1
+		if (onewire_read_bit_slot())
+ 80011ba:	b2e4      	uxtb	r4, r4
+	for (int i = 0; i < 8; i++)
+ 80011bc:	2d00      	cmp	r5, #0
+ 80011be:	d1f5      	bne.n	80011ac <onewire_read_byte+0x8>
+}
+ 80011c0:	0020      	movs	r0, r4
+ 80011c2:	bd70      	pop	{r4, r5, r6, pc}
+
+080011c4 <read_floor_address>:
+{
+ 80011c4:	b510      	push	{r4, lr}
+ 80011c6:	b672      	cpsid	i
+	if (!onewire_reset())
+ 80011c8:	f7ff ff9e 	bl	8001108 <onewire_reset>
+ 80011cc:	2800      	cmp	r0, #0
+ 80011ce:	d102      	bne.n	80011d6 <read_floor_address+0x12>
+  __ASM volatile ("cpsie i" : : : "memory");
+ 80011d0:	b662      	cpsie	i
+		return FLOOR_ADDRESS_NOT_DETECTED;
+ 80011d2:	30ff      	adds	r0, #255	@ 0xff
+}
+ 80011d4:	bd10      	pop	{r4, pc}
+	onewire_write_byte(DS2431_SKIP_ROM);
+ 80011d6:	20cc      	movs	r0, #204	@ 0xcc
+ 80011d8:	f7ff ffd7 	bl	800118a <onewire_write_byte>
+	onewire_write_byte(DS2431_READ_MEMORY);
+ 80011dc:	20f0      	movs	r0, #240	@ 0xf0
+ 80011de:	f7ff ffd4 	bl	800118a <onewire_write_byte>
+	onewire_write_byte(FLOOR_ADDRESS_LOCATION & 0xFF);
+ 80011e2:	2000      	movs	r0, #0
+ 80011e4:	f7ff ffd1 	bl	800118a <onewire_write_byte>
+	onewire_write_byte((FLOOR_ADDRESS_LOCATION >> 8) & 0xFF);
+ 80011e8:	2000      	movs	r0, #0
+ 80011ea:	f7ff ffce 	bl	800118a <onewire_write_byte>
+	uint8_t address = onewire_read_byte();
+ 80011ee:	f7ff ffd9 	bl	80011a4 <onewire_read_byte>
+ 80011f2:	b662      	cpsie	i
+	return address;
+ 80011f4:	e7ee      	b.n	80011d4 <read_floor_address+0x10>
+
+080011f6 <write_floor_address>:
+{
+ 80011f6:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 80011f8:	0004      	movs	r4, r0
+  __ASM volatile ("cpsid i" : : : "memory");
+ 80011fa:	b672      	cpsid	i
+	if (!onewire_reset())
+ 80011fc:	f7ff ff84 	bl	8001108 <onewire_reset>
+ 8001200:	2800      	cmp	r0, #0
+ 8001202:	d102      	bne.n	800120a <write_floor_address+0x14>
+  __ASM volatile ("cpsie i" : : : "memory");
+ 8001204:	b662      	cpsie	i
+		return 0; // Device not present
+ 8001206:	2000      	movs	r0, #0
+}
+ 8001208:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+	onewire_write_byte(DS2431_SKIP_ROM);
+ 800120a:	20cc      	movs	r0, #204	@ 0xcc
+ 800120c:	f7ff ffbd 	bl	800118a <onewire_write_byte>
+	onewire_write_byte(DS2431_WRITE_SCRATCHPAD);
+ 8001210:	200f      	movs	r0, #15
+ 8001212:	f7ff ffba 	bl	800118a <onewire_write_byte>
+	onewire_write_byte(FLOOR_ADDRESS_LOCATION & 0xFF);
+ 8001216:	2000      	movs	r0, #0
+ 8001218:	f7ff ffb7 	bl	800118a <onewire_write_byte>
+	onewire_write_byte((FLOOR_ADDRESS_LOCATION >> 8) & 0xFF);
+ 800121c:	2000      	movs	r0, #0
+ 800121e:	f7ff ffb4 	bl	800118a <onewire_write_byte>
+	onewire_write_byte(address);
+ 8001222:	0020      	movs	r0, r4
+ 8001224:	f7ff ffb1 	bl	800118a <onewire_write_byte>
+ 8001228:	2507      	movs	r5, #7
+		onewire_write_byte(0xFF); // Pad with 0xFF
+ 800122a:	20ff      	movs	r0, #255	@ 0xff
+	for (int i = 1; i < 8; i++)
+ 800122c:	3d01      	subs	r5, #1
+		onewire_write_byte(0xFF); // Pad with 0xFF
+ 800122e:	f7ff ffac 	bl	800118a <onewire_write_byte>
+	for (int i = 1; i < 8; i++)
+ 8001232:	2d00      	cmp	r5, #0
+ 8001234:	d1f9      	bne.n	800122a <write_floor_address+0x34>
+	onewire_delay_us(100);
+ 8001236:	2064      	movs	r0, #100	@ 0x64
+ 8001238:	f7ff ff48 	bl	80010cc <onewire_delay_us>
+	if (!onewire_reset())
+ 800123c:	f7ff ff64 	bl	8001108 <onewire_reset>
+ 8001240:	2800      	cmp	r0, #0
+ 8001242:	d0df      	beq.n	8001204 <write_floor_address+0xe>
+	onewire_write_byte(DS2431_SKIP_ROM);
+ 8001244:	20cc      	movs	r0, #204	@ 0xcc
+ 8001246:	f7ff ffa0 	bl	800118a <onewire_write_byte>
+	onewire_write_byte(DS2431_READ_SCRATCHPAD);
+ 800124a:	20aa      	movs	r0, #170	@ 0xaa
+ 800124c:	f7ff ff9d 	bl	800118a <onewire_write_byte>
+	uint8_t ta1 = onewire_read_byte(); // Target address 1
+ 8001250:	f7ff ffa8 	bl	80011a4 <onewire_read_byte>
+ 8001254:	0007      	movs	r7, r0
+	uint8_t ta2 = onewire_read_byte(); // Target address 2
+ 8001256:	f7ff ffa5 	bl	80011a4 <onewire_read_byte>
+ 800125a:	0006      	movs	r6, r0
+	uint8_t es = onewire_read_byte();  // E/S register
+ 800125c:	f7ff ffa2 	bl	80011a4 <onewire_read_byte>
+ 8001260:	0005      	movs	r5, r0
+	uint8_t verify = onewire_read_byte();
+ 8001262:	f7ff ff9f 	bl	80011a4 <onewire_read_byte>
+	if (verify != address)
+ 8001266:	4284      	cmp	r4, r0
+ 8001268:	d1cc      	bne.n	8001204 <write_floor_address+0xe>
+		onewire_read_byte();
+ 800126a:	f7ff ff9b 	bl	80011a4 <onewire_read_byte>
+ 800126e:	f7ff ff99 	bl	80011a4 <onewire_read_byte>
+ 8001272:	f7ff ff97 	bl	80011a4 <onewire_read_byte>
+ 8001276:	f7ff ff95 	bl	80011a4 <onewire_read_byte>
+ 800127a:	f7ff ff93 	bl	80011a4 <onewire_read_byte>
+ 800127e:	f7ff ff91 	bl	80011a4 <onewire_read_byte>
+ 8001282:	f7ff ff8f 	bl	80011a4 <onewire_read_byte>
+	if (!onewire_reset())
+ 8001286:	f7ff ff3f 	bl	8001108 <onewire_reset>
+ 800128a:	2800      	cmp	r0, #0
+ 800128c:	d0ba      	beq.n	8001204 <write_floor_address+0xe>
+	onewire_write_byte(DS2431_SKIP_ROM);
+ 800128e:	20cc      	movs	r0, #204	@ 0xcc
+ 8001290:	f7ff ff7b 	bl	800118a <onewire_write_byte>
+	onewire_write_byte(DS2431_COPY_SCRATCHPAD);
+ 8001294:	2055      	movs	r0, #85	@ 0x55
+ 8001296:	f7ff ff78 	bl	800118a <onewire_write_byte>
+	onewire_write_byte(ta1);
+ 800129a:	0038      	movs	r0, r7
+ 800129c:	f7ff ff75 	bl	800118a <onewire_write_byte>
+	onewire_write_byte(ta2);
+ 80012a0:	0030      	movs	r0, r6
+ 80012a2:	f7ff ff72 	bl	800118a <onewire_write_byte>
+	onewire_write_byte(es);
+ 80012a6:	0028      	movs	r0, r5
+ 80012a8:	f7ff ff6f 	bl	800118a <onewire_write_byte>
+ 80012ac:	b662      	cpsie	i
+	HAL_Delay(15);
+ 80012ae:	200f      	movs	r0, #15
+ 80012b0:	f001 fb1c 	bl	80028ec <HAL_Delay>
+	uint8_t read_back = read_floor_address();
+ 80012b4:	f7ff ff86 	bl	80011c4 <read_floor_address>
+	return (read_back == address) ? 1 : 0;
+ 80012b8:	1a20      	subs	r0, r4, r0
+ 80012ba:	4243      	negs	r3, r0
+ 80012bc:	4158      	adcs	r0, r3
+ 80012be:	b2c0      	uxtb	r0, r0
+ 80012c0:	e7a2      	b.n	8001208 <write_floor_address+0x12>
+	...
+
+080012c4 <handleRS485Message>:
+{
+ 80012c4:	b5f0      	push	{r4, r5, r6, r7, lr}
+	last_rx_size = size;
+ 80012c6:	4bbb      	ldr	r3, [pc, #748]	@ (80015b4 <handleRS485Message+0x2f0>)
+{
+ 80012c8:	b08b      	sub	sp, #44	@ 0x2c
+	last_rx_size = size;
+ 80012ca:	7019      	strb	r1, [r3, #0]
+ 80012cc:	2300      	movs	r3, #0
+{
+ 80012ce:	0005      	movs	r5, r0
+	for (uint8_t i = 0; i < 8 && i < size; i++) last_rx_bytes[i] = buffer[i];
+ 80012d0:	48b9      	ldr	r0, [pc, #740]	@ (80015b8 <handleRS485Message+0x2f4>)
+ 80012d2:	b2da      	uxtb	r2, r3
+ 80012d4:	4291      	cmp	r1, r2
+ 80012d6:	d807      	bhi.n	80012e8 <handleRS485Message+0x24>
+	if (size >= 1 && buffer[0] == my_address)
+ 80012d8:	2900      	cmp	r1, #0
+ 80012da:	d10a      	bne.n	80012f2 <handleRS485Message+0x2e>
+		drop_size++;
+ 80012dc:	4ab7      	ldr	r2, [pc, #732]	@ (80015bc <handleRS485Message+0x2f8>)
+		drop_addr++;
+ 80012de:	8813      	ldrh	r3, [r2, #0]
+ 80012e0:	3301      	adds	r3, #1
+ 80012e2:	b29b      	uxth	r3, r3
+ 80012e4:	8013      	strh	r3, [r2, #0]
+		return; // message not for us
+ 80012e6:	e036      	b.n	8001356 <handleRS485Message+0x92>
+	for (uint8_t i = 0; i < 8 && i < size; i++) last_rx_bytes[i] = buffer[i];
+ 80012e8:	5cea      	ldrb	r2, [r5, r3]
+ 80012ea:	54c2      	strb	r2, [r0, r3]
+ 80012ec:	3301      	adds	r3, #1
+ 80012ee:	2b08      	cmp	r3, #8
+ 80012f0:	d1ef      	bne.n	80012d2 <handleRS485Message+0xe>
+	if (size >= 1 && buffer[0] == my_address)
+ 80012f2:	4fb3      	ldr	r7, [pc, #716]	@ (80015c0 <handleRS485Message+0x2fc>)
+ 80012f4:	782a      	ldrb	r2, [r5, #0]
+ 80012f6:	783b      	ldrb	r3, [r7, #0]
+ 80012f8:	429a      	cmp	r2, r3
+ 80012fa:	d02e      	beq.n	800135a <handleRS485Message+0x96>
+	if (size < sizeof(PhotonPacketHeader) + 1) // header + at least commandId
+ 80012fc:	2905      	cmp	r1, #5
+ 80012fe:	d9ed      	bls.n	80012dc <handleRS485Message+0x18>
+    uint32_t crc;
+} CRC8_107;
+
+static inline void CRC8_107_init(CRC8_107 *ctx)
+{
+    ctx->crc = 0x0u;
+ 8001300:	2400      	movs	r4, #0
+	last_rx_to = header->toAddress;
+ 8001302:	4bb0      	ldr	r3, [pc, #704]	@ (80015c4 <handleRS485Message+0x300>)
+ 8001304:	7829      	ldrb	r1, [r5, #0]
+	CRC8_107_add(&rx_crc, header->toAddress);
+ 8001306:	a801      	add	r0, sp, #4
+	last_rx_to = header->toAddress;
+ 8001308:	7019      	strb	r1, [r3, #0]
+ 800130a:	9401      	str	r4, [sp, #4]
+	CRC8_107_add(&rx_crc, header->toAddress);
+ 800130c:	f7ff fa1e 	bl	800074c <CRC8_107_add>
+	CRC8_107_add(&rx_crc, header->fromAddress);
+ 8001310:	7869      	ldrb	r1, [r5, #1]
+ 8001312:	a801      	add	r0, sp, #4
+ 8001314:	f7ff fa1a 	bl	800074c <CRC8_107_add>
+	CRC8_107_add(&rx_crc, header->packetId);
+ 8001318:	78a9      	ldrb	r1, [r5, #2]
+ 800131a:	a801      	add	r0, sp, #4
+ 800131c:	f7ff fa16 	bl	800074c <CRC8_107_add>
+	CRC8_107_add(&rx_crc, header->payloadLength);
+ 8001320:	78e9      	ldrb	r1, [r5, #3]
+ 8001322:	a801      	add	r0, sp, #4
+ 8001324:	f7ff fa12 	bl	800074c <CRC8_107_add>
+	for (uint8_t i = 0; i < header->payloadLength; i++)
+ 8001328:	78eb      	ldrb	r3, [r5, #3]
+ 800132a:	42a3      	cmp	r3, r4
+ 800132c:	d822      	bhi.n	8001374 <handleRS485Message+0xb0>
+	if (CRC8_107_getChecksum(&rx_crc) != header->crc)
+ 800132e:	a801      	add	r0, sp, #4
+ 8001330:	f7ff fa20 	bl	8000774 <CRC8_107_getChecksum>
+ 8001334:	792b      	ldrb	r3, [r5, #4]
+		if (header->toAddress == my_address)
+ 8001336:	782c      	ldrb	r4, [r5, #0]
+ 8001338:	783a      	ldrb	r2, [r7, #0]
+	if (CRC8_107_getChecksum(&rx_crc) != header->crc)
+ 800133a:	4283      	cmp	r3, r0
+ 800133c:	d022      	beq.n	8001384 <handleRS485Message+0xc0>
+		drop_crc++;
+ 800133e:	49a2      	ldr	r1, [pc, #648]	@ (80015c8 <handleRS485Message+0x304>)
+ 8001340:	880b      	ldrh	r3, [r1, #0]
+ 8001342:	3301      	adds	r3, #1
+ 8001344:	b29b      	uxth	r3, r3
+ 8001346:	800b      	strh	r3, [r1, #0]
+		if (header->toAddress == my_address)
+ 8001348:	4294      	cmp	r4, r2
+ 800134a:	d104      	bne.n	8001356 <handleRS485Message+0x92>
+			my_addr_crc_exp = CRC8_107_getChecksum(&rx_crc);
+ 800134c:	a801      	add	r0, sp, #4
+ 800134e:	f7ff fa11 	bl	8000774 <CRC8_107_getChecksum>
+ 8001352:	4b9e      	ldr	r3, [pc, #632]	@ (80015cc <handleRS485Message+0x308>)
+ 8001354:	7018      	strb	r0, [r3, #0]
+}
+ 8001356:	b00b      	add	sp, #44	@ 0x2c
+ 8001358:	bdf0      	pop	{r4, r5, r6, r7, pc}
+		my_addr_size = size;
+ 800135a:	4b9d      	ldr	r3, [pc, #628]	@ (80015d0 <handleRS485Message+0x30c>)
+		for (uint8_t i = 0; i < 8 && i < size; i++) my_addr_bytes[i] = buffer[i];
+ 800135c:	489d      	ldr	r0, [pc, #628]	@ (80015d4 <handleRS485Message+0x310>)
+		my_addr_size = size;
+ 800135e:	7019      	strb	r1, [r3, #0]
+ 8001360:	2300      	movs	r3, #0
+		for (uint8_t i = 0; i < 8 && i < size; i++) my_addr_bytes[i] = buffer[i];
+ 8001362:	5cea      	ldrb	r2, [r5, r3]
+ 8001364:	54c2      	strb	r2, [r0, r3]
+ 8001366:	2b07      	cmp	r3, #7
+ 8001368:	d0c8      	beq.n	80012fc <handleRS485Message+0x38>
+ 800136a:	3301      	adds	r3, #1
+ 800136c:	b2da      	uxtb	r2, r3
+ 800136e:	428a      	cmp	r2, r1
+ 8001370:	d3f7      	bcc.n	8001362 <handleRS485Message+0x9e>
+ 8001372:	e7c3      	b.n	80012fc <handleRS485Message+0x38>
+		CRC8_107_add(&rx_crc, buffer[sizeof(PhotonPacketHeader) + i]);
+ 8001374:	192b      	adds	r3, r5, r4
+ 8001376:	7959      	ldrb	r1, [r3, #5]
+ 8001378:	a801      	add	r0, sp, #4
+	for (uint8_t i = 0; i < header->payloadLength; i++)
+ 800137a:	3401      	adds	r4, #1
+		CRC8_107_add(&rx_crc, buffer[sizeof(PhotonPacketHeader) + i]);
+ 800137c:	f7ff f9e6 	bl	800074c <CRC8_107_add>
+	for (uint8_t i = 0; i < header->payloadLength; i++)
+ 8001380:	b2e4      	uxtb	r4, r4
+ 8001382:	e7d1      	b.n	8001328 <handleRS485Message+0x64>
+	if ((header->toAddress != PHOTON_NETWORK_BROADCAST_ADDRESS) &&
+ 8001384:	2cff      	cmp	r4, #255	@ 0xff
+ 8001386:	d003      	beq.n	8001390 <handleRS485Message+0xcc>
+ 8001388:	4294      	cmp	r4, r2
+ 800138a:	d001      	beq.n	8001390 <handleRS485Message+0xcc>
+		drop_addr++;
+ 800138c:	4a92      	ldr	r2, [pc, #584]	@ (80015d8 <handleRS485Message+0x314>)
+ 800138e:	e7a6      	b.n	80012de <handleRS485Message+0x1a>
+ 8001390:	2600      	movs	r6, #0
+	msg_handled++;
+ 8001392:	4992      	ldr	r1, [pc, #584]	@ (80015dc <handleRS485Message+0x318>)
+	last_rx_cmd = buffer[sizeof(PhotonPacketHeader)]; // commandId
+ 8001394:	7968      	ldrb	r0, [r5, #5]
+	msg_handled++;
+ 8001396:	880b      	ldrh	r3, [r1, #0]
+		response.header.fromAddress = my_address;
+ 8001398:	ac03      	add	r4, sp, #12
+	msg_handled++;
+ 800139a:	3301      	adds	r3, #1
+ 800139c:	b29b      	uxth	r3, r3
+ 800139e:	800b      	strh	r3, [r1, #0]
+	last_rx_cmd = buffer[sizeof(PhotonPacketHeader)]; // commandId
+ 80013a0:	4b8f      	ldr	r3, [pc, #572]	@ (80015e0 <handleRS485Message+0x31c>)
+ 80013a2:	9602      	str	r6, [sp, #8]
+ 80013a4:	7018      	strb	r0, [r3, #0]
+		response.header.fromAddress = my_address;
+ 80013a6:	7062      	strb	r2, [r4, #1]
+		response.header.packetId = command->header.packetId;
+ 80013a8:	78ab      	ldrb	r3, [r5, #2]
+ 80013aa:	70a3      	strb	r3, [r4, #2]
+		response.header.toAddress = command->header.fromAddress;
+ 80013ac:	786b      	ldrb	r3, [r5, #1]
+ 80013ae:	7023      	strb	r3, [r4, #0]
+		switch (command->commandId)
+ 80013b0:	2806      	cmp	r0, #6
+ 80013b2:	d809      	bhi.n	80013c8 <handleRS485Message+0x104>
+ 80013b4:	42b0      	cmp	r0, r6
+ 80013b6:	d0ce      	beq.n	8001356 <handleRS485Message+0x92>
+ 80013b8:	3802      	subs	r0, #2
+ 80013ba:	2804      	cmp	r0, #4
+ 80013bc:	d813      	bhi.n	80013e6 <handleRS485Message+0x122>
+ 80013be:	f7fe fea3 	bl	8000108 <__gnu_thumb1_case_uqi>
+ 80013c2:	5430      	.short	0x5430
+ 80013c4:	aa68      	.short	0xaa68
+ 80013c6:	f0          	.byte	0xf0
+ 80013c7:	00          	.byte	0x00
+ 80013c8:	0003      	movs	r3, r0
+ 80013ca:	3341      	adds	r3, #65	@ 0x41
+ 80013cc:	b2db      	uxtb	r3, r3
+ 80013ce:	2b04      	cmp	r3, #4
+ 80013d0:	d8c1      	bhi.n	8001356 <handleRS485Message+0x92>
+ 80013d2:	38c0      	subs	r0, #192	@ 0xc0
+ 80013d4:	2803      	cmp	r0, #3
+ 80013d6:	d900      	bls.n	80013da <handleRS485Message+0x116>
+ 80013d8:	e10c      	b.n	80015f4 <handleRS485Message+0x330>
+ 80013da:	f7fe fe9f 	bl	800011c <__gnu_thumb1_case_uhi>
+ 80013de:	0146      	.short	0x0146
+ 80013e0:	0179015a 	.word	0x0179015a
+ 80013e4:	0189      	.short	0x0189
+				memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH);
+ 80013e6:	2012      	movs	r0, #18
+ 80013e8:	497e      	ldr	r1, [pc, #504]	@ (80015e4 <handleRS485Message+0x320>)
+ 80013ea:	220c      	movs	r2, #12
+ 80013ec:	4468      	add	r0, sp
+ 80013ee:	f003 fef9 	bl	80051e4 <memcpy>
+				response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for status byte
+ 80013f2:	230d      	movs	r3, #13
+				comp_crc_header(&crc,&response);
+ 80013f4:	0021      	movs	r1, r4
+ 80013f6:	a802      	add	r0, sp, #8
+				response.status = STATUS_OK;
+ 80013f8:	7166      	strb	r6, [r4, #5]
+				response.header.payloadLength = sizeof(response.payload.getFeederId)+1; // +1 for status byte
+ 80013fa:	70e3      	strb	r3, [r4, #3]
+				comp_crc_header(&crc,&response);
+ 80013fc:	f7ff fb94 	bl	8000b28 <comp_crc_header>
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
+ 8001400:	78e3      	ldrb	r3, [r4, #3]
+ 8001402:	42b3      	cmp	r3, r6
+ 8001404:	d806      	bhi.n	8001414 <handleRS485Message+0x150>
+				response.header.crc = CRC8_107_getChecksum(&crc);
+ 8001406:	a802      	add	r0, sp, #8
+ 8001408:	f7ff f9b4 	bl	8000774 <CRC8_107_getChecksum>
+				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
+ 800140c:	78e1      	ldrb	r1, [r4, #3]
+				response.header.crc = CRC8_107_getChecksum(&crc);
+ 800140e:	7120      	strb	r0, [r4, #4]
+				rs485_transmit((uint8_t *)&response, packet_len);
+ 8001410:	3105      	adds	r1, #5
+ 8001412:	e126      	b.n	8001662 <handleRS485Message+0x39e>
+					CRC8_107_add(&crc,*(payload_ptr+i));
+ 8001414:	19a3      	adds	r3, r4, r6
+ 8001416:	7959      	ldrb	r1, [r3, #5]
+ 8001418:	a802      	add	r0, sp, #8
+ 800141a:	f7ff f997 	bl	800074c <CRC8_107_add>
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
+ 800141e:	3601      	adds	r6, #1
+ 8001420:	e7ee      	b.n	8001400 <handleRS485Message+0x13c>
+				memcpy(response.payload.initializeFeeder.uuid,UUID,UUID_LENGTH);
+ 8001422:	2012      	movs	r0, #18
+ 8001424:	4e6f      	ldr	r6, [pc, #444]	@ (80015e4 <handleRS485Message+0x320>)
+ 8001426:	220c      	movs	r2, #12
+ 8001428:	0031      	movs	r1, r6
+ 800142a:	4468      	add	r0, sp
+ 800142c:	f003 feda 	bl	80051e4 <memcpy>
+				if(memcmp(UUID,command->payload.initializeFeeder.uuid,UUID_LENGTH) == 0)
+ 8001430:	220c      	movs	r2, #12
+ 8001432:	0030      	movs	r0, r6
+ 8001434:	1da9      	adds	r1, r5, #6
+ 8001436:	f003 fe9b 	bl	8005170 <memcmp>
+ 800143a:	2301      	movs	r3, #1
+ 800143c:	2800      	cmp	r0, #0
+ 800143e:	d102      	bne.n	8001446 <handleRS485Message+0x182>
+					is_initialized = 1;
+ 8001440:	4a69      	ldr	r2, [pc, #420]	@ (80015e8 <handleRS485Message+0x324>)
+ 8001442:	7013      	strb	r3, [r2, #0]
+					response.status = STATUS_OK;
+ 8001444:	0003      	movs	r3, r0
+ 8001446:	7163      	strb	r3, [r4, #5]
+				response.header.payloadLength = sizeof(response.payload.initializeFeeder)+1;
+ 8001448:	230d      	movs	r3, #13
+				comp_crc_header(&crc,&response);
+ 800144a:	0021      	movs	r1, r4
+ 800144c:	a802      	add	r0, sp, #8
+				response.header.payloadLength = sizeof(response.payload.initializeFeeder)+1;
+ 800144e:	70e3      	strb	r3, [r4, #3]
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
+ 8001450:	2500      	movs	r5, #0
+				comp_crc_header(&crc,&response);
+ 8001452:	f7ff fb69 	bl	8000b28 <comp_crc_header>
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
+ 8001456:	78e3      	ldrb	r3, [r4, #3]
+ 8001458:	42ab      	cmp	r3, r5
+ 800145a:	d9d4      	bls.n	8001406 <handleRS485Message+0x142>
+					CRC8_107_add(&crc,*(payload_ptr+i));
+ 800145c:	1963      	adds	r3, r4, r5
+ 800145e:	7959      	ldrb	r1, [r3, #5]
+ 8001460:	a802      	add	r0, sp, #8
+ 8001462:	f7ff f973 	bl	800074c <CRC8_107_add>
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
+ 8001466:	3501      	adds	r5, #1
+ 8001468:	e7f5      	b.n	8001456 <handleRS485Message+0x192>
+				response.payload.protocolVersion.version = PROTOCOL_VERSION;
+ 800146a:	2301      	movs	r3, #1
+				response.status = STATUS_OK;
+ 800146c:	2500      	movs	r5, #0
+				response.payload.protocolVersion.version = PROTOCOL_VERSION;
+ 800146e:	71a3      	strb	r3, [r4, #6]
+				comp_crc_header(&crc,&response);
+ 8001470:	0021      	movs	r1, r4
+				response.header.payloadLength = sizeof(response.payload.protocolVersion)+1;
+ 8001472:	18db      	adds	r3, r3, r3
+				comp_crc_header(&crc,&response);
+ 8001474:	a802      	add	r0, sp, #8
+				response.status = STATUS_OK;
+ 8001476:	7165      	strb	r5, [r4, #5]
+				response.header.payloadLength = sizeof(response.payload.protocolVersion)+1;
+ 8001478:	70e3      	strb	r3, [r4, #3]
+				comp_crc_header(&crc,&response);
+ 800147a:	f7ff fb55 	bl	8000b28 <comp_crc_header>
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
+ 800147e:	78e3      	ldrb	r3, [r4, #3]
+ 8001480:	42ab      	cmp	r3, r5
+ 8001482:	d9c0      	bls.n	8001406 <handleRS485Message+0x142>
+					CRC8_107_add(&crc,*(payload_ptr+i));
+ 8001484:	1963      	adds	r3, r4, r5
+ 8001486:	7959      	ldrb	r1, [r3, #5]
+ 8001488:	a802      	add	r0, sp, #8
+ 800148a:	f7ff f95f 	bl	800074c <CRC8_107_add>
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
+ 800148e:	3501      	adds	r5, #1
+ 8001490:	e7f5      	b.n	800147e <handleRS485Message+0x1ba>
+				if (!is_initialized)
+ 8001492:	4b55      	ldr	r3, [pc, #340]	@ (80015e8 <handleRS485Message+0x324>)
+ 8001494:	781e      	ldrb	r6, [r3, #0]
+ 8001496:	2e00      	cmp	r6, #0
+ 8001498:	d117      	bne.n	80014ca <handleRS485Message+0x206>
+					memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
+ 800149a:	2012      	movs	r0, #18
+					response.status = STATUS_UNINITIALIZED_FEEDER;
+ 800149c:	2303      	movs	r3, #3
+					memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
+ 800149e:	4951      	ldr	r1, [pc, #324]	@ (80015e4 <handleRS485Message+0x320>)
+ 80014a0:	220c      	movs	r2, #12
+ 80014a2:	4468      	add	r0, sp
+					response.status = STATUS_UNINITIALIZED_FEEDER;
+ 80014a4:	7163      	strb	r3, [r4, #5]
+					memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
+ 80014a6:	f003 fe9d 	bl	80051e4 <memcpy>
+					response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
+ 80014aa:	230d      	movs	r3, #13
+					comp_crc_header(&crc, &response);
+ 80014ac:	0021      	movs	r1, r4
+ 80014ae:	a802      	add	r0, sp, #8
+					response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
+ 80014b0:	70e3      	strb	r3, [r4, #3]
+					comp_crc_header(&crc, &response);
+ 80014b2:	f7ff fb39 	bl	8000b28 <comp_crc_header>
+					for (uint32_t i = 0; i < response.header.payloadLength; i++)
+ 80014b6:	78e3      	ldrb	r3, [r4, #3]
+ 80014b8:	42b3      	cmp	r3, r6
+ 80014ba:	d9a4      	bls.n	8001406 <handleRS485Message+0x142>
+						CRC8_107_add(&crc, *(payload_ptr + i));
+ 80014bc:	19a3      	adds	r3, r4, r6
+ 80014be:	7959      	ldrb	r1, [r3, #5]
+ 80014c0:	a802      	add	r0, sp, #8
+ 80014c2:	f7ff f943 	bl	800074c <CRC8_107_add>
+					for (uint32_t i = 0; i < response.header.payloadLength; i++)
+ 80014c6:	3601      	adds	r6, #1
+ 80014c8:	e7f5      	b.n	80014b6 <handleRS485Message+0x1f2>
+						PEEL_BACKOFF_TIME +
+ 80014ca:	2276      	movs	r2, #118	@ 0x76
+ 80014cc:	79ab      	ldrb	r3, [r5, #6]
+					response.status = STATUS_OK;
+ 80014ce:	2600      	movs	r6, #0
+						PEEL_BACKOFF_TIME +
+ 80014d0:	4353      	muls	r3, r2
+		uint16_t time = (distance * PEEL_TIME_PER_TENTH_MM) +
+ 80014d2:	33e6      	adds	r3, #230	@ 0xe6
+					uint16_t exp_time_be = (exp_time >> 8) | (exp_time << 8); // byte swap for network order
+ 80014d4:	ba5b      	rev16	r3, r3
+					response.payload.expectedTimeToFeed.expectedFeedTime = exp_time_be;
+ 80014d6:	80e3      	strh	r3, [r4, #6]
+					response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
+ 80014d8:	2303      	movs	r3, #3
+					comp_crc_header(&crc, &response);
+ 80014da:	0021      	movs	r1, r4
+ 80014dc:	a802      	add	r0, sp, #8
+					response.status = STATUS_OK;
+ 80014de:	7166      	strb	r6, [r4, #5]
+					response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
+ 80014e0:	70e3      	strb	r3, [r4, #3]
+					comp_crc_header(&crc, &response);
+ 80014e2:	f7ff fb21 	bl	8000b28 <comp_crc_header>
+					for (uint32_t i = 0; i < response.header.payloadLength; i++)
+ 80014e6:	78e3      	ldrb	r3, [r4, #3]
+ 80014e8:	42b3      	cmp	r3, r6
+ 80014ea:	d80d      	bhi.n	8001508 <handleRS485Message+0x244>
+					response.header.crc = CRC8_107_getChecksum(&crc);
+ 80014ec:	a802      	add	r0, sp, #8
+ 80014ee:	f7ff f941 	bl	8000774 <CRC8_107_getChecksum>
+					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
+ 80014f2:	78e1      	ldrb	r1, [r4, #3]
+					response.header.crc = CRC8_107_getChecksum(&crc);
+ 80014f4:	7120      	strb	r0, [r4, #4]
+					rs485_transmit((uint8_t *)&response, packet_len);
+ 80014f6:	3105      	adds	r1, #5
+ 80014f8:	0020      	movs	r0, r4
+ 80014fa:	f7ff faeb 	bl	8000ad4 <rs485_transmit>
+					start_feed(command->payload.move.distance, 1);
+ 80014fe:	2101      	movs	r1, #1
+ 8001500:	79a8      	ldrb	r0, [r5, #6]
+					start_feed(command->payload.move.distance, 0);
+ 8001502:	f7ff fbc9 	bl	8000c98 <start_feed>
+				break;
+ 8001506:	e726      	b.n	8001356 <handleRS485Message+0x92>
+						CRC8_107_add(&crc, *(payload_ptr + i));
+ 8001508:	19a3      	adds	r3, r4, r6
+ 800150a:	7959      	ldrb	r1, [r3, #5]
+ 800150c:	a802      	add	r0, sp, #8
+ 800150e:	f7ff f91d 	bl	800074c <CRC8_107_add>
+					for (uint32_t i = 0; i < response.header.payloadLength; i++)
+ 8001512:	3601      	adds	r6, #1
+ 8001514:	e7e7      	b.n	80014e6 <handleRS485Message+0x222>
+				if (!is_initialized)
+ 8001516:	4b34      	ldr	r3, [pc, #208]	@ (80015e8 <handleRS485Message+0x324>)
+ 8001518:	781e      	ldrb	r6, [r3, #0]
+ 800151a:	2e00      	cmp	r6, #0
+ 800151c:	d118      	bne.n	8001550 <handleRS485Message+0x28c>
+					memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
+ 800151e:	2012      	movs	r0, #18
+					response.status = STATUS_UNINITIALIZED_FEEDER;
+ 8001520:	2303      	movs	r3, #3
+					memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
+ 8001522:	4930      	ldr	r1, [pc, #192]	@ (80015e4 <handleRS485Message+0x320>)
+ 8001524:	220c      	movs	r2, #12
+ 8001526:	4468      	add	r0, sp
+					response.status = STATUS_UNINITIALIZED_FEEDER;
+ 8001528:	7163      	strb	r3, [r4, #5]
+					memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
+ 800152a:	f003 fe5b 	bl	80051e4 <memcpy>
+					response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
+ 800152e:	230d      	movs	r3, #13
+					comp_crc_header(&crc, &response);
+ 8001530:	0021      	movs	r1, r4
+ 8001532:	a802      	add	r0, sp, #8
+					response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
+ 8001534:	70e3      	strb	r3, [r4, #3]
+					comp_crc_header(&crc, &response);
+ 8001536:	f7ff faf7 	bl	8000b28 <comp_crc_header>
+					for (uint32_t i = 0; i < response.header.payloadLength; i++)
+ 800153a:	78e3      	ldrb	r3, [r4, #3]
+ 800153c:	42b3      	cmp	r3, r6
+ 800153e:	d800      	bhi.n	8001542 <handleRS485Message+0x27e>
+ 8001540:	e761      	b.n	8001406 <handleRS485Message+0x142>
+						CRC8_107_add(&crc, *(payload_ptr + i));
+ 8001542:	19a3      	adds	r3, r4, r6
+ 8001544:	7959      	ldrb	r1, [r3, #5]
+ 8001546:	a802      	add	r0, sp, #8
+ 8001548:	f7ff f900 	bl	800074c <CRC8_107_add>
+					for (uint32_t i = 0; i < response.header.payloadLength; i++)
+ 800154c:	3601      	adds	r6, #1
+ 800154e:	e7f4      	b.n	800153a <handleRS485Message+0x276>
+		return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) +
+ 8001550:	231e      	movs	r3, #30
+ 8001552:	2164      	movs	r1, #100	@ 0x64
+					uint16_t exp_time = calculate_expected_feed_time(command->payload.move.distance, 0);
+ 8001554:	79aa      	ldrb	r2, [r5, #6]
+					response.status = STATUS_OK;
+ 8001556:	2600      	movs	r6, #0
+		return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) +
+ 8001558:	4353      	muls	r3, r2
+			   ((distance + (BACKLASH_COMP_TENTH_MM * 2)) * TIMEOUT_TIME_PER_TENTH_MM) +
+ 800155a:	3214      	adds	r2, #20
+		return (distance * BACKWARDS_PEEL_TIME_PER_TENTH_MM) +
+ 800155c:	434a      	muls	r2, r1
+			   BACKWARDS_FEED_FILM_SLACK_REMOVAL_TIME + 50;
+ 800155e:	3391      	adds	r3, #145	@ 0x91
+ 8001560:	33ff      	adds	r3, #255	@ 0xff
+ 8001562:	189b      	adds	r3, r3, r2
+					uint16_t exp_time_be = (exp_time >> 8) | (exp_time << 8); // byte swap for network order
+ 8001564:	ba5b      	rev16	r3, r3
+					response.payload.expectedTimeToFeed.expectedFeedTime = exp_time_be;
+ 8001566:	80e3      	strh	r3, [r4, #6]
+					response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
+ 8001568:	2303      	movs	r3, #3
+					comp_crc_header(&crc, &response);
+ 800156a:	0021      	movs	r1, r4
+ 800156c:	a802      	add	r0, sp, #8
+					response.status = STATUS_OK;
+ 800156e:	7166      	strb	r6, [r4, #5]
+					response.header.payloadLength = sizeof(response.payload.expectedTimeToFeed) + 1;
+ 8001570:	70e3      	strb	r3, [r4, #3]
+					comp_crc_header(&crc, &response);
+ 8001572:	f7ff fad9 	bl	8000b28 <comp_crc_header>
+					for (uint32_t i = 0; i < response.header.payloadLength; i++)
+ 8001576:	78e3      	ldrb	r3, [r4, #3]
+ 8001578:	42b3      	cmp	r3, r6
+ 800157a:	d80b      	bhi.n	8001594 <handleRS485Message+0x2d0>
+					response.header.crc = CRC8_107_getChecksum(&crc);
+ 800157c:	a802      	add	r0, sp, #8
+ 800157e:	f7ff f8f9 	bl	8000774 <CRC8_107_getChecksum>
+					packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
+ 8001582:	78e1      	ldrb	r1, [r4, #3]
+					response.header.crc = CRC8_107_getChecksum(&crc);
+ 8001584:	7120      	strb	r0, [r4, #4]
+					rs485_transmit((uint8_t *)&response, packet_len);
+ 8001586:	3105      	adds	r1, #5
+ 8001588:	0020      	movs	r0, r4
+ 800158a:	f7ff faa3 	bl	8000ad4 <rs485_transmit>
+					start_feed(command->payload.move.distance, 0);
+ 800158e:	2100      	movs	r1, #0
+ 8001590:	79a8      	ldrb	r0, [r5, #6]
+ 8001592:	e7b6      	b.n	8001502 <handleRS485Message+0x23e>
+						CRC8_107_add(&crc, *(payload_ptr + i));
+ 8001594:	19a3      	adds	r3, r4, r6
+ 8001596:	7959      	ldrb	r1, [r3, #5]
+ 8001598:	a802      	add	r0, sp, #8
+ 800159a:	f7ff f8d7 	bl	800074c <CRC8_107_add>
+					for (uint32_t i = 0; i < response.header.payloadLength; i++)
+ 800159e:	3601      	adds	r6, #1
+ 80015a0:	e7e9      	b.n	8001576 <handleRS485Message+0x2b2>
+				if (feed_in_progress)
+ 80015a2:	4b12      	ldr	r3, [pc, #72]	@ (80015ec <handleRS485Message+0x328>)
+ 80015a4:	781a      	ldrb	r2, [r3, #0]
+					response.status = STATUS_FEEDING_IN_PROGRESS;
+ 80015a6:	2304      	movs	r3, #4
+				if (feed_in_progress)
+ 80015a8:	2a00      	cmp	r2, #0
+ 80015aa:	d101      	bne.n	80015b0 <handleRS485Message+0x2ec>
+					response.status = last_feed_status;
+ 80015ac:	4b10      	ldr	r3, [pc, #64]	@ (80015f0 <handleRS485Message+0x32c>)
+ 80015ae:	781b      	ldrb	r3, [r3, #0]
+						response.status = STATUS_OK;
+ 80015b0:	7163      	strb	r3, [r4, #5]
+ 80015b2:	e063      	b.n	800167c <handleRS485Message+0x3b8>
+ 80015b4:	20000071 	.word	0x20000071
+ 80015b8:	20000067 	.word	0x20000067
+ 80015bc:	20000078 	.word	0x20000078
+ 80015c0:	20000020 	.word	0x20000020
+ 80015c4:	20000070 	.word	0x20000070
+ 80015c8:	20000076 	.word	0x20000076
+ 80015cc:	2000005d 	.word	0x2000005d
+ 80015d0:	2000005e 	.word	0x2000005e
+ 80015d4:	2000005f 	.word	0x2000005f
+ 80015d8:	20000074 	.word	0x20000074
+ 80015dc:	20000072 	.word	0x20000072
+ 80015e0:	2000006f 	.word	0x2000006f
+ 80015e4:	20000f87 	.word	0x20000f87
+ 80015e8:	20000f86 	.word	0x20000f86
+ 80015ec:	20000121 	.word	0x20000121
+ 80015f0:	20000122 	.word	0x20000122
+				if (!is_initialized)
+ 80015f4:	4b4d      	ldr	r3, [pc, #308]	@ (800172c <handleRS485Message+0x468>)
+ 80015f6:	781f      	ldrb	r7, [r3, #0]
+ 80015f8:	2f00      	cmp	r7, #0
+ 80015fa:	d119      	bne.n	8001630 <handleRS485Message+0x36c>
+					response.status = STATUS_UNINITIALIZED_FEEDER;
+ 80015fc:	2303      	movs	r3, #3
+ 80015fe:	7163      	strb	r3, [r4, #5]
+					memcpy(response.payload.initializeFeeder.uuid, UUID, UUID_LENGTH);
+ 8001600:	330f      	adds	r3, #15
+ 8001602:	446b      	add	r3, sp
+ 8001604:	0018      	movs	r0, r3
+ 8001606:	494a      	ldr	r1, [pc, #296]	@ (8001730 <handleRS485Message+0x46c>)
+ 8001608:	220c      	movs	r2, #12
+ 800160a:	f003 fdeb 	bl	80051e4 <memcpy>
+					response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
+ 800160e:	230d      	movs	r3, #13
+					comp_crc_header(&crc, &response);
+ 8001610:	0021      	movs	r1, r4
+ 8001612:	a802      	add	r0, sp, #8
+					response.header.payloadLength = sizeof(response.payload.initializeFeeder) + 1;
+ 8001614:	70e3      	strb	r3, [r4, #3]
+					comp_crc_header(&crc, &response);
+ 8001616:	f7ff fa87 	bl	8000b28 <comp_crc_header>
+					for (uint32_t i = 0; i < response.header.payloadLength; i++)
+ 800161a:	78e3      	ldrb	r3, [r4, #3]
+ 800161c:	42bb      	cmp	r3, r7
+ 800161e:	d800      	bhi.n	8001622 <handleRS485Message+0x35e>
+ 8001620:	e6f1      	b.n	8001406 <handleRS485Message+0x142>
+						CRC8_107_add(&crc, *(payload_ptr + i));
+ 8001622:	19e3      	adds	r3, r4, r7
+ 8001624:	7959      	ldrb	r1, [r3, #5]
+ 8001626:	a802      	add	r0, sp, #8
+ 8001628:	f7ff f890 	bl	800074c <CRC8_107_add>
+					for (uint32_t i = 0; i < response.header.payloadLength; i++)
+ 800162c:	3701      	adds	r7, #1
+ 800162e:	e7f4      	b.n	800161a <handleRS485Message+0x356>
+				handle_vendor_options(command->payload.vendorOptions.options, response.payload.vendorOptions.options);
+ 8001630:	2312      	movs	r3, #18
+ 8001632:	446b      	add	r3, sp
+ 8001634:	0019      	movs	r1, r3
+ 8001636:	1da8      	adds	r0, r5, #6
+ 8001638:	f7ff fd1c 	bl	8001074 <handle_vendor_options>
+				comp_crc_header(&crc,&response);
+ 800163c:	0021      	movs	r1, r4
+ 800163e:	a802      	add	r0, sp, #8
+				response.status = STATUS_OK;
+ 8001640:	7166      	strb	r6, [r4, #5]
+				comp_crc_header(&crc,&response);
+ 8001642:	f7ff fa71 	bl	8000b28 <comp_crc_header>
+					CRC8_107_add(&crc,*(payload_ptr+i));
+ 8001646:	19a3      	adds	r3, r4, r6
+ 8001648:	7959      	ldrb	r1, [r3, #5]
+ 800164a:	a802      	add	r0, sp, #8
+				for (uint32_t i = 0; i<sizeof(response.payload.vendorOptions)+1; i++)
+ 800164c:	3601      	adds	r6, #1
+					CRC8_107_add(&crc,*(payload_ptr+i));
+ 800164e:	f7ff f87d 	bl	800074c <CRC8_107_add>
+				for (uint32_t i = 0; i<sizeof(response.payload.vendorOptions)+1; i++)
+ 8001652:	2e15      	cmp	r6, #21
+ 8001654:	d1f7      	bne.n	8001646 <handleRS485Message+0x382>
+				response.header.crc = CRC8_107_getChecksum(&crc);
+ 8001656:	a802      	add	r0, sp, #8
+ 8001658:	f7ff f88c 	bl	8000774 <CRC8_107_getChecksum>
+				rs485_transmit((uint8_t *)&response, packet_len);
+ 800165c:	211a      	movs	r1, #26
+				response.header.crc = CRC8_107_getChecksum(&crc);
+ 800165e:	7120      	strb	r0, [r4, #4]
+				response.header.payloadLength = sizeof(response.payload.vendorOptions)+1; // +1 for the status byte
+ 8001660:	70e6      	strb	r6, [r4, #3]
+				rs485_transmit((uint8_t *)&response, packet_len);
+ 8001662:	0020      	movs	r0, r4
+ 8001664:	f7ff fa36 	bl	8000ad4 <rs485_transmit>
+				break;
+ 8001668:	e675      	b.n	8001356 <handleRS485Message+0x92>
+				if(memcmp(UUID,command->payload.getFeederAddress.uuid,UUID_LENGTH) == 0)
+ 800166a:	220c      	movs	r2, #12
+ 800166c:	4830      	ldr	r0, [pc, #192]	@ (8001730 <handleRS485Message+0x46c>)
+ 800166e:	1da9      	adds	r1, r5, #6
+ 8001670:	f003 fd7e 	bl	8005170 <memcmp>
+ 8001674:	2800      	cmp	r0, #0
+ 8001676:	d000      	beq.n	800167a <handleRS485Message+0x3b6>
+ 8001678:	e66d      	b.n	8001356 <handleRS485Message+0x92>
+					response.status = STATUS_OK;
+ 800167a:	7160      	strb	r0, [r4, #5]
+					response.header.payloadLength = 1; // only status byte
+ 800167c:	2301      	movs	r3, #1
+					comp_crc_header(&crc, &response);
+ 800167e:	0021      	movs	r1, r4
+ 8001680:	a802      	add	r0, sp, #8
+					response.header.payloadLength = 1; // only status byte
+ 8001682:	70e3      	strb	r3, [r4, #3]
+					comp_crc_header(&crc, &response);
+ 8001684:	f7ff fa50 	bl	8000b28 <comp_crc_header>
+					CRC8_107_add(&crc, response.status);
+ 8001688:	7961      	ldrb	r1, [r4, #5]
+ 800168a:	a802      	add	r0, sp, #8
+ 800168c:	f7ff f85e 	bl	800074c <CRC8_107_add>
+					response.header.crc = CRC8_107_getChecksum(&crc);
+ 8001690:	e6b9      	b.n	8001406 <handleRS485Message+0x142>
+				if(memcmp(UUID,command->payload.identifyFeeder.uuid,UUID_LENGTH) == 0)
+ 8001692:	220c      	movs	r2, #12
+ 8001694:	4826      	ldr	r0, [pc, #152]	@ (8001730 <handleRS485Message+0x46c>)
+ 8001696:	1da9      	adds	r1, r5, #6
+ 8001698:	f003 fd6a 	bl	8005170 <memcmp>
+ 800169c:	2800      	cmp	r0, #0
+ 800169e:	d000      	beq.n	80016a2 <handleRS485Message+0x3de>
+ 80016a0:	e659      	b.n	8001356 <handleRS485Message+0x92>
+				response.header.payloadLength = 1; // only status byte
+ 80016a2:	2301      	movs	r3, #1
+				comp_crc_header(&crc,&response);
+ 80016a4:	0021      	movs	r1, r4
+					response.status = STATUS_OK;
+ 80016a6:	7160      	strb	r0, [r4, #5]
+				comp_crc_header(&crc,&response);
+ 80016a8:	a802      	add	r0, sp, #8
+				response.header.payloadLength = 1; // only status byte
+ 80016aa:	70e3      	strb	r3, [r4, #3]
+				comp_crc_header(&crc,&response);
+ 80016ac:	f7ff fa3c 	bl	8000b28 <comp_crc_header>
+				CRC8_107_add(&crc,response.status);
+ 80016b0:	7961      	ldrb	r1, [r4, #5]
+ 80016b2:	a802      	add	r0, sp, #8
+ 80016b4:	f7ff f84a 	bl	800074c <CRC8_107_add>
+				response.header.crc = CRC8_107_getChecksum(&crc);
+ 80016b8:	a802      	add	r0, sp, #8
+ 80016ba:	f7ff f85b 	bl	8000774 <CRC8_107_getChecksum>
+				packet_len = sizeof(PhotonPacketHeader) + response.header.payloadLength;
+ 80016be:	78e1      	ldrb	r1, [r4, #3]
+				response.header.crc = CRC8_107_getChecksum(&crc);
+ 80016c0:	7120      	strb	r0, [r4, #4]
+				rs485_transmit((uint8_t *)&response, packet_len);
+ 80016c2:	3105      	adds	r1, #5
+ 80016c4:	0020      	movs	r0, r4
+ 80016c6:	f7ff fa05 	bl	8000ad4 <rs485_transmit>
+				identify_feeder();
+ 80016ca:	f7ff fabb 	bl	8000c44 <identify_feeder>
+				break;
+ 80016ce:	e642      	b.n	8001356 <handleRS485Message+0x92>
+					uint8_t new_address = command->payload.programFeederFloorAddress.address;
+ 80016d0:	7cad      	ldrb	r5, [r5, #18]
+					uint8_t write_success = write_floor_address(new_address);
+ 80016d2:	0028      	movs	r0, r5
+ 80016d4:	f7ff fd8f 	bl	80011f6 <write_floor_address>
+					if (write_success)
+ 80016d8:	2305      	movs	r3, #5
+ 80016da:	2800      	cmp	r0, #0
+ 80016dc:	d100      	bne.n	80016e0 <handleRS485Message+0x41c>
+ 80016de:	e767      	b.n	80015b0 <handleRS485Message+0x2ec>
+						floor_address_status = 2;
+ 80016e0:	2202      	movs	r2, #2
+						floor_address = new_address;
+ 80016e2:	4b14      	ldr	r3, [pc, #80]	@ (8001734 <handleRS485Message+0x470>)
+						my_address = new_address;
+ 80016e4:	703d      	strb	r5, [r7, #0]
+						floor_address = new_address;
+ 80016e6:	701d      	strb	r5, [r3, #0]
+						floor_address_status = 2;
+ 80016e8:	4b13      	ldr	r3, [pc, #76]	@ (8001738 <handleRS485Message+0x474>)
+ 80016ea:	701a      	strb	r2, [r3, #0]
+						response.status = STATUS_OK;
+ 80016ec:	2300      	movs	r3, #0
+ 80016ee:	e75f      	b.n	80015b0 <handleRS485Message+0x2ec>
+				if (is_initialized) return;
+ 80016f0:	4b0e      	ldr	r3, [pc, #56]	@ (800172c <handleRS485Message+0x468>)
+ 80016f2:	781d      	ldrb	r5, [r3, #0]
+ 80016f4:	2d00      	cmp	r5, #0
+ 80016f6:	d000      	beq.n	80016fa <handleRS485Message+0x436>
+ 80016f8:	e62d      	b.n	8001356 <handleRS485Message+0x92>
+				memcpy(response.payload.getFeederId.uuid,UUID,UUID_LENGTH);
+ 80016fa:	2012      	movs	r0, #18
+ 80016fc:	490c      	ldr	r1, [pc, #48]	@ (8001730 <handleRS485Message+0x46c>)
+ 80016fe:	220c      	movs	r2, #12
+ 8001700:	4468      	add	r0, sp
+ 8001702:	f003 fd6f 	bl	80051e4 <memcpy>
+				response.header.payloadLength = sizeof(response.payload.getFeederId)+1;
+ 8001706:	230d      	movs	r3, #13
+				comp_crc_header(&crc,&response);
+ 8001708:	0021      	movs	r1, r4
+ 800170a:	a802      	add	r0, sp, #8
+				response.status=STATUS_OK;
+ 800170c:	7165      	strb	r5, [r4, #5]
+				response.header.payloadLength = sizeof(response.payload.getFeederId)+1;
+ 800170e:	70e3      	strb	r3, [r4, #3]
+				comp_crc_header(&crc,&response);
+ 8001710:	f7ff fa0a 	bl	8000b28 <comp_crc_header>
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
+ 8001714:	78e3      	ldrb	r3, [r4, #3]
+ 8001716:	42ab      	cmp	r3, r5
+ 8001718:	d800      	bhi.n	800171c <handleRS485Message+0x458>
+ 800171a:	e674      	b.n	8001406 <handleRS485Message+0x142>
+					CRC8_107_add(&crc,*(payload_ptr+i));
+ 800171c:	1963      	adds	r3, r4, r5
+ 800171e:	7959      	ldrb	r1, [r3, #5]
+ 8001720:	a802      	add	r0, sp, #8
+ 8001722:	f7ff f813 	bl	800074c <CRC8_107_add>
+				for (uint32_t i = 0; i<response.header.payloadLength; i++)
+ 8001726:	3501      	adds	r5, #1
+ 8001728:	e7f4      	b.n	8001714 <handleRS485Message+0x450>
+ 800172a:	46c0      	nop			@ (mov r8, r8)
+ 800172c:	20000f86 	.word	0x20000f86
+ 8001730:	20000f87 	.word	0x20000f87
+ 8001734:	20000001 	.word	0x20000001
+ 8001738:	200000e8 	.word	0x200000e8
+
+0800173c <debug_itoa>:
+{
+ 800173c:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 800173e:	0004      	movs	r4, r0
+ 8001740:	000d      	movs	r5, r1
+ 8001742:	b087      	sub	sp, #28
+	if (val < 0) { neg = 1; val = -val; }
+ 8001744:	2800      	cmp	r0, #0
+ 8001746:	da1a      	bge.n	800177e <debug_itoa+0x42>
+ 8001748:	2601      	movs	r6, #1
+ 800174a:	4244      	negs	r4, r0
+	uint8_t i = 0, len = 0;
+ 800174c:	2700      	movs	r7, #0
+	else { while (val > 0) { tmp[i++] = '0' + (val % 10); val /= 10; } }
+ 800174e:	0020      	movs	r0, r4
+ 8001750:	210a      	movs	r1, #10
+ 8001752:	9701      	str	r7, [sp, #4]
+ 8001754:	f7fe fe5c 	bl	8000410 <__aeabi_idivmod>
+ 8001758:	9a01      	ldr	r2, [sp, #4]
+ 800175a:	3130      	adds	r1, #48	@ 0x30
+ 800175c:	ab03      	add	r3, sp, #12
+ 800175e:	0020      	movs	r0, r4
+ 8001760:	5499      	strb	r1, [r3, r2]
+ 8001762:	210a      	movs	r1, #10
+ 8001764:	f7fe fd6e 	bl	8000244 <__divsi3>
+ 8001768:	3701      	adds	r7, #1
+ 800176a:	0004      	movs	r4, r0
+ 800176c:	b2ff      	uxtb	r7, r7
+ 800176e:	2800      	cmp	r0, #0
+ 8001770:	d1ed      	bne.n	800174e <debug_itoa+0x12>
+	if (neg) { *buf++ = '-'; len++; }
+ 8001772:	2e00      	cmp	r6, #0
+ 8001774:	d00c      	beq.n	8001790 <debug_itoa+0x54>
+ 8001776:	232d      	movs	r3, #45	@ 0x2d
+ 8001778:	702b      	strb	r3, [r5, #0]
+ 800177a:	3501      	adds	r5, #1
+ 800177c:	e008      	b.n	8001790 <debug_itoa+0x54>
+	if (val == 0) { tmp[i++] = '0'; }
+ 800177e:	2800      	cmp	r0, #0
+ 8001780:	d001      	beq.n	8001786 <debug_itoa+0x4a>
+ 8001782:	2600      	movs	r6, #0
+ 8001784:	e7e2      	b.n	800174c <debug_itoa+0x10>
+ 8001786:	2330      	movs	r3, #48	@ 0x30
+	uint8_t i = 0, len = 0;
+ 8001788:	0006      	movs	r6, r0
+	if (val == 0) { tmp[i++] = '0'; }
+ 800178a:	2701      	movs	r7, #1
+ 800178c:	aa02      	add	r2, sp, #8
+ 800178e:	7113      	strb	r3, [r2, #4]
+ 8001790:	003b      	movs	r3, r7
+	while (i > 0) { *buf++ = tmp[--i]; len++; }
+ 8001792:	2b00      	cmp	r3, #0
+ 8001794:	d103      	bne.n	800179e <debug_itoa+0x62>
+	return len;
+ 8001796:	19f0      	adds	r0, r6, r7
+ 8001798:	b2c0      	uxtb	r0, r0
+}
+ 800179a:	b007      	add	sp, #28
+ 800179c:	bdf0      	pop	{r4, r5, r6, r7, pc}
+	while (i > 0) { *buf++ = tmp[--i]; len++; }
+ 800179e:	3b01      	subs	r3, #1
+ 80017a0:	b2db      	uxtb	r3, r3
+ 80017a2:	aa03      	add	r2, sp, #12
+ 80017a4:	5cd2      	ldrb	r2, [r2, r3]
+ 80017a6:	702a      	strb	r2, [r5, #0]
+ 80017a8:	3501      	adds	r5, #1
+ 80017aa:	e7f2      	b.n	8001792 <debug_itoa+0x56>
+
+080017ac <debug_hex8>:
+{
+ 80017ac:	b570      	push	{r4, r5, r6, lr}
+ 80017ae:	0004      	movs	r4, r0
+ 80017b0:	000d      	movs	r5, r1
+ 80017b2:	b086      	sub	sp, #24
+	const char hex[] = "0123456789ABCDEF";
+ 80017b4:	ae01      	add	r6, sp, #4
+ 80017b6:	2211      	movs	r2, #17
+ 80017b8:	0030      	movs	r0, r6
+ 80017ba:	4906      	ldr	r1, [pc, #24]	@ (80017d4 <debug_hex8+0x28>)
+ 80017bc:	f003 fd12 	bl	80051e4 <memcpy>
+	buf[0] = hex[(val >> 4) & 0x0F];
+ 80017c0:	0923      	lsrs	r3, r4, #4
+ 80017c2:	5cf3      	ldrb	r3, [r6, r3]
+}
+ 80017c4:	2002      	movs	r0, #2
+	buf[0] = hex[(val >> 4) & 0x0F];
+ 80017c6:	702b      	strb	r3, [r5, #0]
+	buf[1] = hex[val & 0x0F];
+ 80017c8:	230f      	movs	r3, #15
+ 80017ca:	401c      	ands	r4, r3
+ 80017cc:	5d33      	ldrb	r3, [r6, r4]
+ 80017ce:	706b      	strb	r3, [r5, #1]
+}
+ 80017d0:	b006      	add	sp, #24
+ 80017d2:	bd70      	pop	{r4, r5, r6, pc}
+ 80017d4:	08005210 	.word	0x08005210
+
+080017d8 <debug_output>:
+{
+ 80017d8:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+	if (!debug_enabled) return;
+ 80017da:	4b6b      	ldr	r3, [pc, #428]	@ (8001988 <debug_output+0x1b0>)
+ 80017dc:	781b      	ldrb	r3, [r3, #0]
+ 80017de:	2b00      	cmp	r3, #0
+ 80017e0:	d100      	bne.n	80017e4 <debug_output+0xc>
+ 80017e2:	e0cf      	b.n	8001984 <debug_output+0x1ac>
+	uint32_t now = HAL_GetTick();
+ 80017e4:	f001 f87c 	bl	80028e0 <HAL_GetTick>
+	if ((now - last_debug_output_time) < DEBUG_OUTPUT_INTERVAL_MS) return;
+ 80017e8:	4a68      	ldr	r2, [pc, #416]	@ (800198c <debug_output+0x1b4>)
+ 80017ea:	6813      	ldr	r3, [r2, #0]
+ 80017ec:	1ac3      	subs	r3, r0, r3
+ 80017ee:	2b63      	cmp	r3, #99	@ 0x63
+ 80017f0:	d800      	bhi.n	80017f4 <debug_output+0x1c>
+ 80017f2:	e0c7      	b.n	8001984 <debug_output+0x1ac>
+	*p++ = '$'; *p++ = 'P'; *p++ = ':';
+ 80017f4:	2324      	movs	r3, #36	@ 0x24
+ 80017f6:	243a      	movs	r4, #58	@ 0x3a
+ 80017f8:	4d65      	ldr	r5, [pc, #404]	@ (8001990 <debug_output+0x1b8>)
+	p += debug_itoa(total_count, p);
+ 80017fa:	4e66      	ldr	r6, [pc, #408]	@ (8001994 <debug_output+0x1bc>)
+ 80017fc:	4f66      	ldr	r7, [pc, #408]	@ (8001998 <debug_output+0x1c0>)
+	last_debug_output_time = now;
+ 80017fe:	6010      	str	r0, [r2, #0]
+	p += debug_itoa(total_count, p);
+ 8001800:	0039      	movs	r1, r7
+ 8001802:	6830      	ldr	r0, [r6, #0]
+	*p++ = '$'; *p++ = 'P'; *p++ = ':';
+ 8001804:	702b      	strb	r3, [r5, #0]
+ 8001806:	332c      	adds	r3, #44	@ 0x2c
+ 8001808:	706b      	strb	r3, [r5, #1]
+ 800180a:	70ac      	strb	r4, [r5, #2]
+	p += debug_itoa(total_count, p);
+ 800180c:	f7ff ff96 	bl	800173c <debug_itoa>
+ 8001810:	183f      	adds	r7, r7, r0
+	*p++ = ':';
+ 8001812:	1c7b      	adds	r3, r7, #1
+ 8001814:	703c      	strb	r4, [r7, #0]
+	p += debug_itoa(target_count, p);
+ 8001816:	4f61      	ldr	r7, [pc, #388]	@ (800199c <debug_output+0x1c4>)
+ 8001818:	0019      	movs	r1, r3
+ 800181a:	6838      	ldr	r0, [r7, #0]
+	*p++ = ':';
+ 800181c:	9301      	str	r3, [sp, #4]
+	p += debug_itoa(target_count, p);
+ 800181e:	f7ff ff8d 	bl	800173c <debug_itoa>
+ 8001822:	9b01      	ldr	r3, [sp, #4]
+ 8001824:	1818      	adds	r0, r3, r0
+	*p++ = ':';
+ 8001826:	1c43      	adds	r3, r0, #1
+ 8001828:	9301      	str	r3, [sp, #4]
+ 800182a:	7004      	strb	r4, [r0, #0]
+	p += debug_itoa(target_count - total_count, p);
+ 800182c:	6833      	ldr	r3, [r6, #0]
+ 800182e:	6838      	ldr	r0, [r7, #0]
+ 8001830:	9901      	ldr	r1, [sp, #4]
+ 8001832:	1ac0      	subs	r0, r0, r3
+ 8001834:	f7ff ff82 	bl	800173c <debug_itoa>
+ 8001838:	9b01      	ldr	r3, [sp, #4]
+	*p++ = ','; *p++ = 'I'; *p++ = ':';
+ 800183a:	272c      	movs	r7, #44	@ 0x2c
+	p += debug_itoa(target_count - total_count, p);
+ 800183c:	1818      	adds	r0, r3, r0
+	*p++ = ','; *p++ = 'I'; *p++ = ':';
+ 800183e:	2349      	movs	r3, #73	@ 0x49
+ 8001840:	7043      	strb	r3, [r0, #1]
+	p += debug_itoa(debug_pid_output, p);
+ 8001842:	4b57      	ldr	r3, [pc, #348]	@ (80019a0 <debug_output+0x1c8>)
+	*p++ = ','; *p++ = 'I'; *p++ = ':';
+ 8001844:	1cc6      	adds	r6, r0, #3
+ 8001846:	7007      	strb	r7, [r0, #0]
+ 8001848:	7084      	strb	r4, [r0, #2]
+	p += debug_itoa(debug_pid_output, p);
+ 800184a:	8818      	ldrh	r0, [r3, #0]
+ 800184c:	0031      	movs	r1, r6
+ 800184e:	b200      	sxth	r0, r0
+ 8001850:	f7ff ff74 	bl	800173c <debug_itoa>
+	*p++ = ','; *p++ = 'S'; *p++ = ':';
+ 8001854:	2353      	movs	r3, #83	@ 0x53
+	p += debug_itoa(debug_pid_output, p);
+ 8001856:	1830      	adds	r0, r6, r0
+	*p++ = ','; *p++ = 'S'; *p++ = ':';
+ 8001858:	7043      	strb	r3, [r0, #1]
+	*p++ = '0' + feed_state; // State as single digit 0-9
+ 800185a:	4b52      	ldr	r3, [pc, #328]	@ (80019a4 <debug_output+0x1cc>)
+	*p++ = ','; *p++ = 'C'; *p++ = ':';
+ 800185c:	0006      	movs	r6, r0
+	*p++ = '0' + feed_state; // State as single digit 0-9
+ 800185e:	781b      	ldrb	r3, [r3, #0]
+	*p++ = ','; *p++ = 'S'; *p++ = ':';
+ 8001860:	7007      	strb	r7, [r0, #0]
+	*p++ = '0' + feed_state; // State as single digit 0-9
+ 8001862:	3330      	adds	r3, #48	@ 0x30
+ 8001864:	70c3      	strb	r3, [r0, #3]
+	*p++ = ','; *p++ = 'F'; *p++ = ':';
+ 8001866:	2346      	movs	r3, #70	@ 0x46
+ 8001868:	7143      	strb	r3, [r0, #5]
+	*p++ = '0' + is_initialized;
+ 800186a:	4b4f      	ldr	r3, [pc, #316]	@ (80019a8 <debug_output+0x1d0>)
+	*p++ = ','; *p++ = 'S'; *p++ = ':';
+ 800186c:	7084      	strb	r4, [r0, #2]
+	*p++ = '0' + is_initialized;
+ 800186e:	781b      	ldrb	r3, [r3, #0]
+	*p++ = ','; *p++ = 'F'; *p++ = ':';
+ 8001870:	7107      	strb	r7, [r0, #4]
+	*p++ = '0' + is_initialized;
+ 8001872:	3330      	adds	r3, #48	@ 0x30
+ 8001874:	71c3      	strb	r3, [r0, #7]
+	*p++ = '0' + feed_in_progress;
+ 8001876:	4b4d      	ldr	r3, [pc, #308]	@ (80019ac <debug_output+0x1d4>)
+	*p++ = ','; *p++ = 'F'; *p++ = ':';
+ 8001878:	7184      	strb	r4, [r0, #6]
+	*p++ = '0' + feed_in_progress;
+ 800187a:	781b      	ldrb	r3, [r3, #0]
+	*p++ = ','; *p++ = 'C'; *p++ = ':';
+ 800187c:	7247      	strb	r7, [r0, #9]
+	*p++ = '0' + feed_in_progress;
+ 800187e:	3330      	adds	r3, #48	@ 0x30
+ 8001880:	7203      	strb	r3, [r0, #8]
+	*p++ = ','; *p++ = 'C'; *p++ = ':';
+ 8001882:	2343      	movs	r3, #67	@ 0x43
+ 8001884:	7283      	strb	r3, [r0, #10]
+	p += debug_itoa(feed_ok_count, p);
+ 8001886:	4b4a      	ldr	r3, [pc, #296]	@ (80019b0 <debug_output+0x1d8>)
+	*p++ = ','; *p++ = 'C'; *p++ = ':';
+ 8001888:	72c4      	strb	r4, [r0, #11]
+	p += debug_itoa(feed_ok_count, p);
+ 800188a:	8818      	ldrh	r0, [r3, #0]
+	*p++ = ','; *p++ = 'C'; *p++ = ':';
+ 800188c:	360c      	adds	r6, #12
+	p += debug_itoa(feed_ok_count, p);
+ 800188e:	0031      	movs	r1, r6
+ 8001890:	b280      	uxth	r0, r0
+ 8001892:	f7ff ff53 	bl	800173c <debug_itoa>
+	p += debug_itoa(feed_fail_count, p);
+ 8001896:	4b47      	ldr	r3, [pc, #284]	@ (80019b4 <debug_output+0x1dc>)
+	p += debug_itoa(feed_ok_count, p);
+ 8001898:	1830      	adds	r0, r6, r0
+	*p++ = ':';
+ 800189a:	1c46      	adds	r6, r0, #1
+ 800189c:	7004      	strb	r4, [r0, #0]
+	p += debug_itoa(feed_fail_count, p);
+ 800189e:	8818      	ldrh	r0, [r3, #0]
+ 80018a0:	0031      	movs	r1, r6
+ 80018a2:	b280      	uxth	r0, r0
+ 80018a4:	f7ff ff4a 	bl	800173c <debug_itoa>
+	p += debug_itoa(brake_time_tenths, p);
+ 80018a8:	4b43      	ldr	r3, [pc, #268]	@ (80019b8 <debug_output+0x1e0>)
+	p += debug_itoa(feed_fail_count, p);
+ 80018aa:	1830      	adds	r0, r6, r0
+	*p++ = ':';
+ 80018ac:	1c46      	adds	r6, r0, #1
+	p += debug_itoa(brake_time_tenths, p);
+ 80018ae:	0031      	movs	r1, r6
+	*p++ = ':';
+ 80018b0:	7004      	strb	r4, [r0, #0]
+	p += debug_itoa(brake_time_tenths, p);
+ 80018b2:	6818      	ldr	r0, [r3, #0]
+ 80018b4:	f7ff ff42 	bl	800173c <debug_itoa>
+	p += debug_itoa(feed_retry_total, p);
+ 80018b8:	4b40      	ldr	r3, [pc, #256]	@ (80019bc <debug_output+0x1e4>)
+	p += debug_itoa(brake_time_tenths, p);
+ 80018ba:	1830      	adds	r0, r6, r0
+	*p++ = ':';
+ 80018bc:	1c46      	adds	r6, r0, #1
+ 80018be:	7004      	strb	r4, [r0, #0]
+	p += debug_itoa(feed_retry_total, p);
+ 80018c0:	8818      	ldrh	r0, [r3, #0]
+ 80018c2:	0031      	movs	r1, r6
+ 80018c4:	b280      	uxth	r0, r0
+ 80018c6:	f7ff ff39 	bl	800173c <debug_itoa>
+	*p++ = ','; *p++ = 'A'; *p++ = ':';
+ 80018ca:	2341      	movs	r3, #65	@ 0x41
+	p += debug_itoa(feed_retry_total, p);
+ 80018cc:	1836      	adds	r6, r6, r0
+	*p++ = ','; *p++ = 'A'; *p++ = ':';
+ 80018ce:	7073      	strb	r3, [r6, #1]
+	p += debug_hex8(my_address, p);
+ 80018d0:	4b3b      	ldr	r3, [pc, #236]	@ (80019c0 <debug_output+0x1e8>)
+	*p++ = ','; *p++ = 'A'; *p++ = ':';
+ 80018d2:	7037      	strb	r7, [r6, #0]
+ 80018d4:	70b4      	strb	r4, [r6, #2]
+ 80018d6:	1cf1      	adds	r1, r6, #3
+	p += debug_hex8(my_address, p);
+ 80018d8:	7818      	ldrb	r0, [r3, #0]
+ 80018da:	f7ff ff67 	bl	80017ac <debug_hex8>
+	*p++ = ','; *p++ = 'R'; *p++ = ':';
+ 80018de:	2352      	movs	r3, #82	@ 0x52
+ 80018e0:	71b3      	strb	r3, [r6, #6]
+ 80018e2:	0033      	movs	r3, r6
+ 80018e4:	3308      	adds	r3, #8
+ 80018e6:	9301      	str	r3, [sp, #4]
+	p += debug_itoa(drop_crc, p);
+ 80018e8:	4b36      	ldr	r3, [pc, #216]	@ (80019c4 <debug_output+0x1ec>)
+	*p++ = ','; *p++ = 'R'; *p++ = ':';
+ 80018ea:	7177      	strb	r7, [r6, #5]
+	p += debug_itoa(drop_crc, p);
+ 80018ec:	8818      	ldrh	r0, [r3, #0]
+	*p++ = ','; *p++ = 'R'; *p++ = ':';
+ 80018ee:	71f4      	strb	r4, [r6, #7]
+	p += debug_itoa(drop_crc, p);
+ 80018f0:	9901      	ldr	r1, [sp, #4]
+ 80018f2:	b280      	uxth	r0, r0
+ 80018f4:	f7ff ff22 	bl	800173c <debug_itoa>
+ 80018f8:	9b01      	ldr	r3, [sp, #4]
+ 80018fa:	1818      	adds	r0, r3, r0
+	p += debug_itoa(msg_handled, p);
+ 80018fc:	4b32      	ldr	r3, [pc, #200]	@ (80019c8 <debug_output+0x1f0>)
+	*p++ = ':';
+ 80018fe:	1c46      	adds	r6, r0, #1
+ 8001900:	7004      	strb	r4, [r0, #0]
+	p += debug_itoa(msg_handled, p);
+ 8001902:	8818      	ldrh	r0, [r3, #0]
+ 8001904:	0031      	movs	r1, r6
+ 8001906:	b280      	uxth	r0, r0
+ 8001908:	f7ff ff18 	bl	800173c <debug_itoa>
+	p += debug_itoa(uart_error_count, p);
+ 800190c:	4b2f      	ldr	r3, [pc, #188]	@ (80019cc <debug_output+0x1f4>)
+	p += debug_itoa(msg_handled, p);
+ 800190e:	1830      	adds	r0, r6, r0
+	*p++ = ':';
+ 8001910:	1c46      	adds	r6, r0, #1
+ 8001912:	7004      	strb	r4, [r0, #0]
+	p += debug_itoa(uart_error_count, p);
+ 8001914:	8818      	ldrh	r0, [r3, #0]
+ 8001916:	0031      	movs	r1, r6
+ 8001918:	b280      	uxth	r0, r0
+ 800191a:	f7ff ff0f 	bl	800173c <debug_itoa>
+	*p++ = ','; *p++ = 'T'; *p++ = ':';
+ 800191e:	2354      	movs	r3, #84	@ 0x54
+	p += debug_itoa(uart_error_count, p);
+ 8001920:	1830      	adds	r0, r6, r0
+	*p++ = ','; *p++ = 'T'; *p++ = ':';
+ 8001922:	7007      	strb	r7, [r0, #0]
+	p += debug_itoa(my_addr_size, p);
+ 8001924:	4f2a      	ldr	r7, [pc, #168]	@ (80019d0 <debug_output+0x1f8>)
+	*p++ = ','; *p++ = 'T'; *p++ = ':';
+ 8001926:	1cc6      	adds	r6, r0, #3
+ 8001928:	7084      	strb	r4, [r0, #2]
+ 800192a:	7043      	strb	r3, [r0, #1]
+	p += debug_itoa(my_addr_size, p);
+ 800192c:	7838      	ldrb	r0, [r7, #0]
+ 800192e:	0031      	movs	r1, r6
+ 8001930:	b2c0      	uxtb	r0, r0
+ 8001932:	f7ff ff03 	bl	800173c <debug_itoa>
+ 8001936:	1830      	adds	r0, r6, r0
+	*p++ = ':';
+ 8001938:	7004      	strb	r4, [r0, #0]
+ 800193a:	2400      	movs	r4, #0
+ 800193c:	1c46      	adds	r6, r0, #1
+	for (uint8_t i = 0; i < 8 && i < my_addr_size; i++)
+ 800193e:	783a      	ldrb	r2, [r7, #0]
+ 8001940:	b2e3      	uxtb	r3, r4
+ 8001942:	429a      	cmp	r2, r3
+ 8001944:	d909      	bls.n	800195a <debug_output+0x182>
+		p += debug_hex8(my_addr_bytes[i], p);
+ 8001946:	4b23      	ldr	r3, [pc, #140]	@ (80019d4 <debug_output+0x1fc>)
+ 8001948:	0031      	movs	r1, r6
+ 800194a:	5d18      	ldrb	r0, [r3, r4]
+	for (uint8_t i = 0; i < 8 && i < my_addr_size; i++)
+ 800194c:	3401      	adds	r4, #1
+		p += debug_hex8(my_addr_bytes[i], p);
+ 800194e:	b2c0      	uxtb	r0, r0
+ 8001950:	f7ff ff2c 	bl	80017ac <debug_hex8>
+ 8001954:	3602      	adds	r6, #2
+	for (uint8_t i = 0; i < 8 && i < my_addr_size; i++)
+ 8001956:	2c08      	cmp	r4, #8
+ 8001958:	d1f1      	bne.n	800193e <debug_output+0x166>
+	*p++ = ':';
+ 800195a:	233a      	movs	r3, #58	@ 0x3a
+ 800195c:	7033      	strb	r3, [r6, #0]
+	p += debug_hex8(my_addr_crc_exp, p);
+ 800195e:	4b1e      	ldr	r3, [pc, #120]	@ (80019d8 <debug_output+0x200>)
+	*p++ = ':';
+ 8001960:	1c71      	adds	r1, r6, #1
+	p += debug_hex8(my_addr_crc_exp, p);
+ 8001962:	7818      	ldrb	r0, [r3, #0]
+ 8001964:	b2c0      	uxtb	r0, r0
+ 8001966:	f7ff ff21 	bl	80017ac <debug_hex8>
+	*p++ = '*'; *p++ = '\r'; *p++ = '\n';
+ 800196a:	232a      	movs	r3, #42	@ 0x2a
+ 800196c:	70f3      	strb	r3, [r6, #3]
+ 800196e:	3b1d      	subs	r3, #29
+ 8001970:	7133      	strb	r3, [r6, #4]
+ 8001972:	3b03      	subs	r3, #3
+ 8001974:	7173      	strb	r3, [r6, #5]
+ 8001976:	3606      	adds	r6, #6
+	HAL_UART_Transmit(&huart1, (uint8_t*)debug_tx_buffer, p - debug_tx_buffer, 10);
+ 8001978:	1b72      	subs	r2, r6, r5
+ 800197a:	0029      	movs	r1, r5
+ 800197c:	4817      	ldr	r0, [pc, #92]	@ (80019dc <debug_output+0x204>)
+ 800197e:	b292      	uxth	r2, r2
+ 8001980:	f003 f999 	bl	8004cb6 <HAL_UART_Transmit>
+}
+ 8001984:	bdf7      	pop	{r0, r1, r2, r4, r5, r6, r7, pc}
+ 8001986:	46c0      	nop			@ (mov r8, r8)
+ 8001988:	20000000 	.word	0x20000000
+ 800198c:	200000e0 	.word	0x200000e0
+ 8001990:	2000007e 	.word	0x2000007e
+ 8001994:	20000154 	.word	0x20000154
+ 8001998:	20000081 	.word	0x20000081
+ 800199c:	20000150 	.word	0x20000150
+ 80019a0:	2000007c 	.word	0x2000007c
+ 80019a4:	20000118 	.word	0x20000118
+ 80019a8:	20000f86 	.word	0x20000f86
+ 80019ac:	20000121 	.word	0x20000121
+ 80019b0:	2000011e 	.word	0x2000011e
+ 80019b4:	2000011c 	.word	0x2000011c
+ 80019b8:	20000004 	.word	0x20000004
+ 80019bc:	2000011a 	.word	0x2000011a
+ 80019c0:	20000020 	.word	0x20000020
+ 80019c4:	20000076 	.word	0x20000076
+ 80019c8:	20000072 	.word	0x20000072
+ 80019cc:	2000007a 	.word	0x2000007a
+ 80019d0:	2000005e 	.word	0x2000005e
+ 80019d4:	2000005f 	.word	0x2000005f
+ 80019d8:	2000005d 	.word	0x2000005d
+ 80019dc:	200010ec 	.word	0x200010ec
+
+080019e0 <reset_position_if_needed>:
+{
+ 80019e0:	b570      	push	{r4, r5, r6, lr}
+	if ((total_count % counts_per_mm) == 0 && feed_state == FEED_STATE_IDLE)
+ 80019e2:	4d12      	ldr	r5, [pc, #72]	@ (8001a2c <reset_position_if_needed+0x4c>)
+ 80019e4:	4b12      	ldr	r3, [pc, #72]	@ (8001a30 <reset_position_if_needed+0x50>)
+ 80019e6:	6828      	ldr	r0, [r5, #0]
+ 80019e8:	4a12      	ldr	r2, [pc, #72]	@ (8001a34 <reset_position_if_needed+0x54>)
+ 80019ea:	4343      	muls	r3, r0
+ 80019ec:	189b      	adds	r3, r3, r2
+ 80019ee:	4a12      	ldr	r2, [pc, #72]	@ (8001a38 <reset_position_if_needed+0x58>)
+ 80019f0:	4293      	cmp	r3, r2
+ 80019f2:	d819      	bhi.n	8001a28 <reset_position_if_needed+0x48>
+ 80019f4:	4b11      	ldr	r3, [pc, #68]	@ (8001a3c <reset_position_if_needed+0x5c>)
+ 80019f6:	781b      	ldrb	r3, [r3, #0]
+ 80019f8:	b2dc      	uxtb	r4, r3
+ 80019fa:	2b00      	cmp	r3, #0
+ 80019fc:	d114      	bne.n	8001a28 <reset_position_if_needed+0x48>
+		int32_t mm_moved = total_count / counts_per_mm;
+ 80019fe:	21e1      	movs	r1, #225	@ 0xe1
+ 8001a00:	f7fe fc20 	bl	8000244 <__divsi3>
+		mm_position += mm_moved;
+ 8001a04:	4e0e      	ldr	r6, [pc, #56]	@ (8001a40 <reset_position_if_needed+0x60>)
+ 8001a06:	6833      	ldr	r3, [r6, #0]
+ 8001a08:	181b      	adds	r3, r3, r0
+ 8001a0a:	6033      	str	r3, [r6, #0]
+  __ASM volatile ("cpsid i" : : : "memory");
+ 8001a0c:	b672      	cpsid	i
+		encoder_count_extra = 0;
+ 8001a0e:	4b0d      	ldr	r3, [pc, #52]	@ (8001a44 <reset_position_if_needed+0x64>)
+		total_count = 0;
+ 8001a10:	602c      	str	r4, [r5, #0]
+		encoder_count_extra = 0;
+ 8001a12:	601c      	str	r4, [r3, #0]
+		htim3.Instance->CNT = 0;
+ 8001a14:	4b0c      	ldr	r3, [pc, #48]	@ (8001a48 <reset_position_if_needed+0x68>)
+ 8001a16:	681b      	ldr	r3, [r3, #0]
+ 8001a18:	625c      	str	r4, [r3, #36]	@ 0x24
+		encoder_previous = 0;
+ 8001a1a:	4b0c      	ldr	r3, [pc, #48]	@ (8001a4c <reset_position_if_needed+0x6c>)
+ 8001a1c:	801c      	strh	r4, [r3, #0]
+		target_count = 0;
+ 8001a1e:	4b0c      	ldr	r3, [pc, #48]	@ (8001a50 <reset_position_if_needed+0x70>)
+ 8001a20:	601c      	str	r4, [r3, #0]
+		feed_target_position = 0;
+ 8001a22:	4b0c      	ldr	r3, [pc, #48]	@ (8001a54 <reset_position_if_needed+0x74>)
+ 8001a24:	601c      	str	r4, [r3, #0]
+  __ASM volatile ("cpsie i" : : : "memory");
+ 8001a26:	b662      	cpsie	i
+}
+ 8001a28:	bd70      	pop	{r4, r5, r6, pc}
+ 8001a2a:	46c0      	nop			@ (mov r8, r8)
+ 8001a2c:	20000154 	.word	0x20000154
+ 8001a30:	87654321 	.word	0x87654321
+ 8001a34:	0091a2b3 	.word	0x0091a2b3
+ 8001a38:	01234566 	.word	0x01234566
+ 8001a3c:	20000118 	.word	0x20000118
+ 8001a40:	200000e4 	.word	0x200000e4
+ 8001a44:	20000f98 	.word	0x20000f98
+ 8001a48:	20001264 	.word	0x20001264
+ 8001a4c:	20000f94 	.word	0x20000f94
+ 8001a50:	20000150 	.word	0x20000150
+ 8001a54:	20000104 	.word	0x20000104
+
+08001a58 <main>:
+{
+ 8001a58:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 8001a5a:	b0a3      	sub	sp, #140	@ 0x8c
+  HAL_Init();
+ 8001a5c:	f000 ff28 	bl	80028b0 <HAL_Init>
+  pid_init(&motor_pid,kp,ki,kd,i_min,i_max,PWM_MAX,pid_max_step);
+ 8001a60:	4bd4      	ldr	r3, [pc, #848]	@ (8001db4 <main+0x35c>)
+ 8001a62:	4ed5      	ldr	r6, [pc, #852]	@ (8001db8 <main+0x360>)
+ 8001a64:	681d      	ldr	r5, [r3, #0]
+ 8001a66:	4bd5      	ldr	r3, [pc, #852]	@ (8001dbc <main+0x364>)
+                            int32_t integrator_min,
+                            int32_t integrator_max,
+                            int32_t out_max,
+                            int32_t max_output_step)
+{
+    pid->kp = kp;
+ 8001a68:	6836      	ldr	r6, [r6, #0]
+ 8001a6a:	681c      	ldr	r4, [r3, #0]
+ 8001a6c:	4bd4      	ldr	r3, [pc, #848]	@ (8001dc0 <main+0x368>)
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8001a6e:	af15      	add	r7, sp, #84	@ 0x54
+  pid_init(&motor_pid,kp,ki,kd,i_min,i_max,PWM_MAX,pid_max_step);
+ 8001a70:	6818      	ldr	r0, [r3, #0]
+ 8001a72:	4bd4      	ldr	r3, [pc, #848]	@ (8001dc4 <main+0x36c>)
+ 8001a74:	6819      	ldr	r1, [r3, #0]
+ 8001a76:	4bd4      	ldr	r3, [pc, #848]	@ (8001dc8 <main+0x370>)
+ 8001a78:	681a      	ldr	r2, [r3, #0]
+ 8001a7a:	4bd4      	ldr	r3, [pc, #848]	@ (8001dcc <main+0x374>)
+
+    pid->integrator = 0;
+    pid->prev_error = 0;
+
+    pid->integrator_min = integrator_min;
+    pid->integrator_max = integrator_max;
+ 8001a7c:	6199      	str	r1, [r3, #24]
+    pid->out_max        = out_max;
+ 8001a7e:	2196      	movs	r1, #150	@ 0x96
+    pid->ki = ki;
+ 8001a80:	605d      	str	r5, [r3, #4]
+    pid->integrator = 0;
+ 8001a82:	2500      	movs	r5, #0
+    pid->out_max        = out_max;
+ 8001a84:	0109      	lsls	r1, r1, #4
+    pid->kp = kp;
+ 8001a86:	601e      	str	r6, [r3, #0]
+    pid->kd = kd;
+ 8001a88:	609c      	str	r4, [r3, #8]
+    pid->integrator_min = integrator_min;
+ 8001a8a:	6158      	str	r0, [r3, #20]
+    pid->out_max        = out_max;
+ 8001a8c:	61d9      	str	r1, [r3, #28]
+
+    pid->max_output_step = max_output_step;
+ 8001a8e:	621a      	str	r2, [r3, #32]
+    pid->integrator = 0;
+ 8001a90:	60dd      	str	r5, [r3, #12]
+    pid->prev_error = 0;
+ 8001a92:	611d      	str	r5, [r3, #16]
+    pid->last_output     = 0;
+ 8001a94:	625d      	str	r5, [r3, #36]	@ 0x24
+  SystemClock_Config();
+ 8001a96:	f7fe fe71 	bl	800077c <SystemClock_Config>
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 8001a9a:	2214      	movs	r2, #20
+ 8001a9c:	0029      	movs	r1, r5
+ 8001a9e:	0038      	movs	r0, r7
+ 8001aa0:	f003 fb74 	bl	800518c <memset>
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+ 8001aa4:	2220      	movs	r2, #32
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8001aa6:	2601      	movs	r6, #1
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+ 8001aa8:	4cc9      	ldr	r4, [pc, #804]	@ (8001dd0 <main+0x378>)
+  HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
+ 8001aaa:	20a0      	movs	r0, #160	@ 0xa0
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+ 8001aac:	6b63      	ldr	r3, [r4, #52]	@ 0x34
+  HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
+ 8001aae:	2141      	movs	r1, #65	@ 0x41
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+ 8001ab0:	4313      	orrs	r3, r2
+ 8001ab2:	6363      	str	r3, [r4, #52]	@ 0x34
+ 8001ab4:	6b63      	ldr	r3, [r4, #52]	@ 0x34
+  HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
+ 8001ab6:	05c0      	lsls	r0, r0, #23
+  __HAL_RCC_GPIOF_CLK_ENABLE();
+ 8001ab8:	4013      	ands	r3, r2
+ 8001aba:	9303      	str	r3, [sp, #12]
+ 8001abc:	9b03      	ldr	r3, [sp, #12]
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8001abe:	6b63      	ldr	r3, [r4, #52]	@ 0x34
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8001ac0:	3a1e      	subs	r2, #30
+  __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8001ac2:	4333      	orrs	r3, r6
+ 8001ac4:	6363      	str	r3, [r4, #52]	@ 0x34
+ 8001ac6:	6b63      	ldr	r3, [r4, #52]	@ 0x34
+ 8001ac8:	4033      	ands	r3, r6
+ 8001aca:	9304      	str	r3, [sp, #16]
+ 8001acc:	9b04      	ldr	r3, [sp, #16]
+  __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8001ace:	6b63      	ldr	r3, [r4, #52]	@ 0x34
+ 8001ad0:	4313      	orrs	r3, r2
+ 8001ad2:	6363      	str	r3, [r4, #52]	@ 0x34
+ 8001ad4:	6b63      	ldr	r3, [r4, #52]	@ 0x34
+ 8001ad6:	4013      	ands	r3, r2
+ 8001ad8:	9305      	str	r3, [sp, #20]
+ 8001ada:	9b05      	ldr	r3, [sp, #20]
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+ 8001adc:	6b63      	ldr	r3, [r4, #52]	@ 0x34
+ 8001ade:	3202      	adds	r2, #2
+ 8001ae0:	4313      	orrs	r3, r2
+ 8001ae2:	6363      	str	r3, [r4, #52]	@ 0x34
+ 8001ae4:	6b63      	ldr	r3, [r4, #52]	@ 0x34
+ 8001ae6:	4013      	ands	r3, r2
+ 8001ae8:	9306      	str	r3, [sp, #24]
+  HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
+ 8001aea:	002a      	movs	r2, r5
+  __HAL_RCC_GPIOC_CLK_ENABLE();
+ 8001aec:	9b06      	ldr	r3, [sp, #24]
+  HAL_GPIO_WritePin(GPIOA, USART2_NRE_Pin|ONEWIRE_Pin, GPIO_PIN_RESET);
+ 8001aee:	f001 fc11 	bl	8003314 <HAL_GPIO_WritePin>
+  HAL_GPIO_WritePin(GPIOB, LED_R_Pin|LED_B_Pin|LED_G_Pin, GPIO_PIN_RESET);
+ 8001af2:	002a      	movs	r2, r5
+ 8001af4:	2138      	movs	r1, #56	@ 0x38
+ 8001af6:	48b7      	ldr	r0, [pc, #732]	@ (8001dd4 <main+0x37c>)
+ 8001af8:	f001 fc0c 	bl	8003314 <HAL_GPIO_WritePin>
+  HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
+ 8001afc:	20a0      	movs	r0, #160	@ 0xa0
+  GPIO_InitStruct.Pin = USART2_NRE_Pin;
+ 8001afe:	9615      	str	r6, [sp, #84]	@ 0x54
+  HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
+ 8001b00:	0039      	movs	r1, r7
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 8001b02:	607e      	str	r6, [r7, #4]
+  HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
+ 8001b04:	05c0      	lsls	r0, r0, #23
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001b06:	60bd      	str	r5, [r7, #8]
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001b08:	60fd      	str	r5, [r7, #12]
+  HAL_GPIO_Init(USART2_NRE_GPIO_Port, &GPIO_InitStruct);
+ 8001b0a:	f001 fb43 	bl	8003194 <HAL_GPIO_Init>
+  GPIO_InitStruct.Pin = ONEWIRE_Pin;
+ 8001b0e:	2340      	movs	r3, #64	@ 0x40
+  HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
+ 8001b10:	20a0      	movs	r0, #160	@ 0xa0
+  GPIO_InitStruct.Pin = ONEWIRE_Pin;
+ 8001b12:	9315      	str	r3, [sp, #84]	@ 0x54
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+ 8001b14:	3b2f      	subs	r3, #47	@ 0x2f
+  HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
+ 8001b16:	0039      	movs	r1, r7
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_OD;
+ 8001b18:	607b      	str	r3, [r7, #4]
+  HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
+ 8001b1a:	05c0      	lsls	r0, r0, #23
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001b1c:	60bd      	str	r5, [r7, #8]
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001b1e:	60fd      	str	r5, [r7, #12]
+  HAL_GPIO_Init(ONEWIRE_GPIO_Port, &GPIO_InitStruct);
+ 8001b20:	f001 fb38 	bl	8003194 <HAL_GPIO_Init>
+  GPIO_InitStruct.Pin = LED_R_Pin|LED_B_Pin|LED_G_Pin;
+ 8001b24:	2338      	movs	r3, #56	@ 0x38
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8001b26:	0039      	movs	r1, r7
+  GPIO_InitStruct.Pin = LED_R_Pin|LED_B_Pin|LED_G_Pin;
+ 8001b28:	9315      	str	r3, [sp, #84]	@ 0x54
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8001b2a:	48aa      	ldr	r0, [pc, #680]	@ (8001dd4 <main+0x37c>)
+  GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
+ 8001b2c:	607e      	str	r6, [r7, #4]
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001b2e:	60bd      	str	r5, [r7, #8]
+  GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8001b30:	60fd      	str	r5, [r7, #12]
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8001b32:	f001 fb2f 	bl	8003194 <HAL_GPIO_Init>
+  GPIO_InitStruct.Pin = SW2_Pin|SW1_Pin;
+ 8001b36:	23c0      	movs	r3, #192	@ 0xc0
+ 8001b38:	009b      	lsls	r3, r3, #2
+ 8001b3a:	9315      	str	r3, [sp, #84]	@ 0x54
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ 8001b3c:	4ba6      	ldr	r3, [pc, #664]	@ (8001dd8 <main+0x380>)
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8001b3e:	0039      	movs	r1, r7
+  GPIO_InitStruct.Mode = GPIO_MODE_IT_FALLING;
+ 8001b40:	607b      	str	r3, [r7, #4]
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8001b42:	48a4      	ldr	r0, [pc, #656]	@ (8001dd4 <main+0x37c>)
+  GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8001b44:	60bd      	str	r5, [r7, #8]
+  HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8001b46:	f001 fb25 	bl	8003194 <HAL_GPIO_Init>
+  HAL_NVIC_SetPriority(EXTI4_15_IRQn, 0, 0);
+ 8001b4a:	002a      	movs	r2, r5
+ 8001b4c:	0029      	movs	r1, r5
+ 8001b4e:	2007      	movs	r0, #7
+ 8001b50:	f001 f928 	bl	8002da4 <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(EXTI4_15_IRQn);
+ 8001b54:	2007      	movs	r0, #7
+ 8001b56:	f001 f94f 	bl	8002df8 <HAL_NVIC_EnableIRQ>
+  __HAL_RCC_DMA1_CLK_ENABLE();
+ 8001b5a:	6ba3      	ldr	r3, [r4, #56]	@ 0x38
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+ 8001b5c:	002a      	movs	r2, r5
+  __HAL_RCC_DMA1_CLK_ENABLE();
+ 8001b5e:	4333      	orrs	r3, r6
+ 8001b60:	63a3      	str	r3, [r4, #56]	@ 0x38
+ 8001b62:	6ba3      	ldr	r3, [r4, #56]	@ 0x38
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+ 8001b64:	0029      	movs	r1, r5
+  __HAL_RCC_DMA1_CLK_ENABLE();
+ 8001b66:	4033      	ands	r3, r6
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+ 8001b68:	2009      	movs	r0, #9
+  __HAL_RCC_DMA1_CLK_ENABLE();
+ 8001b6a:	9302      	str	r3, [sp, #8]
+ 8001b6c:	9b02      	ldr	r3, [sp, #8]
+  HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0);
+ 8001b6e:	f001 f919 	bl	8002da4 <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn);
+ 8001b72:	2009      	movs	r0, #9
+ 8001b74:	f001 f940 	bl	8002df8 <HAL_NVIC_EnableIRQ>
+  HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 0, 0);
+ 8001b78:	002a      	movs	r2, r5
+ 8001b7a:	0029      	movs	r1, r5
+ 8001b7c:	200a      	movs	r0, #10
+ 8001b7e:	f001 f911 	bl	8002da4 <HAL_NVIC_SetPriority>
+  HAL_NVIC_EnableIRQ(DMA1_Channel2_3_IRQn);
+ 8001b82:	200a      	movs	r0, #10
+ 8001b84:	f001 f938 	bl	8002df8 <HAL_NVIC_EnableIRQ>
+  TIM_ClockConfigTypeDef sClockSourceConfig = {0};
+ 8001b88:	2210      	movs	r2, #16
+ 8001b8a:	0029      	movs	r1, r5
+ 8001b8c:	a80a      	add	r0, sp, #40	@ 0x28
+ 8001b8e:	f003 fafd 	bl	800518c <memset>
+  TIM_OC_InitTypeDef sConfigOC = {0};
+ 8001b92:	ae0e      	add	r6, sp, #56	@ 0x38
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 8001b94:	220c      	movs	r2, #12
+ 8001b96:	0029      	movs	r1, r5
+ 8001b98:	a807      	add	r0, sp, #28
+ 8001b9a:	f003 faf7 	bl	800518c <memset>
+  TIM_OC_InitTypeDef sConfigOC = {0};
+ 8001b9e:	221c      	movs	r2, #28
+ 8001ba0:	0029      	movs	r1, r5
+ 8001ba2:	0030      	movs	r0, r6
+ 8001ba4:	f003 faf2 	bl	800518c <memset>
+  TIM_BreakDeadTimeConfigTypeDef sBreakDeadTimeConfig = {0};
+ 8001ba8:	0029      	movs	r1, r5
+ 8001baa:	2234      	movs	r2, #52	@ 0x34
+ 8001bac:	0038      	movs	r0, r7
+ 8001bae:	f003 faed 	bl	800518c <memset>
+  htim1.Init.Period = 2400;
+ 8001bb2:	2196      	movs	r1, #150	@ 0x96
+  htim1.Instance = TIM1;
+ 8001bb4:	4c89      	ldr	r4, [pc, #548]	@ (8001ddc <main+0x384>)
+ 8001bb6:	4b8a      	ldr	r3, [pc, #552]	@ (8001de0 <main+0x388>)
+  htim1.Init.Period = 2400;
+ 8001bb8:	0109      	lsls	r1, r1, #4
+  if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
+ 8001bba:	0020      	movs	r0, r4
+  htim1.Instance = TIM1;
+ 8001bbc:	6023      	str	r3, [r4, #0]
+  htim1.Init.Prescaler = 0;
+ 8001bbe:	6065      	str	r5, [r4, #4]
+  htim1.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8001bc0:	60a5      	str	r5, [r4, #8]
+  htim1.Init.Period = 2400;
+ 8001bc2:	60e1      	str	r1, [r4, #12]
+  htim1.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 8001bc4:	6125      	str	r5, [r4, #16]
+  htim1.Init.RepetitionCounter = 0;
+ 8001bc6:	6165      	str	r5, [r4, #20]
+  htim1.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 8001bc8:	61a5      	str	r5, [r4, #24]
+  if (HAL_TIM_Base_Init(&htim1) != HAL_OK)
+ 8001bca:	f002 f92b 	bl	8003e24 <HAL_TIM_Base_Init>
+ 8001bce:	42a8      	cmp	r0, r5
+ 8001bd0:	d001      	beq.n	8001bd6 <main+0x17e>
+  __ASM volatile ("cpsid i" : : : "memory");
+ 8001bd2:	b672      	cpsid	i
+  while (1)
+ 8001bd4:	e7fe      	b.n	8001bd4 <main+0x17c>
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ 8001bd6:	2380      	movs	r3, #128	@ 0x80
+  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
+ 8001bd8:	0020      	movs	r0, r4
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ 8001bda:	015b      	lsls	r3, r3, #5
+  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
+ 8001bdc:	a90a      	add	r1, sp, #40	@ 0x28
+  sClockSourceConfig.ClockSource = TIM_CLOCKSOURCE_INTERNAL;
+ 8001bde:	930a      	str	r3, [sp, #40]	@ 0x28
+  if (HAL_TIM_ConfigClockSource(&htim1, &sClockSourceConfig) != HAL_OK)
+ 8001be0:	f002 fa98 	bl	8004114 <HAL_TIM_ConfigClockSource>
+ 8001be4:	2800      	cmp	r0, #0
+ 8001be6:	d001      	beq.n	8001bec <main+0x194>
+ 8001be8:	b672      	cpsid	i
+  while (1)
+ 8001bea:	e7fe      	b.n	8001bea <main+0x192>
+  if (HAL_TIM_PWM_Init(&htim1) != HAL_OK)
+ 8001bec:	0020      	movs	r0, r4
+ 8001bee:	f002 f943 	bl	8003e78 <HAL_TIM_PWM_Init>
+ 8001bf2:	2800      	cmp	r0, #0
+ 8001bf4:	d001      	beq.n	8001bfa <main+0x1a2>
+ 8001bf6:	b672      	cpsid	i
+  while (1)
+ 8001bf8:	e7fe      	b.n	8001bf8 <main+0x1a0>
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 8001bfa:	9007      	str	r0, [sp, #28]
+  sMasterConfig.MasterOutputTrigger2 = TIM_TRGO2_RESET;
+ 8001bfc:	9008      	str	r0, [sp, #32]
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 8001bfe:	9009      	str	r0, [sp, #36]	@ 0x24
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim1, &sMasterConfig) != HAL_OK)
+ 8001c00:	a907      	add	r1, sp, #28
+ 8001c02:	0020      	movs	r0, r4
+ 8001c04:	f002 fbac 	bl	8004360 <HAL_TIMEx_MasterConfigSynchronization>
+ 8001c08:	1e02      	subs	r2, r0, #0
+ 8001c0a:	d001      	beq.n	8001c10 <main+0x1b8>
+ 8001c0c:	b672      	cpsid	i
+  while (1)
+ 8001c0e:	e7fe      	b.n	8001c0e <main+0x1b6>
+  sConfigOC.OCMode = TIM_OCMODE_PWM1;
+ 8001c10:	2360      	movs	r3, #96	@ 0x60
+  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+ 8001c12:	0031      	movs	r1, r6
+  sConfigOC.OCMode = TIM_OCMODE_PWM1;
+ 8001c14:	930e      	str	r3, [sp, #56]	@ 0x38
+  sConfigOC.Pulse = 0;
+ 8001c16:	6070      	str	r0, [r6, #4]
+  sConfigOC.OCPolarity = TIM_OCPOLARITY_HIGH;
+ 8001c18:	60b0      	str	r0, [r6, #8]
+  sConfigOC.OCNPolarity = TIM_OCNPOLARITY_HIGH;
+ 8001c1a:	60f0      	str	r0, [r6, #12]
+  sConfigOC.OCFastMode = TIM_OCFAST_DISABLE;
+ 8001c1c:	6130      	str	r0, [r6, #16]
+  sConfigOC.OCIdleState = TIM_OCIDLESTATE_RESET;
+ 8001c1e:	6170      	str	r0, [r6, #20]
+  sConfigOC.OCNIdleState = TIM_OCNIDLESTATE_RESET;
+ 8001c20:	61b0      	str	r0, [r6, #24]
+  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_1) != HAL_OK)
+ 8001c22:	0020      	movs	r0, r4
+ 8001c24:	f002 f9e4 	bl	8003ff0 <HAL_TIM_PWM_ConfigChannel>
+ 8001c28:	2800      	cmp	r0, #0
+ 8001c2a:	d001      	beq.n	8001c30 <main+0x1d8>
+ 8001c2c:	b672      	cpsid	i
+  while (1)
+ 8001c2e:	e7fe      	b.n	8001c2e <main+0x1d6>
+  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_2) != HAL_OK)
+ 8001c30:	2204      	movs	r2, #4
+ 8001c32:	0031      	movs	r1, r6
+ 8001c34:	0020      	movs	r0, r4
+ 8001c36:	f002 f9db 	bl	8003ff0 <HAL_TIM_PWM_ConfigChannel>
+ 8001c3a:	2800      	cmp	r0, #0
+ 8001c3c:	d001      	beq.n	8001c42 <main+0x1ea>
+ 8001c3e:	b672      	cpsid	i
+  while (1)
+ 8001c40:	e7fe      	b.n	8001c40 <main+0x1e8>
+  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_3) != HAL_OK)
+ 8001c42:	2208      	movs	r2, #8
+ 8001c44:	0031      	movs	r1, r6
+ 8001c46:	0020      	movs	r0, r4
+ 8001c48:	f002 f9d2 	bl	8003ff0 <HAL_TIM_PWM_ConfigChannel>
+ 8001c4c:	2800      	cmp	r0, #0
+ 8001c4e:	d001      	beq.n	8001c54 <main+0x1fc>
+ 8001c50:	b672      	cpsid	i
+  while (1)
+ 8001c52:	e7fe      	b.n	8001c52 <main+0x1fa>
+  if (HAL_TIM_PWM_ConfigChannel(&htim1, &sConfigOC, TIM_CHANNEL_4) != HAL_OK)
+ 8001c54:	220c      	movs	r2, #12
+ 8001c56:	0031      	movs	r1, r6
+ 8001c58:	0020      	movs	r0, r4
+ 8001c5a:	f002 f9c9 	bl	8003ff0 <HAL_TIM_PWM_ConfigChannel>
+ 8001c5e:	2800      	cmp	r0, #0
+ 8001c60:	d001      	beq.n	8001c66 <main+0x20e>
+ 8001c62:	b672      	cpsid	i
+  while (1)
+ 8001c64:	e7fe      	b.n	8001c64 <main+0x20c>
+  sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
+ 8001c66:	2380      	movs	r3, #128	@ 0x80
+ 8001c68:	019b      	lsls	r3, r3, #6
+  sBreakDeadTimeConfig.OffStateRunMode = TIM_OSSR_DISABLE;
+ 8001c6a:	9015      	str	r0, [sp, #84]	@ 0x54
+  sBreakDeadTimeConfig.BreakPolarity = TIM_BREAKPOLARITY_HIGH;
+ 8001c6c:	617b      	str	r3, [r7, #20]
+  sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
+ 8001c6e:	2380      	movs	r3, #128	@ 0x80
+ 8001c70:	049b      	lsls	r3, r3, #18
+  sBreakDeadTimeConfig.OffStateIDLEMode = TIM_OSSI_DISABLE;
+ 8001c72:	6078      	str	r0, [r7, #4]
+  sBreakDeadTimeConfig.LockLevel = TIM_LOCKLEVEL_OFF;
+ 8001c74:	60b8      	str	r0, [r7, #8]
+  sBreakDeadTimeConfig.DeadTime = 0;
+ 8001c76:	60f8      	str	r0, [r7, #12]
+  sBreakDeadTimeConfig.BreakState = TIM_BREAK_DISABLE;
+ 8001c78:	6138      	str	r0, [r7, #16]
+  sBreakDeadTimeConfig.BreakFilter = 0;
+ 8001c7a:	61b8      	str	r0, [r7, #24]
+  sBreakDeadTimeConfig.BreakAFMode = TIM_BREAK_AFMODE_INPUT;
+ 8001c7c:	61f8      	str	r0, [r7, #28]
+  sBreakDeadTimeConfig.Break2State = TIM_BREAK2_DISABLE;
+ 8001c7e:	6238      	str	r0, [r7, #32]
+  sBreakDeadTimeConfig.Break2Filter = 0;
+ 8001c80:	62b8      	str	r0, [r7, #40]	@ 0x28
+  sBreakDeadTimeConfig.Break2AFMode = TIM_BREAK_AFMODE_INPUT;
+ 8001c82:	62f8      	str	r0, [r7, #44]	@ 0x2c
+  sBreakDeadTimeConfig.AutomaticOutput = TIM_AUTOMATICOUTPUT_DISABLE;
+ 8001c84:	6338      	str	r0, [r7, #48]	@ 0x30
+  if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
+ 8001c86:	0039      	movs	r1, r7
+ 8001c88:	0020      	movs	r0, r4
+  sBreakDeadTimeConfig.Break2Polarity = TIM_BREAK2POLARITY_HIGH;
+ 8001c8a:	627b      	str	r3, [r7, #36]	@ 0x24
+  if (HAL_TIMEx_ConfigBreakDeadTime(&htim1, &sBreakDeadTimeConfig) != HAL_OK)
+ 8001c8c:	f002 fb9c 	bl	80043c8 <HAL_TIMEx_ConfigBreakDeadTime>
+ 8001c90:	1e05      	subs	r5, r0, #0
+ 8001c92:	d001      	beq.n	8001c98 <main+0x240>
+ 8001c94:	b672      	cpsid	i
+  while (1)
+ 8001c96:	e7fe      	b.n	8001c96 <main+0x23e>
+  HAL_TIM_MspPostInit(&htim1);
+ 8001c98:	0020      	movs	r0, r4
+ 8001c9a:	f000 fc93 	bl	80025c4 <HAL_TIM_MspPostInit>
+  TIM_Encoder_InitTypeDef sConfig = {0};
+ 8001c9e:	2220      	movs	r2, #32
+ 8001ca0:	0029      	movs	r1, r5
+ 8001ca2:	a816      	add	r0, sp, #88	@ 0x58
+ 8001ca4:	f003 fa72 	bl	800518c <memset>
+  TIM_MasterConfigTypeDef sMasterConfig = {0};
+ 8001ca8:	220c      	movs	r2, #12
+ 8001caa:	0029      	movs	r1, r5
+ 8001cac:	0030      	movs	r0, r6
+ 8001cae:	f003 fa6d 	bl	800518c <memset>
+  htim3.Instance = TIM3;
+ 8001cb2:	4b4c      	ldr	r3, [pc, #304]	@ (8001de4 <main+0x38c>)
+  htim3.Init.Period = 65535;
+ 8001cb4:	4c4c      	ldr	r4, [pc, #304]	@ (8001de8 <main+0x390>)
+  htim3.Instance = TIM3;
+ 8001cb6:	9300      	str	r3, [sp, #0]
+ 8001cb8:	9a00      	ldr	r2, [sp, #0]
+ 8001cba:	4b4c      	ldr	r3, [pc, #304]	@ (8001dec <main+0x394>)
+  if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
+ 8001cbc:	0039      	movs	r1, r7
+  htim3.Instance = TIM3;
+ 8001cbe:	6013      	str	r3, [r2, #0]
+  sConfig.EncoderMode = TIM_ENCODERMODE_TI12;
+ 8001cc0:	2303      	movs	r3, #3
+ 8001cc2:	9315      	str	r3, [sp, #84]	@ 0x54
+  sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
+ 8001cc4:	3b02      	subs	r3, #2
+  if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
+ 8001cc6:	0010      	movs	r0, r2
+  sConfig.IC1Selection = TIM_ICSELECTION_DIRECTTI;
+ 8001cc8:	60bb      	str	r3, [r7, #8]
+  sConfig.IC2Selection = TIM_ICSELECTION_DIRECTTI;
+ 8001cca:	61bb      	str	r3, [r7, #24]
+  htim3.Init.Prescaler = 0;
+ 8001ccc:	6055      	str	r5, [r2, #4]
+  htim3.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8001cce:	6095      	str	r5, [r2, #8]
+  htim3.Init.Period = 65535;
+ 8001cd0:	60d4      	str	r4, [r2, #12]
+  htim3.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 8001cd2:	6115      	str	r5, [r2, #16]
+  htim3.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 8001cd4:	6195      	str	r5, [r2, #24]
+  if (HAL_TIM_Encoder_Init(&htim3, &sConfig) != HAL_OK)
+ 8001cd6:	f002 f8f9 	bl	8003ecc <HAL_TIM_Encoder_Init>
+ 8001cda:	2800      	cmp	r0, #0
+ 8001cdc:	d001      	beq.n	8001ce2 <main+0x28a>
+ 8001cde:	b672      	cpsid	i
+  while (1)
+ 8001ce0:	e7fe      	b.n	8001ce0 <main+0x288>
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 8001ce2:	2300      	movs	r3, #0
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+ 8001ce4:	0031      	movs	r1, r6
+  sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET;
+ 8001ce6:	930e      	str	r3, [sp, #56]	@ 0x38
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+ 8001ce8:	9800      	ldr	r0, [sp, #0]
+  sMasterConfig.MasterSlaveMode = TIM_MASTERSLAVEMODE_DISABLE;
+ 8001cea:	60b3      	str	r3, [r6, #8]
+  if (HAL_TIMEx_MasterConfigSynchronization(&htim3, &sMasterConfig) != HAL_OK)
+ 8001cec:	f002 fb38 	bl	8004360 <HAL_TIMEx_MasterConfigSynchronization>
+ 8001cf0:	2800      	cmp	r0, #0
+ 8001cf2:	d001      	beq.n	8001cf8 <main+0x2a0>
+ 8001cf4:	b672      	cpsid	i
+  while (1)
+ 8001cf6:	e7fe      	b.n	8001cf6 <main+0x29e>
+  huart1.Instance = USART1;
+ 8001cf8:	4d3d      	ldr	r5, [pc, #244]	@ (8001df0 <main+0x398>)
+ 8001cfa:	4b3e      	ldr	r3, [pc, #248]	@ (8001df4 <main+0x39c>)
+  huart1.Init.Mode = UART_MODE_TX_RX;
+ 8001cfc:	260c      	movs	r6, #12
+  huart1.Instance = USART1;
+ 8001cfe:	602b      	str	r3, [r5, #0]
+  huart1.Init.BaudRate = 115200;
+ 8001d00:	23e1      	movs	r3, #225	@ 0xe1
+  huart1.Init.WordLength = UART_WORDLENGTH_8B;
+ 8001d02:	60a8      	str	r0, [r5, #8]
+  huart1.Init.BaudRate = 115200;
+ 8001d04:	025b      	lsls	r3, r3, #9
+  huart1.Init.StopBits = UART_STOPBITS_1;
+ 8001d06:	60e8      	str	r0, [r5, #12]
+  huart1.Init.Parity = UART_PARITY_NONE;
+ 8001d08:	6128      	str	r0, [r5, #16]
+  huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8001d0a:	61a8      	str	r0, [r5, #24]
+  huart1.Init.OverSampling = UART_OVERSAMPLING_16;
+ 8001d0c:	61e8      	str	r0, [r5, #28]
+  huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8001d0e:	6228      	str	r0, [r5, #32]
+  huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 8001d10:	6268      	str	r0, [r5, #36]	@ 0x24
+  huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ 8001d12:	62a8      	str	r0, [r5, #40]	@ 0x28
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+ 8001d14:	0028      	movs	r0, r5
+  huart1.Init.BaudRate = 115200;
+ 8001d16:	606b      	str	r3, [r5, #4]
+  huart1.Init.Mode = UART_MODE_TX_RX;
+ 8001d18:	616e      	str	r6, [r5, #20]
+  if (HAL_UART_Init(&huart1) != HAL_OK)
+ 8001d1a:	f003 f89b 	bl	8004e54 <HAL_UART_Init>
+ 8001d1e:	1e01      	subs	r1, r0, #0
+ 8001d20:	d001      	beq.n	8001d26 <main+0x2ce>
+ 8001d22:	b672      	cpsid	i
+  while (1)
+ 8001d24:	e7fe      	b.n	8001d24 <main+0x2cc>
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8001d26:	0028      	movs	r0, r5
+ 8001d28:	f003 f9ae 	bl	8005088 <HAL_UARTEx_SetTxFifoThreshold>
+ 8001d2c:	1e01      	subs	r1, r0, #0
+ 8001d2e:	d001      	beq.n	8001d34 <main+0x2dc>
+ 8001d30:	b672      	cpsid	i
+  while (1)
+ 8001d32:	e7fe      	b.n	8001d32 <main+0x2da>
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK)
+ 8001d34:	0028      	movs	r0, r5
+ 8001d36:	f003 f9c7 	bl	80050c8 <HAL_UARTEx_SetRxFifoThreshold>
+ 8001d3a:	2800      	cmp	r0, #0
+ 8001d3c:	d001      	beq.n	8001d42 <main+0x2ea>
+ 8001d3e:	b672      	cpsid	i
+  while (1)
+ 8001d40:	e7fe      	b.n	8001d40 <main+0x2e8>
+  if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK)
+ 8001d42:	0028      	movs	r0, r5
+ 8001d44:	f003 f982 	bl	800504c <HAL_UARTEx_DisableFifoMode>
+ 8001d48:	1e01      	subs	r1, r0, #0
+ 8001d4a:	d001      	beq.n	8001d50 <main+0x2f8>
+ 8001d4c:	b672      	cpsid	i
+  while (1)
+ 8001d4e:	e7fe      	b.n	8001d4e <main+0x2f6>
+  huart2.Instance = USART2;
+ 8001d50:	4d29      	ldr	r5, [pc, #164]	@ (8001df8 <main+0x3a0>)
+ 8001d52:	4b2a      	ldr	r3, [pc, #168]	@ (8001dfc <main+0x3a4>)
+  huart2.Init.WordLength = UART_WORDLENGTH_8B;
+ 8001d54:	60a8      	str	r0, [r5, #8]
+  huart2.Instance = USART2;
+ 8001d56:	602b      	str	r3, [r5, #0]
+  huart2.Init.BaudRate = 57600;
+ 8001d58:	23e1      	movs	r3, #225	@ 0xe1
+ 8001d5a:	021b      	lsls	r3, r3, #8
+ 8001d5c:	606b      	str	r3, [r5, #4]
+  if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 31, 31) != HAL_OK)
+ 8001d5e:	231f      	movs	r3, #31
+  huart2.Init.StopBits = UART_STOPBITS_1;
+ 8001d60:	60e8      	str	r0, [r5, #12]
+  huart2.Init.Parity = UART_PARITY_NONE;
+ 8001d62:	6128      	str	r0, [r5, #16]
+  huart2.Init.HwFlowCtl = UART_HWCONTROL_NONE;
+ 8001d64:	61a8      	str	r0, [r5, #24]
+  huart2.Init.OverSampling = UART_OVERSAMPLING_16;
+ 8001d66:	61e8      	str	r0, [r5, #28]
+  huart2.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE;
+ 8001d68:	6228      	str	r0, [r5, #32]
+  huart2.Init.ClockPrescaler = UART_PRESCALER_DIV1;
+ 8001d6a:	6268      	str	r0, [r5, #36]	@ 0x24
+  huart2.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT;
+ 8001d6c:	62a8      	str	r0, [r5, #40]	@ 0x28
+  if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 31, 31) != HAL_OK)
+ 8001d6e:	001a      	movs	r2, r3
+ 8001d70:	0028      	movs	r0, r5
+  huart2.Init.Mode = UART_MODE_TX_RX;
+ 8001d72:	616e      	str	r6, [r5, #20]
+  if (HAL_RS485Ex_Init(&huart2, UART_DE_POLARITY_HIGH, 31, 31) != HAL_OK)
+ 8001d74:	f003 f920 	bl	8004fb8 <HAL_RS485Ex_Init>
+ 8001d78:	2800      	cmp	r0, #0
+ 8001d7a:	d001      	beq.n	8001d80 <main+0x328>
+ 8001d7c:	b672      	cpsid	i
+  while (1)
+ 8001d7e:	e7fe      	b.n	8001d7e <main+0x326>
+  if (HAL_UARTEx_SetTxFifoThreshold(&huart2, UART_TXFIFO_THRESHOLD_1_2) != HAL_OK)
+ 8001d80:	2180      	movs	r1, #128	@ 0x80
+ 8001d82:	0028      	movs	r0, r5
+ 8001d84:	05c9      	lsls	r1, r1, #23
+ 8001d86:	f003 f97f 	bl	8005088 <HAL_UARTEx_SetTxFifoThreshold>
+ 8001d8a:	2800      	cmp	r0, #0
+ 8001d8c:	d001      	beq.n	8001d92 <main+0x33a>
+ 8001d8e:	b672      	cpsid	i
+  while (1)
+ 8001d90:	e7fe      	b.n	8001d90 <main+0x338>
+  if (HAL_UARTEx_SetRxFifoThreshold(&huart2, UART_RXFIFO_THRESHOLD_1_2) != HAL_OK)
+ 8001d92:	2180      	movs	r1, #128	@ 0x80
+ 8001d94:	0028      	movs	r0, r5
+ 8001d96:	04c9      	lsls	r1, r1, #19
+ 8001d98:	f003 f996 	bl	80050c8 <HAL_UARTEx_SetRxFifoThreshold>
+ 8001d9c:	2800      	cmp	r0, #0
+ 8001d9e:	d001      	beq.n	8001da4 <main+0x34c>
+ 8001da0:	b672      	cpsid	i
+  while (1)
+ 8001da2:	e7fe      	b.n	8001da2 <main+0x34a>
+  if (HAL_UARTEx_DisableFifoMode(&huart2) != HAL_OK)
+ 8001da4:	0028      	movs	r0, r5
+ 8001da6:	f003 f951 	bl	800504c <HAL_UARTEx_DisableFifoMode>
+ 8001daa:	1e03      	subs	r3, r0, #0
+ 8001dac:	d028      	beq.n	8001e00 <main+0x3a8>
+ 8001dae:	b672      	cpsid	i
+  while (1)
+ 8001db0:	e7fe      	b.n	8001db0 <main+0x358>
+ 8001db2:	46c0      	nop			@ (mov r8, r8)
+ 8001db4:	20000018 	.word	0x20000018
+ 8001db8:	2000001c 	.word	0x2000001c
+ 8001dbc:	20000014 	.word	0x20000014
+ 8001dc0:	20000010 	.word	0x20000010
+ 8001dc4:	2000000c 	.word	0x2000000c
+ 8001dc8:	20000008 	.word	0x20000008
+ 8001dcc:	20000128 	.word	0x20000128
+ 8001dd0:	40021000 	.word	0x40021000
+ 8001dd4:	50000400 	.word	0x50000400
+ 8001dd8:	10210000 	.word	0x10210000
+ 8001ddc:	200012b0 	.word	0x200012b0
+ 8001de0:	40012c00 	.word	0x40012c00
+ 8001de4:	20001264 	.word	0x20001264
+ 8001de8:	0000ffff 	.word	0x0000ffff
+ 8001dec:	40000400 	.word	0x40000400
+ 8001df0:	200010ec 	.word	0x200010ec
+ 8001df4:	40013800 	.word	0x40013800
+ 8001df8:	20001058 	.word	0x20001058
+ 8001dfc:	40004400 	.word	0x40004400
+  htim16.Instance = TIM16;
+ 8001e00:	48d3      	ldr	r0, [pc, #844]	@ (8002150 <main+0x6f8>)
+ 8001e02:	4ad4      	ldr	r2, [pc, #848]	@ (8002154 <main+0x6fc>)
+  htim16.Init.Prescaler = 48000-1;
+ 8001e04:	4ed4      	ldr	r6, [pc, #848]	@ (8002158 <main+0x700>)
+  htim16.Instance = TIM16;
+ 8001e06:	6002      	str	r2, [r0, #0]
+  htim16.Init.Prescaler = 48000-1;
+ 8001e08:	6046      	str	r6, [r0, #4]
+  htim16.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8001e0a:	6083      	str	r3, [r0, #8]
+  htim16.Init.Period = 65535;
+ 8001e0c:	60c4      	str	r4, [r0, #12]
+  htim16.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 8001e0e:	6103      	str	r3, [r0, #16]
+  htim16.Init.RepetitionCounter = 0;
+ 8001e10:	6143      	str	r3, [r0, #20]
+  htim16.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 8001e12:	6183      	str	r3, [r0, #24]
+  if (HAL_TIM_Base_Init(&htim16) != HAL_OK)
+ 8001e14:	f002 f806 	bl	8003e24 <HAL_TIM_Base_Init>
+ 8001e18:	2800      	cmp	r0, #0
+ 8001e1a:	d001      	beq.n	8001e20 <main+0x3c8>
+ 8001e1c:	b672      	cpsid	i
+  while (1)
+ 8001e1e:	e7fe      	b.n	8001e1e <main+0x3c6>
+  htim17.Instance = TIM17;
+ 8001e20:	48ce      	ldr	r0, [pc, #824]	@ (800215c <main+0x704>)
+ 8001e22:	4bcf      	ldr	r3, [pc, #828]	@ (8002160 <main+0x708>)
+  htim17.Init.Prescaler = 48000-1;
+ 8001e24:	6046      	str	r6, [r0, #4]
+  htim17.Instance = TIM17;
+ 8001e26:	6003      	str	r3, [r0, #0]
+  htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8001e28:	2300      	movs	r3, #0
+  htim17.Init.Period = 65535;
+ 8001e2a:	60c4      	str	r4, [r0, #12]
+  htim17.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8001e2c:	6083      	str	r3, [r0, #8]
+  htim17.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 8001e2e:	6103      	str	r3, [r0, #16]
+  htim17.Init.RepetitionCounter = 0;
+ 8001e30:	6143      	str	r3, [r0, #20]
+  htim17.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 8001e32:	6183      	str	r3, [r0, #24]
+  if (HAL_TIM_Base_Init(&htim17) != HAL_OK)
+ 8001e34:	f001 fff6 	bl	8003e24 <HAL_TIM_Base_Init>
+ 8001e38:	2800      	cmp	r0, #0
+ 8001e3a:	d001      	beq.n	8001e40 <main+0x3e8>
+ 8001e3c:	b672      	cpsid	i
+  while (1)
+ 8001e3e:	e7fe      	b.n	8001e3e <main+0x3e6>
+  htim14.Instance = TIM14;
+ 8001e40:	4bc8      	ldr	r3, [pc, #800]	@ (8002164 <main+0x70c>)
+ 8001e42:	9301      	str	r3, [sp, #4]
+ 8001e44:	9a01      	ldr	r2, [sp, #4]
+ 8001e46:	4bc8      	ldr	r3, [pc, #800]	@ (8002168 <main+0x710>)
+  htim14.Init.CounterMode = TIM_COUNTERMODE_UP;
+ 8001e48:	6090      	str	r0, [r2, #8]
+  htim14.Instance = TIM14;
+ 8001e4a:	6013      	str	r3, [r2, #0]
+  htim14.Init.Prescaler = 480-1;
+ 8001e4c:	23e0      	movs	r3, #224	@ 0xe0
+ 8001e4e:	33ff      	adds	r3, #255	@ 0xff
+ 8001e50:	6053      	str	r3, [r2, #4]
+  htim14.Init.Period = 50;
+ 8001e52:	2332      	movs	r3, #50	@ 0x32
+  htim14.Init.ClockDivision = TIM_CLOCKDIVISION_DIV1;
+ 8001e54:	6110      	str	r0, [r2, #16]
+  htim14.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE;
+ 8001e56:	6190      	str	r0, [r2, #24]
+  if (HAL_TIM_Base_Init(&htim14) != HAL_OK)
+ 8001e58:	0010      	movs	r0, r2
+  htim14.Init.Period = 50;
+ 8001e5a:	60d3      	str	r3, [r2, #12]
+  if (HAL_TIM_Base_Init(&htim14) != HAL_OK)
+ 8001e5c:	f001 ffe2 	bl	8003e24 <HAL_TIM_Base_Init>
+ 8001e60:	1e06      	subs	r6, r0, #0
+ 8001e62:	d001      	beq.n	8001e68 <main+0x410>
+ 8001e64:	b672      	cpsid	i
+  while (1)
+ 8001e66:	e7fe      	b.n	8001e66 <main+0x40e>
+  ADC_ChannelConfTypeDef sConfig = {0};
+ 8001e68:	0001      	movs	r1, r0
+ 8001e6a:	220c      	movs	r2, #12
+ 8001e6c:	0038      	movs	r0, r7
+ 8001e6e:	f003 f98d 	bl	800518c <memset>
+  hadc1.Instance = ADC1;
+ 8001e72:	4cbe      	ldr	r4, [pc, #760]	@ (800216c <main+0x714>)
+ 8001e74:	4bbe      	ldr	r3, [pc, #760]	@ (8002170 <main+0x718>)
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+ 8001e76:	0020      	movs	r0, r4
+  hadc1.Instance = ADC1;
+ 8001e78:	6023      	str	r3, [r4, #0]
+  hadc1.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV2;
+ 8001e7a:	2380      	movs	r3, #128	@ 0x80
+ 8001e7c:	05db      	lsls	r3, r3, #23
+ 8001e7e:	6063      	str	r3, [r4, #4]
+  hadc1.Init.ScanConvMode = ADC_SCAN_SEQ_FIXED;
+ 8001e80:	2380      	movs	r3, #128	@ 0x80
+ 8001e82:	061b      	lsls	r3, r3, #24
+ 8001e84:	6123      	str	r3, [r4, #16]
+  hadc1.Init.EOCSelection = ADC_EOC_SINGLE_CONV;
+ 8001e86:	2304      	movs	r3, #4
+ 8001e88:	6163      	str	r3, [r4, #20]
+  hadc1.Init.NbrOfConversion = 1;
+ 8001e8a:	3b03      	subs	r3, #3
+ 8001e8c:	61e3      	str	r3, [r4, #28]
+  hadc1.Init.DiscontinuousConvMode = DISABLE;
+ 8001e8e:	18e3      	adds	r3, r4, r3
+ 8001e90:	77de      	strb	r6, [r3, #31]
+  hadc1.Init.DMAContinuousRequests = DISABLE;
+ 8001e92:	0023      	movs	r3, r4
+ 8001e94:	332c      	adds	r3, #44	@ 0x2c
+ 8001e96:	701e      	strb	r6, [r3, #0]
+  hadc1.Init.OversamplingMode = DISABLE;
+ 8001e98:	0023      	movs	r3, r4
+ 8001e9a:	333c      	adds	r3, #60	@ 0x3c
+  hadc1.Init.Resolution = ADC_RESOLUTION_12B;
+ 8001e9c:	60a6      	str	r6, [r4, #8]
+  hadc1.Init.DataAlign = ADC_DATAALIGN_RIGHT;
+ 8001e9e:	60e6      	str	r6, [r4, #12]
+  hadc1.Init.LowPowerAutoWait = DISABLE;
+ 8001ea0:	8326      	strh	r6, [r4, #24]
+  hadc1.Init.ContinuousConvMode = DISABLE;
+ 8001ea2:	76a6      	strb	r6, [r4, #26]
+  hadc1.Init.ExternalTrigConv = ADC_SOFTWARE_START;
+ 8001ea4:	6266      	str	r6, [r4, #36]	@ 0x24
+  hadc1.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE;
+ 8001ea6:	62a6      	str	r6, [r4, #40]	@ 0x28
+  hadc1.Init.Overrun = ADC_OVR_DATA_PRESERVED;
+ 8001ea8:	6326      	str	r6, [r4, #48]	@ 0x30
+  hadc1.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_1CYCLE_5;
+ 8001eaa:	6366      	str	r6, [r4, #52]	@ 0x34
+  hadc1.Init.OversamplingMode = DISABLE;
+ 8001eac:	701e      	strb	r6, [r3, #0]
+  hadc1.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH;
+ 8001eae:	64e6      	str	r6, [r4, #76]	@ 0x4c
+  if (HAL_ADC_Init(&hadc1) != HAL_OK)
+ 8001eb0:	f000 fd44 	bl	800293c <HAL_ADC_Init>
+ 8001eb4:	2800      	cmp	r0, #0
+ 8001eb6:	d001      	beq.n	8001ebc <main+0x464>
+ 8001eb8:	b672      	cpsid	i
+  while (1)
+ 8001eba:	e7fe      	b.n	8001eba <main+0x462>
+  sConfig.Channel = ADC_CHANNEL_7;
+ 8001ebc:	4bad      	ldr	r3, [pc, #692]	@ (8002174 <main+0x71c>)
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 8001ebe:	0039      	movs	r1, r7
+  sConfig.Channel = ADC_CHANNEL_7;
+ 8001ec0:	9315      	str	r3, [sp, #84]	@ 0x54
+  sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
+ 8001ec2:	2301      	movs	r3, #1
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 8001ec4:	0020      	movs	r0, r4
+  sConfig.Rank = ADC_RANK_CHANNEL_NUMBER;
+ 8001ec6:	607b      	str	r3, [r7, #4]
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 8001ec8:	f000 fe48 	bl	8002b5c <HAL_ADC_ConfigChannel>
+ 8001ecc:	2800      	cmp	r0, #0
+ 8001ece:	d001      	beq.n	8001ed4 <main+0x47c>
+ 8001ed0:	b672      	cpsid	i
+  while (1)
+ 8001ed2:	e7fe      	b.n	8001ed2 <main+0x47a>
+  sConfig.Channel = ADC_CHANNEL_22;
+ 8001ed4:	4ba8      	ldr	r3, [pc, #672]	@ (8002178 <main+0x720>)
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 8001ed6:	0020      	movs	r0, r4
+ 8001ed8:	0039      	movs	r1, r7
+  sConfig.Channel = ADC_CHANNEL_22;
+ 8001eda:	9315      	str	r3, [sp, #84]	@ 0x54
+  if (HAL_ADC_ConfigChannel(&hadc1, &sConfig) != HAL_OK)
+ 8001edc:	f000 fe3e 	bl	8002b5c <HAL_ADC_ConfigChannel>
+ 8001ee0:	1e04      	subs	r4, r0, #0
+ 8001ee2:	d001      	beq.n	8001ee8 <main+0x490>
+ 8001ee4:	b672      	cpsid	i
+  while (1)
+ 8001ee6:	e7fe      	b.n	8001ee6 <main+0x48e>
+  *puuid 		= HAL_GetUIDw0();
+ 8001ee8:	f000 fd12 	bl	8002910 <HAL_GetUIDw0>
+ 8001eec:	4ea3      	ldr	r6, [pc, #652]	@ (800217c <main+0x724>)
+ 8001eee:	0a03      	lsrs	r3, r0, #8
+ 8001ef0:	7030      	strb	r0, [r6, #0]
+ 8001ef2:	7073      	strb	r3, [r6, #1]
+ 8001ef4:	0c03      	lsrs	r3, r0, #16
+ 8001ef6:	0e00      	lsrs	r0, r0, #24
+ 8001ef8:	70b3      	strb	r3, [r6, #2]
+ 8001efa:	70f0      	strb	r0, [r6, #3]
+  *(puuid+1)	= HAL_GetUIDw1();
+ 8001efc:	f000 fd0e 	bl	800291c <HAL_GetUIDw1>
+ 8001f00:	0a03      	lsrs	r3, r0, #8
+ 8001f02:	7130      	strb	r0, [r6, #4]
+ 8001f04:	7173      	strb	r3, [r6, #5]
+ 8001f06:	0c03      	lsrs	r3, r0, #16
+ 8001f08:	0e00      	lsrs	r0, r0, #24
+ 8001f0a:	71b3      	strb	r3, [r6, #6]
+ 8001f0c:	71f0      	strb	r0, [r6, #7]
+  *(puuid+2)	= HAL_GetUIDw2();
+ 8001f0e:	f000 fd0b 	bl	8002928 <HAL_GetUIDw2>
+ 8001f12:	0a03      	lsrs	r3, r0, #8
+ 8001f14:	7230      	strb	r0, [r6, #8]
+ 8001f16:	7273      	strb	r3, [r6, #9]
+ 8001f18:	0c03      	lsrs	r3, r0, #16
+ 8001f1a:	0e00      	lsrs	r0, r0, #24
+ 8001f1c:	72f0      	strb	r0, [r6, #11]
+  HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL);
+ 8001f1e:	213c      	movs	r1, #60	@ 0x3c
+ 8001f20:	9800      	ldr	r0, [sp, #0]
+  *(puuid+2)	= HAL_GetUIDw2();
+ 8001f22:	72b3      	strb	r3, [r6, #10]
+  HAL_TIM_Encoder_Start(&htim3, TIM_CHANNEL_ALL);
+ 8001f24:	f001 fe31 	bl	8003b8a <HAL_TIM_Encoder_Start>
+  HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_1);  // Feed motor
+ 8001f28:	4e95      	ldr	r6, [pc, #596]	@ (8002180 <main+0x728>)
+ 8001f2a:	0021      	movs	r1, r4
+ 8001f2c:	0030      	movs	r0, r6
+ 8001f2e:	f002 fa13 	bl	8004358 <HAL_TIM_PWM_Start>
+  HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_2);  // Feed motor
+ 8001f32:	2104      	movs	r1, #4
+ 8001f34:	0030      	movs	r0, r6
+ 8001f36:	f002 fa0f 	bl	8004358 <HAL_TIM_PWM_Start>
+  HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_3);  // Peel motor
+ 8001f3a:	2108      	movs	r1, #8
+ 8001f3c:	0030      	movs	r0, r6
+ 8001f3e:	f002 fa0b 	bl	8004358 <HAL_TIM_PWM_Start>
+  HAL_TIM_PWM_Start(&htim1, TIM_CHANNEL_4);  // Peel motor
+ 8001f42:	210c      	movs	r1, #12
+ 8001f44:	0030      	movs	r0, r6
+ 8001f46:	f002 fa07 	bl	8004358 <HAL_TIM_PWM_Start>
+  HAL_TIM_Base_Start_IT(&htim14);
+ 8001f4a:	9801      	ldr	r0, [sp, #4]
+ 8001f4c:	f001 fdec 	bl	8003b28 <HAL_TIM_Base_Start_IT>
+  floor_address = read_floor_address();
+ 8001f50:	f7ff f938 	bl	80011c4 <read_floor_address>
+ 8001f54:	4b8b      	ldr	r3, [pc, #556]	@ (8002184 <main+0x72c>)
+ 8001f56:	7018      	strb	r0, [r3, #0]
+  if (floor_address == FLOOR_ADDRESS_NOT_DETECTED)
+ 8001f58:	4b8b      	ldr	r3, [pc, #556]	@ (8002188 <main+0x730>)
+ 8001f5a:	28ff      	cmp	r0, #255	@ 0xff
+ 8001f5c:	d16c      	bne.n	8002038 <main+0x5e0>
+	  set_LED(1, 0, 0); // Red = EEPROM not detected
+ 8001f5e:	0022      	movs	r2, r4
+ 8001f60:	0021      	movs	r1, r4
+	  floor_address_status = 0;
+ 8001f62:	701c      	strb	r4, [r3, #0]
+	  set_LED(1, 0, 0); // Red = EEPROM not detected
+ 8001f64:	38fe      	subs	r0, #254	@ 0xfe
+	  set_LED(0, 0, 1); // Blue = not programmed
+ 8001f66:	f7fe fd99 	bl	8000a9c <set_LED>
+  for (uint8_t i = 0; i < MSG_BUF_COUNT; i++) msg_buf_empty[i] = 1;
+ 8001f6a:	2401      	movs	r4, #1
+{
+ 8001f6c:	2300      	movs	r3, #0
+  for (uint8_t i = 0; i < MSG_BUF_COUNT; i++) msg_buf_empty[i] = 1;
+ 8001f6e:	4a87      	ldr	r2, [pc, #540]	@ (800218c <main+0x734>)
+ 8001f70:	9200      	str	r2, [sp, #0]
+ 8001f72:	9a00      	ldr	r2, [sp, #0]
+ 8001f74:	54d4      	strb	r4, [r2, r3]
+ 8001f76:	3301      	adds	r3, #1
+ 8001f78:	2b36      	cmp	r3, #54	@ 0x36
+ 8001f7a:	d1fa      	bne.n	8001f72 <main+0x51a>
+  HAL_UARTEx_ReceiveToIdle_DMA (&huart2,DMA_buffer,64);
+ 8001f7c:	2240      	movs	r2, #64	@ 0x40
+ 8001f7e:	4984      	ldr	r1, [pc, #528]	@ (8002190 <main+0x738>)
+ 8001f80:	0028      	movs	r0, r5
+ 8001f82:	f003 f8c3 	bl	800510c <HAL_UARTEx_ReceiveToIdle_DMA>
+  __HAL_DMA_DISABLE_IT(huart2.hdmarx, DMA_IT_HT); // Disable half-transfer interrupt
+ 8001f86:	2104      	movs	r1, #4
+ 8001f88:	1d2b      	adds	r3, r5, #4
+ 8001f8a:	6fdb      	ldr	r3, [r3, #124]	@ 0x7c
+ 8001f8c:	681a      	ldr	r2, [r3, #0]
+ 8001f8e:	6813      	ldr	r3, [r2, #0]
+ 8001f90:	438b      	bics	r3, r1
+ 8001f92:	6013      	str	r3, [r2, #0]
+  __HAL_UART_ENABLE_IT(&huart2, UART_IT_ERR); // Enable error interrupt for overrun recovery
+ 8001f94:	682b      	ldr	r3, [r5, #0]
+ 8001f96:	689a      	ldr	r2, [r3, #8]
+ 8001f98:	4314      	orrs	r4, r2
+ 8001f9a:	609c      	str	r4, [r3, #8]
+	  uint8_t sw1_state = HAL_GPIO_ReadPin(SW1_GPIO_Port, SW1_Pin); // 1 = released, 0 = pressed
+ 8001f9c:	2180      	movs	r1, #128	@ 0x80
+ 8001f9e:	487d      	ldr	r0, [pc, #500]	@ (8002194 <main+0x73c>)
+ 8001fa0:	0089      	lsls	r1, r1, #2
+ 8001fa2:	f001 f9b1 	bl	8003308 <HAL_GPIO_ReadPin>
+	  uint8_t sw2_state = HAL_GPIO_ReadPin(SW2_GPIO_Port, SW2_Pin);
+ 8001fa6:	2180      	movs	r1, #128	@ 0x80
+	  uint8_t sw1_state = HAL_GPIO_ReadPin(SW1_GPIO_Port, SW1_Pin); // 1 = released, 0 = pressed
+ 8001fa8:	0006      	movs	r6, r0
+	  uint8_t sw2_state = HAL_GPIO_ReadPin(SW2_GPIO_Port, SW2_Pin);
+ 8001faa:	0049      	lsls	r1, r1, #1
+ 8001fac:	4879      	ldr	r0, [pc, #484]	@ (8002194 <main+0x73c>)
+ 8001fae:	f001 f9ab 	bl	8003308 <HAL_GPIO_ReadPin>
+	  if (driving)
+ 8001fb2:	4f79      	ldr	r7, [pc, #484]	@ (8002198 <main+0x740>)
+ 8001fb4:	783c      	ldrb	r4, [r7, #0]
+ 8001fb6:	2c00      	cmp	r4, #0
+ 8001fb8:	d06e      	beq.n	8002098 <main+0x640>
+		  if ((driving_direction && sw2_state) || (!driving_direction && sw1_state))
+ 8001fba:	4b78      	ldr	r3, [pc, #480]	@ (800219c <main+0x744>)
+ 8001fbc:	7819      	ldrb	r1, [r3, #0]
+ 8001fbe:	2900      	cmp	r1, #0
+ 8001fc0:	d050      	beq.n	8002064 <main+0x60c>
+ 8001fc2:	2800      	cmp	r0, #0
+ 8001fc4:	d150      	bne.n	8002068 <main+0x610>
+		  else if (!drive_mode)
+ 8001fc6:	4b76      	ldr	r3, [pc, #472]	@ (80021a0 <main+0x748>)
+ 8001fc8:	781b      	ldrb	r3, [r3, #0]
+ 8001fca:	2b00      	cmp	r3, #0
+ 8001fcc:	d107      	bne.n	8001fde <main+0x586>
+				  target_count = total_count + 10000;
+ 8001fce:	4b75      	ldr	r3, [pc, #468]	@ (80021a4 <main+0x74c>)
+ 8001fd0:	4a75      	ldr	r2, [pc, #468]	@ (80021a8 <main+0x750>)
+ 8001fd2:	681b      	ldr	r3, [r3, #0]
+			  if (driving_direction)
+ 8001fd4:	2900      	cmp	r1, #0
+ 8001fd6:	d05d      	beq.n	8002094 <main+0x63c>
+				  target_count = total_count + 10000;
+ 8001fd8:	4974      	ldr	r1, [pc, #464]	@ (80021ac <main+0x754>)
+				  target_count = total_count - 10000;
+ 8001fda:	185b      	adds	r3, r3, r1
+ 8001fdc:	6013      	str	r3, [r2, #0]
+	  feed_state_machine_update();
+ 8001fde:	f7fe fed1 	bl	8000d84 <feed_state_machine_update>
+	  peel_ramp_update();
+ 8001fe2:	f7fe fdb5 	bl	8000b50 <peel_ramp_update>
+	  debug_output();
+ 8001fe6:	f7ff fbf7 	bl	80017d8 <debug_output>
+	  if (feed_just_completed)
+ 8001fea:	4b71      	ldr	r3, [pc, #452]	@ (80021b0 <main+0x758>)
+ 8001fec:	781a      	ldrb	r2, [r3, #0]
+ 8001fee:	2a00      	cmp	r2, #0
+ 8001ff0:	d00c      	beq.n	800200c <main+0x5b4>
+		  feed_just_completed = 0;
+ 8001ff2:	2100      	movs	r1, #0
+ 8001ff4:	7019      	strb	r1, [r3, #0]
+		  if (last_feed_status == STATUS_OK)
+ 8001ff6:	4b6f      	ldr	r3, [pc, #444]	@ (80021b4 <main+0x75c>)
+ 8001ff8:	7818      	ldrb	r0, [r3, #0]
+ 8001ffa:	4288      	cmp	r0, r1
+ 8001ffc:	d000      	beq.n	8002000 <main+0x5a8>
+ 8001ffe:	e1cc      	b.n	800239a <main+0x942>
+			  set_LED(0, 0, 0); // Success - LED off
+ 8002000:	0002      	movs	r2, r0
+ 8002002:	0001      	movs	r1, r0
+ 8002004:	f7fe fd4a 	bl	8000a9c <set_LED>
+			  reset_position_if_needed();
+ 8002008:	f7ff fcea 	bl	80019e0 <reset_position_if_needed>
+		  uint16_t time2 = sw2_pressed ? htim17.Instance->CNT : 0;
+ 800200c:	2400      	movs	r4, #0
+			  msg_buf_empty[bi] = 1;
+ 800200e:	2601      	movs	r6, #1
+		  if (!msg_buf_empty[bi])
+ 8002010:	9b00      	ldr	r3, [sp, #0]
+ 8002012:	5d1b      	ldrb	r3, [r3, r4]
+ 8002014:	b2df      	uxtb	r7, r3
+ 8002016:	2b00      	cmp	r3, #0
+ 8002018:	d10a      	bne.n	8002030 <main+0x5d8>
+			  handleRS485Message(msg_buf[bi], msg_buf_size[bi]);
+ 800201a:	4d67      	ldr	r5, [pc, #412]	@ (80021b8 <main+0x760>)
+ 800201c:	4b67      	ldr	r3, [pc, #412]	@ (80021bc <main+0x764>)
+ 800201e:	5d29      	ldrb	r1, [r5, r4]
+ 8002020:	01a0      	lsls	r0, r4, #6
+ 8002022:	18c0      	adds	r0, r0, r3
+ 8002024:	b2c9      	uxtb	r1, r1
+ 8002026:	f7ff f94d 	bl	80012c4 <handleRS485Message>
+			  msg_buf_empty[bi] = 1;
+ 800202a:	9b00      	ldr	r3, [sp, #0]
+			  msg_buf_size[bi] = 0;
+ 800202c:	552f      	strb	r7, [r5, r4]
+			  msg_buf_empty[bi] = 1;
+ 800202e:	551e      	strb	r6, [r3, r4]
+	  for (uint8_t bi = 0; bi < MSG_BUF_COUNT; bi++)
+ 8002030:	3401      	adds	r4, #1
+ 8002032:	2c36      	cmp	r4, #54	@ 0x36
+ 8002034:	d1ec      	bne.n	8002010 <main+0x5b8>
+ 8002036:	e7b1      	b.n	8001f9c <main+0x544>
+  else if (floor_address == FLOOR_ADDRESS_NOT_PROGRAMMED)
+ 8002038:	2800      	cmp	r0, #0
+ 800203a:	d103      	bne.n	8002044 <main+0x5ec>
+	  floor_address_status = 1;
+ 800203c:	2201      	movs	r2, #1
+	  set_LED(0, 0, 1); // Blue = not programmed
+ 800203e:	0001      	movs	r1, r0
+	  floor_address_status = 1;
+ 8002040:	701a      	strb	r2, [r3, #0]
+	  set_LED(0, 0, 1); // Blue = not programmed
+ 8002042:	e790      	b.n	8001f66 <main+0x50e>
+	  floor_address_status = 2;
+ 8002044:	2202      	movs	r2, #2
+ 8002046:	701a      	strb	r2, [r3, #0]
+	  my_address = floor_address;
+ 8002048:	4b5d      	ldr	r3, [pc, #372]	@ (80021c0 <main+0x768>)
+	  set_LED(0, 1, 0); // Green briefly = valid address
+ 800204a:	0022      	movs	r2, r4
+ 800204c:	2101      	movs	r1, #1
+	  my_address = floor_address;
+ 800204e:	7018      	strb	r0, [r3, #0]
+	  set_LED(0, 1, 0); // Green briefly = valid address
+ 8002050:	0020      	movs	r0, r4
+ 8002052:	f7fe fd23 	bl	8000a9c <set_LED>
+	  HAL_Delay(200);
+ 8002056:	20c8      	movs	r0, #200	@ 0xc8
+ 8002058:	f000 fc48 	bl	80028ec <HAL_Delay>
+	  set_LED(0, 0, 0);
+ 800205c:	0022      	movs	r2, r4
+ 800205e:	0021      	movs	r1, r4
+ 8002060:	0020      	movs	r0, r4
+ 8002062:	e780      	b.n	8001f66 <main+0x50e>
+		  if ((driving_direction && sw2_state) || (!driving_direction && sw1_state))
+ 8002064:	2e00      	cmp	r6, #0
+ 8002066:	d0ae      	beq.n	8001fc6 <main+0x56e>
+			  driving = 0;
+ 8002068:	2400      	movs	r4, #0
+			  halt_all();
+ 800206a:	f7fe fdcb 	bl	8000c04 <halt_all>
+			  HAL_TIM_Base_Stop(&htim16);
+ 800206e:	4838      	ldr	r0, [pc, #224]	@ (8002150 <main+0x6f8>)
+			  driving = 0;
+ 8002070:	703c      	strb	r4, [r7, #0]
+			  HAL_TIM_Base_Stop(&htim16);
+ 8002072:	f001 fd43 	bl	8003afc <HAL_TIM_Base_Stop>
+			  HAL_TIM_Base_Stop(&htim17);
+ 8002076:	4839      	ldr	r0, [pc, #228]	@ (800215c <main+0x704>)
+ 8002078:	f001 fd40 	bl	8003afc <HAL_TIM_Base_Stop>
+			  sw1_pressed = 0;
+ 800207c:	4b51      	ldr	r3, [pc, #324]	@ (80021c4 <main+0x76c>)
+ 800207e:	701c      	strb	r4, [r3, #0]
+			  sw2_pressed = 0;
+ 8002080:	4b51      	ldr	r3, [pc, #324]	@ (80021c8 <main+0x770>)
+ 8002082:	701c      	strb	r4, [r3, #0]
+			  sw1_long_handled = 0;
+ 8002084:	4b51      	ldr	r3, [pc, #324]	@ (80021cc <main+0x774>)
+ 8002086:	701c      	strb	r4, [r3, #0]
+			  sw2_long_handled = 0;
+ 8002088:	4b51      	ldr	r3, [pc, #324]	@ (80021d0 <main+0x778>)
+ 800208a:	701c      	strb	r4, [r3, #0]
+			  set_LED(0, 0, 0);
+ 800208c:	0022      	movs	r2, r4
+				  set_LED(0, 0, 1); // Blue = tape mode
+ 800208e:	0021      	movs	r1, r4
+ 8002090:	0020      	movs	r0, r4
+ 8002092:	e038      	b.n	8002106 <main+0x6ae>
+				  target_count = total_count - 10000;
+ 8002094:	494f      	ldr	r1, [pc, #316]	@ (80021d4 <main+0x77c>)
+ 8002096:	e7a0      	b.n	8001fda <main+0x582>
+	  else if (both_pressed_handled)
+ 8002098:	4b4f      	ldr	r3, [pc, #316]	@ (80021d8 <main+0x780>)
+ 800209a:	469c      	mov	ip, r3
+ 800209c:	781b      	ldrb	r3, [r3, #0]
+ 800209e:	2b00      	cmp	r3, #0
+ 80020a0:	d049      	beq.n	8002136 <main+0x6de>
+		  if (sw1_state && sw2_state)
+ 80020a2:	2e00      	cmp	r6, #0
+ 80020a4:	d016      	beq.n	80020d4 <main+0x67c>
+ 80020a6:	2800      	cmp	r0, #0
+ 80020a8:	d014      	beq.n	80020d4 <main+0x67c>
+			  both_pressed_handled = 0;
+ 80020aa:	4663      	mov	r3, ip
+			  HAL_TIM_Base_Stop(&htim16);
+ 80020ac:	4828      	ldr	r0, [pc, #160]	@ (8002150 <main+0x6f8>)
+			  both_pressed_handled = 0;
+ 80020ae:	701c      	strb	r4, [r3, #0]
+			  HAL_TIM_Base_Stop(&htim16);
+ 80020b0:	f001 fd24 	bl	8003afc <HAL_TIM_Base_Stop>
+			  HAL_TIM_Base_Stop(&htim17);
+ 80020b4:	4829      	ldr	r0, [pc, #164]	@ (800215c <main+0x704>)
+ 80020b6:	f001 fd21 	bl	8003afc <HAL_TIM_Base_Stop>
+			  HAL_Delay(400);
+ 80020ba:	20c8      	movs	r0, #200	@ 0xc8
+			  sw1_pressed = 0;
+ 80020bc:	4b41      	ldr	r3, [pc, #260]	@ (80021c4 <main+0x76c>)
+			  HAL_Delay(400);
+ 80020be:	0040      	lsls	r0, r0, #1
+			  sw1_pressed = 0;
+ 80020c0:	701c      	strb	r4, [r3, #0]
+			  sw2_pressed = 0;
+ 80020c2:	4b41      	ldr	r3, [pc, #260]	@ (80021c8 <main+0x770>)
+ 80020c4:	701c      	strb	r4, [r3, #0]
+			  sw1_long_handled = 0;
+ 80020c6:	4b41      	ldr	r3, [pc, #260]	@ (80021cc <main+0x774>)
+ 80020c8:	701c      	strb	r4, [r3, #0]
+			  sw2_long_handled = 0;
+ 80020ca:	4b41      	ldr	r3, [pc, #260]	@ (80021d0 <main+0x778>)
+ 80020cc:	701c      	strb	r4, [r3, #0]
+			  HAL_Delay(400);
+ 80020ce:	f000 fc0d 	bl	80028ec <HAL_Delay>
+ 80020d2:	e7db      	b.n	800208c <main+0x634>
+			  uint32_t hold_time = HAL_GetTick() - both_pressed_start;
+ 80020d4:	f000 fc04 	bl	80028e0 <HAL_GetTick>
+ 80020d8:	4b40      	ldr	r3, [pc, #256]	@ (80021dc <main+0x784>)
+ 80020da:	681b      	ldr	r3, [r3, #0]
+ 80020dc:	1ac0      	subs	r0, r0, r3
+			  if (hold_time > 2000 && hold_time < 2100)
+ 80020de:	4b40      	ldr	r3, [pc, #256]	@ (80021e0 <main+0x788>)
+ 80020e0:	18c3      	adds	r3, r0, r3
+ 80020e2:	2b62      	cmp	r3, #98	@ 0x62
+ 80020e4:	d802      	bhi.n	80020ec <main+0x694>
+				  show_version();
+ 80020e6:	f7fe fdc5 	bl	8000c74 <show_version>
+ 80020ea:	e778      	b.n	8001fde <main+0x586>
+			  else if (hold_time > 4000 && hold_time < 6000)
+ 80020ec:	4b3d      	ldr	r3, [pc, #244]	@ (80021e4 <main+0x78c>)
+ 80020ee:	4a3e      	ldr	r2, [pc, #248]	@ (80021e8 <main+0x790>)
+ 80020f0:	18c3      	adds	r3, r0, r3
+ 80020f2:	4293      	cmp	r3, r2
+ 80020f4:	d80a      	bhi.n	800210c <main+0x6b4>
+				  set_LED((hold_time / 100) % 2, 0, !((hold_time / 100) % 2));
+ 80020f6:	2164      	movs	r1, #100	@ 0x64
+ 80020f8:	f7fe f81a 	bl	8000130 <__udivsi3>
+ 80020fc:	2301      	movs	r3, #1
+ 80020fe:	001a      	movs	r2, r3
+ 8002100:	2100      	movs	r1, #0
+ 8002102:	4382      	bics	r2, r0
+ 8002104:	4018      	ands	r0, r3
+				  if (!driving) set_LED(0, 0, 0);
+ 8002106:	f7fe fcc9 	bl	8000a9c <set_LED>
+ 800210a:	e768      	b.n	8001fde <main+0x586>
+			  else if (hold_time >= 6000)
+ 800210c:	4b37      	ldr	r3, [pc, #220]	@ (80021ec <main+0x794>)
+ 800210e:	4298      	cmp	r0, r3
+ 8002110:	d800      	bhi.n	8002114 <main+0x6bc>
+ 8002112:	e764      	b.n	8001fde <main+0x586>
+				  set_LED(1, 0, 1);
+ 8002114:	2201      	movs	r2, #1
+ 8002116:	2100      	movs	r1, #0
+ 8002118:	0010      	movs	r0, r2
+ 800211a:	f7fe fcbf 	bl	8000a9c <set_LED>
+				  HAL_Delay(100);
+ 800211e:	2064      	movs	r0, #100	@ 0x64
+ 8002120:	f000 fbe4 	bl	80028ec <HAL_Delay>
+  __ASM volatile ("dsb 0xF":::"memory");
+ 8002124:	f3bf 8f4f 	dsb	sy
+ */
+__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
+{
+  __DSB();                                                          /* Ensure all outstanding memory accesses included
+                                                                       buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
+ 8002128:	4b31      	ldr	r3, [pc, #196]	@ (80021f0 <main+0x798>)
+ 800212a:	4a32      	ldr	r2, [pc, #200]	@ (80021f4 <main+0x79c>)
+ 800212c:	60da      	str	r2, [r3, #12]
+ 800212e:	f3bf 8f4f 	dsb	sy
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                          /* Ensure completion of memory access */
+
+  for(;;)                                                           /* wait until reset */
+  {
+    __NOP();
+ 8002132:	46c0      	nop			@ (mov r8, r8)
+  for(;;)                                                           /* wait until reset */
+ 8002134:	e7fd      	b.n	8002132 <main+0x6da>
+	  else if (sw1_pressed || sw2_pressed)
+ 8002136:	4a23      	ldr	r2, [pc, #140]	@ (80021c4 <main+0x76c>)
+ 8002138:	7814      	ldrb	r4, [r2, #0]
+ 800213a:	9201      	str	r2, [sp, #4]
+ 800213c:	4a22      	ldr	r2, [pc, #136]	@ (80021c8 <main+0x770>)
+ 800213e:	7815      	ldrb	r5, [r2, #0]
+ 8002140:	2c00      	cmp	r4, #0
+ 8002142:	d159      	bne.n	80021f8 <main+0x7a0>
+ 8002144:	2d00      	cmp	r5, #0
+ 8002146:	d100      	bne.n	800214a <main+0x6f2>
+ 8002148:	e749      	b.n	8001fde <main+0x586>
+		  uint16_t time1 = sw1_pressed ? htim16.Instance->CNT : 0;
+ 800214a:	0022      	movs	r2, r4
+ 800214c:	e05a      	b.n	8002204 <main+0x7ac>
+ 800214e:	46c0      	nop			@ (mov r8, r8)
+ 8002150:	200011cc 	.word	0x200011cc
+ 8002154:	40014400 	.word	0x40014400
+ 8002158:	0000bb7f 	.word	0x0000bb7f
+ 800215c:	20001180 	.word	0x20001180
+ 8002160:	40014800 	.word	0x40014800
+ 8002164:	20001218 	.word	0x20001218
+ 8002168:	40002000 	.word	0x40002000
+ 800216c:	200012fc 	.word	0x200012fc
+ 8002170:	40012400 	.word	0x40012400
+ 8002174:	1c000080 	.word	0x1c000080
+ 8002178:	58400000 	.word	0x58400000
+ 800217c:	20000f87 	.word	0x20000f87
+ 8002180:	200012b0 	.word	0x200012b0
+ 8002184:	20000001 	.word	0x20000001
+ 8002188:	200000e8 	.word	0x200000e8
+ 800218c:	20000f50 	.word	0x20000f50
+ 8002190:	2000015a 	.word	0x2000015a
+ 8002194:	50000400 	.word	0x50000400
+ 8002198:	200000f4 	.word	0x200000f4
+ 800219c:	200000f3 	.word	0x200000f3
+ 80021a0:	200000f5 	.word	0x200000f5
+ 80021a4:	20000154 	.word	0x20000154
+ 80021a8:	20000150 	.word	0x20000150
+ 80021ac:	00002710 	.word	0x00002710
+ 80021b0:	20000120 	.word	0x20000120
+ 80021b4:	20000122 	.word	0x20000122
+ 80021b8:	20000f1a 	.word	0x20000f1a
+ 80021bc:	2000019a 	.word	0x2000019a
+ 80021c0:	20000020 	.word	0x20000020
+ 80021c4:	20000f9d 	.word	0x20000f9d
+ 80021c8:	20000f9c 	.word	0x20000f9c
+ 80021cc:	200000f2 	.word	0x200000f2
+ 80021d0:	200000f1 	.word	0x200000f1
+ 80021d4:	ffffd8f0 	.word	0xffffd8f0
+ 80021d8:	200000f0 	.word	0x200000f0
+ 80021dc:	200000ec 	.word	0x200000ec
+ 80021e0:	fffff82f 	.word	0xfffff82f
+ 80021e4:	fffff05f 	.word	0xfffff05f
+ 80021e8:	000007ce 	.word	0x000007ce
+ 80021ec:	0000176f 	.word	0x0000176f
+ 80021f0:	e000ed00 	.word	0xe000ed00
+ 80021f4:	05fa0004 	.word	0x05fa0004
+ 80021f8:	4a6a      	ldr	r2, [pc, #424]	@ (80023a4 <main+0x94c>)
+ 80021fa:	6812      	ldr	r2, [r2, #0]
+ 80021fc:	6a52      	ldr	r2, [r2, #36]	@ 0x24
+ 80021fe:	b292      	uxth	r2, r2
+		  uint16_t time2 = sw2_pressed ? htim17.Instance->CNT : 0;
+ 8002200:	2d00      	cmp	r5, #0
+ 8002202:	d003      	beq.n	800220c <main+0x7b4>
+ 8002204:	4b68      	ldr	r3, [pc, #416]	@ (80023a8 <main+0x950>)
+ 8002206:	681b      	ldr	r3, [r3, #0]
+ 8002208:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
+ 800220a:	b29b      	uxth	r3, r3
+		  uint16_t max_time = (time1 > time2) ? time1 : time2;
+ 800220c:	1c11      	adds	r1, r2, #0
+ 800220e:	429a      	cmp	r2, r3
+ 8002210:	d200      	bcs.n	8002214 <main+0x7bc>
+ 8002212:	1c19      	adds	r1, r3, #0
+		  if (max_time < 100)
+ 8002214:	b289      	uxth	r1, r1
+ 8002216:	2963      	cmp	r1, #99	@ 0x63
+ 8002218:	d800      	bhi.n	800221c <main+0x7c4>
+ 800221a:	e6e0      	b.n	8001fde <main+0x586>
+		  else if (sw1_pressed && sw2_pressed && !sw1_state && !sw2_state)
+ 800221c:	2c00      	cmp	r4, #0
+ 800221e:	d061      	beq.n	80022e4 <main+0x88c>
+ 8002220:	2d00      	cmp	r5, #0
+ 8002222:	d017      	beq.n	8002254 <main+0x7fc>
+ 8002224:	0034      	movs	r4, r6
+ 8002226:	4304      	orrs	r4, r0
+ 8002228:	b2e4      	uxtb	r4, r4
+ 800222a:	2c00      	cmp	r4, #0
+ 800222c:	d000      	beq.n	8002230 <main+0x7d8>
+ 800222e:	e09f      	b.n	8002370 <main+0x918>
+			  both_pressed_handled = 1;
+ 8002230:	4663      	mov	r3, ip
+ 8002232:	2501      	movs	r5, #1
+ 8002234:	701d      	strb	r5, [r3, #0]
+			  both_pressed_start = HAL_GetTick();
+ 8002236:	f000 fb53 	bl	80028e0 <HAL_GetTick>
+ 800223a:	4b5c      	ldr	r3, [pc, #368]	@ (80023ac <main+0x954>)
+ 800223c:	6018      	str	r0, [r3, #0]
+			  if (drive_mode)
+ 800223e:	4b5c      	ldr	r3, [pc, #368]	@ (80023b0 <main+0x958>)
+ 8002240:	781a      	ldrb	r2, [r3, #0]
+ 8002242:	2a00      	cmp	r2, #0
+ 8002244:	d002      	beq.n	800224c <main+0x7f4>
+				  set_LED(0, 0, 1); // Blue = tape mode
+ 8002246:	002a      	movs	r2, r5
+				  drive_mode = 0;
+ 8002248:	701c      	strb	r4, [r3, #0]
+				  set_LED(0, 0, 1); // Blue = tape mode
+ 800224a:	e720      	b.n	800208e <main+0x636>
+				  set_LED(1, 1, 0); // Yellow = peel mode
+ 800224c:	0029      	movs	r1, r5
+ 800224e:	0028      	movs	r0, r5
+				  drive_mode = 1;
+ 8002250:	701d      	strb	r5, [r3, #0]
+				  set_LED(1, 1, 0); // Yellow = peel mode
+ 8002252:	e758      	b.n	8002106 <main+0x6ae>
+			  if (!sw1_state && time1 > 2000 && !sw1_long_handled)
+ 8002254:	2e00      	cmp	r6, #0
+ 8002256:	d120      	bne.n	800229a <main+0x842>
+ 8002258:	23fa      	movs	r3, #250	@ 0xfa
+ 800225a:	00db      	lsls	r3, r3, #3
+ 800225c:	429a      	cmp	r2, r3
+ 800225e:	d800      	bhi.n	8002262 <main+0x80a>
+ 8002260:	e6bd      	b.n	8001fde <main+0x586>
+ 8002262:	4b54      	ldr	r3, [pc, #336]	@ (80023b4 <main+0x95c>)
+ 8002264:	781a      	ldrb	r2, [r3, #0]
+ 8002266:	2a00      	cmp	r2, #0
+ 8002268:	d000      	beq.n	800226c <main+0x814>
+ 800226a:	e6b8      	b.n	8001fde <main+0x586>
+				  sw1_long_handled = 1;
+ 800226c:	2001      	movs	r0, #1
+				  set_LED(1, 1, 1);
+ 800226e:	0002      	movs	r2, r0
+ 8002270:	0001      	movs	r1, r0
+				  sw1_long_handled = 1;
+ 8002272:	7018      	strb	r0, [r3, #0]
+				  set_LED(1, 1, 1);
+ 8002274:	f7fe fc12 	bl	8000a9c <set_LED>
+				  if (drive_mode)
+ 8002278:	4b4d      	ldr	r3, [pc, #308]	@ (80023b0 <main+0x958>)
+ 800227a:	781b      	ldrb	r3, [r3, #0]
+ 800227c:	2b00      	cmp	r3, #0
+ 800227e:	d008      	beq.n	8002292 <main+0x83a>
+	peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
+ 8002280:	4b4d      	ldr	r3, [pc, #308]	@ (80023b8 <main+0x960>)
+ 8002282:	4a4e      	ldr	r2, [pc, #312]	@ (80023bc <main+0x964>)
+ 8002284:	801a      	strh	r2, [r3, #0]
+				  driving = 1;
+ 8002286:	2301      	movs	r3, #1
+				  driving_direction = 0;
+ 8002288:	2200      	movs	r2, #0
+				  driving = 1;
+ 800228a:	703b      	strb	r3, [r7, #0]
+				  driving_direction = 0;
+ 800228c:	4b4c      	ldr	r3, [pc, #304]	@ (80023c0 <main+0x968>)
+ 800228e:	701a      	strb	r2, [r3, #0]
+ 8002290:	e6a5      	b.n	8001fde <main+0x586>
+					  drive_continuous(0);
+ 8002292:	0028      	movs	r0, r5
+ 8002294:	f7fe fca2 	bl	8000bdc <drive_continuous>
+ 8002298:	e7f5      	b.n	8002286 <main+0x82e>
+			  else if (sw1_state && time1 <= 2000 && time1 > 100)
+ 800229a:	3a65      	subs	r2, #101	@ 0x65
+ 800229c:	4b49      	ldr	r3, [pc, #292]	@ (80023c4 <main+0x96c>)
+ 800229e:	b292      	uxth	r2, r2
+ 80022a0:	4e40      	ldr	r6, [pc, #256]	@ (80023a4 <main+0x94c>)
+ 80022a2:	4c44      	ldr	r4, [pc, #272]	@ (80023b4 <main+0x95c>)
+ 80022a4:	429a      	cmp	r2, r3
+ 80022a6:	d80f      	bhi.n	80022c8 <main+0x870>
+				  set_LED(1, 1, 1);
+ 80022a8:	2201      	movs	r2, #1
+ 80022aa:	0011      	movs	r1, r2
+ 80022ac:	0010      	movs	r0, r2
+ 80022ae:	f7fe fbf5 	bl	8000a9c <set_LED>
+				  start_feed(20, 0);
+ 80022b2:	0029      	movs	r1, r5
+ 80022b4:	2014      	movs	r0, #20
+ 80022b6:	f7fe fcef 	bl	8000c98 <start_feed>
+				  HAL_TIM_Base_Stop(&htim16);
+ 80022ba:	0030      	movs	r0, r6
+ 80022bc:	f001 fc1e 	bl	8003afc <HAL_TIM_Base_Stop>
+				  sw1_pressed = 0;
+ 80022c0:	4b41      	ldr	r3, [pc, #260]	@ (80023c8 <main+0x970>)
+				  sw1_long_handled = 0;
+ 80022c2:	7025      	strb	r5, [r4, #0]
+				  sw1_pressed = 0;
+ 80022c4:	701d      	strb	r5, [r3, #0]
+				  sw1_long_handled = 0;
+ 80022c6:	e68a      	b.n	8001fde <main+0x586>
+				  HAL_TIM_Base_Stop(&htim16);
+ 80022c8:	0030      	movs	r0, r6
+ 80022ca:	f001 fc17 	bl	8003afc <HAL_TIM_Base_Stop>
+				  sw1_pressed = 0;
+ 80022ce:	9b01      	ldr	r3, [sp, #4]
+				  sw1_long_handled = 0;
+ 80022d0:	7025      	strb	r5, [r4, #0]
+				  sw1_pressed = 0;
+ 80022d2:	701d      	strb	r5, [r3, #0]
+				  if (!driving) set_LED(0, 0, 0);
+ 80022d4:	783b      	ldrb	r3, [r7, #0]
+ 80022d6:	2b00      	cmp	r3, #0
+ 80022d8:	d000      	beq.n	80022dc <main+0x884>
+ 80022da:	e680      	b.n	8001fde <main+0x586>
+ 80022dc:	2200      	movs	r2, #0
+ 80022de:	0011      	movs	r1, r2
+ 80022e0:	0010      	movs	r0, r2
+ 80022e2:	e710      	b.n	8002106 <main+0x6ae>
+		  else if (sw2_pressed && !sw1_pressed)
+ 80022e4:	2d00      	cmp	r5, #0
+ 80022e6:	d043      	beq.n	8002370 <main+0x918>
+			  if (!sw2_state && time2 > 2000 && !sw2_long_handled)
+ 80022e8:	2800      	cmp	r0, #0
+ 80022ea:	d123      	bne.n	8002334 <main+0x8dc>
+ 80022ec:	22fa      	movs	r2, #250	@ 0xfa
+ 80022ee:	00d2      	lsls	r2, r2, #3
+ 80022f0:	4293      	cmp	r3, r2
+ 80022f2:	d800      	bhi.n	80022f6 <main+0x89e>
+ 80022f4:	e673      	b.n	8001fde <main+0x586>
+ 80022f6:	4b35      	ldr	r3, [pc, #212]	@ (80023cc <main+0x974>)
+ 80022f8:	781a      	ldrb	r2, [r3, #0]
+ 80022fa:	2a00      	cmp	r2, #0
+ 80022fc:	d000      	beq.n	8002300 <main+0x8a8>
+ 80022fe:	e66e      	b.n	8001fde <main+0x586>
+				  sw2_long_handled = 1;
+ 8002300:	3001      	adds	r0, #1
+				  set_LED(1, 1, 1);
+ 8002302:	0002      	movs	r2, r0
+ 8002304:	0001      	movs	r1, r0
+				  sw2_long_handled = 1;
+ 8002306:	7018      	strb	r0, [r3, #0]
+				  set_LED(1, 1, 1);
+ 8002308:	f7fe fbc8 	bl	8000a9c <set_LED>
+				  if (drive_mode)
+ 800230c:	4b28      	ldr	r3, [pc, #160]	@ (80023b0 <main+0x958>)
+ 800230e:	781b      	ldrb	r3, [r3, #0]
+ 8002310:	2b00      	cmp	r3, #0
+ 8002312:	d008      	beq.n	8002326 <main+0x8ce>
+	peel_target_pwm = forward ? PWM_MAX : -PWM_MAX;
+ 8002314:	2296      	movs	r2, #150	@ 0x96
+ 8002316:	4b28      	ldr	r3, [pc, #160]	@ (80023b8 <main+0x960>)
+ 8002318:	0112      	lsls	r2, r2, #4
+ 800231a:	801a      	strh	r2, [r3, #0]
+				  driving = 1;
+ 800231c:	2301      	movs	r3, #1
+				  driving_direction = 1;
+ 800231e:	4a28      	ldr	r2, [pc, #160]	@ (80023c0 <main+0x968>)
+				  driving = 1;
+ 8002320:	703b      	strb	r3, [r7, #0]
+			  sw2_long_handled = 0;
+ 8002322:	7013      	strb	r3, [r2, #0]
+ 8002324:	e65b      	b.n	8001fde <main+0x586>
+		target_count = total_count + 10000;
+ 8002326:	4b2a      	ldr	r3, [pc, #168]	@ (80023d0 <main+0x978>)
+ 8002328:	492a      	ldr	r1, [pc, #168]	@ (80023d4 <main+0x97c>)
+ 800232a:	681b      	ldr	r3, [r3, #0]
+ 800232c:	4a2a      	ldr	r2, [pc, #168]	@ (80023d8 <main+0x980>)
+ 800232e:	185b      	adds	r3, r3, r1
+ 8002330:	6013      	str	r3, [r2, #0]
+}
+ 8002332:	e7f3      	b.n	800231c <main+0x8c4>
+ 8002334:	491c      	ldr	r1, [pc, #112]	@ (80023a8 <main+0x950>)
+			  else if (sw2_state && time2 <= 2000 && time2 > 100)
+ 8002336:	3b65      	subs	r3, #101	@ 0x65
+ 8002338:	4a22      	ldr	r2, [pc, #136]	@ (80023c4 <main+0x96c>)
+ 800233a:	b29b      	uxth	r3, r3
+ 800233c:	4e27      	ldr	r6, [pc, #156]	@ (80023dc <main+0x984>)
+ 800233e:	4d23      	ldr	r5, [pc, #140]	@ (80023cc <main+0x974>)
+ 8002340:	9101      	str	r1, [sp, #4]
+ 8002342:	4293      	cmp	r3, r2
+ 8002344:	d80e      	bhi.n	8002364 <main+0x90c>
+				  set_LED(1, 1, 1);
+ 8002346:	2201      	movs	r2, #1
+ 8002348:	0011      	movs	r1, r2
+ 800234a:	0010      	movs	r0, r2
+ 800234c:	f7fe fba6 	bl	8000a9c <set_LED>
+				  start_feed(20, 1);
+ 8002350:	2101      	movs	r1, #1
+ 8002352:	2014      	movs	r0, #20
+ 8002354:	f7fe fca0 	bl	8000c98 <start_feed>
+				  HAL_TIM_Base_Stop(&htim17);
+ 8002358:	9801      	ldr	r0, [sp, #4]
+ 800235a:	f001 fbcf 	bl	8003afc <HAL_TIM_Base_Stop>
+				  sw2_pressed = 0;
+ 800235e:	7034      	strb	r4, [r6, #0]
+				  sw2_long_handled = 0;
+ 8002360:	702c      	strb	r4, [r5, #0]
+ 8002362:	e63c      	b.n	8001fde <main+0x586>
+				  HAL_TIM_Base_Stop(&htim17);
+ 8002364:	9801      	ldr	r0, [sp, #4]
+ 8002366:	f001 fbc9 	bl	8003afc <HAL_TIM_Base_Stop>
+				  sw2_pressed = 0;
+ 800236a:	7034      	strb	r4, [r6, #0]
+				  sw2_long_handled = 0;
+ 800236c:	702c      	strb	r4, [r5, #0]
+				  if (!driving) set_LED(0, 0, 0);
+ 800236e:	e7b1      	b.n	80022d4 <main+0x87c>
+		  else if (sw1_state && sw2_state)
+ 8002370:	2e00      	cmp	r6, #0
+ 8002372:	d100      	bne.n	8002376 <main+0x91e>
+ 8002374:	e633      	b.n	8001fde <main+0x586>
+ 8002376:	2800      	cmp	r0, #0
+ 8002378:	d100      	bne.n	800237c <main+0x924>
+ 800237a:	e630      	b.n	8001fde <main+0x586>
+			  HAL_TIM_Base_Stop(&htim16);
+ 800237c:	4809      	ldr	r0, [pc, #36]	@ (80023a4 <main+0x94c>)
+ 800237e:	f001 fbbd 	bl	8003afc <HAL_TIM_Base_Stop>
+			  HAL_TIM_Base_Stop(&htim17);
+ 8002382:	4809      	ldr	r0, [pc, #36]	@ (80023a8 <main+0x950>)
+ 8002384:	f001 fbba 	bl	8003afc <HAL_TIM_Base_Stop>
+			  sw1_pressed = 0;
+ 8002388:	2300      	movs	r3, #0
+ 800238a:	9a01      	ldr	r2, [sp, #4]
+ 800238c:	7013      	strb	r3, [r2, #0]
+			  sw2_pressed = 0;
+ 800238e:	4a13      	ldr	r2, [pc, #76]	@ (80023dc <main+0x984>)
+ 8002390:	7013      	strb	r3, [r2, #0]
+			  sw1_long_handled = 0;
+ 8002392:	4a08      	ldr	r2, [pc, #32]	@ (80023b4 <main+0x95c>)
+ 8002394:	7013      	strb	r3, [r2, #0]
+			  sw2_long_handled = 0;
+ 8002396:	4a0d      	ldr	r2, [pc, #52]	@ (80023cc <main+0x974>)
+ 8002398:	e7c3      	b.n	8002322 <main+0x8ca>
+			  set_LED(1, 0, 0); // Error - LED red
+ 800239a:	000a      	movs	r2, r1
+ 800239c:	2001      	movs	r0, #1
+ 800239e:	f7fe fb7d 	bl	8000a9c <set_LED>
+ 80023a2:	e633      	b.n	800200c <main+0x5b4>
+ 80023a4:	200011cc 	.word	0x200011cc
+ 80023a8:	20001180 	.word	0x20001180
+ 80023ac:	200000ec 	.word	0x200000ec
+ 80023b0:	200000f5 	.word	0x200000f5
+ 80023b4:	200000f2 	.word	0x200000f2
+ 80023b8:	200000fe 	.word	0x200000fe
+ 80023bc:	fffff6a0 	.word	0xfffff6a0
+ 80023c0:	200000f3 	.word	0x200000f3
+ 80023c4:	0000076b 	.word	0x0000076b
+ 80023c8:	20000f9d 	.word	0x20000f9d
+ 80023cc:	200000f1 	.word	0x200000f1
+ 80023d0:	20000154 	.word	0x20000154
+ 80023d4:	00002710 	.word	0x00002710
+ 80023d8:	20000150 	.word	0x20000150
+ 80023dc:	20000f9c 	.word	0x20000f9c
+
+080023e0 <Error_Handler>:
+  __ASM volatile ("cpsid i" : : : "memory");
+ 80023e0:	b672      	cpsid	i
+  while (1)
+ 80023e2:	e7fe      	b.n	80023e2 <Error_Handler+0x2>
+
+080023e4 <HAL_MspInit>:
 
   /* USER CODE BEGIN MspInit 0 */
 
   /* USER CODE END MspInit 0 */
 
   __HAL_RCC_SYSCFG_CLK_ENABLE();
- 8003a5e:	4b0f      	ldr	r3, [pc, #60]	@ (8003a9c <HAL_MspInit+0x44>)
- 8003a60:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8003a62:	4b0e      	ldr	r3, [pc, #56]	@ (8003a9c <HAL_MspInit+0x44>)
- 8003a64:	2101      	movs	r1, #1
- 8003a66:	430a      	orrs	r2, r1
- 8003a68:	641a      	str	r2, [r3, #64]	@ 0x40
- 8003a6a:	4b0c      	ldr	r3, [pc, #48]	@ (8003a9c <HAL_MspInit+0x44>)
- 8003a6c:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 8003a6e:	2201      	movs	r2, #1
- 8003a70:	4013      	ands	r3, r2
- 8003a72:	607b      	str	r3, [r7, #4]
- 8003a74:	687b      	ldr	r3, [r7, #4]
+ 80023e4:	2101      	movs	r1, #1
+ 80023e6:	4b0a      	ldr	r3, [pc, #40]	@ (8002410 <HAL_MspInit+0x2c>)
+{
+ 80023e8:	b082      	sub	sp, #8
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 80023ea:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+ 80023ec:	430a      	orrs	r2, r1
+ 80023ee:	641a      	str	r2, [r3, #64]	@ 0x40
+ 80023f0:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+ 80023f2:	400a      	ands	r2, r1
   __HAL_RCC_PWR_CLK_ENABLE();
- 8003a76:	4b09      	ldr	r3, [pc, #36]	@ (8003a9c <HAL_MspInit+0x44>)
- 8003a78:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
- 8003a7a:	4b08      	ldr	r3, [pc, #32]	@ (8003a9c <HAL_MspInit+0x44>)
- 8003a7c:	2180      	movs	r1, #128	@ 0x80
- 8003a7e:	0549      	lsls	r1, r1, #21
- 8003a80:	430a      	orrs	r2, r1
- 8003a82:	63da      	str	r2, [r3, #60]	@ 0x3c
- 8003a84:	4b05      	ldr	r3, [pc, #20]	@ (8003a9c <HAL_MspInit+0x44>)
- 8003a86:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
- 8003a88:	2380      	movs	r3, #128	@ 0x80
- 8003a8a:	055b      	lsls	r3, r3, #21
- 8003a8c:	4013      	ands	r3, r2
- 8003a8e:	603b      	str	r3, [r7, #0]
- 8003a90:	683b      	ldr	r3, [r7, #0]
+ 80023f4:	2180      	movs	r1, #128	@ 0x80
+  __HAL_RCC_SYSCFG_CLK_ENABLE();
+ 80023f6:	9200      	str	r2, [sp, #0]
+ 80023f8:	9a00      	ldr	r2, [sp, #0]
+  __HAL_RCC_PWR_CLK_ENABLE();
+ 80023fa:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
+ 80023fc:	0549      	lsls	r1, r1, #21
+ 80023fe:	430a      	orrs	r2, r1
+ 8002400:	63da      	str	r2, [r3, #60]	@ 0x3c
+ 8002402:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
+ 8002404:	400b      	ands	r3, r1
+ 8002406:	9301      	str	r3, [sp, #4]
+ 8002408:	9b01      	ldr	r3, [sp, #4]
   /* System interrupt init*/
 
   /* USER CODE BEGIN MspInit 1 */
 
   /* USER CODE END MspInit 1 */
 }
- 8003a92:	46c0      	nop			@ (mov r8, r8)
- 8003a94:	46bd      	mov	sp, r7
- 8003a96:	b002      	add	sp, #8
- 8003a98:	bd80      	pop	{r7, pc}
- 8003a9a:	46c0      	nop			@ (mov r8, r8)
- 8003a9c:	40021000 	.word	0x40021000
+ 800240a:	b002      	add	sp, #8
+ 800240c:	4770      	bx	lr
+ 800240e:	46c0      	nop			@ (mov r8, r8)
+ 8002410:	40021000 	.word	0x40021000
 
-08003aa0 <HAL_TIM_Base_MspInit>:
+08002414 <HAL_ADC_MspInit>:
+  * This function configures the hardware resources used in this example
+  * @param hadc: ADC handle pointer
+  * @retval None
+  */
+void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
+{
+ 8002414:	b530      	push	{r4, r5, lr}
+ 8002416:	0004      	movs	r4, r0
+ 8002418:	b091      	sub	sp, #68	@ 0x44
+  GPIO_InitTypeDef GPIO_InitStruct = {0};
+ 800241a:	2214      	movs	r2, #20
+ 800241c:	2100      	movs	r1, #0
+ 800241e:	a804      	add	r0, sp, #16
+ 8002420:	f002 feb4 	bl	800518c <memset>
+  RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
+ 8002424:	221c      	movs	r2, #28
+ 8002426:	2100      	movs	r1, #0
+ 8002428:	a809      	add	r0, sp, #36	@ 0x24
+ 800242a:	f002 feaf 	bl	800518c <memset>
+  if(hadc->Instance==ADC1)
+ 800242e:	4b1e      	ldr	r3, [pc, #120]	@ (80024a8 <HAL_ADC_MspInit+0x94>)
+ 8002430:	6822      	ldr	r2, [r4, #0]
+ 8002432:	429a      	cmp	r2, r3
+ 8002434:	d136      	bne.n	80024a4 <HAL_ADC_MspInit+0x90>
+
+    /* USER CODE END ADC1_MspInit 0 */
+
+  /** Initializes the peripherals clocks
+  */
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+ 8002436:	2320      	movs	r3, #32
+    PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK;
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 8002438:	a809      	add	r0, sp, #36	@ 0x24
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+ 800243a:	9309      	str	r3, [sp, #36]	@ 0x24
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 800243c:	f001 f9c4 	bl	80037c8 <HAL_RCCEx_PeriphCLKConfig>
+ 8002440:	2800      	cmp	r0, #0
+ 8002442:	d001      	beq.n	8002448 <HAL_ADC_MspInit+0x34>
+    {
+      Error_Handler();
+ 8002444:	f7ff ffcc 	bl	80023e0 <Error_Handler>
+    }
+
+    /* Peripheral clock enable */
+    __HAL_RCC_ADC_CLK_ENABLE();
+ 8002448:	2180      	movs	r1, #128	@ 0x80
+ 800244a:	4b18      	ldr	r3, [pc, #96]	@ (80024ac <HAL_ADC_MspInit+0x98>)
+ 800244c:	0349      	lsls	r1, r1, #13
+ 800244e:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+    PB12     ------> ADC1_IN22
+    */
+    GPIO_InitStruct.Pin = IPROP_PEEL_Pin;
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
+ 8002450:	20a0      	movs	r0, #160	@ 0xa0
+    __HAL_RCC_ADC_CLK_ENABLE();
+ 8002452:	430a      	orrs	r2, r1
+ 8002454:	641a      	str	r2, [r3, #64]	@ 0x40
+ 8002456:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 8002458:	2503      	movs	r5, #3
+    __HAL_RCC_ADC_CLK_ENABLE();
+ 800245a:	400a      	ands	r2, r1
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 800245c:	2101      	movs	r1, #1
+    __HAL_RCC_ADC_CLK_ENABLE();
+ 800245e:	9201      	str	r2, [sp, #4]
+ 8002460:	9a01      	ldr	r2, [sp, #4]
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8002462:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8002464:	2400      	movs	r4, #0
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 8002466:	430a      	orrs	r2, r1
+ 8002468:	635a      	str	r2, [r3, #52]	@ 0x34
+ 800246a:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
+    HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
+ 800246c:	05c0      	lsls	r0, r0, #23
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 800246e:	400a      	ands	r2, r1
+ 8002470:	9202      	str	r2, [sp, #8]
+ 8002472:	9a02      	ldr	r2, [sp, #8]
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8002474:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
+ 8002476:	1849      	adds	r1, r1, r1
+ 8002478:	430a      	orrs	r2, r1
+ 800247a:	635a      	str	r2, [r3, #52]	@ 0x34
+ 800247c:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 800247e:	9505      	str	r5, [sp, #20]
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8002480:	400b      	ands	r3, r1
+ 8002482:	9303      	str	r3, [sp, #12]
+ 8002484:	9b03      	ldr	r3, [sp, #12]
+    GPIO_InitStruct.Pin = IPROP_PEEL_Pin;
+ 8002486:	2380      	movs	r3, #128	@ 0x80
+    HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
+ 8002488:	a904      	add	r1, sp, #16
+    GPIO_InitStruct.Pin = IPROP_PEEL_Pin;
+ 800248a:	9304      	str	r3, [sp, #16]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800248c:	9406      	str	r4, [sp, #24]
+    HAL_GPIO_Init(IPROP_PEEL_GPIO_Port, &GPIO_InitStruct);
+ 800248e:	f000 fe81 	bl	8003194 <HAL_GPIO_Init>
+
+    GPIO_InitStruct.Pin = IPROP_DRIVE_Pin;
+ 8002492:	2380      	movs	r3, #128	@ 0x80
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+    HAL_GPIO_Init(IPROP_DRIVE_GPIO_Port, &GPIO_InitStruct);
+ 8002494:	4806      	ldr	r0, [pc, #24]	@ (80024b0 <HAL_ADC_MspInit+0x9c>)
+    GPIO_InitStruct.Pin = IPROP_DRIVE_Pin;
+ 8002496:	015b      	lsls	r3, r3, #5
+    HAL_GPIO_Init(IPROP_DRIVE_GPIO_Port, &GPIO_InitStruct);
+ 8002498:	a904      	add	r1, sp, #16
+    GPIO_InitStruct.Pin = IPROP_DRIVE_Pin;
+ 800249a:	9304      	str	r3, [sp, #16]
+    GPIO_InitStruct.Mode = GPIO_MODE_ANALOG;
+ 800249c:	9505      	str	r5, [sp, #20]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800249e:	9406      	str	r4, [sp, #24]
+    HAL_GPIO_Init(IPROP_DRIVE_GPIO_Port, &GPIO_InitStruct);
+ 80024a0:	f000 fe78 	bl	8003194 <HAL_GPIO_Init>
+
+    /* USER CODE END ADC1_MspInit 1 */
+
+  }
+
+}
+ 80024a4:	b011      	add	sp, #68	@ 0x44
+ 80024a6:	bd30      	pop	{r4, r5, pc}
+ 80024a8:	40012400 	.word	0x40012400
+ 80024ac:	40021000 	.word	0x40021000
+ 80024b0:	50000400 	.word	0x50000400
+
+080024b4 <HAL_TIM_Base_MspInit>:
   * This function configures the hardware resources used in this example
   * @param htim_base: TIM_Base handle pointer
   * @retval None
   */
 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
 {
- 8003aa0:	b580      	push	{r7, lr}
- 8003aa2:	b086      	sub	sp, #24
- 8003aa4:	af00      	add	r7, sp, #0
- 8003aa6:	6078      	str	r0, [r7, #4]
+ 80024b4:	b51f      	push	{r0, r1, r2, r3, r4, lr}
   if(htim_base->Instance==TIM1)
- 8003aa8:	687b      	ldr	r3, [r7, #4]
- 8003aaa:	681b      	ldr	r3, [r3, #0]
- 8003aac:	4a34      	ldr	r2, [pc, #208]	@ (8003b80 <HAL_TIM_Base_MspInit+0xe0>)
- 8003aae:	4293      	cmp	r3, r2
- 8003ab0:	d10e      	bne.n	8003ad0 <HAL_TIM_Base_MspInit+0x30>
+ 80024b6:	6803      	ldr	r3, [r0, #0]
+ 80024b8:	4a26      	ldr	r2, [pc, #152]	@ (8002554 <HAL_TIM_Base_MspInit+0xa0>)
+ 80024ba:	4293      	cmp	r3, r2
+ 80024bc:	d10b      	bne.n	80024d6 <HAL_TIM_Base_MspInit+0x22>
   {
     /* USER CODE BEGIN TIM1_MspInit 0 */
 
     /* USER CODE END TIM1_MspInit 0 */
     /* Peripheral clock enable */
     __HAL_RCC_TIM1_CLK_ENABLE();
- 8003ab2:	4b34      	ldr	r3, [pc, #208]	@ (8003b84 <HAL_TIM_Base_MspInit+0xe4>)
- 8003ab4:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8003ab6:	4b33      	ldr	r3, [pc, #204]	@ (8003b84 <HAL_TIM_Base_MspInit+0xe4>)
- 8003ab8:	2180      	movs	r1, #128	@ 0x80
- 8003aba:	0109      	lsls	r1, r1, #4
- 8003abc:	430a      	orrs	r2, r1
- 8003abe:	641a      	str	r2, [r3, #64]	@ 0x40
- 8003ac0:	4b30      	ldr	r3, [pc, #192]	@ (8003b84 <HAL_TIM_Base_MspInit+0xe4>)
- 8003ac2:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8003ac4:	2380      	movs	r3, #128	@ 0x80
- 8003ac6:	011b      	lsls	r3, r3, #4
- 8003ac8:	4013      	ands	r3, r2
- 8003aca:	617b      	str	r3, [r7, #20]
- 8003acc:	697b      	ldr	r3, [r7, #20]
+ 80024be:	2180      	movs	r1, #128	@ 0x80
+ 80024c0:	4b25      	ldr	r3, [pc, #148]	@ (8002558 <HAL_TIM_Base_MspInit+0xa4>)
+ 80024c2:	0109      	lsls	r1, r1, #4
+ 80024c4:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+ 80024c6:	430a      	orrs	r2, r1
+ 80024c8:	641a      	str	r2, [r3, #64]	@ 0x40
+ 80024ca:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 80024cc:	400b      	ands	r3, r1
+ 80024ce:	9300      	str	r3, [sp, #0]
+ 80024d0:	9b00      	ldr	r3, [sp, #0]
     /* USER CODE BEGIN TIM17_MspInit 1 */
 
     /* USER CODE END TIM17_MspInit 1 */
   }
 
 }
- 8003ace:	e052      	b.n	8003b76 <HAL_TIM_Base_MspInit+0xd6>
+ 80024d2:	b005      	add	sp, #20
+ 80024d4:	bd00      	pop	{pc}
   else if(htim_base->Instance==TIM14)
- 8003ad0:	687b      	ldr	r3, [r7, #4]
- 8003ad2:	681b      	ldr	r3, [r3, #0]
- 8003ad4:	4a2c      	ldr	r2, [pc, #176]	@ (8003b88 <HAL_TIM_Base_MspInit+0xe8>)
- 8003ad6:	4293      	cmp	r3, r2
- 8003ad8:	d116      	bne.n	8003b08 <HAL_TIM_Base_MspInit+0x68>
+ 80024d6:	4a21      	ldr	r2, [pc, #132]	@ (800255c <HAL_TIM_Base_MspInit+0xa8>)
+ 80024d8:	4293      	cmp	r3, r2
+ 80024da:	d112      	bne.n	8002502 <HAL_TIM_Base_MspInit+0x4e>
     __HAL_RCC_TIM14_CLK_ENABLE();
- 8003ada:	4b2a      	ldr	r3, [pc, #168]	@ (8003b84 <HAL_TIM_Base_MspInit+0xe4>)
- 8003adc:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8003ade:	4b29      	ldr	r3, [pc, #164]	@ (8003b84 <HAL_TIM_Base_MspInit+0xe4>)
- 8003ae0:	2180      	movs	r1, #128	@ 0x80
- 8003ae2:	0209      	lsls	r1, r1, #8
- 8003ae4:	430a      	orrs	r2, r1
- 8003ae6:	641a      	str	r2, [r3, #64]	@ 0x40
- 8003ae8:	4b26      	ldr	r3, [pc, #152]	@ (8003b84 <HAL_TIM_Base_MspInit+0xe4>)
- 8003aea:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8003aec:	2380      	movs	r3, #128	@ 0x80
- 8003aee:	021b      	lsls	r3, r3, #8
- 8003af0:	4013      	ands	r3, r2
- 8003af2:	613b      	str	r3, [r7, #16]
- 8003af4:	693b      	ldr	r3, [r7, #16]
+ 80024dc:	2180      	movs	r1, #128	@ 0x80
+ 80024de:	4b1e      	ldr	r3, [pc, #120]	@ (8002558 <HAL_TIM_Base_MspInit+0xa4>)
+ 80024e0:	0209      	lsls	r1, r1, #8
+ 80024e2:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
     HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
- 8003af6:	2200      	movs	r2, #0
- 8003af8:	2100      	movs	r1, #0
- 8003afa:	2013      	movs	r0, #19
- 8003afc:	f000 fbe4 	bl	80042c8 <HAL_NVIC_SetPriority>
+ 80024e4:	2013      	movs	r0, #19
+    __HAL_RCC_TIM14_CLK_ENABLE();
+ 80024e6:	430a      	orrs	r2, r1
+ 80024e8:	641a      	str	r2, [r3, #64]	@ 0x40
+    HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
+ 80024ea:	2200      	movs	r2, #0
+    __HAL_RCC_TIM14_CLK_ENABLE();
+ 80024ec:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 80024ee:	400b      	ands	r3, r1
+ 80024f0:	9301      	str	r3, [sp, #4]
+    HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
+ 80024f2:	0011      	movs	r1, r2
+    __HAL_RCC_TIM14_CLK_ENABLE();
+ 80024f4:	9b01      	ldr	r3, [sp, #4]
+    HAL_NVIC_SetPriority(TIM14_IRQn, 0, 0);
+ 80024f6:	f000 fc55 	bl	8002da4 <HAL_NVIC_SetPriority>
     HAL_NVIC_EnableIRQ(TIM14_IRQn);
- 8003b00:	2013      	movs	r0, #19
- 8003b02:	f000 fbf6 	bl	80042f2 <HAL_NVIC_EnableIRQ>
-}
- 8003b06:	e036      	b.n	8003b76 <HAL_TIM_Base_MspInit+0xd6>
-  else if(htim_base->Instance==TIM16)
- 8003b08:	687b      	ldr	r3, [r7, #4]
- 8003b0a:	681b      	ldr	r3, [r3, #0]
- 8003b0c:	4a1f      	ldr	r2, [pc, #124]	@ (8003b8c <HAL_TIM_Base_MspInit+0xec>)
- 8003b0e:	4293      	cmp	r3, r2
- 8003b10:	d116      	bne.n	8003b40 <HAL_TIM_Base_MspInit+0xa0>
-    __HAL_RCC_TIM16_CLK_ENABLE();
- 8003b12:	4b1c      	ldr	r3, [pc, #112]	@ (8003b84 <HAL_TIM_Base_MspInit+0xe4>)
- 8003b14:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8003b16:	4b1b      	ldr	r3, [pc, #108]	@ (8003b84 <HAL_TIM_Base_MspInit+0xe4>)
- 8003b18:	2180      	movs	r1, #128	@ 0x80
- 8003b1a:	0289      	lsls	r1, r1, #10
- 8003b1c:	430a      	orrs	r2, r1
- 8003b1e:	641a      	str	r2, [r3, #64]	@ 0x40
- 8003b20:	4b18      	ldr	r3, [pc, #96]	@ (8003b84 <HAL_TIM_Base_MspInit+0xe4>)
- 8003b22:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8003b24:	2380      	movs	r3, #128	@ 0x80
- 8003b26:	029b      	lsls	r3, r3, #10
- 8003b28:	4013      	ands	r3, r2
- 8003b2a:	60fb      	str	r3, [r7, #12]
- 8003b2c:	68fb      	ldr	r3, [r7, #12]
-    HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
- 8003b2e:	2200      	movs	r2, #0
- 8003b30:	2100      	movs	r1, #0
- 8003b32:	2015      	movs	r0, #21
- 8003b34:	f000 fbc8 	bl	80042c8 <HAL_NVIC_SetPriority>
-    HAL_NVIC_EnableIRQ(TIM16_IRQn);
- 8003b38:	2015      	movs	r0, #21
- 8003b3a:	f000 fbda 	bl	80042f2 <HAL_NVIC_EnableIRQ>
-}
- 8003b3e:	e01a      	b.n	8003b76 <HAL_TIM_Base_MspInit+0xd6>
-  else if(htim_base->Instance==TIM17)
- 8003b40:	687b      	ldr	r3, [r7, #4]
- 8003b42:	681b      	ldr	r3, [r3, #0]
- 8003b44:	4a12      	ldr	r2, [pc, #72]	@ (8003b90 <HAL_TIM_Base_MspInit+0xf0>)
- 8003b46:	4293      	cmp	r3, r2
- 8003b48:	d115      	bne.n	8003b76 <HAL_TIM_Base_MspInit+0xd6>
-    __HAL_RCC_TIM17_CLK_ENABLE();
- 8003b4a:	4b0e      	ldr	r3, [pc, #56]	@ (8003b84 <HAL_TIM_Base_MspInit+0xe4>)
- 8003b4c:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8003b4e:	4b0d      	ldr	r3, [pc, #52]	@ (8003b84 <HAL_TIM_Base_MspInit+0xe4>)
- 8003b50:	2180      	movs	r1, #128	@ 0x80
- 8003b52:	02c9      	lsls	r1, r1, #11
- 8003b54:	430a      	orrs	r2, r1
- 8003b56:	641a      	str	r2, [r3, #64]	@ 0x40
- 8003b58:	4b0a      	ldr	r3, [pc, #40]	@ (8003b84 <HAL_TIM_Base_MspInit+0xe4>)
- 8003b5a:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8003b5c:	2380      	movs	r3, #128	@ 0x80
- 8003b5e:	02db      	lsls	r3, r3, #11
- 8003b60:	4013      	ands	r3, r2
- 8003b62:	60bb      	str	r3, [r7, #8]
- 8003b64:	68bb      	ldr	r3, [r7, #8]
-    HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
- 8003b66:	2200      	movs	r2, #0
- 8003b68:	2100      	movs	r1, #0
- 8003b6a:	2016      	movs	r0, #22
- 8003b6c:	f000 fbac 	bl	80042c8 <HAL_NVIC_SetPriority>
+ 80024fa:	2013      	movs	r0, #19
     HAL_NVIC_EnableIRQ(TIM17_IRQn);
- 8003b70:	2016      	movs	r0, #22
- 8003b72:	f000 fbbe 	bl	80042f2 <HAL_NVIC_EnableIRQ>
+ 80024fc:	f000 fc7c 	bl	8002df8 <HAL_NVIC_EnableIRQ>
 }
- 8003b76:	46c0      	nop			@ (mov r8, r8)
- 8003b78:	46bd      	mov	sp, r7
- 8003b7a:	b006      	add	sp, #24
- 8003b7c:	bd80      	pop	{r7, pc}
- 8003b7e:	46c0      	nop			@ (mov r8, r8)
- 8003b80:	40012c00 	.word	0x40012c00
- 8003b84:	40021000 	.word	0x40021000
- 8003b88:	40002000 	.word	0x40002000
- 8003b8c:	40014400 	.word	0x40014400
- 8003b90:	40014800 	.word	0x40014800
+ 8002500:	e7e7      	b.n	80024d2 <HAL_TIM_Base_MspInit+0x1e>
+  else if(htim_base->Instance==TIM16)
+ 8002502:	4a17      	ldr	r2, [pc, #92]	@ (8002560 <HAL_TIM_Base_MspInit+0xac>)
+ 8002504:	4293      	cmp	r3, r2
+ 8002506:	d110      	bne.n	800252a <HAL_TIM_Base_MspInit+0x76>
+    __HAL_RCC_TIM16_CLK_ENABLE();
+ 8002508:	2180      	movs	r1, #128	@ 0x80
+ 800250a:	4b13      	ldr	r3, [pc, #76]	@ (8002558 <HAL_TIM_Base_MspInit+0xa4>)
+ 800250c:	0289      	lsls	r1, r1, #10
+ 800250e:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+    HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
+ 8002510:	2015      	movs	r0, #21
+    __HAL_RCC_TIM16_CLK_ENABLE();
+ 8002512:	430a      	orrs	r2, r1
+ 8002514:	641a      	str	r2, [r3, #64]	@ 0x40
+    HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
+ 8002516:	2200      	movs	r2, #0
+    __HAL_RCC_TIM16_CLK_ENABLE();
+ 8002518:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 800251a:	400b      	ands	r3, r1
+ 800251c:	9302      	str	r3, [sp, #8]
+    HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
+ 800251e:	0011      	movs	r1, r2
+    __HAL_RCC_TIM16_CLK_ENABLE();
+ 8002520:	9b02      	ldr	r3, [sp, #8]
+    HAL_NVIC_SetPriority(TIM16_IRQn, 0, 0);
+ 8002522:	f000 fc3f 	bl	8002da4 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(TIM16_IRQn);
+ 8002526:	2015      	movs	r0, #21
+ 8002528:	e7e8      	b.n	80024fc <HAL_TIM_Base_MspInit+0x48>
+  else if(htim_base->Instance==TIM17)
+ 800252a:	4a0e      	ldr	r2, [pc, #56]	@ (8002564 <HAL_TIM_Base_MspInit+0xb0>)
+ 800252c:	4293      	cmp	r3, r2
+ 800252e:	d1d0      	bne.n	80024d2 <HAL_TIM_Base_MspInit+0x1e>
+    __HAL_RCC_TIM17_CLK_ENABLE();
+ 8002530:	2180      	movs	r1, #128	@ 0x80
+ 8002532:	4b09      	ldr	r3, [pc, #36]	@ (8002558 <HAL_TIM_Base_MspInit+0xa4>)
+ 8002534:	02c9      	lsls	r1, r1, #11
+ 8002536:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+    HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
+ 8002538:	2016      	movs	r0, #22
+    __HAL_RCC_TIM17_CLK_ENABLE();
+ 800253a:	430a      	orrs	r2, r1
+ 800253c:	641a      	str	r2, [r3, #64]	@ 0x40
+    HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
+ 800253e:	2200      	movs	r2, #0
+    __HAL_RCC_TIM17_CLK_ENABLE();
+ 8002540:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
+ 8002542:	400b      	ands	r3, r1
+ 8002544:	9303      	str	r3, [sp, #12]
+    HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
+ 8002546:	0011      	movs	r1, r2
+    __HAL_RCC_TIM17_CLK_ENABLE();
+ 8002548:	9b03      	ldr	r3, [sp, #12]
+    HAL_NVIC_SetPriority(TIM17_IRQn, 0, 0);
+ 800254a:	f000 fc2b 	bl	8002da4 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(TIM17_IRQn);
+ 800254e:	2016      	movs	r0, #22
+ 8002550:	e7d4      	b.n	80024fc <HAL_TIM_Base_MspInit+0x48>
+ 8002552:	46c0      	nop			@ (mov r8, r8)
+ 8002554:	40012c00 	.word	0x40012c00
+ 8002558:	40021000 	.word	0x40021000
+ 800255c:	40002000 	.word	0x40002000
+ 8002560:	40014400 	.word	0x40014400
+ 8002564:	40014800 	.word	0x40014800
 
-08003b94 <HAL_TIM_Encoder_MspInit>:
+08002568 <HAL_TIM_Encoder_MspInit>:
   * This function configures the hardware resources used in this example
   * @param htim_encoder: TIM_Encoder handle pointer
   * @retval None
   */
 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef* htim_encoder)
 {
- 8003b94:	b590      	push	{r4, r7, lr}
- 8003b96:	b08b      	sub	sp, #44	@ 0x2c
- 8003b98:	af00      	add	r7, sp, #0
- 8003b9a:	6078      	str	r0, [r7, #4]
+ 8002568:	b510      	push	{r4, lr}
+ 800256a:	0004      	movs	r4, r0
+ 800256c:	b088      	sub	sp, #32
   GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8003b9c:	2414      	movs	r4, #20
- 8003b9e:	193b      	adds	r3, r7, r4
- 8003ba0:	0018      	movs	r0, r3
- 8003ba2:	2314      	movs	r3, #20
- 8003ba4:	001a      	movs	r2, r3
- 8003ba6:	2100      	movs	r1, #0
- 8003ba8:	f004 f884 	bl	8007cb4 <memset>
+ 800256e:	2214      	movs	r2, #20
+ 8002570:	2100      	movs	r1, #0
+ 8002572:	a803      	add	r0, sp, #12
+ 8002574:	f002 fe0a 	bl	800518c <memset>
   if(htim_encoder->Instance==TIM3)
- 8003bac:	687b      	ldr	r3, [r7, #4]
- 8003bae:	681b      	ldr	r3, [r3, #0]
- 8003bb0:	4a1a      	ldr	r2, [pc, #104]	@ (8003c1c <HAL_TIM_Encoder_MspInit+0x88>)
- 8003bb2:	4293      	cmp	r3, r2
- 8003bb4:	d12d      	bne.n	8003c12 <HAL_TIM_Encoder_MspInit+0x7e>
+ 8002578:	4b0f      	ldr	r3, [pc, #60]	@ (80025b8 <HAL_TIM_Encoder_MspInit+0x50>)
+ 800257a:	6822      	ldr	r2, [r4, #0]
+ 800257c:	429a      	cmp	r2, r3
+ 800257e:	d119      	bne.n	80025b4 <HAL_TIM_Encoder_MspInit+0x4c>
   {
     /* USER CODE BEGIN TIM3_MspInit 0 */
 
     /* USER CODE END TIM3_MspInit 0 */
     /* Peripheral clock enable */
     __HAL_RCC_TIM3_CLK_ENABLE();
- 8003bb6:	4b1a      	ldr	r3, [pc, #104]	@ (8003c20 <HAL_TIM_Encoder_MspInit+0x8c>)
- 8003bb8:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
- 8003bba:	4b19      	ldr	r3, [pc, #100]	@ (8003c20 <HAL_TIM_Encoder_MspInit+0x8c>)
- 8003bbc:	2102      	movs	r1, #2
- 8003bbe:	430a      	orrs	r2, r1
- 8003bc0:	63da      	str	r2, [r3, #60]	@ 0x3c
- 8003bc2:	4b17      	ldr	r3, [pc, #92]	@ (8003c20 <HAL_TIM_Encoder_MspInit+0x8c>)
- 8003bc4:	6bdb      	ldr	r3, [r3, #60]	@ 0x3c
- 8003bc6:	2202      	movs	r2, #2
- 8003bc8:	4013      	ands	r3, r2
- 8003bca:	613b      	str	r3, [r7, #16]
- 8003bcc:	693b      	ldr	r3, [r7, #16]
+ 8002580:	2202      	movs	r2, #2
 
     __HAL_RCC_GPIOC_CLK_ENABLE();
- 8003bce:	4b14      	ldr	r3, [pc, #80]	@ (8003c20 <HAL_TIM_Encoder_MspInit+0x8c>)
- 8003bd0:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
- 8003bd2:	4b13      	ldr	r3, [pc, #76]	@ (8003c20 <HAL_TIM_Encoder_MspInit+0x8c>)
- 8003bd4:	2104      	movs	r1, #4
- 8003bd6:	430a      	orrs	r2, r1
- 8003bd8:	635a      	str	r2, [r3, #52]	@ 0x34
- 8003bda:	4b11      	ldr	r3, [pc, #68]	@ (8003c20 <HAL_TIM_Encoder_MspInit+0x8c>)
- 8003bdc:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8003bde:	2204      	movs	r2, #4
- 8003be0:	4013      	ands	r3, r2
- 8003be2:	60fb      	str	r3, [r7, #12]
- 8003be4:	68fb      	ldr	r3, [r7, #12]
-    /**TIM3 GPIO Configuration
-    PC6     ------> TIM3_CH1
-    PC7     ------> TIM3_CH2
-    */
+ 8002582:	2004      	movs	r0, #4
+    __HAL_RCC_TIM3_CLK_ENABLE();
+ 8002584:	4b0d      	ldr	r3, [pc, #52]	@ (80025bc <HAL_TIM_Encoder_MspInit+0x54>)
+ 8002586:	6bd9      	ldr	r1, [r3, #60]	@ 0x3c
+ 8002588:	4311      	orrs	r1, r2
+ 800258a:	63d9      	str	r1, [r3, #60]	@ 0x3c
+ 800258c:	6bd9      	ldr	r1, [r3, #60]	@ 0x3c
+ 800258e:	4011      	ands	r1, r2
+ 8002590:	9101      	str	r1, [sp, #4]
+ 8002592:	9901      	ldr	r1, [sp, #4]
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+ 8002594:	6b59      	ldr	r1, [r3, #52]	@ 0x34
+ 8002596:	4301      	orrs	r1, r0
+ 8002598:	6359      	str	r1, [r3, #52]	@ 0x34
+ 800259a:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
     GPIO_InitStruct.Pin = QUAD_A_Pin|QUAD_B_Pin;
- 8003be6:	0021      	movs	r1, r4
- 8003be8:	187b      	adds	r3, r7, r1
- 8003bea:	22c0      	movs	r2, #192	@ 0xc0
- 8003bec:	601a      	str	r2, [r3, #0]
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8003bee:	187b      	adds	r3, r7, r1
- 8003bf0:	2202      	movs	r2, #2
- 8003bf2:	605a      	str	r2, [r3, #4]
     GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8003bf4:	187b      	adds	r3, r7, r1
- 8003bf6:	2200      	movs	r2, #0
- 8003bf8:	609a      	str	r2, [r3, #8]
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8003bfa:	187b      	adds	r3, r7, r1
- 8003bfc:	2200      	movs	r2, #0
- 8003bfe:	60da      	str	r2, [r3, #12]
     GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
- 8003c00:	187b      	adds	r3, r7, r1
- 8003c02:	2201      	movs	r2, #1
- 8003c04:	611a      	str	r2, [r3, #16]
     HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
- 8003c06:	187b      	adds	r3, r7, r1
- 8003c08:	4a06      	ldr	r2, [pc, #24]	@ (8003c24 <HAL_TIM_Encoder_MspInit+0x90>)
- 8003c0a:	0019      	movs	r1, r3
- 8003c0c:	0010      	movs	r0, r2
- 8003c0e:	f000 fde1 	bl	80047d4 <HAL_GPIO_Init>
+ 800259c:	a903      	add	r1, sp, #12
+    __HAL_RCC_GPIOC_CLK_ENABLE();
+ 800259e:	4003      	ands	r3, r0
+ 80025a0:	9302      	str	r3, [sp, #8]
+ 80025a2:	9b02      	ldr	r3, [sp, #8]
+    GPIO_InitStruct.Pin = QUAD_A_Pin|QUAD_B_Pin;
+ 80025a4:	23c0      	movs	r3, #192	@ 0xc0
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 80025a6:	4806      	ldr	r0, [pc, #24]	@ (80025c0 <HAL_TIM_Encoder_MspInit+0x58>)
+    GPIO_InitStruct.Pin = QUAD_A_Pin|QUAD_B_Pin;
+ 80025a8:	9303      	str	r3, [sp, #12]
+    GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
+ 80025aa:	3bbf      	subs	r3, #191	@ 0xbf
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80025ac:	9204      	str	r2, [sp, #16]
+    GPIO_InitStruct.Alternate = GPIO_AF1_TIM3;
+ 80025ae:	9307      	str	r3, [sp, #28]
+    HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
+ 80025b0:	f000 fdf0 	bl	8003194 <HAL_GPIO_Init>
 
     /* USER CODE END TIM3_MspInit 1 */
 
   }
 
 }
- 8003c12:	46c0      	nop			@ (mov r8, r8)
- 8003c14:	46bd      	mov	sp, r7
- 8003c16:	b00b      	add	sp, #44	@ 0x2c
- 8003c18:	bd90      	pop	{r4, r7, pc}
- 8003c1a:	46c0      	nop			@ (mov r8, r8)
- 8003c1c:	40000400 	.word	0x40000400
- 8003c20:	40021000 	.word	0x40021000
- 8003c24:	50000800 	.word	0x50000800
+ 80025b4:	b008      	add	sp, #32
+ 80025b6:	bd10      	pop	{r4, pc}
+ 80025b8:	40000400 	.word	0x40000400
+ 80025bc:	40021000 	.word	0x40021000
+ 80025c0:	50000800 	.word	0x50000800
 
-08003c28 <HAL_TIM_MspPostInit>:
+080025c4 <HAL_TIM_MspPostInit>:
 
 void HAL_TIM_MspPostInit(TIM_HandleTypeDef* htim)
 {
- 8003c28:	b590      	push	{r4, r7, lr}
- 8003c2a:	b089      	sub	sp, #36	@ 0x24
- 8003c2c:	af00      	add	r7, sp, #0
- 8003c2e:	6078      	str	r0, [r7, #4]
+ 80025c4:	b510      	push	{r4, lr}
+ 80025c6:	0004      	movs	r4, r0
+ 80025c8:	b086      	sub	sp, #24
   GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8003c30:	240c      	movs	r4, #12
- 8003c32:	193b      	adds	r3, r7, r4
- 8003c34:	0018      	movs	r0, r3
- 8003c36:	2314      	movs	r3, #20
- 8003c38:	001a      	movs	r2, r3
- 8003c3a:	2100      	movs	r1, #0
- 8003c3c:	f004 f83a 	bl	8007cb4 <memset>
+ 80025ca:	2214      	movs	r2, #20
+ 80025cc:	2100      	movs	r1, #0
+ 80025ce:	a801      	add	r0, sp, #4
+ 80025d0:	f002 fddc 	bl	800518c <memset>
   if(htim->Instance==TIM1)
- 8003c40:	687b      	ldr	r3, [r7, #4]
- 8003c42:	681b      	ldr	r3, [r3, #0]
- 8003c44:	4a20      	ldr	r2, [pc, #128]	@ (8003cc8 <HAL_TIM_MspPostInit+0xa0>)
- 8003c46:	4293      	cmp	r3, r2
- 8003c48:	d139      	bne.n	8003cbe <HAL_TIM_MspPostInit+0x96>
+ 80025d4:	4b13      	ldr	r3, [pc, #76]	@ (8002624 <HAL_TIM_MspPostInit+0x60>)
+ 80025d6:	6822      	ldr	r2, [r4, #0]
+ 80025d8:	429a      	cmp	r2, r3
+ 80025da:	d120      	bne.n	800261e <HAL_TIM_MspPostInit+0x5a>
   {
     /* USER CODE BEGIN TIM1_MspPostInit 0 */
 
     /* USER CODE END TIM1_MspPostInit 0 */
 
     __HAL_RCC_GPIOA_CLK_ENABLE();
- 8003c4a:	4b20      	ldr	r3, [pc, #128]	@ (8003ccc <HAL_TIM_MspPostInit+0xa4>)
- 8003c4c:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
- 8003c4e:	4b1f      	ldr	r3, [pc, #124]	@ (8003ccc <HAL_TIM_MspPostInit+0xa4>)
- 8003c50:	2101      	movs	r1, #1
- 8003c52:	430a      	orrs	r2, r1
- 8003c54:	635a      	str	r2, [r3, #52]	@ 0x34
- 8003c56:	4b1d      	ldr	r3, [pc, #116]	@ (8003ccc <HAL_TIM_MspPostInit+0xa4>)
- 8003c58:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8003c5a:	2201      	movs	r2, #1
- 8003c5c:	4013      	ands	r3, r2
- 8003c5e:	60bb      	str	r3, [r7, #8]
- 8003c60:	68bb      	ldr	r3, [r7, #8]
-    PA2     ------> TIM1_CH3
-    PA3     ------> TIM1_CH4
-    PA8     ------> TIM1_CH1
-    PA9     ------> TIM1_CH2
-    */
+ 80025dc:	2101      	movs	r1, #1
+ 80025de:	4b12      	ldr	r3, [pc, #72]	@ (8002628 <HAL_TIM_MspPostInit+0x64>)
     GPIO_InitStruct.Pin = PEEL1_Pin|PEEL2_Pin;
- 8003c62:	193b      	adds	r3, r7, r4
- 8003c64:	220c      	movs	r2, #12
- 8003c66:	601a      	str	r2, [r3, #0]
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8003c68:	193b      	adds	r3, r7, r4
- 8003c6a:	2202      	movs	r2, #2
- 8003c6c:	605a      	str	r2, [r3, #4]
     GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8003c6e:	193b      	adds	r3, r7, r4
- 8003c70:	2200      	movs	r2, #0
- 8003c72:	609a      	str	r2, [r3, #8]
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8003c74:	193b      	adds	r3, r7, r4
- 8003c76:	2200      	movs	r2, #0
- 8003c78:	60da      	str	r2, [r3, #12]
     GPIO_InitStruct.Alternate = GPIO_AF5_TIM1;
- 8003c7a:	193b      	adds	r3, r7, r4
- 8003c7c:	2205      	movs	r2, #5
- 8003c7e:	611a      	str	r2, [r3, #16]
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8003c80:	193a      	adds	r2, r7, r4
- 8003c82:	23a0      	movs	r3, #160	@ 0xa0
- 8003c84:	05db      	lsls	r3, r3, #23
- 8003c86:	0011      	movs	r1, r2
- 8003c88:	0018      	movs	r0, r3
- 8003c8a:	f000 fda3 	bl	80047d4 <HAL_GPIO_Init>
+ 80025e0:	20a0      	movs	r0, #160	@ 0xa0
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 80025e2:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80025e4:	2402      	movs	r4, #2
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 80025e6:	430a      	orrs	r2, r1
+ 80025e8:	635a      	str	r2, [r3, #52]	@ 0x34
+ 80025ea:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80025ec:	05c0      	lsls	r0, r0, #23
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 80025ee:	400b      	ands	r3, r1
+ 80025f0:	9300      	str	r3, [sp, #0]
+ 80025f2:	9b00      	ldr	r3, [sp, #0]
+    GPIO_InitStruct.Pin = PEEL1_Pin|PEEL2_Pin;
+ 80025f4:	230c      	movs	r3, #12
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80025f6:	a901      	add	r1, sp, #4
+    GPIO_InitStruct.Pin = PEEL1_Pin|PEEL2_Pin;
+ 80025f8:	9301      	str	r3, [sp, #4]
+    GPIO_InitStruct.Alternate = GPIO_AF5_TIM1;
+ 80025fa:	3b07      	subs	r3, #7
+ 80025fc:	9305      	str	r3, [sp, #20]
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80025fe:	9402      	str	r4, [sp, #8]
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 8002600:	f000 fdc8 	bl	8003194 <HAL_GPIO_Init>
 
     GPIO_InitStruct.Pin = DRIVE1_Pin|DRIVE2_Pin;
- 8003c8e:	0021      	movs	r1, r4
- 8003c90:	187b      	adds	r3, r7, r1
- 8003c92:	22c0      	movs	r2, #192	@ 0xc0
- 8003c94:	0092      	lsls	r2, r2, #2
- 8003c96:	601a      	str	r2, [r3, #0]
+ 8002604:	23c0      	movs	r3, #192	@ 0xc0
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8003c98:	187b      	adds	r3, r7, r1
- 8003c9a:	2202      	movs	r2, #2
- 8003c9c:	605a      	str	r2, [r3, #4]
     GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8003c9e:	187b      	adds	r3, r7, r1
- 8003ca0:	2200      	movs	r2, #0
- 8003ca2:	609a      	str	r2, [r3, #8]
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8003ca4:	187b      	adds	r3, r7, r1
- 8003ca6:	2200      	movs	r2, #0
- 8003ca8:	60da      	str	r2, [r3, #12]
     GPIO_InitStruct.Alternate = GPIO_AF2_TIM1;
- 8003caa:	187b      	adds	r3, r7, r1
- 8003cac:	2202      	movs	r2, #2
- 8003cae:	611a      	str	r2, [r3, #16]
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8003cb0:	187a      	adds	r2, r7, r1
- 8003cb2:	23a0      	movs	r3, #160	@ 0xa0
- 8003cb4:	05db      	lsls	r3, r3, #23
- 8003cb6:	0011      	movs	r1, r2
- 8003cb8:	0018      	movs	r0, r3
- 8003cba:	f000 fd8b 	bl	80047d4 <HAL_GPIO_Init>
+ 8002606:	20a0      	movs	r0, #160	@ 0xa0
+    GPIO_InitStruct.Pin = DRIVE1_Pin|DRIVE2_Pin;
+ 8002608:	009b      	lsls	r3, r3, #2
+ 800260a:	9301      	str	r3, [sp, #4]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800260c:	2300      	movs	r3, #0
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 800260e:	a901      	add	r1, sp, #4
+ 8002610:	05c0      	lsls	r0, r0, #23
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 8002612:	9402      	str	r4, [sp, #8]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8002614:	9303      	str	r3, [sp, #12]
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8002616:	9304      	str	r3, [sp, #16]
+    GPIO_InitStruct.Alternate = GPIO_AF2_TIM1;
+ 8002618:	9405      	str	r4, [sp, #20]
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 800261a:	f000 fdbb 	bl	8003194 <HAL_GPIO_Init>
     /* USER CODE BEGIN TIM1_MspPostInit 1 */
 
     /* USER CODE END TIM1_MspPostInit 1 */
   }
 
 }
- 8003cbe:	46c0      	nop			@ (mov r8, r8)
- 8003cc0:	46bd      	mov	sp, r7
- 8003cc2:	b009      	add	sp, #36	@ 0x24
- 8003cc4:	bd90      	pop	{r4, r7, pc}
- 8003cc6:	46c0      	nop			@ (mov r8, r8)
- 8003cc8:	40012c00 	.word	0x40012c00
- 8003ccc:	40021000 	.word	0x40021000
+ 800261e:	b006      	add	sp, #24
+ 8002620:	bd10      	pop	{r4, pc}
+ 8002622:	46c0      	nop			@ (mov r8, r8)
+ 8002624:	40012c00 	.word	0x40012c00
+ 8002628:	40021000 	.word	0x40021000
 
-08003cd0 <HAL_UART_MspInit>:
+0800262c <HAL_UART_MspInit>:
   * This function configures the hardware resources used in this example
   * @param huart: UART handle pointer
   * @retval None
   */
 void HAL_UART_MspInit(UART_HandleTypeDef* huart)
 {
- 8003cd0:	b590      	push	{r4, r7, lr}
- 8003cd2:	b093      	sub	sp, #76	@ 0x4c
- 8003cd4:	af00      	add	r7, sp, #0
- 8003cd6:	6078      	str	r0, [r7, #4]
+ 800262c:	b530      	push	{r4, r5, lr}
+ 800262e:	0005      	movs	r5, r0
+ 8002630:	b091      	sub	sp, #68	@ 0x44
   GPIO_InitTypeDef GPIO_InitStruct = {0};
- 8003cd8:	2334      	movs	r3, #52	@ 0x34
- 8003cda:	18fb      	adds	r3, r7, r3
- 8003cdc:	0018      	movs	r0, r3
- 8003cde:	2314      	movs	r3, #20
- 8003ce0:	001a      	movs	r2, r3
- 8003ce2:	2100      	movs	r1, #0
- 8003ce4:	f003 ffe6 	bl	8007cb4 <memset>
+ 8002632:	2214      	movs	r2, #20
+ 8002634:	2100      	movs	r1, #0
+ 8002636:	a804      	add	r0, sp, #16
+ 8002638:	f002 fda8 	bl	800518c <memset>
   RCC_PeriphCLKInitTypeDef PeriphClkInit = {0};
- 8003ce8:	2418      	movs	r4, #24
- 8003cea:	193b      	adds	r3, r7, r4
- 8003cec:	0018      	movs	r0, r3
- 8003cee:	231c      	movs	r3, #28
- 8003cf0:	001a      	movs	r2, r3
- 8003cf2:	2100      	movs	r1, #0
- 8003cf4:	f003 ffde 	bl	8007cb4 <memset>
+ 800263c:	221c      	movs	r2, #28
+ 800263e:	2100      	movs	r1, #0
+ 8002640:	a809      	add	r0, sp, #36	@ 0x24
+ 8002642:	f002 fda3 	bl	800518c <memset>
   if(huart->Instance==USART1)
- 8003cf8:	687b      	ldr	r3, [r7, #4]
- 8003cfa:	681b      	ldr	r3, [r3, #0]
- 8003cfc:	4a68      	ldr	r2, [pc, #416]	@ (8003ea0 <HAL_UART_MspInit+0x1d0>)
- 8003cfe:	4293      	cmp	r3, r2
- 8003d00:	d13e      	bne.n	8003d80 <HAL_UART_MspInit+0xb0>
+ 8002646:	682b      	ldr	r3, [r5, #0]
+ 8002648:	4a43      	ldr	r2, [pc, #268]	@ (8002758 <HAL_UART_MspInit+0x12c>)
+ 800264a:	4293      	cmp	r3, r2
+ 800264c:	d127      	bne.n	800269e <HAL_UART_MspInit+0x72>
 
     /* USER CODE END USART1_MspInit 0 */
 
   /** Initializes the peripherals clocks
   */
     PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
- 8003d02:	193b      	adds	r3, r7, r4
- 8003d04:	2201      	movs	r2, #1
- 8003d06:	601a      	str	r2, [r3, #0]
+ 800264e:	2301      	movs	r3, #1
     PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK1;
- 8003d08:	193b      	adds	r3, r7, r4
- 8003d0a:	2200      	movs	r2, #0
- 8003d0c:	609a      	str	r2, [r3, #8]
     if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
- 8003d0e:	193b      	adds	r3, r7, r4
- 8003d10:	0018      	movs	r0, r3
- 8003d12:	f001 fab3 	bl	800527c <HAL_RCCEx_PeriphCLKConfig>
- 8003d16:	1e03      	subs	r3, r0, #0
- 8003d18:	d001      	beq.n	8003d1e <HAL_UART_MspInit+0x4e>
+ 8002650:	a809      	add	r0, sp, #36	@ 0x24
+    PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1;
+ 8002652:	9309      	str	r3, [sp, #36]	@ 0x24
+    if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK)
+ 8002654:	f001 f8b8 	bl	80037c8 <HAL_RCCEx_PeriphCLKConfig>
+ 8002658:	2800      	cmp	r0, #0
+ 800265a:	d001      	beq.n	8002660 <HAL_UART_MspInit+0x34>
     {
       Error_Handler();
- 8003d1a:	f7ff fe97 	bl	8003a4c <Error_Handler>
+ 800265c:	f7ff fec0 	bl	80023e0 <Error_Handler>
     }
 
     /* Peripheral clock enable */
     __HAL_RCC_USART1_CLK_ENABLE();
- 8003d1e:	4b61      	ldr	r3, [pc, #388]	@ (8003ea4 <HAL_UART_MspInit+0x1d4>)
- 8003d20:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8003d22:	4b60      	ldr	r3, [pc, #384]	@ (8003ea4 <HAL_UART_MspInit+0x1d4>)
- 8003d24:	2180      	movs	r1, #128	@ 0x80
- 8003d26:	01c9      	lsls	r1, r1, #7
- 8003d28:	430a      	orrs	r2, r1
- 8003d2a:	641a      	str	r2, [r3, #64]	@ 0x40
- 8003d2c:	4b5d      	ldr	r3, [pc, #372]	@ (8003ea4 <HAL_UART_MspInit+0x1d4>)
- 8003d2e:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 8003d30:	2380      	movs	r3, #128	@ 0x80
- 8003d32:	01db      	lsls	r3, r3, #7
- 8003d34:	4013      	ands	r3, r2
- 8003d36:	617b      	str	r3, [r7, #20]
- 8003d38:	697b      	ldr	r3, [r7, #20]
-
-    __HAL_RCC_GPIOB_CLK_ENABLE();
- 8003d3a:	4b5a      	ldr	r3, [pc, #360]	@ (8003ea4 <HAL_UART_MspInit+0x1d4>)
- 8003d3c:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
- 8003d3e:	4b59      	ldr	r3, [pc, #356]	@ (8003ea4 <HAL_UART_MspInit+0x1d4>)
- 8003d40:	2102      	movs	r1, #2
- 8003d42:	430a      	orrs	r2, r1
- 8003d44:	635a      	str	r2, [r3, #52]	@ 0x34
- 8003d46:	4b57      	ldr	r3, [pc, #348]	@ (8003ea4 <HAL_UART_MspInit+0x1d4>)
- 8003d48:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8003d4a:	2202      	movs	r2, #2
- 8003d4c:	4013      	ands	r3, r2
- 8003d4e:	613b      	str	r3, [r7, #16]
- 8003d50:	693b      	ldr	r3, [r7, #16]
-    /**USART1 GPIO Configuration
-    PB6     ------> USART1_TX
-    PB7     ------> USART1_RX
-    */
+ 8002660:	2180      	movs	r1, #128	@ 0x80
+ 8002662:	4b3e      	ldr	r3, [pc, #248]	@ (800275c <HAL_UART_MspInit+0x130>)
+ 8002664:	01c9      	lsls	r1, r1, #7
+ 8002666:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
     GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
- 8003d52:	2134      	movs	r1, #52	@ 0x34
- 8003d54:	187b      	adds	r3, r7, r1
- 8003d56:	22c0      	movs	r2, #192	@ 0xc0
- 8003d58:	601a      	str	r2, [r3, #0]
     GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8003d5a:	187b      	adds	r3, r7, r1
- 8003d5c:	2202      	movs	r2, #2
- 8003d5e:	605a      	str	r2, [r3, #4]
     GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8003d60:	187b      	adds	r3, r7, r1
- 8003d62:	2200      	movs	r2, #0
- 8003d64:	609a      	str	r2, [r3, #8]
     GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8003d66:	187b      	adds	r3, r7, r1
- 8003d68:	2200      	movs	r2, #0
- 8003d6a:	60da      	str	r2, [r3, #12]
     GPIO_InitStruct.Alternate = GPIO_AF0_USART1;
- 8003d6c:	187b      	adds	r3, r7, r1
- 8003d6e:	2200      	movs	r2, #0
- 8003d70:	611a      	str	r2, [r3, #16]
     HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
- 8003d72:	187b      	adds	r3, r7, r1
- 8003d74:	4a4c      	ldr	r2, [pc, #304]	@ (8003ea8 <HAL_UART_MspInit+0x1d8>)
- 8003d76:	0019      	movs	r1, r3
- 8003d78:	0010      	movs	r0, r2
- 8003d7a:	f000 fd2b 	bl	80047d4 <HAL_GPIO_Init>
+ 8002668:	483d      	ldr	r0, [pc, #244]	@ (8002760 <HAL_UART_MspInit+0x134>)
+    __HAL_RCC_USART1_CLK_ENABLE();
+ 800266a:	430a      	orrs	r2, r1
+ 800266c:	641a      	str	r2, [r3, #64]	@ 0x40
+ 800266e:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
+ 8002670:	400a      	ands	r2, r1
+ 8002672:	9200      	str	r2, [sp, #0]
+ 8002674:	9a00      	ldr	r2, [sp, #0]
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8002676:	2202      	movs	r2, #2
+ 8002678:	6b59      	ldr	r1, [r3, #52]	@ 0x34
+ 800267a:	4311      	orrs	r1, r2
+ 800267c:	6359      	str	r1, [r3, #52]	@ 0x34
+ 800267e:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8002680:	a904      	add	r1, sp, #16
+    __HAL_RCC_GPIOB_CLK_ENABLE();
+ 8002682:	4013      	ands	r3, r2
+ 8002684:	9301      	str	r3, [sp, #4]
+ 8002686:	9b01      	ldr	r3, [sp, #4]
+    GPIO_InitStruct.Pin = GPIO_PIN_6|GPIO_PIN_7;
+ 8002688:	23c0      	movs	r3, #192	@ 0xc0
+ 800268a:	9304      	str	r3, [sp, #16]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 800268c:	2300      	movs	r3, #0
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 800268e:	9205      	str	r2, [sp, #20]
+    GPIO_InitStruct.Pull = GPIO_NOPULL;
+ 8002690:	9306      	str	r3, [sp, #24]
+    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
+ 8002692:	9307      	str	r3, [sp, #28]
+    GPIO_InitStruct.Alternate = GPIO_AF0_USART1;
+ 8002694:	9308      	str	r3, [sp, #32]
+    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
+ 8002696:	f000 fd7d 	bl	8003194 <HAL_GPIO_Init>
     /* USER CODE BEGIN USART2_MspInit 1 */
 
     /* USER CODE END USART2_MspInit 1 */
   }
 
 }
- 8003d7e:	e08b      	b.n	8003e98 <HAL_UART_MspInit+0x1c8>
+ 800269a:	b011      	add	sp, #68	@ 0x44
+ 800269c:	bd30      	pop	{r4, r5, pc}
   else if(huart->Instance==USART2)
- 8003d80:	687b      	ldr	r3, [r7, #4]
- 8003d82:	681b      	ldr	r3, [r3, #0]
- 8003d84:	4a49      	ldr	r2, [pc, #292]	@ (8003eac <HAL_UART_MspInit+0x1dc>)
- 8003d86:	4293      	cmp	r3, r2
- 8003d88:	d000      	beq.n	8003d8c <HAL_UART_MspInit+0xbc>
- 8003d8a:	e085      	b.n	8003e98 <HAL_UART_MspInit+0x1c8>
+ 800269e:	4a31      	ldr	r2, [pc, #196]	@ (8002764 <HAL_UART_MspInit+0x138>)
+ 80026a0:	4293      	cmp	r3, r2
+ 80026a2:	d1fa      	bne.n	800269a <HAL_UART_MspInit+0x6e>
     __HAL_RCC_USART2_CLK_ENABLE();
- 8003d8c:	4b45      	ldr	r3, [pc, #276]	@ (8003ea4 <HAL_UART_MspInit+0x1d4>)
- 8003d8e:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
- 8003d90:	4b44      	ldr	r3, [pc, #272]	@ (8003ea4 <HAL_UART_MspInit+0x1d4>)
- 8003d92:	2180      	movs	r1, #128	@ 0x80
- 8003d94:	0289      	lsls	r1, r1, #10
- 8003d96:	430a      	orrs	r2, r1
- 8003d98:	63da      	str	r2, [r3, #60]	@ 0x3c
- 8003d9a:	4b42      	ldr	r3, [pc, #264]	@ (8003ea4 <HAL_UART_MspInit+0x1d4>)
- 8003d9c:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
- 8003d9e:	2380      	movs	r3, #128	@ 0x80
- 8003da0:	029b      	lsls	r3, r3, #10
- 8003da2:	4013      	ands	r3, r2
- 8003da4:	60fb      	str	r3, [r7, #12]
- 8003da6:	68fb      	ldr	r3, [r7, #12]
-    __HAL_RCC_GPIOA_CLK_ENABLE();
- 8003da8:	4b3e      	ldr	r3, [pc, #248]	@ (8003ea4 <HAL_UART_MspInit+0x1d4>)
- 8003daa:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
- 8003dac:	4b3d      	ldr	r3, [pc, #244]	@ (8003ea4 <HAL_UART_MspInit+0x1d4>)
- 8003dae:	2101      	movs	r1, #1
- 8003db0:	430a      	orrs	r2, r1
- 8003db2:	635a      	str	r2, [r3, #52]	@ 0x34
- 8003db4:	4b3b      	ldr	r3, [pc, #236]	@ (8003ea4 <HAL_UART_MspInit+0x1d4>)
- 8003db6:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8003db8:	2201      	movs	r2, #1
- 8003dba:	4013      	ands	r3, r2
- 8003dbc:	60bb      	str	r3, [r7, #8]
- 8003dbe:	68bb      	ldr	r3, [r7, #8]
-    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
- 8003dc0:	2134      	movs	r1, #52	@ 0x34
- 8003dc2:	187b      	adds	r3, r7, r1
- 8003dc4:	2232      	movs	r2, #50	@ 0x32
- 8003dc6:	601a      	str	r2, [r3, #0]
-    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
- 8003dc8:	187b      	adds	r3, r7, r1
- 8003dca:	2202      	movs	r2, #2
- 8003dcc:	605a      	str	r2, [r3, #4]
-    GPIO_InitStruct.Pull = GPIO_NOPULL;
- 8003dce:	187b      	adds	r3, r7, r1
- 8003dd0:	2200      	movs	r2, #0
- 8003dd2:	609a      	str	r2, [r3, #8]
-    GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW;
- 8003dd4:	187b      	adds	r3, r7, r1
- 8003dd6:	2200      	movs	r2, #0
- 8003dd8:	60da      	str	r2, [r3, #12]
-    GPIO_InitStruct.Alternate = GPIO_AF1_USART2;
- 8003dda:	187b      	adds	r3, r7, r1
- 8003ddc:	2201      	movs	r2, #1
- 8003dde:	611a      	str	r2, [r3, #16]
+ 80026a4:	2180      	movs	r1, #128	@ 0x80
+ 80026a6:	4b2d      	ldr	r3, [pc, #180]	@ (800275c <HAL_UART_MspInit+0x130>)
+ 80026a8:	0289      	lsls	r1, r1, #10
+ 80026aa:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
     HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
- 8003de0:	187a      	adds	r2, r7, r1
- 8003de2:	23a0      	movs	r3, #160	@ 0xa0
- 8003de4:	05db      	lsls	r3, r3, #23
- 8003de6:	0011      	movs	r1, r2
- 8003de8:	0018      	movs	r0, r3
- 8003dea:	f000 fcf3 	bl	80047d4 <HAL_GPIO_Init>
+ 80026ac:	20a0      	movs	r0, #160	@ 0xa0
+    __HAL_RCC_USART2_CLK_ENABLE();
+ 80026ae:	430a      	orrs	r2, r1
+ 80026b0:	63da      	str	r2, [r3, #60]	@ 0x3c
+ 80026b2:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80026b4:	05c0      	lsls	r0, r0, #23
+    __HAL_RCC_USART2_CLK_ENABLE();
+ 80026b6:	400a      	ands	r2, r1
+ 80026b8:	9202      	str	r2, [sp, #8]
+ 80026ba:	9a02      	ldr	r2, [sp, #8]
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 80026bc:	2201      	movs	r2, #1
+ 80026be:	6b59      	ldr	r1, [r3, #52]	@ 0x34
+ 80026c0:	4311      	orrs	r1, r2
+ 80026c2:	6359      	str	r1, [r3, #52]	@ 0x34
+ 80026c4:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80026c6:	a904      	add	r1, sp, #16
+    __HAL_RCC_GPIOA_CLK_ENABLE();
+ 80026c8:	4013      	ands	r3, r2
+ 80026ca:	9303      	str	r3, [sp, #12]
+ 80026cc:	9b03      	ldr	r3, [sp, #12]
+    GPIO_InitStruct.Pin = GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5;
+ 80026ce:	2332      	movs	r3, #50	@ 0x32
+ 80026d0:	9304      	str	r3, [sp, #16]
+    GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
+ 80026d2:	3b30      	subs	r3, #48	@ 0x30
+ 80026d4:	9305      	str	r3, [sp, #20]
+    GPIO_InitStruct.Alternate = GPIO_AF1_USART2;
+ 80026d6:	9208      	str	r2, [sp, #32]
+    HAL_GPIO_Init(GPIOA, &GPIO_InitStruct);
+ 80026d8:	f000 fd5c 	bl	8003194 <HAL_GPIO_Init>
     hdma_usart2_rx.Instance = DMA1_Channel2;
- 8003dee:	4b30      	ldr	r3, [pc, #192]	@ (8003eb0 <HAL_UART_MspInit+0x1e0>)
- 8003df0:	4a30      	ldr	r2, [pc, #192]	@ (8003eb4 <HAL_UART_MspInit+0x1e4>)
- 8003df2:	601a      	str	r2, [r3, #0]
-    hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX;
- 8003df4:	4b2e      	ldr	r3, [pc, #184]	@ (8003eb0 <HAL_UART_MspInit+0x1e0>)
- 8003df6:	2234      	movs	r2, #52	@ 0x34
- 8003df8:	605a      	str	r2, [r3, #4]
-    hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
- 8003dfa:	4b2d      	ldr	r3, [pc, #180]	@ (8003eb0 <HAL_UART_MspInit+0x1e0>)
- 8003dfc:	2200      	movs	r2, #0
- 8003dfe:	609a      	str	r2, [r3, #8]
-    hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
- 8003e00:	4b2b      	ldr	r3, [pc, #172]	@ (8003eb0 <HAL_UART_MspInit+0x1e0>)
- 8003e02:	2200      	movs	r2, #0
- 8003e04:	60da      	str	r2, [r3, #12]
+ 80026dc:	4c22      	ldr	r4, [pc, #136]	@ (8002768 <HAL_UART_MspInit+0x13c>)
+ 80026de:	4b23      	ldr	r3, [pc, #140]	@ (800276c <HAL_UART_MspInit+0x140>)
     hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
- 8003e06:	4b2a      	ldr	r3, [pc, #168]	@ (8003eb0 <HAL_UART_MspInit+0x1e0>)
- 8003e08:	2280      	movs	r2, #128	@ 0x80
- 8003e0a:	611a      	str	r2, [r3, #16]
+ 80026e0:	2280      	movs	r2, #128	@ 0x80
+    hdma_usart2_rx.Instance = DMA1_Channel2;
+ 80026e2:	6023      	str	r3, [r4, #0]
+    hdma_usart2_rx.Init.Request = DMA_REQUEST_USART2_RX;
+ 80026e4:	2334      	movs	r3, #52	@ 0x34
+ 80026e6:	6063      	str	r3, [r4, #4]
+    hdma_usart2_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
+ 80026e8:	2300      	movs	r3, #0
+ 80026ea:	60a3      	str	r3, [r4, #8]
+    hdma_usart2_rx.Init.PeriphInc = DMA_PINC_DISABLE;
+ 80026ec:	60e3      	str	r3, [r4, #12]
     hdma_usart2_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
- 8003e0c:	4b28      	ldr	r3, [pc, #160]	@ (8003eb0 <HAL_UART_MspInit+0x1e0>)
- 8003e0e:	2200      	movs	r2, #0
- 8003e10:	615a      	str	r2, [r3, #20]
+ 80026ee:	6163      	str	r3, [r4, #20]
     hdma_usart2_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
- 8003e12:	4b27      	ldr	r3, [pc, #156]	@ (8003eb0 <HAL_UART_MspInit+0x1e0>)
- 8003e14:	2200      	movs	r2, #0
- 8003e16:	619a      	str	r2, [r3, #24]
+ 80026f0:	61a3      	str	r3, [r4, #24]
     hdma_usart2_rx.Init.Mode = DMA_NORMAL;
- 8003e18:	4b25      	ldr	r3, [pc, #148]	@ (8003eb0 <HAL_UART_MspInit+0x1e0>)
- 8003e1a:	2200      	movs	r2, #0
- 8003e1c:	61da      	str	r2, [r3, #28]
+ 80026f2:	61e3      	str	r3, [r4, #28]
     hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
- 8003e1e:	4b24      	ldr	r3, [pc, #144]	@ (8003eb0 <HAL_UART_MspInit+0x1e0>)
- 8003e20:	2280      	movs	r2, #128	@ 0x80
- 8003e22:	0152      	lsls	r2, r2, #5
- 8003e24:	621a      	str	r2, [r3, #32]
+ 80026f4:	2380      	movs	r3, #128	@ 0x80
     if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
- 8003e26:	4b22      	ldr	r3, [pc, #136]	@ (8003eb0 <HAL_UART_MspInit+0x1e0>)
- 8003e28:	0018      	movs	r0, r3
- 8003e2a:	f000 fa7f 	bl	800432c <HAL_DMA_Init>
- 8003e2e:	1e03      	subs	r3, r0, #0
- 8003e30:	d001      	beq.n	8003e36 <HAL_UART_MspInit+0x166>
+ 80026f6:	0020      	movs	r0, r4
+    hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
+ 80026f8:	015b      	lsls	r3, r3, #5
+    hdma_usart2_rx.Init.MemInc = DMA_MINC_ENABLE;
+ 80026fa:	6122      	str	r2, [r4, #16]
+    hdma_usart2_rx.Init.Priority = DMA_PRIORITY_MEDIUM;
+ 80026fc:	6223      	str	r3, [r4, #32]
+    if (HAL_DMA_Init(&hdma_usart2_rx) != HAL_OK)
+ 80026fe:	f000 fbdb 	bl	8002eb8 <HAL_DMA_Init>
+ 8002702:	2800      	cmp	r0, #0
+ 8002704:	d001      	beq.n	800270a <HAL_UART_MspInit+0xde>
       Error_Handler();
- 8003e32:	f7ff fe0b 	bl	8003a4c <Error_Handler>
+ 8002706:	f7ff fe6b 	bl	80023e0 <Error_Handler>
     __HAL_LINKDMA(huart,hdmarx,hdma_usart2_rx);
- 8003e36:	687b      	ldr	r3, [r7, #4]
- 8003e38:	2180      	movs	r1, #128	@ 0x80
- 8003e3a:	4a1d      	ldr	r2, [pc, #116]	@ (8003eb0 <HAL_UART_MspInit+0x1e0>)
- 8003e3c:	505a      	str	r2, [r3, r1]
- 8003e3e:	4b1c      	ldr	r3, [pc, #112]	@ (8003eb0 <HAL_UART_MspInit+0x1e0>)
- 8003e40:	687a      	ldr	r2, [r7, #4]
- 8003e42:	629a      	str	r2, [r3, #40]	@ 0x28
+ 800270a:	1d2b      	adds	r3, r5, #4
+ 800270c:	67dc      	str	r4, [r3, #124]	@ 0x7c
+ 800270e:	62a5      	str	r5, [r4, #40]	@ 0x28
     hdma_usart2_tx.Instance = DMA1_Channel1;
- 8003e44:	4b1c      	ldr	r3, [pc, #112]	@ (8003eb8 <HAL_UART_MspInit+0x1e8>)
- 8003e46:	4a1d      	ldr	r2, [pc, #116]	@ (8003ebc <HAL_UART_MspInit+0x1ec>)
- 8003e48:	601a      	str	r2, [r3, #0]
-    hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX;
- 8003e4a:	4b1b      	ldr	r3, [pc, #108]	@ (8003eb8 <HAL_UART_MspInit+0x1e8>)
- 8003e4c:	2235      	movs	r2, #53	@ 0x35
- 8003e4e:	605a      	str	r2, [r3, #4]
-    hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
- 8003e50:	4b19      	ldr	r3, [pc, #100]	@ (8003eb8 <HAL_UART_MspInit+0x1e8>)
- 8003e52:	2210      	movs	r2, #16
- 8003e54:	609a      	str	r2, [r3, #8]
-    hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
- 8003e56:	4b18      	ldr	r3, [pc, #96]	@ (8003eb8 <HAL_UART_MspInit+0x1e8>)
- 8003e58:	2200      	movs	r2, #0
- 8003e5a:	60da      	str	r2, [r3, #12]
+ 8002710:	4b17      	ldr	r3, [pc, #92]	@ (8002770 <HAL_UART_MspInit+0x144>)
+ 8002712:	4c18      	ldr	r4, [pc, #96]	@ (8002774 <HAL_UART_MspInit+0x148>)
     hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
- 8003e5c:	4b16      	ldr	r3, [pc, #88]	@ (8003eb8 <HAL_UART_MspInit+0x1e8>)
- 8003e5e:	2280      	movs	r2, #128	@ 0x80
- 8003e60:	611a      	str	r2, [r3, #16]
+ 8002714:	2280      	movs	r2, #128	@ 0x80
+    hdma_usart2_tx.Instance = DMA1_Channel1;
+ 8002716:	6023      	str	r3, [r4, #0]
+    hdma_usart2_tx.Init.Request = DMA_REQUEST_USART2_TX;
+ 8002718:	2335      	movs	r3, #53	@ 0x35
+ 800271a:	6063      	str	r3, [r4, #4]
+    hdma_usart2_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
+ 800271c:	3b25      	subs	r3, #37	@ 0x25
+ 800271e:	60a3      	str	r3, [r4, #8]
+    hdma_usart2_tx.Init.PeriphInc = DMA_PINC_DISABLE;
+ 8002720:	2300      	movs	r3, #0
+ 8002722:	60e3      	str	r3, [r4, #12]
     hdma_usart2_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
- 8003e62:	4b15      	ldr	r3, [pc, #84]	@ (8003eb8 <HAL_UART_MspInit+0x1e8>)
- 8003e64:	2200      	movs	r2, #0
- 8003e66:	615a      	str	r2, [r3, #20]
+ 8002724:	6163      	str	r3, [r4, #20]
     hdma_usart2_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
- 8003e68:	4b13      	ldr	r3, [pc, #76]	@ (8003eb8 <HAL_UART_MspInit+0x1e8>)
- 8003e6a:	2200      	movs	r2, #0
- 8003e6c:	619a      	str	r2, [r3, #24]
+ 8002726:	61a3      	str	r3, [r4, #24]
     hdma_usart2_tx.Init.Mode = DMA_NORMAL;
- 8003e6e:	4b12      	ldr	r3, [pc, #72]	@ (8003eb8 <HAL_UART_MspInit+0x1e8>)
- 8003e70:	2200      	movs	r2, #0
- 8003e72:	61da      	str	r2, [r3, #28]
+ 8002728:	61e3      	str	r3, [r4, #28]
     hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH;
- 8003e74:	4b10      	ldr	r3, [pc, #64]	@ (8003eb8 <HAL_UART_MspInit+0x1e8>)
- 8003e76:	2280      	movs	r2, #128	@ 0x80
- 8003e78:	0192      	lsls	r2, r2, #6
- 8003e7a:	621a      	str	r2, [r3, #32]
+ 800272a:	2380      	movs	r3, #128	@ 0x80
     if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
- 8003e7c:	4b0e      	ldr	r3, [pc, #56]	@ (8003eb8 <HAL_UART_MspInit+0x1e8>)
- 8003e7e:	0018      	movs	r0, r3
- 8003e80:	f000 fa54 	bl	800432c <HAL_DMA_Init>
- 8003e84:	1e03      	subs	r3, r0, #0
- 8003e86:	d001      	beq.n	8003e8c <HAL_UART_MspInit+0x1bc>
+ 800272c:	0020      	movs	r0, r4
+    hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH;
+ 800272e:	019b      	lsls	r3, r3, #6
+    hdma_usart2_tx.Init.MemInc = DMA_MINC_ENABLE;
+ 8002730:	6122      	str	r2, [r4, #16]
+    hdma_usart2_tx.Init.Priority = DMA_PRIORITY_HIGH;
+ 8002732:	6223      	str	r3, [r4, #32]
+    if (HAL_DMA_Init(&hdma_usart2_tx) != HAL_OK)
+ 8002734:	f000 fbc0 	bl	8002eb8 <HAL_DMA_Init>
+ 8002738:	2800      	cmp	r0, #0
+ 800273a:	d001      	beq.n	8002740 <HAL_UART_MspInit+0x114>
       Error_Handler();
- 8003e88:	f7ff fde0 	bl	8003a4c <Error_Handler>
+ 800273c:	f7ff fe50 	bl	80023e0 <Error_Handler>
+    HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
+ 8002740:	2200      	movs	r2, #0
+ 8002742:	201c      	movs	r0, #28
+ 8002744:	0011      	movs	r1, r2
     __HAL_LINKDMA(huart,hdmatx,hdma_usart2_tx);
- 8003e8c:	687b      	ldr	r3, [r7, #4]
- 8003e8e:	4a0a      	ldr	r2, [pc, #40]	@ (8003eb8 <HAL_UART_MspInit+0x1e8>)
- 8003e90:	67da      	str	r2, [r3, #124]	@ 0x7c
- 8003e92:	4b09      	ldr	r3, [pc, #36]	@ (8003eb8 <HAL_UART_MspInit+0x1e8>)
- 8003e94:	687a      	ldr	r2, [r7, #4]
- 8003e96:	629a      	str	r2, [r3, #40]	@ 0x28
+ 8002746:	67ec      	str	r4, [r5, #124]	@ 0x7c
+ 8002748:	62a5      	str	r5, [r4, #40]	@ 0x28
+    HAL_NVIC_SetPriority(USART2_IRQn, 0, 0);
+ 800274a:	f000 fb2b 	bl	8002da4 <HAL_NVIC_SetPriority>
+    HAL_NVIC_EnableIRQ(USART2_IRQn);
+ 800274e:	201c      	movs	r0, #28
+ 8002750:	f000 fb52 	bl	8002df8 <HAL_NVIC_EnableIRQ>
 }
- 8003e98:	46c0      	nop			@ (mov r8, r8)
- 8003e9a:	46bd      	mov	sp, r7
- 8003e9c:	b013      	add	sp, #76	@ 0x4c
- 8003e9e:	bd90      	pop	{r4, r7, pc}
- 8003ea0:	40013800 	.word	0x40013800
- 8003ea4:	40021000 	.word	0x40021000
- 8003ea8:	50000400 	.word	0x50000400
- 8003eac:	40004400 	.word	0x40004400
- 8003eb0:	200002f0 	.word	0x200002f0
- 8003eb4:	4002001c 	.word	0x4002001c
- 8003eb8:	2000034c 	.word	0x2000034c
- 8003ebc:	40020008 	.word	0x40020008
+ 8002754:	e7a1      	b.n	800269a <HAL_UART_MspInit+0x6e>
+ 8002756:	46c0      	nop			@ (mov r8, r8)
+ 8002758:	40013800 	.word	0x40013800
+ 800275c:	40021000 	.word	0x40021000
+ 8002760:	50000400 	.word	0x50000400
+ 8002764:	40004400 	.word	0x40004400
+ 8002768:	20000ffc 	.word	0x20000ffc
+ 800276c:	4002001c 	.word	0x4002001c
+ 8002770:	40020008 	.word	0x40020008
+ 8002774:	20000fa0 	.word	0x20000fa0
 
-08003ec0 <NMI_Handler>:
-/******************************************************************************/
-/**
-  * @brief This function handles Non maskable interrupt.
-  */
-void NMI_Handler(void)
+08002778 <NMI_Handler>:
 {
- 8003ec0:	b580      	push	{r7, lr}
- 8003ec2:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN NonMaskableInt_IRQn 0 */
 
   /* USER CODE END NonMaskableInt_IRQn 0 */
   /* USER CODE BEGIN NonMaskableInt_IRQn 1 */
    while (1)
- 8003ec4:	46c0      	nop			@ (mov r8, r8)
- 8003ec6:	e7fd      	b.n	8003ec4 <NMI_Handler+0x4>
+ 8002778:	e7fe      	b.n	8002778 <NMI_Handler>
 
-08003ec8 <HardFault_Handler>:
-
-/**
-  * @brief This function handles Hard fault interrupt.
-  */
+0800277a <HardFault_Handler>:
 void HardFault_Handler(void)
 {
- 8003ec8:	b580      	push	{r7, lr}
- 8003eca:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN HardFault_IRQn 0 */
 
   /* USER CODE END HardFault_IRQn 0 */
   while (1)
- 8003ecc:	46c0      	nop			@ (mov r8, r8)
- 8003ece:	e7fd      	b.n	8003ecc <HardFault_Handler+0x4>
+ 800277a:	e7fe      	b.n	800277a <HardFault_Handler>
 
-08003ed0 <SVC_Handler>:
-
-/**
-  * @brief This function handles System service call via SWI instruction.
-  */
-void SVC_Handler(void)
-{
- 8003ed0:	b580      	push	{r7, lr}
- 8003ed2:	af00      	add	r7, sp, #0
+0800277c <SVC_Handler>:
 
   /* USER CODE END SVCall_IRQn 0 */
   /* USER CODE BEGIN SVCall_IRQn 1 */
 
   /* USER CODE END SVCall_IRQn 1 */
 }
- 8003ed4:	46c0      	nop			@ (mov r8, r8)
- 8003ed6:	46bd      	mov	sp, r7
- 8003ed8:	bd80      	pop	{r7, pc}
+ 800277c:	4770      	bx	lr
 
-08003eda <PendSV_Handler>:
+0800277e <PendSV_Handler>:
 
 /**
   * @brief This function handles Pendable request for system service.
   */
 void PendSV_Handler(void)
-{
- 8003eda:	b580      	push	{r7, lr}
- 8003edc:	af00      	add	r7, sp, #0
+ 800277e:	4770      	bx	lr
 
-  /* USER CODE END PendSV_IRQn 0 */
-  /* USER CODE BEGIN PendSV_IRQn 1 */
-
-  /* USER CODE END PendSV_IRQn 1 */
-}
- 8003ede:	46c0      	nop			@ (mov r8, r8)
- 8003ee0:	46bd      	mov	sp, r7
- 8003ee2:	bd80      	pop	{r7, pc}
-
-08003ee4 <SysTick_Handler>:
+08002780 <SysTick_Handler>:
 
 /**
   * @brief This function handles System tick timer.
   */
 void SysTick_Handler(void)
 {
- 8003ee4:	b580      	push	{r7, lr}
- 8003ee6:	af00      	add	r7, sp, #0
+ 8002780:	b510      	push	{r4, lr}
   /* USER CODE BEGIN SysTick_IRQn 0 */
 
   /* USER CODE END SysTick_IRQn 0 */
   HAL_IncTick();
- 8003ee8:	f000 f8e4 	bl	80040b4 <HAL_IncTick>
+ 8002782:	f000 f8a1 	bl	80028c8 <HAL_IncTick>
   /* USER CODE BEGIN SysTick_IRQn 1 */
 
   /* USER CODE END SysTick_IRQn 1 */
 }
- 8003eec:	46c0      	nop			@ (mov r8, r8)
- 8003eee:	46bd      	mov	sp, r7
- 8003ef0:	bd80      	pop	{r7, pc}
+ 8002786:	bd10      	pop	{r4, pc}
 
-08003ef2 <EXTI4_15_IRQHandler>:
-
-/**
-  * @brief This function handles EXTI line 4 to 15 interrupts.
-  */
+08002788 <EXTI4_15_IRQHandler>:
 void EXTI4_15_IRQHandler(void)
 {
- 8003ef2:	b580      	push	{r7, lr}
- 8003ef4:	af00      	add	r7, sp, #0
   /* USER CODE BEGIN EXTI4_15_IRQn 0 */
 
   /* USER CODE END EXTI4_15_IRQn 0 */
   HAL_GPIO_EXTI_IRQHandler(SW2_Pin);
- 8003ef6:	2380      	movs	r3, #128	@ 0x80
- 8003ef8:	005b      	lsls	r3, r3, #1
- 8003efa:	0018      	movs	r0, r3
- 8003efc:	f000 fe16 	bl	8004b2c <HAL_GPIO_EXTI_IRQHandler>
+ 8002788:	2080      	movs	r0, #128	@ 0x80
+{
+ 800278a:	b510      	push	{r4, lr}
+  HAL_GPIO_EXTI_IRQHandler(SW2_Pin);
+ 800278c:	0040      	lsls	r0, r0, #1
+ 800278e:	f000 fdc9 	bl	8003324 <HAL_GPIO_EXTI_IRQHandler>
   HAL_GPIO_EXTI_IRQHandler(SW1_Pin);
- 8003f00:	2380      	movs	r3, #128	@ 0x80
- 8003f02:	009b      	lsls	r3, r3, #2
- 8003f04:	0018      	movs	r0, r3
- 8003f06:	f000 fe11 	bl	8004b2c <HAL_GPIO_EXTI_IRQHandler>
+ 8002792:	2080      	movs	r0, #128	@ 0x80
+ 8002794:	0080      	lsls	r0, r0, #2
+ 8002796:	f000 fdc5 	bl	8003324 <HAL_GPIO_EXTI_IRQHandler>
   /* USER CODE BEGIN EXTI4_15_IRQn 1 */
 
   /* USER CODE END EXTI4_15_IRQn 1 */
 }
- 8003f0a:	46c0      	nop			@ (mov r8, r8)
- 8003f0c:	46bd      	mov	sp, r7
- 8003f0e:	bd80      	pop	{r7, pc}
+ 800279a:	bd10      	pop	{r4, pc}
 
-08003f10 <DMA1_Channel1_IRQHandler>:
+0800279c <DMA1_Channel1_IRQHandler>:
 
 /**
   * @brief This function handles DMA1 channel 1 interrupt.
   */
 void DMA1_Channel1_IRQHandler(void)
 {
- 8003f10:	b580      	push	{r7, lr}
- 8003f12:	af00      	add	r7, sp, #0
+ 800279c:	b510      	push	{r4, lr}
   /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */
 
   /* USER CODE END DMA1_Channel1_IRQn 0 */
   HAL_DMA_IRQHandler(&hdma_usart2_tx);
- 8003f14:	4b03      	ldr	r3, [pc, #12]	@ (8003f24 <DMA1_Channel1_IRQHandler+0x14>)
- 8003f16:	0018      	movs	r0, r3
- 8003f18:	f000 fb1a 	bl	8004550 <HAL_DMA_IRQHandler>
+ 800279e:	4802      	ldr	r0, [pc, #8]	@ (80027a8 <DMA1_Channel1_IRQHandler+0xc>)
+ 80027a0:	f000 fca4 	bl	80030ec <HAL_DMA_IRQHandler>
   /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */
 
   /* USER CODE END DMA1_Channel1_IRQn 1 */
 }
- 8003f1c:	46c0      	nop			@ (mov r8, r8)
- 8003f1e:	46bd      	mov	sp, r7
- 8003f20:	bd80      	pop	{r7, pc}
- 8003f22:	46c0      	nop			@ (mov r8, r8)
- 8003f24:	2000034c 	.word	0x2000034c
+ 80027a4:	bd10      	pop	{r4, pc}
+ 80027a6:	46c0      	nop			@ (mov r8, r8)
+ 80027a8:	20000fa0 	.word	0x20000fa0
 
-08003f28 <DMA1_Channel2_3_IRQHandler>:
+080027ac <DMA1_Channel2_3_IRQHandler>:
 
 /**
   * @brief This function handles DMA1 channel 2 and channel 3 interrupts.
   */
 void DMA1_Channel2_3_IRQHandler(void)
 {
- 8003f28:	b580      	push	{r7, lr}
- 8003f2a:	af00      	add	r7, sp, #0
+ 80027ac:	b510      	push	{r4, lr}
   /* USER CODE BEGIN DMA1_Channel2_3_IRQn 0 */
 
   /* USER CODE END DMA1_Channel2_3_IRQn 0 */
   HAL_DMA_IRQHandler(&hdma_usart2_rx);
- 8003f2c:	4b03      	ldr	r3, [pc, #12]	@ (8003f3c <DMA1_Channel2_3_IRQHandler+0x14>)
- 8003f2e:	0018      	movs	r0, r3
- 8003f30:	f000 fb0e 	bl	8004550 <HAL_DMA_IRQHandler>
+ 80027ae:	4802      	ldr	r0, [pc, #8]	@ (80027b8 <DMA1_Channel2_3_IRQHandler+0xc>)
+ 80027b0:	f000 fc9c 	bl	80030ec <HAL_DMA_IRQHandler>
   /* USER CODE BEGIN DMA1_Channel2_3_IRQn 1 */
 
   /* USER CODE END DMA1_Channel2_3_IRQn 1 */
 }
- 8003f34:	46c0      	nop			@ (mov r8, r8)
- 8003f36:	46bd      	mov	sp, r7
- 8003f38:	bd80      	pop	{r7, pc}
- 8003f3a:	46c0      	nop			@ (mov r8, r8)
- 8003f3c:	200002f0 	.word	0x200002f0
+ 80027b4:	bd10      	pop	{r4, pc}
+ 80027b6:	46c0      	nop			@ (mov r8, r8)
+ 80027b8:	20000ffc 	.word	0x20000ffc
 
-08003f40 <TIM14_IRQHandler>:
+080027bc <TIM14_IRQHandler>:
 
 /**
   * @brief This function handles TIM14 global interrupt.
   */
 void TIM14_IRQHandler(void)
 {
- 8003f40:	b580      	push	{r7, lr}
- 8003f42:	af00      	add	r7, sp, #0
+ 80027bc:	b510      	push	{r4, lr}
   /* USER CODE BEGIN TIM14_IRQn 0 */
 
   /* USER CODE END TIM14_IRQn 0 */
   HAL_TIM_IRQHandler(&htim14);
- 8003f44:	4b03      	ldr	r3, [pc, #12]	@ (8003f54 <TIM14_IRQHandler+0x14>)
- 8003f46:	0018      	movs	r0, r3
- 8003f48:	f001 fde0 	bl	8005b0c <HAL_TIM_IRQHandler>
+ 80027be:	4802      	ldr	r0, [pc, #8]	@ (80027c8 <TIM14_IRQHandler+0xc>)
+ 80027c0:	f001 fa40 	bl	8003c44 <HAL_TIM_IRQHandler>
   /* USER CODE BEGIN TIM14_IRQn 1 */
 
   /* USER CODE END TIM14_IRQn 1 */
 }
- 8003f4c:	46c0      	nop			@ (mov r8, r8)
- 8003f4e:	46bd      	mov	sp, r7
- 8003f50:	bd80      	pop	{r7, pc}
- 8003f52:	46c0      	nop			@ (mov r8, r8)
- 8003f54:	200000e4 	.word	0x200000e4
+ 80027c4:	bd10      	pop	{r4, pc}
+ 80027c6:	46c0      	nop			@ (mov r8, r8)
+ 80027c8:	20001218 	.word	0x20001218
 
-08003f58 <TIM16_IRQHandler>:
+080027cc <TIM16_IRQHandler>:
 
 /**
   * @brief This function handles TIM16 global interrupt.
   */
 void TIM16_IRQHandler(void)
 {
- 8003f58:	b580      	push	{r7, lr}
- 8003f5a:	af00      	add	r7, sp, #0
+ 80027cc:	b510      	push	{r4, lr}
   /* USER CODE BEGIN TIM16_IRQn 0 */
 
   /* USER CODE END TIM16_IRQn 0 */
   HAL_TIM_IRQHandler(&htim16);
- 8003f5c:	4b03      	ldr	r3, [pc, #12]	@ (8003f6c <TIM16_IRQHandler+0x14>)
- 8003f5e:	0018      	movs	r0, r3
- 8003f60:	f001 fdd4 	bl	8005b0c <HAL_TIM_IRQHandler>
+ 80027ce:	4802      	ldr	r0, [pc, #8]	@ (80027d8 <TIM16_IRQHandler+0xc>)
+ 80027d0:	f001 fa38 	bl	8003c44 <HAL_TIM_IRQHandler>
   /* USER CODE BEGIN TIM16_IRQn 1 */
 
   /* USER CODE END TIM16_IRQn 1 */
 }
- 8003f64:	46c0      	nop			@ (mov r8, r8)
- 8003f66:	46bd      	mov	sp, r7
- 8003f68:	bd80      	pop	{r7, pc}
- 8003f6a:	46c0      	nop			@ (mov r8, r8)
- 8003f6c:	20000130 	.word	0x20000130
+ 80027d4:	bd10      	pop	{r4, pc}
+ 80027d6:	46c0      	nop			@ (mov r8, r8)
+ 80027d8:	200011cc 	.word	0x200011cc
 
-08003f70 <TIM17_IRQHandler>:
+080027dc <TIM17_IRQHandler>:
 
 /**
   * @brief This function handles TIM17 global interrupt.
   */
 void TIM17_IRQHandler(void)
 {
- 8003f70:	b580      	push	{r7, lr}
- 8003f72:	af00      	add	r7, sp, #0
+ 80027dc:	b510      	push	{r4, lr}
   /* USER CODE BEGIN TIM17_IRQn 0 */
 
   /* USER CODE END TIM17_IRQn 0 */
   HAL_TIM_IRQHandler(&htim17);
- 8003f74:	4b03      	ldr	r3, [pc, #12]	@ (8003f84 <TIM17_IRQHandler+0x14>)
- 8003f76:	0018      	movs	r0, r3
- 8003f78:	f001 fdc8 	bl	8005b0c <HAL_TIM_IRQHandler>
+ 80027de:	4802      	ldr	r0, [pc, #8]	@ (80027e8 <TIM17_IRQHandler+0xc>)
+ 80027e0:	f001 fa30 	bl	8003c44 <HAL_TIM_IRQHandler>
   /* USER CODE BEGIN TIM17_IRQn 1 */
 
   /* USER CODE END TIM17_IRQn 1 */
 }
- 8003f7c:	46c0      	nop			@ (mov r8, r8)
- 8003f7e:	46bd      	mov	sp, r7
- 8003f80:	bd80      	pop	{r7, pc}
- 8003f82:	46c0      	nop			@ (mov r8, r8)
- 8003f84:	2000017c 	.word	0x2000017c
+ 80027e4:	bd10      	pop	{r4, pc}
+ 80027e6:	46c0      	nop			@ (mov r8, r8)
+ 80027e8:	20001180 	.word	0x20001180
 
-08003f88 <SystemInit>:
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
+080027ec <USART2_IRQHandler>:
+
+/**
+  * @brief This function handles USART2 interrupt.
   */
-void SystemInit(void)
+void USART2_IRQHandler(void)
 {
- 8003f88:	b580      	push	{r7, lr}
- 8003f8a:	af00      	add	r7, sp, #0
+ 80027ec:	b510      	push	{r4, lr}
+  /* USER CODE BEGIN USART2_IRQn 0 */
+
+  /* USER CODE END USART2_IRQn 0 */
+  HAL_UART_IRQHandler(&huart2);
+ 80027ee:	4802      	ldr	r0, [pc, #8]	@ (80027f8 <USART2_IRQHandler+0xc>)
+ 80027f0:	f001 fed2 	bl	8004598 <HAL_UART_IRQHandler>
+  /* USER CODE BEGIN USART2_IRQn 1 */
+
+  /* USER CODE END USART2_IRQn 1 */
+}
+ 80027f4:	bd10      	pop	{r4, pc}
+ 80027f6:	46c0      	nop			@ (mov r8, r8)
+ 80027f8:	20001058 	.word	0x20001058
+
+080027fc <SystemInit>:
   
   /* Configure the Vector Table location add offset address ------------------*/
 #ifdef VECT_TAB_SRAM
   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 #else
   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
- 8003f8c:	4b03      	ldr	r3, [pc, #12]	@ (8003f9c <SystemInit+0x14>)
- 8003f8e:	2280      	movs	r2, #128	@ 0x80
- 8003f90:	0512      	lsls	r2, r2, #20
- 8003f92:	609a      	str	r2, [r3, #8]
+ 80027fc:	2280      	movs	r2, #128	@ 0x80
+ 80027fe:	4b02      	ldr	r3, [pc, #8]	@ (8002808 <SystemInit+0xc>)
+ 8002800:	0512      	lsls	r2, r2, #20
+ 8002802:	609a      	str	r2, [r3, #8]
 #endif
 }
- 8003f94:	46c0      	nop			@ (mov r8, r8)
- 8003f96:	46bd      	mov	sp, r7
- 8003f98:	bd80      	pop	{r7, pc}
- 8003f9a:	46c0      	nop			@ (mov r8, r8)
- 8003f9c:	e000ed00 	.word	0xe000ed00
+ 8002804:	4770      	bx	lr
+ 8002806:	46c0      	nop			@ (mov r8, r8)
+ 8002808:	e000ed00 	.word	0xe000ed00
 
-08003fa0 <Reset_Handler>:
+0800280c <Reset_Handler>:
 
   .section .text.Reset_Handler
   .weak Reset_Handler
   .type Reset_Handler, %function
 Reset_Handler:
   ldr   r0, =_estack
- 8003fa0:	480d      	ldr	r0, [pc, #52]	@ (8003fd8 <LoopForever+0x2>)
+ 800280c:	480d      	ldr	r0, [pc, #52]	@ (8002844 <LoopForever+0x2>)
   mov   sp, r0          /* set stack pointer */
- 8003fa2:	4685      	mov	sp, r0
+ 800280e:	4685      	mov	sp, r0
 /* Call the clock system initialization function.*/
   bl  SystemInit
- 8003fa4:	f7ff fff0 	bl	8003f88 <SystemInit>
+ 8002810:	f7ff fff4 	bl	80027fc <SystemInit>
 
 /* Copy the data segment initializers from flash to SRAM */
   movs r1, #0
- 8003fa8:	2100      	movs	r1, #0
+ 8002814:	2100      	movs	r1, #0
   b LoopCopyDataInit
- 8003faa:	e003      	b.n	8003fb4 <LoopCopyDataInit>
+ 8002816:	e003      	b.n	8002820 <LoopCopyDataInit>
 
-08003fac <CopyDataInit>:
+08002818 <CopyDataInit>:
 
 CopyDataInit:
   ldr r3, =_sidata
- 8003fac:	4b0b      	ldr	r3, [pc, #44]	@ (8003fdc <LoopForever+0x6>)
+ 8002818:	4b0b      	ldr	r3, [pc, #44]	@ (8002848 <LoopForever+0x6>)
   ldr r3, [r3, r1]
- 8003fae:	585b      	ldr	r3, [r3, r1]
+ 800281a:	585b      	ldr	r3, [r3, r1]
   str r3, [r0, r1]
- 8003fb0:	5043      	str	r3, [r0, r1]
+ 800281c:	5043      	str	r3, [r0, r1]
   adds r1, r1, #4
- 8003fb2:	3104      	adds	r1, #4
+ 800281e:	3104      	adds	r1, #4
 
-08003fb4 <LoopCopyDataInit>:
+08002820 <LoopCopyDataInit>:
 
 LoopCopyDataInit:
   ldr r0, =_sdata
- 8003fb4:	480a      	ldr	r0, [pc, #40]	@ (8003fe0 <LoopForever+0xa>)
+ 8002820:	480a      	ldr	r0, [pc, #40]	@ (800284c <LoopForever+0xa>)
   ldr r3, =_edata
- 8003fb6:	4b0b      	ldr	r3, [pc, #44]	@ (8003fe4 <LoopForever+0xe>)
+ 8002822:	4b0b      	ldr	r3, [pc, #44]	@ (8002850 <LoopForever+0xe>)
   adds r2, r0, r1
- 8003fb8:	1842      	adds	r2, r0, r1
+ 8002824:	1842      	adds	r2, r0, r1
   cmp r2, r3
- 8003fba:	429a      	cmp	r2, r3
+ 8002826:	429a      	cmp	r2, r3
   bcc CopyDataInit
- 8003fbc:	d3f6      	bcc.n	8003fac <CopyDataInit>
+ 8002828:	d3f6      	bcc.n	8002818 <CopyDataInit>
   ldr r2, =_sbss
- 8003fbe:	4a0a      	ldr	r2, [pc, #40]	@ (8003fe8 <LoopForever+0x12>)
+ 800282a:	4a0a      	ldr	r2, [pc, #40]	@ (8002854 <LoopForever+0x12>)
   b LoopFillZerobss
- 8003fc0:	e002      	b.n	8003fc8 <LoopFillZerobss>
+ 800282c:	e002      	b.n	8002834 <LoopFillZerobss>
 
-08003fc2 <FillZerobss>:
+0800282e <FillZerobss>:
 /* Zero fill the bss segment. */
 FillZerobss:
   movs r3, #0
- 8003fc2:	2300      	movs	r3, #0
+ 800282e:	2300      	movs	r3, #0
   str  r3, [r2]
- 8003fc4:	6013      	str	r3, [r2, #0]
+ 8002830:	6013      	str	r3, [r2, #0]
   adds r2, r2, #4
- 8003fc6:	3204      	adds	r2, #4
+ 8002832:	3204      	adds	r2, #4
 
-08003fc8 <LoopFillZerobss>:
+08002834 <LoopFillZerobss>:
 
 
 LoopFillZerobss:
   ldr r3, = _ebss
- 8003fc8:	4b08      	ldr	r3, [pc, #32]	@ (8003fec <LoopForever+0x16>)
+ 8002834:	4b08      	ldr	r3, [pc, #32]	@ (8002858 <LoopForever+0x16>)
   cmp r2, r3
- 8003fca:	429a      	cmp	r2, r3
+ 8002836:	429a      	cmp	r2, r3
   bcc FillZerobss
- 8003fcc:	d3f9      	bcc.n	8003fc2 <FillZerobss>
+ 8002838:	d3f9      	bcc.n	800282e <FillZerobss>
 
 
 /* Call static constructors */
   bl __libc_init_array
- 8003fce:	f003 fe79 	bl	8007cc4 <__libc_init_array>
+ 800283a:	f002 fcaf 	bl	800519c <__libc_init_array>
 /* Call the application's entry point.*/
   bl main
- 8003fd2:	f7fc fd07 	bl	80009e4 <main>
+ 800283e:	f7ff f90b 	bl	8001a58 <main>
 
-08003fd6 <LoopForever>:
+08002842 <LoopForever>:
 
 LoopForever:
     b LoopForever
- 8003fd6:	e7fe      	b.n	8003fd6 <LoopForever>
+ 8002842:	e7fe      	b.n	8002842 <LoopForever>
   ldr   r0, =_estack
- 8003fd8:	20003000 	.word	0x20003000
+ 8002844:	20003000 	.word	0x20003000
   ldr r3, =_sidata
- 8003fdc:	08007e9c 	.word	0x08007e9c
+ 8002848:	080052c8 	.word	0x080052c8
   ldr r0, =_sdata
- 8003fe0:	20000000 	.word	0x20000000
+ 800284c:	20000000 	.word	0x20000000
   ldr r3, =_edata
- 8003fe4:	20000030 	.word	0x20000030
+ 8002850:	20000030 	.word	0x20000030
   ldr r2, =_sbss
- 8003fe8:	20000030 	.word	0x20000030
+ 8002854:	20000030 	.word	0x20000030
   ldr r3, = _ebss
- 8003fec:	200005b0 	.word	0x200005b0
+ 8002858:	20001364 	.word	0x20001364
 
-08003ff0 <ADC1_IRQHandler>:
+0800285c <ADC1_IRQHandler>:
  * @retval : None
 */
     .section .text.Default_Handler,"ax",%progbits
 Default_Handler:
 Infinite_Loop:
   b Infinite_Loop
- 8003ff0:	e7fe      	b.n	8003ff0 <ADC1_IRQHandler>
+ 800285c:	e7fe      	b.n	800285c <ADC1_IRQHandler>
+	...
 
-08003ff2 <HAL_Init>:
-  *         each 1ms in the SysTick_Handler() interrupt handler.
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_Init(void)
-{
- 8003ff2:	b580      	push	{r7, lr}
- 8003ff4:	b082      	sub	sp, #8
- 8003ff6:	af00      	add	r7, sp, #0
-  HAL_StatusTypeDef  status = HAL_OK;
- 8003ff8:	1dfb      	adds	r3, r7, #7
- 8003ffa:	2200      	movs	r2, #0
- 8003ffc:	701a      	strb	r2, [r3, #0]
-#if (PREFETCH_ENABLE != 0U)
-  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
-  /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is HSI) */
-  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
- 8003ffe:	2003      	movs	r0, #3
- 8004000:	f000 f80e 	bl	8004020 <HAL_InitTick>
- 8004004:	1e03      	subs	r3, r0, #0
- 8004006:	d003      	beq.n	8004010 <HAL_Init+0x1e>
-  {
-    status = HAL_ERROR;
- 8004008:	1dfb      	adds	r3, r7, #7
- 800400a:	2201      	movs	r2, #1
- 800400c:	701a      	strb	r2, [r3, #0]
- 800400e:	e001      	b.n	8004014 <HAL_Init+0x22>
-  }
-  else
-  {
-    /* Init the low level hardware */
-    HAL_MspInit();
- 8004010:	f7ff fd22 	bl	8003a58 <HAL_MspInit>
-  }
-
-  /* Return function status */
-  return status;
- 8004014:	1dfb      	adds	r3, r7, #7
- 8004016:	781b      	ldrb	r3, [r3, #0]
-}
- 8004018:	0018      	movs	r0, r3
- 800401a:	46bd      	mov	sp, r7
- 800401c:	b002      	add	sp, #8
- 800401e:	bd80      	pop	{r7, pc}
-
-08004020 <HAL_InitTick>:
+08002860 <HAL_InitTick>:
   *       implementation  in user file.
   * @param TickPriority Tick interrupt priority.
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
 {
- 8004020:	b590      	push	{r4, r7, lr}
- 8004022:	b085      	sub	sp, #20
- 8004024:	af00      	add	r7, sp, #0
- 8004026:	6078      	str	r0, [r7, #4]
+ 8002860:	b570      	push	{r4, r5, r6, lr}
   HAL_StatusTypeDef  status = HAL_OK;
- 8004028:	230f      	movs	r3, #15
- 800402a:	18fb      	adds	r3, r7, r3
- 800402c:	2200      	movs	r2, #0
- 800402e:	701a      	strb	r2, [r3, #0]
 
   if ((uint32_t)uwTickFreq != 0UL)
- 8004030:	4b1d      	ldr	r3, [pc, #116]	@ (80040a8 <HAL_InitTick+0x88>)
- 8004032:	781b      	ldrb	r3, [r3, #0]
- 8004034:	2b00      	cmp	r3, #0
- 8004036:	d02b      	beq.n	8004090 <HAL_InitTick+0x70>
-  {
-    /*Configure the SysTick to have interrupt in 1ms time basis*/
-    if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) == 0U)
- 8004038:	4b1c      	ldr	r3, [pc, #112]	@ (80040ac <HAL_InitTick+0x8c>)
- 800403a:	681c      	ldr	r4, [r3, #0]
- 800403c:	4b1a      	ldr	r3, [pc, #104]	@ (80040a8 <HAL_InitTick+0x88>)
- 800403e:	781b      	ldrb	r3, [r3, #0]
- 8004040:	0019      	movs	r1, r3
- 8004042:	23fa      	movs	r3, #250	@ 0xfa
- 8004044:	0098      	lsls	r0, r3, #2
- 8004046:	f7fc f85f 	bl	8000108 <__udivsi3>
- 800404a:	0003      	movs	r3, r0
- 800404c:	0019      	movs	r1, r3
- 800404e:	0020      	movs	r0, r4
- 8004050:	f7fc f85a 	bl	8000108 <__udivsi3>
- 8004054:	0003      	movs	r3, r0
- 8004056:	0018      	movs	r0, r3
- 8004058:	f000 f95b 	bl	8004312 <HAL_SYSTICK_Config>
- 800405c:	1e03      	subs	r3, r0, #0
- 800405e:	d112      	bne.n	8004086 <HAL_InitTick+0x66>
-    {
-      /* Configure the SysTick IRQ priority */
-      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
- 8004060:	687b      	ldr	r3, [r7, #4]
- 8004062:	2b03      	cmp	r3, #3
- 8004064:	d80a      	bhi.n	800407c <HAL_InitTick+0x5c>
-      {
-        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
- 8004066:	6879      	ldr	r1, [r7, #4]
- 8004068:	2301      	movs	r3, #1
- 800406a:	425b      	negs	r3, r3
- 800406c:	2200      	movs	r2, #0
- 800406e:	0018      	movs	r0, r3
- 8004070:	f000 f92a 	bl	80042c8 <HAL_NVIC_SetPriority>
-        uwTickPrio = TickPriority;
- 8004074:	4b0e      	ldr	r3, [pc, #56]	@ (80040b0 <HAL_InitTick+0x90>)
- 8004076:	687a      	ldr	r2, [r7, #4]
- 8004078:	601a      	str	r2, [r3, #0]
- 800407a:	e00d      	b.n	8004098 <HAL_InitTick+0x78>
-      }
-      else
-      {
+ 8002862:	4b10      	ldr	r3, [pc, #64]	@ (80028a4 <HAL_InitTick+0x44>)
+{
+ 8002864:	0005      	movs	r5, r0
+  if ((uint32_t)uwTickFreq != 0UL)
+ 8002866:	7819      	ldrb	r1, [r3, #0]
+ 8002868:	2900      	cmp	r1, #0
+ 800286a:	d101      	bne.n	8002870 <HAL_InitTick+0x10>
         status = HAL_ERROR;
- 800407c:	230f      	movs	r3, #15
- 800407e:	18fb      	adds	r3, r7, r3
- 8004080:	2201      	movs	r2, #1
- 8004082:	701a      	strb	r2, [r3, #0]
- 8004084:	e008      	b.n	8004098 <HAL_InitTick+0x78>
       }
     }
     else
     {
       status = HAL_ERROR;
- 8004086:	230f      	movs	r3, #15
- 8004088:	18fb      	adds	r3, r7, r3
- 800408a:	2201      	movs	r2, #1
- 800408c:	701a      	strb	r2, [r3, #0]
- 800408e:	e003      	b.n	8004098 <HAL_InitTick+0x78>
-    }
-  }
-  else
-  {
+ 800286c:	2001      	movs	r0, #1
     status = HAL_ERROR;
- 8004090:	230f      	movs	r3, #15
- 8004092:	18fb      	adds	r3, r7, r3
- 8004094:	2201      	movs	r2, #1
- 8004096:	701a      	strb	r2, [r3, #0]
   }
 
   /* Return function status */
   return status;
- 8004098:	230f      	movs	r3, #15
- 800409a:	18fb      	adds	r3, r7, r3
- 800409c:	781b      	ldrb	r3, [r3, #0]
 }
- 800409e:	0018      	movs	r0, r3
- 80040a0:	46bd      	mov	sp, r7
- 80040a2:	b005      	add	sp, #20
- 80040a4:	bd90      	pop	{r4, r7, pc}
- 80040a6:	46c0      	nop			@ (mov r8, r8)
- 80040a8:	2000002c 	.word	0x2000002c
- 80040ac:	20000024 	.word	0x20000024
- 80040b0:	20000028 	.word	0x20000028
+ 800286e:	bd70      	pop	{r4, r5, r6, pc}
+    if (HAL_SYSTICK_Config(SystemCoreClock / (1000UL / (uint32_t)uwTickFreq)) == 0U)
+ 8002870:	20fa      	movs	r0, #250	@ 0xfa
+ 8002872:	0080      	lsls	r0, r0, #2
+ 8002874:	f7fd fc5c 	bl	8000130 <__udivsi3>
+ 8002878:	4c0b      	ldr	r4, [pc, #44]	@ (80028a8 <HAL_InitTick+0x48>)
+ 800287a:	0001      	movs	r1, r0
+ 800287c:	6820      	ldr	r0, [r4, #0]
+ 800287e:	f7fd fc57 	bl	8000130 <__udivsi3>
+ 8002882:	f000 fac5 	bl	8002e10 <HAL_SYSTICK_Config>
+ 8002886:	1e04      	subs	r4, r0, #0
+ 8002888:	d1f0      	bne.n	800286c <HAL_InitTick+0xc>
+      if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ 800288a:	2d03      	cmp	r5, #3
+ 800288c:	d8ee      	bhi.n	800286c <HAL_InitTick+0xc>
+        HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ 800288e:	0002      	movs	r2, r0
+ 8002890:	2001      	movs	r0, #1
+ 8002892:	0029      	movs	r1, r5
+ 8002894:	4240      	negs	r0, r0
+ 8002896:	f000 fa85 	bl	8002da4 <HAL_NVIC_SetPriority>
+        uwTickPrio = TickPriority;
+ 800289a:	4b04      	ldr	r3, [pc, #16]	@ (80028ac <HAL_InitTick+0x4c>)
+ 800289c:	0020      	movs	r0, r4
+ 800289e:	601d      	str	r5, [r3, #0]
+  return status;
+ 80028a0:	e7e5      	b.n	800286e <HAL_InitTick+0xe>
+ 80028a2:	46c0      	nop			@ (mov r8, r8)
+ 80028a4:	20000028 	.word	0x20000028
+ 80028a8:	20000024 	.word	0x20000024
+ 80028ac:	2000002c 	.word	0x2000002c
 
-080040b4 <HAL_IncTick>:
-  * @note This function is declared as __weak to be overwritten in case of other
+080028b0 <HAL_Init>:
+{
+ 80028b0:	b510      	push	{r4, lr}
+  if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ 80028b2:	2003      	movs	r0, #3
+ 80028b4:	f7ff ffd4 	bl	8002860 <HAL_InitTick>
+ 80028b8:	1e04      	subs	r4, r0, #0
+ 80028ba:	d103      	bne.n	80028c4 <HAL_Init+0x14>
+    HAL_MspInit();
+ 80028bc:	f7ff fd92 	bl	80023e4 <HAL_MspInit>
+}
+ 80028c0:	0020      	movs	r0, r4
+ 80028c2:	bd10      	pop	{r4, pc}
+    status = HAL_ERROR;
+ 80028c4:	2401      	movs	r4, #1
+ 80028c6:	e7fb      	b.n	80028c0 <HAL_Init+0x10>
+
+080028c8 <HAL_IncTick>:
   *      implementations in user file.
   * @retval None
   */
 __weak void HAL_IncTick(void)
 {
- 80040b4:	b580      	push	{r7, lr}
- 80040b6:	af00      	add	r7, sp, #0
   uwTick += (uint32_t)uwTickFreq;
- 80040b8:	4b05      	ldr	r3, [pc, #20]	@ (80040d0 <HAL_IncTick+0x1c>)
- 80040ba:	781b      	ldrb	r3, [r3, #0]
- 80040bc:	001a      	movs	r2, r3
- 80040be:	4b05      	ldr	r3, [pc, #20]	@ (80040d4 <HAL_IncTick+0x20>)
- 80040c0:	681b      	ldr	r3, [r3, #0]
- 80040c2:	18d2      	adds	r2, r2, r3
- 80040c4:	4b03      	ldr	r3, [pc, #12]	@ (80040d4 <HAL_IncTick+0x20>)
- 80040c6:	601a      	str	r2, [r3, #0]
+ 80028c8:	4a03      	ldr	r2, [pc, #12]	@ (80028d8 <HAL_IncTick+0x10>)
+ 80028ca:	4b04      	ldr	r3, [pc, #16]	@ (80028dc <HAL_IncTick+0x14>)
+ 80028cc:	6811      	ldr	r1, [r2, #0]
+ 80028ce:	781b      	ldrb	r3, [r3, #0]
+ 80028d0:	185b      	adds	r3, r3, r1
+ 80028d2:	6013      	str	r3, [r2, #0]
 }
- 80040c8:	46c0      	nop			@ (mov r8, r8)
- 80040ca:	46bd      	mov	sp, r7
- 80040cc:	bd80      	pop	{r7, pc}
- 80040ce:	46c0      	nop			@ (mov r8, r8)
- 80040d0:	2000002c 	.word	0x2000002c
- 80040d4:	200005ac 	.word	0x200005ac
+ 80028d4:	4770      	bx	lr
+ 80028d6:	46c0      	nop			@ (mov r8, r8)
+ 80028d8:	20001360 	.word	0x20001360
+ 80028dc:	20000028 	.word	0x20000028
 
-080040d8 <HAL_GetTick>:
-  * @note This function is declared as __weak to be overwritten in case of other
+080028e0 <HAL_GetTick>:
   *       implementations in user file.
   * @retval tick value
   */
 __weak uint32_t HAL_GetTick(void)
 {
- 80040d8:	b580      	push	{r7, lr}
- 80040da:	af00      	add	r7, sp, #0
   return uwTick;
- 80040dc:	4b02      	ldr	r3, [pc, #8]	@ (80040e8 <HAL_GetTick+0x10>)
- 80040de:	681b      	ldr	r3, [r3, #0]
+ 80028e0:	4b01      	ldr	r3, [pc, #4]	@ (80028e8 <HAL_GetTick+0x8>)
+ 80028e2:	6818      	ldr	r0, [r3, #0]
 }
- 80040e0:	0018      	movs	r0, r3
- 80040e2:	46bd      	mov	sp, r7
- 80040e4:	bd80      	pop	{r7, pc}
- 80040e6:	46c0      	nop			@ (mov r8, r8)
- 80040e8:	200005ac 	.word	0x200005ac
+ 80028e4:	4770      	bx	lr
+ 80028e6:	46c0      	nop			@ (mov r8, r8)
+ 80028e8:	20001360 	.word	0x20001360
 
-080040ec <HAL_Delay>:
+080028ec <HAL_Delay>:
   *       implementations in user file.
   * @param Delay  specifies the delay time length, in milliseconds.
   * @retval None
   */
 __weak void HAL_Delay(uint32_t Delay)
 {
- 80040ec:	b580      	push	{r7, lr}
- 80040ee:	b084      	sub	sp, #16
- 80040f0:	af00      	add	r7, sp, #0
- 80040f2:	6078      	str	r0, [r7, #4]
+ 80028ec:	b570      	push	{r4, r5, r6, lr}
+ 80028ee:	0004      	movs	r4, r0
   uint32_t tickstart = HAL_GetTick();
- 80040f4:	f7ff fff0 	bl	80040d8 <HAL_GetTick>
- 80040f8:	0003      	movs	r3, r0
- 80040fa:	60bb      	str	r3, [r7, #8]
+ 80028f0:	f7ff fff6 	bl	80028e0 <HAL_GetTick>
+ 80028f4:	0005      	movs	r5, r0
   uint32_t wait = Delay;
- 80040fc:	687b      	ldr	r3, [r7, #4]
- 80040fe:	60fb      	str	r3, [r7, #12]
 
   /* Add a freq to guarantee minimum wait */
   if (wait < HAL_MAX_DELAY)
- 8004100:	68fb      	ldr	r3, [r7, #12]
- 8004102:	3301      	adds	r3, #1
- 8004104:	d005      	beq.n	8004112 <HAL_Delay+0x26>
+ 80028f6:	1c63      	adds	r3, r4, #1
+ 80028f8:	d002      	beq.n	8002900 <HAL_Delay+0x14>
   {
     wait += (uint32_t)(uwTickFreq);
- 8004106:	4b0a      	ldr	r3, [pc, #40]	@ (8004130 <HAL_Delay+0x44>)
- 8004108:	781b      	ldrb	r3, [r3, #0]
- 800410a:	001a      	movs	r2, r3
- 800410c:	68fb      	ldr	r3, [r7, #12]
- 800410e:	189b      	adds	r3, r3, r2
- 8004110:	60fb      	str	r3, [r7, #12]
+ 80028fa:	4b04      	ldr	r3, [pc, #16]	@ (800290c <HAL_Delay+0x20>)
+ 80028fc:	781b      	ldrb	r3, [r3, #0]
+ 80028fe:	18e4      	adds	r4, r4, r3
   }
 
   while ((HAL_GetTick() - tickstart) < wait)
- 8004112:	46c0      	nop			@ (mov r8, r8)
- 8004114:	f7ff ffe0 	bl	80040d8 <HAL_GetTick>
- 8004118:	0002      	movs	r2, r0
- 800411a:	68bb      	ldr	r3, [r7, #8]
- 800411c:	1ad3      	subs	r3, r2, r3
- 800411e:	68fa      	ldr	r2, [r7, #12]
- 8004120:	429a      	cmp	r2, r3
- 8004122:	d8f7      	bhi.n	8004114 <HAL_Delay+0x28>
+ 8002900:	f7ff ffee 	bl	80028e0 <HAL_GetTick>
+ 8002904:	1b40      	subs	r0, r0, r5
+ 8002906:	42a0      	cmp	r0, r4
+ 8002908:	d3fa      	bcc.n	8002900 <HAL_Delay+0x14>
   {
   }
 }
- 8004124:	46c0      	nop			@ (mov r8, r8)
- 8004126:	46c0      	nop			@ (mov r8, r8)
- 8004128:	46bd      	mov	sp, r7
- 800412a:	b004      	add	sp, #16
- 800412c:	bd80      	pop	{r7, pc}
- 800412e:	46c0      	nop			@ (mov r8, r8)
- 8004130:	2000002c 	.word	0x2000002c
+ 800290a:	bd70      	pop	{r4, r5, r6, pc}
+ 800290c:	20000028 	.word	0x20000028
 
-08004134 <HAL_GetUIDw0>:
-/**
+08002910 <HAL_GetUIDw0>:
   * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
   * @retval Device identifier
   */
 uint32_t HAL_GetUIDw0(void)
 {
- 8004134:	b580      	push	{r7, lr}
- 8004136:	af00      	add	r7, sp, #0
   return (READ_REG(*((uint32_t *)UID_BASE)));
- 8004138:	4b02      	ldr	r3, [pc, #8]	@ (8004144 <HAL_GetUIDw0+0x10>)
- 800413a:	681b      	ldr	r3, [r3, #0]
+ 8002910:	4b01      	ldr	r3, [pc, #4]	@ (8002918 <HAL_GetUIDw0+0x8>)
+ 8002912:	6818      	ldr	r0, [r3, #0]
 }
- 800413c:	0018      	movs	r0, r3
- 800413e:	46bd      	mov	sp, r7
- 8004140:	bd80      	pop	{r7, pc}
- 8004142:	46c0      	nop			@ (mov r8, r8)
- 8004144:	1fff7550 	.word	0x1fff7550
+ 8002914:	4770      	bx	lr
+ 8002916:	46c0      	nop			@ (mov r8, r8)
+ 8002918:	1fff7550 	.word	0x1fff7550
 
-08004148 <HAL_GetUIDw1>:
-/**
+0800291c <HAL_GetUIDw1>:
   * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
   * @retval Device identifier
   */
 uint32_t HAL_GetUIDw1(void)
 {
- 8004148:	b580      	push	{r7, lr}
- 800414a:	af00      	add	r7, sp, #0
   return (READ_REG(*((uint32_t *)(UID_BASE + 4U))));
- 800414c:	4b02      	ldr	r3, [pc, #8]	@ (8004158 <HAL_GetUIDw1+0x10>)
- 800414e:	681b      	ldr	r3, [r3, #0]
+ 800291c:	4b01      	ldr	r3, [pc, #4]	@ (8002924 <HAL_GetUIDw1+0x8>)
+ 800291e:	6818      	ldr	r0, [r3, #0]
 }
- 8004150:	0018      	movs	r0, r3
- 8004152:	46bd      	mov	sp, r7
- 8004154:	bd80      	pop	{r7, pc}
- 8004156:	46c0      	nop			@ (mov r8, r8)
- 8004158:	1fff7554 	.word	0x1fff7554
+ 8002920:	4770      	bx	lr
+ 8002922:	46c0      	nop			@ (mov r8, r8)
+ 8002924:	1fff7554 	.word	0x1fff7554
 
-0800415c <HAL_GetUIDw2>:
-/**
+08002928 <HAL_GetUIDw2>:
   * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
   * @retval Device identifier
   */
 uint32_t HAL_GetUIDw2(void)
 {
- 800415c:	b580      	push	{r7, lr}
- 800415e:	af00      	add	r7, sp, #0
   return (READ_REG(*((uint32_t *)(UID_BASE + 8U))));
- 8004160:	4b02      	ldr	r3, [pc, #8]	@ (800416c <HAL_GetUIDw2+0x10>)
- 8004162:	681b      	ldr	r3, [r3, #0]
+ 8002928:	4b01      	ldr	r3, [pc, #4]	@ (8002930 <HAL_GetUIDw2+0x8>)
+ 800292a:	6818      	ldr	r0, [r3, #0]
 }
- 8004164:	0018      	movs	r0, r3
- 8004166:	46bd      	mov	sp, r7
- 8004168:	bd80      	pop	{r7, pc}
- 800416a:	46c0      	nop			@ (mov r8, r8)
- 800416c:	1fff7558 	.word	0x1fff7558
+ 800292c:	4770      	bx	lr
+ 800292e:	46c0      	nop			@ (mov r8, r8)
+ 8002930:	1fff7558 	.word	0x1fff7558
 
-08004170 <__NVIC_EnableIRQ>:
+08002934 <LL_ADC_REG_IsConversionOngoing>:
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
 {
- 8004170:	b580      	push	{r7, lr}
- 8004172:	b082      	sub	sp, #8
- 8004174:	af00      	add	r7, sp, #0
- 8004176:	0002      	movs	r2, r0
- 8004178:	1dfb      	adds	r3, r7, #7
- 800417a:	701a      	strb	r2, [r3, #0]
-  if ((int32_t)(IRQn) >= 0)
- 800417c:	1dfb      	adds	r3, r7, #7
- 800417e:	781b      	ldrb	r3, [r3, #0]
- 8004180:	2b7f      	cmp	r3, #127	@ 0x7f
- 8004182:	d809      	bhi.n	8004198 <__NVIC_EnableIRQ+0x28>
-    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
- 8004184:	1dfb      	adds	r3, r7, #7
- 8004186:	781b      	ldrb	r3, [r3, #0]
- 8004188:	001a      	movs	r2, r3
- 800418a:	231f      	movs	r3, #31
- 800418c:	401a      	ands	r2, r3
- 800418e:	4b04      	ldr	r3, [pc, #16]	@ (80041a0 <__NVIC_EnableIRQ+0x30>)
- 8004190:	2101      	movs	r1, #1
- 8004192:	4091      	lsls	r1, r2
- 8004194:	000a      	movs	r2, r1
- 8004196:	601a      	str	r2, [r3, #0]
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
+ 8002934:	6880      	ldr	r0, [r0, #8]
+ 8002936:	0740      	lsls	r0, r0, #29
+ 8002938:	0fc0      	lsrs	r0, r0, #31
 }
- 8004198:	46c0      	nop			@ (mov r8, r8)
- 800419a:	46bd      	mov	sp, r7
- 800419c:	b002      	add	sp, #8
- 800419e:	bd80      	pop	{r7, pc}
- 80041a0:	e000e100 	.word	0xe000e100
+ 800293a:	4770      	bx	lr
 
-080041a4 <__NVIC_SetPriority>:
+0800293c <HAL_ADC_Init>:
 {
- 80041a4:	b590      	push	{r4, r7, lr}
- 80041a6:	b083      	sub	sp, #12
- 80041a8:	af00      	add	r7, sp, #0
- 80041aa:	0002      	movs	r2, r0
- 80041ac:	6039      	str	r1, [r7, #0]
- 80041ae:	1dfb      	adds	r3, r7, #7
- 80041b0:	701a      	strb	r2, [r3, #0]
-  if ((int32_t)(IRQn) >= 0)
- 80041b2:	1dfb      	adds	r3, r7, #7
- 80041b4:	781b      	ldrb	r3, [r3, #0]
- 80041b6:	2b7f      	cmp	r3, #127	@ 0x7f
- 80041b8:	d828      	bhi.n	800420c <__NVIC_SetPriority+0x68>
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 80041ba:	4a2f      	ldr	r2, [pc, #188]	@ (8004278 <__NVIC_SetPriority+0xd4>)
- 80041bc:	1dfb      	adds	r3, r7, #7
- 80041be:	781b      	ldrb	r3, [r3, #0]
- 80041c0:	b25b      	sxtb	r3, r3
- 80041c2:	089b      	lsrs	r3, r3, #2
- 80041c4:	33c0      	adds	r3, #192	@ 0xc0
- 80041c6:	009b      	lsls	r3, r3, #2
- 80041c8:	589b      	ldr	r3, [r3, r2]
- 80041ca:	1dfa      	adds	r2, r7, #7
- 80041cc:	7812      	ldrb	r2, [r2, #0]
- 80041ce:	0011      	movs	r1, r2
- 80041d0:	2203      	movs	r2, #3
- 80041d2:	400a      	ands	r2, r1
- 80041d4:	00d2      	lsls	r2, r2, #3
- 80041d6:	21ff      	movs	r1, #255	@ 0xff
- 80041d8:	4091      	lsls	r1, r2
- 80041da:	000a      	movs	r2, r1
- 80041dc:	43d2      	mvns	r2, r2
- 80041de:	401a      	ands	r2, r3
- 80041e0:	0011      	movs	r1, r2
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- 80041e2:	683b      	ldr	r3, [r7, #0]
- 80041e4:	019b      	lsls	r3, r3, #6
- 80041e6:	22ff      	movs	r2, #255	@ 0xff
- 80041e8:	401a      	ands	r2, r3
- 80041ea:	1dfb      	adds	r3, r7, #7
- 80041ec:	781b      	ldrb	r3, [r3, #0]
- 80041ee:	0018      	movs	r0, r3
- 80041f0:	2303      	movs	r3, #3
- 80041f2:	4003      	ands	r3, r0
- 80041f4:	00db      	lsls	r3, r3, #3
- 80041f6:	409a      	lsls	r2, r3
-    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 80041f8:	481f      	ldr	r0, [pc, #124]	@ (8004278 <__NVIC_SetPriority+0xd4>)
- 80041fa:	1dfb      	adds	r3, r7, #7
- 80041fc:	781b      	ldrb	r3, [r3, #0]
- 80041fe:	b25b      	sxtb	r3, r3
- 8004200:	089b      	lsrs	r3, r3, #2
- 8004202:	430a      	orrs	r2, r1
- 8004204:	33c0      	adds	r3, #192	@ 0xc0
- 8004206:	009b      	lsls	r3, r3, #2
- 8004208:	501a      	str	r2, [r3, r0]
-}
- 800420a:	e031      	b.n	8004270 <__NVIC_SetPriority+0xcc>
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 800420c:	4a1b      	ldr	r2, [pc, #108]	@ (800427c <__NVIC_SetPriority+0xd8>)
- 800420e:	1dfb      	adds	r3, r7, #7
- 8004210:	781b      	ldrb	r3, [r3, #0]
- 8004212:	0019      	movs	r1, r3
- 8004214:	230f      	movs	r3, #15
- 8004216:	400b      	ands	r3, r1
- 8004218:	3b08      	subs	r3, #8
- 800421a:	089b      	lsrs	r3, r3, #2
- 800421c:	3306      	adds	r3, #6
- 800421e:	009b      	lsls	r3, r3, #2
- 8004220:	18d3      	adds	r3, r2, r3
- 8004222:	3304      	adds	r3, #4
- 8004224:	681b      	ldr	r3, [r3, #0]
- 8004226:	1dfa      	adds	r2, r7, #7
- 8004228:	7812      	ldrb	r2, [r2, #0]
- 800422a:	0011      	movs	r1, r2
- 800422c:	2203      	movs	r2, #3
- 800422e:	400a      	ands	r2, r1
- 8004230:	00d2      	lsls	r2, r2, #3
- 8004232:	21ff      	movs	r1, #255	@ 0xff
- 8004234:	4091      	lsls	r1, r2
- 8004236:	000a      	movs	r2, r1
- 8004238:	43d2      	mvns	r2, r2
- 800423a:	401a      	ands	r2, r3
- 800423c:	0011      	movs	r1, r2
-       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
- 800423e:	683b      	ldr	r3, [r7, #0]
- 8004240:	019b      	lsls	r3, r3, #6
- 8004242:	22ff      	movs	r2, #255	@ 0xff
- 8004244:	401a      	ands	r2, r3
- 8004246:	1dfb      	adds	r3, r7, #7
- 8004248:	781b      	ldrb	r3, [r3, #0]
- 800424a:	0018      	movs	r0, r3
- 800424c:	2303      	movs	r3, #3
- 800424e:	4003      	ands	r3, r0
- 8004250:	00db      	lsls	r3, r3, #3
- 8004252:	409a      	lsls	r2, r3
-    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
- 8004254:	4809      	ldr	r0, [pc, #36]	@ (800427c <__NVIC_SetPriority+0xd8>)
- 8004256:	1dfb      	adds	r3, r7, #7
- 8004258:	781b      	ldrb	r3, [r3, #0]
- 800425a:	001c      	movs	r4, r3
- 800425c:	230f      	movs	r3, #15
- 800425e:	4023      	ands	r3, r4
- 8004260:	3b08      	subs	r3, #8
- 8004262:	089b      	lsrs	r3, r3, #2
- 8004264:	430a      	orrs	r2, r1
- 8004266:	3306      	adds	r3, #6
- 8004268:	009b      	lsls	r3, r3, #2
- 800426a:	18c3      	adds	r3, r0, r3
- 800426c:	3304      	adds	r3, #4
- 800426e:	601a      	str	r2, [r3, #0]
-}
- 8004270:	46c0      	nop			@ (mov r8, r8)
- 8004272:	46bd      	mov	sp, r7
- 8004274:	b003      	add	sp, #12
- 8004276:	bd90      	pop	{r4, r7, pc}
- 8004278:	e000e100 	.word	0xe000e100
- 800427c:	e000ed00 	.word	0xe000ed00
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmpCFGR1 = 0UL;
+  uint32_t tmpCFGR2 = 0UL;
+  uint32_t tmp_adc_reg_is_conversion_on_going;
+  __IO uint32_t wait_loop_index = 0UL;
+ 800293c:	2300      	movs	r3, #0
+{
+ 800293e:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 8002940:	b085      	sub	sp, #20
+ 8002942:	0004      	movs	r4, r0
+  __IO uint32_t wait_loop_index = 0UL;
+ 8002944:	9303      	str	r3, [sp, #12]
 
-08004280 <SysTick_Config>:
-  \note    When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
-           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
-           must contain a vendor-specific implementation of this function.
- */
-__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
-{
- 8004280:	b580      	push	{r7, lr}
- 8004282:	b082      	sub	sp, #8
- 8004284:	af00      	add	r7, sp, #0
- 8004286:	6078      	str	r0, [r7, #4]
-  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
- 8004288:	687b      	ldr	r3, [r7, #4]
- 800428a:	1e5a      	subs	r2, r3, #1
- 800428c:	2380      	movs	r3, #128	@ 0x80
- 800428e:	045b      	lsls	r3, r3, #17
- 8004290:	429a      	cmp	r2, r3
- 8004292:	d301      	bcc.n	8004298 <SysTick_Config+0x18>
-  {
-    return (1UL);                                                   /* Reload value impossible */
- 8004294:	2301      	movs	r3, #1
- 8004296:	e010      	b.n	80042ba <SysTick_Config+0x3a>
+  /* Check ADC handle */
+  if (hadc == NULL)
+ 8002946:	4298      	cmp	r0, r3
+ 8002948:	d100      	bne.n	800294c <HAL_ADC_Init+0x10>
+ 800294a:	e0ef      	b.n	8002b2c <HAL_ADC_Init+0x1f0>
+  /* continuous mode is disabled.                                             */
+  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+
+  /* Actions performed only if ADC is coming from state reset:                */
+  /* - Initialization of ADC MSP                                              */
+  if (hadc->State == HAL_ADC_STATE_RESET)
+ 800294c:	6d85      	ldr	r5, [r0, #88]	@ 0x58
+ 800294e:	429d      	cmp	r5, r3
+ 8002950:	d105      	bne.n	800295e <HAL_ADC_Init+0x22>
+
+    /* Init the low level hardware */
+    hadc->MspInitCallback(hadc);
+#else
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+ 8002952:	f7ff fd5f 	bl	8002414 <HAL_ADC_MspInit>
+
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+
+    /* Initialize Lock */
+    hadc->Lock = HAL_UNLOCKED;
+ 8002956:	0023      	movs	r3, r4
+ 8002958:	3354      	adds	r3, #84	@ 0x54
+    ADC_CLEAR_ERRORCODE(hadc);
+ 800295a:	65e5      	str	r5, [r4, #92]	@ 0x5c
+    hadc->Lock = HAL_UNLOCKED;
+ 800295c:	701d      	strb	r5, [r3, #0]
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
+ 800295e:	2380      	movs	r3, #128	@ 0x80
   }
 
-  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
- 8004298:	4b0a      	ldr	r3, [pc, #40]	@ (80042c4 <SysTick_Config+0x44>)
- 800429a:	687a      	ldr	r2, [r7, #4]
- 800429c:	3a01      	subs	r2, #1
- 800429e:	605a      	str	r2, [r3, #4]
-  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
- 80042a0:	2301      	movs	r3, #1
- 80042a2:	425b      	negs	r3, r3
- 80042a4:	2103      	movs	r1, #3
- 80042a6:	0018      	movs	r0, r3
- 80042a8:	f7ff ff7c 	bl	80041a4 <__NVIC_SetPriority>
-  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
- 80042ac:	4b05      	ldr	r3, [pc, #20]	@ (80042c4 <SysTick_Config+0x44>)
- 80042ae:	2200      	movs	r2, #0
- 80042b0:	609a      	str	r2, [r3, #8]
-  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
- 80042b2:	4b04      	ldr	r3, [pc, #16]	@ (80042c4 <SysTick_Config+0x44>)
- 80042b4:	2207      	movs	r2, #7
- 80042b6:	601a      	str	r2, [r3, #0]
-                   SysTick_CTRL_TICKINT_Msk   |
-                   SysTick_CTRL_ENABLE_Msk;                         /* Enable SysTick IRQ and SysTick Timer */
-  return (0UL);                                                     /* Function successful */
- 80042b8:	2300      	movs	r3, #0
-}
- 80042ba:	0018      	movs	r0, r3
- 80042bc:	46bd      	mov	sp, r7
- 80042be:	b002      	add	sp, #8
- 80042c0:	bd80      	pop	{r7, pc}
- 80042c2:	46c0      	nop			@ (mov r8, r8)
- 80042c4:	e000e010 	.word	0xe000e010
+  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+ 8002960:	6825      	ldr	r5, [r4, #0]
+ 8002962:	055b      	lsls	r3, r3, #21
+ 8002964:	68aa      	ldr	r2, [r5, #8]
+ 8002966:	421a      	tst	r2, r3
+ 8002968:	d100      	bne.n	800296c <HAL_ADC_Init+0x30>
+ 800296a:	e0a7      	b.n	8002abc <HAL_ADC_Init+0x180>
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 800296c:	2200      	movs	r2, #0
+ 800296e:	68ab      	ldr	r3, [r5, #8]
+ 8002970:	9201      	str	r2, [sp, #4]
+ 8002972:	00db      	lsls	r3, r3, #3
+ 8002974:	d408      	bmi.n	8002988 <HAL_ADC_Init+0x4c>
+  /* or not ADC is coming from state reset (if any potential problem of       */
+  /* clocking, voltage regulator would not be enabled).                       */
+  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 8002976:	2310      	movs	r3, #16
 
-080042c8 <HAL_NVIC_SetPriority>:
+    /* Set ADC error code to ADC peripheral internal error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 8002978:	2601      	movs	r6, #1
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 800297a:	6da2      	ldr	r2, [r4, #88]	@ 0x58
+
+    tmp_hal_status = HAL_ERROR;
+ 800297c:	9601      	str	r6, [sp, #4]
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 800297e:	4313      	orrs	r3, r2
+ 8002980:	65a3      	str	r3, [r4, #88]	@ 0x58
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 8002982:	6de3      	ldr	r3, [r4, #92]	@ 0x5c
+ 8002984:	4333      	orrs	r3, r6
+ 8002986:	65e3      	str	r3, [r4, #92]	@ 0x5c
+
+  /* Configuration of ADC parameters if previous preliminary actions are      */
+  /* correctly completed and if there is no conversion on going on regular    */
+  /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
+  /* called to update a parameter on the fly).                                */
+  tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+ 8002988:	0028      	movs	r0, r5
+ 800298a:	f7ff ffd3 	bl	8002934 <LL_ADC_REG_IsConversionOngoing>
+
+  if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+ 800298e:	2210      	movs	r2, #16
+ 8002990:	6da3      	ldr	r3, [r4, #88]	@ 0x58
+ 8002992:	4013      	ands	r3, r2
+ 8002994:	4303      	orrs	r3, r0
+ 8002996:	d000      	beq.n	800299a <HAL_ADC_Init+0x5e>
+ 8002998:	e0cb      	b.n	8002b32 <HAL_ADC_Init+0x1f6>
+      && (tmp_adc_reg_is_conversion_on_going == 0UL)
+     )
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+ 800299a:	6da2      	ldr	r2, [r4, #88]	@ 0x58
+ 800299c:	4b67      	ldr	r3, [pc, #412]	@ (8002b3c <HAL_ADC_Init+0x200>)
+                   ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)      |
+                   ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff)   |
+                   ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)  |
+                   ADC_CFGR1_OVERRUN(hadc->Init.Overrun)                          |
+                   hadc->Init.DataAlign                                           |
+                   ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode)                     |
+ 800299e:	6920      	ldr	r0, [r4, #16]
+    ADC_STATE_CLR_SET(hadc->State,
+ 80029a0:	401a      	ands	r2, r3
+ 80029a2:	3306      	adds	r3, #6
+ 80029a4:	33ff      	adds	r3, #255	@ 0xff
+ 80029a6:	4313      	orrs	r3, r2
+ 80029a8:	65a3      	str	r3, [r4, #88]	@ 0x58
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
+ 80029aa:	68ab      	ldr	r3, [r5, #8]
+ 80029ac:	07db      	lsls	r3, r3, #31
+ 80029ae:	d461      	bmi.n	8002a74 <HAL_ADC_Init+0x138>
+                   ADC_CFGR1_OVERRUN(hadc->Init.Overrun)                          |
+ 80029b0:	6b27      	ldr	r7, [r4, #48]	@ 0x30
+ 80029b2:	68e1      	ldr	r1, [r4, #12]
+ 80029b4:	1e7b      	subs	r3, r7, #1
+ 80029b6:	419f      	sbcs	r7, r3
+ 80029b8:	68a3      	ldr	r3, [r4, #8]
+                   ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)  |
+ 80029ba:	7ea2      	ldrb	r2, [r4, #26]
+ 80029bc:	430b      	orrs	r3, r1
+                   ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)      |
+ 80029be:	7e21      	ldrb	r1, [r4, #24]
+                   ADC_CFGR1_OVERRUN(hadc->Init.Overrun)                          |
+ 80029c0:	033f      	lsls	r7, r7, #12
+                   ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)      |
+ 80029c2:	0389      	lsls	r1, r1, #14
+ 80029c4:	430b      	orrs	r3, r1
+                   ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff)   |
+ 80029c6:	7e61      	ldrb	r1, [r4, #25]
+ 80029c8:	03c9      	lsls	r1, r1, #15
+ 80029ca:	430b      	orrs	r3, r1
+                   ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)  |
+ 80029cc:	0351      	lsls	r1, r2, #13
+ 80029ce:	430b      	orrs	r3, r1
+ 80029d0:	469c      	mov	ip, r3
+                   ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode)                     |
+ 80029d2:	2800      	cmp	r0, #0
+ 80029d4:	db00      	blt.n	80029d8 <HAL_ADC_Init+0x9c>
+ 80029d6:	e085      	b.n	8002ae4 <HAL_ADC_Init+0x1a8>
+ 80029d8:	0041      	lsls	r1, r0, #1
+ 80029da:	0849      	lsrs	r1, r1, #1
+                   ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+ 80029dc:	0023      	movs	r3, r4
+                   ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode)                     |
+ 80029de:	4666      	mov	r6, ip
+                   ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+ 80029e0:	332c      	adds	r3, #44	@ 0x2c
+ 80029e2:	781b      	ldrb	r3, [r3, #0]
+ 80029e4:	005b      	lsls	r3, r3, #1
+                   ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode)                     |
+ 80029e6:	4333      	orrs	r3, r6
+ 80029e8:	433b      	orrs	r3, r7
+ 80029ea:	430b      	orrs	r3, r1
+
+      /* Update setting of discontinuous mode only if continuous mode is disabled */
+      if (hadc->Init.DiscontinuousConvMode == ENABLE)
+ 80029ec:	1c61      	adds	r1, r4, #1
+ 80029ee:	7fc9      	ldrb	r1, [r1, #31]
+ 80029f0:	2901      	cmp	r1, #1
+ 80029f2:	d105      	bne.n	8002a00 <HAL_ADC_Init+0xc4>
+      {
+        if (hadc->Init.ContinuousConvMode == DISABLE)
+ 80029f4:	2a00      	cmp	r2, #0
+ 80029f6:	d000      	beq.n	80029fa <HAL_ADC_Init+0xbe>
+ 80029f8:	e077      	b.n	8002aea <HAL_ADC_Init+0x1ae>
+        {
+          /* Enable the selected ADC group regular discontinuous mode */
+          tmpCFGR1 |= ADC_CFGR1_DISCEN;
+ 80029fa:	2280      	movs	r2, #128	@ 0x80
+ 80029fc:	0252      	lsls	r2, r2, #9
+ 80029fe:	4313      	orrs	r3, r2
+      /* Enable external trigger if trigger selection is different of software  */
+      /* start.                                                                 */
+      /* Note: This configuration keeps the hardware feature of parameter       */
+      /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+      /*       software start.                                                  */
+      if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+ 8002a00:	6a62      	ldr	r2, [r4, #36]	@ 0x24
+ 8002a02:	2a00      	cmp	r2, #0
+ 8002a04:	d005      	beq.n	8002a12 <HAL_ADC_Init+0xd6>
+      {
+        tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
+ 8002a06:	21e0      	movs	r1, #224	@ 0xe0
+ 8002a08:	0049      	lsls	r1, r1, #1
+ 8002a0a:	400a      	ands	r2, r1
+ 8002a0c:	6aa1      	ldr	r1, [r4, #40]	@ 0x28
+ 8002a0e:	430a      	orrs	r2, r1
+ 8002a10:	4313      	orrs	r3, r2
+                     hadc->Init.ExternalTrigConvEdge);
+      }
+
+      /* Update ADC configuration register with previous settings */
+      MODIFY_REG(hadc->Instance->CFGR1,
+ 8002a12:	68ea      	ldr	r2, [r5, #12]
+ 8002a14:	494a      	ldr	r1, [pc, #296]	@ (8002b40 <HAL_ADC_Init+0x204>)
+ 8002a16:	400a      	ands	r2, r1
+ 8002a18:	4313      	orrs	r3, r2
+ 8002a1a:	60eb      	str	r3, [r5, #12]
+
+      tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
+                   hadc->Init.TriggerFrequencyMode
+                  );
+
+      if (hadc->Init.OversamplingMode == ENABLE)
+ 8002a1c:	0023      	movs	r3, r4
+      tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
+ 8002a1e:	6862      	ldr	r2, [r4, #4]
+      if (hadc->Init.OversamplingMode == ENABLE)
+ 8002a20:	333c      	adds	r3, #60	@ 0x3c
+      tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
+ 8002a22:	6ce1      	ldr	r1, [r4, #76]	@ 0x4c
+      if (hadc->Init.OversamplingMode == ENABLE)
+ 8002a24:	781b      	ldrb	r3, [r3, #0]
+      tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
+ 8002a26:	0f97      	lsrs	r7, r2, #30
+ 8002a28:	07bf      	lsls	r7, r7, #30
+      if (hadc->Init.OversamplingMode == ENABLE)
+ 8002a2a:	469c      	mov	ip, r3
+      tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
+ 8002a2c:	4339      	orrs	r1, r7
+      if (hadc->Init.OversamplingMode == ENABLE)
+ 8002a2e:	2b01      	cmp	r3, #1
+ 8002a30:	d108      	bne.n	8002a44 <HAL_ADC_Init+0x108>
+      {
+        tmpCFGR2 |= (ADC_CFGR2_OVSE |
+ 8002a32:	6c23      	ldr	r3, [r4, #64]	@ 0x40
+ 8002a34:	6c66      	ldr	r6, [r4, #68]	@ 0x44
+ 8002a36:	4333      	orrs	r3, r6
+ 8002a38:	430b      	orrs	r3, r1
+ 8002a3a:	6ca1      	ldr	r1, [r4, #72]	@ 0x48
+ 8002a3c:	430b      	orrs	r3, r1
+ 8002a3e:	4661      	mov	r1, ip
+ 8002a40:	433b      	orrs	r3, r7
+ 8002a42:	4319      	orrs	r1, r3
+                     hadc->Init.Oversampling.RightBitShift |
+                     hadc->Init.Oversampling.TriggeredMode
+                    );
+      }
+
+      MODIFY_REG(hadc->Instance->CFGR2,
+ 8002a44:	692b      	ldr	r3, [r5, #16]
+ 8002a46:	4f3f      	ldr	r7, [pc, #252]	@ (8002b44 <HAL_ADC_Init+0x208>)
+ 8002a48:	403b      	ands	r3, r7
+ 8002a4a:	430b      	orrs	r3, r1
+                 ADC_CFGR2_TOVS,
+                 tmpCFGR2);
+
+      /* Configuration of ADC clock mode: asynchronous clock source           */
+      /* with selectable prescaler.                                           */
+      if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
+ 8002a4c:	2180      	movs	r1, #128	@ 0x80
+      MODIFY_REG(hadc->Instance->CFGR2,
+ 8002a4e:	612b      	str	r3, [r5, #16]
+      if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
+ 8002a50:	0053      	lsls	r3, r2, #1
+ 8002a52:	085b      	lsrs	r3, r3, #1
+ 8002a54:	05c9      	lsls	r1, r1, #23
+ 8002a56:	428b      	cmp	r3, r1
+ 8002a58:	d00c      	beq.n	8002a74 <HAL_ADC_Init+0x138>
+          ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
+ 8002a5a:	2380      	movs	r3, #128	@ 0x80
+ 8002a5c:	061b      	lsls	r3, r3, #24
+ 8002a5e:	429a      	cmp	r2, r3
+ 8002a60:	d008      	beq.n	8002a74 <HAL_ADC_Init+0x138>
+          ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4))
+      {
+        MODIFY_REG(ADC1_COMMON->CCR,
+ 8002a62:	4939      	ldr	r1, [pc, #228]	@ (8002b48 <HAL_ADC_Init+0x20c>)
+ 8002a64:	4f39      	ldr	r7, [pc, #228]	@ (8002b4c <HAL_ADC_Init+0x210>)
+ 8002a66:	680b      	ldr	r3, [r1, #0]
+ 8002a68:	403b      	ands	r3, r7
+ 8002a6a:	27f0      	movs	r7, #240	@ 0xf0
+ 8002a6c:	03bf      	lsls	r7, r7, #14
+ 8002a6e:	403a      	ands	r2, r7
+ 8002a70:	4313      	orrs	r3, r2
+ 8002a72:	600b      	str	r3, [r1, #0]
+  MODIFY_REG(ADCx->SMPR,
+ 8002a74:	2107      	movs	r1, #7
+ 8002a76:	2770      	movs	r7, #112	@ 0x70
+ 8002a78:	696b      	ldr	r3, [r5, #20]
+                   hadc->Init.ClockPrescaler & ADC_CCR_PRESC);
+      }
+    }
+
+    /* Channel sampling time configuration */
+    LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
+ 8002a7a:	6b62      	ldr	r2, [r4, #52]	@ 0x34
+ 8002a7c:	438b      	bics	r3, r1
+ 8002a7e:	4313      	orrs	r3, r2
+ 8002a80:	616b      	str	r3, [r5, #20]
+ 8002a82:	6969      	ldr	r1, [r5, #20]
+ 8002a84:	6ba3      	ldr	r3, [r4, #56]	@ 0x38
+ 8002a86:	43b9      	bics	r1, r7
+ 8002a88:	011b      	lsls	r3, r3, #4
+ 8002a8a:	430b      	orrs	r3, r1
+ 8002a8c:	616b      	str	r3, [r5, #20]
+    /*   emulated by software for alignment over all STM32 devices.           */
+    /* - if scan mode is enabled, regular channels sequence length is set to  */
+    /*   parameter "NbrOfConversion".                                         */
+    /*   Channels must be configured into each rank using function            */
+    /*   "HAL_ADC_ConfigChannel()".                                           */
+    if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
+ 8002a8e:	2800      	cmp	r0, #0
+ 8002a90:	d133      	bne.n	8002afa <HAL_ADC_Init+0x1be>
+    {
+      /* Set sequencer scan length by clearing ranks above rank 1             */
+      /* and do not modify rank 1 value.                                      */
+      SET_BIT(hadc->Instance->CHSELR,
+ 8002a92:	2310      	movs	r3, #16
+ 8002a94:	6aa9      	ldr	r1, [r5, #40]	@ 0x28
+ 8002a96:	425b      	negs	r3, r3
+      /*          therefore after the first call of "HAL_ADC_Init()",       */
+      /*          each rank corresponding to parameter "NbrOfConversion"    */
+      /*          must be set using "HAL_ADC_ConfigChannel()".              */
+      /*  - Set sequencer scan length by clearing ranks above maximum rank  */
+      /*    and do not modify other ranks value.                            */
+      MODIFY_REG(hadc->Instance->CHSELR,
+ 8002a98:	430b      	orrs	r3, r1
+ 8002a9a:	62ab      	str	r3, [r5, #40]	@ 0x28
+  return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
+ 8002a9c:	2107      	movs	r1, #7
+ 8002a9e:	696b      	ldr	r3, [r5, #20]
+ 8002aa0:	400b      	ands	r3, r1
+    {
+      /* Nothing to do */
+    }
+    /* Check back that ADC registers have effectively been configured to      */
+    /* ensure of no potential problem of ADC core peripheral clocking.        */
+    if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
+ 8002aa2:	429a      	cmp	r2, r3
+ 8002aa4:	d138      	bne.n	8002b18 <HAL_ADC_Init+0x1dc>
+        == hadc->Init.SamplingTimeCommon1)
+    {
+      /* Set ADC error code to none */
+      ADC_CLEAR_ERRORCODE(hadc);
+ 8002aa6:	2300      	movs	r3, #0
+ 8002aa8:	65e3      	str	r3, [r4, #92]	@ 0x5c
+
+      /* Set the ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+ 8002aaa:	6da2      	ldr	r2, [r4, #88]	@ 0x58
+ 8002aac:	3303      	adds	r3, #3
+ 8002aae:	439a      	bics	r2, r3
+ 8002ab0:	3b02      	subs	r3, #2
+ 8002ab2:	4313      	orrs	r3, r2
+ 8002ab4:	65a3      	str	r3, [r4, #88]	@ 0x58
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+ 8002ab6:	9801      	ldr	r0, [sp, #4]
+ 8002ab8:	b005      	add	sp, #20
+ 8002aba:	bdf0      	pop	{r4, r5, r6, r7, pc}
+  MODIFY_REG(ADCx->CR,
+ 8002abc:	68aa      	ldr	r2, [r5, #8]
+ 8002abe:	4924      	ldr	r1, [pc, #144]	@ (8002b50 <HAL_ADC_Init+0x214>)
+ 8002ac0:	400a      	ands	r2, r1
+ 8002ac2:	4313      	orrs	r3, r2
+ 8002ac4:	60ab      	str	r3, [r5, #8]
+    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+ 8002ac6:	4b23      	ldr	r3, [pc, #140]	@ (8002b54 <HAL_ADC_Init+0x218>)
+ 8002ac8:	4923      	ldr	r1, [pc, #140]	@ (8002b58 <HAL_ADC_Init+0x21c>)
+ 8002aca:	6818      	ldr	r0, [r3, #0]
+ 8002acc:	f7fd fb30 	bl	8000130 <__udivsi3>
+ 8002ad0:	0040      	lsls	r0, r0, #1
+ 8002ad2:	9003      	str	r0, [sp, #12]
+    while (wait_loop_index != 0UL)
+ 8002ad4:	9b03      	ldr	r3, [sp, #12]
+ 8002ad6:	2b00      	cmp	r3, #0
+ 8002ad8:	d100      	bne.n	8002adc <HAL_ADC_Init+0x1a0>
+ 8002ada:	e747      	b.n	800296c <HAL_ADC_Init+0x30>
+      wait_loop_index--;
+ 8002adc:	9b03      	ldr	r3, [sp, #12]
+ 8002ade:	3b01      	subs	r3, #1
+ 8002ae0:	9303      	str	r3, [sp, #12]
+ 8002ae2:	e7f7      	b.n	8002ad4 <HAL_ADC_Init+0x198>
+                   ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode)                     |
+ 8002ae4:	2180      	movs	r1, #128	@ 0x80
+ 8002ae6:	0389      	lsls	r1, r1, #14
+ 8002ae8:	e778      	b.n	80029dc <HAL_ADC_Init+0xa0>
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 8002aea:	2220      	movs	r2, #32
+ 8002aec:	6da7      	ldr	r7, [r4, #88]	@ 0x58
+ 8002aee:	433a      	orrs	r2, r7
+ 8002af0:	65a2      	str	r2, [r4, #88]	@ 0x58
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 8002af2:	6de2      	ldr	r2, [r4, #92]	@ 0x5c
+ 8002af4:	4311      	orrs	r1, r2
+ 8002af6:	65e1      	str	r1, [r4, #92]	@ 0x5c
+ 8002af8:	e782      	b.n	8002a00 <HAL_ADC_Init+0xc4>
+    else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+ 8002afa:	2380      	movs	r3, #128	@ 0x80
+ 8002afc:	039b      	lsls	r3, r3, #14
+ 8002afe:	4298      	cmp	r0, r3
+ 8002b00:	d1cc      	bne.n	8002a9c <HAL_ADC_Init+0x160>
+      MODIFY_REG(hadc->Instance->CHSELR,
+ 8002b02:	211c      	movs	r1, #28
+ 8002b04:	6aab      	ldr	r3, [r5, #40]	@ 0x28
+ 8002b06:	69e3      	ldr	r3, [r4, #28]
+ 8002b08:	3b01      	subs	r3, #1
+ 8002b0a:	009b      	lsls	r3, r3, #2
+ 8002b0c:	400b      	ands	r3, r1
+ 8002b0e:	392c      	subs	r1, #44	@ 0x2c
+ 8002b10:	4099      	lsls	r1, r3
+ 8002b12:	000b      	movs	r3, r1
+ 8002b14:	6e21      	ldr	r1, [r4, #96]	@ 0x60
+ 8002b16:	e7bf      	b.n	8002a98 <HAL_ADC_Init+0x15c>
+      ADC_STATE_CLR_SET(hadc->State,
+ 8002b18:	2312      	movs	r3, #18
+ 8002b1a:	6da2      	ldr	r2, [r4, #88]	@ 0x58
+ 8002b1c:	439a      	bics	r2, r3
+ 8002b1e:	3b02      	subs	r3, #2
+ 8002b20:	4313      	orrs	r3, r2
+ 8002b22:	65a3      	str	r3, [r4, #88]	@ 0x58
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+ 8002b24:	2301      	movs	r3, #1
+ 8002b26:	6de2      	ldr	r2, [r4, #92]	@ 0x5c
+ 8002b28:	4313      	orrs	r3, r2
+ 8002b2a:	65e3      	str	r3, [r4, #92]	@ 0x5c
+    return HAL_ERROR;
+ 8002b2c:	2301      	movs	r3, #1
+ 8002b2e:	9301      	str	r3, [sp, #4]
+ 8002b30:	e7c1      	b.n	8002ab6 <HAL_ADC_Init+0x17a>
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+ 8002b32:	6da3      	ldr	r3, [r4, #88]	@ 0x58
+ 8002b34:	431a      	orrs	r2, r3
+ 8002b36:	65a2      	str	r2, [r4, #88]	@ 0x58
+    tmp_hal_status = HAL_ERROR;
+ 8002b38:	e7f8      	b.n	8002b2c <HAL_ADC_Init+0x1f0>
+ 8002b3a:	46c0      	nop			@ (mov r8, r8)
+ 8002b3c:	fffffefd 	.word	0xfffffefd
+ 8002b40:	ffde0201 	.word	0xffde0201
+ 8002b44:	1ffffc02 	.word	0x1ffffc02
+ 8002b48:	40012708 	.word	0x40012708
+ 8002b4c:	ffc3ffff 	.word	0xffc3ffff
+ 8002b50:	6fffffe8 	.word	0x6fffffe8
+ 8002b54:	20000024 	.word	0x20000024
+ 8002b58:	00030d40 	.word	0x00030d40
+
+08002b5c <HAL_ADC_ConfigChannel>:
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmp_config_internal_channel;
+  __IO uint32_t wait_loop_index = 0UL;
+ 8002b5c:	2300      	movs	r3, #0
+{
+ 8002b5e:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 8002b60:	b085      	sub	sp, #20
+  __IO uint32_t wait_loop_index = 0UL;
+ 8002b62:	9303      	str	r3, [sp, #12]
+
+    assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+ 8002b64:	0003      	movs	r3, r0
+{
+ 8002b66:	9100      	str	r1, [sp, #0]
+  __HAL_LOCK(hadc);
+ 8002b68:	3354      	adds	r3, #84	@ 0x54
+ 8002b6a:	781a      	ldrb	r2, [r3, #0]
+{
+ 8002b6c:	0004      	movs	r4, r0
+  __HAL_LOCK(hadc);
+ 8002b6e:	2002      	movs	r0, #2
+ 8002b70:	2a01      	cmp	r2, #1
+ 8002b72:	d04d      	beq.n	8002c10 <HAL_ADC_ConfigChannel+0xb4>
+ 8002b74:	2201      	movs	r2, #1
+  if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED)       ||
+ 8002b76:	6927      	ldr	r7, [r4, #16]
+  __HAL_LOCK(hadc);
+ 8002b78:	701a      	strb	r2, [r3, #0]
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Channel number                                                        */
+  /*  - Channel sampling time                                                 */
+  /*  - Management of internal measurement channels: VrefInt/TempSensor       */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+ 8002b7a:	6825      	ldr	r5, [r4, #0]
+ 8002b7c:	0028      	movs	r0, r5
+ 8002b7e:	f7ff fed9 	bl	8002934 <LL_ADC_REG_IsConversionOngoing>
+ 8002b82:	2800      	cmp	r0, #0
+ 8002b84:	d000      	beq.n	8002b88 <HAL_ADC_ConfigChannel+0x2c>
+ 8002b86:	e0f9      	b.n	8002d7c <HAL_ADC_ConfigChannel+0x220>
+    /* If sequencer set to not fully configurable with channel rank set to    */
+    /* none, remove the channel from the sequencer.                           */
+    /* Otherwise (sequencer set to fully configurable or to to not fully      */
+    /* configurable with channel rank to be set), configure the selected      */
+    /* channel.                                                               */
+    if (sConfig->Rank != ADC_RANK_NONE)
+ 8002b88:	9b00      	ldr	r3, [sp, #0]
+      /* Note: ADC channel configuration requires few ADC clock cycles        */
+      /*       to be ready. Processing of ADC settings in this function       */
+      /*       induce that a specific wait time is not necessary.             */
+      /*       For more details on ADC channel configuration ready,           */
+      /*       refer to function "LL_ADC_IsActiveFlag_CCRDY()".               */
+      if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED)       ||
+ 8002b8a:	2204      	movs	r2, #4
+    if (sConfig->Rank != ADC_RANK_NONE)
+ 8002b8c:	685b      	ldr	r3, [r3, #4]
+ 8002b8e:	2180      	movs	r1, #128	@ 0x80
+ 8002b90:	469c      	mov	ip, r3
+      if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED)       ||
+ 8002b92:	4397      	bics	r7, r2
+    if (sConfig->Rank != ADC_RANK_NONE)
+ 8002b94:	4662      	mov	r2, ip
+          (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
+      {
+        /* Sequencer set to not fully configurable:                           */
+        /* Set the channel by enabling the corresponding bitfield.            */
+        LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel);
+ 8002b96:	9b00      	ldr	r3, [sp, #0]
+ 8002b98:	0609      	lsls	r1, r1, #24
+ 8002b9a:	681b      	ldr	r3, [r3, #0]
+    if (sConfig->Rank != ADC_RANK_NONE)
+ 8002b9c:	2a02      	cmp	r2, #2
+ 8002b9e:	d100      	bne.n	8002ba2 <HAL_ADC_ConfigChannel+0x46>
+ 8002ba0:	e0c7      	b.n	8002d32 <HAL_ADC_ConfigChannel+0x1d6>
+  SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
+ 8002ba2:	025a      	lsls	r2, r3, #9
+ 8002ba4:	0a52      	lsrs	r2, r2, #9
+      if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED)       ||
+ 8002ba6:	428f      	cmp	r7, r1
+ 8002ba8:	d134      	bne.n	8002c14 <HAL_ADC_ConfigChannel+0xb8>
+ 8002baa:	6aa9      	ldr	r1, [r5, #40]	@ 0x28
+  MODIFY_REG(ADCx->CHSELR,
+ 8002bac:	430a      	orrs	r2, r1
+ 8002bae:	62aa      	str	r2, [r5, #40]	@ 0x28
+  MODIFY_REG(ADCx->SMPR,
+ 8002bb0:	9a00      	ldr	r2, [sp, #0]
+ 8002bb2:	6968      	ldr	r0, [r5, #20]
+ 8002bb4:	6892      	ldr	r2, [r2, #8]
+ 8002bb6:	0219      	lsls	r1, r3, #8
+ 8002bb8:	4e73      	ldr	r6, [pc, #460]	@ (8002d88 <HAL_ADC_ConfigChannel+0x22c>)
+ 8002bba:	400a      	ands	r2, r1
+ 8002bbc:	4032      	ands	r2, r6
+ 8002bbe:	4388      	bics	r0, r1
+ 8002bc0:	4302      	orrs	r2, r0
+ 8002bc2:	616a      	str	r2, [r5, #20]
+      /* internal measurement paths enable: If internal channel selected,     */
+      /* enable dedicated internal buffers and path.                          */
+      /* Note: these internal measurement paths can be disabled using         */
+      /*       HAL_ADC_DeInit() or removing the channel from sequencer with   */
+      /*       channel configuration parameter "Rank".                        */
+      if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ 8002bc4:	2b00      	cmp	r3, #0
+ 8002bc6:	da1f      	bge.n	8002c08 <HAL_ADC_ConfigChannel+0xac>
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
+ 8002bc8:	20c0      	movs	r0, #192	@ 0xc0
+ 8002bca:	4a70      	ldr	r2, [pc, #448]	@ (8002d8c <HAL_ADC_ConfigChannel+0x230>)
+      {
+        tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+        /* If the requested internal measurement path has already been enabled,   */
+        /* bypass the configuration processing.                                   */
+        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
+ 8002bcc:	4970      	ldr	r1, [pc, #448]	@ (8002d90 <HAL_ADC_ConfigChannel+0x234>)
+ 8002bce:	6815      	ldr	r5, [r2, #0]
+ 8002bd0:	0400      	lsls	r0, r0, #16
+ 8002bd2:	4028      	ands	r0, r5
+ 8002bd4:	428b      	cmp	r3, r1
+ 8002bd6:	d000      	beq.n	8002bda <HAL_ADC_ConfigChannel+0x7e>
+ 8002bd8:	e09b      	b.n	8002d12 <HAL_ADC_ConfigChannel+0x1b6>
+            ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+ 8002bda:	2180      	movs	r1, #128	@ 0x80
+ 8002bdc:	0409      	lsls	r1, r1, #16
+        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
+ 8002bde:	420d      	tst	r5, r1
+ 8002be0:	d112      	bne.n	8002c08 <HAL_ADC_ConfigChannel+0xac>
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
+ 8002be2:	6813      	ldr	r3, [r2, #0]
+ 8002be4:	4d6b      	ldr	r5, [pc, #428]	@ (8002d94 <HAL_ADC_ConfigChannel+0x238>)
+ 8002be6:	402b      	ands	r3, r5
+ 8002be8:	4303      	orrs	r3, r0
+ 8002bea:	4319      	orrs	r1, r3
+          /* Delay for temperature sensor stabilization time */
+          /* Wait loop initialization and execution */
+          /* Note: Variable divided by 2 to compensate partially              */
+          /*       CPU processing cycles, scaling in us split to not          */
+          /*       exceed 32 bits register capacity and handle low frequency. */
+          wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL);
+ 8002bec:	4b6a      	ldr	r3, [pc, #424]	@ (8002d98 <HAL_ADC_ConfigChannel+0x23c>)
+ 8002bee:	6011      	str	r1, [r2, #0]
+ 8002bf0:	6818      	ldr	r0, [r3, #0]
+ 8002bf2:	496a      	ldr	r1, [pc, #424]	@ (8002d9c <HAL_ADC_ConfigChannel+0x240>)
+ 8002bf4:	f7fd fa9c 	bl	8000130 <__udivsi3>
+ 8002bf8:	230c      	movs	r3, #12
+ 8002bfa:	4343      	muls	r3, r0
+ 8002bfc:	3301      	adds	r3, #1
+          while (wait_loop_index != 0UL)
+          {
+            wait_loop_index--;
+ 8002bfe:	9303      	str	r3, [sp, #12]
+          while (wait_loop_index != 0UL)
+ 8002c00:	9b03      	ldr	r3, [sp, #12]
+ 8002c02:	2b00      	cmp	r3, #0
+ 8002c04:	d000      	beq.n	8002c08 <HAL_ADC_ConfigChannel+0xac>
+ 8002c06:	e081      	b.n	8002d0c <HAL_ADC_ConfigChannel+0x1b0>
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+ 8002c08:	2000      	movs	r0, #0
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+ 8002c0a:	2300      	movs	r3, #0
+ 8002c0c:	3454      	adds	r4, #84	@ 0x54
+ 8002c0e:	7023      	strb	r3, [r4, #0]
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+ 8002c10:	b005      	add	sp, #20
+ 8002c12:	bdf0      	pop	{r4, r5, r6, r7, pc}
+        MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
+ 8002c14:	211f      	movs	r1, #31
+ 8002c16:	4667      	mov	r7, ip
+ 8002c18:	400f      	ands	r7, r1
+ 8002c1a:	3910      	subs	r1, #16
+ 8002c1c:	40b9      	lsls	r1, r7
+ 8002c1e:	43ce      	mvns	r6, r1
+ 8002c20:	9601      	str	r6, [sp, #4]
+ 8002c22:	6e26      	ldr	r6, [r4, #96]	@ 0x60
+ 8002c24:	438e      	bics	r6, r1
+ 8002c26:	0031      	movs	r1, r6
+ 8002c28:	2a00      	cmp	r2, #0
+ 8002c2a:	d112      	bne.n	8002c52 <HAL_ADC_ConfigChannel+0xf6>
+ 8002c2c:	0e98      	lsrs	r0, r3, #26
+ 8002c2e:	321f      	adds	r2, #31
+ 8002c30:	4010      	ands	r0, r2
+ 8002c32:	40b8      	lsls	r0, r7
+        if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
+ 8002c34:	4662      	mov	r2, ip
+        MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
+ 8002c36:	4308      	orrs	r0, r1
+        if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
+ 8002c38:	0892      	lsrs	r2, r2, #2
+ 8002c3a:	69e1      	ldr	r1, [r4, #28]
+ 8002c3c:	3201      	adds	r2, #1
+        MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
+ 8002c3e:	6620      	str	r0, [r4, #96]	@ 0x60
+        if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
+ 8002c40:	428a      	cmp	r2, r1
+ 8002c42:	d8b5      	bhi.n	8002bb0 <HAL_ADC_ConfigChannel+0x54>
+  MODIFY_REG(ADCx->CHSELR,
+ 8002c44:	6aa9      	ldr	r1, [r5, #40]	@ 0x28
+ 8002c46:	9801      	ldr	r0, [sp, #4]
+ 8002c48:	009a      	lsls	r2, r3, #2
+ 8002c4a:	0f12      	lsrs	r2, r2, #28
+ 8002c4c:	40ba      	lsls	r2, r7
+ 8002c4e:	4001      	ands	r1, r0
+ 8002c50:	e7ac      	b.n	8002bac <HAL_ADC_ConfigChannel+0x50>
+        MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
+ 8002c52:	2201      	movs	r2, #1
+ 8002c54:	4213      	tst	r3, r2
+ 8002c56:	d1ec      	bne.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002c58:	1892      	adds	r2, r2, r2
+ 8002c5a:	4213      	tst	r3, r2
+ 8002c5c:	d12c      	bne.n	8002cb8 <HAL_ADC_ConfigChannel+0x15c>
+ 8002c5e:	2604      	movs	r6, #4
+ 8002c60:	4233      	tst	r3, r6
+ 8002c62:	d12b      	bne.n	8002cbc <HAL_ADC_ConfigChannel+0x160>
+ 8002c64:	071a      	lsls	r2, r3, #28
+ 8002c66:	d42b      	bmi.n	8002cc0 <HAL_ADC_ConfigChannel+0x164>
+ 8002c68:	06da      	lsls	r2, r3, #27
+ 8002c6a:	d42b      	bmi.n	8002cc4 <HAL_ADC_ConfigChannel+0x168>
+ 8002c6c:	069a      	lsls	r2, r3, #26
+ 8002c6e:	d42b      	bmi.n	8002cc8 <HAL_ADC_ConfigChannel+0x16c>
+ 8002c70:	065a      	lsls	r2, r3, #25
+ 8002c72:	d42b      	bmi.n	8002ccc <HAL_ADC_ConfigChannel+0x170>
+ 8002c74:	061a      	lsls	r2, r3, #24
+ 8002c76:	d42b      	bmi.n	8002cd0 <HAL_ADC_ConfigChannel+0x174>
+ 8002c78:	05da      	lsls	r2, r3, #23
+ 8002c7a:	d42b      	bmi.n	8002cd4 <HAL_ADC_ConfigChannel+0x178>
+ 8002c7c:	059a      	lsls	r2, r3, #22
+ 8002c7e:	d42b      	bmi.n	8002cd8 <HAL_ADC_ConfigChannel+0x17c>
+ 8002c80:	055a      	lsls	r2, r3, #21
+ 8002c82:	d42b      	bmi.n	8002cdc <HAL_ADC_ConfigChannel+0x180>
+ 8002c84:	051a      	lsls	r2, r3, #20
+ 8002c86:	d42b      	bmi.n	8002ce0 <HAL_ADC_ConfigChannel+0x184>
+ 8002c88:	04da      	lsls	r2, r3, #19
+ 8002c8a:	d42b      	bmi.n	8002ce4 <HAL_ADC_ConfigChannel+0x188>
+ 8002c8c:	049a      	lsls	r2, r3, #18
+ 8002c8e:	d42b      	bmi.n	8002ce8 <HAL_ADC_ConfigChannel+0x18c>
+ 8002c90:	045a      	lsls	r2, r3, #17
+ 8002c92:	d42b      	bmi.n	8002cec <HAL_ADC_ConfigChannel+0x190>
+ 8002c94:	041a      	lsls	r2, r3, #16
+ 8002c96:	d42b      	bmi.n	8002cf0 <HAL_ADC_ConfigChannel+0x194>
+ 8002c98:	03da      	lsls	r2, r3, #15
+ 8002c9a:	d42b      	bmi.n	8002cf4 <HAL_ADC_ConfigChannel+0x198>
+ 8002c9c:	039a      	lsls	r2, r3, #14
+ 8002c9e:	d42b      	bmi.n	8002cf8 <HAL_ADC_ConfigChannel+0x19c>
+ 8002ca0:	035a      	lsls	r2, r3, #13
+ 8002ca2:	d42b      	bmi.n	8002cfc <HAL_ADC_ConfigChannel+0x1a0>
+ 8002ca4:	031a      	lsls	r2, r3, #12
+ 8002ca6:	d42b      	bmi.n	8002d00 <HAL_ADC_ConfigChannel+0x1a4>
+ 8002ca8:	02da      	lsls	r2, r3, #11
+ 8002caa:	d42b      	bmi.n	8002d04 <HAL_ADC_ConfigChannel+0x1a8>
+ 8002cac:	029a      	lsls	r2, r3, #10
+ 8002cae:	d42b      	bmi.n	8002d08 <HAL_ADC_ConfigChannel+0x1ac>
+ 8002cb0:	025a      	lsls	r2, r3, #9
+ 8002cb2:	d5be      	bpl.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cb4:	2016      	movs	r0, #22
+ 8002cb6:	e7bc      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cb8:	2001      	movs	r0, #1
+ 8002cba:	e7ba      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cbc:	0010      	movs	r0, r2
+ 8002cbe:	e7b8      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cc0:	2003      	movs	r0, #3
+ 8002cc2:	e7b6      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cc4:	2004      	movs	r0, #4
+ 8002cc6:	e7b4      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cc8:	2005      	movs	r0, #5
+ 8002cca:	e7b2      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002ccc:	2006      	movs	r0, #6
+ 8002cce:	e7b0      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cd0:	2007      	movs	r0, #7
+ 8002cd2:	e7ae      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cd4:	2008      	movs	r0, #8
+ 8002cd6:	e7ac      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cd8:	2009      	movs	r0, #9
+ 8002cda:	e7aa      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cdc:	200a      	movs	r0, #10
+ 8002cde:	e7a8      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002ce0:	200b      	movs	r0, #11
+ 8002ce2:	e7a6      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002ce4:	200c      	movs	r0, #12
+ 8002ce6:	e7a4      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002ce8:	200d      	movs	r0, #13
+ 8002cea:	e7a2      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cec:	200e      	movs	r0, #14
+ 8002cee:	e7a0      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cf0:	200f      	movs	r0, #15
+ 8002cf2:	e79e      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cf4:	2010      	movs	r0, #16
+ 8002cf6:	e79c      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cf8:	2011      	movs	r0, #17
+ 8002cfa:	e79a      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002cfc:	2012      	movs	r0, #18
+ 8002cfe:	e798      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002d00:	2013      	movs	r0, #19
+ 8002d02:	e796      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002d04:	2014      	movs	r0, #20
+ 8002d06:	e794      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+ 8002d08:	2015      	movs	r0, #21
+ 8002d0a:	e792      	b.n	8002c32 <HAL_ADC_ConfigChannel+0xd6>
+            wait_loop_index--;
+ 8002d0c:	9b03      	ldr	r3, [sp, #12]
+ 8002d0e:	3b01      	subs	r3, #1
+ 8002d10:	e775      	b.n	8002bfe <HAL_ADC_ConfigChannel+0xa2>
+        else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) &&
+ 8002d12:	4923      	ldr	r1, [pc, #140]	@ (8002da0 <HAL_ADC_ConfigChannel+0x244>)
+ 8002d14:	428b      	cmp	r3, r1
+ 8002d16:	d000      	beq.n	8002d1a <HAL_ADC_ConfigChannel+0x1be>
+ 8002d18:	e776      	b.n	8002c08 <HAL_ADC_ConfigChannel+0xac>
+                 ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+ 8002d1a:	2180      	movs	r1, #128	@ 0x80
+ 8002d1c:	03c9      	lsls	r1, r1, #15
+        else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) &&
+ 8002d1e:	420d      	tst	r5, r1
+ 8002d20:	d000      	beq.n	8002d24 <HAL_ADC_ConfigChannel+0x1c8>
+ 8002d22:	e771      	b.n	8002c08 <HAL_ADC_ConfigChannel+0xac>
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
+ 8002d24:	6813      	ldr	r3, [r2, #0]
+ 8002d26:	4d1b      	ldr	r5, [pc, #108]	@ (8002d94 <HAL_ADC_ConfigChannel+0x238>)
+ 8002d28:	402b      	ands	r3, r5
+ 8002d2a:	4303      	orrs	r3, r0
+ 8002d2c:	4319      	orrs	r1, r3
+ 8002d2e:	6011      	str	r1, [r2, #0]
+}
+ 8002d30:	e76a      	b.n	8002c08 <HAL_ADC_ConfigChannel+0xac>
+      if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED)       ||
+ 8002d32:	428f      	cmp	r7, r1
+ 8002d34:	d104      	bne.n	8002d40 <HAL_ADC_ConfigChannel+0x1e4>
+  CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
+ 8002d36:	6aaa      	ldr	r2, [r5, #40]	@ 0x28
+ 8002d38:	0259      	lsls	r1, r3, #9
+ 8002d3a:	0a49      	lsrs	r1, r1, #9
+ 8002d3c:	438a      	bics	r2, r1
+ 8002d3e:	62aa      	str	r2, [r5, #40]	@ 0x28
+      if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+ 8002d40:	2b00      	cmp	r3, #0
+ 8002d42:	db00      	blt.n	8002d46 <HAL_ADC_ConfigChannel+0x1ea>
+ 8002d44:	e760      	b.n	8002c08 <HAL_ADC_ConfigChannel+0xac>
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
+ 8002d46:	4911      	ldr	r1, [pc, #68]	@ (8002d8c <HAL_ADC_ConfigChannel+0x230>)
+        if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+ 8002d48:	4811      	ldr	r0, [pc, #68]	@ (8002d90 <HAL_ADC_ConfigChannel+0x234>)
+ 8002d4a:	680a      	ldr	r2, [r1, #0]
+ 8002d4c:	4283      	cmp	r3, r0
+ 8002d4e:	d108      	bne.n	8002d62 <HAL_ADC_ConfigChannel+0x206>
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ 8002d50:	2380      	movs	r3, #128	@ 0x80
+ 8002d52:	03db      	lsls	r3, r3, #15
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
+ 8002d54:	6808      	ldr	r0, [r1, #0]
+ 8002d56:	4013      	ands	r3, r2
+ 8002d58:	4a0e      	ldr	r2, [pc, #56]	@ (8002d94 <HAL_ADC_ConfigChannel+0x238>)
+ 8002d5a:	4002      	ands	r2, r0
+ 8002d5c:	4313      	orrs	r3, r2
+ 8002d5e:	600b      	str	r3, [r1, #0]
+}
+ 8002d60:	e752      	b.n	8002c08 <HAL_ADC_ConfigChannel+0xac>
+        else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
+ 8002d62:	480f      	ldr	r0, [pc, #60]	@ (8002da0 <HAL_ADC_ConfigChannel+0x244>)
+ 8002d64:	4283      	cmp	r3, r0
+ 8002d66:	d000      	beq.n	8002d6a <HAL_ADC_ConfigChannel+0x20e>
+ 8002d68:	e74e      	b.n	8002c08 <HAL_ADC_ConfigChannel+0xac>
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+ 8002d6a:	2080      	movs	r0, #128	@ 0x80
+ 8002d6c:	0400      	lsls	r0, r0, #16
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
+ 8002d6e:	680b      	ldr	r3, [r1, #0]
+ 8002d70:	4002      	ands	r2, r0
+ 8002d72:	4808      	ldr	r0, [pc, #32]	@ (8002d94 <HAL_ADC_ConfigChannel+0x238>)
+ 8002d74:	4003      	ands	r3, r0
+ 8002d76:	431a      	orrs	r2, r3
+ 8002d78:	600a      	str	r2, [r1, #0]
+}
+ 8002d7a:	e745      	b.n	8002c08 <HAL_ADC_ConfigChannel+0xac>
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 8002d7c:	2320      	movs	r3, #32
+ 8002d7e:	6da2      	ldr	r2, [r4, #88]	@ 0x58
+    tmp_hal_status = HAL_ERROR;
+ 8002d80:	2001      	movs	r0, #1
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+ 8002d82:	4313      	orrs	r3, r2
+ 8002d84:	65a3      	str	r3, [r4, #88]	@ 0x58
+    tmp_hal_status = HAL_ERROR;
+ 8002d86:	e740      	b.n	8002c0a <HAL_ADC_ConfigChannel+0xae>
+ 8002d88:	7fffff00 	.word	0x7fffff00
+ 8002d8c:	40012708 	.word	0x40012708
+ 8002d90:	a4000200 	.word	0xa4000200
+ 8002d94:	ff3fffff 	.word	0xff3fffff
+ 8002d98:	20000024 	.word	0x20000024
+ 8002d9c:	00030d40 	.word	0x00030d40
+ 8002da0:	a8000400 	.word	0xa8000400
+
+08002da4 <HAL_NVIC_SetPriority>:
   *         with stm32c0xx devices, this parameter is a dummy value and it is ignored, because
   *         no subpriority supported in Cortex M0+ based products.
   * @retval None
   */
 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
 {
- 80042c8:	b580      	push	{r7, lr}
- 80042ca:	b084      	sub	sp, #16
- 80042cc:	af00      	add	r7, sp, #0
- 80042ce:	60b9      	str	r1, [r7, #8]
- 80042d0:	607a      	str	r2, [r7, #4]
- 80042d2:	210f      	movs	r1, #15
- 80042d4:	187b      	adds	r3, r7, r1
- 80042d6:	1c02      	adds	r2, r0, #0
- 80042d8:	701a      	strb	r2, [r3, #0]
+ 8002da4:	b510      	push	{r4, lr}
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8002da6:	24ff      	movs	r4, #255	@ 0xff
+ 8002da8:	2203      	movs	r2, #3
+ 8002daa:	000b      	movs	r3, r1
+ 8002dac:	0021      	movs	r1, r4
+ 8002dae:	4002      	ands	r2, r0
+ 8002db0:	00d2      	lsls	r2, r2, #3
+ 8002db2:	4091      	lsls	r1, r2
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ 8002db4:	019b      	lsls	r3, r3, #6
+ 8002db6:	4023      	ands	r3, r4
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8002db8:	43c9      	mvns	r1, r1
+       (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
+ 8002dba:	4093      	lsls	r3, r2
+  if ((int32_t)(IRQn) >= 0)
+ 8002dbc:	2800      	cmp	r0, #0
+ 8002dbe:	db0a      	blt.n	8002dd6 <HAL_NVIC_SetPriority+0x32>
+    NVIC->IP[_IP_IDX(IRQn)]  = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)]  & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8002dc0:	24c0      	movs	r4, #192	@ 0xc0
+ 8002dc2:	4a0b      	ldr	r2, [pc, #44]	@ (8002df0 <HAL_NVIC_SetPriority+0x4c>)
+ 8002dc4:	0880      	lsrs	r0, r0, #2
+ 8002dc6:	0080      	lsls	r0, r0, #2
+ 8002dc8:	1880      	adds	r0, r0, r2
+ 8002dca:	00a4      	lsls	r4, r4, #2
+ 8002dcc:	5902      	ldr	r2, [r0, r4]
+ 8002dce:	400a      	ands	r2, r1
+ 8002dd0:	4313      	orrs	r3, r2
+ 8002dd2:	5103      	str	r3, [r0, r4]
   /* Prevent unused argument(s) compilation warning */
   UNUSED(SubPriority);
   /* Check the parameters */
   assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
   NVIC_SetPriority(IRQn, PreemptPriority);
- 80042da:	68ba      	ldr	r2, [r7, #8]
- 80042dc:	187b      	adds	r3, r7, r1
- 80042de:	781b      	ldrb	r3, [r3, #0]
- 80042e0:	b25b      	sxtb	r3, r3
- 80042e2:	0011      	movs	r1, r2
- 80042e4:	0018      	movs	r0, r3
- 80042e6:	f7ff ff5d 	bl	80041a4 <__NVIC_SetPriority>
 }
- 80042ea:	46c0      	nop			@ (mov r8, r8)
- 80042ec:	46bd      	mov	sp, r7
- 80042ee:	b004      	add	sp, #16
- 80042f0:	bd80      	pop	{r7, pc}
+ 8002dd4:	bd10      	pop	{r4, pc}
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8002dd6:	220f      	movs	r2, #15
+ 8002dd8:	4010      	ands	r0, r2
+ 8002dda:	3808      	subs	r0, #8
+ 8002ddc:	4a05      	ldr	r2, [pc, #20]	@ (8002df4 <HAL_NVIC_SetPriority+0x50>)
+ 8002dde:	0880      	lsrs	r0, r0, #2
+ 8002de0:	0080      	lsls	r0, r0, #2
+ 8002de2:	1880      	adds	r0, r0, r2
+ 8002de4:	69c2      	ldr	r2, [r0, #28]
+ 8002de6:	4011      	ands	r1, r2
+ 8002de8:	4319      	orrs	r1, r3
+ 8002dea:	61c1      	str	r1, [r0, #28]
+ 8002dec:	e7f2      	b.n	8002dd4 <HAL_NVIC_SetPriority+0x30>
+ 8002dee:	46c0      	nop			@ (mov r8, r8)
+ 8002df0:	e000e100 	.word	0xe000e100
+ 8002df4:	e000ed00 	.word	0xe000ed00
 
-080042f2 <HAL_NVIC_EnableIRQ>:
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate
-  *         CMSIS device file (stm32c0xxxx.h))
-  * @retval None
-  */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
- 80042f2:	b580      	push	{r7, lr}
- 80042f4:	b082      	sub	sp, #8
- 80042f6:	af00      	add	r7, sp, #0
- 80042f8:	0002      	movs	r2, r0
- 80042fa:	1dfb      	adds	r3, r7, #7
- 80042fc:	701a      	strb	r2, [r3, #0]
+08002df8 <HAL_NVIC_EnableIRQ>:
+  if ((int32_t)(IRQn) >= 0)
+ 8002df8:	2800      	cmp	r0, #0
+ 8002dfa:	db05      	blt.n	8002e08 <HAL_NVIC_EnableIRQ+0x10>
+    NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
+ 8002dfc:	231f      	movs	r3, #31
+ 8002dfe:	4018      	ands	r0, r3
+ 8002e00:	3b1e      	subs	r3, #30
+ 8002e02:	4083      	lsls	r3, r0
+ 8002e04:	4a01      	ldr	r2, [pc, #4]	@ (8002e0c <HAL_NVIC_EnableIRQ+0x14>)
+ 8002e06:	6013      	str	r3, [r2, #0]
   /* Check the parameters */
   assert_param(IS_NVIC_DEVICE_IRQ(IRQn));
 
   /* Enable interrupt */
   NVIC_EnableIRQ(IRQn);
- 80042fe:	1dfb      	adds	r3, r7, #7
- 8004300:	781b      	ldrb	r3, [r3, #0]
- 8004302:	b25b      	sxtb	r3, r3
- 8004304:	0018      	movs	r0, r3
- 8004306:	f7ff ff33 	bl	8004170 <__NVIC_EnableIRQ>
 }
- 800430a:	46c0      	nop			@ (mov r8, r8)
- 800430c:	46bd      	mov	sp, r7
- 800430e:	b002      	add	sp, #8
- 8004310:	bd80      	pop	{r7, pc}
+ 8002e08:	4770      	bx	lr
+ 8002e0a:	46c0      	nop			@ (mov r8, r8)
+ 8002e0c:	e000e100 	.word	0xe000e100
 
-08004312 <HAL_SYSTICK_Config>:
-  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
-  * @retval status:  - 0  Function succeeded.
+08002e10 <HAL_SYSTICK_Config>:
+           function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
+           must contain a vendor-specific implementation of this function.
+ */
+__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ 8002e10:	2280      	movs	r2, #128	@ 0x80
+ 8002e12:	1e43      	subs	r3, r0, #1
+ 8002e14:	0452      	lsls	r2, r2, #17
+  {
+    return (1UL);                                                   /* Reload value impossible */
+ 8002e16:	2001      	movs	r0, #1
+  if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
+ 8002e18:	4293      	cmp	r3, r2
+ 8002e1a:	d20d      	bcs.n	8002e38 <HAL_SYSTICK_Config+0x28>
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8002e1c:	21c0      	movs	r1, #192	@ 0xc0
+  }
+
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+ 8002e1e:	4a07      	ldr	r2, [pc, #28]	@ (8002e3c <HAL_SYSTICK_Config+0x2c>)
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8002e20:	4807      	ldr	r0, [pc, #28]	@ (8002e40 <HAL_SYSTICK_Config+0x30>)
+  SysTick->LOAD  = (uint32_t)(ticks - 1UL);                         /* set reload register */
+ 8002e22:	6053      	str	r3, [r2, #4]
+    SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
+ 8002e24:	6a03      	ldr	r3, [r0, #32]
+ 8002e26:	0609      	lsls	r1, r1, #24
+ 8002e28:	021b      	lsls	r3, r3, #8
+ 8002e2a:	0a1b      	lsrs	r3, r3, #8
+ 8002e2c:	430b      	orrs	r3, r1
+ 8002e2e:	6203      	str	r3, [r0, #32]
+  NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+ 8002e30:	2000      	movs	r0, #0
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+ 8002e32:	2307      	movs	r3, #7
+  SysTick->VAL   = 0UL;                                             /* Load the SysTick Counter Value */
+ 8002e34:	6090      	str	r0, [r2, #8]
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+ 8002e36:	6013      	str	r3, [r2, #0]
   *                  - 1  Function failed.
   */
 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
 {
- 8004312:	b580      	push	{r7, lr}
- 8004314:	b082      	sub	sp, #8
- 8004316:	af00      	add	r7, sp, #0
- 8004318:	6078      	str	r0, [r7, #4]
   return SysTick_Config(TicksNumb);
- 800431a:	687b      	ldr	r3, [r7, #4]
- 800431c:	0018      	movs	r0, r3
- 800431e:	f7ff ffaf 	bl	8004280 <SysTick_Config>
- 8004322:	0003      	movs	r3, r0
 }
- 8004324:	0018      	movs	r0, r3
- 8004326:	46bd      	mov	sp, r7
- 8004328:	b002      	add	sp, #8
- 800432a:	bd80      	pop	{r7, pc}
+ 8002e38:	4770      	bx	lr
+ 8002e3a:	46c0      	nop			@ (mov r8, r8)
+ 8002e3c:	e000e010 	.word	0xe000e010
+ 8002e40:	e000ed00 	.word	0xe000ed00
 
-0800432c <HAL_DMA_Init>:
-  * @param  hdma  Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{
- 800432c:	b580      	push	{r7, lr}
- 800432e:	b082      	sub	sp, #8
- 8004330:	af00      	add	r7, sp, #0
- 8004332:	6078      	str	r0, [r7, #4]
-  /* Check the DMA handle allocation */
-  if (hdma == NULL)
- 8004334:	687b      	ldr	r3, [r7, #4]
- 8004336:	2b00      	cmp	r3, #0
- 8004338:	d101      	bne.n	800433e <HAL_DMA_Init+0x12>
-  {
-    return HAL_ERROR;
- 800433a:	2301      	movs	r3, #1
- 800433c:	e077      	b.n	800442e <HAL_DMA_Init+0x102>
-  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
-  assert_param(IS_DMA_MODE(hdma->Init.Mode));
-  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-
-  /* calculation of the channel index */
-  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \
- 800433e:	687b      	ldr	r3, [r7, #4]
- 8004340:	681b      	ldr	r3, [r3, #0]
- 8004342:	4a3d      	ldr	r2, [pc, #244]	@ (8004438 <HAL_DMA_Init+0x10c>)
- 8004344:	4694      	mov	ip, r2
- 8004346:	4463      	add	r3, ip
- 8004348:	2114      	movs	r1, #20
- 800434a:	0018      	movs	r0, r3
- 800434c:	f7fb fedc 	bl	8000108 <__udivsi3>
- 8004350:	0003      	movs	r3, r0
-                                                                                (uint32_t)DMA1_Channel1)) << 2U;
- 8004352:	009a      	lsls	r2, r3, #2
-  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \
- 8004354:	687b      	ldr	r3, [r7, #4]
- 8004356:	641a      	str	r2, [r3, #64]	@ 0x40
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
- 8004358:	687b      	ldr	r3, [r7, #4]
- 800435a:	2225      	movs	r2, #37	@ 0x25
- 800435c:	2102      	movs	r1, #2
- 800435e:	5499      	strb	r1, [r3, r2]
-
-  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */
-  CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
- 8004360:	687b      	ldr	r3, [r7, #4]
- 8004362:	681b      	ldr	r3, [r3, #0]
- 8004364:	681a      	ldr	r2, [r3, #0]
- 8004366:	687b      	ldr	r3, [r7, #4]
- 8004368:	681b      	ldr	r3, [r3, #0]
- 800436a:	4934      	ldr	r1, [pc, #208]	@ (800443c <HAL_DMA_Init+0x110>)
- 800436c:	400a      	ands	r2, r1
- 800436e:	601a      	str	r2, [r3, #0]
-                                  DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
-                                  DMA_CCR_DIR   | DMA_CCR_MEM2MEM));
-
-  /* Set the DMA Channel configuration */
-  SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction           |                               \
- 8004370:	687b      	ldr	r3, [r7, #4]
- 8004372:	681b      	ldr	r3, [r3, #0]
- 8004374:	6819      	ldr	r1, [r3, #0]
- 8004376:	687b      	ldr	r3, [r7, #4]
- 8004378:	689a      	ldr	r2, [r3, #8]
- 800437a:	687b      	ldr	r3, [r7, #4]
- 800437c:	68db      	ldr	r3, [r3, #12]
- 800437e:	431a      	orrs	r2, r3
- 8004380:	687b      	ldr	r3, [r7, #4]
- 8004382:	691b      	ldr	r3, [r3, #16]
- 8004384:	431a      	orrs	r2, r3
- 8004386:	687b      	ldr	r3, [r7, #4]
- 8004388:	695b      	ldr	r3, [r3, #20]
- 800438a:	431a      	orrs	r2, r3
- 800438c:	687b      	ldr	r3, [r7, #4]
- 800438e:	699b      	ldr	r3, [r3, #24]
- 8004390:	431a      	orrs	r2, r3
- 8004392:	687b      	ldr	r3, [r7, #4]
- 8004394:	69db      	ldr	r3, [r3, #28]
- 8004396:	431a      	orrs	r2, r3
- 8004398:	687b      	ldr	r3, [r7, #4]
- 800439a:	6a1b      	ldr	r3, [r3, #32]
- 800439c:	431a      	orrs	r2, r3
- 800439e:	687b      	ldr	r3, [r7, #4]
- 80043a0:	681b      	ldr	r3, [r3, #0]
- 80043a2:	430a      	orrs	r2, r1
- 80043a4:	601a      	str	r2, [r3, #0]
-                                hdma->Init.Mode                | hdma->Init.Priority));
-
-  /* Initialize parameters for DMAMUX channel :
-     DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask
-  */
-  DMA_CalcDMAMUXChannelBaseAndMask(hdma);
- 80043a6:	687b      	ldr	r3, [r7, #4]
- 80043a8:	0018      	movs	r0, r3
- 80043aa:	f000 f9c3 	bl	8004734 <DMA_CalcDMAMUXChannelBaseAndMask>
-
-  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
- 80043ae:	687b      	ldr	r3, [r7, #4]
- 80043b0:	689a      	ldr	r2, [r3, #8]
- 80043b2:	2380      	movs	r3, #128	@ 0x80
- 80043b4:	01db      	lsls	r3, r3, #7
- 80043b6:	429a      	cmp	r2, r3
- 80043b8:	d102      	bne.n	80043c0 <HAL_DMA_Init+0x94>
-  {
-    /* if memory to memory force the request to 0*/
-    hdma->Init.Request = DMA_REQUEST_MEM2MEM;
- 80043ba:	687b      	ldr	r3, [r7, #4]
- 80043bc:	2200      	movs	r2, #0
- 80043be:	605a      	str	r2, [r3, #4]
-  }
-
-  /* Set peripheral request  to DMAMUX channel */
-  hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
- 80043c0:	687b      	ldr	r3, [r7, #4]
- 80043c2:	685a      	ldr	r2, [r3, #4]
- 80043c4:	687b      	ldr	r3, [r7, #4]
- 80043c6:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
- 80043c8:	21ff      	movs	r1, #255	@ 0xff
- 80043ca:	400a      	ands	r2, r1
- 80043cc:	601a      	str	r2, [r3, #0]
-
-  /* Clear the DMAMUX synchro overrun flag */
-  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
- 80043ce:	687b      	ldr	r3, [r7, #4]
- 80043d0:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
- 80043d2:	687a      	ldr	r2, [r7, #4]
- 80043d4:	6cd2      	ldr	r2, [r2, #76]	@ 0x4c
- 80043d6:	605a      	str	r2, [r3, #4]
-
-  if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
- 80043d8:	687b      	ldr	r3, [r7, #4]
- 80043da:	685b      	ldr	r3, [r3, #4]
- 80043dc:	2b00      	cmp	r3, #0
- 80043de:	d011      	beq.n	8004404 <HAL_DMA_Init+0xd8>
- 80043e0:	687b      	ldr	r3, [r7, #4]
- 80043e2:	685b      	ldr	r3, [r3, #4]
- 80043e4:	2b04      	cmp	r3, #4
- 80043e6:	d80d      	bhi.n	8004404 <HAL_DMA_Init+0xd8>
-  {
-    /* Initialize parameters for DMAMUX request generator :
-       DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask
-    */
-    DMA_CalcDMAMUXRequestGenBaseAndMask(hdma);
- 80043e8:	687b      	ldr	r3, [r7, #4]
- 80043ea:	0018      	movs	r0, r3
- 80043ec:	f000 f9ce 	bl	800478c <DMA_CalcDMAMUXRequestGenBaseAndMask>
-
-    /* Reset the DMAMUX request generator register*/
-    hdma->DMAmuxRequestGen->RGCR = 0U;
- 80043f0:	687b      	ldr	r3, [r7, #4]
- 80043f2:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
- 80043f4:	2200      	movs	r2, #0
- 80043f6:	601a      	str	r2, [r3, #0]
-
-    /* Clear the DMAMUX request generator overrun flag */
-    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- 80043f8:	687b      	ldr	r3, [r7, #4]
- 80043fa:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
- 80043fc:	687a      	ldr	r2, [r7, #4]
- 80043fe:	6d92      	ldr	r2, [r2, #88]	@ 0x58
- 8004400:	605a      	str	r2, [r3, #4]
- 8004402:	e008      	b.n	8004416 <HAL_DMA_Init+0xea>
-  }
-  else
-  {
-    hdma->DMAmuxRequestGen = 0U;
- 8004404:	687b      	ldr	r3, [r7, #4]
- 8004406:	2200      	movs	r2, #0
- 8004408:	651a      	str	r2, [r3, #80]	@ 0x50
-    hdma->DMAmuxRequestGenStatus = 0U;
- 800440a:	687b      	ldr	r3, [r7, #4]
- 800440c:	2200      	movs	r2, #0
- 800440e:	655a      	str	r2, [r3, #84]	@ 0x54
-    hdma->DMAmuxRequestGenStatusMask = 0U;
- 8004410:	687b      	ldr	r3, [r7, #4]
- 8004412:	2200      	movs	r2, #0
- 8004414:	659a      	str	r2, [r3, #88]	@ 0x58
-  }
-
-  /* Initialize the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
- 8004416:	687b      	ldr	r3, [r7, #4]
- 8004418:	2200      	movs	r2, #0
- 800441a:	63da      	str	r2, [r3, #60]	@ 0x3c
-
-  /* Initialize the DMA state*/
-  hdma->State  = HAL_DMA_STATE_READY;
- 800441c:	687b      	ldr	r3, [r7, #4]
- 800441e:	2225      	movs	r2, #37	@ 0x25
- 8004420:	2101      	movs	r1, #1
- 8004422:	5499      	strb	r1, [r3, r2]
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
- 8004424:	687b      	ldr	r3, [r7, #4]
- 8004426:	2224      	movs	r2, #36	@ 0x24
- 8004428:	2100      	movs	r1, #0
- 800442a:	5499      	strb	r1, [r3, r2]
-
-  return HAL_OK;
- 800442c:	2300      	movs	r3, #0
-}
- 800442e:	0018      	movs	r0, r3
- 8004430:	46bd      	mov	sp, r7
- 8004432:	b002      	add	sp, #8
- 8004434:	bd80      	pop	{r7, pc}
- 8004436:	46c0      	nop			@ (mov r8, r8)
- 8004438:	bffdfff8 	.word	0xbffdfff8
- 800443c:	ffff800f 	.word	0xffff800f
-
-08004440 <HAL_DMA_Start_IT>:
-  * @param DataLength The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress,
-                                   uint32_t DataLength)
-{
- 8004440:	b580      	push	{r7, lr}
- 8004442:	b086      	sub	sp, #24
- 8004444:	af00      	add	r7, sp, #0
- 8004446:	60f8      	str	r0, [r7, #12]
- 8004448:	60b9      	str	r1, [r7, #8]
- 800444a:	607a      	str	r2, [r7, #4]
- 800444c:	603b      	str	r3, [r7, #0]
-  HAL_StatusTypeDef status = HAL_OK;
- 800444e:	2317      	movs	r3, #23
- 8004450:	18fb      	adds	r3, r7, r3
- 8004452:	2200      	movs	r2, #0
- 8004454:	701a      	strb	r2, [r3, #0]
-
-  /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-
-  /* Process locked */
-  __HAL_LOCK(hdma);
- 8004456:	68fb      	ldr	r3, [r7, #12]
- 8004458:	2224      	movs	r2, #36	@ 0x24
- 800445a:	5c9b      	ldrb	r3, [r3, r2]
- 800445c:	2b01      	cmp	r3, #1
- 800445e:	d101      	bne.n	8004464 <HAL_DMA_Start_IT+0x24>
- 8004460:	2302      	movs	r3, #2
- 8004462:	e070      	b.n	8004546 <HAL_DMA_Start_IT+0x106>
- 8004464:	68fb      	ldr	r3, [r7, #12]
- 8004466:	2224      	movs	r2, #36	@ 0x24
- 8004468:	2101      	movs	r1, #1
- 800446a:	5499      	strb	r1, [r3, r2]
-
-  if (HAL_DMA_STATE_READY == hdma->State)
- 800446c:	68fb      	ldr	r3, [r7, #12]
- 800446e:	2225      	movs	r2, #37	@ 0x25
- 8004470:	5c9b      	ldrb	r3, [r3, r2]
- 8004472:	b2db      	uxtb	r3, r3
- 8004474:	2b01      	cmp	r3, #1
- 8004476:	d157      	bne.n	8004528 <HAL_DMA_Start_IT+0xe8>
-  {
-    /* Change DMA peripheral state */
-    hdma->State = HAL_DMA_STATE_BUSY;
- 8004478:	68fb      	ldr	r3, [r7, #12]
- 800447a:	2225      	movs	r2, #37	@ 0x25
- 800447c:	2102      	movs	r1, #2
- 800447e:	5499      	strb	r1, [r3, r2]
-    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
- 8004480:	68fb      	ldr	r3, [r7, #12]
- 8004482:	2200      	movs	r2, #0
- 8004484:	63da      	str	r2, [r3, #60]	@ 0x3c
-
-    /* Disable the peripheral */
-    __HAL_DMA_DISABLE(hdma);
- 8004486:	68fb      	ldr	r3, [r7, #12]
- 8004488:	681b      	ldr	r3, [r3, #0]
- 800448a:	681a      	ldr	r2, [r3, #0]
- 800448c:	68fb      	ldr	r3, [r7, #12]
- 800448e:	681b      	ldr	r3, [r3, #0]
- 8004490:	2101      	movs	r1, #1
- 8004492:	438a      	bics	r2, r1
- 8004494:	601a      	str	r2, [r3, #0]
-
-    /* Configure the source, destination address and the data length & clear flags*/
-    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
- 8004496:	683b      	ldr	r3, [r7, #0]
- 8004498:	687a      	ldr	r2, [r7, #4]
- 800449a:	68b9      	ldr	r1, [r7, #8]
- 800449c:	68f8      	ldr	r0, [r7, #12]
- 800449e:	f000 f909 	bl	80046b4 <DMA_SetConfig>
-
-    /* Enable the transfer complete interrupt */
-    /* Enable the transfer Error interrupt */
-    if (NULL != hdma->XferHalfCpltCallback)
- 80044a2:	68fb      	ldr	r3, [r7, #12]
- 80044a4:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
- 80044a6:	2b00      	cmp	r3, #0
- 80044a8:	d008      	beq.n	80044bc <HAL_DMA_Start_IT+0x7c>
-    {
-      /* Enable the Half transfer complete interrupt as well */
-      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
- 80044aa:	68fb      	ldr	r3, [r7, #12]
- 80044ac:	681b      	ldr	r3, [r3, #0]
- 80044ae:	681a      	ldr	r2, [r3, #0]
- 80044b0:	68fb      	ldr	r3, [r7, #12]
- 80044b2:	681b      	ldr	r3, [r3, #0]
- 80044b4:	210e      	movs	r1, #14
- 80044b6:	430a      	orrs	r2, r1
- 80044b8:	601a      	str	r2, [r3, #0]
- 80044ba:	e00f      	b.n	80044dc <HAL_DMA_Start_IT+0x9c>
-    }
-    else
-    {
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
- 80044bc:	68fb      	ldr	r3, [r7, #12]
- 80044be:	681b      	ldr	r3, [r3, #0]
- 80044c0:	681a      	ldr	r2, [r3, #0]
- 80044c2:	68fb      	ldr	r3, [r7, #12]
- 80044c4:	681b      	ldr	r3, [r3, #0]
- 80044c6:	2104      	movs	r1, #4
- 80044c8:	438a      	bics	r2, r1
- 80044ca:	601a      	str	r2, [r3, #0]
-      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
- 80044cc:	68fb      	ldr	r3, [r7, #12]
- 80044ce:	681b      	ldr	r3, [r3, #0]
- 80044d0:	681a      	ldr	r2, [r3, #0]
- 80044d2:	68fb      	ldr	r3, [r7, #12]
- 80044d4:	681b      	ldr	r3, [r3, #0]
- 80044d6:	210a      	movs	r1, #10
- 80044d8:	430a      	orrs	r2, r1
- 80044da:	601a      	str	r2, [r3, #0]
-    }
-
-    /* Check if DMAMUX Synchronization is enabled*/
-    if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
- 80044dc:	68fb      	ldr	r3, [r7, #12]
- 80044de:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
- 80044e0:	681a      	ldr	r2, [r3, #0]
- 80044e2:	2380      	movs	r3, #128	@ 0x80
- 80044e4:	025b      	lsls	r3, r3, #9
- 80044e6:	4013      	ands	r3, r2
- 80044e8:	d008      	beq.n	80044fc <HAL_DMA_Start_IT+0xbc>
-    {
-      /* Enable DMAMUX sync overrun IT*/
-      hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
- 80044ea:	68fb      	ldr	r3, [r7, #12]
- 80044ec:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
- 80044ee:	681a      	ldr	r2, [r3, #0]
- 80044f0:	68fb      	ldr	r3, [r7, #12]
- 80044f2:	6c5b      	ldr	r3, [r3, #68]	@ 0x44
- 80044f4:	2180      	movs	r1, #128	@ 0x80
- 80044f6:	0049      	lsls	r1, r1, #1
- 80044f8:	430a      	orrs	r2, r1
- 80044fa:	601a      	str	r2, [r3, #0]
-    }
-
-    if (hdma->DMAmuxRequestGen != 0U)
- 80044fc:	68fb      	ldr	r3, [r7, #12]
- 80044fe:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
- 8004500:	2b00      	cmp	r3, #0
- 8004502:	d008      	beq.n	8004516 <HAL_DMA_Start_IT+0xd6>
-    {
-      /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/
-      /* enable the request gen overrun IT*/
-      hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
- 8004504:	68fb      	ldr	r3, [r7, #12]
- 8004506:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
- 8004508:	681a      	ldr	r2, [r3, #0]
- 800450a:	68fb      	ldr	r3, [r7, #12]
- 800450c:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
- 800450e:	2180      	movs	r1, #128	@ 0x80
- 8004510:	0049      	lsls	r1, r1, #1
- 8004512:	430a      	orrs	r2, r1
- 8004514:	601a      	str	r2, [r3, #0]
-    }
-
-    /* Enable the Peripheral */
-    __HAL_DMA_ENABLE(hdma);
- 8004516:	68fb      	ldr	r3, [r7, #12]
- 8004518:	681b      	ldr	r3, [r3, #0]
- 800451a:	681a      	ldr	r2, [r3, #0]
- 800451c:	68fb      	ldr	r3, [r7, #12]
- 800451e:	681b      	ldr	r3, [r3, #0]
- 8004520:	2101      	movs	r1, #1
- 8004522:	430a      	orrs	r2, r1
- 8004524:	601a      	str	r2, [r3, #0]
- 8004526:	e007      	b.n	8004538 <HAL_DMA_Start_IT+0xf8>
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
- 8004528:	68fb      	ldr	r3, [r7, #12]
- 800452a:	2224      	movs	r2, #36	@ 0x24
- 800452c:	2100      	movs	r1, #0
- 800452e:	5499      	strb	r1, [r3, r2]
-
-    /* Remain BUSY */
-    status = HAL_BUSY;
- 8004530:	2317      	movs	r3, #23
- 8004532:	18fb      	adds	r3, r7, r3
- 8004534:	2202      	movs	r2, #2
- 8004536:	701a      	strb	r2, [r3, #0]
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hdma);
- 8004538:	68fb      	ldr	r3, [r7, #12]
- 800453a:	2224      	movs	r2, #36	@ 0x24
- 800453c:	2100      	movs	r1, #0
- 800453e:	5499      	strb	r1, [r3, r2]
-
-  return status;
- 8004540:	2317      	movs	r3, #23
- 8004542:	18fb      	adds	r3, r7, r3
- 8004544:	781b      	ldrb	r3, [r3, #0]
-}
- 8004546:	0018      	movs	r0, r3
- 8004548:	46bd      	mov	sp, r7
- 800454a:	b006      	add	sp, #24
- 800454c:	bd80      	pop	{r7, pc}
-	...
-
-08004550 <HAL_DMA_IRQHandler>:
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.
-  * @retval None
-  */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{
- 8004550:	b580      	push	{r7, lr}
- 8004552:	b084      	sub	sp, #16
- 8004554:	af00      	add	r7, sp, #0
- 8004556:	6078      	str	r0, [r7, #4]
-  uint32_t flag_it = DMA1->ISR;
- 8004558:	4b55      	ldr	r3, [pc, #340]	@ (80046b0 <HAL_DMA_IRQHandler+0x160>)
- 800455a:	681b      	ldr	r3, [r3, #0]
- 800455c:	60fb      	str	r3, [r7, #12]
-  uint32_t source_it = hdma->Instance->CCR;
- 800455e:	687b      	ldr	r3, [r7, #4]
- 8004560:	681b      	ldr	r3, [r3, #0]
- 8004562:	681b      	ldr	r3, [r3, #0]
- 8004564:	60bb      	str	r3, [r7, #8]
-
-  /* Half Transfer Complete Interrupt management ******************************/
-  if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
- 8004566:	687b      	ldr	r3, [r7, #4]
- 8004568:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 800456a:	221c      	movs	r2, #28
- 800456c:	4013      	ands	r3, r2
- 800456e:	2204      	movs	r2, #4
- 8004570:	409a      	lsls	r2, r3
- 8004572:	0013      	movs	r3, r2
- 8004574:	68fa      	ldr	r2, [r7, #12]
- 8004576:	4013      	ands	r3, r2
- 8004578:	d027      	beq.n	80045ca <HAL_DMA_IRQHandler+0x7a>
- 800457a:	68bb      	ldr	r3, [r7, #8]
- 800457c:	2204      	movs	r2, #4
- 800457e:	4013      	ands	r3, r2
- 8004580:	d023      	beq.n	80045ca <HAL_DMA_IRQHandler+0x7a>
-  {
-    /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-    if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- 8004582:	687b      	ldr	r3, [r7, #4]
- 8004584:	681b      	ldr	r3, [r3, #0]
- 8004586:	681b      	ldr	r3, [r3, #0]
- 8004588:	2220      	movs	r2, #32
- 800458a:	4013      	ands	r3, r2
- 800458c:	d107      	bne.n	800459e <HAL_DMA_IRQHandler+0x4e>
-    {
-      /* Disable the half transfer interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
- 800458e:	687b      	ldr	r3, [r7, #4]
- 8004590:	681b      	ldr	r3, [r3, #0]
- 8004592:	681a      	ldr	r2, [r3, #0]
- 8004594:	687b      	ldr	r3, [r7, #4]
- 8004596:	681b      	ldr	r3, [r3, #0]
- 8004598:	2104      	movs	r1, #4
- 800459a:	438a      	bics	r2, r1
- 800459c:	601a      	str	r2, [r3, #0]
-    }
-    /* Clear the half transfer complete flag */
-    __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)));
- 800459e:	4b44      	ldr	r3, [pc, #272]	@ (80046b0 <HAL_DMA_IRQHandler+0x160>)
- 80045a0:	6859      	ldr	r1, [r3, #4]
- 80045a2:	687b      	ldr	r3, [r7, #4]
- 80045a4:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 80045a6:	221c      	movs	r2, #28
- 80045a8:	4013      	ands	r3, r2
- 80045aa:	2204      	movs	r2, #4
- 80045ac:	409a      	lsls	r2, r3
- 80045ae:	4b40      	ldr	r3, [pc, #256]	@ (80046b0 <HAL_DMA_IRQHandler+0x160>)
- 80045b0:	430a      	orrs	r2, r1
- 80045b2:	605a      	str	r2, [r3, #4]
-
-    /* DMA peripheral state is not updated in Half Transfer */
-    /* but in Transfer Complete case */
-
-    if (hdma->XferHalfCpltCallback != NULL)
- 80045b4:	687b      	ldr	r3, [r7, #4]
- 80045b6:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
- 80045b8:	2b00      	cmp	r3, #0
- 80045ba:	d100      	bne.n	80045be <HAL_DMA_IRQHandler+0x6e>
- 80045bc:	e073      	b.n	80046a6 <HAL_DMA_IRQHandler+0x156>
-    {
-      /* Half transfer callback */
-      hdma->XferHalfCpltCallback(hdma);
- 80045be:	687b      	ldr	r3, [r7, #4]
- 80045c0:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
- 80045c2:	687a      	ldr	r2, [r7, #4]
- 80045c4:	0010      	movs	r0, r2
- 80045c6:	4798      	blx	r3
-    if (hdma->XferHalfCpltCallback != NULL)
- 80045c8:	e06d      	b.n	80046a6 <HAL_DMA_IRQHandler+0x156>
-    }
-  }
-
-  /* Transfer Complete Interrupt management ***********************************/
-  else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC)))
- 80045ca:	687b      	ldr	r3, [r7, #4]
- 80045cc:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 80045ce:	221c      	movs	r2, #28
- 80045d0:	4013      	ands	r3, r2
- 80045d2:	2202      	movs	r2, #2
- 80045d4:	409a      	lsls	r2, r3
- 80045d6:	0013      	movs	r3, r2
- 80045d8:	68fa      	ldr	r2, [r7, #12]
- 80045da:	4013      	ands	r3, r2
- 80045dc:	d02e      	beq.n	800463c <HAL_DMA_IRQHandler+0xec>
- 80045de:	68bb      	ldr	r3, [r7, #8]
- 80045e0:	2202      	movs	r2, #2
- 80045e2:	4013      	ands	r3, r2
- 80045e4:	d02a      	beq.n	800463c <HAL_DMA_IRQHandler+0xec>
-  {
-    if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
- 80045e6:	687b      	ldr	r3, [r7, #4]
- 80045e8:	681b      	ldr	r3, [r3, #0]
- 80045ea:	681b      	ldr	r3, [r3, #0]
- 80045ec:	2220      	movs	r2, #32
- 80045ee:	4013      	ands	r3, r2
- 80045f0:	d10b      	bne.n	800460a <HAL_DMA_IRQHandler+0xba>
-    {
-      /* Disable the transfer complete and error interrupt */
-      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
- 80045f2:	687b      	ldr	r3, [r7, #4]
- 80045f4:	681b      	ldr	r3, [r3, #0]
- 80045f6:	681a      	ldr	r2, [r3, #0]
- 80045f8:	687b      	ldr	r3, [r7, #4]
- 80045fa:	681b      	ldr	r3, [r3, #0]
- 80045fc:	210a      	movs	r1, #10
- 80045fe:	438a      	bics	r2, r1
- 8004600:	601a      	str	r2, [r3, #0]
-
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_READY;
- 8004602:	687b      	ldr	r3, [r7, #4]
- 8004604:	2225      	movs	r2, #37	@ 0x25
- 8004606:	2101      	movs	r1, #1
- 8004608:	5499      	strb	r1, [r3, r2]
-    }
-    /* Clear the transfer complete flag */
-    __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)));
- 800460a:	4b29      	ldr	r3, [pc, #164]	@ (80046b0 <HAL_DMA_IRQHandler+0x160>)
- 800460c:	6859      	ldr	r1, [r3, #4]
- 800460e:	687b      	ldr	r3, [r7, #4]
- 8004610:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 8004612:	221c      	movs	r2, #28
- 8004614:	4013      	ands	r3, r2
- 8004616:	2202      	movs	r2, #2
- 8004618:	409a      	lsls	r2, r3
- 800461a:	4b25      	ldr	r3, [pc, #148]	@ (80046b0 <HAL_DMA_IRQHandler+0x160>)
- 800461c:	430a      	orrs	r2, r1
- 800461e:	605a      	str	r2, [r3, #4]
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
- 8004620:	687b      	ldr	r3, [r7, #4]
- 8004622:	2224      	movs	r2, #36	@ 0x24
- 8004624:	2100      	movs	r1, #0
- 8004626:	5499      	strb	r1, [r3, r2]
-
-    if (hdma->XferCpltCallback != NULL)
- 8004628:	687b      	ldr	r3, [r7, #4]
- 800462a:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
- 800462c:	2b00      	cmp	r3, #0
- 800462e:	d03a      	beq.n	80046a6 <HAL_DMA_IRQHandler+0x156>
-    {
-      /* Transfer complete callback */
-      hdma->XferCpltCallback(hdma);
- 8004630:	687b      	ldr	r3, [r7, #4]
- 8004632:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
- 8004634:	687a      	ldr	r2, [r7, #4]
- 8004636:	0010      	movs	r0, r2
- 8004638:	4798      	blx	r3
-    if (hdma->XferCpltCallback != NULL)
- 800463a:	e034      	b.n	80046a6 <HAL_DMA_IRQHandler+0x156>
-    }
-  }
-
-  /* Transfer Error Interrupt management **************************************/
-  else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
- 800463c:	687b      	ldr	r3, [r7, #4]
- 800463e:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 8004640:	221c      	movs	r2, #28
- 8004642:	4013      	ands	r3, r2
- 8004644:	2208      	movs	r2, #8
- 8004646:	409a      	lsls	r2, r3
- 8004648:	0013      	movs	r3, r2
- 800464a:	68fa      	ldr	r2, [r7, #12]
- 800464c:	4013      	ands	r3, r2
- 800464e:	d02b      	beq.n	80046a8 <HAL_DMA_IRQHandler+0x158>
- 8004650:	68bb      	ldr	r3, [r7, #8]
- 8004652:	2208      	movs	r2, #8
- 8004654:	4013      	ands	r3, r2
- 8004656:	d027      	beq.n	80046a8 <HAL_DMA_IRQHandler+0x158>
-  {
-    /* When a DMA transfer error occurs */
-    /* A hardware clear of its EN bits is performed */
-    /* Disable ALL DMA IT */
-    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
- 8004658:	687b      	ldr	r3, [r7, #4]
- 800465a:	681b      	ldr	r3, [r3, #0]
- 800465c:	681a      	ldr	r2, [r3, #0]
- 800465e:	687b      	ldr	r3, [r7, #4]
- 8004660:	681b      	ldr	r3, [r3, #0]
- 8004662:	210e      	movs	r1, #14
- 8004664:	438a      	bics	r2, r1
- 8004666:	601a      	str	r2, [r3, #0]
-
-    /* Clear all flags */
-    __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU)));
- 8004668:	4b11      	ldr	r3, [pc, #68]	@ (80046b0 <HAL_DMA_IRQHandler+0x160>)
- 800466a:	6859      	ldr	r1, [r3, #4]
- 800466c:	687b      	ldr	r3, [r7, #4]
- 800466e:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 8004670:	221c      	movs	r2, #28
- 8004672:	4013      	ands	r3, r2
- 8004674:	2201      	movs	r2, #1
- 8004676:	409a      	lsls	r2, r3
- 8004678:	4b0d      	ldr	r3, [pc, #52]	@ (80046b0 <HAL_DMA_IRQHandler+0x160>)
- 800467a:	430a      	orrs	r2, r1
- 800467c:	605a      	str	r2, [r3, #4]
-
-    /* Update error code */
-    hdma->ErrorCode = HAL_DMA_ERROR_TE;
- 800467e:	687b      	ldr	r3, [r7, #4]
- 8004680:	2201      	movs	r2, #1
- 8004682:	63da      	str	r2, [r3, #60]	@ 0x3c
-
-    /* Change the DMA state */
-    hdma->State = HAL_DMA_STATE_READY;
- 8004684:	687b      	ldr	r3, [r7, #4]
- 8004686:	2225      	movs	r2, #37	@ 0x25
- 8004688:	2101      	movs	r1, #1
- 800468a:	5499      	strb	r1, [r3, r2]
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
- 800468c:	687b      	ldr	r3, [r7, #4]
- 800468e:	2224      	movs	r2, #36	@ 0x24
- 8004690:	2100      	movs	r1, #0
- 8004692:	5499      	strb	r1, [r3, r2]
-
-    if (hdma->XferErrorCallback != NULL)
- 8004694:	687b      	ldr	r3, [r7, #4]
- 8004696:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 8004698:	2b00      	cmp	r3, #0
- 800469a:	d005      	beq.n	80046a8 <HAL_DMA_IRQHandler+0x158>
-    {
-      /* Transfer error callback */
-      hdma->XferErrorCallback(hdma);
- 800469c:	687b      	ldr	r3, [r7, #4]
- 800469e:	6b5b      	ldr	r3, [r3, #52]	@ 0x34
- 80046a0:	687a      	ldr	r2, [r7, #4]
- 80046a2:	0010      	movs	r0, r2
- 80046a4:	4798      	blx	r3
-  }
-  else
-  {
-    /* Nothing To Do */
-  }
-  return;
- 80046a6:	46c0      	nop			@ (mov r8, r8)
- 80046a8:	46c0      	nop			@ (mov r8, r8)
-}
- 80046aa:	46bd      	mov	sp, r7
- 80046ac:	b004      	add	sp, #16
- 80046ae:	bd80      	pop	{r7, pc}
- 80046b0:	40020000 	.word	0x40020000
-
-080046b4 <DMA_SetConfig>:
+08002e44 <DMA_SetConfig>:
   * @param DstAddress The destination memory Buffer address
   * @param DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
 {
- 80046b4:	b580      	push	{r7, lr}
- 80046b6:	b084      	sub	sp, #16
- 80046b8:	af00      	add	r7, sp, #0
- 80046ba:	60f8      	str	r0, [r7, #12]
- 80046bc:	60b9      	str	r1, [r7, #8]
- 80046be:	607a      	str	r2, [r7, #4]
- 80046c0:	603b      	str	r3, [r7, #0]
+ 8002e44:	b5f0      	push	{r4, r5, r6, r7, lr}
   /* Clear the DMAMUX synchro overrun flag */
   hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
- 80046c2:	68fb      	ldr	r3, [r7, #12]
- 80046c4:	6c9b      	ldr	r3, [r3, #72]	@ 0x48
- 80046c6:	68fa      	ldr	r2, [r7, #12]
- 80046c8:	6cd2      	ldr	r2, [r2, #76]	@ 0x4c
- 80046ca:	605a      	str	r2, [r3, #4]
+ 8002e46:	6c84      	ldr	r4, [r0, #72]	@ 0x48
+ 8002e48:	6cc5      	ldr	r5, [r0, #76]	@ 0x4c
+ 8002e4a:	6065      	str	r5, [r4, #4]
 
   if (hdma->DMAmuxRequestGen != 0U)
- 80046cc:	68fb      	ldr	r3, [r7, #12]
- 80046ce:	6d1b      	ldr	r3, [r3, #80]	@ 0x50
- 80046d0:	2b00      	cmp	r3, #0
- 80046d2:	d004      	beq.n	80046de <DMA_SetConfig+0x2a>
+ 8002e4c:	6d04      	ldr	r4, [r0, #80]	@ 0x50
+ 8002e4e:	2c00      	cmp	r4, #0
+ 8002e50:	d002      	beq.n	8002e58 <DMA_SetConfig+0x14>
   {
     /* Clear the DMAMUX request generator overrun flag */
     hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
- 80046d4:	68fb      	ldr	r3, [r7, #12]
- 80046d6:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
- 80046d8:	68fa      	ldr	r2, [r7, #12]
- 80046da:	6d92      	ldr	r2, [r2, #88]	@ 0x58
- 80046dc:	605a      	str	r2, [r3, #4]
+ 8002e52:	6d44      	ldr	r4, [r0, #84]	@ 0x54
+ 8002e54:	6d85      	ldr	r5, [r0, #88]	@ 0x58
+ 8002e56:	6065      	str	r5, [r4, #4]
   }
 
   /* Clear all flags */
   __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU)));
- 80046de:	4b14      	ldr	r3, [pc, #80]	@ (8004730 <DMA_SetConfig+0x7c>)
- 80046e0:	6859      	ldr	r1, [r3, #4]
- 80046e2:	68fb      	ldr	r3, [r7, #12]
- 80046e4:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 80046e6:	221c      	movs	r2, #28
- 80046e8:	4013      	ands	r3, r2
- 80046ea:	2201      	movs	r2, #1
- 80046ec:	409a      	lsls	r2, r3
- 80046ee:	4b10      	ldr	r3, [pc, #64]	@ (8004730 <DMA_SetConfig+0x7c>)
- 80046f0:	430a      	orrs	r2, r1
- 80046f2:	605a      	str	r2, [r3, #4]
+ 8002e58:	241c      	movs	r4, #28
+ 8002e5a:	6c05      	ldr	r5, [r0, #64]	@ 0x40
+ 8002e5c:	4e08      	ldr	r6, [pc, #32]	@ (8002e80 <DMA_SetConfig+0x3c>)
+ 8002e5e:	4025      	ands	r5, r4
+ 8002e60:	3c1b      	subs	r4, #27
+ 8002e62:	40ac      	lsls	r4, r5
+ 8002e64:	6877      	ldr	r7, [r6, #4]
+ 8002e66:	433c      	orrs	r4, r7
+ 8002e68:	6074      	str	r4, [r6, #4]
 
   /* Configure DMA Channel data length */
   hdma->Instance->CNDTR = DataLength;
- 80046f4:	68fb      	ldr	r3, [r7, #12]
- 80046f6:	681b      	ldr	r3, [r3, #0]
- 80046f8:	683a      	ldr	r2, [r7, #0]
- 80046fa:	605a      	str	r2, [r3, #4]
+ 8002e6a:	6804      	ldr	r4, [r0, #0]
+ 8002e6c:	6063      	str	r3, [r4, #4]
 
   /* Peripheral to Memory */
   if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
- 80046fc:	68fb      	ldr	r3, [r7, #12]
- 80046fe:	689b      	ldr	r3, [r3, #8]
- 8004700:	2b10      	cmp	r3, #16
- 8004702:	d108      	bne.n	8004716 <DMA_SetConfig+0x62>
+ 8002e6e:	6883      	ldr	r3, [r0, #8]
+ 8002e70:	2b10      	cmp	r3, #16
+ 8002e72:	d102      	bne.n	8002e7a <DMA_SetConfig+0x36>
   {
     /* Configure DMA Channel destination address */
     hdma->Instance->CPAR = DstAddress;
- 8004704:	68fb      	ldr	r3, [r7, #12]
- 8004706:	681b      	ldr	r3, [r3, #0]
- 8004708:	687a      	ldr	r2, [r7, #4]
- 800470a:	609a      	str	r2, [r3, #8]
+ 8002e74:	60a2      	str	r2, [r4, #8]
 
     /* Configure DMA Channel source address */
     hdma->Instance->CMAR = SrcAddress;
- 800470c:	68fb      	ldr	r3, [r7, #12]
- 800470e:	681b      	ldr	r3, [r3, #0]
- 8004710:	68ba      	ldr	r2, [r7, #8]
- 8004712:	60da      	str	r2, [r3, #12]
+ 8002e76:	60e1      	str	r1, [r4, #12]
     hdma->Instance->CPAR = SrcAddress;
 
     /* Configure DMA Channel destination address */
     hdma->Instance->CMAR = DstAddress;
   }
 }
- 8004714:	e007      	b.n	8004726 <DMA_SetConfig+0x72>
+ 8002e78:	bdf0      	pop	{r4, r5, r6, r7, pc}
     hdma->Instance->CPAR = SrcAddress;
- 8004716:	68fb      	ldr	r3, [r7, #12]
- 8004718:	681b      	ldr	r3, [r3, #0]
- 800471a:	68ba      	ldr	r2, [r7, #8]
- 800471c:	609a      	str	r2, [r3, #8]
+ 8002e7a:	60a1      	str	r1, [r4, #8]
     hdma->Instance->CMAR = DstAddress;
- 800471e:	68fb      	ldr	r3, [r7, #12]
- 8004720:	681b      	ldr	r3, [r3, #0]
- 8004722:	687a      	ldr	r2, [r7, #4]
- 8004724:	60da      	str	r2, [r3, #12]
+ 8002e7c:	60e2      	str	r2, [r4, #12]
 }
- 8004726:	46c0      	nop			@ (mov r8, r8)
- 8004728:	46bd      	mov	sp, r7
- 800472a:	b004      	add	sp, #16
- 800472c:	bd80      	pop	{r7, pc}
- 800472e:	46c0      	nop			@ (mov r8, r8)
- 8004730:	40020000 	.word	0x40020000
+ 8002e7e:	e7fb      	b.n	8002e78 <DMA_SetConfig+0x34>
+ 8002e80:	40020000 	.word	0x40020000
 
-08004734 <DMA_CalcDMAMUXChannelBaseAndMask>:
+08002e84 <DMA_CalcDMAMUXChannelBaseAndMask>:
   * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
   *                     the configuration information for the specified DMA Stream.
   * @retval None
   */
 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
 {
- 8004734:	b580      	push	{r7, lr}
- 8004736:	b084      	sub	sp, #16
- 8004738:	af00      	add	r7, sp, #0
- 800473a:	6078      	str	r0, [r7, #4]
+ 8002e84:	b510      	push	{r4, lr}
+ 8002e86:	0004      	movs	r4, r0
   uint32_t channel_number;
 
   channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
- 800473c:	687b      	ldr	r3, [r7, #4]
- 800473e:	681b      	ldr	r3, [r3, #0]
- 8004740:	001a      	movs	r2, r3
- 8004742:	23ff      	movs	r3, #255	@ 0xff
- 8004744:	4013      	ands	r3, r2
- 8004746:	3b08      	subs	r3, #8
- 8004748:	2114      	movs	r1, #20
- 800474a:	0018      	movs	r0, r3
- 800474c:	f7fb fcdc 	bl	8000108 <__udivsi3>
- 8004750:	0003      	movs	r3, r0
- 8004752:	60fb      	str	r3, [r7, #12]
+ 8002e88:	6800      	ldr	r0, [r0, #0]
+ 8002e8a:	2114      	movs	r1, #20
+ 8002e8c:	b2c0      	uxtb	r0, r0
+ 8002e8e:	3808      	subs	r0, #8
+ 8002e90:	f7fd f94e 	bl	8000130 <__udivsi3>
   hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \
                                                              ((hdma->ChannelIndex >> 2U) * \
- 8004754:	687b      	ldr	r3, [r7, #4]
- 8004756:	6c1b      	ldr	r3, [r3, #64]	@ 0x40
- 8004758:	089b      	lsrs	r3, r3, #2
+ 8002e94:	6c23      	ldr	r3, [r4, #64]	@ 0x40
   hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \
- 800475a:	4a0a      	ldr	r2, [pc, #40]	@ (8004784 <DMA_CalcDMAMUXChannelBaseAndMask+0x50>)
- 800475c:	4694      	mov	ip, r2
- 800475e:	4463      	add	r3, ip
- 8004760:	009b      	lsls	r3, r3, #2
- 8004762:	001a      	movs	r2, r3
- 8004764:	687b      	ldr	r3, [r7, #4]
- 8004766:	645a      	str	r2, [r3, #68]	@ 0x44
+ 8002e96:	4a06      	ldr	r2, [pc, #24]	@ (8002eb0 <DMA_CalcDMAMUXChannelBaseAndMask+0x2c>)
+                                                             ((hdma->ChannelIndex >> 2U) * \
+ 8002e98:	089b      	lsrs	r3, r3, #2
+  hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + \
+ 8002e9a:	189b      	adds	r3, r3, r2
+ 8002e9c:	009b      	lsls	r3, r3, #2
+ 8002e9e:	6463      	str	r3, [r4, #68]	@ 0x44
                                                               ((uint32_t)DMAMUX1_Channel1 - \
                                                                (uint32_t)DMAMUX1_Channel0)));
   hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
- 8004768:	687b      	ldr	r3, [r7, #4]
- 800476a:	4a07      	ldr	r2, [pc, #28]	@ (8004788 <DMA_CalcDMAMUXChannelBaseAndMask+0x54>)
- 800476c:	649a      	str	r2, [r3, #72]	@ 0x48
+ 8002ea0:	4b04      	ldr	r3, [pc, #16]	@ (8002eb4 <DMA_CalcDMAMUXChannelBaseAndMask+0x30>)
+ 8002ea2:	64a3      	str	r3, [r4, #72]	@ 0x48
   hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU);
- 800476e:	68fb      	ldr	r3, [r7, #12]
- 8004770:	221c      	movs	r2, #28
- 8004772:	4013      	ands	r3, r2
- 8004774:	2201      	movs	r2, #1
- 8004776:	409a      	lsls	r2, r3
- 8004778:	687b      	ldr	r3, [r7, #4]
- 800477a:	64da      	str	r2, [r3, #76]	@ 0x4c
+ 8002ea4:	231c      	movs	r3, #28
+ 8002ea6:	4018      	ands	r0, r3
+ 8002ea8:	3b1b      	subs	r3, #27
+ 8002eaa:	4083      	lsls	r3, r0
+ 8002eac:	64e3      	str	r3, [r4, #76]	@ 0x4c
 }
- 800477c:	46c0      	nop			@ (mov r8, r8)
- 800477e:	46bd      	mov	sp, r7
- 8004780:	b004      	add	sp, #16
- 8004782:	bd80      	pop	{r7, pc}
- 8004784:	10008200 	.word	0x10008200
- 8004788:	40020880 	.word	0x40020880
-
-0800478c <DMA_CalcDMAMUXRequestGenBaseAndMask>:
-  *                     the configuration information for the specified DMA Stream.
-  * @retval None
-  */
+ 8002eae:	bd10      	pop	{r4, pc}
+ 8002eb0:	10008200 	.word	0x10008200
+ 8002eb4:	40020880 	.word	0x40020880
 
+08002eb8 <HAL_DMA_Init>:
+{
+ 8002eb8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8002eba:	0004      	movs	r4, r0
+    return HAL_ERROR;
+ 8002ebc:	2001      	movs	r0, #1
+  if (hdma == NULL)
+ 8002ebe:	2c00      	cmp	r4, #0
+ 8002ec0:	d045      	beq.n	8002f4e <HAL_DMA_Init+0x96>
+  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \
+ 8002ec2:	6825      	ldr	r5, [r4, #0]
+ 8002ec4:	4b25      	ldr	r3, [pc, #148]	@ (8002f5c <HAL_DMA_Init+0xa4>)
+ 8002ec6:	2114      	movs	r1, #20
+ 8002ec8:	18e8      	adds	r0, r5, r3
+ 8002eca:	f7fd f931 	bl	8000130 <__udivsi3>
+  hdma->State = HAL_DMA_STATE_BUSY;
+ 8002ece:	2302      	movs	r3, #2
+                                                                                (uint32_t)DMA1_Channel1)) << 2U;
+ 8002ed0:	0080      	lsls	r0, r0, #2
+  hdma->State = HAL_DMA_STATE_BUSY;
+ 8002ed2:	1da6      	adds	r6, r4, #6
+  hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - \
+ 8002ed4:	6420      	str	r0, [r4, #64]	@ 0x40
+  hdma->State = HAL_DMA_STATE_BUSY;
+ 8002ed6:	77f3      	strb	r3, [r6, #31]
+  CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
+ 8002ed8:	682b      	ldr	r3, [r5, #0]
+ 8002eda:	4a21      	ldr	r2, [pc, #132]	@ (8002f60 <HAL_DMA_Init+0xa8>)
+  SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction           |                               \
+ 8002edc:	68a7      	ldr	r7, [r4, #8]
+  CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
+ 8002ede:	4013      	ands	r3, r2
+ 8002ee0:	602b      	str	r3, [r5, #0]
+  SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction           |                               \
+ 8002ee2:	68e3      	ldr	r3, [r4, #12]
+ 8002ee4:	6921      	ldr	r1, [r4, #16]
+ 8002ee6:	433b      	orrs	r3, r7
+ 8002ee8:	430b      	orrs	r3, r1
+ 8002eea:	6961      	ldr	r1, [r4, #20]
+ 8002eec:	682a      	ldr	r2, [r5, #0]
+ 8002eee:	430b      	orrs	r3, r1
+ 8002ef0:	69a1      	ldr	r1, [r4, #24]
+  DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+ 8002ef2:	0020      	movs	r0, r4
+  SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction           |                               \
+ 8002ef4:	430b      	orrs	r3, r1
+ 8002ef6:	69e1      	ldr	r1, [r4, #28]
+ 8002ef8:	430b      	orrs	r3, r1
+ 8002efa:	6a21      	ldr	r1, [r4, #32]
+ 8002efc:	430b      	orrs	r3, r1
+ 8002efe:	4313      	orrs	r3, r2
+ 8002f00:	602b      	str	r3, [r5, #0]
+  DMA_CalcDMAMUXChannelBaseAndMask(hdma);
+ 8002f02:	f7ff ffbf 	bl	8002e84 <DMA_CalcDMAMUXChannelBaseAndMask>
+  if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
+ 8002f06:	2380      	movs	r3, #128	@ 0x80
+ 8002f08:	01db      	lsls	r3, r3, #7
+ 8002f0a:	429f      	cmp	r7, r3
+ 8002f0c:	d101      	bne.n	8002f12 <HAL_DMA_Init+0x5a>
+    hdma->Init.Request = DMA_REQUEST_MEM2MEM;
+ 8002f0e:	2300      	movs	r3, #0
+ 8002f10:	6063      	str	r3, [r4, #4]
+  hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID);
+ 8002f12:	6862      	ldr	r2, [r4, #4]
+ 8002f14:	6c61      	ldr	r1, [r4, #68]	@ 0x44
+ 8002f16:	b2d3      	uxtb	r3, r2
+ 8002f18:	600b      	str	r3, [r1, #0]
+  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 8002f1a:	6ce0      	ldr	r0, [r4, #76]	@ 0x4c
+ 8002f1c:	6ca1      	ldr	r1, [r4, #72]	@ 0x48
+  if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
+ 8002f1e:	3a01      	subs	r2, #1
+  hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 8002f20:	6048      	str	r0, [r1, #4]
+  if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3)))
+ 8002f22:	2a03      	cmp	r2, #3
+ 8002f24:	d814      	bhi.n	8002f50 <HAL_DMA_Init+0x98>
 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
 {
- 800478c:	b580      	push	{r7, lr}
- 800478e:	b084      	sub	sp, #16
- 8004790:	af00      	add	r7, sp, #0
- 8004792:	6078      	str	r0, [r7, #4]
   uint32_t request =  hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
- 8004794:	687b      	ldr	r3, [r7, #4]
- 8004796:	685b      	ldr	r3, [r3, #4]
- 8004798:	22ff      	movs	r2, #255	@ 0xff
- 800479a:	4013      	ands	r3, r2
- 800479c:	60fb      	str	r3, [r7, #12]
 
   /* DMA Channels are connected to DMAMUX1 request generator blocks*/
   hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \
- 800479e:	68fb      	ldr	r3, [r7, #12]
- 80047a0:	4a0a      	ldr	r2, [pc, #40]	@ (80047cc <DMA_CalcDMAMUXRequestGenBaseAndMask+0x40>)
- 80047a2:	4694      	mov	ip, r2
- 80047a4:	4463      	add	r3, ip
- 80047a6:	009b      	lsls	r3, r3, #2
- 80047a8:	001a      	movs	r2, r3
- 80047aa:	687b      	ldr	r3, [r7, #4]
- 80047ac:	651a      	str	r2, [r3, #80]	@ 0x50
+ 8002f26:	4a0f      	ldr	r2, [pc, #60]	@ (8002f64 <HAL_DMA_Init+0xac>)
                                                                     ((request - 1U) * 4U)));
 
   hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
- 80047ae:	687b      	ldr	r3, [r7, #4]
- 80047b0:	4a07      	ldr	r2, [pc, #28]	@ (80047d0 <DMA_CalcDMAMUXRequestGenBaseAndMask+0x44>)
- 80047b2:	655a      	str	r2, [r3, #84]	@ 0x54
+ 8002f28:	480f      	ldr	r0, [pc, #60]	@ (8002f68 <HAL_DMA_Init+0xb0>)
+  hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \
+ 8002f2a:	1899      	adds	r1, r3, r2
 
   /* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/
   hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
- 80047b4:	68fb      	ldr	r3, [r7, #12]
- 80047b6:	3b01      	subs	r3, #1
- 80047b8:	2203      	movs	r2, #3
- 80047ba:	4013      	ands	r3, r2
- 80047bc:	2201      	movs	r2, #1
- 80047be:	409a      	lsls	r2, r3
- 80047c0:	687b      	ldr	r3, [r7, #4]
- 80047c2:	659a      	str	r2, [r3, #88]	@ 0x58
+ 8002f2c:	2201      	movs	r2, #1
+ 8002f2e:	3b01      	subs	r3, #1
+ 8002f30:	409a      	lsls	r2, r3
+ 8002f32:	65a2      	str	r2, [r4, #88]	@ 0x58
+ 8002f34:	0013      	movs	r3, r2
+    hdma->DMAmuxRequestGen->RGCR = 0U;
+ 8002f36:	2200      	movs	r2, #0
+  hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + \
+ 8002f38:	0089      	lsls	r1, r1, #2
+ 8002f3a:	6521      	str	r1, [r4, #80]	@ 0x50
+  hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
+ 8002f3c:	6560      	str	r0, [r4, #84]	@ 0x54
+    hdma->DMAmuxRequestGen->RGCR = 0U;
+ 8002f3e:	600a      	str	r2, [r1, #0]
+    hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 8002f40:	6043      	str	r3, [r0, #4]
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 8002f42:	2000      	movs	r0, #0
+  hdma->State  = HAL_DMA_STATE_READY;
+ 8002f44:	2301      	movs	r3, #1
+  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 8002f46:	63e0      	str	r0, [r4, #60]	@ 0x3c
+  __HAL_UNLOCK(hdma);
+ 8002f48:	3405      	adds	r4, #5
+  hdma->State  = HAL_DMA_STATE_READY;
+ 8002f4a:	77f3      	strb	r3, [r6, #31]
+  __HAL_UNLOCK(hdma);
+ 8002f4c:	77e0      	strb	r0, [r4, #31]
 }
- 80047c4:	46c0      	nop			@ (mov r8, r8)
- 80047c6:	46bd      	mov	sp, r7
- 80047c8:	b004      	add	sp, #16
- 80047ca:	bd80      	pop	{r7, pc}
- 80047cc:	1000823f 	.word	0x1000823f
- 80047d0:	40020940 	.word	0x40020940
+ 8002f4e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    hdma->DMAmuxRequestGen = 0U;
+ 8002f50:	2300      	movs	r3, #0
+ 8002f52:	6523      	str	r3, [r4, #80]	@ 0x50
+    hdma->DMAmuxRequestGenStatus = 0U;
+ 8002f54:	6563      	str	r3, [r4, #84]	@ 0x54
+    hdma->DMAmuxRequestGenStatusMask = 0U;
+ 8002f56:	65a3      	str	r3, [r4, #88]	@ 0x58
+ 8002f58:	e7f3      	b.n	8002f42 <HAL_DMA_Init+0x8a>
+ 8002f5a:	46c0      	nop			@ (mov r8, r8)
+ 8002f5c:	bffdfff8 	.word	0xbffdfff8
+ 8002f60:	ffff800f 	.word	0xffff800f
+ 8002f64:	1000823f 	.word	0x1000823f
+ 8002f68:	40020940 	.word	0x40020940
 
-080047d4 <HAL_GPIO_Init>:
-  * @param  pGPIO_Init pointer to a GPIO_InitTypeDef structure that contains
-  *         the configuration information for the specified GPIO peripheral.
-  * @retval None
+08002f6c <HAL_DMA_Start_IT>:
+{
+ 8002f6c:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+  __HAL_LOCK(hdma);
+ 8002f6e:	1d46      	adds	r6, r0, #5
+{
+ 8002f70:	9301      	str	r3, [sp, #4]
+  __HAL_LOCK(hdma);
+ 8002f72:	7ff4      	ldrb	r4, [r6, #31]
+{
+ 8002f74:	0005      	movs	r5, r0
+  __HAL_LOCK(hdma);
+ 8002f76:	2002      	movs	r0, #2
+ 8002f78:	2c01      	cmp	r4, #1
+ 8002f7a:	d036      	beq.n	8002fea <HAL_DMA_Start_IT+0x7e>
+ 8002f7c:	3801      	subs	r0, #1
+ 8002f7e:	77f0      	strb	r0, [r6, #31]
+  if (HAL_DMA_STATE_READY == hdma->State)
+ 8002f80:	1dac      	adds	r4, r5, #6
+ 8002f82:	7fe0      	ldrb	r0, [r4, #31]
+ 8002f84:	2702      	movs	r7, #2
+ 8002f86:	4684      	mov	ip, r0
+ 8002f88:	4663      	mov	r3, ip
+ 8002f8a:	b2c0      	uxtb	r0, r0
+ 8002f8c:	9000      	str	r0, [sp, #0]
+    status = HAL_BUSY;
+ 8002f8e:	0038      	movs	r0, r7
+  if (HAL_DMA_STATE_READY == hdma->State)
+ 8002f90:	2b01      	cmp	r3, #1
+ 8002f92:	d128      	bne.n	8002fe6 <HAL_DMA_Start_IT+0x7a>
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 8002f94:	2000      	movs	r0, #0
+    hdma->State = HAL_DMA_STATE_BUSY;
+ 8002f96:	77e7      	strb	r7, [r4, #31]
+    __HAL_DMA_DISABLE(hdma);
+ 8002f98:	682c      	ldr	r4, [r5, #0]
+    hdma->ErrorCode = HAL_DMA_ERROR_NONE;
+ 8002f9a:	63e8      	str	r0, [r5, #60]	@ 0x3c
+    __HAL_DMA_DISABLE(hdma);
+ 8002f9c:	6820      	ldr	r0, [r4, #0]
+ 8002f9e:	9b00      	ldr	r3, [sp, #0]
+ 8002fa0:	4398      	bics	r0, r3
+ 8002fa2:	6020      	str	r0, [r4, #0]
+    DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
+ 8002fa4:	9b01      	ldr	r3, [sp, #4]
+ 8002fa6:	0028      	movs	r0, r5
+ 8002fa8:	f7ff ff4c 	bl	8002e44 <DMA_SetConfig>
+    if (NULL != hdma->XferHalfCpltCallback)
+ 8002fac:	6b2b      	ldr	r3, [r5, #48]	@ 0x30
+ 8002fae:	2b00      	cmp	r3, #0
+ 8002fb0:	d01c      	beq.n	8002fec <HAL_DMA_Start_IT+0x80>
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 8002fb2:	230e      	movs	r3, #14
+ 8002fb4:	6822      	ldr	r2, [r4, #0]
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
+ 8002fb6:	4313      	orrs	r3, r2
+ 8002fb8:	6023      	str	r3, [r4, #0]
+    if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U)
+ 8002fba:	6c6b      	ldr	r3, [r5, #68]	@ 0x44
+ 8002fbc:	681a      	ldr	r2, [r3, #0]
+ 8002fbe:	03d2      	lsls	r2, r2, #15
+ 8002fc0:	d504      	bpl.n	8002fcc <HAL_DMA_Start_IT+0x60>
+      hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE;
+ 8002fc2:	2280      	movs	r2, #128	@ 0x80
+ 8002fc4:	6819      	ldr	r1, [r3, #0]
+ 8002fc6:	0052      	lsls	r2, r2, #1
+ 8002fc8:	430a      	orrs	r2, r1
+ 8002fca:	601a      	str	r2, [r3, #0]
+    if (hdma->DMAmuxRequestGen != 0U)
+ 8002fcc:	6d2b      	ldr	r3, [r5, #80]	@ 0x50
+ 8002fce:	2b00      	cmp	r3, #0
+ 8002fd0:	d004      	beq.n	8002fdc <HAL_DMA_Start_IT+0x70>
+      hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
+ 8002fd2:	2280      	movs	r2, #128	@ 0x80
+ 8002fd4:	6819      	ldr	r1, [r3, #0]
+ 8002fd6:	0052      	lsls	r2, r2, #1
+ 8002fd8:	430a      	orrs	r2, r1
+ 8002fda:	601a      	str	r2, [r3, #0]
+    __HAL_DMA_ENABLE(hdma);
+ 8002fdc:	2301      	movs	r3, #1
+  HAL_StatusTypeDef status = HAL_OK;
+ 8002fde:	2000      	movs	r0, #0
+    __HAL_DMA_ENABLE(hdma);
+ 8002fe0:	6822      	ldr	r2, [r4, #0]
+ 8002fe2:	4313      	orrs	r3, r2
+ 8002fe4:	6023      	str	r3, [r4, #0]
+  __HAL_UNLOCK(hdma);
+ 8002fe6:	2300      	movs	r3, #0
+ 8002fe8:	77f3      	strb	r3, [r6, #31]
+}
+ 8002fea:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ 8002fec:	2204      	movs	r2, #4
+ 8002fee:	6823      	ldr	r3, [r4, #0]
+ 8002ff0:	4393      	bics	r3, r2
+ 8002ff2:	6023      	str	r3, [r4, #0]
+      __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE));
+ 8002ff4:	6822      	ldr	r2, [r4, #0]
+ 8002ff6:	230a      	movs	r3, #10
+ 8002ff8:	e7dd      	b.n	8002fb6 <HAL_DMA_Start_IT+0x4a>
+	...
+
+08002ffc <HAL_DMA_Abort>:
+{
+ 8002ffc:	b5f0      	push	{r4, r5, r6, r7, lr}
+  if (NULL == hdma)
+ 8002ffe:	2800      	cmp	r0, #0
+ 8003000:	d008      	beq.n	8003014 <HAL_DMA_Abort+0x18>
+  if (hdma->State != HAL_DMA_STATE_BUSY)
+ 8003002:	1d84      	adds	r4, r0, #6
+ 8003004:	7fe3      	ldrb	r3, [r4, #31]
+ 8003006:	1d41      	adds	r1, r0, #5
+ 8003008:	2b02      	cmp	r3, #2
+ 800300a:	d005      	beq.n	8003018 <HAL_DMA_Abort+0x1c>
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 800300c:	2304      	movs	r3, #4
+ 800300e:	63c3      	str	r3, [r0, #60]	@ 0x3c
+    __HAL_UNLOCK(hdma);
+ 8003010:	2300      	movs	r3, #0
+ 8003012:	77cb      	strb	r3, [r1, #31]
+    return HAL_ERROR;
+ 8003014:	2001      	movs	r0, #1
+}
+ 8003016:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 8003018:	250e      	movs	r5, #14
+ 800301a:	6802      	ldr	r2, [r0, #0]
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+ 800301c:	6c46      	ldr	r6, [r0, #68]	@ 0x44
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 800301e:	6813      	ldr	r3, [r2, #0]
+ 8003020:	43ab      	bics	r3, r5
+ 8003022:	6013      	str	r3, [r2, #0]
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+ 8003024:	6833      	ldr	r3, [r6, #0]
+ 8003026:	4d10      	ldr	r5, [pc, #64]	@ (8003068 <HAL_DMA_Abort+0x6c>)
+ 8003028:	402b      	ands	r3, r5
+ 800302a:	6033      	str	r3, [r6, #0]
+    __HAL_DMA_DISABLE(hdma);
+ 800302c:	2301      	movs	r3, #1
+ 800302e:	6816      	ldr	r6, [r2, #0]
+ 8003030:	439e      	bics	r6, r3
+ 8003032:	6016      	str	r6, [r2, #0]
+    __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex  & 0x1cU)));
+ 8003034:	6c02      	ldr	r2, [r0, #64]	@ 0x40
+ 8003036:	331b      	adds	r3, #27
+ 8003038:	401a      	ands	r2, r3
+ 800303a:	3b1b      	subs	r3, #27
+ 800303c:	4093      	lsls	r3, r2
+ 800303e:	4e0b      	ldr	r6, [pc, #44]	@ (800306c <HAL_DMA_Abort+0x70>)
+ 8003040:	6877      	ldr	r7, [r6, #4]
+ 8003042:	433b      	orrs	r3, r7
+ 8003044:	6073      	str	r3, [r6, #4]
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 8003046:	6cc2      	ldr	r2, [r0, #76]	@ 0x4c
+ 8003048:	6c83      	ldr	r3, [r0, #72]	@ 0x48
+ 800304a:	605a      	str	r2, [r3, #4]
+    if (hdma->DMAmuxRequestGen != 0U)
+ 800304c:	6d03      	ldr	r3, [r0, #80]	@ 0x50
+ 800304e:	2b00      	cmp	r3, #0
+ 8003050:	d005      	beq.n	800305e <HAL_DMA_Abort+0x62>
+      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+ 8003052:	681a      	ldr	r2, [r3, #0]
+ 8003054:	402a      	ands	r2, r5
+ 8003056:	601a      	str	r2, [r3, #0]
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 8003058:	6d43      	ldr	r3, [r0, #84]	@ 0x54
+ 800305a:	6d82      	ldr	r2, [r0, #88]	@ 0x58
+ 800305c:	605a      	str	r2, [r3, #4]
+    hdma->State = HAL_DMA_STATE_READY;
+ 800305e:	2301      	movs	r3, #1
+    __HAL_UNLOCK(hdma);
+ 8003060:	2000      	movs	r0, #0
+    hdma->State = HAL_DMA_STATE_READY;
+ 8003062:	77e3      	strb	r3, [r4, #31]
+    __HAL_UNLOCK(hdma);
+ 8003064:	77c8      	strb	r0, [r1, #31]
+  return HAL_OK;
+ 8003066:	e7d6      	b.n	8003016 <HAL_DMA_Abort+0x1a>
+ 8003068:	fffffeff 	.word	0xfffffeff
+ 800306c:	40020000 	.word	0x40020000
+
+08003070 <HAL_DMA_Abort_IT>:
+{
+ 8003070:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+  __HAL_LOCK(hdma);
+ 8003072:	2301      	movs	r3, #1
+ 8003074:	1d41      	adds	r1, r0, #5
+ 8003076:	77cb      	strb	r3, [r1, #31]
+  if (HAL_DMA_STATE_BUSY != hdma->State)
+ 8003078:	1d84      	adds	r4, r0, #6
+ 800307a:	7fe2      	ldrb	r2, [r4, #31]
+ 800307c:	2a02      	cmp	r2, #2
+ 800307e:	d003      	beq.n	8003088 <HAL_DMA_Abort_IT+0x18>
+    hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
+ 8003080:	2204      	movs	r2, #4
+ 8003082:	63c2      	str	r2, [r0, #60]	@ 0x3c
+    status = HAL_ERROR;
+ 8003084:	0018      	movs	r0, r3
+}
+ 8003086:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 8003088:	260e      	movs	r6, #14
+ 800308a:	6802      	ldr	r2, [r0, #0]
+ 800308c:	6815      	ldr	r5, [r2, #0]
+ 800308e:	43b5      	bics	r5, r6
+ 8003090:	6015      	str	r5, [r2, #0]
+    __HAL_DMA_DISABLE(hdma);
+ 8003092:	6815      	ldr	r5, [r2, #0]
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+ 8003094:	6c46      	ldr	r6, [r0, #68]	@ 0x44
+    __HAL_DMA_DISABLE(hdma);
+ 8003096:	439d      	bics	r5, r3
+ 8003098:	6015      	str	r5, [r2, #0]
+    hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE;
+ 800309a:	6832      	ldr	r2, [r6, #0]
+ 800309c:	4d11      	ldr	r5, [pc, #68]	@ (80030e4 <HAL_DMA_Abort_IT+0x74>)
+ 800309e:	402a      	ands	r2, r5
+ 80030a0:	6032      	str	r2, [r6, #0]
+    __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1cU)));
+ 80030a2:	6c02      	ldr	r2, [r0, #64]	@ 0x40
+ 80030a4:	4e10      	ldr	r6, [pc, #64]	@ (80030e8 <HAL_DMA_Abort_IT+0x78>)
+ 80030a6:	0015      	movs	r5, r2
+ 80030a8:	221c      	movs	r2, #28
+ 80030aa:	4015      	ands	r5, r2
+ 80030ac:	40ab      	lsls	r3, r5
+ 80030ae:	6877      	ldr	r7, [r6, #4]
+ 80030b0:	433b      	orrs	r3, r7
+ 80030b2:	6073      	str	r3, [r6, #4]
+    hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
+ 80030b4:	6cc2      	ldr	r2, [r0, #76]	@ 0x4c
+ 80030b6:	6c83      	ldr	r3, [r0, #72]	@ 0x48
+ 80030b8:	605a      	str	r2, [r3, #4]
+    if (hdma->DMAmuxRequestGen != 0U)
+ 80030ba:	6d03      	ldr	r3, [r0, #80]	@ 0x50
+ 80030bc:	2b00      	cmp	r3, #0
+ 80030be:	d006      	beq.n	80030ce <HAL_DMA_Abort_IT+0x5e>
+      hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE;
+ 80030c0:	681a      	ldr	r2, [r3, #0]
+ 80030c2:	4d08      	ldr	r5, [pc, #32]	@ (80030e4 <HAL_DMA_Abort_IT+0x74>)
+ 80030c4:	402a      	ands	r2, r5
+ 80030c6:	601a      	str	r2, [r3, #0]
+      hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
+ 80030c8:	6d43      	ldr	r3, [r0, #84]	@ 0x54
+ 80030ca:	6d82      	ldr	r2, [r0, #88]	@ 0x58
+ 80030cc:	605a      	str	r2, [r3, #4]
+    hdma->State = HAL_DMA_STATE_READY;
+ 80030ce:	2301      	movs	r3, #1
+ 80030d0:	77e3      	strb	r3, [r4, #31]
+    __HAL_UNLOCK(hdma);
+ 80030d2:	2300      	movs	r3, #0
+ 80030d4:	77cb      	strb	r3, [r1, #31]
+    if (hdma->XferAbortCallback != NULL)
+ 80030d6:	6b83      	ldr	r3, [r0, #56]	@ 0x38
+ 80030d8:	2b00      	cmp	r3, #0
+ 80030da:	d000      	beq.n	80030de <HAL_DMA_Abort_IT+0x6e>
+      hdma->XferAbortCallback(hdma);
+ 80030dc:	4798      	blx	r3
+  HAL_StatusTypeDef status = HAL_OK;
+ 80030de:	2000      	movs	r0, #0
+ 80030e0:	e7d1      	b.n	8003086 <HAL_DMA_Abort_IT+0x16>
+ 80030e2:	46c0      	nop			@ (mov r8, r8)
+ 80030e4:	fffffeff 	.word	0xfffffeff
+ 80030e8:	40020000 	.word	0x40020000
+
+080030ec <HAL_DMA_IRQHandler>:
+{
+ 80030ec:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+  if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
+ 80030ee:	241c      	movs	r4, #28
+ 80030f0:	2704      	movs	r7, #4
+ 80030f2:	6c01      	ldr	r1, [r0, #64]	@ 0x40
+  uint32_t flag_it = DMA1->ISR;
+ 80030f4:	4a26      	ldr	r2, [pc, #152]	@ (8003190 <HAL_DMA_IRQHandler+0xa4>)
+  if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
+ 80030f6:	4021      	ands	r1, r4
+ 80030f8:	003c      	movs	r4, r7
+ 80030fa:	408c      	lsls	r4, r1
+  uint32_t flag_it = DMA1->ISR;
+ 80030fc:	6816      	ldr	r6, [r2, #0]
+  uint32_t source_it = hdma->Instance->CCR;
+ 80030fe:	6803      	ldr	r3, [r0, #0]
+ 8003100:	681d      	ldr	r5, [r3, #0]
+  if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_HT) != 0U))
+ 8003102:	4226      	tst	r6, r4
+ 8003104:	d00f      	beq.n	8003126 <HAL_DMA_IRQHandler+0x3a>
+ 8003106:	423d      	tst	r5, r7
+ 8003108:	d00d      	beq.n	8003126 <HAL_DMA_IRQHandler+0x3a>
+    if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ 800310a:	6819      	ldr	r1, [r3, #0]
+ 800310c:	0689      	lsls	r1, r1, #26
+ 800310e:	d402      	bmi.n	8003116 <HAL_DMA_IRQHandler+0x2a>
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
+ 8003110:	6819      	ldr	r1, [r3, #0]
+ 8003112:	43b9      	bics	r1, r7
+ 8003114:	6019      	str	r1, [r3, #0]
+    __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)));
+ 8003116:	6853      	ldr	r3, [r2, #4]
+ 8003118:	431c      	orrs	r4, r3
+    if (hdma->XferHalfCpltCallback != NULL)
+ 800311a:	6b03      	ldr	r3, [r0, #48]	@ 0x30
+    __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)));
+ 800311c:	6054      	str	r4, [r2, #4]
+    if (hdma->XferHalfCpltCallback != NULL)
+ 800311e:	2b00      	cmp	r3, #0
+ 8003120:	d01b      	beq.n	800315a <HAL_DMA_IRQHandler+0x6e>
+      hdma->XferErrorCallback(hdma);
+ 8003122:	4798      	blx	r3
+  return;
+ 8003124:	e019      	b.n	800315a <HAL_DMA_IRQHandler+0x6e>
+  else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC)))
+ 8003126:	2702      	movs	r7, #2
+ 8003128:	003c      	movs	r4, r7
+ 800312a:	408c      	lsls	r4, r1
+ 800312c:	4226      	tst	r6, r4
+ 800312e:	d015      	beq.n	800315c <HAL_DMA_IRQHandler+0x70>
+ 8003130:	423d      	tst	r5, r7
+ 8003132:	d013      	beq.n	800315c <HAL_DMA_IRQHandler+0x70>
+    if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
+ 8003134:	6819      	ldr	r1, [r3, #0]
+ 8003136:	0689      	lsls	r1, r1, #26
+ 8003138:	d406      	bmi.n	8003148 <HAL_DMA_IRQHandler+0x5c>
+      __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
+ 800313a:	250a      	movs	r5, #10
+ 800313c:	6819      	ldr	r1, [r3, #0]
+ 800313e:	43a9      	bics	r1, r5
+ 8003140:	6019      	str	r1, [r3, #0]
+      hdma->State = HAL_DMA_STATE_READY;
+ 8003142:	2101      	movs	r1, #1
+ 8003144:	1d83      	adds	r3, r0, #6
+ 8003146:	77d9      	strb	r1, [r3, #31]
+    __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)));
+ 8003148:	6853      	ldr	r3, [r2, #4]
+ 800314a:	431c      	orrs	r4, r3
+ 800314c:	6054      	str	r4, [r2, #4]
+    __HAL_UNLOCK(hdma);
+ 800314e:	2200      	movs	r2, #0
+ 8003150:	1d43      	adds	r3, r0, #5
+ 8003152:	77da      	strb	r2, [r3, #31]
+    if (hdma->XferCpltCallback != NULL)
+ 8003154:	6ac3      	ldr	r3, [r0, #44]	@ 0x2c
+    if (hdma->XferErrorCallback != NULL)
+ 8003156:	4293      	cmp	r3, r2
+ 8003158:	d1e3      	bne.n	8003122 <HAL_DMA_IRQHandler+0x36>
+}
+ 800315a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+  else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TE) != 0U))
+ 800315c:	2408      	movs	r4, #8
+ 800315e:	0027      	movs	r7, r4
+ 8003160:	408f      	lsls	r7, r1
+ 8003162:	423e      	tst	r6, r7
+ 8003164:	d0f9      	beq.n	800315a <HAL_DMA_IRQHandler+0x6e>
+ 8003166:	4225      	tst	r5, r4
+ 8003168:	d0f7      	beq.n	800315a <HAL_DMA_IRQHandler+0x6e>
+    __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
+ 800316a:	250e      	movs	r5, #14
+ 800316c:	681c      	ldr	r4, [r3, #0]
+ 800316e:	43ac      	bics	r4, r5
+ 8003170:	601c      	str	r4, [r3, #0]
+    __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1cU)));
+ 8003172:	2301      	movs	r3, #1
+ 8003174:	001d      	movs	r5, r3
+ 8003176:	408d      	lsls	r5, r1
+ 8003178:	0029      	movs	r1, r5
+ 800317a:	6854      	ldr	r4, [r2, #4]
+ 800317c:	4321      	orrs	r1, r4
+ 800317e:	6051      	str	r1, [r2, #4]
+    hdma->State = HAL_DMA_STATE_READY;
+ 8003180:	1d82      	adds	r2, r0, #6
+    hdma->ErrorCode = HAL_DMA_ERROR_TE;
+ 8003182:	63c3      	str	r3, [r0, #60]	@ 0x3c
+    hdma->State = HAL_DMA_STATE_READY;
+ 8003184:	77d3      	strb	r3, [r2, #31]
+    __HAL_UNLOCK(hdma);
+ 8003186:	2200      	movs	r2, #0
+ 8003188:	1d43      	adds	r3, r0, #5
+ 800318a:	77da      	strb	r2, [r3, #31]
+    if (hdma->XferErrorCallback != NULL)
+ 800318c:	6b43      	ldr	r3, [r0, #52]	@ 0x34
+ 800318e:	e7e2      	b.n	8003156 <HAL_DMA_IRQHandler+0x6a>
+ 8003190:	40020000 	.word	0x40020000
+
+08003194 <HAL_GPIO_Init>:
   */
 void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, const GPIO_InitTypeDef *pGPIO_Init)
 {
- 80047d4:	b580      	push	{r7, lr}
- 80047d6:	b086      	sub	sp, #24
- 80047d8:	af00      	add	r7, sp, #0
- 80047da:	6078      	str	r0, [r7, #4]
- 80047dc:	6039      	str	r1, [r7, #0]
   uint32_t tmp;
   uint32_t iocurrent;
   uint32_t position = 0U;
- 80047de:	2300      	movs	r3, #0
- 80047e0:	613b      	str	r3, [r7, #16]
+ 8003194:	2300      	movs	r3, #0
+ 8003196:	469c      	mov	ip, r3
+{
+ 8003198:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 800319a:	b085      	sub	sp, #20
   assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
   assert_param(IS_GPIO_PIN(pGPIO_Init->Pin));
   assert_param(IS_GPIO_MODE(pGPIO_Init->Mode));
 
   /* Configure the port pins */
   while (((pGPIO_Init->Pin) >> position) != 0U)
- 80047e2:	e153      	b.n	8004a8c <HAL_GPIO_Init+0x2b8>
-  {
-    /* Get current io position */
-    iocurrent = (pGPIO_Init->Pin) & (1UL << position);
- 80047e4:	683b      	ldr	r3, [r7, #0]
- 80047e6:	681b      	ldr	r3, [r3, #0]
- 80047e8:	2101      	movs	r1, #1
- 80047ea:	693a      	ldr	r2, [r7, #16]
- 80047ec:	4091      	lsls	r1, r2
- 80047ee:	000a      	movs	r2, r1
- 80047f0:	4013      	ands	r3, r2
- 80047f2:	60fb      	str	r3, [r7, #12]
-
-    if (iocurrent != 0U)
- 80047f4:	68fb      	ldr	r3, [r7, #12]
- 80047f6:	2b00      	cmp	r3, #0
- 80047f8:	d100      	bne.n	80047fc <HAL_GPIO_Init+0x28>
- 80047fa:	e144      	b.n	8004a86 <HAL_GPIO_Init+0x2b2>
-    {
-      /*--------------------- GPIO Mode Configuration ------------------------*/
-      /* In case of Alternate function mode selection */
-      if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD))
- 80047fc:	683b      	ldr	r3, [r7, #0]
- 80047fe:	685b      	ldr	r3, [r3, #4]
- 8004800:	2b02      	cmp	r3, #2
- 8004802:	d003      	beq.n	800480c <HAL_GPIO_Init+0x38>
- 8004804:	683b      	ldr	r3, [r7, #0]
- 8004806:	685b      	ldr	r3, [r3, #4]
- 8004808:	2b12      	cmp	r3, #18
- 800480a:	d125      	bne.n	8004858 <HAL_GPIO_Init+0x84>
-        /* Check the Alternate function parameters */
-        assert_param(IS_GPIO_AF_INSTANCE(GPIOx));
-        assert_param(IS_GPIO_AF(pGPIO_Init->Alternate));
-
-        /* Configure Alternate function mapped with the current IO */
-        tmp = GPIOx->AFR[position >> 3U];
- 800480c:	693b      	ldr	r3, [r7, #16]
- 800480e:	08da      	lsrs	r2, r3, #3
- 8004810:	687b      	ldr	r3, [r7, #4]
- 8004812:	3208      	adds	r2, #8
- 8004814:	0092      	lsls	r2, r2, #2
- 8004816:	58d3      	ldr	r3, [r2, r3]
- 8004818:	617b      	str	r3, [r7, #20]
-        tmp &= ~(0xFUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ;
- 800481a:	693b      	ldr	r3, [r7, #16]
- 800481c:	2207      	movs	r2, #7
- 800481e:	4013      	ands	r3, r2
- 8004820:	009b      	lsls	r3, r3, #2
- 8004822:	220f      	movs	r2, #15
- 8004824:	409a      	lsls	r2, r3
- 8004826:	0013      	movs	r3, r2
- 8004828:	43da      	mvns	r2, r3
- 800482a:	697b      	ldr	r3, [r7, #20]
- 800482c:	4013      	ands	r3, r2
- 800482e:	617b      	str	r3, [r7, #20]
-        tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos));
- 8004830:	683b      	ldr	r3, [r7, #0]
- 8004832:	691b      	ldr	r3, [r3, #16]
- 8004834:	220f      	movs	r2, #15
- 8004836:	401a      	ands	r2, r3
- 8004838:	693b      	ldr	r3, [r7, #16]
- 800483a:	2107      	movs	r1, #7
- 800483c:	400b      	ands	r3, r1
- 800483e:	009b      	lsls	r3, r3, #2
- 8004840:	409a      	lsls	r2, r3
- 8004842:	0013      	movs	r3, r2
- 8004844:	697a      	ldr	r2, [r7, #20]
- 8004846:	4313      	orrs	r3, r2
- 8004848:	617b      	str	r3, [r7, #20]
-        GPIOx->AFR[position >> 3U] = tmp;
- 800484a:	693b      	ldr	r3, [r7, #16]
- 800484c:	08da      	lsrs	r2, r3, #3
- 800484e:	687b      	ldr	r3, [r7, #4]
- 8004850:	3208      	adds	r2, #8
- 8004852:	0092      	lsls	r2, r2, #2
- 8004854:	6979      	ldr	r1, [r7, #20]
- 8004856:	50d1      	str	r1, [r2, r3]
-      }
-
-      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
-      tmp = GPIOx->MODER;
- 8004858:	687b      	ldr	r3, [r7, #4]
- 800485a:	681b      	ldr	r3, [r3, #0]
- 800485c:	617b      	str	r3, [r7, #20]
-      tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
- 800485e:	693b      	ldr	r3, [r7, #16]
- 8004860:	005b      	lsls	r3, r3, #1
- 8004862:	2203      	movs	r2, #3
- 8004864:	409a      	lsls	r2, r3
- 8004866:	0013      	movs	r3, r2
- 8004868:	43da      	mvns	r2, r3
- 800486a:	697b      	ldr	r3, [r7, #20]
- 800486c:	4013      	ands	r3, r2
- 800486e:	617b      	str	r3, [r7, #20]
-      tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos));
- 8004870:	683b      	ldr	r3, [r7, #0]
- 8004872:	685b      	ldr	r3, [r3, #4]
- 8004874:	2203      	movs	r2, #3
- 8004876:	401a      	ands	r2, r3
- 8004878:	693b      	ldr	r3, [r7, #16]
- 800487a:	005b      	lsls	r3, r3, #1
- 800487c:	409a      	lsls	r2, r3
- 800487e:	0013      	movs	r3, r2
- 8004880:	697a      	ldr	r2, [r7, #20]
- 8004882:	4313      	orrs	r3, r2
- 8004884:	617b      	str	r3, [r7, #20]
-      GPIOx->MODER = tmp;
- 8004886:	687b      	ldr	r3, [r7, #4]
- 8004888:	697a      	ldr	r2, [r7, #20]
- 800488a:	601a      	str	r2, [r3, #0]
-
-      /* In case of Output or Alternate function mode selection */
-      if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 800488c:	683b      	ldr	r3, [r7, #0]
- 800488e:	685b      	ldr	r3, [r3, #4]
- 8004890:	2b01      	cmp	r3, #1
- 8004892:	d00b      	beq.n	80048ac <HAL_GPIO_Init+0xd8>
- 8004894:	683b      	ldr	r3, [r7, #0]
- 8004896:	685b      	ldr	r3, [r3, #4]
- 8004898:	2b02      	cmp	r3, #2
- 800489a:	d007      	beq.n	80048ac <HAL_GPIO_Init+0xd8>
-          (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD))
- 800489c:	683b      	ldr	r3, [r7, #0]
- 800489e:	685b      	ldr	r3, [r3, #4]
-      if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
- 80048a0:	2b11      	cmp	r3, #17
- 80048a2:	d003      	beq.n	80048ac <HAL_GPIO_Init+0xd8>
-          (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD))
- 80048a4:	683b      	ldr	r3, [r7, #0]
- 80048a6:	685b      	ldr	r3, [r3, #4]
- 80048a8:	2b12      	cmp	r3, #18
- 80048aa:	d130      	bne.n	800490e <HAL_GPIO_Init+0x13a>
-      {
-        /* Check the Speed parameter */
-        assert_param(IS_GPIO_SPEED(pGPIO_Init->Speed));
-
-        /* Configure the IO Speed */
-        tmp = GPIOx->OSPEEDR;
- 80048ac:	687b      	ldr	r3, [r7, #4]
- 80048ae:	689b      	ldr	r3, [r3, #8]
- 80048b0:	617b      	str	r3, [r7, #20]
-        tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
- 80048b2:	693b      	ldr	r3, [r7, #16]
- 80048b4:	005b      	lsls	r3, r3, #1
- 80048b6:	2203      	movs	r2, #3
- 80048b8:	409a      	lsls	r2, r3
- 80048ba:	0013      	movs	r3, r2
- 80048bc:	43da      	mvns	r2, r3
- 80048be:	697b      	ldr	r3, [r7, #20]
- 80048c0:	4013      	ands	r3, r2
- 80048c2:	617b      	str	r3, [r7, #20]
-        tmp |= (pGPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos));
- 80048c4:	683b      	ldr	r3, [r7, #0]
- 80048c6:	68da      	ldr	r2, [r3, #12]
- 80048c8:	693b      	ldr	r3, [r7, #16]
- 80048ca:	005b      	lsls	r3, r3, #1
- 80048cc:	409a      	lsls	r2, r3
- 80048ce:	0013      	movs	r3, r2
- 80048d0:	697a      	ldr	r2, [r7, #20]
- 80048d2:	4313      	orrs	r3, r2
- 80048d4:	617b      	str	r3, [r7, #20]
-        GPIOx->OSPEEDR = tmp;
- 80048d6:	687b      	ldr	r3, [r7, #4]
- 80048d8:	697a      	ldr	r2, [r7, #20]
- 80048da:	609a      	str	r2, [r3, #8]
-
-        /* Configure the IO Output Type */
-        tmp = GPIOx->OTYPER;
- 80048dc:	687b      	ldr	r3, [r7, #4]
- 80048de:	685b      	ldr	r3, [r3, #4]
- 80048e0:	617b      	str	r3, [r7, #20]
-        tmp &= ~(GPIO_OTYPER_OT0 << position) ;
- 80048e2:	2201      	movs	r2, #1
- 80048e4:	693b      	ldr	r3, [r7, #16]
- 80048e6:	409a      	lsls	r2, r3
- 80048e8:	0013      	movs	r3, r2
- 80048ea:	43da      	mvns	r2, r3
- 80048ec:	697b      	ldr	r3, [r7, #20]
- 80048ee:	4013      	ands	r3, r2
- 80048f0:	617b      	str	r3, [r7, #20]
-        tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
- 80048f2:	683b      	ldr	r3, [r7, #0]
- 80048f4:	685b      	ldr	r3, [r3, #4]
- 80048f6:	091b      	lsrs	r3, r3, #4
- 80048f8:	2201      	movs	r2, #1
- 80048fa:	401a      	ands	r2, r3
- 80048fc:	693b      	ldr	r3, [r7, #16]
- 80048fe:	409a      	lsls	r2, r3
- 8004900:	0013      	movs	r3, r2
- 8004902:	697a      	ldr	r2, [r7, #20]
- 8004904:	4313      	orrs	r3, r2
- 8004906:	617b      	str	r3, [r7, #20]
-        GPIOx->OTYPER = tmp;
- 8004908:	687b      	ldr	r3, [r7, #4]
- 800490a:	697a      	ldr	r2, [r7, #20]
- 800490c:	605a      	str	r2, [r3, #4]
-      }
-
-      if (pGPIO_Init->Mode != GPIO_MODE_ANALOG)
- 800490e:	683b      	ldr	r3, [r7, #0]
- 8004910:	685b      	ldr	r3, [r3, #4]
- 8004912:	2b03      	cmp	r3, #3
- 8004914:	d017      	beq.n	8004946 <HAL_GPIO_Init+0x172>
-      {
-        /* Check the Pull parameters */
-        assert_param(IS_GPIO_PULL(pGPIO_Init->Pull));
-
-        /* Activate the Pull-up or Pull down resistor for the current IO */
-        tmp = GPIOx->PUPDR;
- 8004916:	687b      	ldr	r3, [r7, #4]
- 8004918:	68db      	ldr	r3, [r3, #12]
- 800491a:	617b      	str	r3, [r7, #20]
-        tmp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos));
- 800491c:	693b      	ldr	r3, [r7, #16]
- 800491e:	005b      	lsls	r3, r3, #1
- 8004920:	2203      	movs	r2, #3
- 8004922:	409a      	lsls	r2, r3
- 8004924:	0013      	movs	r3, r2
- 8004926:	43da      	mvns	r2, r3
- 8004928:	697b      	ldr	r3, [r7, #20]
- 800492a:	4013      	ands	r3, r2
- 800492c:	617b      	str	r3, [r7, #20]
-        tmp |= ((pGPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos));
- 800492e:	683b      	ldr	r3, [r7, #0]
- 8004930:	689a      	ldr	r2, [r3, #8]
- 8004932:	693b      	ldr	r3, [r7, #16]
- 8004934:	005b      	lsls	r3, r3, #1
- 8004936:	409a      	lsls	r2, r3
- 8004938:	0013      	movs	r3, r2
- 800493a:	697a      	ldr	r2, [r7, #20]
- 800493c:	4313      	orrs	r3, r2
- 800493e:	617b      	str	r3, [r7, #20]
-        GPIOx->PUPDR = tmp;
- 8004940:	687b      	ldr	r3, [r7, #4]
- 8004942:	697a      	ldr	r2, [r7, #20]
- 8004944:	60da      	str	r2, [r3, #12]
-      }
-
-      /*--------------------- EXTI Mode Configuration ------------------------*/
-      /* Configure the External Interrupt or event for the current IO */
-      if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
- 8004946:	683b      	ldr	r3, [r7, #0]
- 8004948:	685a      	ldr	r2, [r3, #4]
- 800494a:	2380      	movs	r3, #128	@ 0x80
- 800494c:	055b      	lsls	r3, r3, #21
- 800494e:	4013      	ands	r3, r2
- 8004950:	d100      	bne.n	8004954 <HAL_GPIO_Init+0x180>
- 8004952:	e098      	b.n	8004a86 <HAL_GPIO_Init+0x2b2>
-      {
-        tmp = EXTI->EXTICR[position >> 2U];
- 8004954:	4a53      	ldr	r2, [pc, #332]	@ (8004aa4 <HAL_GPIO_Init+0x2d0>)
- 8004956:	693b      	ldr	r3, [r7, #16]
- 8004958:	089b      	lsrs	r3, r3, #2
- 800495a:	3318      	adds	r3, #24
- 800495c:	009b      	lsls	r3, r3, #2
- 800495e:	589b      	ldr	r3, [r3, r2]
- 8004960:	617b      	str	r3, [r7, #20]
-        tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
- 8004962:	693b      	ldr	r3, [r7, #16]
- 8004964:	2203      	movs	r2, #3
- 8004966:	4013      	ands	r3, r2
- 8004968:	00db      	lsls	r3, r3, #3
- 800496a:	220f      	movs	r2, #15
- 800496c:	409a      	lsls	r2, r3
- 800496e:	0013      	movs	r3, r2
- 8004970:	43da      	mvns	r2, r3
- 8004972:	697b      	ldr	r3, [r7, #20]
- 8004974:	4013      	ands	r3, r2
- 8004976:	617b      	str	r3, [r7, #20]
-        tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
- 8004978:	687a      	ldr	r2, [r7, #4]
- 800497a:	23a0      	movs	r3, #160	@ 0xa0
- 800497c:	05db      	lsls	r3, r3, #23
- 800497e:	429a      	cmp	r2, r3
- 8004980:	d019      	beq.n	80049b6 <HAL_GPIO_Init+0x1e2>
- 8004982:	687b      	ldr	r3, [r7, #4]
- 8004984:	4a48      	ldr	r2, [pc, #288]	@ (8004aa8 <HAL_GPIO_Init+0x2d4>)
- 8004986:	4293      	cmp	r3, r2
- 8004988:	d013      	beq.n	80049b2 <HAL_GPIO_Init+0x1de>
- 800498a:	687b      	ldr	r3, [r7, #4]
- 800498c:	4a47      	ldr	r2, [pc, #284]	@ (8004aac <HAL_GPIO_Init+0x2d8>)
- 800498e:	4293      	cmp	r3, r2
- 8004990:	d00d      	beq.n	80049ae <HAL_GPIO_Init+0x1da>
- 8004992:	687b      	ldr	r3, [r7, #4]
- 8004994:	4a46      	ldr	r2, [pc, #280]	@ (8004ab0 <HAL_GPIO_Init+0x2dc>)
- 8004996:	4293      	cmp	r3, r2
- 8004998:	d007      	beq.n	80049aa <HAL_GPIO_Init+0x1d6>
- 800499a:	687b      	ldr	r3, [r7, #4]
- 800499c:	4a45      	ldr	r2, [pc, #276]	@ (8004ab4 <HAL_GPIO_Init+0x2e0>)
- 800499e:	4293      	cmp	r3, r2
- 80049a0:	d101      	bne.n	80049a6 <HAL_GPIO_Init+0x1d2>
- 80049a2:	2305      	movs	r3, #5
- 80049a4:	e008      	b.n	80049b8 <HAL_GPIO_Init+0x1e4>
- 80049a6:	2306      	movs	r3, #6
- 80049a8:	e006      	b.n	80049b8 <HAL_GPIO_Init+0x1e4>
- 80049aa:	2303      	movs	r3, #3
- 80049ac:	e004      	b.n	80049b8 <HAL_GPIO_Init+0x1e4>
- 80049ae:	2302      	movs	r3, #2
- 80049b0:	e002      	b.n	80049b8 <HAL_GPIO_Init+0x1e4>
- 80049b2:	2301      	movs	r3, #1
- 80049b4:	e000      	b.n	80049b8 <HAL_GPIO_Init+0x1e4>
- 80049b6:	2300      	movs	r3, #0
- 80049b8:	693a      	ldr	r2, [r7, #16]
- 80049ba:	2103      	movs	r1, #3
- 80049bc:	400a      	ands	r2, r1
- 80049be:	00d2      	lsls	r2, r2, #3
- 80049c0:	4093      	lsls	r3, r2
- 80049c2:	697a      	ldr	r2, [r7, #20]
- 80049c4:	4313      	orrs	r3, r2
- 80049c6:	617b      	str	r3, [r7, #20]
-        EXTI->EXTICR[position >> 2U] = tmp;
- 80049c8:	4936      	ldr	r1, [pc, #216]	@ (8004aa4 <HAL_GPIO_Init+0x2d0>)
- 80049ca:	693b      	ldr	r3, [r7, #16]
- 80049cc:	089b      	lsrs	r3, r3, #2
- 80049ce:	3318      	adds	r3, #24
- 80049d0:	009b      	lsls	r3, r3, #2
- 80049d2:	697a      	ldr	r2, [r7, #20]
- 80049d4:	505a      	str	r2, [r3, r1]
-
-        /* Clear EXTI line configuration */
-        tmp = EXTI->IMR1;
- 80049d6:	4a33      	ldr	r2, [pc, #204]	@ (8004aa4 <HAL_GPIO_Init+0x2d0>)
- 80049d8:	2380      	movs	r3, #128	@ 0x80
- 80049da:	58d3      	ldr	r3, [r2, r3]
- 80049dc:	617b      	str	r3, [r7, #20]
-        tmp &= ~((uint32_t)iocurrent);
- 80049de:	68fb      	ldr	r3, [r7, #12]
- 80049e0:	43da      	mvns	r2, r3
- 80049e2:	697b      	ldr	r3, [r7, #20]
- 80049e4:	4013      	ands	r3, r2
- 80049e6:	617b      	str	r3, [r7, #20]
-        if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
- 80049e8:	683b      	ldr	r3, [r7, #0]
- 80049ea:	685a      	ldr	r2, [r3, #4]
- 80049ec:	2380      	movs	r3, #128	@ 0x80
- 80049ee:	025b      	lsls	r3, r3, #9
- 80049f0:	4013      	ands	r3, r2
- 80049f2:	d003      	beq.n	80049fc <HAL_GPIO_Init+0x228>
-        {
-          tmp |= iocurrent;
- 80049f4:	697a      	ldr	r2, [r7, #20]
- 80049f6:	68fb      	ldr	r3, [r7, #12]
- 80049f8:	4313      	orrs	r3, r2
- 80049fa:	617b      	str	r3, [r7, #20]
-        }
-        EXTI->IMR1 = tmp;
- 80049fc:	4929      	ldr	r1, [pc, #164]	@ (8004aa4 <HAL_GPIO_Init+0x2d0>)
- 80049fe:	2280      	movs	r2, #128	@ 0x80
- 8004a00:	697b      	ldr	r3, [r7, #20]
- 8004a02:	508b      	str	r3, [r1, r2]
-
-        tmp = EXTI->EMR1;
- 8004a04:	4a27      	ldr	r2, [pc, #156]	@ (8004aa4 <HAL_GPIO_Init+0x2d0>)
- 8004a06:	2384      	movs	r3, #132	@ 0x84
- 8004a08:	58d3      	ldr	r3, [r2, r3]
- 8004a0a:	617b      	str	r3, [r7, #20]
-        tmp &= ~((uint32_t)iocurrent);
- 8004a0c:	68fb      	ldr	r3, [r7, #12]
- 8004a0e:	43da      	mvns	r2, r3
- 8004a10:	697b      	ldr	r3, [r7, #20]
- 8004a12:	4013      	ands	r3, r2
- 8004a14:	617b      	str	r3, [r7, #20]
-        if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
- 8004a16:	683b      	ldr	r3, [r7, #0]
- 8004a18:	685a      	ldr	r2, [r3, #4]
- 8004a1a:	2380      	movs	r3, #128	@ 0x80
- 8004a1c:	029b      	lsls	r3, r3, #10
- 8004a1e:	4013      	ands	r3, r2
- 8004a20:	d003      	beq.n	8004a2a <HAL_GPIO_Init+0x256>
-        {
-          tmp |= iocurrent;
- 8004a22:	697a      	ldr	r2, [r7, #20]
- 8004a24:	68fb      	ldr	r3, [r7, #12]
- 8004a26:	4313      	orrs	r3, r2
- 8004a28:	617b      	str	r3, [r7, #20]
-        }
-        EXTI->EMR1 = tmp;
- 8004a2a:	491e      	ldr	r1, [pc, #120]	@ (8004aa4 <HAL_GPIO_Init+0x2d0>)
- 8004a2c:	2284      	movs	r2, #132	@ 0x84
- 8004a2e:	697b      	ldr	r3, [r7, #20]
- 8004a30:	508b      	str	r3, [r1, r2]
-
-        /* Clear Rising Falling edge configuration */
-        tmp = EXTI->RTSR1;
- 8004a32:	4b1c      	ldr	r3, [pc, #112]	@ (8004aa4 <HAL_GPIO_Init+0x2d0>)
- 8004a34:	681b      	ldr	r3, [r3, #0]
- 8004a36:	617b      	str	r3, [r7, #20]
-        tmp &= ~((uint32_t)iocurrent);
- 8004a38:	68fb      	ldr	r3, [r7, #12]
- 8004a3a:	43da      	mvns	r2, r3
- 8004a3c:	697b      	ldr	r3, [r7, #20]
- 8004a3e:	4013      	ands	r3, r2
- 8004a40:	617b      	str	r3, [r7, #20]
-        if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
- 8004a42:	683b      	ldr	r3, [r7, #0]
- 8004a44:	685a      	ldr	r2, [r3, #4]
- 8004a46:	2380      	movs	r3, #128	@ 0x80
- 8004a48:	035b      	lsls	r3, r3, #13
- 8004a4a:	4013      	ands	r3, r2
- 8004a4c:	d003      	beq.n	8004a56 <HAL_GPIO_Init+0x282>
-        {
-          tmp |= iocurrent;
- 8004a4e:	697a      	ldr	r2, [r7, #20]
- 8004a50:	68fb      	ldr	r3, [r7, #12]
- 8004a52:	4313      	orrs	r3, r2
- 8004a54:	617b      	str	r3, [r7, #20]
-        }
-        EXTI->RTSR1 = tmp;
- 8004a56:	4b13      	ldr	r3, [pc, #76]	@ (8004aa4 <HAL_GPIO_Init+0x2d0>)
- 8004a58:	697a      	ldr	r2, [r7, #20]
- 8004a5a:	601a      	str	r2, [r3, #0]
-
-        tmp = EXTI->FTSR1;
- 8004a5c:	4b11      	ldr	r3, [pc, #68]	@ (8004aa4 <HAL_GPIO_Init+0x2d0>)
- 8004a5e:	685b      	ldr	r3, [r3, #4]
- 8004a60:	617b      	str	r3, [r7, #20]
-        tmp &= ~((uint32_t)iocurrent);
- 8004a62:	68fb      	ldr	r3, [r7, #12]
- 8004a64:	43da      	mvns	r2, r3
- 8004a66:	697b      	ldr	r3, [r7, #20]
- 8004a68:	4013      	ands	r3, r2
- 8004a6a:	617b      	str	r3, [r7, #20]
-        if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
- 8004a6c:	683b      	ldr	r3, [r7, #0]
- 8004a6e:	685a      	ldr	r2, [r3, #4]
- 8004a70:	2380      	movs	r3, #128	@ 0x80
- 8004a72:	039b      	lsls	r3, r3, #14
- 8004a74:	4013      	ands	r3, r2
- 8004a76:	d003      	beq.n	8004a80 <HAL_GPIO_Init+0x2ac>
-        {
-          tmp |= iocurrent;
- 8004a78:	697a      	ldr	r2, [r7, #20]
- 8004a7a:	68fb      	ldr	r3, [r7, #12]
- 8004a7c:	4313      	orrs	r3, r2
- 8004a7e:	617b      	str	r3, [r7, #20]
-        }
-        EXTI->FTSR1 = tmp;
- 8004a80:	4b08      	ldr	r3, [pc, #32]	@ (8004aa4 <HAL_GPIO_Init+0x2d0>)
- 8004a82:	697a      	ldr	r2, [r7, #20]
- 8004a84:	605a      	str	r2, [r3, #4]
+ 800319c:	680b      	ldr	r3, [r1, #0]
+ 800319e:	4664      	mov	r4, ip
+ 80031a0:	001a      	movs	r2, r3
+ 80031a2:	40e2      	lsrs	r2, r4
+ 80031a4:	d101      	bne.n	80031aa <HAL_GPIO_Init+0x16>
       }
     }
 
     position++;
- 8004a86:	693b      	ldr	r3, [r7, #16]
- 8004a88:	3301      	adds	r3, #1
- 8004a8a:	613b      	str	r3, [r7, #16]
-  while (((pGPIO_Init->Pin) >> position) != 0U)
- 8004a8c:	683b      	ldr	r3, [r7, #0]
- 8004a8e:	681a      	ldr	r2, [r3, #0]
- 8004a90:	693b      	ldr	r3, [r7, #16]
- 8004a92:	40da      	lsrs	r2, r3
- 8004a94:	1e13      	subs	r3, r2, #0
- 8004a96:	d000      	beq.n	8004a9a <HAL_GPIO_Init+0x2c6>
- 8004a98:	e6a4      	b.n	80047e4 <HAL_GPIO_Init+0x10>
   }
 }
- 8004a9a:	46c0      	nop			@ (mov r8, r8)
- 8004a9c:	46c0      	nop			@ (mov r8, r8)
- 8004a9e:	46bd      	mov	sp, r7
- 8004aa0:	b006      	add	sp, #24
- 8004aa2:	bd80      	pop	{r7, pc}
- 8004aa4:	40021800 	.word	0x40021800
- 8004aa8:	50000400 	.word	0x50000400
- 8004aac:	50000800 	.word	0x50000800
- 8004ab0:	50000c00 	.word	0x50000c00
- 8004ab4:	50001400 	.word	0x50001400
+ 80031a6:	b005      	add	sp, #20
+ 80031a8:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    iocurrent = (pGPIO_Init->Pin) & (1UL << position);
+ 80031aa:	4662      	mov	r2, ip
+ 80031ac:	2601      	movs	r6, #1
+ 80031ae:	4096      	lsls	r6, r2
+ 80031b0:	001a      	movs	r2, r3
+ 80031b2:	4032      	ands	r2, r6
+ 80031b4:	9201      	str	r2, [sp, #4]
+    if (iocurrent != 0U)
+ 80031b6:	4233      	tst	r3, r6
+ 80031b8:	d100      	bne.n	80031bc <HAL_GPIO_Init+0x28>
+ 80031ba:	e084      	b.n	80032c6 <HAL_GPIO_Init+0x132>
+      if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD))
+ 80031bc:	684f      	ldr	r7, [r1, #4]
+ 80031be:	2310      	movs	r3, #16
+ 80031c0:	003d      	movs	r5, r7
+ 80031c2:	439d      	bics	r5, r3
+ 80031c4:	9503      	str	r5, [sp, #12]
+ 80031c6:	2d02      	cmp	r5, #2
+ 80031c8:	d114      	bne.n	80031f4 <HAL_GPIO_Init+0x60>
+        tmp = GPIOx->AFR[position >> 3U];
+ 80031ca:	4663      	mov	r3, ip
+ 80031cc:	08da      	lsrs	r2, r3, #3
+ 80031ce:	0092      	lsls	r2, r2, #2
+ 80031d0:	1882      	adds	r2, r0, r2
+ 80031d2:	6a13      	ldr	r3, [r2, #32]
+        tmp &= ~(0xFUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ;
+ 80031d4:	2407      	movs	r4, #7
+        tmp = GPIOx->AFR[position >> 3U];
+ 80031d6:	001d      	movs	r5, r3
+        tmp &= ~(0xFUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)) ;
+ 80031d8:	4663      	mov	r3, ip
+ 80031da:	401c      	ands	r4, r3
+ 80031dc:	230f      	movs	r3, #15
+ 80031de:	00a4      	lsls	r4, r4, #2
+ 80031e0:	40a3      	lsls	r3, r4
+ 80031e2:	439d      	bics	r5, r3
+ 80031e4:	9502      	str	r5, [sp, #8]
+        tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos));
+ 80031e6:	250f      	movs	r5, #15
+ 80031e8:	690b      	ldr	r3, [r1, #16]
+ 80031ea:	402b      	ands	r3, r5
+ 80031ec:	40a3      	lsls	r3, r4
+ 80031ee:	9c02      	ldr	r4, [sp, #8]
+ 80031f0:	4323      	orrs	r3, r4
+        GPIOx->AFR[position >> 3U] = tmp;
+ 80031f2:	6213      	str	r3, [r2, #32]
+      tmp = GPIOx->MODER;
+ 80031f4:	4663      	mov	r3, ip
+ 80031f6:	005a      	lsls	r2, r3, #1
+      tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
+ 80031f8:	2303      	movs	r3, #3
+ 80031fa:	4093      	lsls	r3, r2
+      tmp = GPIOx->MODER;
+ 80031fc:	6804      	ldr	r4, [r0, #0]
+      tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
+ 80031fe:	43dd      	mvns	r5, r3
+ 8003200:	439c      	bics	r4, r3
+      tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos));
+ 8003202:	2303      	movs	r3, #3
+ 8003204:	403b      	ands	r3, r7
+ 8003206:	4093      	lsls	r3, r2
+      tmp &= ~(GPIO_MODER_MODE0 << (position * GPIO_MODER_MODE1_Pos));
+ 8003208:	9502      	str	r5, [sp, #8]
+      if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ 800320a:	9d03      	ldr	r5, [sp, #12]
+      tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (position * GPIO_MODER_MODE1_Pos));
+ 800320c:	4323      	orrs	r3, r4
+      if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ 800320e:	3d01      	subs	r5, #1
+      GPIOx->MODER = tmp;
+ 8003210:	6003      	str	r3, [r0, #0]
+      if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) ||
+ 8003212:	2d01      	cmp	r5, #1
+ 8003214:	d95a      	bls.n	80032cc <HAL_GPIO_Init+0x138>
+      if (pGPIO_Init->Mode != GPIO_MODE_ANALOG)
+ 8003216:	2f03      	cmp	r7, #3
+ 8003218:	d055      	beq.n	80032c6 <HAL_GPIO_Init+0x132>
+        tmp = GPIOx->PUPDR;
+ 800321a:	68c4      	ldr	r4, [r0, #12]
+        tmp &= ~(GPIO_PUPDR_PUPD0 << (position * GPIO_PUPDR_PUPD1_Pos));
+ 800321c:	9b02      	ldr	r3, [sp, #8]
+ 800321e:	401c      	ands	r4, r3
+        tmp |= ((pGPIO_Init->Pull) << (position * GPIO_PUPDR_PUPD1_Pos));
+ 8003220:	688b      	ldr	r3, [r1, #8]
+ 8003222:	4093      	lsls	r3, r2
+ 8003224:	4323      	orrs	r3, r4
+        GPIOx->PUPDR = tmp;
+ 8003226:	60c3      	str	r3, [r0, #12]
+      if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE)
+ 8003228:	2380      	movs	r3, #128	@ 0x80
+ 800322a:	055b      	lsls	r3, r3, #21
+ 800322c:	421f      	tst	r7, r3
+ 800322e:	d04a      	beq.n	80032c6 <HAL_GPIO_Init+0x132>
+        tmp = EXTI->EXTICR[position >> 2U];
+ 8003230:	4663      	mov	r3, ip
+ 8003232:	089a      	lsrs	r2, r3, #2
+ 8003234:	4b2d      	ldr	r3, [pc, #180]	@ (80032ec <HAL_GPIO_Init+0x158>)
+ 8003236:	0092      	lsls	r2, r2, #2
+ 8003238:	18d2      	adds	r2, r2, r3
+        tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
+ 800323a:	2403      	movs	r4, #3
+ 800323c:	4663      	mov	r3, ip
+ 800323e:	401c      	ands	r4, r3
+ 8003240:	230f      	movs	r3, #15
+ 8003242:	00e4      	lsls	r4, r4, #3
+ 8003244:	40a3      	lsls	r3, r4
+        tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
+ 8003246:	26a0      	movs	r6, #160	@ 0xa0
+        tmp = EXTI->EXTICR[position >> 2U];
+ 8003248:	6e15      	ldr	r5, [r2, #96]	@ 0x60
+        tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
+ 800324a:	05f6      	lsls	r6, r6, #23
+        tmp &= ~((0x0FUL) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
+ 800324c:	439d      	bics	r5, r3
+        tmp |= (GPIO_GET_INDEX(GPIOx) << ((position & 0x03U) * EXTI_EXTICR1_EXTI1_Pos));
+ 800324e:	2300      	movs	r3, #0
+ 8003250:	42b0      	cmp	r0, r6
+ 8003252:	d010      	beq.n	8003276 <HAL_GPIO_Init+0xe2>
+ 8003254:	4e26      	ldr	r6, [pc, #152]	@ (80032f0 <HAL_GPIO_Init+0x15c>)
+ 8003256:	3301      	adds	r3, #1
+ 8003258:	42b0      	cmp	r0, r6
+ 800325a:	d00c      	beq.n	8003276 <HAL_GPIO_Init+0xe2>
+ 800325c:	4e25      	ldr	r6, [pc, #148]	@ (80032f4 <HAL_GPIO_Init+0x160>)
+ 800325e:	3301      	adds	r3, #1
+ 8003260:	42b0      	cmp	r0, r6
+ 8003262:	d008      	beq.n	8003276 <HAL_GPIO_Init+0xe2>
+ 8003264:	4e24      	ldr	r6, [pc, #144]	@ (80032f8 <HAL_GPIO_Init+0x164>)
+ 8003266:	3301      	adds	r3, #1
+ 8003268:	42b0      	cmp	r0, r6
+ 800326a:	d004      	beq.n	8003276 <HAL_GPIO_Init+0xe2>
+ 800326c:	4b23      	ldr	r3, [pc, #140]	@ (80032fc <HAL_GPIO_Init+0x168>)
+ 800326e:	18c3      	adds	r3, r0, r3
+ 8003270:	1e5e      	subs	r6, r3, #1
+ 8003272:	41b3      	sbcs	r3, r6
+ 8003274:	3305      	adds	r3, #5
+ 8003276:	40a3      	lsls	r3, r4
+ 8003278:	432b      	orrs	r3, r5
+        EXTI->EXTICR[position >> 2U] = tmp;
+ 800327a:	6613      	str	r3, [r2, #96]	@ 0x60
+        tmp = EXTI->IMR1;
+ 800327c:	4b20      	ldr	r3, [pc, #128]	@ (8003300 <HAL_GPIO_Init+0x16c>)
+        tmp &= ~((uint32_t)iocurrent);
+ 800327e:	9a01      	ldr	r2, [sp, #4]
+        tmp = EXTI->IMR1;
+ 8003280:	6fdd      	ldr	r5, [r3, #124]	@ 0x7c
+          tmp |= iocurrent;
+ 8003282:	9c01      	ldr	r4, [sp, #4]
+        tmp &= ~((uint32_t)iocurrent);
+ 8003284:	43d2      	mvns	r2, r2
+          tmp |= iocurrent;
+ 8003286:	432c      	orrs	r4, r5
+        if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
+ 8003288:	03fe      	lsls	r6, r7, #15
+ 800328a:	d401      	bmi.n	8003290 <HAL_GPIO_Init+0xfc>
+        tmp &= ~((uint32_t)iocurrent);
+ 800328c:	002c      	movs	r4, r5
+ 800328e:	4014      	ands	r4, r2
+        EXTI->IMR1 = tmp;
+ 8003290:	67dc      	str	r4, [r3, #124]	@ 0x7c
+        tmp = EXTI->EMR1;
+ 8003292:	4c1c      	ldr	r4, [pc, #112]	@ (8003304 <HAL_GPIO_Init+0x170>)
+          tmp |= iocurrent;
+ 8003294:	9d01      	ldr	r5, [sp, #4]
+        tmp = EXTI->EMR1;
+ 8003296:	6fe3      	ldr	r3, [r4, #124]	@ 0x7c
+          tmp |= iocurrent;
+ 8003298:	431d      	orrs	r5, r3
+        if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
+ 800329a:	03be      	lsls	r6, r7, #14
+ 800329c:	d401      	bmi.n	80032a2 <HAL_GPIO_Init+0x10e>
+        tmp &= ~((uint32_t)iocurrent);
+ 800329e:	4013      	ands	r3, r2
+ 80032a0:	001d      	movs	r5, r3
+        EXTI->EMR1 = tmp;
+ 80032a2:	4b12      	ldr	r3, [pc, #72]	@ (80032ec <HAL_GPIO_Init+0x158>)
+ 80032a4:	67e5      	str	r5, [r4, #124]	@ 0x7c
+        tmp = EXTI->RTSR1;
+ 80032a6:	681d      	ldr	r5, [r3, #0]
+          tmp |= iocurrent;
+ 80032a8:	9c01      	ldr	r4, [sp, #4]
+ 80032aa:	432c      	orrs	r4, r5
+        if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
+ 80032ac:	02fe      	lsls	r6, r7, #11
+ 80032ae:	d401      	bmi.n	80032b4 <HAL_GPIO_Init+0x120>
+        tmp &= ~((uint32_t)iocurrent);
+ 80032b0:	002c      	movs	r4, r5
+ 80032b2:	4014      	ands	r4, r2
+        EXTI->RTSR1 = tmp;
+ 80032b4:	601c      	str	r4, [r3, #0]
+        tmp = EXTI->FTSR1;
+ 80032b6:	685c      	ldr	r4, [r3, #4]
+          tmp |= iocurrent;
+ 80032b8:	9d01      	ldr	r5, [sp, #4]
+ 80032ba:	4325      	orrs	r5, r4
+        if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
+ 80032bc:	02bf      	lsls	r7, r7, #10
+ 80032be:	d401      	bmi.n	80032c4 <HAL_GPIO_Init+0x130>
+        tmp &= ~((uint32_t)iocurrent);
+ 80032c0:	4014      	ands	r4, r2
+ 80032c2:	0025      	movs	r5, r4
+        EXTI->FTSR1 = tmp;
+ 80032c4:	605d      	str	r5, [r3, #4]
+    position++;
+ 80032c6:	2301      	movs	r3, #1
+ 80032c8:	449c      	add	ip, r3
+ 80032ca:	e767      	b.n	800319c <HAL_GPIO_Init+0x8>
+        tmp = GPIOx->OSPEEDR;
+ 80032cc:	6884      	ldr	r4, [r0, #8]
+        tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
+ 80032ce:	9b02      	ldr	r3, [sp, #8]
+        tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ 80032d0:	4665      	mov	r5, ip
+        tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * GPIO_OSPEEDR_OSPEED1_Pos));
+ 80032d2:	401c      	ands	r4, r3
+        tmp |= (pGPIO_Init->Speed << (position * GPIO_OSPEEDR_OSPEED1_Pos));
+ 80032d4:	68cb      	ldr	r3, [r1, #12]
+ 80032d6:	4093      	lsls	r3, r2
+ 80032d8:	4323      	orrs	r3, r4
+        GPIOx->OSPEEDR = tmp;
+ 80032da:	6083      	str	r3, [r0, #8]
+        tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ 80032dc:	093b      	lsrs	r3, r7, #4
+ 80032de:	40ab      	lsls	r3, r5
+        tmp = GPIOx->OTYPER;
+ 80032e0:	6844      	ldr	r4, [r0, #4]
+        tmp &= ~(GPIO_OTYPER_OT0 << position) ;
+ 80032e2:	43b4      	bics	r4, r6
+        tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << position);
+ 80032e4:	4323      	orrs	r3, r4
+        GPIOx->OTYPER = tmp;
+ 80032e6:	6043      	str	r3, [r0, #4]
+      if (pGPIO_Init->Mode != GPIO_MODE_ANALOG)
+ 80032e8:	e797      	b.n	800321a <HAL_GPIO_Init+0x86>
+ 80032ea:	46c0      	nop			@ (mov r8, r8)
+ 80032ec:	40021800 	.word	0x40021800
+ 80032f0:	50000400 	.word	0x50000400
+ 80032f4:	50000800 	.word	0x50000800
+ 80032f8:	50000c00 	.word	0x50000c00
+ 80032fc:	afffec00 	.word	0xafffec00
+ 8003300:	40021804 	.word	0x40021804
+ 8003304:	40021808 	.word	0x40021808
 
-08004ab8 <HAL_GPIO_ReadPin>:
-  * @param  GPIO_Pin specifies the port bit to read.
-  *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-  * @retval The input port pin value.
-  */
-GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
-{
- 8004ab8:	b580      	push	{r7, lr}
- 8004aba:	b084      	sub	sp, #16
- 8004abc:	af00      	add	r7, sp, #0
- 8004abe:	6078      	str	r0, [r7, #4]
- 8004ac0:	000a      	movs	r2, r1
- 8004ac2:	1cbb      	adds	r3, r7, #2
- 8004ac4:	801a      	strh	r2, [r3, #0]
+08003308 <HAL_GPIO_ReadPin>:
   GPIO_PinState bitstatus;
 
   /* Check the parameters */
   assert_param(IS_GPIO_PIN(GPIO_Pin));
 
   if ((GPIOx->IDR & GPIO_Pin) != 0U)
- 8004ac6:	687b      	ldr	r3, [r7, #4]
- 8004ac8:	691b      	ldr	r3, [r3, #16]
- 8004aca:	1cba      	adds	r2, r7, #2
- 8004acc:	8812      	ldrh	r2, [r2, #0]
- 8004ace:	4013      	ands	r3, r2
- 8004ad0:	d004      	beq.n	8004adc <HAL_GPIO_ReadPin+0x24>
-  {
-    bitstatus = GPIO_PIN_SET;
- 8004ad2:	230f      	movs	r3, #15
- 8004ad4:	18fb      	adds	r3, r7, r3
- 8004ad6:	2201      	movs	r2, #1
- 8004ad8:	701a      	strb	r2, [r3, #0]
- 8004ada:	e003      	b.n	8004ae4 <HAL_GPIO_ReadPin+0x2c>
+ 8003308:	6900      	ldr	r0, [r0, #16]
+ 800330a:	4008      	ands	r0, r1
+ 800330c:	1e43      	subs	r3, r0, #1
+ 800330e:	4198      	sbcs	r0, r3
   }
   else
   {
     bitstatus = GPIO_PIN_RESET;
- 8004adc:	230f      	movs	r3, #15
- 8004ade:	18fb      	adds	r3, r7, r3
- 8004ae0:	2200      	movs	r2, #0
- 8004ae2:	701a      	strb	r2, [r3, #0]
   }
   return bitstatus;
- 8004ae4:	230f      	movs	r3, #15
- 8004ae6:	18fb      	adds	r3, r7, r3
- 8004ae8:	781b      	ldrb	r3, [r3, #0]
+ 8003310:	b2c0      	uxtb	r0, r0
 }
- 8004aea:	0018      	movs	r0, r3
- 8004aec:	46bd      	mov	sp, r7
- 8004aee:	b004      	add	sp, #16
- 8004af0:	bd80      	pop	{r7, pc}
+ 8003312:	4770      	bx	lr
 
-08004af2 <HAL_GPIO_WritePin>:
-  *            @arg GPIO_PIN_RESET: to clear the port pin
-  *            @arg GPIO_PIN_SET: to set the port pin
-  * @retval None
-  */
-void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
+08003314 <HAL_GPIO_WritePin>:
 {
- 8004af2:	b580      	push	{r7, lr}
- 8004af4:	b082      	sub	sp, #8
- 8004af6:	af00      	add	r7, sp, #0
- 8004af8:	6078      	str	r0, [r7, #4]
- 8004afa:	0008      	movs	r0, r1
- 8004afc:	0011      	movs	r1, r2
- 8004afe:	1cbb      	adds	r3, r7, #2
- 8004b00:	1c02      	adds	r2, r0, #0
- 8004b02:	801a      	strh	r2, [r3, #0]
- 8004b04:	1c7b      	adds	r3, r7, #1
- 8004b06:	1c0a      	adds	r2, r1, #0
- 8004b08:	701a      	strb	r2, [r3, #0]
   /* Check the parameters */
   assert_param(IS_GPIO_PIN(GPIO_Pin));
   assert_param(IS_GPIO_PIN_ACTION(PinState));
 
   if (PinState != GPIO_PIN_RESET)
- 8004b0a:	1c7b      	adds	r3, r7, #1
- 8004b0c:	781b      	ldrb	r3, [r3, #0]
- 8004b0e:	2b00      	cmp	r3, #0
- 8004b10:	d004      	beq.n	8004b1c <HAL_GPIO_WritePin+0x2a>
+ 8003314:	2a00      	cmp	r2, #0
+ 8003316:	d001      	beq.n	800331c <HAL_GPIO_WritePin+0x8>
   {
     GPIOx->BSRR = (uint32_t)GPIO_Pin;
- 8004b12:	1cbb      	adds	r3, r7, #2
- 8004b14:	881a      	ldrh	r2, [r3, #0]
- 8004b16:	687b      	ldr	r3, [r7, #4]
- 8004b18:	619a      	str	r2, [r3, #24]
+ 8003318:	6181      	str	r1, [r0, #24]
   }
   else
   {
     GPIOx->BRR = (uint32_t)GPIO_Pin;
   }
 }
- 8004b1a:	e003      	b.n	8004b24 <HAL_GPIO_WritePin+0x32>
+ 800331a:	4770      	bx	lr
     GPIOx->BRR = (uint32_t)GPIO_Pin;
- 8004b1c:	1cbb      	adds	r3, r7, #2
- 8004b1e:	881a      	ldrh	r2, [r3, #0]
- 8004b20:	687b      	ldr	r3, [r7, #4]
- 8004b22:	629a      	str	r2, [r3, #40]	@ 0x28
+ 800331c:	6281      	str	r1, [r0, #40]	@ 0x28
 }
- 8004b24:	46c0      	nop			@ (mov r8, r8)
- 8004b26:	46bd      	mov	sp, r7
- 8004b28:	b002      	add	sp, #8
- 8004b2a:	bd80      	pop	{r7, pc}
+ 800331e:	e7fc      	b.n	800331a <HAL_GPIO_WritePin+0x6>
 
-08004b2c <HAL_GPIO_EXTI_IRQHandler>:
-  * @brief  Handle EXTI interrupt request.
-  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
-  * @retval None
-  */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
- 8004b2c:	b580      	push	{r7, lr}
- 8004b2e:	b082      	sub	sp, #8
- 8004b30:	af00      	add	r7, sp, #0
- 8004b32:	0002      	movs	r2, r0
- 8004b34:	1dbb      	adds	r3, r7, #6
- 8004b36:	801a      	strh	r2, [r3, #0]
-  /* EXTI line interrupt detected */
-  if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U)
- 8004b38:	4b10      	ldr	r3, [pc, #64]	@ (8004b7c <HAL_GPIO_EXTI_IRQHandler+0x50>)
- 8004b3a:	68db      	ldr	r3, [r3, #12]
- 8004b3c:	1dba      	adds	r2, r7, #6
- 8004b3e:	8812      	ldrh	r2, [r2, #0]
- 8004b40:	4013      	ands	r3, r2
- 8004b42:	d008      	beq.n	8004b56 <HAL_GPIO_EXTI_IRQHandler+0x2a>
-  {
-    __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
- 8004b44:	4b0d      	ldr	r3, [pc, #52]	@ (8004b7c <HAL_GPIO_EXTI_IRQHandler+0x50>)
- 8004b46:	1dba      	adds	r2, r7, #6
- 8004b48:	8812      	ldrh	r2, [r2, #0]
- 8004b4a:	60da      	str	r2, [r3, #12]
-    HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
- 8004b4c:	1dbb      	adds	r3, r7, #6
- 8004b4e:	881b      	ldrh	r3, [r3, #0]
- 8004b50:	0018      	movs	r0, r3
- 8004b52:	f000 f815 	bl	8004b80 <HAL_GPIO_EXTI_Rising_Callback>
-  }
-
-  if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U)
- 8004b56:	4b09      	ldr	r3, [pc, #36]	@ (8004b7c <HAL_GPIO_EXTI_IRQHandler+0x50>)
- 8004b58:	691b      	ldr	r3, [r3, #16]
- 8004b5a:	1dba      	adds	r2, r7, #6
- 8004b5c:	8812      	ldrh	r2, [r2, #0]
- 8004b5e:	4013      	ands	r3, r2
- 8004b60:	d008      	beq.n	8004b74 <HAL_GPIO_EXTI_IRQHandler+0x48>
-  {
-    __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
- 8004b62:	4b06      	ldr	r3, [pc, #24]	@ (8004b7c <HAL_GPIO_EXTI_IRQHandler+0x50>)
- 8004b64:	1dba      	adds	r2, r7, #6
- 8004b66:	8812      	ldrh	r2, [r2, #0]
- 8004b68:	611a      	str	r2, [r3, #16]
-    HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
- 8004b6a:	1dbb      	adds	r3, r7, #6
- 8004b6c:	881b      	ldrh	r3, [r3, #0]
- 8004b6e:	0018      	movs	r0, r3
- 8004b70:	f7fc ff6e 	bl	8001a50 <HAL_GPIO_EXTI_Falling_Callback>
-  }
-}
- 8004b74:	46c0      	nop			@ (mov r8, r8)
- 8004b76:	46bd      	mov	sp, r7
- 8004b78:	b002      	add	sp, #8
- 8004b7a:	bd80      	pop	{r7, pc}
- 8004b7c:	40021800 	.word	0x40021800
-
-08004b80 <HAL_GPIO_EXTI_Rising_Callback>:
-  * @brief  EXTI line detection callback.
-  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
-  * @retval None
-  */
-__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin)
-{
- 8004b80:	b580      	push	{r7, lr}
- 8004b82:	b082      	sub	sp, #8
- 8004b84:	af00      	add	r7, sp, #0
- 8004b86:	0002      	movs	r2, r0
- 8004b88:	1dbb      	adds	r3, r7, #6
- 8004b8a:	801a      	strh	r2, [r3, #0]
+08003320 <HAL_GPIO_EXTI_Rising_Callback>:
   UNUSED(GPIO_Pin);
 
   /* NOTE: This function should not be modified, when the callback is needed,
            the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file
    */
 }
- 8004b8c:	46c0      	nop			@ (mov r8, r8)
- 8004b8e:	46bd      	mov	sp, r7
- 8004b90:	b002      	add	sp, #8
- 8004b92:	bd80      	pop	{r7, pc}
+ 8003320:	4770      	bx	lr
+	...
 
-08004b94 <HAL_RCC_OscConfig>:
+08003324 <HAL_GPIO_EXTI_IRQHandler>:
+{
+ 8003324:	b570      	push	{r4, r5, r6, lr}
+  if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U)
+ 8003326:	4d08      	ldr	r5, [pc, #32]	@ (8003348 <HAL_GPIO_EXTI_IRQHandler+0x24>)
+{
+ 8003328:	0004      	movs	r4, r0
+  if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U)
+ 800332a:	68eb      	ldr	r3, [r5, #12]
+ 800332c:	4218      	tst	r0, r3
+ 800332e:	d002      	beq.n	8003336 <HAL_GPIO_EXTI_IRQHandler+0x12>
+    __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin);
+ 8003330:	60e8      	str	r0, [r5, #12]
+    HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin);
+ 8003332:	f7ff fff5 	bl	8003320 <HAL_GPIO_EXTI_Rising_Callback>
+  if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U)
+ 8003336:	692b      	ldr	r3, [r5, #16]
+ 8003338:	4223      	tst	r3, r4
+ 800333a:	d003      	beq.n	8003344 <HAL_GPIO_EXTI_IRQHandler+0x20>
+    HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
+ 800333c:	0020      	movs	r0, r4
+    __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin);
+ 800333e:	612c      	str	r4, [r5, #16]
+    HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin);
+ 8003340:	f7fd fb2e 	bl	80009a0 <HAL_GPIO_EXTI_Falling_Callback>
+}
+ 8003344:	bd70      	pop	{r4, r5, r6, pc}
+ 8003346:	46c0      	nop			@ (mov r8, r8)
+ 8003348:	40021800 	.word	0x40021800
+
+0800334c <HAL_RCC_OscConfig>:
             must adjust the number of CPU wait states in their application (SystemClock_Config() API)
             before calling the HAL_RCC_OscConfig() API to update the HSI48 clock division factor.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef  *RCC_OscInitStruct)
 {
- 8004b94:	b580      	push	{r7, lr}
- 8004b96:	b086      	sub	sp, #24
- 8004b98:	af00      	add	r7, sp, #0
- 8004b9a:	6078      	str	r0, [r7, #4]
+ 800334c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 800334e:	1e05      	subs	r5, r0, #0
   uint32_t tickstart;
   uint32_t temp_sysclksrc;
 
   /* Check Null pointer */
   if (RCC_OscInitStruct == NULL)
- 8004b9c:	687b      	ldr	r3, [r7, #4]
- 8004b9e:	2b00      	cmp	r3, #0
- 8004ba0:	d101      	bne.n	8004ba6 <HAL_RCC_OscConfig+0x12>
+ 8003350:	d101      	bne.n	8003356 <HAL_RCC_OscConfig+0xa>
   {
     return HAL_ERROR;
- 8004ba2:	2301      	movs	r3, #1
- 8004ba4:	e1d0      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-
-  /* Check the parameters */
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
-  /*------------------------------- HSE Configuration ------------------------*/
-  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
- 8004ba6:	687b      	ldr	r3, [r7, #4]
- 8004ba8:	681b      	ldr	r3, [r3, #0]
- 8004baa:	2201      	movs	r2, #1
- 8004bac:	4013      	ands	r3, r2
- 8004bae:	d100      	bne.n	8004bb2 <HAL_RCC_OscConfig+0x1e>
- 8004bb0:	e069      	b.n	8004c86 <HAL_RCC_OscConfig+0xf2>
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-
-    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
- 8004bb2:	4bc8      	ldr	r3, [pc, #800]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004bb4:	689b      	ldr	r3, [r3, #8]
- 8004bb6:	2238      	movs	r2, #56	@ 0x38
- 8004bb8:	4013      	ands	r3, r2
- 8004bba:	617b      	str	r3, [r7, #20]
-
-    /* When the HSE is used as system clock in these cases it is not allowed to be disabled */
-    if (temp_sysclksrc == RCC_CFGR_SWS_HSE)
- 8004bbc:	697b      	ldr	r3, [r7, #20]
- 8004bbe:	2b08      	cmp	r3, #8
- 8004bc0:	d105      	bne.n	8004bce <HAL_RCC_OscConfig+0x3a>
-    {
-      if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)
- 8004bc2:	687b      	ldr	r3, [r7, #4]
- 8004bc4:	685b      	ldr	r3, [r3, #4]
- 8004bc6:	2b00      	cmp	r3, #0
- 8004bc8:	d15d      	bne.n	8004c86 <HAL_RCC_OscConfig+0xf2>
-      {
-        return HAL_ERROR;
- 8004bca:	2301      	movs	r3, #1
- 8004bcc:	e1bc      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-      }
-    }
-    else
-    {
-      /* Set the new HSE configuration ---------------------------------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
- 8004bce:	687b      	ldr	r3, [r7, #4]
- 8004bd0:	685a      	ldr	r2, [r3, #4]
- 8004bd2:	2380      	movs	r3, #128	@ 0x80
- 8004bd4:	025b      	lsls	r3, r3, #9
- 8004bd6:	429a      	cmp	r2, r3
- 8004bd8:	d107      	bne.n	8004bea <HAL_RCC_OscConfig+0x56>
- 8004bda:	4bbe      	ldr	r3, [pc, #760]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004bdc:	681a      	ldr	r2, [r3, #0]
- 8004bde:	4bbd      	ldr	r3, [pc, #756]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004be0:	2180      	movs	r1, #128	@ 0x80
- 8004be2:	0249      	lsls	r1, r1, #9
- 8004be4:	430a      	orrs	r2, r1
- 8004be6:	601a      	str	r2, [r3, #0]
- 8004be8:	e020      	b.n	8004c2c <HAL_RCC_OscConfig+0x98>
- 8004bea:	687b      	ldr	r3, [r7, #4]
- 8004bec:	685a      	ldr	r2, [r3, #4]
- 8004bee:	23a0      	movs	r3, #160	@ 0xa0
- 8004bf0:	02db      	lsls	r3, r3, #11
- 8004bf2:	429a      	cmp	r2, r3
- 8004bf4:	d10e      	bne.n	8004c14 <HAL_RCC_OscConfig+0x80>
- 8004bf6:	4bb7      	ldr	r3, [pc, #732]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004bf8:	681a      	ldr	r2, [r3, #0]
- 8004bfa:	4bb6      	ldr	r3, [pc, #728]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004bfc:	2180      	movs	r1, #128	@ 0x80
- 8004bfe:	02c9      	lsls	r1, r1, #11
- 8004c00:	430a      	orrs	r2, r1
- 8004c02:	601a      	str	r2, [r3, #0]
- 8004c04:	4bb3      	ldr	r3, [pc, #716]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004c06:	681a      	ldr	r2, [r3, #0]
- 8004c08:	4bb2      	ldr	r3, [pc, #712]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004c0a:	2180      	movs	r1, #128	@ 0x80
- 8004c0c:	0249      	lsls	r1, r1, #9
- 8004c0e:	430a      	orrs	r2, r1
- 8004c10:	601a      	str	r2, [r3, #0]
- 8004c12:	e00b      	b.n	8004c2c <HAL_RCC_OscConfig+0x98>
- 8004c14:	4baf      	ldr	r3, [pc, #700]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004c16:	681a      	ldr	r2, [r3, #0]
- 8004c18:	4bae      	ldr	r3, [pc, #696]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004c1a:	49af      	ldr	r1, [pc, #700]	@ (8004ed8 <HAL_RCC_OscConfig+0x344>)
- 8004c1c:	400a      	ands	r2, r1
- 8004c1e:	601a      	str	r2, [r3, #0]
- 8004c20:	4bac      	ldr	r3, [pc, #688]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004c22:	681a      	ldr	r2, [r3, #0]
- 8004c24:	4bab      	ldr	r3, [pc, #684]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004c26:	49ad      	ldr	r1, [pc, #692]	@ (8004edc <HAL_RCC_OscConfig+0x348>)
- 8004c28:	400a      	ands	r2, r1
- 8004c2a:	601a      	str	r2, [r3, #0]
-
-      /* Check the HSE State */
-      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
- 8004c2c:	687b      	ldr	r3, [r7, #4]
- 8004c2e:	685b      	ldr	r3, [r3, #4]
- 8004c30:	2b00      	cmp	r3, #0
- 8004c32:	d014      	beq.n	8004c5e <HAL_RCC_OscConfig+0xca>
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8004c34:	f7ff fa50 	bl	80040d8 <HAL_GetTick>
- 8004c38:	0003      	movs	r3, r0
- 8004c3a:	613b      	str	r3, [r7, #16]
-
-        /* Wait till HSE is ready */
-        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
- 8004c3c:	e008      	b.n	8004c50 <HAL_RCC_OscConfig+0xbc>
-        {
-          if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
- 8004c3e:	f7ff fa4b 	bl	80040d8 <HAL_GetTick>
- 8004c42:	0002      	movs	r2, r0
- 8004c44:	693b      	ldr	r3, [r7, #16]
- 8004c46:	1ad3      	subs	r3, r2, r3
- 8004c48:	2b64      	cmp	r3, #100	@ 0x64
- 8004c4a:	d901      	bls.n	8004c50 <HAL_RCC_OscConfig+0xbc>
-          {
-            return HAL_TIMEOUT;
- 8004c4c:	2303      	movs	r3, #3
- 8004c4e:	e17b      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
- 8004c50:	4ba0      	ldr	r3, [pc, #640]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004c52:	681a      	ldr	r2, [r3, #0]
- 8004c54:	2380      	movs	r3, #128	@ 0x80
- 8004c56:	029b      	lsls	r3, r3, #10
- 8004c58:	4013      	ands	r3, r2
- 8004c5a:	d0f0      	beq.n	8004c3e <HAL_RCC_OscConfig+0xaa>
- 8004c5c:	e013      	b.n	8004c86 <HAL_RCC_OscConfig+0xf2>
-        }
-      }
-      else
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8004c5e:	f7ff fa3b 	bl	80040d8 <HAL_GetTick>
- 8004c62:	0003      	movs	r3, r0
- 8004c64:	613b      	str	r3, [r7, #16]
-
-        /* Wait till HSE is disabled */
-        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
- 8004c66:	e008      	b.n	8004c7a <HAL_RCC_OscConfig+0xe6>
-        {
-          if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
- 8004c68:	f7ff fa36 	bl	80040d8 <HAL_GetTick>
- 8004c6c:	0002      	movs	r2, r0
- 8004c6e:	693b      	ldr	r3, [r7, #16]
- 8004c70:	1ad3      	subs	r3, r2, r3
- 8004c72:	2b64      	cmp	r3, #100	@ 0x64
- 8004c74:	d901      	bls.n	8004c7a <HAL_RCC_OscConfig+0xe6>
-          {
-            return HAL_TIMEOUT;
- 8004c76:	2303      	movs	r3, #3
- 8004c78:	e166      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
- 8004c7a:	4b96      	ldr	r3, [pc, #600]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004c7c:	681a      	ldr	r2, [r3, #0]
- 8004c7e:	2380      	movs	r3, #128	@ 0x80
- 8004c80:	029b      	lsls	r3, r3, #10
- 8004c82:	4013      	ands	r3, r2
- 8004c84:	d1f0      	bne.n	8004c68 <HAL_RCC_OscConfig+0xd4>
-        }
-      }
-    }
-  }
-  /*----------------------------- HSI Configuration --------------------------*/
-  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
- 8004c86:	687b      	ldr	r3, [r7, #4]
- 8004c88:	681b      	ldr	r3, [r3, #0]
- 8004c8a:	2202      	movs	r2, #2
- 8004c8c:	4013      	ands	r3, r2
- 8004c8e:	d100      	bne.n	8004c92 <HAL_RCC_OscConfig+0xfe>
- 8004c90:	e086      	b.n	8004da0 <HAL_RCC_OscConfig+0x20c>
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
-    assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-    assert_param(IS_RCC_HSIDIV(RCC_OscInitStruct->HSIDiv));
-
-    /* Check if HSI48 is used as system clock  */
-    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
- 8004c92:	4b90      	ldr	r3, [pc, #576]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004c94:	689b      	ldr	r3, [r3, #8]
- 8004c96:	2238      	movs	r2, #56	@ 0x38
- 8004c98:	4013      	ands	r3, r2
- 8004c9a:	617b      	str	r3, [r7, #20]
-
-    if (temp_sysclksrc == RCC_CFGR_SWS_HSI)
- 8004c9c:	697b      	ldr	r3, [r7, #20]
- 8004c9e:	2b00      	cmp	r3, #0
- 8004ca0:	d12f      	bne.n	8004d02 <HAL_RCC_OscConfig+0x16e>
-    {
-      /* When HSI is used as system clock it can not be disabled */
-      if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
- 8004ca2:	687b      	ldr	r3, [r7, #4]
- 8004ca4:	68db      	ldr	r3, [r3, #12]
- 8004ca6:	2b00      	cmp	r3, #0
- 8004ca8:	d101      	bne.n	8004cae <HAL_RCC_OscConfig+0x11a>
-      {
-        return HAL_ERROR;
- 8004caa:	2301      	movs	r3, #1
- 8004cac:	e14c      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-      }
-      /* Otherwise, just the calibration is allowed */
-      else
-      {
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8004cae:	4b89      	ldr	r3, [pc, #548]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004cb0:	685b      	ldr	r3, [r3, #4]
- 8004cb2:	4a8b      	ldr	r2, [pc, #556]	@ (8004ee0 <HAL_RCC_OscConfig+0x34c>)
- 8004cb4:	4013      	ands	r3, r2
- 8004cb6:	0019      	movs	r1, r3
- 8004cb8:	687b      	ldr	r3, [r7, #4]
- 8004cba:	695b      	ldr	r3, [r3, #20]
- 8004cbc:	021a      	lsls	r2, r3, #8
- 8004cbe:	4b85      	ldr	r3, [pc, #532]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004cc0:	430a      	orrs	r2, r1
- 8004cc2:	605a      	str	r2, [r3, #4]
-
-        if (temp_sysclksrc == RCC_CFGR_SWS_HSI)
- 8004cc4:	697b      	ldr	r3, [r7, #20]
- 8004cc6:	2b00      	cmp	r3, #0
- 8004cc8:	d112      	bne.n	8004cf0 <HAL_RCC_OscConfig+0x15c>
-        {
-          /* Adjust the HSI48 division factor */
-          __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
- 8004cca:	4b82      	ldr	r3, [pc, #520]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004ccc:	681b      	ldr	r3, [r3, #0]
- 8004cce:	4a85      	ldr	r2, [pc, #532]	@ (8004ee4 <HAL_RCC_OscConfig+0x350>)
- 8004cd0:	4013      	ands	r3, r2
- 8004cd2:	0019      	movs	r1, r3
- 8004cd4:	687b      	ldr	r3, [r7, #4]
- 8004cd6:	691a      	ldr	r2, [r3, #16]
- 8004cd8:	4b7e      	ldr	r3, [pc, #504]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004cda:	430a      	orrs	r2, r1
- 8004cdc:	601a      	str	r2, [r3, #0]
-
-          /* Update the SystemCoreClock global variable with HSISYS value  */
-          SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
- 8004cde:	4b7d      	ldr	r3, [pc, #500]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004ce0:	681b      	ldr	r3, [r3, #0]
- 8004ce2:	0adb      	lsrs	r3, r3, #11
- 8004ce4:	2207      	movs	r2, #7
- 8004ce6:	4013      	ands	r3, r2
- 8004ce8:	4a7f      	ldr	r2, [pc, #508]	@ (8004ee8 <HAL_RCC_OscConfig+0x354>)
- 8004cea:	40da      	lsrs	r2, r3
- 8004cec:	4b7f      	ldr	r3, [pc, #508]	@ (8004eec <HAL_RCC_OscConfig+0x358>)
- 8004cee:	601a      	str	r2, [r3, #0]
-        }
-
-        /* Adapt Systick interrupt period */
-        if (HAL_InitTick(uwTickPrio) != HAL_OK)
- 8004cf0:	4b7f      	ldr	r3, [pc, #508]	@ (8004ef0 <HAL_RCC_OscConfig+0x35c>)
- 8004cf2:	681b      	ldr	r3, [r3, #0]
- 8004cf4:	0018      	movs	r0, r3
- 8004cf6:	f7ff f993 	bl	8004020 <HAL_InitTick>
- 8004cfa:	1e03      	subs	r3, r0, #0
- 8004cfc:	d050      	beq.n	8004da0 <HAL_RCC_OscConfig+0x20c>
-        {
-          return HAL_ERROR;
- 8004cfe:	2301      	movs	r3, #1
- 8004d00:	e122      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-      }
-    }
-    else
-    {
-      /* Check the HSI State */
-      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
- 8004d02:	687b      	ldr	r3, [r7, #4]
- 8004d04:	68db      	ldr	r3, [r3, #12]
- 8004d06:	2b00      	cmp	r3, #0
- 8004d08:	d030      	beq.n	8004d6c <HAL_RCC_OscConfig+0x1d8>
-      {
-        /* Configure the HSI48 division factor */
-        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
- 8004d0a:	4b72      	ldr	r3, [pc, #456]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004d0c:	681b      	ldr	r3, [r3, #0]
- 8004d0e:	4a75      	ldr	r2, [pc, #468]	@ (8004ee4 <HAL_RCC_OscConfig+0x350>)
- 8004d10:	4013      	ands	r3, r2
- 8004d12:	0019      	movs	r1, r3
- 8004d14:	687b      	ldr	r3, [r7, #4]
- 8004d16:	691a      	ldr	r2, [r3, #16]
- 8004d18:	4b6e      	ldr	r3, [pc, #440]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004d1a:	430a      	orrs	r2, r1
- 8004d1c:	601a      	str	r2, [r3, #0]
-
-        /* Enable the Internal High Speed oscillator (HSI48). */
-        __HAL_RCC_HSI_ENABLE();
- 8004d1e:	4b6d      	ldr	r3, [pc, #436]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004d20:	681a      	ldr	r2, [r3, #0]
- 8004d22:	4b6c      	ldr	r3, [pc, #432]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004d24:	2180      	movs	r1, #128	@ 0x80
- 8004d26:	0049      	lsls	r1, r1, #1
- 8004d28:	430a      	orrs	r2, r1
- 8004d2a:	601a      	str	r2, [r3, #0]
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8004d2c:	f7ff f9d4 	bl	80040d8 <HAL_GetTick>
- 8004d30:	0003      	movs	r3, r0
- 8004d32:	613b      	str	r3, [r7, #16]
-
-        /* Wait till HSI is ready */
-        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
- 8004d34:	e008      	b.n	8004d48 <HAL_RCC_OscConfig+0x1b4>
-        {
-          if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
- 8004d36:	f7ff f9cf 	bl	80040d8 <HAL_GetTick>
- 8004d3a:	0002      	movs	r2, r0
- 8004d3c:	693b      	ldr	r3, [r7, #16]
- 8004d3e:	1ad3      	subs	r3, r2, r3
- 8004d40:	2b02      	cmp	r3, #2
- 8004d42:	d901      	bls.n	8004d48 <HAL_RCC_OscConfig+0x1b4>
-          {
-            return HAL_TIMEOUT;
- 8004d44:	2303      	movs	r3, #3
- 8004d46:	e0ff      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
- 8004d48:	4b62      	ldr	r3, [pc, #392]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004d4a:	681a      	ldr	r2, [r3, #0]
- 8004d4c:	2380      	movs	r3, #128	@ 0x80
- 8004d4e:	00db      	lsls	r3, r3, #3
- 8004d50:	4013      	ands	r3, r2
- 8004d52:	d0f0      	beq.n	8004d36 <HAL_RCC_OscConfig+0x1a2>
-          }
-        }
-
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
- 8004d54:	4b5f      	ldr	r3, [pc, #380]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004d56:	685b      	ldr	r3, [r3, #4]
- 8004d58:	4a61      	ldr	r2, [pc, #388]	@ (8004ee0 <HAL_RCC_OscConfig+0x34c>)
- 8004d5a:	4013      	ands	r3, r2
- 8004d5c:	0019      	movs	r1, r3
- 8004d5e:	687b      	ldr	r3, [r7, #4]
- 8004d60:	695b      	ldr	r3, [r3, #20]
- 8004d62:	021a      	lsls	r2, r3, #8
- 8004d64:	4b5b      	ldr	r3, [pc, #364]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004d66:	430a      	orrs	r2, r1
- 8004d68:	605a      	str	r2, [r3, #4]
- 8004d6a:	e019      	b.n	8004da0 <HAL_RCC_OscConfig+0x20c>
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI48). */
-        __HAL_RCC_HSI_DISABLE();
- 8004d6c:	4b59      	ldr	r3, [pc, #356]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004d6e:	681a      	ldr	r2, [r3, #0]
- 8004d70:	4b58      	ldr	r3, [pc, #352]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004d72:	4960      	ldr	r1, [pc, #384]	@ (8004ef4 <HAL_RCC_OscConfig+0x360>)
- 8004d74:	400a      	ands	r2, r1
- 8004d76:	601a      	str	r2, [r3, #0]
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8004d78:	f7ff f9ae 	bl	80040d8 <HAL_GetTick>
- 8004d7c:	0003      	movs	r3, r0
- 8004d7e:	613b      	str	r3, [r7, #16]
-
-        /* Wait till HSI is disabled */
-        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
- 8004d80:	e008      	b.n	8004d94 <HAL_RCC_OscConfig+0x200>
-        {
-          if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
- 8004d82:	f7ff f9a9 	bl	80040d8 <HAL_GetTick>
- 8004d86:	0002      	movs	r2, r0
- 8004d88:	693b      	ldr	r3, [r7, #16]
- 8004d8a:	1ad3      	subs	r3, r2, r3
- 8004d8c:	2b02      	cmp	r3, #2
- 8004d8e:	d901      	bls.n	8004d94 <HAL_RCC_OscConfig+0x200>
-          {
-            return HAL_TIMEOUT;
- 8004d90:	2303      	movs	r3, #3
- 8004d92:	e0d9      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
- 8004d94:	4b4f      	ldr	r3, [pc, #316]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004d96:	681a      	ldr	r2, [r3, #0]
- 8004d98:	2380      	movs	r3, #128	@ 0x80
- 8004d9a:	00db      	lsls	r3, r3, #3
- 8004d9c:	4013      	ands	r3, r2
- 8004d9e:	d1f0      	bne.n	8004d82 <HAL_RCC_OscConfig+0x1ee>
-        }
-      }
-    }
-  }
-  /*------------------------------ LSI Configuration -------------------------*/
-  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
- 8004da0:	687b      	ldr	r3, [r7, #4]
- 8004da2:	681b      	ldr	r3, [r3, #0]
- 8004da4:	2208      	movs	r2, #8
- 8004da6:	4013      	ands	r3, r2
- 8004da8:	d042      	beq.n	8004e30 <HAL_RCC_OscConfig+0x29c>
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-
-    /* Check if LSI is used as system clock */
-    if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
- 8004daa:	4b4a      	ldr	r3, [pc, #296]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004dac:	689b      	ldr	r3, [r3, #8]
- 8004dae:	2238      	movs	r2, #56	@ 0x38
- 8004db0:	4013      	ands	r3, r2
- 8004db2:	2b18      	cmp	r3, #24
- 8004db4:	d105      	bne.n	8004dc2 <HAL_RCC_OscConfig+0x22e>
-    {
-      /* When LSI is used as system clock it will not be disabled */
-      if (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)
- 8004db6:	687b      	ldr	r3, [r7, #4]
- 8004db8:	699b      	ldr	r3, [r3, #24]
- 8004dba:	2b00      	cmp	r3, #0
- 8004dbc:	d138      	bne.n	8004e30 <HAL_RCC_OscConfig+0x29c>
-      {
-        return HAL_ERROR;
- 8004dbe:	2301      	movs	r3, #1
- 8004dc0:	e0c2      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-      }
-    }
-    else
-    {
-      /* Check the LSI State */
-      if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
- 8004dc2:	687b      	ldr	r3, [r7, #4]
- 8004dc4:	699b      	ldr	r3, [r3, #24]
- 8004dc6:	2b00      	cmp	r3, #0
- 8004dc8:	d019      	beq.n	8004dfe <HAL_RCC_OscConfig+0x26a>
-      {
-        /* Enable the Internal Low Speed oscillator (LSI). */
-        __HAL_RCC_LSI_ENABLE();
- 8004dca:	4b42      	ldr	r3, [pc, #264]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004dcc:	6e1a      	ldr	r2, [r3, #96]	@ 0x60
- 8004dce:	4b41      	ldr	r3, [pc, #260]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004dd0:	2101      	movs	r1, #1
- 8004dd2:	430a      	orrs	r2, r1
- 8004dd4:	661a      	str	r2, [r3, #96]	@ 0x60
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8004dd6:	f7ff f97f 	bl	80040d8 <HAL_GetTick>
- 8004dda:	0003      	movs	r3, r0
- 8004ddc:	613b      	str	r3, [r7, #16]
-
-        /* Wait till LSI is ready */
-        while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
- 8004dde:	e008      	b.n	8004df2 <HAL_RCC_OscConfig+0x25e>
-        {
-          if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE)
- 8004de0:	f7ff f97a 	bl	80040d8 <HAL_GetTick>
- 8004de4:	0002      	movs	r2, r0
- 8004de6:	693b      	ldr	r3, [r7, #16]
- 8004de8:	1ad3      	subs	r3, r2, r3
- 8004dea:	2b02      	cmp	r3, #2
- 8004dec:	d901      	bls.n	8004df2 <HAL_RCC_OscConfig+0x25e>
-          {
-            return HAL_TIMEOUT;
- 8004dee:	2303      	movs	r3, #3
- 8004df0:	e0aa      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-        while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
- 8004df2:	4b38      	ldr	r3, [pc, #224]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004df4:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
- 8004df6:	2202      	movs	r2, #2
- 8004df8:	4013      	ands	r3, r2
- 8004dfa:	d0f1      	beq.n	8004de0 <HAL_RCC_OscConfig+0x24c>
- 8004dfc:	e018      	b.n	8004e30 <HAL_RCC_OscConfig+0x29c>
-        }
-      }
-      else
-      {
-        /* Disable the Internal Low Speed oscillator (LSI). */
-        __HAL_RCC_LSI_DISABLE();
- 8004dfe:	4b35      	ldr	r3, [pc, #212]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004e00:	6e1a      	ldr	r2, [r3, #96]	@ 0x60
- 8004e02:	4b34      	ldr	r3, [pc, #208]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004e04:	2101      	movs	r1, #1
- 8004e06:	438a      	bics	r2, r1
- 8004e08:	661a      	str	r2, [r3, #96]	@ 0x60
-
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8004e0a:	f7ff f965 	bl	80040d8 <HAL_GetTick>
- 8004e0e:	0003      	movs	r3, r0
- 8004e10:	613b      	str	r3, [r7, #16]
-
-        /* Wait till LSI is disabled */
-        while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U)
- 8004e12:	e008      	b.n	8004e26 <HAL_RCC_OscConfig+0x292>
-        {
-          if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE)
- 8004e14:	f7ff f960 	bl	80040d8 <HAL_GetTick>
- 8004e18:	0002      	movs	r2, r0
- 8004e1a:	693b      	ldr	r3, [r7, #16]
- 8004e1c:	1ad3      	subs	r3, r2, r3
- 8004e1e:	2b02      	cmp	r3, #2
- 8004e20:	d901      	bls.n	8004e26 <HAL_RCC_OscConfig+0x292>
-          {
-            return HAL_TIMEOUT;
- 8004e22:	2303      	movs	r3, #3
- 8004e24:	e090      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-        while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U)
- 8004e26:	4b2b      	ldr	r3, [pc, #172]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004e28:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
- 8004e2a:	2202      	movs	r2, #2
- 8004e2c:	4013      	ands	r3, r2
- 8004e2e:	d1f1      	bne.n	8004e14 <HAL_RCC_OscConfig+0x280>
-        }
-      }
-    }
-  }
-  /*------------------------------ LSE Configuration -------------------------*/
-  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
- 8004e30:	687b      	ldr	r3, [r7, #4]
- 8004e32:	681b      	ldr	r3, [r3, #0]
- 8004e34:	2204      	movs	r2, #4
- 8004e36:	4013      	ands	r3, r2
- 8004e38:	d100      	bne.n	8004e3c <HAL_RCC_OscConfig+0x2a8>
- 8004e3a:	e084      	b.n	8004f46 <HAL_RCC_OscConfig+0x3b2>
-  {
-    FlagStatus       pwrclkchanged = RESET;
- 8004e3c:	230f      	movs	r3, #15
- 8004e3e:	18fb      	adds	r3, r7, r3
- 8004e40:	2200      	movs	r2, #0
- 8004e42:	701a      	strb	r2, [r3, #0]
-
-    /* Check the parameters */
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
-    /* When the LSE is used as system clock, it is not allowed disable it */
-    if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
- 8004e44:	4b23      	ldr	r3, [pc, #140]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004e46:	689b      	ldr	r3, [r3, #8]
- 8004e48:	2238      	movs	r2, #56	@ 0x38
- 8004e4a:	4013      	ands	r3, r2
- 8004e4c:	2b20      	cmp	r3, #32
- 8004e4e:	d106      	bne.n	8004e5e <HAL_RCC_OscConfig+0x2ca>
-    {
-      if (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)
- 8004e50:	687b      	ldr	r3, [r7, #4]
- 8004e52:	689b      	ldr	r3, [r3, #8]
- 8004e54:	2b00      	cmp	r3, #0
- 8004e56:	d000      	beq.n	8004e5a <HAL_RCC_OscConfig+0x2c6>
- 8004e58:	e075      	b.n	8004f46 <HAL_RCC_OscConfig+0x3b2>
-      {
-        return HAL_ERROR;
- 8004e5a:	2301      	movs	r3, #1
- 8004e5c:	e074      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-    }
-    else
-    {
-      /* Update LSE configuration in RTC Domain control register    */
-      /* Set the new LSE configuration -----------------------------------------*/
-      __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
- 8004e5e:	687b      	ldr	r3, [r7, #4]
- 8004e60:	689b      	ldr	r3, [r3, #8]
- 8004e62:	2b01      	cmp	r3, #1
- 8004e64:	d106      	bne.n	8004e74 <HAL_RCC_OscConfig+0x2e0>
- 8004e66:	4b1b      	ldr	r3, [pc, #108]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004e68:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
- 8004e6a:	4b1a      	ldr	r3, [pc, #104]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004e6c:	2101      	movs	r1, #1
- 8004e6e:	430a      	orrs	r2, r1
- 8004e70:	65da      	str	r2, [r3, #92]	@ 0x5c
- 8004e72:	e01c      	b.n	8004eae <HAL_RCC_OscConfig+0x31a>
- 8004e74:	687b      	ldr	r3, [r7, #4]
- 8004e76:	689b      	ldr	r3, [r3, #8]
- 8004e78:	2b05      	cmp	r3, #5
- 8004e7a:	d10c      	bne.n	8004e96 <HAL_RCC_OscConfig+0x302>
- 8004e7c:	4b15      	ldr	r3, [pc, #84]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004e7e:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
- 8004e80:	4b14      	ldr	r3, [pc, #80]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004e82:	2104      	movs	r1, #4
- 8004e84:	430a      	orrs	r2, r1
- 8004e86:	65da      	str	r2, [r3, #92]	@ 0x5c
- 8004e88:	4b12      	ldr	r3, [pc, #72]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004e8a:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
- 8004e8c:	4b11      	ldr	r3, [pc, #68]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004e8e:	2101      	movs	r1, #1
- 8004e90:	430a      	orrs	r2, r1
- 8004e92:	65da      	str	r2, [r3, #92]	@ 0x5c
- 8004e94:	e00b      	b.n	8004eae <HAL_RCC_OscConfig+0x31a>
- 8004e96:	4b0f      	ldr	r3, [pc, #60]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004e98:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
- 8004e9a:	4b0e      	ldr	r3, [pc, #56]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004e9c:	2101      	movs	r1, #1
- 8004e9e:	438a      	bics	r2, r1
- 8004ea0:	65da      	str	r2, [r3, #92]	@ 0x5c
- 8004ea2:	4b0c      	ldr	r3, [pc, #48]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004ea4:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
- 8004ea6:	4b0b      	ldr	r3, [pc, #44]	@ (8004ed4 <HAL_RCC_OscConfig+0x340>)
- 8004ea8:	2104      	movs	r1, #4
- 8004eaa:	438a      	bics	r2, r1
- 8004eac:	65da      	str	r2, [r3, #92]	@ 0x5c
-
-      /* Check the LSE State */
-      if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
- 8004eae:	687b      	ldr	r3, [r7, #4]
- 8004eb0:	689b      	ldr	r3, [r3, #8]
- 8004eb2:	2b00      	cmp	r3, #0
- 8004eb4:	d028      	beq.n	8004f08 <HAL_RCC_OscConfig+0x374>
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8004eb6:	f7ff f90f 	bl	80040d8 <HAL_GetTick>
- 8004eba:	0003      	movs	r3, r0
- 8004ebc:	613b      	str	r3, [r7, #16]
-
-        /* Wait till LSE is ready */
-        while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
- 8004ebe:	e01d      	b.n	8004efc <HAL_RCC_OscConfig+0x368>
-        {
-          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- 8004ec0:	f7ff f90a 	bl	80040d8 <HAL_GetTick>
- 8004ec4:	0002      	movs	r2, r0
- 8004ec6:	693b      	ldr	r3, [r7, #16]
- 8004ec8:	1ad3      	subs	r3, r2, r3
- 8004eca:	4a0b      	ldr	r2, [pc, #44]	@ (8004ef8 <HAL_RCC_OscConfig+0x364>)
- 8004ecc:	4293      	cmp	r3, r2
- 8004ece:	d915      	bls.n	8004efc <HAL_RCC_OscConfig+0x368>
-          {
-            return HAL_TIMEOUT;
- 8004ed0:	2303      	movs	r3, #3
- 8004ed2:	e039      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
- 8004ed4:	40021000 	.word	0x40021000
- 8004ed8:	fffeffff 	.word	0xfffeffff
- 8004edc:	fffbffff 	.word	0xfffbffff
- 8004ee0:	ffff80ff 	.word	0xffff80ff
- 8004ee4:	ffffc7ff 	.word	0xffffc7ff
- 8004ee8:	02dc6c00 	.word	0x02dc6c00
- 8004eec:	20000024 	.word	0x20000024
- 8004ef0:	20000028 	.word	0x20000028
- 8004ef4:	fffffeff 	.word	0xfffffeff
- 8004ef8:	00001388 	.word	0x00001388
-        while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
- 8004efc:	4b14      	ldr	r3, [pc, #80]	@ (8004f50 <HAL_RCC_OscConfig+0x3bc>)
- 8004efe:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
- 8004f00:	2202      	movs	r2, #2
- 8004f02:	4013      	ands	r3, r2
- 8004f04:	d0dc      	beq.n	8004ec0 <HAL_RCC_OscConfig+0x32c>
- 8004f06:	e013      	b.n	8004f30 <HAL_RCC_OscConfig+0x39c>
-        }
-      }
-      else
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
- 8004f08:	f7ff f8e6 	bl	80040d8 <HAL_GetTick>
- 8004f0c:	0003      	movs	r3, r0
- 8004f0e:	613b      	str	r3, [r7, #16]
-
-        /* Wait till LSE is disabled */
-        while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U)
- 8004f10:	e009      	b.n	8004f26 <HAL_RCC_OscConfig+0x392>
-        {
-          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- 8004f12:	f7ff f8e1 	bl	80040d8 <HAL_GetTick>
- 8004f16:	0002      	movs	r2, r0
- 8004f18:	693b      	ldr	r3, [r7, #16]
- 8004f1a:	1ad3      	subs	r3, r2, r3
- 8004f1c:	4a0d      	ldr	r2, [pc, #52]	@ (8004f54 <HAL_RCC_OscConfig+0x3c0>)
- 8004f1e:	4293      	cmp	r3, r2
- 8004f20:	d901      	bls.n	8004f26 <HAL_RCC_OscConfig+0x392>
-          {
-            return HAL_TIMEOUT;
- 8004f22:	2303      	movs	r3, #3
- 8004f24:	e010      	b.n	8004f48 <HAL_RCC_OscConfig+0x3b4>
-        while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U)
- 8004f26:	4b0a      	ldr	r3, [pc, #40]	@ (8004f50 <HAL_RCC_OscConfig+0x3bc>)
- 8004f28:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
- 8004f2a:	2202      	movs	r2, #2
- 8004f2c:	4013      	ands	r3, r2
- 8004f2e:	d1f0      	bne.n	8004f12 <HAL_RCC_OscConfig+0x37e>
-          }
-        }
-      }
-
-      /* Restore clock configuration if changed */
-      if (pwrclkchanged == SET)
- 8004f30:	230f      	movs	r3, #15
- 8004f32:	18fb      	adds	r3, r7, r3
- 8004f34:	781b      	ldrb	r3, [r3, #0]
- 8004f36:	2b01      	cmp	r3, #1
- 8004f38:	d105      	bne.n	8004f46 <HAL_RCC_OscConfig+0x3b2>
-      {
-        __HAL_RCC_PWR_CLK_DISABLE();
- 8004f3a:	4b05      	ldr	r3, [pc, #20]	@ (8004f50 <HAL_RCC_OscConfig+0x3bc>)
- 8004f3c:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
- 8004f3e:	4b04      	ldr	r3, [pc, #16]	@ (8004f50 <HAL_RCC_OscConfig+0x3bc>)
- 8004f40:	4905      	ldr	r1, [pc, #20]	@ (8004f58 <HAL_RCC_OscConfig+0x3c4>)
- 8004f42:	400a      	ands	r2, r1
- 8004f44:	63da      	str	r2, [r3, #60]	@ 0x3c
-        }
+ 8003352:	2001      	movs	r0, #1
       }
     }
   }
 #endif /* RCC_CR_HSIUSB48ON */
   return HAL_OK;
- 8004f46:	2300      	movs	r3, #0
 }
- 8004f48:	0018      	movs	r0, r3
- 8004f4a:	46bd      	mov	sp, r7
- 8004f4c:	b006      	add	sp, #24
- 8004f4e:	bd80      	pop	{r7, pc}
- 8004f50:	40021000 	.word	0x40021000
- 8004f54:	00001388 	.word	0x00001388
- 8004f58:	efffffff 	.word	0xefffffff
+ 8003354:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
+ 8003356:	6803      	ldr	r3, [r0, #0]
+ 8003358:	07db      	lsls	r3, r3, #31
+ 800335a:	d40d      	bmi.n	8003378 <HAL_RCC_OscConfig+0x2c>
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
+ 800335c:	682b      	ldr	r3, [r5, #0]
+ 800335e:	079b      	lsls	r3, r3, #30
+ 8003360:	d44f      	bmi.n	8003402 <HAL_RCC_OscConfig+0xb6>
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
+ 8003362:	682b      	ldr	r3, [r5, #0]
+ 8003364:	071b      	lsls	r3, r3, #28
+ 8003366:	d500      	bpl.n	800336a <HAL_RCC_OscConfig+0x1e>
+ 8003368:	e0a4      	b.n	80034b4 <HAL_RCC_OscConfig+0x168>
+  if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
+ 800336a:	2204      	movs	r2, #4
+ 800336c:	682b      	ldr	r3, [r5, #0]
+ 800336e:	4213      	tst	r3, r2
+ 8003370:	d000      	beq.n	8003374 <HAL_RCC_OscConfig+0x28>
+ 8003372:	e0cf      	b.n	8003514 <HAL_RCC_OscConfig+0x1c8>
+  return HAL_OK;
+ 8003374:	2000      	movs	r0, #0
+ 8003376:	e7ed      	b.n	8003354 <HAL_RCC_OscConfig+0x8>
+    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 8003378:	2138      	movs	r1, #56	@ 0x38
+ 800337a:	4c85      	ldr	r4, [pc, #532]	@ (8003590 <HAL_RCC_OscConfig+0x244>)
+      if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)
+ 800337c:	6843      	ldr	r3, [r0, #4]
+    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 800337e:	68a2      	ldr	r2, [r4, #8]
+ 8003380:	400a      	ands	r2, r1
+    if (temp_sysclksrc == RCC_CFGR_SWS_HSE)
+ 8003382:	2a08      	cmp	r2, #8
+ 8003384:	d102      	bne.n	800338c <HAL_RCC_OscConfig+0x40>
+      if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF)
+ 8003386:	2b00      	cmp	r3, #0
+ 8003388:	d1e8      	bne.n	800335c <HAL_RCC_OscConfig+0x10>
+ 800338a:	e7e2      	b.n	8003352 <HAL_RCC_OscConfig+0x6>
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 800338c:	2280      	movs	r2, #128	@ 0x80
+ 800338e:	0252      	lsls	r2, r2, #9
+ 8003390:	4293      	cmp	r3, r2
+ 8003392:	d111      	bne.n	80033b8 <HAL_RCC_OscConfig+0x6c>
+ 8003394:	6822      	ldr	r2, [r4, #0]
+ 8003396:	4313      	orrs	r3, r2
+ 8003398:	6023      	str	r3, [r4, #0]
+        tickstart = HAL_GetTick();
+ 800339a:	f7ff faa1 	bl	80028e0 <HAL_GetTick>
+        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ 800339e:	2780      	movs	r7, #128	@ 0x80
+        tickstart = HAL_GetTick();
+ 80033a0:	0006      	movs	r6, r0
+        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ 80033a2:	02bf      	lsls	r7, r7, #10
+ 80033a4:	6823      	ldr	r3, [r4, #0]
+ 80033a6:	423b      	tst	r3, r7
+ 80033a8:	d1d8      	bne.n	800335c <HAL_RCC_OscConfig+0x10>
+          if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
+ 80033aa:	f7ff fa99 	bl	80028e0 <HAL_GetTick>
+ 80033ae:	1b80      	subs	r0, r0, r6
+ 80033b0:	2864      	cmp	r0, #100	@ 0x64
+ 80033b2:	d9f7      	bls.n	80033a4 <HAL_RCC_OscConfig+0x58>
+            return HAL_TIMEOUT;
+ 80033b4:	2003      	movs	r0, #3
+ 80033b6:	e7cd      	b.n	8003354 <HAL_RCC_OscConfig+0x8>
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 80033b8:	21a0      	movs	r1, #160	@ 0xa0
+ 80033ba:	02c9      	lsls	r1, r1, #11
+ 80033bc:	428b      	cmp	r3, r1
+ 80033be:	d108      	bne.n	80033d2 <HAL_RCC_OscConfig+0x86>
+ 80033c0:	2380      	movs	r3, #128	@ 0x80
+ 80033c2:	6821      	ldr	r1, [r4, #0]
+ 80033c4:	02db      	lsls	r3, r3, #11
+ 80033c6:	430b      	orrs	r3, r1
+ 80033c8:	6023      	str	r3, [r4, #0]
+ 80033ca:	6823      	ldr	r3, [r4, #0]
+ 80033cc:	431a      	orrs	r2, r3
+ 80033ce:	6022      	str	r2, [r4, #0]
+      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 80033d0:	e7e3      	b.n	800339a <HAL_RCC_OscConfig+0x4e>
+      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
+ 80033d2:	6822      	ldr	r2, [r4, #0]
+ 80033d4:	496f      	ldr	r1, [pc, #444]	@ (8003594 <HAL_RCC_OscConfig+0x248>)
+ 80033d6:	400a      	ands	r2, r1
+ 80033d8:	6022      	str	r2, [r4, #0]
+ 80033da:	6822      	ldr	r2, [r4, #0]
+ 80033dc:	496e      	ldr	r1, [pc, #440]	@ (8003598 <HAL_RCC_OscConfig+0x24c>)
+ 80033de:	400a      	ands	r2, r1
+ 80033e0:	6022      	str	r2, [r4, #0]
+      if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
+ 80033e2:	2b00      	cmp	r3, #0
+ 80033e4:	d1d9      	bne.n	800339a <HAL_RCC_OscConfig+0x4e>
+        tickstart = HAL_GetTick();
+ 80033e6:	f7ff fa7b 	bl	80028e0 <HAL_GetTick>
+        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
+ 80033ea:	2780      	movs	r7, #128	@ 0x80
+        tickstart = HAL_GetTick();
+ 80033ec:	0006      	movs	r6, r0
+        while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U)
+ 80033ee:	02bf      	lsls	r7, r7, #10
+ 80033f0:	6823      	ldr	r3, [r4, #0]
+ 80033f2:	423b      	tst	r3, r7
+ 80033f4:	d0b2      	beq.n	800335c <HAL_RCC_OscConfig+0x10>
+          if ((HAL_GetTick() - tickstart) > RCC_HSE_TIMEOUT_VALUE)
+ 80033f6:	f7ff fa73 	bl	80028e0 <HAL_GetTick>
+ 80033fa:	1b80      	subs	r0, r0, r6
+ 80033fc:	2864      	cmp	r0, #100	@ 0x64
+ 80033fe:	d9f7      	bls.n	80033f0 <HAL_RCC_OscConfig+0xa4>
+ 8003400:	e7d8      	b.n	80033b4 <HAL_RCC_OscConfig+0x68>
+    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 8003402:	2238      	movs	r2, #56	@ 0x38
+ 8003404:	4c62      	ldr	r4, [pc, #392]	@ (8003590 <HAL_RCC_OscConfig+0x244>)
+      if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
+ 8003406:	68eb      	ldr	r3, [r5, #12]
+    temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
+ 8003408:	68a1      	ldr	r1, [r4, #8]
+    if (temp_sysclksrc == RCC_CFGR_SWS_HSI)
+ 800340a:	4211      	tst	r1, r2
+ 800340c:	d11c      	bne.n	8003448 <HAL_RCC_OscConfig+0xfc>
+      if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF)
+ 800340e:	2b00      	cmp	r3, #0
+ 8003410:	d09f      	beq.n	8003352 <HAL_RCC_OscConfig+0x6>
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 8003412:	6862      	ldr	r2, [r4, #4]
+ 8003414:	696b      	ldr	r3, [r5, #20]
+ 8003416:	4961      	ldr	r1, [pc, #388]	@ (800359c <HAL_RCC_OscConfig+0x250>)
+ 8003418:	021b      	lsls	r3, r3, #8
+ 800341a:	400a      	ands	r2, r1
+ 800341c:	4313      	orrs	r3, r2
+ 800341e:	6063      	str	r3, [r4, #4]
+          __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
+ 8003420:	6823      	ldr	r3, [r4, #0]
+ 8003422:	4a5f      	ldr	r2, [pc, #380]	@ (80035a0 <HAL_RCC_OscConfig+0x254>)
+          SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
+ 8003424:	495f      	ldr	r1, [pc, #380]	@ (80035a4 <HAL_RCC_OscConfig+0x258>)
+          __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
+ 8003426:	4013      	ands	r3, r2
+ 8003428:	692a      	ldr	r2, [r5, #16]
+ 800342a:	4313      	orrs	r3, r2
+ 800342c:	6023      	str	r3, [r4, #0]
+          SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
+ 800342e:	6823      	ldr	r3, [r4, #0]
+ 8003430:	4a5d      	ldr	r2, [pc, #372]	@ (80035a8 <HAL_RCC_OscConfig+0x25c>)
+ 8003432:	049b      	lsls	r3, r3, #18
+ 8003434:	0f5b      	lsrs	r3, r3, #29
+ 8003436:	40da      	lsrs	r2, r3
+        if (HAL_InitTick(uwTickPrio) != HAL_OK)
+ 8003438:	4b5c      	ldr	r3, [pc, #368]	@ (80035ac <HAL_RCC_OscConfig+0x260>)
+          SystemCoreClock = (HSI_VALUE / (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos)));
+ 800343a:	600a      	str	r2, [r1, #0]
+        if (HAL_InitTick(uwTickPrio) != HAL_OK)
+ 800343c:	6818      	ldr	r0, [r3, #0]
+ 800343e:	f7ff fa0f 	bl	8002860 <HAL_InitTick>
+ 8003442:	2800      	cmp	r0, #0
+ 8003444:	d08d      	beq.n	8003362 <HAL_RCC_OscConfig+0x16>
+ 8003446:	e784      	b.n	8003352 <HAL_RCC_OscConfig+0x6>
+      if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF)
+ 8003448:	2b00      	cmp	r3, #0
+ 800344a:	d020      	beq.n	800348e <HAL_RCC_OscConfig+0x142>
+        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
+ 800344c:	6823      	ldr	r3, [r4, #0]
+ 800344e:	4a54      	ldr	r2, [pc, #336]	@ (80035a0 <HAL_RCC_OscConfig+0x254>)
+        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ 8003450:	2780      	movs	r7, #128	@ 0x80
+        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
+ 8003452:	4013      	ands	r3, r2
+ 8003454:	692a      	ldr	r2, [r5, #16]
+        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ 8003456:	00ff      	lsls	r7, r7, #3
+        __HAL_RCC_HSI_CONFIG(RCC_OscInitStruct->HSIDiv);
+ 8003458:	4313      	orrs	r3, r2
+ 800345a:	6023      	str	r3, [r4, #0]
+        __HAL_RCC_HSI_ENABLE();
+ 800345c:	2380      	movs	r3, #128	@ 0x80
+ 800345e:	6822      	ldr	r2, [r4, #0]
+ 8003460:	005b      	lsls	r3, r3, #1
+ 8003462:	4313      	orrs	r3, r2
+ 8003464:	6023      	str	r3, [r4, #0]
+        tickstart = HAL_GetTick();
+ 8003466:	f7ff fa3b 	bl	80028e0 <HAL_GetTick>
+ 800346a:	0006      	movs	r6, r0
+        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ 800346c:	6823      	ldr	r3, [r4, #0]
+ 800346e:	423b      	tst	r3, r7
+ 8003470:	d007      	beq.n	8003482 <HAL_RCC_OscConfig+0x136>
+        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
+ 8003472:	6862      	ldr	r2, [r4, #4]
+ 8003474:	696b      	ldr	r3, [r5, #20]
+ 8003476:	4949      	ldr	r1, [pc, #292]	@ (800359c <HAL_RCC_OscConfig+0x250>)
+ 8003478:	021b      	lsls	r3, r3, #8
+ 800347a:	400a      	ands	r2, r1
+ 800347c:	4313      	orrs	r3, r2
+ 800347e:	6063      	str	r3, [r4, #4]
+ 8003480:	e76f      	b.n	8003362 <HAL_RCC_OscConfig+0x16>
+          if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
+ 8003482:	f7ff fa2d 	bl	80028e0 <HAL_GetTick>
+ 8003486:	1b80      	subs	r0, r0, r6
+ 8003488:	2802      	cmp	r0, #2
+ 800348a:	d9ef      	bls.n	800346c <HAL_RCC_OscConfig+0x120>
+ 800348c:	e792      	b.n	80033b4 <HAL_RCC_OscConfig+0x68>
+        __HAL_RCC_HSI_DISABLE();
+ 800348e:	6823      	ldr	r3, [r4, #0]
+ 8003490:	4a47      	ldr	r2, [pc, #284]	@ (80035b0 <HAL_RCC_OscConfig+0x264>)
+        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
+ 8003492:	2780      	movs	r7, #128	@ 0x80
+        __HAL_RCC_HSI_DISABLE();
+ 8003494:	4013      	ands	r3, r2
+ 8003496:	6023      	str	r3, [r4, #0]
+        tickstart = HAL_GetTick();
+ 8003498:	f7ff fa22 	bl	80028e0 <HAL_GetTick>
+ 800349c:	0006      	movs	r6, r0
+        while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U)
+ 800349e:	00ff      	lsls	r7, r7, #3
+ 80034a0:	6823      	ldr	r3, [r4, #0]
+ 80034a2:	423b      	tst	r3, r7
+ 80034a4:	d100      	bne.n	80034a8 <HAL_RCC_OscConfig+0x15c>
+ 80034a6:	e75c      	b.n	8003362 <HAL_RCC_OscConfig+0x16>
+          if ((HAL_GetTick() - tickstart) > RCC_HSI_TIMEOUT_VALUE)
+ 80034a8:	f7ff fa1a 	bl	80028e0 <HAL_GetTick>
+ 80034ac:	1b80      	subs	r0, r0, r6
+ 80034ae:	2802      	cmp	r0, #2
+ 80034b0:	d9f6      	bls.n	80034a0 <HAL_RCC_OscConfig+0x154>
+ 80034b2:	e77f      	b.n	80033b4 <HAL_RCC_OscConfig+0x68>
+    if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
+ 80034b4:	2138      	movs	r1, #56	@ 0x38
+ 80034b6:	4c36      	ldr	r4, [pc, #216]	@ (8003590 <HAL_RCC_OscConfig+0x244>)
+      if (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)
+ 80034b8:	69aa      	ldr	r2, [r5, #24]
+    if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
+ 80034ba:	68a3      	ldr	r3, [r4, #8]
+ 80034bc:	400b      	ands	r3, r1
+ 80034be:	2b18      	cmp	r3, #24
+ 80034c0:	d103      	bne.n	80034ca <HAL_RCC_OscConfig+0x17e>
+      if (RCC_OscInitStruct->LSIState == RCC_LSI_OFF)
+ 80034c2:	2a00      	cmp	r2, #0
+ 80034c4:	d000      	beq.n	80034c8 <HAL_RCC_OscConfig+0x17c>
+ 80034c6:	e750      	b.n	800336a <HAL_RCC_OscConfig+0x1e>
+ 80034c8:	e743      	b.n	8003352 <HAL_RCC_OscConfig+0x6>
+      if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF)
+ 80034ca:	2301      	movs	r3, #1
+ 80034cc:	2a00      	cmp	r2, #0
+ 80034ce:	d010      	beq.n	80034f2 <HAL_RCC_OscConfig+0x1a6>
+        __HAL_RCC_LSI_ENABLE();
+ 80034d0:	6e22      	ldr	r2, [r4, #96]	@ 0x60
+        while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
+ 80034d2:	2702      	movs	r7, #2
+        __HAL_RCC_LSI_ENABLE();
+ 80034d4:	4313      	orrs	r3, r2
+ 80034d6:	6623      	str	r3, [r4, #96]	@ 0x60
+        tickstart = HAL_GetTick();
+ 80034d8:	f7ff fa02 	bl	80028e0 <HAL_GetTick>
+ 80034dc:	0006      	movs	r6, r0
+        while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
+ 80034de:	6e23      	ldr	r3, [r4, #96]	@ 0x60
+ 80034e0:	423b      	tst	r3, r7
+ 80034e2:	d000      	beq.n	80034e6 <HAL_RCC_OscConfig+0x19a>
+ 80034e4:	e741      	b.n	800336a <HAL_RCC_OscConfig+0x1e>
+          if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE)
+ 80034e6:	f7ff f9fb 	bl	80028e0 <HAL_GetTick>
+ 80034ea:	1b80      	subs	r0, r0, r6
+ 80034ec:	2802      	cmp	r0, #2
+ 80034ee:	d9f6      	bls.n	80034de <HAL_RCC_OscConfig+0x192>
+ 80034f0:	e760      	b.n	80033b4 <HAL_RCC_OscConfig+0x68>
+        __HAL_RCC_LSI_DISABLE();
+ 80034f2:	6e22      	ldr	r2, [r4, #96]	@ 0x60
+        while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U)
+ 80034f4:	2702      	movs	r7, #2
+        __HAL_RCC_LSI_DISABLE();
+ 80034f6:	439a      	bics	r2, r3
+ 80034f8:	6622      	str	r2, [r4, #96]	@ 0x60
+        tickstart = HAL_GetTick();
+ 80034fa:	f7ff f9f1 	bl	80028e0 <HAL_GetTick>
+ 80034fe:	0006      	movs	r6, r0
+        while (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) != 0U)
+ 8003500:	6e23      	ldr	r3, [r4, #96]	@ 0x60
+ 8003502:	423b      	tst	r3, r7
+ 8003504:	d100      	bne.n	8003508 <HAL_RCC_OscConfig+0x1bc>
+ 8003506:	e730      	b.n	800336a <HAL_RCC_OscConfig+0x1e>
+          if ((HAL_GetTick() - tickstart) > RCC_LSI_TIMEOUT_VALUE)
+ 8003508:	f7ff f9ea 	bl	80028e0 <HAL_GetTick>
+ 800350c:	1b80      	subs	r0, r0, r6
+ 800350e:	2802      	cmp	r0, #2
+ 8003510:	d9f6      	bls.n	8003500 <HAL_RCC_OscConfig+0x1b4>
+ 8003512:	e74f      	b.n	80033b4 <HAL_RCC_OscConfig+0x68>
+    if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
+ 8003514:	2138      	movs	r1, #56	@ 0x38
+ 8003516:	4c1e      	ldr	r4, [pc, #120]	@ (8003590 <HAL_RCC_OscConfig+0x244>)
+      if (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)
+ 8003518:	68a8      	ldr	r0, [r5, #8]
+    if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
+ 800351a:	68a3      	ldr	r3, [r4, #8]
+ 800351c:	400b      	ands	r3, r1
+ 800351e:	2b20      	cmp	r3, #32
+ 8003520:	d103      	bne.n	800352a <HAL_RCC_OscConfig+0x1de>
+      if (RCC_OscInitStruct->LSEState == RCC_LSE_OFF)
+ 8003522:	4243      	negs	r3, r0
+ 8003524:	4158      	adcs	r0, r3
+ 8003526:	b2c0      	uxtb	r0, r0
+ 8003528:	e714      	b.n	8003354 <HAL_RCC_OscConfig+0x8>
+      __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 800352a:	6de3      	ldr	r3, [r4, #92]	@ 0x5c
+ 800352c:	2801      	cmp	r0, #1
+ 800352e:	d110      	bne.n	8003552 <HAL_RCC_OscConfig+0x206>
+ 8003530:	4303      	orrs	r3, r0
+ 8003532:	65e3      	str	r3, [r4, #92]	@ 0x5c
+        tickstart = HAL_GetTick();
+ 8003534:	f7ff f9d4 	bl	80028e0 <HAL_GetTick>
+        while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
+ 8003538:	2602      	movs	r6, #2
+        tickstart = HAL_GetTick();
+ 800353a:	0005      	movs	r5, r0
+        while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
+ 800353c:	6de3      	ldr	r3, [r4, #92]	@ 0x5c
+ 800353e:	4233      	tst	r3, r6
+ 8003540:	d000      	beq.n	8003544 <HAL_RCC_OscConfig+0x1f8>
+ 8003542:	e717      	b.n	8003374 <HAL_RCC_OscConfig+0x28>
+          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 8003544:	f7ff f9cc 	bl	80028e0 <HAL_GetTick>
+ 8003548:	4b1a      	ldr	r3, [pc, #104]	@ (80035b4 <HAL_RCC_OscConfig+0x268>)
+ 800354a:	1b40      	subs	r0, r0, r5
+ 800354c:	4298      	cmp	r0, r3
+ 800354e:	d9f5      	bls.n	800353c <HAL_RCC_OscConfig+0x1f0>
+ 8003550:	e730      	b.n	80033b4 <HAL_RCC_OscConfig+0x68>
+      __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
+ 8003552:	2805      	cmp	r0, #5
+ 8003554:	d105      	bne.n	8003562 <HAL_RCC_OscConfig+0x216>
+ 8003556:	4313      	orrs	r3, r2
+ 8003558:	65e3      	str	r3, [r4, #92]	@ 0x5c
+ 800355a:	2301      	movs	r3, #1
+ 800355c:	6de2      	ldr	r2, [r4, #92]	@ 0x5c
+ 800355e:	4313      	orrs	r3, r2
+ 8003560:	e7e7      	b.n	8003532 <HAL_RCC_OscConfig+0x1e6>
+ 8003562:	2101      	movs	r1, #1
+ 8003564:	438b      	bics	r3, r1
+ 8003566:	65e3      	str	r3, [r4, #92]	@ 0x5c
+ 8003568:	6de3      	ldr	r3, [r4, #92]	@ 0x5c
+ 800356a:	4393      	bics	r3, r2
+ 800356c:	65e3      	str	r3, [r4, #92]	@ 0x5c
+      if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF)
+ 800356e:	2800      	cmp	r0, #0
+ 8003570:	d1e0      	bne.n	8003534 <HAL_RCC_OscConfig+0x1e8>
+        tickstart = HAL_GetTick();
+ 8003572:	f7ff f9b5 	bl	80028e0 <HAL_GetTick>
+        while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U)
+ 8003576:	2602      	movs	r6, #2
+        tickstart = HAL_GetTick();
+ 8003578:	0005      	movs	r5, r0
+        while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) != 0U)
+ 800357a:	6de3      	ldr	r3, [r4, #92]	@ 0x5c
+ 800357c:	4233      	tst	r3, r6
+ 800357e:	d100      	bne.n	8003582 <HAL_RCC_OscConfig+0x236>
+ 8003580:	e6f8      	b.n	8003374 <HAL_RCC_OscConfig+0x28>
+          if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 8003582:	f7ff f9ad 	bl	80028e0 <HAL_GetTick>
+ 8003586:	4b0b      	ldr	r3, [pc, #44]	@ (80035b4 <HAL_RCC_OscConfig+0x268>)
+ 8003588:	1b40      	subs	r0, r0, r5
+ 800358a:	4298      	cmp	r0, r3
+ 800358c:	d9f5      	bls.n	800357a <HAL_RCC_OscConfig+0x22e>
+ 800358e:	e711      	b.n	80033b4 <HAL_RCC_OscConfig+0x68>
+ 8003590:	40021000 	.word	0x40021000
+ 8003594:	fffeffff 	.word	0xfffeffff
+ 8003598:	fffbffff 	.word	0xfffbffff
+ 800359c:	ffff80ff 	.word	0xffff80ff
+ 80035a0:	ffffc7ff 	.word	0xffffc7ff
+ 80035a4:	20000024 	.word	0x20000024
+ 80035a8:	02dc6c00 	.word	0x02dc6c00
+ 80035ac:	2000002c 	.word	0x2000002c
+ 80035b0:	fffffeff 	.word	0xfffffeff
+ 80035b4:	00001388 	.word	0x00001388
 
-08004f5c <HAL_RCC_ClockConfig>:
-  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
-  *         (for more details refer to section above "Initialization/de-initialization functions")
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
-{
- 8004f5c:	b580      	push	{r7, lr}
- 8004f5e:	b084      	sub	sp, #16
- 8004f60:	af00      	add	r7, sp, #0
- 8004f62:	6078      	str	r0, [r7, #4]
- 8004f64:	6039      	str	r1, [r7, #0]
-  uint32_t tickstart;
-
-  /* Check Null pointer */
-  if (RCC_ClkInitStruct == NULL)
- 8004f66:	687b      	ldr	r3, [r7, #4]
- 8004f68:	2b00      	cmp	r3, #0
- 8004f6a:	d101      	bne.n	8004f70 <HAL_RCC_ClockConfig+0x14>
-  {
-    return HAL_ERROR;
- 8004f6c:	2301      	movs	r3, #1
- 8004f6e:	e0e9      	b.n	8005144 <HAL_RCC_ClockConfig+0x1e8>
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
-    must be correctly programmed according to the frequency of the FLASH clock
-    (HCLK) and the supply voltage of the device. */
-
-  /* Increasing the number of wait states because of higher CPU frequency */
-  if (FLatency > __HAL_FLASH_GET_LATENCY())
- 8004f70:	4b76      	ldr	r3, [pc, #472]	@ (800514c <HAL_RCC_ClockConfig+0x1f0>)
- 8004f72:	681b      	ldr	r3, [r3, #0]
- 8004f74:	2207      	movs	r2, #7
- 8004f76:	4013      	ands	r3, r2
- 8004f78:	683a      	ldr	r2, [r7, #0]
- 8004f7a:	429a      	cmp	r2, r3
- 8004f7c:	d91e      	bls.n	8004fbc <HAL_RCC_ClockConfig+0x60>
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
- 8004f7e:	4b73      	ldr	r3, [pc, #460]	@ (800514c <HAL_RCC_ClockConfig+0x1f0>)
- 8004f80:	681b      	ldr	r3, [r3, #0]
- 8004f82:	2207      	movs	r2, #7
- 8004f84:	4393      	bics	r3, r2
- 8004f86:	0019      	movs	r1, r3
- 8004f88:	4b70      	ldr	r3, [pc, #448]	@ (800514c <HAL_RCC_ClockConfig+0x1f0>)
- 8004f8a:	683a      	ldr	r2, [r7, #0]
- 8004f8c:	430a      	orrs	r2, r1
- 8004f8e:	601a      	str	r2, [r3, #0]
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by polling the FLASH_ACR register */
-    tickstart = HAL_GetTick();
- 8004f90:	f7ff f8a2 	bl	80040d8 <HAL_GetTick>
- 8004f94:	0003      	movs	r3, r0
- 8004f96:	60fb      	str	r3, [r7, #12]
-
-    while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
- 8004f98:	e009      	b.n	8004fae <HAL_RCC_ClockConfig+0x52>
-    {
-      if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
- 8004f9a:	f7ff f89d 	bl	80040d8 <HAL_GetTick>
- 8004f9e:	0002      	movs	r2, r0
- 8004fa0:	68fb      	ldr	r3, [r7, #12]
- 8004fa2:	1ad3      	subs	r3, r2, r3
- 8004fa4:	4a6a      	ldr	r2, [pc, #424]	@ (8005150 <HAL_RCC_ClockConfig+0x1f4>)
- 8004fa6:	4293      	cmp	r3, r2
- 8004fa8:	d901      	bls.n	8004fae <HAL_RCC_ClockConfig+0x52>
-      {
-        return HAL_TIMEOUT;
- 8004faa:	2303      	movs	r3, #3
- 8004fac:	e0ca      	b.n	8005144 <HAL_RCC_ClockConfig+0x1e8>
-    while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
- 8004fae:	4b67      	ldr	r3, [pc, #412]	@ (800514c <HAL_RCC_ClockConfig+0x1f0>)
- 8004fb0:	681b      	ldr	r3, [r3, #0]
- 8004fb2:	2207      	movs	r2, #7
- 8004fb4:	4013      	ands	r3, r2
- 8004fb6:	683a      	ldr	r2, [r7, #0]
- 8004fb8:	429a      	cmp	r2, r3
- 8004fba:	d1ee      	bne.n	8004f9a <HAL_RCC_ClockConfig+0x3e>
-      }
-    }
-  }
-
-  /*-------------------------- HCLK Configuration --------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
- 8004fbc:	687b      	ldr	r3, [r7, #4]
- 8004fbe:	681b      	ldr	r3, [r3, #0]
- 8004fc0:	2202      	movs	r2, #2
- 8004fc2:	4013      	ands	r3, r2
- 8004fc4:	d017      	beq.n	8004ff6 <HAL_RCC_ClockConfig+0x9a>
-  {
-    /* Set the highest APB divider in order to ensure that we do not go through
-       a non-spec phase whatever we decrease or increase HCLK. */
-    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 8004fc6:	687b      	ldr	r3, [r7, #4]
- 8004fc8:	681b      	ldr	r3, [r3, #0]
- 8004fca:	2204      	movs	r2, #4
- 8004fcc:	4013      	ands	r3, r2
- 8004fce:	d008      	beq.n	8004fe2 <HAL_RCC_ClockConfig+0x86>
-    {
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
- 8004fd0:	4b60      	ldr	r3, [pc, #384]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 8004fd2:	689b      	ldr	r3, [r3, #8]
- 8004fd4:	4a60      	ldr	r2, [pc, #384]	@ (8005158 <HAL_RCC_ClockConfig+0x1fc>)
- 8004fd6:	401a      	ands	r2, r3
- 8004fd8:	4b5e      	ldr	r3, [pc, #376]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 8004fda:	21b0      	movs	r1, #176	@ 0xb0
- 8004fdc:	0109      	lsls	r1, r1, #4
- 8004fde:	430a      	orrs	r2, r1
- 8004fe0:	609a      	str	r2, [r3, #8]
-    }
-
-    /* Set the new HCLK clock divider */
-    assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
- 8004fe2:	4b5c      	ldr	r3, [pc, #368]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 8004fe4:	689b      	ldr	r3, [r3, #8]
- 8004fe6:	4a5d      	ldr	r2, [pc, #372]	@ (800515c <HAL_RCC_ClockConfig+0x200>)
- 8004fe8:	4013      	ands	r3, r2
- 8004fea:	0019      	movs	r1, r3
- 8004fec:	687b      	ldr	r3, [r7, #4]
- 8004fee:	68da      	ldr	r2, [r3, #12]
- 8004ff0:	4b58      	ldr	r3, [pc, #352]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 8004ff2:	430a      	orrs	r2, r1
- 8004ff4:	609a      	str	r2, [r3, #8]
-  }
-
-  /*------------------------- SYSCLK Configuration ---------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- 8004ff6:	687b      	ldr	r3, [r7, #4]
- 8004ff8:	681b      	ldr	r3, [r3, #0]
- 8004ffa:	2201      	movs	r2, #1
- 8004ffc:	4013      	ands	r3, r2
- 8004ffe:	d055      	beq.n	80050ac <HAL_RCC_ClockConfig+0x150>
-  {
-    assert_param(IS_RCC_SYSCLK(RCC_ClkInitStruct->SYSCLKDivider));
-    assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
-#if defined(RCC_CR_SYSDIV)
-    MODIFY_REG(RCC->CR, RCC_CR_SYSDIV, RCC_ClkInitStruct->SYSCLKDivider);
- 8005000:	4b54      	ldr	r3, [pc, #336]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 8005002:	681b      	ldr	r3, [r3, #0]
- 8005004:	221c      	movs	r2, #28
- 8005006:	4393      	bics	r3, r2
- 8005008:	0019      	movs	r1, r3
- 800500a:	687b      	ldr	r3, [r7, #4]
- 800500c:	689a      	ldr	r2, [r3, #8]
- 800500e:	4b51      	ldr	r3, [pc, #324]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 8005010:	430a      	orrs	r2, r1
- 8005012:	601a      	str	r2, [r3, #0]
-#endif /* RCC_CR_SYSDIV */
-
-    /* HSE is selected as System Clock Source */
-    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
- 8005014:	687b      	ldr	r3, [r7, #4]
- 8005016:	685b      	ldr	r3, [r3, #4]
- 8005018:	2b01      	cmp	r3, #1
- 800501a:	d107      	bne.n	800502c <HAL_RCC_ClockConfig+0xd0>
-    {
-      /* Check the HSE ready flag */
-      if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
- 800501c:	4b4d      	ldr	r3, [pc, #308]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 800501e:	681a      	ldr	r2, [r3, #0]
- 8005020:	2380      	movs	r3, #128	@ 0x80
- 8005022:	029b      	lsls	r3, r3, #10
- 8005024:	4013      	ands	r3, r2
- 8005026:	d11f      	bne.n	8005068 <HAL_RCC_ClockConfig+0x10c>
-      {
-        return HAL_ERROR;
- 8005028:	2301      	movs	r3, #1
- 800502a:	e08b      	b.n	8005144 <HAL_RCC_ClockConfig+0x1e8>
-      }
-    }
-    /* HSI is selected as System Clock Source */
-    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
- 800502c:	687b      	ldr	r3, [r7, #4]
- 800502e:	685b      	ldr	r3, [r3, #4]
- 8005030:	2b00      	cmp	r3, #0
- 8005032:	d107      	bne.n	8005044 <HAL_RCC_ClockConfig+0xe8>
-    {
-      /* Check the HSI ready flag */
-      if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
- 8005034:	4b47      	ldr	r3, [pc, #284]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 8005036:	681a      	ldr	r2, [r3, #0]
- 8005038:	2380      	movs	r3, #128	@ 0x80
- 800503a:	00db      	lsls	r3, r3, #3
- 800503c:	4013      	ands	r3, r2
- 800503e:	d113      	bne.n	8005068 <HAL_RCC_ClockConfig+0x10c>
-      {
-        return HAL_ERROR;
- 8005040:	2301      	movs	r3, #1
- 8005042:	e07f      	b.n	8005144 <HAL_RCC_ClockConfig+0x1e8>
-        return HAL_ERROR;
-      }
-    }
-#endif /* RCC_HSI48_SUPPORT */
-    /* LSI is selected as System Clock Source */
-    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
- 8005044:	687b      	ldr	r3, [r7, #4]
- 8005046:	685b      	ldr	r3, [r3, #4]
- 8005048:	2b03      	cmp	r3, #3
- 800504a:	d106      	bne.n	800505a <HAL_RCC_ClockConfig+0xfe>
-    {
-      /* Check the LSI ready flag */
-      if (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
- 800504c:	4b41      	ldr	r3, [pc, #260]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 800504e:	6e1b      	ldr	r3, [r3, #96]	@ 0x60
- 8005050:	2202      	movs	r2, #2
- 8005052:	4013      	ands	r3, r2
- 8005054:	d108      	bne.n	8005068 <HAL_RCC_ClockConfig+0x10c>
-      {
-        return HAL_ERROR;
- 8005056:	2301      	movs	r3, #1
- 8005058:	e074      	b.n	8005144 <HAL_RCC_ClockConfig+0x1e8>
-    }
-    /* LSE is selected as System Clock Source */
-    else
-    {
-      /* Check the LSE ready flag */
-      if (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
- 800505a:	4b3e      	ldr	r3, [pc, #248]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 800505c:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
- 800505e:	2202      	movs	r2, #2
- 8005060:	4013      	ands	r3, r2
- 8005062:	d101      	bne.n	8005068 <HAL_RCC_ClockConfig+0x10c>
-      {
-        return HAL_ERROR;
- 8005064:	2301      	movs	r3, #1
- 8005066:	e06d      	b.n	8005144 <HAL_RCC_ClockConfig+0x1e8>
-      }
-    }
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
- 8005068:	4b3a      	ldr	r3, [pc, #232]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 800506a:	689b      	ldr	r3, [r3, #8]
- 800506c:	2207      	movs	r2, #7
- 800506e:	4393      	bics	r3, r2
- 8005070:	0019      	movs	r1, r3
- 8005072:	687b      	ldr	r3, [r7, #4]
- 8005074:	685a      	ldr	r2, [r3, #4]
- 8005076:	4b37      	ldr	r3, [pc, #220]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 8005078:	430a      	orrs	r2, r1
- 800507a:	609a      	str	r2, [r3, #8]
-
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
- 800507c:	f7ff f82c 	bl	80040d8 <HAL_GetTick>
- 8005080:	0003      	movs	r3, r0
- 8005082:	60fb      	str	r3, [r7, #12]
-
-    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 8005084:	e009      	b.n	800509a <HAL_RCC_ClockConfig+0x13e>
-    {
-      if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
- 8005086:	f7ff f827 	bl	80040d8 <HAL_GetTick>
- 800508a:	0002      	movs	r2, r0
- 800508c:	68fb      	ldr	r3, [r7, #12]
- 800508e:	1ad3      	subs	r3, r2, r3
- 8005090:	4a2f      	ldr	r2, [pc, #188]	@ (8005150 <HAL_RCC_ClockConfig+0x1f4>)
- 8005092:	4293      	cmp	r3, r2
- 8005094:	d901      	bls.n	800509a <HAL_RCC_ClockConfig+0x13e>
-      {
-        return HAL_TIMEOUT;
- 8005096:	2303      	movs	r3, #3
- 8005098:	e054      	b.n	8005144 <HAL_RCC_ClockConfig+0x1e8>
-    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
- 800509a:	4b2e      	ldr	r3, [pc, #184]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 800509c:	689b      	ldr	r3, [r3, #8]
- 800509e:	2238      	movs	r2, #56	@ 0x38
- 80050a0:	401a      	ands	r2, r3
- 80050a2:	687b      	ldr	r3, [r7, #4]
- 80050a4:	685b      	ldr	r3, [r3, #4]
- 80050a6:	00db      	lsls	r3, r3, #3
- 80050a8:	429a      	cmp	r2, r3
- 80050aa:	d1ec      	bne.n	8005086 <HAL_RCC_ClockConfig+0x12a>
-      }
-    }
-  }
-
-  /* Decreasing the number of wait states because of lower CPU frequency */
-  if (FLatency < __HAL_FLASH_GET_LATENCY())
- 80050ac:	4b27      	ldr	r3, [pc, #156]	@ (800514c <HAL_RCC_ClockConfig+0x1f0>)
- 80050ae:	681b      	ldr	r3, [r3, #0]
- 80050b0:	2207      	movs	r2, #7
- 80050b2:	4013      	ands	r3, r2
- 80050b4:	683a      	ldr	r2, [r7, #0]
- 80050b6:	429a      	cmp	r2, r3
- 80050b8:	d21e      	bcs.n	80050f8 <HAL_RCC_ClockConfig+0x19c>
-  {
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
- 80050ba:	4b24      	ldr	r3, [pc, #144]	@ (800514c <HAL_RCC_ClockConfig+0x1f0>)
- 80050bc:	681b      	ldr	r3, [r3, #0]
- 80050be:	2207      	movs	r2, #7
- 80050c0:	4393      	bics	r3, r2
- 80050c2:	0019      	movs	r1, r3
- 80050c4:	4b21      	ldr	r3, [pc, #132]	@ (800514c <HAL_RCC_ClockConfig+0x1f0>)
- 80050c6:	683a      	ldr	r2, [r7, #0]
- 80050c8:	430a      	orrs	r2, r1
- 80050ca:	601a      	str	r2, [r3, #0]
-
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by polling the FLASH_ACR register */
-    tickstart = HAL_GetTick();
- 80050cc:	f7ff f804 	bl	80040d8 <HAL_GetTick>
- 80050d0:	0003      	movs	r3, r0
- 80050d2:	60fb      	str	r3, [r7, #12]
-
-    while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
- 80050d4:	e009      	b.n	80050ea <HAL_RCC_ClockConfig+0x18e>
-    {
-      if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
- 80050d6:	f7fe ffff 	bl	80040d8 <HAL_GetTick>
- 80050da:	0002      	movs	r2, r0
- 80050dc:	68fb      	ldr	r3, [r7, #12]
- 80050de:	1ad3      	subs	r3, r2, r3
- 80050e0:	4a1b      	ldr	r2, [pc, #108]	@ (8005150 <HAL_RCC_ClockConfig+0x1f4>)
- 80050e2:	4293      	cmp	r3, r2
- 80050e4:	d901      	bls.n	80050ea <HAL_RCC_ClockConfig+0x18e>
-      {
-        return HAL_TIMEOUT;
- 80050e6:	2303      	movs	r3, #3
- 80050e8:	e02c      	b.n	8005144 <HAL_RCC_ClockConfig+0x1e8>
-    while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
- 80050ea:	4b18      	ldr	r3, [pc, #96]	@ (800514c <HAL_RCC_ClockConfig+0x1f0>)
- 80050ec:	681b      	ldr	r3, [r3, #0]
- 80050ee:	2207      	movs	r2, #7
- 80050f0:	4013      	ands	r3, r2
- 80050f2:	683a      	ldr	r2, [r7, #0]
- 80050f4:	429a      	cmp	r2, r3
- 80050f6:	d1ee      	bne.n	80050d6 <HAL_RCC_ClockConfig+0x17a>
-      }
-    }
-  }
-
-  /*-------------------------- PCLK1 Configuration ---------------------------*/
-  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
- 80050f8:	687b      	ldr	r3, [r7, #4]
- 80050fa:	681b      	ldr	r3, [r3, #0]
- 80050fc:	2204      	movs	r2, #4
- 80050fe:	4013      	ands	r3, r2
- 8005100:	d009      	beq.n	8005116 <HAL_RCC_ClockConfig+0x1ba>
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
- 8005102:	4b14      	ldr	r3, [pc, #80]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 8005104:	689b      	ldr	r3, [r3, #8]
- 8005106:	4a16      	ldr	r2, [pc, #88]	@ (8005160 <HAL_RCC_ClockConfig+0x204>)
- 8005108:	4013      	ands	r3, r2
- 800510a:	0019      	movs	r1, r3
- 800510c:	687b      	ldr	r3, [r7, #4]
- 800510e:	691a      	ldr	r2, [r3, #16]
- 8005110:	4b10      	ldr	r3, [pc, #64]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 8005112:	430a      	orrs	r2, r1
- 8005114:	609a      	str	r2, [r3, #8]
-  }
-
-  /* Update the SystemCoreClock global variable */
-  SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
- 8005116:	f000 f82b 	bl	8005170 <HAL_RCC_GetSysClockFreq>
- 800511a:	0001      	movs	r1, r0
- 800511c:	4b0d      	ldr	r3, [pc, #52]	@ (8005154 <HAL_RCC_ClockConfig+0x1f8>)
- 800511e:	689b      	ldr	r3, [r3, #8]
-                                                                  >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
- 8005120:	0a1b      	lsrs	r3, r3, #8
- 8005122:	220f      	movs	r2, #15
- 8005124:	401a      	ands	r2, r3
-  SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
- 8005126:	4b0f      	ldr	r3, [pc, #60]	@ (8005164 <HAL_RCC_ClockConfig+0x208>)
- 8005128:	0092      	lsls	r2, r2, #2
- 800512a:	58d3      	ldr	r3, [r2, r3]
-                                                                  >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
- 800512c:	221f      	movs	r2, #31
- 800512e:	4013      	ands	r3, r2
-  SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
- 8005130:	000a      	movs	r2, r1
- 8005132:	40da      	lsrs	r2, r3
- 8005134:	4b0c      	ldr	r3, [pc, #48]	@ (8005168 <HAL_RCC_ClockConfig+0x20c>)
- 8005136:	601a      	str	r2, [r3, #0]
-
-  /* Configure the source of time base considering new system clocks settings*/
-  return HAL_InitTick(uwTickPrio);
- 8005138:	4b0c      	ldr	r3, [pc, #48]	@ (800516c <HAL_RCC_ClockConfig+0x210>)
- 800513a:	681b      	ldr	r3, [r3, #0]
- 800513c:	0018      	movs	r0, r3
- 800513e:	f7fe ff6f 	bl	8004020 <HAL_InitTick>
- 8005142:	0003      	movs	r3, r0
-}
- 8005144:	0018      	movs	r0, r3
- 8005146:	46bd      	mov	sp, r7
- 8005148:	b004      	add	sp, #16
- 800514a:	bd80      	pop	{r7, pc}
- 800514c:	40022000 	.word	0x40022000
- 8005150:	00001388 	.word	0x00001388
- 8005154:	40021000 	.word	0x40021000
- 8005158:	ffff84ff 	.word	0xffff84ff
- 800515c:	fffff0ff 	.word	0xfffff0ff
- 8005160:	ffff8fff 	.word	0xffff8fff
- 8005164:	08007db0 	.word	0x08007db0
- 8005168:	20000024 	.word	0x20000024
- 800516c:	20000028 	.word	0x20000028
-
-08005170 <HAL_RCC_GetSysClockFreq>:
-  *
-  *
-  * @retval SYSCLK frequency
-  */
+080035b8 <HAL_RCC_GetSysClockFreq>:
 uint32_t HAL_RCC_GetSysClockFreq(void)
 {
- 8005170:	b580      	push	{r7, lr}
- 8005172:	b084      	sub	sp, #16
- 8005174:	af00      	add	r7, sp, #0
   uint32_t hsidiv;
   uint32_t sysclockfreq;
 #if defined(RCC_CR_SYSDIV)
   uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
- 8005176:	4b23      	ldr	r3, [pc, #140]	@ (8005204 <HAL_RCC_GetSysClockFreq+0x94>)
- 8005178:	681b      	ldr	r3, [r3, #0]
- 800517a:	089b      	lsrs	r3, r3, #2
- 800517c:	2207      	movs	r2, #7
- 800517e:	4013      	ands	r3, r2
- 8005180:	3301      	adds	r3, #1
- 8005182:	60bb      	str	r3, [r7, #8]
+ 80035b8:	2007      	movs	r0, #7
 #endif /* RCC_CR_SYSDIV */
 
   if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
- 8005184:	4b1f      	ldr	r3, [pc, #124]	@ (8005204 <HAL_RCC_GetSysClockFreq+0x94>)
- 8005186:	689b      	ldr	r3, [r3, #8]
- 8005188:	2238      	movs	r2, #56	@ 0x38
- 800518a:	4013      	ands	r3, r2
- 800518c:	d10f      	bne.n	80051ae <HAL_RCC_GetSysClockFreq+0x3e>
+ 80035ba:	2238      	movs	r2, #56	@ 0x38
+  uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
+ 80035bc:	4b12      	ldr	r3, [pc, #72]	@ (8003608 <HAL_RCC_GetSysClockFreq+0x50>)
+{
+ 80035be:	b510      	push	{r4, lr}
+  uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
+ 80035c0:	6819      	ldr	r1, [r3, #0]
+  if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
+ 80035c2:	689c      	ldr	r4, [r3, #8]
+  uint32_t sysclockdiv = (uint32_t)(((RCC->CR & RCC_CR_SYSDIV) >> RCC_CR_SYSDIV_Pos) + 1U);
+ 80035c4:	0889      	lsrs	r1, r1, #2
+ 80035c6:	4001      	ands	r1, r0
+ 80035c8:	3101      	adds	r1, #1
+  if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI)
+ 80035ca:	4214      	tst	r4, r2
+ 80035cc:	d107      	bne.n	80035de <HAL_RCC_GetSysClockFreq+0x26>
   {
     /* HSISYS can be derived for HSI48 */
     hsidiv = (1UL << ((READ_BIT(RCC->CR, RCC_CR_HSIDIV)) >> RCC_CR_HSIDIV_Pos));
- 800518e:	4b1d      	ldr	r3, [pc, #116]	@ (8005204 <HAL_RCC_GetSysClockFreq+0x94>)
- 8005190:	681b      	ldr	r3, [r3, #0]
- 8005192:	0adb      	lsrs	r3, r3, #11
- 8005194:	2207      	movs	r2, #7
- 8005196:	4013      	ands	r3, r2
- 8005198:	2201      	movs	r2, #1
- 800519a:	409a      	lsls	r2, r3
- 800519c:	0013      	movs	r3, r2
- 800519e:	607b      	str	r3, [r7, #4]
+ 80035ce:	681b      	ldr	r3, [r3, #0]
+ 80035d0:	0adb      	lsrs	r3, r3, #11
+ 80035d2:	4003      	ands	r3, r0
 
     /* HSI used as system clock source */
     sysclockfreq = (HSI_VALUE / hsidiv);
- 80051a0:	6879      	ldr	r1, [r7, #4]
- 80051a2:	4819      	ldr	r0, [pc, #100]	@ (8005208 <HAL_RCC_GetSysClockFreq+0x98>)
- 80051a4:	f7fa ffb0 	bl	8000108 <__udivsi3>
- 80051a8:	0003      	movs	r3, r0
- 80051aa:	60fb      	str	r3, [r7, #12]
- 80051ac:	e01e      	b.n	80051ec <HAL_RCC_GetSysClockFreq+0x7c>
-  }
-  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
- 80051ae:	4b15      	ldr	r3, [pc, #84]	@ (8005204 <HAL_RCC_GetSysClockFreq+0x94>)
- 80051b0:	689b      	ldr	r3, [r3, #8]
- 80051b2:	2238      	movs	r2, #56	@ 0x38
- 80051b4:	4013      	ands	r3, r2
- 80051b6:	2b08      	cmp	r3, #8
- 80051b8:	d102      	bne.n	80051c0 <HAL_RCC_GetSysClockFreq+0x50>
-  {
-    /* HSE used as system clock source */
-    sysclockfreq = HSE_VALUE;
- 80051ba:	4b14      	ldr	r3, [pc, #80]	@ (800520c <HAL_RCC_GetSysClockFreq+0x9c>)
- 80051bc:	60fb      	str	r3, [r7, #12]
- 80051be:	e015      	b.n	80051ec <HAL_RCC_GetSysClockFreq+0x7c>
-  }
-  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
- 80051c0:	4b10      	ldr	r3, [pc, #64]	@ (8005204 <HAL_RCC_GetSysClockFreq+0x94>)
- 80051c2:	689b      	ldr	r3, [r3, #8]
- 80051c4:	2238      	movs	r2, #56	@ 0x38
- 80051c6:	4013      	ands	r3, r2
- 80051c8:	2b20      	cmp	r3, #32
- 80051ca:	d103      	bne.n	80051d4 <HAL_RCC_GetSysClockFreq+0x64>
-  {
-    /* LSE used as system clock source */
-    sysclockfreq = LSE_VALUE;
- 80051cc:	2380      	movs	r3, #128	@ 0x80
- 80051ce:	021b      	lsls	r3, r3, #8
- 80051d0:	60fb      	str	r3, [r7, #12]
- 80051d2:	e00b      	b.n	80051ec <HAL_RCC_GetSysClockFreq+0x7c>
-  }
-  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
- 80051d4:	4b0b      	ldr	r3, [pc, #44]	@ (8005204 <HAL_RCC_GetSysClockFreq+0x94>)
- 80051d6:	689b      	ldr	r3, [r3, #8]
- 80051d8:	2238      	movs	r2, #56	@ 0x38
- 80051da:	4013      	ands	r3, r2
- 80051dc:	2b18      	cmp	r3, #24
- 80051de:	d103      	bne.n	80051e8 <HAL_RCC_GetSysClockFreq+0x78>
-  {
-    /* LSI used as system clock source */
-    sysclockfreq = LSI_VALUE;
- 80051e0:	23fa      	movs	r3, #250	@ 0xfa
- 80051e2:	01db      	lsls	r3, r3, #7
- 80051e4:	60fb      	str	r3, [r7, #12]
- 80051e6:	e001      	b.n	80051ec <HAL_RCC_GetSysClockFreq+0x7c>
-    sysclockfreq = HSI48_VALUE;
-  }
-#endif /* RCC_HSI48_SUPPORT */
+ 80035d4:	480d      	ldr	r0, [pc, #52]	@ (800360c <HAL_RCC_GetSysClockFreq+0x54>)
+ 80035d6:	40d8      	lsrs	r0, r3
   else
   {
     sysclockfreq = 0U;
- 80051e8:	2300      	movs	r3, #0
- 80051ea:	60fb      	str	r3, [r7, #12]
   }
 #if defined(RCC_CR_SYSDIV)
   sysclockfreq = sysclockfreq / sysclockdiv;
- 80051ec:	68b9      	ldr	r1, [r7, #8]
- 80051ee:	68f8      	ldr	r0, [r7, #12]
- 80051f0:	f7fa ff8a 	bl	8000108 <__udivsi3>
- 80051f4:	0003      	movs	r3, r0
- 80051f6:	60fb      	str	r3, [r7, #12]
+ 80035d8:	f7fc fdaa 	bl	8000130 <__udivsi3>
 #endif /* RCC_CR_SYSDIV */
   return sysclockfreq;
- 80051f8:	68fb      	ldr	r3, [r7, #12]
 }
- 80051fa:	0018      	movs	r0, r3
- 80051fc:	46bd      	mov	sp, r7
- 80051fe:	b004      	add	sp, #16
- 8005200:	bd80      	pop	{r7, pc}
- 8005202:	46c0      	nop			@ (mov r8, r8)
- 8005204:	40021000 	.word	0x40021000
- 8005208:	02dc6c00 	.word	0x02dc6c00
- 800520c:	007a1200 	.word	0x007a1200
+ 80035dc:	bd10      	pop	{r4, pc}
+  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE)
+ 80035de:	6898      	ldr	r0, [r3, #8]
+ 80035e0:	4010      	ands	r0, r2
+ 80035e2:	2808      	cmp	r0, #8
+ 80035e4:	d00b      	beq.n	80035fe <HAL_RCC_GetSysClockFreq+0x46>
+  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSE)
+ 80035e6:	6898      	ldr	r0, [r3, #8]
+ 80035e8:	4010      	ands	r0, r2
+ 80035ea:	2820      	cmp	r0, #32
+ 80035ec:	d009      	beq.n	8003602 <HAL_RCC_GetSysClockFreq+0x4a>
+  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
+ 80035ee:	689b      	ldr	r3, [r3, #8]
+    sysclockfreq = 0U;
+ 80035f0:	2000      	movs	r0, #0
+  else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_LSI)
+ 80035f2:	4013      	ands	r3, r2
+ 80035f4:	2b18      	cmp	r3, #24
+ 80035f6:	d1ef      	bne.n	80035d8 <HAL_RCC_GetSysClockFreq+0x20>
+    sysclockfreq = LSI_VALUE;
+ 80035f8:	20fa      	movs	r0, #250	@ 0xfa
+ 80035fa:	01c0      	lsls	r0, r0, #7
+ 80035fc:	e7ec      	b.n	80035d8 <HAL_RCC_GetSysClockFreq+0x20>
+    sysclockfreq = HSE_VALUE;
+ 80035fe:	4804      	ldr	r0, [pc, #16]	@ (8003610 <HAL_RCC_GetSysClockFreq+0x58>)
+ 8003600:	e7ea      	b.n	80035d8 <HAL_RCC_GetSysClockFreq+0x20>
+    sysclockfreq = LSE_VALUE;
+ 8003602:	2080      	movs	r0, #128	@ 0x80
+ 8003604:	0200      	lsls	r0, r0, #8
+ 8003606:	e7e7      	b.n	80035d8 <HAL_RCC_GetSysClockFreq+0x20>
+ 8003608:	40021000 	.word	0x40021000
+ 800360c:	02dc6c00 	.word	0x02dc6c00
+ 8003610:	007a1200 	.word	0x007a1200
 
-08005210 <HAL_RCC_GetHCLKFreq>:
+08003614 <HAL_RCC_ClockConfig>:
+{
+ 8003614:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+ 8003616:	0004      	movs	r4, r0
+ 8003618:	000d      	movs	r5, r1
+  if (RCC_ClkInitStruct == NULL)
+ 800361a:	2800      	cmp	r0, #0
+ 800361c:	d101      	bne.n	8003622 <HAL_RCC_ClockConfig+0xe>
+    return HAL_ERROR;
+ 800361e:	2001      	movs	r0, #1
+}
+ 8003620:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+  if (FLatency > __HAL_FLASH_GET_LATENCY())
+ 8003622:	2707      	movs	r7, #7
+ 8003624:	4e4b      	ldr	r6, [pc, #300]	@ (8003754 <HAL_RCC_ClockConfig+0x140>)
+ 8003626:	6833      	ldr	r3, [r6, #0]
+ 8003628:	403b      	ands	r3, r7
+ 800362a:	428b      	cmp	r3, r1
+ 800362c:	d32a      	bcc.n	8003684 <HAL_RCC_ClockConfig+0x70>
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
+ 800362e:	6822      	ldr	r2, [r4, #0]
+ 8003630:	0793      	lsls	r3, r2, #30
+ 8003632:	d43b      	bmi.n	80036ac <HAL_RCC_ClockConfig+0x98>
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
+ 8003634:	07d2      	lsls	r2, r2, #31
+ 8003636:	d44a      	bmi.n	80036ce <HAL_RCC_ClockConfig+0xba>
+  if (FLatency < __HAL_FLASH_GET_LATENCY())
+ 8003638:	2707      	movs	r7, #7
+ 800363a:	6833      	ldr	r3, [r6, #0]
+ 800363c:	403b      	ands	r3, r7
+ 800363e:	42ab      	cmp	r3, r5
+ 8003640:	d90a      	bls.n	8003658 <HAL_RCC_ClockConfig+0x44>
+    __HAL_FLASH_SET_LATENCY(FLatency);
+ 8003642:	6833      	ldr	r3, [r6, #0]
+ 8003644:	43bb      	bics	r3, r7
+ 8003646:	432b      	orrs	r3, r5
+ 8003648:	6033      	str	r3, [r6, #0]
+    tickstart = HAL_GetTick();
+ 800364a:	f7ff f949 	bl	80028e0 <HAL_GetTick>
+ 800364e:	9001      	str	r0, [sp, #4]
+    while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ 8003650:	6833      	ldr	r3, [r6, #0]
+ 8003652:	403b      	ands	r3, r7
+ 8003654:	42ab      	cmp	r3, r5
+ 8003656:	d16d      	bne.n	8003734 <HAL_RCC_ClockConfig+0x120>
+  if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 8003658:	6823      	ldr	r3, [r4, #0]
+ 800365a:	4d3f      	ldr	r5, [pc, #252]	@ (8003758 <HAL_RCC_ClockConfig+0x144>)
+ 800365c:	075b      	lsls	r3, r3, #29
+ 800365e:	d471      	bmi.n	8003744 <HAL_RCC_ClockConfig+0x130>
+  SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
+ 8003660:	f7ff ffaa 	bl	80035b8 <HAL_RCC_GetSysClockFreq>
+ 8003664:	68ab      	ldr	r3, [r5, #8]
+ 8003666:	493d      	ldr	r1, [pc, #244]	@ (800375c <HAL_RCC_ClockConfig+0x148>)
+                                                                  >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
+ 8003668:	051b      	lsls	r3, r3, #20
+ 800366a:	0f1b      	lsrs	r3, r3, #28
+  SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
+ 800366c:	009b      	lsls	r3, r3, #2
+                                                                  >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
+ 800366e:	585b      	ldr	r3, [r3, r1]
+ 8003670:	211f      	movs	r1, #31
+ 8003672:	400b      	ands	r3, r1
+  SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
+ 8003674:	40d8      	lsrs	r0, r3
+ 8003676:	4a3a      	ldr	r2, [pc, #232]	@ (8003760 <HAL_RCC_ClockConfig+0x14c>)
+  return HAL_InitTick(uwTickPrio);
+ 8003678:	4b3a      	ldr	r3, [pc, #232]	@ (8003764 <HAL_RCC_ClockConfig+0x150>)
+  SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
+ 800367a:	6010      	str	r0, [r2, #0]
+  return HAL_InitTick(uwTickPrio);
+ 800367c:	6818      	ldr	r0, [r3, #0]
+ 800367e:	f7ff f8ef 	bl	8002860 <HAL_InitTick>
+ 8003682:	e7cd      	b.n	8003620 <HAL_RCC_ClockConfig+0xc>
+    __HAL_FLASH_SET_LATENCY(FLatency);
+ 8003684:	6833      	ldr	r3, [r6, #0]
+ 8003686:	43bb      	bics	r3, r7
+ 8003688:	430b      	orrs	r3, r1
+ 800368a:	6033      	str	r3, [r6, #0]
+    tickstart = HAL_GetTick();
+ 800368c:	f7ff f928 	bl	80028e0 <HAL_GetTick>
+ 8003690:	9001      	str	r0, [sp, #4]
+    while ((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ 8003692:	6833      	ldr	r3, [r6, #0]
+ 8003694:	403b      	ands	r3, r7
+ 8003696:	42ab      	cmp	r3, r5
+ 8003698:	d0c9      	beq.n	800362e <HAL_RCC_ClockConfig+0x1a>
+      if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
+ 800369a:	f7ff f921 	bl	80028e0 <HAL_GetTick>
+ 800369e:	9b01      	ldr	r3, [sp, #4]
+ 80036a0:	1ac0      	subs	r0, r0, r3
+ 80036a2:	4b31      	ldr	r3, [pc, #196]	@ (8003768 <HAL_RCC_ClockConfig+0x154>)
+ 80036a4:	4298      	cmp	r0, r3
+ 80036a6:	d9f4      	bls.n	8003692 <HAL_RCC_ClockConfig+0x7e>
+        return HAL_TIMEOUT;
+ 80036a8:	2003      	movs	r0, #3
+ 80036aa:	e7b9      	b.n	8003620 <HAL_RCC_ClockConfig+0xc>
+    if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ 80036ac:	492a      	ldr	r1, [pc, #168]	@ (8003758 <HAL_RCC_ClockConfig+0x144>)
+ 80036ae:	0753      	lsls	r3, r2, #29
+ 80036b0:	d506      	bpl.n	80036c0 <HAL_RCC_ClockConfig+0xac>
+      MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_HCLK_DIV16);
+ 80036b2:	6888      	ldr	r0, [r1, #8]
+ 80036b4:	4b2d      	ldr	r3, [pc, #180]	@ (800376c <HAL_RCC_ClockConfig+0x158>)
+ 80036b6:	4018      	ands	r0, r3
+ 80036b8:	23b0      	movs	r3, #176	@ 0xb0
+ 80036ba:	011b      	lsls	r3, r3, #4
+ 80036bc:	4303      	orrs	r3, r0
+ 80036be:	608b      	str	r3, [r1, #8]
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
+ 80036c0:	688b      	ldr	r3, [r1, #8]
+ 80036c2:	482b      	ldr	r0, [pc, #172]	@ (8003770 <HAL_RCC_ClockConfig+0x15c>)
+ 80036c4:	4003      	ands	r3, r0
+ 80036c6:	68e0      	ldr	r0, [r4, #12]
+ 80036c8:	4303      	orrs	r3, r0
+ 80036ca:	608b      	str	r3, [r1, #8]
+ 80036cc:	e7b2      	b.n	8003634 <HAL_RCC_ClockConfig+0x20>
+    MODIFY_REG(RCC->CR, RCC_CR_SYSDIV, RCC_ClkInitStruct->SYSCLKDivider);
+ 80036ce:	221c      	movs	r2, #28
+ 80036d0:	4f21      	ldr	r7, [pc, #132]	@ (8003758 <HAL_RCC_ClockConfig+0x144>)
+ 80036d2:	683b      	ldr	r3, [r7, #0]
+ 80036d4:	4393      	bics	r3, r2
+ 80036d6:	68a2      	ldr	r2, [r4, #8]
+ 80036d8:	4313      	orrs	r3, r2
+ 80036da:	603b      	str	r3, [r7, #0]
+    if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+ 80036dc:	6862      	ldr	r2, [r4, #4]
+ 80036de:	2a01      	cmp	r2, #1
+ 80036e0:	d119      	bne.n	8003716 <HAL_RCC_ClockConfig+0x102>
+      if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U)
+ 80036e2:	683b      	ldr	r3, [r7, #0]
+ 80036e4:	039b      	lsls	r3, r3, #14
+ 80036e6:	d59a      	bpl.n	800361e <HAL_RCC_ClockConfig+0xa>
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
+ 80036e8:	2107      	movs	r1, #7
+ 80036ea:	68bb      	ldr	r3, [r7, #8]
+ 80036ec:	438b      	bics	r3, r1
+ 80036ee:	4313      	orrs	r3, r2
+ 80036f0:	60bb      	str	r3, [r7, #8]
+    tickstart = HAL_GetTick();
+ 80036f2:	f7ff f8f5 	bl	80028e0 <HAL_GetTick>
+ 80036f6:	9001      	str	r0, [sp, #4]
+    while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
+ 80036f8:	2338      	movs	r3, #56	@ 0x38
+ 80036fa:	68ba      	ldr	r2, [r7, #8]
+ 80036fc:	401a      	ands	r2, r3
+ 80036fe:	6863      	ldr	r3, [r4, #4]
+ 8003700:	00db      	lsls	r3, r3, #3
+ 8003702:	429a      	cmp	r2, r3
+ 8003704:	d098      	beq.n	8003638 <HAL_RCC_ClockConfig+0x24>
+      if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
+ 8003706:	f7ff f8eb 	bl	80028e0 <HAL_GetTick>
+ 800370a:	9b01      	ldr	r3, [sp, #4]
+ 800370c:	1ac0      	subs	r0, r0, r3
+ 800370e:	4b16      	ldr	r3, [pc, #88]	@ (8003768 <HAL_RCC_ClockConfig+0x154>)
+ 8003710:	4298      	cmp	r0, r3
+ 8003712:	d9f1      	bls.n	80036f8 <HAL_RCC_ClockConfig+0xe4>
+ 8003714:	e7c8      	b.n	80036a8 <HAL_RCC_ClockConfig+0x94>
+    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
+ 8003716:	2a00      	cmp	r2, #0
+ 8003718:	d103      	bne.n	8003722 <HAL_RCC_ClockConfig+0x10e>
+      if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U)
+ 800371a:	683b      	ldr	r3, [r7, #0]
+ 800371c:	055b      	lsls	r3, r3, #21
+ 800371e:	d4e3      	bmi.n	80036e8 <HAL_RCC_ClockConfig+0xd4>
+ 8003720:	e77d      	b.n	800361e <HAL_RCC_ClockConfig+0xa>
+    else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_LSI)
+ 8003722:	2302      	movs	r3, #2
+ 8003724:	2a03      	cmp	r2, #3
+ 8003726:	d103      	bne.n	8003730 <HAL_RCC_ClockConfig+0x11c>
+      if (READ_BIT(RCC->CSR2, RCC_CSR2_LSIRDY) == 0U)
+ 8003728:	6e39      	ldr	r1, [r7, #96]	@ 0x60
+      if (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
+ 800372a:	4219      	tst	r1, r3
+ 800372c:	d1dc      	bne.n	80036e8 <HAL_RCC_ClockConfig+0xd4>
+ 800372e:	e776      	b.n	800361e <HAL_RCC_ClockConfig+0xa>
+ 8003730:	6df9      	ldr	r1, [r7, #92]	@ 0x5c
+ 8003732:	e7fa      	b.n	800372a <HAL_RCC_ClockConfig+0x116>
+      if ((HAL_GetTick() - tickstart) > RCC_CLOCKSWITCH_TIMEOUT_VALUE)
+ 8003734:	f7ff f8d4 	bl	80028e0 <HAL_GetTick>
+ 8003738:	9b01      	ldr	r3, [sp, #4]
+ 800373a:	1ac0      	subs	r0, r0, r3
+ 800373c:	4b0a      	ldr	r3, [pc, #40]	@ (8003768 <HAL_RCC_ClockConfig+0x154>)
+ 800373e:	4298      	cmp	r0, r3
+ 8003740:	d986      	bls.n	8003650 <HAL_RCC_ClockConfig+0x3c>
+ 8003742:	e7b1      	b.n	80036a8 <HAL_RCC_ClockConfig+0x94>
+    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, RCC_ClkInitStruct->APB1CLKDivider);
+ 8003744:	68ab      	ldr	r3, [r5, #8]
+ 8003746:	4a0b      	ldr	r2, [pc, #44]	@ (8003774 <HAL_RCC_ClockConfig+0x160>)
+ 8003748:	4013      	ands	r3, r2
+ 800374a:	6922      	ldr	r2, [r4, #16]
+ 800374c:	4313      	orrs	r3, r2
+ 800374e:	60ab      	str	r3, [r5, #8]
+ 8003750:	e786      	b.n	8003660 <HAL_RCC_ClockConfig+0x4c>
+ 8003752:	46c0      	nop			@ (mov r8, r8)
+ 8003754:	40022000 	.word	0x40022000
+ 8003758:	40021000 	.word	0x40021000
+ 800375c:	0800524c 	.word	0x0800524c
+ 8003760:	20000024 	.word	0x20000024
+ 8003764:	2000002c 	.word	0x2000002c
+ 8003768:	00001388 	.word	0x00001388
+ 800376c:	ffff84ff 	.word	0xffff84ff
+ 8003770:	fffff0ff 	.word	0xfffff0ff
+ 8003774:	ffff8fff 	.word	0xffff8fff
+
+08003778 <HAL_RCC_GetHCLKFreq>:
   *
   * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
   * @retval HCLK frequency in Hz
   */
 uint32_t HAL_RCC_GetHCLKFreq(void)
 {
- 8005210:	b580      	push	{r7, lr}
- 8005212:	af00      	add	r7, sp, #0
+ 8003778:	b510      	push	{r4, lr}
   SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
- 8005214:	f7ff ffac 	bl	8005170 <HAL_RCC_GetSysClockFreq>
- 8005218:	0001      	movs	r1, r0
- 800521a:	4b09      	ldr	r3, [pc, #36]	@ (8005240 <HAL_RCC_GetHCLKFreq+0x30>)
- 800521c:	689b      	ldr	r3, [r3, #8]
+ 800377a:	f7ff ff1d 	bl	80035b8 <HAL_RCC_GetSysClockFreq>
+ 800377e:	4b06      	ldr	r3, [pc, #24]	@ (8003798 <HAL_RCC_GetHCLKFreq+0x20>)
+ 8003780:	4a06      	ldr	r2, [pc, #24]	@ (800379c <HAL_RCC_GetHCLKFreq+0x24>)
+ 8003782:	689b      	ldr	r3, [r3, #8]
                                                                   >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
- 800521e:	0a1b      	lsrs	r3, r3, #8
- 8005220:	220f      	movs	r2, #15
- 8005222:	401a      	ands	r2, r3
+ 8003784:	051b      	lsls	r3, r3, #20
+ 8003786:	0f1b      	lsrs	r3, r3, #28
   SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
- 8005224:	4b07      	ldr	r3, [pc, #28]	@ (8005244 <HAL_RCC_GetHCLKFreq+0x34>)
- 8005226:	0092      	lsls	r2, r2, #2
- 8005228:	58d3      	ldr	r3, [r2, r3]
+ 8003788:	009b      	lsls	r3, r3, #2
                                                                   >> RCC_CFGR_HPRE_Pos]) & 0x1FU));
- 800522a:	221f      	movs	r2, #31
- 800522c:	4013      	ands	r3, r2
+ 800378a:	589b      	ldr	r3, [r3, r2]
+ 800378c:	221f      	movs	r2, #31
+ 800378e:	4013      	ands	r3, r2
   SystemCoreClock = (HAL_RCC_GetSysClockFreq() >> ((AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE) \
- 800522e:	000a      	movs	r2, r1
- 8005230:	40da      	lsrs	r2, r3
- 8005232:	4b05      	ldr	r3, [pc, #20]	@ (8005248 <HAL_RCC_GetHCLKFreq+0x38>)
- 8005234:	601a      	str	r2, [r3, #0]
+ 8003790:	40d8      	lsrs	r0, r3
+ 8003792:	4b03      	ldr	r3, [pc, #12]	@ (80037a0 <HAL_RCC_GetHCLKFreq+0x28>)
+ 8003794:	6018      	str	r0, [r3, #0]
   return SystemCoreClock;
- 8005236:	4b04      	ldr	r3, [pc, #16]	@ (8005248 <HAL_RCC_GetHCLKFreq+0x38>)
- 8005238:	681b      	ldr	r3, [r3, #0]
 }
- 800523a:	0018      	movs	r0, r3
- 800523c:	46bd      	mov	sp, r7
- 800523e:	bd80      	pop	{r7, pc}
- 8005240:	40021000 	.word	0x40021000
- 8005244:	08007db0 	.word	0x08007db0
- 8005248:	20000024 	.word	0x20000024
+ 8003796:	bd10      	pop	{r4, pc}
+ 8003798:	40021000 	.word	0x40021000
+ 800379c:	0800524c 	.word	0x0800524c
+ 80037a0:	20000024 	.word	0x20000024
 
-0800524c <HAL_RCC_GetPCLK1Freq>:
+080037a4 <HAL_RCC_GetPCLK1Freq>:
   * @note   Each time PCLK1 changes, this function must be called to update the
   *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
   * @retval PCLK1 frequency in Hz
   */
 uint32_t HAL_RCC_GetPCLK1Freq(void)
 {
- 800524c:	b580      	push	{r7, lr}
- 800524e:	af00      	add	r7, sp, #0
+ 80037a4:	b510      	push	{r4, lr}
   /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
   return (HAL_RCC_GetHCLKFreq() >> ((APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE) >> RCC_CFGR_PPRE_Pos]) & 0x1FU));
- 8005250:	f7ff ffde 	bl	8005210 <HAL_RCC_GetHCLKFreq>
- 8005254:	0001      	movs	r1, r0
- 8005256:	4b07      	ldr	r3, [pc, #28]	@ (8005274 <HAL_RCC_GetPCLK1Freq+0x28>)
- 8005258:	689b      	ldr	r3, [r3, #8]
- 800525a:	0b1b      	lsrs	r3, r3, #12
- 800525c:	2207      	movs	r2, #7
- 800525e:	401a      	ands	r2, r3
- 8005260:	4b05      	ldr	r3, [pc, #20]	@ (8005278 <HAL_RCC_GetPCLK1Freq+0x2c>)
- 8005262:	0092      	lsls	r2, r2, #2
- 8005264:	58d3      	ldr	r3, [r2, r3]
- 8005266:	221f      	movs	r2, #31
- 8005268:	4013      	ands	r3, r2
- 800526a:	40d9      	lsrs	r1, r3
- 800526c:	000b      	movs	r3, r1
+ 80037a6:	f7ff ffe7 	bl	8003778 <HAL_RCC_GetHCLKFreq>
+ 80037aa:	4b05      	ldr	r3, [pc, #20]	@ (80037c0 <HAL_RCC_GetPCLK1Freq+0x1c>)
+ 80037ac:	4a05      	ldr	r2, [pc, #20]	@ (80037c4 <HAL_RCC_GetPCLK1Freq+0x20>)
+ 80037ae:	689b      	ldr	r3, [r3, #8]
+ 80037b0:	045b      	lsls	r3, r3, #17
+ 80037b2:	0f5b      	lsrs	r3, r3, #29
+ 80037b4:	009b      	lsls	r3, r3, #2
+ 80037b6:	589b      	ldr	r3, [r3, r2]
+ 80037b8:	221f      	movs	r2, #31
+ 80037ba:	4013      	ands	r3, r2
+ 80037bc:	40d8      	lsrs	r0, r3
 }
- 800526e:	0018      	movs	r0, r3
- 8005270:	46bd      	mov	sp, r7
- 8005272:	bd80      	pop	{r7, pc}
- 8005274:	40021000 	.word	0x40021000
- 8005278:	08007df0 	.word	0x08007df0
+ 80037be:	bd10      	pop	{r4, pc}
+ 80037c0:	40021000 	.word	0x40021000
+ 80037c4:	0800522c 	.word	0x0800522c
 
-0800527c <HAL_RCCEx_PeriphCLKConfig>:
+080037c8 <HAL_RCCEx_PeriphCLKConfig>:
   * @note (*) not available on all devices
   *
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
 {
- 800527c:	b580      	push	{r7, lr}
- 800527e:	b086      	sub	sp, #24
- 8005280:	af00      	add	r7, sp, #0
- 8005282:	6078      	str	r0, [r7, #4]
-  uint32_t tmpregister;
-  uint32_t tickstart;
-  HAL_StatusTypeDef ret    = HAL_OK;   /* Intermediate status */
- 8005284:	2313      	movs	r3, #19
- 8005286:	18fb      	adds	r3, r7, r3
- 8005288:	2200      	movs	r2, #0
- 800528a:	701a      	strb	r2, [r3, #0]
-  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
- 800528c:	2312      	movs	r3, #18
- 800528e:	18fb      	adds	r3, r7, r3
- 8005290:	2200      	movs	r2, #0
- 8005292:	701a      	strb	r2, [r3, #0]
+ 80037c8:	b5f0      	push	{r4, r5, r6, r7, lr}
 
   /* Check the parameters */
   assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
 
   /*-------------------------- RTC clock source configuration ----------------------*/
   if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
- 8005294:	687b      	ldr	r3, [r7, #4]
- 8005296:	681b      	ldr	r3, [r3, #0]
- 8005298:	2240      	movs	r2, #64	@ 0x40
- 800529a:	4013      	ands	r3, r2
- 800529c:	d100      	bne.n	80052a0 <HAL_RCCEx_PeriphCLKConfig+0x24>
- 800529e:	e079      	b.n	8005394 <HAL_RCCEx_PeriphCLKConfig+0x118>
-  {
-    FlagStatus       pwrclkchanged = RESET;
- 80052a0:	2011      	movs	r0, #17
- 80052a2:	183b      	adds	r3, r7, r0
- 80052a4:	2200      	movs	r2, #0
- 80052a6:	701a      	strb	r2, [r3, #0]
+ 80037ca:	6803      	ldr	r3, [r0, #0]
+{
+ 80037cc:	0005      	movs	r5, r0
+ 80037ce:	b085      	sub	sp, #20
+  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+ 80037d0:	2000      	movs	r0, #0
+  if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
+ 80037d2:	065b      	lsls	r3, r3, #25
+ 80037d4:	d522      	bpl.n	800381c <HAL_RCCEx_PeriphCLKConfig+0x54>
 
     /* Check for RTC Parameters used to output RTCCLK */
     assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
 
     /* Enable Power Clock */
     if (__HAL_RCC_PWR_IS_CLK_DISABLED())
- 80052a8:	4b63      	ldr	r3, [pc, #396]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80052aa:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
- 80052ac:	2380      	movs	r3, #128	@ 0x80
- 80052ae:	055b      	lsls	r3, r3, #21
- 80052b0:	4013      	ands	r3, r2
- 80052b2:	d110      	bne.n	80052d6 <HAL_RCCEx_PeriphCLKConfig+0x5a>
+ 80037d6:	2280      	movs	r2, #128	@ 0x80
+ 80037d8:	4c39      	ldr	r4, [pc, #228]	@ (80038c0 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
+ 80037da:	0552      	lsls	r2, r2, #21
+ 80037dc:	6be3      	ldr	r3, [r4, #60]	@ 0x3c
+    FlagStatus       pwrclkchanged = RESET;
+ 80037de:	0006      	movs	r6, r0
+    if (__HAL_RCC_PWR_IS_CLK_DISABLED())
+ 80037e0:	4213      	tst	r3, r2
+ 80037e2:	d107      	bne.n	80037f4 <HAL_RCCEx_PeriphCLKConfig+0x2c>
     {
       __HAL_RCC_PWR_CLK_ENABLE();
- 80052b4:	4b60      	ldr	r3, [pc, #384]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80052b6:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
- 80052b8:	4b5f      	ldr	r3, [pc, #380]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80052ba:	2180      	movs	r1, #128	@ 0x80
- 80052bc:	0549      	lsls	r1, r1, #21
- 80052be:	430a      	orrs	r2, r1
- 80052c0:	63da      	str	r2, [r3, #60]	@ 0x3c
- 80052c2:	4b5d      	ldr	r3, [pc, #372]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80052c4:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
- 80052c6:	2380      	movs	r3, #128	@ 0x80
- 80052c8:	055b      	lsls	r3, r3, #21
- 80052ca:	4013      	ands	r3, r2
- 80052cc:	60bb      	str	r3, [r7, #8]
- 80052ce:	68bb      	ldr	r3, [r7, #8]
+ 80037e4:	6be3      	ldr	r3, [r4, #60]	@ 0x3c
       pwrclkchanged = SET;
- 80052d0:	183b      	adds	r3, r7, r0
- 80052d2:	2201      	movs	r2, #1
- 80052d4:	701a      	strb	r2, [r3, #0]
+ 80037e6:	3601      	adds	r6, #1
+      __HAL_RCC_PWR_CLK_ENABLE();
+ 80037e8:	4313      	orrs	r3, r2
+ 80037ea:	63e3      	str	r3, [r4, #60]	@ 0x3c
+ 80037ec:	6be3      	ldr	r3, [r4, #60]	@ 0x3c
+ 80037ee:	4013      	ands	r3, r2
+ 80037f0:	9303      	str	r3, [sp, #12]
+ 80037f2:	9b03      	ldr	r3, [sp, #12]
     }
 
 
     /* Reset the RTC domain only if the RTC Clock source selection is modified from default */
     tmpregister = READ_BIT(RCC->CSR1, RCC_CSR1_RTCSEL);
- 80052d6:	4b58      	ldr	r3, [pc, #352]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80052d8:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
- 80052da:	23c0      	movs	r3, #192	@ 0xc0
- 80052dc:	009b      	lsls	r3, r3, #2
- 80052de:	4013      	ands	r3, r2
- 80052e0:	617b      	str	r3, [r7, #20]
+ 80037f4:	6de2      	ldr	r2, [r4, #92]	@ 0x5c
+ 80037f6:	23c0      	movs	r3, #192	@ 0xc0
+ 80037f8:	0011      	movs	r1, r2
+ 80037fa:	009b      	lsls	r3, r3, #2
+ 80037fc:	4f31      	ldr	r7, [pc, #196]	@ (80038c4 <HAL_RCCEx_PeriphCLKConfig+0xfc>)
+ 80037fe:	4019      	ands	r1, r3
 
     /* Reset the RTC domain only if the RTC Clock source selection is modified */
     if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
- 80052e2:	697b      	ldr	r3, [r7, #20]
- 80052e4:	2b00      	cmp	r3, #0
- 80052e6:	d019      	beq.n	800531c <HAL_RCCEx_PeriphCLKConfig+0xa0>
- 80052e8:	687b      	ldr	r3, [r7, #4]
- 80052ea:	699b      	ldr	r3, [r3, #24]
- 80052ec:	697a      	ldr	r2, [r7, #20]
- 80052ee:	429a      	cmp	r2, r3
- 80052f0:	d014      	beq.n	800531c <HAL_RCCEx_PeriphCLKConfig+0xa0>
-    {
-      /* Store the content of CSR1 register before the reset of RTC Domain */
-      tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL));
- 80052f2:	4b51      	ldr	r3, [pc, #324]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80052f4:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
- 80052f6:	4a51      	ldr	r2, [pc, #324]	@ (800543c <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
- 80052f8:	4013      	ands	r3, r2
- 80052fa:	617b      	str	r3, [r7, #20]
-      /* RTC Clock selection can be changed only if the RTC Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
- 80052fc:	4b4e      	ldr	r3, [pc, #312]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80052fe:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
- 8005300:	4b4d      	ldr	r3, [pc, #308]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 8005302:	2180      	movs	r1, #128	@ 0x80
- 8005304:	0249      	lsls	r1, r1, #9
- 8005306:	430a      	orrs	r2, r1
- 8005308:	65da      	str	r2, [r3, #92]	@ 0x5c
-      __HAL_RCC_BACKUPRESET_RELEASE();
- 800530a:	4b4b      	ldr	r3, [pc, #300]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 800530c:	6dda      	ldr	r2, [r3, #92]	@ 0x5c
- 800530e:	4b4a      	ldr	r3, [pc, #296]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 8005310:	494b      	ldr	r1, [pc, #300]	@ (8005440 <HAL_RCCEx_PeriphCLKConfig+0x1c4>)
- 8005312:	400a      	ands	r2, r1
- 8005314:	65da      	str	r2, [r3, #92]	@ 0x5c
-      /* Restore the Content of CSR1 register */
-      RCC->CSR1 = tmpregister;
- 8005316:	4b48      	ldr	r3, [pc, #288]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 8005318:	697a      	ldr	r2, [r7, #20]
- 800531a:	65da      	str	r2, [r3, #92]	@ 0x5c
-    }
-
-    /* Wait for LSE reactivation if LSE was enable prior to RTC Domain reset */
-    if (HAL_IS_BIT_SET(tmpregister, RCC_CSR1_LSEON))
- 800531c:	697b      	ldr	r3, [r7, #20]
- 800531e:	2201      	movs	r2, #1
- 8005320:	4013      	ands	r3, r2
- 8005322:	d016      	beq.n	8005352 <HAL_RCCEx_PeriphCLKConfig+0xd6>
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
- 8005324:	f7fe fed8 	bl	80040d8 <HAL_GetTick>
- 8005328:	0003      	movs	r3, r0
- 800532a:	60fb      	str	r3, [r7, #12]
-
-      /* Wait till LSE is ready */
-      while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
- 800532c:	e00c      	b.n	8005348 <HAL_RCCEx_PeriphCLKConfig+0xcc>
-      {
-        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
- 800532e:	f7fe fed3 	bl	80040d8 <HAL_GetTick>
- 8005332:	0002      	movs	r2, r0
- 8005334:	68fb      	ldr	r3, [r7, #12]
- 8005336:	1ad3      	subs	r3, r2, r3
- 8005338:	4a42      	ldr	r2, [pc, #264]	@ (8005444 <HAL_RCCEx_PeriphCLKConfig+0x1c8>)
- 800533a:	4293      	cmp	r3, r2
- 800533c:	d904      	bls.n	8005348 <HAL_RCCEx_PeriphCLKConfig+0xcc>
-        {
-          ret = HAL_TIMEOUT;
- 800533e:	2313      	movs	r3, #19
- 8005340:	18fb      	adds	r3, r7, r3
- 8005342:	2203      	movs	r2, #3
- 8005344:	701a      	strb	r2, [r3, #0]
-          break;
- 8005346:	e004      	b.n	8005352 <HAL_RCCEx_PeriphCLKConfig+0xd6>
-      while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
- 8005348:	4b3b      	ldr	r3, [pc, #236]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 800534a:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
- 800534c:	2202      	movs	r2, #2
- 800534e:	4013      	ands	r3, r2
- 8005350:	d0ed      	beq.n	800532e <HAL_RCCEx_PeriphCLKConfig+0xb2>
-        }
-      }
+ 8003800:	421a      	tst	r2, r3
+ 8003802:	d13b      	bne.n	800387c <HAL_RCCEx_PeriphCLKConfig+0xb4>
+  HAL_StatusTypeDef status = HAL_OK;   /* Final status */
+ 8003804:	2000      	movs	r0, #0
     }
 
     if (ret == HAL_OK)
- 8005352:	2313      	movs	r3, #19
- 8005354:	18fb      	adds	r3, r7, r3
- 8005356:	781b      	ldrb	r3, [r3, #0]
- 8005358:	2b00      	cmp	r3, #0
- 800535a:	d10a      	bne.n	8005372 <HAL_RCCEx_PeriphCLKConfig+0xf6>
     {
       /* Apply new RTC clock source selection */
       __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
- 800535c:	4b36      	ldr	r3, [pc, #216]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 800535e:	6ddb      	ldr	r3, [r3, #92]	@ 0x5c
- 8005360:	4a36      	ldr	r2, [pc, #216]	@ (800543c <HAL_RCCEx_PeriphCLKConfig+0x1c0>)
- 8005362:	4013      	ands	r3, r2
- 8005364:	0019      	movs	r1, r3
- 8005366:	687b      	ldr	r3, [r7, #4]
- 8005368:	699a      	ldr	r2, [r3, #24]
- 800536a:	4b33      	ldr	r3, [pc, #204]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 800536c:	430a      	orrs	r2, r1
- 800536e:	65da      	str	r2, [r3, #92]	@ 0x5c
- 8005370:	e005      	b.n	800537e <HAL_RCCEx_PeriphCLKConfig+0x102>
-    }
-    else
-    {
+ 8003806:	6de3      	ldr	r3, [r4, #92]	@ 0x5c
+ 8003808:	69aa      	ldr	r2, [r5, #24]
+ 800380a:	403b      	ands	r3, r7
+ 800380c:	4313      	orrs	r3, r2
+ 800380e:	65e3      	str	r3, [r4, #92]	@ 0x5c
       /* set overall return value */
       status = ret;
- 8005372:	2312      	movs	r3, #18
- 8005374:	18fb      	adds	r3, r7, r3
- 8005376:	2213      	movs	r2, #19
- 8005378:	18ba      	adds	r2, r7, r2
- 800537a:	7812      	ldrb	r2, [r2, #0]
- 800537c:	701a      	strb	r2, [r3, #0]
     }
 
     /* Restore clock configuration if changed */
     if (pwrclkchanged == SET)
- 800537e:	2311      	movs	r3, #17
- 8005380:	18fb      	adds	r3, r7, r3
- 8005382:	781b      	ldrb	r3, [r3, #0]
- 8005384:	2b01      	cmp	r3, #1
- 8005386:	d105      	bne.n	8005394 <HAL_RCCEx_PeriphCLKConfig+0x118>
+ 8003810:	2e01      	cmp	r6, #1
+ 8003812:	d103      	bne.n	800381c <HAL_RCCEx_PeriphCLKConfig+0x54>
     {
       __HAL_RCC_PWR_CLK_DISABLE();
- 8005388:	4b2b      	ldr	r3, [pc, #172]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 800538a:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
- 800538c:	4b2a      	ldr	r3, [pc, #168]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 800538e:	492e      	ldr	r1, [pc, #184]	@ (8005448 <HAL_RCCEx_PeriphCLKConfig+0x1cc>)
- 8005390:	400a      	ands	r2, r1
- 8005392:	63da      	str	r2, [r3, #60]	@ 0x3c
+ 8003814:	6be3      	ldr	r3, [r4, #60]	@ 0x3c
+ 8003816:	4a2c      	ldr	r2, [pc, #176]	@ (80038c8 <HAL_RCCEx_PeriphCLKConfig+0x100>)
+ 8003818:	4013      	ands	r3, r2
+ 800381a:	63e3      	str	r3, [r4, #60]	@ 0x3c
     }
   }
 
   /*-------------------------- USART1 clock source configuration -------------------*/
   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1)
- 8005394:	687b      	ldr	r3, [r7, #4]
- 8005396:	681b      	ldr	r3, [r3, #0]
- 8005398:	2201      	movs	r2, #1
- 800539a:	4013      	ands	r3, r2
- 800539c:	d009      	beq.n	80053b2 <HAL_RCCEx_PeriphCLKConfig+0x136>
+ 800381c:	682a      	ldr	r2, [r5, #0]
+ 800381e:	07d3      	lsls	r3, r2, #31
+ 8003820:	d506      	bpl.n	8003830 <HAL_RCCEx_PeriphCLKConfig+0x68>
   {
     /* Check the parameters */
     assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection));
 
     /* Configure the USART1 clock source */
     __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
- 800539e:	4b26      	ldr	r3, [pc, #152]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80053a0:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
- 80053a2:	2203      	movs	r2, #3
- 80053a4:	4393      	bics	r3, r2
- 80053a6:	0019      	movs	r1, r3
- 80053a8:	687b      	ldr	r3, [r7, #4]
- 80053aa:	689a      	ldr	r2, [r3, #8]
- 80053ac:	4b22      	ldr	r3, [pc, #136]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80053ae:	430a      	orrs	r2, r1
- 80053b0:	655a      	str	r2, [r3, #84]	@ 0x54
+ 8003822:	2403      	movs	r4, #3
+ 8003824:	4926      	ldr	r1, [pc, #152]	@ (80038c0 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
+ 8003826:	6d4b      	ldr	r3, [r1, #84]	@ 0x54
+ 8003828:	43a3      	bics	r3, r4
+ 800382a:	68ac      	ldr	r4, [r5, #8]
+ 800382c:	4323      	orrs	r3, r4
+ 800382e:	654b      	str	r3, [r1, #84]	@ 0x54
   }
 
   /*-------------------------- I2C1 clock source configuration ---------------------*/
   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1)
- 80053b2:	687b      	ldr	r3, [r7, #4]
- 80053b4:	681b      	ldr	r3, [r3, #0]
- 80053b6:	2202      	movs	r2, #2
- 80053b8:	4013      	ands	r3, r2
- 80053ba:	d009      	beq.n	80053d0 <HAL_RCCEx_PeriphCLKConfig+0x154>
+ 8003830:	0793      	lsls	r3, r2, #30
+ 8003832:	d506      	bpl.n	8003842 <HAL_RCCEx_PeriphCLKConfig+0x7a>
   {
     /* Check the parameters */
     assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection));
 
     /* Configure the I2C1 clock source */
     __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
- 80053bc:	4b1e      	ldr	r3, [pc, #120]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80053be:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
- 80053c0:	4a22      	ldr	r2, [pc, #136]	@ (800544c <HAL_RCCEx_PeriphCLKConfig+0x1d0>)
- 80053c2:	4013      	ands	r3, r2
- 80053c4:	0019      	movs	r1, r3
- 80053c6:	687b      	ldr	r3, [r7, #4]
- 80053c8:	68da      	ldr	r2, [r3, #12]
- 80053ca:	4b1b      	ldr	r3, [pc, #108]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80053cc:	430a      	orrs	r2, r1
- 80053ce:	655a      	str	r2, [r3, #84]	@ 0x54
+ 8003834:	4922      	ldr	r1, [pc, #136]	@ (80038c0 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
+ 8003836:	4c25      	ldr	r4, [pc, #148]	@ (80038cc <HAL_RCCEx_PeriphCLKConfig+0x104>)
+ 8003838:	6d4b      	ldr	r3, [r1, #84]	@ 0x54
+ 800383a:	4023      	ands	r3, r4
+ 800383c:	68ec      	ldr	r4, [r5, #12]
+ 800383e:	4323      	orrs	r3, r4
+ 8003840:	654b      	str	r3, [r1, #84]	@ 0x54
   }
 
   /*-------------------------- ADC clock source configuration ----------------------*/
   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC)
- 80053d0:	687b      	ldr	r3, [r7, #4]
- 80053d2:	681b      	ldr	r3, [r3, #0]
- 80053d4:	2220      	movs	r2, #32
- 80053d6:	4013      	ands	r3, r2
- 80053d8:	d008      	beq.n	80053ec <HAL_RCCEx_PeriphCLKConfig+0x170>
+ 8003842:	0693      	lsls	r3, r2, #26
+ 8003844:	d506      	bpl.n	8003854 <HAL_RCCEx_PeriphCLKConfig+0x8c>
   {
     /* Check the parameters */
     assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection));
 
     /* Configure the ADC interface clock source */
     __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection);
- 80053da:	4b17      	ldr	r3, [pc, #92]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80053dc:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
- 80053de:	009b      	lsls	r3, r3, #2
- 80053e0:	0899      	lsrs	r1, r3, #2
- 80053e2:	687b      	ldr	r3, [r7, #4]
- 80053e4:	695a      	ldr	r2, [r3, #20]
- 80053e6:	4b14      	ldr	r3, [pc, #80]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80053e8:	430a      	orrs	r2, r1
- 80053ea:	655a      	str	r2, [r3, #84]	@ 0x54
+ 8003846:	491e      	ldr	r1, [pc, #120]	@ (80038c0 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
+ 8003848:	696c      	ldr	r4, [r5, #20]
+ 800384a:	6d4b      	ldr	r3, [r1, #84]	@ 0x54
+ 800384c:	009b      	lsls	r3, r3, #2
+ 800384e:	089b      	lsrs	r3, r3, #2
+ 8003850:	4323      	orrs	r3, r4
+ 8003852:	654b      	str	r3, [r1, #84]	@ 0x54
     __HAL_RCC_FDCAN1_CONFIG(PeriphClkInit->Fdcan1ClockSelection);
 
   }
 #endif /* FDCAN1 */
   /*-------------------------- I2S1 clock source configuration ---------------------*/
   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S1) == RCC_PERIPHCLK_I2S1)
- 80053ec:	687b      	ldr	r3, [r7, #4]
- 80053ee:	681b      	ldr	r3, [r3, #0]
- 80053f0:	2204      	movs	r2, #4
- 80053f2:	4013      	ands	r3, r2
- 80053f4:	d009      	beq.n	800540a <HAL_RCCEx_PeriphCLKConfig+0x18e>
+ 8003854:	0753      	lsls	r3, r2, #29
+ 8003856:	d506      	bpl.n	8003866 <HAL_RCCEx_PeriphCLKConfig+0x9e>
   {
     /* Check the parameters */
     assert_param(IS_RCC_I2S1CLKSOURCE(PeriphClkInit->I2s1ClockSelection));
 
     /* Configure the I2S1 clock source */
     __HAL_RCC_I2S1_CONFIG(PeriphClkInit->I2s1ClockSelection);
- 80053f6:	4b10      	ldr	r3, [pc, #64]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 80053f8:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
- 80053fa:	4a15      	ldr	r2, [pc, #84]	@ (8005450 <HAL_RCCEx_PeriphCLKConfig+0x1d4>)
- 80053fc:	4013      	ands	r3, r2
- 80053fe:	0019      	movs	r1, r3
- 8005400:	687b      	ldr	r3, [r7, #4]
- 8005402:	691a      	ldr	r2, [r3, #16]
- 8005404:	4b0c      	ldr	r3, [pc, #48]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 8005406:	430a      	orrs	r2, r1
- 8005408:	655a      	str	r2, [r3, #84]	@ 0x54
+ 8003858:	4919      	ldr	r1, [pc, #100]	@ (80038c0 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
+ 800385a:	4c1d      	ldr	r4, [pc, #116]	@ (80038d0 <HAL_RCCEx_PeriphCLKConfig+0x108>)
+ 800385c:	6d4b      	ldr	r3, [r1, #84]	@ 0x54
+ 800385e:	4023      	ands	r3, r4
+ 8003860:	692c      	ldr	r4, [r5, #16]
+ 8003862:	4323      	orrs	r3, r4
+ 8003864:	654b      	str	r3, [r1, #84]	@ 0x54
   }
   /*------------------------------------ HSI Kernel clock source configuration --------------------------------------*/
   if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSIKER) == RCC_PERIPHCLK_HSIKER)
- 800540a:	687b      	ldr	r3, [r7, #4]
- 800540c:	681b      	ldr	r3, [r3, #0]
- 800540e:	2280      	movs	r2, #128	@ 0x80
- 8005410:	4013      	ands	r3, r2
- 8005412:	d009      	beq.n	8005428 <HAL_RCCEx_PeriphCLKConfig+0x1ac>
+ 8003866:	0612      	lsls	r2, r2, #24
+ 8003868:	d506      	bpl.n	8003878 <HAL_RCCEx_PeriphCLKConfig+0xb0>
   {
     /* Check the parameters */
     assert_param(IS_RCC_HSIKERDIV(PeriphClkInit->HSIKerClockDivider));
 
     /* Configure the HSI Kernel clock source Divider */
     __HAL_RCC_HSIKER_CONFIG(PeriphClkInit->HSIKerClockDivider);
- 8005414:	4b08      	ldr	r3, [pc, #32]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 8005416:	681b      	ldr	r3, [r3, #0]
- 8005418:	22e0      	movs	r2, #224	@ 0xe0
- 800541a:	4393      	bics	r3, r2
- 800541c:	0019      	movs	r1, r3
- 800541e:	687b      	ldr	r3, [r7, #4]
- 8005420:	685a      	ldr	r2, [r3, #4]
- 8005422:	4b05      	ldr	r3, [pc, #20]	@ (8005438 <HAL_RCCEx_PeriphCLKConfig+0x1bc>)
- 8005424:	430a      	orrs	r2, r1
- 8005426:	601a      	str	r2, [r3, #0]
+ 800386a:	21e0      	movs	r1, #224	@ 0xe0
+ 800386c:	4a14      	ldr	r2, [pc, #80]	@ (80038c0 <HAL_RCCEx_PeriphCLKConfig+0xf8>)
+ 800386e:	6813      	ldr	r3, [r2, #0]
+ 8003870:	438b      	bics	r3, r1
+ 8003872:	6869      	ldr	r1, [r5, #4]
+ 8003874:	430b      	orrs	r3, r1
+ 8003876:	6013      	str	r3, [r2, #0]
   }
   return status;
- 8005428:	2312      	movs	r3, #18
- 800542a:	18fb      	adds	r3, r7, r3
- 800542c:	781b      	ldrb	r3, [r3, #0]
 }
- 800542e:	0018      	movs	r0, r3
- 8005430:	46bd      	mov	sp, r7
- 8005432:	b006      	add	sp, #24
- 8005434:	bd80      	pop	{r7, pc}
- 8005436:	46c0      	nop			@ (mov r8, r8)
- 8005438:	40021000 	.word	0x40021000
- 800543c:	fffffcff 	.word	0xfffffcff
- 8005440:	fffeffff 	.word	0xfffeffff
- 8005444:	00001388 	.word	0x00001388
- 8005448:	efffffff 	.word	0xefffffff
- 800544c:	ffffcfff 	.word	0xffffcfff
- 8005450:	ffff3fff 	.word	0xffff3fff
-
-08005454 <HAL_TIM_Base_Init>:
-  *         Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
- 8005454:	b580      	push	{r7, lr}
- 8005456:	b082      	sub	sp, #8
- 8005458:	af00      	add	r7, sp, #0
- 800545a:	6078      	str	r0, [r7, #4]
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
- 800545c:	687b      	ldr	r3, [r7, #4]
- 800545e:	2b00      	cmp	r3, #0
- 8005460:	d101      	bne.n	8005466 <HAL_TIM_Base_Init+0x12>
-  {
-    return HAL_ERROR;
- 8005462:	2301      	movs	r3, #1
- 8005464:	e04a      	b.n	80054fc <HAL_TIM_Base_Init+0xa8>
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
- 8005466:	687b      	ldr	r3, [r7, #4]
- 8005468:	223d      	movs	r2, #61	@ 0x3d
- 800546a:	5c9b      	ldrb	r3, [r3, r2]
- 800546c:	b2db      	uxtb	r3, r3
- 800546e:	2b00      	cmp	r3, #0
- 8005470:	d107      	bne.n	8005482 <HAL_TIM_Base_Init+0x2e>
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
- 8005472:	687b      	ldr	r3, [r7, #4]
- 8005474:	223c      	movs	r2, #60	@ 0x3c
- 8005476:	2100      	movs	r1, #0
- 8005478:	5499      	strb	r1, [r3, r2]
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->Base_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    HAL_TIM_Base_MspInit(htim);
- 800547a:	687b      	ldr	r3, [r7, #4]
- 800547c:	0018      	movs	r0, r3
- 800547e:	f7fe fb0f 	bl	8003aa0 <HAL_TIM_Base_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
- 8005482:	687b      	ldr	r3, [r7, #4]
- 8005484:	223d      	movs	r2, #61	@ 0x3d
- 8005486:	2102      	movs	r1, #2
- 8005488:	5499      	strb	r1, [r3, r2]
-
-  /* Set the Time Base configuration */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 800548a:	687b      	ldr	r3, [r7, #4]
- 800548c:	681a      	ldr	r2, [r3, #0]
- 800548e:	687b      	ldr	r3, [r7, #4]
- 8005490:	3304      	adds	r3, #4
- 8005492:	0019      	movs	r1, r3
- 8005494:	0010      	movs	r0, r2
- 8005496:	f000 fe37 	bl	8006108 <TIM_Base_SetConfig>
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
- 800549a:	687b      	ldr	r3, [r7, #4]
- 800549c:	2248      	movs	r2, #72	@ 0x48
- 800549e:	2101      	movs	r1, #1
- 80054a0:	5499      	strb	r1, [r3, r2]
-
-  /* Initialize the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- 80054a2:	687b      	ldr	r3, [r7, #4]
- 80054a4:	223e      	movs	r2, #62	@ 0x3e
- 80054a6:	2101      	movs	r1, #1
- 80054a8:	5499      	strb	r1, [r3, r2]
- 80054aa:	687b      	ldr	r3, [r7, #4]
- 80054ac:	223f      	movs	r2, #63	@ 0x3f
- 80054ae:	2101      	movs	r1, #1
- 80054b0:	5499      	strb	r1, [r3, r2]
- 80054b2:	687b      	ldr	r3, [r7, #4]
- 80054b4:	2240      	movs	r2, #64	@ 0x40
- 80054b6:	2101      	movs	r1, #1
- 80054b8:	5499      	strb	r1, [r3, r2]
- 80054ba:	687b      	ldr	r3, [r7, #4]
- 80054bc:	2241      	movs	r2, #65	@ 0x41
- 80054be:	2101      	movs	r1, #1
- 80054c0:	5499      	strb	r1, [r3, r2]
- 80054c2:	687b      	ldr	r3, [r7, #4]
- 80054c4:	2242      	movs	r2, #66	@ 0x42
- 80054c6:	2101      	movs	r1, #1
- 80054c8:	5499      	strb	r1, [r3, r2]
- 80054ca:	687b      	ldr	r3, [r7, #4]
- 80054cc:	2243      	movs	r2, #67	@ 0x43
- 80054ce:	2101      	movs	r1, #1
- 80054d0:	5499      	strb	r1, [r3, r2]
-  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- 80054d2:	687b      	ldr	r3, [r7, #4]
- 80054d4:	2244      	movs	r2, #68	@ 0x44
- 80054d6:	2101      	movs	r1, #1
- 80054d8:	5499      	strb	r1, [r3, r2]
- 80054da:	687b      	ldr	r3, [r7, #4]
- 80054dc:	2245      	movs	r2, #69	@ 0x45
- 80054de:	2101      	movs	r1, #1
- 80054e0:	5499      	strb	r1, [r3, r2]
- 80054e2:	687b      	ldr	r3, [r7, #4]
- 80054e4:	2246      	movs	r2, #70	@ 0x46
- 80054e6:	2101      	movs	r1, #1
- 80054e8:	5499      	strb	r1, [r3, r2]
- 80054ea:	687b      	ldr	r3, [r7, #4]
- 80054ec:	2247      	movs	r2, #71	@ 0x47
- 80054ee:	2101      	movs	r1, #1
- 80054f0:	5499      	strb	r1, [r3, r2]
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
- 80054f2:	687b      	ldr	r3, [r7, #4]
- 80054f4:	223d      	movs	r2, #61	@ 0x3d
- 80054f6:	2101      	movs	r1, #1
- 80054f8:	5499      	strb	r1, [r3, r2]
-
-  return HAL_OK;
- 80054fa:	2300      	movs	r3, #0
-}
- 80054fc:	0018      	movs	r0, r3
- 80054fe:	46bd      	mov	sp, r7
- 8005500:	b002      	add	sp, #8
- 8005502:	bd80      	pop	{r7, pc}
-
-08005504 <HAL_TIM_Base_Stop>:
-  * @brief  Stops the TIM Base generation.
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
-{
- 8005504:	b580      	push	{r7, lr}
- 8005506:	b082      	sub	sp, #8
- 8005508:	af00      	add	r7, sp, #0
- 800550a:	6078      	str	r0, [r7, #4]
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
- 800550c:	687b      	ldr	r3, [r7, #4]
- 800550e:	681b      	ldr	r3, [r3, #0]
- 8005510:	6a1b      	ldr	r3, [r3, #32]
- 8005512:	4a0d      	ldr	r2, [pc, #52]	@ (8005548 <HAL_TIM_Base_Stop+0x44>)
- 8005514:	4013      	ands	r3, r2
- 8005516:	d10d      	bne.n	8005534 <HAL_TIM_Base_Stop+0x30>
- 8005518:	687b      	ldr	r3, [r7, #4]
- 800551a:	681b      	ldr	r3, [r3, #0]
- 800551c:	6a1b      	ldr	r3, [r3, #32]
- 800551e:	4a0b      	ldr	r2, [pc, #44]	@ (800554c <HAL_TIM_Base_Stop+0x48>)
- 8005520:	4013      	ands	r3, r2
- 8005522:	d107      	bne.n	8005534 <HAL_TIM_Base_Stop+0x30>
- 8005524:	687b      	ldr	r3, [r7, #4]
- 8005526:	681b      	ldr	r3, [r3, #0]
- 8005528:	681a      	ldr	r2, [r3, #0]
- 800552a:	687b      	ldr	r3, [r7, #4]
- 800552c:	681b      	ldr	r3, [r3, #0]
- 800552e:	2101      	movs	r1, #1
- 8005530:	438a      	bics	r2, r1
- 8005532:	601a      	str	r2, [r3, #0]
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
- 8005534:	687b      	ldr	r3, [r7, #4]
- 8005536:	223d      	movs	r2, #61	@ 0x3d
- 8005538:	2101      	movs	r1, #1
- 800553a:	5499      	strb	r1, [r3, r2]
-
-  /* Return function status */
-  return HAL_OK;
- 800553c:	2300      	movs	r3, #0
-}
- 800553e:	0018      	movs	r0, r3
- 8005540:	46bd      	mov	sp, r7
- 8005542:	b002      	add	sp, #8
- 8005544:	bd80      	pop	{r7, pc}
- 8005546:	46c0      	nop			@ (mov r8, r8)
- 8005548:	00001111 	.word	0x00001111
- 800554c:	00000444 	.word	0x00000444
-
-08005550 <HAL_TIM_Base_Start_IT>:
-  * @brief  Starts the TIM Base generation in interrupt mode.
-  * @param  htim TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
- 8005550:	b580      	push	{r7, lr}
- 8005552:	b084      	sub	sp, #16
- 8005554:	af00      	add	r7, sp, #0
- 8005556:	6078      	str	r0, [r7, #4]
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Check the TIM state */
-  if (htim->State != HAL_TIM_STATE_READY)
- 8005558:	687b      	ldr	r3, [r7, #4]
- 800555a:	223d      	movs	r2, #61	@ 0x3d
- 800555c:	5c9b      	ldrb	r3, [r3, r2]
- 800555e:	b2db      	uxtb	r3, r3
- 8005560:	2b01      	cmp	r3, #1
- 8005562:	d001      	beq.n	8005568 <HAL_TIM_Base_Start_IT+0x18>
-  {
-    return HAL_ERROR;
- 8005564:	2301      	movs	r3, #1
- 8005566:	e03d      	b.n	80055e4 <HAL_TIM_Base_Start_IT+0x94>
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
- 8005568:	687b      	ldr	r3, [r7, #4]
- 800556a:	223d      	movs	r2, #61	@ 0x3d
- 800556c:	2102      	movs	r1, #2
- 800556e:	5499      	strb	r1, [r3, r2]
-
-  /* Enable the TIM Update interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
- 8005570:	687b      	ldr	r3, [r7, #4]
- 8005572:	681b      	ldr	r3, [r3, #0]
- 8005574:	68da      	ldr	r2, [r3, #12]
- 8005576:	687b      	ldr	r3, [r7, #4]
- 8005578:	681b      	ldr	r3, [r3, #0]
- 800557a:	2101      	movs	r1, #1
- 800557c:	430a      	orrs	r2, r1
- 800557e:	60da      	str	r2, [r3, #12]
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- 8005580:	687b      	ldr	r3, [r7, #4]
- 8005582:	681b      	ldr	r3, [r3, #0]
- 8005584:	4a19      	ldr	r2, [pc, #100]	@ (80055ec <HAL_TIM_Base_Start_IT+0x9c>)
- 8005586:	4293      	cmp	r3, r2
- 8005588:	d00a      	beq.n	80055a0 <HAL_TIM_Base_Start_IT+0x50>
- 800558a:	687b      	ldr	r3, [r7, #4]
- 800558c:	681a      	ldr	r2, [r3, #0]
- 800558e:	2380      	movs	r3, #128	@ 0x80
- 8005590:	05db      	lsls	r3, r3, #23
- 8005592:	429a      	cmp	r2, r3
- 8005594:	d004      	beq.n	80055a0 <HAL_TIM_Base_Start_IT+0x50>
- 8005596:	687b      	ldr	r3, [r7, #4]
- 8005598:	681b      	ldr	r3, [r3, #0]
- 800559a:	4a15      	ldr	r2, [pc, #84]	@ (80055f0 <HAL_TIM_Base_Start_IT+0xa0>)
- 800559c:	4293      	cmp	r3, r2
- 800559e:	d116      	bne.n	80055ce <HAL_TIM_Base_Start_IT+0x7e>
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 80055a0:	687b      	ldr	r3, [r7, #4]
- 80055a2:	681b      	ldr	r3, [r3, #0]
- 80055a4:	689b      	ldr	r3, [r3, #8]
- 80055a6:	4a13      	ldr	r2, [pc, #76]	@ (80055f4 <HAL_TIM_Base_Start_IT+0xa4>)
- 80055a8:	4013      	ands	r3, r2
- 80055aa:	60fb      	str	r3, [r7, #12]
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 80055ac:	68fb      	ldr	r3, [r7, #12]
- 80055ae:	2b06      	cmp	r3, #6
- 80055b0:	d016      	beq.n	80055e0 <HAL_TIM_Base_Start_IT+0x90>
- 80055b2:	68fa      	ldr	r2, [r7, #12]
- 80055b4:	2380      	movs	r3, #128	@ 0x80
- 80055b6:	025b      	lsls	r3, r3, #9
- 80055b8:	429a      	cmp	r2, r3
- 80055ba:	d011      	beq.n	80055e0 <HAL_TIM_Base_Start_IT+0x90>
-    {
-      __HAL_TIM_ENABLE(htim);
- 80055bc:	687b      	ldr	r3, [r7, #4]
- 80055be:	681b      	ldr	r3, [r3, #0]
- 80055c0:	681a      	ldr	r2, [r3, #0]
- 80055c2:	687b      	ldr	r3, [r7, #4]
- 80055c4:	681b      	ldr	r3, [r3, #0]
- 80055c6:	2101      	movs	r1, #1
- 80055c8:	430a      	orrs	r2, r1
- 80055ca:	601a      	str	r2, [r3, #0]
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 80055cc:	e008      	b.n	80055e0 <HAL_TIM_Base_Start_IT+0x90>
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
- 80055ce:	687b      	ldr	r3, [r7, #4]
- 80055d0:	681b      	ldr	r3, [r3, #0]
- 80055d2:	681a      	ldr	r2, [r3, #0]
- 80055d4:	687b      	ldr	r3, [r7, #4]
- 80055d6:	681b      	ldr	r3, [r3, #0]
- 80055d8:	2101      	movs	r1, #1
- 80055da:	430a      	orrs	r2, r1
- 80055dc:	601a      	str	r2, [r3, #0]
- 80055de:	e000      	b.n	80055e2 <HAL_TIM_Base_Start_IT+0x92>
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 80055e0:	46c0      	nop			@ (mov r8, r8)
-  }
-
-  /* Return function status */
-  return HAL_OK;
- 80055e2:	2300      	movs	r3, #0
-}
- 80055e4:	0018      	movs	r0, r3
- 80055e6:	46bd      	mov	sp, r7
- 80055e8:	b004      	add	sp, #16
- 80055ea:	bd80      	pop	{r7, pc}
- 80055ec:	40012c00 	.word	0x40012c00
- 80055f0:	40000400 	.word	0x40000400
- 80055f4:	00010007 	.word	0x00010007
-
-080055f8 <HAL_TIM_PWM_Init>:
-  *         Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
-  * @param  htim TIM PWM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
- 80055f8:	b580      	push	{r7, lr}
- 80055fa:	b082      	sub	sp, #8
- 80055fc:	af00      	add	r7, sp, #0
- 80055fe:	6078      	str	r0, [r7, #4]
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
- 8005600:	687b      	ldr	r3, [r7, #4]
- 8005602:	2b00      	cmp	r3, #0
- 8005604:	d101      	bne.n	800560a <HAL_TIM_PWM_Init+0x12>
-  {
-    return HAL_ERROR;
- 8005606:	2301      	movs	r3, #1
- 8005608:	e04a      	b.n	80056a0 <HAL_TIM_PWM_Init+0xa8>
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
-  assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
- 800560a:	687b      	ldr	r3, [r7, #4]
- 800560c:	223d      	movs	r2, #61	@ 0x3d
- 800560e:	5c9b      	ldrb	r3, [r3, r2]
- 8005610:	b2db      	uxtb	r3, r3
- 8005612:	2b00      	cmp	r3, #0
- 8005614:	d107      	bne.n	8005626 <HAL_TIM_PWM_Init+0x2e>
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
- 8005616:	687b      	ldr	r3, [r7, #4]
- 8005618:	223c      	movs	r2, #60	@ 0x3c
- 800561a:	2100      	movs	r1, #0
- 800561c:	5499      	strb	r1, [r3, r2]
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->PWM_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_PWM_MspInit(htim);
- 800561e:	687b      	ldr	r3, [r7, #4]
- 8005620:	0018      	movs	r0, r3
- 8005622:	f000 f841 	bl	80056a8 <HAL_TIM_PWM_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
- 8005626:	687b      	ldr	r3, [r7, #4]
- 8005628:	223d      	movs	r2, #61	@ 0x3d
- 800562a:	2102      	movs	r1, #2
- 800562c:	5499      	strb	r1, [r3, r2]
-
-  /* Init the base time for the PWM */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 800562e:	687b      	ldr	r3, [r7, #4]
- 8005630:	681a      	ldr	r2, [r3, #0]
- 8005632:	687b      	ldr	r3, [r7, #4]
- 8005634:	3304      	adds	r3, #4
- 8005636:	0019      	movs	r1, r3
- 8005638:	0010      	movs	r0, r2
- 800563a:	f000 fd65 	bl	8006108 <TIM_Base_SetConfig>
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
- 800563e:	687b      	ldr	r3, [r7, #4]
- 8005640:	2248      	movs	r2, #72	@ 0x48
- 8005642:	2101      	movs	r1, #1
- 8005644:	5499      	strb	r1, [r3, r2]
-
-  /* Initialize the TIM channels state */
-  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- 8005646:	687b      	ldr	r3, [r7, #4]
- 8005648:	223e      	movs	r2, #62	@ 0x3e
- 800564a:	2101      	movs	r1, #1
- 800564c:	5499      	strb	r1, [r3, r2]
- 800564e:	687b      	ldr	r3, [r7, #4]
- 8005650:	223f      	movs	r2, #63	@ 0x3f
- 8005652:	2101      	movs	r1, #1
- 8005654:	5499      	strb	r1, [r3, r2]
- 8005656:	687b      	ldr	r3, [r7, #4]
- 8005658:	2240      	movs	r2, #64	@ 0x40
- 800565a:	2101      	movs	r1, #1
- 800565c:	5499      	strb	r1, [r3, r2]
- 800565e:	687b      	ldr	r3, [r7, #4]
- 8005660:	2241      	movs	r2, #65	@ 0x41
- 8005662:	2101      	movs	r1, #1
- 8005664:	5499      	strb	r1, [r3, r2]
- 8005666:	687b      	ldr	r3, [r7, #4]
- 8005668:	2242      	movs	r2, #66	@ 0x42
- 800566a:	2101      	movs	r1, #1
- 800566c:	5499      	strb	r1, [r3, r2]
- 800566e:	687b      	ldr	r3, [r7, #4]
- 8005670:	2243      	movs	r2, #67	@ 0x43
- 8005672:	2101      	movs	r1, #1
- 8005674:	5499      	strb	r1, [r3, r2]
-  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
- 8005676:	687b      	ldr	r3, [r7, #4]
- 8005678:	2244      	movs	r2, #68	@ 0x44
- 800567a:	2101      	movs	r1, #1
- 800567c:	5499      	strb	r1, [r3, r2]
- 800567e:	687b      	ldr	r3, [r7, #4]
- 8005680:	2245      	movs	r2, #69	@ 0x45
- 8005682:	2101      	movs	r1, #1
- 8005684:	5499      	strb	r1, [r3, r2]
- 8005686:	687b      	ldr	r3, [r7, #4]
- 8005688:	2246      	movs	r2, #70	@ 0x46
- 800568a:	2101      	movs	r1, #1
- 800568c:	5499      	strb	r1, [r3, r2]
- 800568e:	687b      	ldr	r3, [r7, #4]
- 8005690:	2247      	movs	r2, #71	@ 0x47
- 8005692:	2101      	movs	r1, #1
- 8005694:	5499      	strb	r1, [r3, r2]
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
- 8005696:	687b      	ldr	r3, [r7, #4]
- 8005698:	223d      	movs	r2, #61	@ 0x3d
- 800569a:	2101      	movs	r1, #1
- 800569c:	5499      	strb	r1, [r3, r2]
-
-  return HAL_OK;
- 800569e:	2300      	movs	r3, #0
-}
- 80056a0:	0018      	movs	r0, r3
- 80056a2:	46bd      	mov	sp, r7
- 80056a4:	b002      	add	sp, #8
- 80056a6:	bd80      	pop	{r7, pc}
-
-080056a8 <HAL_TIM_PWM_MspInit>:
-  * @brief  Initializes the TIM PWM MSP.
-  * @param  htim TIM PWM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
- 80056a8:	b580      	push	{r7, lr}
- 80056aa:	b082      	sub	sp, #8
- 80056ac:	af00      	add	r7, sp, #0
- 80056ae:	6078      	str	r0, [r7, #4]
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspInit could be implemented in the user file
-   */
-}
- 80056b0:	46c0      	nop			@ (mov r8, r8)
- 80056b2:	46bd      	mov	sp, r7
- 80056b4:	b002      	add	sp, #8
- 80056b6:	bd80      	pop	{r7, pc}
-
-080056b8 <HAL_TIM_PWM_Start>:
-  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected
-  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- 80056b8:	b580      	push	{r7, lr}
- 80056ba:	b084      	sub	sp, #16
- 80056bc:	af00      	add	r7, sp, #0
- 80056be:	6078      	str	r0, [r7, #4]
- 80056c0:	6039      	str	r1, [r7, #0]
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Check the TIM channel state */
-  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
- 80056c2:	683b      	ldr	r3, [r7, #0]
- 80056c4:	2b00      	cmp	r3, #0
- 80056c6:	d108      	bne.n	80056da <HAL_TIM_PWM_Start+0x22>
- 80056c8:	687b      	ldr	r3, [r7, #4]
- 80056ca:	223e      	movs	r2, #62	@ 0x3e
- 80056cc:	5c9b      	ldrb	r3, [r3, r2]
- 80056ce:	b2db      	uxtb	r3, r3
- 80056d0:	3b01      	subs	r3, #1
- 80056d2:	1e5a      	subs	r2, r3, #1
- 80056d4:	4193      	sbcs	r3, r2
- 80056d6:	b2db      	uxtb	r3, r3
- 80056d8:	e037      	b.n	800574a <HAL_TIM_PWM_Start+0x92>
- 80056da:	683b      	ldr	r3, [r7, #0]
- 80056dc:	2b04      	cmp	r3, #4
- 80056de:	d108      	bne.n	80056f2 <HAL_TIM_PWM_Start+0x3a>
- 80056e0:	687b      	ldr	r3, [r7, #4]
- 80056e2:	223f      	movs	r2, #63	@ 0x3f
- 80056e4:	5c9b      	ldrb	r3, [r3, r2]
- 80056e6:	b2db      	uxtb	r3, r3
- 80056e8:	3b01      	subs	r3, #1
- 80056ea:	1e5a      	subs	r2, r3, #1
- 80056ec:	4193      	sbcs	r3, r2
- 80056ee:	b2db      	uxtb	r3, r3
- 80056f0:	e02b      	b.n	800574a <HAL_TIM_PWM_Start+0x92>
- 80056f2:	683b      	ldr	r3, [r7, #0]
- 80056f4:	2b08      	cmp	r3, #8
- 80056f6:	d108      	bne.n	800570a <HAL_TIM_PWM_Start+0x52>
- 80056f8:	687b      	ldr	r3, [r7, #4]
- 80056fa:	2240      	movs	r2, #64	@ 0x40
- 80056fc:	5c9b      	ldrb	r3, [r3, r2]
- 80056fe:	b2db      	uxtb	r3, r3
- 8005700:	3b01      	subs	r3, #1
- 8005702:	1e5a      	subs	r2, r3, #1
- 8005704:	4193      	sbcs	r3, r2
- 8005706:	b2db      	uxtb	r3, r3
- 8005708:	e01f      	b.n	800574a <HAL_TIM_PWM_Start+0x92>
- 800570a:	683b      	ldr	r3, [r7, #0]
- 800570c:	2b0c      	cmp	r3, #12
- 800570e:	d108      	bne.n	8005722 <HAL_TIM_PWM_Start+0x6a>
- 8005710:	687b      	ldr	r3, [r7, #4]
- 8005712:	2241      	movs	r2, #65	@ 0x41
- 8005714:	5c9b      	ldrb	r3, [r3, r2]
- 8005716:	b2db      	uxtb	r3, r3
- 8005718:	3b01      	subs	r3, #1
- 800571a:	1e5a      	subs	r2, r3, #1
- 800571c:	4193      	sbcs	r3, r2
- 800571e:	b2db      	uxtb	r3, r3
- 8005720:	e013      	b.n	800574a <HAL_TIM_PWM_Start+0x92>
- 8005722:	683b      	ldr	r3, [r7, #0]
- 8005724:	2b10      	cmp	r3, #16
- 8005726:	d108      	bne.n	800573a <HAL_TIM_PWM_Start+0x82>
- 8005728:	687b      	ldr	r3, [r7, #4]
- 800572a:	2242      	movs	r2, #66	@ 0x42
- 800572c:	5c9b      	ldrb	r3, [r3, r2]
- 800572e:	b2db      	uxtb	r3, r3
- 8005730:	3b01      	subs	r3, #1
- 8005732:	1e5a      	subs	r2, r3, #1
- 8005734:	4193      	sbcs	r3, r2
- 8005736:	b2db      	uxtb	r3, r3
- 8005738:	e007      	b.n	800574a <HAL_TIM_PWM_Start+0x92>
- 800573a:	687b      	ldr	r3, [r7, #4]
- 800573c:	2243      	movs	r2, #67	@ 0x43
- 800573e:	5c9b      	ldrb	r3, [r3, r2]
- 8005740:	b2db      	uxtb	r3, r3
- 8005742:	3b01      	subs	r3, #1
- 8005744:	1e5a      	subs	r2, r3, #1
- 8005746:	4193      	sbcs	r3, r2
- 8005748:	b2db      	uxtb	r3, r3
- 800574a:	2b00      	cmp	r3, #0
- 800574c:	d001      	beq.n	8005752 <HAL_TIM_PWM_Start+0x9a>
-  {
-    return HAL_ERROR;
- 800574e:	2301      	movs	r3, #1
- 8005750:	e081      	b.n	8005856 <HAL_TIM_PWM_Start+0x19e>
-  }
-
-  /* Set the TIM channel state */
-  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
- 8005752:	683b      	ldr	r3, [r7, #0]
- 8005754:	2b00      	cmp	r3, #0
- 8005756:	d104      	bne.n	8005762 <HAL_TIM_PWM_Start+0xaa>
- 8005758:	687b      	ldr	r3, [r7, #4]
- 800575a:	223e      	movs	r2, #62	@ 0x3e
- 800575c:	2102      	movs	r1, #2
- 800575e:	5499      	strb	r1, [r3, r2]
- 8005760:	e023      	b.n	80057aa <HAL_TIM_PWM_Start+0xf2>
- 8005762:	683b      	ldr	r3, [r7, #0]
- 8005764:	2b04      	cmp	r3, #4
- 8005766:	d104      	bne.n	8005772 <HAL_TIM_PWM_Start+0xba>
- 8005768:	687b      	ldr	r3, [r7, #4]
- 800576a:	223f      	movs	r2, #63	@ 0x3f
- 800576c:	2102      	movs	r1, #2
- 800576e:	5499      	strb	r1, [r3, r2]
- 8005770:	e01b      	b.n	80057aa <HAL_TIM_PWM_Start+0xf2>
- 8005772:	683b      	ldr	r3, [r7, #0]
- 8005774:	2b08      	cmp	r3, #8
- 8005776:	d104      	bne.n	8005782 <HAL_TIM_PWM_Start+0xca>
- 8005778:	687b      	ldr	r3, [r7, #4]
- 800577a:	2240      	movs	r2, #64	@ 0x40
- 800577c:	2102      	movs	r1, #2
- 800577e:	5499      	strb	r1, [r3, r2]
- 8005780:	e013      	b.n	80057aa <HAL_TIM_PWM_Start+0xf2>
- 8005782:	683b      	ldr	r3, [r7, #0]
- 8005784:	2b0c      	cmp	r3, #12
- 8005786:	d104      	bne.n	8005792 <HAL_TIM_PWM_Start+0xda>
- 8005788:	687b      	ldr	r3, [r7, #4]
- 800578a:	2241      	movs	r2, #65	@ 0x41
- 800578c:	2102      	movs	r1, #2
- 800578e:	5499      	strb	r1, [r3, r2]
- 8005790:	e00b      	b.n	80057aa <HAL_TIM_PWM_Start+0xf2>
- 8005792:	683b      	ldr	r3, [r7, #0]
- 8005794:	2b10      	cmp	r3, #16
- 8005796:	d104      	bne.n	80057a2 <HAL_TIM_PWM_Start+0xea>
- 8005798:	687b      	ldr	r3, [r7, #4]
- 800579a:	2242      	movs	r2, #66	@ 0x42
- 800579c:	2102      	movs	r1, #2
- 800579e:	5499      	strb	r1, [r3, r2]
- 80057a0:	e003      	b.n	80057aa <HAL_TIM_PWM_Start+0xf2>
- 80057a2:	687b      	ldr	r3, [r7, #4]
- 80057a4:	2243      	movs	r2, #67	@ 0x43
- 80057a6:	2102      	movs	r1, #2
- 80057a8:	5499      	strb	r1, [r3, r2]
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
- 80057aa:	687b      	ldr	r3, [r7, #4]
- 80057ac:	681b      	ldr	r3, [r3, #0]
- 80057ae:	6839      	ldr	r1, [r7, #0]
- 80057b0:	2201      	movs	r2, #1
- 80057b2:	0018      	movs	r0, r3
- 80057b4:	f001 f85c 	bl	8006870 <TIM_CCxChannelCmd>
-
-  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
- 80057b8:	687b      	ldr	r3, [r7, #4]
- 80057ba:	681b      	ldr	r3, [r3, #0]
- 80057bc:	4a28      	ldr	r2, [pc, #160]	@ (8005860 <HAL_TIM_PWM_Start+0x1a8>)
- 80057be:	4293      	cmp	r3, r2
- 80057c0:	d009      	beq.n	80057d6 <HAL_TIM_PWM_Start+0x11e>
- 80057c2:	687b      	ldr	r3, [r7, #4]
- 80057c4:	681b      	ldr	r3, [r3, #0]
- 80057c6:	4a27      	ldr	r2, [pc, #156]	@ (8005864 <HAL_TIM_PWM_Start+0x1ac>)
- 80057c8:	4293      	cmp	r3, r2
- 80057ca:	d004      	beq.n	80057d6 <HAL_TIM_PWM_Start+0x11e>
- 80057cc:	687b      	ldr	r3, [r7, #4]
- 80057ce:	681b      	ldr	r3, [r3, #0]
- 80057d0:	4a25      	ldr	r2, [pc, #148]	@ (8005868 <HAL_TIM_PWM_Start+0x1b0>)
- 80057d2:	4293      	cmp	r3, r2
- 80057d4:	d101      	bne.n	80057da <HAL_TIM_PWM_Start+0x122>
- 80057d6:	2301      	movs	r3, #1
- 80057d8:	e000      	b.n	80057dc <HAL_TIM_PWM_Start+0x124>
- 80057da:	2300      	movs	r3, #0
- 80057dc:	2b00      	cmp	r3, #0
- 80057de:	d008      	beq.n	80057f2 <HAL_TIM_PWM_Start+0x13a>
-  {
-    /* Enable the main output */
-    __HAL_TIM_MOE_ENABLE(htim);
- 80057e0:	687b      	ldr	r3, [r7, #4]
- 80057e2:	681b      	ldr	r3, [r3, #0]
- 80057e4:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
- 80057e6:	687b      	ldr	r3, [r7, #4]
- 80057e8:	681b      	ldr	r3, [r3, #0]
- 80057ea:	2180      	movs	r1, #128	@ 0x80
- 80057ec:	0209      	lsls	r1, r1, #8
- 80057ee:	430a      	orrs	r2, r1
- 80057f0:	645a      	str	r2, [r3, #68]	@ 0x44
-  }
-
-  /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
-  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- 80057f2:	687b      	ldr	r3, [r7, #4]
- 80057f4:	681b      	ldr	r3, [r3, #0]
- 80057f6:	4a1a      	ldr	r2, [pc, #104]	@ (8005860 <HAL_TIM_PWM_Start+0x1a8>)
- 80057f8:	4293      	cmp	r3, r2
- 80057fa:	d00a      	beq.n	8005812 <HAL_TIM_PWM_Start+0x15a>
- 80057fc:	687b      	ldr	r3, [r7, #4]
- 80057fe:	681a      	ldr	r2, [r3, #0]
- 8005800:	2380      	movs	r3, #128	@ 0x80
- 8005802:	05db      	lsls	r3, r3, #23
- 8005804:	429a      	cmp	r2, r3
- 8005806:	d004      	beq.n	8005812 <HAL_TIM_PWM_Start+0x15a>
- 8005808:	687b      	ldr	r3, [r7, #4]
- 800580a:	681b      	ldr	r3, [r3, #0]
- 800580c:	4a17      	ldr	r2, [pc, #92]	@ (800586c <HAL_TIM_PWM_Start+0x1b4>)
- 800580e:	4293      	cmp	r3, r2
- 8005810:	d116      	bne.n	8005840 <HAL_TIM_PWM_Start+0x188>
-  {
-    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
- 8005812:	687b      	ldr	r3, [r7, #4]
- 8005814:	681b      	ldr	r3, [r3, #0]
- 8005816:	689b      	ldr	r3, [r3, #8]
- 8005818:	4a15      	ldr	r2, [pc, #84]	@ (8005870 <HAL_TIM_PWM_Start+0x1b8>)
- 800581a:	4013      	ands	r3, r2
- 800581c:	60fb      	str	r3, [r7, #12]
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 800581e:	68fb      	ldr	r3, [r7, #12]
- 8005820:	2b06      	cmp	r3, #6
- 8005822:	d016      	beq.n	8005852 <HAL_TIM_PWM_Start+0x19a>
- 8005824:	68fa      	ldr	r2, [r7, #12]
- 8005826:	2380      	movs	r3, #128	@ 0x80
- 8005828:	025b      	lsls	r3, r3, #9
- 800582a:	429a      	cmp	r2, r3
- 800582c:	d011      	beq.n	8005852 <HAL_TIM_PWM_Start+0x19a>
-    {
-      __HAL_TIM_ENABLE(htim);
- 800582e:	687b      	ldr	r3, [r7, #4]
- 8005830:	681b      	ldr	r3, [r3, #0]
- 8005832:	681a      	ldr	r2, [r3, #0]
- 8005834:	687b      	ldr	r3, [r7, #4]
- 8005836:	681b      	ldr	r3, [r3, #0]
- 8005838:	2101      	movs	r1, #1
- 800583a:	430a      	orrs	r2, r1
- 800583c:	601a      	str	r2, [r3, #0]
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 800583e:	e008      	b.n	8005852 <HAL_TIM_PWM_Start+0x19a>
-    }
-  }
-  else
-  {
-    __HAL_TIM_ENABLE(htim);
- 8005840:	687b      	ldr	r3, [r7, #4]
- 8005842:	681b      	ldr	r3, [r3, #0]
- 8005844:	681a      	ldr	r2, [r3, #0]
- 8005846:	687b      	ldr	r3, [r7, #4]
- 8005848:	681b      	ldr	r3, [r3, #0]
- 800584a:	2101      	movs	r1, #1
- 800584c:	430a      	orrs	r2, r1
- 800584e:	601a      	str	r2, [r3, #0]
- 8005850:	e000      	b.n	8005854 <HAL_TIM_PWM_Start+0x19c>
-    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
- 8005852:	46c0      	nop			@ (mov r8, r8)
-  }
-
-  /* Return function status */
-  return HAL_OK;
- 8005854:	2300      	movs	r3, #0
-}
- 8005856:	0018      	movs	r0, r3
- 8005858:	46bd      	mov	sp, r7
- 800585a:	b004      	add	sp, #16
- 800585c:	bd80      	pop	{r7, pc}
- 800585e:	46c0      	nop			@ (mov r8, r8)
- 8005860:	40012c00 	.word	0x40012c00
- 8005864:	40014400 	.word	0x40014400
- 8005868:	40014800 	.word	0x40014800
- 800586c:	40000400 	.word	0x40000400
- 8005870:	00010007 	.word	0x00010007
-
-08005874 <HAL_TIM_Encoder_Init>:
-  * @param  htim TIM Encoder Interface handle
-  * @param  sConfig TIM Encoder Interface configuration structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
-{
- 8005874:	b580      	push	{r7, lr}
- 8005876:	b086      	sub	sp, #24
- 8005878:	af00      	add	r7, sp, #0
- 800587a:	6078      	str	r0, [r7, #4]
- 800587c:	6039      	str	r1, [r7, #0]
-  uint32_t tmpsmcr;
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Check the TIM handle allocation */
-  if (htim == NULL)
- 800587e:	687b      	ldr	r3, [r7, #4]
- 8005880:	2b00      	cmp	r3, #0
- 8005882:	d101      	bne.n	8005888 <HAL_TIM_Encoder_Init+0x14>
-  {
-    return HAL_ERROR;
- 8005884:	2301      	movs	r3, #1
- 8005886:	e090      	b.n	80059aa <HAL_TIM_Encoder_Init+0x136>
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-  assert_param(IS_TIM_PERIOD(htim, htim->Init.Period));
-
-  if (htim->State == HAL_TIM_STATE_RESET)
- 8005888:	687b      	ldr	r3, [r7, #4]
- 800588a:	223d      	movs	r2, #61	@ 0x3d
- 800588c:	5c9b      	ldrb	r3, [r3, r2]
- 800588e:	b2db      	uxtb	r3, r3
- 8005890:	2b00      	cmp	r3, #0
- 8005892:	d107      	bne.n	80058a4 <HAL_TIM_Encoder_Init+0x30>
-  {
-    /* Allocate lock resource and initialize it */
-    htim->Lock = HAL_UNLOCKED;
- 8005894:	687b      	ldr	r3, [r7, #4]
- 8005896:	223c      	movs	r2, #60	@ 0x3c
- 8005898:	2100      	movs	r1, #0
- 800589a:	5499      	strb	r1, [r3, r2]
-    }
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    htim->Encoder_MspInitCallback(htim);
-#else
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_Encoder_MspInit(htim);
- 800589c:	687b      	ldr	r3, [r7, #4]
- 800589e:	0018      	movs	r0, r3
- 80058a0:	f7fe f978 	bl	8003b94 <HAL_TIM_Encoder_MspInit>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-  }
-
-  /* Set the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
- 80058a4:	687b      	ldr	r3, [r7, #4]
- 80058a6:	223d      	movs	r2, #61	@ 0x3d
- 80058a8:	2102      	movs	r1, #2
- 80058aa:	5499      	strb	r1, [r3, r2]
-
-  /* Reset the SMS and ECE bits */
-  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
- 80058ac:	687b      	ldr	r3, [r7, #4]
- 80058ae:	681b      	ldr	r3, [r3, #0]
- 80058b0:	689a      	ldr	r2, [r3, #8]
- 80058b2:	687b      	ldr	r3, [r7, #4]
- 80058b4:	681b      	ldr	r3, [r3, #0]
- 80058b6:	493f      	ldr	r1, [pc, #252]	@ (80059b4 <HAL_TIM_Encoder_Init+0x140>)
- 80058b8:	400a      	ands	r2, r1
- 80058ba:	609a      	str	r2, [r3, #8]
-
-  /* Configure the Time base in the Encoder Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
- 80058bc:	687b      	ldr	r3, [r7, #4]
- 80058be:	681a      	ldr	r2, [r3, #0]
- 80058c0:	687b      	ldr	r3, [r7, #4]
- 80058c2:	3304      	adds	r3, #4
- 80058c4:	0019      	movs	r1, r3
- 80058c6:	0010      	movs	r0, r2
- 80058c8:	f000 fc1e 	bl	8006108 <TIM_Base_SetConfig>
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
- 80058cc:	687b      	ldr	r3, [r7, #4]
- 80058ce:	681b      	ldr	r3, [r3, #0]
- 80058d0:	689b      	ldr	r3, [r3, #8]
- 80058d2:	617b      	str	r3, [r7, #20]
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = htim->Instance->CCMR1;
- 80058d4:	687b      	ldr	r3, [r7, #4]
- 80058d6:	681b      	ldr	r3, [r3, #0]
- 80058d8:	699b      	ldr	r3, [r3, #24]
- 80058da:	613b      	str	r3, [r7, #16]
-
-  /* Get the TIMx CCER register value */
-  tmpccer = htim->Instance->CCER;
- 80058dc:	687b      	ldr	r3, [r7, #4]
- 80058de:	681b      	ldr	r3, [r3, #0]
- 80058e0:	6a1b      	ldr	r3, [r3, #32]
- 80058e2:	60fb      	str	r3, [r7, #12]
-
-  /* Set the encoder Mode */
-  tmpsmcr |= sConfig->EncoderMode;
- 80058e4:	683b      	ldr	r3, [r7, #0]
- 80058e6:	681b      	ldr	r3, [r3, #0]
- 80058e8:	697a      	ldr	r2, [r7, #20]
- 80058ea:	4313      	orrs	r3, r2
- 80058ec:	617b      	str	r3, [r7, #20]
-
-  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
-  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
- 80058ee:	693b      	ldr	r3, [r7, #16]
- 80058f0:	4a31      	ldr	r2, [pc, #196]	@ (80059b8 <HAL_TIM_Encoder_Init+0x144>)
- 80058f2:	4013      	ands	r3, r2
- 80058f4:	613b      	str	r3, [r7, #16]
-  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
- 80058f6:	683b      	ldr	r3, [r7, #0]
- 80058f8:	689a      	ldr	r2, [r3, #8]
- 80058fa:	683b      	ldr	r3, [r7, #0]
- 80058fc:	699b      	ldr	r3, [r3, #24]
- 80058fe:	021b      	lsls	r3, r3, #8
- 8005900:	4313      	orrs	r3, r2
- 8005902:	693a      	ldr	r2, [r7, #16]
- 8005904:	4313      	orrs	r3, r2
- 8005906:	613b      	str	r3, [r7, #16]
-
-  /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
-  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
- 8005908:	693b      	ldr	r3, [r7, #16]
- 800590a:	4a2c      	ldr	r2, [pc, #176]	@ (80059bc <HAL_TIM_Encoder_Init+0x148>)
- 800590c:	4013      	ands	r3, r2
- 800590e:	613b      	str	r3, [r7, #16]
-  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
- 8005910:	693b      	ldr	r3, [r7, #16]
- 8005912:	4a2b      	ldr	r2, [pc, #172]	@ (80059c0 <HAL_TIM_Encoder_Init+0x14c>)
- 8005914:	4013      	ands	r3, r2
- 8005916:	613b      	str	r3, [r7, #16]
-  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
- 8005918:	683b      	ldr	r3, [r7, #0]
- 800591a:	68da      	ldr	r2, [r3, #12]
- 800591c:	683b      	ldr	r3, [r7, #0]
- 800591e:	69db      	ldr	r3, [r3, #28]
- 8005920:	021b      	lsls	r3, r3, #8
- 8005922:	4313      	orrs	r3, r2
- 8005924:	693a      	ldr	r2, [r7, #16]
- 8005926:	4313      	orrs	r3, r2
- 8005928:	613b      	str	r3, [r7, #16]
-  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
- 800592a:	683b      	ldr	r3, [r7, #0]
- 800592c:	691b      	ldr	r3, [r3, #16]
- 800592e:	011a      	lsls	r2, r3, #4
- 8005930:	683b      	ldr	r3, [r7, #0]
- 8005932:	6a1b      	ldr	r3, [r3, #32]
- 8005934:	031b      	lsls	r3, r3, #12
- 8005936:	4313      	orrs	r3, r2
- 8005938:	693a      	ldr	r2, [r7, #16]
- 800593a:	4313      	orrs	r3, r2
- 800593c:	613b      	str	r3, [r7, #16]
-
-  /* Set the TI1 and the TI2 Polarities */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
- 800593e:	68fb      	ldr	r3, [r7, #12]
- 8005940:	2222      	movs	r2, #34	@ 0x22
- 8005942:	4393      	bics	r3, r2
- 8005944:	60fb      	str	r3, [r7, #12]
-  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
- 8005946:	68fb      	ldr	r3, [r7, #12]
- 8005948:	2288      	movs	r2, #136	@ 0x88
- 800594a:	4393      	bics	r3, r2
- 800594c:	60fb      	str	r3, [r7, #12]
-  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
- 800594e:	683b      	ldr	r3, [r7, #0]
- 8005950:	685a      	ldr	r2, [r3, #4]
- 8005952:	683b      	ldr	r3, [r7, #0]
- 8005954:	695b      	ldr	r3, [r3, #20]
- 8005956:	011b      	lsls	r3, r3, #4
- 8005958:	4313      	orrs	r3, r2
- 800595a:	68fa      	ldr	r2, [r7, #12]
- 800595c:	4313      	orrs	r3, r2
- 800595e:	60fb      	str	r3, [r7, #12]
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
- 8005960:	687b      	ldr	r3, [r7, #4]
- 8005962:	681b      	ldr	r3, [r3, #0]
- 8005964:	697a      	ldr	r2, [r7, #20]
- 8005966:	609a      	str	r2, [r3, #8]
-
-  /* Write to TIMx CCMR1 */
-  htim->Instance->CCMR1 = tmpccmr1;
- 8005968:	687b      	ldr	r3, [r7, #4]
- 800596a:	681b      	ldr	r3, [r3, #0]
- 800596c:	693a      	ldr	r2, [r7, #16]
- 800596e:	619a      	str	r2, [r3, #24]
-
-  /* Write to TIMx CCER */
-  htim->Instance->CCER = tmpccer;
- 8005970:	687b      	ldr	r3, [r7, #4]
- 8005972:	681b      	ldr	r3, [r3, #0]
- 8005974:	68fa      	ldr	r2, [r7, #12]
- 8005976:	621a      	str	r2, [r3, #32]
-
-  /* Initialize the DMA burst operation state */
-  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
- 8005978:	687b      	ldr	r3, [r7, #4]
- 800597a:	2248      	movs	r2, #72	@ 0x48
- 800597c:	2101      	movs	r1, #1
- 800597e:	5499      	strb	r1, [r3, r2]
-
-  /* Set the TIM channels state */
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- 8005980:	687b      	ldr	r3, [r7, #4]
- 8005982:	223e      	movs	r2, #62	@ 0x3e
- 8005984:	2101      	movs	r1, #1
- 8005986:	5499      	strb	r1, [r3, r2]
-  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- 8005988:	687b      	ldr	r3, [r7, #4]
- 800598a:	223f      	movs	r2, #63	@ 0x3f
- 800598c:	2101      	movs	r1, #1
- 800598e:	5499      	strb	r1, [r3, r2]
-  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
- 8005990:	687b      	ldr	r3, [r7, #4]
- 8005992:	2244      	movs	r2, #68	@ 0x44
- 8005994:	2101      	movs	r1, #1
- 8005996:	5499      	strb	r1, [r3, r2]
-  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
- 8005998:	687b      	ldr	r3, [r7, #4]
- 800599a:	2245      	movs	r2, #69	@ 0x45
- 800599c:	2101      	movs	r1, #1
- 800599e:	5499      	strb	r1, [r3, r2]
-
-  /* Initialize the TIM state*/
-  htim->State = HAL_TIM_STATE_READY;
- 80059a0:	687b      	ldr	r3, [r7, #4]
- 80059a2:	223d      	movs	r2, #61	@ 0x3d
- 80059a4:	2101      	movs	r1, #1
- 80059a6:	5499      	strb	r1, [r3, r2]
-
-  return HAL_OK;
- 80059a8:	2300      	movs	r3, #0
-}
- 80059aa:	0018      	movs	r0, r3
- 80059ac:	46bd      	mov	sp, r7
- 80059ae:	b006      	add	sp, #24
- 80059b0:	bd80      	pop	{r7, pc}
- 80059b2:	46c0      	nop			@ (mov r8, r8)
- 80059b4:	fffebff8 	.word	0xfffebff8
- 80059b8:	fffffcfc 	.word	0xfffffcfc
- 80059bc:	fffff3f3 	.word	0xfffff3f3
- 80059c0:	ffff0f0f 	.word	0xffff0f0f
-
-080059c4 <HAL_TIM_Encoder_Start>:
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
- 80059c4:	b590      	push	{r4, r7, lr}
- 80059c6:	b085      	sub	sp, #20
- 80059c8:	af00      	add	r7, sp, #0
- 80059ca:	6078      	str	r0, [r7, #4]
- 80059cc:	6039      	str	r1, [r7, #0]
-  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
- 80059ce:	200f      	movs	r0, #15
- 80059d0:	183b      	adds	r3, r7, r0
- 80059d2:	687a      	ldr	r2, [r7, #4]
- 80059d4:	213e      	movs	r1, #62	@ 0x3e
- 80059d6:	5c52      	ldrb	r2, [r2, r1]
- 80059d8:	701a      	strb	r2, [r3, #0]
-  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
- 80059da:	230e      	movs	r3, #14
- 80059dc:	18fb      	adds	r3, r7, r3
- 80059de:	687a      	ldr	r2, [r7, #4]
- 80059e0:	213f      	movs	r1, #63	@ 0x3f
- 80059e2:	5c52      	ldrb	r2, [r2, r1]
- 80059e4:	701a      	strb	r2, [r3, #0]
-  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
- 80059e6:	240d      	movs	r4, #13
- 80059e8:	193b      	adds	r3, r7, r4
- 80059ea:	687a      	ldr	r2, [r7, #4]
- 80059ec:	2144      	movs	r1, #68	@ 0x44
- 80059ee:	5c52      	ldrb	r2, [r2, r1]
- 80059f0:	701a      	strb	r2, [r3, #0]
-  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
- 80059f2:	230c      	movs	r3, #12
- 80059f4:	18fb      	adds	r3, r7, r3
- 80059f6:	687a      	ldr	r2, [r7, #4]
- 80059f8:	2145      	movs	r1, #69	@ 0x45
- 80059fa:	5c52      	ldrb	r2, [r2, r1]
- 80059fc:	701a      	strb	r2, [r3, #0]
-
-  /* Check the parameters */
-  assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
-
-  /* Set the TIM channel(s) state */
-  if (Channel == TIM_CHANNEL_1)
- 80059fe:	683b      	ldr	r3, [r7, #0]
- 8005a00:	2b00      	cmp	r3, #0
- 8005a02:	d112      	bne.n	8005a2a <HAL_TIM_Encoder_Start+0x66>
-  {
-    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- 8005a04:	183b      	adds	r3, r7, r0
- 8005a06:	781b      	ldrb	r3, [r3, #0]
- 8005a08:	2b01      	cmp	r3, #1
- 8005a0a:	d103      	bne.n	8005a14 <HAL_TIM_Encoder_Start+0x50>
-        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
- 8005a0c:	193b      	adds	r3, r7, r4
- 8005a0e:	781b      	ldrb	r3, [r3, #0]
- 8005a10:	2b01      	cmp	r3, #1
- 8005a12:	d001      	beq.n	8005a18 <HAL_TIM_Encoder_Start+0x54>
-    {
-      return HAL_ERROR;
- 8005a14:	2301      	movs	r3, #1
- 8005a16:	e075      	b.n	8005b04 <HAL_TIM_Encoder_Start+0x140>
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- 8005a18:	687b      	ldr	r3, [r7, #4]
- 8005a1a:	223e      	movs	r2, #62	@ 0x3e
- 8005a1c:	2102      	movs	r1, #2
- 8005a1e:	5499      	strb	r1, [r3, r2]
-      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- 8005a20:	687b      	ldr	r3, [r7, #4]
- 8005a22:	2244      	movs	r2, #68	@ 0x44
- 8005a24:	2102      	movs	r1, #2
- 8005a26:	5499      	strb	r1, [r3, r2]
- 8005a28:	e03d      	b.n	8005aa6 <HAL_TIM_Encoder_Start+0xe2>
-    }
-  }
-  else if (Channel == TIM_CHANNEL_2)
- 8005a2a:	683b      	ldr	r3, [r7, #0]
- 8005a2c:	2b04      	cmp	r3, #4
- 8005a2e:	d114      	bne.n	8005a5a <HAL_TIM_Encoder_Start+0x96>
-  {
-    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- 8005a30:	230e      	movs	r3, #14
- 8005a32:	18fb      	adds	r3, r7, r3
- 8005a34:	781b      	ldrb	r3, [r3, #0]
- 8005a36:	2b01      	cmp	r3, #1
- 8005a38:	d104      	bne.n	8005a44 <HAL_TIM_Encoder_Start+0x80>
-        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- 8005a3a:	230c      	movs	r3, #12
- 8005a3c:	18fb      	adds	r3, r7, r3
- 8005a3e:	781b      	ldrb	r3, [r3, #0]
- 8005a40:	2b01      	cmp	r3, #1
- 8005a42:	d001      	beq.n	8005a48 <HAL_TIM_Encoder_Start+0x84>
-    {
-      return HAL_ERROR;
- 8005a44:	2301      	movs	r3, #1
- 8005a46:	e05d      	b.n	8005b04 <HAL_TIM_Encoder_Start+0x140>
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- 8005a48:	687b      	ldr	r3, [r7, #4]
- 8005a4a:	223f      	movs	r2, #63	@ 0x3f
- 8005a4c:	2102      	movs	r1, #2
- 8005a4e:	5499      	strb	r1, [r3, r2]
-      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- 8005a50:	687b      	ldr	r3, [r7, #4]
- 8005a52:	2245      	movs	r2, #69	@ 0x45
- 8005a54:	2102      	movs	r1, #2
- 8005a56:	5499      	strb	r1, [r3, r2]
- 8005a58:	e025      	b.n	8005aa6 <HAL_TIM_Encoder_Start+0xe2>
-    }
-  }
-  else
-  {
-    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- 8005a5a:	230f      	movs	r3, #15
- 8005a5c:	18fb      	adds	r3, r7, r3
- 8005a5e:	781b      	ldrb	r3, [r3, #0]
- 8005a60:	2b01      	cmp	r3, #1
- 8005a62:	d10e      	bne.n	8005a82 <HAL_TIM_Encoder_Start+0xbe>
-        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
- 8005a64:	230e      	movs	r3, #14
- 8005a66:	18fb      	adds	r3, r7, r3
- 8005a68:	781b      	ldrb	r3, [r3, #0]
- 8005a6a:	2b01      	cmp	r3, #1
- 8005a6c:	d109      	bne.n	8005a82 <HAL_TIM_Encoder_Start+0xbe>
-        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
- 8005a6e:	230d      	movs	r3, #13
- 8005a70:	18fb      	adds	r3, r7, r3
- 8005a72:	781b      	ldrb	r3, [r3, #0]
- 8005a74:	2b01      	cmp	r3, #1
- 8005a76:	d104      	bne.n	8005a82 <HAL_TIM_Encoder_Start+0xbe>
-        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
- 8005a78:	230c      	movs	r3, #12
- 8005a7a:	18fb      	adds	r3, r7, r3
- 8005a7c:	781b      	ldrb	r3, [r3, #0]
- 8005a7e:	2b01      	cmp	r3, #1
- 8005a80:	d001      	beq.n	8005a86 <HAL_TIM_Encoder_Start+0xc2>
-    {
-      return HAL_ERROR;
- 8005a82:	2301      	movs	r3, #1
- 8005a84:	e03e      	b.n	8005b04 <HAL_TIM_Encoder_Start+0x140>
-    }
-    else
-    {
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- 8005a86:	687b      	ldr	r3, [r7, #4]
- 8005a88:	223e      	movs	r2, #62	@ 0x3e
- 8005a8a:	2102      	movs	r1, #2
- 8005a8c:	5499      	strb	r1, [r3, r2]
-      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- 8005a8e:	687b      	ldr	r3, [r7, #4]
- 8005a90:	223f      	movs	r2, #63	@ 0x3f
- 8005a92:	2102      	movs	r1, #2
- 8005a94:	5499      	strb	r1, [r3, r2]
-      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
- 8005a96:	687b      	ldr	r3, [r7, #4]
- 8005a98:	2244      	movs	r2, #68	@ 0x44
- 8005a9a:	2102      	movs	r1, #2
- 8005a9c:	5499      	strb	r1, [r3, r2]
-      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
- 8005a9e:	687b      	ldr	r3, [r7, #4]
- 8005aa0:	2245      	movs	r2, #69	@ 0x45
- 8005aa2:	2102      	movs	r1, #2
- 8005aa4:	5499      	strb	r1, [r3, r2]
-    }
-  }
-
-  /* Enable the encoder interface channels */
-  switch (Channel)
- 8005aa6:	683b      	ldr	r3, [r7, #0]
- 8005aa8:	2b00      	cmp	r3, #0
- 8005aaa:	d003      	beq.n	8005ab4 <HAL_TIM_Encoder_Start+0xf0>
- 8005aac:	683b      	ldr	r3, [r7, #0]
- 8005aae:	2b04      	cmp	r3, #4
- 8005ab0:	d008      	beq.n	8005ac4 <HAL_TIM_Encoder_Start+0x100>
- 8005ab2:	e00f      	b.n	8005ad4 <HAL_TIM_Encoder_Start+0x110>
-  {
-    case TIM_CHANNEL_1:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- 8005ab4:	687b      	ldr	r3, [r7, #4]
- 8005ab6:	681b      	ldr	r3, [r3, #0]
- 8005ab8:	2201      	movs	r2, #1
- 8005aba:	2100      	movs	r1, #0
- 8005abc:	0018      	movs	r0, r3
- 8005abe:	f000 fed7 	bl	8006870 <TIM_CCxChannelCmd>
-      break;
- 8005ac2:	e016      	b.n	8005af2 <HAL_TIM_Encoder_Start+0x12e>
-    }
-
-    case TIM_CHANNEL_2:
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- 8005ac4:	687b      	ldr	r3, [r7, #4]
- 8005ac6:	681b      	ldr	r3, [r3, #0]
- 8005ac8:	2201      	movs	r2, #1
- 8005aca:	2104      	movs	r1, #4
- 8005acc:	0018      	movs	r0, r3
- 8005ace:	f000 fecf 	bl	8006870 <TIM_CCxChannelCmd>
-      break;
- 8005ad2:	e00e      	b.n	8005af2 <HAL_TIM_Encoder_Start+0x12e>
-    }
-
-    default :
-    {
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
- 8005ad4:	687b      	ldr	r3, [r7, #4]
- 8005ad6:	681b      	ldr	r3, [r3, #0]
- 8005ad8:	2201      	movs	r2, #1
- 8005ada:	2100      	movs	r1, #0
- 8005adc:	0018      	movs	r0, r3
- 8005ade:	f000 fec7 	bl	8006870 <TIM_CCxChannelCmd>
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
- 8005ae2:	687b      	ldr	r3, [r7, #4]
- 8005ae4:	681b      	ldr	r3, [r3, #0]
- 8005ae6:	2201      	movs	r2, #1
- 8005ae8:	2104      	movs	r1, #4
- 8005aea:	0018      	movs	r0, r3
- 8005aec:	f000 fec0 	bl	8006870 <TIM_CCxChannelCmd>
-      break;
- 8005af0:	46c0      	nop			@ (mov r8, r8)
-    }
-  }
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
- 8005af2:	687b      	ldr	r3, [r7, #4]
- 8005af4:	681b      	ldr	r3, [r3, #0]
- 8005af6:	681a      	ldr	r2, [r3, #0]
- 8005af8:	687b      	ldr	r3, [r7, #4]
- 8005afa:	681b      	ldr	r3, [r3, #0]
- 8005afc:	2101      	movs	r1, #1
- 8005afe:	430a      	orrs	r2, r1
- 8005b00:	601a      	str	r2, [r3, #0]
-
-  /* Return function status */
-  return HAL_OK;
- 8005b02:	2300      	movs	r3, #0
-}
- 8005b04:	0018      	movs	r0, r3
- 8005b06:	46bd      	mov	sp, r7
- 8005b08:	b005      	add	sp, #20
- 8005b0a:	bd90      	pop	{r4, r7, pc}
-
-08005b0c <HAL_TIM_IRQHandler>:
-  * @brief  This function handles TIM interrupts requests.
-  * @param  htim TIM  handle
-  * @retval None
-  */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
- 8005b0c:	b580      	push	{r7, lr}
- 8005b0e:	b084      	sub	sp, #16
- 8005b10:	af00      	add	r7, sp, #0
- 8005b12:	6078      	str	r0, [r7, #4]
-  uint32_t itsource = htim->Instance->DIER;
- 8005b14:	687b      	ldr	r3, [r7, #4]
- 8005b16:	681b      	ldr	r3, [r3, #0]
- 8005b18:	68db      	ldr	r3, [r3, #12]
- 8005b1a:	60fb      	str	r3, [r7, #12]
-  uint32_t itflag   = htim->Instance->SR;
- 8005b1c:	687b      	ldr	r3, [r7, #4]
- 8005b1e:	681b      	ldr	r3, [r3, #0]
- 8005b20:	691b      	ldr	r3, [r3, #16]
- 8005b22:	60bb      	str	r3, [r7, #8]
-
-  /* Capture compare 1 event */
-  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
- 8005b24:	68bb      	ldr	r3, [r7, #8]
- 8005b26:	2202      	movs	r2, #2
- 8005b28:	4013      	ands	r3, r2
- 8005b2a:	d021      	beq.n	8005b70 <HAL_TIM_IRQHandler+0x64>
-  {
-    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
- 8005b2c:	68fb      	ldr	r3, [r7, #12]
- 8005b2e:	2202      	movs	r2, #2
- 8005b30:	4013      	ands	r3, r2
- 8005b32:	d01d      	beq.n	8005b70 <HAL_TIM_IRQHandler+0x64>
-    {
-      {
-        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
- 8005b34:	687b      	ldr	r3, [r7, #4]
- 8005b36:	681b      	ldr	r3, [r3, #0]
- 8005b38:	2203      	movs	r2, #3
- 8005b3a:	4252      	negs	r2, r2
- 8005b3c:	611a      	str	r2, [r3, #16]
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
- 8005b3e:	687b      	ldr	r3, [r7, #4]
- 8005b40:	2201      	movs	r2, #1
- 8005b42:	771a      	strb	r2, [r3, #28]
-
-        /* Input capture event */
-        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
- 8005b44:	687b      	ldr	r3, [r7, #4]
- 8005b46:	681b      	ldr	r3, [r3, #0]
- 8005b48:	699b      	ldr	r3, [r3, #24]
- 8005b4a:	2203      	movs	r2, #3
- 8005b4c:	4013      	ands	r3, r2
- 8005b4e:	d004      	beq.n	8005b5a <HAL_TIM_IRQHandler+0x4e>
-        {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-          htim->IC_CaptureCallback(htim);
-#else
-          HAL_TIM_IC_CaptureCallback(htim);
- 8005b50:	687b      	ldr	r3, [r7, #4]
- 8005b52:	0018      	movs	r0, r3
- 8005b54:	f000 fac0 	bl	80060d8 <HAL_TIM_IC_CaptureCallback>
- 8005b58:	e007      	b.n	8005b6a <HAL_TIM_IRQHandler+0x5e>
-        {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-          htim->OC_DelayElapsedCallback(htim);
-          htim->PWM_PulseFinishedCallback(htim);
-#else
-          HAL_TIM_OC_DelayElapsedCallback(htim);
- 8005b5a:	687b      	ldr	r3, [r7, #4]
- 8005b5c:	0018      	movs	r0, r3
- 8005b5e:	f000 fab3 	bl	80060c8 <HAL_TIM_OC_DelayElapsedCallback>
-          HAL_TIM_PWM_PulseFinishedCallback(htim);
- 8005b62:	687b      	ldr	r3, [r7, #4]
- 8005b64:	0018      	movs	r0, r3
- 8005b66:	f000 fabf 	bl	80060e8 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-        }
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8005b6a:	687b      	ldr	r3, [r7, #4]
- 8005b6c:	2200      	movs	r2, #0
- 8005b6e:	771a      	strb	r2, [r3, #28]
-      }
-    }
-  }
-  /* Capture compare 2 event */
-  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
- 8005b70:	68bb      	ldr	r3, [r7, #8]
- 8005b72:	2204      	movs	r2, #4
- 8005b74:	4013      	ands	r3, r2
- 8005b76:	d022      	beq.n	8005bbe <HAL_TIM_IRQHandler+0xb2>
-  {
-    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
- 8005b78:	68fb      	ldr	r3, [r7, #12]
- 8005b7a:	2204      	movs	r2, #4
- 8005b7c:	4013      	ands	r3, r2
- 8005b7e:	d01e      	beq.n	8005bbe <HAL_TIM_IRQHandler+0xb2>
-    {
-      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
- 8005b80:	687b      	ldr	r3, [r7, #4]
- 8005b82:	681b      	ldr	r3, [r3, #0]
- 8005b84:	2205      	movs	r2, #5
- 8005b86:	4252      	negs	r2, r2
- 8005b88:	611a      	str	r2, [r3, #16]
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
- 8005b8a:	687b      	ldr	r3, [r7, #4]
- 8005b8c:	2202      	movs	r2, #2
- 8005b8e:	771a      	strb	r2, [r3, #28]
-      /* Input capture event */
-      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
- 8005b90:	687b      	ldr	r3, [r7, #4]
- 8005b92:	681b      	ldr	r3, [r3, #0]
- 8005b94:	699a      	ldr	r2, [r3, #24]
- 8005b96:	23c0      	movs	r3, #192	@ 0xc0
- 8005b98:	009b      	lsls	r3, r3, #2
- 8005b9a:	4013      	ands	r3, r2
- 8005b9c:	d004      	beq.n	8005ba8 <HAL_TIM_IRQHandler+0x9c>
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->IC_CaptureCallback(htim);
-#else
-        HAL_TIM_IC_CaptureCallback(htim);
- 8005b9e:	687b      	ldr	r3, [r7, #4]
- 8005ba0:	0018      	movs	r0, r3
- 8005ba2:	f000 fa99 	bl	80060d8 <HAL_TIM_IC_CaptureCallback>
- 8005ba6:	e007      	b.n	8005bb8 <HAL_TIM_IRQHandler+0xac>
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->OC_DelayElapsedCallback(htim);
-        htim->PWM_PulseFinishedCallback(htim);
-#else
-        HAL_TIM_OC_DelayElapsedCallback(htim);
- 8005ba8:	687b      	ldr	r3, [r7, #4]
- 8005baa:	0018      	movs	r0, r3
- 8005bac:	f000 fa8c 	bl	80060c8 <HAL_TIM_OC_DelayElapsedCallback>
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
- 8005bb0:	687b      	ldr	r3, [r7, #4]
- 8005bb2:	0018      	movs	r0, r3
- 8005bb4:	f000 fa98 	bl	80060e8 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8005bb8:	687b      	ldr	r3, [r7, #4]
- 8005bba:	2200      	movs	r2, #0
- 8005bbc:	771a      	strb	r2, [r3, #28]
-    }
-  }
-  /* Capture compare 3 event */
-  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
- 8005bbe:	68bb      	ldr	r3, [r7, #8]
- 8005bc0:	2208      	movs	r2, #8
- 8005bc2:	4013      	ands	r3, r2
- 8005bc4:	d021      	beq.n	8005c0a <HAL_TIM_IRQHandler+0xfe>
-  {
-    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
- 8005bc6:	68fb      	ldr	r3, [r7, #12]
- 8005bc8:	2208      	movs	r2, #8
- 8005bca:	4013      	ands	r3, r2
- 8005bcc:	d01d      	beq.n	8005c0a <HAL_TIM_IRQHandler+0xfe>
-    {
-      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
- 8005bce:	687b      	ldr	r3, [r7, #4]
- 8005bd0:	681b      	ldr	r3, [r3, #0]
- 8005bd2:	2209      	movs	r2, #9
- 8005bd4:	4252      	negs	r2, r2
- 8005bd6:	611a      	str	r2, [r3, #16]
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
- 8005bd8:	687b      	ldr	r3, [r7, #4]
- 8005bda:	2204      	movs	r2, #4
- 8005bdc:	771a      	strb	r2, [r3, #28]
-      /* Input capture event */
-      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
- 8005bde:	687b      	ldr	r3, [r7, #4]
- 8005be0:	681b      	ldr	r3, [r3, #0]
- 8005be2:	69db      	ldr	r3, [r3, #28]
- 8005be4:	2203      	movs	r2, #3
- 8005be6:	4013      	ands	r3, r2
- 8005be8:	d004      	beq.n	8005bf4 <HAL_TIM_IRQHandler+0xe8>
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->IC_CaptureCallback(htim);
-#else
-        HAL_TIM_IC_CaptureCallback(htim);
- 8005bea:	687b      	ldr	r3, [r7, #4]
- 8005bec:	0018      	movs	r0, r3
- 8005bee:	f000 fa73 	bl	80060d8 <HAL_TIM_IC_CaptureCallback>
- 8005bf2:	e007      	b.n	8005c04 <HAL_TIM_IRQHandler+0xf8>
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->OC_DelayElapsedCallback(htim);
-        htim->PWM_PulseFinishedCallback(htim);
-#else
-        HAL_TIM_OC_DelayElapsedCallback(htim);
- 8005bf4:	687b      	ldr	r3, [r7, #4]
- 8005bf6:	0018      	movs	r0, r3
- 8005bf8:	f000 fa66 	bl	80060c8 <HAL_TIM_OC_DelayElapsedCallback>
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
- 8005bfc:	687b      	ldr	r3, [r7, #4]
- 8005bfe:	0018      	movs	r0, r3
- 8005c00:	f000 fa72 	bl	80060e8 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8005c04:	687b      	ldr	r3, [r7, #4]
- 8005c06:	2200      	movs	r2, #0
- 8005c08:	771a      	strb	r2, [r3, #28]
-    }
-  }
-  /* Capture compare 4 event */
-  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
- 8005c0a:	68bb      	ldr	r3, [r7, #8]
- 8005c0c:	2210      	movs	r2, #16
- 8005c0e:	4013      	ands	r3, r2
- 8005c10:	d022      	beq.n	8005c58 <HAL_TIM_IRQHandler+0x14c>
-  {
-    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
- 8005c12:	68fb      	ldr	r3, [r7, #12]
- 8005c14:	2210      	movs	r2, #16
- 8005c16:	4013      	ands	r3, r2
- 8005c18:	d01e      	beq.n	8005c58 <HAL_TIM_IRQHandler+0x14c>
-    {
-      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
- 8005c1a:	687b      	ldr	r3, [r7, #4]
- 8005c1c:	681b      	ldr	r3, [r3, #0]
- 8005c1e:	2211      	movs	r2, #17
- 8005c20:	4252      	negs	r2, r2
- 8005c22:	611a      	str	r2, [r3, #16]
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
- 8005c24:	687b      	ldr	r3, [r7, #4]
- 8005c26:	2208      	movs	r2, #8
- 8005c28:	771a      	strb	r2, [r3, #28]
-      /* Input capture event */
-      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
- 8005c2a:	687b      	ldr	r3, [r7, #4]
- 8005c2c:	681b      	ldr	r3, [r3, #0]
- 8005c2e:	69da      	ldr	r2, [r3, #28]
- 8005c30:	23c0      	movs	r3, #192	@ 0xc0
- 8005c32:	009b      	lsls	r3, r3, #2
- 8005c34:	4013      	ands	r3, r2
- 8005c36:	d004      	beq.n	8005c42 <HAL_TIM_IRQHandler+0x136>
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->IC_CaptureCallback(htim);
-#else
-        HAL_TIM_IC_CaptureCallback(htim);
- 8005c38:	687b      	ldr	r3, [r7, #4]
- 8005c3a:	0018      	movs	r0, r3
- 8005c3c:	f000 fa4c 	bl	80060d8 <HAL_TIM_IC_CaptureCallback>
- 8005c40:	e007      	b.n	8005c52 <HAL_TIM_IRQHandler+0x146>
-      {
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-        htim->OC_DelayElapsedCallback(htim);
-        htim->PWM_PulseFinishedCallback(htim);
-#else
-        HAL_TIM_OC_DelayElapsedCallback(htim);
- 8005c42:	687b      	ldr	r3, [r7, #4]
- 8005c44:	0018      	movs	r0, r3
- 8005c46:	f000 fa3f 	bl	80060c8 <HAL_TIM_OC_DelayElapsedCallback>
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
- 8005c4a:	687b      	ldr	r3, [r7, #4]
- 8005c4c:	0018      	movs	r0, r3
- 8005c4e:	f000 fa4b 	bl	80060e8 <HAL_TIM_PWM_PulseFinishedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
- 8005c52:	687b      	ldr	r3, [r7, #4]
- 8005c54:	2200      	movs	r2, #0
- 8005c56:	771a      	strb	r2, [r3, #28]
-    }
-  }
-  /* TIM Update event */
-  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
- 8005c58:	68bb      	ldr	r3, [r7, #8]
- 8005c5a:	2201      	movs	r2, #1
- 8005c5c:	4013      	ands	r3, r2
- 8005c5e:	d00c      	beq.n	8005c7a <HAL_TIM_IRQHandler+0x16e>
-  {
-    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
- 8005c60:	68fb      	ldr	r3, [r7, #12]
- 8005c62:	2201      	movs	r2, #1
- 8005c64:	4013      	ands	r3, r2
- 8005c66:	d008      	beq.n	8005c7a <HAL_TIM_IRQHandler+0x16e>
-    {
-      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
- 8005c68:	687b      	ldr	r3, [r7, #4]
- 8005c6a:	681b      	ldr	r3, [r3, #0]
- 8005c6c:	2202      	movs	r2, #2
- 8005c6e:	4252      	negs	r2, r2
- 8005c70:	611a      	str	r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-      htim->PeriodElapsedCallback(htim);
-#else
-      HAL_TIM_PeriodElapsedCallback(htim);
- 8005c72:	687b      	ldr	r3, [r7, #4]
- 8005c74:	0018      	movs	r0, r3
- 8005c76:	f7fb fde1 	bl	800183c <HAL_TIM_PeriodElapsedCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-    }
-  }
-  /* TIM Break input event */
-  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
- 8005c7a:	68bb      	ldr	r3, [r7, #8]
- 8005c7c:	2280      	movs	r2, #128	@ 0x80
- 8005c7e:	4013      	ands	r3, r2
- 8005c80:	d104      	bne.n	8005c8c <HAL_TIM_IRQHandler+0x180>
-      ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
- 8005c82:	68ba      	ldr	r2, [r7, #8]
- 8005c84:	2380      	movs	r3, #128	@ 0x80
- 8005c86:	019b      	lsls	r3, r3, #6
- 8005c88:	4013      	ands	r3, r2
-  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
- 8005c8a:	d00b      	beq.n	8005ca4 <HAL_TIM_IRQHandler+0x198>
-  {
-    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
- 8005c8c:	68fb      	ldr	r3, [r7, #12]
- 8005c8e:	2280      	movs	r2, #128	@ 0x80
- 8005c90:	4013      	ands	r3, r2
- 8005c92:	d007      	beq.n	8005ca4 <HAL_TIM_IRQHandler+0x198>
-    {
-      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
- 8005c94:	687b      	ldr	r3, [r7, #4]
- 8005c96:	681b      	ldr	r3, [r3, #0]
- 8005c98:	4a1e      	ldr	r2, [pc, #120]	@ (8005d14 <HAL_TIM_IRQHandler+0x208>)
- 8005c9a:	611a      	str	r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-      htim->BreakCallback(htim);
-#else
-      HAL_TIMEx_BreakCallback(htim);
- 8005c9c:	687b      	ldr	r3, [r7, #4]
- 8005c9e:	0018      	movs	r0, r3
- 8005ca0:	f000 ff16 	bl	8006ad0 <HAL_TIMEx_BreakCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-    }
-  }
-  /* TIM Break2 input event */
-  if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
- 8005ca4:	68ba      	ldr	r2, [r7, #8]
- 8005ca6:	2380      	movs	r3, #128	@ 0x80
- 8005ca8:	005b      	lsls	r3, r3, #1
- 8005caa:	4013      	ands	r3, r2
- 8005cac:	d00b      	beq.n	8005cc6 <HAL_TIM_IRQHandler+0x1ba>
-  {
-    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
- 8005cae:	68fb      	ldr	r3, [r7, #12]
- 8005cb0:	2280      	movs	r2, #128	@ 0x80
- 8005cb2:	4013      	ands	r3, r2
- 8005cb4:	d007      	beq.n	8005cc6 <HAL_TIM_IRQHandler+0x1ba>
-    {
-      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
- 8005cb6:	687b      	ldr	r3, [r7, #4]
- 8005cb8:	681b      	ldr	r3, [r3, #0]
- 8005cba:	4a17      	ldr	r2, [pc, #92]	@ (8005d18 <HAL_TIM_IRQHandler+0x20c>)
- 8005cbc:	611a      	str	r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-      htim->Break2Callback(htim);
-#else
-      HAL_TIMEx_Break2Callback(htim);
- 8005cbe:	687b      	ldr	r3, [r7, #4]
- 8005cc0:	0018      	movs	r0, r3
- 8005cc2:	f000 ff0d 	bl	8006ae0 <HAL_TIMEx_Break2Callback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-    }
-  }
-  /* TIM Trigger detection event */
-  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
- 8005cc6:	68bb      	ldr	r3, [r7, #8]
- 8005cc8:	2240      	movs	r2, #64	@ 0x40
- 8005cca:	4013      	ands	r3, r2
- 8005ccc:	d00c      	beq.n	8005ce8 <HAL_TIM_IRQHandler+0x1dc>
-  {
-    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
- 8005cce:	68fb      	ldr	r3, [r7, #12]
- 8005cd0:	2240      	movs	r2, #64	@ 0x40
- 8005cd2:	4013      	ands	r3, r2
- 8005cd4:	d008      	beq.n	8005ce8 <HAL_TIM_IRQHandler+0x1dc>
-    {
-      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
- 8005cd6:	687b      	ldr	r3, [r7, #4]
- 8005cd8:	681b      	ldr	r3, [r3, #0]
- 8005cda:	2241      	movs	r2, #65	@ 0x41
- 8005cdc:	4252      	negs	r2, r2
- 8005cde:	611a      	str	r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-      htim->TriggerCallback(htim);
-#else
-      HAL_TIM_TriggerCallback(htim);
- 8005ce0:	687b      	ldr	r3, [r7, #4]
- 8005ce2:	0018      	movs	r0, r3
- 8005ce4:	f000 fa08 	bl	80060f8 <HAL_TIM_TriggerCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-    }
-  }
-  /* TIM commutation event */
-  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
- 8005ce8:	68bb      	ldr	r3, [r7, #8]
- 8005cea:	2220      	movs	r2, #32
- 8005cec:	4013      	ands	r3, r2
- 8005cee:	d00c      	beq.n	8005d0a <HAL_TIM_IRQHandler+0x1fe>
-  {
-    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
- 8005cf0:	68fb      	ldr	r3, [r7, #12]
- 8005cf2:	2220      	movs	r2, #32
- 8005cf4:	4013      	ands	r3, r2
- 8005cf6:	d008      	beq.n	8005d0a <HAL_TIM_IRQHandler+0x1fe>
-    {
-      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
- 8005cf8:	687b      	ldr	r3, [r7, #4]
- 8005cfa:	681b      	ldr	r3, [r3, #0]
- 8005cfc:	2221      	movs	r2, #33	@ 0x21
- 8005cfe:	4252      	negs	r2, r2
- 8005d00:	611a      	str	r2, [r3, #16]
-#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
-      htim->CommutationCallback(htim);
-#else
-      HAL_TIMEx_CommutCallback(htim);
- 8005d02:	687b      	ldr	r3, [r7, #4]
- 8005d04:	0018      	movs	r0, r3
- 8005d06:	f000 fedb 	bl	8006ac0 <HAL_TIMEx_CommutCallback>
-#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
-    }
-  }
-}
- 8005d0a:	46c0      	nop			@ (mov r8, r8)
- 8005d0c:	46bd      	mov	sp, r7
- 8005d0e:	b004      	add	sp, #16
- 8005d10:	bd80      	pop	{r7, pc}
- 8005d12:	46c0      	nop			@ (mov r8, r8)
- 8005d14:	ffffdf7f 	.word	0xffffdf7f
- 8005d18:	fffffeff 	.word	0xfffffeff
-
-08005d1c <HAL_TIM_PWM_ConfigChannel>:
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
-                                            const TIM_OC_InitTypeDef *sConfig,
-                                            uint32_t Channel)
-{
- 8005d1c:	b580      	push	{r7, lr}
- 8005d1e:	b086      	sub	sp, #24
- 8005d20:	af00      	add	r7, sp, #0
- 8005d22:	60f8      	str	r0, [r7, #12]
- 8005d24:	60b9      	str	r1, [r7, #8]
- 8005d26:	607a      	str	r2, [r7, #4]
-  HAL_StatusTypeDef status = HAL_OK;
- 8005d28:	2317      	movs	r3, #23
- 8005d2a:	18fb      	adds	r3, r7, r3
- 8005d2c:	2200      	movs	r2, #0
- 8005d2e:	701a      	strb	r2, [r3, #0]
-  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
- 8005d30:	68fb      	ldr	r3, [r7, #12]
- 8005d32:	223c      	movs	r2, #60	@ 0x3c
- 8005d34:	5c9b      	ldrb	r3, [r3, r2]
- 8005d36:	2b01      	cmp	r3, #1
- 8005d38:	d101      	bne.n	8005d3e <HAL_TIM_PWM_ConfigChannel+0x22>
- 8005d3a:	2302      	movs	r3, #2
- 8005d3c:	e0e5      	b.n	8005f0a <HAL_TIM_PWM_ConfigChannel+0x1ee>
- 8005d3e:	68fb      	ldr	r3, [r7, #12]
- 8005d40:	223c      	movs	r2, #60	@ 0x3c
- 8005d42:	2101      	movs	r1, #1
- 8005d44:	5499      	strb	r1, [r3, r2]
-
-  switch (Channel)
- 8005d46:	687b      	ldr	r3, [r7, #4]
- 8005d48:	2b14      	cmp	r3, #20
- 8005d4a:	d900      	bls.n	8005d4e <HAL_TIM_PWM_ConfigChannel+0x32>
- 8005d4c:	e0d1      	b.n	8005ef2 <HAL_TIM_PWM_ConfigChannel+0x1d6>
- 8005d4e:	687b      	ldr	r3, [r7, #4]
- 8005d50:	009a      	lsls	r2, r3, #2
- 8005d52:	4b70      	ldr	r3, [pc, #448]	@ (8005f14 <HAL_TIM_PWM_ConfigChannel+0x1f8>)
- 8005d54:	18d3      	adds	r3, r2, r3
- 8005d56:	681b      	ldr	r3, [r3, #0]
- 8005d58:	469f      	mov	pc, r3
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 1 in PWM mode */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
- 8005d5a:	68fb      	ldr	r3, [r7, #12]
- 8005d5c:	681b      	ldr	r3, [r3, #0]
- 8005d5e:	68ba      	ldr	r2, [r7, #8]
- 8005d60:	0011      	movs	r1, r2
- 8005d62:	0018      	movs	r0, r3
- 8005d64:	f000 fa4c 	bl	8006200 <TIM_OC1_SetConfig>
-
-      /* Set the Preload enable bit for channel1 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
- 8005d68:	68fb      	ldr	r3, [r7, #12]
- 8005d6a:	681b      	ldr	r3, [r3, #0]
- 8005d6c:	699a      	ldr	r2, [r3, #24]
- 8005d6e:	68fb      	ldr	r3, [r7, #12]
- 8005d70:	681b      	ldr	r3, [r3, #0]
- 8005d72:	2108      	movs	r1, #8
- 8005d74:	430a      	orrs	r2, r1
- 8005d76:	619a      	str	r2, [r3, #24]
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
- 8005d78:	68fb      	ldr	r3, [r7, #12]
- 8005d7a:	681b      	ldr	r3, [r3, #0]
- 8005d7c:	699a      	ldr	r2, [r3, #24]
- 8005d7e:	68fb      	ldr	r3, [r7, #12]
- 8005d80:	681b      	ldr	r3, [r3, #0]
- 8005d82:	2104      	movs	r1, #4
- 8005d84:	438a      	bics	r2, r1
- 8005d86:	619a      	str	r2, [r3, #24]
-      htim->Instance->CCMR1 |= sConfig->OCFastMode;
- 8005d88:	68fb      	ldr	r3, [r7, #12]
- 8005d8a:	681b      	ldr	r3, [r3, #0]
- 8005d8c:	6999      	ldr	r1, [r3, #24]
- 8005d8e:	68bb      	ldr	r3, [r7, #8]
- 8005d90:	691a      	ldr	r2, [r3, #16]
- 8005d92:	68fb      	ldr	r3, [r7, #12]
- 8005d94:	681b      	ldr	r3, [r3, #0]
- 8005d96:	430a      	orrs	r2, r1
- 8005d98:	619a      	str	r2, [r3, #24]
-      break;
- 8005d9a:	e0af      	b.n	8005efc <HAL_TIM_PWM_ConfigChannel+0x1e0>
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 2 in PWM mode */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
- 8005d9c:	68fb      	ldr	r3, [r7, #12]
- 8005d9e:	681b      	ldr	r3, [r3, #0]
- 8005da0:	68ba      	ldr	r2, [r7, #8]
- 8005da2:	0011      	movs	r1, r2
- 8005da4:	0018      	movs	r0, r3
- 8005da6:	f000 faab 	bl	8006300 <TIM_OC2_SetConfig>
-
-      /* Set the Preload enable bit for channel2 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
- 8005daa:	68fb      	ldr	r3, [r7, #12]
- 8005dac:	681b      	ldr	r3, [r3, #0]
- 8005dae:	699a      	ldr	r2, [r3, #24]
- 8005db0:	68fb      	ldr	r3, [r7, #12]
- 8005db2:	681b      	ldr	r3, [r3, #0]
- 8005db4:	2180      	movs	r1, #128	@ 0x80
- 8005db6:	0109      	lsls	r1, r1, #4
- 8005db8:	430a      	orrs	r2, r1
- 8005dba:	619a      	str	r2, [r3, #24]
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
- 8005dbc:	68fb      	ldr	r3, [r7, #12]
- 8005dbe:	681b      	ldr	r3, [r3, #0]
- 8005dc0:	699a      	ldr	r2, [r3, #24]
- 8005dc2:	68fb      	ldr	r3, [r7, #12]
- 8005dc4:	681b      	ldr	r3, [r3, #0]
- 8005dc6:	4954      	ldr	r1, [pc, #336]	@ (8005f18 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
- 8005dc8:	400a      	ands	r2, r1
- 8005dca:	619a      	str	r2, [r3, #24]
-      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
- 8005dcc:	68fb      	ldr	r3, [r7, #12]
- 8005dce:	681b      	ldr	r3, [r3, #0]
- 8005dd0:	6999      	ldr	r1, [r3, #24]
- 8005dd2:	68bb      	ldr	r3, [r7, #8]
- 8005dd4:	691b      	ldr	r3, [r3, #16]
- 8005dd6:	021a      	lsls	r2, r3, #8
- 8005dd8:	68fb      	ldr	r3, [r7, #12]
- 8005dda:	681b      	ldr	r3, [r3, #0]
- 8005ddc:	430a      	orrs	r2, r1
- 8005dde:	619a      	str	r2, [r3, #24]
-      break;
- 8005de0:	e08c      	b.n	8005efc <HAL_TIM_PWM_ConfigChannel+0x1e0>
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 3 in PWM mode */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
- 8005de2:	68fb      	ldr	r3, [r7, #12]
- 8005de4:	681b      	ldr	r3, [r3, #0]
- 8005de6:	68ba      	ldr	r2, [r7, #8]
- 8005de8:	0011      	movs	r1, r2
- 8005dea:	0018      	movs	r0, r3
- 8005dec:	f000 fb06 	bl	80063fc <TIM_OC3_SetConfig>
-
-      /* Set the Preload enable bit for channel3 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
- 8005df0:	68fb      	ldr	r3, [r7, #12]
- 8005df2:	681b      	ldr	r3, [r3, #0]
- 8005df4:	69da      	ldr	r2, [r3, #28]
- 8005df6:	68fb      	ldr	r3, [r7, #12]
- 8005df8:	681b      	ldr	r3, [r3, #0]
- 8005dfa:	2108      	movs	r1, #8
- 8005dfc:	430a      	orrs	r2, r1
- 8005dfe:	61da      	str	r2, [r3, #28]
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
- 8005e00:	68fb      	ldr	r3, [r7, #12]
- 8005e02:	681b      	ldr	r3, [r3, #0]
- 8005e04:	69da      	ldr	r2, [r3, #28]
- 8005e06:	68fb      	ldr	r3, [r7, #12]
- 8005e08:	681b      	ldr	r3, [r3, #0]
- 8005e0a:	2104      	movs	r1, #4
- 8005e0c:	438a      	bics	r2, r1
- 8005e0e:	61da      	str	r2, [r3, #28]
-      htim->Instance->CCMR2 |= sConfig->OCFastMode;
- 8005e10:	68fb      	ldr	r3, [r7, #12]
- 8005e12:	681b      	ldr	r3, [r3, #0]
- 8005e14:	69d9      	ldr	r1, [r3, #28]
- 8005e16:	68bb      	ldr	r3, [r7, #8]
- 8005e18:	691a      	ldr	r2, [r3, #16]
- 8005e1a:	68fb      	ldr	r3, [r7, #12]
- 8005e1c:	681b      	ldr	r3, [r3, #0]
- 8005e1e:	430a      	orrs	r2, r1
- 8005e20:	61da      	str	r2, [r3, #28]
-      break;
- 8005e22:	e06b      	b.n	8005efc <HAL_TIM_PWM_ConfigChannel+0x1e0>
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 4 in PWM mode */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
- 8005e24:	68fb      	ldr	r3, [r7, #12]
- 8005e26:	681b      	ldr	r3, [r3, #0]
- 8005e28:	68ba      	ldr	r2, [r7, #8]
- 8005e2a:	0011      	movs	r1, r2
- 8005e2c:	0018      	movs	r0, r3
- 8005e2e:	f000 fb67 	bl	8006500 <TIM_OC4_SetConfig>
-
-      /* Set the Preload enable bit for channel4 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
- 8005e32:	68fb      	ldr	r3, [r7, #12]
- 8005e34:	681b      	ldr	r3, [r3, #0]
- 8005e36:	69da      	ldr	r2, [r3, #28]
- 8005e38:	68fb      	ldr	r3, [r7, #12]
- 8005e3a:	681b      	ldr	r3, [r3, #0]
- 8005e3c:	2180      	movs	r1, #128	@ 0x80
- 8005e3e:	0109      	lsls	r1, r1, #4
- 8005e40:	430a      	orrs	r2, r1
- 8005e42:	61da      	str	r2, [r3, #28]
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
- 8005e44:	68fb      	ldr	r3, [r7, #12]
- 8005e46:	681b      	ldr	r3, [r3, #0]
- 8005e48:	69da      	ldr	r2, [r3, #28]
- 8005e4a:	68fb      	ldr	r3, [r7, #12]
- 8005e4c:	681b      	ldr	r3, [r3, #0]
- 8005e4e:	4932      	ldr	r1, [pc, #200]	@ (8005f18 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
- 8005e50:	400a      	ands	r2, r1
- 8005e52:	61da      	str	r2, [r3, #28]
-      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
- 8005e54:	68fb      	ldr	r3, [r7, #12]
- 8005e56:	681b      	ldr	r3, [r3, #0]
- 8005e58:	69d9      	ldr	r1, [r3, #28]
- 8005e5a:	68bb      	ldr	r3, [r7, #8]
- 8005e5c:	691b      	ldr	r3, [r3, #16]
- 8005e5e:	021a      	lsls	r2, r3, #8
- 8005e60:	68fb      	ldr	r3, [r7, #12]
- 8005e62:	681b      	ldr	r3, [r3, #0]
- 8005e64:	430a      	orrs	r2, r1
- 8005e66:	61da      	str	r2, [r3, #28]
-      break;
- 8005e68:	e048      	b.n	8005efc <HAL_TIM_PWM_ConfigChannel+0x1e0>
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 5 in PWM mode */
-      TIM_OC5_SetConfig(htim->Instance, sConfig);
- 8005e6a:	68fb      	ldr	r3, [r7, #12]
- 8005e6c:	681b      	ldr	r3, [r3, #0]
- 8005e6e:	68ba      	ldr	r2, [r7, #8]
- 8005e70:	0011      	movs	r1, r2
- 8005e72:	0018      	movs	r0, r3
- 8005e74:	f000 fba8 	bl	80065c8 <TIM_OC5_SetConfig>
-
-      /* Set the Preload enable bit for channel5*/
-      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
- 8005e78:	68fb      	ldr	r3, [r7, #12]
- 8005e7a:	681b      	ldr	r3, [r3, #0]
- 8005e7c:	6d5a      	ldr	r2, [r3, #84]	@ 0x54
- 8005e7e:	68fb      	ldr	r3, [r7, #12]
- 8005e80:	681b      	ldr	r3, [r3, #0]
- 8005e82:	2108      	movs	r1, #8
- 8005e84:	430a      	orrs	r2, r1
- 8005e86:	655a      	str	r2, [r3, #84]	@ 0x54
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
- 8005e88:	68fb      	ldr	r3, [r7, #12]
- 8005e8a:	681b      	ldr	r3, [r3, #0]
- 8005e8c:	6d5a      	ldr	r2, [r3, #84]	@ 0x54
- 8005e8e:	68fb      	ldr	r3, [r7, #12]
- 8005e90:	681b      	ldr	r3, [r3, #0]
- 8005e92:	2104      	movs	r1, #4
- 8005e94:	438a      	bics	r2, r1
- 8005e96:	655a      	str	r2, [r3, #84]	@ 0x54
-      htim->Instance->CCMR3 |= sConfig->OCFastMode;
- 8005e98:	68fb      	ldr	r3, [r7, #12]
- 8005e9a:	681b      	ldr	r3, [r3, #0]
- 8005e9c:	6d59      	ldr	r1, [r3, #84]	@ 0x54
- 8005e9e:	68bb      	ldr	r3, [r7, #8]
- 8005ea0:	691a      	ldr	r2, [r3, #16]
- 8005ea2:	68fb      	ldr	r3, [r7, #12]
- 8005ea4:	681b      	ldr	r3, [r3, #0]
- 8005ea6:	430a      	orrs	r2, r1
- 8005ea8:	655a      	str	r2, [r3, #84]	@ 0x54
-      break;
- 8005eaa:	e027      	b.n	8005efc <HAL_TIM_PWM_ConfigChannel+0x1e0>
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
-
-      /* Configure the Channel 6 in PWM mode */
-      TIM_OC6_SetConfig(htim->Instance, sConfig);
- 8005eac:	68fb      	ldr	r3, [r7, #12]
- 8005eae:	681b      	ldr	r3, [r3, #0]
- 8005eb0:	68ba      	ldr	r2, [r7, #8]
- 8005eb2:	0011      	movs	r1, r2
- 8005eb4:	0018      	movs	r0, r3
- 8005eb6:	f000 fbe1 	bl	800667c <TIM_OC6_SetConfig>
-
-      /* Set the Preload enable bit for channel6 */
-      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
- 8005eba:	68fb      	ldr	r3, [r7, #12]
- 8005ebc:	681b      	ldr	r3, [r3, #0]
- 8005ebe:	6d5a      	ldr	r2, [r3, #84]	@ 0x54
- 8005ec0:	68fb      	ldr	r3, [r7, #12]
- 8005ec2:	681b      	ldr	r3, [r3, #0]
- 8005ec4:	2180      	movs	r1, #128	@ 0x80
- 8005ec6:	0109      	lsls	r1, r1, #4
- 8005ec8:	430a      	orrs	r2, r1
- 8005eca:	655a      	str	r2, [r3, #84]	@ 0x54
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
- 8005ecc:	68fb      	ldr	r3, [r7, #12]
- 8005ece:	681b      	ldr	r3, [r3, #0]
- 8005ed0:	6d5a      	ldr	r2, [r3, #84]	@ 0x54
- 8005ed2:	68fb      	ldr	r3, [r7, #12]
- 8005ed4:	681b      	ldr	r3, [r3, #0]
- 8005ed6:	4910      	ldr	r1, [pc, #64]	@ (8005f18 <HAL_TIM_PWM_ConfigChannel+0x1fc>)
- 8005ed8:	400a      	ands	r2, r1
- 8005eda:	655a      	str	r2, [r3, #84]	@ 0x54
-      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
- 8005edc:	68fb      	ldr	r3, [r7, #12]
- 8005ede:	681b      	ldr	r3, [r3, #0]
- 8005ee0:	6d59      	ldr	r1, [r3, #84]	@ 0x54
- 8005ee2:	68bb      	ldr	r3, [r7, #8]
- 8005ee4:	691b      	ldr	r3, [r3, #16]
- 8005ee6:	021a      	lsls	r2, r3, #8
- 8005ee8:	68fb      	ldr	r3, [r7, #12]
- 8005eea:	681b      	ldr	r3, [r3, #0]
- 8005eec:	430a      	orrs	r2, r1
- 8005eee:	655a      	str	r2, [r3, #84]	@ 0x54
-      break;
- 8005ef0:	e004      	b.n	8005efc <HAL_TIM_PWM_ConfigChannel+0x1e0>
-    }
-
-    default:
-      status = HAL_ERROR;
- 8005ef2:	2317      	movs	r3, #23
- 8005ef4:	18fb      	adds	r3, r7, r3
- 8005ef6:	2201      	movs	r2, #1
- 8005ef8:	701a      	strb	r2, [r3, #0]
-      break;
- 8005efa:	46c0      	nop			@ (mov r8, r8)
-  }
-
-  __HAL_UNLOCK(htim);
- 8005efc:	68fb      	ldr	r3, [r7, #12]
- 8005efe:	223c      	movs	r2, #60	@ 0x3c
- 8005f00:	2100      	movs	r1, #0
- 8005f02:	5499      	strb	r1, [r3, r2]
-
-  return status;
- 8005f04:	2317      	movs	r3, #23
- 8005f06:	18fb      	adds	r3, r7, r3
- 8005f08:	781b      	ldrb	r3, [r3, #0]
-}
- 8005f0a:	0018      	movs	r0, r3
- 8005f0c:	46bd      	mov	sp, r7
- 8005f0e:	b006      	add	sp, #24
- 8005f10:	bd80      	pop	{r7, pc}
- 8005f12:	46c0      	nop			@ (mov r8, r8)
- 8005f14:	08007e10 	.word	0x08007e10
- 8005f18:	fffffbff 	.word	0xfffffbff
-
-08005f1c <HAL_TIM_ConfigClockSource>:
-  * @param  sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
-  *         contains the clock source information for the TIM peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig)
-{
- 8005f1c:	b580      	push	{r7, lr}
- 8005f1e:	b084      	sub	sp, #16
- 8005f20:	af00      	add	r7, sp, #0
- 8005f22:	6078      	str	r0, [r7, #4]
- 8005f24:	6039      	str	r1, [r7, #0]
-  HAL_StatusTypeDef status = HAL_OK;
- 8005f26:	230f      	movs	r3, #15
- 8005f28:	18fb      	adds	r3, r7, r3
- 8005f2a:	2200      	movs	r2, #0
- 8005f2c:	701a      	strb	r2, [r3, #0]
-  uint32_t tmpsmcr;
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
- 8005f2e:	687b      	ldr	r3, [r7, #4]
- 8005f30:	223c      	movs	r2, #60	@ 0x3c
- 8005f32:	5c9b      	ldrb	r3, [r3, r2]
- 8005f34:	2b01      	cmp	r3, #1
- 8005f36:	d101      	bne.n	8005f3c <HAL_TIM_ConfigClockSource+0x20>
- 8005f38:	2302      	movs	r3, #2
- 8005f3a:	e0bc      	b.n	80060b6 <HAL_TIM_ConfigClockSource+0x19a>
- 8005f3c:	687b      	ldr	r3, [r7, #4]
- 8005f3e:	223c      	movs	r2, #60	@ 0x3c
- 8005f40:	2101      	movs	r1, #1
- 8005f42:	5499      	strb	r1, [r3, r2]
-
-  htim->State = HAL_TIM_STATE_BUSY;
- 8005f44:	687b      	ldr	r3, [r7, #4]
- 8005f46:	223d      	movs	r2, #61	@ 0x3d
- 8005f48:	2102      	movs	r1, #2
- 8005f4a:	5499      	strb	r1, [r3, r2]
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-
-  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
-  tmpsmcr = htim->Instance->SMCR;
- 8005f4c:	687b      	ldr	r3, [r7, #4]
- 8005f4e:	681b      	ldr	r3, [r3, #0]
- 8005f50:	689b      	ldr	r3, [r3, #8]
- 8005f52:	60bb      	str	r3, [r7, #8]
-  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
- 8005f54:	68bb      	ldr	r3, [r7, #8]
- 8005f56:	4a5a      	ldr	r2, [pc, #360]	@ (80060c0 <HAL_TIM_ConfigClockSource+0x1a4>)
- 8005f58:	4013      	ands	r3, r2
- 8005f5a:	60bb      	str	r3, [r7, #8]
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 8005f5c:	68bb      	ldr	r3, [r7, #8]
- 8005f5e:	4a59      	ldr	r2, [pc, #356]	@ (80060c4 <HAL_TIM_ConfigClockSource+0x1a8>)
- 8005f60:	4013      	ands	r3, r2
- 8005f62:	60bb      	str	r3, [r7, #8]
-  htim->Instance->SMCR = tmpsmcr;
- 8005f64:	687b      	ldr	r3, [r7, #4]
- 8005f66:	681b      	ldr	r3, [r3, #0]
- 8005f68:	68ba      	ldr	r2, [r7, #8]
- 8005f6a:	609a      	str	r2, [r3, #8]
-
-  switch (sClockSourceConfig->ClockSource)
- 8005f6c:	683b      	ldr	r3, [r7, #0]
- 8005f6e:	681b      	ldr	r3, [r3, #0]
- 8005f70:	2280      	movs	r2, #128	@ 0x80
- 8005f72:	0192      	lsls	r2, r2, #6
- 8005f74:	4293      	cmp	r3, r2
- 8005f76:	d040      	beq.n	8005ffa <HAL_TIM_ConfigClockSource+0xde>
- 8005f78:	2280      	movs	r2, #128	@ 0x80
- 8005f7a:	0192      	lsls	r2, r2, #6
- 8005f7c:	4293      	cmp	r3, r2
- 8005f7e:	d900      	bls.n	8005f82 <HAL_TIM_ConfigClockSource+0x66>
- 8005f80:	e088      	b.n	8006094 <HAL_TIM_ConfigClockSource+0x178>
- 8005f82:	2280      	movs	r2, #128	@ 0x80
- 8005f84:	0152      	lsls	r2, r2, #5
- 8005f86:	4293      	cmp	r3, r2
- 8005f88:	d100      	bne.n	8005f8c <HAL_TIM_ConfigClockSource+0x70>
- 8005f8a:	e088      	b.n	800609e <HAL_TIM_ConfigClockSource+0x182>
- 8005f8c:	2280      	movs	r2, #128	@ 0x80
- 8005f8e:	0152      	lsls	r2, r2, #5
- 8005f90:	4293      	cmp	r3, r2
- 8005f92:	d900      	bls.n	8005f96 <HAL_TIM_ConfigClockSource+0x7a>
- 8005f94:	e07e      	b.n	8006094 <HAL_TIM_ConfigClockSource+0x178>
- 8005f96:	2b70      	cmp	r3, #112	@ 0x70
- 8005f98:	d018      	beq.n	8005fcc <HAL_TIM_ConfigClockSource+0xb0>
- 8005f9a:	d900      	bls.n	8005f9e <HAL_TIM_ConfigClockSource+0x82>
- 8005f9c:	e07a      	b.n	8006094 <HAL_TIM_ConfigClockSource+0x178>
- 8005f9e:	2b60      	cmp	r3, #96	@ 0x60
- 8005fa0:	d04f      	beq.n	8006042 <HAL_TIM_ConfigClockSource+0x126>
- 8005fa2:	d900      	bls.n	8005fa6 <HAL_TIM_ConfigClockSource+0x8a>
- 8005fa4:	e076      	b.n	8006094 <HAL_TIM_ConfigClockSource+0x178>
- 8005fa6:	2b50      	cmp	r3, #80	@ 0x50
- 8005fa8:	d03b      	beq.n	8006022 <HAL_TIM_ConfigClockSource+0x106>
- 8005faa:	d900      	bls.n	8005fae <HAL_TIM_ConfigClockSource+0x92>
- 8005fac:	e072      	b.n	8006094 <HAL_TIM_ConfigClockSource+0x178>
- 8005fae:	2b40      	cmp	r3, #64	@ 0x40
- 8005fb0:	d057      	beq.n	8006062 <HAL_TIM_ConfigClockSource+0x146>
- 8005fb2:	d900      	bls.n	8005fb6 <HAL_TIM_ConfigClockSource+0x9a>
- 8005fb4:	e06e      	b.n	8006094 <HAL_TIM_ConfigClockSource+0x178>
- 8005fb6:	2b30      	cmp	r3, #48	@ 0x30
- 8005fb8:	d063      	beq.n	8006082 <HAL_TIM_ConfigClockSource+0x166>
- 8005fba:	d86b      	bhi.n	8006094 <HAL_TIM_ConfigClockSource+0x178>
- 8005fbc:	2b20      	cmp	r3, #32
- 8005fbe:	d060      	beq.n	8006082 <HAL_TIM_ConfigClockSource+0x166>
- 8005fc0:	d868      	bhi.n	8006094 <HAL_TIM_ConfigClockSource+0x178>
- 8005fc2:	2b00      	cmp	r3, #0
- 8005fc4:	d05d      	beq.n	8006082 <HAL_TIM_ConfigClockSource+0x166>
- 8005fc6:	2b10      	cmp	r3, #16
- 8005fc8:	d05b      	beq.n	8006082 <HAL_TIM_ConfigClockSource+0x166>
- 8005fca:	e063      	b.n	8006094 <HAL_TIM_ConfigClockSource+0x178>
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance,
- 8005fcc:	687b      	ldr	r3, [r7, #4]
- 8005fce:	6818      	ldr	r0, [r3, #0]
-                        sClockSourceConfig->ClockPrescaler,
- 8005fd0:	683b      	ldr	r3, [r7, #0]
- 8005fd2:	6899      	ldr	r1, [r3, #8]
-                        sClockSourceConfig->ClockPolarity,
- 8005fd4:	683b      	ldr	r3, [r7, #0]
- 8005fd6:	685a      	ldr	r2, [r3, #4]
-                        sClockSourceConfig->ClockFilter);
- 8005fd8:	683b      	ldr	r3, [r7, #0]
- 8005fda:	68db      	ldr	r3, [r3, #12]
-      TIM_ETR_SetConfig(htim->Instance,
- 8005fdc:	f000 fc28 	bl	8006830 <TIM_ETR_SetConfig>
-
-      /* Select the External clock mode1 and the ETRF trigger */
-      tmpsmcr = htim->Instance->SMCR;
- 8005fe0:	687b      	ldr	r3, [r7, #4]
- 8005fe2:	681b      	ldr	r3, [r3, #0]
- 8005fe4:	689b      	ldr	r3, [r3, #8]
- 8005fe6:	60bb      	str	r3, [r7, #8]
-      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
- 8005fe8:	68bb      	ldr	r3, [r7, #8]
- 8005fea:	2277      	movs	r2, #119	@ 0x77
- 8005fec:	4313      	orrs	r3, r2
- 8005fee:	60bb      	str	r3, [r7, #8]
-      /* Write to TIMx SMCR */
-      htim->Instance->SMCR = tmpsmcr;
- 8005ff0:	687b      	ldr	r3, [r7, #4]
- 8005ff2:	681b      	ldr	r3, [r3, #0]
- 8005ff4:	68ba      	ldr	r2, [r7, #8]
- 8005ff6:	609a      	str	r2, [r3, #8]
-      break;
- 8005ff8:	e052      	b.n	80060a0 <HAL_TIM_ConfigClockSource+0x184>
-      assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance,
- 8005ffa:	687b      	ldr	r3, [r7, #4]
- 8005ffc:	6818      	ldr	r0, [r3, #0]
-                        sClockSourceConfig->ClockPrescaler,
- 8005ffe:	683b      	ldr	r3, [r7, #0]
- 8006000:	6899      	ldr	r1, [r3, #8]
-                        sClockSourceConfig->ClockPolarity,
- 8006002:	683b      	ldr	r3, [r7, #0]
- 8006004:	685a      	ldr	r2, [r3, #4]
-                        sClockSourceConfig->ClockFilter);
- 8006006:	683b      	ldr	r3, [r7, #0]
- 8006008:	68db      	ldr	r3, [r3, #12]
-      TIM_ETR_SetConfig(htim->Instance,
- 800600a:	f000 fc11 	bl	8006830 <TIM_ETR_SetConfig>
-      /* Enable the External clock mode2 */
-      htim->Instance->SMCR |= TIM_SMCR_ECE;
- 800600e:	687b      	ldr	r3, [r7, #4]
- 8006010:	681b      	ldr	r3, [r3, #0]
- 8006012:	689a      	ldr	r2, [r3, #8]
- 8006014:	687b      	ldr	r3, [r7, #4]
- 8006016:	681b      	ldr	r3, [r3, #0]
- 8006018:	2180      	movs	r1, #128	@ 0x80
- 800601a:	01c9      	lsls	r1, r1, #7
- 800601c:	430a      	orrs	r2, r1
- 800601e:	609a      	str	r2, [r3, #8]
-      break;
- 8006020:	e03e      	b.n	80060a0 <HAL_TIM_ConfigClockSource+0x184>
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI1_ConfigInputStage(htim->Instance,
- 8006022:	687b      	ldr	r3, [r7, #4]
- 8006024:	6818      	ldr	r0, [r3, #0]
-                               sClockSourceConfig->ClockPolarity,
- 8006026:	683b      	ldr	r3, [r7, #0]
- 8006028:	6859      	ldr	r1, [r3, #4]
-                               sClockSourceConfig->ClockFilter);
- 800602a:	683b      	ldr	r3, [r7, #0]
- 800602c:	68db      	ldr	r3, [r3, #12]
-      TIM_TI1_ConfigInputStage(htim->Instance,
- 800602e:	001a      	movs	r2, r3
- 8006030:	f000 fb82 	bl	8006738 <TIM_TI1_ConfigInputStage>
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
- 8006034:	687b      	ldr	r3, [r7, #4]
- 8006036:	681b      	ldr	r3, [r3, #0]
- 8006038:	2150      	movs	r1, #80	@ 0x50
- 800603a:	0018      	movs	r0, r3
- 800603c:	f000 fbdc 	bl	80067f8 <TIM_ITRx_SetConfig>
-      break;
- 8006040:	e02e      	b.n	80060a0 <HAL_TIM_ConfigClockSource+0x184>
-
-      /* Check TI2 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI2_ConfigInputStage(htim->Instance,
- 8006042:	687b      	ldr	r3, [r7, #4]
- 8006044:	6818      	ldr	r0, [r3, #0]
-                               sClockSourceConfig->ClockPolarity,
- 8006046:	683b      	ldr	r3, [r7, #0]
- 8006048:	6859      	ldr	r1, [r3, #4]
-                               sClockSourceConfig->ClockFilter);
- 800604a:	683b      	ldr	r3, [r7, #0]
- 800604c:	68db      	ldr	r3, [r3, #12]
-      TIM_TI2_ConfigInputStage(htim->Instance,
- 800604e:	001a      	movs	r2, r3
- 8006050:	f000 fba0 	bl	8006794 <TIM_TI2_ConfigInputStage>
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
- 8006054:	687b      	ldr	r3, [r7, #4]
- 8006056:	681b      	ldr	r3, [r3, #0]
- 8006058:	2160      	movs	r1, #96	@ 0x60
- 800605a:	0018      	movs	r0, r3
- 800605c:	f000 fbcc 	bl	80067f8 <TIM_ITRx_SetConfig>
-      break;
- 8006060:	e01e      	b.n	80060a0 <HAL_TIM_ConfigClockSource+0x184>
-
-      /* Check TI1 input conditioning related parameters */
-      assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-      assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-      TIM_TI1_ConfigInputStage(htim->Instance,
- 8006062:	687b      	ldr	r3, [r7, #4]
- 8006064:	6818      	ldr	r0, [r3, #0]
-                               sClockSourceConfig->ClockPolarity,
- 8006066:	683b      	ldr	r3, [r7, #0]
- 8006068:	6859      	ldr	r1, [r3, #4]
-                               sClockSourceConfig->ClockFilter);
- 800606a:	683b      	ldr	r3, [r7, #0]
- 800606c:	68db      	ldr	r3, [r3, #12]
-      TIM_TI1_ConfigInputStage(htim->Instance,
- 800606e:	001a      	movs	r2, r3
- 8006070:	f000 fb62 	bl	8006738 <TIM_TI1_ConfigInputStage>
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
- 8006074:	687b      	ldr	r3, [r7, #4]
- 8006076:	681b      	ldr	r3, [r3, #0]
- 8006078:	2140      	movs	r1, #64	@ 0x40
- 800607a:	0018      	movs	r0, r3
- 800607c:	f000 fbbc 	bl	80067f8 <TIM_ITRx_SetConfig>
-      break;
- 8006080:	e00e      	b.n	80060a0 <HAL_TIM_ConfigClockSource+0x184>
-    case TIM_CLOCKSOURCE_ITR3:
-    {
-      /* Check whether or not the timer instance supports internal trigger input */
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
-      TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
- 8006082:	687b      	ldr	r3, [r7, #4]
- 8006084:	681a      	ldr	r2, [r3, #0]
- 8006086:	683b      	ldr	r3, [r7, #0]
- 8006088:	681b      	ldr	r3, [r3, #0]
- 800608a:	0019      	movs	r1, r3
- 800608c:	0010      	movs	r0, r2
- 800608e:	f000 fbb3 	bl	80067f8 <TIM_ITRx_SetConfig>
-      break;
- 8006092:	e005      	b.n	80060a0 <HAL_TIM_ConfigClockSource+0x184>
-    }
-
-    default:
-      status = HAL_ERROR;
- 8006094:	230f      	movs	r3, #15
- 8006096:	18fb      	adds	r3, r7, r3
- 8006098:	2201      	movs	r2, #1
- 800609a:	701a      	strb	r2, [r3, #0]
-      break;
- 800609c:	e000      	b.n	80060a0 <HAL_TIM_ConfigClockSource+0x184>
-      break;
- 800609e:	46c0      	nop			@ (mov r8, r8)
-  }
-  htim->State = HAL_TIM_STATE_READY;
- 80060a0:	687b      	ldr	r3, [r7, #4]
- 80060a2:	223d      	movs	r2, #61	@ 0x3d
- 80060a4:	2101      	movs	r1, #1
- 80060a6:	5499      	strb	r1, [r3, r2]
-
-  __HAL_UNLOCK(htim);
- 80060a8:	687b      	ldr	r3, [r7, #4]
- 80060aa:	223c      	movs	r2, #60	@ 0x3c
- 80060ac:	2100      	movs	r1, #0
- 80060ae:	5499      	strb	r1, [r3, r2]
-
-  return status;
- 80060b0:	230f      	movs	r3, #15
- 80060b2:	18fb      	adds	r3, r7, r3
- 80060b4:	781b      	ldrb	r3, [r3, #0]
-}
- 80060b6:	0018      	movs	r0, r3
- 80060b8:	46bd      	mov	sp, r7
- 80060ba:	b004      	add	sp, #16
- 80060bc:	bd80      	pop	{r7, pc}
- 80060be:	46c0      	nop			@ (mov r8, r8)
- 80060c0:	ffceff88 	.word	0xffceff88
- 80060c4:	ffff00ff 	.word	0xffff00ff
-
-080060c8 <HAL_TIM_OC_DelayElapsedCallback>:
-  * @brief  Output Compare callback in non-blocking mode
-  * @param  htim TIM OC handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
- 80060c8:	b580      	push	{r7, lr}
- 80060ca:	b082      	sub	sp, #8
- 80060cc:	af00      	add	r7, sp, #0
- 80060ce:	6078      	str	r0, [r7, #4]
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
-   */
-}
- 80060d0:	46c0      	nop			@ (mov r8, r8)
- 80060d2:	46bd      	mov	sp, r7
- 80060d4:	b002      	add	sp, #8
- 80060d6:	bd80      	pop	{r7, pc}
-
-080060d8 <HAL_TIM_IC_CaptureCallback>:
-  * @brief  Input Capture callback in non-blocking mode
-  * @param  htim TIM IC handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
- 80060d8:	b580      	push	{r7, lr}
- 80060da:	b082      	sub	sp, #8
- 80060dc:	af00      	add	r7, sp, #0
- 80060de:	6078      	str	r0, [r7, #4]
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_IC_CaptureCallback could be implemented in the user file
-   */
-}
- 80060e0:	46c0      	nop			@ (mov r8, r8)
- 80060e2:	46bd      	mov	sp, r7
- 80060e4:	b002      	add	sp, #8
- 80060e6:	bd80      	pop	{r7, pc}
-
-080060e8 <HAL_TIM_PWM_PulseFinishedCallback>:
-  * @brief  PWM Pulse finished callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
- 80060e8:	b580      	push	{r7, lr}
- 80060ea:	b082      	sub	sp, #8
- 80060ec:	af00      	add	r7, sp, #0
- 80060ee:	6078      	str	r0, [r7, #4]
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
-   */
-}
- 80060f0:	46c0      	nop			@ (mov r8, r8)
- 80060f2:	46bd      	mov	sp, r7
- 80060f4:	b002      	add	sp, #8
- 80060f6:	bd80      	pop	{r7, pc}
-
-080060f8 <HAL_TIM_TriggerCallback>:
-  * @brief  Hall Trigger detection callback in non-blocking mode
-  * @param  htim TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
- 80060f8:	b580      	push	{r7, lr}
- 80060fa:	b082      	sub	sp, #8
- 80060fc:	af00      	add	r7, sp, #0
- 80060fe:	6078      	str	r0, [r7, #4]
-  UNUSED(htim);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIM_TriggerCallback could be implemented in the user file
-   */
-}
- 8006100:	46c0      	nop			@ (mov r8, r8)
- 8006102:	46bd      	mov	sp, r7
- 8006104:	b002      	add	sp, #8
- 8006106:	bd80      	pop	{r7, pc}
-
-08006108 <TIM_Base_SetConfig>:
-  * @param  TIMx TIM peripheral
-  * @param  Structure TIM Base configuration structure
-  * @retval None
-  */
-void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure)
-{
- 8006108:	b580      	push	{r7, lr}
- 800610a:	b084      	sub	sp, #16
- 800610c:	af00      	add	r7, sp, #0
- 800610e:	6078      	str	r0, [r7, #4]
- 8006110:	6039      	str	r1, [r7, #0]
-  uint32_t tmpcr1;
-  tmpcr1 = TIMx->CR1;
- 8006112:	687b      	ldr	r3, [r7, #4]
- 8006114:	681b      	ldr	r3, [r3, #0]
- 8006116:	60fb      	str	r3, [r7, #12]
-
-  /* Set TIM Time Base Unit parameters ---------------------------------------*/
-  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
- 8006118:	687b      	ldr	r3, [r7, #4]
- 800611a:	4a33      	ldr	r2, [pc, #204]	@ (80061e8 <TIM_Base_SetConfig+0xe0>)
- 800611c:	4293      	cmp	r3, r2
- 800611e:	d008      	beq.n	8006132 <TIM_Base_SetConfig+0x2a>
- 8006120:	687a      	ldr	r2, [r7, #4]
- 8006122:	2380      	movs	r3, #128	@ 0x80
- 8006124:	05db      	lsls	r3, r3, #23
- 8006126:	429a      	cmp	r2, r3
- 8006128:	d003      	beq.n	8006132 <TIM_Base_SetConfig+0x2a>
- 800612a:	687b      	ldr	r3, [r7, #4]
- 800612c:	4a2f      	ldr	r2, [pc, #188]	@ (80061ec <TIM_Base_SetConfig+0xe4>)
- 800612e:	4293      	cmp	r3, r2
- 8006130:	d108      	bne.n	8006144 <TIM_Base_SetConfig+0x3c>
-  {
-    /* Select the Counter Mode */
-    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
- 8006132:	68fb      	ldr	r3, [r7, #12]
- 8006134:	2270      	movs	r2, #112	@ 0x70
- 8006136:	4393      	bics	r3, r2
- 8006138:	60fb      	str	r3, [r7, #12]
-    tmpcr1 |= Structure->CounterMode;
- 800613a:	683b      	ldr	r3, [r7, #0]
- 800613c:	685b      	ldr	r3, [r3, #4]
- 800613e:	68fa      	ldr	r2, [r7, #12]
- 8006140:	4313      	orrs	r3, r2
- 8006142:	60fb      	str	r3, [r7, #12]
-  }
-
-  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
- 8006144:	687b      	ldr	r3, [r7, #4]
- 8006146:	4a28      	ldr	r2, [pc, #160]	@ (80061e8 <TIM_Base_SetConfig+0xe0>)
- 8006148:	4293      	cmp	r3, r2
- 800614a:	d014      	beq.n	8006176 <TIM_Base_SetConfig+0x6e>
- 800614c:	687a      	ldr	r2, [r7, #4]
- 800614e:	2380      	movs	r3, #128	@ 0x80
- 8006150:	05db      	lsls	r3, r3, #23
- 8006152:	429a      	cmp	r2, r3
- 8006154:	d00f      	beq.n	8006176 <TIM_Base_SetConfig+0x6e>
- 8006156:	687b      	ldr	r3, [r7, #4]
- 8006158:	4a24      	ldr	r2, [pc, #144]	@ (80061ec <TIM_Base_SetConfig+0xe4>)
- 800615a:	4293      	cmp	r3, r2
- 800615c:	d00b      	beq.n	8006176 <TIM_Base_SetConfig+0x6e>
- 800615e:	687b      	ldr	r3, [r7, #4]
- 8006160:	4a23      	ldr	r2, [pc, #140]	@ (80061f0 <TIM_Base_SetConfig+0xe8>)
- 8006162:	4293      	cmp	r3, r2
- 8006164:	d007      	beq.n	8006176 <TIM_Base_SetConfig+0x6e>
- 8006166:	687b      	ldr	r3, [r7, #4]
- 8006168:	4a22      	ldr	r2, [pc, #136]	@ (80061f4 <TIM_Base_SetConfig+0xec>)
- 800616a:	4293      	cmp	r3, r2
- 800616c:	d003      	beq.n	8006176 <TIM_Base_SetConfig+0x6e>
- 800616e:	687b      	ldr	r3, [r7, #4]
- 8006170:	4a21      	ldr	r2, [pc, #132]	@ (80061f8 <TIM_Base_SetConfig+0xf0>)
- 8006172:	4293      	cmp	r3, r2
- 8006174:	d108      	bne.n	8006188 <TIM_Base_SetConfig+0x80>
-  {
-    /* Set the clock division */
-    tmpcr1 &= ~TIM_CR1_CKD;
- 8006176:	68fb      	ldr	r3, [r7, #12]
- 8006178:	4a20      	ldr	r2, [pc, #128]	@ (80061fc <TIM_Base_SetConfig+0xf4>)
- 800617a:	4013      	ands	r3, r2
- 800617c:	60fb      	str	r3, [r7, #12]
-    tmpcr1 |= (uint32_t)Structure->ClockDivision;
- 800617e:	683b      	ldr	r3, [r7, #0]
- 8006180:	68db      	ldr	r3, [r3, #12]
- 8006182:	68fa      	ldr	r2, [r7, #12]
- 8006184:	4313      	orrs	r3, r2
- 8006186:	60fb      	str	r3, [r7, #12]
-  }
-
-  /* Set the auto-reload preload */
-  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
- 8006188:	68fb      	ldr	r3, [r7, #12]
- 800618a:	2280      	movs	r2, #128	@ 0x80
- 800618c:	4393      	bics	r3, r2
- 800618e:	001a      	movs	r2, r3
- 8006190:	683b      	ldr	r3, [r7, #0]
- 8006192:	695b      	ldr	r3, [r3, #20]
- 8006194:	4313      	orrs	r3, r2
- 8006196:	60fb      	str	r3, [r7, #12]
-
-  /* Set the Autoreload value */
-  TIMx->ARR = (uint32_t)Structure->Period ;
- 8006198:	683b      	ldr	r3, [r7, #0]
- 800619a:	689a      	ldr	r2, [r3, #8]
- 800619c:	687b      	ldr	r3, [r7, #4]
- 800619e:	62da      	str	r2, [r3, #44]	@ 0x2c
-
-  /* Set the Prescaler value */
-  TIMx->PSC = Structure->Prescaler;
- 80061a0:	683b      	ldr	r3, [r7, #0]
- 80061a2:	681a      	ldr	r2, [r3, #0]
- 80061a4:	687b      	ldr	r3, [r7, #4]
- 80061a6:	629a      	str	r2, [r3, #40]	@ 0x28
-
-  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
- 80061a8:	687b      	ldr	r3, [r7, #4]
- 80061aa:	4a0f      	ldr	r2, [pc, #60]	@ (80061e8 <TIM_Base_SetConfig+0xe0>)
- 80061ac:	4293      	cmp	r3, r2
- 80061ae:	d007      	beq.n	80061c0 <TIM_Base_SetConfig+0xb8>
- 80061b0:	687b      	ldr	r3, [r7, #4]
- 80061b2:	4a10      	ldr	r2, [pc, #64]	@ (80061f4 <TIM_Base_SetConfig+0xec>)
- 80061b4:	4293      	cmp	r3, r2
- 80061b6:	d003      	beq.n	80061c0 <TIM_Base_SetConfig+0xb8>
- 80061b8:	687b      	ldr	r3, [r7, #4]
- 80061ba:	4a0f      	ldr	r2, [pc, #60]	@ (80061f8 <TIM_Base_SetConfig+0xf0>)
- 80061bc:	4293      	cmp	r3, r2
- 80061be:	d103      	bne.n	80061c8 <TIM_Base_SetConfig+0xc0>
-  {
-    /* Set the Repetition Counter value */
-    TIMx->RCR = Structure->RepetitionCounter;
- 80061c0:	683b      	ldr	r3, [r7, #0]
- 80061c2:	691a      	ldr	r2, [r3, #16]
- 80061c4:	687b      	ldr	r3, [r7, #4]
- 80061c6:	631a      	str	r2, [r3, #48]	@ 0x30
-  }
-
-  /* Disable Update Event (UEV) with Update Generation (UG)
-     by changing Update Request Source (URS) to avoid Update flag (UIF) */
-  SET_BIT(TIMx->CR1, TIM_CR1_URS);
- 80061c8:	687b      	ldr	r3, [r7, #4]
- 80061ca:	681b      	ldr	r3, [r3, #0]
- 80061cc:	2204      	movs	r2, #4
- 80061ce:	431a      	orrs	r2, r3
- 80061d0:	687b      	ldr	r3, [r7, #4]
- 80061d2:	601a      	str	r2, [r3, #0]
-
-  /* Generate an update event to reload the Prescaler
-     and the repetition counter (only for advanced timer) value immediately */
-  TIMx->EGR = TIM_EGR_UG;
- 80061d4:	687b      	ldr	r3, [r7, #4]
- 80061d6:	2201      	movs	r2, #1
- 80061d8:	615a      	str	r2, [r3, #20]
-
-  TIMx->CR1 = tmpcr1;
- 80061da:	687b      	ldr	r3, [r7, #4]
- 80061dc:	68fa      	ldr	r2, [r7, #12]
- 80061de:	601a      	str	r2, [r3, #0]
-}
- 80061e0:	46c0      	nop			@ (mov r8, r8)
- 80061e2:	46bd      	mov	sp, r7
- 80061e4:	b004      	add	sp, #16
- 80061e6:	bd80      	pop	{r7, pc}
- 80061e8:	40012c00 	.word	0x40012c00
- 80061ec:	40000400 	.word	0x40000400
- 80061f0:	40002000 	.word	0x40002000
- 80061f4:	40014400 	.word	0x40014400
- 80061f8:	40014800 	.word	0x40014800
- 80061fc:	fffffcff 	.word	0xfffffcff
-
-08006200 <TIM_OC1_SetConfig>:
+ 8003878:	b005      	add	sp, #20
+ 800387a:	bdf0      	pop	{r4, r5, r6, r7, pc}
+    if ((tmpregister != RCC_RTCCLKSOURCE_NONE) && (tmpregister != PeriphClkInit->RTCClockSelection))
+ 800387c:	69ab      	ldr	r3, [r5, #24]
+ 800387e:	428b      	cmp	r3, r1
+ 8003880:	d0c0      	beq.n	8003804 <HAL_RCCEx_PeriphCLKConfig+0x3c>
+      __HAL_RCC_BACKUPRESET_FORCE();
+ 8003882:	2280      	movs	r2, #128	@ 0x80
+      tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL));
+ 8003884:	6de3      	ldr	r3, [r4, #92]	@ 0x5c
+      __HAL_RCC_BACKUPRESET_FORCE();
+ 8003886:	6de0      	ldr	r0, [r4, #92]	@ 0x5c
+      tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL));
+ 8003888:	0019      	movs	r1, r3
+      __HAL_RCC_BACKUPRESET_FORCE();
+ 800388a:	0252      	lsls	r2, r2, #9
+ 800388c:	4302      	orrs	r2, r0
+ 800388e:	65e2      	str	r2, [r4, #92]	@ 0x5c
+      __HAL_RCC_BACKUPRESET_RELEASE();
+ 8003890:	6de2      	ldr	r2, [r4, #92]	@ 0x5c
+ 8003892:	4810      	ldr	r0, [pc, #64]	@ (80038d4 <HAL_RCCEx_PeriphCLKConfig+0x10c>)
+      tmpregister = READ_BIT(RCC->CSR1, ~(RCC_CSR1_RTCSEL));
+ 8003894:	4039      	ands	r1, r7
+      __HAL_RCC_BACKUPRESET_RELEASE();
+ 8003896:	4002      	ands	r2, r0
+ 8003898:	65e2      	str	r2, [r4, #92]	@ 0x5c
+      RCC->CSR1 = tmpregister;
+ 800389a:	65e1      	str	r1, [r4, #92]	@ 0x5c
+    if (HAL_IS_BIT_SET(tmpregister, RCC_CSR1_LSEON))
+ 800389c:	07db      	lsls	r3, r3, #31
+ 800389e:	d5b1      	bpl.n	8003804 <HAL_RCCEx_PeriphCLKConfig+0x3c>
+      tickstart = HAL_GetTick();
+ 80038a0:	f7ff f81e 	bl	80028e0 <HAL_GetTick>
+ 80038a4:	9001      	str	r0, [sp, #4]
+      while (READ_BIT(RCC->CSR1, RCC_CSR1_LSERDY) == 0U)
+ 80038a6:	2202      	movs	r2, #2
+ 80038a8:	6de3      	ldr	r3, [r4, #92]	@ 0x5c
+ 80038aa:	4213      	tst	r3, r2
+ 80038ac:	d1aa      	bne.n	8003804 <HAL_RCCEx_PeriphCLKConfig+0x3c>
+        if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE)
+ 80038ae:	f7ff f817 	bl	80028e0 <HAL_GetTick>
+ 80038b2:	9b01      	ldr	r3, [sp, #4]
+ 80038b4:	1ac0      	subs	r0, r0, r3
+ 80038b6:	4b08      	ldr	r3, [pc, #32]	@ (80038d8 <HAL_RCCEx_PeriphCLKConfig+0x110>)
+ 80038b8:	4298      	cmp	r0, r3
+ 80038ba:	d9f4      	bls.n	80038a6 <HAL_RCCEx_PeriphCLKConfig+0xde>
+      status = ret;
+ 80038bc:	2003      	movs	r0, #3
+ 80038be:	e7a7      	b.n	8003810 <HAL_RCCEx_PeriphCLKConfig+0x48>
+ 80038c0:	40021000 	.word	0x40021000
+ 80038c4:	fffffcff 	.word	0xfffffcff
+ 80038c8:	efffffff 	.word	0xefffffff
+ 80038cc:	ffffcfff 	.word	0xffffcfff
+ 80038d0:	ffff3fff 	.word	0xffff3fff
+ 80038d4:	fffeffff 	.word	0xfffeffff
+ 80038d8:	00001388 	.word	0x00001388
+
+080038dc <TIM_OC1_SetConfig>:
   * @param  TIMx to select the TIM peripheral
   * @param  OC_Config The output configuration structure
   * @retval None
   */
 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
 {
- 8006200:	b580      	push	{r7, lr}
- 8006202:	b086      	sub	sp, #24
- 8006204:	af00      	add	r7, sp, #0
- 8006206:	6078      	str	r0, [r7, #4]
- 8006208:	6039      	str	r1, [r7, #0]
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
+ 80038dc:	b570      	push	{r4, r5, r6, lr}
 
   /* Get the TIMx CCER register value */
   tmpccer = TIMx->CCER;
- 800620a:	687b      	ldr	r3, [r7, #4]
- 800620c:	6a1b      	ldr	r3, [r3, #32]
- 800620e:	617b      	str	r3, [r7, #20]
 
   /* Disable the Channel 1: Reset the CC1E Bit */
   TIMx->CCER &= ~TIM_CCER_CC1E;
- 8006210:	687b      	ldr	r3, [r7, #4]
- 8006212:	6a1b      	ldr	r3, [r3, #32]
- 8006214:	2201      	movs	r2, #1
- 8006216:	4393      	bics	r3, r2
- 8006218:	001a      	movs	r2, r3
- 800621a:	687b      	ldr	r3, [r7, #4]
- 800621c:	621a      	str	r2, [r3, #32]
+ 80038de:	2401      	movs	r4, #1
+  tmpccer = TIMx->CCER;
+ 80038e0:	6a03      	ldr	r3, [r0, #32]
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+ 80038e2:	6a02      	ldr	r2, [r0, #32]
+ 80038e4:	43a2      	bics	r2, r4
+ 80038e6:	6202      	str	r2, [r0, #32]
 
   /* Get the TIMx CR2 register value */
   tmpcr2 =  TIMx->CR2;
- 800621e:	687b      	ldr	r3, [r7, #4]
- 8006220:	685b      	ldr	r3, [r3, #4]
- 8006222:	613b      	str	r3, [r7, #16]
-
+ 80038e8:	6844      	ldr	r4, [r0, #4]
   /* Get the TIMx CCMR1 register value */
   tmpccmrx = TIMx->CCMR1;
- 8006224:	687b      	ldr	r3, [r7, #4]
- 8006226:	699b      	ldr	r3, [r3, #24]
- 8006228:	60fb      	str	r3, [r7, #12]
 
   /* Reset the Output Compare Mode Bits */
   tmpccmrx &= ~TIM_CCMR1_OC1M;
- 800622a:	68fb      	ldr	r3, [r7, #12]
- 800622c:	4a2e      	ldr	r2, [pc, #184]	@ (80062e8 <TIM_OC1_SetConfig+0xe8>)
- 800622e:	4013      	ands	r3, r2
- 8006230:	60fb      	str	r3, [r7, #12]
   tmpccmrx &= ~TIM_CCMR1_CC1S;
- 8006232:	68fb      	ldr	r3, [r7, #12]
- 8006234:	2203      	movs	r2, #3
- 8006236:	4393      	bics	r3, r2
- 8006238:	60fb      	str	r3, [r7, #12]
+ 80038ea:	4a12      	ldr	r2, [pc, #72]	@ (8003934 <TIM_OC1_SetConfig+0x58>)
+  tmpccmrx = TIMx->CCMR1;
+ 80038ec:	6985      	ldr	r5, [r0, #24]
+  tmpccmrx &= ~TIM_CCMR1_CC1S;
+ 80038ee:	4015      	ands	r5, r2
   /* Select the Output Compare Mode */
   tmpccmrx |= OC_Config->OCMode;
- 800623a:	683b      	ldr	r3, [r7, #0]
- 800623c:	681b      	ldr	r3, [r3, #0]
- 800623e:	68fa      	ldr	r2, [r7, #12]
- 8006240:	4313      	orrs	r3, r2
- 8006242:	60fb      	str	r3, [r7, #12]
+ 80038f0:	680a      	ldr	r2, [r1, #0]
+ 80038f2:	4315      	orrs	r5, r2
 
   /* Reset the Output Polarity level */
   tmpccer &= ~TIM_CCER_CC1P;
- 8006244:	697b      	ldr	r3, [r7, #20]
- 8006246:	2202      	movs	r2, #2
- 8006248:	4393      	bics	r3, r2
- 800624a:	617b      	str	r3, [r7, #20]
+ 80038f4:	2202      	movs	r2, #2
+ 80038f6:	4393      	bics	r3, r2
   /* Set the Output Compare Polarity */
   tmpccer |= OC_Config->OCPolarity;
- 800624c:	683b      	ldr	r3, [r7, #0]
- 800624e:	689b      	ldr	r3, [r3, #8]
- 8006250:	697a      	ldr	r2, [r7, #20]
- 8006252:	4313      	orrs	r3, r2
- 8006254:	617b      	str	r3, [r7, #20]
+ 80038f8:	688a      	ldr	r2, [r1, #8]
+ 80038fa:	4313      	orrs	r3, r2
 
   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
- 8006256:	687b      	ldr	r3, [r7, #4]
- 8006258:	4a24      	ldr	r2, [pc, #144]	@ (80062ec <TIM_OC1_SetConfig+0xec>)
- 800625a:	4293      	cmp	r3, r2
- 800625c:	d007      	beq.n	800626e <TIM_OC1_SetConfig+0x6e>
- 800625e:	687b      	ldr	r3, [r7, #4]
- 8006260:	4a23      	ldr	r2, [pc, #140]	@ (80062f0 <TIM_OC1_SetConfig+0xf0>)
- 8006262:	4293      	cmp	r3, r2
- 8006264:	d003      	beq.n	800626e <TIM_OC1_SetConfig+0x6e>
- 8006266:	687b      	ldr	r3, [r7, #4]
- 8006268:	4a22      	ldr	r2, [pc, #136]	@ (80062f4 <TIM_OC1_SetConfig+0xf4>)
- 800626a:	4293      	cmp	r3, r2
- 800626c:	d10c      	bne.n	8006288 <TIM_OC1_SetConfig+0x88>
+ 80038fc:	4a0e      	ldr	r2, [pc, #56]	@ (8003938 <TIM_OC1_SetConfig+0x5c>)
+ 80038fe:	4290      	cmp	r0, r2
+ 8003900:	d005      	beq.n	800390e <TIM_OC1_SetConfig+0x32>
+ 8003902:	4a0e      	ldr	r2, [pc, #56]	@ (800393c <TIM_OC1_SetConfig+0x60>)
+ 8003904:	4290      	cmp	r0, r2
+ 8003906:	d002      	beq.n	800390e <TIM_OC1_SetConfig+0x32>
+ 8003908:	4a0d      	ldr	r2, [pc, #52]	@ (8003940 <TIM_OC1_SetConfig+0x64>)
+ 800390a:	4290      	cmp	r0, r2
+ 800390c:	d10b      	bne.n	8003926 <TIM_OC1_SetConfig+0x4a>
   {
     /* Check parameters */
     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
 
     /* Reset the Output N Polarity level */
     tmpccer &= ~TIM_CCER_CC1NP;
- 800626e:	697b      	ldr	r3, [r7, #20]
- 8006270:	2208      	movs	r2, #8
- 8006272:	4393      	bics	r3, r2
- 8006274:	617b      	str	r3, [r7, #20]
+ 800390e:	2208      	movs	r2, #8
+ 8003910:	4393      	bics	r3, r2
     /* Set the Output N Polarity */
     tmpccer |= OC_Config->OCNPolarity;
- 8006276:	683b      	ldr	r3, [r7, #0]
- 8006278:	68db      	ldr	r3, [r3, #12]
- 800627a:	697a      	ldr	r2, [r7, #20]
- 800627c:	4313      	orrs	r3, r2
- 800627e:	617b      	str	r3, [r7, #20]
-    /* Reset the Output N State */
-    tmpccer &= ~TIM_CCER_CC1NE;
- 8006280:	697b      	ldr	r3, [r7, #20]
- 8006282:	2204      	movs	r2, #4
- 8006284:	4393      	bics	r3, r2
- 8006286:	617b      	str	r3, [r7, #20]
-  }
-
-  if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8006288:	687b      	ldr	r3, [r7, #4]
- 800628a:	4a18      	ldr	r2, [pc, #96]	@ (80062ec <TIM_OC1_SetConfig+0xec>)
- 800628c:	4293      	cmp	r3, r2
- 800628e:	d007      	beq.n	80062a0 <TIM_OC1_SetConfig+0xa0>
- 8006290:	687b      	ldr	r3, [r7, #4]
- 8006292:	4a17      	ldr	r2, [pc, #92]	@ (80062f0 <TIM_OC1_SetConfig+0xf0>)
- 8006294:	4293      	cmp	r3, r2
- 8006296:	d003      	beq.n	80062a0 <TIM_OC1_SetConfig+0xa0>
- 8006298:	687b      	ldr	r3, [r7, #4]
- 800629a:	4a16      	ldr	r2, [pc, #88]	@ (80062f4 <TIM_OC1_SetConfig+0xf4>)
- 800629c:	4293      	cmp	r3, r2
- 800629e:	d111      	bne.n	80062c4 <TIM_OC1_SetConfig+0xc4>
-    /* Check parameters */
-    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
-    /* Reset the Output Compare and Output Compare N IDLE State */
+ 8003912:	68ca      	ldr	r2, [r1, #12]
     tmpcr2 &= ~TIM_CR2_OIS1;
- 80062a0:	693b      	ldr	r3, [r7, #16]
- 80062a2:	4a15      	ldr	r2, [pc, #84]	@ (80062f8 <TIM_OC1_SetConfig+0xf8>)
- 80062a4:	4013      	ands	r3, r2
- 80062a6:	613b      	str	r3, [r7, #16]
     tmpcr2 &= ~TIM_CR2_OIS1N;
- 80062a8:	693b      	ldr	r3, [r7, #16]
- 80062aa:	4a14      	ldr	r2, [pc, #80]	@ (80062fc <TIM_OC1_SetConfig+0xfc>)
- 80062ac:	4013      	ands	r3, r2
- 80062ae:	613b      	str	r3, [r7, #16]
     /* Set the Output Idle state */
     tmpcr2 |= OC_Config->OCIdleState;
- 80062b0:	683b      	ldr	r3, [r7, #0]
- 80062b2:	695b      	ldr	r3, [r3, #20]
- 80062b4:	693a      	ldr	r2, [r7, #16]
- 80062b6:	4313      	orrs	r3, r2
- 80062b8:	613b      	str	r3, [r7, #16]
     /* Set the Output N Idle state */
     tmpcr2 |= OC_Config->OCNIdleState;
- 80062ba:	683b      	ldr	r3, [r7, #0]
- 80062bc:	699b      	ldr	r3, [r3, #24]
- 80062be:	693a      	ldr	r2, [r7, #16]
- 80062c0:	4313      	orrs	r3, r2
- 80062c2:	613b      	str	r3, [r7, #16]
-  }
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
- 80062c4:	687b      	ldr	r3, [r7, #4]
- 80062c6:	693a      	ldr	r2, [r7, #16]
- 80062c8:	605a      	str	r2, [r3, #4]
+ 8003914:	698e      	ldr	r6, [r1, #24]
+    tmpccer |= OC_Config->OCNPolarity;
+ 8003916:	4313      	orrs	r3, r2
+    tmpccer &= ~TIM_CCER_CC1NE;
+ 8003918:	2204      	movs	r2, #4
+ 800391a:	4393      	bics	r3, r2
+    tmpcr2 &= ~TIM_CR2_OIS1N;
+ 800391c:	4a09      	ldr	r2, [pc, #36]	@ (8003944 <TIM_OC1_SetConfig+0x68>)
+ 800391e:	4022      	ands	r2, r4
+    tmpcr2 |= OC_Config->OCNIdleState;
+ 8003920:	694c      	ldr	r4, [r1, #20]
+ 8003922:	4334      	orrs	r4, r6
+ 8003924:	4314      	orrs	r4, r2
 
   /* Write to TIMx CCMR1 */
   TIMx->CCMR1 = tmpccmrx;
- 80062ca:	687b      	ldr	r3, [r7, #4]
- 80062cc:	68fa      	ldr	r2, [r7, #12]
- 80062ce:	619a      	str	r2, [r3, #24]
 
   /* Set the Capture Compare Register value */
   TIMx->CCR1 = OC_Config->Pulse;
- 80062d0:	683b      	ldr	r3, [r7, #0]
- 80062d2:	685a      	ldr	r2, [r3, #4]
- 80062d4:	687b      	ldr	r3, [r7, #4]
- 80062d6:	635a      	str	r2, [r3, #52]	@ 0x34
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
- 80062d8:	687b      	ldr	r3, [r7, #4]
- 80062da:	697a      	ldr	r2, [r7, #20]
- 80062dc:	621a      	str	r2, [r3, #32]
-}
- 80062de:	46c0      	nop			@ (mov r8, r8)
- 80062e0:	46bd      	mov	sp, r7
- 80062e2:	b006      	add	sp, #24
- 80062e4:	bd80      	pop	{r7, pc}
- 80062e6:	46c0      	nop			@ (mov r8, r8)
- 80062e8:	fffeff8f 	.word	0xfffeff8f
- 80062ec:	40012c00 	.word	0x40012c00
- 80062f0:	40014400 	.word	0x40014400
- 80062f4:	40014800 	.word	0x40014800
- 80062f8:	fffffeff 	.word	0xfffffeff
- 80062fc:	fffffdff 	.word	0xfffffdff
-
-08006300 <TIM_OC2_SetConfig>:
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config The output configuration structure
-  * @retval None
-  */
-void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
-{
- 8006300:	b580      	push	{r7, lr}
- 8006302:	b086      	sub	sp, #24
- 8006304:	af00      	add	r7, sp, #0
- 8006306:	6078      	str	r0, [r7, #4]
- 8006308:	6039      	str	r1, [r7, #0]
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
- 800630a:	687b      	ldr	r3, [r7, #4]
- 800630c:	6a1b      	ldr	r3, [r3, #32]
- 800630e:	617b      	str	r3, [r7, #20]
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
- 8006310:	687b      	ldr	r3, [r7, #4]
- 8006312:	6a1b      	ldr	r3, [r3, #32]
- 8006314:	2210      	movs	r2, #16
- 8006316:	4393      	bics	r3, r2
- 8006318:	001a      	movs	r2, r3
- 800631a:	687b      	ldr	r3, [r7, #4]
- 800631c:	621a      	str	r2, [r3, #32]
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
- 800631e:	687b      	ldr	r3, [r7, #4]
- 8006320:	685b      	ldr	r3, [r3, #4]
- 8006322:	613b      	str	r3, [r7, #16]
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
- 8006324:	687b      	ldr	r3, [r7, #4]
- 8006326:	699b      	ldr	r3, [r3, #24]
- 8006328:	60fb      	str	r3, [r7, #12]
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC2M;
- 800632a:	68fb      	ldr	r3, [r7, #12]
- 800632c:	4a2c      	ldr	r2, [pc, #176]	@ (80063e0 <TIM_OC2_SetConfig+0xe0>)
- 800632e:	4013      	ands	r3, r2
- 8006330:	60fb      	str	r3, [r7, #12]
-  tmpccmrx &= ~TIM_CCMR1_CC2S;
- 8006332:	68fb      	ldr	r3, [r7, #12]
- 8006334:	4a2b      	ldr	r2, [pc, #172]	@ (80063e4 <TIM_OC2_SetConfig+0xe4>)
- 8006336:	4013      	ands	r3, r2
- 8006338:	60fb      	str	r3, [r7, #12]
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8U);
- 800633a:	683b      	ldr	r3, [r7, #0]
- 800633c:	681b      	ldr	r3, [r3, #0]
- 800633e:	021b      	lsls	r3, r3, #8
- 8006340:	68fa      	ldr	r2, [r7, #12]
- 8006342:	4313      	orrs	r3, r2
- 8006344:	60fb      	str	r3, [r7, #12]
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC2P;
- 8006346:	697b      	ldr	r3, [r7, #20]
- 8006348:	2220      	movs	r2, #32
- 800634a:	4393      	bics	r3, r2
- 800634c:	617b      	str	r3, [r7, #20]
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 4U);
- 800634e:	683b      	ldr	r3, [r7, #0]
- 8006350:	689b      	ldr	r3, [r3, #8]
- 8006352:	011b      	lsls	r3, r3, #4
- 8006354:	697a      	ldr	r2, [r7, #20]
- 8006356:	4313      	orrs	r3, r2
- 8006358:	617b      	str	r3, [r7, #20]
-
-  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
- 800635a:	687b      	ldr	r3, [r7, #4]
- 800635c:	4a22      	ldr	r2, [pc, #136]	@ (80063e8 <TIM_OC2_SetConfig+0xe8>)
- 800635e:	4293      	cmp	r3, r2
- 8006360:	d10d      	bne.n	800637e <TIM_OC2_SetConfig+0x7e>
-  {
-    assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
-
-    /* Reset the Output N Polarity level */
-    tmpccer &= ~TIM_CCER_CC2NP;
- 8006362:	697b      	ldr	r3, [r7, #20]
- 8006364:	2280      	movs	r2, #128	@ 0x80
- 8006366:	4393      	bics	r3, r2
- 8006368:	617b      	str	r3, [r7, #20]
-    /* Set the Output N Polarity */
-    tmpccer |= (OC_Config->OCNPolarity << 4U);
- 800636a:	683b      	ldr	r3, [r7, #0]
- 800636c:	68db      	ldr	r3, [r3, #12]
- 800636e:	011b      	lsls	r3, r3, #4
- 8006370:	697a      	ldr	r2, [r7, #20]
- 8006372:	4313      	orrs	r3, r2
- 8006374:	617b      	str	r3, [r7, #20]
-    /* Reset the Output N State */
-    tmpccer &= ~TIM_CCER_CC2NE;
- 8006376:	697b      	ldr	r3, [r7, #20]
- 8006378:	2240      	movs	r2, #64	@ 0x40
- 800637a:	4393      	bics	r3, r2
- 800637c:	617b      	str	r3, [r7, #20]
-  }
-
-  if (IS_TIM_BREAK_INSTANCE(TIMx))
- 800637e:	687b      	ldr	r3, [r7, #4]
- 8006380:	4a19      	ldr	r2, [pc, #100]	@ (80063e8 <TIM_OC2_SetConfig+0xe8>)
- 8006382:	4293      	cmp	r3, r2
- 8006384:	d007      	beq.n	8006396 <TIM_OC2_SetConfig+0x96>
- 8006386:	687b      	ldr	r3, [r7, #4]
- 8006388:	4a18      	ldr	r2, [pc, #96]	@ (80063ec <TIM_OC2_SetConfig+0xec>)
- 800638a:	4293      	cmp	r3, r2
- 800638c:	d003      	beq.n	8006396 <TIM_OC2_SetConfig+0x96>
- 800638e:	687b      	ldr	r3, [r7, #4]
- 8006390:	4a17      	ldr	r2, [pc, #92]	@ (80063f0 <TIM_OC2_SetConfig+0xf0>)
- 8006392:	4293      	cmp	r3, r2
- 8006394:	d113      	bne.n	80063be <TIM_OC2_SetConfig+0xbe>
-    /* Check parameters */
-    assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
-    assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
-
-    /* Reset the Output Compare and Output Compare N IDLE State */
-    tmpcr2 &= ~TIM_CR2_OIS2;
- 8006396:	693b      	ldr	r3, [r7, #16]
- 8006398:	4a16      	ldr	r2, [pc, #88]	@ (80063f4 <TIM_OC2_SetConfig+0xf4>)
- 800639a:	4013      	ands	r3, r2
- 800639c:	613b      	str	r3, [r7, #16]
-    tmpcr2 &= ~TIM_CR2_OIS2N;
- 800639e:	693b      	ldr	r3, [r7, #16]
- 80063a0:	4a15      	ldr	r2, [pc, #84]	@ (80063f8 <TIM_OC2_SetConfig+0xf8>)
- 80063a2:	4013      	ands	r3, r2
- 80063a4:	613b      	str	r3, [r7, #16]
-    /* Set the Output Idle state */
-    tmpcr2 |= (OC_Config->OCIdleState << 2U);
- 80063a6:	683b      	ldr	r3, [r7, #0]
- 80063a8:	695b      	ldr	r3, [r3, #20]
- 80063aa:	009b      	lsls	r3, r3, #2
- 80063ac:	693a      	ldr	r2, [r7, #16]
- 80063ae:	4313      	orrs	r3, r2
- 80063b0:	613b      	str	r3, [r7, #16]
-    /* Set the Output N Idle state */
-    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
- 80063b2:	683b      	ldr	r3, [r7, #0]
- 80063b4:	699b      	ldr	r3, [r3, #24]
- 80063b6:	009b      	lsls	r3, r3, #2
- 80063b8:	693a      	ldr	r2, [r7, #16]
- 80063ba:	4313      	orrs	r3, r2
- 80063bc:	613b      	str	r3, [r7, #16]
-  }
-
-  /* Write to TIMx CR2 */
+ 8003926:	684a      	ldr	r2, [r1, #4]
   TIMx->CR2 = tmpcr2;
- 80063be:	687b      	ldr	r3, [r7, #4]
- 80063c0:	693a      	ldr	r2, [r7, #16]
- 80063c2:	605a      	str	r2, [r3, #4]
-
-  /* Write to TIMx CCMR1 */
+ 8003928:	6044      	str	r4, [r0, #4]
   TIMx->CCMR1 = tmpccmrx;
- 80063c4:	687b      	ldr	r3, [r7, #4]
- 80063c6:	68fa      	ldr	r2, [r7, #12]
- 80063c8:	619a      	str	r2, [r3, #24]
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR2 = OC_Config->Pulse;
- 80063ca:	683b      	ldr	r3, [r7, #0]
- 80063cc:	685a      	ldr	r2, [r3, #4]
- 80063ce:	687b      	ldr	r3, [r7, #4]
- 80063d0:	639a      	str	r2, [r3, #56]	@ 0x38
+ 800392a:	6185      	str	r5, [r0, #24]
+  TIMx->CCR1 = OC_Config->Pulse;
+ 800392c:	6342      	str	r2, [r0, #52]	@ 0x34
 
   /* Write to TIMx CCER */
   TIMx->CCER = tmpccer;
- 80063d2:	687b      	ldr	r3, [r7, #4]
- 80063d4:	697a      	ldr	r2, [r7, #20]
- 80063d6:	621a      	str	r2, [r3, #32]
+ 800392e:	6203      	str	r3, [r0, #32]
 }
- 80063d8:	46c0      	nop			@ (mov r8, r8)
- 80063da:	46bd      	mov	sp, r7
- 80063dc:	b006      	add	sp, #24
- 80063de:	bd80      	pop	{r7, pc}
- 80063e0:	feff8fff 	.word	0xfeff8fff
- 80063e4:	fffffcff 	.word	0xfffffcff
- 80063e8:	40012c00 	.word	0x40012c00
- 80063ec:	40014400 	.word	0x40014400
- 80063f0:	40014800 	.word	0x40014800
- 80063f4:	fffffbff 	.word	0xfffffbff
- 80063f8:	fffff7ff 	.word	0xfffff7ff
+ 8003930:	bd70      	pop	{r4, r5, r6, pc}
+ 8003932:	46c0      	nop			@ (mov r8, r8)
+ 8003934:	fffeff8c 	.word	0xfffeff8c
+ 8003938:	40012c00 	.word	0x40012c00
+ 800393c:	40014400 	.word	0x40014400
+ 8003940:	40014800 	.word	0x40014800
+ 8003944:	fffffcff 	.word	0xfffffcff
 
-080063fc <TIM_OC3_SetConfig>:
+08003948 <TIM_OC3_SetConfig>:
   * @param  TIMx to select the TIM peripheral
   * @param  OC_Config The output configuration structure
   * @retval None
   */
 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
 {
- 80063fc:	b580      	push	{r7, lr}
- 80063fe:	b086      	sub	sp, #24
- 8006400:	af00      	add	r7, sp, #0
- 8006402:	6078      	str	r0, [r7, #4]
- 8006404:	6039      	str	r1, [r7, #0]
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
+ 8003948:	b570      	push	{r4, r5, r6, lr}
 
   /* Get the TIMx CCER register value */
   tmpccer = TIMx->CCER;
- 8006406:	687b      	ldr	r3, [r7, #4]
- 8006408:	6a1b      	ldr	r3, [r3, #32]
- 800640a:	617b      	str	r3, [r7, #20]
 
   /* Disable the Channel 3: Reset the CC2E Bit */
   TIMx->CCER &= ~TIM_CCER_CC3E;
- 800640c:	687b      	ldr	r3, [r7, #4]
- 800640e:	6a1b      	ldr	r3, [r3, #32]
- 8006410:	4a31      	ldr	r2, [pc, #196]	@ (80064d8 <TIM_OC3_SetConfig+0xdc>)
- 8006412:	401a      	ands	r2, r3
- 8006414:	687b      	ldr	r3, [r7, #4]
- 8006416:	621a      	str	r2, [r3, #32]
+ 800394a:	4a17      	ldr	r2, [pc, #92]	@ (80039a8 <TIM_OC3_SetConfig+0x60>)
+  tmpccer = TIMx->CCER;
+ 800394c:	6a05      	ldr	r5, [r0, #32]
+  TIMx->CCER &= ~TIM_CCER_CC3E;
+ 800394e:	6a03      	ldr	r3, [r0, #32]
+ 8003950:	4013      	ands	r3, r2
+ 8003952:	6203      	str	r3, [r0, #32]
 
   /* Get the TIMx CR2 register value */
   tmpcr2 =  TIMx->CR2;
- 8006418:	687b      	ldr	r3, [r7, #4]
- 800641a:	685b      	ldr	r3, [r3, #4]
- 800641c:	613b      	str	r3, [r7, #16]
-
+ 8003954:	6842      	ldr	r2, [r0, #4]
   /* Get the TIMx CCMR2 register value */
   tmpccmrx = TIMx->CCMR2;
- 800641e:	687b      	ldr	r3, [r7, #4]
- 8006420:	69db      	ldr	r3, [r3, #28]
- 8006422:	60fb      	str	r3, [r7, #12]
 
   /* Reset the Output Compare mode and Capture/Compare selection Bits */
   tmpccmrx &= ~TIM_CCMR2_OC3M;
- 8006424:	68fb      	ldr	r3, [r7, #12]
- 8006426:	4a2d      	ldr	r2, [pc, #180]	@ (80064dc <TIM_OC3_SetConfig+0xe0>)
- 8006428:	4013      	ands	r3, r2
- 800642a:	60fb      	str	r3, [r7, #12]
   tmpccmrx &= ~TIM_CCMR2_CC3S;
- 800642c:	68fb      	ldr	r3, [r7, #12]
- 800642e:	2203      	movs	r2, #3
- 8006430:	4393      	bics	r3, r2
- 8006432:	60fb      	str	r3, [r7, #12]
+ 8003956:	4b15      	ldr	r3, [pc, #84]	@ (80039ac <TIM_OC3_SetConfig+0x64>)
+  tmpccmrx = TIMx->CCMR2;
+ 8003958:	69c4      	ldr	r4, [r0, #28]
+  tmpccmrx &= ~TIM_CCMR2_CC3S;
+ 800395a:	401c      	ands	r4, r3
   /* Select the Output Compare Mode */
   tmpccmrx |= OC_Config->OCMode;
- 8006434:	683b      	ldr	r3, [r7, #0]
- 8006436:	681b      	ldr	r3, [r3, #0]
- 8006438:	68fa      	ldr	r2, [r7, #12]
- 800643a:	4313      	orrs	r3, r2
- 800643c:	60fb      	str	r3, [r7, #12]
+ 800395c:	680b      	ldr	r3, [r1, #0]
+ 800395e:	431c      	orrs	r4, r3
 
   /* Reset the Output Polarity level */
   tmpccer &= ~TIM_CCER_CC3P;
- 800643e:	697b      	ldr	r3, [r7, #20]
- 8006440:	4a27      	ldr	r2, [pc, #156]	@ (80064e0 <TIM_OC3_SetConfig+0xe4>)
- 8006442:	4013      	ands	r3, r2
- 8006444:	617b      	str	r3, [r7, #20]
+ 8003960:	4b13      	ldr	r3, [pc, #76]	@ (80039b0 <TIM_OC3_SetConfig+0x68>)
+ 8003962:	401d      	ands	r5, r3
   /* Set the Output Compare Polarity */
   tmpccer |= (OC_Config->OCPolarity << 8U);
- 8006446:	683b      	ldr	r3, [r7, #0]
- 8006448:	689b      	ldr	r3, [r3, #8]
- 800644a:	021b      	lsls	r3, r3, #8
- 800644c:	697a      	ldr	r2, [r7, #20]
- 800644e:	4313      	orrs	r3, r2
- 8006450:	617b      	str	r3, [r7, #20]
+ 8003964:	688b      	ldr	r3, [r1, #8]
+ 8003966:	021b      	lsls	r3, r3, #8
+ 8003968:	432b      	orrs	r3, r5
 
   if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
- 8006452:	687b      	ldr	r3, [r7, #4]
- 8006454:	4a23      	ldr	r2, [pc, #140]	@ (80064e4 <TIM_OC3_SetConfig+0xe8>)
- 8006456:	4293      	cmp	r3, r2
- 8006458:	d10d      	bne.n	8006476 <TIM_OC3_SetConfig+0x7a>
+ 800396a:	4d12      	ldr	r5, [pc, #72]	@ (80039b4 <TIM_OC3_SetConfig+0x6c>)
+ 800396c:	42a8      	cmp	r0, r5
+ 800396e:	d10e      	bne.n	800398e <TIM_OC3_SetConfig+0x46>
   {
     assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
 
     /* Reset the Output N Polarity level */
     tmpccer &= ~TIM_CCER_CC3NP;
- 800645a:	697b      	ldr	r3, [r7, #20]
- 800645c:	4a22      	ldr	r2, [pc, #136]	@ (80064e8 <TIM_OC3_SetConfig+0xec>)
- 800645e:	4013      	ands	r3, r2
- 8006460:	617b      	str	r3, [r7, #20]
+ 8003970:	4d11      	ldr	r5, [pc, #68]	@ (80039b8 <TIM_OC3_SetConfig+0x70>)
+ 8003972:	401d      	ands	r5, r3
     /* Set the Output N Polarity */
     tmpccer |= (OC_Config->OCNPolarity << 8U);
- 8006462:	683b      	ldr	r3, [r7, #0]
- 8006464:	68db      	ldr	r3, [r3, #12]
- 8006466:	021b      	lsls	r3, r3, #8
- 8006468:	697a      	ldr	r2, [r7, #20]
- 800646a:	4313      	orrs	r3, r2
- 800646c:	617b      	str	r3, [r7, #20]
+ 8003974:	68cb      	ldr	r3, [r1, #12]
+ 8003976:	021b      	lsls	r3, r3, #8
+ 8003978:	432b      	orrs	r3, r5
     /* Reset the Output N State */
     tmpccer &= ~TIM_CCER_CC3NE;
- 800646e:	697b      	ldr	r3, [r7, #20]
- 8006470:	4a1e      	ldr	r2, [pc, #120]	@ (80064ec <TIM_OC3_SetConfig+0xf0>)
- 8006472:	4013      	ands	r3, r2
- 8006474:	617b      	str	r3, [r7, #20]
-  }
-
-  if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8006476:	687b      	ldr	r3, [r7, #4]
- 8006478:	4a1a      	ldr	r2, [pc, #104]	@ (80064e4 <TIM_OC3_SetConfig+0xe8>)
- 800647a:	4293      	cmp	r3, r2
- 800647c:	d007      	beq.n	800648e <TIM_OC3_SetConfig+0x92>
- 800647e:	687b      	ldr	r3, [r7, #4]
- 8006480:	4a1b      	ldr	r2, [pc, #108]	@ (80064f0 <TIM_OC3_SetConfig+0xf4>)
- 8006482:	4293      	cmp	r3, r2
- 8006484:	d003      	beq.n	800648e <TIM_OC3_SetConfig+0x92>
- 8006486:	687b      	ldr	r3, [r7, #4]
- 8006488:	4a1a      	ldr	r2, [pc, #104]	@ (80064f4 <TIM_OC3_SetConfig+0xf8>)
- 800648a:	4293      	cmp	r3, r2
- 800648c:	d113      	bne.n	80064b6 <TIM_OC3_SetConfig+0xba>
-    /* Check parameters */
+ 800397a:	4d10      	ldr	r5, [pc, #64]	@ (80039bc <TIM_OC3_SetConfig+0x74>)
+ 800397c:	402b      	ands	r3, r5
     assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
 
     /* Reset the Output Compare and Output Compare N IDLE State */
     tmpcr2 &= ~TIM_CR2_OIS3;
- 800648e:	693b      	ldr	r3, [r7, #16]
- 8006490:	4a19      	ldr	r2, [pc, #100]	@ (80064f8 <TIM_OC3_SetConfig+0xfc>)
- 8006492:	4013      	ands	r3, r2
- 8006494:	613b      	str	r3, [r7, #16]
     tmpcr2 &= ~TIM_CR2_OIS3N;
- 8006496:	693b      	ldr	r3, [r7, #16]
- 8006498:	4a18      	ldr	r2, [pc, #96]	@ (80064fc <TIM_OC3_SetConfig+0x100>)
- 800649a:	4013      	ands	r3, r2
- 800649c:	613b      	str	r3, [r7, #16]
+ 800397e:	4d10      	ldr	r5, [pc, #64]	@ (80039c0 <TIM_OC3_SetConfig+0x78>)
     /* Set the Output Idle state */
     tmpcr2 |= (OC_Config->OCIdleState << 4U);
- 800649e:	683b      	ldr	r3, [r7, #0]
- 80064a0:	695b      	ldr	r3, [r3, #20]
- 80064a2:	011b      	lsls	r3, r3, #4
- 80064a4:	693a      	ldr	r2, [r7, #16]
- 80064a6:	4313      	orrs	r3, r2
- 80064a8:	613b      	str	r3, [r7, #16]
     /* Set the Output N Idle state */
     tmpcr2 |= (OC_Config->OCNIdleState << 4U);
- 80064aa:	683b      	ldr	r3, [r7, #0]
- 80064ac:	699b      	ldr	r3, [r3, #24]
- 80064ae:	011b      	lsls	r3, r3, #4
- 80064b0:	693a      	ldr	r2, [r7, #16]
- 80064b2:	4313      	orrs	r3, r2
- 80064b4:	613b      	str	r3, [r7, #16]
+ 8003980:	698e      	ldr	r6, [r1, #24]
+    tmpcr2 &= ~TIM_CR2_OIS3N;
+ 8003982:	4015      	ands	r5, r2
+    tmpcr2 |= (OC_Config->OCNIdleState << 4U);
+ 8003984:	694a      	ldr	r2, [r1, #20]
+ 8003986:	4332      	orrs	r2, r6
+ 8003988:	0112      	lsls	r2, r2, #4
+ 800398a:	432a      	orrs	r2, r5
+ 800398c:	e005      	b.n	800399a <TIM_OC3_SetConfig+0x52>
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 800398e:	4d0d      	ldr	r5, [pc, #52]	@ (80039c4 <TIM_OC3_SetConfig+0x7c>)
+ 8003990:	42a8      	cmp	r0, r5
+ 8003992:	d0f4      	beq.n	800397e <TIM_OC3_SetConfig+0x36>
+ 8003994:	4d0c      	ldr	r5, [pc, #48]	@ (80039c8 <TIM_OC3_SetConfig+0x80>)
+ 8003996:	42a8      	cmp	r0, r5
+ 8003998:	d0f1      	beq.n	800397e <TIM_OC3_SetConfig+0x36>
   }
 
   /* Write to TIMx CR2 */
   TIMx->CR2 = tmpcr2;
- 80064b6:	687b      	ldr	r3, [r7, #4]
- 80064b8:	693a      	ldr	r2, [r7, #16]
- 80064ba:	605a      	str	r2, [r3, #4]
+ 800399a:	6042      	str	r2, [r0, #4]
 
   /* Write to TIMx CCMR2 */
   TIMx->CCMR2 = tmpccmrx;
- 80064bc:	687b      	ldr	r3, [r7, #4]
- 80064be:	68fa      	ldr	r2, [r7, #12]
- 80064c0:	61da      	str	r2, [r3, #28]
 
   /* Set the Capture Compare Register value */
   TIMx->CCR3 = OC_Config->Pulse;
- 80064c2:	683b      	ldr	r3, [r7, #0]
- 80064c4:	685a      	ldr	r2, [r3, #4]
- 80064c6:	687b      	ldr	r3, [r7, #4]
- 80064c8:	63da      	str	r2, [r3, #60]	@ 0x3c
+ 800399c:	684a      	ldr	r2, [r1, #4]
+  TIMx->CCMR2 = tmpccmrx;
+ 800399e:	61c4      	str	r4, [r0, #28]
+  TIMx->CCR3 = OC_Config->Pulse;
+ 80039a0:	63c2      	str	r2, [r0, #60]	@ 0x3c
 
   /* Write to TIMx CCER */
   TIMx->CCER = tmpccer;
- 80064ca:	687b      	ldr	r3, [r7, #4]
- 80064cc:	697a      	ldr	r2, [r7, #20]
- 80064ce:	621a      	str	r2, [r3, #32]
+ 80039a2:	6203      	str	r3, [r0, #32]
 }
- 80064d0:	46c0      	nop			@ (mov r8, r8)
- 80064d2:	46bd      	mov	sp, r7
- 80064d4:	b006      	add	sp, #24
- 80064d6:	bd80      	pop	{r7, pc}
- 80064d8:	fffffeff 	.word	0xfffffeff
- 80064dc:	fffeff8f 	.word	0xfffeff8f
- 80064e0:	fffffdff 	.word	0xfffffdff
- 80064e4:	40012c00 	.word	0x40012c00
- 80064e8:	fffff7ff 	.word	0xfffff7ff
- 80064ec:	fffffbff 	.word	0xfffffbff
- 80064f0:	40014400 	.word	0x40014400
- 80064f4:	40014800 	.word	0x40014800
- 80064f8:	ffffefff 	.word	0xffffefff
- 80064fc:	ffffdfff 	.word	0xffffdfff
+ 80039a4:	bd70      	pop	{r4, r5, r6, pc}
+ 80039a6:	46c0      	nop			@ (mov r8, r8)
+ 80039a8:	fffffeff 	.word	0xfffffeff
+ 80039ac:	fffeff8c 	.word	0xfffeff8c
+ 80039b0:	fffffdff 	.word	0xfffffdff
+ 80039b4:	40012c00 	.word	0x40012c00
+ 80039b8:	fffff7ff 	.word	0xfffff7ff
+ 80039bc:	fffffbff 	.word	0xfffffbff
+ 80039c0:	ffffcfff 	.word	0xffffcfff
+ 80039c4:	40014400 	.word	0x40014400
+ 80039c8:	40014800 	.word	0x40014800
 
-08006500 <TIM_OC4_SetConfig>:
+080039cc <TIM_OC4_SetConfig>:
   * @param  TIMx to select the TIM peripheral
   * @param  OC_Config The output configuration structure
   * @retval None
   */
 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
 {
- 8006500:	b580      	push	{r7, lr}
- 8006502:	b086      	sub	sp, #24
- 8006504:	af00      	add	r7, sp, #0
- 8006506:	6078      	str	r0, [r7, #4]
- 8006508:	6039      	str	r1, [r7, #0]
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
+ 80039cc:	b530      	push	{r4, r5, lr}
 
   /* Get the TIMx CCER register value */
   tmpccer = TIMx->CCER;
- 800650a:	687b      	ldr	r3, [r7, #4]
- 800650c:	6a1b      	ldr	r3, [r3, #32]
- 800650e:	613b      	str	r3, [r7, #16]
 
   /* Disable the Channel 4: Reset the CC4E Bit */
   TIMx->CCER &= ~TIM_CCER_CC4E;
- 8006510:	687b      	ldr	r3, [r7, #4]
- 8006512:	6a1b      	ldr	r3, [r3, #32]
- 8006514:	4a24      	ldr	r2, [pc, #144]	@ (80065a8 <TIM_OC4_SetConfig+0xa8>)
- 8006516:	401a      	ands	r2, r3
- 8006518:	687b      	ldr	r3, [r7, #4]
- 800651a:	621a      	str	r2, [r3, #32]
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
- 800651c:	687b      	ldr	r3, [r7, #4]
- 800651e:	685b      	ldr	r3, [r3, #4]
- 8006520:	617b      	str	r3, [r7, #20]
-
+ 80039ce:	4a12      	ldr	r2, [pc, #72]	@ (8003a18 <TIM_OC4_SetConfig+0x4c>)
+  tmpccer = TIMx->CCER;
+ 80039d0:	6a04      	ldr	r4, [r0, #32]
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+ 80039d2:	6a03      	ldr	r3, [r0, #32]
   /* Get the TIMx CCMR2 register value */
   tmpccmrx = TIMx->CCMR2;
- 8006522:	687b      	ldr	r3, [r7, #4]
- 8006524:	69db      	ldr	r3, [r3, #28]
- 8006526:	60fb      	str	r3, [r7, #12]
 
   /* Reset the Output Compare mode and Capture/Compare selection Bits */
   tmpccmrx &= ~TIM_CCMR2_OC4M;
- 8006528:	68fb      	ldr	r3, [r7, #12]
- 800652a:	4a20      	ldr	r2, [pc, #128]	@ (80065ac <TIM_OC4_SetConfig+0xac>)
- 800652c:	4013      	ands	r3, r2
- 800652e:	60fb      	str	r3, [r7, #12]
   tmpccmrx &= ~TIM_CCMR2_CC4S;
- 8006530:	68fb      	ldr	r3, [r7, #12]
- 8006532:	4a1f      	ldr	r2, [pc, #124]	@ (80065b0 <TIM_OC4_SetConfig+0xb0>)
- 8006534:	4013      	ands	r3, r2
- 8006536:	60fb      	str	r3, [r7, #12]
+ 80039d4:	4d11      	ldr	r5, [pc, #68]	@ (8003a1c <TIM_OC4_SetConfig+0x50>)
+  TIMx->CCER &= ~TIM_CCER_CC4E;
+ 80039d6:	4013      	ands	r3, r2
+ 80039d8:	6203      	str	r3, [r0, #32]
+  tmpcr2 =  TIMx->CR2;
+ 80039da:	6843      	ldr	r3, [r0, #4]
+  tmpccmrx = TIMx->CCMR2;
+ 80039dc:	69c2      	ldr	r2, [r0, #28]
+  tmpccmrx &= ~TIM_CCMR2_CC4S;
+ 80039de:	402a      	ands	r2, r5
 
   /* Select the Output Compare Mode */
   tmpccmrx |= (OC_Config->OCMode << 8U);
- 8006538:	683b      	ldr	r3, [r7, #0]
- 800653a:	681b      	ldr	r3, [r3, #0]
- 800653c:	021b      	lsls	r3, r3, #8
- 800653e:	68fa      	ldr	r2, [r7, #12]
- 8006540:	4313      	orrs	r3, r2
- 8006542:	60fb      	str	r3, [r7, #12]
+ 80039e0:	680d      	ldr	r5, [r1, #0]
+ 80039e2:	022d      	lsls	r5, r5, #8
+ 80039e4:	4315      	orrs	r5, r2
 
   /* Reset the Output Polarity level */
   tmpccer &= ~TIM_CCER_CC4P;
- 8006544:	693b      	ldr	r3, [r7, #16]
- 8006546:	4a1b      	ldr	r2, [pc, #108]	@ (80065b4 <TIM_OC4_SetConfig+0xb4>)
- 8006548:	4013      	ands	r3, r2
- 800654a:	613b      	str	r3, [r7, #16]
+ 80039e6:	4a0e      	ldr	r2, [pc, #56]	@ (8003a20 <TIM_OC4_SetConfig+0x54>)
+ 80039e8:	4014      	ands	r4, r2
   /* Set the Output Compare Polarity */
   tmpccer |= (OC_Config->OCPolarity << 12U);
- 800654c:	683b      	ldr	r3, [r7, #0]
- 800654e:	689b      	ldr	r3, [r3, #8]
- 8006550:	031b      	lsls	r3, r3, #12
- 8006552:	693a      	ldr	r2, [r7, #16]
- 8006554:	4313      	orrs	r3, r2
- 8006556:	613b      	str	r3, [r7, #16]
+ 80039ea:	688a      	ldr	r2, [r1, #8]
+ 80039ec:	0312      	lsls	r2, r2, #12
+ 80039ee:	4322      	orrs	r2, r4
 
   if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8006558:	687b      	ldr	r3, [r7, #4]
- 800655a:	4a17      	ldr	r2, [pc, #92]	@ (80065b8 <TIM_OC4_SetConfig+0xb8>)
- 800655c:	4293      	cmp	r3, r2
- 800655e:	d007      	beq.n	8006570 <TIM_OC4_SetConfig+0x70>
- 8006560:	687b      	ldr	r3, [r7, #4]
- 8006562:	4a16      	ldr	r2, [pc, #88]	@ (80065bc <TIM_OC4_SetConfig+0xbc>)
- 8006564:	4293      	cmp	r3, r2
- 8006566:	d003      	beq.n	8006570 <TIM_OC4_SetConfig+0x70>
- 8006568:	687b      	ldr	r3, [r7, #4]
- 800656a:	4a15      	ldr	r2, [pc, #84]	@ (80065c0 <TIM_OC4_SetConfig+0xc0>)
- 800656c:	4293      	cmp	r3, r2
- 800656e:	d109      	bne.n	8006584 <TIM_OC4_SetConfig+0x84>
+ 80039f0:	4c0c      	ldr	r4, [pc, #48]	@ (8003a24 <TIM_OC4_SetConfig+0x58>)
+ 80039f2:	42a0      	cmp	r0, r4
+ 80039f4:	d005      	beq.n	8003a02 <TIM_OC4_SetConfig+0x36>
+ 80039f6:	4c0c      	ldr	r4, [pc, #48]	@ (8003a28 <TIM_OC4_SetConfig+0x5c>)
+ 80039f8:	42a0      	cmp	r0, r4
+ 80039fa:	d002      	beq.n	8003a02 <TIM_OC4_SetConfig+0x36>
+ 80039fc:	4c0b      	ldr	r4, [pc, #44]	@ (8003a2c <TIM_OC4_SetConfig+0x60>)
+ 80039fe:	42a0      	cmp	r0, r4
+ 8003a00:	d104      	bne.n	8003a0c <TIM_OC4_SetConfig+0x40>
   {
     /* Check parameters */
     assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
 
     /* Reset the Output Compare IDLE State */
     tmpcr2 &= ~TIM_CR2_OIS4;
- 8006570:	697b      	ldr	r3, [r7, #20]
- 8006572:	4a14      	ldr	r2, [pc, #80]	@ (80065c4 <TIM_OC4_SetConfig+0xc4>)
- 8006574:	4013      	ands	r3, r2
- 8006576:	617b      	str	r3, [r7, #20]
+ 8003a02:	4c0b      	ldr	r4, [pc, #44]	@ (8003a30 <TIM_OC4_SetConfig+0x64>)
+ 8003a04:	401c      	ands	r4, r3
 
     /* Set the Output Idle state */
     tmpcr2 |= (OC_Config->OCIdleState << 6U);
- 8006578:	683b      	ldr	r3, [r7, #0]
- 800657a:	695b      	ldr	r3, [r3, #20]
- 800657c:	019b      	lsls	r3, r3, #6
- 800657e:	697a      	ldr	r2, [r7, #20]
- 8006580:	4313      	orrs	r3, r2
- 8006582:	617b      	str	r3, [r7, #20]
+ 8003a06:	694b      	ldr	r3, [r1, #20]
+ 8003a08:	019b      	lsls	r3, r3, #6
+ 8003a0a:	4323      	orrs	r3, r4
   }
 
   /* Write to TIMx CR2 */
   TIMx->CR2 = tmpcr2;
- 8006584:	687b      	ldr	r3, [r7, #4]
- 8006586:	697a      	ldr	r2, [r7, #20]
- 8006588:	605a      	str	r2, [r3, #4]
+ 8003a0c:	6043      	str	r3, [r0, #4]
 
   /* Write to TIMx CCMR2 */
   TIMx->CCMR2 = tmpccmrx;
- 800658a:	687b      	ldr	r3, [r7, #4]
- 800658c:	68fa      	ldr	r2, [r7, #12]
- 800658e:	61da      	str	r2, [r3, #28]
 
   /* Set the Capture Compare Register value */
   TIMx->CCR4 = OC_Config->Pulse;
- 8006590:	683b      	ldr	r3, [r7, #0]
- 8006592:	685a      	ldr	r2, [r3, #4]
- 8006594:	687b      	ldr	r3, [r7, #4]
- 8006596:	641a      	str	r2, [r3, #64]	@ 0x40
+ 8003a0e:	684b      	ldr	r3, [r1, #4]
+  TIMx->CCMR2 = tmpccmrx;
+ 8003a10:	61c5      	str	r5, [r0, #28]
+  TIMx->CCR4 = OC_Config->Pulse;
+ 8003a12:	6403      	str	r3, [r0, #64]	@ 0x40
 
   /* Write to TIMx CCER */
   TIMx->CCER = tmpccer;
- 8006598:	687b      	ldr	r3, [r7, #4]
- 800659a:	693a      	ldr	r2, [r7, #16]
- 800659c:	621a      	str	r2, [r3, #32]
+ 8003a14:	6202      	str	r2, [r0, #32]
 }
- 800659e:	46c0      	nop			@ (mov r8, r8)
- 80065a0:	46bd      	mov	sp, r7
- 80065a2:	b006      	add	sp, #24
- 80065a4:	bd80      	pop	{r7, pc}
- 80065a6:	46c0      	nop			@ (mov r8, r8)
- 80065a8:	ffffefff 	.word	0xffffefff
- 80065ac:	feff8fff 	.word	0xfeff8fff
- 80065b0:	fffffcff 	.word	0xfffffcff
- 80065b4:	ffffdfff 	.word	0xffffdfff
- 80065b8:	40012c00 	.word	0x40012c00
- 80065bc:	40014400 	.word	0x40014400
- 80065c0:	40014800 	.word	0x40014800
- 80065c4:	ffffbfff 	.word	0xffffbfff
+ 8003a16:	bd30      	pop	{r4, r5, pc}
+ 8003a18:	ffffefff 	.word	0xffffefff
+ 8003a1c:	feff8cff 	.word	0xfeff8cff
+ 8003a20:	ffffdfff 	.word	0xffffdfff
+ 8003a24:	40012c00 	.word	0x40012c00
+ 8003a28:	40014400 	.word	0x40014400
+ 8003a2c:	40014800 	.word	0x40014800
+ 8003a30:	ffffbfff 	.word	0xffffbfff
 
-080065c8 <TIM_OC5_SetConfig>:
+08003a34 <TIM_OC5_SetConfig>:
   * @param  OC_Config The output configuration structure
   * @retval None
   */
 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
                               const TIM_OC_InitTypeDef *OC_Config)
 {
- 80065c8:	b580      	push	{r7, lr}
- 80065ca:	b086      	sub	sp, #24
- 80065cc:	af00      	add	r7, sp, #0
- 80065ce:	6078      	str	r0, [r7, #4]
- 80065d0:	6039      	str	r1, [r7, #0]
+ 8003a34:	b570      	push	{r4, r5, r6, lr}
   uint32_t tmpccmrx;
   uint32_t tmpccer;
   uint32_t tmpcr2;
 
   /* Get the TIMx CCER register value */
   tmpccer = TIMx->CCER;
- 80065d2:	687b      	ldr	r3, [r7, #4]
- 80065d4:	6a1b      	ldr	r3, [r3, #32]
- 80065d6:	613b      	str	r3, [r7, #16]
+ 8003a36:	6a06      	ldr	r6, [r0, #32]
 
   /* Disable the output: Reset the CCxE Bit */
   TIMx->CCER &= ~TIM_CCER_CC5E;
- 80065d8:	687b      	ldr	r3, [r7, #4]
- 80065da:	6a1b      	ldr	r3, [r3, #32]
- 80065dc:	4a21      	ldr	r2, [pc, #132]	@ (8006664 <TIM_OC5_SetConfig+0x9c>)
- 80065de:	401a      	ands	r2, r3
- 80065e0:	687b      	ldr	r3, [r7, #4]
- 80065e2:	621a      	str	r2, [r3, #32]
-
-  /* Get the TIMx CR2 register value */
+ 8003a38:	4c10      	ldr	r4, [pc, #64]	@ (8003a7c <TIM_OC5_SetConfig+0x48>)
+ 8003a3a:	6a03      	ldr	r3, [r0, #32]
   tmpcr2 =  TIMx->CR2;
- 80065e4:	687b      	ldr	r3, [r7, #4]
- 80065e6:	685b      	ldr	r3, [r3, #4]
- 80065e8:	617b      	str	r3, [r7, #20]
   /* Get the TIMx CCMR1 register value */
   tmpccmrx = TIMx->CCMR3;
- 80065ea:	687b      	ldr	r3, [r7, #4]
- 80065ec:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
- 80065ee:	60fb      	str	r3, [r7, #12]
 
   /* Reset the Output Compare Mode Bits */
   tmpccmrx &= ~(TIM_CCMR3_OC5M);
- 80065f0:	68fb      	ldr	r3, [r7, #12]
- 80065f2:	4a1d      	ldr	r2, [pc, #116]	@ (8006668 <TIM_OC5_SetConfig+0xa0>)
- 80065f4:	4013      	ands	r3, r2
- 80065f6:	60fb      	str	r3, [r7, #12]
+ 8003a3c:	4a10      	ldr	r2, [pc, #64]	@ (8003a80 <TIM_OC5_SetConfig+0x4c>)
+  TIMx->CCER &= ~TIM_CCER_CC5E;
+ 8003a3e:	4023      	ands	r3, r4
+ 8003a40:	6203      	str	r3, [r0, #32]
+  tmpcr2 =  TIMx->CR2;
+ 8003a42:	6843      	ldr	r3, [r0, #4]
+  tmpccmrx = TIMx->CCMR3;
+ 8003a44:	6d45      	ldr	r5, [r0, #84]	@ 0x54
+  tmpccmrx &= ~(TIM_CCMR3_OC5M);
+ 8003a46:	4015      	ands	r5, r2
   /* Select the Output Compare Mode */
   tmpccmrx |= OC_Config->OCMode;
- 80065f8:	683b      	ldr	r3, [r7, #0]
- 80065fa:	681b      	ldr	r3, [r3, #0]
- 80065fc:	68fa      	ldr	r2, [r7, #12]
- 80065fe:	4313      	orrs	r3, r2
- 8006600:	60fb      	str	r3, [r7, #12]
+ 8003a48:	680a      	ldr	r2, [r1, #0]
+ 8003a4a:	4315      	orrs	r5, r2
 
   /* Reset the Output Polarity level */
   tmpccer &= ~TIM_CCER_CC5P;
- 8006602:	693b      	ldr	r3, [r7, #16]
- 8006604:	4a19      	ldr	r2, [pc, #100]	@ (800666c <TIM_OC5_SetConfig+0xa4>)
- 8006606:	4013      	ands	r3, r2
- 8006608:	613b      	str	r3, [r7, #16]
+ 8003a4c:	4a0d      	ldr	r2, [pc, #52]	@ (8003a84 <TIM_OC5_SetConfig+0x50>)
+ 8003a4e:	4016      	ands	r6, r2
   /* Set the Output Compare Polarity */
   tmpccer |= (OC_Config->OCPolarity << 16U);
- 800660a:	683b      	ldr	r3, [r7, #0]
- 800660c:	689b      	ldr	r3, [r3, #8]
- 800660e:	041b      	lsls	r3, r3, #16
- 8006610:	693a      	ldr	r2, [r7, #16]
- 8006612:	4313      	orrs	r3, r2
- 8006614:	613b      	str	r3, [r7, #16]
+ 8003a50:	688a      	ldr	r2, [r1, #8]
+ 8003a52:	0412      	lsls	r2, r2, #16
+ 8003a54:	4332      	orrs	r2, r6
 
   if (IS_TIM_BREAK_INSTANCE(TIMx))
- 8006616:	687b      	ldr	r3, [r7, #4]
- 8006618:	4a15      	ldr	r2, [pc, #84]	@ (8006670 <TIM_OC5_SetConfig+0xa8>)
- 800661a:	4293      	cmp	r3, r2
- 800661c:	d007      	beq.n	800662e <TIM_OC5_SetConfig+0x66>
- 800661e:	687b      	ldr	r3, [r7, #4]
- 8006620:	4a14      	ldr	r2, [pc, #80]	@ (8006674 <TIM_OC5_SetConfig+0xac>)
- 8006622:	4293      	cmp	r3, r2
- 8006624:	d003      	beq.n	800662e <TIM_OC5_SetConfig+0x66>
- 8006626:	687b      	ldr	r3, [r7, #4]
- 8006628:	4a13      	ldr	r2, [pc, #76]	@ (8006678 <TIM_OC5_SetConfig+0xb0>)
- 800662a:	4293      	cmp	r3, r2
- 800662c:	d109      	bne.n	8006642 <TIM_OC5_SetConfig+0x7a>
+ 8003a56:	4e0c      	ldr	r6, [pc, #48]	@ (8003a88 <TIM_OC5_SetConfig+0x54>)
+ 8003a58:	42b0      	cmp	r0, r6
+ 8003a5a:	d005      	beq.n	8003a68 <TIM_OC5_SetConfig+0x34>
+ 8003a5c:	4e0b      	ldr	r6, [pc, #44]	@ (8003a8c <TIM_OC5_SetConfig+0x58>)
+ 8003a5e:	42b0      	cmp	r0, r6
+ 8003a60:	d002      	beq.n	8003a68 <TIM_OC5_SetConfig+0x34>
+ 8003a62:	4e0b      	ldr	r6, [pc, #44]	@ (8003a90 <TIM_OC5_SetConfig+0x5c>)
+ 8003a64:	42b0      	cmp	r0, r6
+ 8003a66:	d103      	bne.n	8003a70 <TIM_OC5_SetConfig+0x3c>
   {
     /* Reset the Output Compare IDLE State */
     tmpcr2 &= ~TIM_CR2_OIS5;
- 800662e:	697b      	ldr	r3, [r7, #20]
- 8006630:	4a0c      	ldr	r2, [pc, #48]	@ (8006664 <TIM_OC5_SetConfig+0x9c>)
- 8006632:	4013      	ands	r3, r2
- 8006634:	617b      	str	r3, [r7, #20]
+ 8003a68:	401c      	ands	r4, r3
     /* Set the Output Idle state */
     tmpcr2 |= (OC_Config->OCIdleState << 8U);
- 8006636:	683b      	ldr	r3, [r7, #0]
- 8006638:	695b      	ldr	r3, [r3, #20]
- 800663a:	021b      	lsls	r3, r3, #8
- 800663c:	697a      	ldr	r2, [r7, #20]
- 800663e:	4313      	orrs	r3, r2
- 8006640:	617b      	str	r3, [r7, #20]
+ 8003a6a:	694b      	ldr	r3, [r1, #20]
+ 8003a6c:	021b      	lsls	r3, r3, #8
+ 8003a6e:	4323      	orrs	r3, r4
   }
   /* Write to TIMx CR2 */
   TIMx->CR2 = tmpcr2;
- 8006642:	687b      	ldr	r3, [r7, #4]
- 8006644:	697a      	ldr	r2, [r7, #20]
- 8006646:	605a      	str	r2, [r3, #4]
+ 8003a70:	6043      	str	r3, [r0, #4]
 
   /* Write to TIMx CCMR3 */
   TIMx->CCMR3 = tmpccmrx;
- 8006648:	687b      	ldr	r3, [r7, #4]
- 800664a:	68fa      	ldr	r2, [r7, #12]
- 800664c:	655a      	str	r2, [r3, #84]	@ 0x54
 
   /* Set the Capture Compare Register value */
   TIMx->CCR5 = OC_Config->Pulse;
- 800664e:	683b      	ldr	r3, [r7, #0]
- 8006650:	685a      	ldr	r2, [r3, #4]
- 8006652:	687b      	ldr	r3, [r7, #4]
- 8006654:	659a      	str	r2, [r3, #88]	@ 0x58
+ 8003a72:	684b      	ldr	r3, [r1, #4]
+  TIMx->CCMR3 = tmpccmrx;
+ 8003a74:	6545      	str	r5, [r0, #84]	@ 0x54
+  TIMx->CCR5 = OC_Config->Pulse;
+ 8003a76:	6583      	str	r3, [r0, #88]	@ 0x58
 
   /* Write to TIMx CCER */
   TIMx->CCER = tmpccer;
- 8006656:	687b      	ldr	r3, [r7, #4]
- 8006658:	693a      	ldr	r2, [r7, #16]
- 800665a:	621a      	str	r2, [r3, #32]
+ 8003a78:	6202      	str	r2, [r0, #32]
 }
- 800665c:	46c0      	nop			@ (mov r8, r8)
- 800665e:	46bd      	mov	sp, r7
- 8006660:	b006      	add	sp, #24
- 8006662:	bd80      	pop	{r7, pc}
- 8006664:	fffeffff 	.word	0xfffeffff
- 8006668:	fffeff8f 	.word	0xfffeff8f
- 800666c:	fffdffff 	.word	0xfffdffff
- 8006670:	40012c00 	.word	0x40012c00
- 8006674:	40014400 	.word	0x40014400
- 8006678:	40014800 	.word	0x40014800
+ 8003a7a:	bd70      	pop	{r4, r5, r6, pc}
+ 8003a7c:	fffeffff 	.word	0xfffeffff
+ 8003a80:	fffeff8f 	.word	0xfffeff8f
+ 8003a84:	fffdffff 	.word	0xfffdffff
+ 8003a88:	40012c00 	.word	0x40012c00
+ 8003a8c:	40014400 	.word	0x40014400
+ 8003a90:	40014800 	.word	0x40014800
 
-0800667c <TIM_OC6_SetConfig>:
+08003a94 <TIM_OC6_SetConfig>:
   * @param  OC_Config The output configuration structure
   * @retval None
   */
 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
                               const TIM_OC_InitTypeDef *OC_Config)
 {
- 800667c:	b580      	push	{r7, lr}
- 800667e:	b086      	sub	sp, #24
- 8006680:	af00      	add	r7, sp, #0
- 8006682:	6078      	str	r0, [r7, #4]
- 8006684:	6039      	str	r1, [r7, #0]
-  uint32_t tmpccmrx;
-  uint32_t tmpccer;
-  uint32_t tmpcr2;
+ 8003a94:	b530      	push	{r4, r5, lr}
 
   /* Get the TIMx CCER register value */
   tmpccer = TIMx->CCER;
- 8006686:	687b      	ldr	r3, [r7, #4]
- 8006688:	6a1b      	ldr	r3, [r3, #32]
- 800668a:	613b      	str	r3, [r7, #16]
 
   /* Disable the output: Reset the CCxE Bit */
   TIMx->CCER &= ~TIM_CCER_CC6E;
- 800668c:	687b      	ldr	r3, [r7, #4]
- 800668e:	6a1b      	ldr	r3, [r3, #32]
- 8006690:	4a22      	ldr	r2, [pc, #136]	@ (800671c <TIM_OC6_SetConfig+0xa0>)
- 8006692:	401a      	ands	r2, r3
- 8006694:	687b      	ldr	r3, [r7, #4]
- 8006696:	621a      	str	r2, [r3, #32]
-
-  /* Get the TIMx CR2 register value */
+ 8003a96:	4a12      	ldr	r2, [pc, #72]	@ (8003ae0 <TIM_OC6_SetConfig+0x4c>)
+  tmpccer = TIMx->CCER;
+ 8003a98:	6a04      	ldr	r4, [r0, #32]
+  TIMx->CCER &= ~TIM_CCER_CC6E;
+ 8003a9a:	6a03      	ldr	r3, [r0, #32]
   tmpcr2 =  TIMx->CR2;
- 8006698:	687b      	ldr	r3, [r7, #4]
- 800669a:	685b      	ldr	r3, [r3, #4]
- 800669c:	617b      	str	r3, [r7, #20]
   /* Get the TIMx CCMR1 register value */
   tmpccmrx = TIMx->CCMR3;
- 800669e:	687b      	ldr	r3, [r7, #4]
- 80066a0:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
- 80066a2:	60fb      	str	r3, [r7, #12]
 
   /* Reset the Output Compare Mode Bits */
   tmpccmrx &= ~(TIM_CCMR3_OC6M);
- 80066a4:	68fb      	ldr	r3, [r7, #12]
- 80066a6:	4a1e      	ldr	r2, [pc, #120]	@ (8006720 <TIM_OC6_SetConfig+0xa4>)
- 80066a8:	4013      	ands	r3, r2
- 80066aa:	60fb      	str	r3, [r7, #12]
+ 8003a9c:	4d11      	ldr	r5, [pc, #68]	@ (8003ae4 <TIM_OC6_SetConfig+0x50>)
+  TIMx->CCER &= ~TIM_CCER_CC6E;
+ 8003a9e:	4013      	ands	r3, r2
+ 8003aa0:	6203      	str	r3, [r0, #32]
+  tmpcr2 =  TIMx->CR2;
+ 8003aa2:	6843      	ldr	r3, [r0, #4]
+  tmpccmrx = TIMx->CCMR3;
+ 8003aa4:	6d42      	ldr	r2, [r0, #84]	@ 0x54
+  tmpccmrx &= ~(TIM_CCMR3_OC6M);
+ 8003aa6:	402a      	ands	r2, r5
   /* Select the Output Compare Mode */
   tmpccmrx |= (OC_Config->OCMode << 8U);
- 80066ac:	683b      	ldr	r3, [r7, #0]
- 80066ae:	681b      	ldr	r3, [r3, #0]
- 80066b0:	021b      	lsls	r3, r3, #8
- 80066b2:	68fa      	ldr	r2, [r7, #12]
- 80066b4:	4313      	orrs	r3, r2
- 80066b6:	60fb      	str	r3, [r7, #12]
+ 8003aa8:	680d      	ldr	r5, [r1, #0]
+ 8003aaa:	022d      	lsls	r5, r5, #8
+ 8003aac:	4315      	orrs	r5, r2
 
   /* Reset the Output Polarity level */
   tmpccer &= (uint32_t)~TIM_CCER_CC6P;
- 80066b8:	693b      	ldr	r3, [r7, #16]
- 80066ba:	4a1a      	ldr	r2, [pc, #104]	@ (8006724 <TIM_OC6_SetConfig+0xa8>)
- 80066bc:	4013      	ands	r3, r2
- 80066be:	613b      	str	r3, [r7, #16]
+ 8003aae:	4a0e      	ldr	r2, [pc, #56]	@ (8003ae8 <TIM_OC6_SetConfig+0x54>)
+ 8003ab0:	4014      	ands	r4, r2
   /* Set the Output Compare Polarity */
   tmpccer |= (OC_Config->OCPolarity << 20U);
- 80066c0:	683b      	ldr	r3, [r7, #0]
- 80066c2:	689b      	ldr	r3, [r3, #8]
- 80066c4:	051b      	lsls	r3, r3, #20
- 80066c6:	693a      	ldr	r2, [r7, #16]
- 80066c8:	4313      	orrs	r3, r2
- 80066ca:	613b      	str	r3, [r7, #16]
+ 8003ab2:	688a      	ldr	r2, [r1, #8]
+ 8003ab4:	0512      	lsls	r2, r2, #20
+ 8003ab6:	4322      	orrs	r2, r4
 
   if (IS_TIM_BREAK_INSTANCE(TIMx))
- 80066cc:	687b      	ldr	r3, [r7, #4]
- 80066ce:	4a16      	ldr	r2, [pc, #88]	@ (8006728 <TIM_OC6_SetConfig+0xac>)
- 80066d0:	4293      	cmp	r3, r2
- 80066d2:	d007      	beq.n	80066e4 <TIM_OC6_SetConfig+0x68>
- 80066d4:	687b      	ldr	r3, [r7, #4]
- 80066d6:	4a15      	ldr	r2, [pc, #84]	@ (800672c <TIM_OC6_SetConfig+0xb0>)
- 80066d8:	4293      	cmp	r3, r2
- 80066da:	d003      	beq.n	80066e4 <TIM_OC6_SetConfig+0x68>
- 80066dc:	687b      	ldr	r3, [r7, #4]
- 80066de:	4a14      	ldr	r2, [pc, #80]	@ (8006730 <TIM_OC6_SetConfig+0xb4>)
- 80066e0:	4293      	cmp	r3, r2
- 80066e2:	d109      	bne.n	80066f8 <TIM_OC6_SetConfig+0x7c>
+ 8003ab8:	4c0c      	ldr	r4, [pc, #48]	@ (8003aec <TIM_OC6_SetConfig+0x58>)
+ 8003aba:	42a0      	cmp	r0, r4
+ 8003abc:	d005      	beq.n	8003aca <TIM_OC6_SetConfig+0x36>
+ 8003abe:	4c0c      	ldr	r4, [pc, #48]	@ (8003af0 <TIM_OC6_SetConfig+0x5c>)
+ 8003ac0:	42a0      	cmp	r0, r4
+ 8003ac2:	d002      	beq.n	8003aca <TIM_OC6_SetConfig+0x36>
+ 8003ac4:	4c0b      	ldr	r4, [pc, #44]	@ (8003af4 <TIM_OC6_SetConfig+0x60>)
+ 8003ac6:	42a0      	cmp	r0, r4
+ 8003ac8:	d104      	bne.n	8003ad4 <TIM_OC6_SetConfig+0x40>
   {
     /* Reset the Output Compare IDLE State */
     tmpcr2 &= ~TIM_CR2_OIS6;
- 80066e4:	697b      	ldr	r3, [r7, #20]
- 80066e6:	4a13      	ldr	r2, [pc, #76]	@ (8006734 <TIM_OC6_SetConfig+0xb8>)
- 80066e8:	4013      	ands	r3, r2
- 80066ea:	617b      	str	r3, [r7, #20]
+ 8003aca:	4c0b      	ldr	r4, [pc, #44]	@ (8003af8 <TIM_OC6_SetConfig+0x64>)
+ 8003acc:	401c      	ands	r4, r3
     /* Set the Output Idle state */
     tmpcr2 |= (OC_Config->OCIdleState << 10U);
- 80066ec:	683b      	ldr	r3, [r7, #0]
- 80066ee:	695b      	ldr	r3, [r3, #20]
- 80066f0:	029b      	lsls	r3, r3, #10
- 80066f2:	697a      	ldr	r2, [r7, #20]
- 80066f4:	4313      	orrs	r3, r2
- 80066f6:	617b      	str	r3, [r7, #20]
+ 8003ace:	694b      	ldr	r3, [r1, #20]
+ 8003ad0:	029b      	lsls	r3, r3, #10
+ 8003ad2:	4323      	orrs	r3, r4
   }
 
   /* Write to TIMx CR2 */
   TIMx->CR2 = tmpcr2;
- 80066f8:	687b      	ldr	r3, [r7, #4]
- 80066fa:	697a      	ldr	r2, [r7, #20]
- 80066fc:	605a      	str	r2, [r3, #4]
+ 8003ad4:	6043      	str	r3, [r0, #4]
 
   /* Write to TIMx CCMR3 */
   TIMx->CCMR3 = tmpccmrx;
- 80066fe:	687b      	ldr	r3, [r7, #4]
- 8006700:	68fa      	ldr	r2, [r7, #12]
- 8006702:	655a      	str	r2, [r3, #84]	@ 0x54
 
   /* Set the Capture Compare Register value */
   TIMx->CCR6 = OC_Config->Pulse;
- 8006704:	683b      	ldr	r3, [r7, #0]
- 8006706:	685a      	ldr	r2, [r3, #4]
- 8006708:	687b      	ldr	r3, [r7, #4]
- 800670a:	65da      	str	r2, [r3, #92]	@ 0x5c
+ 8003ad6:	684b      	ldr	r3, [r1, #4]
+  TIMx->CCMR3 = tmpccmrx;
+ 8003ad8:	6545      	str	r5, [r0, #84]	@ 0x54
+  TIMx->CCR6 = OC_Config->Pulse;
+ 8003ada:	65c3      	str	r3, [r0, #92]	@ 0x5c
 
   /* Write to TIMx CCER */
   TIMx->CCER = tmpccer;
- 800670c:	687b      	ldr	r3, [r7, #4]
- 800670e:	693a      	ldr	r2, [r7, #16]
- 8006710:	621a      	str	r2, [r3, #32]
+ 8003adc:	6202      	str	r2, [r0, #32]
 }
- 8006712:	46c0      	nop			@ (mov r8, r8)
- 8006714:	46bd      	mov	sp, r7
- 8006716:	b006      	add	sp, #24
- 8006718:	bd80      	pop	{r7, pc}
- 800671a:	46c0      	nop			@ (mov r8, r8)
- 800671c:	ffefffff 	.word	0xffefffff
- 8006720:	feff8fff 	.word	0xfeff8fff
- 8006724:	ffdfffff 	.word	0xffdfffff
- 8006728:	40012c00 	.word	0x40012c00
- 800672c:	40014400 	.word	0x40014400
- 8006730:	40014800 	.word	0x40014800
- 8006734:	fffbffff 	.word	0xfffbffff
+ 8003ade:	bd30      	pop	{r4, r5, pc}
+ 8003ae0:	ffefffff 	.word	0xffefffff
+ 8003ae4:	feff8fff 	.word	0xfeff8fff
+ 8003ae8:	ffdfffff 	.word	0xffdfffff
+ 8003aec:	40012c00 	.word	0x40012c00
+ 8003af0:	40014400 	.word	0x40014400
+ 8003af4:	40014800 	.word	0x40014800
+ 8003af8:	fffbffff 	.word	0xfffbffff
 
-08006738 <TIM_TI1_ConfigInputStage>:
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
- 8006738:	b580      	push	{r7, lr}
- 800673a:	b086      	sub	sp, #24
- 800673c:	af00      	add	r7, sp, #0
- 800673e:	60f8      	str	r0, [r7, #12]
- 8006740:	60b9      	str	r1, [r7, #8]
- 8006742:	607a      	str	r2, [r7, #4]
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  tmpccer = TIMx->CCER;
- 8006744:	68fb      	ldr	r3, [r7, #12]
- 8006746:	6a1b      	ldr	r3, [r3, #32]
- 8006748:	617b      	str	r3, [r7, #20]
-  TIMx->CCER &= ~TIM_CCER_CC1E;
- 800674a:	68fb      	ldr	r3, [r7, #12]
- 800674c:	6a1b      	ldr	r3, [r3, #32]
- 800674e:	2201      	movs	r2, #1
- 8006750:	4393      	bics	r3, r2
- 8006752:	001a      	movs	r2, r3
- 8006754:	68fb      	ldr	r3, [r7, #12]
- 8006756:	621a      	str	r2, [r3, #32]
-  tmpccmr1 = TIMx->CCMR1;
- 8006758:	68fb      	ldr	r3, [r7, #12]
- 800675a:	699b      	ldr	r3, [r3, #24]
- 800675c:	613b      	str	r3, [r7, #16]
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
- 800675e:	693b      	ldr	r3, [r7, #16]
- 8006760:	22f0      	movs	r2, #240	@ 0xf0
- 8006762:	4393      	bics	r3, r2
- 8006764:	613b      	str	r3, [r7, #16]
-  tmpccmr1 |= (TIM_ICFilter << 4U);
- 8006766:	687b      	ldr	r3, [r7, #4]
- 8006768:	011b      	lsls	r3, r3, #4
- 800676a:	693a      	ldr	r2, [r7, #16]
- 800676c:	4313      	orrs	r3, r2
- 800676e:	613b      	str	r3, [r7, #16]
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
- 8006770:	697b      	ldr	r3, [r7, #20]
- 8006772:	220a      	movs	r2, #10
- 8006774:	4393      	bics	r3, r2
- 8006776:	617b      	str	r3, [r7, #20]
-  tmpccer |= TIM_ICPolarity;
- 8006778:	697a      	ldr	r2, [r7, #20]
- 800677a:	68bb      	ldr	r3, [r7, #8]
- 800677c:	4313      	orrs	r3, r2
- 800677e:	617b      	str	r3, [r7, #20]
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
- 8006780:	68fb      	ldr	r3, [r7, #12]
- 8006782:	693a      	ldr	r2, [r7, #16]
- 8006784:	619a      	str	r2, [r3, #24]
-  TIMx->CCER = tmpccer;
- 8006786:	68fb      	ldr	r3, [r7, #12]
- 8006788:	697a      	ldr	r2, [r7, #20]
- 800678a:	621a      	str	r2, [r3, #32]
+08003afc <HAL_TIM_Base_Stop>:
+  __HAL_TIM_DISABLE(htim);
+ 8003afc:	6803      	ldr	r3, [r0, #0]
+ 8003afe:	4a08      	ldr	r2, [pc, #32]	@ (8003b20 <HAL_TIM_Base_Stop+0x24>)
+ 8003b00:	6a19      	ldr	r1, [r3, #32]
+ 8003b02:	4211      	tst	r1, r2
+ 8003b04:	d107      	bne.n	8003b16 <HAL_TIM_Base_Stop+0x1a>
+ 8003b06:	6a19      	ldr	r1, [r3, #32]
+ 8003b08:	4a06      	ldr	r2, [pc, #24]	@ (8003b24 <HAL_TIM_Base_Stop+0x28>)
+ 8003b0a:	4211      	tst	r1, r2
+ 8003b0c:	d103      	bne.n	8003b16 <HAL_TIM_Base_Stop+0x1a>
+ 8003b0e:	2101      	movs	r1, #1
+ 8003b10:	681a      	ldr	r2, [r3, #0]
+ 8003b12:	438a      	bics	r2, r1
+ 8003b14:	601a      	str	r2, [r3, #0]
+  htim->State = HAL_TIM_STATE_READY;
+ 8003b16:	2301      	movs	r3, #1
+ 8003b18:	303d      	adds	r0, #61	@ 0x3d
+ 8003b1a:	7003      	strb	r3, [r0, #0]
 }
- 800678c:	46c0      	nop			@ (mov r8, r8)
- 800678e:	46bd      	mov	sp, r7
- 8006790:	b006      	add	sp, #24
- 8006792:	bd80      	pop	{r7, pc}
+ 8003b1c:	2000      	movs	r0, #0
+ 8003b1e:	4770      	bx	lr
+ 8003b20:	00001111 	.word	0x00001111
+ 8003b24:	00000444 	.word	0x00000444
 
-08006794 <TIM_TI2_ConfigInputStage>:
-  * @param  TIM_ICFilter Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
+08003b28 <HAL_TIM_Base_Start_IT>:
+  if (htim->State != HAL_TIM_STATE_READY)
+ 8003b28:	0001      	movs	r1, r0
 {
- 8006794:	b580      	push	{r7, lr}
- 8006796:	b086      	sub	sp, #24
- 8006798:	af00      	add	r7, sp, #0
- 800679a:	60f8      	str	r0, [r7, #12]
- 800679c:	60b9      	str	r1, [r7, #8]
- 800679e:	607a      	str	r2, [r7, #4]
-  uint32_t tmpccmr1;
-  uint32_t tmpccer;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  tmpccer = TIMx->CCER;
- 80067a0:	68fb      	ldr	r3, [r7, #12]
- 80067a2:	6a1b      	ldr	r3, [r3, #32]
- 80067a4:	617b      	str	r3, [r7, #20]
-  TIMx->CCER &= ~TIM_CCER_CC2E;
- 80067a6:	68fb      	ldr	r3, [r7, #12]
- 80067a8:	6a1b      	ldr	r3, [r3, #32]
- 80067aa:	2210      	movs	r2, #16
- 80067ac:	4393      	bics	r3, r2
- 80067ae:	001a      	movs	r2, r3
- 80067b0:	68fb      	ldr	r3, [r7, #12]
- 80067b2:	621a      	str	r2, [r3, #32]
-  tmpccmr1 = TIMx->CCMR1;
- 80067b4:	68fb      	ldr	r3, [r7, #12]
- 80067b6:	699b      	ldr	r3, [r3, #24]
- 80067b8:	613b      	str	r3, [r7, #16]
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
- 80067ba:	693b      	ldr	r3, [r7, #16]
- 80067bc:	4a0d      	ldr	r2, [pc, #52]	@ (80067f4 <TIM_TI2_ConfigInputStage+0x60>)
- 80067be:	4013      	ands	r3, r2
- 80067c0:	613b      	str	r3, [r7, #16]
-  tmpccmr1 |= (TIM_ICFilter << 12U);
- 80067c2:	687b      	ldr	r3, [r7, #4]
- 80067c4:	031b      	lsls	r3, r3, #12
- 80067c6:	693a      	ldr	r2, [r7, #16]
- 80067c8:	4313      	orrs	r3, r2
- 80067ca:	613b      	str	r3, [r7, #16]
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
- 80067cc:	697b      	ldr	r3, [r7, #20]
- 80067ce:	22a0      	movs	r2, #160	@ 0xa0
- 80067d0:	4393      	bics	r3, r2
- 80067d2:	617b      	str	r3, [r7, #20]
-  tmpccer |= (TIM_ICPolarity << 4U);
- 80067d4:	68bb      	ldr	r3, [r7, #8]
- 80067d6:	011b      	lsls	r3, r3, #4
- 80067d8:	697a      	ldr	r2, [r7, #20]
- 80067da:	4313      	orrs	r3, r2
- 80067dc:	617b      	str	r3, [r7, #20]
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
- 80067de:	68fb      	ldr	r3, [r7, #12]
- 80067e0:	693a      	ldr	r2, [r7, #16]
- 80067e2:	619a      	str	r2, [r3, #24]
-  TIMx->CCER = tmpccer;
- 80067e4:	68fb      	ldr	r3, [r7, #12]
- 80067e6:	697a      	ldr	r2, [r7, #20]
- 80067e8:	621a      	str	r2, [r3, #32]
+ 8003b2a:	0003      	movs	r3, r0
+    return HAL_ERROR;
+ 8003b2c:	2001      	movs	r0, #1
+{
+ 8003b2e:	b510      	push	{r4, lr}
+  if (htim->State != HAL_TIM_STATE_READY)
+ 8003b30:	313d      	adds	r1, #61	@ 0x3d
+ 8003b32:	780c      	ldrb	r4, [r1, #0]
+ 8003b34:	b2e2      	uxtb	r2, r4
+ 8003b36:	4284      	cmp	r4, r0
+ 8003b38:	d11c      	bne.n	8003b74 <HAL_TIM_Base_Start_IT+0x4c>
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8003b3a:	1800      	adds	r0, r0, r0
+ 8003b3c:	7008      	strb	r0, [r1, #0]
+  __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
+ 8003b3e:	681b      	ldr	r3, [r3, #0]
+ 8003b40:	68d9      	ldr	r1, [r3, #12]
+ 8003b42:	4311      	orrs	r1, r2
+ 8003b44:	60d9      	str	r1, [r3, #12]
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 8003b46:	490d      	ldr	r1, [pc, #52]	@ (8003b7c <HAL_TIM_Base_Start_IT+0x54>)
+ 8003b48:	428b      	cmp	r3, r1
+ 8003b4a:	d006      	beq.n	8003b5a <HAL_TIM_Base_Start_IT+0x32>
+ 8003b4c:	2180      	movs	r1, #128	@ 0x80
+ 8003b4e:	05c9      	lsls	r1, r1, #23
+ 8003b50:	428b      	cmp	r3, r1
+ 8003b52:	d002      	beq.n	8003b5a <HAL_TIM_Base_Start_IT+0x32>
+ 8003b54:	490a      	ldr	r1, [pc, #40]	@ (8003b80 <HAL_TIM_Base_Start_IT+0x58>)
+ 8003b56:	428b      	cmp	r3, r1
+ 8003b58:	d10d      	bne.n	8003b76 <HAL_TIM_Base_Start_IT+0x4e>
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 8003b5a:	689a      	ldr	r2, [r3, #8]
+ 8003b5c:	4909      	ldr	r1, [pc, #36]	@ (8003b84 <HAL_TIM_Base_Start_IT+0x5c>)
+ 8003b5e:	400a      	ands	r2, r1
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 8003b60:	2a06      	cmp	r2, #6
+ 8003b62:	d006      	beq.n	8003b72 <HAL_TIM_Base_Start_IT+0x4a>
+ 8003b64:	3907      	subs	r1, #7
+ 8003b66:	428a      	cmp	r2, r1
+ 8003b68:	d003      	beq.n	8003b72 <HAL_TIM_Base_Start_IT+0x4a>
+      __HAL_TIM_ENABLE(htim);
+ 8003b6a:	2201      	movs	r2, #1
+ 8003b6c:	6819      	ldr	r1, [r3, #0]
+ 8003b6e:	430a      	orrs	r2, r1
+ 8003b70:	601a      	str	r2, [r3, #0]
+  return HAL_OK;
+ 8003b72:	2000      	movs	r0, #0
 }
- 80067ea:	46c0      	nop			@ (mov r8, r8)
- 80067ec:	46bd      	mov	sp, r7
- 80067ee:	b006      	add	sp, #24
- 80067f0:	bd80      	pop	{r7, pc}
- 80067f2:	46c0      	nop			@ (mov r8, r8)
- 80067f4:	ffff0fff 	.word	0xffff0fff
+ 8003b74:	bd10      	pop	{r4, pc}
+    __HAL_TIM_ENABLE(htim);
+ 8003b76:	6819      	ldr	r1, [r3, #0]
+ 8003b78:	e7f9      	b.n	8003b6e <HAL_TIM_Base_Start_IT+0x46>
+ 8003b7a:	46c0      	nop			@ (mov r8, r8)
+ 8003b7c:	40012c00 	.word	0x40012c00
+ 8003b80:	40000400 	.word	0x40000400
+ 8003b84:	00010007 	.word	0x00010007
 
-080067f8 <TIM_ITRx_SetConfig>:
-  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
-  *            @arg TIM_TS_ETRF: External Trigger input
-  * @retval None
-  */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
+08003b88 <HAL_TIM_PWM_MspInit>:
+__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
+ 8003b88:	4770      	bx	lr
+
+08003b8a <HAL_TIM_Encoder_Start>:
 {
- 80067f8:	b580      	push	{r7, lr}
- 80067fa:	b084      	sub	sp, #16
- 80067fc:	af00      	add	r7, sp, #0
- 80067fe:	6078      	str	r0, [r7, #4]
- 8006800:	6039      	str	r1, [r7, #0]
-  uint32_t tmpsmcr;
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = TIMx->SMCR;
- 8006802:	687b      	ldr	r3, [r7, #4]
- 8006804:	689b      	ldr	r3, [r3, #8]
- 8006806:	60fb      	str	r3, [r7, #12]
-  /* Reset the TS Bits */
-  tmpsmcr &= ~TIM_SMCR_TS;
- 8006808:	68fb      	ldr	r3, [r7, #12]
- 800680a:	4a08      	ldr	r2, [pc, #32]	@ (800682c <TIM_ITRx_SetConfig+0x34>)
- 800680c:	4013      	ands	r3, r2
- 800680e:	60fb      	str	r3, [r7, #12]
-  /* Set the Input Trigger source and the slave mode*/
-  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
- 8006810:	683a      	ldr	r2, [r7, #0]
- 8006812:	68fb      	ldr	r3, [r7, #12]
- 8006814:	4313      	orrs	r3, r2
- 8006816:	2207      	movs	r2, #7
- 8006818:	4313      	orrs	r3, r2
- 800681a:	60fb      	str	r3, [r7, #12]
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
- 800681c:	687b      	ldr	r3, [r7, #4]
- 800681e:	68fa      	ldr	r2, [r7, #12]
- 8006820:	609a      	str	r2, [r3, #8]
-}
- 8006822:	46c0      	nop			@ (mov r8, r8)
- 8006824:	46bd      	mov	sp, r7
- 8006826:	b004      	add	sp, #16
- 8006828:	bd80      	pop	{r7, pc}
- 800682a:	46c0      	nop			@ (mov r8, r8)
- 800682c:	ffcfff8f 	.word	0xffcfff8f
-
-08006830 <TIM_ETR_SetConfig>:
-  *          This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
-                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
+ 8003b8a:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 8003b8c:	223e      	movs	r2, #62	@ 0x3e
 {
- 8006830:	b580      	push	{r7, lr}
- 8006832:	b086      	sub	sp, #24
- 8006834:	af00      	add	r7, sp, #0
- 8006836:	60f8      	str	r0, [r7, #12]
- 8006838:	60b9      	str	r1, [r7, #8]
- 800683a:	607a      	str	r2, [r7, #4]
- 800683c:	603b      	str	r3, [r7, #0]
-  uint32_t tmpsmcr;
-
-  tmpsmcr = TIMx->SMCR;
- 800683e:	68fb      	ldr	r3, [r7, #12]
- 8006840:	689b      	ldr	r3, [r3, #8]
- 8006842:	617b      	str	r3, [r7, #20]
-
-  /* Reset the ETR Bits */
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
- 8006844:	697b      	ldr	r3, [r7, #20]
- 8006846:	4a09      	ldr	r2, [pc, #36]	@ (800686c <TIM_ETR_SetConfig+0x3c>)
- 8006848:	4013      	ands	r3, r2
- 800684a:	617b      	str	r3, [r7, #20]
-
-  /* Set the Prescaler, the Filter value and the Polarity */
-  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
- 800684c:	683b      	ldr	r3, [r7, #0]
- 800684e:	021a      	lsls	r2, r3, #8
- 8006850:	687b      	ldr	r3, [r7, #4]
- 8006852:	431a      	orrs	r2, r3
- 8006854:	68bb      	ldr	r3, [r7, #8]
- 8006856:	4313      	orrs	r3, r2
- 8006858:	697a      	ldr	r2, [r7, #20]
- 800685a:	4313      	orrs	r3, r2
- 800685c:	617b      	str	r3, [r7, #20]
-
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
- 800685e:	68fb      	ldr	r3, [r7, #12]
- 8006860:	697a      	ldr	r2, [r7, #20]
- 8006862:	609a      	str	r2, [r3, #8]
-}
- 8006864:	46c0      	nop			@ (mov r8, r8)
- 8006866:	46bd      	mov	sp, r7
- 8006868:	b006      	add	sp, #24
- 800686a:	bd80      	pop	{r7, pc}
- 800686c:	ffff00ff 	.word	0xffff00ff
-
-08006870 <TIM_CCxChannelCmd>:
-  * @param  ChannelState specifies the TIM Channel CCxE bit new state.
-  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
-  * @retval None
-  */
-void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
-{
- 8006870:	b580      	push	{r7, lr}
- 8006872:	b086      	sub	sp, #24
- 8006874:	af00      	add	r7, sp, #0
- 8006876:	60f8      	str	r0, [r7, #12]
- 8006878:	60b9      	str	r1, [r7, #8]
- 800687a:	607a      	str	r2, [r7, #4]
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
+ 8003b8e:	0003      	movs	r3, r0
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 8003b90:	4694      	mov	ip, r2
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 8003b92:	001f      	movs	r7, r3
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 8003b94:	4484      	add	ip, r0
+ 8003b96:	4662      	mov	r2, ip
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ 8003b98:	001e      	movs	r6, r3
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+ 8003b9a:	001d      	movs	r5, r3
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 8003b9c:	373f      	adds	r7, #63	@ 0x3f
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 8003b9e:	7810      	ldrb	r0, [r2, #0]
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 8003ba0:	783a      	ldrb	r2, [r7, #0]
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ 8003ba2:	3644      	adds	r6, #68	@ 0x44
+  HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
+ 8003ba4:	b2d2      	uxtb	r2, r2
+ 8003ba6:	9201      	str	r2, [sp, #4]
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+ 8003ba8:	3545      	adds	r5, #69	@ 0x45
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ 8003baa:	7834      	ldrb	r4, [r6, #0]
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+ 8003bac:	782a      	ldrb	r2, [r5, #0]
+  HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
+ 8003bae:	b2c0      	uxtb	r0, r0
+  HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
+ 8003bb0:	b2e4      	uxtb	r4, r4
+  HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
+ 8003bb2:	b2d2      	uxtb	r2, r2
+  if (Channel == TIM_CHANNEL_1)
+ 8003bb4:	2900      	cmp	r1, #0
+ 8003bb6:	d114      	bne.n	8003be2 <HAL_TIM_Encoder_Start+0x58>
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 8003bb8:	2801      	cmp	r0, #1
+ 8003bba:	d13c      	bne.n	8003c36 <HAL_TIM_Encoder_Start+0xac>
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
+ 8003bbc:	2c01      	cmp	r4, #1
+ 8003bbe:	d10f      	bne.n	8003be0 <HAL_TIM_Encoder_Start+0x56>
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 8003bc0:	2202      	movs	r2, #2
+ 8003bc2:	4661      	mov	r1, ip
+ 8003bc4:	700a      	strb	r2, [r1, #0]
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 8003bc6:	7032      	strb	r2, [r6, #0]
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ 8003bc8:	681b      	ldr	r3, [r3, #0]
   assert_param(IS_TIM_CHANNELS(Channel));
 
   tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
- 800687c:	68bb      	ldr	r3, [r7, #8]
- 800687e:	221f      	movs	r2, #31
- 8006880:	4013      	ands	r3, r2
- 8006882:	2201      	movs	r2, #1
- 8006884:	409a      	lsls	r2, r3
- 8006886:	0013      	movs	r3, r2
- 8006888:	617b      	str	r3, [r7, #20]
 
   /* Reset the CCxE Bit */
   TIMx->CCER &= ~tmp;
- 800688a:	68fb      	ldr	r3, [r7, #12]
- 800688c:	6a1b      	ldr	r3, [r3, #32]
- 800688e:	697a      	ldr	r2, [r7, #20]
- 8006890:	43d2      	mvns	r2, r2
- 8006892:	401a      	ands	r2, r3
- 8006894:	68fb      	ldr	r3, [r7, #12]
- 8006896:	621a      	str	r2, [r3, #32]
+ 8003bca:	6a1a      	ldr	r2, [r3, #32]
+ 8003bcc:	43a2      	bics	r2, r4
+ 8003bce:	621a      	str	r2, [r3, #32]
 
   /* Set or reset the CCxE Bit */
   TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
- 8006898:	68fb      	ldr	r3, [r7, #12]
- 800689a:	6a1a      	ldr	r2, [r3, #32]
- 800689c:	68bb      	ldr	r3, [r7, #8]
- 800689e:	211f      	movs	r1, #31
- 80068a0:	400b      	ands	r3, r1
- 80068a2:	6879      	ldr	r1, [r7, #4]
- 80068a4:	4099      	lsls	r1, r3
- 80068a6:	000b      	movs	r3, r1
- 80068a8:	431a      	orrs	r2, r3
- 80068aa:	68fb      	ldr	r3, [r7, #12]
- 80068ac:	621a      	str	r2, [r3, #32]
+ 8003bd0:	6a1a      	ldr	r2, [r3, #32]
+ 8003bd2:	4322      	orrs	r2, r4
+ 8003bd4:	621a      	str	r2, [r3, #32]
+  __HAL_TIM_ENABLE(htim);
+ 8003bd6:	2201      	movs	r2, #1
+  return HAL_OK;
+ 8003bd8:	2000      	movs	r0, #0
+  __HAL_TIM_ENABLE(htim);
+ 8003bda:	6819      	ldr	r1, [r3, #0]
+ 8003bdc:	430a      	orrs	r2, r1
+ 8003bde:	601a      	str	r2, [r3, #0]
 }
- 80068ae:	46c0      	nop			@ (mov r8, r8)
- 80068b0:	46bd      	mov	sp, r7
- 80068b2:	b006      	add	sp, #24
- 80068b4:	bd80      	pop	{r7, pc}
+ 8003be0:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+  else if (Channel == TIM_CHANNEL_2)
+ 8003be2:	2904      	cmp	r1, #4
+ 8003be4:	d110      	bne.n	8003c08 <HAL_TIM_Encoder_Start+0x7e>
+      return HAL_ERROR;
+ 8003be6:	2001      	movs	r0, #1
+    if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 8003be8:	9901      	ldr	r1, [sp, #4]
+ 8003bea:	4281      	cmp	r1, r0
+ 8003bec:	d1f8      	bne.n	8003be0 <HAL_TIM_Encoder_Start+0x56>
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 8003bee:	4282      	cmp	r2, r0
+ 8003bf0:	d1f6      	bne.n	8003be0 <HAL_TIM_Encoder_Start+0x56>
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 8003bf2:	2202      	movs	r2, #2
+ 8003bf4:	703a      	strb	r2, [r7, #0]
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 8003bf6:	702a      	strb	r2, [r5, #0]
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
+ 8003bf8:	681b      	ldr	r3, [r3, #0]
+  TIMx->CCER &= ~tmp;
+ 8003bfa:	2210      	movs	r2, #16
+ 8003bfc:	6a19      	ldr	r1, [r3, #32]
+ 8003bfe:	4391      	bics	r1, r2
+ 8003c00:	6219      	str	r1, [r3, #32]
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ 8003c02:	6a19      	ldr	r1, [r3, #32]
+ 8003c04:	430a      	orrs	r2, r1
+ 8003c06:	e7e5      	b.n	8003bd4 <HAL_TIM_Encoder_Start+0x4a>
+    if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 8003c08:	2801      	cmp	r0, #1
+ 8003c0a:	d114      	bne.n	8003c36 <HAL_TIM_Encoder_Start+0xac>
+        || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
+ 8003c0c:	9901      	ldr	r1, [sp, #4]
+ 8003c0e:	2901      	cmp	r1, #1
+ 8003c10:	d1e6      	bne.n	8003be0 <HAL_TIM_Encoder_Start+0x56>
+        || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
+ 8003c12:	2c01      	cmp	r4, #1
+ 8003c14:	d1e4      	bne.n	8003be0 <HAL_TIM_Encoder_Start+0x56>
+        || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
+ 8003c16:	2a01      	cmp	r2, #1
+ 8003c18:	d1e2      	bne.n	8003be0 <HAL_TIM_Encoder_Start+0x56>
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 8003c1a:	4660      	mov	r0, ip
+ 8003c1c:	3101      	adds	r1, #1
+ 8003c1e:	7001      	strb	r1, [r0, #0]
+      TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 8003c20:	7039      	strb	r1, [r7, #0]
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
+ 8003c22:	7031      	strb	r1, [r6, #0]
+      TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
+ 8003c24:	7029      	strb	r1, [r5, #0]
+      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
+ 8003c26:	681b      	ldr	r3, [r3, #0]
+  TIMx->CCER &= ~tmp;
+ 8003c28:	6a19      	ldr	r1, [r3, #32]
+ 8003c2a:	4391      	bics	r1, r2
+ 8003c2c:	6219      	str	r1, [r3, #32]
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ 8003c2e:	6a19      	ldr	r1, [r3, #32]
+ 8003c30:	430a      	orrs	r2, r1
+ 8003c32:	621a      	str	r2, [r3, #32]
+ 8003c34:	e7e1      	b.n	8003bfa <HAL_TIM_Encoder_Start+0x70>
+      return HAL_ERROR;
+ 8003c36:	2001      	movs	r0, #1
+ 8003c38:	e7d2      	b.n	8003be0 <HAL_TIM_Encoder_Start+0x56>
+
+08003c3a <HAL_TIM_OC_DelayElapsedCallback>:
+__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
+ 8003c3a:	4770      	bx	lr
+
+08003c3c <HAL_TIM_IC_CaptureCallback>:
+__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
+ 8003c3c:	4770      	bx	lr
+
+08003c3e <HAL_TIM_PWM_PulseFinishedCallback>:
+__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
+ 8003c3e:	4770      	bx	lr
+
+08003c40 <HAL_TIM_TriggerCallback>:
+__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
+ 8003c40:	4770      	bx	lr
 	...
 
-080068b8 <HAL_TIMEx_MasterConfigSynchronization>:
+08003c44 <HAL_TIM_IRQHandler>:
+  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
+ 8003c44:	2202      	movs	r2, #2
+  uint32_t itsource = htim->Instance->DIER;
+ 8003c46:	6803      	ldr	r3, [r0, #0]
+{
+ 8003c48:	b570      	push	{r4, r5, r6, lr}
+  uint32_t itsource = htim->Instance->DIER;
+ 8003c4a:	68dd      	ldr	r5, [r3, #12]
+  uint32_t itflag   = htim->Instance->SR;
+ 8003c4c:	691e      	ldr	r6, [r3, #16]
+{
+ 8003c4e:	0004      	movs	r4, r0
+  if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
+ 8003c50:	4216      	tst	r6, r2
+ 8003c52:	d00d      	beq.n	8003c70 <HAL_TIM_IRQHandler+0x2c>
+    if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
+ 8003c54:	4215      	tst	r5, r2
+ 8003c56:	d00b      	beq.n	8003c70 <HAL_TIM_IRQHandler+0x2c>
+        __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
+ 8003c58:	3a05      	subs	r2, #5
+ 8003c5a:	611a      	str	r2, [r3, #16]
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
+ 8003c5c:	3204      	adds	r2, #4
+ 8003c5e:	7702      	strb	r2, [r0, #28]
+        if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
+ 8003c60:	699b      	ldr	r3, [r3, #24]
+ 8003c62:	079b      	lsls	r3, r3, #30
+ 8003c64:	d100      	bne.n	8003c68 <HAL_TIM_IRQHandler+0x24>
+ 8003c66:	e07c      	b.n	8003d62 <HAL_TIM_IRQHandler+0x11e>
+          HAL_TIM_IC_CaptureCallback(htim);
+ 8003c68:	f7ff ffe8 	bl	8003c3c <HAL_TIM_IC_CaptureCallback>
+        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 8003c6c:	2300      	movs	r3, #0
+ 8003c6e:	7723      	strb	r3, [r4, #28]
+  if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
+ 8003c70:	2304      	movs	r3, #4
+ 8003c72:	421e      	tst	r6, r3
+ 8003c74:	d012      	beq.n	8003c9c <HAL_TIM_IRQHandler+0x58>
+    if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
+ 8003c76:	421d      	tst	r5, r3
+ 8003c78:	d010      	beq.n	8003c9c <HAL_TIM_IRQHandler+0x58>
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
+ 8003c7a:	2205      	movs	r2, #5
+ 8003c7c:	6823      	ldr	r3, [r4, #0]
+ 8003c7e:	4252      	negs	r2, r2
+ 8003c80:	611a      	str	r2, [r3, #16]
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
+ 8003c82:	3207      	adds	r2, #7
+ 8003c84:	7722      	strb	r2, [r4, #28]
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ 8003c86:	699a      	ldr	r2, [r3, #24]
+ 8003c88:	23c0      	movs	r3, #192	@ 0xc0
+ 8003c8a:	009b      	lsls	r3, r3, #2
+        HAL_TIM_IC_CaptureCallback(htim);
+ 8003c8c:	0020      	movs	r0, r4
+      if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
+ 8003c8e:	421a      	tst	r2, r3
+ 8003c90:	d100      	bne.n	8003c94 <HAL_TIM_IRQHandler+0x50>
+ 8003c92:	e06c      	b.n	8003d6e <HAL_TIM_IRQHandler+0x12a>
+        HAL_TIM_IC_CaptureCallback(htim);
+ 8003c94:	f7ff ffd2 	bl	8003c3c <HAL_TIM_IC_CaptureCallback>
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 8003c98:	2300      	movs	r3, #0
+ 8003c9a:	7723      	strb	r3, [r4, #28]
+  if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
+ 8003c9c:	2308      	movs	r3, #8
+ 8003c9e:	421e      	tst	r6, r3
+ 8003ca0:	d00f      	beq.n	8003cc2 <HAL_TIM_IRQHandler+0x7e>
+    if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
+ 8003ca2:	421d      	tst	r5, r3
+ 8003ca4:	d00d      	beq.n	8003cc2 <HAL_TIM_IRQHandler+0x7e>
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
+ 8003ca6:	2209      	movs	r2, #9
+ 8003ca8:	6823      	ldr	r3, [r4, #0]
+ 8003caa:	4252      	negs	r2, r2
+ 8003cac:	611a      	str	r2, [r3, #16]
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
+ 8003cae:	320d      	adds	r2, #13
+ 8003cb0:	7722      	strb	r2, [r4, #28]
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ 8003cb2:	69db      	ldr	r3, [r3, #28]
+        HAL_TIM_IC_CaptureCallback(htim);
+ 8003cb4:	0020      	movs	r0, r4
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
+ 8003cb6:	079b      	lsls	r3, r3, #30
+ 8003cb8:	d05f      	beq.n	8003d7a <HAL_TIM_IRQHandler+0x136>
+        HAL_TIM_IC_CaptureCallback(htim);
+ 8003cba:	f7ff ffbf 	bl	8003c3c <HAL_TIM_IC_CaptureCallback>
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 8003cbe:	2300      	movs	r3, #0
+ 8003cc0:	7723      	strb	r3, [r4, #28]
+  if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
+ 8003cc2:	2310      	movs	r3, #16
+ 8003cc4:	421e      	tst	r6, r3
+ 8003cc6:	d011      	beq.n	8003cec <HAL_TIM_IRQHandler+0xa8>
+    if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
+ 8003cc8:	421d      	tst	r5, r3
+ 8003cca:	d00f      	beq.n	8003cec <HAL_TIM_IRQHandler+0xa8>
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
+ 8003ccc:	2211      	movs	r2, #17
+ 8003cce:	6823      	ldr	r3, [r4, #0]
+ 8003cd0:	4252      	negs	r2, r2
+ 8003cd2:	611a      	str	r2, [r3, #16]
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
+ 8003cd4:	3219      	adds	r2, #25
+ 8003cd6:	7722      	strb	r2, [r4, #28]
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ 8003cd8:	69da      	ldr	r2, [r3, #28]
+ 8003cda:	23c0      	movs	r3, #192	@ 0xc0
+ 8003cdc:	009b      	lsls	r3, r3, #2
+        HAL_TIM_IC_CaptureCallback(htim);
+ 8003cde:	0020      	movs	r0, r4
+      if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
+ 8003ce0:	421a      	tst	r2, r3
+ 8003ce2:	d050      	beq.n	8003d86 <HAL_TIM_IRQHandler+0x142>
+        HAL_TIM_IC_CaptureCallback(htim);
+ 8003ce4:	f7ff ffaa 	bl	8003c3c <HAL_TIM_IC_CaptureCallback>
+      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
+ 8003ce8:	2300      	movs	r3, #0
+ 8003cea:	7723      	strb	r3, [r4, #28]
+  if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
+ 8003cec:	2301      	movs	r3, #1
+ 8003cee:	421e      	tst	r6, r3
+ 8003cf0:	d008      	beq.n	8003d04 <HAL_TIM_IRQHandler+0xc0>
+    if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
+ 8003cf2:	421d      	tst	r5, r3
+ 8003cf4:	d006      	beq.n	8003d04 <HAL_TIM_IRQHandler+0xc0>
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
+ 8003cf6:	2202      	movs	r2, #2
+ 8003cf8:	6823      	ldr	r3, [r4, #0]
+ 8003cfa:	4252      	negs	r2, r2
+      HAL_TIM_PeriodElapsedCallback(htim);
+ 8003cfc:	0020      	movs	r0, r4
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
+ 8003cfe:	611a      	str	r2, [r3, #16]
+      HAL_TIM_PeriodElapsedCallback(htim);
+ 8003d00:	f7fc fd70 	bl	80007e4 <HAL_TIM_PeriodElapsedCallback>
+  if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
+ 8003d04:	2382      	movs	r3, #130	@ 0x82
+ 8003d06:	019b      	lsls	r3, r3, #6
+ 8003d08:	421e      	tst	r6, r3
+ 8003d0a:	d007      	beq.n	8003d1c <HAL_TIM_IRQHandler+0xd8>
+    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
+ 8003d0c:	062b      	lsls	r3, r5, #24
+ 8003d0e:	d505      	bpl.n	8003d1c <HAL_TIM_IRQHandler+0xd8>
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
+ 8003d10:	6823      	ldr	r3, [r4, #0]
+ 8003d12:	4a20      	ldr	r2, [pc, #128]	@ (8003d94 <HAL_TIM_IRQHandler+0x150>)
+      HAL_TIMEx_BreakCallback(htim);
+ 8003d14:	0020      	movs	r0, r4
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
+ 8003d16:	611a      	str	r2, [r3, #16]
+      HAL_TIMEx_BreakCallback(htim);
+ 8003d18:	f000 fbb5 	bl	8004486 <HAL_TIMEx_BreakCallback>
+  if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
+ 8003d1c:	05f3      	lsls	r3, r6, #23
+ 8003d1e:	d507      	bpl.n	8003d30 <HAL_TIM_IRQHandler+0xec>
+    if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
+ 8003d20:	062b      	lsls	r3, r5, #24
+ 8003d22:	d505      	bpl.n	8003d30 <HAL_TIM_IRQHandler+0xec>
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+ 8003d24:	6823      	ldr	r3, [r4, #0]
+ 8003d26:	4a1c      	ldr	r2, [pc, #112]	@ (8003d98 <HAL_TIM_IRQHandler+0x154>)
+      HAL_TIMEx_Break2Callback(htim);
+ 8003d28:	0020      	movs	r0, r4
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
+ 8003d2a:	611a      	str	r2, [r3, #16]
+      HAL_TIMEx_Break2Callback(htim);
+ 8003d2c:	f000 fbac 	bl	8004488 <HAL_TIMEx_Break2Callback>
+  if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
+ 8003d30:	2340      	movs	r3, #64	@ 0x40
+ 8003d32:	421e      	tst	r6, r3
+ 8003d34:	d008      	beq.n	8003d48 <HAL_TIM_IRQHandler+0x104>
+    if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
+ 8003d36:	421d      	tst	r5, r3
+ 8003d38:	d006      	beq.n	8003d48 <HAL_TIM_IRQHandler+0x104>
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
+ 8003d3a:	2241      	movs	r2, #65	@ 0x41
+ 8003d3c:	6823      	ldr	r3, [r4, #0]
+ 8003d3e:	4252      	negs	r2, r2
+      HAL_TIM_TriggerCallback(htim);
+ 8003d40:	0020      	movs	r0, r4
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
+ 8003d42:	611a      	str	r2, [r3, #16]
+      HAL_TIM_TriggerCallback(htim);
+ 8003d44:	f7ff ff7c 	bl	8003c40 <HAL_TIM_TriggerCallback>
+  if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
+ 8003d48:	2320      	movs	r3, #32
+ 8003d4a:	421e      	tst	r6, r3
+ 8003d4c:	d008      	beq.n	8003d60 <HAL_TIM_IRQHandler+0x11c>
+    if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
+ 8003d4e:	421d      	tst	r5, r3
+ 8003d50:	d006      	beq.n	8003d60 <HAL_TIM_IRQHandler+0x11c>
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
+ 8003d52:	2221      	movs	r2, #33	@ 0x21
+ 8003d54:	6823      	ldr	r3, [r4, #0]
+ 8003d56:	4252      	negs	r2, r2
+      HAL_TIMEx_CommutCallback(htim);
+ 8003d58:	0020      	movs	r0, r4
+      __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
+ 8003d5a:	611a      	str	r2, [r3, #16]
+      HAL_TIMEx_CommutCallback(htim);
+ 8003d5c:	f000 fb92 	bl	8004484 <HAL_TIMEx_CommutCallback>
+}
+ 8003d60:	bd70      	pop	{r4, r5, r6, pc}
+          HAL_TIM_OC_DelayElapsedCallback(htim);
+ 8003d62:	f7ff ff6a 	bl	8003c3a <HAL_TIM_OC_DelayElapsedCallback>
+          HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 8003d66:	0020      	movs	r0, r4
+ 8003d68:	f7ff ff69 	bl	8003c3e <HAL_TIM_PWM_PulseFinishedCallback>
+ 8003d6c:	e77e      	b.n	8003c6c <HAL_TIM_IRQHandler+0x28>
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+ 8003d6e:	f7ff ff64 	bl	8003c3a <HAL_TIM_OC_DelayElapsedCallback>
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 8003d72:	0020      	movs	r0, r4
+ 8003d74:	f7ff ff63 	bl	8003c3e <HAL_TIM_PWM_PulseFinishedCallback>
+ 8003d78:	e78e      	b.n	8003c98 <HAL_TIM_IRQHandler+0x54>
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+ 8003d7a:	f7ff ff5e 	bl	8003c3a <HAL_TIM_OC_DelayElapsedCallback>
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 8003d7e:	0020      	movs	r0, r4
+ 8003d80:	f7ff ff5d 	bl	8003c3e <HAL_TIM_PWM_PulseFinishedCallback>
+ 8003d84:	e79b      	b.n	8003cbe <HAL_TIM_IRQHandler+0x7a>
+        HAL_TIM_OC_DelayElapsedCallback(htim);
+ 8003d86:	f7ff ff58 	bl	8003c3a <HAL_TIM_OC_DelayElapsedCallback>
+        HAL_TIM_PWM_PulseFinishedCallback(htim);
+ 8003d8a:	0020      	movs	r0, r4
+ 8003d8c:	f7ff ff57 	bl	8003c3e <HAL_TIM_PWM_PulseFinishedCallback>
+ 8003d90:	e7aa      	b.n	8003ce8 <HAL_TIM_IRQHandler+0xa4>
+ 8003d92:	46c0      	nop			@ (mov r8, r8)
+ 8003d94:	ffffdf7f 	.word	0xffffdf7f
+ 8003d98:	fffffeff 	.word	0xfffffeff
+
+08003d9c <TIM_Base_SetConfig>:
+{
+ 8003d9c:	b510      	push	{r4, lr}
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ 8003d9e:	4c1b      	ldr	r4, [pc, #108]	@ (8003e0c <TIM_Base_SetConfig+0x70>)
+  tmpcr1 = TIMx->CR1;
+ 8003da0:	6803      	ldr	r3, [r0, #0]
+  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
+ 8003da2:	42a0      	cmp	r0, r4
+ 8003da4:	d006      	beq.n	8003db4 <TIM_Base_SetConfig+0x18>
+ 8003da6:	2280      	movs	r2, #128	@ 0x80
+ 8003da8:	05d2      	lsls	r2, r2, #23
+ 8003daa:	4290      	cmp	r0, r2
+ 8003dac:	d002      	beq.n	8003db4 <TIM_Base_SetConfig+0x18>
+ 8003dae:	4a18      	ldr	r2, [pc, #96]	@ (8003e10 <TIM_Base_SetConfig+0x74>)
+ 8003db0:	4290      	cmp	r0, r2
+ 8003db2:	d108      	bne.n	8003dc6 <TIM_Base_SetConfig+0x2a>
+    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
+ 8003db4:	2270      	movs	r2, #112	@ 0x70
+ 8003db6:	4393      	bics	r3, r2
+    tmpcr1 |= Structure->CounterMode;
+ 8003db8:	684a      	ldr	r2, [r1, #4]
+ 8003dba:	4313      	orrs	r3, r2
+    tmpcr1 &= ~TIM_CR1_CKD;
+ 8003dbc:	4a15      	ldr	r2, [pc, #84]	@ (8003e14 <TIM_Base_SetConfig+0x78>)
+ 8003dbe:	401a      	ands	r2, r3
+    tmpcr1 |= (uint32_t)Structure->ClockDivision;
+ 8003dc0:	68cb      	ldr	r3, [r1, #12]
+ 8003dc2:	4313      	orrs	r3, r2
+ 8003dc4:	e008      	b.n	8003dd8 <TIM_Base_SetConfig+0x3c>
+  if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
+ 8003dc6:	4a14      	ldr	r2, [pc, #80]	@ (8003e18 <TIM_Base_SetConfig+0x7c>)
+ 8003dc8:	4290      	cmp	r0, r2
+ 8003dca:	d0f7      	beq.n	8003dbc <TIM_Base_SetConfig+0x20>
+ 8003dcc:	4a13      	ldr	r2, [pc, #76]	@ (8003e1c <TIM_Base_SetConfig+0x80>)
+ 8003dce:	4290      	cmp	r0, r2
+ 8003dd0:	d0f4      	beq.n	8003dbc <TIM_Base_SetConfig+0x20>
+ 8003dd2:	4a13      	ldr	r2, [pc, #76]	@ (8003e20 <TIM_Base_SetConfig+0x84>)
+ 8003dd4:	4290      	cmp	r0, r2
+ 8003dd6:	d0f1      	beq.n	8003dbc <TIM_Base_SetConfig+0x20>
+  MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
+ 8003dd8:	2280      	movs	r2, #128	@ 0x80
+ 8003dda:	4393      	bics	r3, r2
+ 8003ddc:	694a      	ldr	r2, [r1, #20]
+ 8003dde:	4313      	orrs	r3, r2
+  TIMx->ARR = (uint32_t)Structure->Period ;
+ 8003de0:	688a      	ldr	r2, [r1, #8]
+ 8003de2:	62c2      	str	r2, [r0, #44]	@ 0x2c
+  TIMx->PSC = Structure->Prescaler;
+ 8003de4:	680a      	ldr	r2, [r1, #0]
+ 8003de6:	6282      	str	r2, [r0, #40]	@ 0x28
+  if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
+ 8003de8:	42a0      	cmp	r0, r4
+ 8003dea:	d005      	beq.n	8003df8 <TIM_Base_SetConfig+0x5c>
+ 8003dec:	4a0b      	ldr	r2, [pc, #44]	@ (8003e1c <TIM_Base_SetConfig+0x80>)
+ 8003dee:	4290      	cmp	r0, r2
+ 8003df0:	d002      	beq.n	8003df8 <TIM_Base_SetConfig+0x5c>
+ 8003df2:	4a0b      	ldr	r2, [pc, #44]	@ (8003e20 <TIM_Base_SetConfig+0x84>)
+ 8003df4:	4290      	cmp	r0, r2
+ 8003df6:	d101      	bne.n	8003dfc <TIM_Base_SetConfig+0x60>
+    TIMx->RCR = Structure->RepetitionCounter;
+ 8003df8:	690a      	ldr	r2, [r1, #16]
+ 8003dfa:	6302      	str	r2, [r0, #48]	@ 0x30
+  SET_BIT(TIMx->CR1, TIM_CR1_URS);
+ 8003dfc:	2204      	movs	r2, #4
+ 8003dfe:	6801      	ldr	r1, [r0, #0]
+ 8003e00:	430a      	orrs	r2, r1
+ 8003e02:	6002      	str	r2, [r0, #0]
+  TIMx->EGR = TIM_EGR_UG;
+ 8003e04:	2201      	movs	r2, #1
+ 8003e06:	6142      	str	r2, [r0, #20]
+  TIMx->CR1 = tmpcr1;
+ 8003e08:	6003      	str	r3, [r0, #0]
+}
+ 8003e0a:	bd10      	pop	{r4, pc}
+ 8003e0c:	40012c00 	.word	0x40012c00
+ 8003e10:	40000400 	.word	0x40000400
+ 8003e14:	fffffcff 	.word	0xfffffcff
+ 8003e18:	40002000 	.word	0x40002000
+ 8003e1c:	40014400 	.word	0x40014400
+ 8003e20:	40014800 	.word	0x40014800
+
+08003e24 <HAL_TIM_Base_Init>:
+{
+ 8003e24:	b570      	push	{r4, r5, r6, lr}
+ 8003e26:	0004      	movs	r4, r0
+    return HAL_ERROR;
+ 8003e28:	2001      	movs	r0, #1
+  if (htim == NULL)
+ 8003e2a:	2c00      	cmp	r4, #0
+ 8003e2c:	d023      	beq.n	8003e76 <HAL_TIM_Base_Init+0x52>
+  if (htim->State == HAL_TIM_STATE_RESET)
+ 8003e2e:	0025      	movs	r5, r4
+ 8003e30:	353d      	adds	r5, #61	@ 0x3d
+ 8003e32:	782b      	ldrb	r3, [r5, #0]
+ 8003e34:	b2da      	uxtb	r2, r3
+ 8003e36:	2b00      	cmp	r3, #0
+ 8003e38:	d105      	bne.n	8003e46 <HAL_TIM_Base_Init+0x22>
+    htim->Lock = HAL_UNLOCKED;
+ 8003e3a:	0023      	movs	r3, r4
+ 8003e3c:	333c      	adds	r3, #60	@ 0x3c
+    HAL_TIM_Base_MspInit(htim);
+ 8003e3e:	0020      	movs	r0, r4
+    htim->Lock = HAL_UNLOCKED;
+ 8003e40:	701a      	strb	r2, [r3, #0]
+    HAL_TIM_Base_MspInit(htim);
+ 8003e42:	f7fe fb37 	bl	80024b4 <HAL_TIM_Base_MspInit>
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8003e46:	2302      	movs	r3, #2
+ 8003e48:	702b      	strb	r3, [r5, #0]
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 8003e4a:	6820      	ldr	r0, [r4, #0]
+ 8003e4c:	1d21      	adds	r1, r4, #4
+ 8003e4e:	f7ff ffa5 	bl	8003d9c <TIM_Base_SetConfig>
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 8003e52:	0022      	movs	r2, r4
+ 8003e54:	2301      	movs	r3, #1
+  return HAL_OK;
+ 8003e56:	2000      	movs	r0, #0
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 8003e58:	3248      	adds	r2, #72	@ 0x48
+ 8003e5a:	7013      	strb	r3, [r2, #0]
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 8003e5c:	3447      	adds	r4, #71	@ 0x47
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 8003e5e:	3a0a      	subs	r2, #10
+ 8003e60:	7013      	strb	r3, [r2, #0]
+ 8003e62:	7053      	strb	r3, [r2, #1]
+ 8003e64:	7093      	strb	r3, [r2, #2]
+ 8003e66:	70d3      	strb	r3, [r2, #3]
+ 8003e68:	7113      	strb	r3, [r2, #4]
+ 8003e6a:	7153      	strb	r3, [r2, #5]
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 8003e6c:	7193      	strb	r3, [r2, #6]
+ 8003e6e:	71d3      	strb	r3, [r2, #7]
+ 8003e70:	7213      	strb	r3, [r2, #8]
+ 8003e72:	7023      	strb	r3, [r4, #0]
+  htim->State = HAL_TIM_STATE_READY;
+ 8003e74:	702b      	strb	r3, [r5, #0]
+}
+ 8003e76:	bd70      	pop	{r4, r5, r6, pc}
+
+08003e78 <HAL_TIM_PWM_Init>:
+{
+ 8003e78:	b570      	push	{r4, r5, r6, lr}
+ 8003e7a:	0004      	movs	r4, r0
+    return HAL_ERROR;
+ 8003e7c:	2001      	movs	r0, #1
+  if (htim == NULL)
+ 8003e7e:	2c00      	cmp	r4, #0
+ 8003e80:	d023      	beq.n	8003eca <HAL_TIM_PWM_Init+0x52>
+  if (htim->State == HAL_TIM_STATE_RESET)
+ 8003e82:	0025      	movs	r5, r4
+ 8003e84:	353d      	adds	r5, #61	@ 0x3d
+ 8003e86:	782b      	ldrb	r3, [r5, #0]
+ 8003e88:	b2da      	uxtb	r2, r3
+ 8003e8a:	2b00      	cmp	r3, #0
+ 8003e8c:	d105      	bne.n	8003e9a <HAL_TIM_PWM_Init+0x22>
+    htim->Lock = HAL_UNLOCKED;
+ 8003e8e:	0023      	movs	r3, r4
+ 8003e90:	333c      	adds	r3, #60	@ 0x3c
+    HAL_TIM_PWM_MspInit(htim);
+ 8003e92:	0020      	movs	r0, r4
+    htim->Lock = HAL_UNLOCKED;
+ 8003e94:	701a      	strb	r2, [r3, #0]
+    HAL_TIM_PWM_MspInit(htim);
+ 8003e96:	f7ff fe77 	bl	8003b88 <HAL_TIM_PWM_MspInit>
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8003e9a:	2302      	movs	r3, #2
+ 8003e9c:	702b      	strb	r3, [r5, #0]
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 8003e9e:	6820      	ldr	r0, [r4, #0]
+ 8003ea0:	1d21      	adds	r1, r4, #4
+ 8003ea2:	f7ff ff7b 	bl	8003d9c <TIM_Base_SetConfig>
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 8003ea6:	0022      	movs	r2, r4
+ 8003ea8:	2301      	movs	r3, #1
+  return HAL_OK;
+ 8003eaa:	2000      	movs	r0, #0
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 8003eac:	3248      	adds	r2, #72	@ 0x48
+ 8003eae:	7013      	strb	r3, [r2, #0]
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 8003eb0:	3447      	adds	r4, #71	@ 0x47
+  TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 8003eb2:	3a0a      	subs	r2, #10
+ 8003eb4:	7013      	strb	r3, [r2, #0]
+ 8003eb6:	7053      	strb	r3, [r2, #1]
+ 8003eb8:	7093      	strb	r3, [r2, #2]
+ 8003eba:	70d3      	strb	r3, [r2, #3]
+ 8003ebc:	7113      	strb	r3, [r2, #4]
+ 8003ebe:	7153      	strb	r3, [r2, #5]
+  TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
+ 8003ec0:	7193      	strb	r3, [r2, #6]
+ 8003ec2:	71d3      	strb	r3, [r2, #7]
+ 8003ec4:	7213      	strb	r3, [r2, #8]
+ 8003ec6:	7023      	strb	r3, [r4, #0]
+  htim->State = HAL_TIM_STATE_READY;
+ 8003ec8:	702b      	strb	r3, [r5, #0]
+}
+ 8003eca:	bd70      	pop	{r4, r5, r6, pc}
+
+08003ecc <HAL_TIM_Encoder_Init>:
+{
+ 8003ecc:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+ 8003ece:	0004      	movs	r4, r0
+ 8003ed0:	000d      	movs	r5, r1
+    return HAL_ERROR;
+ 8003ed2:	2001      	movs	r0, #1
+  if (htim == NULL)
+ 8003ed4:	2c00      	cmp	r4, #0
+ 8003ed6:	d047      	beq.n	8003f68 <HAL_TIM_Encoder_Init+0x9c>
+  if (htim->State == HAL_TIM_STATE_RESET)
+ 8003ed8:	0026      	movs	r6, r4
+ 8003eda:	363d      	adds	r6, #61	@ 0x3d
+ 8003edc:	7833      	ldrb	r3, [r6, #0]
+ 8003ede:	b2da      	uxtb	r2, r3
+ 8003ee0:	2b00      	cmp	r3, #0
+ 8003ee2:	d105      	bne.n	8003ef0 <HAL_TIM_Encoder_Init+0x24>
+    htim->Lock = HAL_UNLOCKED;
+ 8003ee4:	0023      	movs	r3, r4
+ 8003ee6:	333c      	adds	r3, #60	@ 0x3c
+    HAL_TIM_Encoder_MspInit(htim);
+ 8003ee8:	0020      	movs	r0, r4
+    htim->Lock = HAL_UNLOCKED;
+ 8003eea:	701a      	strb	r2, [r3, #0]
+    HAL_TIM_Encoder_MspInit(htim);
+ 8003eec:	f7fe fb3c 	bl	8002568 <HAL_TIM_Encoder_MspInit>
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8003ef0:	2302      	movs	r3, #2
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+ 8003ef2:	0021      	movs	r1, r4
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8003ef4:	7033      	strb	r3, [r6, #0]
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+ 8003ef6:	c980      	ldmia	r1!, {r7}
+ 8003ef8:	4a1c      	ldr	r2, [pc, #112]	@ (8003f6c <HAL_TIM_Encoder_Init+0xa0>)
+ 8003efa:	68bb      	ldr	r3, [r7, #8]
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 8003efc:	0038      	movs	r0, r7
+  htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
+ 8003efe:	4013      	ands	r3, r2
+ 8003f00:	60bb      	str	r3, [r7, #8]
+  TIM_Base_SetConfig(htim->Instance, &htim->Init);
+ 8003f02:	f7ff ff4b 	bl	8003d9c <TIM_Base_SetConfig>
+  tmpsmcr = htim->Instance->SMCR;
+ 8003f06:	68b9      	ldr	r1, [r7, #8]
+  tmpsmcr |= sConfig->EncoderMode;
+ 8003f08:	682a      	ldr	r2, [r5, #0]
+  tmpccmr1 = htim->Instance->CCMR1;
+ 8003f0a:	69bb      	ldr	r3, [r7, #24]
+  tmpsmcr |= sConfig->EncoderMode;
+ 8003f0c:	4311      	orrs	r1, r2
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ 8003f0e:	4a18      	ldr	r2, [pc, #96]	@ (8003f70 <HAL_TIM_Encoder_Init+0xa4>)
+  tmpsmcr |= sConfig->EncoderMode;
+ 8003f10:	9101      	str	r1, [sp, #4]
+  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
+ 8003f12:	4013      	ands	r3, r2
+  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
+ 8003f14:	69aa      	ldr	r2, [r5, #24]
+ 8003f16:	68a9      	ldr	r1, [r5, #8]
+ 8003f18:	0212      	lsls	r2, r2, #8
+ 8003f1a:	430a      	orrs	r2, r1
+ 8003f1c:	431a      	orrs	r2, r3
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ 8003f1e:	4b15      	ldr	r3, [pc, #84]	@ (8003f74 <HAL_TIM_Encoder_Init+0xa8>)
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 8003f20:	6929      	ldr	r1, [r5, #16]
+  tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
+ 8003f22:	401a      	ands	r2, r3
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ 8003f24:	69eb      	ldr	r3, [r5, #28]
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 8003f26:	0109      	lsls	r1, r1, #4
+  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
+ 8003f28:	021b      	lsls	r3, r3, #8
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 8003f2a:	430b      	orrs	r3, r1
+ 8003f2c:	68e9      	ldr	r1, [r5, #12]
+  tmpccer = htim->Instance->CCER;
+ 8003f2e:	6a38      	ldr	r0, [r7, #32]
+  tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
+ 8003f30:	430b      	orrs	r3, r1
+ 8003f32:	6a29      	ldr	r1, [r5, #32]
+ 8003f34:	0309      	lsls	r1, r1, #12
+ 8003f36:	430b      	orrs	r3, r1
+ 8003f38:	4313      	orrs	r3, r2
+  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
+ 8003f3a:	22aa      	movs	r2, #170	@ 0xaa
+ 8003f3c:	4390      	bics	r0, r2
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+ 8003f3e:	696a      	ldr	r2, [r5, #20]
+ 8003f40:	686d      	ldr	r5, [r5, #4]
+ 8003f42:	0112      	lsls	r2, r2, #4
+  htim->Instance->SMCR = tmpsmcr;
+ 8003f44:	9901      	ldr	r1, [sp, #4]
+  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
+ 8003f46:	432a      	orrs	r2, r5
+ 8003f48:	4302      	orrs	r2, r0
+  htim->Instance->SMCR = tmpsmcr;
+ 8003f4a:	60b9      	str	r1, [r7, #8]
+  htim->Instance->CCMR1 = tmpccmr1;
+ 8003f4c:	61bb      	str	r3, [r7, #24]
+  htim->Instance->CCER = tmpccer;
+ 8003f4e:	623a      	str	r2, [r7, #32]
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 8003f50:	0022      	movs	r2, r4
+ 8003f52:	2301      	movs	r3, #1
+  return HAL_OK;
+ 8003f54:	2000      	movs	r0, #0
+  htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
+ 8003f56:	3248      	adds	r2, #72	@ 0x48
+ 8003f58:	7013      	strb	r3, [r2, #0]
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 8003f5a:	3445      	adds	r4, #69	@ 0x45
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 8003f5c:	3a0a      	subs	r2, #10
+ 8003f5e:	7013      	strb	r3, [r2, #0]
+  TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 8003f60:	7053      	strb	r3, [r2, #1]
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
+ 8003f62:	7193      	strb	r3, [r2, #6]
+  TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
+ 8003f64:	7023      	strb	r3, [r4, #0]
+  htim->State = HAL_TIM_STATE_READY;
+ 8003f66:	7033      	strb	r3, [r6, #0]
+}
+ 8003f68:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+ 8003f6a:	46c0      	nop			@ (mov r8, r8)
+ 8003f6c:	fffebff8 	.word	0xfffebff8
+ 8003f70:	fffffcfc 	.word	0xfffffcfc
+ 8003f74:	ffff0303 	.word	0xffff0303
+
+08003f78 <TIM_OC2_SetConfig>:
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+ 8003f78:	2210      	movs	r2, #16
+{
+ 8003f7a:	b570      	push	{r4, r5, r6, lr}
+  tmpccer = TIMx->CCER;
+ 8003f7c:	6a05      	ldr	r5, [r0, #32]
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+ 8003f7e:	6a03      	ldr	r3, [r0, #32]
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+ 8003f80:	4c16      	ldr	r4, [pc, #88]	@ (8003fdc <TIM_OC2_SetConfig+0x64>)
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+ 8003f82:	4393      	bics	r3, r2
+ 8003f84:	6203      	str	r3, [r0, #32]
+  tmpcr2 =  TIMx->CR2;
+ 8003f86:	6842      	ldr	r2, [r0, #4]
+  tmpccmrx = TIMx->CCMR1;
+ 8003f88:	6983      	ldr	r3, [r0, #24]
+  tmpccmrx &= ~TIM_CCMR1_CC2S;
+ 8003f8a:	4023      	ands	r3, r4
+  tmpccmrx |= (OC_Config->OCMode << 8U);
+ 8003f8c:	680c      	ldr	r4, [r1, #0]
+ 8003f8e:	0224      	lsls	r4, r4, #8
+ 8003f90:	431c      	orrs	r4, r3
+  tmpccer &= ~TIM_CCER_CC2P;
+ 8003f92:	2320      	movs	r3, #32
+ 8003f94:	439d      	bics	r5, r3
+  tmpccer |= (OC_Config->OCPolarity << 4U);
+ 8003f96:	688b      	ldr	r3, [r1, #8]
+ 8003f98:	011b      	lsls	r3, r3, #4
+ 8003f9a:	432b      	orrs	r3, r5
+  if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
+ 8003f9c:	4d10      	ldr	r5, [pc, #64]	@ (8003fe0 <TIM_OC2_SetConfig+0x68>)
+ 8003f9e:	42a8      	cmp	r0, r5
+ 8003fa0:	d10f      	bne.n	8003fc2 <TIM_OC2_SetConfig+0x4a>
+    tmpccer &= ~TIM_CCER_CC2NP;
+ 8003fa2:	2580      	movs	r5, #128	@ 0x80
+ 8003fa4:	43ab      	bics	r3, r5
+ 8003fa6:	001e      	movs	r6, r3
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+ 8003fa8:	68cb      	ldr	r3, [r1, #12]
+    tmpccer &= ~TIM_CCER_CC2NE;
+ 8003faa:	3d40      	subs	r5, #64	@ 0x40
+    tmpccer |= (OC_Config->OCNPolarity << 4U);
+ 8003fac:	011b      	lsls	r3, r3, #4
+ 8003fae:	4333      	orrs	r3, r6
+    tmpccer &= ~TIM_CCER_CC2NE;
+ 8003fb0:	43ab      	bics	r3, r5
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+ 8003fb2:	4d0c      	ldr	r5, [pc, #48]	@ (8003fe4 <TIM_OC2_SetConfig+0x6c>)
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+ 8003fb4:	698e      	ldr	r6, [r1, #24]
+    tmpcr2 &= ~TIM_CR2_OIS2N;
+ 8003fb6:	4015      	ands	r5, r2
+    tmpcr2 |= (OC_Config->OCNIdleState << 2U);
+ 8003fb8:	694a      	ldr	r2, [r1, #20]
+ 8003fba:	4332      	orrs	r2, r6
+ 8003fbc:	0092      	lsls	r2, r2, #2
+ 8003fbe:	432a      	orrs	r2, r5
+ 8003fc0:	e005      	b.n	8003fce <TIM_OC2_SetConfig+0x56>
+  if (IS_TIM_BREAK_INSTANCE(TIMx))
+ 8003fc2:	4d09      	ldr	r5, [pc, #36]	@ (8003fe8 <TIM_OC2_SetConfig+0x70>)
+ 8003fc4:	42a8      	cmp	r0, r5
+ 8003fc6:	d0f4      	beq.n	8003fb2 <TIM_OC2_SetConfig+0x3a>
+ 8003fc8:	4d08      	ldr	r5, [pc, #32]	@ (8003fec <TIM_OC2_SetConfig+0x74>)
+ 8003fca:	42a8      	cmp	r0, r5
+ 8003fcc:	d0f1      	beq.n	8003fb2 <TIM_OC2_SetConfig+0x3a>
+  TIMx->CR2 = tmpcr2;
+ 8003fce:	6042      	str	r2, [r0, #4]
+  TIMx->CCR2 = OC_Config->Pulse;
+ 8003fd0:	684a      	ldr	r2, [r1, #4]
+  TIMx->CCMR1 = tmpccmrx;
+ 8003fd2:	6184      	str	r4, [r0, #24]
+  TIMx->CCR2 = OC_Config->Pulse;
+ 8003fd4:	6382      	str	r2, [r0, #56]	@ 0x38
+  TIMx->CCER = tmpccer;
+ 8003fd6:	6203      	str	r3, [r0, #32]
+}
+ 8003fd8:	bd70      	pop	{r4, r5, r6, pc}
+ 8003fda:	46c0      	nop			@ (mov r8, r8)
+ 8003fdc:	feff8cff 	.word	0xfeff8cff
+ 8003fe0:	40012c00 	.word	0x40012c00
+ 8003fe4:	fffff3ff 	.word	0xfffff3ff
+ 8003fe8:	40014400 	.word	0x40014400
+ 8003fec:	40014800 	.word	0x40014800
+
+08003ff0 <HAL_TIM_PWM_ConfigChannel>:
+{
+ 8003ff0:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+  __HAL_LOCK(htim);
+ 8003ff2:	0007      	movs	r7, r0
+ 8003ff4:	373c      	adds	r7, #60	@ 0x3c
+{
+ 8003ff6:	0015      	movs	r5, r2
+  __HAL_LOCK(htim);
+ 8003ff8:	783a      	ldrb	r2, [r7, #0]
+{
+ 8003ffa:	0003      	movs	r3, r0
+ 8003ffc:	000c      	movs	r4, r1
+  __HAL_LOCK(htim);
+ 8003ffe:	2002      	movs	r0, #2
+ 8004000:	2a01      	cmp	r2, #1
+ 8004002:	d00c      	beq.n	800401e <HAL_TIM_PWM_ConfigChannel+0x2e>
+ 8004004:	3801      	subs	r0, #1
+ 8004006:	7038      	strb	r0, [r7, #0]
+  switch (Channel)
+ 8004008:	2d0c      	cmp	r5, #12
+ 800400a:	d051      	beq.n	80040b0 <HAL_TIM_PWM_ConfigChannel+0xc0>
+ 800400c:	d808      	bhi.n	8004020 <HAL_TIM_PWM_ConfigChannel+0x30>
+ 800400e:	2d04      	cmp	r5, #4
+ 8004010:	d02d      	beq.n	800406e <HAL_TIM_PWM_ConfigChannel+0x7e>
+ 8004012:	2d08      	cmp	r5, #8
+ 8004014:	d03c      	beq.n	8004090 <HAL_TIM_PWM_ConfigChannel+0xa0>
+ 8004016:	2d00      	cmp	r5, #0
+ 8004018:	d017      	beq.n	800404a <HAL_TIM_PWM_ConfigChannel+0x5a>
+  __HAL_UNLOCK(htim);
+ 800401a:	2300      	movs	r3, #0
+ 800401c:	703b      	strb	r3, [r7, #0]
+}
+ 800401e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+  switch (Channel)
+ 8004020:	2d10      	cmp	r5, #16
+ 8004022:	d058      	beq.n	80040d6 <HAL_TIM_PWM_ConfigChannel+0xe6>
+ 8004024:	2d14      	cmp	r5, #20
+ 8004026:	d1f8      	bne.n	800401a <HAL_TIM_PWM_ConfigChannel+0x2a>
+      TIM_OC6_SetConfig(htim->Instance, sConfig);
+ 8004028:	681d      	ldr	r5, [r3, #0]
+ 800402a:	0028      	movs	r0, r5
+ 800402c:	f7ff fd32 	bl	8003a94 <TIM_OC6_SetConfig>
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
+ 8004030:	2380      	movs	r3, #128	@ 0x80
+ 8004032:	6d6a      	ldr	r2, [r5, #84]	@ 0x54
+ 8004034:	011b      	lsls	r3, r3, #4
+ 8004036:	4313      	orrs	r3, r2
+ 8004038:	656b      	str	r3, [r5, #84]	@ 0x54
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
+ 800403a:	6d6b      	ldr	r3, [r5, #84]	@ 0x54
+ 800403c:	4a2e      	ldr	r2, [pc, #184]	@ (80040f8 <HAL_TIM_PWM_ConfigChannel+0x108>)
+ 800403e:	4013      	ands	r3, r2
+ 8004040:	656b      	str	r3, [r5, #84]	@ 0x54
+      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ 8004042:	6923      	ldr	r3, [r4, #16]
+ 8004044:	6d6a      	ldr	r2, [r5, #84]	@ 0x54
+ 8004046:	021b      	lsls	r3, r3, #8
+ 8004048:	e053      	b.n	80040f2 <HAL_TIM_PWM_ConfigChannel+0x102>
+      TIM_OC1_SetConfig(htim->Instance, sConfig);
+ 800404a:	681d      	ldr	r5, [r3, #0]
+ 800404c:	0028      	movs	r0, r5
+ 800404e:	f7ff fc45 	bl	80038dc <TIM_OC1_SetConfig>
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+ 8004052:	2308      	movs	r3, #8
+ 8004054:	69aa      	ldr	r2, [r5, #24]
+ 8004056:	4313      	orrs	r3, r2
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ 8004058:	2204      	movs	r2, #4
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
+ 800405a:	61ab      	str	r3, [r5, #24]
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
+ 800405c:	69ab      	ldr	r3, [r5, #24]
+ 800405e:	4393      	bics	r3, r2
+ 8004060:	61ab      	str	r3, [r5, #24]
+      htim->Instance->CCMR1 |= sConfig->OCFastMode;
+ 8004062:	69ab      	ldr	r3, [r5, #24]
+ 8004064:	6922      	ldr	r2, [r4, #16]
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ 8004066:	4313      	orrs	r3, r2
+ 8004068:	61ab      	str	r3, [r5, #24]
+  HAL_StatusTypeDef status = HAL_OK;
+ 800406a:	2000      	movs	r0, #0
+ 800406c:	e7d5      	b.n	800401a <HAL_TIM_PWM_ConfigChannel+0x2a>
+      TIM_OC2_SetConfig(htim->Instance, sConfig);
+ 800406e:	681d      	ldr	r5, [r3, #0]
+ 8004070:	0028      	movs	r0, r5
+ 8004072:	f7ff ff81 	bl	8003f78 <TIM_OC2_SetConfig>
+      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
+ 8004076:	2380      	movs	r3, #128	@ 0x80
+ 8004078:	69aa      	ldr	r2, [r5, #24]
+ 800407a:	011b      	lsls	r3, r3, #4
+ 800407c:	4313      	orrs	r3, r2
+ 800407e:	61ab      	str	r3, [r5, #24]
+      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
+ 8004080:	69ab      	ldr	r3, [r5, #24]
+ 8004082:	4a1d      	ldr	r2, [pc, #116]	@ (80040f8 <HAL_TIM_PWM_ConfigChannel+0x108>)
+ 8004084:	4013      	ands	r3, r2
+ 8004086:	61ab      	str	r3, [r5, #24]
+      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
+ 8004088:	6923      	ldr	r3, [r4, #16]
+ 800408a:	69aa      	ldr	r2, [r5, #24]
+ 800408c:	021b      	lsls	r3, r3, #8
+ 800408e:	e7ea      	b.n	8004066 <HAL_TIM_PWM_ConfigChannel+0x76>
+      TIM_OC3_SetConfig(htim->Instance, sConfig);
+ 8004090:	681e      	ldr	r6, [r3, #0]
+ 8004092:	0030      	movs	r0, r6
+ 8004094:	f7ff fc58 	bl	8003948 <TIM_OC3_SetConfig>
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ 8004098:	2204      	movs	r2, #4
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
+ 800409a:	69f3      	ldr	r3, [r6, #28]
+ 800409c:	431d      	orrs	r5, r3
+ 800409e:	61f5      	str	r5, [r6, #28]
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
+ 80040a0:	69f3      	ldr	r3, [r6, #28]
+ 80040a2:	4393      	bics	r3, r2
+ 80040a4:	61f3      	str	r3, [r6, #28]
+      htim->Instance->CCMR2 |= sConfig->OCFastMode;
+ 80040a6:	69f3      	ldr	r3, [r6, #28]
+ 80040a8:	6922      	ldr	r2, [r4, #16]
+ 80040aa:	4313      	orrs	r3, r2
+ 80040ac:	61f3      	str	r3, [r6, #28]
+      break;
+ 80040ae:	e7dc      	b.n	800406a <HAL_TIM_PWM_ConfigChannel+0x7a>
+      TIM_OC4_SetConfig(htim->Instance, sConfig);
+ 80040b0:	681d      	ldr	r5, [r3, #0]
+ 80040b2:	0028      	movs	r0, r5
+ 80040b4:	f7ff fc8a 	bl	80039cc <TIM_OC4_SetConfig>
+      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
+ 80040b8:	2380      	movs	r3, #128	@ 0x80
+ 80040ba:	69ea      	ldr	r2, [r5, #28]
+ 80040bc:	011b      	lsls	r3, r3, #4
+ 80040be:	4313      	orrs	r3, r2
+ 80040c0:	61eb      	str	r3, [r5, #28]
+      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
+ 80040c2:	69eb      	ldr	r3, [r5, #28]
+ 80040c4:	4a0c      	ldr	r2, [pc, #48]	@ (80040f8 <HAL_TIM_PWM_ConfigChannel+0x108>)
+ 80040c6:	4013      	ands	r3, r2
+ 80040c8:	61eb      	str	r3, [r5, #28]
+      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
+ 80040ca:	6923      	ldr	r3, [r4, #16]
+ 80040cc:	69ea      	ldr	r2, [r5, #28]
+ 80040ce:	021b      	lsls	r3, r3, #8
+ 80040d0:	4313      	orrs	r3, r2
+ 80040d2:	61eb      	str	r3, [r5, #28]
+      break;
+ 80040d4:	e7c9      	b.n	800406a <HAL_TIM_PWM_ConfigChannel+0x7a>
+      TIM_OC5_SetConfig(htim->Instance, sConfig);
+ 80040d6:	681d      	ldr	r5, [r3, #0]
+ 80040d8:	0028      	movs	r0, r5
+ 80040da:	f7ff fcab 	bl	8003a34 <TIM_OC5_SetConfig>
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+ 80040de:	2308      	movs	r3, #8
+ 80040e0:	6d6a      	ldr	r2, [r5, #84]	@ 0x54
+ 80040e2:	4313      	orrs	r3, r2
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+ 80040e4:	2204      	movs	r2, #4
+      htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
+ 80040e6:	656b      	str	r3, [r5, #84]	@ 0x54
+      htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
+ 80040e8:	6d6b      	ldr	r3, [r5, #84]	@ 0x54
+ 80040ea:	4393      	bics	r3, r2
+ 80040ec:	656b      	str	r3, [r5, #84]	@ 0x54
+      htim->Instance->CCMR3 |= sConfig->OCFastMode;
+ 80040ee:	6d6b      	ldr	r3, [r5, #84]	@ 0x54
+ 80040f0:	6922      	ldr	r2, [r4, #16]
+      htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
+ 80040f2:	4313      	orrs	r3, r2
+ 80040f4:	656b      	str	r3, [r5, #84]	@ 0x54
+      break;
+ 80040f6:	e7b8      	b.n	800406a <HAL_TIM_PWM_ConfigChannel+0x7a>
+ 80040f8:	fffffbff 	.word	0xfffffbff
+
+080040fc <TIM_ETR_SetConfig>:
+{
+ 80040fc:	b530      	push	{r4, r5, lr}
+  tmpsmcr = TIMx->SMCR;
+ 80040fe:	6884      	ldr	r4, [r0, #8]
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 8004100:	4d03      	ldr	r5, [pc, #12]	@ (8004110 <TIM_ETR_SetConfig+0x14>)
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+ 8004102:	430a      	orrs	r2, r1
+ 8004104:	021b      	lsls	r3, r3, #8
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 8004106:	402c      	ands	r4, r5
+  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
+ 8004108:	4313      	orrs	r3, r2
+ 800410a:	4323      	orrs	r3, r4
+  TIMx->SMCR = tmpsmcr;
+ 800410c:	6083      	str	r3, [r0, #8]
+}
+ 800410e:	bd30      	pop	{r4, r5, pc}
+ 8004110:	ffff00ff 	.word	0xffff00ff
+
+08004114 <HAL_TIM_ConfigClockSource>:
+{
+ 8004114:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+  __HAL_LOCK(htim);
+ 8004116:	0005      	movs	r5, r0
+ 8004118:	2202      	movs	r2, #2
+ 800411a:	353c      	adds	r5, #60	@ 0x3c
+ 800411c:	782c      	ldrb	r4, [r5, #0]
+{
+ 800411e:	0003      	movs	r3, r0
+  __HAL_LOCK(htim);
+ 8004120:	0010      	movs	r0, r2
+ 8004122:	2c01      	cmp	r4, #1
+ 8004124:	d01b      	beq.n	800415e <HAL_TIM_ConfigClockSource+0x4a>
+  htim->State = HAL_TIM_STATE_BUSY;
+ 8004126:	001e      	movs	r6, r3
+  __HAL_LOCK(htim);
+ 8004128:	3801      	subs	r0, #1
+  htim->State = HAL_TIM_STATE_BUSY;
+ 800412a:	363d      	adds	r6, #61	@ 0x3d
+  __HAL_LOCK(htim);
+ 800412c:	7028      	strb	r0, [r5, #0]
+  htim->State = HAL_TIM_STATE_BUSY;
+ 800412e:	7032      	strb	r2, [r6, #0]
+  tmpsmcr = htim->Instance->SMCR;
+ 8004130:	681c      	ldr	r4, [r3, #0]
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 8004132:	4a41      	ldr	r2, [pc, #260]	@ (8004238 <HAL_TIM_ConfigClockSource+0x124>)
+  tmpsmcr = htim->Instance->SMCR;
+ 8004134:	68a3      	ldr	r3, [r4, #8]
+  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
+ 8004136:	4013      	ands	r3, r2
+  htim->Instance->SMCR = tmpsmcr;
+ 8004138:	60a3      	str	r3, [r4, #8]
+  switch (sClockSourceConfig->ClockSource)
+ 800413a:	680b      	ldr	r3, [r1, #0]
+ 800413c:	2b60      	cmp	r3, #96	@ 0x60
+ 800413e:	d04e      	beq.n	80041de <HAL_TIM_ConfigClockSource+0xca>
+ 8004140:	d82d      	bhi.n	800419e <HAL_TIM_ConfigClockSource+0x8a>
+ 8004142:	2b40      	cmp	r3, #64	@ 0x40
+ 8004144:	d062      	beq.n	800420c <HAL_TIM_ConfigClockSource+0xf8>
+ 8004146:	d813      	bhi.n	8004170 <HAL_TIM_ConfigClockSource+0x5c>
+ 8004148:	2b20      	cmp	r3, #32
+ 800414a:	d00b      	beq.n	8004164 <HAL_TIM_ConfigClockSource+0x50>
+ 800414c:	d808      	bhi.n	8004160 <HAL_TIM_ConfigClockSource+0x4c>
+ 800414e:	2210      	movs	r2, #16
+ 8004150:	0019      	movs	r1, r3
+ 8004152:	4391      	bics	r1, r2
+ 8004154:	d006      	beq.n	8004164 <HAL_TIM_ConfigClockSource+0x50>
+  htim->State = HAL_TIM_STATE_READY;
+ 8004156:	2301      	movs	r3, #1
+ 8004158:	7033      	strb	r3, [r6, #0]
+  __HAL_UNLOCK(htim);
+ 800415a:	2300      	movs	r3, #0
+ 800415c:	702b      	strb	r3, [r5, #0]
+}
+ 800415e:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+  switch (sClockSourceConfig->ClockSource)
+ 8004160:	2b30      	cmp	r3, #48	@ 0x30
+ 8004162:	d1f8      	bne.n	8004156 <HAL_TIM_ConfigClockSource+0x42>
+  tmpsmcr = TIMx->SMCR;
+ 8004164:	68a2      	ldr	r2, [r4, #8]
+  tmpsmcr &= ~TIM_SMCR_TS;
+ 8004166:	4935      	ldr	r1, [pc, #212]	@ (800423c <HAL_TIM_ConfigClockSource+0x128>)
+ 8004168:	400a      	ands	r2, r1
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ 800416a:	4313      	orrs	r3, r2
+ 800416c:	2207      	movs	r2, #7
+ 800416e:	e028      	b.n	80041c2 <HAL_TIM_ConfigClockSource+0xae>
+  switch (sClockSourceConfig->ClockSource)
+ 8004170:	2b50      	cmp	r3, #80	@ 0x50
+ 8004172:	d1f0      	bne.n	8004156 <HAL_TIM_ConfigClockSource+0x42>
+                               sClockSourceConfig->ClockPolarity,
+ 8004174:	684a      	ldr	r2, [r1, #4]
+                               sClockSourceConfig->ClockFilter);
+ 8004176:	68cb      	ldr	r3, [r1, #12]
+  tmpccer = TIMx->CCER;
+ 8004178:	6a21      	ldr	r1, [r4, #32]
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+ 800417a:	6a27      	ldr	r7, [r4, #32]
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+ 800417c:	011b      	lsls	r3, r3, #4
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+ 800417e:	4387      	bics	r7, r0
+ 8004180:	6227      	str	r7, [r4, #32]
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ 8004182:	27f0      	movs	r7, #240	@ 0xf0
+  tmpccmr1 = TIMx->CCMR1;
+ 8004184:	69a0      	ldr	r0, [r4, #24]
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ 8004186:	43b8      	bics	r0, r7
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+ 8004188:	4303      	orrs	r3, r0
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ 800418a:	200a      	movs	r0, #10
+ 800418c:	4381      	bics	r1, r0
+  tmpccer |= TIM_ICPolarity;
+ 800418e:	430a      	orrs	r2, r1
+  TIMx->CCMR1 = tmpccmr1;
+ 8004190:	61a3      	str	r3, [r4, #24]
+  TIMx->CCER = tmpccer;
+ 8004192:	6222      	str	r2, [r4, #32]
+  tmpsmcr &= ~TIM_SMCR_TS;
+ 8004194:	4b29      	ldr	r3, [pc, #164]	@ (800423c <HAL_TIM_ConfigClockSource+0x128>)
+  tmpsmcr = TIMx->SMCR;
+ 8004196:	68a2      	ldr	r2, [r4, #8]
+  tmpsmcr &= ~TIM_SMCR_TS;
+ 8004198:	401a      	ands	r2, r3
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ 800419a:	2357      	movs	r3, #87	@ 0x57
+ 800419c:	e011      	b.n	80041c2 <HAL_TIM_ConfigClockSource+0xae>
+  switch (sClockSourceConfig->ClockSource)
+ 800419e:	2280      	movs	r2, #128	@ 0x80
+ 80041a0:	0152      	lsls	r2, r2, #5
+ 80041a2:	4293      	cmp	r3, r2
+ 80041a4:	d00f      	beq.n	80041c6 <HAL_TIM_ConfigClockSource+0xb2>
+ 80041a6:	2280      	movs	r2, #128	@ 0x80
+ 80041a8:	0192      	lsls	r2, r2, #6
+ 80041aa:	4293      	cmp	r3, r2
+ 80041ac:	d00d      	beq.n	80041ca <HAL_TIM_ConfigClockSource+0xb6>
+ 80041ae:	2b70      	cmp	r3, #112	@ 0x70
+ 80041b0:	d1d1      	bne.n	8004156 <HAL_TIM_ConfigClockSource+0x42>
+      TIM_ETR_SetConfig(htim->Instance,
+ 80041b2:	68cb      	ldr	r3, [r1, #12]
+ 80041b4:	684a      	ldr	r2, [r1, #4]
+ 80041b6:	0020      	movs	r0, r4
+ 80041b8:	6889      	ldr	r1, [r1, #8]
+ 80041ba:	f7ff ff9f 	bl	80040fc <TIM_ETR_SetConfig>
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 80041be:	2377      	movs	r3, #119	@ 0x77
+      tmpsmcr = htim->Instance->SMCR;
+ 80041c0:	68a2      	ldr	r2, [r4, #8]
+      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
+ 80041c2:	4313      	orrs	r3, r2
+      htim->Instance->SMCR = tmpsmcr;
+ 80041c4:	60a3      	str	r3, [r4, #8]
+  HAL_StatusTypeDef status = HAL_OK;
+ 80041c6:	2000      	movs	r0, #0
+ 80041c8:	e7c5      	b.n	8004156 <HAL_TIM_ConfigClockSource+0x42>
+      TIM_ETR_SetConfig(htim->Instance,
+ 80041ca:	68cb      	ldr	r3, [r1, #12]
+ 80041cc:	684a      	ldr	r2, [r1, #4]
+ 80041ce:	0020      	movs	r0, r4
+ 80041d0:	6889      	ldr	r1, [r1, #8]
+ 80041d2:	f7ff ff93 	bl	80040fc <TIM_ETR_SetConfig>
+      htim->Instance->SMCR |= TIM_SMCR_ECE;
+ 80041d6:	2380      	movs	r3, #128	@ 0x80
+ 80041d8:	68a2      	ldr	r2, [r4, #8]
+ 80041da:	01db      	lsls	r3, r3, #7
+ 80041dc:	e7f1      	b.n	80041c2 <HAL_TIM_ConfigClockSource+0xae>
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+ 80041de:	2710      	movs	r7, #16
+                               sClockSourceConfig->ClockPolarity,
+ 80041e0:	684b      	ldr	r3, [r1, #4]
+                               sClockSourceConfig->ClockFilter);
+ 80041e2:	68ca      	ldr	r2, [r1, #12]
+  tmpccer = TIMx->CCER;
+ 80041e4:	6a21      	ldr	r1, [r4, #32]
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+ 80041e6:	6a20      	ldr	r0, [r4, #32]
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+ 80041e8:	0312      	lsls	r2, r2, #12
+  TIMx->CCER &= ~TIM_CCER_CC2E;
+ 80041ea:	43b8      	bics	r0, r7
+ 80041ec:	6220      	str	r0, [r4, #32]
+  tmpccmr1 = TIMx->CCMR1;
+ 80041ee:	69a0      	ldr	r0, [r4, #24]
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ 80041f0:	4f13      	ldr	r7, [pc, #76]	@ (8004240 <HAL_TIM_ConfigClockSource+0x12c>)
+  tmpccer |= (TIM_ICPolarity << 4U);
+ 80041f2:	011b      	lsls	r3, r3, #4
+  tmpccmr1 &= ~TIM_CCMR1_IC2F;
+ 80041f4:	4038      	ands	r0, r7
+  tmpccmr1 |= (TIM_ICFilter << 12U);
+ 80041f6:	4302      	orrs	r2, r0
+  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+ 80041f8:	20a0      	movs	r0, #160	@ 0xa0
+ 80041fa:	4381      	bics	r1, r0
+  tmpccer |= (TIM_ICPolarity << 4U);
+ 80041fc:	430b      	orrs	r3, r1
+  TIMx->CCMR1 = tmpccmr1 ;
+ 80041fe:	61a2      	str	r2, [r4, #24]
+  TIMx->CCER = tmpccer;
+ 8004200:	6223      	str	r3, [r4, #32]
+  tmpsmcr = TIMx->SMCR;
+ 8004202:	68a2      	ldr	r2, [r4, #8]
+  tmpsmcr &= ~TIM_SMCR_TS;
+ 8004204:	4b0d      	ldr	r3, [pc, #52]	@ (800423c <HAL_TIM_ConfigClockSource+0x128>)
+ 8004206:	401a      	ands	r2, r3
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ 8004208:	2367      	movs	r3, #103	@ 0x67
+ 800420a:	e7da      	b.n	80041c2 <HAL_TIM_ConfigClockSource+0xae>
+                               sClockSourceConfig->ClockPolarity,
+ 800420c:	684a      	ldr	r2, [r1, #4]
+                               sClockSourceConfig->ClockFilter);
+ 800420e:	68cb      	ldr	r3, [r1, #12]
+  tmpccer = TIMx->CCER;
+ 8004210:	6a21      	ldr	r1, [r4, #32]
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+ 8004212:	6a27      	ldr	r7, [r4, #32]
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+ 8004214:	011b      	lsls	r3, r3, #4
+  TIMx->CCER &= ~TIM_CCER_CC1E;
+ 8004216:	4387      	bics	r7, r0
+ 8004218:	6227      	str	r7, [r4, #32]
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ 800421a:	27f0      	movs	r7, #240	@ 0xf0
+  tmpccmr1 = TIMx->CCMR1;
+ 800421c:	69a0      	ldr	r0, [r4, #24]
+  tmpccmr1 &= ~TIM_CCMR1_IC1F;
+ 800421e:	43b8      	bics	r0, r7
+  tmpccmr1 |= (TIM_ICFilter << 4U);
+ 8004220:	4303      	orrs	r3, r0
+  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+ 8004222:	200a      	movs	r0, #10
+ 8004224:	4381      	bics	r1, r0
+  tmpccer |= TIM_ICPolarity;
+ 8004226:	430a      	orrs	r2, r1
+  TIMx->CCMR1 = tmpccmr1;
+ 8004228:	61a3      	str	r3, [r4, #24]
+  TIMx->CCER = tmpccer;
+ 800422a:	6222      	str	r2, [r4, #32]
+  tmpsmcr &= ~TIM_SMCR_TS;
+ 800422c:	4b03      	ldr	r3, [pc, #12]	@ (800423c <HAL_TIM_ConfigClockSource+0x128>)
+  tmpsmcr = TIMx->SMCR;
+ 800422e:	68a2      	ldr	r2, [r4, #8]
+  tmpsmcr &= ~TIM_SMCR_TS;
+ 8004230:	401a      	ands	r2, r3
+  tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
+ 8004232:	2347      	movs	r3, #71	@ 0x47
+ 8004234:	e7c5      	b.n	80041c2 <HAL_TIM_ConfigClockSource+0xae>
+ 8004236:	46c0      	nop			@ (mov r8, r8)
+ 8004238:	ffce0088 	.word	0xffce0088
+ 800423c:	ffcfff8f 	.word	0xffcfff8f
+ 8004240:	ffff0fff 	.word	0xffff0fff
+
+08004244 <TIM_CCxChannelCmd>:
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+ 8004244:	231f      	movs	r3, #31
+{
+ 8004246:	b510      	push	{r4, lr}
+  tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
+ 8004248:	2401      	movs	r4, #1
+ 800424a:	4019      	ands	r1, r3
+ 800424c:	408c      	lsls	r4, r1
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ 800424e:	408a      	lsls	r2, r1
+  TIMx->CCER &= ~tmp;
+ 8004250:	6a03      	ldr	r3, [r0, #32]
+ 8004252:	43a3      	bics	r3, r4
+ 8004254:	6203      	str	r3, [r0, #32]
+  TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
+ 8004256:	6a03      	ldr	r3, [r0, #32]
+ 8004258:	431a      	orrs	r2, r3
+ 800425a:	6202      	str	r2, [r0, #32]
+}
+ 800425c:	bd10      	pop	{r4, pc}
+	...
+
+08004260 <HAL_TIM_OC_Start>:
+{
+ 8004260:	0002      	movs	r2, r0
+ 8004262:	b510      	push	{r4, lr}
+ 8004264:	2908      	cmp	r1, #8
+ 8004266:	d01c      	beq.n	80042a2 <HAL_TIM_OC_Start+0x42>
+ 8004268:	d806      	bhi.n	8004278 <HAL_TIM_OC_Start+0x18>
+ 800426a:	2900      	cmp	r1, #0
+ 800426c:	d00b      	beq.n	8004286 <HAL_TIM_OC_Start+0x26>
+ 800426e:	2904      	cmp	r1, #4
+ 8004270:	d014      	beq.n	800429c <HAL_TIM_OC_Start+0x3c>
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ 8004272:	0013      	movs	r3, r2
+ 8004274:	3343      	adds	r3, #67	@ 0x43
+ 8004276:	e008      	b.n	800428a <HAL_TIM_OC_Start+0x2a>
+ 8004278:	290c      	cmp	r1, #12
+ 800427a:	d015      	beq.n	80042a8 <HAL_TIM_OC_Start+0x48>
+ 800427c:	2910      	cmp	r1, #16
+ 800427e:	d1f8      	bne.n	8004272 <HAL_TIM_OC_Start+0x12>
+ 8004280:	0003      	movs	r3, r0
+ 8004282:	3342      	adds	r3, #66	@ 0x42
+ 8004284:	e001      	b.n	800428a <HAL_TIM_OC_Start+0x2a>
+ 8004286:	0003      	movs	r3, r0
+ 8004288:	333e      	adds	r3, #62	@ 0x3e
+ 800428a:	781b      	ldrb	r3, [r3, #0]
+ 800428c:	3b01      	subs	r3, #1
+ 800428e:	1e58      	subs	r0, r3, #1
+ 8004290:	4183      	sbcs	r3, r0
+ 8004292:	b2db      	uxtb	r3, r3
+    return HAL_ERROR;
+ 8004294:	2001      	movs	r0, #1
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ 8004296:	2b00      	cmp	r3, #0
+ 8004298:	d009      	beq.n	80042ae <HAL_TIM_OC_Start+0x4e>
+}
+ 800429a:	bd10      	pop	{r4, pc}
+  if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
+ 800429c:	0003      	movs	r3, r0
+ 800429e:	333f      	adds	r3, #63	@ 0x3f
+ 80042a0:	e7f3      	b.n	800428a <HAL_TIM_OC_Start+0x2a>
+ 80042a2:	0003      	movs	r3, r0
+ 80042a4:	3340      	adds	r3, #64	@ 0x40
+ 80042a6:	e7f0      	b.n	800428a <HAL_TIM_OC_Start+0x2a>
+ 80042a8:	0003      	movs	r3, r0
+ 80042aa:	3341      	adds	r3, #65	@ 0x41
+ 80042ac:	e7ed      	b.n	800428a <HAL_TIM_OC_Start+0x2a>
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 80042ae:	2302      	movs	r3, #2
+ 80042b0:	2908      	cmp	r1, #8
+ 80042b2:	d030      	beq.n	8004316 <HAL_TIM_OC_Start+0xb6>
+ 80042b4:	d806      	bhi.n	80042c4 <HAL_TIM_OC_Start+0x64>
+ 80042b6:	2900      	cmp	r1, #0
+ 80042b8:	d00b      	beq.n	80042d2 <HAL_TIM_OC_Start+0x72>
+ 80042ba:	2904      	cmp	r1, #4
+ 80042bc:	d028      	beq.n	8004310 <HAL_TIM_OC_Start+0xb0>
+ 80042be:	0010      	movs	r0, r2
+ 80042c0:	3043      	adds	r0, #67	@ 0x43
+ 80042c2:	e008      	b.n	80042d6 <HAL_TIM_OC_Start+0x76>
+ 80042c4:	290c      	cmp	r1, #12
+ 80042c6:	d029      	beq.n	800431c <HAL_TIM_OC_Start+0xbc>
+ 80042c8:	2910      	cmp	r1, #16
+ 80042ca:	d1f8      	bne.n	80042be <HAL_TIM_OC_Start+0x5e>
+ 80042cc:	0010      	movs	r0, r2
+ 80042ce:	3042      	adds	r0, #66	@ 0x42
+ 80042d0:	e001      	b.n	80042d6 <HAL_TIM_OC_Start+0x76>
+ 80042d2:	0010      	movs	r0, r2
+ 80042d4:	303e      	adds	r0, #62	@ 0x3e
+ 80042d6:	7003      	strb	r3, [r0, #0]
+  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
+ 80042d8:	6814      	ldr	r4, [r2, #0]
+ 80042da:	2201      	movs	r2, #1
+ 80042dc:	0020      	movs	r0, r4
+ 80042de:	f7ff ffb1 	bl	8004244 <TIM_CCxChannelCmd>
+  if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
+ 80042e2:	4a18      	ldr	r2, [pc, #96]	@ (8004344 <HAL_TIM_OC_Start+0xe4>)
+ 80042e4:	4294      	cmp	r4, r2
+ 80042e6:	d005      	beq.n	80042f4 <HAL_TIM_OC_Start+0x94>
+ 80042e8:	4b17      	ldr	r3, [pc, #92]	@ (8004348 <HAL_TIM_OC_Start+0xe8>)
+ 80042ea:	429c      	cmp	r4, r3
+ 80042ec:	d002      	beq.n	80042f4 <HAL_TIM_OC_Start+0x94>
+ 80042ee:	4b17      	ldr	r3, [pc, #92]	@ (800434c <HAL_TIM_OC_Start+0xec>)
+ 80042f0:	429c      	cmp	r4, r3
+ 80042f2:	d116      	bne.n	8004322 <HAL_TIM_OC_Start+0xc2>
+    __HAL_TIM_MOE_ENABLE(htim);
+ 80042f4:	2380      	movs	r3, #128	@ 0x80
+ 80042f6:	6c61      	ldr	r1, [r4, #68]	@ 0x44
+ 80042f8:	021b      	lsls	r3, r3, #8
+ 80042fa:	430b      	orrs	r3, r1
+ 80042fc:	6463      	str	r3, [r4, #68]	@ 0x44
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 80042fe:	4294      	cmp	r4, r2
+ 8004300:	d116      	bne.n	8004330 <HAL_TIM_OC_Start+0xd0>
+    tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
+ 8004302:	68a3      	ldr	r3, [r4, #8]
+ 8004304:	4a12      	ldr	r2, [pc, #72]	@ (8004350 <HAL_TIM_OC_Start+0xf0>)
+ 8004306:	4013      	ands	r3, r2
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 8004308:	2b06      	cmp	r3, #6
+ 800430a:	d116      	bne.n	800433a <HAL_TIM_OC_Start+0xda>
+  return HAL_OK;
+ 800430c:	2000      	movs	r0, #0
+ 800430e:	e7c4      	b.n	800429a <HAL_TIM_OC_Start+0x3a>
+  TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
+ 8004310:	0010      	movs	r0, r2
+ 8004312:	303f      	adds	r0, #63	@ 0x3f
+ 8004314:	e7df      	b.n	80042d6 <HAL_TIM_OC_Start+0x76>
+ 8004316:	0010      	movs	r0, r2
+ 8004318:	3040      	adds	r0, #64	@ 0x40
+ 800431a:	e7dc      	b.n	80042d6 <HAL_TIM_OC_Start+0x76>
+ 800431c:	0010      	movs	r0, r2
+ 800431e:	3041      	adds	r0, #65	@ 0x41
+ 8004320:	e7d9      	b.n	80042d6 <HAL_TIM_OC_Start+0x76>
+  if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
+ 8004322:	2380      	movs	r3, #128	@ 0x80
+ 8004324:	05db      	lsls	r3, r3, #23
+ 8004326:	429c      	cmp	r4, r3
+ 8004328:	d0eb      	beq.n	8004302 <HAL_TIM_OC_Start+0xa2>
+ 800432a:	4b0a      	ldr	r3, [pc, #40]	@ (8004354 <HAL_TIM_OC_Start+0xf4>)
+ 800432c:	429c      	cmp	r4, r3
+ 800432e:	d0e8      	beq.n	8004302 <HAL_TIM_OC_Start+0xa2>
+      __HAL_TIM_ENABLE(htim);
+ 8004330:	2301      	movs	r3, #1
+ 8004332:	6822      	ldr	r2, [r4, #0]
+ 8004334:	4313      	orrs	r3, r2
+ 8004336:	6023      	str	r3, [r4, #0]
+ 8004338:	e7e8      	b.n	800430c <HAL_TIM_OC_Start+0xac>
+    if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
+ 800433a:	2280      	movs	r2, #128	@ 0x80
+ 800433c:	0252      	lsls	r2, r2, #9
+ 800433e:	4293      	cmp	r3, r2
+ 8004340:	d1f6      	bne.n	8004330 <HAL_TIM_OC_Start+0xd0>
+ 8004342:	e7e3      	b.n	800430c <HAL_TIM_OC_Start+0xac>
+ 8004344:	40012c00 	.word	0x40012c00
+ 8004348:	40014400 	.word	0x40014400
+ 800434c:	40014800 	.word	0x40014800
+ 8004350:	00010007 	.word	0x00010007
+ 8004354:	40000400 	.word	0x40000400
+
+08004358 <HAL_TIM_PWM_Start>:
+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
+ 8004358:	b510      	push	{r4, lr}
+ 800435a:	f7ff ff81 	bl	8004260 <HAL_TIM_OC_Start>
+ 800435e:	bd10      	pop	{r4, pc}
+
+08004360 <HAL_TIMEx_MasterConfigSynchronization>:
   *         mode.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
                                                         const TIM_MasterConfigTypeDef *sMasterConfig)
 {
- 80068b8:	b580      	push	{r7, lr}
- 80068ba:	b084      	sub	sp, #16
- 80068bc:	af00      	add	r7, sp, #0
- 80068be:	6078      	str	r0, [r7, #4]
- 80068c0:	6039      	str	r1, [r7, #0]
+ 8004360:	b5f0      	push	{r4, r5, r6, r7, lr}
   assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
   assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
   assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
 
   /* Check input state */
   __HAL_LOCK(htim);
- 80068c2:	687b      	ldr	r3, [r7, #4]
- 80068c4:	223c      	movs	r2, #60	@ 0x3c
- 80068c6:	5c9b      	ldrb	r3, [r3, r2]
- 80068c8:	2b01      	cmp	r3, #1
- 80068ca:	d101      	bne.n	80068d0 <HAL_TIMEx_MasterConfigSynchronization+0x18>
- 80068cc:	2302      	movs	r3, #2
- 80068ce:	e050      	b.n	8006972 <HAL_TIMEx_MasterConfigSynchronization+0xba>
- 80068d0:	687b      	ldr	r3, [r7, #4]
- 80068d2:	223c      	movs	r2, #60	@ 0x3c
- 80068d4:	2101      	movs	r1, #1
- 80068d6:	5499      	strb	r1, [r3, r2]
+ 8004362:	0004      	movs	r4, r0
+ 8004364:	2202      	movs	r2, #2
+ 8004366:	343c      	adds	r4, #60	@ 0x3c
+ 8004368:	7825      	ldrb	r5, [r4, #0]
+{
+ 800436a:	0003      	movs	r3, r0
+  __HAL_LOCK(htim);
+ 800436c:	0010      	movs	r0, r2
+ 800436e:	2d01      	cmp	r5, #1
+ 8004370:	d023      	beq.n	80043ba <HAL_TIMEx_MasterConfigSynchronization+0x5a>
 
   /* Change the handler state */
   htim->State = HAL_TIM_STATE_BUSY;
- 80068d8:	687b      	ldr	r3, [r7, #4]
- 80068da:	223d      	movs	r2, #61	@ 0x3d
- 80068dc:	2102      	movs	r1, #2
- 80068de:	5499      	strb	r1, [r3, r2]
+ 8004372:	001d      	movs	r5, r3
+ 8004374:	353d      	adds	r5, #61	@ 0x3d
+ 8004376:	702a      	strb	r2, [r5, #0]
 
   /* Get the TIMx CR2 register value */
   tmpcr2 = htim->Instance->CR2;
- 80068e0:	687b      	ldr	r3, [r7, #4]
- 80068e2:	681b      	ldr	r3, [r3, #0]
- 80068e4:	685b      	ldr	r3, [r3, #4]
- 80068e6:	60fb      	str	r3, [r7, #12]
+ 8004378:	681a      	ldr	r2, [r3, #0]
 
   /* Get the TIMx SMCR register value */
   tmpsmcr = htim->Instance->SMCR;
- 80068e8:	687b      	ldr	r3, [r7, #4]
- 80068ea:	681b      	ldr	r3, [r3, #0]
- 80068ec:	689b      	ldr	r3, [r3, #8]
- 80068ee:	60bb      	str	r3, [r7, #8]
 
   /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */
   if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
- 80068f0:	687b      	ldr	r3, [r7, #4]
- 80068f2:	681b      	ldr	r3, [r3, #0]
- 80068f4:	4a21      	ldr	r2, [pc, #132]	@ (800697c <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
- 80068f6:	4293      	cmp	r3, r2
- 80068f8:	d108      	bne.n	800690c <HAL_TIMEx_MasterConfigSynchronization+0x54>
+ 800437a:	4e10      	ldr	r6, [pc, #64]	@ (80043bc <HAL_TIMEx_MasterConfigSynchronization+0x5c>)
+  tmpcr2 = htim->Instance->CR2;
+ 800437c:	6853      	ldr	r3, [r2, #4]
+  tmpsmcr = htim->Instance->SMCR;
+ 800437e:	6890      	ldr	r0, [r2, #8]
+  if (IS_TIM_TRGO2_INSTANCE(htim->Instance))
+ 8004380:	42b2      	cmp	r2, r6
+ 8004382:	d103      	bne.n	800438c <HAL_TIMEx_MasterConfigSynchronization+0x2c>
   {
     /* Check the parameters */
     assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2));
 
     /* Clear the MMS2 bits */
     tmpcr2 &= ~TIM_CR2_MMS2;
- 80068fa:	68fb      	ldr	r3, [r7, #12]
- 80068fc:	4a20      	ldr	r2, [pc, #128]	@ (8006980 <HAL_TIMEx_MasterConfigSynchronization+0xc8>)
- 80068fe:	4013      	ands	r3, r2
- 8006900:	60fb      	str	r3, [r7, #12]
+ 8004384:	4f0e      	ldr	r7, [pc, #56]	@ (80043c0 <HAL_TIMEx_MasterConfigSynchronization+0x60>)
+ 8004386:	403b      	ands	r3, r7
     /* Select the TRGO2 source*/
     tmpcr2 |= sMasterConfig->MasterOutputTrigger2;
- 8006902:	683b      	ldr	r3, [r7, #0]
- 8006904:	685b      	ldr	r3, [r3, #4]
- 8006906:	68fa      	ldr	r2, [r7, #12]
- 8006908:	4313      	orrs	r3, r2
- 800690a:	60fb      	str	r3, [r7, #12]
+ 8004388:	684f      	ldr	r7, [r1, #4]
+ 800438a:	433b      	orrs	r3, r7
   }
 
   /* Reset the MMS Bits */
   tmpcr2 &= ~TIM_CR2_MMS;
- 800690c:	68fb      	ldr	r3, [r7, #12]
- 800690e:	2270      	movs	r2, #112	@ 0x70
- 8006910:	4393      	bics	r3, r2
- 8006912:	60fb      	str	r3, [r7, #12]
+ 800438c:	2770      	movs	r7, #112	@ 0x70
+ 800438e:	43bb      	bics	r3, r7
   /* Select the TRGO source */
   tmpcr2 |=  sMasterConfig->MasterOutputTrigger;
- 8006914:	683b      	ldr	r3, [r7, #0]
- 8006916:	681b      	ldr	r3, [r3, #0]
- 8006918:	68fa      	ldr	r2, [r7, #12]
- 800691a:	4313      	orrs	r3, r2
- 800691c:	60fb      	str	r3, [r7, #12]
+ 8004390:	680f      	ldr	r7, [r1, #0]
+ 8004392:	433b      	orrs	r3, r7
 
   /* Update TIMx CR2 */
   htim->Instance->CR2 = tmpcr2;
- 800691e:	687b      	ldr	r3, [r7, #4]
- 8006920:	681b      	ldr	r3, [r3, #0]
- 8006922:	68fa      	ldr	r2, [r7, #12]
- 8006924:	605a      	str	r2, [r3, #4]
+ 8004394:	6053      	str	r3, [r2, #4]
 
   if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
- 8006926:	687b      	ldr	r3, [r7, #4]
- 8006928:	681b      	ldr	r3, [r3, #0]
- 800692a:	4a14      	ldr	r2, [pc, #80]	@ (800697c <HAL_TIMEx_MasterConfigSynchronization+0xc4>)
- 800692c:	4293      	cmp	r3, r2
- 800692e:	d00a      	beq.n	8006946 <HAL_TIMEx_MasterConfigSynchronization+0x8e>
- 8006930:	687b      	ldr	r3, [r7, #4]
- 8006932:	681a      	ldr	r2, [r3, #0]
- 8006934:	2380      	movs	r3, #128	@ 0x80
- 8006936:	05db      	lsls	r3, r3, #23
- 8006938:	429a      	cmp	r2, r3
- 800693a:	d004      	beq.n	8006946 <HAL_TIMEx_MasterConfigSynchronization+0x8e>
- 800693c:	687b      	ldr	r3, [r7, #4]
- 800693e:	681b      	ldr	r3, [r3, #0]
- 8006940:	4a10      	ldr	r2, [pc, #64]	@ (8006984 <HAL_TIMEx_MasterConfigSynchronization+0xcc>)
- 8006942:	4293      	cmp	r3, r2
- 8006944:	d10c      	bne.n	8006960 <HAL_TIMEx_MasterConfigSynchronization+0xa8>
+ 8004396:	42b2      	cmp	r2, r6
+ 8004398:	d006      	beq.n	80043a8 <HAL_TIMEx_MasterConfigSynchronization+0x48>
+ 800439a:	2380      	movs	r3, #128	@ 0x80
+ 800439c:	05db      	lsls	r3, r3, #23
+ 800439e:	429a      	cmp	r2, r3
+ 80043a0:	d002      	beq.n	80043a8 <HAL_TIMEx_MasterConfigSynchronization+0x48>
+ 80043a2:	4b08      	ldr	r3, [pc, #32]	@ (80043c4 <HAL_TIMEx_MasterConfigSynchronization+0x64>)
+ 80043a4:	429a      	cmp	r2, r3
+ 80043a6:	d104      	bne.n	80043b2 <HAL_TIMEx_MasterConfigSynchronization+0x52>
   {
     /* Reset the MSM Bit */
     tmpsmcr &= ~TIM_SMCR_MSM;
- 8006946:	68bb      	ldr	r3, [r7, #8]
- 8006948:	2280      	movs	r2, #128	@ 0x80
- 800694a:	4393      	bics	r3, r2
- 800694c:	60bb      	str	r3, [r7, #8]
+ 80043a8:	2380      	movs	r3, #128	@ 0x80
+ 80043aa:	4398      	bics	r0, r3
     /* Set master mode */
     tmpsmcr |= sMasterConfig->MasterSlaveMode;
- 800694e:	683b      	ldr	r3, [r7, #0]
- 8006950:	689b      	ldr	r3, [r3, #8]
- 8006952:	68ba      	ldr	r2, [r7, #8]
- 8006954:	4313      	orrs	r3, r2
- 8006956:	60bb      	str	r3, [r7, #8]
+ 80043ac:	688b      	ldr	r3, [r1, #8]
+ 80043ae:	4318      	orrs	r0, r3
 
     /* Update TIMx SMCR */
     htim->Instance->SMCR = tmpsmcr;
- 8006958:	687b      	ldr	r3, [r7, #4]
- 800695a:	681b      	ldr	r3, [r3, #0]
- 800695c:	68ba      	ldr	r2, [r7, #8]
- 800695e:	609a      	str	r2, [r3, #8]
+ 80043b0:	6090      	str	r0, [r2, #8]
   }
 
   /* Change the htim state */
   htim->State = HAL_TIM_STATE_READY;
- 8006960:	687b      	ldr	r3, [r7, #4]
- 8006962:	223d      	movs	r2, #61	@ 0x3d
- 8006964:	2101      	movs	r1, #1
- 8006966:	5499      	strb	r1, [r3, r2]
+ 80043b2:	2301      	movs	r3, #1
 
   __HAL_UNLOCK(htim);
- 8006968:	687b      	ldr	r3, [r7, #4]
- 800696a:	223c      	movs	r2, #60	@ 0x3c
- 800696c:	2100      	movs	r1, #0
- 800696e:	5499      	strb	r1, [r3, r2]
+ 80043b4:	2000      	movs	r0, #0
+  htim->State = HAL_TIM_STATE_READY;
+ 80043b6:	702b      	strb	r3, [r5, #0]
+  __HAL_UNLOCK(htim);
+ 80043b8:	7020      	strb	r0, [r4, #0]
 
   return HAL_OK;
- 8006970:	2300      	movs	r3, #0
 }
- 8006972:	0018      	movs	r0, r3
- 8006974:	46bd      	mov	sp, r7
- 8006976:	b004      	add	sp, #16
- 8006978:	bd80      	pop	{r7, pc}
- 800697a:	46c0      	nop			@ (mov r8, r8)
- 800697c:	40012c00 	.word	0x40012c00
- 8006980:	ff0fffff 	.word	0xff0fffff
- 8006984:	40000400 	.word	0x40000400
+ 80043ba:	bdf0      	pop	{r4, r5, r6, r7, pc}
+ 80043bc:	40012c00 	.word	0x40012c00
+ 80043c0:	ff0fffff 	.word	0xff0fffff
+ 80043c4:	40000400 	.word	0x40000400
 
-08006988 <HAL_TIMEx_ConfigBreakDeadTime>:
+080043c8 <HAL_TIMEx_ConfigBreakDeadTime>:
   *         interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
                                                 const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig)
 {
- 8006988:	b580      	push	{r7, lr}
- 800698a:	b084      	sub	sp, #16
- 800698c:	af00      	add	r7, sp, #0
- 800698e:	6078      	str	r0, [r7, #4]
- 8006990:	6039      	str	r1, [r7, #0]
-  /* Keep this variable initialized to 0 as it is used to configure BDTR register */
-  uint32_t tmpbdtr = 0U;
- 8006992:	2300      	movs	r3, #0
- 8006994:	60fb      	str	r3, [r7, #12]
+ 80043c8:	b510      	push	{r4, lr}
   assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
   assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
   assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
 
   /* Check input state */
   __HAL_LOCK(htim);
- 8006996:	687b      	ldr	r3, [r7, #4]
- 8006998:	223c      	movs	r2, #60	@ 0x3c
- 800699a:	5c9b      	ldrb	r3, [r3, r2]
- 800699c:	2b01      	cmp	r3, #1
- 800699e:	d101      	bne.n	80069a4 <HAL_TIMEx_ConfigBreakDeadTime+0x1c>
- 80069a0:	2302      	movs	r3, #2
- 80069a2:	e06f      	b.n	8006a84 <HAL_TIMEx_ConfigBreakDeadTime+0xfc>
- 80069a4:	687b      	ldr	r3, [r7, #4]
- 80069a6:	223c      	movs	r2, #60	@ 0x3c
- 80069a8:	2101      	movs	r1, #1
- 80069aa:	5499      	strb	r1, [r3, r2]
-
+ 80043ca:	0004      	movs	r4, r0
+ 80043cc:	343c      	adds	r4, #60	@ 0x3c
+ 80043ce:	7823      	ldrb	r3, [r4, #0]
+{
+ 80043d0:	0002      	movs	r2, r0
+  __HAL_LOCK(htim);
+ 80043d2:	2002      	movs	r0, #2
+ 80043d4:	2b01      	cmp	r3, #1
+ 80043d6:	d039      	beq.n	800444c <HAL_TIMEx_ConfigBreakDeadTime+0x84>
   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
      the OSSI State, the dead time value and the Automatic Output Enable Bit */
 
   /* Set the BDTR bits */
   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime);
- 80069ac:	68fb      	ldr	r3, [r7, #12]
- 80069ae:	22ff      	movs	r2, #255	@ 0xff
- 80069b0:	4393      	bics	r3, r2
- 80069b2:	001a      	movs	r2, r3
- 80069b4:	683b      	ldr	r3, [r7, #0]
- 80069b6:	68db      	ldr	r3, [r3, #12]
- 80069b8:	4313      	orrs	r3, r2
- 80069ba:	60fb      	str	r3, [r7, #12]
   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel);
- 80069bc:	68fb      	ldr	r3, [r7, #12]
- 80069be:	4a33      	ldr	r2, [pc, #204]	@ (8006a8c <HAL_TIMEx_ConfigBreakDeadTime+0x104>)
- 80069c0:	401a      	ands	r2, r3
- 80069c2:	683b      	ldr	r3, [r7, #0]
- 80069c4:	689b      	ldr	r3, [r3, #8]
- 80069c6:	4313      	orrs	r3, r2
- 80069c8:	60fb      	str	r3, [r7, #12]
+ 80043d8:	481d      	ldr	r0, [pc, #116]	@ (8004450 <HAL_TIMEx_ConfigBreakDeadTime+0x88>)
+ 80043da:	68cb      	ldr	r3, [r1, #12]
+ 80043dc:	4003      	ands	r3, r0
+ 80043de:	6888      	ldr	r0, [r1, #8]
+ 80043e0:	4303      	orrs	r3, r0
   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode);
- 80069ca:	68fb      	ldr	r3, [r7, #12]
- 80069cc:	4a30      	ldr	r2, [pc, #192]	@ (8006a90 <HAL_TIMEx_ConfigBreakDeadTime+0x108>)
- 80069ce:	401a      	ands	r2, r3
- 80069d0:	683b      	ldr	r3, [r7, #0]
- 80069d2:	685b      	ldr	r3, [r3, #4]
- 80069d4:	4313      	orrs	r3, r2
- 80069d6:	60fb      	str	r3, [r7, #12]
+ 80043e2:	481c      	ldr	r0, [pc, #112]	@ (8004454 <HAL_TIMEx_ConfigBreakDeadTime+0x8c>)
+ 80043e4:	4003      	ands	r3, r0
+ 80043e6:	6848      	ldr	r0, [r1, #4]
+ 80043e8:	4303      	orrs	r3, r0
   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode);
- 80069d8:	68fb      	ldr	r3, [r7, #12]
- 80069da:	4a2e      	ldr	r2, [pc, #184]	@ (8006a94 <HAL_TIMEx_ConfigBreakDeadTime+0x10c>)
- 80069dc:	401a      	ands	r2, r3
- 80069de:	683b      	ldr	r3, [r7, #0]
- 80069e0:	681b      	ldr	r3, [r3, #0]
- 80069e2:	4313      	orrs	r3, r2
- 80069e4:	60fb      	str	r3, [r7, #12]
+ 80043ea:	481b      	ldr	r0, [pc, #108]	@ (8004458 <HAL_TIMEx_ConfigBreakDeadTime+0x90>)
+ 80043ec:	4003      	ands	r3, r0
+ 80043ee:	6808      	ldr	r0, [r1, #0]
+ 80043f0:	4303      	orrs	r3, r0
   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState);
- 80069e6:	68fb      	ldr	r3, [r7, #12]
- 80069e8:	4a2b      	ldr	r2, [pc, #172]	@ (8006a98 <HAL_TIMEx_ConfigBreakDeadTime+0x110>)
- 80069ea:	401a      	ands	r2, r3
- 80069ec:	683b      	ldr	r3, [r7, #0]
- 80069ee:	691b      	ldr	r3, [r3, #16]
- 80069f0:	4313      	orrs	r3, r2
- 80069f2:	60fb      	str	r3, [r7, #12]
+ 80043f2:	481a      	ldr	r0, [pc, #104]	@ (800445c <HAL_TIMEx_ConfigBreakDeadTime+0x94>)
+ 80043f4:	4003      	ands	r3, r0
+ 80043f6:	6908      	ldr	r0, [r1, #16]
+ 80043f8:	4303      	orrs	r3, r0
   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
- 80069f4:	68fb      	ldr	r3, [r7, #12]
- 80069f6:	4a29      	ldr	r2, [pc, #164]	@ (8006a9c <HAL_TIMEx_ConfigBreakDeadTime+0x114>)
- 80069f8:	401a      	ands	r2, r3
- 80069fa:	683b      	ldr	r3, [r7, #0]
- 80069fc:	695b      	ldr	r3, [r3, #20]
- 80069fe:	4313      	orrs	r3, r2
- 8006a00:	60fb      	str	r3, [r7, #12]
+ 80043fa:	4819      	ldr	r0, [pc, #100]	@ (8004460 <HAL_TIMEx_ConfigBreakDeadTime+0x98>)
+ 80043fc:	4003      	ands	r3, r0
+ 80043fe:	6948      	ldr	r0, [r1, #20]
+ 8004400:	4303      	orrs	r3, r0
   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
- 8006a02:	68fb      	ldr	r3, [r7, #12]
- 8006a04:	4a26      	ldr	r2, [pc, #152]	@ (8006aa0 <HAL_TIMEx_ConfigBreakDeadTime+0x118>)
- 8006a06:	401a      	ands	r2, r3
- 8006a08:	683b      	ldr	r3, [r7, #0]
- 8006a0a:	6b1b      	ldr	r3, [r3, #48]	@ 0x30
- 8006a0c:	4313      	orrs	r3, r2
- 8006a0e:	60fb      	str	r3, [r7, #12]
+ 8004402:	4818      	ldr	r0, [pc, #96]	@ (8004464 <HAL_TIMEx_ConfigBreakDeadTime+0x9c>)
+ 8004404:	4003      	ands	r3, r0
+ 8004406:	6b08      	ldr	r0, [r1, #48]	@ 0x30
+ 8004408:	4303      	orrs	r3, r0
   MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
- 8006a10:	68fb      	ldr	r3, [r7, #12]
- 8006a12:	4a24      	ldr	r2, [pc, #144]	@ (8006aa4 <HAL_TIMEx_ConfigBreakDeadTime+0x11c>)
- 8006a14:	401a      	ands	r2, r3
- 8006a16:	683b      	ldr	r3, [r7, #0]
- 8006a18:	699b      	ldr	r3, [r3, #24]
- 8006a1a:	041b      	lsls	r3, r3, #16
- 8006a1c:	4313      	orrs	r3, r2
- 8006a1e:	60fb      	str	r3, [r7, #12]
+ 800440a:	4817      	ldr	r0, [pc, #92]	@ (8004468 <HAL_TIMEx_ConfigBreakDeadTime+0xa0>)
+ 800440c:	4003      	ands	r3, r0
+ 800440e:	6988      	ldr	r0, [r1, #24]
+ 8004410:	0400      	lsls	r0, r0, #16
+ 8004412:	4303      	orrs	r3, r0
   MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
- 8006a20:	68fb      	ldr	r3, [r7, #12]
- 8006a22:	4a21      	ldr	r2, [pc, #132]	@ (8006aa8 <HAL_TIMEx_ConfigBreakDeadTime+0x120>)
- 8006a24:	401a      	ands	r2, r3
- 8006a26:	683b      	ldr	r3, [r7, #0]
- 8006a28:	69db      	ldr	r3, [r3, #28]
- 8006a2a:	4313      	orrs	r3, r2
- 8006a2c:	60fb      	str	r3, [r7, #12]
+ 8004414:	4815      	ldr	r0, [pc, #84]	@ (800446c <HAL_TIMEx_ConfigBreakDeadTime+0xa4>)
+ 8004416:	4003      	ands	r3, r0
+ 8004418:	69c8      	ldr	r0, [r1, #28]
+ 800441a:	4303      	orrs	r3, r0
 
   if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
- 8006a2e:	687b      	ldr	r3, [r7, #4]
- 8006a30:	681b      	ldr	r3, [r3, #0]
- 8006a32:	4a1e      	ldr	r2, [pc, #120]	@ (8006aac <HAL_TIMEx_ConfigBreakDeadTime+0x124>)
- 8006a34:	4293      	cmp	r3, r2
- 8006a36:	d11c      	bne.n	8006a72 <HAL_TIMEx_ConfigBreakDeadTime+0xea>
+ 800441c:	6810      	ldr	r0, [r2, #0]
+ 800441e:	4a14      	ldr	r2, [pc, #80]	@ (8004470 <HAL_TIMEx_ConfigBreakDeadTime+0xa8>)
+ 8004420:	4290      	cmp	r0, r2
+ 8004422:	d110      	bne.n	8004446 <HAL_TIMEx_ConfigBreakDeadTime+0x7e>
     assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
     assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
     assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
 
     /* Set the BREAK2 input related BDTR bits */
     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
- 8006a38:	68fb      	ldr	r3, [r7, #12]
- 8006a3a:	4a1d      	ldr	r2, [pc, #116]	@ (8006ab0 <HAL_TIMEx_ConfigBreakDeadTime+0x128>)
- 8006a3c:	401a      	ands	r2, r3
- 8006a3e:	683b      	ldr	r3, [r7, #0]
- 8006a40:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8006a42:	051b      	lsls	r3, r3, #20
- 8006a44:	4313      	orrs	r3, r2
- 8006a46:	60fb      	str	r3, [r7, #12]
+ 8004424:	4a13      	ldr	r2, [pc, #76]	@ (8004474 <HAL_TIMEx_ConfigBreakDeadTime+0xac>)
+ 8004426:	4013      	ands	r3, r2
+ 8004428:	6a8a      	ldr	r2, [r1, #40]	@ 0x28
+ 800442a:	0512      	lsls	r2, r2, #20
+ 800442c:	431a      	orrs	r2, r3
     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
- 8006a48:	68fb      	ldr	r3, [r7, #12]
- 8006a4a:	4a1a      	ldr	r2, [pc, #104]	@ (8006ab4 <HAL_TIMEx_ConfigBreakDeadTime+0x12c>)
- 8006a4c:	401a      	ands	r2, r3
- 8006a4e:	683b      	ldr	r3, [r7, #0]
- 8006a50:	6a1b      	ldr	r3, [r3, #32]
- 8006a52:	4313      	orrs	r3, r2
- 8006a54:	60fb      	str	r3, [r7, #12]
+ 800442e:	4b12      	ldr	r3, [pc, #72]	@ (8004478 <HAL_TIMEx_ConfigBreakDeadTime+0xb0>)
+ 8004430:	401a      	ands	r2, r3
+ 8004432:	6a0b      	ldr	r3, [r1, #32]
+ 8004434:	431a      	orrs	r2, r3
     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
- 8006a56:	68fb      	ldr	r3, [r7, #12]
- 8006a58:	4a17      	ldr	r2, [pc, #92]	@ (8006ab8 <HAL_TIMEx_ConfigBreakDeadTime+0x130>)
- 8006a5a:	401a      	ands	r2, r3
- 8006a5c:	683b      	ldr	r3, [r7, #0]
- 8006a5e:	6a5b      	ldr	r3, [r3, #36]	@ 0x24
- 8006a60:	4313      	orrs	r3, r2
- 8006a62:	60fb      	str	r3, [r7, #12]
+ 8004436:	4b11      	ldr	r3, [pc, #68]	@ (800447c <HAL_TIMEx_ConfigBreakDeadTime+0xb4>)
+ 8004438:	401a      	ands	r2, r3
+ 800443a:	6a4b      	ldr	r3, [r1, #36]	@ 0x24
+ 800443c:	431a      	orrs	r2, r3
     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
- 8006a64:	68fb      	ldr	r3, [r7, #12]
- 8006a66:	4a15      	ldr	r2, [pc, #84]	@ (8006abc <HAL_TIMEx_ConfigBreakDeadTime+0x134>)
- 8006a68:	401a      	ands	r2, r3
- 8006a6a:	683b      	ldr	r3, [r7, #0]
- 8006a6c:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
- 8006a6e:	4313      	orrs	r3, r2
- 8006a70:	60fb      	str	r3, [r7, #12]
+ 800443e:	4b10      	ldr	r3, [pc, #64]	@ (8004480 <HAL_TIMEx_ConfigBreakDeadTime+0xb8>)
+ 8004440:	401a      	ands	r2, r3
+ 8004442:	6acb      	ldr	r3, [r1, #44]	@ 0x2c
+ 8004444:	4313      	orrs	r3, r2
   }
 
   /* Set TIMx_BDTR */
   htim->Instance->BDTR = tmpbdtr;
- 8006a72:	687b      	ldr	r3, [r7, #4]
- 8006a74:	681b      	ldr	r3, [r3, #0]
- 8006a76:	68fa      	ldr	r2, [r7, #12]
- 8006a78:	645a      	str	r2, [r3, #68]	@ 0x44
+ 8004446:	6443      	str	r3, [r0, #68]	@ 0x44
 
   __HAL_UNLOCK(htim);
- 8006a7a:	687b      	ldr	r3, [r7, #4]
- 8006a7c:	223c      	movs	r2, #60	@ 0x3c
- 8006a7e:	2100      	movs	r1, #0
- 8006a80:	5499      	strb	r1, [r3, r2]
+ 8004448:	2000      	movs	r0, #0
+ 800444a:	7020      	strb	r0, [r4, #0]
 
   return HAL_OK;
- 8006a82:	2300      	movs	r3, #0
 }
- 8006a84:	0018      	movs	r0, r3
- 8006a86:	46bd      	mov	sp, r7
- 8006a88:	b004      	add	sp, #16
- 8006a8a:	bd80      	pop	{r7, pc}
- 8006a8c:	fffffcff 	.word	0xfffffcff
- 8006a90:	fffffbff 	.word	0xfffffbff
- 8006a94:	fffff7ff 	.word	0xfffff7ff
- 8006a98:	ffffefff 	.word	0xffffefff
- 8006a9c:	ffffdfff 	.word	0xffffdfff
- 8006aa0:	ffffbfff 	.word	0xffffbfff
- 8006aa4:	fff0ffff 	.word	0xfff0ffff
- 8006aa8:	efffffff 	.word	0xefffffff
- 8006aac:	40012c00 	.word	0x40012c00
- 8006ab0:	ff0fffff 	.word	0xff0fffff
- 8006ab4:	feffffff 	.word	0xfeffffff
- 8006ab8:	fdffffff 	.word	0xfdffffff
- 8006abc:	dfffffff 	.word	0xdfffffff
+ 800444c:	bd10      	pop	{r4, pc}
+ 800444e:	46c0      	nop			@ (mov r8, r8)
+ 8004450:	fffffcff 	.word	0xfffffcff
+ 8004454:	fffffbff 	.word	0xfffffbff
+ 8004458:	fffff7ff 	.word	0xfffff7ff
+ 800445c:	ffffefff 	.word	0xffffefff
+ 8004460:	ffffdfff 	.word	0xffffdfff
+ 8004464:	ffffbfff 	.word	0xffffbfff
+ 8004468:	fff0ffff 	.word	0xfff0ffff
+ 800446c:	efffffff 	.word	0xefffffff
+ 8004470:	40012c00 	.word	0x40012c00
+ 8004474:	ff0fffff 	.word	0xff0fffff
+ 8004478:	feffffff 	.word	0xfeffffff
+ 800447c:	fdffffff 	.word	0xfdffffff
+ 8004480:	dfffffff 	.word	0xdfffffff
 
-08006ac0 <HAL_TIMEx_CommutCallback>:
+08004484 <HAL_TIMEx_CommutCallback>:
+/**
   * @brief  Commutation callback in non-blocking mode
   * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
-{
- 8006ac0:	b580      	push	{r7, lr}
- 8006ac2:	b082      	sub	sp, #8
- 8006ac4:	af00      	add	r7, sp, #0
- 8006ac6:	6078      	str	r0, [r7, #4]
-  UNUSED(htim);
+ 8004484:	4770      	bx	lr
 
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIMEx_CommutCallback could be implemented in the user file
-   */
-}
- 8006ac8:	46c0      	nop			@ (mov r8, r8)
- 8006aca:	46bd      	mov	sp, r7
- 8006acc:	b002      	add	sp, #8
- 8006ace:	bd80      	pop	{r7, pc}
-
-08006ad0 <HAL_TIMEx_BreakCallback>:
+08004486 <HAL_TIMEx_BreakCallback>:
+/**
   * @brief  Break detection callback in non-blocking mode
   * @param  htim TIM handle
   * @retval None
   */
 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
-{
- 8006ad0:	b580      	push	{r7, lr}
- 8006ad2:	b082      	sub	sp, #8
- 8006ad4:	af00      	add	r7, sp, #0
- 8006ad6:	6078      	str	r0, [r7, #4]
-  UNUSED(htim);
+ 8004486:	4770      	bx	lr
 
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_TIMEx_BreakCallback could be implemented in the user file
-   */
-}
- 8006ad8:	46c0      	nop			@ (mov r8, r8)
- 8006ada:	46bd      	mov	sp, r7
- 8006adc:	b002      	add	sp, #8
- 8006ade:	bd80      	pop	{r7, pc}
-
-08006ae0 <HAL_TIMEx_Break2Callback>:
+08004488 <HAL_TIMEx_Break2Callback>:
+/**
   * @brief  Break2 detection callback in non blocking mode
   * @param  htim: TIM handle
   * @retval None
   */
 __weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim)
-{
- 8006ae0:	b580      	push	{r7, lr}
- 8006ae2:	b082      	sub	sp, #8
- 8006ae4:	af00      	add	r7, sp, #0
- 8006ae6:	6078      	str	r0, [r7, #4]
-  UNUSED(htim);
-
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIMEx_Break2Callback could be implemented in the user file
-   */
-}
- 8006ae8:	46c0      	nop			@ (mov r8, r8)
- 8006aea:	46bd      	mov	sp, r7
- 8006aec:	b002      	add	sp, #8
- 8006aee:	bd80      	pop	{r7, pc}
-
-08006af0 <HAL_UART_Init>:
-  *        parameters in the UART_InitTypeDef and initialize the associated handle.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
- 8006af0:	b580      	push	{r7, lr}
- 8006af2:	b082      	sub	sp, #8
- 8006af4:	af00      	add	r7, sp, #0
- 8006af6:	6078      	str	r0, [r7, #4]
-  /* Check the UART handle allocation */
-  if (huart == NULL)
- 8006af8:	687b      	ldr	r3, [r7, #4]
- 8006afa:	2b00      	cmp	r3, #0
- 8006afc:	d101      	bne.n	8006b02 <HAL_UART_Init+0x12>
-  {
-    return HAL_ERROR;
- 8006afe:	2301      	movs	r3, #1
- 8006b00:	e046      	b.n	8006b90 <HAL_UART_Init+0xa0>
-  {
-    /* Check the parameters */
-    assert_param(IS_UART_INSTANCE(huart->Instance));
-  }
-
-  if (huart->gState == HAL_UART_STATE_RESET)
- 8006b02:	687b      	ldr	r3, [r7, #4]
- 8006b04:	2288      	movs	r2, #136	@ 0x88
- 8006b06:	589b      	ldr	r3, [r3, r2]
- 8006b08:	2b00      	cmp	r3, #0
- 8006b0a:	d107      	bne.n	8006b1c <HAL_UART_Init+0x2c>
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
- 8006b0c:	687b      	ldr	r3, [r7, #4]
- 8006b0e:	2284      	movs	r2, #132	@ 0x84
- 8006b10:	2100      	movs	r1, #0
- 8006b12:	5499      	strb	r1, [r3, r2]
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
-#else
-    /* Init the low level hardware : GPIO, CLOCK */
-    HAL_UART_MspInit(huart);
- 8006b14:	687b      	ldr	r3, [r7, #4]
- 8006b16:	0018      	movs	r0, r3
- 8006b18:	f7fd f8da 	bl	8003cd0 <HAL_UART_MspInit>
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
- 8006b1c:	687b      	ldr	r3, [r7, #4]
- 8006b1e:	2288      	movs	r2, #136	@ 0x88
- 8006b20:	2124      	movs	r1, #36	@ 0x24
- 8006b22:	5099      	str	r1, [r3, r2]
-
-  __HAL_UART_DISABLE(huart);
- 8006b24:	687b      	ldr	r3, [r7, #4]
- 8006b26:	681b      	ldr	r3, [r3, #0]
- 8006b28:	681a      	ldr	r2, [r3, #0]
- 8006b2a:	687b      	ldr	r3, [r7, #4]
- 8006b2c:	681b      	ldr	r3, [r3, #0]
- 8006b2e:	2101      	movs	r1, #1
- 8006b30:	438a      	bics	r2, r1
- 8006b32:	601a      	str	r2, [r3, #0]
-
-  /* Perform advanced settings configuration */
-  /* For some items, configuration requires to be done prior TE and RE bits are set */
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- 8006b34:	687b      	ldr	r3, [r7, #4]
- 8006b36:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8006b38:	2b00      	cmp	r3, #0
- 8006b3a:	d003      	beq.n	8006b44 <HAL_UART_Init+0x54>
-  {
-    UART_AdvFeatureConfig(huart);
- 8006b3c:	687b      	ldr	r3, [r7, #4]
- 8006b3e:	0018      	movs	r0, r3
- 8006b40:	f000 fa66 	bl	8007010 <UART_AdvFeatureConfig>
-  }
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
- 8006b44:	687b      	ldr	r3, [r7, #4]
- 8006b46:	0018      	movs	r0, r3
- 8006b48:	f000 f8e4 	bl	8006d14 <UART_SetConfig>
- 8006b4c:	0003      	movs	r3, r0
- 8006b4e:	2b01      	cmp	r3, #1
- 8006b50:	d101      	bne.n	8006b56 <HAL_UART_Init+0x66>
-  {
-    return HAL_ERROR;
- 8006b52:	2301      	movs	r3, #1
- 8006b54:	e01c      	b.n	8006b90 <HAL_UART_Init+0xa0>
-  }
-
-  /* In asynchronous mode, the following bits must be kept cleared:
-  - LINEN and CLKEN bits in the USART_CR2 register,
-  - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
-  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
- 8006b56:	687b      	ldr	r3, [r7, #4]
- 8006b58:	681b      	ldr	r3, [r3, #0]
- 8006b5a:	685a      	ldr	r2, [r3, #4]
- 8006b5c:	687b      	ldr	r3, [r7, #4]
- 8006b5e:	681b      	ldr	r3, [r3, #0]
- 8006b60:	490d      	ldr	r1, [pc, #52]	@ (8006b98 <HAL_UART_Init+0xa8>)
- 8006b62:	400a      	ands	r2, r1
- 8006b64:	605a      	str	r2, [r3, #4]
-  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
- 8006b66:	687b      	ldr	r3, [r7, #4]
- 8006b68:	681b      	ldr	r3, [r3, #0]
- 8006b6a:	689a      	ldr	r2, [r3, #8]
- 8006b6c:	687b      	ldr	r3, [r7, #4]
- 8006b6e:	681b      	ldr	r3, [r3, #0]
- 8006b70:	212a      	movs	r1, #42	@ 0x2a
- 8006b72:	438a      	bics	r2, r1
- 8006b74:	609a      	str	r2, [r3, #8]
-
-  __HAL_UART_ENABLE(huart);
- 8006b76:	687b      	ldr	r3, [r7, #4]
- 8006b78:	681b      	ldr	r3, [r3, #0]
- 8006b7a:	681a      	ldr	r2, [r3, #0]
- 8006b7c:	687b      	ldr	r3, [r7, #4]
- 8006b7e:	681b      	ldr	r3, [r3, #0]
- 8006b80:	2101      	movs	r1, #1
- 8006b82:	430a      	orrs	r2, r1
- 8006b84:	601a      	str	r2, [r3, #0]
-
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
-  return (UART_CheckIdleState(huart));
- 8006b86:	687b      	ldr	r3, [r7, #4]
- 8006b88:	0018      	movs	r0, r3
- 8006b8a:	f000 faf5 	bl	8007178 <UART_CheckIdleState>
- 8006b8e:	0003      	movs	r3, r0
-}
- 8006b90:	0018      	movs	r0, r3
- 8006b92:	46bd      	mov	sp, r7
- 8006b94:	b002      	add	sp, #8
- 8006b96:	bd80      	pop	{r7, pc}
- 8006b98:	ffffb7ff 	.word	0xffffb7ff
-
-08006b9c <HAL_UART_Transmit>:
-  * @param Size    Amount of data elements (u8 or u16) to be sent.
-  * @param Timeout Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
- 8006b9c:	b580      	push	{r7, lr}
- 8006b9e:	b08a      	sub	sp, #40	@ 0x28
- 8006ba0:	af02      	add	r7, sp, #8
- 8006ba2:	60f8      	str	r0, [r7, #12]
- 8006ba4:	60b9      	str	r1, [r7, #8]
- 8006ba6:	603b      	str	r3, [r7, #0]
- 8006ba8:	1dbb      	adds	r3, r7, #6
- 8006baa:	801a      	strh	r2, [r3, #0]
-  const uint8_t  *pdata8bits;
-  const uint16_t *pdata16bits;
-  uint32_t tickstart;
-
-  /* Check that a Tx process is not already ongoing */
-  if (huart->gState == HAL_UART_STATE_READY)
- 8006bac:	68fb      	ldr	r3, [r7, #12]
- 8006bae:	2288      	movs	r2, #136	@ 0x88
- 8006bb0:	589b      	ldr	r3, [r3, r2]
- 8006bb2:	2b20      	cmp	r3, #32
- 8006bb4:	d000      	beq.n	8006bb8 <HAL_UART_Transmit+0x1c>
- 8006bb6:	e090      	b.n	8006cda <HAL_UART_Transmit+0x13e>
-  {
-    if ((pData == NULL) || (Size == 0U))
- 8006bb8:	68bb      	ldr	r3, [r7, #8]
- 8006bba:	2b00      	cmp	r3, #0
- 8006bbc:	d003      	beq.n	8006bc6 <HAL_UART_Transmit+0x2a>
- 8006bbe:	1dbb      	adds	r3, r7, #6
- 8006bc0:	881b      	ldrh	r3, [r3, #0]
- 8006bc2:	2b00      	cmp	r3, #0
- 8006bc4:	d101      	bne.n	8006bca <HAL_UART_Transmit+0x2e>
-    {
-      return  HAL_ERROR;
- 8006bc6:	2301      	movs	r3, #1
- 8006bc8:	e088      	b.n	8006cdc <HAL_UART_Transmit+0x140>
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a u16 frontier, as data to be filled into TDR will be
-       handled through a u16 cast. */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 8006bca:	68fb      	ldr	r3, [r7, #12]
- 8006bcc:	689a      	ldr	r2, [r3, #8]
- 8006bce:	2380      	movs	r3, #128	@ 0x80
- 8006bd0:	015b      	lsls	r3, r3, #5
- 8006bd2:	429a      	cmp	r2, r3
- 8006bd4:	d109      	bne.n	8006bea <HAL_UART_Transmit+0x4e>
- 8006bd6:	68fb      	ldr	r3, [r7, #12]
- 8006bd8:	691b      	ldr	r3, [r3, #16]
- 8006bda:	2b00      	cmp	r3, #0
- 8006bdc:	d105      	bne.n	8006bea <HAL_UART_Transmit+0x4e>
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
- 8006bde:	68bb      	ldr	r3, [r7, #8]
- 8006be0:	2201      	movs	r2, #1
- 8006be2:	4013      	ands	r3, r2
- 8006be4:	d001      	beq.n	8006bea <HAL_UART_Transmit+0x4e>
-      {
-        return  HAL_ERROR;
- 8006be6:	2301      	movs	r3, #1
- 8006be8:	e078      	b.n	8006cdc <HAL_UART_Transmit+0x140>
-      }
-    }
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8006bea:	68fb      	ldr	r3, [r7, #12]
- 8006bec:	2290      	movs	r2, #144	@ 0x90
- 8006bee:	2100      	movs	r1, #0
- 8006bf0:	5099      	str	r1, [r3, r2]
-    huart->gState = HAL_UART_STATE_BUSY_TX;
- 8006bf2:	68fb      	ldr	r3, [r7, #12]
- 8006bf4:	2288      	movs	r2, #136	@ 0x88
- 8006bf6:	2121      	movs	r1, #33	@ 0x21
- 8006bf8:	5099      	str	r1, [r3, r2]
-
-    /* Init tickstart for timeout management */
-    tickstart = HAL_GetTick();
- 8006bfa:	f7fd fa6d 	bl	80040d8 <HAL_GetTick>
- 8006bfe:	0003      	movs	r3, r0
- 8006c00:	617b      	str	r3, [r7, #20]
-
-    huart->TxXferSize  = Size;
- 8006c02:	68fb      	ldr	r3, [r7, #12]
- 8006c04:	1dba      	adds	r2, r7, #6
- 8006c06:	2154      	movs	r1, #84	@ 0x54
- 8006c08:	8812      	ldrh	r2, [r2, #0]
- 8006c0a:	525a      	strh	r2, [r3, r1]
-    huart->TxXferCount = Size;
- 8006c0c:	68fb      	ldr	r3, [r7, #12]
- 8006c0e:	1dba      	adds	r2, r7, #6
- 8006c10:	2156      	movs	r1, #86	@ 0x56
- 8006c12:	8812      	ldrh	r2, [r2, #0]
- 8006c14:	525a      	strh	r2, [r3, r1]
-
-    /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 8006c16:	68fb      	ldr	r3, [r7, #12]
- 8006c18:	689a      	ldr	r2, [r3, #8]
- 8006c1a:	2380      	movs	r3, #128	@ 0x80
- 8006c1c:	015b      	lsls	r3, r3, #5
- 8006c1e:	429a      	cmp	r2, r3
- 8006c20:	d108      	bne.n	8006c34 <HAL_UART_Transmit+0x98>
- 8006c22:	68fb      	ldr	r3, [r7, #12]
- 8006c24:	691b      	ldr	r3, [r3, #16]
- 8006c26:	2b00      	cmp	r3, #0
- 8006c28:	d104      	bne.n	8006c34 <HAL_UART_Transmit+0x98>
-    {
-      pdata8bits  = NULL;
- 8006c2a:	2300      	movs	r3, #0
- 8006c2c:	61fb      	str	r3, [r7, #28]
-      pdata16bits = (const uint16_t *) pData;
- 8006c2e:	68bb      	ldr	r3, [r7, #8]
- 8006c30:	61bb      	str	r3, [r7, #24]
- 8006c32:	e003      	b.n	8006c3c <HAL_UART_Transmit+0xa0>
-    }
-    else
-    {
-      pdata8bits  = pData;
- 8006c34:	68bb      	ldr	r3, [r7, #8]
- 8006c36:	61fb      	str	r3, [r7, #28]
-      pdata16bits = NULL;
- 8006c38:	2300      	movs	r3, #0
- 8006c3a:	61bb      	str	r3, [r7, #24]
-    }
-
-    while (huart->TxXferCount > 0U)
- 8006c3c:	e030      	b.n	8006ca0 <HAL_UART_Transmit+0x104>
-    {
-      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
- 8006c3e:	697a      	ldr	r2, [r7, #20]
- 8006c40:	68f8      	ldr	r0, [r7, #12]
- 8006c42:	683b      	ldr	r3, [r7, #0]
- 8006c44:	9300      	str	r3, [sp, #0]
- 8006c46:	0013      	movs	r3, r2
- 8006c48:	2200      	movs	r2, #0
- 8006c4a:	2180      	movs	r1, #128	@ 0x80
- 8006c4c:	f000 fb3e 	bl	80072cc <UART_WaitOnFlagUntilTimeout>
- 8006c50:	1e03      	subs	r3, r0, #0
- 8006c52:	d005      	beq.n	8006c60 <HAL_UART_Transmit+0xc4>
-      {
-
-        huart->gState = HAL_UART_STATE_READY;
- 8006c54:	68fb      	ldr	r3, [r7, #12]
- 8006c56:	2288      	movs	r2, #136	@ 0x88
- 8006c58:	2120      	movs	r1, #32
- 8006c5a:	5099      	str	r1, [r3, r2]
-
-        return HAL_TIMEOUT;
- 8006c5c:	2303      	movs	r3, #3
- 8006c5e:	e03d      	b.n	8006cdc <HAL_UART_Transmit+0x140>
-      }
-      if (pdata8bits == NULL)
- 8006c60:	69fb      	ldr	r3, [r7, #28]
- 8006c62:	2b00      	cmp	r3, #0
- 8006c64:	d10b      	bne.n	8006c7e <HAL_UART_Transmit+0xe2>
-      {
-        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
- 8006c66:	69bb      	ldr	r3, [r7, #24]
- 8006c68:	881b      	ldrh	r3, [r3, #0]
- 8006c6a:	001a      	movs	r2, r3
- 8006c6c:	68fb      	ldr	r3, [r7, #12]
- 8006c6e:	681b      	ldr	r3, [r3, #0]
- 8006c70:	05d2      	lsls	r2, r2, #23
- 8006c72:	0dd2      	lsrs	r2, r2, #23
- 8006c74:	629a      	str	r2, [r3, #40]	@ 0x28
-        pdata16bits++;
- 8006c76:	69bb      	ldr	r3, [r7, #24]
- 8006c78:	3302      	adds	r3, #2
- 8006c7a:	61bb      	str	r3, [r7, #24]
- 8006c7c:	e007      	b.n	8006c8e <HAL_UART_Transmit+0xf2>
-      }
-      else
-      {
-        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
- 8006c7e:	69fb      	ldr	r3, [r7, #28]
- 8006c80:	781a      	ldrb	r2, [r3, #0]
- 8006c82:	68fb      	ldr	r3, [r7, #12]
- 8006c84:	681b      	ldr	r3, [r3, #0]
- 8006c86:	629a      	str	r2, [r3, #40]	@ 0x28
-        pdata8bits++;
- 8006c88:	69fb      	ldr	r3, [r7, #28]
- 8006c8a:	3301      	adds	r3, #1
- 8006c8c:	61fb      	str	r3, [r7, #28]
-      }
-      huart->TxXferCount--;
- 8006c8e:	68fb      	ldr	r3, [r7, #12]
- 8006c90:	2256      	movs	r2, #86	@ 0x56
- 8006c92:	5a9b      	ldrh	r3, [r3, r2]
- 8006c94:	b29b      	uxth	r3, r3
- 8006c96:	3b01      	subs	r3, #1
- 8006c98:	b299      	uxth	r1, r3
- 8006c9a:	68fb      	ldr	r3, [r7, #12]
- 8006c9c:	2256      	movs	r2, #86	@ 0x56
- 8006c9e:	5299      	strh	r1, [r3, r2]
-    while (huart->TxXferCount > 0U)
- 8006ca0:	68fb      	ldr	r3, [r7, #12]
- 8006ca2:	2256      	movs	r2, #86	@ 0x56
- 8006ca4:	5a9b      	ldrh	r3, [r3, r2]
- 8006ca6:	b29b      	uxth	r3, r3
- 8006ca8:	2b00      	cmp	r3, #0
- 8006caa:	d1c8      	bne.n	8006c3e <HAL_UART_Transmit+0xa2>
-    }
-
-    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
- 8006cac:	697a      	ldr	r2, [r7, #20]
- 8006cae:	68f8      	ldr	r0, [r7, #12]
- 8006cb0:	683b      	ldr	r3, [r7, #0]
- 8006cb2:	9300      	str	r3, [sp, #0]
- 8006cb4:	0013      	movs	r3, r2
- 8006cb6:	2200      	movs	r2, #0
- 8006cb8:	2140      	movs	r1, #64	@ 0x40
- 8006cba:	f000 fb07 	bl	80072cc <UART_WaitOnFlagUntilTimeout>
- 8006cbe:	1e03      	subs	r3, r0, #0
- 8006cc0:	d005      	beq.n	8006cce <HAL_UART_Transmit+0x132>
-    {
-      huart->gState = HAL_UART_STATE_READY;
- 8006cc2:	68fb      	ldr	r3, [r7, #12]
- 8006cc4:	2288      	movs	r2, #136	@ 0x88
- 8006cc6:	2120      	movs	r1, #32
- 8006cc8:	5099      	str	r1, [r3, r2]
-
-      return HAL_TIMEOUT;
- 8006cca:	2303      	movs	r3, #3
- 8006ccc:	e006      	b.n	8006cdc <HAL_UART_Transmit+0x140>
-    }
-
-    /* At end of Tx process, restore huart->gState to Ready */
-    huart->gState = HAL_UART_STATE_READY;
- 8006cce:	68fb      	ldr	r3, [r7, #12]
- 8006cd0:	2288      	movs	r2, #136	@ 0x88
- 8006cd2:	2120      	movs	r1, #32
- 8006cd4:	5099      	str	r1, [r3, r2]
-
-    return HAL_OK;
- 8006cd6:	2300      	movs	r3, #0
- 8006cd8:	e000      	b.n	8006cdc <HAL_UART_Transmit+0x140>
-  }
-  else
-  {
-    return HAL_BUSY;
- 8006cda:	2302      	movs	r3, #2
-  }
-}
- 8006cdc:	0018      	movs	r0, r3
- 8006cde:	46bd      	mov	sp, r7
- 8006ce0:	b008      	add	sp, #32
- 8006ce2:	bd80      	pop	{r7, pc}
-
-08006ce4 <HAL_UART_RxCpltCallback>:
-  * @brief  Rx Transfer completed callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
-{
- 8006ce4:	b580      	push	{r7, lr}
- 8006ce6:	b082      	sub	sp, #8
- 8006ce8:	af00      	add	r7, sp, #0
- 8006cea:	6078      	str	r0, [r7, #4]
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_RxCpltCallback can be implemented in the user file.
-   */
-}
- 8006cec:	46c0      	nop			@ (mov r8, r8)
- 8006cee:	46bd      	mov	sp, r7
- 8006cf0:	b002      	add	sp, #8
- 8006cf2:	bd80      	pop	{r7, pc}
-
-08006cf4 <HAL_UART_RxHalfCpltCallback>:
-  * @brief  Rx Half Transfer completed callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
- 8006cf4:	b580      	push	{r7, lr}
- 8006cf6:	b082      	sub	sp, #8
- 8006cf8:	af00      	add	r7, sp, #0
- 8006cfa:	6078      	str	r0, [r7, #4]
-  UNUSED(huart);
-
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_UART_RxHalfCpltCallback can be implemented in the user file.
-   */
-}
- 8006cfc:	46c0      	nop			@ (mov r8, r8)
- 8006cfe:	46bd      	mov	sp, r7
- 8006d00:	b002      	add	sp, #8
- 8006d02:	bd80      	pop	{r7, pc}
-
-08006d04 <HAL_UART_ErrorCallback>:
-  * @brief  UART error callback.
-  * @param  huart UART handle.
-  * @retval None
-  */
-__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
- 8006d04:	b580      	push	{r7, lr}
- 8006d06:	b082      	sub	sp, #8
- 8006d08:	af00      	add	r7, sp, #0
- 8006d0a:	6078      	str	r0, [r7, #4]
-  UNUSED(huart);
-
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_UART_ErrorCallback can be implemented in the user file.
-   */
-}
- 8006d0c:	46c0      	nop			@ (mov r8, r8)
- 8006d0e:	46bd      	mov	sp, r7
- 8006d10:	b002      	add	sp, #8
- 8006d12:	bd80      	pop	{r7, pc}
-
-08006d14 <UART_SetConfig>:
-  * @brief Configure the UART peripheral.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart)
-{
- 8006d14:	b580      	push	{r7, lr}
- 8006d16:	b088      	sub	sp, #32
- 8006d18:	af00      	add	r7, sp, #0
- 8006d1a:	6078      	str	r0, [r7, #4]
-  uint32_t tmpreg;
-  uint16_t brrtemp;
-  UART_ClockSourceTypeDef clocksource;
-  uint32_t usartdiv;
-  HAL_StatusTypeDef ret               = HAL_OK;
- 8006d1c:	231e      	movs	r3, #30
- 8006d1e:	18fb      	adds	r3, r7, r3
- 8006d20:	2200      	movs	r2, #0
- 8006d22:	701a      	strb	r2, [r3, #0]
-  *  the UART Word Length, Parity, Mode and oversampling:
-  *  set the M bits according to huart->Init.WordLength value
-  *  set PCE and PS bits according to huart->Init.Parity value
-  *  set TE and RE bits according to huart->Init.Mode value
-  *  set OVER8 bit according to huart->Init.OverSampling value */
-  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
- 8006d24:	687b      	ldr	r3, [r7, #4]
- 8006d26:	689a      	ldr	r2, [r3, #8]
- 8006d28:	687b      	ldr	r3, [r7, #4]
- 8006d2a:	691b      	ldr	r3, [r3, #16]
- 8006d2c:	431a      	orrs	r2, r3
- 8006d2e:	687b      	ldr	r3, [r7, #4]
- 8006d30:	695b      	ldr	r3, [r3, #20]
- 8006d32:	431a      	orrs	r2, r3
- 8006d34:	687b      	ldr	r3, [r7, #4]
- 8006d36:	69db      	ldr	r3, [r3, #28]
- 8006d38:	4313      	orrs	r3, r2
- 8006d3a:	617b      	str	r3, [r7, #20]
-  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
- 8006d3c:	687b      	ldr	r3, [r7, #4]
- 8006d3e:	681b      	ldr	r3, [r3, #0]
- 8006d40:	681b      	ldr	r3, [r3, #0]
- 8006d42:	4aab      	ldr	r2, [pc, #684]	@ (8006ff0 <UART_SetConfig+0x2dc>)
- 8006d44:	4013      	ands	r3, r2
- 8006d46:	0019      	movs	r1, r3
- 8006d48:	687b      	ldr	r3, [r7, #4]
- 8006d4a:	681b      	ldr	r3, [r3, #0]
- 8006d4c:	697a      	ldr	r2, [r7, #20]
- 8006d4e:	430a      	orrs	r2, r1
- 8006d50:	601a      	str	r2, [r3, #0]
-
-  /*-------------------------- USART CR2 Configuration -----------------------*/
-  /* Configure the UART Stop Bits: Set STOP[13:12] bits according
-  * to huart->Init.StopBits value */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
- 8006d52:	687b      	ldr	r3, [r7, #4]
- 8006d54:	681b      	ldr	r3, [r3, #0]
- 8006d56:	685b      	ldr	r3, [r3, #4]
- 8006d58:	4aa6      	ldr	r2, [pc, #664]	@ (8006ff4 <UART_SetConfig+0x2e0>)
- 8006d5a:	4013      	ands	r3, r2
- 8006d5c:	0019      	movs	r1, r3
- 8006d5e:	687b      	ldr	r3, [r7, #4]
- 8006d60:	68da      	ldr	r2, [r3, #12]
- 8006d62:	687b      	ldr	r3, [r7, #4]
- 8006d64:	681b      	ldr	r3, [r3, #0]
- 8006d66:	430a      	orrs	r2, r1
- 8006d68:	605a      	str	r2, [r3, #4]
-  /* Configure
-  * - UART HardWare Flow Control: set CTSE and RTSE bits according
-  *   to huart->Init.HwFlowCtl value
-  * - one-bit sampling method versus three samples' majority rule according
-  *   to huart->Init.OneBitSampling (not applicable to LPUART) */
-  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
- 8006d6a:	687b      	ldr	r3, [r7, #4]
- 8006d6c:	699b      	ldr	r3, [r3, #24]
- 8006d6e:	617b      	str	r3, [r7, #20]
-
-  tmpreg |= huart->Init.OneBitSampling;
- 8006d70:	687b      	ldr	r3, [r7, #4]
- 8006d72:	6a1b      	ldr	r3, [r3, #32]
- 8006d74:	697a      	ldr	r2, [r7, #20]
- 8006d76:	4313      	orrs	r3, r2
- 8006d78:	617b      	str	r3, [r7, #20]
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
- 8006d7a:	687b      	ldr	r3, [r7, #4]
- 8006d7c:	681b      	ldr	r3, [r3, #0]
- 8006d7e:	689b      	ldr	r3, [r3, #8]
- 8006d80:	4a9d      	ldr	r2, [pc, #628]	@ (8006ff8 <UART_SetConfig+0x2e4>)
- 8006d82:	4013      	ands	r3, r2
- 8006d84:	0019      	movs	r1, r3
- 8006d86:	687b      	ldr	r3, [r7, #4]
- 8006d88:	681b      	ldr	r3, [r3, #0]
- 8006d8a:	697a      	ldr	r2, [r7, #20]
- 8006d8c:	430a      	orrs	r2, r1
- 8006d8e:	609a      	str	r2, [r3, #8]
-
-  /*-------------------------- USART PRESC Configuration -----------------------*/
-  /* Configure
-  * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */
-  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
- 8006d90:	687b      	ldr	r3, [r7, #4]
- 8006d92:	681b      	ldr	r3, [r3, #0]
- 8006d94:	6adb      	ldr	r3, [r3, #44]	@ 0x2c
- 8006d96:	220f      	movs	r2, #15
- 8006d98:	4393      	bics	r3, r2
- 8006d9a:	0019      	movs	r1, r3
- 8006d9c:	687b      	ldr	r3, [r7, #4]
- 8006d9e:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
- 8006da0:	687b      	ldr	r3, [r7, #4]
- 8006da2:	681b      	ldr	r3, [r3, #0]
- 8006da4:	430a      	orrs	r2, r1
- 8006da6:	62da      	str	r2, [r3, #44]	@ 0x2c
-
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  UART_GETCLOCKSOURCE(huart, clocksource);
- 8006da8:	687b      	ldr	r3, [r7, #4]
- 8006daa:	681b      	ldr	r3, [r3, #0]
- 8006dac:	4a93      	ldr	r2, [pc, #588]	@ (8006ffc <UART_SetConfig+0x2e8>)
- 8006dae:	4293      	cmp	r3, r2
- 8006db0:	d127      	bne.n	8006e02 <UART_SetConfig+0xee>
- 8006db2:	4b93      	ldr	r3, [pc, #588]	@ (8007000 <UART_SetConfig+0x2ec>)
- 8006db4:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
- 8006db6:	2203      	movs	r2, #3
- 8006db8:	4013      	ands	r3, r2
- 8006dba:	2b03      	cmp	r3, #3
- 8006dbc:	d017      	beq.n	8006dee <UART_SetConfig+0xda>
- 8006dbe:	d81b      	bhi.n	8006df8 <UART_SetConfig+0xe4>
- 8006dc0:	2b02      	cmp	r3, #2
- 8006dc2:	d00a      	beq.n	8006dda <UART_SetConfig+0xc6>
- 8006dc4:	d818      	bhi.n	8006df8 <UART_SetConfig+0xe4>
- 8006dc6:	2b00      	cmp	r3, #0
- 8006dc8:	d002      	beq.n	8006dd0 <UART_SetConfig+0xbc>
- 8006dca:	2b01      	cmp	r3, #1
- 8006dcc:	d00a      	beq.n	8006de4 <UART_SetConfig+0xd0>
- 8006dce:	e013      	b.n	8006df8 <UART_SetConfig+0xe4>
- 8006dd0:	231f      	movs	r3, #31
- 8006dd2:	18fb      	adds	r3, r7, r3
- 8006dd4:	2200      	movs	r2, #0
- 8006dd6:	701a      	strb	r2, [r3, #0]
- 8006dd8:	e021      	b.n	8006e1e <UART_SetConfig+0x10a>
- 8006dda:	231f      	movs	r3, #31
- 8006ddc:	18fb      	adds	r3, r7, r3
- 8006dde:	2202      	movs	r2, #2
- 8006de0:	701a      	strb	r2, [r3, #0]
- 8006de2:	e01c      	b.n	8006e1e <UART_SetConfig+0x10a>
- 8006de4:	231f      	movs	r3, #31
- 8006de6:	18fb      	adds	r3, r7, r3
- 8006de8:	2204      	movs	r2, #4
- 8006dea:	701a      	strb	r2, [r3, #0]
- 8006dec:	e017      	b.n	8006e1e <UART_SetConfig+0x10a>
- 8006dee:	231f      	movs	r3, #31
- 8006df0:	18fb      	adds	r3, r7, r3
- 8006df2:	2208      	movs	r2, #8
- 8006df4:	701a      	strb	r2, [r3, #0]
- 8006df6:	e012      	b.n	8006e1e <UART_SetConfig+0x10a>
- 8006df8:	231f      	movs	r3, #31
- 8006dfa:	18fb      	adds	r3, r7, r3
- 8006dfc:	2210      	movs	r2, #16
- 8006dfe:	701a      	strb	r2, [r3, #0]
- 8006e00:	e00d      	b.n	8006e1e <UART_SetConfig+0x10a>
- 8006e02:	687b      	ldr	r3, [r7, #4]
- 8006e04:	681b      	ldr	r3, [r3, #0]
- 8006e06:	4a7f      	ldr	r2, [pc, #508]	@ (8007004 <UART_SetConfig+0x2f0>)
- 8006e08:	4293      	cmp	r3, r2
- 8006e0a:	d104      	bne.n	8006e16 <UART_SetConfig+0x102>
- 8006e0c:	231f      	movs	r3, #31
- 8006e0e:	18fb      	adds	r3, r7, r3
- 8006e10:	2200      	movs	r2, #0
- 8006e12:	701a      	strb	r2, [r3, #0]
- 8006e14:	e003      	b.n	8006e1e <UART_SetConfig+0x10a>
- 8006e16:	231f      	movs	r3, #31
- 8006e18:	18fb      	adds	r3, r7, r3
- 8006e1a:	2210      	movs	r2, #16
- 8006e1c:	701a      	strb	r2, [r3, #0]
-
-  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
- 8006e1e:	687b      	ldr	r3, [r7, #4]
- 8006e20:	69da      	ldr	r2, [r3, #28]
- 8006e22:	2380      	movs	r3, #128	@ 0x80
- 8006e24:	021b      	lsls	r3, r3, #8
- 8006e26:	429a      	cmp	r2, r3
- 8006e28:	d000      	beq.n	8006e2c <UART_SetConfig+0x118>
- 8006e2a:	e06f      	b.n	8006f0c <UART_SetConfig+0x1f8>
-  {
-    switch (clocksource)
- 8006e2c:	231f      	movs	r3, #31
- 8006e2e:	18fb      	adds	r3, r7, r3
- 8006e30:	781b      	ldrb	r3, [r3, #0]
- 8006e32:	2b08      	cmp	r3, #8
- 8006e34:	d01f      	beq.n	8006e76 <UART_SetConfig+0x162>
- 8006e36:	dc22      	bgt.n	8006e7e <UART_SetConfig+0x16a>
- 8006e38:	2b04      	cmp	r3, #4
- 8006e3a:	d017      	beq.n	8006e6c <UART_SetConfig+0x158>
- 8006e3c:	dc1f      	bgt.n	8006e7e <UART_SetConfig+0x16a>
- 8006e3e:	2b00      	cmp	r3, #0
- 8006e40:	d002      	beq.n	8006e48 <UART_SetConfig+0x134>
- 8006e42:	2b02      	cmp	r3, #2
- 8006e44:	d005      	beq.n	8006e52 <UART_SetConfig+0x13e>
- 8006e46:	e01a      	b.n	8006e7e <UART_SetConfig+0x16a>
-    {
-      case UART_CLOCKSOURCE_PCLK1:
-        pclk = HAL_RCC_GetPCLK1Freq();
- 8006e48:	f7fe fa00 	bl	800524c <HAL_RCC_GetPCLK1Freq>
- 8006e4c:	0003      	movs	r3, r0
- 8006e4e:	61bb      	str	r3, [r7, #24]
-        break;
- 8006e50:	e01c      	b.n	8006e8c <UART_SetConfig+0x178>
-      case UART_CLOCKSOURCE_HSI:
-        pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
- 8006e52:	4b6b      	ldr	r3, [pc, #428]	@ (8007000 <UART_SetConfig+0x2ec>)
- 8006e54:	681b      	ldr	r3, [r3, #0]
- 8006e56:	095b      	lsrs	r3, r3, #5
- 8006e58:	2207      	movs	r2, #7
- 8006e5a:	4013      	ands	r3, r2
- 8006e5c:	3301      	adds	r3, #1
- 8006e5e:	0019      	movs	r1, r3
- 8006e60:	4869      	ldr	r0, [pc, #420]	@ (8007008 <UART_SetConfig+0x2f4>)
- 8006e62:	f7f9 f951 	bl	8000108 <__udivsi3>
- 8006e66:	0003      	movs	r3, r0
- 8006e68:	61bb      	str	r3, [r7, #24]
-        break;
- 8006e6a:	e00f      	b.n	8006e8c <UART_SetConfig+0x178>
-      case UART_CLOCKSOURCE_SYSCLK:
-        pclk = HAL_RCC_GetSysClockFreq();
- 8006e6c:	f7fe f980 	bl	8005170 <HAL_RCC_GetSysClockFreq>
- 8006e70:	0003      	movs	r3, r0
- 8006e72:	61bb      	str	r3, [r7, #24]
-        break;
- 8006e74:	e00a      	b.n	8006e8c <UART_SetConfig+0x178>
-      case UART_CLOCKSOURCE_LSE:
-        pclk = (uint32_t) LSE_VALUE;
- 8006e76:	2380      	movs	r3, #128	@ 0x80
- 8006e78:	021b      	lsls	r3, r3, #8
- 8006e7a:	61bb      	str	r3, [r7, #24]
-        break;
- 8006e7c:	e006      	b.n	8006e8c <UART_SetConfig+0x178>
-      default:
-        pclk = 0U;
- 8006e7e:	2300      	movs	r3, #0
- 8006e80:	61bb      	str	r3, [r7, #24]
-        ret = HAL_ERROR;
- 8006e82:	231e      	movs	r3, #30
- 8006e84:	18fb      	adds	r3, r7, r3
- 8006e86:	2201      	movs	r2, #1
- 8006e88:	701a      	strb	r2, [r3, #0]
-        break;
- 8006e8a:	46c0      	nop			@ (mov r8, r8)
-    }
-
-    /* USARTDIV must be greater than or equal to 0d16 */
-    if (pclk != 0U)
- 8006e8c:	69bb      	ldr	r3, [r7, #24]
- 8006e8e:	2b00      	cmp	r3, #0
- 8006e90:	d100      	bne.n	8006e94 <UART_SetConfig+0x180>
- 8006e92:	e097      	b.n	8006fc4 <UART_SetConfig+0x2b0>
-    {
-      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- 8006e94:	687b      	ldr	r3, [r7, #4]
- 8006e96:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
- 8006e98:	4b5c      	ldr	r3, [pc, #368]	@ (800700c <UART_SetConfig+0x2f8>)
- 8006e9a:	0052      	lsls	r2, r2, #1
- 8006e9c:	5ad3      	ldrh	r3, [r2, r3]
- 8006e9e:	0019      	movs	r1, r3
- 8006ea0:	69b8      	ldr	r0, [r7, #24]
- 8006ea2:	f7f9 f931 	bl	8000108 <__udivsi3>
- 8006ea6:	0003      	movs	r3, r0
- 8006ea8:	005a      	lsls	r2, r3, #1
- 8006eaa:	687b      	ldr	r3, [r7, #4]
- 8006eac:	685b      	ldr	r3, [r3, #4]
- 8006eae:	085b      	lsrs	r3, r3, #1
- 8006eb0:	18d2      	adds	r2, r2, r3
- 8006eb2:	687b      	ldr	r3, [r7, #4]
- 8006eb4:	685b      	ldr	r3, [r3, #4]
- 8006eb6:	0019      	movs	r1, r3
- 8006eb8:	0010      	movs	r0, r2
- 8006eba:	f7f9 f925 	bl	8000108 <__udivsi3>
- 8006ebe:	0003      	movs	r3, r0
- 8006ec0:	613b      	str	r3, [r7, #16]
-      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8006ec2:	693b      	ldr	r3, [r7, #16]
- 8006ec4:	2b0f      	cmp	r3, #15
- 8006ec6:	d91c      	bls.n	8006f02 <UART_SetConfig+0x1ee>
- 8006ec8:	693a      	ldr	r2, [r7, #16]
- 8006eca:	2380      	movs	r3, #128	@ 0x80
- 8006ecc:	025b      	lsls	r3, r3, #9
- 8006ece:	429a      	cmp	r2, r3
- 8006ed0:	d217      	bcs.n	8006f02 <UART_SetConfig+0x1ee>
-      {
-        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
- 8006ed2:	693b      	ldr	r3, [r7, #16]
- 8006ed4:	b29a      	uxth	r2, r3
- 8006ed6:	200e      	movs	r0, #14
- 8006ed8:	183b      	adds	r3, r7, r0
- 8006eda:	210f      	movs	r1, #15
- 8006edc:	438a      	bics	r2, r1
- 8006ede:	801a      	strh	r2, [r3, #0]
-        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
- 8006ee0:	693b      	ldr	r3, [r7, #16]
- 8006ee2:	085b      	lsrs	r3, r3, #1
- 8006ee4:	b29b      	uxth	r3, r3
- 8006ee6:	2207      	movs	r2, #7
- 8006ee8:	4013      	ands	r3, r2
- 8006eea:	b299      	uxth	r1, r3
- 8006eec:	183b      	adds	r3, r7, r0
- 8006eee:	183a      	adds	r2, r7, r0
- 8006ef0:	8812      	ldrh	r2, [r2, #0]
- 8006ef2:	430a      	orrs	r2, r1
- 8006ef4:	801a      	strh	r2, [r3, #0]
-        huart->Instance->BRR = brrtemp;
- 8006ef6:	687b      	ldr	r3, [r7, #4]
- 8006ef8:	681b      	ldr	r3, [r3, #0]
- 8006efa:	183a      	adds	r2, r7, r0
- 8006efc:	8812      	ldrh	r2, [r2, #0]
- 8006efe:	60da      	str	r2, [r3, #12]
- 8006f00:	e060      	b.n	8006fc4 <UART_SetConfig+0x2b0>
-      }
-      else
-      {
-        ret = HAL_ERROR;
- 8006f02:	231e      	movs	r3, #30
- 8006f04:	18fb      	adds	r3, r7, r3
- 8006f06:	2201      	movs	r2, #1
- 8006f08:	701a      	strb	r2, [r3, #0]
- 8006f0a:	e05b      	b.n	8006fc4 <UART_SetConfig+0x2b0>
-      }
-    }
-  }
-  else
-  {
-    switch (clocksource)
- 8006f0c:	231f      	movs	r3, #31
- 8006f0e:	18fb      	adds	r3, r7, r3
- 8006f10:	781b      	ldrb	r3, [r3, #0]
- 8006f12:	2b08      	cmp	r3, #8
- 8006f14:	d01f      	beq.n	8006f56 <UART_SetConfig+0x242>
- 8006f16:	dc22      	bgt.n	8006f5e <UART_SetConfig+0x24a>
- 8006f18:	2b04      	cmp	r3, #4
- 8006f1a:	d017      	beq.n	8006f4c <UART_SetConfig+0x238>
- 8006f1c:	dc1f      	bgt.n	8006f5e <UART_SetConfig+0x24a>
- 8006f1e:	2b00      	cmp	r3, #0
- 8006f20:	d002      	beq.n	8006f28 <UART_SetConfig+0x214>
- 8006f22:	2b02      	cmp	r3, #2
- 8006f24:	d005      	beq.n	8006f32 <UART_SetConfig+0x21e>
- 8006f26:	e01a      	b.n	8006f5e <UART_SetConfig+0x24a>
-    {
-      case UART_CLOCKSOURCE_PCLK1:
-        pclk = HAL_RCC_GetPCLK1Freq();
- 8006f28:	f7fe f990 	bl	800524c <HAL_RCC_GetPCLK1Freq>
- 8006f2c:	0003      	movs	r3, r0
- 8006f2e:	61bb      	str	r3, [r7, #24]
-        break;
- 8006f30:	e01c      	b.n	8006f6c <UART_SetConfig+0x258>
-      case UART_CLOCKSOURCE_HSI:
-        pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
- 8006f32:	4b33      	ldr	r3, [pc, #204]	@ (8007000 <UART_SetConfig+0x2ec>)
- 8006f34:	681b      	ldr	r3, [r3, #0]
- 8006f36:	095b      	lsrs	r3, r3, #5
- 8006f38:	2207      	movs	r2, #7
- 8006f3a:	4013      	ands	r3, r2
- 8006f3c:	3301      	adds	r3, #1
- 8006f3e:	0019      	movs	r1, r3
- 8006f40:	4831      	ldr	r0, [pc, #196]	@ (8007008 <UART_SetConfig+0x2f4>)
- 8006f42:	f7f9 f8e1 	bl	8000108 <__udivsi3>
- 8006f46:	0003      	movs	r3, r0
- 8006f48:	61bb      	str	r3, [r7, #24]
-        break;
- 8006f4a:	e00f      	b.n	8006f6c <UART_SetConfig+0x258>
-      case UART_CLOCKSOURCE_SYSCLK:
-        pclk = HAL_RCC_GetSysClockFreq();
- 8006f4c:	f7fe f910 	bl	8005170 <HAL_RCC_GetSysClockFreq>
- 8006f50:	0003      	movs	r3, r0
- 8006f52:	61bb      	str	r3, [r7, #24]
-        break;
- 8006f54:	e00a      	b.n	8006f6c <UART_SetConfig+0x258>
-      case UART_CLOCKSOURCE_LSE:
-        pclk = (uint32_t) LSE_VALUE;
- 8006f56:	2380      	movs	r3, #128	@ 0x80
- 8006f58:	021b      	lsls	r3, r3, #8
- 8006f5a:	61bb      	str	r3, [r7, #24]
-        break;
- 8006f5c:	e006      	b.n	8006f6c <UART_SetConfig+0x258>
-      default:
-        pclk = 0U;
- 8006f5e:	2300      	movs	r3, #0
- 8006f60:	61bb      	str	r3, [r7, #24]
-        ret = HAL_ERROR;
- 8006f62:	231e      	movs	r3, #30
- 8006f64:	18fb      	adds	r3, r7, r3
- 8006f66:	2201      	movs	r2, #1
- 8006f68:	701a      	strb	r2, [r3, #0]
-        break;
- 8006f6a:	46c0      	nop			@ (mov r8, r8)
-    }
-
-    if (pclk != 0U)
- 8006f6c:	69bb      	ldr	r3, [r7, #24]
- 8006f6e:	2b00      	cmp	r3, #0
- 8006f70:	d028      	beq.n	8006fc4 <UART_SetConfig+0x2b0>
-    {
-      /* USARTDIV must be greater than or equal to 0d16 */
-      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
- 8006f72:	687b      	ldr	r3, [r7, #4]
- 8006f74:	6a5a      	ldr	r2, [r3, #36]	@ 0x24
- 8006f76:	4b25      	ldr	r3, [pc, #148]	@ (800700c <UART_SetConfig+0x2f8>)
- 8006f78:	0052      	lsls	r2, r2, #1
- 8006f7a:	5ad3      	ldrh	r3, [r2, r3]
- 8006f7c:	0019      	movs	r1, r3
- 8006f7e:	69b8      	ldr	r0, [r7, #24]
- 8006f80:	f7f9 f8c2 	bl	8000108 <__udivsi3>
- 8006f84:	0003      	movs	r3, r0
- 8006f86:	001a      	movs	r2, r3
- 8006f88:	687b      	ldr	r3, [r7, #4]
- 8006f8a:	685b      	ldr	r3, [r3, #4]
- 8006f8c:	085b      	lsrs	r3, r3, #1
- 8006f8e:	18d2      	adds	r2, r2, r3
- 8006f90:	687b      	ldr	r3, [r7, #4]
- 8006f92:	685b      	ldr	r3, [r3, #4]
- 8006f94:	0019      	movs	r1, r3
- 8006f96:	0010      	movs	r0, r2
- 8006f98:	f7f9 f8b6 	bl	8000108 <__udivsi3>
- 8006f9c:	0003      	movs	r3, r0
- 8006f9e:	613b      	str	r3, [r7, #16]
-      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
- 8006fa0:	693b      	ldr	r3, [r7, #16]
- 8006fa2:	2b0f      	cmp	r3, #15
- 8006fa4:	d90a      	bls.n	8006fbc <UART_SetConfig+0x2a8>
- 8006fa6:	693a      	ldr	r2, [r7, #16]
- 8006fa8:	2380      	movs	r3, #128	@ 0x80
- 8006faa:	025b      	lsls	r3, r3, #9
- 8006fac:	429a      	cmp	r2, r3
- 8006fae:	d205      	bcs.n	8006fbc <UART_SetConfig+0x2a8>
-      {
-        huart->Instance->BRR = (uint16_t)usartdiv;
- 8006fb0:	693b      	ldr	r3, [r7, #16]
- 8006fb2:	b29a      	uxth	r2, r3
- 8006fb4:	687b      	ldr	r3, [r7, #4]
- 8006fb6:	681b      	ldr	r3, [r3, #0]
- 8006fb8:	60da      	str	r2, [r3, #12]
- 8006fba:	e003      	b.n	8006fc4 <UART_SetConfig+0x2b0>
-      }
-      else
-      {
-        ret = HAL_ERROR;
- 8006fbc:	231e      	movs	r3, #30
- 8006fbe:	18fb      	adds	r3, r7, r3
- 8006fc0:	2201      	movs	r2, #1
- 8006fc2:	701a      	strb	r2, [r3, #0]
-      }
-    }
-  }
-
-  /* Initialize the number of data to process during RX/TX ISR execution */
-  huart->NbTxDataToProcess = 1;
- 8006fc4:	687b      	ldr	r3, [r7, #4]
- 8006fc6:	226a      	movs	r2, #106	@ 0x6a
- 8006fc8:	2101      	movs	r1, #1
- 8006fca:	5299      	strh	r1, [r3, r2]
-  huart->NbRxDataToProcess = 1;
- 8006fcc:	687b      	ldr	r3, [r7, #4]
- 8006fce:	2268      	movs	r2, #104	@ 0x68
- 8006fd0:	2101      	movs	r1, #1
- 8006fd2:	5299      	strh	r1, [r3, r2]
-
-  /* Clear ISR function pointers */
-  huart->RxISR = NULL;
- 8006fd4:	687b      	ldr	r3, [r7, #4]
- 8006fd6:	2200      	movs	r2, #0
- 8006fd8:	675a      	str	r2, [r3, #116]	@ 0x74
-  huart->TxISR = NULL;
- 8006fda:	687b      	ldr	r3, [r7, #4]
- 8006fdc:	2200      	movs	r2, #0
- 8006fde:	679a      	str	r2, [r3, #120]	@ 0x78
-
-  return ret;
- 8006fe0:	231e      	movs	r3, #30
- 8006fe2:	18fb      	adds	r3, r7, r3
- 8006fe4:	781b      	ldrb	r3, [r3, #0]
-}
- 8006fe6:	0018      	movs	r0, r3
- 8006fe8:	46bd      	mov	sp, r7
- 8006fea:	b008      	add	sp, #32
- 8006fec:	bd80      	pop	{r7, pc}
- 8006fee:	46c0      	nop			@ (mov r8, r8)
- 8006ff0:	cfff69f3 	.word	0xcfff69f3
- 8006ff4:	ffffcfff 	.word	0xffffcfff
- 8006ff8:	11fff4ff 	.word	0x11fff4ff
- 8006ffc:	40013800 	.word	0x40013800
- 8007000:	40021000 	.word	0x40021000
- 8007004:	40004400 	.word	0x40004400
- 8007008:	02dc6c00 	.word	0x02dc6c00
- 800700c:	08007e64 	.word	0x08007e64
-
-08007010 <UART_AdvFeatureConfig>:
-  * @brief Configure the UART peripheral advanced features.
-  * @param huart UART handle.
-  * @retval None
-  */
-void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
-{
- 8007010:	b580      	push	{r7, lr}
- 8007012:	b082      	sub	sp, #8
- 8007014:	af00      	add	r7, sp, #0
- 8007016:	6078      	str	r0, [r7, #4]
-  /* Check whether the set of advanced features to configure is properly set */
-  assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
-
-  /* if required, configure RX/TX pins swap */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
- 8007018:	687b      	ldr	r3, [r7, #4]
- 800701a:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 800701c:	2208      	movs	r2, #8
- 800701e:	4013      	ands	r3, r2
- 8007020:	d00b      	beq.n	800703a <UART_AdvFeatureConfig+0x2a>
-  {
-    assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
- 8007022:	687b      	ldr	r3, [r7, #4]
- 8007024:	681b      	ldr	r3, [r3, #0]
- 8007026:	685b      	ldr	r3, [r3, #4]
- 8007028:	4a4a      	ldr	r2, [pc, #296]	@ (8007154 <UART_AdvFeatureConfig+0x144>)
- 800702a:	4013      	ands	r3, r2
- 800702c:	0019      	movs	r1, r3
- 800702e:	687b      	ldr	r3, [r7, #4]
- 8007030:	6b9a      	ldr	r2, [r3, #56]	@ 0x38
- 8007032:	687b      	ldr	r3, [r7, #4]
- 8007034:	681b      	ldr	r3, [r3, #0]
- 8007036:	430a      	orrs	r2, r1
- 8007038:	605a      	str	r2, [r3, #4]
-  }
-
-  /* if required, configure TX pin active level inversion */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
- 800703a:	687b      	ldr	r3, [r7, #4]
- 800703c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 800703e:	2201      	movs	r2, #1
- 8007040:	4013      	ands	r3, r2
- 8007042:	d00b      	beq.n	800705c <UART_AdvFeatureConfig+0x4c>
-  {
-    assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
- 8007044:	687b      	ldr	r3, [r7, #4]
- 8007046:	681b      	ldr	r3, [r3, #0]
- 8007048:	685b      	ldr	r3, [r3, #4]
- 800704a:	4a43      	ldr	r2, [pc, #268]	@ (8007158 <UART_AdvFeatureConfig+0x148>)
- 800704c:	4013      	ands	r3, r2
- 800704e:	0019      	movs	r1, r3
- 8007050:	687b      	ldr	r3, [r7, #4]
- 8007052:	6ada      	ldr	r2, [r3, #44]	@ 0x2c
- 8007054:	687b      	ldr	r3, [r7, #4]
- 8007056:	681b      	ldr	r3, [r3, #0]
- 8007058:	430a      	orrs	r2, r1
- 800705a:	605a      	str	r2, [r3, #4]
-  }
-
-  /* if required, configure RX pin active level inversion */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
- 800705c:	687b      	ldr	r3, [r7, #4]
- 800705e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8007060:	2202      	movs	r2, #2
- 8007062:	4013      	ands	r3, r2
- 8007064:	d00b      	beq.n	800707e <UART_AdvFeatureConfig+0x6e>
-  {
-    assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
- 8007066:	687b      	ldr	r3, [r7, #4]
- 8007068:	681b      	ldr	r3, [r3, #0]
- 800706a:	685b      	ldr	r3, [r3, #4]
- 800706c:	4a3b      	ldr	r2, [pc, #236]	@ (800715c <UART_AdvFeatureConfig+0x14c>)
- 800706e:	4013      	ands	r3, r2
- 8007070:	0019      	movs	r1, r3
- 8007072:	687b      	ldr	r3, [r7, #4]
- 8007074:	6b1a      	ldr	r2, [r3, #48]	@ 0x30
- 8007076:	687b      	ldr	r3, [r7, #4]
- 8007078:	681b      	ldr	r3, [r3, #0]
- 800707a:	430a      	orrs	r2, r1
- 800707c:	605a      	str	r2, [r3, #4]
-  }
-
-  /* if required, configure data inversion */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
- 800707e:	687b      	ldr	r3, [r7, #4]
- 8007080:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8007082:	2204      	movs	r2, #4
- 8007084:	4013      	ands	r3, r2
- 8007086:	d00b      	beq.n	80070a0 <UART_AdvFeatureConfig+0x90>
-  {
-    assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
- 8007088:	687b      	ldr	r3, [r7, #4]
- 800708a:	681b      	ldr	r3, [r3, #0]
- 800708c:	685b      	ldr	r3, [r3, #4]
- 800708e:	4a34      	ldr	r2, [pc, #208]	@ (8007160 <UART_AdvFeatureConfig+0x150>)
- 8007090:	4013      	ands	r3, r2
- 8007092:	0019      	movs	r1, r3
- 8007094:	687b      	ldr	r3, [r7, #4]
- 8007096:	6b5a      	ldr	r2, [r3, #52]	@ 0x34
- 8007098:	687b      	ldr	r3, [r7, #4]
- 800709a:	681b      	ldr	r3, [r3, #0]
- 800709c:	430a      	orrs	r2, r1
- 800709e:	605a      	str	r2, [r3, #4]
-  }
-
-  /* if required, configure RX overrun detection disabling */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
- 80070a0:	687b      	ldr	r3, [r7, #4]
- 80070a2:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 80070a4:	2210      	movs	r2, #16
- 80070a6:	4013      	ands	r3, r2
- 80070a8:	d00b      	beq.n	80070c2 <UART_AdvFeatureConfig+0xb2>
-  {
-    assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable));
-    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
- 80070aa:	687b      	ldr	r3, [r7, #4]
- 80070ac:	681b      	ldr	r3, [r3, #0]
- 80070ae:	689b      	ldr	r3, [r3, #8]
- 80070b0:	4a2c      	ldr	r2, [pc, #176]	@ (8007164 <UART_AdvFeatureConfig+0x154>)
- 80070b2:	4013      	ands	r3, r2
- 80070b4:	0019      	movs	r1, r3
- 80070b6:	687b      	ldr	r3, [r7, #4]
- 80070b8:	6bda      	ldr	r2, [r3, #60]	@ 0x3c
- 80070ba:	687b      	ldr	r3, [r7, #4]
- 80070bc:	681b      	ldr	r3, [r3, #0]
- 80070be:	430a      	orrs	r2, r1
- 80070c0:	609a      	str	r2, [r3, #8]
-  }
-
-#if defined(HAL_DMA_MODULE_ENABLED)
-  /* if required, configure DMA disabling on reception error */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
- 80070c2:	687b      	ldr	r3, [r7, #4]
- 80070c4:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 80070c6:	2220      	movs	r2, #32
- 80070c8:	4013      	ands	r3, r2
- 80070ca:	d00b      	beq.n	80070e4 <UART_AdvFeatureConfig+0xd4>
-  {
-    assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError));
-    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
- 80070cc:	687b      	ldr	r3, [r7, #4]
- 80070ce:	681b      	ldr	r3, [r3, #0]
- 80070d0:	689b      	ldr	r3, [r3, #8]
- 80070d2:	4a25      	ldr	r2, [pc, #148]	@ (8007168 <UART_AdvFeatureConfig+0x158>)
- 80070d4:	4013      	ands	r3, r2
- 80070d6:	0019      	movs	r1, r3
- 80070d8:	687b      	ldr	r3, [r7, #4]
- 80070da:	6c1a      	ldr	r2, [r3, #64]	@ 0x40
- 80070dc:	687b      	ldr	r3, [r7, #4]
- 80070de:	681b      	ldr	r3, [r3, #0]
- 80070e0:	430a      	orrs	r2, r1
- 80070e2:	609a      	str	r2, [r3, #8]
-  }
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-  /* if required, configure auto Baud rate detection scheme */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
- 80070e4:	687b      	ldr	r3, [r7, #4]
- 80070e6:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 80070e8:	2240      	movs	r2, #64	@ 0x40
- 80070ea:	4013      	ands	r3, r2
- 80070ec:	d01d      	beq.n	800712a <UART_AdvFeatureConfig+0x11a>
-  {
-    assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance));
-    assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
- 80070ee:	687b      	ldr	r3, [r7, #4]
- 80070f0:	681b      	ldr	r3, [r3, #0]
- 80070f2:	685b      	ldr	r3, [r3, #4]
- 80070f4:	4a1d      	ldr	r2, [pc, #116]	@ (800716c <UART_AdvFeatureConfig+0x15c>)
- 80070f6:	4013      	ands	r3, r2
- 80070f8:	0019      	movs	r1, r3
- 80070fa:	687b      	ldr	r3, [r7, #4]
- 80070fc:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
- 80070fe:	687b      	ldr	r3, [r7, #4]
- 8007100:	681b      	ldr	r3, [r3, #0]
- 8007102:	430a      	orrs	r2, r1
- 8007104:	605a      	str	r2, [r3, #4]
-    /* set auto Baudrate detection parameters if detection is enabled */
-    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
- 8007106:	687b      	ldr	r3, [r7, #4]
- 8007108:	6c5a      	ldr	r2, [r3, #68]	@ 0x44
- 800710a:	2380      	movs	r3, #128	@ 0x80
- 800710c:	035b      	lsls	r3, r3, #13
- 800710e:	429a      	cmp	r2, r3
- 8007110:	d10b      	bne.n	800712a <UART_AdvFeatureConfig+0x11a>
-    {
-      assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode));
-      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
- 8007112:	687b      	ldr	r3, [r7, #4]
- 8007114:	681b      	ldr	r3, [r3, #0]
- 8007116:	685b      	ldr	r3, [r3, #4]
- 8007118:	4a15      	ldr	r2, [pc, #84]	@ (8007170 <UART_AdvFeatureConfig+0x160>)
- 800711a:	4013      	ands	r3, r2
- 800711c:	0019      	movs	r1, r3
- 800711e:	687b      	ldr	r3, [r7, #4]
- 8007120:	6c9a      	ldr	r2, [r3, #72]	@ 0x48
- 8007122:	687b      	ldr	r3, [r7, #4]
- 8007124:	681b      	ldr	r3, [r3, #0]
- 8007126:	430a      	orrs	r2, r1
- 8007128:	605a      	str	r2, [r3, #4]
-    }
-  }
-
-  /* if required, configure MSB first on communication line */
-  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
- 800712a:	687b      	ldr	r3, [r7, #4]
- 800712c:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 800712e:	2280      	movs	r2, #128	@ 0x80
- 8007130:	4013      	ands	r3, r2
- 8007132:	d00b      	beq.n	800714c <UART_AdvFeatureConfig+0x13c>
-  {
-    assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst));
-    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
- 8007134:	687b      	ldr	r3, [r7, #4]
- 8007136:	681b      	ldr	r3, [r3, #0]
- 8007138:	685b      	ldr	r3, [r3, #4]
- 800713a:	4a0e      	ldr	r2, [pc, #56]	@ (8007174 <UART_AdvFeatureConfig+0x164>)
- 800713c:	4013      	ands	r3, r2
- 800713e:	0019      	movs	r1, r3
- 8007140:	687b      	ldr	r3, [r7, #4]
- 8007142:	6cda      	ldr	r2, [r3, #76]	@ 0x4c
- 8007144:	687b      	ldr	r3, [r7, #4]
- 8007146:	681b      	ldr	r3, [r3, #0]
- 8007148:	430a      	orrs	r2, r1
- 800714a:	605a      	str	r2, [r3, #4]
-  }
-}
- 800714c:	46c0      	nop			@ (mov r8, r8)
- 800714e:	46bd      	mov	sp, r7
- 8007150:	b002      	add	sp, #8
- 8007152:	bd80      	pop	{r7, pc}
- 8007154:	ffff7fff 	.word	0xffff7fff
- 8007158:	fffdffff 	.word	0xfffdffff
- 800715c:	fffeffff 	.word	0xfffeffff
- 8007160:	fffbffff 	.word	0xfffbffff
- 8007164:	ffffefff 	.word	0xffffefff
- 8007168:	ffffdfff 	.word	0xffffdfff
- 800716c:	ffefffff 	.word	0xffefffff
- 8007170:	ff9fffff 	.word	0xff9fffff
- 8007174:	fff7ffff 	.word	0xfff7ffff
-
-08007178 <UART_CheckIdleState>:
-  * @brief Check the UART Idle State.
-  * @param huart UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart)
-{
- 8007178:	b580      	push	{r7, lr}
- 800717a:	b092      	sub	sp, #72	@ 0x48
- 800717c:	af02      	add	r7, sp, #8
- 800717e:	6078      	str	r0, [r7, #4]
-  uint32_t tickstart;
-
-  /* Initialize the UART ErrorCode */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
- 8007180:	687b      	ldr	r3, [r7, #4]
- 8007182:	2290      	movs	r2, #144	@ 0x90
- 8007184:	2100      	movs	r1, #0
- 8007186:	5099      	str	r1, [r3, r2]
-
-  /* Init tickstart for timeout management */
-  tickstart = HAL_GetTick();
- 8007188:	f7fc ffa6 	bl	80040d8 <HAL_GetTick>
- 800718c:	0003      	movs	r3, r0
- 800718e:	63fb      	str	r3, [r7, #60]	@ 0x3c
-
-  /* Check if the Transmitter is enabled */
-  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
- 8007190:	687b      	ldr	r3, [r7, #4]
- 8007192:	681b      	ldr	r3, [r3, #0]
- 8007194:	681b      	ldr	r3, [r3, #0]
- 8007196:	2208      	movs	r2, #8
- 8007198:	4013      	ands	r3, r2
- 800719a:	2b08      	cmp	r3, #8
- 800719c:	d12d      	bne.n	80071fa <UART_CheckIdleState+0x82>
-  {
-    /* Wait until TEACK flag is set */
-    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- 800719e:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 80071a0:	2280      	movs	r2, #128	@ 0x80
- 80071a2:	0391      	lsls	r1, r2, #14
- 80071a4:	6878      	ldr	r0, [r7, #4]
- 80071a6:	4a47      	ldr	r2, [pc, #284]	@ (80072c4 <UART_CheckIdleState+0x14c>)
- 80071a8:	9200      	str	r2, [sp, #0]
- 80071aa:	2200      	movs	r2, #0
- 80071ac:	f000 f88e 	bl	80072cc <UART_WaitOnFlagUntilTimeout>
- 80071b0:	1e03      	subs	r3, r0, #0
- 80071b2:	d022      	beq.n	80071fa <UART_CheckIdleState+0x82>
- */
-__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
-{
-  uint32_t result;
-
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 80071b4:	f3ef 8310 	mrs	r3, PRIMASK
- 80071b8:	627b      	str	r3, [r7, #36]	@ 0x24
-  return(result);
- 80071ba:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
-    {
-      /* Disable TXE interrupt for the interrupt process */
-      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
- 80071bc:	63bb      	str	r3, [r7, #56]	@ 0x38
- 80071be:	2301      	movs	r3, #1
- 80071c0:	62bb      	str	r3, [r7, #40]	@ 0x28
-  \details Assigns the given value to the Priority Mask Register.
-  \param [in]    priMask  Priority Mask
- */
-__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
-{
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80071c2:	6abb      	ldr	r3, [r7, #40]	@ 0x28
- 80071c4:	f383 8810 	msr	PRIMASK, r3
-}
- 80071c8:	46c0      	nop			@ (mov r8, r8)
- 80071ca:	687b      	ldr	r3, [r7, #4]
- 80071cc:	681b      	ldr	r3, [r3, #0]
- 80071ce:	681a      	ldr	r2, [r3, #0]
- 80071d0:	687b      	ldr	r3, [r7, #4]
- 80071d2:	681b      	ldr	r3, [r3, #0]
- 80071d4:	2180      	movs	r1, #128	@ 0x80
- 80071d6:	438a      	bics	r2, r1
- 80071d8:	601a      	str	r2, [r3, #0]
- 80071da:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 80071dc:	62fb      	str	r3, [r7, #44]	@ 0x2c
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80071de:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
- 80071e0:	f383 8810 	msr	PRIMASK, r3
-}
- 80071e4:	46c0      	nop			@ (mov r8, r8)
-
-      huart->gState = HAL_UART_STATE_READY;
- 80071e6:	687b      	ldr	r3, [r7, #4]
- 80071e8:	2288      	movs	r2, #136	@ 0x88
- 80071ea:	2120      	movs	r1, #32
- 80071ec:	5099      	str	r1, [r3, r2]
-
-      __HAL_UNLOCK(huart);
- 80071ee:	687b      	ldr	r3, [r7, #4]
- 80071f0:	2284      	movs	r2, #132	@ 0x84
- 80071f2:	2100      	movs	r1, #0
- 80071f4:	5499      	strb	r1, [r3, r2]
-
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
- 80071f6:	2303      	movs	r3, #3
- 80071f8:	e060      	b.n	80072bc <UART_CheckIdleState+0x144>
-    }
-  }
-
-  /* Check if the Receiver is enabled */
-  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
- 80071fa:	687b      	ldr	r3, [r7, #4]
- 80071fc:	681b      	ldr	r3, [r3, #0]
- 80071fe:	681b      	ldr	r3, [r3, #0]
- 8007200:	2204      	movs	r2, #4
- 8007202:	4013      	ands	r3, r2
- 8007204:	2b04      	cmp	r3, #4
- 8007206:	d146      	bne.n	8007296 <UART_CheckIdleState+0x11e>
-  {
-    /* Wait until REACK flag is set */
-    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
- 8007208:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 800720a:	2280      	movs	r2, #128	@ 0x80
- 800720c:	03d1      	lsls	r1, r2, #15
- 800720e:	6878      	ldr	r0, [r7, #4]
- 8007210:	4a2c      	ldr	r2, [pc, #176]	@ (80072c4 <UART_CheckIdleState+0x14c>)
- 8007212:	9200      	str	r2, [sp, #0]
- 8007214:	2200      	movs	r2, #0
- 8007216:	f000 f859 	bl	80072cc <UART_WaitOnFlagUntilTimeout>
- 800721a:	1e03      	subs	r3, r0, #0
- 800721c:	d03b      	beq.n	8007296 <UART_CheckIdleState+0x11e>
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 800721e:	f3ef 8310 	mrs	r3, PRIMASK
- 8007222:	60fb      	str	r3, [r7, #12]
-  return(result);
- 8007224:	68fb      	ldr	r3, [r7, #12]
-    {
-      /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error)
-      interrupts for the interrupt process */
-      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
- 8007226:	637b      	str	r3, [r7, #52]	@ 0x34
- 8007228:	2301      	movs	r3, #1
- 800722a:	613b      	str	r3, [r7, #16]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 800722c:	693b      	ldr	r3, [r7, #16]
- 800722e:	f383 8810 	msr	PRIMASK, r3
-}
- 8007232:	46c0      	nop			@ (mov r8, r8)
- 8007234:	687b      	ldr	r3, [r7, #4]
- 8007236:	681b      	ldr	r3, [r3, #0]
- 8007238:	681a      	ldr	r2, [r3, #0]
- 800723a:	687b      	ldr	r3, [r7, #4]
- 800723c:	681b      	ldr	r3, [r3, #0]
- 800723e:	4922      	ldr	r1, [pc, #136]	@ (80072c8 <UART_CheckIdleState+0x150>)
- 8007240:	400a      	ands	r2, r1
- 8007242:	601a      	str	r2, [r3, #0]
- 8007244:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
- 8007246:	617b      	str	r3, [r7, #20]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8007248:	697b      	ldr	r3, [r7, #20]
- 800724a:	f383 8810 	msr	PRIMASK, r3
-}
- 800724e:	46c0      	nop			@ (mov r8, r8)
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 8007250:	f3ef 8310 	mrs	r3, PRIMASK
- 8007254:	61bb      	str	r3, [r7, #24]
-  return(result);
- 8007256:	69bb      	ldr	r3, [r7, #24]
-      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8007258:	633b      	str	r3, [r7, #48]	@ 0x30
- 800725a:	2301      	movs	r3, #1
- 800725c:	61fb      	str	r3, [r7, #28]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 800725e:	69fb      	ldr	r3, [r7, #28]
- 8007260:	f383 8810 	msr	PRIMASK, r3
-}
- 8007264:	46c0      	nop			@ (mov r8, r8)
- 8007266:	687b      	ldr	r3, [r7, #4]
- 8007268:	681b      	ldr	r3, [r3, #0]
- 800726a:	689a      	ldr	r2, [r3, #8]
- 800726c:	687b      	ldr	r3, [r7, #4]
- 800726e:	681b      	ldr	r3, [r3, #0]
- 8007270:	2101      	movs	r1, #1
- 8007272:	438a      	bics	r2, r1
- 8007274:	609a      	str	r2, [r3, #8]
- 8007276:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
- 8007278:	623b      	str	r3, [r7, #32]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 800727a:	6a3b      	ldr	r3, [r7, #32]
- 800727c:	f383 8810 	msr	PRIMASK, r3
-}
- 8007280:	46c0      	nop			@ (mov r8, r8)
-
-      huart->RxState = HAL_UART_STATE_READY;
- 8007282:	687b      	ldr	r3, [r7, #4]
- 8007284:	228c      	movs	r2, #140	@ 0x8c
- 8007286:	2120      	movs	r1, #32
- 8007288:	5099      	str	r1, [r3, r2]
-
-      __HAL_UNLOCK(huart);
- 800728a:	687b      	ldr	r3, [r7, #4]
- 800728c:	2284      	movs	r2, #132	@ 0x84
- 800728e:	2100      	movs	r1, #0
- 8007290:	5499      	strb	r1, [r3, r2]
-
-      /* Timeout occurred */
-      return HAL_TIMEOUT;
- 8007292:	2303      	movs	r3, #3
- 8007294:	e012      	b.n	80072bc <UART_CheckIdleState+0x144>
-    }
-  }
-
-  /* Initialize the UART State */
-  huart->gState = HAL_UART_STATE_READY;
- 8007296:	687b      	ldr	r3, [r7, #4]
- 8007298:	2288      	movs	r2, #136	@ 0x88
- 800729a:	2120      	movs	r1, #32
- 800729c:	5099      	str	r1, [r3, r2]
-  huart->RxState = HAL_UART_STATE_READY;
- 800729e:	687b      	ldr	r3, [r7, #4]
- 80072a0:	228c      	movs	r2, #140	@ 0x8c
- 80072a2:	2120      	movs	r1, #32
- 80072a4:	5099      	str	r1, [r3, r2]
-  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- 80072a6:	687b      	ldr	r3, [r7, #4]
- 80072a8:	2200      	movs	r2, #0
- 80072aa:	66da      	str	r2, [r3, #108]	@ 0x6c
-  huart->RxEventType = HAL_UART_RXEVENT_TC;
- 80072ac:	687b      	ldr	r3, [r7, #4]
- 80072ae:	2200      	movs	r2, #0
- 80072b0:	671a      	str	r2, [r3, #112]	@ 0x70
-
-  __HAL_UNLOCK(huart);
- 80072b2:	687b      	ldr	r3, [r7, #4]
- 80072b4:	2284      	movs	r2, #132	@ 0x84
- 80072b6:	2100      	movs	r1, #0
- 80072b8:	5499      	strb	r1, [r3, r2]
-
-  return HAL_OK;
- 80072ba:	2300      	movs	r3, #0
-}
- 80072bc:	0018      	movs	r0, r3
- 80072be:	46bd      	mov	sp, r7
- 80072c0:	b010      	add	sp, #64	@ 0x40
- 80072c2:	bd80      	pop	{r7, pc}
- 80072c4:	01ffffff 	.word	0x01ffffff
- 80072c8:	fffffedf 	.word	0xfffffedf
-
-080072cc <UART_WaitOnFlagUntilTimeout>:
-  * @param Timeout   Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,
-                                              uint32_t Tickstart, uint32_t Timeout)
-{
- 80072cc:	b580      	push	{r7, lr}
- 80072ce:	b084      	sub	sp, #16
- 80072d0:	af00      	add	r7, sp, #0
- 80072d2:	60f8      	str	r0, [r7, #12]
- 80072d4:	60b9      	str	r1, [r7, #8]
- 80072d6:	603b      	str	r3, [r7, #0]
- 80072d8:	1dfb      	adds	r3, r7, #7
- 80072da:	701a      	strb	r2, [r3, #0]
-  /* Wait until flag is set */
-  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 80072dc:	e051      	b.n	8007382 <UART_WaitOnFlagUntilTimeout+0xb6>
-  {
-    /* Check for the Timeout */
-    if (Timeout != HAL_MAX_DELAY)
- 80072de:	69bb      	ldr	r3, [r7, #24]
- 80072e0:	3301      	adds	r3, #1
- 80072e2:	d04e      	beq.n	8007382 <UART_WaitOnFlagUntilTimeout+0xb6>
-    {
-      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
- 80072e4:	f7fc fef8 	bl	80040d8 <HAL_GetTick>
- 80072e8:	0002      	movs	r2, r0
- 80072ea:	683b      	ldr	r3, [r7, #0]
- 80072ec:	1ad3      	subs	r3, r2, r3
- 80072ee:	69ba      	ldr	r2, [r7, #24]
- 80072f0:	429a      	cmp	r2, r3
- 80072f2:	d302      	bcc.n	80072fa <UART_WaitOnFlagUntilTimeout+0x2e>
- 80072f4:	69bb      	ldr	r3, [r7, #24]
- 80072f6:	2b00      	cmp	r3, #0
- 80072f8:	d101      	bne.n	80072fe <UART_WaitOnFlagUntilTimeout+0x32>
-      {
-
-        return HAL_TIMEOUT;
- 80072fa:	2303      	movs	r3, #3
- 80072fc:	e051      	b.n	80073a2 <UART_WaitOnFlagUntilTimeout+0xd6>
-      }
-
-      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
- 80072fe:	68fb      	ldr	r3, [r7, #12]
- 8007300:	681b      	ldr	r3, [r3, #0]
- 8007302:	681b      	ldr	r3, [r3, #0]
- 8007304:	2204      	movs	r2, #4
- 8007306:	4013      	ands	r3, r2
- 8007308:	d03b      	beq.n	8007382 <UART_WaitOnFlagUntilTimeout+0xb6>
- 800730a:	68bb      	ldr	r3, [r7, #8]
- 800730c:	2b80      	cmp	r3, #128	@ 0x80
- 800730e:	d038      	beq.n	8007382 <UART_WaitOnFlagUntilTimeout+0xb6>
- 8007310:	68bb      	ldr	r3, [r7, #8]
- 8007312:	2b40      	cmp	r3, #64	@ 0x40
- 8007314:	d035      	beq.n	8007382 <UART_WaitOnFlagUntilTimeout+0xb6>
-      {
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
- 8007316:	68fb      	ldr	r3, [r7, #12]
- 8007318:	681b      	ldr	r3, [r3, #0]
- 800731a:	69db      	ldr	r3, [r3, #28]
- 800731c:	2208      	movs	r2, #8
- 800731e:	4013      	ands	r3, r2
- 8007320:	2b08      	cmp	r3, #8
- 8007322:	d111      	bne.n	8007348 <UART_WaitOnFlagUntilTimeout+0x7c>
-        {
-          /* Clear Overrun Error flag*/
-          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
- 8007324:	68fb      	ldr	r3, [r7, #12]
- 8007326:	681b      	ldr	r3, [r3, #0]
- 8007328:	2208      	movs	r2, #8
- 800732a:	621a      	str	r2, [r3, #32]
-
-          /* Blocking error : transfer is aborted
-          Set the UART state ready to be able to start again the process,
-          Disable Rx Interrupts if ongoing */
-          UART_EndRxTransfer(huart);
- 800732c:	68fb      	ldr	r3, [r7, #12]
- 800732e:	0018      	movs	r0, r3
- 8007330:	f000 f922 	bl	8007578 <UART_EndRxTransfer>
-
-          huart->ErrorCode = HAL_UART_ERROR_ORE;
- 8007334:	68fb      	ldr	r3, [r7, #12]
- 8007336:	2290      	movs	r2, #144	@ 0x90
- 8007338:	2108      	movs	r1, #8
- 800733a:	5099      	str	r1, [r3, r2]
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(huart);
- 800733c:	68fb      	ldr	r3, [r7, #12]
- 800733e:	2284      	movs	r2, #132	@ 0x84
- 8007340:	2100      	movs	r1, #0
- 8007342:	5499      	strb	r1, [r3, r2]
-
-          return HAL_ERROR;
- 8007344:	2301      	movs	r3, #1
- 8007346:	e02c      	b.n	80073a2 <UART_WaitOnFlagUntilTimeout+0xd6>
-        }
-        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
- 8007348:	68fb      	ldr	r3, [r7, #12]
- 800734a:	681b      	ldr	r3, [r3, #0]
- 800734c:	69da      	ldr	r2, [r3, #28]
- 800734e:	2380      	movs	r3, #128	@ 0x80
- 8007350:	011b      	lsls	r3, r3, #4
- 8007352:	401a      	ands	r2, r3
- 8007354:	2380      	movs	r3, #128	@ 0x80
- 8007356:	011b      	lsls	r3, r3, #4
- 8007358:	429a      	cmp	r2, r3
- 800735a:	d112      	bne.n	8007382 <UART_WaitOnFlagUntilTimeout+0xb6>
-        {
-          /* Clear Receiver Timeout flag*/
-          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
- 800735c:	68fb      	ldr	r3, [r7, #12]
- 800735e:	681b      	ldr	r3, [r3, #0]
- 8007360:	2280      	movs	r2, #128	@ 0x80
- 8007362:	0112      	lsls	r2, r2, #4
- 8007364:	621a      	str	r2, [r3, #32]
-
-          /* Blocking error : transfer is aborted
-          Set the UART state ready to be able to start again the process,
-          Disable Rx Interrupts if ongoing */
-          UART_EndRxTransfer(huart);
- 8007366:	68fb      	ldr	r3, [r7, #12]
- 8007368:	0018      	movs	r0, r3
- 800736a:	f000 f905 	bl	8007578 <UART_EndRxTransfer>
-
-          huart->ErrorCode = HAL_UART_ERROR_RTO;
- 800736e:	68fb      	ldr	r3, [r7, #12]
- 8007370:	2290      	movs	r2, #144	@ 0x90
- 8007372:	2120      	movs	r1, #32
- 8007374:	5099      	str	r1, [r3, r2]
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(huart);
- 8007376:	68fb      	ldr	r3, [r7, #12]
- 8007378:	2284      	movs	r2, #132	@ 0x84
- 800737a:	2100      	movs	r1, #0
- 800737c:	5499      	strb	r1, [r3, r2]
-
-          return HAL_TIMEOUT;
- 800737e:	2303      	movs	r3, #3
- 8007380:	e00f      	b.n	80073a2 <UART_WaitOnFlagUntilTimeout+0xd6>
-  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
- 8007382:	68fb      	ldr	r3, [r7, #12]
- 8007384:	681b      	ldr	r3, [r3, #0]
- 8007386:	69db      	ldr	r3, [r3, #28]
- 8007388:	68ba      	ldr	r2, [r7, #8]
- 800738a:	4013      	ands	r3, r2
- 800738c:	68ba      	ldr	r2, [r7, #8]
- 800738e:	1ad3      	subs	r3, r2, r3
- 8007390:	425a      	negs	r2, r3
- 8007392:	4153      	adcs	r3, r2
- 8007394:	b2db      	uxtb	r3, r3
- 8007396:	001a      	movs	r2, r3
- 8007398:	1dfb      	adds	r3, r7, #7
- 800739a:	781b      	ldrb	r3, [r3, #0]
- 800739c:	429a      	cmp	r2, r3
- 800739e:	d09e      	beq.n	80072de <UART_WaitOnFlagUntilTimeout+0x12>
-        }
-      }
-    }
-  }
-  return HAL_OK;
- 80073a0:	2300      	movs	r3, #0
-}
- 80073a2:	0018      	movs	r0, r3
- 80073a4:	46bd      	mov	sp, r7
- 80073a6:	b004      	add	sp, #16
- 80073a8:	bd80      	pop	{r7, pc}
+ 8004488:	4770      	bx	lr
 	...
 
-080073ac <UART_Start_Receive_DMA>:
-  * @param  pData Pointer to data buffer (u8 or u16 data elements).
-  * @param  Size  Amount of data elements (u8 or u16) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- 80073ac:	b580      	push	{r7, lr}
- 80073ae:	b090      	sub	sp, #64	@ 0x40
- 80073b0:	af00      	add	r7, sp, #0
- 80073b2:	60f8      	str	r0, [r7, #12]
- 80073b4:	60b9      	str	r1, [r7, #8]
- 80073b6:	1dbb      	adds	r3, r7, #6
- 80073b8:	801a      	strh	r2, [r3, #0]
-  huart->pRxBuffPtr = pData;
- 80073ba:	68fb      	ldr	r3, [r7, #12]
- 80073bc:	68ba      	ldr	r2, [r7, #8]
- 80073be:	659a      	str	r2, [r3, #88]	@ 0x58
-  huart->RxXferSize = Size;
- 80073c0:	68fb      	ldr	r3, [r7, #12]
- 80073c2:	1dba      	adds	r2, r7, #6
- 80073c4:	215c      	movs	r1, #92	@ 0x5c
- 80073c6:	8812      	ldrh	r2, [r2, #0]
- 80073c8:	525a      	strh	r2, [r3, r1]
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
- 80073ca:	68fb      	ldr	r3, [r7, #12]
- 80073cc:	2290      	movs	r2, #144	@ 0x90
- 80073ce:	2100      	movs	r1, #0
- 80073d0:	5099      	str	r1, [r3, r2]
-  huart->RxState = HAL_UART_STATE_BUSY_RX;
- 80073d2:	68fb      	ldr	r3, [r7, #12]
- 80073d4:	228c      	movs	r2, #140	@ 0x8c
- 80073d6:	2122      	movs	r1, #34	@ 0x22
- 80073d8:	5099      	str	r1, [r3, r2]
-
-  if (huart->hdmarx != NULL)
- 80073da:	68fb      	ldr	r3, [r7, #12]
- 80073dc:	2280      	movs	r2, #128	@ 0x80
- 80073de:	589b      	ldr	r3, [r3, r2]
- 80073e0:	2b00      	cmp	r3, #0
- 80073e2:	d02d      	beq.n	8007440 <UART_Start_Receive_DMA+0x94>
-  {
-    /* Set the UART DMA transfer complete callback */
-    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
- 80073e4:	68fb      	ldr	r3, [r7, #12]
- 80073e6:	2280      	movs	r2, #128	@ 0x80
- 80073e8:	589b      	ldr	r3, [r3, r2]
- 80073ea:	4a40      	ldr	r2, [pc, #256]	@ (80074ec <UART_Start_Receive_DMA+0x140>)
- 80073ec:	62da      	str	r2, [r3, #44]	@ 0x2c
-
-    /* Set the UART DMA Half transfer complete callback */
-    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
- 80073ee:	68fb      	ldr	r3, [r7, #12]
- 80073f0:	2280      	movs	r2, #128	@ 0x80
- 80073f2:	589b      	ldr	r3, [r3, r2]
- 80073f4:	4a3e      	ldr	r2, [pc, #248]	@ (80074f0 <UART_Start_Receive_DMA+0x144>)
- 80073f6:	631a      	str	r2, [r3, #48]	@ 0x30
-
-    /* Set the DMA error callback */
-    huart->hdmarx->XferErrorCallback = UART_DMAError;
- 80073f8:	68fb      	ldr	r3, [r7, #12]
- 80073fa:	2280      	movs	r2, #128	@ 0x80
- 80073fc:	589b      	ldr	r3, [r3, r2]
- 80073fe:	4a3d      	ldr	r2, [pc, #244]	@ (80074f4 <UART_Start_Receive_DMA+0x148>)
- 8007400:	635a      	str	r2, [r3, #52]	@ 0x34
-
-    /* Set the DMA abort callback */
-    huart->hdmarx->XferAbortCallback = NULL;
- 8007402:	68fb      	ldr	r3, [r7, #12]
- 8007404:	2280      	movs	r2, #128	@ 0x80
- 8007406:	589b      	ldr	r3, [r3, r2]
- 8007408:	2200      	movs	r2, #0
- 800740a:	639a      	str	r2, [r3, #56]	@ 0x38
-
-    /* Enable the DMA channel */
-    if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
- 800740c:	68fb      	ldr	r3, [r7, #12]
- 800740e:	2280      	movs	r2, #128	@ 0x80
- 8007410:	5898      	ldr	r0, [r3, r2]
- 8007412:	68fb      	ldr	r3, [r7, #12]
- 8007414:	681b      	ldr	r3, [r3, #0]
- 8007416:	3324      	adds	r3, #36	@ 0x24
- 8007418:	0019      	movs	r1, r3
- 800741a:	68fb      	ldr	r3, [r7, #12]
- 800741c:	6d9b      	ldr	r3, [r3, #88]	@ 0x58
- 800741e:	001a      	movs	r2, r3
- 8007420:	1dbb      	adds	r3, r7, #6
- 8007422:	881b      	ldrh	r3, [r3, #0]
- 8007424:	f7fd f80c 	bl	8004440 <HAL_DMA_Start_IT>
- 8007428:	1e03      	subs	r3, r0, #0
- 800742a:	d009      	beq.n	8007440 <UART_Start_Receive_DMA+0x94>
-    {
-      /* Set error code to DMA */
-      huart->ErrorCode = HAL_UART_ERROR_DMA;
- 800742c:	68fb      	ldr	r3, [r7, #12]
- 800742e:	2290      	movs	r2, #144	@ 0x90
- 8007430:	2110      	movs	r1, #16
- 8007432:	5099      	str	r1, [r3, r2]
-
-      /* Restore huart->RxState to ready */
-      huart->RxState = HAL_UART_STATE_READY;
- 8007434:	68fb      	ldr	r3, [r7, #12]
- 8007436:	228c      	movs	r2, #140	@ 0x8c
- 8007438:	2120      	movs	r1, #32
- 800743a:	5099      	str	r1, [r3, r2]
-
-      return HAL_ERROR;
- 800743c:	2301      	movs	r3, #1
- 800743e:	e050      	b.n	80074e2 <UART_Start_Receive_DMA+0x136>
-    }
-  }
-
-  /* Enable the UART Parity Error Interrupt */
-  if (huart->Init.Parity != UART_PARITY_NONE)
- 8007440:	68fb      	ldr	r3, [r7, #12]
- 8007442:	691b      	ldr	r3, [r3, #16]
- 8007444:	2b00      	cmp	r3, #0
- 8007446:	d019      	beq.n	800747c <UART_Start_Receive_DMA+0xd0>
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 8007448:	f3ef 8310 	mrs	r3, PRIMASK
- 800744c:	62bb      	str	r3, [r7, #40]	@ 0x28
-  return(result);
- 800744e:	6abb      	ldr	r3, [r7, #40]	@ 0x28
-  {
-    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- 8007450:	63fb      	str	r3, [r7, #60]	@ 0x3c
- 8007452:	2301      	movs	r3, #1
- 8007454:	62fb      	str	r3, [r7, #44]	@ 0x2c
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8007456:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
- 8007458:	f383 8810 	msr	PRIMASK, r3
-}
- 800745c:	46c0      	nop			@ (mov r8, r8)
- 800745e:	68fb      	ldr	r3, [r7, #12]
- 8007460:	681b      	ldr	r3, [r3, #0]
- 8007462:	681a      	ldr	r2, [r3, #0]
- 8007464:	68fb      	ldr	r3, [r7, #12]
- 8007466:	681b      	ldr	r3, [r3, #0]
- 8007468:	2180      	movs	r1, #128	@ 0x80
- 800746a:	0049      	lsls	r1, r1, #1
- 800746c:	430a      	orrs	r2, r1
- 800746e:	601a      	str	r2, [r3, #0]
- 8007470:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8007472:	633b      	str	r3, [r7, #48]	@ 0x30
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8007474:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
- 8007476:	f383 8810 	msr	PRIMASK, r3
-}
- 800747a:	46c0      	nop			@ (mov r8, r8)
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 800747c:	f3ef 8310 	mrs	r3, PRIMASK
- 8007480:	613b      	str	r3, [r7, #16]
-  return(result);
- 8007482:	693b      	ldr	r3, [r7, #16]
-  }
-
-  /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 8007484:	63bb      	str	r3, [r7, #56]	@ 0x38
- 8007486:	2301      	movs	r3, #1
- 8007488:	617b      	str	r3, [r7, #20]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 800748a:	697b      	ldr	r3, [r7, #20]
- 800748c:	f383 8810 	msr	PRIMASK, r3
-}
- 8007490:	46c0      	nop			@ (mov r8, r8)
- 8007492:	68fb      	ldr	r3, [r7, #12]
- 8007494:	681b      	ldr	r3, [r3, #0]
- 8007496:	689a      	ldr	r2, [r3, #8]
- 8007498:	68fb      	ldr	r3, [r7, #12]
- 800749a:	681b      	ldr	r3, [r3, #0]
- 800749c:	2101      	movs	r1, #1
- 800749e:	430a      	orrs	r2, r1
- 80074a0:	609a      	str	r2, [r3, #8]
- 80074a2:	6bbb      	ldr	r3, [r7, #56]	@ 0x38
- 80074a4:	61bb      	str	r3, [r7, #24]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80074a6:	69bb      	ldr	r3, [r7, #24]
- 80074a8:	f383 8810 	msr	PRIMASK, r3
-}
- 80074ac:	46c0      	nop			@ (mov r8, r8)
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 80074ae:	f3ef 8310 	mrs	r3, PRIMASK
- 80074b2:	61fb      	str	r3, [r7, #28]
-  return(result);
- 80074b4:	69fb      	ldr	r3, [r7, #28]
-
-  /* Enable the DMA transfer for the receiver request by setting the DMAR bit
-  in the UART CR3 register */
-  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- 80074b6:	637b      	str	r3, [r7, #52]	@ 0x34
- 80074b8:	2301      	movs	r3, #1
- 80074ba:	623b      	str	r3, [r7, #32]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80074bc:	6a3b      	ldr	r3, [r7, #32]
- 80074be:	f383 8810 	msr	PRIMASK, r3
-}
- 80074c2:	46c0      	nop			@ (mov r8, r8)
- 80074c4:	68fb      	ldr	r3, [r7, #12]
- 80074c6:	681b      	ldr	r3, [r3, #0]
- 80074c8:	689a      	ldr	r2, [r3, #8]
- 80074ca:	68fb      	ldr	r3, [r7, #12]
- 80074cc:	681b      	ldr	r3, [r3, #0]
- 80074ce:	2140      	movs	r1, #64	@ 0x40
- 80074d0:	430a      	orrs	r2, r1
- 80074d2:	609a      	str	r2, [r3, #8]
- 80074d4:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
- 80074d6:	627b      	str	r3, [r7, #36]	@ 0x24
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80074d8:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 80074da:	f383 8810 	msr	PRIMASK, r3
-}
- 80074de:	46c0      	nop			@ (mov r8, r8)
-
-  return HAL_OK;
- 80074e0:	2300      	movs	r3, #0
-}
- 80074e2:	0018      	movs	r0, r3
- 80074e4:	46bd      	mov	sp, r7
- 80074e6:	b010      	add	sp, #64	@ 0x40
- 80074e8:	bd80      	pop	{r7, pc}
- 80074ea:	46c0      	nop			@ (mov r8, r8)
- 80074ec:	08007645 	.word	0x08007645
- 80074f0:	080077ad 	.word	0x080077ad
- 80074f4:	0800782b 	.word	0x0800782b
-
-080074f8 <UART_EndTxTransfer>:
+0800448c <UART_EndTxTransfer>:
   * @brief  End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
   * @param  huart UART handle.
   * @retval None
   */
 static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
 {
- 80074f8:	b580      	push	{r7, lr}
- 80074fa:	b08a      	sub	sp, #40	@ 0x28
- 80074fc:	af00      	add	r7, sp, #0
- 80074fe:	6078      	str	r0, [r7, #4]
+ 800448c:	b530      	push	{r4, r5, lr}
+ */
+__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
   __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 8007500:	f3ef 8310 	mrs	r3, PRIMASK
- 8007504:	60bb      	str	r3, [r7, #8]
-  return(result);
- 8007506:	68bb      	ldr	r3, [r7, #8]
+ 800448e:	f3ef 8410 	mrs	r4, PRIMASK
+  \details Assigns the given value to the Priority Mask Register.
+  \param [in]    priMask  Priority Mask
+ */
+__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004492:	2201      	movs	r2, #1
+ 8004494:	f382 8810 	msr	PRIMASK, r2
   /* Disable TXEIE, TCIE, TXFT interrupts */
   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE));
- 8007508:	627b      	str	r3, [r7, #36]	@ 0x24
- 800750a:	2301      	movs	r3, #1
- 800750c:	60fb      	str	r3, [r7, #12]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 800750e:	68fb      	ldr	r3, [r7, #12]
- 8007510:	f383 8810 	msr	PRIMASK, r3
-}
- 8007514:	46c0      	nop			@ (mov r8, r8)
- 8007516:	687b      	ldr	r3, [r7, #4]
- 8007518:	681b      	ldr	r3, [r3, #0]
- 800751a:	681a      	ldr	r2, [r3, #0]
- 800751c:	687b      	ldr	r3, [r7, #4]
- 800751e:	681b      	ldr	r3, [r3, #0]
- 8007520:	21c0      	movs	r1, #192	@ 0xc0
- 8007522:	438a      	bics	r2, r1
- 8007524:	601a      	str	r2, [r3, #0]
- 8007526:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 8007528:	613b      	str	r3, [r7, #16]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 800752a:	693b      	ldr	r3, [r7, #16]
- 800752c:	f383 8810 	msr	PRIMASK, r3
-}
- 8007530:	46c0      	nop			@ (mov r8, r8)
+ 8004498:	25c0      	movs	r5, #192	@ 0xc0
+ 800449a:	6801      	ldr	r1, [r0, #0]
+ 800449c:	680b      	ldr	r3, [r1, #0]
+ 800449e:	43ab      	bics	r3, r5
+ 80044a0:	600b      	str	r3, [r1, #0]
+ 80044a2:	f384 8810 	msr	PRIMASK, r4
   __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 8007532:	f3ef 8310 	mrs	r3, PRIMASK
- 8007536:	617b      	str	r3, [r7, #20]
-  return(result);
- 8007538:	697b      	ldr	r3, [r7, #20]
+ 80044a6:	f3ef 8110 	mrs	r1, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 80044aa:	f382 8810 	msr	PRIMASK, r2
   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE));
- 800753a:	623b      	str	r3, [r7, #32]
- 800753c:	2301      	movs	r3, #1
- 800753e:	61bb      	str	r3, [r7, #24]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8007540:	69bb      	ldr	r3, [r7, #24]
- 8007542:	f383 8810 	msr	PRIMASK, r3
-}
- 8007546:	46c0      	nop			@ (mov r8, r8)
- 8007548:	687b      	ldr	r3, [r7, #4]
- 800754a:	681b      	ldr	r3, [r3, #0]
- 800754c:	689a      	ldr	r2, [r3, #8]
- 800754e:	687b      	ldr	r3, [r7, #4]
- 8007550:	681b      	ldr	r3, [r3, #0]
- 8007552:	4908      	ldr	r1, [pc, #32]	@ (8007574 <UART_EndTxTransfer+0x7c>)
- 8007554:	400a      	ands	r2, r1
- 8007556:	609a      	str	r2, [r3, #8]
- 8007558:	6a3b      	ldr	r3, [r7, #32]
- 800755a:	61fb      	str	r3, [r7, #28]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 800755c:	69fb      	ldr	r3, [r7, #28]
- 800755e:	f383 8810 	msr	PRIMASK, r3
-}
- 8007562:	46c0      	nop			@ (mov r8, r8)
+ 80044ae:	6802      	ldr	r2, [r0, #0]
+ 80044b0:	4c04      	ldr	r4, [pc, #16]	@ (80044c4 <UART_EndTxTransfer+0x38>)
+ 80044b2:	6893      	ldr	r3, [r2, #8]
+ 80044b4:	4023      	ands	r3, r4
+ 80044b6:	6093      	str	r3, [r2, #8]
+ 80044b8:	f381 8810 	msr	PRIMASK, r1
 
   /* At end of Tx process, restore huart->gState to Ready */
   huart->gState = HAL_UART_STATE_READY;
- 8007564:	687b      	ldr	r3, [r7, #4]
- 8007566:	2288      	movs	r2, #136	@ 0x88
- 8007568:	2120      	movs	r1, #32
- 800756a:	5099      	str	r1, [r3, r2]
+ 80044bc:	2320      	movs	r3, #32
+ 80044be:	3088      	adds	r0, #136	@ 0x88
+ 80044c0:	6003      	str	r3, [r0, #0]
 }
- 800756c:	46c0      	nop			@ (mov r8, r8)
- 800756e:	46bd      	mov	sp, r7
- 8007570:	b00a      	add	sp, #40	@ 0x28
- 8007572:	bd80      	pop	{r7, pc}
- 8007574:	ff7fffff 	.word	0xff7fffff
+ 80044c2:	bd30      	pop	{r4, r5, pc}
+ 80044c4:	ff7fffff 	.word	0xff7fffff
 
-08007578 <UART_EndRxTransfer>:
+080044c8 <UART_EndRxTransfer>:
   * @brief  End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
   * @param  huart UART handle.
   * @retval None
   */
 static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
 {
- 8007578:	b580      	push	{r7, lr}
- 800757a:	b08e      	sub	sp, #56	@ 0x38
- 800757c:	af00      	add	r7, sp, #0
- 800757e:	6078      	str	r0, [r7, #4]
+ 80044c8:	b530      	push	{r4, r5, lr}
   __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 8007580:	f3ef 8310 	mrs	r3, PRIMASK
- 8007584:	617b      	str	r3, [r7, #20]
-  return(result);
- 8007586:	697b      	ldr	r3, [r7, #20]
+ 80044ca:	f3ef 8410 	mrs	r4, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 80044ce:	2201      	movs	r2, #1
+ 80044d0:	f382 8810 	msr	PRIMASK, r2
   /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */
   ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
- 8007588:	637b      	str	r3, [r7, #52]	@ 0x34
- 800758a:	2301      	movs	r3, #1
- 800758c:	61bb      	str	r3, [r7, #24]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 800758e:	69bb      	ldr	r3, [r7, #24]
- 8007590:	f383 8810 	msr	PRIMASK, r3
-}
- 8007594:	46c0      	nop			@ (mov r8, r8)
- 8007596:	687b      	ldr	r3, [r7, #4]
- 8007598:	681b      	ldr	r3, [r3, #0]
- 800759a:	681a      	ldr	r2, [r3, #0]
- 800759c:	687b      	ldr	r3, [r7, #4]
- 800759e:	681b      	ldr	r3, [r3, #0]
- 80075a0:	4926      	ldr	r1, [pc, #152]	@ (800763c <UART_EndRxTransfer+0xc4>)
- 80075a2:	400a      	ands	r2, r1
- 80075a4:	601a      	str	r2, [r3, #0]
- 80075a6:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
- 80075a8:	61fb      	str	r3, [r7, #28]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80075aa:	69fb      	ldr	r3, [r7, #28]
- 80075ac:	f383 8810 	msr	PRIMASK, r3
-}
- 80075b0:	46c0      	nop			@ (mov r8, r8)
+ 80044d4:	6801      	ldr	r1, [r0, #0]
+ 80044d6:	4d13      	ldr	r5, [pc, #76]	@ (8004524 <UART_EndRxTransfer+0x5c>)
+ 80044d8:	680b      	ldr	r3, [r1, #0]
+ 80044da:	402b      	ands	r3, r5
+ 80044dc:	600b      	str	r3, [r1, #0]
+ 80044de:	f384 8810 	msr	PRIMASK, r4
   __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 80075b2:	f3ef 8310 	mrs	r3, PRIMASK
- 80075b6:	623b      	str	r3, [r7, #32]
-  return(result);
- 80075b8:	6a3b      	ldr	r3, [r7, #32]
+ 80044e2:	f3ef 8110 	mrs	r1, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 80044e6:	f382 8810 	msr	PRIMASK, r2
   ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
- 80075ba:	633b      	str	r3, [r7, #48]	@ 0x30
- 80075bc:	2301      	movs	r3, #1
- 80075be:	627b      	str	r3, [r7, #36]	@ 0x24
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80075c0:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 80075c2:	f383 8810 	msr	PRIMASK, r3
-}
- 80075c6:	46c0      	nop			@ (mov r8, r8)
- 80075c8:	687b      	ldr	r3, [r7, #4]
- 80075ca:	681b      	ldr	r3, [r3, #0]
- 80075cc:	689a      	ldr	r2, [r3, #8]
- 80075ce:	687b      	ldr	r3, [r7, #4]
- 80075d0:	681b      	ldr	r3, [r3, #0]
- 80075d2:	491b      	ldr	r1, [pc, #108]	@ (8007640 <UART_EndRxTransfer+0xc8>)
- 80075d4:	400a      	ands	r2, r1
- 80075d6:	609a      	str	r2, [r3, #8]
- 80075d8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
- 80075da:	62bb      	str	r3, [r7, #40]	@ 0x28
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80075dc:	6abb      	ldr	r3, [r7, #40]	@ 0x28
- 80075de:	f383 8810 	msr	PRIMASK, r3
-}
- 80075e2:	46c0      	nop			@ (mov r8, r8)
+ 80044ea:	6802      	ldr	r2, [r0, #0]
+ 80044ec:	4c0e      	ldr	r4, [pc, #56]	@ (8004528 <UART_EndRxTransfer+0x60>)
+ 80044ee:	6893      	ldr	r3, [r2, #8]
+ 80044f0:	4023      	ands	r3, r4
+ 80044f2:	6093      	str	r3, [r2, #8]
+ 80044f4:	f381 8810 	msr	PRIMASK, r1
 
   /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */
   if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- 80075e4:	687b      	ldr	r3, [r7, #4]
- 80075e6:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
- 80075e8:	2b01      	cmp	r3, #1
- 80075ea:	d118      	bne.n	800761e <UART_EndRxTransfer+0xa6>
+ 80044f8:	6ec3      	ldr	r3, [r0, #108]	@ 0x6c
+ 80044fa:	2b01      	cmp	r3, #1
+ 80044fc:	d10a      	bne.n	8004514 <UART_EndRxTransfer+0x4c>
   __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 80075ec:	f3ef 8310 	mrs	r3, PRIMASK
- 80075f0:	60bb      	str	r3, [r7, #8]
-  return(result);
- 80075f2:	68bb      	ldr	r3, [r7, #8]
+ 80044fe:	f3ef 8110 	mrs	r1, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004502:	f383 8810 	msr	PRIMASK, r3
   {
     ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- 80075f4:	62fb      	str	r3, [r7, #44]	@ 0x2c
- 80075f6:	2301      	movs	r3, #1
- 80075f8:	60fb      	str	r3, [r7, #12]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80075fa:	68fb      	ldr	r3, [r7, #12]
- 80075fc:	f383 8810 	msr	PRIMASK, r3
-}
- 8007600:	46c0      	nop			@ (mov r8, r8)
- 8007602:	687b      	ldr	r3, [r7, #4]
- 8007604:	681b      	ldr	r3, [r3, #0]
- 8007606:	681a      	ldr	r2, [r3, #0]
- 8007608:	687b      	ldr	r3, [r7, #4]
- 800760a:	681b      	ldr	r3, [r3, #0]
- 800760c:	2110      	movs	r1, #16
- 800760e:	438a      	bics	r2, r1
- 8007610:	601a      	str	r2, [r3, #0]
- 8007612:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
- 8007614:	613b      	str	r3, [r7, #16]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8007616:	693b      	ldr	r3, [r7, #16]
- 8007618:	f383 8810 	msr	PRIMASK, r3
-}
- 800761c:	46c0      	nop			@ (mov r8, r8)
+ 8004506:	2410      	movs	r4, #16
+ 8004508:	6802      	ldr	r2, [r0, #0]
+ 800450a:	6813      	ldr	r3, [r2, #0]
+ 800450c:	43a3      	bics	r3, r4
+ 800450e:	6013      	str	r3, [r2, #0]
+ 8004510:	f381 8810 	msr	PRIMASK, r1
   }
 
   /* At end of Rx process, restore huart->RxState to Ready */
   huart->RxState = HAL_UART_STATE_READY;
- 800761e:	687b      	ldr	r3, [r7, #4]
- 8007620:	228c      	movs	r2, #140	@ 0x8c
- 8007622:	2120      	movs	r1, #32
- 8007624:	5099      	str	r1, [r3, r2]
+ 8004514:	0003      	movs	r3, r0
+ 8004516:	2220      	movs	r2, #32
+ 8004518:	338c      	adds	r3, #140	@ 0x8c
+ 800451a:	601a      	str	r2, [r3, #0]
   huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
- 8007626:	687b      	ldr	r3, [r7, #4]
- 8007628:	2200      	movs	r2, #0
- 800762a:	66da      	str	r2, [r3, #108]	@ 0x6c
+ 800451c:	2300      	movs	r3, #0
+ 800451e:	66c3      	str	r3, [r0, #108]	@ 0x6c
 
   /* Reset RxIsr function pointer */
   huart->RxISR = NULL;
- 800762c:	687b      	ldr	r3, [r7, #4]
- 800762e:	2200      	movs	r2, #0
- 8007630:	675a      	str	r2, [r3, #116]	@ 0x74
+ 8004520:	6743      	str	r3, [r0, #116]	@ 0x74
 }
- 8007632:	46c0      	nop			@ (mov r8, r8)
- 8007634:	46bd      	mov	sp, r7
- 8007636:	b00e      	add	sp, #56	@ 0x38
- 8007638:	bd80      	pop	{r7, pc}
- 800763a:	46c0      	nop			@ (mov r8, r8)
- 800763c:	fffffedf 	.word	0xfffffedf
- 8007640:	effffffe 	.word	0xeffffffe
+ 8004522:	bd30      	pop	{r4, r5, pc}
+ 8004524:	fffffedf 	.word	0xfffffedf
+ 8004528:	effffffe 	.word	0xeffffffe
 
-08007644 <UART_DMAReceiveCplt>:
-  * @brief DMA UART receive process complete callback.
-  * @param hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
- 8007644:	b580      	push	{r7, lr}
- 8007646:	b094      	sub	sp, #80	@ 0x50
- 8007648:	af00      	add	r7, sp, #0
- 800764a:	6078      	str	r0, [r7, #4]
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- 800764c:	687b      	ldr	r3, [r7, #4]
- 800764e:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8007650:	64fb      	str	r3, [r7, #76]	@ 0x4c
+0800452c <HAL_UART_TxCpltCallback>:
+__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
+ 800452c:	4770      	bx	lr
 
-  /* DMA Normal mode */
-  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
- 8007652:	687b      	ldr	r3, [r7, #4]
- 8007654:	681b      	ldr	r3, [r3, #0]
- 8007656:	681b      	ldr	r3, [r3, #0]
- 8007658:	2220      	movs	r2, #32
- 800765a:	4013      	ands	r3, r2
- 800765c:	d16f      	bne.n	800773e <UART_DMAReceiveCplt+0xfa>
-  {
-    huart->RxXferCount = 0U;
- 800765e:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8007660:	225e      	movs	r2, #94	@ 0x5e
- 8007662:	2100      	movs	r1, #0
- 8007664:	5299      	strh	r1, [r3, r2]
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 8007666:	f3ef 8310 	mrs	r3, PRIMASK
- 800766a:	617b      	str	r3, [r7, #20]
-  return(result);
- 800766c:	697b      	ldr	r3, [r7, #20]
+0800452e <HAL_UART_RxCpltCallback>:
+__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
+ 800452e:	4770      	bx	lr
 
-    /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
- 800766e:	64bb      	str	r3, [r7, #72]	@ 0x48
- 8007670:	2301      	movs	r3, #1
- 8007672:	61bb      	str	r3, [r7, #24]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8007674:	69bb      	ldr	r3, [r7, #24]
- 8007676:	f383 8810 	msr	PRIMASK, r3
-}
- 800767a:	46c0      	nop			@ (mov r8, r8)
- 800767c:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 800767e:	681b      	ldr	r3, [r3, #0]
- 8007680:	681a      	ldr	r2, [r3, #0]
- 8007682:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8007684:	681b      	ldr	r3, [r3, #0]
- 8007686:	4948      	ldr	r1, [pc, #288]	@ (80077a8 <UART_DMAReceiveCplt+0x164>)
- 8007688:	400a      	ands	r2, r1
- 800768a:	601a      	str	r2, [r3, #0]
- 800768c:	6cbb      	ldr	r3, [r7, #72]	@ 0x48
- 800768e:	61fb      	str	r3, [r7, #28]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8007690:	69fb      	ldr	r3, [r7, #28]
- 8007692:	f383 8810 	msr	PRIMASK, r3
-}
- 8007696:	46c0      	nop			@ (mov r8, r8)
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 8007698:	f3ef 8310 	mrs	r3, PRIMASK
- 800769c:	623b      	str	r3, [r7, #32]
-  return(result);
- 800769e:	6a3b      	ldr	r3, [r7, #32]
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
- 80076a0:	647b      	str	r3, [r7, #68]	@ 0x44
- 80076a2:	2301      	movs	r3, #1
- 80076a4:	627b      	str	r3, [r7, #36]	@ 0x24
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80076a6:	6a7b      	ldr	r3, [r7, #36]	@ 0x24
- 80076a8:	f383 8810 	msr	PRIMASK, r3
-}
- 80076ac:	46c0      	nop			@ (mov r8, r8)
- 80076ae:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 80076b0:	681b      	ldr	r3, [r3, #0]
- 80076b2:	689a      	ldr	r2, [r3, #8]
- 80076b4:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 80076b6:	681b      	ldr	r3, [r3, #0]
- 80076b8:	2101      	movs	r1, #1
- 80076ba:	438a      	bics	r2, r1
- 80076bc:	609a      	str	r2, [r3, #8]
- 80076be:	6c7b      	ldr	r3, [r7, #68]	@ 0x44
- 80076c0:	62bb      	str	r3, [r7, #40]	@ 0x28
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80076c2:	6abb      	ldr	r3, [r7, #40]	@ 0x28
- 80076c4:	f383 8810 	msr	PRIMASK, r3
-}
- 80076c8:	46c0      	nop			@ (mov r8, r8)
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 80076ca:	f3ef 8310 	mrs	r3, PRIMASK
- 80076ce:	62fb      	str	r3, [r7, #44]	@ 0x2c
-  return(result);
- 80076d0:	6afb      	ldr	r3, [r7, #44]	@ 0x2c
+08004530 <HAL_UART_RxHalfCpltCallback>:
+__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
+ 8004530:	4770      	bx	lr
 
-    /* Disable the DMA transfer for the receiver request by resetting the DMAR bit
-       in the UART CR3 register */
-    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
- 80076d2:	643b      	str	r3, [r7, #64]	@ 0x40
- 80076d4:	2301      	movs	r3, #1
- 80076d6:	633b      	str	r3, [r7, #48]	@ 0x30
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80076d8:	6b3b      	ldr	r3, [r7, #48]	@ 0x30
- 80076da:	f383 8810 	msr	PRIMASK, r3
-}
- 80076de:	46c0      	nop			@ (mov r8, r8)
- 80076e0:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 80076e2:	681b      	ldr	r3, [r3, #0]
- 80076e4:	689a      	ldr	r2, [r3, #8]
- 80076e6:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 80076e8:	681b      	ldr	r3, [r3, #0]
- 80076ea:	2140      	movs	r1, #64	@ 0x40
- 80076ec:	438a      	bics	r2, r1
- 80076ee:	609a      	str	r2, [r3, #8]
- 80076f0:	6c3b      	ldr	r3, [r7, #64]	@ 0x40
- 80076f2:	637b      	str	r3, [r7, #52]	@ 0x34
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 80076f4:	6b7b      	ldr	r3, [r7, #52]	@ 0x34
- 80076f6:	f383 8810 	msr	PRIMASK, r3
-}
- 80076fa:	46c0      	nop			@ (mov r8, r8)
-
-    /* At end of Rx process, restore huart->RxState to Ready */
-    huart->RxState = HAL_UART_STATE_READY;
- 80076fc:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 80076fe:	228c      	movs	r2, #140	@ 0x8c
- 8007700:	2120      	movs	r1, #32
- 8007702:	5099      	str	r1, [r3, r2]
-
-    /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */
-    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- 8007704:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8007706:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
- 8007708:	2b01      	cmp	r3, #1
- 800770a:	d118      	bne.n	800773e <UART_DMAReceiveCplt+0xfa>
-  __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 800770c:	f3ef 8310 	mrs	r3, PRIMASK
- 8007710:	60bb      	str	r3, [r7, #8]
-  return(result);
- 8007712:	68bb      	ldr	r3, [r7, #8]
-    {
-      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- 8007714:	63fb      	str	r3, [r7, #60]	@ 0x3c
- 8007716:	2301      	movs	r3, #1
- 8007718:	60fb      	str	r3, [r7, #12]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 800771a:	68fb      	ldr	r3, [r7, #12]
- 800771c:	f383 8810 	msr	PRIMASK, r3
-}
- 8007720:	46c0      	nop			@ (mov r8, r8)
- 8007722:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8007724:	681b      	ldr	r3, [r3, #0]
- 8007726:	681a      	ldr	r2, [r3, #0]
- 8007728:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 800772a:	681b      	ldr	r3, [r3, #0]
- 800772c:	2110      	movs	r1, #16
- 800772e:	438a      	bics	r2, r1
- 8007730:	601a      	str	r2, [r3, #0]
- 8007732:	6bfb      	ldr	r3, [r7, #60]	@ 0x3c
- 8007734:	613b      	str	r3, [r7, #16]
-  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8007736:	693b      	ldr	r3, [r7, #16]
- 8007738:	f383 8810 	msr	PRIMASK, r3
-}
- 800773c:	46c0      	nop			@ (mov r8, r8)
-    }
-  }
-
-  /* Initialize type of RxEvent that correspond to RxEvent callback execution;
-     In this case, Rx Event type is Transfer Complete */
-  huart->RxEventType = HAL_UART_RXEVENT_TC;
- 800773e:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8007740:	2200      	movs	r2, #0
- 8007742:	671a      	str	r2, [r3, #112]	@ 0x70
-
-  /* Check current reception Mode :
-     If Reception till IDLE event has been selected : use Rx Event callback */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- 8007744:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8007746:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
- 8007748:	2b01      	cmp	r3, #1
- 800774a:	d124      	bne.n	8007796 <UART_DMAReceiveCplt+0x152>
-  {
-    huart->RxXferCount = 0;
- 800774c:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 800774e:	225e      	movs	r2, #94	@ 0x5e
- 8007750:	2100      	movs	r1, #0
- 8007752:	5299      	strh	r1, [r3, r2]
-
-    /* Check current nb of data still to be received on DMA side.
-       DMA Normal mode, remaining nb of data will be 0
-       DMA Circular mode, remaining nb of data is reset to RxXferSize */
-    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
- 8007754:	687b      	ldr	r3, [r7, #4]
- 8007756:	681b      	ldr	r3, [r3, #0]
- 8007758:	685a      	ldr	r2, [r3, #4]
- 800775a:	213a      	movs	r1, #58	@ 0x3a
- 800775c:	187b      	adds	r3, r7, r1
- 800775e:	801a      	strh	r2, [r3, #0]
-    if (nb_remaining_rx_data < huart->RxXferSize)
- 8007760:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8007762:	225c      	movs	r2, #92	@ 0x5c
- 8007764:	5a9b      	ldrh	r3, [r3, r2]
- 8007766:	187a      	adds	r2, r7, r1
- 8007768:	8812      	ldrh	r2, [r2, #0]
- 800776a:	429a      	cmp	r2, r3
- 800776c:	d204      	bcs.n	8007778 <UART_DMAReceiveCplt+0x134>
-    {
-      /* Update nb of remaining data */
-      huart->RxXferCount = nb_remaining_rx_data;
- 800776e:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8007770:	187a      	adds	r2, r7, r1
- 8007772:	215e      	movs	r1, #94	@ 0x5e
- 8007774:	8812      	ldrh	r2, [r2, #0]
- 8007776:	525a      	strh	r2, [r3, r1]
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx Event callback*/
-    huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
-#else
-    /*Call legacy weak Rx Event callback*/
-    HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
- 8007778:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 800777a:	225c      	movs	r2, #92	@ 0x5c
- 800777c:	5a9a      	ldrh	r2, [r3, r2]
- 800777e:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8007780:	215e      	movs	r1, #94	@ 0x5e
- 8007782:	5a5b      	ldrh	r3, [r3, r1]
- 8007784:	b29b      	uxth	r3, r3
- 8007786:	1ad3      	subs	r3, r2, r3
- 8007788:	b29a      	uxth	r2, r3
- 800778a:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 800778c:	0011      	movs	r1, r2
- 800778e:	0018      	movs	r0, r3
- 8007790:	f7fa f99c 	bl	8001acc <HAL_UARTEx_RxEventCallback>
-#else
-    /*Call legacy weak Rx complete callback*/
-    HAL_UART_RxCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-}
- 8007794:	e003      	b.n	800779e <UART_DMAReceiveCplt+0x15a>
-    HAL_UART_RxCpltCallback(huart);
- 8007796:	6cfb      	ldr	r3, [r7, #76]	@ 0x4c
- 8007798:	0018      	movs	r0, r3
- 800779a:	f7ff faa3 	bl	8006ce4 <HAL_UART_RxCpltCallback>
-}
- 800779e:	46c0      	nop			@ (mov r8, r8)
- 80077a0:	46bd      	mov	sp, r7
- 80077a2:	b014      	add	sp, #80	@ 0x50
- 80077a4:	bd80      	pop	{r7, pc}
- 80077a6:	46c0      	nop			@ (mov r8, r8)
- 80077a8:	fffffeff 	.word	0xfffffeff
-
-080077ac <UART_DMARxHalfCplt>:
-  * @brief DMA UART receive process half complete callback.
-  * @param hdma DMA handle.
-  * @retval None
-  */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
- 80077ac:	b580      	push	{r7, lr}
- 80077ae:	b084      	sub	sp, #16
- 80077b0:	af00      	add	r7, sp, #0
- 80077b2:	6078      	str	r0, [r7, #4]
-  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- 80077b4:	687b      	ldr	r3, [r7, #4]
- 80077b6:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 80077b8:	60fb      	str	r3, [r7, #12]
-
-  /* Initialize type of RxEvent that correspond to RxEvent callback execution;
-     In this case, Rx Event type is Half Transfer */
-  huart->RxEventType = HAL_UART_RXEVENT_HT;
- 80077ba:	68fb      	ldr	r3, [r7, #12]
- 80077bc:	2201      	movs	r2, #1
- 80077be:	671a      	str	r2, [r3, #112]	@ 0x70
-
-  /* Check current reception Mode :
-     If Reception till IDLE event has been selected : use Rx Event callback */
-  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- 80077c0:	68fb      	ldr	r3, [r7, #12]
- 80077c2:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
- 80077c4:	2b01      	cmp	r3, #1
- 80077c6:	d128      	bne.n	800781a <UART_DMARxHalfCplt+0x6e>
-  {
-    huart->RxXferCount = huart->RxXferSize / 2U;
- 80077c8:	68fb      	ldr	r3, [r7, #12]
- 80077ca:	225c      	movs	r2, #92	@ 0x5c
- 80077cc:	5a9b      	ldrh	r3, [r3, r2]
- 80077ce:	085b      	lsrs	r3, r3, #1
- 80077d0:	b299      	uxth	r1, r3
- 80077d2:	68fb      	ldr	r3, [r7, #12]
- 80077d4:	225e      	movs	r2, #94	@ 0x5e
- 80077d6:	5299      	strh	r1, [r3, r2]
-
-    /* Check current nb of data still to be received on DMA side. */
-    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
- 80077d8:	687b      	ldr	r3, [r7, #4]
- 80077da:	681b      	ldr	r3, [r3, #0]
- 80077dc:	685a      	ldr	r2, [r3, #4]
- 80077de:	210a      	movs	r1, #10
- 80077e0:	187b      	adds	r3, r7, r1
- 80077e2:	801a      	strh	r2, [r3, #0]
-    if (nb_remaining_rx_data <= huart->RxXferSize)
- 80077e4:	68fb      	ldr	r3, [r7, #12]
- 80077e6:	225c      	movs	r2, #92	@ 0x5c
- 80077e8:	5a9b      	ldrh	r3, [r3, r2]
- 80077ea:	187a      	adds	r2, r7, r1
- 80077ec:	8812      	ldrh	r2, [r2, #0]
- 80077ee:	429a      	cmp	r2, r3
- 80077f0:	d804      	bhi.n	80077fc <UART_DMARxHalfCplt+0x50>
-    {
-      /* Update nb of remaining data */
-      huart->RxXferCount = nb_remaining_rx_data;
- 80077f2:	68fb      	ldr	r3, [r7, #12]
- 80077f4:	187a      	adds	r2, r7, r1
- 80077f6:	215e      	movs	r1, #94	@ 0x5e
- 80077f8:	8812      	ldrh	r2, [r2, #0]
- 80077fa:	525a      	strh	r2, [r3, r1]
-#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
-    /*Call registered Rx Event callback*/
-    huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
-#else
-    /*Call legacy weak Rx Event callback*/
-    HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
- 80077fc:	68fb      	ldr	r3, [r7, #12]
- 80077fe:	225c      	movs	r2, #92	@ 0x5c
- 8007800:	5a9a      	ldrh	r2, [r3, r2]
- 8007802:	68fb      	ldr	r3, [r7, #12]
- 8007804:	215e      	movs	r1, #94	@ 0x5e
- 8007806:	5a5b      	ldrh	r3, [r3, r1]
- 8007808:	b29b      	uxth	r3, r3
- 800780a:	1ad3      	subs	r3, r2, r3
- 800780c:	b29a      	uxth	r2, r3
- 800780e:	68fb      	ldr	r3, [r7, #12]
- 8007810:	0011      	movs	r1, r2
- 8007812:	0018      	movs	r0, r3
- 8007814:	f7fa f95a 	bl	8001acc <HAL_UARTEx_RxEventCallback>
-#else
-    /*Call legacy weak Rx Half complete callback*/
-    HAL_UART_RxHalfCpltCallback(huart);
-#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
-  }
-}
- 8007818:	e003      	b.n	8007822 <UART_DMARxHalfCplt+0x76>
-    HAL_UART_RxHalfCpltCallback(huart);
- 800781a:	68fb      	ldr	r3, [r7, #12]
- 800781c:	0018      	movs	r0, r3
- 800781e:	f7ff fa69 	bl	8006cf4 <HAL_UART_RxHalfCpltCallback>
-}
- 8007822:	46c0      	nop			@ (mov r8, r8)
- 8007824:	46bd      	mov	sp, r7
- 8007826:	b004      	add	sp, #16
- 8007828:	bd80      	pop	{r7, pc}
-
-0800782a <UART_DMAError>:
+08004532 <UART_DMAError>:
   * @brief DMA UART communication error callback.
   * @param hdma DMA handle.
   * @retval None
   */
 static void UART_DMAError(DMA_HandleTypeDef *hdma)
 {
- 800782a:	b580      	push	{r7, lr}
- 800782c:	b086      	sub	sp, #24
- 800782e:	af00      	add	r7, sp, #0
- 8007830:	6078      	str	r0, [r7, #4]
+ 8004532:	b570      	push	{r4, r5, r6, lr}
   UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
- 8007832:	687b      	ldr	r3, [r7, #4]
- 8007834:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 8007836:	617b      	str	r3, [r7, #20]
+ 8004534:	6a84      	ldr	r4, [r0, #40]	@ 0x28
 
   const HAL_UART_StateTypeDef gstate = huart->gState;
- 8007838:	697b      	ldr	r3, [r7, #20]
- 800783a:	2288      	movs	r2, #136	@ 0x88
- 800783c:	589b      	ldr	r3, [r3, r2]
- 800783e:	613b      	str	r3, [r7, #16]
+ 8004536:	0023      	movs	r3, r4
+ 8004538:	3388      	adds	r3, #136	@ 0x88
+ 800453a:	681a      	ldr	r2, [r3, #0]
   const HAL_UART_StateTypeDef rxstate = huart->RxState;
- 8007840:	697b      	ldr	r3, [r7, #20]
- 8007842:	228c      	movs	r2, #140	@ 0x8c
- 8007844:	589b      	ldr	r3, [r3, r2]
- 8007846:	60fb      	str	r3, [r7, #12]
+ 800453c:	685d      	ldr	r5, [r3, #4]
 
   /* Stop UART DMA Tx request if ongoing */
   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) &&
- 8007848:	697b      	ldr	r3, [r7, #20]
- 800784a:	681b      	ldr	r3, [r3, #0]
- 800784c:	689b      	ldr	r3, [r3, #8]
- 800784e:	2280      	movs	r2, #128	@ 0x80
- 8007850:	4013      	ands	r3, r2
- 8007852:	2b80      	cmp	r3, #128	@ 0x80
- 8007854:	d10a      	bne.n	800786c <UART_DMAError+0x42>
- 8007856:	693b      	ldr	r3, [r7, #16]
- 8007858:	2b21      	cmp	r3, #33	@ 0x21
- 800785a:	d107      	bne.n	800786c <UART_DMAError+0x42>
+ 800453e:	6823      	ldr	r3, [r4, #0]
+ 8004540:	689b      	ldr	r3, [r3, #8]
+ 8004542:	061b      	lsls	r3, r3, #24
+ 8004544:	d508      	bpl.n	8004558 <UART_DMAError+0x26>
+ 8004546:	2a21      	cmp	r2, #33	@ 0x21
+ 8004548:	d106      	bne.n	8004558 <UART_DMAError+0x26>
       (gstate == HAL_UART_STATE_BUSY_TX))
   {
     huart->TxXferCount = 0U;
- 800785c:	697b      	ldr	r3, [r7, #20]
- 800785e:	2256      	movs	r2, #86	@ 0x56
- 8007860:	2100      	movs	r1, #0
- 8007862:	5299      	strh	r1, [r3, r2]
+ 800454a:	0023      	movs	r3, r4
+ 800454c:	2200      	movs	r2, #0
+ 800454e:	3356      	adds	r3, #86	@ 0x56
     UART_EndTxTransfer(huart);
- 8007864:	697b      	ldr	r3, [r7, #20]
- 8007866:	0018      	movs	r0, r3
- 8007868:	f7ff fe46 	bl	80074f8 <UART_EndTxTransfer>
+ 8004550:	0020      	movs	r0, r4
+    huart->TxXferCount = 0U;
+ 8004552:	801a      	strh	r2, [r3, #0]
+    UART_EndTxTransfer(huart);
+ 8004554:	f7ff ff9a 	bl	800448c <UART_EndTxTransfer>
   }
 
   /* Stop UART DMA Rx request if ongoing */
   if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) &&
- 800786c:	697b      	ldr	r3, [r7, #20]
- 800786e:	681b      	ldr	r3, [r3, #0]
- 8007870:	689b      	ldr	r3, [r3, #8]
- 8007872:	2240      	movs	r2, #64	@ 0x40
- 8007874:	4013      	ands	r3, r2
- 8007876:	2b40      	cmp	r3, #64	@ 0x40
- 8007878:	d10a      	bne.n	8007890 <UART_DMAError+0x66>
- 800787a:	68fb      	ldr	r3, [r7, #12]
- 800787c:	2b22      	cmp	r3, #34	@ 0x22
- 800787e:	d107      	bne.n	8007890 <UART_DMAError+0x66>
+ 8004558:	6823      	ldr	r3, [r4, #0]
+ 800455a:	689b      	ldr	r3, [r3, #8]
+ 800455c:	065b      	lsls	r3, r3, #25
+ 800455e:	d508      	bpl.n	8004572 <UART_DMAError+0x40>
+ 8004560:	2d22      	cmp	r5, #34	@ 0x22
+ 8004562:	d106      	bne.n	8004572 <UART_DMAError+0x40>
       (rxstate == HAL_UART_STATE_BUSY_RX))
   {
     huart->RxXferCount = 0U;
- 8007880:	697b      	ldr	r3, [r7, #20]
- 8007882:	225e      	movs	r2, #94	@ 0x5e
- 8007884:	2100      	movs	r1, #0
- 8007886:	5299      	strh	r1, [r3, r2]
+ 8004564:	0023      	movs	r3, r4
+ 8004566:	2200      	movs	r2, #0
+ 8004568:	335e      	adds	r3, #94	@ 0x5e
     UART_EndRxTransfer(huart);
- 8007888:	697b      	ldr	r3, [r7, #20]
- 800788a:	0018      	movs	r0, r3
- 800788c:	f7ff fe74 	bl	8007578 <UART_EndRxTransfer>
+ 800456a:	0020      	movs	r0, r4
+    huart->RxXferCount = 0U;
+ 800456c:	801a      	strh	r2, [r3, #0]
+    UART_EndRxTransfer(huart);
+ 800456e:	f7ff ffab 	bl	80044c8 <UART_EndRxTransfer>
   }
 
   huart->ErrorCode |= HAL_UART_ERROR_DMA;
- 8007890:	697b      	ldr	r3, [r7, #20]
- 8007892:	2290      	movs	r2, #144	@ 0x90
- 8007894:	589b      	ldr	r3, [r3, r2]
- 8007896:	2210      	movs	r2, #16
- 8007898:	431a      	orrs	r2, r3
- 800789a:	697b      	ldr	r3, [r7, #20]
- 800789c:	2190      	movs	r1, #144	@ 0x90
- 800789e:	505a      	str	r2, [r3, r1]
+ 8004572:	0022      	movs	r2, r4
+ 8004574:	2310      	movs	r3, #16
+ 8004576:	3290      	adds	r2, #144	@ 0x90
+ 8004578:	6811      	ldr	r1, [r2, #0]
 #if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
   /*Call registered error callback*/
   huart->ErrorCallback(huart);
 #else
   /*Call legacy weak error callback*/
   HAL_UART_ErrorCallback(huart);
- 80078a0:	697b      	ldr	r3, [r7, #20]
- 80078a2:	0018      	movs	r0, r3
- 80078a4:	f7ff fa2e 	bl	8006d04 <HAL_UART_ErrorCallback>
+ 800457a:	0020      	movs	r0, r4
+  huart->ErrorCode |= HAL_UART_ERROR_DMA;
+ 800457c:	430b      	orrs	r3, r1
+ 800457e:	6013      	str	r3, [r2, #0]
+  HAL_UART_ErrorCallback(huart);
+ 8004580:	f7fc fa6a 	bl	8000a58 <HAL_UART_ErrorCallback>
 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 }
- 80078a8:	46c0      	nop			@ (mov r8, r8)
- 80078aa:	46bd      	mov	sp, r7
- 80078ac:	b006      	add	sp, #24
- 80078ae:	bd80      	pop	{r7, pc}
+ 8004584:	bd70      	pop	{r4, r5, r6, pc}
 
-080078b0 <HAL_RS485Ex_Init>:
-  *       oversampling rate).
-  * @retval HAL status
+08004586 <UART_DMAAbortOnError>:
+  * @param  hdma DMA handle.
+  * @retval None
   */
-HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,
-                                   uint32_t DeassertionTime)
+static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
 {
- 80078b0:	b580      	push	{r7, lr}
- 80078b2:	b086      	sub	sp, #24
- 80078b4:	af00      	add	r7, sp, #0
- 80078b6:	60f8      	str	r0, [r7, #12]
- 80078b8:	60b9      	str	r1, [r7, #8]
- 80078ba:	607a      	str	r2, [r7, #4]
- 80078bc:	603b      	str	r3, [r7, #0]
-  uint32_t temp;
-
-  /* Check the UART handle allocation */
-  if (huart == NULL)
- 80078be:	68fb      	ldr	r3, [r7, #12]
- 80078c0:	2b00      	cmp	r3, #0
- 80078c2:	d101      	bne.n	80078c8 <HAL_RS485Ex_Init+0x18>
-  {
-    return HAL_ERROR;
- 80078c4:	2301      	movs	r3, #1
- 80078c6:	e05d      	b.n	8007984 <HAL_RS485Ex_Init+0xd4>
-  assert_param(IS_UART_ASSERTIONTIME(AssertionTime));
-
-  /* Check the Driver Enable deassertion time */
-  assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime));
-
-  if (huart->gState == HAL_UART_STATE_RESET)
- 80078c8:	68fb      	ldr	r3, [r7, #12]
- 80078ca:	2288      	movs	r2, #136	@ 0x88
- 80078cc:	589b      	ldr	r3, [r3, r2]
- 80078ce:	2b00      	cmp	r3, #0
- 80078d0:	d107      	bne.n	80078e2 <HAL_RS485Ex_Init+0x32>
-  {
-    /* Allocate lock resource and initialize it */
-    huart->Lock = HAL_UNLOCKED;
- 80078d2:	68fb      	ldr	r3, [r7, #12]
- 80078d4:	2284      	movs	r2, #132	@ 0x84
- 80078d6:	2100      	movs	r1, #0
- 80078d8:	5499      	strb	r1, [r3, r2]
-
-    /* Init the low level hardware */
-    huart->MspInitCallback(huart);
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 8004586:	6a80      	ldr	r0, [r0, #40]	@ 0x28
+  huart->RxXferCount = 0U;
+ 8004588:	2200      	movs	r2, #0
+ 800458a:	0003      	movs	r3, r0
+{
+ 800458c:	b510      	push	{r4, lr}
+  huart->RxXferCount = 0U;
+ 800458e:	335e      	adds	r3, #94	@ 0x5e
+ 8004590:	801a      	strh	r2, [r3, #0]
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered error callback*/
+  huart->ErrorCallback(huart);
 #else
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX */
-    HAL_UART_MspInit(huart);
- 80078da:	68fb      	ldr	r3, [r7, #12]
- 80078dc:	0018      	movs	r0, r3
- 80078de:	f7fc f9f7 	bl	8003cd0 <HAL_UART_MspInit>
-#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */
-  }
-
-  huart->gState = HAL_UART_STATE_BUSY;
- 80078e2:	68fb      	ldr	r3, [r7, #12]
- 80078e4:	2288      	movs	r2, #136	@ 0x88
- 80078e6:	2124      	movs	r1, #36	@ 0x24
- 80078e8:	5099      	str	r1, [r3, r2]
-
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
- 80078ea:	68fb      	ldr	r3, [r7, #12]
- 80078ec:	681b      	ldr	r3, [r3, #0]
- 80078ee:	681a      	ldr	r2, [r3, #0]
- 80078f0:	68fb      	ldr	r3, [r7, #12]
- 80078f2:	681b      	ldr	r3, [r3, #0]
- 80078f4:	2101      	movs	r1, #1
- 80078f6:	438a      	bics	r2, r1
- 80078f8:	601a      	str	r2, [r3, #0]
-
-  /* Perform advanced settings configuration */
-  /* For some items, configuration requires to be done prior TE and RE bits are set */
-  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
- 80078fa:	68fb      	ldr	r3, [r7, #12]
- 80078fc:	6a9b      	ldr	r3, [r3, #40]	@ 0x28
- 80078fe:	2b00      	cmp	r3, #0
- 8007900:	d003      	beq.n	800790a <HAL_RS485Ex_Init+0x5a>
-  {
-    UART_AdvFeatureConfig(huart);
- 8007902:	68fb      	ldr	r3, [r7, #12]
- 8007904:	0018      	movs	r0, r3
- 8007906:	f7ff fb83 	bl	8007010 <UART_AdvFeatureConfig>
-  }
-
-  /* Set the UART Communication parameters */
-  if (UART_SetConfig(huart) == HAL_ERROR)
- 800790a:	68fb      	ldr	r3, [r7, #12]
- 800790c:	0018      	movs	r0, r3
- 800790e:	f7ff fa01 	bl	8006d14 <UART_SetConfig>
- 8007912:	0003      	movs	r3, r0
- 8007914:	2b01      	cmp	r3, #1
- 8007916:	d101      	bne.n	800791c <HAL_RS485Ex_Init+0x6c>
-  {
-    return HAL_ERROR;
- 8007918:	2301      	movs	r3, #1
- 800791a:	e033      	b.n	8007984 <HAL_RS485Ex_Init+0xd4>
-  }
-
-  /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
-  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
- 800791c:	68fb      	ldr	r3, [r7, #12]
- 800791e:	681b      	ldr	r3, [r3, #0]
- 8007920:	689a      	ldr	r2, [r3, #8]
- 8007922:	68fb      	ldr	r3, [r7, #12]
- 8007924:	681b      	ldr	r3, [r3, #0]
- 8007926:	2180      	movs	r1, #128	@ 0x80
- 8007928:	01c9      	lsls	r1, r1, #7
- 800792a:	430a      	orrs	r2, r1
- 800792c:	609a      	str	r2, [r3, #8]
-
-  /* Set the Driver Enable polarity */
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
- 800792e:	68fb      	ldr	r3, [r7, #12]
- 8007930:	681b      	ldr	r3, [r3, #0]
- 8007932:	689b      	ldr	r3, [r3, #8]
- 8007934:	4a15      	ldr	r2, [pc, #84]	@ (800798c <HAL_RS485Ex_Init+0xdc>)
- 8007936:	4013      	ands	r3, r2
- 8007938:	0019      	movs	r1, r3
- 800793a:	68fb      	ldr	r3, [r7, #12]
- 800793c:	681b      	ldr	r3, [r3, #0]
- 800793e:	68ba      	ldr	r2, [r7, #8]
- 8007940:	430a      	orrs	r2, r1
- 8007942:	609a      	str	r2, [r3, #8]
-
-  /* Set the Driver Enable assertion and deassertion times */
-  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
- 8007944:	687b      	ldr	r3, [r7, #4]
- 8007946:	055b      	lsls	r3, r3, #21
- 8007948:	617b      	str	r3, [r7, #20]
-  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
- 800794a:	683b      	ldr	r3, [r7, #0]
- 800794c:	041b      	lsls	r3, r3, #16
- 800794e:	697a      	ldr	r2, [r7, #20]
- 8007950:	4313      	orrs	r3, r2
- 8007952:	617b      	str	r3, [r7, #20]
-  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
- 8007954:	68fb      	ldr	r3, [r7, #12]
- 8007956:	681b      	ldr	r3, [r3, #0]
- 8007958:	681b      	ldr	r3, [r3, #0]
- 800795a:	4a0d      	ldr	r2, [pc, #52]	@ (8007990 <HAL_RS485Ex_Init+0xe0>)
- 800795c:	4013      	ands	r3, r2
- 800795e:	0019      	movs	r1, r3
- 8007960:	68fb      	ldr	r3, [r7, #12]
- 8007962:	681b      	ldr	r3, [r3, #0]
- 8007964:	697a      	ldr	r2, [r7, #20]
- 8007966:	430a      	orrs	r2, r1
- 8007968:	601a      	str	r2, [r3, #0]
-
-  /* Enable the Peripheral */
-  __HAL_UART_ENABLE(huart);
- 800796a:	68fb      	ldr	r3, [r7, #12]
- 800796c:	681b      	ldr	r3, [r3, #0]
- 800796e:	681a      	ldr	r2, [r3, #0]
- 8007970:	68fb      	ldr	r3, [r7, #12]
- 8007972:	681b      	ldr	r3, [r3, #0]
- 8007974:	2101      	movs	r1, #1
- 8007976:	430a      	orrs	r2, r1
- 8007978:	601a      	str	r2, [r3, #0]
-
-  /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */
-  return (UART_CheckIdleState(huart));
- 800797a:	68fb      	ldr	r3, [r7, #12]
- 800797c:	0018      	movs	r0, r3
- 800797e:	f7ff fbfb 	bl	8007178 <UART_CheckIdleState>
- 8007982:	0003      	movs	r3, r0
+  /*Call legacy weak error callback*/
+  HAL_UART_ErrorCallback(huart);
+ 8004592:	f7fc fa61 	bl	8000a58 <HAL_UART_ErrorCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
 }
- 8007984:	0018      	movs	r0, r3
- 8007986:	46bd      	mov	sp, r7
- 8007988:	b006      	add	sp, #24
- 800798a:	bd80      	pop	{r7, pc}
- 800798c:	ffff7fff 	.word	0xffff7fff
- 8007990:	fc00ffff 	.word	0xfc00ffff
+ 8004596:	bd10      	pop	{r4, pc}
 
-08007994 <HAL_UARTEx_DisableFifoMode>:
-  * @brief  Disable the FIFO mode.
-  * @param huart      UART handle.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart)
+08004598 <HAL_UART_IRQHandler>:
 {
- 8007994:	b580      	push	{r7, lr}
- 8007996:	b084      	sub	sp, #16
- 8007998:	af00      	add	r7, sp, #0
- 800799a:	6078      	str	r0, [r7, #4]
-
-  /* Check parameters */
-  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
- 800799c:	687b      	ldr	r3, [r7, #4]
- 800799e:	2284      	movs	r2, #132	@ 0x84
- 80079a0:	5c9b      	ldrb	r3, [r3, r2]
- 80079a2:	2b01      	cmp	r3, #1
- 80079a4:	d101      	bne.n	80079aa <HAL_UARTEx_DisableFifoMode+0x16>
- 80079a6:	2302      	movs	r3, #2
- 80079a8:	e027      	b.n	80079fa <HAL_UARTEx_DisableFifoMode+0x66>
- 80079aa:	687b      	ldr	r3, [r7, #4]
- 80079ac:	2284      	movs	r2, #132	@ 0x84
- 80079ae:	2101      	movs	r1, #1
- 80079b0:	5499      	strb	r1, [r3, r2]
-
-  huart->gState = HAL_UART_STATE_BUSY;
- 80079b2:	687b      	ldr	r3, [r7, #4]
- 80079b4:	2288      	movs	r2, #136	@ 0x88
- 80079b6:	2124      	movs	r1, #36	@ 0x24
- 80079b8:	5099      	str	r1, [r3, r2]
-
-  /* Save actual UART configuration */
-  tmpcr1 = READ_REG(huart->Instance->CR1);
- 80079ba:	687b      	ldr	r3, [r7, #4]
- 80079bc:	681b      	ldr	r3, [r3, #0]
- 80079be:	681b      	ldr	r3, [r3, #0]
- 80079c0:	60fb      	str	r3, [r7, #12]
-
-  /* Disable UART */
-  __HAL_UART_DISABLE(huart);
- 80079c2:	687b      	ldr	r3, [r7, #4]
- 80079c4:	681b      	ldr	r3, [r3, #0]
- 80079c6:	681a      	ldr	r2, [r3, #0]
- 80079c8:	687b      	ldr	r3, [r7, #4]
- 80079ca:	681b      	ldr	r3, [r3, #0]
- 80079cc:	2101      	movs	r1, #1
- 80079ce:	438a      	bics	r2, r1
- 80079d0:	601a      	str	r2, [r3, #0]
-
-  /* Disable FIFO mode */
-  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
- 80079d2:	68fb      	ldr	r3, [r7, #12]
- 80079d4:	4a0b      	ldr	r2, [pc, #44]	@ (8007a04 <HAL_UARTEx_DisableFifoMode+0x70>)
- 80079d6:	4013      	ands	r3, r2
- 80079d8:	60fb      	str	r3, [r7, #12]
-  huart->FifoMode = UART_FIFOMODE_DISABLE;
- 80079da:	687b      	ldr	r3, [r7, #4]
- 80079dc:	2200      	movs	r2, #0
- 80079de:	665a      	str	r2, [r3, #100]	@ 0x64
-
-  /* Restore UART configuration */
-  WRITE_REG(huart->Instance->CR1, tmpcr1);
- 80079e0:	687b      	ldr	r3, [r7, #4]
- 80079e2:	681b      	ldr	r3, [r3, #0]
- 80079e4:	68fa      	ldr	r2, [r7, #12]
- 80079e6:	601a      	str	r2, [r3, #0]
-
-  huart->gState = HAL_UART_STATE_READY;
- 80079e8:	687b      	ldr	r3, [r7, #4]
- 80079ea:	2288      	movs	r2, #136	@ 0x88
- 80079ec:	2120      	movs	r1, #32
- 80079ee:	5099      	str	r1, [r3, r2]
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
- 80079f0:	687b      	ldr	r3, [r7, #4]
- 80079f2:	2284      	movs	r2, #132	@ 0x84
- 80079f4:	2100      	movs	r1, #0
- 80079f6:	5499      	strb	r1, [r3, r2]
-
-  return HAL_OK;
- 80079f8:	2300      	movs	r3, #0
-}
- 80079fa:	0018      	movs	r0, r3
- 80079fc:	46bd      	mov	sp, r7
- 80079fe:	b004      	add	sp, #16
- 8007a00:	bd80      	pop	{r7, pc}
- 8007a02:	46c0      	nop			@ (mov r8, r8)
- 8007a04:	dfffffff 	.word	0xdfffffff
-
-08007a08 <HAL_UARTEx_SetTxFifoThreshold>:
-  *            @arg @ref UART_TXFIFO_THRESHOLD_7_8
-  *            @arg @ref UART_TXFIFO_THRESHOLD_8_8
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+ 8004598:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+ 800459a:	6801      	ldr	r1, [r0, #0]
+  errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF));
+ 800459c:	4dc3      	ldr	r5, [pc, #780]	@ (80048ac <HAL_UART_IRQHandler+0x314>)
+  uint32_t isrflags   = READ_REG(huart->Instance->ISR);
+ 800459e:	69cb      	ldr	r3, [r1, #28]
 {
- 8007a08:	b580      	push	{r7, lr}
- 8007a0a:	b084      	sub	sp, #16
- 8007a0c:	af00      	add	r7, sp, #0
- 8007a0e:	6078      	str	r0, [r7, #4]
- 8007a10:	6039      	str	r1, [r7, #0]
-  /* Check parameters */
-  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
-  assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
- 8007a12:	687b      	ldr	r3, [r7, #4]
- 8007a14:	2284      	movs	r2, #132	@ 0x84
- 8007a16:	5c9b      	ldrb	r3, [r3, r2]
- 8007a18:	2b01      	cmp	r3, #1
- 8007a1a:	d101      	bne.n	8007a20 <HAL_UARTEx_SetTxFifoThreshold+0x18>
- 8007a1c:	2302      	movs	r3, #2
- 8007a1e:	e02e      	b.n	8007a7e <HAL_UARTEx_SetTxFifoThreshold+0x76>
- 8007a20:	687b      	ldr	r3, [r7, #4]
- 8007a22:	2284      	movs	r2, #132	@ 0x84
- 8007a24:	2101      	movs	r1, #1
- 8007a26:	5499      	strb	r1, [r3, r2]
-
-  huart->gState = HAL_UART_STATE_BUSY;
- 8007a28:	687b      	ldr	r3, [r7, #4]
- 8007a2a:	2288      	movs	r2, #136	@ 0x88
- 8007a2c:	2124      	movs	r1, #36	@ 0x24
- 8007a2e:	5099      	str	r1, [r3, r2]
-
-  /* Save actual UART configuration */
-  tmpcr1 = READ_REG(huart->Instance->CR1);
- 8007a30:	687b      	ldr	r3, [r7, #4]
- 8007a32:	681b      	ldr	r3, [r3, #0]
- 8007a34:	681b      	ldr	r3, [r3, #0]
- 8007a36:	60fb      	str	r3, [r7, #12]
-
-  /* Disable UART */
-  __HAL_UART_DISABLE(huart);
- 8007a38:	687b      	ldr	r3, [r7, #4]
- 8007a3a:	681b      	ldr	r3, [r3, #0]
- 8007a3c:	681a      	ldr	r2, [r3, #0]
- 8007a3e:	687b      	ldr	r3, [r7, #4]
- 8007a40:	681b      	ldr	r3, [r3, #0]
- 8007a42:	2101      	movs	r1, #1
- 8007a44:	438a      	bics	r2, r1
- 8007a46:	601a      	str	r2, [r3, #0]
-
-  /* Update TX threshold configuration */
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
- 8007a48:	687b      	ldr	r3, [r7, #4]
- 8007a4a:	681b      	ldr	r3, [r3, #0]
- 8007a4c:	689b      	ldr	r3, [r3, #8]
- 8007a4e:	00db      	lsls	r3, r3, #3
- 8007a50:	08d9      	lsrs	r1, r3, #3
- 8007a52:	687b      	ldr	r3, [r7, #4]
- 8007a54:	681b      	ldr	r3, [r3, #0]
- 8007a56:	683a      	ldr	r2, [r7, #0]
- 8007a58:	430a      	orrs	r2, r1
- 8007a5a:	609a      	str	r2, [r3, #8]
-
-  /* Determine the number of data to process during RX/TX ISR execution */
-  UARTEx_SetNbDataToProcess(huart);
- 8007a5c:	687b      	ldr	r3, [r7, #4]
- 8007a5e:	0018      	movs	r0, r3
- 8007a60:	f000 f8bc 	bl	8007bdc <UARTEx_SetNbDataToProcess>
-
-  /* Restore UART configuration */
-  WRITE_REG(huart->Instance->CR1, tmpcr1);
- 8007a64:	687b      	ldr	r3, [r7, #4]
- 8007a66:	681b      	ldr	r3, [r3, #0]
- 8007a68:	68fa      	ldr	r2, [r7, #12]
- 8007a6a:	601a      	str	r2, [r3, #0]
-
-  huart->gState = HAL_UART_STATE_READY;
- 8007a6c:	687b      	ldr	r3, [r7, #4]
- 8007a6e:	2288      	movs	r2, #136	@ 0x88
- 8007a70:	2120      	movs	r1, #32
- 8007a72:	5099      	str	r1, [r3, r2]
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
- 8007a74:	687b      	ldr	r3, [r7, #4]
- 8007a76:	2284      	movs	r2, #132	@ 0x84
- 8007a78:	2100      	movs	r1, #0
- 8007a7a:	5499      	strb	r1, [r3, r2]
-
-  return HAL_OK;
- 8007a7c:	2300      	movs	r3, #0
+ 80045a0:	0004      	movs	r4, r0
+  uint32_t cr1its     = READ_REG(huart->Instance->CR1);
+ 80045a2:	680a      	ldr	r2, [r1, #0]
+  uint32_t cr3its     = READ_REG(huart->Instance->CR3);
+ 80045a4:	6888      	ldr	r0, [r1, #8]
+  if (errorflags == 0U)
+ 80045a6:	422b      	tst	r3, r5
+ 80045a8:	d110      	bne.n	80045cc <HAL_UART_IRQHandler+0x34>
+    if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ 80045aa:	2520      	movs	r5, #32
+ 80045ac:	422b      	tst	r3, r5
+ 80045ae:	d100      	bne.n	80045b2 <HAL_UART_IRQHandler+0x1a>
+ 80045b0:	e09b      	b.n	80046ea <HAL_UART_IRQHandler+0x152>
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ 80045b2:	2680      	movs	r6, #128	@ 0x80
+ 80045b4:	0576      	lsls	r6, r6, #21
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ 80045b6:	4015      	ands	r5, r2
+            || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ 80045b8:	4006      	ands	r6, r0
+ 80045ba:	4335      	orrs	r5, r6
+ 80045bc:	d100      	bne.n	80045c0 <HAL_UART_IRQHandler+0x28>
+ 80045be:	e094      	b.n	80046ea <HAL_UART_IRQHandler+0x152>
+      if (huart->RxISR != NULL)
+ 80045c0:	6f63      	ldr	r3, [r4, #116]	@ 0x74
+      huart->TxISR(huart);
+ 80045c2:	0020      	movs	r0, r4
+    if (huart->TxISR != NULL)
+ 80045c4:	2b00      	cmp	r3, #0
+ 80045c6:	d000      	beq.n	80045ca <HAL_UART_IRQHandler+0x32>
+ 80045c8:	e085      	b.n	80046d6 <HAL_UART_IRQHandler+0x13e>
+ 80045ca:	e085      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+      && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U)
+ 80045cc:	4db8      	ldr	r5, [pc, #736]	@ (80048b0 <HAL_UART_IRQHandler+0x318>)
+ 80045ce:	4005      	ands	r5, r0
+ 80045d0:	9500      	str	r5, [sp, #0]
+           || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U))))
+ 80045d2:	4db8      	ldr	r5, [pc, #736]	@ (80048b4 <HAL_UART_IRQHandler+0x31c>)
+ 80045d4:	9e00      	ldr	r6, [sp, #0]
+ 80045d6:	4015      	ands	r5, r2
+ 80045d8:	4335      	orrs	r5, r6
+ 80045da:	d100      	bne.n	80045de <HAL_UART_IRQHandler+0x46>
+ 80045dc:	e085      	b.n	80046ea <HAL_UART_IRQHandler+0x152>
+    if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U))
+ 80045de:	0025      	movs	r5, r4
+ 80045e0:	2601      	movs	r6, #1
+ 80045e2:	3590      	adds	r5, #144	@ 0x90
+ 80045e4:	4233      	tst	r3, r6
+ 80045e6:	d005      	beq.n	80045f4 <HAL_UART_IRQHandler+0x5c>
+ 80045e8:	05d7      	lsls	r7, r2, #23
+ 80045ea:	d503      	bpl.n	80045f4 <HAL_UART_IRQHandler+0x5c>
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF);
+ 80045ec:	620e      	str	r6, [r1, #32]
+      huart->ErrorCode |= HAL_UART_ERROR_PE;
+ 80045ee:	682f      	ldr	r7, [r5, #0]
+ 80045f0:	433e      	orrs	r6, r7
+ 80045f2:	602e      	str	r6, [r5, #0]
+    if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ 80045f4:	2602      	movs	r6, #2
+ 80045f6:	4233      	tst	r3, r6
+ 80045f8:	d00c      	beq.n	8004614 <HAL_UART_IRQHandler+0x7c>
+ 80045fa:	07c7      	lsls	r7, r0, #31
+ 80045fc:	d50a      	bpl.n	8004614 <HAL_UART_IRQHandler+0x7c>
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+ 80045fe:	0027      	movs	r7, r4
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF);
+ 8004600:	620e      	str	r6, [r1, #32]
+      huart->ErrorCode |= HAL_UART_ERROR_FE;
+ 8004602:	3790      	adds	r7, #144	@ 0x90
+ 8004604:	683e      	ldr	r6, [r7, #0]
+ 8004606:	9701      	str	r7, [sp, #4]
+ 8004608:	46b4      	mov	ip, r6
+ 800460a:	2604      	movs	r6, #4
+ 800460c:	4667      	mov	r7, ip
+ 800460e:	433e      	orrs	r6, r7
+ 8004610:	9f01      	ldr	r7, [sp, #4]
+ 8004612:	603e      	str	r6, [r7, #0]
+    if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U))
+ 8004614:	2604      	movs	r6, #4
+ 8004616:	4233      	tst	r3, r6
+ 8004618:	d00c      	beq.n	8004634 <HAL_UART_IRQHandler+0x9c>
+ 800461a:	07c7      	lsls	r7, r0, #31
+ 800461c:	d50a      	bpl.n	8004634 <HAL_UART_IRQHandler+0x9c>
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+ 800461e:	0027      	movs	r7, r4
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF);
+ 8004620:	620e      	str	r6, [r1, #32]
+      huart->ErrorCode |= HAL_UART_ERROR_NE;
+ 8004622:	3790      	adds	r7, #144	@ 0x90
+ 8004624:	683e      	ldr	r6, [r7, #0]
+ 8004626:	9701      	str	r7, [sp, #4]
+ 8004628:	46b4      	mov	ip, r6
+ 800462a:	2602      	movs	r6, #2
+ 800462c:	4667      	mov	r7, ip
+ 800462e:	433e      	orrs	r6, r7
+ 8004630:	9f01      	ldr	r7, [sp, #4]
+ 8004632:	603e      	str	r6, [r7, #0]
+    if (((isrflags & USART_ISR_ORE) != 0U)
+ 8004634:	2608      	movs	r6, #8
+ 8004636:	46b4      	mov	ip, r6
+ 8004638:	4233      	tst	r3, r6
+ 800463a:	d009      	beq.n	8004650 <HAL_UART_IRQHandler+0xb8>
+        && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) ||
+ 800463c:	2720      	movs	r7, #32
+ 800463e:	9e00      	ldr	r6, [sp, #0]
+ 8004640:	4017      	ands	r7, r2
+ 8004642:	4337      	orrs	r7, r6
+ 8004644:	d004      	beq.n	8004650 <HAL_UART_IRQHandler+0xb8>
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+ 8004646:	4666      	mov	r6, ip
+ 8004648:	620e      	str	r6, [r1, #32]
+      huart->ErrorCode |= HAL_UART_ERROR_ORE;
+ 800464a:	682f      	ldr	r7, [r5, #0]
+ 800464c:	433e      	orrs	r6, r7
+ 800464e:	602e      	str	r6, [r5, #0]
+    if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U))
+ 8004650:	2680      	movs	r6, #128	@ 0x80
+ 8004652:	0136      	lsls	r6, r6, #4
+ 8004654:	4233      	tst	r3, r6
+ 8004656:	d006      	beq.n	8004666 <HAL_UART_IRQHandler+0xce>
+ 8004658:	0157      	lsls	r7, r2, #5
+ 800465a:	d504      	bpl.n	8004666 <HAL_UART_IRQHandler+0xce>
+      __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+ 800465c:	620e      	str	r6, [r1, #32]
+      huart->ErrorCode |= HAL_UART_ERROR_RTO;
+ 800465e:	2120      	movs	r1, #32
+ 8004660:	682e      	ldr	r6, [r5, #0]
+ 8004662:	4331      	orrs	r1, r6
+ 8004664:	6029      	str	r1, [r5, #0]
+    if (huart->ErrorCode != HAL_UART_ERROR_NONE)
+ 8004666:	6829      	ldr	r1, [r5, #0]
+ 8004668:	2900      	cmp	r1, #0
+ 800466a:	d035      	beq.n	80046d8 <HAL_UART_IRQHandler+0x140>
+      if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U)
+ 800466c:	2120      	movs	r1, #32
+ 800466e:	420b      	tst	r3, r1
+ 8004670:	d00a      	beq.n	8004688 <HAL_UART_IRQHandler+0xf0>
+              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ 8004672:	2380      	movs	r3, #128	@ 0x80
+ 8004674:	055b      	lsls	r3, r3, #21
+          && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U)
+ 8004676:	4011      	ands	r1, r2
+              || ((cr3its & USART_CR3_RXFTIE) != 0U)))
+ 8004678:	4003      	ands	r3, r0
+ 800467a:	4319      	orrs	r1, r3
+ 800467c:	d004      	beq.n	8004688 <HAL_UART_IRQHandler+0xf0>
+        if (huart->RxISR != NULL)
+ 800467e:	6f63      	ldr	r3, [r4, #116]	@ 0x74
+ 8004680:	2b00      	cmp	r3, #0
+ 8004682:	d001      	beq.n	8004688 <HAL_UART_IRQHandler+0xf0>
+          huart->RxISR(huart);
+ 8004684:	0020      	movs	r0, r4
+ 8004686:	4798      	blx	r3
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ 8004688:	6822      	ldr	r2, [r4, #0]
+      errorcode = huart->ErrorCode;
+ 800468a:	682b      	ldr	r3, [r5, #0]
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ 800468c:	2740      	movs	r7, #64	@ 0x40
+ 800468e:	6896      	ldr	r6, [r2, #8]
+          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+ 8004690:	2228      	movs	r2, #40	@ 0x28
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ 8004692:	403e      	ands	r6, r7
+          ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U))
+ 8004694:	4013      	ands	r3, r2
+        UART_EndRxTransfer(huart);
+ 8004696:	0020      	movs	r0, r4
+      if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) ||
+ 8004698:	431e      	orrs	r6, r3
+ 800469a:	d022      	beq.n	80046e2 <HAL_UART_IRQHandler+0x14a>
+        UART_EndRxTransfer(huart);
+ 800469c:	f7ff ff14 	bl	80044c8 <UART_EndRxTransfer>
+        if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 80046a0:	6823      	ldr	r3, [r4, #0]
+ 80046a2:	689b      	ldr	r3, [r3, #8]
+ 80046a4:	423b      	tst	r3, r7
+ 80046a6:	d018      	beq.n	80046da <HAL_UART_IRQHandler+0x142>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 80046a8:	f3ef 8110 	mrs	r1, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 80046ac:	2301      	movs	r3, #1
+ 80046ae:	f383 8810 	msr	PRIMASK, r3
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ 80046b2:	0025      	movs	r5, r4
+ 80046b4:	cd04      	ldmia	r5!, {r2}
+ 80046b6:	6893      	ldr	r3, [r2, #8]
+ 80046b8:	43bb      	bics	r3, r7
+ 80046ba:	6093      	str	r3, [r2, #8]
+ 80046bc:	f381 8810 	msr	PRIMASK, r1
+          if (huart->hdmarx != NULL)
+ 80046c0:	6fe8      	ldr	r0, [r5, #124]	@ 0x7c
+ 80046c2:	2800      	cmp	r0, #0
+ 80046c4:	d009      	beq.n	80046da <HAL_UART_IRQHandler+0x142>
+            huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError;
+ 80046c6:	4b7c      	ldr	r3, [pc, #496]	@ (80048b8 <HAL_UART_IRQHandler+0x320>)
+ 80046c8:	6383      	str	r3, [r0, #56]	@ 0x38
+            if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK)
+ 80046ca:	f7fe fcd1 	bl	8003070 <HAL_DMA_Abort_IT>
+ 80046ce:	2800      	cmp	r0, #0
+ 80046d0:	d002      	beq.n	80046d8 <HAL_UART_IRQHandler+0x140>
+              huart->hdmarx->XferAbortCallback(huart->hdmarx);
+ 80046d2:	6fe8      	ldr	r0, [r5, #124]	@ 0x7c
+ 80046d4:	6b83      	ldr	r3, [r0, #56]	@ 0x38
+ 80046d6:	4798      	blx	r3
 }
- 8007a7e:	0018      	movs	r0, r3
- 8007a80:	46bd      	mov	sp, r7
- 8007a82:	b004      	add	sp, #16
- 8007a84:	bd80      	pop	{r7, pc}
+ 80046d8:	bdf7      	pop	{r0, r1, r2, r4, r5, r6, r7, pc}
+            HAL_UART_ErrorCallback(huart);
+ 80046da:	0020      	movs	r0, r4
+ 80046dc:	f7fc f9bc 	bl	8000a58 <HAL_UART_ErrorCallback>
+ 80046e0:	e7fa      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+        HAL_UART_ErrorCallback(huart);
+ 80046e2:	f7fc f9b9 	bl	8000a58 <HAL_UART_ErrorCallback>
+        huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 80046e6:	602e      	str	r6, [r5, #0]
+ 80046e8:	e7f6      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+  if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 80046ea:	6ee5      	ldr	r5, [r4, #108]	@ 0x6c
+ 80046ec:	2d01      	cmp	r5, #1
+ 80046ee:	d000      	beq.n	80046f2 <HAL_UART_IRQHandler+0x15a>
+ 80046f0:	e0a4      	b.n	800483c <HAL_UART_IRQHandler+0x2a4>
+      && ((isrflags & USART_ISR_IDLE) != 0U)
+ 80046f2:	2610      	movs	r6, #16
+ 80046f4:	4233      	tst	r3, r6
+ 80046f6:	d100      	bne.n	80046fa <HAL_UART_IRQHandler+0x162>
+ 80046f8:	e0a0      	b.n	800483c <HAL_UART_IRQHandler+0x2a4>
+      && ((cr1its & USART_ISR_IDLE) != 0U))
+ 80046fa:	4232      	tst	r2, r6
+ 80046fc:	d100      	bne.n	8004700 <HAL_UART_IRQHandler+0x168>
+ 80046fe:	e09d      	b.n	800483c <HAL_UART_IRQHandler+0x2a4>
+          && (nb_remaining_rx_data < huart->RxXferSize))
+ 8004700:	0023      	movs	r3, r4
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ 8004702:	620e      	str	r6, [r1, #32]
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 8004704:	6889      	ldr	r1, [r1, #8]
+          && (nb_remaining_rx_data < huart->RxXferSize))
+ 8004706:	335c      	adds	r3, #92	@ 0x5c
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 8004708:	0008      	movs	r0, r1
+          && (nb_remaining_rx_data < huart->RxXferSize))
+ 800470a:	881a      	ldrh	r2, [r3, #0]
+    if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR))
+ 800470c:	2340      	movs	r3, #64	@ 0x40
+ 800470e:	4018      	ands	r0, r3
+ 8004710:	4219      	tst	r1, r3
+ 8004712:	d05e      	beq.n	80047d2 <HAL_UART_IRQHandler+0x23a>
+      uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx);
+ 8004714:	1d20      	adds	r0, r4, #4
+ 8004716:	6fc1      	ldr	r1, [r0, #124]	@ 0x7c
+ 8004718:	680f      	ldr	r7, [r1, #0]
+ 800471a:	6879      	ldr	r1, [r7, #4]
+ 800471c:	b289      	uxth	r1, r1
+      if ((nb_remaining_rx_data > 0U)
+ 800471e:	2900      	cmp	r1, #0
+ 8004720:	d04d      	beq.n	80047be <HAL_UART_IRQHandler+0x226>
+          && (nb_remaining_rx_data < huart->RxXferSize))
+ 8004722:	4291      	cmp	r1, r2
+ 8004724:	d24b      	bcs.n	80047be <HAL_UART_IRQHandler+0x226>
+        huart->RxXferCount = nb_remaining_rx_data;
+ 8004726:	0022      	movs	r2, r4
+ 8004728:	325e      	adds	r2, #94	@ 0x5e
+ 800472a:	8011      	strh	r1, [r2, #0]
+        if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
+ 800472c:	2120      	movs	r1, #32
+ 800472e:	468c      	mov	ip, r1
+ 8004730:	683a      	ldr	r2, [r7, #0]
+ 8004732:	4011      	ands	r1, r2
+ 8004734:	9100      	str	r1, [sp, #0]
+ 8004736:	4661      	mov	r1, ip
+ 8004738:	420a      	tst	r2, r1
+ 800473a:	d132      	bne.n	80047a2 <HAL_UART_IRQHandler+0x20a>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 800473c:	f3ef 8710 	mrs	r7, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004740:	f385 8810 	msr	PRIMASK, r5
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ 8004744:	6821      	ldr	r1, [r4, #0]
+ 8004746:	4e5d      	ldr	r6, [pc, #372]	@ (80048bc <HAL_UART_IRQHandler+0x324>)
+ 8004748:	680a      	ldr	r2, [r1, #0]
+ 800474a:	4032      	ands	r2, r6
+ 800474c:	600a      	str	r2, [r1, #0]
+ 800474e:	f387 8810 	msr	PRIMASK, r7
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004752:	f3ef 8710 	mrs	r7, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004756:	f385 8810 	msr	PRIMASK, r5
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 800475a:	6821      	ldr	r1, [r4, #0]
+ 800475c:	688a      	ldr	r2, [r1, #8]
+ 800475e:	43aa      	bics	r2, r5
+ 8004760:	608a      	str	r2, [r1, #8]
+ 8004762:	f387 8810 	msr	PRIMASK, r7
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004766:	f3ef 8710 	mrs	r7, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 800476a:	f385 8810 	msr	PRIMASK, r5
+          ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ 800476e:	6821      	ldr	r1, [r4, #0]
+ 8004770:	688a      	ldr	r2, [r1, #8]
+ 8004772:	439a      	bics	r2, r3
+ 8004774:	608a      	str	r2, [r1, #8]
+ 8004776:	f387 8810 	msr	PRIMASK, r7
+          huart->RxState = HAL_UART_STATE_READY;
+ 800477a:	0023      	movs	r3, r4
+ 800477c:	4662      	mov	r2, ip
+ 800477e:	338c      	adds	r3, #140	@ 0x8c
+ 8004780:	601a      	str	r2, [r3, #0]
+          huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 8004782:	9b00      	ldr	r3, [sp, #0]
+ 8004784:	66e3      	str	r3, [r4, #108]	@ 0x6c
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004786:	f3ef 8110 	mrs	r1, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 800478a:	f385 8810 	msr	PRIMASK, r5
+          ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 800478e:	6822      	ldr	r2, [r4, #0]
+ 8004790:	350f      	adds	r5, #15
+ 8004792:	6813      	ldr	r3, [r2, #0]
+ 8004794:	43ab      	bics	r3, r5
+ 8004796:	6013      	str	r3, [r2, #0]
+ 8004798:	f381 8810 	msr	PRIMASK, r1
+          (void)HAL_DMA_Abort(huart->hdmarx);
+ 800479c:	6fc0      	ldr	r0, [r0, #124]	@ 0x7c
+ 800479e:	f7fe fc2d 	bl	8002ffc <HAL_DMA_Abort>
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+ 80047a2:	2302      	movs	r3, #2
+        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+ 80047a4:	0022      	movs	r2, r4
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+ 80047a6:	6723      	str	r3, [r4, #112]	@ 0x70
+        HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+ 80047a8:	0023      	movs	r3, r4
+ 80047aa:	325c      	adds	r2, #92	@ 0x5c
+ 80047ac:	335e      	adds	r3, #94	@ 0x5e
+ 80047ae:	881b      	ldrh	r3, [r3, #0]
+ 80047b0:	8811      	ldrh	r1, [r2, #0]
+ 80047b2:	1ac9      	subs	r1, r1, r3
+ 80047b4:	b289      	uxth	r1, r1
+            HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize);
+ 80047b6:	0020      	movs	r0, r4
+ 80047b8:	f7fc f916 	bl	80009e8 <HAL_UARTEx_RxEventCallback>
+ 80047bc:	e78c      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+        if (nb_remaining_rx_data == huart->RxXferSize)
+ 80047be:	4291      	cmp	r1, r2
+ 80047c0:	d000      	beq.n	80047c4 <HAL_UART_IRQHandler+0x22c>
+ 80047c2:	e789      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+          if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC))
+ 80047c4:	683b      	ldr	r3, [r7, #0]
+ 80047c6:	069b      	lsls	r3, r3, #26
+ 80047c8:	d400      	bmi.n	80047cc <HAL_UART_IRQHandler+0x234>
+ 80047ca:	e785      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+            huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+ 80047cc:	2302      	movs	r3, #2
+ 80047ce:	6723      	str	r3, [r4, #112]	@ 0x70
+ 80047d0:	e7f1      	b.n	80047b6 <HAL_UART_IRQHandler+0x21e>
+      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+ 80047d2:	0021      	movs	r1, r4
+ 80047d4:	315e      	adds	r1, #94	@ 0x5e
+ 80047d6:	880b      	ldrh	r3, [r1, #0]
+      if ((huart->RxXferCount > 0U)
+ 80047d8:	8809      	ldrh	r1, [r1, #0]
+      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+ 80047da:	b29b      	uxth	r3, r3
+      if ((huart->RxXferCount > 0U)
+ 80047dc:	2900      	cmp	r1, #0
+ 80047de:	d100      	bne.n	80047e2 <HAL_UART_IRQHandler+0x24a>
+ 80047e0:	e77a      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+      uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount;
+ 80047e2:	1ad2      	subs	r2, r2, r3
+ 80047e4:	b291      	uxth	r1, r2
+          && (nb_rx_data > 0U))
+ 80047e6:	2900      	cmp	r1, #0
+ 80047e8:	d100      	bne.n	80047ec <HAL_UART_IRQHandler+0x254>
+ 80047ea:	e775      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 80047ec:	f3ef 8710 	mrs	r7, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 80047f0:	f385 8810 	msr	PRIMASK, r5
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ 80047f4:	6822      	ldr	r2, [r4, #0]
+ 80047f6:	4e32      	ldr	r6, [pc, #200]	@ (80048c0 <HAL_UART_IRQHandler+0x328>)
+ 80047f8:	6813      	ldr	r3, [r2, #0]
+ 80047fa:	4033      	ands	r3, r6
+ 80047fc:	6013      	str	r3, [r2, #0]
+ 80047fe:	f387 8810 	msr	PRIMASK, r7
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004802:	f3ef 8710 	mrs	r7, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004806:	f385 8810 	msr	PRIMASK, r5
+        ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE));
+ 800480a:	6822      	ldr	r2, [r4, #0]
+ 800480c:	4e2d      	ldr	r6, [pc, #180]	@ (80048c4 <HAL_UART_IRQHandler+0x32c>)
+ 800480e:	6893      	ldr	r3, [r2, #8]
+ 8004810:	4033      	ands	r3, r6
+ 8004812:	6093      	str	r3, [r2, #8]
+ 8004814:	f387 8810 	msr	PRIMASK, r7
+        huart->RxState = HAL_UART_STATE_READY;
+ 8004818:	0023      	movs	r3, r4
+ 800481a:	2220      	movs	r2, #32
+ 800481c:	338c      	adds	r3, #140	@ 0x8c
+ 800481e:	601a      	str	r2, [r3, #0]
+        huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 8004820:	66e0      	str	r0, [r4, #108]	@ 0x6c
+        huart->RxISR = NULL;
+ 8004822:	6760      	str	r0, [r4, #116]	@ 0x74
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004824:	f3ef 8010 	mrs	r0, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004828:	f385 8810 	msr	PRIMASK, r5
+        ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 800482c:	2510      	movs	r5, #16
+ 800482e:	6822      	ldr	r2, [r4, #0]
+ 8004830:	6813      	ldr	r3, [r2, #0]
+ 8004832:	43ab      	bics	r3, r5
+ 8004834:	6013      	str	r3, [r2, #0]
+ 8004836:	f380 8810 	msr	PRIMASK, r0
+        huart->RxEventType = HAL_UART_RXEVENT_IDLE;
+ 800483a:	e7c7      	b.n	80047cc <HAL_UART_IRQHandler+0x234>
+  if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U))
+ 800483c:	2580      	movs	r5, #128	@ 0x80
+ 800483e:	036d      	lsls	r5, r5, #13
+ 8004840:	422b      	tst	r3, r5
+ 8004842:	d006      	beq.n	8004852 <HAL_UART_IRQHandler+0x2ba>
+ 8004844:	0246      	lsls	r6, r0, #9
+ 8004846:	d504      	bpl.n	8004852 <HAL_UART_IRQHandler+0x2ba>
+    HAL_UARTEx_WakeupCallback(huart);
+ 8004848:	0020      	movs	r0, r4
+    __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF);
+ 800484a:	620d      	str	r5, [r1, #32]
+    HAL_UARTEx_WakeupCallback(huart);
+ 800484c:	f000 fbfa 	bl	8005044 <HAL_UARTEx_WakeupCallback>
+    return;
+ 8004850:	e742      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+  if (((isrflags & USART_ISR_TXE_TXFNF) != 0U)
+ 8004852:	2180      	movs	r1, #128	@ 0x80
+ 8004854:	420b      	tst	r3, r1
+ 8004856:	d007      	beq.n	8004868 <HAL_UART_IRQHandler+0x2d0>
+          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+ 8004858:	2580      	movs	r5, #128	@ 0x80
+ 800485a:	042d      	lsls	r5, r5, #16
+      && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U)
+ 800485c:	4011      	ands	r1, r2
+          || ((cr3its & USART_CR3_TXFTIE) != 0U)))
+ 800485e:	4028      	ands	r0, r5
+ 8004860:	4301      	orrs	r1, r0
+ 8004862:	d001      	beq.n	8004868 <HAL_UART_IRQHandler+0x2d0>
+    if (huart->TxISR != NULL)
+ 8004864:	6fa3      	ldr	r3, [r4, #120]	@ 0x78
+ 8004866:	e6ac      	b.n	80045c2 <HAL_UART_IRQHandler+0x2a>
+  if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U))
+ 8004868:	2140      	movs	r1, #64	@ 0x40
+ 800486a:	420b      	tst	r3, r1
+ 800486c:	d016      	beq.n	800489c <HAL_UART_IRQHandler+0x304>
+ 800486e:	420a      	tst	r2, r1
+ 8004870:	d014      	beq.n	800489c <HAL_UART_IRQHandler+0x304>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004872:	f3ef 8010 	mrs	r0, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004876:	2301      	movs	r3, #1
+ 8004878:	f383 8810 	msr	PRIMASK, r3
+  * @retval None
+  */
+static void UART_EndTransmit_IT(UART_HandleTypeDef *huart)
+{
+  /* Disable the UART Transmit Complete Interrupt */
+  ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE);
+ 800487c:	6822      	ldr	r2, [r4, #0]
+ 800487e:	6813      	ldr	r3, [r2, #0]
+ 8004880:	438b      	bics	r3, r1
+ 8004882:	6013      	str	r3, [r2, #0]
+ 8004884:	f380 8810 	msr	PRIMASK, r0
+
+  /* Tx process is ended, restore huart->gState to Ready */
+  huart->gState = HAL_UART_STATE_READY;
+ 8004888:	0023      	movs	r3, r4
+ 800488a:	2220      	movs	r2, #32
+ 800488c:	3388      	adds	r3, #136	@ 0x88
+ 800488e:	601a      	str	r2, [r3, #0]
+
+  /* Cleat TxISR function pointer */
+  huart->TxISR = NULL;
+ 8004890:	2300      	movs	r3, #0
+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
+  /*Call registered Tx complete callback*/
+  huart->TxCpltCallback(huart);
+#else
+  /*Call legacy weak Tx complete callback*/
+  HAL_UART_TxCpltCallback(huart);
+ 8004892:	0020      	movs	r0, r4
+  huart->TxISR = NULL;
+ 8004894:	67a3      	str	r3, [r4, #120]	@ 0x78
+  HAL_UART_TxCpltCallback(huart);
+ 8004896:	f7ff fe49 	bl	800452c <HAL_UART_TxCpltCallback>
+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */
+}
+ 800489a:	e71d      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+  if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U))
+ 800489c:	0219      	lsls	r1, r3, #8
+ 800489e:	d513      	bpl.n	80048c8 <HAL_UART_IRQHandler+0x330>
+ 80048a0:	0051      	lsls	r1, r2, #1
+ 80048a2:	d511      	bpl.n	80048c8 <HAL_UART_IRQHandler+0x330>
+    HAL_UARTEx_TxFifoEmptyCallback(huart);
+ 80048a4:	0020      	movs	r0, r4
+ 80048a6:	f000 fbcf 	bl	8005048 <HAL_UARTEx_TxFifoEmptyCallback>
+    return;
+ 80048aa:	e715      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+ 80048ac:	0000080f 	.word	0x0000080f
+ 80048b0:	10000001 	.word	0x10000001
+ 80048b4:	04000120 	.word	0x04000120
+ 80048b8:	08004587 	.word	0x08004587
+ 80048bc:	fffffeff 	.word	0xfffffeff
+ 80048c0:	fffffedf 	.word	0xfffffedf
+ 80048c4:	effffffe 	.word	0xeffffffe
+  if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U))
+ 80048c8:	01db      	lsls	r3, r3, #7
+ 80048ca:	d400      	bmi.n	80048ce <HAL_UART_IRQHandler+0x336>
+ 80048cc:	e704      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+ 80048ce:	2a00      	cmp	r2, #0
+ 80048d0:	db00      	blt.n	80048d4 <HAL_UART_IRQHandler+0x33c>
+ 80048d2:	e701      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+    HAL_UARTEx_RxFifoFullCallback(huart);
+ 80048d4:	0020      	movs	r0, r4
+ 80048d6:	f000 fbb6 	bl	8005046 <HAL_UARTEx_RxFifoFullCallback>
+    return;
+ 80048da:	e6fd      	b.n	80046d8 <HAL_UART_IRQHandler+0x140>
+
+080048dc <UART_DMARxHalfCplt>:
+  huart->RxEventType = HAL_UART_RXEVENT_HT;
+ 80048dc:	2201      	movs	r2, #1
+{
+ 80048de:	0003      	movs	r3, r0
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 80048e0:	6a80      	ldr	r0, [r0, #40]	@ 0x28
+{
+ 80048e2:	b510      	push	{r4, lr}
+  huart->RxEventType = HAL_UART_RXEVENT_HT;
+ 80048e4:	6702      	str	r2, [r0, #112]	@ 0x70
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 80048e6:	6ec2      	ldr	r2, [r0, #108]	@ 0x6c
+ 80048e8:	2a01      	cmp	r2, #1
+ 80048ea:	d111      	bne.n	8004910 <UART_DMARxHalfCplt+0x34>
+    huart->RxXferCount = huart->RxXferSize / 2U;
+ 80048ec:	0002      	movs	r2, r0
+ 80048ee:	325c      	adds	r2, #92	@ 0x5c
+ 80048f0:	8811      	ldrh	r1, [r2, #0]
+    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
+ 80048f2:	681b      	ldr	r3, [r3, #0]
+    huart->RxXferCount = huart->RxXferSize / 2U;
+ 80048f4:	084c      	lsrs	r4, r1, #1
+ 80048f6:	8054      	strh	r4, [r2, #2]
+    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
+ 80048f8:	685b      	ldr	r3, [r3, #4]
+    huart->RxXferCount = huart->RxXferSize / 2U;
+ 80048fa:	3202      	adds	r2, #2
+    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
+ 80048fc:	b29b      	uxth	r3, r3
+    if (nb_remaining_rx_data <= huart->RxXferSize)
+ 80048fe:	4299      	cmp	r1, r3
+ 8004900:	d300      	bcc.n	8004904 <UART_DMARxHalfCplt+0x28>
+      huart->RxXferCount = nb_remaining_rx_data;
+ 8004902:	8013      	strh	r3, [r2, #0]
+    HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+ 8004904:	8813      	ldrh	r3, [r2, #0]
+ 8004906:	1ac9      	subs	r1, r1, r3
+ 8004908:	b289      	uxth	r1, r1
+ 800490a:	f7fc f86d 	bl	80009e8 <HAL_UARTEx_RxEventCallback>
+}
+ 800490e:	bd10      	pop	{r4, pc}
+    HAL_UART_RxHalfCpltCallback(huart);
+ 8004910:	f7ff fe0e 	bl	8004530 <HAL_UART_RxHalfCpltCallback>
+}
+ 8004914:	e7fb      	b.n	800490e <UART_DMARxHalfCplt+0x32>
 	...
 
-08007a88 <HAL_UARTEx_SetRxFifoThreshold>:
-  *            @arg @ref UART_RXFIFO_THRESHOLD_7_8
-  *            @arg @ref UART_RXFIFO_THRESHOLD_8_8
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold)
+08004918 <UART_DMAReceiveCplt>:
 {
- 8007a88:	b580      	push	{r7, lr}
- 8007a8a:	b084      	sub	sp, #16
- 8007a8c:	af00      	add	r7, sp, #0
- 8007a8e:	6078      	str	r0, [r7, #4]
- 8007a90:	6039      	str	r1, [r7, #0]
-  /* Check the parameters */
-  assert_param(IS_UART_FIFO_INSTANCE(huart->Instance));
-  assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold));
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
- 8007a92:	687b      	ldr	r3, [r7, #4]
- 8007a94:	2284      	movs	r2, #132	@ 0x84
- 8007a96:	5c9b      	ldrb	r3, [r3, r2]
- 8007a98:	2b01      	cmp	r3, #1
- 8007a9a:	d101      	bne.n	8007aa0 <HAL_UARTEx_SetRxFifoThreshold+0x18>
- 8007a9c:	2302      	movs	r3, #2
- 8007a9e:	e02f      	b.n	8007b00 <HAL_UARTEx_SetRxFifoThreshold+0x78>
- 8007aa0:	687b      	ldr	r3, [r7, #4]
- 8007aa2:	2284      	movs	r2, #132	@ 0x84
- 8007aa4:	2101      	movs	r1, #1
- 8007aa6:	5499      	strb	r1, [r3, r2]
-
-  huart->gState = HAL_UART_STATE_BUSY;
- 8007aa8:	687b      	ldr	r3, [r7, #4]
- 8007aaa:	2288      	movs	r2, #136	@ 0x88
- 8007aac:	2124      	movs	r1, #36	@ 0x24
- 8007aae:	5099      	str	r1, [r3, r2]
-
-  /* Save actual UART configuration */
-  tmpcr1 = READ_REG(huart->Instance->CR1);
- 8007ab0:	687b      	ldr	r3, [r7, #4]
- 8007ab2:	681b      	ldr	r3, [r3, #0]
- 8007ab4:	681b      	ldr	r3, [r3, #0]
- 8007ab6:	60fb      	str	r3, [r7, #12]
-
-  /* Disable UART */
-  __HAL_UART_DISABLE(huart);
- 8007ab8:	687b      	ldr	r3, [r7, #4]
- 8007aba:	681b      	ldr	r3, [r3, #0]
- 8007abc:	681a      	ldr	r2, [r3, #0]
- 8007abe:	687b      	ldr	r3, [r7, #4]
- 8007ac0:	681b      	ldr	r3, [r3, #0]
- 8007ac2:	2101      	movs	r1, #1
- 8007ac4:	438a      	bics	r2, r1
- 8007ac6:	601a      	str	r2, [r3, #0]
-
-  /* Update RX threshold configuration */
-  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
- 8007ac8:	687b      	ldr	r3, [r7, #4]
- 8007aca:	681b      	ldr	r3, [r3, #0]
- 8007acc:	689b      	ldr	r3, [r3, #8]
- 8007ace:	4a0e      	ldr	r2, [pc, #56]	@ (8007b08 <HAL_UARTEx_SetRxFifoThreshold+0x80>)
- 8007ad0:	4013      	ands	r3, r2
- 8007ad2:	0019      	movs	r1, r3
- 8007ad4:	687b      	ldr	r3, [r7, #4]
- 8007ad6:	681b      	ldr	r3, [r3, #0]
- 8007ad8:	683a      	ldr	r2, [r7, #0]
- 8007ada:	430a      	orrs	r2, r1
- 8007adc:	609a      	str	r2, [r3, #8]
-
-  /* Determine the number of data to process during RX/TX ISR execution */
-  UARTEx_SetNbDataToProcess(huart);
- 8007ade:	687b      	ldr	r3, [r7, #4]
- 8007ae0:	0018      	movs	r0, r3
- 8007ae2:	f000 f87b 	bl	8007bdc <UARTEx_SetNbDataToProcess>
-
-  /* Restore UART configuration */
-  WRITE_REG(huart->Instance->CR1, tmpcr1);
- 8007ae6:	687b      	ldr	r3, [r7, #4]
- 8007ae8:	681b      	ldr	r3, [r3, #0]
- 8007aea:	68fa      	ldr	r2, [r7, #12]
- 8007aec:	601a      	str	r2, [r3, #0]
-
-  huart->gState = HAL_UART_STATE_READY;
- 8007aee:	687b      	ldr	r3, [r7, #4]
- 8007af0:	2288      	movs	r2, #136	@ 0x88
- 8007af2:	2120      	movs	r1, #32
- 8007af4:	5099      	str	r1, [r3, r2]
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
- 8007af6:	687b      	ldr	r3, [r7, #4]
- 8007af8:	2284      	movs	r2, #132	@ 0x84
- 8007afa:	2100      	movs	r1, #0
- 8007afc:	5499      	strb	r1, [r3, r2]
-
-  return HAL_OK;
- 8007afe:	2300      	movs	r3, #0
-}
- 8007b00:	0018      	movs	r0, r3
- 8007b02:	46bd      	mov	sp, r7
- 8007b04:	b004      	add	sp, #16
- 8007b06:	bd80      	pop	{r7, pc}
- 8007b08:	f1ffffff 	.word	0xf1ffffff
-
-08007b0c <HAL_UARTEx_ReceiveToIdle_DMA>:
-  * @param pData Pointer to data buffer (uint8_t or uint16_t data elements).
-  * @param Size  Amount of data elements (uint8_t or uint16_t) to be received.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
- 8007b0c:	b5b0      	push	{r4, r5, r7, lr}
- 8007b0e:	b08a      	sub	sp, #40	@ 0x28
- 8007b10:	af00      	add	r7, sp, #0
- 8007b12:	60f8      	str	r0, [r7, #12]
- 8007b14:	60b9      	str	r1, [r7, #8]
- 8007b16:	1dbb      	adds	r3, r7, #6
- 8007b18:	801a      	strh	r2, [r3, #0]
-  HAL_StatusTypeDef status;
-
-  /* Check that a Rx process is not already ongoing */
-  if (huart->RxState == HAL_UART_STATE_READY)
- 8007b1a:	68fb      	ldr	r3, [r7, #12]
- 8007b1c:	228c      	movs	r2, #140	@ 0x8c
- 8007b1e:	589b      	ldr	r3, [r3, r2]
- 8007b20:	2b20      	cmp	r3, #32
- 8007b22:	d156      	bne.n	8007bd2 <HAL_UARTEx_ReceiveToIdle_DMA+0xc6>
-  {
-    if ((pData == NULL) || (Size == 0U))
- 8007b24:	68bb      	ldr	r3, [r7, #8]
- 8007b26:	2b00      	cmp	r3, #0
- 8007b28:	d003      	beq.n	8007b32 <HAL_UARTEx_ReceiveToIdle_DMA+0x26>
- 8007b2a:	1dbb      	adds	r3, r7, #6
- 8007b2c:	881b      	ldrh	r3, [r3, #0]
- 8007b2e:	2b00      	cmp	r3, #0
- 8007b30:	d101      	bne.n	8007b36 <HAL_UARTEx_ReceiveToIdle_DMA+0x2a>
-    {
-      return HAL_ERROR;
- 8007b32:	2301      	movs	r3, #1
- 8007b34:	e04e      	b.n	8007bd4 <HAL_UARTEx_ReceiveToIdle_DMA+0xc8>
-    }
-
-    /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter
-       should be aligned on a uint16_t frontier, as data copy from RDR will be
-       handled by DMA from a uint16_t frontier. */
-    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
- 8007b36:	68fb      	ldr	r3, [r7, #12]
- 8007b38:	689a      	ldr	r2, [r3, #8]
- 8007b3a:	2380      	movs	r3, #128	@ 0x80
- 8007b3c:	015b      	lsls	r3, r3, #5
- 8007b3e:	429a      	cmp	r2, r3
- 8007b40:	d109      	bne.n	8007b56 <HAL_UARTEx_ReceiveToIdle_DMA+0x4a>
- 8007b42:	68fb      	ldr	r3, [r7, #12]
- 8007b44:	691b      	ldr	r3, [r3, #16]
- 8007b46:	2b00      	cmp	r3, #0
- 8007b48:	d105      	bne.n	8007b56 <HAL_UARTEx_ReceiveToIdle_DMA+0x4a>
-    {
-      if ((((uint32_t)pData) & 1U) != 0U)
- 8007b4a:	68bb      	ldr	r3, [r7, #8]
- 8007b4c:	2201      	movs	r2, #1
- 8007b4e:	4013      	ands	r3, r2
- 8007b50:	d001      	beq.n	8007b56 <HAL_UARTEx_ReceiveToIdle_DMA+0x4a>
-      {
-        return  HAL_ERROR;
- 8007b52:	2301      	movs	r3, #1
- 8007b54:	e03e      	b.n	8007bd4 <HAL_UARTEx_ReceiveToIdle_DMA+0xc8>
-      }
-    }
-
-    /* Set Reception type to reception till IDLE Event*/
-    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
- 8007b56:	68fb      	ldr	r3, [r7, #12]
- 8007b58:	2201      	movs	r2, #1
- 8007b5a:	66da      	str	r2, [r3, #108]	@ 0x6c
-    huart->RxEventType = HAL_UART_RXEVENT_TC;
- 8007b5c:	68fb      	ldr	r3, [r7, #12]
- 8007b5e:	2200      	movs	r2, #0
- 8007b60:	671a      	str	r2, [r3, #112]	@ 0x70
-
-    status =  UART_Start_Receive_DMA(huart, pData, Size);
- 8007b62:	2527      	movs	r5, #39	@ 0x27
- 8007b64:	197c      	adds	r4, r7, r5
- 8007b66:	1dbb      	adds	r3, r7, #6
- 8007b68:	881a      	ldrh	r2, [r3, #0]
- 8007b6a:	68b9      	ldr	r1, [r7, #8]
- 8007b6c:	68fb      	ldr	r3, [r7, #12]
- 8007b6e:	0018      	movs	r0, r3
- 8007b70:	f7ff fc1c 	bl	80073ac <UART_Start_Receive_DMA>
- 8007b74:	0003      	movs	r3, r0
- 8007b76:	7023      	strb	r3, [r4, #0]
-
-    /* Check Rx process has been successfully started */
-    if (status == HAL_OK)
- 8007b78:	197b      	adds	r3, r7, r5
- 8007b7a:	781b      	ldrb	r3, [r3, #0]
- 8007b7c:	2b00      	cmp	r3, #0
- 8007b7e:	d124      	bne.n	8007bca <HAL_UARTEx_ReceiveToIdle_DMA+0xbe>
-    {
-      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
- 8007b80:	68fb      	ldr	r3, [r7, #12]
- 8007b82:	6edb      	ldr	r3, [r3, #108]	@ 0x6c
- 8007b84:	2b01      	cmp	r3, #1
- 8007b86:	d11c      	bne.n	8007bc2 <HAL_UARTEx_ReceiveToIdle_DMA+0xb6>
-      {
-        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
- 8007b88:	68fb      	ldr	r3, [r7, #12]
- 8007b8a:	681b      	ldr	r3, [r3, #0]
- 8007b8c:	2210      	movs	r2, #16
- 8007b8e:	621a      	str	r2, [r3, #32]
+ 8004918:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 800491a:	0003      	movs	r3, r0
+  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+ 800491c:	681a      	ldr	r2, [r3, #0]
+ 800491e:	2120      	movs	r1, #32
+ 8004920:	6812      	ldr	r2, [r2, #0]
+  UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent);
+ 8004922:	6a80      	ldr	r0, [r0, #40]	@ 0x28
+  if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC))
+ 8004924:	0014      	movs	r4, r2
+ 8004926:	400c      	ands	r4, r1
+ 8004928:	420a      	tst	r2, r1
+ 800492a:	d134      	bne.n	8004996 <UART_DMAReceiveCplt+0x7e>
+    huart->RxXferCount = 0U;
+ 800492c:	0002      	movs	r2, r0
+ 800492e:	325e      	adds	r2, #94	@ 0x5e
+ 8004930:	8014      	strh	r4, [r2, #0]
   __ASM volatile ("MRS %0, primask" : "=r" (result) );
- 8007b90:	f3ef 8310 	mrs	r3, PRIMASK
- 8007b94:	617b      	str	r3, [r7, #20]
-  return(result);
- 8007b96:	697b      	ldr	r3, [r7, #20]
-        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
- 8007b98:	623b      	str	r3, [r7, #32]
- 8007b9a:	2301      	movs	r3, #1
- 8007b9c:	61bb      	str	r3, [r7, #24]
+ 8004932:	f3ef 8610 	mrs	r6, PRIMASK
   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8007b9e:	69bb      	ldr	r3, [r7, #24]
- 8007ba0:	f383 8810 	msr	PRIMASK, r3
-}
- 8007ba4:	46c0      	nop			@ (mov r8, r8)
- 8007ba6:	68fb      	ldr	r3, [r7, #12]
- 8007ba8:	681b      	ldr	r3, [r3, #0]
- 8007baa:	681a      	ldr	r2, [r3, #0]
- 8007bac:	68fb      	ldr	r3, [r7, #12]
- 8007bae:	681b      	ldr	r3, [r3, #0]
- 8007bb0:	2110      	movs	r1, #16
- 8007bb2:	430a      	orrs	r2, r1
- 8007bb4:	601a      	str	r2, [r3, #0]
- 8007bb6:	6a3b      	ldr	r3, [r7, #32]
- 8007bb8:	61fb      	str	r3, [r7, #28]
+ 8004936:	2201      	movs	r2, #1
+ 8004938:	f382 8810 	msr	PRIMASK, r2
+    ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ 800493c:	6805      	ldr	r5, [r0, #0]
+ 800493e:	4f23      	ldr	r7, [pc, #140]	@ (80049cc <UART_DMAReceiveCplt+0xb4>)
+ 8004940:	682c      	ldr	r4, [r5, #0]
+ 8004942:	403c      	ands	r4, r7
+ 8004944:	602c      	str	r4, [r5, #0]
+ 8004946:	f386 8810 	msr	PRIMASK, r6
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 800494a:	f3ef 8610 	mrs	r6, PRIMASK
   __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
- 8007bba:	69fb      	ldr	r3, [r7, #28]
- 8007bbc:	f383 8810 	msr	PRIMASK, r3
+ 800494e:	f382 8810 	msr	PRIMASK, r2
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8004952:	6805      	ldr	r5, [r0, #0]
+ 8004954:	68ac      	ldr	r4, [r5, #8]
+ 8004956:	4394      	bics	r4, r2
+ 8004958:	60ac      	str	r4, [r5, #8]
+ 800495a:	f386 8810 	msr	PRIMASK, r6
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 800495e:	f3ef 8510 	mrs	r5, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004962:	f382 8810 	msr	PRIMASK, r2
+    ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ 8004966:	2640      	movs	r6, #64	@ 0x40
+ 8004968:	6804      	ldr	r4, [r0, #0]
+ 800496a:	68a2      	ldr	r2, [r4, #8]
+ 800496c:	43b2      	bics	r2, r6
+ 800496e:	60a2      	str	r2, [r4, #8]
+ 8004970:	f385 8810 	msr	PRIMASK, r5
+    huart->RxState = HAL_UART_STATE_READY;
+ 8004974:	0002      	movs	r2, r0
+ 8004976:	328c      	adds	r2, #140	@ 0x8c
+ 8004978:	6011      	str	r1, [r2, #0]
+    if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 800497a:	6ec2      	ldr	r2, [r0, #108]	@ 0x6c
+ 800497c:	2a01      	cmp	r2, #1
+ 800497e:	d10a      	bne.n	8004996 <UART_DMAReceiveCplt+0x7e>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004980:	f3ef 8410 	mrs	r4, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004984:	f382 8810 	msr	PRIMASK, r2
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 8004988:	2510      	movs	r5, #16
+ 800498a:	6801      	ldr	r1, [r0, #0]
+ 800498c:	680a      	ldr	r2, [r1, #0]
+ 800498e:	43aa      	bics	r2, r5
+ 8004990:	600a      	str	r2, [r1, #0]
+ 8004992:	f384 8810 	msr	PRIMASK, r4
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+ 8004996:	2100      	movs	r1, #0
+ 8004998:	6701      	str	r1, [r0, #112]	@ 0x70
+  if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 800499a:	6ec2      	ldr	r2, [r0, #108]	@ 0x6c
+ 800499c:	2a01      	cmp	r2, #1
+ 800499e:	d111      	bne.n	80049c4 <UART_DMAReceiveCplt+0xac>
+    huart->RxXferCount = 0;
+ 80049a0:	0002      	movs	r2, r0
+ 80049a2:	325e      	adds	r2, #94	@ 0x5e
+ 80049a4:	8011      	strh	r1, [r2, #0]
+    if (nb_remaining_rx_data < huart->RxXferSize)
+ 80049a6:	0001      	movs	r1, r0
+    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
+ 80049a8:	681b      	ldr	r3, [r3, #0]
+    if (nb_remaining_rx_data < huart->RxXferSize)
+ 80049aa:	315c      	adds	r1, #92	@ 0x5c
+    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
+ 80049ac:	685b      	ldr	r3, [r3, #4]
+    if (nb_remaining_rx_data < huart->RxXferSize)
+ 80049ae:	8809      	ldrh	r1, [r1, #0]
+    uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma);
+ 80049b0:	b29b      	uxth	r3, r3
+    if (nb_remaining_rx_data < huart->RxXferSize)
+ 80049b2:	4299      	cmp	r1, r3
+ 80049b4:	d900      	bls.n	80049b8 <UART_DMAReceiveCplt+0xa0>
+      huart->RxXferCount = nb_remaining_rx_data;
+ 80049b6:	8013      	strh	r3, [r2, #0]
+    HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount));
+ 80049b8:	8813      	ldrh	r3, [r2, #0]
+ 80049ba:	1ac9      	subs	r1, r1, r3
+ 80049bc:	b289      	uxth	r1, r1
+ 80049be:	f7fc f813 	bl	80009e8 <HAL_UARTEx_RxEventCallback>
 }
- 8007bc0:	e003      	b.n	8007bca <HAL_UARTEx_ReceiveToIdle_DMA+0xbe>
-      {
-        /* In case of errors already pending when reception is started,
-           Interrupts may have already been raised and lead to reception abortion.
-           (Overrun error for instance).
-           In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
-        status = HAL_ERROR;
- 8007bc2:	2327      	movs	r3, #39	@ 0x27
- 8007bc4:	18fb      	adds	r3, r7, r3
- 8007bc6:	2201      	movs	r2, #1
- 8007bc8:	701a      	strb	r2, [r3, #0]
-      }
-    }
+ 80049c2:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+    HAL_UART_RxCpltCallback(huart);
+ 80049c4:	f7ff fdb3 	bl	800452e <HAL_UART_RxCpltCallback>
+}
+ 80049c8:	e7fb      	b.n	80049c2 <UART_DMAReceiveCplt+0xaa>
+ 80049ca:	46c0      	nop			@ (mov r8, r8)
+ 80049cc:	fffffeff 	.word	0xfffffeff
 
-    return status;
- 8007bca:	2327      	movs	r3, #39	@ 0x27
- 8007bcc:	18fb      	adds	r3, r7, r3
- 8007bce:	781b      	ldrb	r3, [r3, #0]
- 8007bd0:	e000      	b.n	8007bd4 <HAL_UARTEx_ReceiveToIdle_DMA+0xc8>
-  }
-  else
-  {
+080049d0 <UART_SetConfig>:
+{
+ 80049d0:	b570      	push	{r4, r5, r6, lr}
+ 80049d2:	0004      	movs	r4, r0
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ 80049d4:	6925      	ldr	r5, [r4, #16]
+ 80049d6:	68a1      	ldr	r1, [r4, #8]
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 80049d8:	6803      	ldr	r3, [r0, #0]
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ 80049da:	4329      	orrs	r1, r5
+ 80049dc:	6965      	ldr	r5, [r4, #20]
+ 80049de:	69c2      	ldr	r2, [r0, #28]
+ 80049e0:	4329      	orrs	r1, r5
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 80049e2:	6818      	ldr	r0, [r3, #0]
+ 80049e4:	4d50      	ldr	r5, [pc, #320]	@ (8004b28 <UART_SetConfig+0x158>)
+  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ;
+ 80049e6:	4311      	orrs	r1, r2
+  MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg);
+ 80049e8:	4028      	ands	r0, r5
+ 80049ea:	4301      	orrs	r1, r0
+ 80049ec:	6019      	str	r1, [r3, #0]
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+ 80049ee:	6859      	ldr	r1, [r3, #4]
+ 80049f0:	484e      	ldr	r0, [pc, #312]	@ (8004b2c <UART_SetConfig+0x15c>)
+  tmpreg |= huart->Init.OneBitSampling;
+ 80049f2:	6a25      	ldr	r5, [r4, #32]
+  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
+ 80049f4:	4001      	ands	r1, r0
+ 80049f6:	68e0      	ldr	r0, [r4, #12]
+ 80049f8:	4301      	orrs	r1, r0
+ 80049fa:	6059      	str	r1, [r3, #4]
+  tmpreg = (uint32_t)huart->Init.HwFlowCtl;
+ 80049fc:	69a1      	ldr	r1, [r4, #24]
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+ 80049fe:	6898      	ldr	r0, [r3, #8]
+  tmpreg |= huart->Init.OneBitSampling;
+ 8004a00:	4329      	orrs	r1, r5
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+ 8004a02:	4d4b      	ldr	r5, [pc, #300]	@ (8004b30 <UART_SetConfig+0x160>)
+ 8004a04:	4028      	ands	r0, r5
+ 8004a06:	4301      	orrs	r1, r0
+  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+ 8004a08:	200f      	movs	r0, #15
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg);
+ 8004a0a:	6099      	str	r1, [r3, #8]
+  MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler);
+ 8004a0c:	6ad9      	ldr	r1, [r3, #44]	@ 0x2c
+ 8004a0e:	4381      	bics	r1, r0
+ 8004a10:	6a60      	ldr	r0, [r4, #36]	@ 0x24
+ 8004a12:	4301      	orrs	r1, r0
+ 8004a14:	62d9      	str	r1, [r3, #44]	@ 0x2c
+  UART_GETCLOCKSOURCE(huart, clocksource);
+ 8004a16:	4947      	ldr	r1, [pc, #284]	@ (8004b34 <UART_SetConfig+0x164>)
+ 8004a18:	428b      	cmp	r3, r1
+ 8004a1a:	d115      	bne.n	8004a48 <UART_SetConfig+0x78>
+ 8004a1c:	2103      	movs	r1, #3
+ 8004a1e:	4b46      	ldr	r3, [pc, #280]	@ (8004b38 <UART_SetConfig+0x168>)
+ 8004a20:	6d5b      	ldr	r3, [r3, #84]	@ 0x54
+ 8004a22:	400b      	ands	r3, r1
+ 8004a24:	3b01      	subs	r3, #1
+ 8004a26:	2b02      	cmp	r3, #2
+ 8004a28:	d86f      	bhi.n	8004b0a <UART_SetConfig+0x13a>
+ 8004a2a:	4944      	ldr	r1, [pc, #272]	@ (8004b3c <UART_SetConfig+0x16c>)
+ 8004a2c:	5cc8      	ldrb	r0, [r1, r3]
+  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ 8004a2e:	2380      	movs	r3, #128	@ 0x80
+ 8004a30:	021b      	lsls	r3, r3, #8
+ 8004a32:	429a      	cmp	r2, r3
+ 8004a34:	d137      	bne.n	8004aa6 <UART_SetConfig+0xd6>
+    switch (clocksource)
+ 8004a36:	2808      	cmp	r0, #8
+ 8004a38:	d865      	bhi.n	8004b06 <UART_SetConfig+0x136>
+ 8004a3a:	f7fb fb65 	bl	8000108 <__gnu_thumb1_case_uqi>
+ 8004a3e:	646a      	.short	0x646a
+ 8004a40:	6431640b 	.word	0x6431640b
+ 8004a44:	6464      	.short	0x6464
+ 8004a46:	14          	.byte	0x14
+ 8004a47:	00          	.byte	0x00
+  UART_GETCLOCKSOURCE(huart, clocksource);
+ 8004a48:	493d      	ldr	r1, [pc, #244]	@ (8004b40 <UART_SetConfig+0x170>)
+ 8004a4a:	185b      	adds	r3, r3, r1
+ 8004a4c:	1e59      	subs	r1, r3, #1
+ 8004a4e:	418b      	sbcs	r3, r1
+ 8004a50:	0118      	lsls	r0, r3, #4
+ 8004a52:	e7ec      	b.n	8004a2e <UART_SetConfig+0x5e>
+        pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ 8004a54:	4b38      	ldr	r3, [pc, #224]	@ (8004b38 <UART_SetConfig+0x168>)
+ 8004a56:	483b      	ldr	r0, [pc, #236]	@ (8004b44 <UART_SetConfig+0x174>)
+ 8004a58:	6819      	ldr	r1, [r3, #0]
+ 8004a5a:	0609      	lsls	r1, r1, #24
+ 8004a5c:	0f49      	lsrs	r1, r1, #29
+ 8004a5e:	3101      	adds	r1, #1
+ 8004a60:	f7fb fb66 	bl	8000130 <__udivsi3>
+ 8004a64:	0002      	movs	r2, r0
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ 8004a66:	6a61      	ldr	r1, [r4, #36]	@ 0x24
+ 8004a68:	4b37      	ldr	r3, [pc, #220]	@ (8004b48 <UART_SetConfig+0x178>)
+ 8004a6a:	0049      	lsls	r1, r1, #1
+ 8004a6c:	0010      	movs	r0, r2
+ 8004a6e:	5ac9      	ldrh	r1, [r1, r3]
+ 8004a70:	f7fb fb5e 	bl	8000130 <__udivsi3>
+ 8004a74:	6865      	ldr	r5, [r4, #4]
+ 8004a76:	0040      	lsls	r0, r0, #1
+ 8004a78:	086b      	lsrs	r3, r5, #1
+ 8004a7a:	18c0      	adds	r0, r0, r3
+ 8004a7c:	0029      	movs	r1, r5
+ 8004a7e:	f7fb fb57 	bl	8000130 <__udivsi3>
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 8004a82:	0002      	movs	r2, r0
+ 8004a84:	4b31      	ldr	r3, [pc, #196]	@ (8004b4c <UART_SetConfig+0x17c>)
+ 8004a86:	3a10      	subs	r2, #16
+ 8004a88:	429a      	cmp	r2, r3
+ 8004a8a:	d83c      	bhi.n	8004b06 <UART_SetConfig+0x136>
+        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ 8004a8c:	230f      	movs	r3, #15
+ 8004a8e:	0002      	movs	r2, r0
+        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 8004a90:	0700      	lsls	r0, r0, #28
+        brrtemp = (uint16_t)(usartdiv & 0xFFF0U);
+ 8004a92:	439a      	bics	r2, r3
+ 8004a94:	b293      	uxth	r3, r2
+        brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);
+ 8004a96:	0f40      	lsrs	r0, r0, #29
+        huart->Instance->BRR = brrtemp;
+ 8004a98:	6822      	ldr	r2, [r4, #0]
+ 8004a9a:	4303      	orrs	r3, r0
+ 8004a9c:	60d3      	str	r3, [r2, #12]
+ 8004a9e:	e03c      	b.n	8004b1a <UART_SetConfig+0x14a>
+        pclk = HAL_RCC_GetSysClockFreq();
+ 8004aa0:	f7fe fd8a 	bl	80035b8 <HAL_RCC_GetSysClockFreq>
+ 8004aa4:	e037      	b.n	8004b16 <UART_SetConfig+0x146>
+    switch (clocksource)
+ 8004aa6:	2808      	cmp	r0, #8
+ 8004aa8:	d82d      	bhi.n	8004b06 <UART_SetConfig+0x136>
+ 8004aaa:	f7fb fb2d 	bl	8000108 <__gnu_thumb1_case_uqi>
+ 8004aae:	2c05      	.short	0x2c05
+ 8004ab0:	2c262c0a 	.word	0x2c262c0a
+ 8004ab4:	2c2c      	.short	0x2c2c
+ 8004ab6:	29          	.byte	0x29
+ 8004ab7:	00          	.byte	0x00
+        pclk = HAL_RCC_GetPCLK1Freq();
+ 8004ab8:	f7fe fe74 	bl	80037a4 <HAL_RCC_GetPCLK1Freq>
+    if (pclk != 0U)
+ 8004abc:	2800      	cmp	r0, #0
+ 8004abe:	d02c      	beq.n	8004b1a <UART_SetConfig+0x14a>
+ 8004ac0:	e007      	b.n	8004ad2 <UART_SetConfig+0x102>
+        pclk = (HSI_VALUE / ((__HAL_RCC_GET_HSIKER_DIVIDER() >> RCC_CR_HSIKERDIV_Pos) + 1U));
+ 8004ac2:	4b1d      	ldr	r3, [pc, #116]	@ (8004b38 <UART_SetConfig+0x168>)
+ 8004ac4:	481f      	ldr	r0, [pc, #124]	@ (8004b44 <UART_SetConfig+0x174>)
+ 8004ac6:	6819      	ldr	r1, [r3, #0]
+ 8004ac8:	0609      	lsls	r1, r1, #24
+ 8004aca:	0f49      	lsrs	r1, r1, #29
+ 8004acc:	3101      	adds	r1, #1
+ 8004ace:	f7fb fb2f 	bl	8000130 <__udivsi3>
+      usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler));
+ 8004ad2:	6a62      	ldr	r2, [r4, #36]	@ 0x24
+ 8004ad4:	4b1c      	ldr	r3, [pc, #112]	@ (8004b48 <UART_SetConfig+0x178>)
+ 8004ad6:	0052      	lsls	r2, r2, #1
+ 8004ad8:	5ad1      	ldrh	r1, [r2, r3]
+ 8004ada:	f7fb fb29 	bl	8000130 <__udivsi3>
+ 8004ade:	6865      	ldr	r5, [r4, #4]
+ 8004ae0:	086b      	lsrs	r3, r5, #1
+ 8004ae2:	18c0      	adds	r0, r0, r3
+ 8004ae4:	0029      	movs	r1, r5
+ 8004ae6:	f7fb fb23 	bl	8000130 <__udivsi3>
+      if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX))
+ 8004aea:	0002      	movs	r2, r0
+ 8004aec:	4b17      	ldr	r3, [pc, #92]	@ (8004b4c <UART_SetConfig+0x17c>)
+ 8004aee:	3a10      	subs	r2, #16
+ 8004af0:	429a      	cmp	r2, r3
+ 8004af2:	d808      	bhi.n	8004b06 <UART_SetConfig+0x136>
+        huart->Instance->BRR = (uint16_t)usartdiv;
+ 8004af4:	6823      	ldr	r3, [r4, #0]
+ 8004af6:	60d8      	str	r0, [r3, #12]
+ 8004af8:	e00f      	b.n	8004b1a <UART_SetConfig+0x14a>
+        pclk = HAL_RCC_GetSysClockFreq();
+ 8004afa:	f7fe fd5d 	bl	80035b8 <HAL_RCC_GetSysClockFreq>
+        break;
+ 8004afe:	e7dd      	b.n	8004abc <UART_SetConfig+0xec>
+    switch (clocksource)
+ 8004b00:	2080      	movs	r0, #128	@ 0x80
+ 8004b02:	0200      	lsls	r0, r0, #8
+ 8004b04:	e7e5      	b.n	8004ad2 <UART_SetConfig+0x102>
+        ret = HAL_ERROR;
+ 8004b06:	2001      	movs	r0, #1
+ 8004b08:	e008      	b.n	8004b1c <UART_SetConfig+0x14c>
+  if (huart->Init.OverSampling == UART_OVERSAMPLING_8)
+ 8004b0a:	2380      	movs	r3, #128	@ 0x80
+ 8004b0c:	021b      	lsls	r3, r3, #8
+ 8004b0e:	429a      	cmp	r2, r3
+ 8004b10:	d1d2      	bne.n	8004ab8 <UART_SetConfig+0xe8>
+        pclk = HAL_RCC_GetPCLK1Freq();
+ 8004b12:	f7fe fe47 	bl	80037a4 <HAL_RCC_GetPCLK1Freq>
+        pclk = HAL_RCC_GetSysClockFreq();
+ 8004b16:	1e02      	subs	r2, r0, #0
+    if (pclk != 0U)
+ 8004b18:	d1a5      	bne.n	8004a66 <UART_SetConfig+0x96>
+    switch (clocksource)
+ 8004b1a:	2000      	movs	r0, #0
+  huart->NbRxDataToProcess = 1;
+ 8004b1c:	4b0c      	ldr	r3, [pc, #48]	@ (8004b50 <UART_SetConfig+0x180>)
+ 8004b1e:	66a3      	str	r3, [r4, #104]	@ 0x68
+  huart->RxISR = NULL;
+ 8004b20:	2300      	movs	r3, #0
+ 8004b22:	6763      	str	r3, [r4, #116]	@ 0x74
+  huart->TxISR = NULL;
+ 8004b24:	67a3      	str	r3, [r4, #120]	@ 0x78
+}
+ 8004b26:	bd70      	pop	{r4, r5, r6, pc}
+ 8004b28:	cfff69f3 	.word	0xcfff69f3
+ 8004b2c:	ffffcfff 	.word	0xffffcfff
+ 8004b30:	11fff4ff 	.word	0x11fff4ff
+ 8004b34:	40013800 	.word	0x40013800
+ 8004b38:	40021000 	.word	0x40021000
+ 8004b3c:	0800528c 	.word	0x0800528c
+ 8004b40:	bfffbc00 	.word	0xbfffbc00
+ 8004b44:	02dc6c00 	.word	0x02dc6c00
+ 8004b48:	08005290 	.word	0x08005290
+ 8004b4c:	0000ffef 	.word	0x0000ffef
+ 8004b50:	00010001 	.word	0x00010001
+
+08004b54 <UART_AdvFeatureConfig>:
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ 8004b54:	6a83      	ldr	r3, [r0, #40]	@ 0x28
+{
+ 8004b56:	b530      	push	{r4, r5, lr}
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
+ 8004b58:	071a      	lsls	r2, r3, #28
+ 8004b5a:	d506      	bpl.n	8004b6a <UART_AdvFeatureConfig+0x16>
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
+ 8004b5c:	6801      	ldr	r1, [r0, #0]
+ 8004b5e:	4c28      	ldr	r4, [pc, #160]	@ (8004c00 <UART_AdvFeatureConfig+0xac>)
+ 8004b60:	684a      	ldr	r2, [r1, #4]
+ 8004b62:	4022      	ands	r2, r4
+ 8004b64:	6b84      	ldr	r4, [r0, #56]	@ 0x38
+ 8004b66:	4322      	orrs	r2, r4
+ 8004b68:	604a      	str	r2, [r1, #4]
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
+ 8004b6a:	07da      	lsls	r2, r3, #31
+ 8004b6c:	d506      	bpl.n	8004b7c <UART_AdvFeatureConfig+0x28>
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert);
+ 8004b6e:	6801      	ldr	r1, [r0, #0]
+ 8004b70:	4c24      	ldr	r4, [pc, #144]	@ (8004c04 <UART_AdvFeatureConfig+0xb0>)
+ 8004b72:	684a      	ldr	r2, [r1, #4]
+ 8004b74:	4022      	ands	r2, r4
+ 8004b76:	6ac4      	ldr	r4, [r0, #44]	@ 0x2c
+ 8004b78:	4322      	orrs	r2, r4
+ 8004b7a:	604a      	str	r2, [r1, #4]
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT))
+ 8004b7c:	079a      	lsls	r2, r3, #30
+ 8004b7e:	d506      	bpl.n	8004b8e <UART_AdvFeatureConfig+0x3a>
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert);
+ 8004b80:	6801      	ldr	r1, [r0, #0]
+ 8004b82:	4c21      	ldr	r4, [pc, #132]	@ (8004c08 <UART_AdvFeatureConfig+0xb4>)
+ 8004b84:	684a      	ldr	r2, [r1, #4]
+ 8004b86:	4022      	ands	r2, r4
+ 8004b88:	6b04      	ldr	r4, [r0, #48]	@ 0x30
+ 8004b8a:	4322      	orrs	r2, r4
+ 8004b8c:	604a      	str	r2, [r1, #4]
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT))
+ 8004b8e:	075a      	lsls	r2, r3, #29
+ 8004b90:	d506      	bpl.n	8004ba0 <UART_AdvFeatureConfig+0x4c>
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
+ 8004b92:	6801      	ldr	r1, [r0, #0]
+ 8004b94:	4c1d      	ldr	r4, [pc, #116]	@ (8004c0c <UART_AdvFeatureConfig+0xb8>)
+ 8004b96:	684a      	ldr	r2, [r1, #4]
+ 8004b98:	4022      	ands	r2, r4
+ 8004b9a:	6b44      	ldr	r4, [r0, #52]	@ 0x34
+ 8004b9c:	4322      	orrs	r2, r4
+ 8004b9e:	604a      	str	r2, [r1, #4]
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
+ 8004ba0:	06da      	lsls	r2, r3, #27
+ 8004ba2:	d506      	bpl.n	8004bb2 <UART_AdvFeatureConfig+0x5e>
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable);
+ 8004ba4:	6801      	ldr	r1, [r0, #0]
+ 8004ba6:	4c1a      	ldr	r4, [pc, #104]	@ (8004c10 <UART_AdvFeatureConfig+0xbc>)
+ 8004ba8:	688a      	ldr	r2, [r1, #8]
+ 8004baa:	4022      	ands	r2, r4
+ 8004bac:	6bc4      	ldr	r4, [r0, #60]	@ 0x3c
+ 8004bae:	4322      	orrs	r2, r4
+ 8004bb0:	608a      	str	r2, [r1, #8]
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT))
+ 8004bb2:	069a      	lsls	r2, r3, #26
+ 8004bb4:	d506      	bpl.n	8004bc4 <UART_AdvFeatureConfig+0x70>
+    MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError);
+ 8004bb6:	6801      	ldr	r1, [r0, #0]
+ 8004bb8:	4c16      	ldr	r4, [pc, #88]	@ (8004c14 <UART_AdvFeatureConfig+0xc0>)
+ 8004bba:	688a      	ldr	r2, [r1, #8]
+ 8004bbc:	4022      	ands	r2, r4
+ 8004bbe:	6c04      	ldr	r4, [r0, #64]	@ 0x40
+ 8004bc0:	4322      	orrs	r2, r4
+ 8004bc2:	608a      	str	r2, [r1, #8]
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT))
+ 8004bc4:	065a      	lsls	r2, r3, #25
+ 8004bc6:	d510      	bpl.n	8004bea <UART_AdvFeatureConfig+0x96>
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable);
+ 8004bc8:	6801      	ldr	r1, [r0, #0]
+ 8004bca:	4d13      	ldr	r5, [pc, #76]	@ (8004c18 <UART_AdvFeatureConfig+0xc4>)
+ 8004bcc:	684a      	ldr	r2, [r1, #4]
+ 8004bce:	6c44      	ldr	r4, [r0, #68]	@ 0x44
+ 8004bd0:	402a      	ands	r2, r5
+ 8004bd2:	4322      	orrs	r2, r4
+ 8004bd4:	604a      	str	r2, [r1, #4]
+    if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)
+ 8004bd6:	2280      	movs	r2, #128	@ 0x80
+ 8004bd8:	0352      	lsls	r2, r2, #13
+ 8004bda:	4294      	cmp	r4, r2
+ 8004bdc:	d105      	bne.n	8004bea <UART_AdvFeatureConfig+0x96>
+      MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode);
+ 8004bde:	684a      	ldr	r2, [r1, #4]
+ 8004be0:	4c0e      	ldr	r4, [pc, #56]	@ (8004c1c <UART_AdvFeatureConfig+0xc8>)
+ 8004be2:	4022      	ands	r2, r4
+ 8004be4:	6c84      	ldr	r4, [r0, #72]	@ 0x48
+ 8004be6:	4322      	orrs	r2, r4
+ 8004be8:	604a      	str	r2, [r1, #4]
+  if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT))
+ 8004bea:	061b      	lsls	r3, r3, #24
+ 8004bec:	d506      	bpl.n	8004bfc <UART_AdvFeatureConfig+0xa8>
+    MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst);
+ 8004bee:	6802      	ldr	r2, [r0, #0]
+ 8004bf0:	490b      	ldr	r1, [pc, #44]	@ (8004c20 <UART_AdvFeatureConfig+0xcc>)
+ 8004bf2:	6853      	ldr	r3, [r2, #4]
+ 8004bf4:	400b      	ands	r3, r1
+ 8004bf6:	6cc1      	ldr	r1, [r0, #76]	@ 0x4c
+ 8004bf8:	430b      	orrs	r3, r1
+ 8004bfa:	6053      	str	r3, [r2, #4]
+}
+ 8004bfc:	bd30      	pop	{r4, r5, pc}
+ 8004bfe:	46c0      	nop			@ (mov r8, r8)
+ 8004c00:	ffff7fff 	.word	0xffff7fff
+ 8004c04:	fffdffff 	.word	0xfffdffff
+ 8004c08:	fffeffff 	.word	0xfffeffff
+ 8004c0c:	fffbffff 	.word	0xfffbffff
+ 8004c10:	ffffefff 	.word	0xffffefff
+ 8004c14:	ffffdfff 	.word	0xffffdfff
+ 8004c18:	ffefffff 	.word	0xffefffff
+ 8004c1c:	ff9fffff 	.word	0xff9fffff
+ 8004c20:	fff7ffff 	.word	0xfff7ffff
+
+08004c24 <UART_WaitOnFlagUntilTimeout>:
+{
+ 8004c24:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+ 8004c26:	0004      	movs	r4, r0
+ 8004c28:	000d      	movs	r5, r1
+ 8004c2a:	0017      	movs	r7, r2
+ 8004c2c:	9300      	str	r3, [sp, #0]
+  while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status)
+ 8004c2e:	6822      	ldr	r2, [r4, #0]
+ 8004c30:	69d3      	ldr	r3, [r2, #28]
+ 8004c32:	402b      	ands	r3, r5
+ 8004c34:	1b5b      	subs	r3, r3, r5
+ 8004c36:	4259      	negs	r1, r3
+ 8004c38:	414b      	adcs	r3, r1
+ 8004c3a:	42bb      	cmp	r3, r7
+ 8004c3c:	d001      	beq.n	8004c42 <UART_WaitOnFlagUntilTimeout+0x1e>
+  return HAL_OK;
+ 8004c3e:	2000      	movs	r0, #0
+ 8004c40:	e026      	b.n	8004c90 <UART_WaitOnFlagUntilTimeout+0x6c>
+    if (Timeout != HAL_MAX_DELAY)
+ 8004c42:	9b08      	ldr	r3, [sp, #32]
+ 8004c44:	3301      	adds	r3, #1
+ 8004c46:	d0f3      	beq.n	8004c30 <UART_WaitOnFlagUntilTimeout+0xc>
+      if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
+ 8004c48:	f7fd fe4a 	bl	80028e0 <HAL_GetTick>
+ 8004c4c:	9b00      	ldr	r3, [sp, #0]
+ 8004c4e:	1ac0      	subs	r0, r0, r3
+ 8004c50:	9b08      	ldr	r3, [sp, #32]
+ 8004c52:	4298      	cmp	r0, r3
+ 8004c54:	d82d      	bhi.n	8004cb2 <UART_WaitOnFlagUntilTimeout+0x8e>
+ 8004c56:	2b00      	cmp	r3, #0
+ 8004c58:	d02b      	beq.n	8004cb2 <UART_WaitOnFlagUntilTimeout+0x8e>
+      if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
+ 8004c5a:	6823      	ldr	r3, [r4, #0]
+ 8004c5c:	681a      	ldr	r2, [r3, #0]
+ 8004c5e:	0752      	lsls	r2, r2, #29
+ 8004c60:	d5e5      	bpl.n	8004c2e <UART_WaitOnFlagUntilTimeout+0xa>
+ 8004c62:	002a      	movs	r2, r5
+ 8004c64:	2140      	movs	r1, #64	@ 0x40
+ 8004c66:	3a40      	subs	r2, #64	@ 0x40
+ 8004c68:	438a      	bics	r2, r1
+ 8004c6a:	d0e0      	beq.n	8004c2e <UART_WaitOnFlagUntilTimeout+0xa>
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
+ 8004c6c:	69da      	ldr	r2, [r3, #28]
+ 8004c6e:	2608      	movs	r6, #8
+ 8004c70:	0011      	movs	r1, r2
+ 8004c72:	4031      	ands	r1, r6
+ 8004c74:	9101      	str	r1, [sp, #4]
+ 8004c76:	4232      	tst	r2, r6
+ 8004c78:	d00b      	beq.n	8004c92 <UART_WaitOnFlagUntilTimeout+0x6e>
+          UART_EndRxTransfer(huart);
+ 8004c7a:	0020      	movs	r0, r4
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
+ 8004c7c:	621e      	str	r6, [r3, #32]
+          UART_EndRxTransfer(huart);
+ 8004c7e:	f7ff fc23 	bl	80044c8 <UART_EndRxTransfer>
+          huart->ErrorCode = HAL_UART_ERROR_ORE;
+ 8004c82:	0023      	movs	r3, r4
+ 8004c84:	3390      	adds	r3, #144	@ 0x90
+ 8004c86:	601e      	str	r6, [r3, #0]
+          __HAL_UNLOCK(huart);
+ 8004c88:	2300      	movs	r3, #0
+          return HAL_ERROR;
+ 8004c8a:	2001      	movs	r0, #1
+          __HAL_UNLOCK(huart);
+ 8004c8c:	3484      	adds	r4, #132	@ 0x84
+ 8004c8e:	7023      	strb	r3, [r4, #0]
+}
+ 8004c90:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+        if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
+ 8004c92:	2280      	movs	r2, #128	@ 0x80
+ 8004c94:	69d9      	ldr	r1, [r3, #28]
+ 8004c96:	0112      	lsls	r2, r2, #4
+ 8004c98:	4211      	tst	r1, r2
+ 8004c9a:	d0c8      	beq.n	8004c2e <UART_WaitOnFlagUntilTimeout+0xa>
+          __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF);
+ 8004c9c:	621a      	str	r2, [r3, #32]
+          UART_EndRxTransfer(huart);
+ 8004c9e:	0020      	movs	r0, r4
+ 8004ca0:	f7ff fc12 	bl	80044c8 <UART_EndRxTransfer>
+          huart->ErrorCode = HAL_UART_ERROR_RTO;
+ 8004ca4:	0023      	movs	r3, r4
+ 8004ca6:	2220      	movs	r2, #32
+ 8004ca8:	3390      	adds	r3, #144	@ 0x90
+ 8004caa:	601a      	str	r2, [r3, #0]
+          __HAL_UNLOCK(huart);
+ 8004cac:	9b01      	ldr	r3, [sp, #4]
+ 8004cae:	3484      	adds	r4, #132	@ 0x84
+ 8004cb0:	7023      	strb	r3, [r4, #0]
+        return HAL_TIMEOUT;
+ 8004cb2:	2003      	movs	r0, #3
+ 8004cb4:	e7ec      	b.n	8004c90 <UART_WaitOnFlagUntilTimeout+0x6c>
+
+08004cb6 <HAL_UART_Transmit>:
+{
+ 8004cb6:	b5f0      	push	{r4, r5, r6, r7, lr}
+ 8004cb8:	0017      	movs	r7, r2
+  if (huart->gState == HAL_UART_STATE_READY)
+ 8004cba:	0002      	movs	r2, r0
+{
+ 8004cbc:	b087      	sub	sp, #28
+  if (huart->gState == HAL_UART_STATE_READY)
+ 8004cbe:	3288      	adds	r2, #136	@ 0x88
+{
+ 8004cc0:	9305      	str	r3, [sp, #20]
+  if (huart->gState == HAL_UART_STATE_READY)
+ 8004cc2:	6813      	ldr	r3, [r2, #0]
+{
+ 8004cc4:	0004      	movs	r4, r0
+ 8004cc6:	000d      	movs	r5, r1
     return HAL_BUSY;
- 8007bd2:	2302      	movs	r3, #2
-  }
+ 8004cc8:	2002      	movs	r0, #2
+  if (huart->gState == HAL_UART_STATE_READY)
+ 8004cca:	2b20      	cmp	r3, #32
+ 8004ccc:	d139      	bne.n	8004d42 <HAL_UART_Transmit+0x8c>
+      return  HAL_ERROR;
+ 8004cce:	3801      	subs	r0, #1
+    if ((pData == NULL) || (Size == 0U))
+ 8004cd0:	2900      	cmp	r1, #0
+ 8004cd2:	d036      	beq.n	8004d42 <HAL_UART_Transmit+0x8c>
+ 8004cd4:	2f00      	cmp	r7, #0
+ 8004cd6:	d034      	beq.n	8004d42 <HAL_UART_Transmit+0x8c>
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ 8004cd8:	2380      	movs	r3, #128	@ 0x80
+ 8004cda:	68a1      	ldr	r1, [r4, #8]
+ 8004cdc:	015b      	lsls	r3, r3, #5
+ 8004cde:	4299      	cmp	r1, r3
+ 8004ce0:	d104      	bne.n	8004cec <HAL_UART_Transmit+0x36>
+ 8004ce2:	6923      	ldr	r3, [r4, #16]
+ 8004ce4:	2b00      	cmp	r3, #0
+ 8004ce6:	d101      	bne.n	8004cec <HAL_UART_Transmit+0x36>
+      if ((((uint32_t)pData) & 1U) != 0U)
+ 8004ce8:	4205      	tst	r5, r0
+ 8004cea:	d12a      	bne.n	8004d42 <HAL_UART_Transmit+0x8c>
+    huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8004cec:	0023      	movs	r3, r4
+ 8004cee:	2600      	movs	r6, #0
+ 8004cf0:	3390      	adds	r3, #144	@ 0x90
+ 8004cf2:	601e      	str	r6, [r3, #0]
+    huart->gState = HAL_UART_STATE_BUSY_TX;
+ 8004cf4:	2321      	movs	r3, #33	@ 0x21
+ 8004cf6:	6013      	str	r3, [r2, #0]
+    tickstart = HAL_GetTick();
+ 8004cf8:	f7fd fdf2 	bl	80028e0 <HAL_GetTick>
+    huart->TxXferSize  = Size;
+ 8004cfc:	0023      	movs	r3, r4
+ 8004cfe:	3354      	adds	r3, #84	@ 0x54
+ 8004d00:	801f      	strh	r7, [r3, #0]
+    huart->TxXferCount = Size;
+ 8004d02:	3302      	adds	r3, #2
+ 8004d04:	9303      	str	r3, [sp, #12]
+ 8004d06:	801f      	strh	r7, [r3, #0]
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ 8004d08:	2380      	movs	r3, #128	@ 0x80
+ 8004d0a:	68a2      	ldr	r2, [r4, #8]
+    tickstart = HAL_GetTick();
+ 8004d0c:	9004      	str	r0, [sp, #16]
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ 8004d0e:	015b      	lsls	r3, r3, #5
+ 8004d10:	429a      	cmp	r2, r3
+ 8004d12:	d104      	bne.n	8004d1e <HAL_UART_Transmit+0x68>
+ 8004d14:	6923      	ldr	r3, [r4, #16]
+ 8004d16:	42b3      	cmp	r3, r6
+ 8004d18:	d101      	bne.n	8004d1e <HAL_UART_Transmit+0x68>
+      pdata16bits = (const uint16_t *) pData;
+ 8004d1a:	002e      	movs	r6, r5
+      pdata8bits  = NULL;
+ 8004d1c:	001d      	movs	r5, r3
+    while (huart->TxXferCount > 0U)
+ 8004d1e:	0023      	movs	r3, r4
+ 8004d20:	3356      	adds	r3, #86	@ 0x56
+ 8004d22:	881b      	ldrh	r3, [r3, #0]
+ 8004d24:	b29a      	uxth	r2, r3
+ 8004d26:	2b00      	cmp	r3, #0
+ 8004d28:	d10d      	bne.n	8004d46 <HAL_UART_Transmit+0x90>
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ 8004d2a:	9b05      	ldr	r3, [sp, #20]
+ 8004d2c:	0020      	movs	r0, r4
+ 8004d2e:	9300      	str	r3, [sp, #0]
+ 8004d30:	2140      	movs	r1, #64	@ 0x40
+ 8004d32:	9b04      	ldr	r3, [sp, #16]
+ 8004d34:	f7ff ff76 	bl	8004c24 <UART_WaitOnFlagUntilTimeout>
+ 8004d38:	2320      	movs	r3, #32
+ 8004d3a:	3488      	adds	r4, #136	@ 0x88
+      huart->gState = HAL_UART_STATE_READY;
+ 8004d3c:	6023      	str	r3, [r4, #0]
+    if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK)
+ 8004d3e:	2800      	cmp	r0, #0
+ 8004d40:	d10e      	bne.n	8004d60 <HAL_UART_Transmit+0xaa>
 }
- 8007bd4:	0018      	movs	r0, r3
- 8007bd6:	46bd      	mov	sp, r7
- 8007bd8:	b00a      	add	sp, #40	@ 0x28
- 8007bda:	bdb0      	pop	{r4, r5, r7, pc}
+ 8004d42:	b007      	add	sp, #28
+ 8004d44:	bdf0      	pop	{r4, r5, r6, r7, pc}
+      if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK)
+ 8004d46:	9b05      	ldr	r3, [sp, #20]
+ 8004d48:	2200      	movs	r2, #0
+ 8004d4a:	9300      	str	r3, [sp, #0]
+ 8004d4c:	2180      	movs	r1, #128	@ 0x80
+ 8004d4e:	0020      	movs	r0, r4
+ 8004d50:	9b04      	ldr	r3, [sp, #16]
+ 8004d52:	f7ff ff67 	bl	8004c24 <UART_WaitOnFlagUntilTimeout>
+ 8004d56:	2800      	cmp	r0, #0
+ 8004d58:	d004      	beq.n	8004d64 <HAL_UART_Transmit+0xae>
+        huart->gState = HAL_UART_STATE_READY;
+ 8004d5a:	2320      	movs	r3, #32
+ 8004d5c:	3488      	adds	r4, #136	@ 0x88
+ 8004d5e:	6023      	str	r3, [r4, #0]
+        return HAL_TIMEOUT;
+ 8004d60:	2003      	movs	r0, #3
+ 8004d62:	e7ee      	b.n	8004d42 <HAL_UART_Transmit+0x8c>
+        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ 8004d64:	6822      	ldr	r2, [r4, #0]
+      if (pdata8bits == NULL)
+ 8004d66:	2d00      	cmp	r5, #0
+ 8004d68:	d10b      	bne.n	8004d82 <HAL_UART_Transmit+0xcc>
+        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ 8004d6a:	8833      	ldrh	r3, [r6, #0]
+        pdata16bits++;
+ 8004d6c:	3602      	adds	r6, #2
+        huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU);
+ 8004d6e:	05db      	lsls	r3, r3, #23
+ 8004d70:	0ddb      	lsrs	r3, r3, #23
+ 8004d72:	6293      	str	r3, [r2, #40]	@ 0x28
+      huart->TxXferCount--;
+ 8004d74:	9b03      	ldr	r3, [sp, #12]
+ 8004d76:	9a03      	ldr	r2, [sp, #12]
+ 8004d78:	881b      	ldrh	r3, [r3, #0]
+ 8004d7a:	3b01      	subs	r3, #1
+ 8004d7c:	b29b      	uxth	r3, r3
+ 8004d7e:	8013      	strh	r3, [r2, #0]
+ 8004d80:	e7cd      	b.n	8004d1e <HAL_UART_Transmit+0x68>
+        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ 8004d82:	782b      	ldrb	r3, [r5, #0]
+        pdata8bits++;
+ 8004d84:	3501      	adds	r5, #1
+        huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU);
+ 8004d86:	6293      	str	r3, [r2, #40]	@ 0x28
+        pdata8bits++;
+ 8004d88:	e7f4      	b.n	8004d74 <HAL_UART_Transmit+0xbe>
+	...
 
-08007bdc <UARTEx_SetNbDataToProcess>:
+08004d8c <UART_CheckIdleState>:
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8004d8c:	0003      	movs	r3, r0
+{
+ 8004d8e:	b573      	push	{r0, r1, r4, r5, r6, lr}
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8004d90:	2600      	movs	r6, #0
+{
+ 8004d92:	0004      	movs	r4, r0
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8004d94:	3390      	adds	r3, #144	@ 0x90
+ 8004d96:	601e      	str	r6, [r3, #0]
+  tickstart = HAL_GetTick();
+ 8004d98:	f7fd fda2 	bl	80028e0 <HAL_GetTick>
+  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ 8004d9c:	6823      	ldr	r3, [r4, #0]
+  tickstart = HAL_GetTick();
+ 8004d9e:	0005      	movs	r5, r0
+  if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE)
+ 8004da0:	681b      	ldr	r3, [r3, #0]
+ 8004da2:	071b      	lsls	r3, r3, #28
+ 8004da4:	d51f      	bpl.n	8004de6 <UART_CheckIdleState+0x5a>
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ 8004da6:	2180      	movs	r1, #128	@ 0x80
+ 8004da8:	4b28      	ldr	r3, [pc, #160]	@ (8004e4c <UART_CheckIdleState+0xc0>)
+ 8004daa:	0032      	movs	r2, r6
+ 8004dac:	9300      	str	r3, [sp, #0]
+ 8004dae:	0389      	lsls	r1, r1, #14
+ 8004db0:	0003      	movs	r3, r0
+ 8004db2:	0020      	movs	r0, r4
+ 8004db4:	f7ff ff36 	bl	8004c24 <UART_WaitOnFlagUntilTimeout>
+ 8004db8:	42b0      	cmp	r0, r6
+ 8004dba:	d014      	beq.n	8004de6 <UART_CheckIdleState+0x5a>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004dbc:	f3ef 8110 	mrs	r1, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004dc0:	2301      	movs	r3, #1
+ 8004dc2:	f383 8810 	msr	PRIMASK, r3
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE));
+ 8004dc6:	2080      	movs	r0, #128	@ 0x80
+ 8004dc8:	6822      	ldr	r2, [r4, #0]
+ 8004dca:	6813      	ldr	r3, [r2, #0]
+ 8004dcc:	4383      	bics	r3, r0
+ 8004dce:	6013      	str	r3, [r2, #0]
+ 8004dd0:	f381 8810 	msr	PRIMASK, r1
+      huart->gState = HAL_UART_STATE_READY;
+ 8004dd4:	0023      	movs	r3, r4
+ 8004dd6:	2220      	movs	r2, #32
+ 8004dd8:	3388      	adds	r3, #136	@ 0x88
+ 8004dda:	601a      	str	r2, [r3, #0]
+      return HAL_TIMEOUT;
+ 8004ddc:	2003      	movs	r0, #3
+      __HAL_UNLOCK(huart);
+ 8004dde:	2300      	movs	r3, #0
+ 8004de0:	3484      	adds	r4, #132	@ 0x84
+ 8004de2:	7023      	strb	r3, [r4, #0]
+}
+ 8004de4:	bd76      	pop	{r1, r2, r4, r5, r6, pc}
+  if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE)
+ 8004de6:	0026      	movs	r6, r4
+ 8004de8:	6823      	ldr	r3, [r4, #0]
+ 8004dea:	368c      	adds	r6, #140	@ 0x8c
+ 8004dec:	681b      	ldr	r3, [r3, #0]
+ 8004dee:	075b      	lsls	r3, r3, #29
+ 8004df0:	d523      	bpl.n	8004e3a <UART_CheckIdleState+0xae>
+    if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK)
+ 8004df2:	2180      	movs	r1, #128	@ 0x80
+ 8004df4:	4b15      	ldr	r3, [pc, #84]	@ (8004e4c <UART_CheckIdleState+0xc0>)
+ 8004df6:	2200      	movs	r2, #0
+ 8004df8:	9300      	str	r3, [sp, #0]
+ 8004dfa:	0020      	movs	r0, r4
+ 8004dfc:	002b      	movs	r3, r5
+ 8004dfe:	03c9      	lsls	r1, r1, #15
+ 8004e00:	f7ff ff10 	bl	8004c24 <UART_WaitOnFlagUntilTimeout>
+ 8004e04:	2800      	cmp	r0, #0
+ 8004e06:	d018      	beq.n	8004e3a <UART_CheckIdleState+0xae>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004e08:	f3ef 8010 	mrs	r0, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004e0c:	2201      	movs	r2, #1
+ 8004e0e:	f382 8810 	msr	PRIMASK, r2
+      ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE));
+ 8004e12:	6821      	ldr	r1, [r4, #0]
+ 8004e14:	4d0e      	ldr	r5, [pc, #56]	@ (8004e50 <UART_CheckIdleState+0xc4>)
+ 8004e16:	680b      	ldr	r3, [r1, #0]
+ 8004e18:	402b      	ands	r3, r5
+ 8004e1a:	600b      	str	r3, [r1, #0]
+ 8004e1c:	f380 8810 	msr	PRIMASK, r0
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004e20:	f3ef 8010 	mrs	r0, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004e24:	f382 8810 	msr	PRIMASK, r2
+      ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8004e28:	6821      	ldr	r1, [r4, #0]
+ 8004e2a:	688b      	ldr	r3, [r1, #8]
+ 8004e2c:	4393      	bics	r3, r2
+ 8004e2e:	608b      	str	r3, [r1, #8]
+ 8004e30:	f380 8810 	msr	PRIMASK, r0
+      huart->RxState = HAL_UART_STATE_READY;
+ 8004e34:	2320      	movs	r3, #32
+ 8004e36:	6033      	str	r3, [r6, #0]
+      return HAL_TIMEOUT;
+ 8004e38:	e7d0      	b.n	8004ddc <UART_CheckIdleState+0x50>
+  huart->gState = HAL_UART_STATE_READY;
+ 8004e3a:	0023      	movs	r3, r4
+ 8004e3c:	2220      	movs	r2, #32
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 8004e3e:	2000      	movs	r0, #0
+  huart->gState = HAL_UART_STATE_READY;
+ 8004e40:	3388      	adds	r3, #136	@ 0x88
+ 8004e42:	601a      	str	r2, [r3, #0]
+  huart->RxState = HAL_UART_STATE_READY;
+ 8004e44:	6032      	str	r2, [r6, #0]
+  huart->ReceptionType = HAL_UART_RECEPTION_STANDARD;
+ 8004e46:	66e0      	str	r0, [r4, #108]	@ 0x6c
+  huart->RxEventType = HAL_UART_RXEVENT_TC;
+ 8004e48:	6720      	str	r0, [r4, #112]	@ 0x70
+  return HAL_OK;
+ 8004e4a:	e7c8      	b.n	8004dde <UART_CheckIdleState+0x52>
+ 8004e4c:	01ffffff 	.word	0x01ffffff
+ 8004e50:	fffffedf 	.word	0xfffffedf
+
+08004e54 <HAL_UART_Init>:
+{
+ 8004e54:	b570      	push	{r4, r5, r6, lr}
+ 8004e56:	1e04      	subs	r4, r0, #0
+  if (huart == NULL)
+ 8004e58:	d101      	bne.n	8004e5e <HAL_UART_Init+0xa>
+    return HAL_ERROR;
+ 8004e5a:	2001      	movs	r0, #1
+}
+ 8004e5c:	bd70      	pop	{r4, r5, r6, pc}
+  if (huart->gState == HAL_UART_STATE_RESET)
+ 8004e5e:	0005      	movs	r5, r0
+ 8004e60:	3588      	adds	r5, #136	@ 0x88
+ 8004e62:	682b      	ldr	r3, [r5, #0]
+ 8004e64:	2b00      	cmp	r3, #0
+ 8004e66:	d104      	bne.n	8004e72 <HAL_UART_Init+0x1e>
+    huart->Lock = HAL_UNLOCKED;
+ 8004e68:	0002      	movs	r2, r0
+ 8004e6a:	3284      	adds	r2, #132	@ 0x84
+ 8004e6c:	7013      	strb	r3, [r2, #0]
+    HAL_UART_MspInit(huart);
+ 8004e6e:	f7fd fbdd 	bl	800262c <HAL_UART_MspInit>
+  huart->gState = HAL_UART_STATE_BUSY;
+ 8004e72:	2324      	movs	r3, #36	@ 0x24
+  __HAL_UART_DISABLE(huart);
+ 8004e74:	2101      	movs	r1, #1
+ 8004e76:	6822      	ldr	r2, [r4, #0]
+  huart->gState = HAL_UART_STATE_BUSY;
+ 8004e78:	602b      	str	r3, [r5, #0]
+  __HAL_UART_DISABLE(huart);
+ 8004e7a:	6813      	ldr	r3, [r2, #0]
+ 8004e7c:	438b      	bics	r3, r1
+ 8004e7e:	6013      	str	r3, [r2, #0]
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ 8004e80:	6aa3      	ldr	r3, [r4, #40]	@ 0x28
+ 8004e82:	2b00      	cmp	r3, #0
+ 8004e84:	d002      	beq.n	8004e8c <HAL_UART_Init+0x38>
+    UART_AdvFeatureConfig(huart);
+ 8004e86:	0020      	movs	r0, r4
+ 8004e88:	f7ff fe64 	bl	8004b54 <UART_AdvFeatureConfig>
+  if (UART_SetConfig(huart) == HAL_ERROR)
+ 8004e8c:	0020      	movs	r0, r4
+ 8004e8e:	f7ff fd9f 	bl	80049d0 <UART_SetConfig>
+ 8004e92:	2801      	cmp	r0, #1
+ 8004e94:	d0e1      	beq.n	8004e5a <HAL_UART_Init+0x6>
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ 8004e96:	6823      	ldr	r3, [r4, #0]
+ 8004e98:	4907      	ldr	r1, [pc, #28]	@ (8004eb8 <HAL_UART_Init+0x64>)
+ 8004e9a:	685a      	ldr	r2, [r3, #4]
+  return (UART_CheckIdleState(huart));
+ 8004e9c:	0020      	movs	r0, r4
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ 8004e9e:	400a      	ands	r2, r1
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ 8004ea0:	212a      	movs	r1, #42	@ 0x2a
+  CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));
+ 8004ea2:	605a      	str	r2, [r3, #4]
+  CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));
+ 8004ea4:	689a      	ldr	r2, [r3, #8]
+ 8004ea6:	438a      	bics	r2, r1
+ 8004ea8:	609a      	str	r2, [r3, #8]
+  __HAL_UART_ENABLE(huart);
+ 8004eaa:	2201      	movs	r2, #1
+ 8004eac:	6819      	ldr	r1, [r3, #0]
+ 8004eae:	430a      	orrs	r2, r1
+ 8004eb0:	601a      	str	r2, [r3, #0]
+  return (UART_CheckIdleState(huart));
+ 8004eb2:	f7ff ff6b 	bl	8004d8c <UART_CheckIdleState>
+ 8004eb6:	e7d1      	b.n	8004e5c <HAL_UART_Init+0x8>
+ 8004eb8:	ffffb7ff 	.word	0xffffb7ff
+
+08004ebc <UART_Start_Receive_DMA>:
+{
+ 8004ebc:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8004ebe:	0013      	movs	r3, r2
+  huart->RxXferSize = Size;
+ 8004ec0:	0002      	movs	r2, r0
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8004ec2:	0006      	movs	r6, r0
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 8004ec4:	0005      	movs	r5, r0
+  huart->RxXferSize = Size;
+ 8004ec6:	325c      	adds	r2, #92	@ 0x5c
+  huart->pRxBuffPtr = pData;
+ 8004ec8:	6581      	str	r1, [r0, #88]	@ 0x58
+{
+ 8004eca:	000f      	movs	r7, r1
+  huart->RxXferSize = Size;
+ 8004ecc:	8013      	strh	r3, [r2, #0]
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 8004ece:	2122      	movs	r1, #34	@ 0x22
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8004ed0:	2200      	movs	r2, #0
+ 8004ed2:	3690      	adds	r6, #144	@ 0x90
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 8004ed4:	358c      	adds	r5, #140	@ 0x8c
+  huart->ErrorCode = HAL_UART_ERROR_NONE;
+ 8004ed6:	6032      	str	r2, [r6, #0]
+  huart->RxState = HAL_UART_STATE_BUSY_RX;
+ 8004ed8:	6029      	str	r1, [r5, #0]
+  if (huart->hdmarx != NULL)
+ 8004eda:	1d01      	adds	r1, r0, #4
+{
+ 8004edc:	0004      	movs	r4, r0
+  if (huart->hdmarx != NULL)
+ 8004ede:	6fc8      	ldr	r0, [r1, #124]	@ 0x7c
+ 8004ee0:	4290      	cmp	r0, r2
+ 8004ee2:	d013      	beq.n	8004f0c <UART_Start_Receive_DMA+0x50>
+    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+ 8004ee4:	491d      	ldr	r1, [pc, #116]	@ (8004f5c <UART_Start_Receive_DMA+0xa0>)
+    huart->hdmarx->XferAbortCallback = NULL;
+ 8004ee6:	6382      	str	r2, [r0, #56]	@ 0x38
+    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
+ 8004ee8:	62c1      	str	r1, [r0, #44]	@ 0x2c
+    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+ 8004eea:	491d      	ldr	r1, [pc, #116]	@ (8004f60 <UART_Start_Receive_DMA+0xa4>)
+    if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+ 8004eec:	003a      	movs	r2, r7
+    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
+ 8004eee:	6301      	str	r1, [r0, #48]	@ 0x30
+    huart->hdmarx->XferErrorCallback = UART_DMAError;
+ 8004ef0:	491c      	ldr	r1, [pc, #112]	@ (8004f64 <UART_Start_Receive_DMA+0xa8>)
+ 8004ef2:	6341      	str	r1, [r0, #52]	@ 0x34
+    if (HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, Size) != HAL_OK)
+ 8004ef4:	6821      	ldr	r1, [r4, #0]
+ 8004ef6:	3124      	adds	r1, #36	@ 0x24
+ 8004ef8:	f7fe f838 	bl	8002f6c <HAL_DMA_Start_IT>
+ 8004efc:	2800      	cmp	r0, #0
+ 8004efe:	d005      	beq.n	8004f0c <UART_Start_Receive_DMA+0x50>
+      huart->ErrorCode = HAL_UART_ERROR_DMA;
+ 8004f00:	2310      	movs	r3, #16
+      return HAL_ERROR;
+ 8004f02:	2001      	movs	r0, #1
+      huart->ErrorCode = HAL_UART_ERROR_DMA;
+ 8004f04:	6033      	str	r3, [r6, #0]
+      huart->RxState = HAL_UART_STATE_READY;
+ 8004f06:	18db      	adds	r3, r3, r3
+ 8004f08:	602b      	str	r3, [r5, #0]
+}
+ 8004f0a:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+  if (huart->Init.Parity != UART_PARITY_NONE)
+ 8004f0c:	6923      	ldr	r3, [r4, #16]
+ 8004f0e:	2b00      	cmp	r3, #0
+ 8004f10:	d00b      	beq.n	8004f2a <UART_Start_Receive_DMA+0x6e>
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004f12:	f3ef 8110 	mrs	r1, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004f16:	2301      	movs	r3, #1
+ 8004f18:	f383 8810 	msr	PRIMASK, r3
+    ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE);
+ 8004f1c:	6822      	ldr	r2, [r4, #0]
+ 8004f1e:	33ff      	adds	r3, #255	@ 0xff
+ 8004f20:	6810      	ldr	r0, [r2, #0]
+ 8004f22:	4303      	orrs	r3, r0
+ 8004f24:	6013      	str	r3, [r2, #0]
+ 8004f26:	f381 8810 	msr	PRIMASK, r1
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004f2a:	f3ef 8010 	mrs	r0, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004f2e:	2301      	movs	r3, #1
+ 8004f30:	f383 8810 	msr	PRIMASK, r3
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE);
+ 8004f34:	6821      	ldr	r1, [r4, #0]
+ 8004f36:	688a      	ldr	r2, [r1, #8]
+ 8004f38:	431a      	orrs	r2, r3
+ 8004f3a:	608a      	str	r2, [r1, #8]
+ 8004f3c:	f380 8810 	msr	PRIMASK, r0
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 8004f40:	f3ef 8110 	mrs	r1, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 8004f44:	f383 8810 	msr	PRIMASK, r3
+  ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR);
+ 8004f48:	6822      	ldr	r2, [r4, #0]
+ 8004f4a:	333f      	adds	r3, #63	@ 0x3f
+ 8004f4c:	6890      	ldr	r0, [r2, #8]
+ 8004f4e:	4303      	orrs	r3, r0
+ 8004f50:	6093      	str	r3, [r2, #8]
+ 8004f52:	f381 8810 	msr	PRIMASK, r1
+  return HAL_OK;
+ 8004f56:	2000      	movs	r0, #0
+ 8004f58:	e7d7      	b.n	8004f0a <UART_Start_Receive_DMA+0x4e>
+ 8004f5a:	46c0      	nop			@ (mov r8, r8)
+ 8004f5c:	08004919 	.word	0x08004919
+ 8004f60:	080048dd 	.word	0x080048dd
+ 8004f64:	08004533 	.word	0x08004533
+
+08004f68 <UARTEx_SetNbDataToProcess>:
   *       the UART configuration registers.
   * @param huart UART handle.
   * @retval None
   */
 static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart)
 {
- 8007bdc:	b5f0      	push	{r4, r5, r6, r7, lr}
- 8007bde:	b085      	sub	sp, #20
- 8007be0:	af00      	add	r7, sp, #0
- 8007be2:	6078      	str	r0, [r7, #4]
+ 8004f68:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+ 8004f6a:	0007      	movs	r7, r0
   uint8_t rx_fifo_threshold;
   uint8_t tx_fifo_threshold;
   static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U};
   static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U};
 
   if (huart->FifoMode == UART_FIFOMODE_DISABLE)
- 8007be4:	687b      	ldr	r3, [r7, #4]
- 8007be6:	6e5b      	ldr	r3, [r3, #100]	@ 0x64
- 8007be8:	2b00      	cmp	r3, #0
- 8007bea:	d108      	bne.n	8007bfe <UARTEx_SetNbDataToProcess+0x22>
+ 8004f6c:	6e43      	ldr	r3, [r0, #100]	@ 0x64
+{
+ 8004f6e:	0004      	movs	r4, r0
+ 8004f70:	376a      	adds	r7, #106	@ 0x6a
+  if (huart->FifoMode == UART_FIFOMODE_DISABLE)
+ 8004f72:	2b00      	cmp	r3, #0
+ 8004f74:	d104      	bne.n	8004f80 <UARTEx_SetNbDataToProcess+0x18>
   {
     huart->NbTxDataToProcess = 1U;
- 8007bec:	687b      	ldr	r3, [r7, #4]
- 8007bee:	226a      	movs	r2, #106	@ 0x6a
- 8007bf0:	2101      	movs	r1, #1
- 8007bf2:	5299      	strh	r1, [r3, r2]
+ 8004f76:	2001      	movs	r0, #1
+ 8004f78:	8038      	strh	r0, [r7, #0]
     huart->NbRxDataToProcess = 1U;
- 8007bf4:	687b      	ldr	r3, [r7, #4]
- 8007bf6:	2268      	movs	r2, #104	@ 0x68
- 8007bf8:	2101      	movs	r1, #1
- 8007bfa:	5299      	strh	r1, [r3, r2]
+ 8004f7a:	3468      	adds	r4, #104	@ 0x68
+ 8004f7c:	8020      	strh	r0, [r4, #0]
     huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
                                (uint16_t)denominator[tx_fifo_threshold];
     huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
                                (uint16_t)denominator[rx_fifo_threshold];
   }
 }
- 8007bfc:	e043      	b.n	8007c86 <UARTEx_SetNbDataToProcess+0xaa>
-    rx_fifo_depth = RX_FIFO_DEPTH;
- 8007bfe:	260f      	movs	r6, #15
- 8007c00:	19bb      	adds	r3, r7, r6
- 8007c02:	2208      	movs	r2, #8
- 8007c04:	701a      	strb	r2, [r3, #0]
-    tx_fifo_depth = TX_FIFO_DEPTH;
- 8007c06:	200e      	movs	r0, #14
- 8007c08:	183b      	adds	r3, r7, r0
- 8007c0a:	2208      	movs	r2, #8
- 8007c0c:	701a      	strb	r2, [r3, #0]
+ 8004f7e:	bdf7      	pop	{r0, r1, r2, r4, r5, r6, r7, pc}
     rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
- 8007c0e:	687b      	ldr	r3, [r7, #4]
- 8007c10:	681b      	ldr	r3, [r3, #0]
- 8007c12:	689b      	ldr	r3, [r3, #8]
- 8007c14:	0e5b      	lsrs	r3, r3, #25
- 8007c16:	b2da      	uxtb	r2, r3
- 8007c18:	240d      	movs	r4, #13
- 8007c1a:	193b      	adds	r3, r7, r4
- 8007c1c:	2107      	movs	r1, #7
- 8007c1e:	400a      	ands	r2, r1
- 8007c20:	701a      	strb	r2, [r3, #0]
+ 8004f80:	6803      	ldr	r3, [r0, #0]
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ 8004f82:	4e0b      	ldr	r6, [pc, #44]	@ (8004fb0 <UARTEx_SetNbDataToProcess+0x48>)
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+ 8004f84:	689a      	ldr	r2, [r3, #8]
     tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
- 8007c22:	687b      	ldr	r3, [r7, #4]
- 8007c24:	681b      	ldr	r3, [r3, #0]
- 8007c26:	689b      	ldr	r3, [r3, #8]
- 8007c28:	0f5b      	lsrs	r3, r3, #29
- 8007c2a:	b2da      	uxtb	r2, r3
- 8007c2c:	250c      	movs	r5, #12
- 8007c2e:	197b      	adds	r3, r7, r5
- 8007c30:	2107      	movs	r1, #7
- 8007c32:	400a      	ands	r2, r1
- 8007c34:	701a      	strb	r2, [r3, #0]
-    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
- 8007c36:	183b      	adds	r3, r7, r0
- 8007c38:	781b      	ldrb	r3, [r3, #0]
- 8007c3a:	197a      	adds	r2, r7, r5
- 8007c3c:	7812      	ldrb	r2, [r2, #0]
- 8007c3e:	4914      	ldr	r1, [pc, #80]	@ (8007c90 <UARTEx_SetNbDataToProcess+0xb4>)
- 8007c40:	5c8a      	ldrb	r2, [r1, r2]
- 8007c42:	435a      	muls	r2, r3
- 8007c44:	0010      	movs	r0, r2
+ 8004f86:	689b      	ldr	r3, [r3, #8]
                                (uint16_t)denominator[tx_fifo_threshold];
- 8007c46:	197b      	adds	r3, r7, r5
- 8007c48:	781b      	ldrb	r3, [r3, #0]
- 8007c4a:	4a12      	ldr	r2, [pc, #72]	@ (8007c94 <UARTEx_SetNbDataToProcess+0xb8>)
- 8007c4c:	5cd3      	ldrb	r3, [r2, r3]
+ 8004f88:	4d0a      	ldr	r5, [pc, #40]	@ (8004fb4 <UARTEx_SetNbDataToProcess+0x4c>)
+    tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);
+ 8004f8a:	0f5b      	lsrs	r3, r3, #29
     huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
- 8007c4e:	0019      	movs	r1, r3
- 8007c50:	f7f8 fae4 	bl	800021c <__divsi3>
- 8007c54:	0003      	movs	r3, r0
- 8007c56:	b299      	uxth	r1, r3
- 8007c58:	687b      	ldr	r3, [r7, #4]
- 8007c5a:	226a      	movs	r2, #106	@ 0x6a
- 8007c5c:	5299      	strh	r1, [r3, r2]
+ 8004f8c:	5cf0      	ldrb	r0, [r6, r3]
+                               (uint16_t)denominator[tx_fifo_threshold];
+ 8004f8e:	5ce9      	ldrb	r1, [r5, r3]
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ 8004f90:	00c0      	lsls	r0, r0, #3
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+ 8004f92:	9201      	str	r2, [sp, #4]
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ 8004f94:	f7fb f956 	bl	8000244 <__divsi3>
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+ 8004f98:	9b01      	ldr	r3, [sp, #4]
+    huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) /
+ 8004f9a:	8038      	strh	r0, [r7, #0]
+    rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);
+ 8004f9c:	011b      	lsls	r3, r3, #4
     huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
- 8007c5e:	19bb      	adds	r3, r7, r6
- 8007c60:	781b      	ldrb	r3, [r3, #0]
- 8007c62:	193a      	adds	r2, r7, r4
- 8007c64:	7812      	ldrb	r2, [r2, #0]
- 8007c66:	490a      	ldr	r1, [pc, #40]	@ (8007c90 <UARTEx_SetNbDataToProcess+0xb4>)
- 8007c68:	5c8a      	ldrb	r2, [r1, r2]
- 8007c6a:	435a      	muls	r2, r3
- 8007c6c:	0010      	movs	r0, r2
+ 8004f9e:	0f5b      	lsrs	r3, r3, #29
+ 8004fa0:	5cf0      	ldrb	r0, [r6, r3]
                                (uint16_t)denominator[rx_fifo_threshold];
- 8007c6e:	193b      	adds	r3, r7, r4
- 8007c70:	781b      	ldrb	r3, [r3, #0]
- 8007c72:	4a08      	ldr	r2, [pc, #32]	@ (8007c94 <UARTEx_SetNbDataToProcess+0xb8>)
- 8007c74:	5cd3      	ldrb	r3, [r2, r3]
+ 8004fa2:	5ce9      	ldrb	r1, [r5, r3]
     huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) /
- 8007c76:	0019      	movs	r1, r3
- 8007c78:	f7f8 fad0 	bl	800021c <__divsi3>
- 8007c7c:	0003      	movs	r3, r0
- 8007c7e:	b299      	uxth	r1, r3
- 8007c80:	687b      	ldr	r3, [r7, #4]
- 8007c82:	2268      	movs	r2, #104	@ 0x68
- 8007c84:	5299      	strh	r1, [r3, r2]
+ 8004fa4:	00c0      	lsls	r0, r0, #3
+ 8004fa6:	f7fb f94d 	bl	8000244 <__divsi3>
+ 8004faa:	b280      	uxth	r0, r0
 }
- 8007c86:	46c0      	nop			@ (mov r8, r8)
- 8007c88:	46bd      	mov	sp, r7
- 8007c8a:	b005      	add	sp, #20
- 8007c8c:	bdf0      	pop	{r4, r5, r6, r7, pc}
- 8007c8e:	46c0      	nop			@ (mov r8, r8)
- 8007c90:	08007e7c 	.word	0x08007e7c
- 8007c94:	08007e84 	.word	0x08007e84
+ 8004fac:	e7e5      	b.n	8004f7a <UARTEx_SetNbDataToProcess+0x12>
+ 8004fae:	46c0      	nop			@ (mov r8, r8)
+ 8004fb0:	080052b0 	.word	0x080052b0
+ 8004fb4:	080052a8 	.word	0x080052a8
 
-08007c98 <memcmp>:
- 8007c98:	b530      	push	{r4, r5, lr}
- 8007c9a:	2400      	movs	r4, #0
- 8007c9c:	3901      	subs	r1, #1
- 8007c9e:	42a2      	cmp	r2, r4
- 8007ca0:	d101      	bne.n	8007ca6 <memcmp+0xe>
- 8007ca2:	2000      	movs	r0, #0
- 8007ca4:	e005      	b.n	8007cb2 <memcmp+0x1a>
- 8007ca6:	5d03      	ldrb	r3, [r0, r4]
- 8007ca8:	3401      	adds	r4, #1
- 8007caa:	5d0d      	ldrb	r5, [r1, r4]
- 8007cac:	42ab      	cmp	r3, r5
- 8007cae:	d0f6      	beq.n	8007c9e <memcmp+0x6>
- 8007cb0:	1b58      	subs	r0, r3, r5
- 8007cb2:	bd30      	pop	{r4, r5, pc}
+08004fb8 <HAL_RS485Ex_Init>:
+{
+ 8004fb8:	b5f7      	push	{r0, r1, r2, r4, r5, r6, r7, lr}
+ 8004fba:	0004      	movs	r4, r0
+ 8004fbc:	000e      	movs	r6, r1
+ 8004fbe:	001d      	movs	r5, r3
+ 8004fc0:	9201      	str	r2, [sp, #4]
+  if (huart == NULL)
+ 8004fc2:	2800      	cmp	r0, #0
+ 8004fc4:	d101      	bne.n	8004fca <HAL_RS485Ex_Init+0x12>
+    return HAL_ERROR;
+ 8004fc6:	2001      	movs	r0, #1
+}
+ 8004fc8:	bdfe      	pop	{r1, r2, r3, r4, r5, r6, r7, pc}
+  if (huart->gState == HAL_UART_STATE_RESET)
+ 8004fca:	0007      	movs	r7, r0
+ 8004fcc:	3788      	adds	r7, #136	@ 0x88
+ 8004fce:	683b      	ldr	r3, [r7, #0]
+ 8004fd0:	2b00      	cmp	r3, #0
+ 8004fd2:	d104      	bne.n	8004fde <HAL_RS485Ex_Init+0x26>
+    huart->Lock = HAL_UNLOCKED;
+ 8004fd4:	0002      	movs	r2, r0
+ 8004fd6:	3284      	adds	r2, #132	@ 0x84
+ 8004fd8:	7013      	strb	r3, [r2, #0]
+    HAL_UART_MspInit(huart);
+ 8004fda:	f7fd fb27 	bl	800262c <HAL_UART_MspInit>
+  huart->gState = HAL_UART_STATE_BUSY;
+ 8004fde:	2324      	movs	r3, #36	@ 0x24
+  __HAL_UART_DISABLE(huart);
+ 8004fe0:	2101      	movs	r1, #1
+ 8004fe2:	6822      	ldr	r2, [r4, #0]
+  huart->gState = HAL_UART_STATE_BUSY;
+ 8004fe4:	603b      	str	r3, [r7, #0]
+  __HAL_UART_DISABLE(huart);
+ 8004fe6:	6813      	ldr	r3, [r2, #0]
+ 8004fe8:	438b      	bics	r3, r1
+ 8004fea:	6013      	str	r3, [r2, #0]
+  if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
+ 8004fec:	6aa3      	ldr	r3, [r4, #40]	@ 0x28
+ 8004fee:	2b00      	cmp	r3, #0
+ 8004ff0:	d002      	beq.n	8004ff8 <HAL_RS485Ex_Init+0x40>
+    UART_AdvFeatureConfig(huart);
+ 8004ff2:	0020      	movs	r0, r4
+ 8004ff4:	f7ff fdae 	bl	8004b54 <UART_AdvFeatureConfig>
+  if (UART_SetConfig(huart) == HAL_ERROR)
+ 8004ff8:	0020      	movs	r0, r4
+ 8004ffa:	f7ff fce9 	bl	80049d0 <UART_SetConfig>
+ 8004ffe:	2801      	cmp	r0, #1
+ 8005000:	d0e1      	beq.n	8004fc6 <HAL_RS485Ex_Init+0xe>
+  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+ 8005002:	2280      	movs	r2, #128	@ 0x80
+ 8005004:	6823      	ldr	r3, [r4, #0]
+ 8005006:	01d2      	lsls	r2, r2, #7
+ 8005008:	6899      	ldr	r1, [r3, #8]
+  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ 800500a:	042d      	lsls	r5, r5, #16
+  SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
+ 800500c:	430a      	orrs	r2, r1
+ 800500e:	609a      	str	r2, [r3, #8]
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+ 8005010:	689a      	ldr	r2, [r3, #8]
+ 8005012:	490a      	ldr	r1, [pc, #40]	@ (800503c <HAL_RS485Ex_Init+0x84>)
+  return (UART_CheckIdleState(huart));
+ 8005014:	0020      	movs	r0, r4
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity);
+ 8005016:	400a      	ands	r2, r1
+ 8005018:	4332      	orrs	r2, r6
+ 800501a:	609a      	str	r2, [r3, #8]
+  temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS);
+ 800501c:	9a01      	ldr	r2, [sp, #4]
+ 800501e:	0551      	lsls	r1, r2, #21
+  temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS);
+ 8005020:	430d      	orrs	r5, r1
+  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+ 8005022:	681a      	ldr	r2, [r3, #0]
+ 8005024:	4906      	ldr	r1, [pc, #24]	@ (8005040 <HAL_RS485Ex_Init+0x88>)
+ 8005026:	400a      	ands	r2, r1
+ 8005028:	4315      	orrs	r5, r2
+  __HAL_UART_ENABLE(huart);
+ 800502a:	2201      	movs	r2, #1
+  MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp);
+ 800502c:	601d      	str	r5, [r3, #0]
+  __HAL_UART_ENABLE(huart);
+ 800502e:	6819      	ldr	r1, [r3, #0]
+ 8005030:	430a      	orrs	r2, r1
+ 8005032:	601a      	str	r2, [r3, #0]
+  return (UART_CheckIdleState(huart));
+ 8005034:	f7ff feaa 	bl	8004d8c <UART_CheckIdleState>
+ 8005038:	e7c6      	b.n	8004fc8 <HAL_RS485Ex_Init+0x10>
+ 800503a:	46c0      	nop			@ (mov r8, r8)
+ 800503c:	ffff7fff 	.word	0xffff7fff
+ 8005040:	fc00ffff 	.word	0xfc00ffff
 
-08007cb4 <memset>:
- 8007cb4:	0003      	movs	r3, r0
- 8007cb6:	1882      	adds	r2, r0, r2
- 8007cb8:	4293      	cmp	r3, r2
- 8007cba:	d100      	bne.n	8007cbe <memset+0xa>
- 8007cbc:	4770      	bx	lr
- 8007cbe:	7019      	strb	r1, [r3, #0]
- 8007cc0:	3301      	adds	r3, #1
- 8007cc2:	e7f9      	b.n	8007cb8 <memset+0x4>
+08005044 <HAL_UARTEx_WakeupCallback>:
+}
+ 8005044:	4770      	bx	lr
 
-08007cc4 <__libc_init_array>:
- 8007cc4:	b570      	push	{r4, r5, r6, lr}
- 8007cc6:	2600      	movs	r6, #0
- 8007cc8:	4c0c      	ldr	r4, [pc, #48]	@ (8007cfc <__libc_init_array+0x38>)
- 8007cca:	4d0d      	ldr	r5, [pc, #52]	@ (8007d00 <__libc_init_array+0x3c>)
- 8007ccc:	1b64      	subs	r4, r4, r5
- 8007cce:	10a4      	asrs	r4, r4, #2
- 8007cd0:	42a6      	cmp	r6, r4
- 8007cd2:	d109      	bne.n	8007ce8 <__libc_init_array+0x24>
- 8007cd4:	2600      	movs	r6, #0
- 8007cd6:	f000 f823 	bl	8007d20 <_init>
- 8007cda:	4c0a      	ldr	r4, [pc, #40]	@ (8007d04 <__libc_init_array+0x40>)
- 8007cdc:	4d0a      	ldr	r5, [pc, #40]	@ (8007d08 <__libc_init_array+0x44>)
- 8007cde:	1b64      	subs	r4, r4, r5
- 8007ce0:	10a4      	asrs	r4, r4, #2
- 8007ce2:	42a6      	cmp	r6, r4
- 8007ce4:	d105      	bne.n	8007cf2 <__libc_init_array+0x2e>
- 8007ce6:	bd70      	pop	{r4, r5, r6, pc}
- 8007ce8:	00b3      	lsls	r3, r6, #2
- 8007cea:	58eb      	ldr	r3, [r5, r3]
- 8007cec:	4798      	blx	r3
- 8007cee:	3601      	adds	r6, #1
- 8007cf0:	e7ee      	b.n	8007cd0 <__libc_init_array+0xc>
- 8007cf2:	00b3      	lsls	r3, r6, #2
- 8007cf4:	58eb      	ldr	r3, [r5, r3]
- 8007cf6:	4798      	blx	r3
- 8007cf8:	3601      	adds	r6, #1
- 8007cfa:	e7f2      	b.n	8007ce2 <__libc_init_array+0x1e>
- 8007cfc:	08007e94 	.word	0x08007e94
- 8007d00:	08007e94 	.word	0x08007e94
- 8007d04:	08007e98 	.word	0x08007e98
- 8007d08:	08007e94 	.word	0x08007e94
+08005046 <HAL_UARTEx_RxFifoFullCallback>:
+__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart)
+ 8005046:	4770      	bx	lr
 
-08007d0c <memcpy>:
- 8007d0c:	2300      	movs	r3, #0
- 8007d0e:	b510      	push	{r4, lr}
- 8007d10:	429a      	cmp	r2, r3
- 8007d12:	d100      	bne.n	8007d16 <memcpy+0xa>
- 8007d14:	bd10      	pop	{r4, pc}
- 8007d16:	5ccc      	ldrb	r4, [r1, r3]
- 8007d18:	54c4      	strb	r4, [r0, r3]
- 8007d1a:	3301      	adds	r3, #1
- 8007d1c:	e7f8      	b.n	8007d10 <memcpy+0x4>
+08005048 <HAL_UARTEx_TxFifoEmptyCallback>:
+__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart)
+ 8005048:	4770      	bx	lr
 	...
 
-08007d20 <_init>:
- 8007d20:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 8007d22:	46c0      	nop			@ (mov r8, r8)
- 8007d24:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 8007d26:	bc08      	pop	{r3}
- 8007d28:	469e      	mov	lr, r3
- 8007d2a:	4770      	bx	lr
+0800504c <HAL_UARTEx_DisableFifoMode>:
+{
+ 800504c:	b570      	push	{r4, r5, r6, lr}
+  __HAL_LOCK(huart);
+ 800504e:	0004      	movs	r4, r0
+ 8005050:	3484      	adds	r4, #132	@ 0x84
+ 8005052:	7822      	ldrb	r2, [r4, #0]
+{
+ 8005054:	0003      	movs	r3, r0
+  __HAL_LOCK(huart);
+ 8005056:	2002      	movs	r0, #2
+ 8005058:	2a01      	cmp	r2, #1
+ 800505a:	d011      	beq.n	8005080 <HAL_UARTEx_DisableFifoMode+0x34>
+  huart->gState = HAL_UART_STATE_BUSY;
+ 800505c:	001d      	movs	r5, r3
+ 800505e:	2224      	movs	r2, #36	@ 0x24
+  __HAL_UART_DISABLE(huart);
+ 8005060:	2601      	movs	r6, #1
+  huart->gState = HAL_UART_STATE_BUSY;
+ 8005062:	3588      	adds	r5, #136	@ 0x88
+ 8005064:	602a      	str	r2, [r5, #0]
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+ 8005066:	681a      	ldr	r2, [r3, #0]
+ 8005068:	6811      	ldr	r1, [r2, #0]
+  __HAL_UART_DISABLE(huart);
+ 800506a:	6810      	ldr	r0, [r2, #0]
+ 800506c:	43b0      	bics	r0, r6
+ 800506e:	6010      	str	r0, [r2, #0]
+  CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN);
+ 8005070:	4804      	ldr	r0, [pc, #16]	@ (8005084 <HAL_UARTEx_DisableFifoMode+0x38>)
+ 8005072:	4001      	ands	r1, r0
+  huart->FifoMode = UART_FIFOMODE_DISABLE;
+ 8005074:	2000      	movs	r0, #0
+ 8005076:	6658      	str	r0, [r3, #100]	@ 0x64
+  huart->gState = HAL_UART_STATE_READY;
+ 8005078:	2320      	movs	r3, #32
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 800507a:	6011      	str	r1, [r2, #0]
+  huart->gState = HAL_UART_STATE_READY;
+ 800507c:	602b      	str	r3, [r5, #0]
+  __HAL_UNLOCK(huart);
+ 800507e:	7020      	strb	r0, [r4, #0]
+}
+ 8005080:	bd70      	pop	{r4, r5, r6, pc}
+ 8005082:	46c0      	nop			@ (mov r8, r8)
+ 8005084:	dfffffff 	.word	0xdfffffff
 
-08007d2c <_fini>:
- 8007d2c:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
- 8007d2e:	46c0      	nop			@ (mov r8, r8)
- 8007d30:	bcf8      	pop	{r3, r4, r5, r6, r7}
- 8007d32:	bc08      	pop	{r3}
- 8007d34:	469e      	mov	lr, r3
- 8007d36:	4770      	bx	lr
+08005088 <HAL_UARTEx_SetTxFifoThreshold>:
+{
+ 8005088:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+  __HAL_LOCK(huart);
+ 800508a:	0005      	movs	r5, r0
+ 800508c:	3584      	adds	r5, #132	@ 0x84
+{
+ 800508e:	000b      	movs	r3, r1
+  __HAL_LOCK(huart);
+ 8005090:	7829      	ldrb	r1, [r5, #0]
+ 8005092:	2202      	movs	r2, #2
+ 8005094:	2901      	cmp	r1, #1
+ 8005096:	d015      	beq.n	80050c4 <HAL_UARTEx_SetTxFifoThreshold+0x3c>
+  huart->gState = HAL_UART_STATE_BUSY;
+ 8005098:	0006      	movs	r6, r0
+  __HAL_UART_DISABLE(huart);
+ 800509a:	2101      	movs	r1, #1
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+ 800509c:	6804      	ldr	r4, [r0, #0]
+  huart->gState = HAL_UART_STATE_BUSY;
+ 800509e:	3688      	adds	r6, #136	@ 0x88
+ 80050a0:	3222      	adds	r2, #34	@ 0x22
+ 80050a2:	6032      	str	r2, [r6, #0]
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+ 80050a4:	6827      	ldr	r7, [r4, #0]
+  __HAL_UART_DISABLE(huart);
+ 80050a6:	6822      	ldr	r2, [r4, #0]
+ 80050a8:	438a      	bics	r2, r1
+ 80050aa:	6022      	str	r2, [r4, #0]
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold);
+ 80050ac:	68a1      	ldr	r1, [r4, #8]
+ 80050ae:	00c9      	lsls	r1, r1, #3
+ 80050b0:	08c9      	lsrs	r1, r1, #3
+ 80050b2:	4319      	orrs	r1, r3
+ 80050b4:	60a1      	str	r1, [r4, #8]
+  UARTEx_SetNbDataToProcess(huart);
+ 80050b6:	f7ff ff57 	bl	8004f68 <UARTEx_SetNbDataToProcess>
+  huart->gState = HAL_UART_STATE_READY;
+ 80050ba:	2320      	movs	r3, #32
+  __HAL_UNLOCK(huart);
+ 80050bc:	2200      	movs	r2, #0
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 80050be:	6027      	str	r7, [r4, #0]
+  huart->gState = HAL_UART_STATE_READY;
+ 80050c0:	6033      	str	r3, [r6, #0]
+  __HAL_UNLOCK(huart);
+ 80050c2:	702a      	strb	r2, [r5, #0]
+}
+ 80050c4:	0010      	movs	r0, r2
+ 80050c6:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+
+080050c8 <HAL_UARTEx_SetRxFifoThreshold>:
+{
+ 80050c8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+  __HAL_LOCK(huart);
+ 80050ca:	0005      	movs	r5, r0
+ 80050cc:	3584      	adds	r5, #132	@ 0x84
+{
+ 80050ce:	000a      	movs	r2, r1
+  __HAL_LOCK(huart);
+ 80050d0:	7829      	ldrb	r1, [r5, #0]
+ 80050d2:	2302      	movs	r3, #2
+ 80050d4:	2901      	cmp	r1, #1
+ 80050d6:	d015      	beq.n	8005104 <HAL_UARTEx_SetRxFifoThreshold+0x3c>
+  huart->gState = HAL_UART_STATE_BUSY;
+ 80050d8:	0006      	movs	r6, r0
+  __HAL_UART_DISABLE(huart);
+ 80050da:	2101      	movs	r1, #1
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+ 80050dc:	6804      	ldr	r4, [r0, #0]
+  huart->gState = HAL_UART_STATE_BUSY;
+ 80050de:	3688      	adds	r6, #136	@ 0x88
+ 80050e0:	3322      	adds	r3, #34	@ 0x22
+ 80050e2:	6033      	str	r3, [r6, #0]
+  tmpcr1 = READ_REG(huart->Instance->CR1);
+ 80050e4:	6827      	ldr	r7, [r4, #0]
+  __HAL_UART_DISABLE(huart);
+ 80050e6:	6823      	ldr	r3, [r4, #0]
+ 80050e8:	438b      	bics	r3, r1
+ 80050ea:	6023      	str	r3, [r4, #0]
+  MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold);
+ 80050ec:	68a1      	ldr	r1, [r4, #8]
+ 80050ee:	4b06      	ldr	r3, [pc, #24]	@ (8005108 <HAL_UARTEx_SetRxFifoThreshold+0x40>)
+ 80050f0:	4019      	ands	r1, r3
+ 80050f2:	4311      	orrs	r1, r2
+ 80050f4:	60a1      	str	r1, [r4, #8]
+  UARTEx_SetNbDataToProcess(huart);
+ 80050f6:	f7ff ff37 	bl	8004f68 <UARTEx_SetNbDataToProcess>
+  huart->gState = HAL_UART_STATE_READY;
+ 80050fa:	2320      	movs	r3, #32
+  WRITE_REG(huart->Instance->CR1, tmpcr1);
+ 80050fc:	6027      	str	r7, [r4, #0]
+  huart->gState = HAL_UART_STATE_READY;
+ 80050fe:	6033      	str	r3, [r6, #0]
+  __HAL_UNLOCK(huart);
+ 8005100:	2300      	movs	r3, #0
+ 8005102:	702b      	strb	r3, [r5, #0]
+}
+ 8005104:	0018      	movs	r0, r3
+ 8005106:	bdf8      	pop	{r3, r4, r5, r6, r7, pc}
+ 8005108:	f1ffffff 	.word	0xf1ffffff
+
+0800510c <HAL_UARTEx_ReceiveToIdle_DMA>:
+  if (huart->RxState == HAL_UART_STATE_READY)
+ 800510c:	0003      	movs	r3, r0
+ 800510e:	338c      	adds	r3, #140	@ 0x8c
+ 8005110:	681b      	ldr	r3, [r3, #0]
+{
+ 8005112:	b570      	push	{r4, r5, r6, lr}
+ 8005114:	0004      	movs	r4, r0
+    return HAL_BUSY;
+ 8005116:	2002      	movs	r0, #2
+  if (huart->RxState == HAL_UART_STATE_READY)
+ 8005118:	2b20      	cmp	r3, #32
+ 800511a:	d102      	bne.n	8005122 <HAL_UARTEx_ReceiveToIdle_DMA+0x16>
+    if ((pData == NULL) || (Size == 0U))
+ 800511c:	2900      	cmp	r1, #0
+ 800511e:	d101      	bne.n	8005124 <HAL_UARTEx_ReceiveToIdle_DMA+0x18>
+      return HAL_ERROR;
+ 8005120:	2001      	movs	r0, #1
+}
+ 8005122:	bd70      	pop	{r4, r5, r6, pc}
+    if ((pData == NULL) || (Size == 0U))
+ 8005124:	2a00      	cmp	r2, #0
+ 8005126:	d0fb      	beq.n	8005120 <HAL_UARTEx_ReceiveToIdle_DMA+0x14>
+    if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE))
+ 8005128:	2080      	movs	r0, #128	@ 0x80
+ 800512a:	68a5      	ldr	r5, [r4, #8]
+ 800512c:	2301      	movs	r3, #1
+ 800512e:	0140      	lsls	r0, r0, #5
+ 8005130:	4285      	cmp	r5, r0
+ 8005132:	d104      	bne.n	800513e <HAL_UARTEx_ReceiveToIdle_DMA+0x32>
+ 8005134:	6920      	ldr	r0, [r4, #16]
+ 8005136:	2800      	cmp	r0, #0
+ 8005138:	d101      	bne.n	800513e <HAL_UARTEx_ReceiveToIdle_DMA+0x32>
+      if ((((uint32_t)pData) & 1U) != 0U)
+ 800513a:	4219      	tst	r1, r3
+ 800513c:	d1f0      	bne.n	8005120 <HAL_UARTEx_ReceiveToIdle_DMA+0x14>
+    huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
+ 800513e:	66e3      	str	r3, [r4, #108]	@ 0x6c
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
+ 8005140:	2300      	movs	r3, #0
+    status =  UART_Start_Receive_DMA(huart, pData, Size);
+ 8005142:	0020      	movs	r0, r4
+    huart->RxEventType = HAL_UART_RXEVENT_TC;
+ 8005144:	6723      	str	r3, [r4, #112]	@ 0x70
+    status =  UART_Start_Receive_DMA(huart, pData, Size);
+ 8005146:	f7ff feb9 	bl	8004ebc <UART_Start_Receive_DMA>
+    if (status == HAL_OK)
+ 800514a:	2800      	cmp	r0, #0
+ 800514c:	d1e9      	bne.n	8005122 <HAL_UARTEx_ReceiveToIdle_DMA+0x16>
+      if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
+ 800514e:	6ee2      	ldr	r2, [r4, #108]	@ 0x6c
+ 8005150:	2a01      	cmp	r2, #1
+ 8005152:	d1e5      	bne.n	8005120 <HAL_UARTEx_ReceiveToIdle_DMA+0x14>
+        __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
+ 8005154:	2310      	movs	r3, #16
+ 8005156:	6821      	ldr	r1, [r4, #0]
+ 8005158:	620b      	str	r3, [r1, #32]
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ 800515a:	f3ef 8110 	mrs	r1, PRIMASK
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
+ 800515e:	f382 8810 	msr	PRIMASK, r2
+        ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
+ 8005162:	6822      	ldr	r2, [r4, #0]
+ 8005164:	6814      	ldr	r4, [r2, #0]
+ 8005166:	4323      	orrs	r3, r4
+ 8005168:	6013      	str	r3, [r2, #0]
+ 800516a:	f381 8810 	msr	PRIMASK, r1
+}
+ 800516e:	e7d8      	b.n	8005122 <HAL_UARTEx_ReceiveToIdle_DMA+0x16>
+
+08005170 <memcmp>:
+ 8005170:	b530      	push	{r4, r5, lr}
+ 8005172:	2400      	movs	r4, #0
+ 8005174:	3901      	subs	r1, #1
+ 8005176:	42a2      	cmp	r2, r4
+ 8005178:	d101      	bne.n	800517e <memcmp+0xe>
+ 800517a:	2000      	movs	r0, #0
+ 800517c:	e005      	b.n	800518a <memcmp+0x1a>
+ 800517e:	5d03      	ldrb	r3, [r0, r4]
+ 8005180:	3401      	adds	r4, #1
+ 8005182:	5d0d      	ldrb	r5, [r1, r4]
+ 8005184:	42ab      	cmp	r3, r5
+ 8005186:	d0f6      	beq.n	8005176 <memcmp+0x6>
+ 8005188:	1b58      	subs	r0, r3, r5
+ 800518a:	bd30      	pop	{r4, r5, pc}
+
+0800518c <memset>:
+ 800518c:	0003      	movs	r3, r0
+ 800518e:	1882      	adds	r2, r0, r2
+ 8005190:	4293      	cmp	r3, r2
+ 8005192:	d100      	bne.n	8005196 <memset+0xa>
+ 8005194:	4770      	bx	lr
+ 8005196:	7019      	strb	r1, [r3, #0]
+ 8005198:	3301      	adds	r3, #1
+ 800519a:	e7f9      	b.n	8005190 <memset+0x4>
+
+0800519c <__libc_init_array>:
+ 800519c:	b570      	push	{r4, r5, r6, lr}
+ 800519e:	2600      	movs	r6, #0
+ 80051a0:	4c0c      	ldr	r4, [pc, #48]	@ (80051d4 <__libc_init_array+0x38>)
+ 80051a2:	4d0d      	ldr	r5, [pc, #52]	@ (80051d8 <__libc_init_array+0x3c>)
+ 80051a4:	1b64      	subs	r4, r4, r5
+ 80051a6:	10a4      	asrs	r4, r4, #2
+ 80051a8:	42a6      	cmp	r6, r4
+ 80051aa:	d109      	bne.n	80051c0 <__libc_init_array+0x24>
+ 80051ac:	2600      	movs	r6, #0
+ 80051ae:	f000 f823 	bl	80051f8 <_init>
+ 80051b2:	4c0a      	ldr	r4, [pc, #40]	@ (80051dc <__libc_init_array+0x40>)
+ 80051b4:	4d0a      	ldr	r5, [pc, #40]	@ (80051e0 <__libc_init_array+0x44>)
+ 80051b6:	1b64      	subs	r4, r4, r5
+ 80051b8:	10a4      	asrs	r4, r4, #2
+ 80051ba:	42a6      	cmp	r6, r4
+ 80051bc:	d105      	bne.n	80051ca <__libc_init_array+0x2e>
+ 80051be:	bd70      	pop	{r4, r5, r6, pc}
+ 80051c0:	00b3      	lsls	r3, r6, #2
+ 80051c2:	58eb      	ldr	r3, [r5, r3]
+ 80051c4:	4798      	blx	r3
+ 80051c6:	3601      	adds	r6, #1
+ 80051c8:	e7ee      	b.n	80051a8 <__libc_init_array+0xc>
+ 80051ca:	00b3      	lsls	r3, r6, #2
+ 80051cc:	58eb      	ldr	r3, [r5, r3]
+ 80051ce:	4798      	blx	r3
+ 80051d0:	3601      	adds	r6, #1
+ 80051d2:	e7f2      	b.n	80051ba <__libc_init_array+0x1e>
+ 80051d4:	080052c0 	.word	0x080052c0
+ 80051d8:	080052c0 	.word	0x080052c0
+ 80051dc:	080052c4 	.word	0x080052c4
+ 80051e0:	080052c0 	.word	0x080052c0
+
+080051e4 <memcpy>:
+ 80051e4:	2300      	movs	r3, #0
+ 80051e6:	b510      	push	{r4, lr}
+ 80051e8:	429a      	cmp	r2, r3
+ 80051ea:	d100      	bne.n	80051ee <memcpy+0xa>
+ 80051ec:	bd10      	pop	{r4, pc}
+ 80051ee:	5ccc      	ldrb	r4, [r1, r3]
+ 80051f0:	54c4      	strb	r4, [r0, r3]
+ 80051f2:	3301      	adds	r3, #1
+ 80051f4:	e7f8      	b.n	80051e8 <memcpy+0x4>
+	...
+
+080051f8 <_init>:
+ 80051f8:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 80051fa:	46c0      	nop			@ (mov r8, r8)
+ 80051fc:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 80051fe:	bc08      	pop	{r3}
+ 8005200:	469e      	mov	lr, r3
+ 8005202:	4770      	bx	lr
+
+08005204 <_fini>:
+ 8005204:	b5f8      	push	{r3, r4, r5, r6, r7, lr}
+ 8005206:	46c0      	nop			@ (mov r8, r8)
+ 8005208:	bcf8      	pop	{r3, r4, r5, r6, r7}
+ 800520a:	bc08      	pop	{r3}
+ 800520c:	469e      	mov	lr, r3
+ 800520e:	4770      	bx	lr
diff --git a/code/Debug/feeder_mk2.map b/code/Debug/feeder_mk2.map
index 16181b6..bfb82d7 100644
--- a/code/Debug/feeder_mk2.map
+++ b/code/Debug/feeder_mk2.map
@@ -1,80 +1,84 @@
 Archive member included to satisfy reference by file (symbol)
 
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                               ./Core/Src/main.o (memcmp)
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                               ./Core/Src/syscalls.o (__errno)
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-                              C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-findfp.o) (__retarget_lock_init_recursive)
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                               ./Core/Src/main.o (memcpy)
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-                              C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) (_sbrk_r)
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+C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-sbrkr.o)
+                              C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-mallocr.o) (_sbrk_r)
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+                              ./Core/Src/main.o (__gnu_thumb1_case_uqi)
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+                              ./Core/Src/main.o (__gnu_thumb1_case_uhi)
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                               ./Core/Src/main.o (__aeabi_uidiv)
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                               ./Core/Src/main.o (__aeabi_idiv)
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                               ./Core/Src/main.o (__aeabi_ldivmod)
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                               ./Core/Src/main.o (__aeabi_lmul)
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+                              C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(bpabi.o) (__divdi3)
+C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_clzdi2.o)
+                              C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divdi3.o) (__clzdi2)
+C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_clzsi2.o)
+                              C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_clzdi2.o) (__clzsi2)
 
 Discarded input sections
 
- .text          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o
- .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o
- .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o
- .data          0x00000000        0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o
- .rodata        0x00000000       0x24 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o
- .text          0x00000000       0x80 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
- .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
- .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
- .ARM.extab     0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
- .ARM.exidx     0x00000000       0x10 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
+ .text          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o
+ .data          0x00000000        0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o
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+ .text          0x00000000       0x80 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
+ .ARM.extab     0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
+ .ARM.exidx     0x00000000       0x10 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
  .ARM.attributes
-                0x00000000       0x1b C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
+                0x00000000       0x1b C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
  .group         0x00000000        0xc ./Core/Src/crc.o
  .group         0x00000000        0xc ./Core/Src/crc.o
  .group         0x00000000        0xc ./Core/Src/crc.o
@@ -145,18 +149,37 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/main.o
  .group         0x00000000        0xc ./Core/Src/main.o
  .group         0x00000000        0xc ./Core/Src/main.o
+ .group         0x00000000        0xc ./Core/Src/main.o
+ .group         0x00000000        0xc ./Core/Src/main.o
+ .group         0x00000000        0xc ./Core/Src/main.o
  .text          0x00000000        0x0 ./Core/Src/main.o
  .data          0x00000000        0x0 ./Core/Src/main.o
  .bss           0x00000000        0x0 ./Core/Src/main.o
- .bss.network_buffer_RX
-                0x00000000       0x40 ./Core/Src/main.o
- .bss.vendor_options
-                0x00000000       0x14 ./Core/Src/main.o
+ .text.update_Feeder_Target
+                0x00000000       0x28 ./Core/Src/main.o
+ .text.set_Feeder_PWM
+                0x00000000       0x1c ./Core/Src/main.o
+ .text.peel_motor
+                0x00000000       0x20 ./Core/Src/main.o
+ .text.peel_brake
+                0x00000000        0xc ./Core/Src/main.o
+ .text.tenths_to_counts
+                0x00000000       0x20 ./Core/Src/main.o
+ .text.calculate_expected_feed_time
+                0x00000000       0x22 ./Core/Src/main.o
+ .text.onewire_drive_low
+                0x00000000        0xa ./Core/Src/main.o
+ .text.onewire_release
+                0x00000000        0xa ./Core/Src/main.o
  .data.feed_distance
                 0x00000000        0x1 ./Core/Src/main.o
- .text.update_Feeder_Target
-                0x00000000       0x8c ./Core/Src/main.o
- .debug_macro   0x00000000      0xaae ./Core/Src/main.o
+ .bss.vendor_options
+                0x00000000       0x14 ./Core/Src/main.o
+ .bss.motor_cmd
+                0x00000000        0x4 ./Core/Src/main.o
+ .bss.network_buffer_RX
+                0x00000000       0x40 ./Core/Src/main.o
+ .debug_macro   0x00000000      0xab4 ./Core/Src/main.o
  .debug_macro   0x00000000       0x22 ./Core/Src/main.o
  .debug_macro   0x00000000       0x8e ./Core/Src/main.o
  .debug_macro   0x00000000       0x51 ./Core/Src/main.o
@@ -206,16 +229,21 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/stm32c0xx_hal_msp.o
  .group         0x00000000        0xc ./Core/Src/stm32c0xx_hal_msp.o
  .group         0x00000000        0xc ./Core/Src/stm32c0xx_hal_msp.o
+ .group         0x00000000        0xc ./Core/Src/stm32c0xx_hal_msp.o
+ .group         0x00000000        0xc ./Core/Src/stm32c0xx_hal_msp.o
+ .group         0x00000000        0xc ./Core/Src/stm32c0xx_hal_msp.o
  .text          0x00000000        0x0 ./Core/Src/stm32c0xx_hal_msp.o
  .data          0x00000000        0x0 ./Core/Src/stm32c0xx_hal_msp.o
  .bss           0x00000000        0x0 ./Core/Src/stm32c0xx_hal_msp.o
- .text.HAL_TIM_Base_MspDeInit
-                0x00000000       0xa4 ./Core/Src/stm32c0xx_hal_msp.o
- .text.HAL_TIM_Encoder_MspDeInit
+ .text.HAL_ADC_MspDeInit
                 0x00000000       0x3c ./Core/Src/stm32c0xx_hal_msp.o
+ .text.HAL_TIM_Base_MspDeInit
+                0x00000000       0x7c ./Core/Src/stm32c0xx_hal_msp.o
+ .text.HAL_TIM_Encoder_MspDeInit
+                0x00000000       0x2c ./Core/Src/stm32c0xx_hal_msp.o
  .text.HAL_UART_MspDeInit
-                0x00000000       0x84 ./Core/Src/stm32c0xx_hal_msp.o
- .debug_macro   0x00000000      0xaae ./Core/Src/stm32c0xx_hal_msp.o
+                0x00000000       0x68 ./Core/Src/stm32c0xx_hal_msp.o
+ .debug_macro   0x00000000      0xab4 ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000       0x2e ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000       0x28 ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000       0x22 ./Core/Src/stm32c0xx_hal_msp.o
@@ -232,7 +260,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000       0x6d ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000      0x1f2 ./Core/Src/stm32c0xx_hal_msp.o
- .debug_macro   0x00000000       0xe9 ./Core/Src/stm32c0xx_hal_msp.o
+ .debug_macro   0x00000000       0xef ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000     0x3440 ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000      0x190 ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000       0x5b ./Core/Src/stm32c0xx_hal_msp.o
@@ -245,6 +273,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000       0x43 ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000      0x1f1 ./Core/Src/stm32c0xx_hal_msp.o
+ .debug_macro   0x00000000      0x924 ./Core/Src/stm32c0xx_hal_msp.o
+ .debug_macro   0x00000000      0x5de ./Core/Src/stm32c0xx_hal_msp.o
+ .debug_macro   0x00000000       0x2e ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000      0x1b1 ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000      0x37c ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000       0x28 ./Core/Src/stm32c0xx_hal_msp.o
@@ -256,7 +287,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x67e ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000       0xa6 ./Core/Src/stm32c0xx_hal_msp.o
  .debug_macro   0x00000000      0x42c ./Core/Src/stm32c0xx_hal_msp.o
- .debug_macro   0x00000000       0xac ./Core/Src/stm32c0xx_hal_msp.o
+ .debug_macro   0x00000000       0xc4 ./Core/Src/stm32c0xx_hal_msp.o
+ .group         0x00000000        0xc ./Core/Src/stm32c0xx_it.o
+ .group         0x00000000        0xc ./Core/Src/stm32c0xx_it.o
+ .group         0x00000000        0xc ./Core/Src/stm32c0xx_it.o
  .group         0x00000000        0xc ./Core/Src/stm32c0xx_it.o
  .group         0x00000000        0xc ./Core/Src/stm32c0xx_it.o
  .group         0x00000000        0xc ./Core/Src/stm32c0xx_it.o
@@ -302,7 +336,7 @@ Discarded input sections
  .text          0x00000000        0x0 ./Core/Src/stm32c0xx_it.o
  .data          0x00000000        0x0 ./Core/Src/stm32c0xx_it.o
  .bss           0x00000000        0x0 ./Core/Src/stm32c0xx_it.o
- .debug_macro   0x00000000      0xaae ./Core/Src/stm32c0xx_it.o
+ .debug_macro   0x00000000      0xab4 ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000       0x2e ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000       0x28 ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000       0x22 ./Core/Src/stm32c0xx_it.o
@@ -319,7 +353,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000       0x6d ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000      0x1f2 ./Core/Src/stm32c0xx_it.o
- .debug_macro   0x00000000       0xe9 ./Core/Src/stm32c0xx_it.o
+ .debug_macro   0x00000000       0xef ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000     0x3440 ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000      0x190 ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000       0x5b ./Core/Src/stm32c0xx_it.o
@@ -332,6 +366,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000       0x43 ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000      0x1f1 ./Core/Src/stm32c0xx_it.o
+ .debug_macro   0x00000000      0x924 ./Core/Src/stm32c0xx_it.o
+ .debug_macro   0x00000000      0x5de ./Core/Src/stm32c0xx_it.o
+ .debug_macro   0x00000000       0x2e ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000      0x1b1 ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000      0x37c ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000       0x28 ./Core/Src/stm32c0xx_it.o
@@ -343,7 +380,7 @@ Discarded input sections
  .debug_macro   0x00000000      0x67e ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000       0xa6 ./Core/Src/stm32c0xx_it.o
  .debug_macro   0x00000000      0x42c ./Core/Src/stm32c0xx_it.o
- .debug_macro   0x00000000       0xac ./Core/Src/stm32c0xx_it.o
+ .debug_macro   0x00000000       0xc4 ./Core/Src/stm32c0xx_it.o
  .group         0x00000000        0xc ./Core/Src/syscalls.o
  .group         0x00000000        0xc ./Core/Src/syscalls.o
  .group         0x00000000        0xc ./Core/Src/syscalls.o
@@ -396,35 +433,37 @@ Discarded input sections
  .text          0x00000000        0x0 ./Core/Src/syscalls.o
  .data          0x00000000        0x0 ./Core/Src/syscalls.o
  .bss           0x00000000        0x0 ./Core/Src/syscalls.o
- .bss.__env     0x00000000        0x4 ./Core/Src/syscalls.o
- .data.environ  0x00000000        0x4 ./Core/Src/syscalls.o
  .text.initialise_monitor_handles
-                0x00000000        0xa ./Core/Src/syscalls.o
- .text._getpid  0x00000000        0xc ./Core/Src/syscalls.o
- .text._kill    0x00000000       0x20 ./Core/Src/syscalls.o
- .text._exit    0x00000000       0x1a ./Core/Src/syscalls.o
- .text._read    0x00000000       0x3a ./Core/Src/syscalls.o
- .text._write   0x00000000       0x38 ./Core/Src/syscalls.o
- .text._close   0x00000000       0x14 ./Core/Src/syscalls.o
- .text._fstat   0x00000000       0x1c ./Core/Src/syscalls.o
- .text._isatty  0x00000000       0x12 ./Core/Src/syscalls.o
- .text._lseek   0x00000000       0x16 ./Core/Src/syscalls.o
- .text._open    0x00000000       0x1c ./Core/Src/syscalls.o
- .text._wait    0x00000000       0x1e ./Core/Src/syscalls.o
- .text._unlink  0x00000000       0x1e ./Core/Src/syscalls.o
- .text._times   0x00000000       0x14 ./Core/Src/syscalls.o
- .text._stat    0x00000000       0x1c ./Core/Src/syscalls.o
- .text._link    0x00000000       0x20 ./Core/Src/syscalls.o
- .text._fork    0x00000000       0x18 ./Core/Src/syscalls.o
- .text._execve  0x00000000       0x22 ./Core/Src/syscalls.o
- .debug_info    0x00000000      0x6a3 ./Core/Src/syscalls.o
- .debug_abbrev  0x00000000      0x1b6 ./Core/Src/syscalls.o
+                0x00000000        0x2 ./Core/Src/syscalls.o
+ .text._getpid  0x00000000        0x4 ./Core/Src/syscalls.o
+ .text._kill    0x00000000       0x10 ./Core/Src/syscalls.o
+ .text._exit    0x00000000        0xc ./Core/Src/syscalls.o
+ .text._read    0x00000000       0x1a ./Core/Src/syscalls.o
+ .text._write   0x00000000       0x1a ./Core/Src/syscalls.o
+ .text._close   0x00000000        0x6 ./Core/Src/syscalls.o
+ .text._fstat   0x00000000        0xa ./Core/Src/syscalls.o
+ .text._isatty  0x00000000        0x4 ./Core/Src/syscalls.o
+ .text._lseek   0x00000000        0x4 ./Core/Src/syscalls.o
+ .text._open    0x00000000        0xa ./Core/Src/syscalls.o
+ .text._wait    0x00000000       0x10 ./Core/Src/syscalls.o
+ .text._unlink  0x00000000       0x10 ./Core/Src/syscalls.o
+ .text._times   0x00000000        0x6 ./Core/Src/syscalls.o
+ .text._stat    0x00000000        0xa ./Core/Src/syscalls.o
+ .text._link    0x00000000       0x10 ./Core/Src/syscalls.o
+ .text._fork    0x00000000       0x10 ./Core/Src/syscalls.o
+ .text._execve  0x00000000       0x10 ./Core/Src/syscalls.o
+ .data.environ  0x00000000        0x4 ./Core/Src/syscalls.o
+ .bss.__env     0x00000000        0x4 ./Core/Src/syscalls.o
+ .debug_info    0x00000000      0x7b5 ./Core/Src/syscalls.o
+ .debug_abbrev  0x00000000      0x208 ./Core/Src/syscalls.o
+ .debug_loclists
+                0x00000000      0x369 ./Core/Src/syscalls.o
  .debug_aranges
                 0x00000000       0xa8 ./Core/Src/syscalls.o
  .debug_rnglists
-                0x00000000       0x79 ./Core/Src/syscalls.o
+                0x00000000       0x85 ./Core/Src/syscalls.o
  .debug_macro   0x00000000      0x274 ./Core/Src/syscalls.o
- .debug_macro   0x00000000      0xaae ./Core/Src/syscalls.o
+ .debug_macro   0x00000000      0xab4 ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x22 ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x5b ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x24 ./Core/Src/syscalls.o
@@ -433,7 +472,7 @@ Discarded input sections
  .debug_macro   0x00000000       0x34 ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x57 ./Core/Src/syscalls.o
  .debug_macro   0x00000000      0x190 ./Core/Src/syscalls.o
- .debug_macro   0x00000000      0x370 ./Core/Src/syscalls.o
+ .debug_macro   0x00000000      0x364 ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x16 ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x4a ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x34 ./Core/Src/syscalls.o
@@ -441,7 +480,7 @@ Discarded input sections
  .debug_macro   0x00000000       0x58 ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x8e ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x1c ./Core/Src/syscalls.o
- .debug_macro   0x00000000      0x185 ./Core/Src/syscalls.o
+ .debug_macro   0x00000000      0x17e ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x10 ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x3c ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x10 ./Core/Src/syscalls.o
@@ -473,10 +512,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x18a ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0x16 ./Core/Src/syscalls.o
  .debug_macro   0x00000000       0xce ./Core/Src/syscalls.o
- .debug_line    0x00000000      0x8b6 ./Core/Src/syscalls.o
- .debug_str     0x00000000     0x98c5 ./Core/Src/syscalls.o
+ .debug_line    0x00000000      0x9bd ./Core/Src/syscalls.o
+ .debug_str     0x00000000     0x9856 ./Core/Src/syscalls.o
  .comment       0x00000000       0x44 ./Core/Src/syscalls.o
- .debug_frame   0x00000000      0x244 ./Core/Src/syscalls.o
+ .debug_frame   0x00000000      0x184 ./Core/Src/syscalls.o
  .ARM.attributes
                 0x00000000       0x2c ./Core/Src/syscalls.o
  .group         0x00000000        0xc ./Core/Src/sysmem.o
@@ -505,17 +544,19 @@ Discarded input sections
  .text          0x00000000        0x0 ./Core/Src/sysmem.o
  .data          0x00000000        0x0 ./Core/Src/sysmem.o
  .bss           0x00000000        0x0 ./Core/Src/sysmem.o
+ .text._sbrk    0x00000000       0x40 ./Core/Src/sysmem.o
  .bss.__sbrk_heap_end
                 0x00000000        0x4 ./Core/Src/sysmem.o
- .text._sbrk    0x00000000       0x6c ./Core/Src/sysmem.o
- .debug_info    0x00000000      0x168 ./Core/Src/sysmem.o
- .debug_abbrev  0x00000000       0xbc ./Core/Src/sysmem.o
+ .debug_info    0x00000000      0x186 ./Core/Src/sysmem.o
+ .debug_abbrev  0x00000000       0xdc ./Core/Src/sysmem.o
+ .debug_loclists
+                0x00000000       0x53 ./Core/Src/sysmem.o
  .debug_aranges
                 0x00000000       0x20 ./Core/Src/sysmem.o
  .debug_rnglists
                 0x00000000       0x13 ./Core/Src/sysmem.o
  .debug_macro   0x00000000      0x112 ./Core/Src/sysmem.o
- .debug_macro   0x00000000      0xaae ./Core/Src/sysmem.o
+ .debug_macro   0x00000000      0xab4 ./Core/Src/sysmem.o
  .debug_macro   0x00000000       0x10 ./Core/Src/sysmem.o
  .debug_macro   0x00000000       0x22 ./Core/Src/sysmem.o
  .debug_macro   0x00000000       0x5b ./Core/Src/sysmem.o
@@ -525,7 +566,7 @@ Discarded input sections
  .debug_macro   0x00000000       0x34 ./Core/Src/sysmem.o
  .debug_macro   0x00000000      0x190 ./Core/Src/sysmem.o
  .debug_macro   0x00000000       0x57 ./Core/Src/sysmem.o
- .debug_macro   0x00000000      0x370 ./Core/Src/sysmem.o
+ .debug_macro   0x00000000      0x364 ./Core/Src/sysmem.o
  .debug_macro   0x00000000       0x16 ./Core/Src/sysmem.o
  .debug_macro   0x00000000       0x4a ./Core/Src/sysmem.o
  .debug_macro   0x00000000       0x34 ./Core/Src/sysmem.o
@@ -533,15 +574,15 @@ Discarded input sections
  .debug_macro   0x00000000       0x58 ./Core/Src/sysmem.o
  .debug_macro   0x00000000       0x8e ./Core/Src/sysmem.o
  .debug_macro   0x00000000       0x1c ./Core/Src/sysmem.o
- .debug_macro   0x00000000      0x185 ./Core/Src/sysmem.o
+ .debug_macro   0x00000000      0x17e ./Core/Src/sysmem.o
  .debug_macro   0x00000000      0x23c ./Core/Src/sysmem.o
  .debug_macro   0x00000000      0x103 ./Core/Src/sysmem.o
  .debug_macro   0x00000000       0x6a ./Core/Src/sysmem.o
  .debug_macro   0x00000000      0x1df ./Core/Src/sysmem.o
- .debug_line    0x00000000      0x592 ./Core/Src/sysmem.o
- .debug_str     0x00000000     0x7663 ./Core/Src/sysmem.o
+ .debug_line    0x00000000      0x5c2 ./Core/Src/sysmem.o
+ .debug_str     0x00000000     0x7600 ./Core/Src/sysmem.o
  .comment       0x00000000       0x44 ./Core/Src/sysmem.o
- .debug_frame   0x00000000       0x30 ./Core/Src/sysmem.o
+ .debug_frame   0x00000000       0x28 ./Core/Src/sysmem.o
  .ARM.attributes
                 0x00000000       0x2c ./Core/Src/sysmem.o
  .group         0x00000000        0xc ./Core/Src/system_stm32c0xx.o
@@ -585,12 +626,15 @@ Discarded input sections
  .group         0x00000000        0xc ./Core/Src/system_stm32c0xx.o
  .group         0x00000000        0xc ./Core/Src/system_stm32c0xx.o
  .group         0x00000000        0xc ./Core/Src/system_stm32c0xx.o
+ .group         0x00000000        0xc ./Core/Src/system_stm32c0xx.o
+ .group         0x00000000        0xc ./Core/Src/system_stm32c0xx.o
+ .group         0x00000000        0xc ./Core/Src/system_stm32c0xx.o
  .text          0x00000000        0x0 ./Core/Src/system_stm32c0xx.o
  .data          0x00000000        0x0 ./Core/Src/system_stm32c0xx.o
  .bss           0x00000000        0x0 ./Core/Src/system_stm32c0xx.o
  .text.SystemCoreClockUpdate
-                0x00000000       0xd0 ./Core/Src/system_stm32c0xx.o
- .debug_macro   0x00000000      0xaae ./Core/Src/system_stm32c0xx.o
+                0x00000000       0x6c ./Core/Src/system_stm32c0xx.o
+ .debug_macro   0x00000000      0xab4 ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000       0x2e ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000       0x28 ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000       0x22 ./Core/Src/system_stm32c0xx.o
@@ -607,7 +651,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000       0x6d ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000      0x1f2 ./Core/Src/system_stm32c0xx.o
- .debug_macro   0x00000000       0xe9 ./Core/Src/system_stm32c0xx.o
+ .debug_macro   0x00000000       0xef ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000     0x3440 ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000      0x190 ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000       0x5b ./Core/Src/system_stm32c0xx.o
@@ -620,6 +664,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000       0x43 ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000      0x1f1 ./Core/Src/system_stm32c0xx.o
+ .debug_macro   0x00000000      0x924 ./Core/Src/system_stm32c0xx.o
+ .debug_macro   0x00000000      0x5de ./Core/Src/system_stm32c0xx.o
+ .debug_macro   0x00000000       0x2e ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000      0x1b1 ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000      0x37c ./Core/Src/system_stm32c0xx.o
  .debug_macro   0x00000000       0x28 ./Core/Src/system_stm32c0xx.o
@@ -675,52 +722,51 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
- .text.LL_SYSCFG_ConfigPinMux
-                0x00000000       0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
- .text.LL_SYSCFG_GetConfigPinMux
-                0x00000000       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
- .text.HAL_DeInit
-                0x00000000       0x4c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_MspInit
-                0x00000000        0xa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_MspDeInit
-                0x00000000        0xa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+ .text.HAL_DeInit
+                0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_GetTickPrio
-                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_SetTickFreq
-                0x00000000       0x58 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_GetTickFreq
-                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_SuspendTick
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_ResumeTick
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_GetHalVersion
-                0x00000000        0xe ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000        0x6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_GetREVID
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_GetDEVID
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_DBGMCU_EnableDBGStopMode
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_DBGMCU_DisableDBGStopMode
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_DBGMCU_EnableDBGStandbyMode
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_DBGMCU_DisableDBGStandbyMode
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_SYSCFG_EnableRemap
-                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_SYSCFG_DisableRemap
-                0x00000000       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_SYSCFG_SetPinBinding
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .text.HAL_SYSCFG_GetPinBinding
-                0x00000000       0x1a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
@@ -737,7 +783,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
@@ -750,6 +796,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
@@ -761,6 +810,280 @@ Discarded input sections
  .debug_macro   0x00000000      0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000       0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .debug_macro   0x00000000      0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
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+ .debug_macro   0x00000000      0x2e2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000       0xb3 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000      0x104 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000       0xf6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000      0xaa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000       0xf1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000      0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000       0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_macro   0x00000000      0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_line    0x00000000      0xc2f ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_str     0x00000000    0x86739 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .comment       0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .debug_frame   0x00000000       0xac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .ARM.attributes
+                0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
@@ -805,47 +1128,35 @@ Discarded input sections
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.__NVIC_DisableIRQ
-                0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.__NVIC_GetPendingIRQ
-                0x00000000       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.__NVIC_SetPendingIRQ
-                0x00000000       0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.__NVIC_ClearPendingIRQ
-                0x00000000       0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.__NVIC_GetPriority
-                0x00000000       0x7c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.__NVIC_SystemReset
-                0x00000000       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .text.HAL_NVIC_DisableIRQ
                 0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .text.HAL_NVIC_SystemReset
-                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.HAL_NVIC_GetPriority
-                0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.HAL_NVIC_SetPendingIRQ
-                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.HAL_NVIC_GetPendingIRQ
-                0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.HAL_NVIC_ClearPendingIRQ
-                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.HAL_SYSTICK_CLKSourceConfig
-                0x00000000       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.HAL_SYSTICK_IRQHandler
-                0x00000000        0xe ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.HAL_SYSTICK_Callback
-                0x00000000        0xa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.HAL_MPU_Enable
-                0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.HAL_MPU_Disable
                 0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .text.HAL_NVIC_GetPriority
+                0x00000000       0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .text.HAL_NVIC_SetPendingIRQ
+                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .text.HAL_NVIC_GetPendingIRQ
+                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .text.HAL_NVIC_ClearPendingIRQ
+                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .text.HAL_SYSTICK_CLKSourceConfig
+                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .text.HAL_SYSTICK_Callback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .text.HAL_SYSTICK_IRQHandler
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .text.HAL_MPU_Enable
+                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .text.HAL_MPU_Disable
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .text.HAL_MPU_EnableRegion
-                0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .text.HAL_MPU_DisableRegion
-                0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .text.HAL_MPU_ConfigRegion
-                0x00000000       0x7c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+                0x00000000       0x4c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
@@ -862,7 +1173,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
@@ -875,6 +1186,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
@@ -927,30 +1241,27 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .text.HAL_DMA_DeInit
-                0x00000000       0xf0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x00000000       0x88 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .text.HAL_DMA_Start
-                0x00000000       0x9a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
- .text.HAL_DMA_Abort
-                0x00000000       0xc4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
- .text.HAL_DMA_Abort_IT
-                0x00000000       0xf4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x00000000       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .text.HAL_DMA_PollForTransfer
-                0x00000000      0x1c8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x00000000      0x11c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .text.HAL_DMA_RegisterCallback
-                0x00000000       0xa0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x00000000       0x42 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .text.HAL_DMA_UnRegisterCallback
-                0x00000000       0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
- .rodata.HAL_DMA_UnRegisterCallback
-                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x00000000       0x50 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .text.HAL_DMA_GetState
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .text.HAL_DMA_GetError
-                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x00000000        0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
@@ -967,7 +1278,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
@@ -980,6 +1291,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
@@ -1032,27 +1346,32 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .text.HAL_DMAEx_ConfigMuxSync
-                0x00000000       0x7c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+                0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .text.HAL_DMAEx_ConfigMuxRequestGenerator
-                0x00000000       0x66 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+                0x00000000       0x36 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .text.HAL_DMAEx_EnableMuxRequestGenerator
-                0x00000000       0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .text.HAL_DMAEx_DisableMuxRequestGenerator
-                0x00000000       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+                0x00000000       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .text.HAL_DMAEx_MUX_IRQHandler
-                0x00000000       0xac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
- .debug_info    0x00000000      0x54b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
- .debug_abbrev  0x00000000      0x112 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+                0x00000000       0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .debug_info    0x00000000      0x58a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .debug_abbrev  0x00000000      0x12e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .debug_loclists
+                0x00000000      0x11a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_aranges
                 0x00000000       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_rnglists
-                0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
- .debug_macro   0x00000000      0x1d0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+                0x00000000       0x2b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .debug_macro   0x00000000      0x1f8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
@@ -1069,7 +1388,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
@@ -1082,6 +1401,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
@@ -1093,10 +1415,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000       0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .debug_macro   0x00000000      0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
- .debug_line    0x00000000      0x900 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
- .debug_str     0x00000000    0x7c927 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .debug_line    0x00000000      0x9d4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .debug_str     0x00000000    0x86301 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .comment       0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
- .debug_frame   0x00000000       0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
+ .debug_frame   0x00000000       0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .ARM.attributes
                 0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
@@ -1140,35 +1462,40 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .text.HAL_EXTI_SetConfigLine
-                0x00000000      0x1a4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+                0x00000000       0xd4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .text.HAL_EXTI_GetConfigLine
-                0x00000000      0x144 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+                0x00000000       0xa4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .text.HAL_EXTI_ClearConfigLine
-                0x00000000      0x11c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
- .text.HAL_EXTI_RegisterCallback
-                0x00000000       0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
- .text.HAL_EXTI_GetHandle
-                0x00000000       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
- .text.HAL_EXTI_IRQHandler
                 0x00000000       0x94 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .text.HAL_EXTI_RegisterCallback
+                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .text.HAL_EXTI_GetHandle
+                0x00000000        0xe ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .text.HAL_EXTI_IRQHandler
+                0x00000000       0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .text.HAL_EXTI_GetPending
-                0x00000000       0x6c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+                0x00000000       0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .text.HAL_EXTI_ClearPending
-                0x00000000       0x5c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+                0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .text.HAL_EXTI_GenerateSWI
-                0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
- .debug_info    0x00000000      0x63f ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
- .debug_abbrev  0x00000000      0x165 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .debug_info    0x00000000      0x70c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .debug_abbrev  0x00000000      0x183 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .debug_loclists
+                0x00000000      0x68b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_aranges
                 0x00000000       0x60 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_rnglists
-                0x00000000       0x47 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
- .debug_macro   0x00000000      0x1dc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+                0x00000000       0x46 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .debug_macro   0x00000000      0x204 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
@@ -1185,7 +1512,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
@@ -1198,6 +1525,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
@@ -1209,10 +1539,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000       0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .debug_macro   0x00000000      0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
- .debug_line    0x00000000      0xb3d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
- .debug_str     0x00000000    0x7c767 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .debug_line    0x00000000      0xdf4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .debug_str     0x00000000    0x86141 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .comment       0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
- .debug_frame   0x00000000      0x130 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
+ .debug_frame   0x00000000       0xf4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .ARM.attributes
                 0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_exti.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
@@ -1256,45 +1586,48 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .bss.pFlash    0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .text.HAL_FLASH_Program
-                0x00000000       0x9c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .text.HAL_FLASH_Program_IT
-                0x00000000       0x98 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .text.HAL_FLASH_IRQHandler
-                0x00000000      0x108 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .RamFunc       0x00000000       0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .text.HAL_FLASH_EndOfOperationCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .text.HAL_FLASH_OperationErrorCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .text.HAL_FLASH_IRQHandler
+                0x00000000       0x98 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .text.HAL_FLASH_Unlock
-                0x00000000       0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+                0x00000000       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .text.HAL_FLASH_Lock
-                0x00000000       0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .text.HAL_FLASH_OB_Unlock
-                0x00000000       0x50 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+                0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .text.HAL_FLASH_OB_Lock
-                0x00000000       0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .text.HAL_FLASH_OB_Launch
-                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .text.HAL_FLASH_GetError
                 0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .text.HAL_FLASH_GetError
+                0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .text.FLASH_WaitForLastOperation
-                0x00000000       0xb4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .text.FLASH_Program_DoubleWord
-                0x00000000       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .RamFunc       0x00000000       0x88 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .debug_info    0x00000000      0x62f ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .debug_abbrev  0x00000000      0x2e3 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+                0x00000000       0x60 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .text.HAL_FLASH_Program
+                0x00000000       0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .text.HAL_FLASH_Program_IT
+                0x00000000       0x6c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .bss.pFlash    0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .debug_info    0x00000000      0x7f0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .debug_abbrev  0x00000000      0x34b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .debug_loclists
+                0x00000000      0x3d8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_aranges
-                0x00000000       0x88 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+                0x00000000       0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_rnglists
-                0x00000000       0x66 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .debug_macro   0x00000000      0x1d0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+                0x00000000       0x5c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .debug_macro   0x00000000      0x1f8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
@@ -1311,7 +1644,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
@@ -1324,6 +1657,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
@@ -1335,10 +1671,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000       0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .debug_macro   0x00000000      0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .debug_line    0x00000000      0xad6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .debug_str     0x00000000    0x7c7fe ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .debug_line    0x00000000      0xce0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .debug_str     0x00000000    0x861d8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .comment       0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
- .debug_frame   0x00000000      0x1d4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
+ .debug_frame   0x00000000      0x130 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .ARM.attributes
                 0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
@@ -1382,63 +1718,44 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.HAL_FLASHEx_Erase
-                0x00000000       0xd4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.HAL_FLASHEx_Erase_IT
-                0x00000000       0x9c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .text.HAL_FLASHEx_OBProgram
-                0x00000000      0x164 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+                0x00000000      0x14c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .text.HAL_FLASHEx_OBGetConfig
-                0x00000000       0x90 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+                0x00000000       0xac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .text.HAL_FLASHEx_EnableDebugger
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .text.HAL_FLASHEx_DisableDebugger
-                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .text.HAL_FLASHEx_FlashEmptyCheck
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .text.HAL_FLASHEx_ForceFlashEmpty
-                0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .text.HAL_FLASHEx_EnableSecMemProtection
-                0x00000000       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.FLASH_MassErase
-                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .text.FLASH_PageErase
-                0x00000000       0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .text.HAL_FLASHEx_Erase
+                0x00000000       0x90 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .text.HAL_FLASHEx_Erase_IT
+                0x00000000       0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .text.FLASH_FlushCaches
-                0x00000000       0x58 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.FLASH_OB_WRPConfig
-                0x00000000       0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.FLASH_OB_OptrConfig
                 0x00000000       0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.FLASH_OB_PCROP1AConfig
-                0x00000000       0x70 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.FLASH_OB_PCROP1BConfig
-                0x00000000       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.FLASH_OB_SecMemConfig
-                0x00000000       0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.FLASH_OB_GetWRP
-                0x00000000       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.FLASH_OB_GetRDP
-                0x00000000       0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.FLASH_OB_GetUser
-                0x00000000       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.FLASH_OB_GetPCROP1A
-                0x00000000       0x78 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.FLASH_OB_GetPCROP1B
-                0x00000000       0x58 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .text.FLASH_OB_GetSecMem
-                0x00000000       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .debug_info    0x00000000      0x86e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .debug_abbrev  0x00000000      0x260 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .debug_info    0x00000000      0xc42 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .debug_abbrev  0x00000000      0x32a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .debug_loclists
+                0x00000000      0x496 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_aranges
-                0x00000000       0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+                0x00000000       0x70 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_rnglists
-                0x00000000       0x9b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .debug_macro   0x00000000      0x1d0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+                0x00000000       0xd2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .debug_macro   0x00000000      0x1f8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
@@ -1455,7 +1772,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
@@ -1468,6 +1785,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
@@ -1479,10 +1799,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000       0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .debug_macro   0x00000000      0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .debug_line    0x00000000      0xc4b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .debug_str     0x00000000    0x7c98e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .debug_line    0x00000000      0xf33 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .debug_str     0x00000000    0x86368 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .comment       0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
- .debug_frame   0x00000000      0x2e8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
+ .debug_frame   0x00000000      0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .ARM.attributes
                 0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_flash_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
@@ -1526,20 +1846,23 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .text.HAL_GPIO_DeInit
-                0x00000000      0x1b0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+                0x00000000       0xf0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .text.HAL_GPIO_WriteMultipleStatePin
-                0x00000000       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .text.HAL_GPIO_TogglePin
-                0x00000000       0x36 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .text.HAL_GPIO_LockPin
-                0x00000000       0x58 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+                0x00000000       0x2a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .text.HAL_GPIO_EXTI_Falling_Callback
-                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
@@ -1556,7 +1879,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
@@ -1569,6 +1892,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
@@ -1621,37 +1947,42 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .text.HAL_PWR_DeInit
-                0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .text.HAL_PWR_EnableWakeUpPin
-                0x00000000       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .text.HAL_PWR_DisableWakeUpPin
-                0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .text.HAL_PWR_EnterSLEEPMode
-                0x00000000       0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .text.HAL_PWR_EnterSTOPMode
-                0x00000000       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
- .text.HAL_PWR_EnterSTANDBYMode
                 0x00000000       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .text.HAL_PWR_EnterSTANDBYMode
+                0x00000000       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .text.HAL_PWR_EnableSleepOnExit
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .text.HAL_PWR_DisableSleepOnExit
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .text.HAL_PWR_EnableSEVOnPend
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .text.HAL_PWR_DisableSEVOnPend
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
- .debug_info    0x00000000      0x556 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
- .debug_abbrev  0x00000000      0x12f ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .debug_info    0x00000000      0x56f ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .debug_abbrev  0x00000000      0x146 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .debug_loclists
+                0x00000000       0xa4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_aranges
                 0x00000000       0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_rnglists
                 0x00000000       0x49 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
- .debug_macro   0x00000000      0x1d0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .debug_macro   0x00000000      0x1f8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
@@ -1668,7 +1999,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
@@ -1681,6 +2012,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
@@ -1692,10 +2026,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000       0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .debug_macro   0x00000000      0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
- .debug_line    0x00000000      0x882 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
- .debug_str     0x00000000    0x7c74c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .debug_line    0x00000000      0x925 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .debug_str     0x00000000    0x86126 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .comment       0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
- .debug_frame   0x00000000      0x138 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
+ .debug_frame   0x00000000       0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .ARM.attributes
                 0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
@@ -1739,51 +2073,48 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_EnableInternalWakeUpLine
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_DisableInternalWakeUpLine
-                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_EnableGPIOPullUp
-                0x00000000       0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
- .rodata.HAL_PWREx_EnableGPIOPullUp
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x6c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_DisableGPIOPullUp
-                0x00000000       0x94 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
- .rodata.HAL_PWREx_DisableGPIOPullUp
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x4c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_EnableGPIOPullDown
-                0x00000000       0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
- .rodata.HAL_PWREx_EnableGPIOPullDown
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x6c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_DisableGPIOPullDown
-                0x00000000       0x94 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
- .rodata.HAL_PWREx_DisableGPIOPullDown
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x4c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_EnablePullUpPullDownConfig
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_DisablePullUpPullDownConfig
-                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_EnableFlashPowerDown
-                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_DisableFlashPowerDown
-                0x00000000       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_EnterSHUTDOWNMode
-                0x00000000       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_BKUPWrite
-                0x00000000       0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .text.HAL_PWREx_BKUPRead
-                0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
- .debug_info    0x00000000      0x53e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
- .debug_abbrev  0x00000000      0x1a4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .debug_info    0x00000000      0x573 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .debug_abbrev  0x00000000      0x1d7 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .debug_loclists
+                0x00000000      0x226 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_aranges
                 0x00000000       0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_rnglists
-                0x00000000       0x5f ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
- .debug_macro   0x00000000      0x1d6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+                0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .debug_macro   0x00000000      0x1fe ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
@@ -1800,7 +2131,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
@@ -1813,6 +2144,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
@@ -1824,10 +2158,10 @@ Discarded input sections
  .debug_macro   0x00000000      0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000       0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .debug_macro   0x00000000      0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
- .debug_line    0x00000000      0x93f ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
- .debug_str     0x00000000    0x7c78a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .debug_line    0x00000000      0xa22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .debug_str     0x00000000    0x86164 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .comment       0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
- .debug_frame   0x00000000      0x19c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
+ .debug_frame   0x00000000      0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .ARM.attributes
                 0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_pwr_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
@@ -1871,34 +2205,33 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
- .text.LL_RCC_ConfigMCO
-                0x00000000       0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
- .text.LL_RCC_ConfigMCO2
-                0x00000000       0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .text.HAL_RCC_DeInit
-                0x00000000      0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x00000000       0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .text.HAL_RCC_MCOConfig
-                0x00000000       0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x00000000       0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .text.HAL_RCC_GetOscConfig
-                0x00000000       0x74 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x00000000       0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .text.HAL_RCC_GetClockConfig
-                0x00000000       0x60 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x00000000       0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .text.HAL_RCC_EnableCSS
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .text.HAL_RCC_EnableLSECSS
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .text.HAL_RCC_DisableLSECSS
-                0x00000000       0x1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
- .text.HAL_RCC_NMI_IRQHandler
-                0x00000000       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .text.HAL_RCC_CSSCallback
-                0x00000000        0xa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .text.HAL_RCC_LSECSSCallback
-                0x00000000        0xa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+ .text.HAL_RCC_NMI_IRQHandler
+                0x00000000       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
@@ -1915,7 +2248,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
@@ -1928,6 +2261,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
@@ -1980,18 +2316,21 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .text.HAL_RCCEx_GetPeriphCLKConfig
-                0x00000000       0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+                0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .text.HAL_RCCEx_GetPeriphCLKFreq
-                0x00000000      0x270 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+                0x00000000      0x144 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .text.HAL_RCCEx_EnableLSCO
-                0x00000000       0x70 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+                0x00000000       0x4c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .text.HAL_RCCEx_DisableLSCO
-                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
@@ -2008,7 +2347,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
@@ -2021,6 +2360,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
@@ -2073,202 +2415,193 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Base_DeInit
-                0x00000000       0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .text.HAL_TIM_Base_MspInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .text.HAL_TIM_Base_MspDeInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Base_Start
-                0x00000000       0x98 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Base_Stop_IT
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Base_DeInit
                 0x00000000       0x5c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Base_Start
+                0x00000000       0x58 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Base_Stop_IT
+                0x00000000       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .text.HAL_TIM_Base_Start_DMA
-                0x00000000      0x118 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x00000000       0xa0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .text.HAL_TIM_Base_Stop_DMA
-                0x00000000       0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OC_Init
-                0x00000000       0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OC_DeInit
-                0x00000000       0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .text.HAL_TIM_OC_MspInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .text.HAL_TIM_OC_MspDeInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OC_Start
-                0x00000000      0x1bc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OC_Stop
-                0x00000000      0x10c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OC_Start_IT
-                0x00000000      0x248 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OC_Stop_IT
-                0x00000000      0x19c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OC_Start_DMA
-                0x00000000      0x3e8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OC_Stop_DMA
-                0x00000000      0x1d4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_PWM_DeInit
-                0x00000000       0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OC_DeInit
+                0x00000000       0x5c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .text.HAL_TIM_PWM_MspDeInit
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_PWM_DeInit
+                0x00000000       0x5c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_MspInit
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_MspDeInit
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_DeInit
+                0x00000000       0x5c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_MspInit
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_MspDeInit
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_DeInit
+                0x00000000       0x50 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_Start
+                0x00000000       0x98 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_Stop
+                0x00000000       0x88 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_Start_IT
+                0x00000000       0xa4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_Stop_IT
+                0x00000000       0x98 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Encoder_MspInit
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Encoder_MspDeInit
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Encoder_DeInit
+                0x00000000       0x50 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Encoder_Stop
+                0x00000000       0x7c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Encoder_Start_IT
+                0x00000000       0xd6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Encoder_Stop_IT
+                0x00000000       0xa8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Encoder_Start_DMA
+                0x00000000      0x1e4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Encoder_Stop_DMA
+                0x00000000       0xcc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_DMABurst_MultiWriteStart
+                0x00000000       0xe4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_DMABurst_WriteStart
+                0x00000000       0x12 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_DMABurst_WriteStop
+                0x00000000       0x74 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_DMABurst_MultiReadStart
+                0x00000000       0xe4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_DMABurst_ReadStart
+                0x00000000       0x12 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_DMABurst_ReadStop
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_GenerateEvent
+                0x00000000       0x26 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_ConfigTI1Input
                 0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_ReadCapturedValue
+                0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_PeriodElapsedCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_DMAPeriodElapsedCplt
+                0x00000000       0x1a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_PeriodElapsedHalfCpltCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_DMAPeriodElapsedHalfCplt
+                0x00000000        0xa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_DMACaptureCplt
+                0x00000000       0x74 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_CaptureHalfCpltCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_DMACaptureHalfCplt
+                0x00000000       0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_DMADelayPulseCplt
+                0x00000000       0x70 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_DMADelayPulseHalfCplt
+                0x00000000       0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_DMATriggerCplt
+                0x00000000       0x1a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_TriggerHalfCpltCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_DMATriggerHalfCplt
+                0x00000000        0xa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_ErrorCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_DMAError
+                0x00000000       0x5c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Base_GetState
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OC_GetState
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_PWM_GetState
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_GetState
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_GetState
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Encoder_GetState
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_GetActiveChannel
+                0x00000000        0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_GetChannelState
+                0x00000000       0x32 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_DMABurstState
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OC_Init
+                0x00000000       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_Init
+                0x00000000       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_Init
+                0x00000000       0x5a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OC_ConfigChannel
+                0x00000000       0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_TI1_SetConfig
+                0x00000000       0x50 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_ConfigChannel
+                0x00000000      0x154 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OnePulse_ConfigChannel
+                0x00000000      0x120 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_ConfigOCrefClear
+                0x00000000      0x12c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_SlaveTimer_SetConfig.constprop.0
+                0x00000000       0xd4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_SlaveConfigSynchro_IT
+                0x00000000       0x4c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_SlaveConfigSynchro
+                0x00000000       0x4c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OC_Stop
+                0x00000000       0x9c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .text.HAL_TIM_PWM_Stop
+                0x00000000        0xa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OC_Start_IT
                 0x00000000      0x10c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .text.HAL_TIM_PWM_Start_IT
-                0x00000000      0x248 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_PWM_Stop_IT
-                0x00000000      0x19c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_PWM_Start_DMA
-                0x00000000      0x3e8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_PWM_Stop_DMA
-                0x00000000      0x1d4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_Init
-                0x00000000       0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_DeInit
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OC_Stop_IT
                 0x00000000       0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_MspInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_MspDeInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_Start
-                0x00000000      0x1d4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_Stop
-                0x00000000       0xe4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_Start_IT
-                0x00000000      0x260 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_Stop_IT
-                0x00000000      0x174 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_Start_DMA
-                0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_Stop_DMA
-                0x00000000      0x1a8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OnePulse_Init
-                0x00000000       0xa2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OnePulse_DeInit
-                0x00000000       0x8c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OnePulse_MspInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OnePulse_MspDeInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OnePulse_Start
+ .text.HAL_TIM_PWM_Stop_IT
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OC_Start_DMA
+                0x00000000      0x1f0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_PWM_Start_DMA
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_OC_Stop_DMA
                 0x00000000       0xec ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OnePulse_Stop
-                0x00000000       0xe0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OnePulse_Start_IT
-                0x00000000      0x10c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OnePulse_Stop_IT
-                0x00000000      0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Encoder_DeInit
-                0x00000000       0x8c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Encoder_MspInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Encoder_MspDeInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Encoder_Stop
-                0x00000000      0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Encoder_Start_IT
-                0x00000000      0x188 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Encoder_Stop_IT
-                0x00000000      0x18c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Encoder_Start_DMA
-                0x00000000      0x35c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Encoder_Stop_DMA
-                0x00000000      0x1bc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OC_ConfigChannel
-                0x00000000       0xc0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .rodata.HAL_TIM_OC_ConfigChannel
-                0x00000000       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_ConfigChannel
-                0x00000000      0x148 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OnePulse_ConfigChannel
-                0x00000000      0x1c8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_DMABurst_WriteStart
-                0x00000000       0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_DMABurst_MultiWriteStart
-                0x00000000      0x2c4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_DMABurst_WriteStop
-                0x00000000      0x11c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_DMABurst_ReadStart
-                0x00000000       0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_DMABurst_MultiReadStart
-                0x00000000      0x2c4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_DMABurst_ReadStop
-                0x00000000      0x11c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_GenerateEvent
-                0x00000000       0x4a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_ConfigOCrefClear
-                0x00000000      0x200 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .rodata.HAL_TIM_ConfigOCrefClear
-                0x00000000       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_ConfigTI1Input
-                0x00000000       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_SlaveConfigSynchro
-                0x00000000       0x8c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_SlaveConfigSynchro_IT
-                0x00000000       0x8c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_ReadCapturedValue
-                0x00000000       0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_PeriodElapsedCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_PeriodElapsedHalfCpltCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_CaptureHalfCpltCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_PWM_PulseFinishedHalfCpltCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_TriggerHalfCpltCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_ErrorCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Base_GetState
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OC_GetState
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_PWM_GetState
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_IC_GetState
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_OnePulse_GetState
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_Encoder_GetState
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_GetActiveChannel
-                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_GetChannelState
-                0x00000000       0x74 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.HAL_TIM_DMABurstState
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_DMAError
-                0x00000000       0x94 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_DMADelayPulseCplt
-                0x00000000       0xaa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_DMADelayPulseHalfCplt
-                0x00000000       0x6a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_DMACaptureCplt
-                0x00000000       0xca ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_DMACaptureHalfCplt
-                0x00000000       0x6a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_DMAPeriodElapsedCplt
-                0x00000000       0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_DMAPeriodElapsedHalfCplt
-                0x00000000       0x1e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_DMATriggerCplt
-                0x00000000       0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_DMATriggerHalfCplt
-                0x00000000       0x1e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_SlaveTimer_SetConfig
-                0x00000000      0x12c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_TI1_SetConfig
-                0x00000000       0xac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_TI2_SetConfig
+ .text.HAL_TIM_PWM_Stop_DMA
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_Start
+                0x00000000       0xe8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_Stop
                 0x00000000       0x84 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_TI3_SetConfig
-                0x00000000       0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_TI4_SetConfig
-                0x00000000       0x8c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_Start_IT
+                0x00000000      0x114 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_Stop_IT
+                0x00000000       0x94 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_Start_DMA
+                0x00000000      0x1d0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_IC_Stop_DMA
+                0x00000000       0xc0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
@@ -2285,7 +2618,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
@@ -2298,6 +2631,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
@@ -2350,96 +2686,99 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_HallSensor_Init
-                0x00000000      0x16c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_HallSensor_DeInit
-                0x00000000       0x8c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_HallSensor_MspInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_HallSensor_MspDeInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_HallSensor_Start
-                0x00000000      0x104 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_HallSensor_Stop
-                0x00000000       0x70 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_HallSensor_Start_IT
-                0x00000000      0x114 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_HallSensor_Stop_IT
-                0x00000000       0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_HallSensor_Start_DMA
-                0x00000000      0x154 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_HallSensor_Stop_DMA
-                0x00000000       0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_OCN_Start
-                0x00000000      0x13c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_OCN_Stop
-                0x00000000       0xb8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_OCN_Start_IT
-                0x00000000      0x1bc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_OCN_Stop_IT
-                0x00000000      0x148 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_OCN_Start_DMA
-                0x00000000      0x2dc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_OCN_Stop_DMA
-                0x00000000      0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_PWMN_Start
-                0x00000000      0x13c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_PWMN_Stop
-                0x00000000       0xb8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_PWMN_Start_IT
-                0x00000000      0x1bc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_PWMN_Stop_IT
-                0x00000000      0x148 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_PWMN_Start_DMA
-                0x00000000      0x2dc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_PWMN_Stop_DMA
-                0x00000000      0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_OnePulseN_Start
-                0x00000000       0xc4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_OnePulseN_Stop
-                0x00000000       0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_OnePulseN_Start_IT
-                0x00000000       0xe4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_OnePulseN_Stop_IT
-                0x00000000       0xdc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_ConfigCommutEvent
-                0x00000000       0xc4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_ConfigCommutEvent_IT
-                0x00000000       0xc4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_ConfigCommutEvent_DMA
-                0x00000000       0xe8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_ConfigBreakInput
-                0x00000000      0x122 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_RemapConfig
-                0x00000000       0x4c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_TISelection
-                0x00000000       0xb4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_GroupChannel5
-                0x00000000       0x62 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_DisarmBreakInput
-                0x00000000       0x9e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_ReArmBreakInput
-                0x00000000       0xda ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_CommutHalfCpltCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_HallSensor_GetState
-                0x00000000       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.HAL_TIMEx_GetChannelNState
-                0x00000000       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.TIMEx_DMACommutationCplt
-                0x00000000       0x26 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.TIMEx_DMACommutationHalfCplt
-                0x00000000       0x26 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.TIM_DMADelayPulseNCplt
-                0x00000000       0x88 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .text.TIM_DMAErrorCCxN
-                0x00000000       0x70 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .text.TIM_CCxNChannelCmd
+                0x00000000       0x1a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.TIM_DMAErrorCCxN
                 0x00000000       0x46 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.TIM_DMADelayPulseNCplt
+                0x00000000       0x58 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_MspInit
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Init
+                0x00000000       0xc8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_MspDeInit
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_DeInit
+                0x00000000       0x50 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Start
+                0x00000000       0xa0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Stop
+                0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Start_IT
+                0x00000000       0xa4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Stop_IT
+                0x00000000       0x4c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Start_DMA
+                0x00000000       0xb8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_Stop_DMA
+                0x00000000       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OCN_Start
+                0x00000000       0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OCN_Stop
+                0x00000000       0x6c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OCN_Start_IT
+                0x00000000       0xa8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OCN_Stop_IT
+                0x00000000       0x90 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OCN_Start_DMA
+                0x00000000      0x15c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OCN_Stop_DMA
+                0x00000000       0xac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_PWMN_Start
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_PWMN_Stop
+                0x00000000        0xa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_PWMN_Start_IT
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_PWMN_Stop_IT
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_PWMN_Start_DMA
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_PWMN_Stop_DMA
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OnePulseN_Start
+                0x00000000       0x82 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OnePulseN_Stop
+                0x00000000       0x70 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OnePulseN_Start_IT
+                0x00000000       0x8e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_OnePulseN_Stop_IT
+                0x00000000       0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_ConfigCommutEvent
+                0x00000000       0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_ConfigCommutEvent_IT
+                0x00000000       0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_ConfigCommutEvent_DMA
+                0x00000000       0x7c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_ConfigBreakInput
+                0x00000000       0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_RemapConfig
+                0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_TISelection
+                0x00000000       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_GroupChannel5
+                0x00000000       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_DisarmBreakInput
+                0x00000000       0x4c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_ReArmBreakInput
+                0x00000000       0x70 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.TIMEx_DMACommutationCplt
+                0x00000000       0x12 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_CommutHalfCpltCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.TIMEx_DMACommutationHalfCplt
+                0x00000000       0x12 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_HallSensor_GetState
+                0x00000000        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .text.HAL_TIMEx_GetChannelNState
+                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
@@ -2456,7 +2795,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
@@ -2469,6 +2808,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
@@ -2521,120 +2863,119 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_HalfDuplex_Init
-                0x00000000       0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_LIN_Init
-                0x00000000       0xf4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_MultiProcessor_Init
-                0x00000000       0xf4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_DeInit
-                0x00000000       0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_MspInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_MspDeInit
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_Receive
-                0x00000000      0x1cc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_Transmit_IT
-                0x00000000      0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_Receive_IT
-                0x00000000       0xae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_Transmit_DMA
-                0x00000000      0x124 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_Receive_DMA
-                0x00000000       0xae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_DMAPause
-                0x00000000      0x118 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_DMAResume
-                0x00000000      0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_DMAStop
-                0x00000000      0x128 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_Abort
-                0x00000000      0x218 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_AbortTransmit
-                0x00000000      0x120 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_AbortReceive
-                0x00000000      0x168 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_Abort_IT
-                0x00000000      0x268 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_AbortTransmit_IT
-                0x00000000      0x148 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_AbortReceive_IT
-                0x00000000      0x1a0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_IRQHandler
-                0x00000000      0x68c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_TxCpltCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_TxHalfCpltCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_AbortCpltCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_AbortTransmitCpltCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_AbortReceiveCpltCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UARTEx_RxEventCallback
-                0x00000000       0x16 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_ReceiverTimeout_Config
-                0x00000000       0x26 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_EnableReceiverTimeout
-                0x00000000       0x60 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_DisableReceiverTimeout
-                0x00000000       0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_MultiProcessor_EnableMuteMode
-                0x00000000       0x74 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_MultiProcessor_DisableMuteMode
-                0x00000000       0x78 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_MultiProcessor_EnterMuteMode
-                0x00000000       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_HalfDuplex_EnableTransmitter
-                0x00000000       0xa4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_HalfDuplex_EnableReceiver
-                0x00000000       0xa4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_LIN_SendBreak
-                0x00000000       0x50 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_GetState
-                0x00000000       0x26 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_UART_GetError
-                0x00000000       0x16 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.UART_Start_Receive_IT
-                0x00000000      0x248 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.UART_DMATransmitCplt
-                0x00000000       0x98 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.UART_DMATxHalfCplt
-                0x00000000       0x1e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.UART_DMAAbortOnError
-                0x00000000       0x26 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.UART_DMATxAbortCallback
-                0x00000000       0x90 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.UART_DMARxAbortCallback
-                0x00000000       0x82 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.UART_DMATxOnlyAbortCallback
-                0x00000000       0x4a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.UART_DMARxOnlyAbortCallback
-                0x00000000       0x4c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.UART_TxISR_8BIT.part.0
+                0x00000000       0x32 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .text.UART_TxISR_8BIT
-                0x00000000       0xb4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x00000000       0x32 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .text.UART_TxISR_16BIT
-                0x00000000       0xbe ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x00000000       0x36 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .text.UART_TxISR_8BIT_FIFOEN
-                0x00000000       0xec ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x00000000       0x78 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .text.UART_TxISR_16BIT_FIFOEN
-                0x00000000       0xf4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.UART_EndTransmit_IT
-                0x00000000       0x58 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x00000000       0x7c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_MspInit
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_MspDeInit
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_DeInit
+                0x00000000       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_Transmit_IT
+                0x00000000       0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_Transmit_DMA
+                0x00000000       0xa4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_DMAPause
+                0x00000000       0x88 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_DMAResume
+                0x00000000       0x82 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_DMAStop
+                0x00000000       0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_Abort
+                0x00000000      0x118 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_AbortTransmit
+                0x00000000       0xa0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_AbortReceive
+                0x00000000       0xc0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.UART_DMATransmitCplt
+                0x00000000       0x50 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_TxHalfCpltCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.UART_DMATxHalfCplt
+                0x00000000        0xa ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_ErrorCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_AbortCpltCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_Abort_IT
+                0x00000000      0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.UART_DMARxAbortCallback
+                0x00000000       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.UART_DMATxAbortCallback
+                0x00000000       0x50 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_AbortTransmitCpltCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_AbortTransmit_IT
+                0x00000000       0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.UART_DMATxOnlyAbortCallback
+                0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_AbortReceiveCpltCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_AbortReceive_IT
+                0x00000000       0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.UART_DMARxOnlyAbortCallback
+                0x00000000       0x2a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UARTEx_RxEventCallback
+                0x00000000        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .text.UART_RxISR_8BIT
-                0x00000000      0x1b8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x00000000       0xd8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .text.UART_RxISR_16BIT
-                0x00000000      0x1b8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x00000000       0xd4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .text.UART_RxISR_8BIT_FIFOEN
-                0x00000000      0x334 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x00000000      0x1cc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .text.UART_RxISR_16BIT_FIFOEN
-                0x00000000      0x34c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x00000000      0x1c8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_ReceiverTimeout_Config
+                0x00000000        0xe ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_EnableReceiverTimeout
+                0x00000000       0x32 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_DisableReceiverTimeout
+                0x00000000       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_MultiProcessor_EnterMuteMode
+                0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_HalfDuplex_EnableTransmitter
+                0x00000000       0x52 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_HalfDuplex_EnableReceiver
+                0x00000000       0x52 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_LIN_SendBreak
+                0x00000000       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_GetState
+                0x00000000        0xe ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_GetError
+                0x00000000        0x6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_Receive
+                0x00000000      0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_HalfDuplex_Init
+                0x00000000       0x70 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_LIN_Init
+                0x00000000       0x90 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_MultiProcessor_Init
+                0x00000000       0x90 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_MultiProcessor_EnableMuteMode
+                0x00000000       0x3e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_MultiProcessor_DisableMuteMode
+                0x00000000       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.UART_Start_Receive_IT
+                0x00000000      0x134 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_Receive_IT
+                0x00000000       0x5e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_Receive_DMA
+                0x00000000       0x5c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
@@ -2651,7 +2992,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
@@ -2664,6 +3005,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
@@ -2716,34 +3060,29 @@ Discarded input sections
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+ .group         0x00000000        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .text          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .data          0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .bss           0x00000000        0x0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
- .text.HAL_UARTEx_WakeupCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
- .text.HAL_UARTEx_RxFifoFullCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
- .text.HAL_UARTEx_TxFifoEmptyCallback
-                0x00000000       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .text.HAL_MultiProcessorEx_AddressLength_Set
-                0x00000000       0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x00000000       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .text.HAL_UARTEx_StopModeWakeUpSourceConfig
-                0x00000000       0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x00000000       0x90 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .text.HAL_UARTEx_EnableStopMode
-                0x00000000       0x62 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x00000000       0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .text.HAL_UARTEx_DisableStopMode
-                0x00000000       0x62 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x00000000       0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .text.HAL_UARTEx_EnableFifoMode
-                0x00000000       0x7a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x00000000       0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .text.HAL_UARTEx_ReceiveToIdle
-                0x00000000      0x240 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x00000000      0x158 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .text.HAL_UARTEx_ReceiveToIdle_IT
-                0x00000000       0xc8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x00000000       0x62 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .text.HAL_UARTEx_GetRxEventType
-                0x00000000       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
- .text.UARTEx_Wakeup_AddressConfig
-                0x00000000       0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
- .debug_macro   0x00000000      0xaae ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x00000000        0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+ .debug_macro   0x00000000      0xab4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000       0x22 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
@@ -2760,7 +3099,7 @@ Discarded input sections
  .debug_macro   0x00000000     0x9821 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000       0x6d ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000      0x1f2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
- .debug_macro   0x00000000       0xe9 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+ .debug_macro   0x00000000       0xef ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000     0x3440 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000      0x190 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000       0x5b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
@@ -2773,6 +3112,9 @@ Discarded input sections
  .debug_macro   0x00000000      0x18b ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000       0x43 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000      0x1f1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+ .debug_macro   0x00000000      0x924 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+ .debug_macro   0x00000000      0x5de ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+ .debug_macro   0x00000000       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000      0x1b1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000      0x37c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
@@ -2784,254 +3126,258 @@ Discarded input sections
  .debug_macro   0x00000000      0x67e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000       0xa6 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
  .debug_macro   0x00000000      0x42c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
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+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o)
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divsi3.o)
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o)
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o)
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_aeabi_ldivmod.o)
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_aeabi_ldivmod.o)
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_muldi3.o)
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_muldi3.o)
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(bpabi.o)
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(bpabi.o)
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divdi3.o)
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divdi3.o)
+ .ARM.extab     0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divdi3.o)
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_clzdi2.o)
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_clzdi2.o)
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_clzsi2.o)
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_clzsi2.o)
+ .text          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o
+ .rodata        0x00000000       0x24 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o
+ .eh_frame      0x00000000        0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o
  .ARM.attributes
-                0x00000000       0x2c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtend.o
- .text          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o
- .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o
- .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o
+                0x00000000       0x2c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o
+ .text          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtn.o
+ .data          0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtn.o
+ .bss           0x00000000        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtn.o
 
 Memory Configuration
 
@@ -3042,9 +3388,9 @@ FLASH            0x08000000         0x00008000         xr
 
 Linker script and memory map
 
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp/crt0.o
 LOAD ./Core/Src/crc.o
 LOAD ./Core/Src/main.o
 LOAD ./Core/Src/stm32c0xx_hal_msp.o
@@ -3054,6 +3400,8 @@ LOAD ./Core/Src/sysmem.o
 LOAD ./Core/Src/system_stm32c0xx.o
 LOAD ./Core/Startup/startup_stm32c051c6tx.o
 LOAD ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+LOAD ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+LOAD ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o
 LOAD ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
 LOAD ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
 LOAD ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o
@@ -3070,25 +3418,25 @@ LOAD ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
 LOAD ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
 LOAD ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
 START GROUP
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a
 END GROUP
 START GROUP
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a
 END GROUP
 START GROUP
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a
 END GROUP
 START GROUP
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libnosys.a
 END GROUP
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtend.o
-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtend.o
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtn.o
                 0x20003000                        _estack = (ORIGIN (RAM) + LENGTH (RAM))
                 0x00000200                        _Min_Heap_Size = 0x200
                 0x00000400                        _Min_Stack_Size = 0x400
@@ -3100,874 +3448,867 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext
                 0x08000000                g_pfnVectors
                 0x080000c0                        . = ALIGN (0x4)
 
-.text           0x080000c0     0x7c78
+.text           0x080000c0     0x5150
                 0x080000c0                        . = ALIGN (0x4)
  *(.text)
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- .text          0x08000108      0x114 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o)
-                0x08000108                __aeabi_uidiv
-                0x08000108                __udivsi3
-                0x08000214                __aeabi_uidivmod
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-                0x0800021c                __divsi3
-                0x0800021c                __aeabi_idiv
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-                0x080003f0                __aeabi_idiv0
-                0x080003f0                __aeabi_ldiv0
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-                0x0800043c                __muldi3
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-                0x080004d4                __divdi3
- .text          0x080006ac       0x18 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_clzdi2.o)
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-                0x080006c4                __clzsi2
+ .text          0x080000c0       0x48 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o
+ .text          0x08000108       0x14 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_thumb1_case_uqi.o)
+                0x08000108                __gnu_thumb1_case_uqi
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+                0x0800011c                __gnu_thumb1_case_uhi
+ .text          0x08000130      0x114 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_udivsi3.o)
+                0x08000130                __aeabi_uidiv
+                0x08000130                __udivsi3
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+                0x08000244                __divsi3
+                0x08000244                __aeabi_idiv
+                0x08000410                __aeabi_idivmod
+ .text          0x08000418        0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_dvmd_tls.o)
+                0x08000418                __aeabi_idiv0
+                0x08000418                __aeabi_ldiv0
+ .text          0x0800041c       0x48 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_aeabi_ldivmod.o)
+                0x0800041c                __aeabi_ldivmod
+ .text          0x08000464       0x5c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_muldi3.o)
+                0x08000464                __muldi3
+                0x08000464                __aeabi_lmul
+ .text          0x080004c0       0x3c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(bpabi.o)
+                0x080004c0                __gnu_ldivmod_helper
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+                0x080004fc                __divdi3
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+                0x080006f8                __clzdi2
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+                0x08000710                __clzsi2
  *(.text*)
  .text.CRC8_107_add
-                0x08000700       0x60 ./Core/Src/crc.o
-                0x08000700                CRC8_107_add
+                0x0800074c       0x28 ./Core/Src/crc.o
+                0x0800074c                CRC8_107_add
  .text.CRC8_107_getChecksum
-                0x08000760       0x18 ./Core/Src/crc.o
-                0x08000760                CRC8_107_getChecksum
- .text.__NVIC_SystemReset
-                0x08000778       0x24 ./Core/Src/main.o
- .text.clamp_i32
-                0x0800079c       0x2e ./Core/Src/main.o
- .text.pid_init
-                0x080007ca       0x52 ./Core/Src/main.o
- .text.pid_reset
-                0x0800081c       0x22 ./Core/Src/main.o
- .text.pid_update_motor
-                0x0800083e      0x18e ./Core/Src/main.o
- .text.CRC8_107_init
-                0x080009cc       0x16 ./Core/Src/main.o
- *fill*         0x080009e2        0x2 
- .text.main     0x080009e4      0x778 ./Core/Src/main.o
-                0x080009e4                main
+                0x08000774        0x8 ./Core/Src/crc.o
+                0x08000774                CRC8_107_getChecksum
  .text.SystemClock_Config
-                0x0800115c       0x9c ./Core/Src/main.o
-                0x0800115c                SystemClock_Config
- .text.MX_TIM1_Init
-                0x080011f8      0x1d8 ./Core/Src/main.o
- .text.MX_TIM3_Init
-                0x080013d0       0xc8 ./Core/Src/main.o
- .text.MX_TIM14_Init
-                0x08001498       0x48 ./Core/Src/main.o
- .text.MX_TIM16_Init
-                0x080014e0       0x54 ./Core/Src/main.o
- .text.MX_TIM17_Init
-                0x08001534       0x54 ./Core/Src/main.o
- .text.MX_USART1_UART_Init
-                0x08001588       0x9c ./Core/Src/main.o
- .text.MX_USART2_UART_Init
-                0x08001624       0xa8 ./Core/Src/main.o
- .text.MX_DMA_Init
-                0x080016cc       0x4c ./Core/Src/main.o
- .text.MX_GPIO_Init
-                0x08001718      0x124 ./Core/Src/main.o
+                0x0800077c       0x68 ./Core/Src/main.o
+                0x0800077c                SystemClock_Config
  .text.HAL_TIM_PeriodElapsedCallback
-                0x0800183c      0x214 ./Core/Src/main.o
-                0x0800183c                HAL_TIM_PeriodElapsedCallback
+                0x080007e4      0x1bc ./Core/Src/main.o
+                0x080007e4                HAL_TIM_PeriodElapsedCallback
  .text.HAL_GPIO_EXTI_Falling_Callback
-                0x08001a50       0x7c ./Core/Src/main.o
-                0x08001a50                HAL_GPIO_EXTI_Falling_Callback
+                0x080009a0       0x48 ./Core/Src/main.o
+                0x080009a0                HAL_GPIO_EXTI_Falling_Callback
  .text.HAL_UARTEx_RxEventCallback
-                0x08001acc       0xa0 ./Core/Src/main.o
-                0x08001acc                HAL_UARTEx_RxEventCallback
- .text.set_LED  0x08001b6c       0x80 ./Core/Src/main.o
-                0x08001b6c                set_LED
- .text.comp_crc_header
-                0x08001bec       0x4a ./Core/Src/main.o
-                0x08001bec                comp_crc_header
- *fill*         0x08001c36        0x2 
- .text.handleRS485Message
-                0x08001c38      0x964 ./Core/Src/main.o
-                0x08001c38                handleRS485Message
- .text.set_Feeder_PWM
-                0x0800259c       0x68 ./Core/Src/main.o
-                0x0800259c                set_Feeder_PWM
- .text.peel_motor
-                0x08002604       0x30 ./Core/Src/main.o
-                0x08002604                peel_motor
- .text.peel_brake
-                0x08002634       0x14 ./Core/Src/main.o
-                0x08002634                peel_brake
- .text.peel_ramp_update
-                0x08002648      0x154 ./Core/Src/main.o
-                0x08002648                peel_ramp_update
- .text.drive_continuous
-                0x0800279c       0x54 ./Core/Src/main.o
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- .text.halt_all
-                0x080027f0       0x6c ./Core/Src/main.o
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- .text.identify_feeder
-                0x0800285c       0x4a ./Core/Src/main.o
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- .text.show_version
-                0x080028a6       0x2a ./Core/Src/main.o
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- .text.tenths_to_counts
-                0x080028d0       0x50 ./Core/Src/main.o
-                0x080028d0                tenths_to_counts
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-                0x08002920       0x90 ./Core/Src/main.o
-                0x08002920                calculate_expected_feed_time
- .text.start_feed
-                0x080029b0      0x138 ./Core/Src/main.o
-                0x080029b0                start_feed
- .text.feed_state_machine_update
-                0x08002ae8      0x368 ./Core/Src/main.o
-                0x08002ae8                feed_state_machine_update
- .text.check_tape_loaded
-                0x08002e50       0xcc ./Core/Src/main.o
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-                0x08002f1c      0x100 ./Core/Src/main.o
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- .text.onewire_set_input
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- .text.onewire_write_byte
-                0x08003326       0x42 ./Core/Src/main.o
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- .text.read_floor_address
-                0x080033b2       0x4c ./Core/Src/main.o
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- .text.write_floor_address
-                0x080033fe      0x144 ./Core/Src/main.o
-                0x080033fe                write_floor_address
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-                0x08003542       0xf2 ./Core/Src/main.o
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-                0x08003634       0x58 ./Core/Src/main.o
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-                0x080039b0       0x9c ./Core/Src/main.o
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-                0x08003a58       0x48 ./Core/Src/stm32c0xx_hal_msp.o
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- .text.HAL_UART_MspInit
-                0x08003cd0      0x1f0 ./Core/Src/stm32c0xx_hal_msp.o
-                0x08003cd0                HAL_UART_MspInit
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-                0x08003ec0        0x8 ./Core/Src/stm32c0xx_it.o
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-                0x08003ec8        0x8 ./Core/Src/stm32c0xx_it.o
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-                0x08003ed0        0xa ./Core/Src/stm32c0xx_it.o
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-                0x08003eda        0xa ./Core/Src/stm32c0xx_it.o
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-                0x08003ee4        0xe ./Core/Src/stm32c0xx_it.o
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- .text.EXTI4_15_IRQHandler
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-                0x08003f10       0x18 ./Core/Src/stm32c0xx_it.o
-                0x08003f10                DMA1_Channel1_IRQHandler
- .text.DMA1_Channel2_3_IRQHandler
-                0x08003f28       0x18 ./Core/Src/stm32c0xx_it.o
-                0x08003f28                DMA1_Channel2_3_IRQHandler
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-                0x08003f58       0x18 ./Core/Src/stm32c0xx_it.o
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-                0x08003f88       0x18 ./Core/Src/system_stm32c0xx.o
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- .text.Reset_Handler
-                0x08003fa0       0x50 ./Core/Startup/startup_stm32c051c6tx.o
-                0x08003fa0                Reset_Handler
- .text.Default_Handler
-                0x08003ff0        0x2 ./Core/Startup/startup_stm32c051c6tx.o
-                0x08003ff0                TIM1_CC_IRQHandler
-                0x08003ff0                I2C1_IRQHandler
-                0x08003ff0                SPI1_IRQHandler
-                0x08003ff0                EXTI2_3_IRQHandler
-                0x08003ff0                ADC1_IRQHandler
-                0x08003ff0                I2C2_IRQHandler
-                0x08003ff0                RTC_IRQHandler
-                0x08003ff0                TIM3_IRQHandler
-                0x08003ff0                RCC_IRQHandler
-                0x08003ff0                Default_Handler
-                0x08003ff0                EXTI0_1_IRQHandler
-                0x08003ff0                SPI2_IRQHandler
-                0x08003ff0                WWDG_IRQHandler
-                0x08003ff0                TIM2_IRQHandler
-                0x08003ff0                DMAMUX1_DMA1_CH4_5_IRQHandler
-                0x08003ff0                USART2_IRQHandler
-                0x08003ff0                FLASH_IRQHandler
-                0x08003ff0                USART1_IRQHandler
-                0x08003ff0                TIM1_BRK_UP_TRG_COM_IRQHandler
- .text.HAL_Init
-                0x08003ff2       0x2e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
-                0x08003ff2                HAL_Init
- .text.HAL_InitTick
-                0x08004020       0x94 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
-                0x08004020                HAL_InitTick
- .text.HAL_IncTick
-                0x080040b4       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
-                0x080040b4                HAL_IncTick
- .text.HAL_GetTick
-                0x080040d8       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
-                0x080040d8                HAL_GetTick
- .text.HAL_Delay
-                0x080040ec       0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
-                0x080040ec                HAL_Delay
- .text.HAL_GetUIDw0
-                0x08004134       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
-                0x08004134                HAL_GetUIDw0
- .text.HAL_GetUIDw1
-                0x08004148       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
-                0x08004148                HAL_GetUIDw1
- .text.HAL_GetUIDw2
-                0x0800415c       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
-                0x0800415c                HAL_GetUIDw2
- .text.__NVIC_EnableIRQ
-                0x08004170       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.__NVIC_SetPriority
-                0x080041a4       0xdc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.SysTick_Config
-                0x08004280       0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
- .text.HAL_NVIC_SetPriority
-                0x080042c8       0x2a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
-                0x080042c8                HAL_NVIC_SetPriority
- .text.HAL_NVIC_EnableIRQ
-                0x080042f2       0x20 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
-                0x080042f2                HAL_NVIC_EnableIRQ
- .text.HAL_SYSTICK_Config
-                0x08004312       0x1a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
-                0x08004312                HAL_SYSTICK_Config
- .text.HAL_DMA_Init
-                0x0800432c      0x114 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
-                0x0800432c                HAL_DMA_Init
- .text.HAL_DMA_Start_IT
-                0x08004440      0x10e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
-                0x08004440                HAL_DMA_Start_IT
- *fill*         0x0800454e        0x2 
- .text.HAL_DMA_IRQHandler
-                0x08004550      0x164 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
-                0x08004550                HAL_DMA_IRQHandler
- .text.DMA_SetConfig
-                0x080046b4       0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
- .text.DMA_CalcDMAMUXChannelBaseAndMask
-                0x08004734       0x58 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
- .text.DMA_CalcDMAMUXRequestGenBaseAndMask
-                0x0800478c       0x48 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
- .text.HAL_GPIO_Init
-                0x080047d4      0x2e4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
-                0x080047d4                HAL_GPIO_Init
- .text.HAL_GPIO_ReadPin
-                0x08004ab8       0x3a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
-                0x08004ab8                HAL_GPIO_ReadPin
- .text.HAL_GPIO_WritePin
-                0x08004af2       0x3a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
-                0x08004af2                HAL_GPIO_WritePin
- .text.HAL_GPIO_EXTI_IRQHandler
-                0x08004b2c       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
-                0x08004b2c                HAL_GPIO_EXTI_IRQHandler
- .text.HAL_GPIO_EXTI_Rising_Callback
-                0x08004b80       0x14 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
-                0x08004b80                HAL_GPIO_EXTI_Rising_Callback
- .text.HAL_RCC_OscConfig
-                0x08004b94      0x3c8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
-                0x08004b94                HAL_RCC_OscConfig
- .text.HAL_RCC_ClockConfig
-                0x08004f5c      0x214 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
-                0x08004f5c                HAL_RCC_ClockConfig
- .text.HAL_RCC_GetSysClockFreq
-                0x08005170       0xa0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
-                0x08005170                HAL_RCC_GetSysClockFreq
- .text.HAL_RCC_GetHCLKFreq
-                0x08005210       0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
-                0x08005210                HAL_RCC_GetHCLKFreq
- .text.HAL_RCC_GetPCLK1Freq
-                0x0800524c       0x30 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
-                0x0800524c                HAL_RCC_GetPCLK1Freq
- .text.HAL_RCCEx_PeriphCLKConfig
-                0x0800527c      0x1d8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
-                0x0800527c                HAL_RCCEx_PeriphCLKConfig
- .text.HAL_TIM_Base_Init
-                0x08005454       0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x08005454                HAL_TIM_Base_Init
- .text.HAL_TIM_Base_Stop
-                0x08005504       0x4c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x08005504                HAL_TIM_Base_Stop
- .text.HAL_TIM_Base_Start_IT
-                0x08005550       0xa8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x08005550                HAL_TIM_Base_Start_IT
- .text.HAL_TIM_PWM_Init
-                0x080055f8       0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x080055f8                HAL_TIM_PWM_Init
- .text.HAL_TIM_PWM_MspInit
-                0x080056a8       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x080056a8                HAL_TIM_PWM_MspInit
- .text.HAL_TIM_PWM_Start
-                0x080056b8      0x1bc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x080056b8                HAL_TIM_PWM_Start
- .text.HAL_TIM_Encoder_Init
-                0x08005874      0x150 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x08005874                HAL_TIM_Encoder_Init
- .text.HAL_TIM_Encoder_Start
-                0x080059c4      0x148 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x080059c4                HAL_TIM_Encoder_Start
- .text.HAL_TIM_IRQHandler
-                0x08005b0c      0x210 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x08005b0c                HAL_TIM_IRQHandler
- .text.HAL_TIM_PWM_ConfigChannel
-                0x08005d1c      0x200 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x08005d1c                HAL_TIM_PWM_ConfigChannel
- .text.HAL_TIM_ConfigClockSource
-                0x08005f1c      0x1ac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x08005f1c                HAL_TIM_ConfigClockSource
- .text.HAL_TIM_OC_DelayElapsedCallback
-                0x080060c8       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x080060c8                HAL_TIM_OC_DelayElapsedCallback
- .text.HAL_TIM_IC_CaptureCallback
-                0x080060d8       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x080060d8                HAL_TIM_IC_CaptureCallback
- .text.HAL_TIM_PWM_PulseFinishedCallback
-                0x080060e8       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x080060e8                HAL_TIM_PWM_PulseFinishedCallback
- .text.HAL_TIM_TriggerCallback
-                0x080060f8       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x080060f8                HAL_TIM_TriggerCallback
- .text.TIM_Base_SetConfig
-                0x08006108       0xf8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x08006108                TIM_Base_SetConfig
- .text.TIM_OC1_SetConfig
-                0x08006200      0x100 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_OC2_SetConfig
-                0x08006300       0xfc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x08006300                TIM_OC2_SetConfig
- .text.TIM_OC3_SetConfig
-                0x080063fc      0x104 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_OC4_SetConfig
-                0x08006500       0xc8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_OC5_SetConfig
-                0x080065c8       0xb4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_OC6_SetConfig
-                0x0800667c       0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_TI1_ConfigInputStage
-                0x08006738       0x5c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_TI2_ConfigInputStage
-                0x08006794       0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_ITRx_SetConfig
-                0x080067f8       0x38 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
- .text.TIM_ETR_SetConfig
-                0x08006830       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x08006830                TIM_ETR_SetConfig
- .text.TIM_CCxChannelCmd
-                0x08006870       0x46 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
-                0x08006870                TIM_CCxChannelCmd
- *fill*         0x080068b6        0x2 
- .text.HAL_TIMEx_MasterConfigSynchronization
-                0x080068b8       0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
-                0x080068b8                HAL_TIMEx_MasterConfigSynchronization
- .text.HAL_TIMEx_ConfigBreakDeadTime
-                0x08006988      0x138 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
-                0x08006988                HAL_TIMEx_ConfigBreakDeadTime
- .text.HAL_TIMEx_CommutCallback
-                0x08006ac0       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
-                0x08006ac0                HAL_TIMEx_CommutCallback
- .text.HAL_TIMEx_BreakCallback
-                0x08006ad0       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
-                0x08006ad0                HAL_TIMEx_BreakCallback
- .text.HAL_TIMEx_Break2Callback
-                0x08006ae0       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
-                0x08006ae0                HAL_TIMEx_Break2Callback
- .text.HAL_UART_Init
-                0x08006af0       0xac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
-                0x08006af0                HAL_UART_Init
- .text.HAL_UART_Transmit
-                0x08006b9c      0x148 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
-                0x08006b9c                HAL_UART_Transmit
- .text.HAL_UART_RxCpltCallback
-                0x08006ce4       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
-                0x08006ce4                HAL_UART_RxCpltCallback
- .text.HAL_UART_RxHalfCpltCallback
-                0x08006cf4       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
-                0x08006cf4                HAL_UART_RxHalfCpltCallback
+                0x080009e8       0x70 ./Core/Src/main.o
+                0x080009e8                HAL_UARTEx_RxEventCallback
  .text.HAL_UART_ErrorCallback
-                0x08006d04       0x10 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
-                0x08006d04                HAL_UART_ErrorCallback
- .text.UART_SetConfig
-                0x08006d14      0x2fc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
-                0x08006d14                UART_SetConfig
- .text.UART_AdvFeatureConfig
-                0x08007010      0x168 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
-                0x08007010                UART_AdvFeatureConfig
- .text.UART_CheckIdleState
-                0x08007178      0x154 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
-                0x08007178                UART_CheckIdleState
- .text.UART_WaitOnFlagUntilTimeout
-                0x080072cc       0xde ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
-                0x080072cc                UART_WaitOnFlagUntilTimeout
- *fill*         0x080073aa        0x2 
- .text.UART_Start_Receive_DMA
-                0x080073ac      0x14c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
-                0x080073ac                UART_Start_Receive_DMA
+                0x08000a58       0x44 ./Core/Src/main.o
+                0x08000a58                HAL_UART_ErrorCallback
+ .text.set_LED  0x08000a9c       0x38 ./Core/Src/main.o
+                0x08000a9c                set_LED
+ .text.rs485_transmit
+                0x08000ad4       0x54 ./Core/Src/main.o
+                0x08000ad4                rs485_transmit
+ .text.comp_crc_header
+                0x08000b28       0x26 ./Core/Src/main.o
+                0x08000b28                comp_crc_header
+ *fill*         0x08000b4e        0x2 
+ .text.peel_ramp_update
+                0x08000b50       0x8c ./Core/Src/main.o
+                0x08000b50                peel_ramp_update
+ .text.drive_continuous
+                0x08000bdc       0x28 ./Core/Src/main.o
+                0x08000bdc                drive_continuous
+ .text.halt_all
+                0x08000c04       0x40 ./Core/Src/main.o
+                0x08000c04                halt_all
+ .text.identify_feeder
+                0x08000c44       0x30 ./Core/Src/main.o
+                0x08000c44                identify_feeder
+ .text.show_version
+                0x08000c74       0x24 ./Core/Src/main.o
+                0x08000c74                show_version
+ .text.start_feed
+                0x08000c98       0xec ./Core/Src/main.o
+                0x08000c98                start_feed
+ .text.feed_state_machine_update
+                0x08000d84      0x2f0 ./Core/Src/main.o
+                0x08000d84                feed_state_machine_update
+ .text.handle_vendor_options
+                0x08001074       0x58 ./Core/Src/main.o
+                0x08001074                handle_vendor_options
+ .text.onewire_delay_us
+                0x080010cc       0x30 ./Core/Src/main.o
+                0x080010cc                onewire_delay_us
+ .text.onewire_read_bit
+                0x080010fc        0xc ./Core/Src/main.o
+                0x080010fc                onewire_read_bit
+ .text.onewire_reset
+                0x08001108       0x30 ./Core/Src/main.o
+                0x08001108                onewire_reset
+ .text.onewire_write_bit
+                0x08001138       0x2a ./Core/Src/main.o
+                0x08001138                onewire_write_bit
+ .text.onewire_read_bit_slot
+                0x08001162       0x28 ./Core/Src/main.o
+                0x08001162                onewire_read_bit_slot
+ .text.onewire_write_byte
+                0x0800118a       0x1a ./Core/Src/main.o
+                0x0800118a                onewire_write_byte
+ .text.onewire_read_byte
+                0x080011a4       0x20 ./Core/Src/main.o
+                0x080011a4                onewire_read_byte
+ .text.read_floor_address
+                0x080011c4       0x32 ./Core/Src/main.o
+                0x080011c4                read_floor_address
+ .text.write_floor_address
+                0x080011f6       0xcc ./Core/Src/main.o
+                0x080011f6                write_floor_address
+ *fill*         0x080012c2        0x2 
+ .text.handleRS485Message
+                0x080012c4      0x478 ./Core/Src/main.o
+                0x080012c4                handleRS485Message
+ .text.debug_itoa
+                0x0800173c       0x70 ./Core/Src/main.o
+                0x0800173c                debug_itoa
+ .text.debug_hex8
+                0x080017ac       0x2c ./Core/Src/main.o
+                0x080017ac                debug_hex8
+ .text.debug_output
+                0x080017d8      0x208 ./Core/Src/main.o
+                0x080017d8                debug_output
+ .text.reset_position_if_needed
+                0x080019e0       0x78 ./Core/Src/main.o
+                0x080019e0                reset_position_if_needed
+ .text.startup.main
+                0x08001a58      0x988 ./Core/Src/main.o
+                0x08001a58                main
+ .text.Error_Handler
+                0x080023e0        0x4 ./Core/Src/main.o
+                0x080023e0                Error_Handler
+ .text.HAL_MspInit
+                0x080023e4       0x30 ./Core/Src/stm32c0xx_hal_msp.o
+                0x080023e4                HAL_MspInit
+ .text.HAL_ADC_MspInit
+                0x08002414       0xa0 ./Core/Src/stm32c0xx_hal_msp.o
+                0x08002414                HAL_ADC_MspInit
+ .text.HAL_TIM_Base_MspInit
+                0x080024b4       0xb4 ./Core/Src/stm32c0xx_hal_msp.o
+                0x080024b4                HAL_TIM_Base_MspInit
+ .text.HAL_TIM_Encoder_MspInit
+                0x08002568       0x5c ./Core/Src/stm32c0xx_hal_msp.o
+                0x08002568                HAL_TIM_Encoder_MspInit
+ .text.HAL_TIM_MspPostInit
+                0x080025c4       0x68 ./Core/Src/stm32c0xx_hal_msp.o
+                0x080025c4                HAL_TIM_MspPostInit
+ .text.HAL_UART_MspInit
+                0x0800262c      0x14c ./Core/Src/stm32c0xx_hal_msp.o
+                0x0800262c                HAL_UART_MspInit
+ .text.NMI_Handler
+                0x08002778        0x2 ./Core/Src/stm32c0xx_it.o
+                0x08002778                NMI_Handler
+ .text.HardFault_Handler
+                0x0800277a        0x2 ./Core/Src/stm32c0xx_it.o
+                0x0800277a                HardFault_Handler
+ .text.SVC_Handler
+                0x0800277c        0x2 ./Core/Src/stm32c0xx_it.o
+                0x0800277c                SVC_Handler
+ .text.PendSV_Handler
+                0x0800277e        0x2 ./Core/Src/stm32c0xx_it.o
+                0x0800277e                PendSV_Handler
+ .text.SysTick_Handler
+                0x08002780        0x8 ./Core/Src/stm32c0xx_it.o
+                0x08002780                SysTick_Handler
+ .text.EXTI4_15_IRQHandler
+                0x08002788       0x14 ./Core/Src/stm32c0xx_it.o
+                0x08002788                EXTI4_15_IRQHandler
+ .text.DMA1_Channel1_IRQHandler
+                0x0800279c       0x10 ./Core/Src/stm32c0xx_it.o
+                0x0800279c                DMA1_Channel1_IRQHandler
+ .text.DMA1_Channel2_3_IRQHandler
+                0x080027ac       0x10 ./Core/Src/stm32c0xx_it.o
+                0x080027ac                DMA1_Channel2_3_IRQHandler
+ .text.TIM14_IRQHandler
+                0x080027bc       0x10 ./Core/Src/stm32c0xx_it.o
+                0x080027bc                TIM14_IRQHandler
+ .text.TIM16_IRQHandler
+                0x080027cc       0x10 ./Core/Src/stm32c0xx_it.o
+                0x080027cc                TIM16_IRQHandler
+ .text.TIM17_IRQHandler
+                0x080027dc       0x10 ./Core/Src/stm32c0xx_it.o
+                0x080027dc                TIM17_IRQHandler
+ .text.USART2_IRQHandler
+                0x080027ec       0x10 ./Core/Src/stm32c0xx_it.o
+                0x080027ec                USART2_IRQHandler
+ .text.SystemInit
+                0x080027fc       0x10 ./Core/Src/system_stm32c0xx.o
+                0x080027fc                SystemInit
+ .text.Reset_Handler
+                0x0800280c       0x50 ./Core/Startup/startup_stm32c051c6tx.o
+                0x0800280c                Reset_Handler
+ .text.Default_Handler
+                0x0800285c        0x2 ./Core/Startup/startup_stm32c051c6tx.o
+                0x0800285c                TIM1_CC_IRQHandler
+                0x0800285c                I2C1_IRQHandler
+                0x0800285c                SPI1_IRQHandler
+                0x0800285c                EXTI2_3_IRQHandler
+                0x0800285c                ADC1_IRQHandler
+                0x0800285c                I2C2_IRQHandler
+                0x0800285c                RTC_IRQHandler
+                0x0800285c                TIM3_IRQHandler
+                0x0800285c                RCC_IRQHandler
+                0x0800285c                Default_Handler
+                0x0800285c                EXTI0_1_IRQHandler
+                0x0800285c                SPI2_IRQHandler
+                0x0800285c                WWDG_IRQHandler
+                0x0800285c                TIM2_IRQHandler
+                0x0800285c                DMAMUX1_DMA1_CH4_5_IRQHandler
+                0x0800285c                FLASH_IRQHandler
+                0x0800285c                USART1_IRQHandler
+                0x0800285c                TIM1_BRK_UP_TRG_COM_IRQHandler
+ *fill*         0x0800285e        0x2 
+ .text.HAL_InitTick
+                0x08002860       0x50 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x08002860                HAL_InitTick
+ .text.HAL_Init
+                0x080028b0       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x080028b0                HAL_Init
+ .text.HAL_IncTick
+                0x080028c8       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x080028c8                HAL_IncTick
+ .text.HAL_GetTick
+                0x080028e0        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x080028e0                HAL_GetTick
+ .text.HAL_Delay
+                0x080028ec       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x080028ec                HAL_Delay
+ .text.HAL_GetUIDw0
+                0x08002910        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x08002910                HAL_GetUIDw0
+ .text.HAL_GetUIDw1
+                0x0800291c        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x0800291c                HAL_GetUIDw1
+ .text.HAL_GetUIDw2
+                0x08002928        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x08002928                HAL_GetUIDw2
+ .text.LL_ADC_REG_IsConversionOngoing
+                0x08002934        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+ .text.HAL_ADC_Init
+                0x0800293c      0x220 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+                0x0800293c                HAL_ADC_Init
+ .text.HAL_ADC_ConfigChannel
+                0x08002b5c      0x248 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
+                0x08002b5c                HAL_ADC_ConfigChannel
+ .text.HAL_NVIC_SetPriority
+                0x08002da4       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+                0x08002da4                HAL_NVIC_SetPriority
+ .text.HAL_NVIC_EnableIRQ
+                0x08002df8       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+                0x08002df8                HAL_NVIC_EnableIRQ
+ .text.HAL_SYSTICK_Config
+                0x08002e10       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+                0x08002e10                HAL_SYSTICK_Config
+ .text.DMA_SetConfig
+                0x08002e44       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+ .text.DMA_CalcDMAMUXChannelBaseAndMask
+                0x08002e84       0x34 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+ .text.HAL_DMA_Init
+                0x08002eb8       0xb4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x08002eb8                HAL_DMA_Init
+ .text.HAL_DMA_Start_IT
+                0x08002f6c       0x8e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x08002f6c                HAL_DMA_Start_IT
+ *fill*         0x08002ffa        0x2 
+ .text.HAL_DMA_Abort
+                0x08002ffc       0x74 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x08002ffc                HAL_DMA_Abort
+ .text.HAL_DMA_Abort_IT
+                0x08003070       0x7c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x08003070                HAL_DMA_Abort_IT
+ .text.HAL_DMA_IRQHandler
+                0x080030ec       0xa8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x080030ec                HAL_DMA_IRQHandler
+ .text.HAL_GPIO_Init
+                0x08003194      0x174 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+                0x08003194                HAL_GPIO_Init
+ .text.HAL_GPIO_ReadPin
+                0x08003308        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+                0x08003308                HAL_GPIO_ReadPin
+ .text.HAL_GPIO_WritePin
+                0x08003314        0xc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+                0x08003314                HAL_GPIO_WritePin
+ .text.HAL_GPIO_EXTI_Rising_Callback
+                0x08003320        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+                0x08003320                HAL_GPIO_EXTI_Rising_Callback
+ *fill*         0x08003322        0x2 
+ .text.HAL_GPIO_EXTI_IRQHandler
+                0x08003324       0x28 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+                0x08003324                HAL_GPIO_EXTI_IRQHandler
+ .text.HAL_RCC_OscConfig
+                0x0800334c      0x26c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x0800334c                HAL_RCC_OscConfig
+ .text.HAL_RCC_GetSysClockFreq
+                0x080035b8       0x5c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x080035b8                HAL_RCC_GetSysClockFreq
+ .text.HAL_RCC_ClockConfig
+                0x08003614      0x164 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x08003614                HAL_RCC_ClockConfig
+ .text.HAL_RCC_GetHCLKFreq
+                0x08003778       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x08003778                HAL_RCC_GetHCLKFreq
+ .text.HAL_RCC_GetPCLK1Freq
+                0x080037a4       0x24 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x080037a4                HAL_RCC_GetPCLK1Freq
+ .text.HAL_RCCEx_PeriphCLKConfig
+                0x080037c8      0x114 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+                0x080037c8                HAL_RCCEx_PeriphCLKConfig
+ .text.TIM_OC1_SetConfig
+                0x080038dc       0x6c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_OC3_SetConfig
+                0x08003948       0x84 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_OC4_SetConfig
+                0x080039cc       0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_OC5_SetConfig
+                0x08003a34       0x60 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.TIM_OC6_SetConfig
+                0x08003a94       0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .text.HAL_TIM_Base_Stop
+                0x08003afc       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003afc                HAL_TIM_Base_Stop
+ .text.HAL_TIM_Base_Start_IT
+                0x08003b28       0x60 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003b28                HAL_TIM_Base_Start_IT
+ .text.HAL_TIM_PWM_MspInit
+                0x08003b88        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003b88                HAL_TIM_PWM_MspInit
+ .text.HAL_TIM_Encoder_Start
+                0x08003b8a       0xb0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003b8a                HAL_TIM_Encoder_Start
+ .text.HAL_TIM_OC_DelayElapsedCallback
+                0x08003c3a        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003c3a                HAL_TIM_OC_DelayElapsedCallback
+ .text.HAL_TIM_IC_CaptureCallback
+                0x08003c3c        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003c3c                HAL_TIM_IC_CaptureCallback
+ .text.HAL_TIM_PWM_PulseFinishedCallback
+                0x08003c3e        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003c3e                HAL_TIM_PWM_PulseFinishedCallback
+ .text.HAL_TIM_TriggerCallback
+                0x08003c40        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003c40                HAL_TIM_TriggerCallback
+ *fill*         0x08003c42        0x2 
+ .text.HAL_TIM_IRQHandler
+                0x08003c44      0x158 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003c44                HAL_TIM_IRQHandler
+ .text.TIM_Base_SetConfig
+                0x08003d9c       0x88 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003d9c                TIM_Base_SetConfig
+ .text.HAL_TIM_Base_Init
+                0x08003e24       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003e24                HAL_TIM_Base_Init
+ .text.HAL_TIM_PWM_Init
+                0x08003e78       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003e78                HAL_TIM_PWM_Init
+ .text.HAL_TIM_Encoder_Init
+                0x08003ecc       0xac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003ecc                HAL_TIM_Encoder_Init
+ .text.TIM_OC2_SetConfig
+                0x08003f78       0x78 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003f78                TIM_OC2_SetConfig
+ .text.HAL_TIM_PWM_ConfigChannel
+                0x08003ff0      0x10c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08003ff0                HAL_TIM_PWM_ConfigChannel
+ .text.TIM_ETR_SetConfig
+                0x080040fc       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x080040fc                TIM_ETR_SetConfig
+ .text.HAL_TIM_ConfigClockSource
+                0x08004114      0x130 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08004114                HAL_TIM_ConfigClockSource
+ .text.TIM_CCxChannelCmd
+                0x08004244       0x1a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08004244                TIM_CCxChannelCmd
+ *fill*         0x0800425e        0x2 
+ .text.HAL_TIM_OC_Start
+                0x08004260       0xf8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08004260                HAL_TIM_OC_Start
+ .text.HAL_TIM_PWM_Start
+                0x08004358        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x08004358                HAL_TIM_PWM_Start
+ .text.HAL_TIMEx_MasterConfigSynchronization
+                0x08004360       0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+                0x08004360                HAL_TIMEx_MasterConfigSynchronization
+ .text.HAL_TIMEx_ConfigBreakDeadTime
+                0x080043c8       0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+                0x080043c8                HAL_TIMEx_ConfigBreakDeadTime
+ .text.HAL_TIMEx_CommutCallback
+                0x08004484        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+                0x08004484                HAL_TIMEx_CommutCallback
+ .text.HAL_TIMEx_BreakCallback
+                0x08004486        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+                0x08004486                HAL_TIMEx_BreakCallback
+ .text.HAL_TIMEx_Break2Callback
+                0x08004488        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+                0x08004488                HAL_TIMEx_Break2Callback
+ *fill*         0x0800448a        0x2 
  .text.UART_EndTxTransfer
-                0x080074f8       0x80 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x0800448c       0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
  .text.UART_EndRxTransfer
-                0x08007578       0xcc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.UART_DMAReceiveCplt
-                0x08007644      0x168 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.UART_DMARxHalfCplt
-                0x080077ac       0x7e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x080044c8       0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_TxCpltCallback
+                0x0800452c        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x0800452c                HAL_UART_TxCpltCallback
+ .text.HAL_UART_RxCpltCallback
+                0x0800452e        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x0800452e                HAL_UART_RxCpltCallback
+ .text.HAL_UART_RxHalfCpltCallback
+                0x08004530        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x08004530                HAL_UART_RxHalfCpltCallback
  .text.UART_DMAError
-                0x0800782a       0x86 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
- .text.HAL_RS485Ex_Init
-                0x080078b0       0xe4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
-                0x080078b0                HAL_RS485Ex_Init
- .text.HAL_UARTEx_DisableFifoMode
-                0x08007994       0x74 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
-                0x08007994                HAL_UARTEx_DisableFifoMode
- .text.HAL_UARTEx_SetTxFifoThreshold
-                0x08007a08       0x7e ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
-                0x08007a08                HAL_UARTEx_SetTxFifoThreshold
- *fill*         0x08007a86        0x2 
- .text.HAL_UARTEx_SetRxFifoThreshold
-                0x08007a88       0x84 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
-                0x08007a88                HAL_UARTEx_SetRxFifoThreshold
- .text.HAL_UARTEx_ReceiveToIdle_DMA
-                0x08007b0c       0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
-                0x08007b0c                HAL_UARTEx_ReceiveToIdle_DMA
+                0x08004532       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.UART_DMAAbortOnError
+                0x08004586       0x12 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.HAL_UART_IRQHandler
+                0x08004598      0x344 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x08004598                HAL_UART_IRQHandler
+ .text.UART_DMARxHalfCplt
+                0x080048dc       0x3a ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ *fill*         0x08004916        0x2 
+ .text.UART_DMAReceiveCplt
+                0x08004918       0xb8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ .text.UART_SetConfig
+                0x080049d0      0x184 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x080049d0                UART_SetConfig
+ .text.UART_AdvFeatureConfig
+                0x08004b54       0xd0 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x08004b54                UART_AdvFeatureConfig
+ .text.UART_WaitOnFlagUntilTimeout
+                0x08004c24       0x92 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x08004c24                UART_WaitOnFlagUntilTimeout
+ .text.HAL_UART_Transmit
+                0x08004cb6       0xd4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x08004cb6                HAL_UART_Transmit
+ *fill*         0x08004d8a        0x2 
+ .text.UART_CheckIdleState
+                0x08004d8c       0xc8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x08004d8c                UART_CheckIdleState
+ .text.HAL_UART_Init
+                0x08004e54       0x68 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x08004e54                HAL_UART_Init
+ .text.UART_Start_Receive_DMA
+                0x08004ebc       0xac ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x08004ebc                UART_Start_Receive_DMA
  .text.UARTEx_SetNbDataToProcess
-                0x08007bdc       0xbc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
- .text.memcmp   0x08007c98       0x1c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcmp.o)
-                0x08007c98                memcmp
- .text.memset   0x08007cb4       0x10 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o)
-                0x08007cb4                memset
+                0x08004f68       0x50 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+ .text.HAL_RS485Ex_Init
+                0x08004fb8       0x8c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x08004fb8                HAL_RS485Ex_Init
+ .text.HAL_UARTEx_WakeupCallback
+                0x08005044        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x08005044                HAL_UARTEx_WakeupCallback
+ .text.HAL_UARTEx_RxFifoFullCallback
+                0x08005046        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x08005046                HAL_UARTEx_RxFifoFullCallback
+ .text.HAL_UARTEx_TxFifoEmptyCallback
+                0x08005048        0x2 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x08005048                HAL_UARTEx_TxFifoEmptyCallback
+ *fill*         0x0800504a        0x2 
+ .text.HAL_UARTEx_DisableFifoMode
+                0x0800504c       0x3c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x0800504c                HAL_UARTEx_DisableFifoMode
+ .text.HAL_UARTEx_SetTxFifoThreshold
+                0x08005088       0x40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x08005088                HAL_UARTEx_SetTxFifoThreshold
+ .text.HAL_UARTEx_SetRxFifoThreshold
+                0x080050c8       0x44 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x080050c8                HAL_UARTEx_SetRxFifoThreshold
+ .text.HAL_UARTEx_ReceiveToIdle_DMA
+                0x0800510c       0x64 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x0800510c                HAL_UARTEx_ReceiveToIdle_DMA
+ .text.memcmp   0x08005170       0x1c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcmp.o)
+                0x08005170                memcmp
+ .text.memset   0x0800518c       0x10 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memset.o)
+                0x0800518c                memset
  .text.__libc_init_array
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-                0x08007cc4                __libc_init_array
- .text.memcpy   0x08007d0c       0x12 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o)
-                0x08007d0c                memcpy
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+                0x0800519c                __libc_init_array
+ .text.memcpy   0x080051e4       0x12 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc_nano.a(libc_a-memcpy-stub.o)
+                0x080051e4                memcpy
  *(.glue_7)
- .glue_7        0x08007d1e        0x0 linker stubs
+ .glue_7        0x080051f6        0x0 linker stubs
  *(.glue_7t)
- .glue_7t       0x08007d1e        0x0 linker stubs
+ .glue_7t       0x080051f6        0x0 linker stubs
  *(.eh_frame)
- *fill*         0x08007d1e        0x2 
- .eh_frame      0x08007d20        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o
+ *fill*         0x080051f6        0x2 
+ .eh_frame      0x080051f8        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o
  *(.init)
- .init          0x08007d20        0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o
-                0x08007d20                _init
- .init          0x08007d24        0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o
+ .init          0x080051f8        0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o
+                0x080051f8                _init
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  *(.fini)
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-                0x08007d2c                _fini
- .fini          0x08007d30        0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtn.o
-                0x08007d38                        . = ALIGN (0x4)
-                0x08007d38                        _etext = .
+ .fini          0x08005204        0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o
+                0x08005204                _fini
+ .fini          0x08005208        0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtn.o
+                0x08005210                        . = ALIGN (0x4)
+                0x08005210                        _etext = .
 
-.vfp11_veneer   0x08007d38        0x0
- .vfp11_veneer  0x08007d38        0x0 linker stubs
+.vfp11_veneer   0x08005210        0x0
+ .vfp11_veneer  0x08005210        0x0 linker stubs
 
-.v4_bx          0x08007d38        0x0
- .v4_bx         0x08007d38        0x0 linker stubs
+.v4_bx          0x08005210        0x0
+ .v4_bx         0x08005210        0x0 linker stubs
 
-.iplt           0x08007d38        0x0
- .iplt          0x08007d38        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o
+.iplt           0x08005210        0x0
+ .iplt          0x08005210        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o
 
-.rodata         0x08007d38      0x154
-                0x08007d38                        . = ALIGN (0x4)
+.rodata         0x08005210       0xa8
+                0x08005210                        . = ALIGN (0x4)
  *(.rodata)
- .rodata        0x08007d38       0x11 ./Core/Src/main.o
  *(.rodata*)
- *fill*         0x08007d49        0x3 
+ .rodata.debug_hex8.str1.1
+                0x08005210       0x11 ./Core/Src/main.o
  .rodata.VERSION_STRING
-                0x08007d4c        0xa ./Core/Src/main.o
-                0x08007d4c                VERSION_STRING
- *fill*         0x08007d56        0x2 
- .rodata.handleRS485Message
-                0x08007d58       0x30 ./Core/Src/main.o
- .rodata.feed_state_machine_update
-                0x08007d88       0x28 ./Core/Src/main.o
- .rodata.AHBPrescTable
-                0x08007db0       0x40 ./Core/Src/system_stm32c0xx.o
-                0x08007db0                AHBPrescTable
+                0x08005221        0xa ./Core/Src/main.o
+                0x08005221                VERSION_STRING
+ *fill*         0x0800522b        0x1 
  .rodata.APBPrescTable
-                0x08007df0       0x20 ./Core/Src/system_stm32c0xx.o
-                0x08007df0                APBPrescTable
- .rodata.HAL_TIM_PWM_ConfigChannel
-                0x08007e10       0x54 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+                0x0800522c       0x20 ./Core/Src/system_stm32c0xx.o
+                0x0800522c                APBPrescTable
+ .rodata.AHBPrescTable
+                0x0800524c       0x40 ./Core/Src/system_stm32c0xx.o
+                0x0800524c                AHBPrescTable
+ .rodata.CSWTCH.66
+                0x0800528c        0x3 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+ *fill*         0x0800528f        0x1 
  .rodata.UARTPrescTable
-                0x08007e64       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
-                0x08007e64                UARTPrescTable
- .rodata.numerator.1
-                0x08007e7c        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x08005290       0x18 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
+                0x08005290                UARTPrescTable
  .rodata.denominator.0
-                0x08007e84        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
-                0x08007e8c                        . = ALIGN (0x4)
+                0x080052a8        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+ .rodata.numerator.1
+                0x080052b0        0x8 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart_ex.o
+                0x080052b8                        . = ALIGN (0x4)
 
-.ARM.extab      0x08007e8c        0x0
-                0x08007e8c                        . = ALIGN (0x4)
+.ARM.extab      0x080052b8        0x0
+                0x080052b8                        . = ALIGN (0x4)
  *(.ARM.extab* .gnu.linkonce.armextab.*)
-                0x08007e8c                        . = ALIGN (0x4)
+                0x080052b8                        . = ALIGN (0x4)
 
-.ARM            0x08007e8c        0x8
-                0x08007e8c                        . = ALIGN (0x4)
-                0x08007e8c                        __exidx_start = .
+.ARM            0x080052b8        0x8
+                0x080052b8                        . = ALIGN (0x4)
+                0x080052b8                        __exidx_start = .
  *(.ARM.exidx*)
- .ARM.exidx     0x08007e8c        0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp\libgcc.a(_divdi3.o)
-                0x08007e94                        __exidx_end = .
-                0x08007e94                        . = ALIGN (0x4)
+ .ARM.exidx     0x080052b8        0x8 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divdi3.o)
+                0x080052c0                        __exidx_end = .
+                0x080052c0                        . = ALIGN (0x4)
 
-.preinit_array  0x08007e94        0x0
-                0x08007e94                        . = ALIGN (0x4)
-                0x08007e94                        PROVIDE (__preinit_array_start = .)
+.preinit_array  0x080052c0        0x0
+                0x080052c0                        . = ALIGN (0x4)
+                0x080052c0                        PROVIDE (__preinit_array_start = .)
  *(.preinit_array*)
-                0x08007e94                        PROVIDE (__preinit_array_end = .)
-                0x08007e94                        . = ALIGN (0x4)
+                0x080052c0                        PROVIDE (__preinit_array_end = .)
+                0x080052c0                        . = ALIGN (0x4)
 
-.init_array     0x08007e94        0x4
-                0x08007e94                        . = ALIGN (0x4)
-                0x08007e94                        PROVIDE (__init_array_start = .)
+.init_array     0x080052c0        0x4
+                0x080052c0                        . = ALIGN (0x4)
+                0x080052c0                        PROVIDE (__init_array_start = .)
  *(SORT_BY_NAME(.init_array.*))
  *(.init_array*)
- .init_array    0x08007e94        0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o
-                0x08007e98                        PROVIDE (__init_array_end = .)
-                0x08007e98                        . = ALIGN (0x4)
+ .init_array    0x080052c0        0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o
+                0x080052c4                        PROVIDE (__init_array_end = .)
+                0x080052c4                        . = ALIGN (0x4)
 
-.fini_array     0x08007e98        0x4
-                0x08007e98                        . = ALIGN (0x4)
+.fini_array     0x080052c4        0x4
+                0x080052c4                        . = ALIGN (0x4)
                 [!provide]                        PROVIDE (__fini_array_start = .)
  *(SORT_BY_NAME(.fini_array.*))
  *(.fini_array*)
- .fini_array    0x08007e98        0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o
+ .fini_array    0x080052c4        0x4 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o
                 [!provide]                        PROVIDE (__fini_array_end = .)
-                0x08007e9c                        . = ALIGN (0x4)
-                0x08007e9c                        _sidata = LOADADDR (.data)
+                0x080052c8                        . = ALIGN (0x4)
+                0x080052c8                        _sidata = LOADADDR (.data)
 
-.rel.dyn        0x08007e9c        0x0
- .rel.iplt      0x08007e9c        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o
+.rel.dyn        0x080052c8        0x0
+ .rel.iplt      0x080052c8        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o
 
-.data           0x20000000       0x30 load address 0x08007e9c
+.data           0x20000000       0x30 load address 0x080052c8
                 0x20000000                        . = ALIGN (0x4)
                 0x20000000                        _sdata = .
  *(.data)
  *(.data*)
- .data.msg_buffer1_empty
+ .data.debug_enabled
                 0x20000000        0x1 ./Core/Src/main.o
-                0x20000000                msg_buffer1_empty
- .data.msg_buffer2_empty
+                0x20000000                debug_enabled
+ .data.floor_address
                 0x20000001        0x1 ./Core/Src/main.o
-                0x20000001                msg_buffer2_empty
- .data.my_address
+                0x20000001                floor_address
+ .data.feed_direction
                 0x20000002        0x1 ./Core/Src/main.o
-                0x20000002                my_address
+                0x20000002                feed_direction
  *fill*         0x20000003        0x1 
- .data.kp       0x20000004        0x4 ./Core/Src/main.o
-                0x20000004                kp
- .data.ki       0x20000008        0x4 ./Core/Src/main.o
-                0x20000008                ki
- .data.kd       0x2000000c        0x4 ./Core/Src/main.o
-                0x2000000c                kd
+ .data.brake_time_tenths
+                0x20000004        0x4 ./Core/Src/main.o
+                0x20000004                brake_time_tenths
+ .data.pid_max_step
+                0x20000008        0x4 ./Core/Src/main.o
+                0x20000008                pid_max_step
+ .data.i_max    0x2000000c        0x4 ./Core/Src/main.o
+                0x2000000c                i_max
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                 0x20000010                i_min
- .data.i_max    0x20000014        0x4 ./Core/Src/main.o
-                0x20000014                i_max
- .data.pid_max_step
-                0x20000018        0x4 ./Core/Src/main.o
-                0x20000018                pid_max_step
- .data.feed_direction
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-                0x2000001c                feed_direction
- .data.first_feed_since_load
-                0x2000001d        0x1 ./Core/Src/main.o
-                0x2000001d                first_feed_since_load
- .data.current_drive_value
-                0x2000001e        0x1 ./Core/Src/main.o
-                0x2000001e                current_drive_value
- .data.floor_address
-                0x2000001f        0x1 ./Core/Src/main.o
-                0x2000001f                floor_address
- .data.debug_enabled
+ .data.kd       0x20000014        0x4 ./Core/Src/main.o
+                0x20000014                kd
+ .data.ki       0x20000018        0x4 ./Core/Src/main.o
+                0x20000018                ki
+ .data.kp       0x2000001c        0x4 ./Core/Src/main.o
+                0x2000001c                kp
+ .data.my_address
                 0x20000020        0x1 ./Core/Src/main.o
-                0x20000020                debug_enabled
+                0x20000020                my_address
  *fill*         0x20000021        0x3 
  .data.SystemCoreClock
                 0x20000024        0x4 ./Core/Src/system_stm32c0xx.o
                 0x20000024                SystemCoreClock
- .data.uwTickPrio
-                0x20000028        0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
-                0x20000028                uwTickPrio
  .data.uwTickFreq
-                0x2000002c        0x1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
-                0x2000002c                uwTickFreq
+                0x20000028        0x1 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x20000028                uwTickFreq
+ *fill*         0x20000029        0x3 
+ .data.uwTickPrio
+                0x2000002c        0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x2000002c                uwTickPrio
  *(.RamFunc)
  *(.RamFunc*)
                 0x20000030                        . = ALIGN (0x4)
- *fill*         0x2000002d        0x3 
                 0x20000030                        _edata = .
 
-.igot.plt       0x20000030        0x0 load address 0x08007ecc
- .igot.plt      0x20000030        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o
+.igot.plt       0x20000030        0x0 load address 0x080052f8
+ .igot.plt      0x20000030        0x0 C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o
                 0x20000030                        . = ALIGN (0x4)
 
-.bss            0x20000030      0x580 load address 0x08007ecc
+.bss            0x20000030     0x1334 load address 0x080052f8
                 0x20000030                        _sbss = .
                 0x20000030                        __bss_start__ = _sbss
  *(.bss)
- .bss           0x20000030       0x1c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o
+ .bss           0x20000030       0x1c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o
  *(.bss*)
- .bss.htim1     0x2000004c       0x4c ./Core/Src/main.o
-                0x2000004c                htim1
- .bss.htim3     0x20000098       0x4c ./Core/Src/main.o
-                0x20000098                htim3
- .bss.htim14    0x200000e4       0x4c ./Core/Src/main.o
-                0x200000e4                htim14
- .bss.htim16    0x20000130       0x4c ./Core/Src/main.o
-                0x20000130                htim16
- .bss.htim17    0x2000017c       0x4c ./Core/Src/main.o
-                0x2000017c                htim17
- .bss.huart1    0x200001c8       0x94 ./Core/Src/main.o
-                0x200001c8                huart1
- .bss.huart2    0x2000025c       0x94 ./Core/Src/main.o
-                0x2000025c                huart2
- .bss.hdma_usart2_rx
-                0x200002f0       0x5c ./Core/Src/main.o
-                0x200002f0                hdma_usart2_rx
- .bss.hdma_usart2_tx
-                0x2000034c       0x5c ./Core/Src/main.o
-                0x2000034c                hdma_usart2_tx
- .bss.sw1_pressed
-                0x200003a8        0x1 ./Core/Src/main.o
-                0x200003a8                sw1_pressed
- .bss.sw2_pressed
-                0x200003a9        0x1 ./Core/Src/main.o
-                0x200003a9                sw2_pressed
- *fill*         0x200003aa        0x2 
- .bss.encoder_count_extra
-                0x200003ac        0x4 ./Core/Src/main.o
-                0x200003ac                encoder_count_extra
- .bss.encoder_previous
-                0x200003b0        0x2 ./Core/Src/main.o
-                0x200003b0                encoder_previous
- *fill*         0x200003b2        0x2 
- .bss.UUID      0x200003b4        0xc ./Core/Src/main.o
-                0x200003b4                UUID
- .bss.is_initialized
-                0x200003c0        0x1 ./Core/Src/main.o
-                0x200003c0                is_initialized
- .bss.msg_buffer1_size
-                0x200003c1        0x1 ./Core/Src/main.o
-                0x200003c1                msg_buffer1_size
- .bss.msg_buffer2_size
-                0x200003c2        0x1 ./Core/Src/main.o
-                0x200003c2                msg_buffer2_size
- *fill*         0x200003c3        0x1 
- .bss.msg_buffer1
-                0x200003c4       0x40 ./Core/Src/main.o
-                0x200003c4                msg_buffer1
- .bss.msg_buffer2
-                0x20000404       0x40 ./Core/Src/main.o
-                0x20000404                msg_buffer2
- .bss.DMA_buffer
-                0x20000444       0x40 ./Core/Src/main.o
-                0x20000444                DMA_buffer
- .bss.total_count
-                0x20000484        0x4 ./Core/Src/main.o
-                0x20000484                total_count
- .bss.target_count
-                0x20000488        0x4 ./Core/Src/main.o
-                0x20000488                target_count
- .bss.motor_pid
-                0x2000048c       0x28 ./Core/Src/main.o
-                0x2000048c                motor_pid
- .bss.motor_cmd
-                0x200004b4        0x4 ./Core/Src/main.o
-                0x200004b4                motor_cmd
- .bss.pid_add   0x200004b8        0x4 ./Core/Src/main.o
-                0x200004b8                pid_add
- .bss.last_feed_status
-                0x200004bc        0x1 ./Core/Src/main.o
-                0x200004bc                last_feed_status
- .bss.feed_in_progress
-                0x200004bd        0x1 ./Core/Src/main.o
-                0x200004bd                feed_in_progress
- .bss.feed_just_completed
-                0x200004be        0x1 ./Core/Src/main.o
-                0x200004be                feed_just_completed
- .bss.feed_state
-                0x200004bf        0x1 ./Core/Src/main.o
-                0x200004bf                feed_state
- .bss.feed_state_start_time
-                0x200004c0        0x4 ./Core/Src/main.o
-                0x200004c0                feed_state_start_time
- .bss.feed_state_duration
-                0x200004c4        0x4 ./Core/Src/main.o
-                0x200004c4                feed_state_duration
- .bss.feed_timeout_time
-                0x200004c8        0x4 ./Core/Src/main.o
-                0x200004c8                feed_timeout_time
- .bss.feed_distance_tenths
-                0x200004cc        0x2 ./Core/Src/main.o
-                0x200004cc                feed_distance_tenths
- *fill*         0x200004ce        0x2 
- .bss.feed_target_position
-                0x200004d0        0x4 ./Core/Src/main.o
-                0x200004d0                feed_target_position
- .bss.feed_retry_count
-                0x200004d4        0x1 ./Core/Src/main.o
-                0x200004d4                feed_retry_count
- .bss.beefy_tape
-                0x200004d5        0x1 ./Core/Src/main.o
-                0x200004d5                beefy_tape
- .bss.peel_target_pwm
-                0x200004d6        0x2 ./Core/Src/main.o
-                0x200004d6                peel_target_pwm
- .bss.peel_current_pwm
-                0x200004d8        0x2 ./Core/Src/main.o
-                0x200004d8                peel_current_pwm
- *fill*         0x200004da        0x2 
- .bss.peel_last_ramp_time
-                0x200004dc        0x4 ./Core/Src/main.o
-                0x200004dc                peel_last_ramp_time
- .bss.drive_mode
-                0x200004e0        0x1 ./Core/Src/main.o
-                0x200004e0                drive_mode
- .bss.driving   0x200004e1        0x1 ./Core/Src/main.o
-                0x200004e1                driving
- .bss.driving_direction
-                0x200004e2        0x1 ./Core/Src/main.o
-                0x200004e2                driving_direction
- .bss.sw1_long_handled
-                0x200004e3        0x1 ./Core/Src/main.o
-                0x200004e3                sw1_long_handled
- .bss.sw2_long_handled
-                0x200004e4        0x1 ./Core/Src/main.o
-                0x200004e4                sw2_long_handled
- .bss.both_pressed_handled
-                0x200004e5        0x1 ./Core/Src/main.o
-                0x200004e5                both_pressed_handled
- *fill*         0x200004e6        0x2 
- .bss.both_pressed_start
-                0x200004e8        0x4 ./Core/Src/main.o
-                0x200004e8                both_pressed_start
- .bss.stall_history
-                0x200004ec       0x50 ./Core/Src/main.o
-                0x200004ec                stall_history
- .bss.stall_history_index
-                0x2000053c        0x1 ./Core/Src/main.o
-                0x2000053c                stall_history_index
- *fill*         0x2000053d        0x3 
- .bss.last_stall_sample_time
-                0x20000540        0x4 ./Core/Src/main.o
-                0x20000540                last_stall_sample_time
- .bss.stall_cooldown
-                0x20000544        0x1 ./Core/Src/main.o
-                0x20000544                stall_cooldown
- *fill*         0x20000545        0x3 
- .bss.stall_cooldown_time
-                0x20000548        0x4 ./Core/Src/main.o
-                0x20000548                stall_cooldown_time
- .bss.floor_address_status
-                0x2000054c        0x1 ./Core/Src/main.o
-                0x2000054c                floor_address_status
- *fill*         0x2000054d        0x3 
- .bss.mm_position
-                0x20000550        0x4 ./Core/Src/main.o
-                0x20000550                mm_position
- .bss.last_debug_output_time
-                0x20000554        0x4 ./Core/Src/main.o
-                0x20000554                last_debug_output_time
- .bss.debug_tx_buffer
-                0x20000558       0x50 ./Core/Src/main.o
-                0x20000558                debug_tx_buffer
+ .bss.still_counter.0
+                0x2000004c        0x2 ./Core/Src/main.o
+ *fill*         0x2000004e        0x2 
+ .bss.last_moved_pos.1
+                0x20000050        0x4 ./Core/Src/main.o
+ .bss.velocity.2
+                0x20000054        0x4 ./Core/Src/main.o
+ .bss.vel_prev_pos.3
+                0x20000058        0x4 ./Core/Src/main.o
+ .bss.vel_counter.4
+                0x2000005c        0x1 ./Core/Src/main.o
+ .bss.my_addr_crc_exp
+                0x2000005d        0x1 ./Core/Src/main.o
+                0x2000005d                my_addr_crc_exp
+ .bss.my_addr_size
+                0x2000005e        0x1 ./Core/Src/main.o
+                0x2000005e                my_addr_size
+ .bss.my_addr_bytes
+                0x2000005f        0x8 ./Core/Src/main.o
+                0x2000005f                my_addr_bytes
+ .bss.last_rx_bytes
+                0x20000067        0x8 ./Core/Src/main.o
+                0x20000067                last_rx_bytes
+ .bss.last_rx_cmd
+                0x2000006f        0x1 ./Core/Src/main.o
+                0x2000006f                last_rx_cmd
+ .bss.last_rx_to
+                0x20000070        0x1 ./Core/Src/main.o
+                0x20000070                last_rx_to
+ .bss.last_rx_size
+                0x20000071        0x1 ./Core/Src/main.o
+                0x20000071                last_rx_size
+ .bss.msg_handled
+                0x20000072        0x2 ./Core/Src/main.o
+                0x20000072                msg_handled
+ .bss.drop_addr
+                0x20000074        0x2 ./Core/Src/main.o
+                0x20000074                drop_addr
+ .bss.drop_crc  0x20000076        0x2 ./Core/Src/main.o
+                0x20000076                drop_crc
+ .bss.drop_size
+                0x20000078        0x2 ./Core/Src/main.o
+                0x20000078                drop_size
+ .bss.uart_error_count
+                0x2000007a        0x2 ./Core/Src/main.o
+                0x2000007a                uart_error_count
  .bss.debug_pid_output
-                0x200005a8        0x2 ./Core/Src/main.o
-                0x200005a8                debug_pid_output
- *fill*         0x200005aa        0x2 
- .bss.uwTick    0x200005ac        0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
-                0x200005ac                uwTick
+                0x2000007c        0x2 ./Core/Src/main.o
+                0x2000007c                debug_pid_output
+ .bss.debug_tx_buffer
+                0x2000007e       0x60 ./Core/Src/main.o
+                0x2000007e                debug_tx_buffer
+ *fill*         0x200000de        0x2 
+ .bss.last_debug_output_time
+                0x200000e0        0x4 ./Core/Src/main.o
+                0x200000e0                last_debug_output_time
+ .bss.mm_position
+                0x200000e4        0x4 ./Core/Src/main.o
+                0x200000e4                mm_position
+ .bss.floor_address_status
+                0x200000e8        0x1 ./Core/Src/main.o
+                0x200000e8                floor_address_status
+ *fill*         0x200000e9        0x3 
+ .bss.both_pressed_start
+                0x200000ec        0x4 ./Core/Src/main.o
+                0x200000ec                both_pressed_start
+ .bss.both_pressed_handled
+                0x200000f0        0x1 ./Core/Src/main.o
+                0x200000f0                both_pressed_handled
+ .bss.sw2_long_handled
+                0x200000f1        0x1 ./Core/Src/main.o
+                0x200000f1                sw2_long_handled
+ .bss.sw1_long_handled
+                0x200000f2        0x1 ./Core/Src/main.o
+                0x200000f2                sw1_long_handled
+ .bss.driving_direction
+                0x200000f3        0x1 ./Core/Src/main.o
+                0x200000f3                driving_direction
+ .bss.driving   0x200000f4        0x1 ./Core/Src/main.o
+                0x200000f4                driving
+ .bss.drive_mode
+                0x200000f5        0x1 ./Core/Src/main.o
+                0x200000f5                drive_mode
+ *fill*         0x200000f6        0x2 
+ .bss.peel_last_ramp_time
+                0x200000f8        0x4 ./Core/Src/main.o
+                0x200000f8                peel_last_ramp_time
+ .bss.peel_current_pwm
+                0x200000fc        0x2 ./Core/Src/main.o
+                0x200000fc                peel_current_pwm
+ .bss.peel_target_pwm
+                0x200000fe        0x2 ./Core/Src/main.o
+                0x200000fe                peel_target_pwm
+ .bss.feed_retry_count
+                0x20000100        0x1 ./Core/Src/main.o
+                0x20000100                feed_retry_count
+ *fill*         0x20000101        0x3 
+ .bss.feed_target_position
+                0x20000104        0x4 ./Core/Src/main.o
+                0x20000104                feed_target_position
+ .bss.feed_distance_tenths
+                0x20000108        0x2 ./Core/Src/main.o
+                0x20000108                feed_distance_tenths
+ *fill*         0x2000010a        0x2 
+ .bss.feed_timeout_time
+                0x2000010c        0x4 ./Core/Src/main.o
+                0x2000010c                feed_timeout_time
+ .bss.feed_state_duration
+                0x20000110        0x4 ./Core/Src/main.o
+                0x20000110                feed_state_duration
+ .bss.feed_state_start_time
+                0x20000114        0x4 ./Core/Src/main.o
+                0x20000114                feed_state_start_time
+ .bss.feed_state
+                0x20000118        0x1 ./Core/Src/main.o
+                0x20000118                feed_state
+ *fill*         0x20000119        0x1 
+ .bss.feed_retry_total
+                0x2000011a        0x2 ./Core/Src/main.o
+                0x2000011a                feed_retry_total
+ .bss.feed_fail_count
+                0x2000011c        0x2 ./Core/Src/main.o
+                0x2000011c                feed_fail_count
+ .bss.feed_ok_count
+                0x2000011e        0x2 ./Core/Src/main.o
+                0x2000011e                feed_ok_count
+ .bss.feed_just_completed
+                0x20000120        0x1 ./Core/Src/main.o
+                0x20000120                feed_just_completed
+ .bss.feed_in_progress
+                0x20000121        0x1 ./Core/Src/main.o
+                0x20000121                feed_in_progress
+ .bss.last_feed_status
+                0x20000122        0x1 ./Core/Src/main.o
+                0x20000122                last_feed_status
+ *fill*         0x20000123        0x1 
+ .bss.pid_add   0x20000124        0x4 ./Core/Src/main.o
+                0x20000124                pid_add
+ .bss.motor_pid
+                0x20000128       0x28 ./Core/Src/main.o
+                0x20000128                motor_pid
+ .bss.target_count
+                0x20000150        0x4 ./Core/Src/main.o
+                0x20000150                target_count
+ .bss.total_count
+                0x20000154        0x4 ./Core/Src/main.o
+                0x20000154                total_count
+ .bss.rx_msg_count
+                0x20000158        0x2 ./Core/Src/main.o
+                0x20000158                rx_msg_count
+ .bss.DMA_buffer
+                0x2000015a       0x40 ./Core/Src/main.o
+                0x2000015a                DMA_buffer
+ .bss.msg_buf   0x2000019a      0xd80 ./Core/Src/main.o
+                0x2000019a                msg_buf
+ .bss.msg_buf_size
+                0x20000f1a       0x36 ./Core/Src/main.o
+                0x20000f1a                msg_buf_size
+ .bss.msg_buf_empty
+                0x20000f50       0x36 ./Core/Src/main.o
+                0x20000f50                msg_buf_empty
+ .bss.is_initialized
+                0x20000f86        0x1 ./Core/Src/main.o
+                0x20000f86                is_initialized
+ .bss.UUID      0x20000f87        0xc ./Core/Src/main.o
+                0x20000f87                UUID
+ *fill*         0x20000f93        0x1 
+ .bss.encoder_previous
+                0x20000f94        0x2 ./Core/Src/main.o
+                0x20000f94                encoder_previous
+ *fill*         0x20000f96        0x2 
+ .bss.encoder_count_extra
+                0x20000f98        0x4 ./Core/Src/main.o
+                0x20000f98                encoder_count_extra
+ .bss.sw2_pressed
+                0x20000f9c        0x1 ./Core/Src/main.o
+                0x20000f9c                sw2_pressed
+ .bss.sw1_pressed
+                0x20000f9d        0x1 ./Core/Src/main.o
+                0x20000f9d                sw1_pressed
+ *fill*         0x20000f9e        0x2 
+ .bss.hdma_usart2_tx
+                0x20000fa0       0x5c ./Core/Src/main.o
+                0x20000fa0                hdma_usart2_tx
+ .bss.hdma_usart2_rx
+                0x20000ffc       0x5c ./Core/Src/main.o
+                0x20000ffc                hdma_usart2_rx
+ .bss.huart2    0x20001058       0x94 ./Core/Src/main.o
+                0x20001058                huart2
+ .bss.huart1    0x200010ec       0x94 ./Core/Src/main.o
+                0x200010ec                huart1
+ .bss.htim17    0x20001180       0x4c ./Core/Src/main.o
+                0x20001180                htim17
+ .bss.htim16    0x200011cc       0x4c ./Core/Src/main.o
+                0x200011cc                htim16
+ .bss.htim14    0x20001218       0x4c ./Core/Src/main.o
+                0x20001218                htim14
+ .bss.htim3     0x20001264       0x4c ./Core/Src/main.o
+                0x20001264                htim3
+ .bss.htim1     0x200012b0       0x4c ./Core/Src/main.o
+                0x200012b0                htim1
+ .bss.hadc1     0x200012fc       0x64 ./Core/Src/main.o
+                0x200012fc                hadc1
+ .bss.uwTick    0x20001360        0x4 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
+                0x20001360                uwTick
  *(COMMON)
-                0x200005b0                        . = ALIGN (0x4)
-                0x200005b0                        _ebss = .
-                0x200005b0                        __bss_end__ = _ebss
+                0x20001364                        . = ALIGN (0x4)
+                0x20001364                        _ebss = .
+                0x20001364                        __bss_end__ = _ebss
 
 ._user_heap_stack
-                0x200005b0      0x600 load address 0x08007ecc
-                0x200005b0                        . = ALIGN (0x8)
+                0x20001364      0x604 load address 0x080052f8
+                0x20001368                        . = ALIGN (0x8)
+ *fill*         0x20001364        0x4 
                 [!provide]                        PROVIDE (end = .)
-                0x200005b0                        PROVIDE (_end = .)
-                0x200007b0                        . = (. + _Min_Heap_Size)
- *fill*         0x200005b0      0x200 
-                0x20000bb0                        . = (. + _Min_Stack_Size)
- *fill*         0x200007b0      0x400 
-                0x20000bb0                        . = ALIGN (0x8)
+                0x20001368                        PROVIDE (_end = .)
+                0x20001568                        . = (. + _Min_Heap_Size)
+ *fill*         0x20001368      0x200 
+                0x20001968                        . = (. + _Min_Stack_Size)
+ *fill*         0x20001568      0x400 
+                0x20001968                        . = ALIGN (0x8)
 
 /DISCARD/
  libc.a(*)
@@ -3978,9 +4319,9 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext
                 0x00000000       0x28
  *(.ARM.attributes)
  .ARM.attributes
-                0x00000000       0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crti.o
+                0x00000000       0x1e C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crti.o
  .ARM.attributes
-                0x0000001e       0x2c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/thumb/v6-m/nofp/crtbegin.o
+                0x0000001e       0x2c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp/crtbegin.o
  .ARM.attributes
                 0x0000004a       0x2c ./Core/Src/crc.o
  .ARM.attributes
@@ -3996,347 +4337,371 @@ LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.ext
  .ARM.attributes
                 0x00000148       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
  .ARM.attributes
-                0x00000174       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+                0x00000174       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o
  .ARM.attributes
-                0x000001a0       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
+                0x000001a0       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
  .ARM.attributes
-                0x000001cc       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
+                0x000001cc       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
  .ARM.attributes
-                0x000001f8       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
+                0x000001f8       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_gpio.o
  .ARM.attributes
-                0x00000224       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+                0x00000224       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc.o
  .ARM.attributes
-                0x00000250       0x2c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
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 OUTPUT(feeder_mk2.elf elf32-littlearm)
 LOAD linker stubs
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-LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.13.3.rel1.win32_1.0.100.202509120712/tools/bin/../lib/gcc/arm-none-eabi/13.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a
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+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libc.a
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/nofp\libm.a
+LOAD C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a
 
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- .debug_info    0x00004f58      0x36f ./Core/Src/system_stm32c0xx.o
- .debug_info    0x000052c7       0x30 ./Core/Startup/startup_stm32c051c6tx.o
- .debug_info    0x000052f7      0x844 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o
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- .debug_info    0x00007ac4      0x551 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
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+.debug_info     0x00000000    0x1b022
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+ .debug_info    0x0000b13e      0xa1c ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o
+ .debug_info    0x0000bb5a      0x9fc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o
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+ .debug_info    0x0000d680      0x5cc ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_rcc_ex.o
+ .debug_info    0x0000dc4c     0x4334 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim.o
+ .debug_info    0x00011f80     0x1d40 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_tim_ex.o
+ .debug_info    0x00013cc0     0x6102 ./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_uart.o
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+ .debug_frame   0x00002b74       0x3c C:/ST/STM32CubeIDE_1.14.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.14.3.rel1.win32_1.0.100.202602081740/tools/bin/../lib/gcc/arm-none-eabi/14.3.1/thumb/v6-m/nofp\libgcc.a(_divdi3.o)
 
 .debug_line_str
                 0x00000000       0x4d
diff --git a/code/Debug/makefile b/code/Debug/makefile
index 149975a..2358afb 100644
--- a/code/Debug/makefile
+++ b/code/Debug/makefile
@@ -1,6 +1,6 @@
 ################################################################################
 # Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (13.3.rel1)
+# Toolchain: GNU Tools for STM32 (14.3.rel1)
 ################################################################################
 
 -include ../makefile.init
diff --git a/code/Debug/objects.list b/code/Debug/objects.list
index f188521..3a1431a 100644
--- a/code/Debug/objects.list
+++ b/code/Debug/objects.list
@@ -7,6 +7,8 @@
 "./Core/Src/system_stm32c0xx.o"
 "./Core/Startup/startup_stm32c051c6tx.o"
 "./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal.o"
+"./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.o"
+"./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.o"
 "./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_cortex.o"
 "./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma.o"
 "./Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_dma_ex.o"
diff --git a/code/Debug/objects.mk b/code/Debug/objects.mk
index b471e98..281954c 100644
--- a/code/Debug/objects.mk
+++ b/code/Debug/objects.mk
@@ -1,6 +1,6 @@
 ################################################################################
 # Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (13.3.rel1)
+# Toolchain: GNU Tools for STM32 (14.3.rel1)
 ################################################################################
 
 USER_OBJS :=
diff --git a/code/Debug/sources.mk b/code/Debug/sources.mk
index ad88b61..c79997e 100644
--- a/code/Debug/sources.mk
+++ b/code/Debug/sources.mk
@@ -1,6 +1,6 @@
 ################################################################################
 # Automatically-generated file. Do not edit!
-# Toolchain: GNU Tools for STM32 (13.3.rel1)
+# Toolchain: GNU Tools for STM32 (14.3.rel1)
 ################################################################################
 
 ELF_SRCS := 
diff --git a/code/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h b/code/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h
new file mode 100644
index 0000000..07388f8
--- /dev/null
+++ b/code/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h
@@ -0,0 +1,1934 @@
+/**
+  ******************************************************************************
+  * @file    stm32c0xx_hal_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_HAL_ADC_H
+#define STM32C0xx_HAL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal_def.h"
+
+/* Include low level driver */
+#include "stm32c0xx_ll_adc.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADC_Exported_Types ADC Exported Types
+  * @{
+  */
+
+/**
+  * @brief  ADC group regular oversampling structure definition
+  */
+typedef struct
+{
+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
+
+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
+
+  uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.
+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */
+
+} ADC_OversamplingTypeDef;
+
+/**
+  * @brief  Structure definition of ADC instance and ADC group regular.
+  * @note   Parameters of this structure are shared within 2 scopes:
+  *          - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC
+  *            groups regular and injected): ClockPrescaler, Resolution, DataAlign,
+  *            ScanConvMode, EOCSelection, LowPowerAutoWait.
+  *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode,
+  *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.
+  * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled
+  *          - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on
+  *            group regular.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another
+  *         parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous
+                                       clock derived from system clock or PLL (Refer to reference manual for list of
+                                       clocks available)) and clock prescaler.
+                                       This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
+                                       Note: The ADC clock configuration is common to all ADC instances.
+                                       Note: In case of synchronous clock mode based on HCLK/1, the configuration must
+                                             be enabled only if the system clock has a 50% duty clock cycle (APB
+                                             prescaler configured inside RCC  must be bypassed and PCLK clock must have
+                                             50% duty cycle). Refer to reference manual for details.
+                                       Note: In case of usage of asynchronous clock, the selected clock must be
+                                             preliminarily enabled at RCC top level.
+                                       Note: This parameter can be modified only if all ADC instances are disabled. */
+
+  uint32_t Resolution;            /*!< Configure the ADC resolution.
+                                       This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
+
+  uint32_t DataAlign;             /*!< Specify ADC data alignment in conversion data register (right or left).
+                                       Refer to reference manual for alignments formats versus resolutions.
+                                       This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */
+
+  uint32_t ScanConvMode;          /*!< Configure the sequencer of ADC group regular.
+                                       On this STM32 series, ADC group regular sequencer both modes "fully configurable"
+                                       or "not fully configurable" are available:
+                                        - sequencer configured to fully configurable:
+                                          sequencer length and each rank affectation to a channel are configurable.
+                                           - Sequence length: Set number of ranks in the scan sequence.
+                                           - Sequence direction: Unless specified in parameters, sequencer
+                                             scan direction is forward (from rank 1 to rank n).
+                                        - sequencer configured to not fully configurable:
+                                            sequencer length and each rank affectation to a channel are fixed by channel
+                                            HW number.
+                                           - Sequence length: Number of ranks in the scan sequence is
+                                             defined by number of channels set in the sequence,
+                                             rank of each channel is fixed by channel HW number.
+                                             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+                                           - Sequence direction: Unless specified in parameters, sequencer
+                                             scan direction is forward (from lowest channel number to
+                                             highest channel number).
+                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have
+                                       main sequence subdivided in successive parts. Sequencer is automatically enabled
+                                       if several channels are set (sequencer cannot be disabled, as it can be the case
+                                       on other STM32 devices):
+                                       If only 1 channel is set: Conversion is performed in single mode.
+                                       If several channels are set:  Conversions are performed in sequence mode.
+                                       This parameter can be a value of @ref ADC_Scan_mode */
+
+  uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and
+                                       interruption: end of unitary conversion or end of sequence conversions.
+                                       This parameter can be a value of @ref ADC_EOCSelection. */
+
+  FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the
+                                       previous conversion (for ADC group regular) has been retrieved by user software,
+                                       using function HAL_ADC_GetValue().
+                                       This feature automatically adapts the frequency of ADC conversions triggers to
+                                       the speed of the system that reads the data. Moreover, this avoids risk of
+                                       overrun for low frequency applications.
+                                       This parameter can be set to ENABLE or DISABLE.
+                                       Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(),
+                                             HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC
+                                             flag (by CPU to free the IRQ pending event or by DMA).
+                                             Auto wait will work but fort a very short time, discarding its intended
+                                             benefit (except specific case of high load of CPU or DMA transfers which
+                                             can justify usage of auto wait).
+                                             Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on,
+                                             when ADC conversion data is needed:
+                                             use HAL_ADC_PollForConversion() to ensure that conversion is completed and
+                                             HAL_ADC_GetValue() to retrieve conversion result and trig another
+                                             conversion start. */
+
+  FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a
+                                             conversion and automatically wakes-up when a new conversion is triggered
+                                             (with startup time between trigger and start of sampling).
+                                              This feature can be combined with automatic wait mode
+                                             (parameter 'LowPowerAutoWait').
+                                              This parameter can be set to ENABLE or DISABLE. */
+
+  FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion)
+                                           or continuous mode for ADC group regular, after the first ADC conversion
+                                           start trigger occurred (software start or external trigger). This parameter
+                                           can be set to ENABLE or DISABLE. */
+
+  uint32_t NbrOfConversion;       /*!< Specify the number of ranks that will be converted within the regular group
+                                       sequencer.
+                                       This parameter is dependent on ScanConvMode:
+                                        - sequencer configured to fully configurable:
+                                          Number of ranks in the scan sequence is configurable using this parameter.
+                                          Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to
+                                                parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'.
+                                                Afterwards, when all needed sequencer ranks are set, parameter
+                                                'NbrOfConversion' can be updated without modifying configuration of
+                                                sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded).
+                                        - sequencer configured to not fully configurable:
+                                          Number of ranks in the scan sequence is defined by number of channels set in
+                                          the sequence. This parameter is discarded.
+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8.
+                                       Note: This parameter must be modified when no conversion is on going on regular
+                                             group (ADC disabled, or ADC enabled without continuous mode or external
+                                             trigger that could launch a conversion). */
+
+  FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed
+                                              in Complete-sequence/Discontinuous-sequence (main sequence subdivided in
+                                              successive parts).
+                                              Discontinuous mode is used only if sequencer is enabled (parameter
+                                              'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
+                                              Discontinuous mode can be enabled only if continuous mode is disabled.
+                                              If continuous mode is enabled, this parameter setting is discarded.
+                                              This parameter can be set to ENABLE or DISABLE.
+                                              Note: On this STM32 series, ADC group regular number of discontinuous
+                                                    ranks increment is fixed to one-by-one. */
+
+  uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion
+                                       start.
+                                       If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger
+                                       is used instead.
+                                       This parameter can be a value of @ref ADC_regular_external_trigger_source.
+                                       Caution: external trigger source is common to all ADC instances. */
+
+  uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start
+                                       If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
+                                       This parameter can be a value of @ref ADC_regular_external_trigger_edge */
+
+  FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA
+                                              transfer stops when number of conversions is reached) or in continuous
+                                              mode (DMA transfer unlimited, whatever number of conversions).
+                                              This parameter can be set to ENABLE or DISABLE.
+                                              Note: In continuous mode, DMA must be configured in circular mode.
+                                                    Otherwise an overrun will be triggered when DMA buffer maximum
+                                                    pointer is reached. */
+
+  uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
+                                       This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
+                                       Note: In case of overrun set to data preserved and usage with programming model
+                                             with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of
+                                             conversion flags, this induces the release of the preserved data. If
+                                             needed, this data can be saved in function HAL_ADC_ConvCpltCallback(),
+                                             placed in user program code (called before end of conversion flags clear)
+                                       Note: Error reporting with respect to the conversion mode:
+                                             - Usage with ADC conversion by polling for event or interruption: Error is
+                                               reported only if overrun is set to data preserved. If overrun is set to
+                                               data overwritten, user can willingly not read all the converted data,
+                                               this is not considered as an erroneous case.
+                                             - Usage with ADC conversion by DMA: Error is reported whatever overrun
+                                               setting (DMA is expected to process all data from data register). */
+
+  uint32_t SamplingTimeCommon1;   /*!< Set sampling time common to a group of channels.
+                                       Unit: ADC clock cycles
+                                       Conversion time is the addition of sampling time and processing time
+                                       (12.5 ADC clock cycles at ADC resolution 12 bits,
+                                        10.5 cycles at 10 bits,
+                                         8.5 cycles at 8 bits,
+                                         6.5 cycles at 6 bits).
+                                       Note: On this STM32 family, two different sampling time settings are available,
+                                             each channel can use one of these two settings. On some other STM32 devices
+                                             this parameter in channel wise and is located into ADC channel
+                                             initialization structure.
+                                       This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
+                                       Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor)
+                                             sampling time constraints must be respected (sampling time can be adjusted
+                                             in function of ADC clock frequency and sampling time setting)
+                                             Refer to device datasheet for timings values, parameters TS_vrefint,
+                                             TS_vbat, TS_temp (values rough order: few tens of microseconds). */
+
+  uint32_t SamplingTimeCommon2;   /*!< Set sampling time common to a group of channels, second common setting possible.
+                                       Unit: ADC clock cycles
+                                       Conversion time is the addition of sampling time and processing time
+                                       (12.5 ADC clock cycles at ADC resolution 12 bits,
+                                        10.5 cycles at 10 bits,
+                                         8.5 cycles at 8 bits,
+                                         6.5 cycles at 6 bits).
+                                       Note: On this STM32 family, two different sampling time settings are available,
+                                             each channel can use one of these two settings. On some other STM32 devices
+                                             this parameter in channel wise and is located into ADC channel
+                                             initialization structure.
+                                       This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME
+                                       Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor)
+                                             sampling time constraints must be respected (sampling time can be adjusted
+                                             in function of ADC clock frequency and sampling time setting)
+                                             Refer to device datasheet for timings values, parameters TS_vrefint,
+                                             TS_vbat, TS_temp (values rough order: few tens of microseconds). */
+
+  FunctionalState OversamplingMode;       /*!< Specify whether the oversampling feature is enabled or disabled.
+                                               This parameter can be set to ENABLE or DISABLE.
+                                               Note: This parameter can be modified only if there is no conversion is
+                                                     ongoing on ADC group regular. */
+
+  ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.
+                                               Caution: this setting overwrites the previous oversampling configuration
+                                                        if oversampling is already enabled. */
+
+  uint32_t TriggerFrequencyMode;  /*!< Set ADC trigger frequency mode.
+                                       This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ.
+                                       Note: ADC trigger frequency mode must be set to low frequency when
+                                             a duration is exceeded before ADC conversion start trigger event
+                                             (between ADC enable and ADC conversion start trigger event
+                                             or between two ADC conversion start trigger event).
+                                             Duration value: Refer to device datasheet, parameter "tIdle".
+                                       Note: When ADC trigger frequency mode is set to low frequency,
+                                             some rearm cycles are inserted before performing ADC conversion
+                                             start, inducing a delay of 2 ADC clock cycles. */
+
+} ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of ADC channel for regular group
+  * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters: ADC disabled or enabled without conversion on going on regular group.
+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
+  *         without error reporting (as it can be the expected behavior in case of intended action to update another
+  *         parameter (which fulfills the ADC state condition) on the fly).
+  */
+typedef struct
+{
+  uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.
+                                        This parameter can be a value of @ref ADC_HAL_EC_CHANNEL
+                                        Note: Depending on devices and ADC instances, some channels may not be available
+                                              on device package pins. Refer to device datasheet for channels
+                                              availability. */
+
+  uint32_t Rank;                   /*!< Add or remove the channel from ADC regular group sequencer and specify its
+                                        conversion rank.
+                                        This parameter is dependent on ScanConvMode:
+                                        - sequencer configured to fully configurable:
+                                          Channels ordering into each rank of scan sequence:
+                                          whatever channel can be placed into whatever rank.
+                                        - sequencer configured to not fully configurable:
+                                          rank of each channel is fixed by channel HW number.
+                                          (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+                                          Despite the channel rank is fixed, this parameter allow an additional
+                                          possibility: to remove the selected rank (selected channel) from sequencer.
+                                        This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */
+
+  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
+                                        Unit: ADC clock cycles
+                                        Conversion time is the addition of sampling time and processing time
+                                        (12.5 ADC clock cycles at ADC resolution 12 bits,
+                                         10.5 cycles at 10 bits,
+                                         8.5 cycles at 8 bits,
+                                         6.5 cycles at 6 bits).
+                                        This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON
+                                        Note: On this STM32 family, two different sampling time settings are available
+                                              (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"),
+                                               each channel can use one of these two settings.
+
+                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/
+                                              TempSensor), sampling time constraints must be respected (sampling time
+                                              can be adjusted in function of ADC clock frequency and sampling time
+                                              setting)
+                                              Refer to device datasheet for timings values. */
+
+} ADC_ChannelConfTypeDef;
+
+/**
+  * @brief  Structure definition of ADC analog watchdog
+  * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.
+  *         ADC state can be either:
+  *          - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion
+               on going on ADC groups regular.
+  *          - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular.
+  */
+typedef struct
+{
+  uint32_t WatchdogNumber;    /*!< Select which ADC analog watchdog is monitoring the selected channel.
+                                   For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels
+                                                          by setting parameter 'WatchdogMode')
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls
+                                                                of 'HAL_ADC_AnalogWDGConfig()' for each channel)
+                                   This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */
+
+  uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.
+                                   For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all
+                                                          channels, ADC group regular.
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored by applying
+                                                                successively the AWD init structure.
+                                   This parameter can be a value of @ref ADC_analog_watchdog_mode. */
+
+  uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.
+                                   For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode'
+                                                          is configured on single channel (only 1 channel can be
+                                                          monitored).
+                                   For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature,
+                                                                call successively the function HAL_ADC_AnalogWDGConfig()
+                                                                for each channel to be added (or removed with value
+                                                                'ADC_ANALOGWATCHDOG_NONE').
+                                   This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */
+
+  FunctionalState ITMode;     /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.
+                                   This parameter can be set to ENABLE or DISABLE */
+
+  uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
+                                   number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
+                                   respectively.
+                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
+                                         resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
+                                         LSB are ignored.
+                                   Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+                                         impacted: the comparison of analog watchdog thresholds is done on
+                                         oversampling final computation (after ratio and shift application):
+                                         ADC data register bitfield [15:4] (12 most significant bits). */
+
+  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.
+                                   Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a
+                                   number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F
+                                   respectively.
+                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC
+                                         resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2
+                                         LSB are ignored.
+                                   Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
+                                         impacted: the comparison of analog watchdog thresholds is done on
+                                         oversampling final computation (after ratio and shift application):
+                                         ADC data register bitfield [15:4] (12 most significant bits).*/
+} ADC_AnalogWDGConfTypeDef;
+
+/** @defgroup ADC_States ADC States
+  * @{
+  */
+
+/**
+  * @brief  HAL ADC state machine: ADC states definition (bitfields)
+  * @note   ADC state machine is managed by bitfields, state must be compared
+  *         with bit by bit.
+  *         For example:
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+  */
+/* States of ADC global scope */
+#define HAL_ADC_STATE_RESET             (0x00000000UL)   /*!< ADC not yet initialized or disabled */
+#define HAL_ADC_STATE_READY             (0x00000001UL)   /*!< ADC peripheral ready for use */
+#define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002UL)   /*!< ADC is busy from internal process (ex : calibration, ...) */
+#define HAL_ADC_STATE_TIMEOUT           (0x00000004UL)   /*!< TimeOut occurrence */
+
+/* States of ADC errors */
+#define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010UL)   /*!< Internal error occurrence */
+#define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020UL)   /*!< Configuration error occurrence */
+#define HAL_ADC_STATE_ERROR_DMA         (0x00000040UL)   /*!< DMA error occurrence */
+
+/* States of ADC group regular */
+#define HAL_ADC_STATE_REG_BUSY          (0x00000100UL)   /*!< A conversion on ADC group regular is ongoing or can occur
+                                                              (either by continuous mode, external trigger, low power
+                                                              auto power-on (if feature available), multimode ADC master
+                                                              control (if feature available)) */
+#define HAL_ADC_STATE_REG_EOC           (0x00000200UL)   /*!< Conversion data available on group regular */
+#define HAL_ADC_STATE_REG_OVR           (0x00000400UL)   /*!< Overrun occurrence */
+#define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 series: End Of Sampling flag
+                                                              raised  */
+
+/* States of ADC group injected */
+#define HAL_ADC_STATE_INJ_BUSY          (0x00001000UL)  /*!< Not available on this STM32 series: A conversion on group
+                                                             injected is ongoing or can occur (either by auto-injection
+                                                             mode, external trigger, low power auto power-on (if feature
+                                                             available), multimode ADC master control (if feature
+                                                             available))*/
+#define HAL_ADC_STATE_INJ_EOC           (0x00002000UL)  /*!< Not available on this STM32 series: Conversion data
+                                                             available on group injected */
+#define HAL_ADC_STATE_INJ_JQOVF         (0x00004000UL)  /*!< Not available on this STM32 series: Injected queue overflow
+                                                             occurrence */
+
+/* States of ADC analog watchdogs */
+#define HAL_ADC_STATE_AWD1              (0x00010000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 1 */
+#define HAL_ADC_STATE_AWD2              (0x00020000UL)   /*!< Not available on this STM32 series: Out-of-window occurrence
+                                                              of ADC analog watchdog 2 */
+#define HAL_ADC_STATE_AWD3              (0x00040000UL)   /*!< Not available on this STM32 series: Out-of-window occurrence
+                                                              of ADC analog watchdog 3 */
+
+/* States of ADC multi-mode */
+#define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000UL)   /*!< Not available on this STM32 series: ADC in multimode slave
+                                                              state, controlled by another ADC master (when feature
+                                                              available) */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  ADC handle Structure definition
+  */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+typedef struct __ADC_HandleTypeDef
+#else
+typedef struct
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+{
+  ADC_TypeDef                   *Instance;         /*!< Register base address */
+  ADC_InitTypeDef               Init;              /*!< ADC initialization parameters and regular conversions setting */
+  DMA_HandleTypeDef             *DMA_Handle;       /*!< Pointer DMA Handler */
+  HAL_LockTypeDef               Lock;              /*!< ADC locking object */
+  __IO uint32_t                 State;             /*!< ADC communication state (bitmap of ADC states) */
+  __IO uint32_t                 ErrorCode;         /*!< ADC Error code */
+
+  uint32_t                      ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks
+                                                                    setting, used in mode "fully configurable" (refer to
+                                                                    parameter 'ScanConvMode') */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */
+  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer
+                                                                                 callback */
+  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */
+  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */
+  void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 2 callback */
+  void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 3 callback */
+  void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc);         /*!< ADC end of sampling callback */
+  void (* CalibrationCpltCallback)(struct __ADC_HandleTypeDef *hadc);       /*!< ADC end of calibration callback */
+  void (* ADCReadyCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC Ready callback */
+  void (* ChannelConfigReadyCallback)(struct __ADC_HandleTypeDef *hadc);    /*!< ADC Channel Configuration Ready
+                                                                                 callback */
+  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */
+  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+} ADC_HandleTypeDef;
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  HAL ADC Callback ID enumeration definition
+  */
+typedef enum
+{
+  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */
+  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */
+  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID   = 0x06U,  /*!< ADC analog watchdog 2 callback ID */
+  HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID   = 0x07U,  /*!< ADC analog watchdog 3 callback ID */
+  HAL_ADC_END_OF_SAMPLING_CB_ID         = 0x08U,  /*!< ADC end of sampling callback ID */
+  HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID */
+  HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID */
+} HAL_ADC_CallbackIDTypeDef;
+
+/**
+  * @brief  HAL ADC Callback pointer definition
+  */
+typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_Error_Code ADC Error Code
+  * @{
+  */
+#define HAL_ADC_ERROR_NONE              (0x00U)   /*!< No error                                    */
+#define HAL_ADC_ERROR_INTERNAL          (0x01U)   /*!< ADC peripheral internal error (problem of clocking,
+                                                       enable/disable, erroneous state, ...)       */
+#define HAL_ADC_ERROR_OVR               (0x02U)   /*!< Overrun error                               */
+#define HAL_ADC_ERROR_DMA               (0x04U)   /*!< DMA transfer error                          */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
+  * @{
+  */
+#define ADC_CLOCK_SYNC_PCLK_DIV1           (LL_ADC_CLOCK_SYNC_PCLK_DIV1)  /*!< ADC synchronous clock from AHB clock
+                                           without prescaler. This configuration must be enabled only if PCLK has
+                                           a 50% duty clock cycle (APB prescaler configured inside the RCC must
+                                           be bypassed and the system clock must by 50% duty cycle) */
+#define ADC_CLOCK_SYNC_PCLK_DIV2           (LL_ADC_CLOCK_SYNC_PCLK_DIV2)  /*!< ADC synchronous clock from AHB clock
+                                           with prescaler division by 2 */
+#define ADC_CLOCK_SYNC_PCLK_DIV4           (LL_ADC_CLOCK_SYNC_PCLK_DIV4)  /*!< ADC synchronous clock from AHB clock
+                                           with prescaler division by 4 */
+
+#define ADC_CLOCK_ASYNC_DIV1               (LL_ADC_CLOCK_ASYNC_DIV1)      /*!< ADC asynchronous clock without
+                                           prescaler */
+#define ADC_CLOCK_ASYNC_DIV2               (LL_ADC_CLOCK_ASYNC_DIV2)      /*!< ADC asynchronous clock with prescaler
+                                           division by 2   */
+#define ADC_CLOCK_ASYNC_DIV4               (LL_ADC_CLOCK_ASYNC_DIV4)      /*!< ADC asynchronous clock with prescaler
+                                           division by 4   */
+#define ADC_CLOCK_ASYNC_DIV6               (LL_ADC_CLOCK_ASYNC_DIV6)      /*!< ADC asynchronous clock with prescaler
+                                           division by 6   */
+#define ADC_CLOCK_ASYNC_DIV8               (LL_ADC_CLOCK_ASYNC_DIV8)      /*!< ADC asynchronous clock with prescaler
+                                           division by 8   */
+#define ADC_CLOCK_ASYNC_DIV10              (LL_ADC_CLOCK_ASYNC_DIV10)     /*!< ADC asynchronous clock with prescaler
+                                           division by 10  */
+#define ADC_CLOCK_ASYNC_DIV12              (LL_ADC_CLOCK_ASYNC_DIV12)     /*!< ADC asynchronous clock with prescaler
+                                           division by 12  */
+#define ADC_CLOCK_ASYNC_DIV16              (LL_ADC_CLOCK_ASYNC_DIV16)     /*!< ADC asynchronous clock with prescaler
+                                           division by 16  */
+#define ADC_CLOCK_ASYNC_DIV32              (LL_ADC_CLOCK_ASYNC_DIV32)     /*!< ADC asynchronous clock with prescaler
+                                           division by 32  */
+#define ADC_CLOCK_ASYNC_DIV64              (LL_ADC_CLOCK_ASYNC_DIV64)     /*!< ADC asynchronous clock with prescaler
+                                           division by 64  */
+#define ADC_CLOCK_ASYNC_DIV128             (LL_ADC_CLOCK_ASYNC_DIV128)    /*!< ADC asynchronous clock with prescaler
+                                           division by 128 */
+#define ADC_CLOCK_ASYNC_DIV256             (LL_ADC_CLOCK_ASYNC_DIV256)    /*!< ADC asynchronous clock with prescaler
+                                           division by 256 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_RESOLUTION  ADC instance - Resolution
+  * @{
+  */
+#define ADC_RESOLUTION_12B                 (LL_ADC_RESOLUTION_12B)  /*!< ADC resolution 12 bits */
+#define ADC_RESOLUTION_10B                 (LL_ADC_RESOLUTION_10B)  /*!< ADC resolution 10 bits */
+#define ADC_RESOLUTION_8B                  (LL_ADC_RESOLUTION_8B)   /*!< ADC resolution  8 bits */
+#define ADC_RESOLUTION_6B                  (LL_ADC_RESOLUTION_6B)   /*!< ADC resolution  6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment
+  * @{
+  */
+#define ADC_DATAALIGN_RIGHT                (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned
+                                           (alignment on data register LSB bit 0)*/
+#define ADC_DATAALIGN_LEFT                 (LL_ADC_DATA_ALIGN_LEFT)  /*!< ADC conversion data alignment: left aligned
+                                           (alignment on data register MSB bit 15)*/
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Scan_mode ADC sequencer scan mode
+  * @{
+  */
+/* Note: On this STM32 family, ADC group regular sequencer both modes         */
+/*       "fully configurable" or "not fully configurable" are                 */
+/*       available.                                                           */
+/*       Scan mode values must be compatible with other STM32 devices having  */
+/*       a configurable sequencer.                                            */
+/*       Scan direction setting values are defined by taking in account       */
+/*       already defined values for other STM32 devices:                      */
+/*         ADC_SCAN_DISABLE         (0x00000000UL)                            */
+/*         ADC_SCAN_ENABLE          (0x00000001UL)                            */
+/*       Sequencer fully configurable with only rank 1 enabled is considered  */
+/*       as default setting equivalent to scan enable.                        */
+/*       In case of migration from another STM32 device, the user will be     */
+/*       warned of change of setting choices with assert check.               */
+/* Sequencer set to fully configurable */
+#define ADC_SCAN_DISABLE                  (0x00000000UL)                /*!< Sequencer set to fully configurable:
+                                          only the rank 1 is enabled (no scan sequence on several ranks) */
+#define ADC_SCAN_ENABLE                   (ADC_CFGR1_CHSELRMOD)         /*!< Sequencer set to fully configurable:
+                                          sequencer length and each rank affectation to a channel are configurable. */
+
+/* Sequencer set to not fully configurable */
+#define ADC_SCAN_SEQ_FIXED                (ADC_SCAN_SEQ_FIXED_INT)      /*!< Sequencer set to not fully configurable:
+                                          sequencer length and each rank affectation to a channel are fixed by
+                                          channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+                                          Scan direction forward: from channel 0 to channel 18 */
+#define ADC_SCAN_SEQ_FIXED_BACKWARD       (ADC_SCAN_SEQ_FIXED_INT \
+                                           | ADC_CFGR1_SCANDIR)         /*!< Sequencer set to not fully configurable:
+                                          sequencer length and each rank affectation to a channel are fixed by
+                                          channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+                                          Scan direction backward: from channel 18 to channel 0 */
+
+#define ADC_SCAN_DIRECTION_FORWARD        (ADC_SCAN_SEQ_FIXED)          /* For compatibility with other STM32 series */
+#define ADC_SCAN_DIRECTION_BACKWARD       (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 series */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source
+  * @{
+  */
+/* ADC group regular trigger sources for all ADC instances */
+#define ADC_SOFTWARE_START            (LL_ADC_REG_TRIG_SOFTWARE)                 /*!< ADC group regular conversion
+                                      trigger internal: SW start. */
+#define ADC_EXTERNALTRIG_T1_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)           /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM1 TRGO.
+                                      Trigger edge set to rising edge (default setting). */
+#define ADC_EXTERNALTRIG_T1_CC4       (LL_ADC_REG_TRIG_EXT_TIM1_CH4)             /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM1 channel 4 event
+                                      (capture compare: input capture or output capture).
+                                      Trigger edge set to rising edge (default setting). */
+#if defined(TIM2)
+#define ADC_EXTERNALTRIG_T2_TRGO      (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM2 TRGO.
+                                      Trigger edge set to rising edge (default setting). */
+#endif /* TIM2 */
+#define ADC_EXTERNALTRIG_T3_TRGO      (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM3 TRGO.
+                                      Trigger edge set to rising edge (default setting). */
+#if defined(TIM4)
+#define ADC_EXTERNALTRIG_T4_TRGO      (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM4 TRGO.
+                                      Trigger edge set to rising edge (default setting). */
+#endif /* TIM4 */
+#if defined(TIM6)
+#define ADC_EXTERNALTRIG_T6_TRGO      (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)            /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM6 TRGO.
+                                      Trigger edge set to rising edge (default setting). */
+#endif /* TIM6 */
+#if defined(TIM15)
+#define ADC_EXTERNALTRIG_T15_TRGO     (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)           /*!< ADC group regular conversion
+                                      trigger from external peripheral: TIM15 TRGO.
+                                      Trigger edge set to rising edge (default setting). */
+#endif /* TIM15 */
+#define ADC_EXTERNALTRIG_EXT_IT11     (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)          /*!< ADC group regular conversion
+                                      trigger from external peripheral: external interrupt line 11.
+                                      Trigger edge set to rising edge (default setting). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)
+  * @{
+  */
+#define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000UL)                      /*!< Regular conversions hardware
+                                                trigger detection disabled */
+#define ADC_EXTERNALTRIGCONVEDGE_RISING         (LL_ADC_REG_TRIG_EXT_RISING)        /*!< ADC group regular conversion
+                                                trigger polarity set to rising edge */
+#define ADC_EXTERNALTRIGCONVEDGE_FALLING        (LL_ADC_REG_TRIG_EXT_FALLING)       /*!< ADC group regular conversion
+                                                trigger polarity set to falling edge */
+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion
+                                                trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions
+  * @{
+  */
+#define ADC_EOC_SINGLE_CONV         (ADC_ISR_EOC)                 /*!< End of unitary conversion flag   */
+#define ADC_EOC_SEQ_CONV            (ADC_ISR_EOS)                 /*!< End of sequence conversions flag */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
+  * @{
+  */
+#define ADC_OVR_DATA_PRESERVED             (LL_ADC_REG_OVR_DATA_PRESERVED)    /*!< ADC group regular behavior in case
+                                           of overrun: data preserved */
+#define ADC_OVR_DATA_OVERWRITTEN           (LL_ADC_REG_OVR_DATA_OVERWRITTEN)  /*!< ADC group regular behavior in case
+                                           of overrun: data overwritten */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
+  * @{
+  */
+#define ADC_RANK_CHANNEL_NUMBER            (0x00000001U)  /*!< Setting relevant if parameter "ScanConvMode" is set
+                                           to sequencer not fully configurable: Enable the rank of the selected
+                                           channels. Number of ranks in the sequence is defined by number of channels
+                                           enabled, rank of each channel is defined by channel number
+                                           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */
+#define ADC_RANK_NONE                      (0x00000002U)  /*!< Setting relevant if parameter "ScanConvMode"
+                                           is set to sequencer not fully configurable: Disable the selected rank
+                                           (selected channel) from sequencer */
+
+#define ADC_REGULAR_RANK_1                 (LL_ADC_REG_RANK_1)  /*!< ADC group regular sequencer rank 1 */
+#define ADC_REGULAR_RANK_2                 (LL_ADC_REG_RANK_2)  /*!< ADC group regular sequencer rank 2 */
+#define ADC_REGULAR_RANK_3                 (LL_ADC_REG_RANK_3)  /*!< ADC group regular sequencer rank 3 */
+#define ADC_REGULAR_RANK_4                 (LL_ADC_REG_RANK_4)  /*!< ADC group regular sequencer rank 4 */
+#define ADC_REGULAR_RANK_5                 (LL_ADC_REG_RANK_5)  /*!< ADC group regular sequencer rank 5 */
+#define ADC_REGULAR_RANK_6                 (LL_ADC_REG_RANK_6)  /*!< ADC group regular sequencer rank 6 */
+#define ADC_REGULAR_RANK_7                 (LL_ADC_REG_RANK_7)  /*!< ADC group regular sequencer rank 7 */
+#define ADC_REGULAR_RANK_8                 (LL_ADC_REG_RANK_8)  /*!< ADC group regular sequencer rank 8 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON  ADC instance - Sampling time common to a group of channels
+  * @{
+  */
+#define ADC_SAMPLINGTIME_COMMON_1          (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of
+                                                                               channels: sampling time nb 1 */
+#define ADC_SAMPLINGTIME_COMMON_2          (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of
+                                                                               channels: sampling time nb 2 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+  * @{
+  */
+#define ADC_SAMPLETIME_1CYCLE_5          (LL_ADC_SAMPLINGTIME_1CYCLE_5)     /*!< Sampling time 1.5 ADC clock cycle */
+#define ADC_SAMPLETIME_3CYCLES_5         (LL_ADC_SAMPLINGTIME_3CYCLES_5)    /*!< Sampling time 3.5 ADC clock cycles */
+#define ADC_SAMPLETIME_7CYCLES_5         (LL_ADC_SAMPLINGTIME_7CYCLES_5)    /*!< Sampling time 7.5 ADC clock cycles */
+#define ADC_SAMPLETIME_12CYCLES_5        (LL_ADC_SAMPLINGTIME_12CYCLES_5)   /*!< Sampling time 12.5 ADC clock cycles */
+#define ADC_SAMPLETIME_19CYCLES_5        (LL_ADC_SAMPLINGTIME_19CYCLES_5)   /*!< Sampling time 19.5 ADC clock cycles */
+#define ADC_SAMPLETIME_39CYCLES_5        (LL_ADC_SAMPLINGTIME_39CYCLES_5)   /*!< Sampling time 39.5 ADC clock cycles */
+#define ADC_SAMPLETIME_79CYCLES_5        (LL_ADC_SAMPLINGTIME_79CYCLES_5)   /*!< Sampling time 79.5 ADC clock cycles */
+#define ADC_SAMPLETIME_160CYCLES_5       (LL_ADC_SAMPLINGTIME_160CYCLES_5)  /*!< Sampling time 160.5 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_CHANNEL  ADC instance - Channel number
+  * @{
+  */
+#define ADC_CHANNEL_0                      (LL_ADC_CHANNEL_0)              /*!< External channel (GPIO pin) ADCx_IN0  */
+#define ADC_CHANNEL_1                      (LL_ADC_CHANNEL_1)              /*!< External channel (GPIO pin) ADCx_IN1  */
+#define ADC_CHANNEL_2                      (LL_ADC_CHANNEL_2)              /*!< External channel (GPIO pin) ADCx_IN2  */
+#define ADC_CHANNEL_3                      (LL_ADC_CHANNEL_3)              /*!< External channel (GPIO pin) ADCx_IN3  */
+#define ADC_CHANNEL_4                      (LL_ADC_CHANNEL_4)              /*!< External channel (GPIO pin) ADCx_IN4  */
+#define ADC_CHANNEL_5                      (LL_ADC_CHANNEL_5)              /*!< External channel (GPIO pin) ADCx_IN5  */
+#define ADC_CHANNEL_6                      (LL_ADC_CHANNEL_6)              /*!< External channel (GPIO pin) ADCx_IN6  */
+#define ADC_CHANNEL_7                      (LL_ADC_CHANNEL_7)              /*!< External channel (GPIO pin) ADCx_IN7  */
+#define ADC_CHANNEL_8                      (LL_ADC_CHANNEL_8)              /*!< External channel (GPIO pin) ADCx_IN8  */
+#define ADC_CHANNEL_9                      (LL_ADC_CHANNEL_9)              /*!< External channel (GPIO pin) ADCx_IN9  */
+#define ADC_CHANNEL_10                     (LL_ADC_CHANNEL_10)             /*!< External channel (GPIO pin) ADCx_IN10 */
+#define ADC_CHANNEL_11                     (LL_ADC_CHANNEL_11)             /*!< External channel (GPIO pin) ADCx_IN11 */
+#define ADC_CHANNEL_12                     (LL_ADC_CHANNEL_12)             /*!< External channel (GPIO pin) ADCx_IN12 */
+#define ADC_CHANNEL_13                     (LL_ADC_CHANNEL_13)             /*!< External channel (GPIO pin) ADCx_IN13 */
+#define ADC_CHANNEL_14                     (LL_ADC_CHANNEL_14)             /*!< External channel (GPIO pin) ADCx_IN14 */
+#define ADC_CHANNEL_15                     (LL_ADC_CHANNEL_15)             /*!< External channel (GPIO pin) ADCx_IN15 */
+#define ADC_CHANNEL_16                     (LL_ADC_CHANNEL_16)             /*!< External channel (GPIO pin) ADCx_IN16 */
+#define ADC_CHANNEL_17                     (LL_ADC_CHANNEL_17)             /*!< External channel (GPIO pin) ADCx_IN17 */
+#define ADC_CHANNEL_18                     (LL_ADC_CHANNEL_18)             /*!< External channel (GPIO pin) ADCx_IN18 */
+#define ADC_CHANNEL_19                     (LL_ADC_CHANNEL_19)             /*!< External channel (GPIO pin) ADCx_IN19 */
+#define ADC_CHANNEL_20                     (LL_ADC_CHANNEL_20)             /*!< External channel (GPIO pin) ADCx_IN20 */
+#define ADC_CHANNEL_21                     (LL_ADC_CHANNEL_21)             /*!< External channel (GPIO pin) ADCx_IN21 */
+#define ADC_CHANNEL_22                     (LL_ADC_CHANNEL_22)             /*!< External channel (GPIO pin) ADCx_IN22 */
+#define ADC_CHANNEL_VREFINT                (LL_ADC_CHANNEL_VREFINT)        /*!< Internal channel VrefInt:
+                                           Internal voltage reference. */
+#define ADC_CHANNEL_TEMPSENSOR             (LL_ADC_CHANNEL_TEMPSENSOR)     /*!< Internal channel Temperature sensor. */
+#define ADC_CHANNEL_VDDA                   (LL_ADC_CHANNEL_VDDA)           /*!< Internal channel VDDA */
+#define ADC_CHANNEL_VSSA                   (LL_ADC_CHANNEL_VSSA)           /*!< Internal channel VSSA */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+  * @{
+  */
+#define ADC_ANALOGWATCHDOG_1               (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */
+#define ADC_ANALOGWATCHDOG_2               (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */
+#define ADC_ANALOGWATCHDOG_3               (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode
+  * @{
+  */
+#define ADC_ANALOGWATCHDOG_NONE                 (0x00000000UL)                         /*!< ADC AWD not selected */
+#define ADC_ANALOGWATCHDOG_SINGLE_REG           (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to a regular
+                                                group single channel */
+#define ADC_ANALOGWATCHDOG_ALL_REG              (ADC_CFGR1_AWD1EN)                     /*!< ADC AWD applied to regular
+                                                group all channels */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_RATIO  Oversampling - Ratio
+  * @{
+  */
+/**
+  * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed
+  *       to result as the ADC oversampling conversion data (before potential shift)
+  */
+#define ADC_OVERSAMPLING_RATIO_2           (LL_ADC_OVS_RATIO_2)    /*!< ADC oversampling ratio    2 */
+#define ADC_OVERSAMPLING_RATIO_4           (LL_ADC_OVS_RATIO_4)    /*!< ADC oversampling ratio    4 */
+#define ADC_OVERSAMPLING_RATIO_8           (LL_ADC_OVS_RATIO_8)    /*!< ADC oversampling ratio    8 */
+#define ADC_OVERSAMPLING_RATIO_16          (LL_ADC_OVS_RATIO_16)   /*!< ADC oversampling ratio   16 */
+#define ADC_OVERSAMPLING_RATIO_32          (LL_ADC_OVS_RATIO_32)   /*!< ADC oversampling ratio   32 */
+#define ADC_OVERSAMPLING_RATIO_64          (LL_ADC_OVS_RATIO_64)   /*!< ADC oversampling ratio   64 */
+#define ADC_OVERSAMPLING_RATIO_128         (LL_ADC_OVS_RATIO_128)  /*!< ADC oversampling ratio  128 */
+#define ADC_OVERSAMPLING_RATIO_256         (LL_ADC_OVS_RATIO_256)  /*!< ADC oversampling ratio  256 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_SHIFT  Oversampling - Data shift
+  * @{
+  */
+/**
+  * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling
+  *       conversion data)
+  */
+#define ADC_RIGHTBITSHIFT_NONE             (LL_ADC_OVS_SHIFT_NONE)    /*!< ADC oversampling no shift   */
+#define ADC_RIGHTBITSHIFT_1                (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */
+#define ADC_RIGHTBITSHIFT_2                (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */
+#define ADC_RIGHTBITSHIFT_3                (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */
+#define ADC_RIGHTBITSHIFT_4                (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */
+#define ADC_RIGHTBITSHIFT_5                (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */
+#define ADC_RIGHTBITSHIFT_6                (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */
+#define ADC_RIGHTBITSHIFT_7                (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */
+#define ADC_RIGHTBITSHIFT_8                (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
+  * @{
+  */
+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER   (LL_ADC_OVS_REG_CONT)          /*!< ADC oversampling discontinuous mode:
+                                           continuous mode (all conversions of OVS ratio are done from 1 trigger) */
+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER    (LL_ADC_OVS_REG_DISCONT)       /*!< ADC oversampling discontinuous mode:
+                                           discontinuous mode (each conversion of OVS ratio needs a trigger) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ  ADC group regular - Trigger frequency mode
+  * @{
+  */
+
+/**
+  * @note ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion
+  *       start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion
+  *       start trigger event).
+  *       Duration value: Refer to device datasheet, parameter "tIdle".
+  */
+#define ADC_TRIGGER_FREQ_HIGH         (LL_ADC_TRIGGER_FREQ_HIGH) /*!< Trigger frequency mode set to high frequency. */
+#define ADC_TRIGGER_FREQ_LOW          (LL_ADC_TRIGGER_FREQ_LOW)  /*!< Trigger frequency mode set to low frequency.  */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Event_type ADC Event type
+  * @{
+  */
+/**
+  * @note Analog watchdog 1 is available on all stm32 series
+  *       Analog watchdog 2 and 3 are not available on all series
+  */
+#define ADC_EOSMP_EVENT          (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */
+#define ADC_AWD1_EVENT           (ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog)       */
+#define ADC_AWD2_EVENT           (ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog) */
+#define ADC_AWD3_EVENT           (ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog) */
+#define ADC_OVR_EVENT            (ADC_FLAG_OVR)   /*!< ADC overrun event */
+/**
+  * @}
+  */
+#define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility
+                                                          with other STM32 devices having only one analog watchdog */
+
+/** @defgroup ADC_interrupts_definition ADC interrupts definition
+  * @{
+  */
+#define ADC_IT_RDY           ADC_IER_ADRDYIE    /*!< ADC Ready interrupt source */
+#define ADC_IT_CCRDY         ADC_IER_CCRDYIE    /*!< ADC channel configuration ready interrupt source */
+#define ADC_IT_EOSMP         ADC_IER_EOSMPIE    /*!< ADC End of sampling interrupt source */
+#define ADC_IT_EOC           ADC_IER_EOCIE      /*!< ADC End of regular conversion interrupt source */
+#define ADC_IT_EOS           ADC_IER_EOSIE      /*!< ADC End of regular sequence of conversions interrupt source */
+#define ADC_IT_OVR           ADC_IER_OVRIE      /*!< ADC overrun interrupt source */
+#define ADC_IT_AWD1          ADC_IER_AWD1IE     /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */
+#define ADC_IT_AWD2          ADC_IER_AWD2IE     /*!< ADC Analog watchdog 2 interrupt source (additional analog
+                             watchdog) */
+#define ADC_IT_AWD3          ADC_IER_AWD3IE     /*!< ADC Analog watchdog 3 interrupt source (additional analog
+                             watchdog) */
+#define ADC_IT_EOCAL         ADC_IER_EOCALIE    /*!< ADC End of Calibration interrupt source */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_flags_definition ADC flags definition
+  * @{
+  */
+#define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */
+#define ADC_FLAG_CCRDY         ADC_ISR_CCRDY    /*!< ADC channel configuration ready flag */
+#define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */
+#define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */
+#define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */
+#define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */
+#define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag */
+#define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag */
+#define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag */
+#define ADC_FLAG_EOCAL         ADC_ISR_EOCAL    /*!< ADC End of Calibration interrupt flag */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Macros ADC Private Macros
+  * @{
+  */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+  * @brief Test if conversion trigger of regular group is software start
+  *        or external trigger.
+  * @param __HANDLE__ ADC handle
+  * @retval SET (software start) or RESET (external trigger)
+  */
+#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
+  (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL)
+
+/**
+  * @brief Return resolution bits in CFGR1 register RES[1:0] field.
+  * @param __HANDLE__ ADC handle
+  * @retval Value of bitfield RES in CFGR1 register.
+  */
+#define ADC_GET_RESOLUTION(__HANDLE__)                                         \
+  (LL_ADC_GetResolution((__HANDLE__)->Instance))
+
+/**
+  * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
+
+/**
+  * @brief Simultaneously clear and set specific bits of the handle State.
+  * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
+  *        the first parameter is the ADC handle State, the second parameter is the
+  *        bit field to clear, the third and last parameter is the bit field to set.
+  * @retval None
+  */
+#define ADC_STATE_CLR_SET MODIFY_REG
+
+/**
+  * @brief Enable ADC discontinuous conversion mode for regular group
+  * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
+  * @retval None
+  */
+#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_)                 \
+  ((_REG_DISCONTINUOUS_MODE_) << 16U)
+
+/**
+  * @brief Enable the ADC auto off mode.
+  * @param _AUTOOFF_ Auto off bit enable or disable.
+  * @retval None
+  */
+#define ADC_CFGR1_AUTOOFF(_AUTOOFF_)                                           \
+  ((_AUTOOFF_) << 15U)
+
+/**
+  * @brief Enable the ADC auto delay mode.
+  * @param _AUTOWAIT_ Auto delay bit enable or disable.
+  * @retval None
+  */
+#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_)                                         \
+  ((_AUTOWAIT_) << 14U)
+
+/**
+  * @brief Enable ADC continuous conversion mode.
+  * @param _CONTINUOUS_MODE_ Continuous mode.
+  * @retval None
+  */
+#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_)                                \
+  ((_CONTINUOUS_MODE_) << 13U)
+
+/**
+  * @brief Enable ADC overrun mode.
+  * @param _OVERRUN_MODE_ Overrun mode.
+  * @retval Overrun bit setting to be programmed into CFGR register
+  */
+/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant                   */
+/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it    */
+/* as the default case to be compliant with other STM32 devices.              */
+#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_)                                      \
+  ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED)                             \
+    )? (ADC_CFGR1_OVRMOD) : (0x00000000UL)                                     \
+  )
+
+/**
+  * @brief Set ADC scan mode with differentiation of sequencer setting
+  *        fixed or configurable
+  * @param _SCAN_MODE_ Scan conversion mode.
+  * @retval None
+  */
+/* Note: Scan mode set using this macro (instead of parameter direct set)     */
+/*       due to different modes on other STM32 devices:                       */
+/*       if scan mode is disabled, sequencer is set to fully configurable     */
+/*       with setting of only rank 1 enabled afterwards.                      */
+#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_)                                         \
+  ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL                           \
+    )?                                                                         \
+    ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT))                                \
+    :                                                                          \
+    (ADC_CFGR1_CHSELRMOD)                                                      \
+  )
+
+/**
+  * @brief Enable the ADC DMA continuous request.
+  * @param _DMACONTREQ_MODE_: DMA continuous request mode.
+  * @retval None
+  */
+#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_)                                \
+  ((_DMACONTREQ_MODE_) << 1U)
+
+/**
+  * @brief Shift the AWD threshold in function of the selected ADC resolution.
+  *        Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0.
+  *        If resolution 12 bits, no shift.
+  *        If resolution 10 bits, shift of 2 ranks on the left.
+  *        If resolution 8 bits, shift of 4 ranks on the left.
+  *        If resolution 6 bits, shift of 6 ranks on the left.
+  *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
+  * @param __HANDLE__ ADC handle
+  * @param _Threshold_ Value to be shifted
+  * @retval None
+  */
+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_)            \
+  ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U))
+
+#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1  )   ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2  )   ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4  )   ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6  )   ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8  )   ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 )   ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 )   ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 )   ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 )   ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 )   ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 )  ||\
+                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256))
+
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \
+                                       ((RESOLUTION) == ADC_RESOLUTION_10B) || \
+                                       ((RESOLUTION) == ADC_RESOLUTION_8B)  || \
+                                       ((RESOLUTION) == ADC_RESOLUTION_6B)    )
+
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
+                                  ((ALIGN) == ADC_DATAALIGN_LEFT)    )
+
+#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE)            || \
+                                     ((SCAN_MODE) == ADC_SCAN_ENABLE)             || \
+                                     ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED)          || \
+                                     ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD)   )
+
+#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
+                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
+                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
+                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
+
+#if defined(TIM2)
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4)   || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO)  || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO)  || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \
+                                 ((REGTRIG) == ADC_SOFTWARE_START))
+#else
+#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4)   || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO)  || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \
+                                 ((REGTRIG) == ADC_SOFTWARE_START))
+#endif /* TIM2 */
+
+#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)    || \
+                                             ((EOC_SELECTION) == ADC_EOC_SEQ_CONV))
+
+#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED)  || \
+                             ((OVR) == ADC_OVR_DATA_OVERWRITTEN)  )
+
+#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \
+                                             ((RANK) == ADC_RANK_NONE)             )
+
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \
+                                   ((RANK) == ADC_REGULAR_RANK_2 ) || \
+                                   ((RANK) == ADC_REGULAR_RANK_3 ) || \
+                                   ((RANK) == ADC_REGULAR_RANK_4 ) || \
+                                   ((RANK) == ADC_REGULAR_RANK_5 ) || \
+                                   ((RANK) == ADC_REGULAR_RANK_6 ) || \
+                                   ((RANK) == ADC_REGULAR_RANK_7 ) || \
+                                   ((RANK) == ADC_REGULAR_RANK_8 )   )
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
+                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_16)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_17)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_18)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_19)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_20)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_21)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_22)          || \
+                                 ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR)  || \
+                                 ((CHANNEL) == ADC_CHANNEL_VREFINT)     || \
+                                 ((CHANNEL) == ADC_CHANNEL_VDDA)        || \
+                                 ((CHANNEL) == ADC_CHANNEL_VSSA)          )
+
+#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \
+                                                           ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2)   )
+
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5)    || \
+                                  ((TIME) == ADC_SAMPLETIME_3CYCLES_5)   || \
+                                  ((TIME) == ADC_SAMPLETIME_7CYCLES_5)   || \
+                                  ((TIME) == ADC_SAMPLETIME_12CYCLES_5)  || \
+                                  ((TIME) == ADC_SAMPLETIME_19CYCLES_5)  || \
+                                  ((TIME) == ADC_SAMPLETIME_39CYCLES_5)  || \
+                                  ((TIME) == ADC_SAMPLETIME_79CYCLES_5)  || \
+                                  ((TIME) == ADC_SAMPLETIME_160CYCLES_5)   )
+
+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \
+                                                 ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \
+                                                 ((WATCHDOG) == ADC_ANALOGWATCHDOG_3)   )
+
+#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
+                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
+                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)            )
+
+#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \
+                                           ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW)    )
+
+#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \
+                                  ((EVENT) == ADC_AWD1_EVENT)  || \
+                                  ((EVENT) == ADC_AWD2_EVENT)  || \
+                                  ((EVENT) == ADC_AWD3_EVENT)  || \
+                                  ((EVENT) == ADC_OVR_EVENT)     )
+
+/**
+  * @brief Verify that a given value is aligned with the ADC resolution range.
+  * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
+  * @param __ADC_VALUE__ value checked against the resolution.
+  * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
+  */
+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
+  ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))
+
+/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification
+  * @{
+  */
+#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL))
+/**
+  * @}
+  */
+
+
+/* Private constants ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */
+#define ADC_FLAG_POSTCONV_ALL    (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC)
+
+/* Internal definition to differentiate sequencer setting fixed or configurable */
+#define ADC_SCAN_SEQ_FIXED_INT  0x80000000U
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Macros ADC Exported Macros
+  * @{
+  */
+/* Macro for internal HAL driver usage, and possibly can be used into code of */
+/* final user.                                                                */
+
+/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.
+  * @{
+  */
+
+/** @brief  Reset ADC handle state.
+  * @param __HANDLE__ ADC handle
+  * @retval None
+  */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  do{                                                                          \
+    (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \
+    (__HANDLE__)->MspInitCallback = NULL;                                      \
+    (__HANDLE__)->MspDeInitCallback = NULL;                                    \
+  } while(0)
+#else
+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
+  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @brief Enable ADC interrupt.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC Interrupt
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
+  *            @arg @ref ADC_IT_CCRDY  ADC channel configuration ready interrupt source
+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  * @retval None
+  */
+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
+  (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+  * @brief Disable ADC interrupt.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC Interrupt
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
+  *            @arg @ref ADC_IT_CCRDY  ADC channel configuration ready interrupt source
+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  * @retval None
+  */
+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
+  (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
+  * @param __HANDLE__ ADC handle
+  * @param __INTERRUPT__ ADC interrupt source to check
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source
+  *            @arg @ref ADC_IT_CCRDY  ADC channel configuration ready interrupt source
+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source
+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source
+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source
+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source
+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)
+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)
+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)
+  * @retval State of interruption (SET or RESET)
+  */
+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
+  (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
+
+/**
+  * @brief Check whether the specified ADC flag is set or not.
+  * @param __HANDLE__ ADC handle
+  * @param __FLAG__ ADC flag
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_FLAG_RDY    ADC Ready flag
+  *            @arg @ref ADC_FLAG_CCRDY  ADC channel configuration ready flag
+  *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
+  *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
+  *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
+  *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
+  * @retval State of flag (TRUE or FALSE).
+  */
+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
+  ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
+
+/**
+  * @brief Clear the specified ADC flag.
+  * @param __HANDLE__ ADC handle
+  * @param __FLAG__ ADC flag
+  *        This parameter can be one of the following values:
+  *            @arg @ref ADC_FLAG_RDY    ADC Ready flag
+  *            @arg @ref ADC_FLAG_CCRDY  ADC channel configuration ready flag
+  *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag
+  *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag
+  *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag
+  *            @arg @ref ADC_FLAG_OVR     ADC overrun flag
+  *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)
+  *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)
+  * @retval None
+  */
+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \
+  (((__HANDLE__)->Instance->ISR) = (__FLAG__))
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get ADC channel number in decimal format
+  *         from literals ADC_CHANNEL_x.
+  * @note   Example:
+  *           __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)
+  *           will return decimal number "4".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned, either defined with number
+  *         or with bitfield (only one bit must be set).
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @retval Value between Min_Data=0 and Max_Data=18
+  */
+#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                           \
+  __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
+
+/**
+  * @brief  Helper macro to get ADC channel in literal format ADC_CHANNEL_x
+  *         from number in decimal format.
+  * @note   Example:
+  *           __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+  *           will return a data equivalent to "ADC_CHANNEL_4".
+  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  */
+#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                        \
+  __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
+
+/**
+  * @brief  Helper macro to determine whether the selected channel
+  *         corresponds to literal definitions of driver.
+  * @note   The different literal definitions of ADC channels are:
+  *         - ADC internal channel:
+  *           ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...
+  *         - ADC external channel (channel connected to a GPIO pin):
+  *           ADC_CHANNEL_1, ADC_CHANNEL_2, ...
+  * @note   The channel parameter must be a value defined from literal
+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+  *         ADC_CHANNEL_TEMPSENSOR, ...),
+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),
+  *         must not be a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @retval Value "0" if the channel corresponds to a parameter definition of a
+  *         ADC external channel (channel connected to a GPIO pin).
+  *         Value "1" if the channel corresponds to a parameter definition of
+  *         a ADC internal channel.
+  */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                             \
+  __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
+
+/**
+  * @brief  Helper macro to convert a channel defined from parameter
+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+  *         ADC_CHANNEL_TEMPSENSOR, ...),
+  *         to its equivalent parameter definition of a ADC external channel
+  *         (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).
+  * @note   The channel parameter can be, additionally to a value
+  *         defined from parameter definition of a ADC internal channel
+  *         (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),
+  *         a value defined from parameter definition of
+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is returned
+  *         from ADC registers.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8
+  *         @arg @ref ADC_CHANNEL_9
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15
+  *         @arg @ref ADC_CHANNEL_16
+  *         @arg @ref ADC_CHANNEL_17
+  *         @arg @ref ADC_CHANNEL_18
+  *         @arg @ref ADC_CHANNEL_19
+  *         @arg @ref ADC_CHANNEL_20
+  *         @arg @ref ADC_CHANNEL_21
+  *         @arg @ref ADC_CHANNEL_22
+  */
+#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                    \
+  __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
+
+/**
+  * @brief  Helper macro to determine whether the internal channel
+  *         selected is available on the ADC instance selected.
+  * @note   The channel parameter must be a value defined from parameter
+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,
+  *         ADC_CHANNEL_TEMPSENSOR, ...),
+  *         must not be a value defined from parameter definition of
+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __ADC_INSTANCE__ ADC instance
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_VREFINT
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR
+  *         @arg @ref ADC_CHANNEL_VDDA
+  *         @arg @ref ADC_CHANNEL_VSSA
+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+  *         Value "1" if the internal channel selected is available on the ADC instance selected.
+  */
+#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
+
+/**
+  * @brief  Helper macro to select the ADC common instance
+  *         to which is belonging the selected ADC instance.
+  * @note   ADC common register instance can be used for:
+  *         - Set parameters common to several ADC instances
+  *         - Multimode (for devices with several ADC instances)
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @param  __ADCx__ ADC instance
+  * @retval ADC common register instance
+  */
+#define __HAL_ADC_COMMON_INSTANCE(__ADCx__)                                    \
+  __LL_ADC_COMMON_INSTANCE((__ADCx__))
+
+/**
+  * @brief  Helper macro to check if all ADC instances sharing the same
+  *         ADC common instance are disabled.
+  * @note   This check is required by functions with setting conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @note   On devices with only 1 ADC common instance, parameter of this macro
+  *         is useless and can be ignored (parameter kept for compatibility
+  *         with devices featuring several ADC common instances).
+  * @param  __ADCXY_COMMON__ ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value "0" if all ADC instances sharing the same ADC common instance
+  *         are disabled.
+  *         Value "1" if at least one ADC instance sharing the same ADC common instance
+  *         is enabled.
+  */
+#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
+
+/**
+  * @brief  Helper macro to define the ADC conversion data full-scale digital
+  *         value corresponding to the selected ADC resolution.
+  * @note   ADC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data full-scale digital value
+  */
+#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+  __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to convert the ADC conversion data from
+  *         a resolution to another resolution.
+  * @param  __DATA__ ADC conversion data to be converted
+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data to the requested resolution
+  */
+#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+                                          __ADC_RESOLUTION_CURRENT__,\
+                                          __ADC_RESOLUTION_TARGET__) \
+__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\
+                                 (__ADC_RESOLUTION_CURRENT__),\
+                                 (__ADC_RESOLUTION_TARGET__))
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                       __ADC_DATA__,\
+                                       __ADC_RESOLUTION__) \
+__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\
+                              (__ADC_DATA__),\
+                              (__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to calculate analog reference voltage (Vref+)
+  *         (unit: mVolt) from ADC conversion data of internal voltage
+  *         reference VrefInt.
+  * @note   Computation is using VrefInt calibration value
+  *         stored in system memory for each device during production.
+  * @note   This voltage depends on user board environment: voltage level
+  *         connected to pin Vref+.
+  *         On devices with small package, the pin Vref+ is not present
+  *         and internally bonded to pin Vdda.
+  * @note   On this STM32 series, calibration data of internal voltage reference
+  *         VrefInt corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         internal voltage reference VrefInt.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *         of internal voltage reference VrefInt (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval Analog reference voltage (unit: mV)
+  */
+#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+                                          __ADC_RESOLUTION__) \
+__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\
+                                 (__ADC_RESOLUTION__))
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor typical values
+  *         (refer to device datasheet).
+  * @note   Calculation formula:
+  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+  *                         / Avg_Slope + CALx_TEMP
+  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
+  *                                   (unit: digital value)
+  *                Avg_Slope        = temperature sensor slope
+  *                                   (unit: uV/Degree Celsius)
+  *                TS_TYP_CALx_VOLT = temperature sensor digital value at
+  *                                   temperature CALx_TEMP (unit: mV)
+  *         Caution: Calculation relevancy under reserve the temperature sensor
+  *                  of the current device has characteristics in line with
+  *                  datasheet typical values.
+  * @note:  On this STM32 series, calibtation parameter TS_CAL1 can be used
+  *         to improve calculation accuracy.
+  *         Refer to @ref TEMPSENSOR_CAL1_ADDR.
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   ADC measurement data must correspond to a resolution of 12bits
+  * @param  __TEMPSENSOR_TYP_AVGSLOPE__    Device datasheet data: Temperature sensor slope typical value
+  *                                        (unit: uV/DegCelsius).
+  *                                        On this STM32 series, refer to device datasheet parameter "Avg_Slope".
+  * @param  __TEMPSENSOR_TYP_CALX_V__      Device datasheet data: Temperature sensor voltage typical value (at
+  *                                        temperature and Vref+ defined in parameters below) (unit: mV).
+  *                                        On this STM32 series, refer to device datasheet parameter "V30"
+  *                                        (corresponding to TS_CAL1).
+  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see
+  *                                                              parameter above) is corresponding (unit: mV)
+  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref ADC_RESOLUTION_12B
+  *         @arg @ref ADC_RESOLUTION_10B
+  *         @arg @ref ADC_RESOLUTION_8B
+  *         @arg @ref ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+                                              __TEMPSENSOR_TYP_CALX_V__,\
+                                              __TEMPSENSOR_CALX_TEMP__,\
+                                              __VREFANALOG_VOLTAGE__,\
+                                              __TEMPSENSOR_ADC_DATA__,\
+                                              __ADC_RESOLUTION__) \
+__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\
+                                     (__TEMPSENSOR_TYP_CALX_V__),\
+                                     (__TEMPSENSOR_CALX_TEMP__),\
+                                     (__VREFANALOG_VOLTAGE__),\
+                                     (__TEMPSENSOR_ADC_DATA__),\
+                                     (__ADC_RESOLUTION__))
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Include ADC HAL Extended module */
+#include "stm32c0xx_hal_adc_ex.h"
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADC_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group1
+  * @brief    Initialization and Configuration functions
+  * @{
+  */
+/* Initialization and de-initialization functions  ****************************/
+HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/* Callbacks Register/UnRegister functions  ***********************************/
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+                                           pADC_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group2
+  * @brief    IO operation functions
+  * @{
+  */
+/* IO operation functions  *****************************************************/
+
+/* Blocking mode: Polling */
+HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
+HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
+
+/* Non-blocking mode: Interruption */
+HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
+
+/* Non-blocking mode: DMA */
+HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
+HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
+
+/* ADC retrieve conversion value intended to be used with polling or interruption */
+uint32_t                HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
+void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc);
+/**
+  * @}
+  */
+
+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
+  *  @brief    Peripheral Control functions
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig);
+HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
+
+/**
+  * @}
+  */
+
+/* Peripheral State functions *************************************************/
+/** @addtogroup ADC_Exported_Functions_Group4
+  * @{
+  */
+uint32_t                HAL_ADC_GetState(const ADC_HandleTypeDef *hadc);
+uint32_t                HAL_ADC_GetError(const ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Private functions ---------------------------------------------------------*/
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* STM32C0xx_HAL_ADC_H */
diff --git a/code/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h b/code/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h
new file mode 100644
index 0000000..57ccdeb
--- /dev/null
+++ b/code/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h
@@ -0,0 +1,185 @@
+/**
+  ******************************************************************************
+  * @file    stm32c0xx_hal_adc_ex.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC HAL extended module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_HAL_ADC_EX_H
+#define STM32C0xx_HAL_ADC_EX_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal_def.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+  * @{
+  */
+
+/** @addtogroup ADCEx
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_HAL_EC_GROUPS  ADC instance - Groups
+  * @{
+  */
+#define ADC_REGULAR_GROUP                  (LL_ADC_GROUP_REGULAR)           /*!< ADC group regular (available on all STM32 devices) */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macros -----------------------------------------------------------*/
+
+/* Private macros ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros
+  * @{
+  */
+/* Macro reserved for internal HAL driver usage, not intended to be used in   */
+/* code of final user.                                                        */
+
+/**
+  * @brief Check whether or not ADC is independent.
+  * @param __HANDLE__ ADC handle.
+  * @note  When multimode feature is not available, the macro always returns SET.
+  * @retval SET (ADC is independent) or RESET (ADC is not).
+  */
+#define ADC_IS_INDEPENDENT(__HANDLE__)   (SET)
+
+
+/**
+  * @brief Calibration factor size verification (7 bits maximum).
+  * @param __CALIBRATION_FACTOR__ Calibration factor value.
+  * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)
+  */
+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))
+
+/**
+  * @brief Verify the ADC oversampling ratio.
+  * @param __RATIO__ programmed ADC oversampling ratio.
+  * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
+  */
+#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__)      (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2   ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4   ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8   ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16  ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32  ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64  ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \
+                                                   ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
+
+/**
+  * @brief Verify the ADC oversampling shift.
+  * @param __SHIFT__ programmed ADC oversampling shift.
+  * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
+  */
+#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \
+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))
+
+/**
+  * @brief Verify the ADC oversampling triggered mode.
+  * @param __MODE__ programmed ADC oversampling triggered mode.
+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
+  */
+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
+                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
+
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup ADCEx_Exported_Functions
+  * @{
+  */
+
+/** @addtogroup ADCEx_Exported_Functions_Group1
+  * @{
+  */
+/* IO operation functions *****************************************************/
+
+/* ADC calibration */
+HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc);
+uint32_t                HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc);
+HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor);
+
+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
+void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
+void                    HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */
+
+/** @addtogroup ADCEx_Exported_Functions_Group2
+  * @{
+  */
+/* Peripheral Control functions ***********************************************/
+HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32C0xx_HAL_ADC_EX_H */
diff --git a/code/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h b/code/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h
new file mode 100644
index 0000000..40edaef
--- /dev/null
+++ b/code/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h
@@ -0,0 +1,5516 @@
+/**
+  ******************************************************************************
+  * @file    stm32c0xx_ll_adc.h
+  * @author  MCD Application Team
+  * @brief   Header file of ADC LL module.
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef STM32C0xx_LL_ADC_H
+#define STM32C0xx_LL_ADC_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx.h"
+
+/** @addtogroup STM32C0xx_LL_Driver
+  * @{
+  */
+
+#if defined (ADC1)
+
+/** @defgroup ADC_LL ADC
+  * @{
+  */
+
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Internal mask for ADC group regular sequencer:                             */
+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */
+/* - sequencer rank bits position into the selected register                  */
+
+#define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)
+
+/* Definition of ADC group regular sequencer bits information to be inserted  */
+/* into ADC group regular sequencer ranks literals definition.                */
+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */
+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */
+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */
+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */
+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */
+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */
+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */
+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */
+
+
+/* Internal mask for ADC group regular trigger:                               */
+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */
+/* - regular trigger source                                                   */
+/* - regular trigger edge                                                     */
+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT      (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for
+                                                                  compatibility with some ADC on other STM32 series
+                                                                  having this setting set by HW default value) */
+
+/* Mask containing trigger source masks for each of possible                  */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_SOURCE_MASK           (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \
+                                            ((ADC_CFGR1_EXTSEL)                            << (4U * 1UL)) | \
+                                            ((ADC_CFGR1_EXTSEL)                            << (4U * 2UL)) | \
+                                            ((ADC_CFGR1_EXTSEL)                            << (4U * 3UL))  )
+
+/* Mask containing trigger edge masks for each of possible                    */
+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */
+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */
+#define ADC_REG_TRIG_EDGE_MASK             (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \
+                                            ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \
+                                            ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \
+                                            ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )
+
+/* Definition of ADC group regular trigger bits information.                  */
+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */
+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */
+
+
+/* Internal mask for ADC channel:                                             */
+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */
+/* - channel identifier defined by number                                     */
+/* - channel identifier defined by bitfield                                   */
+/* - channel differentiation between external channels (connected to          */
+/*   GPIO pins) and internal channels (connected to internal paths)           */
+#define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR1_AWD1CH)
+#define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_CHSELR_CHSEL)
+#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ     (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to
+  ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer,
+  if set to mode "fully configurable", can contain channels with a restricted channel number.
+  Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */
+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)              /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK"
+                                                                   position in register */
+#define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \
+                                            ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */
+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK
+  >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */
+
+/* Channel differentiation between external and internal channels */
+#define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */
+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH)
+
+/* Definition of channels ID number information to be inserted into           */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_NUMBER               (0x00000000UL)
+#define ADC_CHANNEL_1_NUMBER               (ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_2_NUMBER               (ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_3_NUMBER               (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_4_NUMBER               (ADC_CFGR1_AWD1CH_2)
+#define ADC_CHANNEL_5_NUMBER               (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_6_NUMBER               (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_7_NUMBER               (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_8_NUMBER               (ADC_CFGR1_AWD1CH_3)
+#define ADC_CHANNEL_9_NUMBER               (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_10_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_11_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_12_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2)
+#define ADC_CHANNEL_13_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_14_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
+#define ADC_CHANNEL_15_NUMBER              (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \
+                                            ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_16_NUMBER              (ADC_CFGR1_AWD1CH_4)
+#define ADC_CHANNEL_17_NUMBER              (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_18_NUMBER              (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1)
+
+#define ADC_CHANNEL_19_NUMBER              (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_20_NUMBER              (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 )
+#define ADC_CHANNEL_21_NUMBER              (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0)
+#define ADC_CHANNEL_22_NUMBER              (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1)
+
+/* Definition of channels ID bitfield information to be inserted into         */
+/* channels literals definition.                                              */
+#define ADC_CHANNEL_0_BITFIELD             (ADC_CHSELR_CHSEL0)
+#define ADC_CHANNEL_1_BITFIELD             (ADC_CHSELR_CHSEL1)
+#define ADC_CHANNEL_2_BITFIELD             (ADC_CHSELR_CHSEL2)
+#define ADC_CHANNEL_3_BITFIELD             (ADC_CHSELR_CHSEL3)
+#define ADC_CHANNEL_4_BITFIELD             (ADC_CHSELR_CHSEL4)
+#define ADC_CHANNEL_5_BITFIELD             (ADC_CHSELR_CHSEL5)
+#define ADC_CHANNEL_6_BITFIELD             (ADC_CHSELR_CHSEL6)
+#define ADC_CHANNEL_7_BITFIELD             (ADC_CHSELR_CHSEL7)
+#define ADC_CHANNEL_8_BITFIELD             (ADC_CHSELR_CHSEL8)
+#define ADC_CHANNEL_9_BITFIELD             (ADC_CHSELR_CHSEL9)
+#define ADC_CHANNEL_10_BITFIELD            (ADC_CHSELR_CHSEL10)
+#define ADC_CHANNEL_11_BITFIELD            (ADC_CHSELR_CHSEL11)
+#define ADC_CHANNEL_12_BITFIELD            (ADC_CHSELR_CHSEL12)
+#define ADC_CHANNEL_13_BITFIELD            (ADC_CHSELR_CHSEL13)
+#define ADC_CHANNEL_14_BITFIELD            (ADC_CHSELR_CHSEL14)
+#define ADC_CHANNEL_15_BITFIELD            (ADC_CHSELR_CHSEL15)
+#define ADC_CHANNEL_16_BITFIELD            (ADC_CHSELR_CHSEL16)
+#define ADC_CHANNEL_17_BITFIELD            (ADC_CHSELR_CHSEL17)
+#define ADC_CHANNEL_18_BITFIELD            (ADC_CHSELR_CHSEL18)
+#define ADC_CHANNEL_19_BITFIELD            (ADC_CHSELR_CHSEL19)
+#define ADC_CHANNEL_20_BITFIELD            (ADC_CHSELR_CHSEL20)
+#define ADC_CHANNEL_21_BITFIELD            (ADC_CHSELR_CHSEL21)
+#define ADC_CHANNEL_22_BITFIELD            (ADC_CHSELR_CHSEL22)
+
+/* Internal mask for ADC channel sampling time:                               */
+/* To select into literals LL_ADC_SAMPLINGTIME_x                              */
+/* the relevant bits for:                                                     */
+/* (concatenation of multiple bits used in register SMPR)                     */
+/* - ADC channels sampling time: setting channel wise, to map each channel    */
+/*   on one of the common sampling time available.                            */
+/* - ADC channels common sampling time: set a sampling time into one of the   */
+/*   common sampling time available.                                          */
+#define ADC_SAMPLING_TIME_CH_MASK          (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS)
+#define ADC_SAMPLING_TIME_SMP_MASK         (ADC_SMPR_SMP2 | ADC_SMPR_SMP1)
+#define ADC_SAMPLING_TIME_SMP_SHIFT_MASK   (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS)
+
+/* Internal mask for ADC analog watchdog:                                     */
+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */
+/* (concatenation of multiple bits used in different analog watchdogs,        */
+/* (feature of several watchdogs not available on all STM32 series)).         */
+/* - analog watchdog 1: monitored channel defined by number,                  */
+/*   selection of ADC group (ADC group regular).                              */
+/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */
+/*   selection on groups.                                                     */
+
+/* Internal register offset for ADC analog watchdog channel configuration */
+#define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)
+#define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)
+#define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)
+
+/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */
+/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */
+#define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)
+#define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)
+
+#define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)
+#define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL)
+
+#define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
+#define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)
+#define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)
+
+#define ADC_AWD_CRX_REGOFFSET_POS          (20UL)                      /* Position of bits ADC_AWD_CRx_REGOFFSET
+                                                                          in ADC_AWD_CRX_REGOFFSET_MASK */
+
+/* Internal register offset for ADC analog watchdog threshold configuration */
+#define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)
+#define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)
+#define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS))
+#define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)
+#define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)      /* Position of bits ADC_SQRx_REGOFFSET
+                                                                               in ADC_AWD_TRX_REGOFFSET_MASK */
+#define ADC_AWD_TRX_BIT_HIGH_MASK          (0x00010000UL)                   /* Selection of 1 bit to discriminate
+                                                                               threshold high: mask of bit */
+#define ADC_AWD_TRX_BIT_HIGH_POS           (16UL)                           /* Selection of 1 bit to discriminate
+                                                                               threshold high: position of bit */
+#define ADC_AWD_TRX_BIT_HIGH_SHIFT4        (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to
+                                                                               position to perform a shift of 4 ranks */
+#define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL)
+
+
+/* ADC registers bits positions */
+#define ADC_CFGR1_RES_BITOFFSET_POS        ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */
+#define ADC_CFGR1_AWDSGL_BITOFFSET_POS     (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */
+#define ADC_TR1_HT1_BITOFFSET_POS          (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */
+#define ADC_CHSELR_CHSEL0_BITOFFSET_POS    ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */
+#define ADC_CHSELR_CHSEL1_BITOFFSET_POS    ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */
+#define ADC_CHSELR_CHSEL2_BITOFFSET_POS    ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */
+#define ADC_CHSELR_CHSEL3_BITOFFSET_POS    ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */
+#define ADC_CHSELR_CHSEL4_BITOFFSET_POS    ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */
+#define ADC_CHSELR_CHSEL5_BITOFFSET_POS    ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */
+#define ADC_CHSELR_CHSEL6_BITOFFSET_POS    ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */
+#define ADC_CHSELR_CHSEL7_BITOFFSET_POS    ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */
+#define ADC_CHSELR_CHSEL8_BITOFFSET_POS    ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */
+#define ADC_CHSELR_CHSEL9_BITOFFSET_POS    ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */
+#define ADC_CHSELR_CHSEL10_BITOFFSET_POS   (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */
+#define ADC_CHSELR_CHSEL11_BITOFFSET_POS   (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */
+#define ADC_CHSELR_CHSEL12_BITOFFSET_POS   (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */
+#define ADC_CHSELR_CHSEL13_BITOFFSET_POS   (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */
+#define ADC_CHSELR_CHSEL14_BITOFFSET_POS   (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */
+#define ADC_CHSELR_CHSEL15_BITOFFSET_POS   (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */
+#define ADC_CHSELR_CHSEL16_BITOFFSET_POS   (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */
+#define ADC_CHSELR_CHSEL17_BITOFFSET_POS   (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */
+#define ADC_CHSELR_CHSEL18_BITOFFSET_POS   (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */
+#define ADC_CHSELR_CHSEL19_BITOFFSET_POS   (19UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL19" position in register */
+#define ADC_CHSELR_CHSEL20_BITOFFSET_POS   (20UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL20" position in register */
+#define ADC_CHSELR_CHSEL21_BITOFFSET_POS   (21UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL21" position in register */
+#define ADC_CHSELR_CHSEL22_BITOFFSET_POS   (22UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL22" position in register */
+#define ADC_SMPR_SMP1_BITOFFSET_POS        ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */
+#define ADC_SMPR_SMP2_BITOFFSET_POS        ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */
+#define ADC_SMPR_SMPSEL0_BITOFFSET_POS     ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */
+
+
+/* ADC registers bits groups */
+#define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART \
+                                            | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property
+                                           "rs": Software can read as well as set this bit. Writing '0' has no effect
+                                           on the bit value. */
+
+
+/* ADC internal channels related definitions */
+/* Internal voltage reference VrefInt */
+#define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FFF756AUL)) /* Internal voltage reference, address of
+                                           parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC
+                                           (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */
+#define VREFINT_CAL_VREF                   ( 3000UL)                    /* Analog voltage reference (Vref+)
+                                           voltage with which VrefInt has been calibrated in production
+                                           (tolerance: +-10 mV) (unit: mV). */
+/* Temperature sensor */
+/* Note: On all devices of series STM32C0, calibration parameter TS_CAL2 is not available.
+         Therefore, macro "__LL_ADC_CALC_TEMPERATURE()" is not available,
+         macro "__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS()" must be used and parameter TS_CAL1 can improve accuracy:
+         replace datasheet parameter of temperature offset (macro argument __TEMPSENSOR_TYP_CALX_V__)
+         by TEMPSENSOR_CAL1_ADDR
+         (with taking into account conversion from digital value resolution 12 bit, analog voltage reference ratio
+         between calibration and application environments) */
+#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FFF7568UL)) /* Internal temperature sensor, address of
+                                           parameter TS_CAL1: On STM32C0, temperature sensor ADC raw data acquired at
+                                           temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V
+                                           (tolerance: +-10 mV). */
+#define TEMPSENSOR_CAL1_TEMP               (( int32_t)   30)            /* Internal temperature sensor, temperature at
+                                           which temperature sensor has been calibrated in production for data into
+                                           TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */
+#define TEMPSENSOR_CAL_VREFANALOG          ( 3000UL)                    /* Analog voltage reference (Vref+) voltage
+                                           with which temperature sensor has been calibrated in production
+                                           (tolerance: +-10 mV) (unit: mV). */
+
+/**
+  * @}
+  */
+
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Private_Macros ADC Private Macros
+  * @{
+  */
+
+/**
+  * @brief  Driver macro reserved for internal use: set a pointer to
+  *         a register from a register basis from which an offset
+  *         is applied.
+  * @param  __REG__ Register basis from which the offset is applied.
+  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).
+  * @retval Pointer to register address
+  */
+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \
+  ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))
+
+/**
+  * @}
+  */
+
+
+/* Exported types ------------------------------------------------------------*/
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure
+  * @{
+  */
+
+/**
+  * @brief  Structure definition of some features of ADC common parameters
+  *         and multimode
+  *         (all ADC instances belonging to the same ADC common instance).
+  * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()
+  *         is conditioned to ADC instances state (all ADC instances
+  *         sharing the same ADC common instance):
+  *         All ADC instances sharing the same ADC common instance must be
+  *         disabled.
+  */
+typedef struct
+{
+  uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.
+                                             This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetCommonClock(). */
+
+} LL_ADC_CommonInitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC instance.
+  * @note   These parameters have an impact on ADC scope: ADC instance.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .
+  * @note   The setting of these parameters by function @ref LL_ADC_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 series. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t Clock;                       /*!< Set ADC instance clock source and prescaler.
+                                             This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE
+                                            @note On this STM32 series, this parameter has some clock ratio constraints:
+                                                  ADC clock synchronous (from PCLK) with prescaler 1 must be enabled
+                                                  only if PCLK has a 50% duty clock cycle (APB prescaler configured
+                                                  inside the RCC must be bypassed and the system clock must by 50% duty
+                                                  cycle).
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetClock().
+                                             For more details, refer to description of this function. */
+
+  uint32_t Resolution;                  /*!< Set ADC resolution.
+                                             This parameter can be a value of @ref ADC_LL_EC_RESOLUTION
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetResolution(). */
+
+  uint32_t DataAlignment;               /*!< Set ADC conversion data alignment.
+                                             This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetDataAlignment(). */
+
+  uint32_t LowPowerMode;                /*!< Set ADC low power mode.
+                                             This parameter can be a value of @ref ADC_LL_EC_LP_MODE
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_SetLowPowerMode(). */
+
+} LL_ADC_InitTypeDef;
+
+/**
+  * @brief  Structure definition of some features of ADC group regular.
+  * @note   These parameters have an impact on ADC scope: ADC group regular.
+  *         Refer to corresponding unitary functions into
+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular
+  *         (functions with prefix "REG").
+  * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()
+  *         is conditioned to ADC state:
+  *         ADC instance must be disabled.
+  *         This condition is applied to all ADC features, for efficiency
+  *         and compatibility over all STM32 series. However, the different
+  *         features can be set under different ADC state conditions
+  *         (setting possible with ADC enabled without conversion on going,
+  *         ADC enabled with conversion on going, ...)
+  *         Each feature can be updated afterwards with a unitary function
+  *         and potentially with ADC in a different state than disabled,
+  *         refer to description of each function for setting
+  *         conditioned to ADC state.
+  */
+typedef struct
+{
+  uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or
+                                             from external peripheral (timer event, external interrupt line).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE
+                                             @note On this STM32 series, setting trigger source to external trigger also
+                                                   set trigger polarity to rising edge(default setting for compatibility
+                                                   with some ADC on other STM32 series having this setting set by HW
+                                                   default value).
+                                                   In case of need to modify trigger edge, use function
+                                                   @ref LL_ADC_REG_SetTriggerEdge().
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetTriggerSource(). */
+
+  uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.
+                                             @note This parameter has an effect only if group regular sequencer is set
+                                                    to mode "fully configurable". Refer to function
+                                                    @ref LL_ADC_REG_SetSequencerConfigurable().
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetSequencerLength(). */
+
+  uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided
+                                             and scan conversions interrupted every selected number of ranks.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE
+                                             @note This parameter has an effect only if group regular sequencer is
+                                                   enabled (depending on the sequencer mode: scan length of 2 ranks or
+                                                   more, or several ADC channels enabled in group regular sequencer.
+                                                   Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ).
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetSequencerDiscont(). */
+
+  uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC
+                                             conversions are performed in single mode (one conversion per trigger) or in
+                                             continuous mode (after the first trigger, following conversions launched
+                                             successively automatically).
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE
+                                             Note: It is not possible to enable both ADC group regular continuous mode
+                                                   and discontinuous mode.
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetContinuousMode(). */
+
+  uint32_t DMATransfer;                 /*!< Set ADC group regular conversion data transfer: no transfer or transfer
+                                             by DMA, and DMA requests mode.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetDMATransfer(). */
+
+  uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:
+                                             data preserved or overwritten.
+                                             This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR
+                                             This feature can be modified afterwards using unitary function
+                                             @ref LL_ADC_REG_SetOverrun(). */
+
+} LL_ADC_REG_InitTypeDef;
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants
+  * @{
+  */
+
+/** @defgroup ADC_LL_EC_FLAG ADC flags
+  * @brief    Flags defines which can be used with LL_ADC_ReadReg function
+  * @{
+  */
+#define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */
+#define LL_ADC_FLAG_CCRDY                  ADC_ISR_CCRDY      /*!< ADC flag ADC channel configuration ready */
+#define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary
+                                           conversion */
+#define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence
+                                           conversions */
+#define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */
+#define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */
+#define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */
+#define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */
+#define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */
+#define LL_ADC_FLAG_EOCAL                  ADC_ISR_EOCAL      /*!< ADC flag end of calibration */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)
+  * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions
+  * @{
+  */
+#define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */
+#define LL_ADC_IT_CCRDY                    ADC_IER_CCRDYIE    /*!< ADC interruption channel configuration ready */
+#define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary
+                                                                   conversion */
+#define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence
+                                                                   conversions */
+#define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */
+#define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling
+                                                                   phase */
+#define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */
+#define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */
+#define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */
+#define LL_ADC_IT_EOCAL                    ADC_IER_EOCALIE    /*!< ADC interruption ADC end of calibration */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose
+  * @{
+  */
+/* List of ADC registers intended to be used (most commonly) with             */
+/* DMA transfer.                                                              */
+/* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */
+#define LL_ADC_DMA_REG_REGULAR_DATA        (0x00000000UL)      /* ADC group regular conversion data register
+                                           (corresponding to register DR) to be used with ADC configured in independent
+                                           mode. Without DMA transfer, register accessed by LL function
+                                           @ref LL_ADC_REG_ReadConversionData32() and other
+                                           functions @ref LL_ADC_REG_ReadConversionDatax() */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source
+  * @{
+  */
+#define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                      /*!< ADC asynchronous clock without
+                                           prescaler */
+#define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with
+                                           prescaler division by 2. Setting common to ADC instances of ADC common
+                                           group, applied ADC instance wise to each instance clock set to clock source
+                                           asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with
+                                           prescaler division by 4. Setting common to ADC instances of ADC common
+                                           group, applied ADC instance wise to each  instance clock set to clock source
+                                           asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
+                                           prescaler division by 6. Setting common to ADC instances of ADC common
+                                           group, applied ADC instance wise to each instance clock set to clock source
+                                           asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2)                   /*!< ADC asynchronous clock with
+                                           prescaler division by 8. Setting common to ADC instances of ADC common
+                                           group, applied ADC instance wise to each instance clock  set to clock source
+                                           asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
+                                           prescaler division by 10. Setting common to ADC instances of ADC common
+                                           group, applied ADC instance wise to each instance clock  set to clock source
+                                           asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
+                                           prescaler division by 12. Setting common to ADC instances of ADC common
+                                           group, applied ADC instance wise to each instance clock  set to clock source
+                                           asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \
+                                            | ADC_CCR_PRESC_0)                  /*!< ADC asynchronous clock with
+                                           prescaler division by 16. Setting common to ADC instances of ADC common
+                                           group, applied ADC instance wise to each instance clock  set to clock source
+                                           asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                   /*!< ADC asynchronous clock with
+                                           prescaler division by 32. Setting common to ADC instances of ADC common
+                                           group, applied ADC instance wise to each instance clock  set to clock source
+                                           asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with
+                                           prescaler division by 64. Setting common to ADC instances of ADC common
+                                           group, applied ADC instance wise to each instance clock  set to clock source
+                                           asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with
+                                           prescaler division by 128. Setting common to ADC instances of ADC common
+                                           group, applied ADC instance wise to each instance clock  set to clock source
+                                           asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+#define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \
+                                            | ADC_CCR_PRESC_0)                  /*!< ADC asynchronous clock with
+                                           prescaler division by 256. Setting common to ADC instances of ADC common
+                                           group, applied ADC instance wise to each instance clock  set to clock source
+                                           asynchronous (refer to function @ref LL_ADC_SetClock() ). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels
+  * @{
+  */
+/* Note: Other measurement paths to internal channels may be available        */
+/*       (connections to other peripherals).                                  */
+/*       If they are not listed below, they do not require any specific       */
+/*       path enable. In this case, Access to measurement path is done        */
+/*       only by selecting the corresponding ADC internal channel.            */
+#define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)     /*!< ADC measurement paths all disabled */
+#define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)   /*!< ADC measurement path to internal channel VrefInt */
+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)     /*!< ADC measurement path to internal channel
+                                                                   temperature sensor */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CLOCK_SOURCE  ADC instance - Clock source
+  * @{
+  */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock
+                                           divided by 4 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock
+                                           divided by 2 */
+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CFGR2_CKMODE_1 \
+                                            | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock
+                                           not divided */
+#define LL_ADC_CLOCK_ASYNC                 (0x00000000UL)       /*!< ADC asynchronous clock. Asynchronous clock
+                                           prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution
+  * @{
+  */
+#define LL_ADC_RESOLUTION_12B              (0x00000000UL)                      /*!< ADC resolution 12 bits */
+#define LL_ADC_RESOLUTION_10B              (                  ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */
+#define LL_ADC_RESOLUTION_8B               (ADC_CFGR1_RES_1                  ) /*!< ADC resolution  8 bits */
+#define LL_ADC_RESOLUTION_6B               (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution  6 bits */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_DATA_ALIGN  ADC instance - Data alignment
+  * @{
+  */
+#define LL_ADC_DATA_ALIGN_RIGHT            (0x00000000UL)     /*!< ADC conversion data alignment: right aligned
+                                           (alignment on data register LSB bit 0)*/
+#define LL_ADC_DATA_ALIGN_LEFT             (ADC_CFGR1_ALIGN)  /*!< ADC conversion data alignment: left aligned
+                                           (alignment on data register MSB bit 15)*/
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode
+  * @{
+  */
+#define LL_ADC_LP_MODE_NONE                (0x00000000UL)     /*!< No ADC low power mode activated */
+#define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR1_WAIT)   /*!< ADC low power mode auto delay: Dynamic low power
+                                           mode, ADC conversions are performed only when necessary
+                                           (when previous ADC conversion data is read).
+                                           See description with function @ref LL_ADC_SetLowPowerMode(). */
+#define LL_ADC_LP_AUTOPOWEROFF             (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC
+                                           automatically powers-off after a ADC conversion and automatically wakes up
+                                           when a new ADC conversion is triggered (with startup time between trigger
+                                           and start of sampling). See description with function
+                                           @ref LL_ADC_SetLowPowerMode(). */
+#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF    (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait
+and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ  ADC group regular - Trigger frequency mode
+  * @{
+  */
+#define LL_ADC_TRIGGER_FREQ_HIGH           (0x00000000UL)     /*!< ADC trigger frequency mode set to high frequency.
+                                           Note: ADC trigger frequency mode must be set to low frequency when a duration
+                                           is exceeded before ADC conversion start trigger event (between ADC enable
+                                           and ADC conversion start trigger event or between two ADC conversion start
+                                           trigger event).
+                                           Duration value: Refer to device datasheet, parameter "tIdle". */
+#define LL_ADC_TRIGGER_FREQ_LOW            (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency.
+                                           Note: ADC trigger frequency mode must be set to low frequency when a duration
+                                           is exceeded before ADC conversion start trigger event (between ADC enable
+                                           and ADC conversion start trigger event or between two ADC conversion start
+                                           trigger event).
+                                           Duration value: Refer to device datasheet, parameter "tIdle". */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE  ADC common - Clock frequency mode
+  * @{
+  */
+#define LL_ADC_CLOCK_FREQ_MODE_HIGH        LL_ADC_TRIGGER_FREQ_HIGH   /*!< LL ADC define maintained for legacy purpose */
+#define LL_ADC_CLOCK_FREQ_MODE_LOW         LL_ADC_TRIGGER_FREQ_LOW    /*!< LL ADC define maintained for legacy purpose */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON  ADC instance - Sampling time common to a group of channels
+  * @{
+  */
+#define LL_ADC_SAMPLINGTIME_COMMON_1       (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group
+                                           of channels: sampling time nb 1 */
+#define LL_ADC_SAMPLINGTIME_COMMON_2       (ADC_SMPR_SMP2_BITOFFSET_POS \
+                                            | ADC_SAMPLING_TIME_CH_MASK)  /*!< Set sampling time common to a group
+                                           of channels: sampling time nb 2 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups
+  * @{
+  */
+#define LL_ADC_GROUP_REGULAR               (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number
+  * @{
+  */
+#define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER \
+                                            | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0  */
+#define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER \
+                                            | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1  */
+#define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER \
+                                            | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2  */
+#define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER \
+                                            | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3  */
+#define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER \
+                                            | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4  */
+#define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER \
+                                            | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5  */
+#define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER \
+                                            | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6  */
+#define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER \
+                                            | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7  */
+#define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER \
+                                            | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8  */
+#define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER \
+                                            | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9  */
+#define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER \
+                                            | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */
+#define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER \
+                                            | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */
+#define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER \
+                                            | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */
+#define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER \
+                                            | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */
+#define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER \
+                                            | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */
+#define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER \
+                                            | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */
+#define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER \
+                                            | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */
+#define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER \
+                                            | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */
+#define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER \
+                                            | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */
+#define LL_ADC_CHANNEL_19                  (ADC_CHANNEL_19_NUMBER \
+                                            | ADC_CHANNEL_19_BITFIELD) /*!< ADC channel ADCx_IN19 */
+#define LL_ADC_CHANNEL_20                  (ADC_CHANNEL_20_NUMBER \
+                                            | ADC_CHANNEL_20_BITFIELD) /*!< ADC channel ADCx_IN20 */
+#define LL_ADC_CHANNEL_21                  (ADC_CHANNEL_21_NUMBER \
+                                            | ADC_CHANNEL_21_BITFIELD) /*!< ADC channel ADCx_IN21 */
+#define LL_ADC_CHANNEL_22                  (ADC_CHANNEL_22_NUMBER \
+                                            | ADC_CHANNEL_22_BITFIELD) /*!< ADC channel ADCx_IN22 */
+#define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_10 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel
+                                           connected to VrefInt: Internal voltage reference. */
+#define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_9 | ADC_CHANNEL_ID_INTERNAL_CH)   /*!< ADC internal channel
+                                           connected to Temperature sensor. */
+#define LL_ADC_CHANNEL_VDDA                (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel
+                                           connected to VDDA. */
+#define LL_ADC_CHANNEL_VSSA                (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH)  /*!< ADC internal channel
+                                           connected to VSSA. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source
+  * @{
+  */
+#define LL_ADC_REG_TRIG_SOFTWARE         (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start */
+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2   (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger
+                                         from external peripheral: TIM1 TRGO.
+                                         Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_TIM1_CH4     (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+                                         conversion trigger from external peripheral:
+                                         TIM1 channel 4 event (capture compare: input capture or output capture).
+                                         Trigger edge set to rising edge (default setting). */
+#if defined(TIM2)
+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO    (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+                                         conversion trigger from external peripheral: TIM2 TRGO.
+                                         Trigger edge set to rising edge (default setting). */
+#endif /* TIM2 */
+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO    (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \
+                                          | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger
+                                         from external peripheral: TIM3 TRGO.
+                                         Trigger edge set to rising edge (default setting). */
+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11  (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \
+                                          | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular
+                                         conversion trigger from external peripheral: external interrupt line 11.
+                                         Trigger edge set to rising edge (default setting). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge
+  * @{
+  */
+#define LL_ADC_REG_TRIG_EXT_RISING         (ADC_CFGR1_EXTEN_0)                     /*!< ADC group regular conversion
+                                           trigger polarity set to rising edge */
+#define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR1_EXTEN_1)                     /*!< ADC group regular conversion
+                                           trigger polarity set to falling edge */
+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion
+                                           trigger polarity set to both rising and falling edges */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode
+  * @{
+  */
+#define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)     /*!< ADC conversions performed in single mode:
+                                           one conversion per trigger */
+#define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR1_CONT)   /*!< ADC conversions performed in continuous mode:
+                                           after the first trigger, following conversions launched successively
+                                           automatically */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER  ADC group regular - DMA transfer of ADC conversion data
+  * @{
+  */
+#define LL_ADC_REG_DMA_TRANSFER_NONE       (0x00000000UL)     /*!< ADC conversions are not transferred by DMA */
+#define LL_ADC_REG_DMA_TRANSFER_LIMITED    (ADC_CFGR1_DMAEN)  /*!< ADC conversion data are transferred by DMA,
+                                           in limited mode (one shot mode): DMA transfer requests are stopped when
+                                           number of DMA data transfers (number of ADC conversions) is reached.
+                                           This ADC mode is intended to be used with DMA mode non-circular. */
+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN)  /*!< ADC conversion data are
+                                           transferred by DMA, in unlimited mode: DMA transfer requests are unlimited,
+                                           whatever number of DMA data transferred (number of ADC conversions).
+                                           This ADC mode is intended to be used with DMA mode circular. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data
+  * @{
+  */
+#define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)     /*!< ADC group regular behavior in case of overrun:
+                                                                   data preserved */
+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun:
+                                                                   data overwritten */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_MODE  ADC group regular - Sequencer configuration flexibility
+  * @{
+  */
+#define LL_ADC_REG_SEQ_FIXED               (0x00000000UL)        /*!< Sequencer configured to not fully configurable:
+                                           sequencer length and each rank affectation to a channel are fixed
+                                           by channel HW number. Refer to description of function
+                                           @ref LL_ADC_REG_SetSequencerChannels(). */
+#define LL_ADC_REG_SEQ_CONFIGURABLE        (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable:
+                                           sequencer length and each rank affectation to a channel are configurable.
+                                           Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length
+  * @{
+  */
+#define LL_ADC_REG_SEQ_SCAN_DISABLE        (ADC_CHSELR_SQ2)               /*!< ADC group regular sequencer disable
+                                           (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (ADC_CHSELR_SQ3)               /*!< ADC group regular sequencer enable
+                                           with 2 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (ADC_CHSELR_SQ4)               /*!< ADC group regular sequencer enable
+                                           with 3 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (ADC_CHSELR_SQ5)               /*!< ADC group regular sequencer enable
+                                           with 4 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (ADC_CHSELR_SQ6)               /*!< ADC group regular sequencer enable
+                                           with 5 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (ADC_CHSELR_SQ7)               /*!< ADC group regular sequencer enable
+                                           with 6 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (ADC_CHSELR_SQ8)               /*!< ADC group regular sequencer enable
+                                           with 7 ranks in the sequence */
+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (0x00000000UL)                 /*!< ADC group regular sequencer enable
+                                           with 8 ranks in the sequence */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION  ADC group regular - Sequencer scan direction
+  * @{
+  */
+#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD    (0x00000000UL)      /*!< On this STM32 series, parameter relevant only if
+                                           sequencer set to mode not fully configurable, refer to function
+                                           @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan
+                                           direction forward: from lowest channel number to highest channel number
+                                           (scan of all ranks, ADC conversion of ranks with channels enabled in
+                                           sequencer). On some other STM32 series, this setting is not available
+                                           and the default scan direction is forward. */
+#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD   (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only if
+                                           sequencer set to mode not fully configurable, refer to function
+                                           @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan
+                                           direction backward: from highest channel number to lowest channel number
+                                           (scan of all ranks, ADC conversion of ranks with channels enabled in
+                                           sequencer) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode
+  * @{
+  */
+#define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                          /*!< ADC group regular sequencer
+                                           discontinuous mode disable */
+#define LL_ADC_REG_SEQ_DISCONT_1RANK       (ADC_CFGR1_DISCEN)                      /*!< ADC group regular sequencer
+                                           discontinuous mode enable with sequence interruption every rank */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks
+  * @{
+  */
+#define LL_ADC_REG_RANK_1                  (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 1 */
+#define LL_ADC_REG_RANK_2                  (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 2 */
+#define LL_ADC_REG_RANK_3                  (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 3 */
+#define LL_ADC_REG_RANK_4                  (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 4 */
+#define LL_ADC_REG_RANK_5                  (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 5 */
+#define LL_ADC_REG_RANK_6                  (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 6 */
+#define LL_ADC_REG_RANK_7                  (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 7 */
+#define LL_ADC_REG_RANK_8                  (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 8 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time
+  * @{
+  */
+#define LL_ADC_SAMPLINGTIME_1CYCLE_5       (0x00000000UL)     /*!< Sampling time 1.5 ADC clock cycle */
+#define LL_ADC_SAMPLINGTIME_3CYCLES_5      (ADC_SMPR_SMP1_0)  /*!< Sampling time 3.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_7CYCLES_5      (ADC_SMPR_SMP1_1)  /*!< Sampling time 7.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_12CYCLES_5     (ADC_SMPR_SMP1_1 \
+                                            | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_19CYCLES_5     (ADC_SMPR_SMP1_2)  /*!< Sampling time 19.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_39CYCLES_5     (ADC_SMPR_SMP1_2 \
+                                            | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_79CYCLES_5     (ADC_SMPR_SMP1_2 \
+                                            | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */
+#define LL_ADC_SAMPLINGTIME_160CYCLES_5    (ADC_SMPR_SMP1_2 \
+                                            | ADC_SMPR_SMP1_1 \
+                                            | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number
+  * @{
+  */
+#define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK \
+                                            | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */
+#define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */
+#define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels
+  * @{
+  */
+#define LL_ADC_AWD_DISABLE                 (0x00000000UL)                           /*!< ADC analog watchdog monitoring
+                                           disabled */
+#define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK \
+                                            | ADC_CFGR1_AWD1EN)                     /*!< ADC analog watchdog monitoring
+                                           of all channels, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN0, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN1, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN2, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN3, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN4, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN5, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN6, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN7, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN8, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN9, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN10, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN11, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN12, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN13, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN14, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)  /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN15, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN16, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN17, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN18, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_19_REG          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN19, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_20_REG          ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN20, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_21_REG          ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN21, converted by group regular only */
+#define LL_ADC_AWD_CHANNEL_22_REG          ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC channel ADCx_IN22, converted by group regular only */
+#define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT    & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to VrefInt: Internal voltage reference,
+                                           converted by group regular only */
+#define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to Temperature sensor,
+                                           converted by group regular only */
+#define LL_ADC_AWD_CH_VSSA_REG             ((LL_ADC_CHANNEL_16         & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to VSSA : internal analog supply ground,
+                                           converted by group regular only */
+#define LL_ADC_AWD_CH_VDDA_REG             ((LL_ADC_CHANNEL_15         & ADC_CHANNEL_ID_MASK) \
+                                            | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring
+                                           of ADC internal channel connected to VDDA : internal analog power supply,
+                                           converted by group regular only */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds
+  * @{
+  */
+#define LL_ADC_AWD_THRESHOLD_HIGH          (ADC_AWD1TR_HT1)   /*!< ADC analog watchdog threshold high */
+#define LL_ADC_AWD_THRESHOLD_LOW           (ADC_AWD1TR_LT1)   /*!< ADC analog watchdog threshold low */
+#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW     (ADC_AWD1TR_HT1 \
+                                            | ADC_AWD1TR_LT1)  /*!< ADC analog watchdog both thresholds high and low
+                                                                   concatenated into the same data */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope
+  * @{
+  */
+#define LL_ADC_OVS_DISABLE                 (0x00000000UL)                      /*!< ADC oversampling disabled. */
+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (ADC_CFGR2_OVSE)                    /*!< ADC oversampling on conversions of
+                                           ADC group regular. Literal suffix "continued" is kept for compatibility
+                                           with other STM32 devices featuring ADC group injected, in this case other
+                                           oversampling scope parameters are available. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode
+  * @{
+  */
+#define LL_ADC_OVS_REG_CONT                (0x00000000UL)     /*!< ADC oversampling discontinuous mode: continuous mode
+(all conversions of oversampling ratio are done from 1 trigger) */
+#define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TOVS)   /*!< ADC oversampling discontinuous mode: discontinuous
+                                           mode (each conversion of oversampling ratio needs a trigger) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_RATIO  Oversampling - Ratio
+  * @{
+  */
+#define LL_ADC_OVS_RATIO_2                 (0x00000000UL)                        /*!< ADC oversampling ratio of 2
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_4                 (ADC_CFGR2_OVSR_0)                    /*!< ADC oversampling ratio of 4
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_8                 (ADC_CFGR2_OVSR_1)                    /*!< ADC oversampling ratio of 8
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_16                (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_32                (ADC_CFGR2_OVSR_2)                    /*!< ADC oversampling ratio of 32
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_64                (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_128               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+#define LL_ADC_OVS_RATIO_256               (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \
+                                            | ADC_CFGR2_OVSR_0)                   /*!< ADC oversampling ratio of 256
+                                           (sum of conversions data computed to result as oversampling conversion data
+                                           (before potential shift) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data right shift
+  * @{
+  */
+#define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                        /*!< ADC oversampling no shift
+                                           (sum of the ADC conversions data is not divided to result as oversampling
+                                           conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_1           (ADC_CFGR2_OVSS_0)                    /*!< ADC oversampling right shift of 1
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 2
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_2           (ADC_CFGR2_OVSS_1)                    /*!< ADC oversampling right shift of 2
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 4
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_3           (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 8
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_4           (ADC_CFGR2_OVSS_2)                    /*!< ADC oversampling right shift of 4
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 16
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_5           (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 32
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_6           (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 64
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_7           (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \
+                                            | ADC_CFGR2_OVSS_0)                   /*!< ADC oversampling right shift of 7
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 128
+                                           to result as oversampling conversion data) */
+#define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3)                    /*!< ADC oversampling right shift of 8
+                                           (sum of the ADC conversions data (after OVS ratio) is divided by 256
+                                           to result as oversampling conversion data) */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_HELPER_MACRO  Definitions of constants used by helper macro
+  * @{
+  */
+#define LL_ADC_TEMPERATURE_CALC_ERROR      ((int16_t)0x7FFF)  /* Temperature calculation error using helper macro
+                                                                 @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on
+                                                                 calibration parameters. This value is coded on 16 bits
+                                                                 (to fit on signed word or double word) and corresponds
+                                                                 to an inconsistent temperature value. */
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays
+  * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,
+  *         not timeout values.
+  *         For details on delays values, refer to descriptions in source code
+  *         above each literal definition.
+  * @{
+  */
+
+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */
+/*       not timeout values.                                                  */
+/*       Timeout values for ADC operations are dependent to device clock      */
+/*       configuration (system clock versus ADC clock),                       */
+/*       and therefore must be defined in user application.                   */
+/*       Indications for estimation of ADC timeout delays, for this           */
+/*       STM32 series:                                                        */
+/*       - ADC calibration time: maximum delay is 82/fADC.                    */
+/*         (refer to device datasheet, parameter "tCAL")                      */
+/*       - ADC enable time: maximum delay is 1 conversion cycle.              */
+/*         (refer to device datasheet, parameter "tSTAB")                     */
+/*       - ADC disable time: maximum delay should be a few ADC clock cycles   */
+/*       - ADC stop conversion time: maximum delay should be a few ADC clock  */
+/*         cycles                                                             */
+/*       - ADC conversion time: duration depending on ADC clock and ADC       */
+/*         configuration.                                                     */
+/*         (refer to device reference manual, section "Timing")               */
+
+/* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "tADCVREG_STUP").                                                */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL)           /*!< Delay for ADC stabilization time (ADC voltage
+                                                              regulator start-up time) */
+
+/* Delay for internal voltage reference stabilization time.                   */
+/* Delay set to maximum value (refer to device datasheet,                     */
+/* parameter "tstart_vrefint").                                               */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_VREFINT_STAB_US           ( 12UL)        /*!< Delay for internal voltage reference stabilization
+                                                                   time */
+
+/* Delay for temperature sensor stabilization time.                           */
+/* Literal set to maximum value (refer to device datasheet,                   */
+/* parameter "tSTART").                                                       */
+/* Unit: us                                                                   */
+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US        (120UL)        /*!< Delay for temperature sensor stabilization time
+                                                                   (starting from temperature sensor enable, refer to
+                                                                   @ref LL_ADC_SetCommonPathInternalCh()) */
+#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL)        /*!< Delay for temperature sensor buffer stabilization
+                                                                   time (starting from ADC enable, refer to
+                                                                   @ref LL_ADC_Enable()) */
+
+/* Delay required between ADC end of calibration and ADC enable.              */
+/* Note: On this STM32 series, a minimum number of ADC clock cycles           */
+/*       are required between ADC end of calibration and ADC enable.          */
+/*       Wait time can be computed in user application by waiting for the     */
+/*       equivalent number of CPU cycles, by taking into account              */
+/*       ratio of CPU clock versus ADC clock prescalers.                      */
+/* Unit: ADC clock cycles.                                                    */
+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES   (  2UL)        /*!< Delay required between ADC end of calibration
+                                                                   and ADC enable */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros
+  * @{
+  */
+
+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros
+  * @{
+  */
+
+/**
+  * @brief  Write a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be written
+  * @param  __VALUE__ Value to be written in the register
+  * @retval None
+  */
+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
+
+/**
+  * @brief  Read a value in ADC register
+  * @param  __INSTANCE__ ADC Instance
+  * @param  __REG__ Register to be read
+  * @retval Register value
+  */
+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro
+  * @{
+  */
+
+/**
+  * @brief  Helper macro to get ADC channel number in decimal format
+  *         from literals LL_ADC_CHANNEL_x.
+  * @note   Example:
+  *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)
+  *           will return decimal number "4".
+  * @note   The input can be a value from functions where a channel
+  *         number is returned, either defined with number
+  *         or with bitfield (only one bit must be set).
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @retval Value between Min_Data=0 and Max_Data=18
+  */
+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                                         \
+  ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ?                                                \
+   (                                                                                                        \
+       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS                  \
+   )                                                                                                        \
+   :                                                                                                        \
+   ((((__CHANNEL__) & ADC_CHANNEL_0_BITFIELD) == ADC_CHANNEL_0_BITFIELD) ? (0UL) :                          \
+    ((((__CHANNEL__) & ADC_CHANNEL_1_BITFIELD) == ADC_CHANNEL_1_BITFIELD) ? (1UL) :                         \
+     ((((__CHANNEL__) & ADC_CHANNEL_2_BITFIELD) == ADC_CHANNEL_2_BITFIELD) ? (2UL) :                        \
+      ((((__CHANNEL__) & ADC_CHANNEL_3_BITFIELD) == ADC_CHANNEL_3_BITFIELD) ? (3UL) :                       \
+       ((((__CHANNEL__) & ADC_CHANNEL_4_BITFIELD) == ADC_CHANNEL_4_BITFIELD) ? (4UL) :                      \
+        ((((__CHANNEL__) & ADC_CHANNEL_5_BITFIELD) == ADC_CHANNEL_5_BITFIELD) ? (5UL) :                     \
+         ((((__CHANNEL__) & ADC_CHANNEL_6_BITFIELD) == ADC_CHANNEL_6_BITFIELD) ? (6UL) :                    \
+          ((((__CHANNEL__) & ADC_CHANNEL_7_BITFIELD) == ADC_CHANNEL_7_BITFIELD) ? (7UL) :                   \
+           ((((__CHANNEL__) & ADC_CHANNEL_8_BITFIELD) == ADC_CHANNEL_8_BITFIELD) ? (8UL) :                  \
+            ((((__CHANNEL__) & ADC_CHANNEL_9_BITFIELD) == ADC_CHANNEL_9_BITFIELD) ? (9UL) :                 \
+             ((((__CHANNEL__) & ADC_CHANNEL_10_BITFIELD) == ADC_CHANNEL_10_BITFIELD) ? (10UL) :             \
+              ((((__CHANNEL__) & ADC_CHANNEL_11_BITFIELD) == ADC_CHANNEL_11_BITFIELD) ? (11UL) :            \
+               ((((__CHANNEL__) & ADC_CHANNEL_12_BITFIELD) == ADC_CHANNEL_12_BITFIELD) ? (12UL) :           \
+                ((((__CHANNEL__) & ADC_CHANNEL_13_BITFIELD) == ADC_CHANNEL_13_BITFIELD) ? (13UL) :          \
+                 ((((__CHANNEL__) & ADC_CHANNEL_14_BITFIELD) == ADC_CHANNEL_14_BITFIELD) ? (14UL) :         \
+                  ((((__CHANNEL__) & ADC_CHANNEL_15_BITFIELD) == ADC_CHANNEL_15_BITFIELD) ? (15UL) :        \
+                   ((((__CHANNEL__) & ADC_CHANNEL_16_BITFIELD) == ADC_CHANNEL_16_BITFIELD) ? (16UL) :       \
+                    ((((__CHANNEL__) & ADC_CHANNEL_17_BITFIELD) == ADC_CHANNEL_17_BITFIELD) ? (17UL) :      \
+                     ((((__CHANNEL__) & ADC_CHANNEL_18_BITFIELD) == ADC_CHANNEL_18_BITFIELD) ? (18UL) :     \
+                      ((((__CHANNEL__) & ADC_CHANNEL_19_BITFIELD) == ADC_CHANNEL_19_BITFIELD) ? (19UL) :    \
+                       ((((__CHANNEL__) & ADC_CHANNEL_20_BITFIELD) == ADC_CHANNEL_20_BITFIELD) ? (20UL) :   \
+                        ((((__CHANNEL__) & ADC_CHANNEL_21_BITFIELD) == ADC_CHANNEL_21_BITFIELD) ? (21UL) :  \
+                         ((((__CHANNEL__) & ADC_CHANNEL_22_BITFIELD) == ADC_CHANNEL_22_BITFIELD) ? (22UL) : \
+                          (0UL)))))))))))))))))))))))))
+
+/**
+  * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x
+  *         from number in decimal format.
+  * @note   Example:
+  *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)
+  *           will return a data equivalent to "LL_ADC_CHANNEL_4".
+  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  */
+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \
+  (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) |                 \
+   (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)))
+
+/**
+  * @brief  Helper macro to determine whether the selected channel
+  *         corresponds to literal definitions of driver.
+  * @note   The different literal definitions of ADC channels are:
+  *         - ADC internal channel:
+  *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...
+  *         - ADC external channel (channel connected to a GPIO pin):
+  *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...
+  * @note   The channel parameter must be a value defined from literal
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),
+  *         must not be a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel
+  *         (channel connected to a GPIO pin).
+  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
+  */
+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \
+  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)
+
+/**
+  * @brief  Helper macro to convert a channel defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         to its equivalent parameter definition of a ADC external channel
+  *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).
+  * @note   The channel parameter can be, additionally to a value
+  *         defined from parameter definition of a ADC internal channel
+  *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is returned
+  *         from ADC registers.
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CHANNEL_0
+  *         @arg @ref LL_ADC_CHANNEL_1
+  *         @arg @ref LL_ADC_CHANNEL_2
+  *         @arg @ref LL_ADC_CHANNEL_3
+  *         @arg @ref LL_ADC_CHANNEL_4
+  *         @arg @ref LL_ADC_CHANNEL_5
+  *         @arg @ref LL_ADC_CHANNEL_6
+  *         @arg @ref LL_ADC_CHANNEL_7
+  *         @arg @ref LL_ADC_CHANNEL_8
+  *         @arg @ref LL_ADC_CHANNEL_9
+  *         @arg @ref LL_ADC_CHANNEL_10
+  *         @arg @ref LL_ADC_CHANNEL_11
+  *         @arg @ref LL_ADC_CHANNEL_12
+  *         @arg @ref LL_ADC_CHANNEL_13
+  *         @arg @ref LL_ADC_CHANNEL_14
+  *         @arg @ref LL_ADC_CHANNEL_15
+  *         @arg @ref LL_ADC_CHANNEL_16
+  *         @arg @ref LL_ADC_CHANNEL_17
+  *         @arg @ref LL_ADC_CHANNEL_18
+  *         @arg @ref LL_ADC_CHANNEL_19
+  *         @arg @ref LL_ADC_CHANNEL_20
+  *         @arg @ref LL_ADC_CHANNEL_21
+  *         @arg @ref LL_ADC_CHANNEL_22
+  */
+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \
+  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)
+
+/**
+  * @brief  Helper macro to determine whether the internal channel
+  *         selected is available on the ADC instance selected.
+  * @note   The channel parameter must be a value defined from parameter
+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,
+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),
+  *         must not be a value defined from parameter definition of
+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)
+  *         or a value from functions where a channel number is
+  *         returned from ADC registers,
+  *         because internal and external channels share the same channel
+  *         number in ADC registers. The differentiation is made only with
+  *         parameters definitions of driver.
+  * @param  __ADC_INSTANCE__ ADC instance
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_VREFINT
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR
+  *         @arg @ref ADC_CHANNEL_VDDA
+  *         @arg @ref ADC_CHANNEL_VSSA
+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.
+  *         Value "1" if the internal channel selected is available on the ADC instance selected.
+  */
+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \
+  (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)    ||                             \
+   ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) ||                             \
+   ((__CHANNEL__) == LL_ADC_CHANNEL_VDDA)       ||                             \
+   ((__CHANNEL__) == LL_ADC_CHANNEL_VSSA))
+
+/**
+  * @brief  Helper macro to define ADC analog watchdog parameter:
+  *         define a single channel to monitor with analog watchdog
+  *         from sequencer channel and groups definition.
+  * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().
+  *         Example:
+  *           LL_ADC_SetAnalogWDMonitChannels(
+  *             ADC1, LL_ADC_AWD1,
+  *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))
+  * @param  __CHANNEL__ This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @param  __GROUP__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_GROUP_REGULAR
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
+  *         @arg @ref LL_ADC_AWD_CH_VDDA_REG
+  *         @arg @ref LL_ADC_AWD_CH_VSSA_REG
+  *         (1) On STM32C0, parameter not available on all devices: only on STM32C031xx.
+  */
+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \
+  (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
+
+/**
+  * @brief  Helper macro to set the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_ConfigAnalogWDThresholds()
+  *         or @ref LL_ADC_SetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to set the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           LL_ADC_SetAnalogWDThresholds
+  *            (< ADCx param >,
+  *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_8_bits>)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \
+  ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
+
+/**
+  * @brief  Helper macro to get the value of ADC analog watchdog threshold high
+  *         or low in function of ADC resolution, when ADC resolution is
+  *         different of 12 bits.
+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+  *         Example, with a ADC resolution of 8 bits, to get the value of
+  *         analog watchdog threshold high (on 8 bits):
+  *           < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION
+  *            (LL_ADC_RESOLUTION_8B,
+  *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)
+  *            );
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \
+  ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U )))
+
+/**
+  * @brief  Helper macro to get the ADC analog watchdog threshold high
+  *         or low from raw value containing both thresholds concatenated.
+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().
+  *         Example, to get analog watchdog threshold high from the register raw value:
+  *           __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, <raw_value_with_both_thresholds>);
+  * @param  __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @param  __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__)                            \
+  (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \
+   & LL_ADC_AWD_THRESHOLD_LOW)
+
+/**
+  * @brief  Helper macro to select the ADC common instance
+  *         to which is belonging the selected ADC instance.
+  * @note   ADC common register instance can be used for:
+  *         - Set parameters common to several ADC instances
+  *         - Multimode (for devices with several ADC instances)
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @param  __ADCx__ ADC instance
+  * @retval ADC common register instance
+  */
+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \
+  (ADC1_COMMON)
+
+/**
+  * @brief  Helper macro to check if all ADC instances sharing the same
+  *         ADC common instance are disabled.
+  * @note   This check is required by functions with setting conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.
+  * @note   On devices with only 1 ADC common instance, parameter of this macro
+  *         is useless and can be ignored (parameter kept for compatibility
+  *         with devices featuring several ADC common instances).
+  * @param  __ADCXY_COMMON__ ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Value "0" if all ADC instances sharing the same ADC common instance
+  *         are disabled.
+  *         Value "1" if at least one ADC instance sharing the same ADC common instance
+  *         is enabled.
+  */
+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \
+  LL_ADC_IsEnabled(ADC1)
+
+/**
+  * @brief  Helper macro to define the ADC conversion data full-scale digital
+  *         value corresponding to the selected ADC resolution.
+  * @note   ADC conversion data full-scale corresponds to voltage range
+  *         determined by analog voltage references Vref+ and Vref-
+  *         (refer to reference manual).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)
+  */
+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \
+  (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))
+
+/**
+  * @brief  Helper macro to convert the ADC conversion data from
+  *         a resolution to another resolution.
+  * @param  __DATA__ ADC conversion data to be converted
+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data to the requested resolution
+  */
+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
+                                         __ADC_RESOLUTION_CURRENT__,\
+                                         __ADC_RESOLUTION_TARGET__)          \
+(((__DATA__)                                                                 \
+  << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)))  \
+ >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))     \
+)
+
+/**
+  * @brief  Helper macro to calculate the voltage (unit: mVolt)
+  *         corresponding to a ADC conversion data (unit: digital value).
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)
+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *                       (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)
+  */
+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
+                                      __ADC_DATA__,\
+                                      __ADC_RESOLUTION__)                    \
+((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \
+ / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \
+)
+
+/**
+  * @brief  Helper macro to calculate analog reference voltage (Vref+)
+  *         (unit: mVolt) from ADC conversion data of internal voltage
+  *         reference VrefInt.
+  * @note   Computation is using VrefInt calibration value
+  *         stored in system memory for each device during production.
+  * @note   This voltage depends on user board environment: voltage level
+  *         connected to pin Vref+.
+  *         On devices with small package, the pin Vref+ is not present
+  *         and internally bonded to pin Vdda.
+  * @note   On this STM32 series, calibration data of internal voltage reference
+  *         VrefInt corresponds to a resolution of 12 bits,
+  *         this is the recommended ADC resolution to convert voltage of
+  *         internal voltage reference VrefInt.
+  *         Otherwise, this macro performs the processing to scale
+  *         ADC conversion data to 12 bits.
+  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)
+  *         of internal voltage reference VrefInt (unit: digital value).
+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Analog reference voltage (unit: mV)
+  */
+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
+                                         __ADC_RESOLUTION__)                 \
+(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \
+ / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \
+                                    (__ADC_RESOLUTION__),                    \
+                                    LL_ADC_RESOLUTION_12B)                   \
+)
+
+/**
+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)
+  *         from ADC conversion data of internal temperature sensor.
+  * @note   Computation is using temperature sensor typical values
+  *         (refer to device datasheet).
+  * @note   Calculation formula:
+  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)
+  *                         / Avg_Slope + CALx_TEMP
+  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC
+  *                                   (unit: digital value)
+  *                Avg_Slope        = temperature sensor slope
+  *                                   (unit: uV/Degree Celsius)
+  *                TS_TYP_CALx_VOLT = temperature sensor digital value at
+  *                                   temperature CALx_TEMP (unit: mV)
+  *         Caution: Calculation relevancy under reserve the temperature sensor
+  *                  of the current device has characteristics in line with
+  *                  datasheet typical values.
+  * @note:  On this STM32 series, calibtation parameter TS_CAL1 can be used
+  *         to improve calculation accuracy.
+  *         Refer to @ref TEMPSENSOR_CAL1_ADDR.
+  * @note   As calculation input, the analog reference voltage (Vref+) must be
+  *         defined as it impacts the ADC LSB equivalent voltage.
+  * @note   Analog reference voltage (Vref+) must be either known from
+  *         user board environment or can be calculated using ADC measurement
+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().
+  * @note   ADC measurement data must correspond to a resolution of 12 bits
+  *         (full scale digital value 4095). If not the case, the data must be
+  *         preliminarily rescaled to an equivalent resolution of 12 bits.
+  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value
+                                          (unit: uV/DegCelsius).
+  *                                       On this STM32 series, refer to device datasheet parameter "Avg_Slope".
+  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value
+                                          (at temperature and Vref+ defined in parameters below) (unit: mV).
+  *                                       On this STM32 series, refer to datasheet parameter "V30" (corresponding
+  *                                       to TS_CAL1).
+  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage
+                                          (see parameter above) is corresponding (unit: mV)
+  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) value (unit: mV)
+  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).
+  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.
+  *         This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval Temperature (unit: degree Celsius)
+  */
+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\
+                                             __TEMPSENSOR_TYP_CALX_V__,\
+                                             __TEMPSENSOR_CALX_TEMP__,\
+                                             __VREFANALOG_VOLTAGE__,\
+                                             __TEMPSENSOR_ADC_DATA__,\
+                                             __ADC_RESOLUTION__)            \
+(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \
+               / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \
+              * 1000UL)                                                     \
+    -                                                                       \
+    (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \
+              * 1000UL)                                                     \
+   )                                                                        \
+  ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                \
+ ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                    \
+)
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management
+  * @{
+  */
+/* Note: LL ADC functions to set DMA transfer are located into sections of    */
+/*       configuration of ADC instance, groups and multimode (if available):  */
+/*       @ref LL_ADC_REG_SetDMATransfer(), ...                                */
+
+/**
+  * @brief  Function to help to configure DMA transfer from ADC: retrieve the
+  *         ADC register address from ADC instance and a list of ADC registers
+  *         intended to be used (most commonly) with DMA transfer.
+  * @note   These ADC registers are data registers:
+  *         when ADC conversion data is available in ADC data registers,
+  *         ADC generates a DMA transfer request.
+  * @note   This macro is intended to be used with LL DMA driver, refer to
+  *         function "LL_DMA_ConfigAddresses()".
+  *         Example:
+  *           LL_DMA_ConfigAddresses(DMA1,
+  *                                  LL_DMA_CHANNEL_1,
+  *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),
+  *                                  (uint32_t)&< array or variable >,
+  *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);
+  * @note   For devices with several ADC: in multimode, some devices
+  *         use a different data register outside of ADC instance scope
+  *         (common data register). This macro manages this register difference,
+  *         only ADC instance has to be set as parameter.
+  * @rmtoll DR       DATA           LL_ADC_DMA_GetRegAddr
+  * @param  ADCx ADC instance
+  * @param  Register This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA
+  * @retval ADC register address
+  */
+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register)
+{
+  /* Prevent unused argument(s) compilation warning */
+  (void)(Register);
+
+  /* Retrieve address of register DR */
+  return (uint32_t) &(ADCx->DR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several
+  *           ADC instances
+  * @{
+  */
+
+/**
+  * @brief  Set parameter common to several ADC: Clock source and prescaler.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      PRESC          LL_ADC_SetCommonClock
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  CommonClock This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
+  *
+  *         (1) ADC common clock asynchronous prescaler is applied to
+  *             each ADC instance if the corresponding ADC instance clock
+  *             is set to clock source asynchronous.
+  *             (refer to function @ref LL_ADC_SetClock() ).
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: Clock source and prescaler.
+  * @rmtoll CCR      PRESC          LL_ADC_GetCommonClock
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8   (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64  (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1)
+  *
+  *         (1) ADC common clock asynchronous prescaler is applied to
+  *             each ADC instance if the corresponding ADC instance clock
+  *             is set to clock source asynchronous.
+  *             (refer to function @ref LL_ADC_SetClock() ).
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC));
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Configure all paths (overwrite current configuration).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  *         The values not selected are removed from configuration.
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay is required for internal voltage reference and
+  *         temperature sensor stabilization time.
+  *         Refer to device datasheet.
+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+  *         Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
+  *         @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n
+  *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n
+  *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal);
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Add paths to the current configuration.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @note   Stabilization time of measurement path to internal channel:
+  *         After enabling internal paths, before starting ADC conversion,
+  *         a delay is required for internal voltage reference and
+  *         temperature sensor stabilization time.
+  *         Refer to device datasheet.
+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.
+  *         Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US,
+  *         @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US.
+  * @note   ADC internal channel sampling time constraint:
+  *         For ADC conversion of internal channels,
+  *         a sampling time minimum value is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChAdd\n
+  *         CCR      TSEN           LL_ADC_SetCommonPathInternalChAdd\n
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  SET_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+  * @brief  Set parameter common to several ADC: measurement path to
+  *         internal channels (VrefInt, temperature sensor, ...).
+  *         Remove paths to the current configuration.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         All ADC instances of the ADC common group must be disabled.
+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each
+  *         ADC instance or by using helper macro helper macro
+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().
+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalChRem\n
+  *         CCR      TSEN           LL_ADC_SetCommonPathInternalChRem\n
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @param  PathInternal This parameter can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)
+{
+  CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal);
+}
+
+/**
+  * @brief  Get parameter common to several ADC: measurement path to internal
+  *         channels (VrefInt, temperature sensor, ...).
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |
+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+  * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n
+  *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n
+  *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh
+  * @param  ADCxy_COMMON ADC common instance
+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
+  * @retval Returned value can be a combination of the following values:
+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE
+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT
+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON)
+{
+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Set ADC instance clock source and prescaler.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR2    CKMODE         LL_ADC_SetClock
+  * @param  ADCx ADC instance
+  * @param  ClockSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC (1)
+  *
+  *         (1) Asynchronous clock prescaler can be configured using
+  *             function @ref LL_ADC_SetCommonClock().\n
+  *         (2) Caution: This parameter has some clock ratio constraints:
+  *             This configuration must be enabled only if PCLK has a 50%
+  *             duty clock cycle (APB prescaler configured inside the RCC
+  *             must be bypassed and the system clock must by 50% duty
+  *             cycle).
+  *             Refer to reference manual.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource);
+}
+
+/**
+  * @brief  Get ADC instance clock source and prescaler.
+  * @rmtoll CFGR2    CKMODE         LL_ADC_GetClock
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2
+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2)
+  *         @arg @ref LL_ADC_CLOCK_ASYNC (1)
+  *
+  *         (1) Asynchronous clock prescaler can be retrieved using
+  *             function @ref LL_ADC_GetCommonClock().\n
+  *         (2) Caution: This parameter has some clock ratio constraints:
+  *             This configuration must be enabled only if PCLK has a 50%
+  *             duty clock cycle (APB prescaler configured inside the RCC
+  *             must be bypassed and the system clock must by 50% duty
+  *             cycle).
+  *             Refer to reference manual.
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetClock(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE));
+}
+
+/**
+  * @brief  Set ADC calibration factor in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   This function is intended to set calibration parameters
+  *         without having to perform a new calibration using
+  *         @ref LL_ADC_StartCalibration().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled, without calibration on going, without conversion
+  *         on going on group regular.
+  * @rmtoll CALFACT  CALFACT        LL_ADC_SetCalibrationFactor
+  * @param  ADCx ADC instance
+  * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor)
+{
+  MODIFY_REG(ADCx->CALFACT,
+             ADC_CALFACT_CALFACT,
+             CalibrationFactor);
+}
+
+/**
+  * @brief  Get ADC calibration factor in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   Calibration factors are set by hardware after performing
+  *         a calibration run using function @ref LL_ADC_StartCalibration().
+  * @rmtoll CALFACT  CALFACT        LL_ADC_GetCalibrationFactor
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x7F
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT));
+}
+
+/**
+  * @brief  Set ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR1    RES            LL_ADC_SetResolution
+  * @param  ADCx ADC instance
+  * @param  Resolution This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);
+}
+
+/**
+  * @brief  Get ADC resolution.
+  *         Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CFGR1    RES            LL_ADC_GetResolution
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_RESOLUTION_12B
+  *         @arg @ref LL_ADC_RESOLUTION_10B
+  *         @arg @ref LL_ADC_RESOLUTION_8B
+  *         @arg @ref LL_ADC_RESOLUTION_6B
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));
+}
+
+/**
+  * @brief  Set ADC conversion data alignment.
+  * @note   Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR1    ALIGN          LL_ADC_SetDataAlignment
+  * @param  ADCx ADC instance
+  * @param  DataAlignment This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);
+}
+
+/**
+  * @brief  Get ADC conversion data alignment.
+  * @note   Refer to reference manual for alignments formats
+  *         dependencies to ADC resolutions.
+  * @rmtoll CFGR1    ALIGN          LL_ADC_GetDataAlignment
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_DATA_ALIGN_RIGHT
+  *         @arg @ref LL_ADC_DATA_ALIGN_LEFT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));
+}
+
+/**
+  * @brief  Set ADC low power mode.
+  * @note   Description of ADC low power modes:
+  *         - ADC low power mode "auto wait": Dynamic low power mode,
+  *           ADC conversions occurrences are limited to the minimum necessary
+  *           in order to reduce power consumption.
+  *           New ADC conversion starts only when the previous
+  *           unitary conversion data (for ADC group regular)
+  *           has been retrieved by user software.
+  *           In the meantime, ADC remains idle: does not performs any
+  *           other conversion.
+  *           This mode allows to automatically adapt the ADC conversions
+  *           triggers to the speed of the software that reads the data.
+  *           Moreover, this avoids risk of overrun for low frequency
+  *           applications.
+  *           How to use this low power mode:
+  *           - It is not recommended to use with interruption or DMA
+  *             since these modes have to clear immediately the EOC flag
+  *             (by CPU to free the IRQ pending event or by DMA).
+  *             Auto wait will work but fort a very short time, discarding
+  *             its intended benefit (except specific case of high load of CPU
+  *             or DMA transfers which can justify usage of auto wait).
+  *           - Do use with polling: 1. Start conversion,
+  *             2. Later on, when conversion data is needed: poll for end of
+  *             conversion  to ensure that conversion is completed and
+  *             retrieve ADC conversion data. This will trig another
+  *             ADC conversion start.
+  *         - ADC low power mode "auto power-off" (feature available on
+  *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+  *           the ADC automatically powers-off after a conversion and
+  *           automatically wakes up when a new conversion is triggered
+  *           (with startup time between trigger and start of sampling).
+  *           This feature can be combined with low power mode "auto wait".
+  * @note   With ADC low power mode "auto wait", the ADC conversion data read
+  *         is corresponding to previous ADC conversion start, independently
+  *         of delay during which ADC was idle.
+  *         Therefore, the ADC conversion data may be outdated: does not
+  *         correspond to the current voltage level on the selected
+  *         ADC channel.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR1    WAIT           LL_ADC_SetLowPowerMode\n
+  *         CFGR1    AUTOFF         LL_ADC_SetLowPowerMode
+  * @param  ADCx ADC instance
+  * @param  LowPowerMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_LP_MODE_NONE
+  *         @arg @ref LL_ADC_LP_AUTOWAIT
+  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF
+  *         @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)
+{
+  MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);
+}
+
+/**
+  * @brief  Get ADC low power mode:
+  * @note   Description of ADC low power modes:
+  *         - ADC low power mode "auto wait": Dynamic low power mode,
+  *           ADC conversions occurrences are limited to the minimum necessary
+  *           in order to reduce power consumption.
+  *           New ADC conversion starts only when the previous
+  *           unitary conversion data (for ADC group regular)
+  *           has been retrieved by user software.
+  *           In the meantime, ADC remains idle: does not performs any
+  *           other conversion.
+  *           This mode allows to automatically adapt the ADC conversions
+  *           triggers to the speed of the software that reads the data.
+  *           Moreover, this avoids risk of overrun for low frequency
+  *           applications.
+  *           How to use this low power mode:
+  *           - It is not recommended to use with interruption or DMA
+  *             since these modes have to clear immediately the EOC flag
+  *             (by CPU to free the IRQ pending event or by DMA).
+  *             Auto wait will work but fort a very short time, discarding
+  *             its intended benefit (except specific case of high load of CPU
+  *             or DMA transfers which can justify usage of auto wait).
+  *           - Do use with polling: 1. Start conversion,
+  *             2. Later on, when conversion data is needed: poll for end of
+  *             conversion  to ensure that conversion is completed and
+  *             retrieve ADC conversion data. This will trig another
+  *             ADC conversion start.
+  *         - ADC low power mode "auto power-off" (feature available on
+  *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):
+  *           the ADC automatically powers-off after a conversion and
+  *           automatically wakes up when a new conversion is triggered
+  *           (with startup time between trigger and start of sampling).
+  *           This feature can be combined with low power mode "auto wait".
+  * @note   With ADC low power mode "auto wait", the ADC conversion data read
+  *         is corresponding to previous ADC conversion start, independently
+  *         of delay during which ADC was idle.
+  *         Therefore, the ADC conversion data may be outdated: does not
+  *         correspond to the current voltage level on the selected
+  *         ADC channel.
+  * @rmtoll CFGR1    WAIT           LL_ADC_GetLowPowerMode\n
+  *         CFGR1    AUTOFF         LL_ADC_GetLowPowerMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_LP_MODE_NONE
+  *         @arg @ref LL_ADC_LP_AUTOWAIT
+  *         @arg @ref LL_ADC_LP_AUTOPOWEROFF
+  *         @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));
+}
+
+/**
+  * @brief  Set ADC trigger frequency mode.
+  * @note   ADC trigger frequency mode must be set to low frequency when
+  *         a duration is exceeded before ADC conversion start trigger event
+  *         (between ADC enable and ADC conversion start trigger event
+  *         or between two ADC conversion start trigger event).
+  *         Duration value: Refer to device datasheet, parameter "tIdle".
+  * @note   When ADC trigger frequency mode is set to low frequency,
+  *         some rearm cycles are inserted before performing ADC conversion
+  *         start, inducing a delay of 2 ADC clock cycles.
+  * @note   Usage of ADC trigger frequency mode with ADC low power mode:
+  *         - Low power mode auto wait: Only the first ADC conversion
+  *           start trigger inserts the rearm delay.
+  *         - Low power mode auto power-off: ADC trigger frequency mode
+  *           is discarded.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR2    LFTRIG         LL_ADC_SetTriggerFrequencyMode
+  * @param  ADCx ADC instance
+  * @param  TriggerFrequencyMode This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
+  *         @arg @ref LL_ADC_TRIGGER_FREQ_LOW
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode);
+}
+
+/**
+  * @brief  Get ADC trigger frequency mode.
+  * @rmtoll CFGR2    LFTRIG         LL_ADC_GetTriggerFrequencyMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_TRIGGER_FREQ_HIGH
+  *         @arg @ref LL_ADC_TRIGGER_FREQ_LOW
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG));
+}
+
+/**
+  * @brief  Set sampling time common to a group of channels.
+  * @note   Unit: ADC clock cycles.
+  * @note   On this STM32 series, sampling time scope is on ADC instance:
+  *         Sampling time common to all channels.
+  *         (on some other STM32 families, sampling time is channel wise)
+  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
+  *         converted:
+  *         sampling time constraints must be respected (sampling time can be
+  *         adjusted in function of ADC clock frequency and sampling time
+  *         setting).
+  *         Refer to device datasheet for timings values (parameters TS_vrefint,
+  *         TS_temp, ...).
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         On this STM32 series, ADC processing time is:
+  *         - 12.5 ADC clock cycles at ADC resolution 12 bits
+  *         - 10.5 ADC clock cycles at ADC resolution 10 bits
+  *         - 8.5 ADC clock cycles at ADC resolution 8 bits
+  *         - 6.5 ADC clock cycles at ADC resolution 6 bits
+  * @note   In case of ADC conversion of internal channel (VrefInt,
+  *         temperature sensor, ...), a sampling time minimum value
+  *         is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll SMPR     SMP1           LL_ADC_SetSamplingTimeCommonChannels\n
+  * @rmtoll SMPR     SMP2           LL_ADC_SetSamplingTimeCommonChannels
+  * @param  ADCx ADC instance
+  * @param  SamplingTimeY This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
+  * @param  SamplingTime This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY,
+                                                          uint32_t SamplingTime)
+{
+  MODIFY_REG(ADCx->SMPR,
+             ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK),
+             SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
+}
+
+/**
+  * @brief  Get sampling time common to a group of channels.
+  * @note   Unit: ADC clock cycles.
+  * @note   On this STM32 series, sampling time scope is on ADC instance:
+  *         Sampling time common to all channels.
+  *         (on some other STM32 families, sampling time is channel wise)
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         Refer to reference manual for ADC processing time of
+  *         this STM32 series.
+  * @rmtoll SMPR     SMP1           LL_ADC_GetSamplingTimeCommonChannels\n
+  * @rmtoll SMPR     SMP2           LL_ADC_GetSamplingTimeCommonChannels
+  * @param  ADCx ADC instance
+  * @param  SamplingTimeY This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5
+  *         @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY)
+{
+  return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)))
+                    >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Set ADC group regular conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   On this STM32 series, setting trigger source to external trigger
+  *         also set trigger polarity to rising edge
+  *         (default setting for compatibility with some ADC on other
+  *         STM32 families having this setting set by HW default value).
+  *         In case of need to modify trigger edge, use
+  *         function @ref LL_ADC_REG_SetTriggerEdge().
+  * @note   On this STM32 series, ADC trigger frequency mode must be set
+  *         in function of frequency of ADC group regular conversion trigger.
+  *         Refer to description of function
+  *         @ref LL_ADC_SetTriggerFrequencyMode().
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR1    EXTSEL         LL_ADC_REG_SetTriggerSource\n
+  *         CFGR1    EXTEN          LL_ADC_REG_SetTriggerSource
+  * @param  ADCx ADC instance
+  * @param  TriggerSource This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+  *         (1) ADC external trigger available on STM32C071xx device only.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source:
+  *         internal (SW start) or from external peripheral (timer event,
+  *         external interrupt line).
+  * @note   To determine whether group regular trigger source is
+  *         internal (SW start) or external, without detail
+  *         of which peripheral is selected as external trigger,
+  *         (equivalent to
+  *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")
+  *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.
+  * @note   Availability of parameters of trigger sources from timer
+  *         depends on timers availability on the selected device.
+  * @rmtoll CFGR1    EXTSEL         LL_ADC_REG_GetTriggerSource\n
+  *         CFGR1    EXTEN          LL_ADC_REG_GetTriggerSource
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1)
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11
+  *         (1) ADC external trigger available on STM32C071xx device only.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx)
+{
+  __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);
+
+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */
+  /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}.                           */
+  uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));
+
+  /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL       */
+  /* to match with triggers literals definition.                              */
+  return ((TriggerSource
+           & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL)
+          | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN)
+         );
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger source internal (SW start)
+  *         or external.
+  * @note   In case of group regular trigger source set to external trigger,
+  *         to determine which peripheral is selected as external trigger,
+  *         use function @ref LL_ADC_REG_GetTriggerSource().
+  * @rmtoll CFGR1    EXTEN          LL_ADC_REG_IsTriggerSourceSWStart
+  * @param  ADCx ADC instance
+  * @retval Value "0" if trigger source external trigger
+  *         Value "1" if trigger source SW start.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Set ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    EXTEN          LL_ADC_REG_SetTriggerEdge
+  * @param  ADCx ADC instance
+  * @param  ExternalTriggerEdge This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);
+}
+
+/**
+  * @brief  Get ADC group regular conversion trigger polarity.
+  * @note   Applicable only for trigger source set to external trigger.
+  * @rmtoll CFGR1    EXTEN          LL_ADC_REG_GetTriggerEdge
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING
+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));
+}
+
+/**
+  * @brief  Set ADC group regular sequencer configuration flexibility.
+  * @note   On this STM32 series, ADC group regular sequencer both modes
+  *         "fully configurable" or "not fully configurable" are
+  *         available:
+  *         - sequencer configured to fully configurable:
+  *           sequencer length and each rank
+  *           affectation to a channel are configurable.
+  *           Refer to description of function
+  *           @ref LL_ADC_REG_SetSequencerLength().
+  *         - sequencer configured to not fully configurable:
+  *           sequencer length and each rank affectation to a channel
+  *           are fixed by channel HW number.
+  *           Refer to description of function
+  *           @ref LL_ADC_REG_SetSequencerChannels().
+  * @note   On this STM32 series, after modifying sequencer (functions
+  *         @ref LL_ADC_REG_SetSequencerLength()
+  *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
+  *         it is mandatory to wait for the assertion of CCRDY flag
+  *         Otherwise, some actions may be ignored.
+  *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
+  *         for more details.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR     CHSELRMOD      LL_ADC_REG_SetSequencerConfigurable
+  * @param  ADCx ADC instance
+  * @param  Configurability This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_FIXED
+  *         @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer configuration flexibility.
+  * @note   On this STM32 series, ADC group regular sequencer both modes
+  *         "fully configurable" or "not fully configurable" are
+  *         available:
+  *         - sequencer configured to fully configurable:
+  *           sequencer length and each rank
+  *           affectation to a channel are configurable.
+  *           Refer to description of function
+  *           @ref LL_ADC_REG_SetSequencerLength().
+  *         - sequencer configured to not fully configurable:
+  *           sequencer length and each rank affectation to a channel
+  *           are fixed by channel HW number.
+  *           Refer to description of function
+  *           @ref LL_ADC_REG_SetSequencerChannels().
+  * @rmtoll CFGR     CHSELRMOD      LL_ADC_REG_SetSequencerConfigurable
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_FIXED
+  *         @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));
+}
+
+/**
+  * @brief  Set ADC group regular sequencer length and scan direction.
+  * @note   Description of ADC group regular sequencer features:
+  *         - For devices with sequencer fully configurable
+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are configurable.
+  *           This function performs configuration of:
+  *           - Sequence length: Number of ranks in the scan sequence.
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from rank 1 to rank n).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerRanks()".
+  *         - For devices with sequencer not fully configurable
+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are defined by channel number.
+  *           This function performs configuration of:
+  *           - Sequence length: Number of ranks in the scan sequence is
+  *             defined by number of channels set in the sequence,
+  *             rank of each channel is fixed by channel HW number.
+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from lowest channel number to
+  *             highest channel number).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerChannels()".
+  *           To set scan direction differently, refer to function
+  *           @ref LL_ADC_REG_SetSequencerScanDirection().
+  * @note   On this STM32 series, ADC group regular sequencer both modes
+  *         "fully configurable" or "not fully configurable"
+  *         are available, they can be chosen using
+  *         function @ref LL_ADC_REG_SetSequencerConfigurable().
+  * @note   On this STM32 series, after modifying sequencer (functions
+  *         @ref LL_ADC_REG_SetSequencerLength()
+  *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
+  *         it is mandatory to wait for the assertion of CCRDY flag
+  *         using @ref LL_ADC_IsActiveFlag_CCRDY().
+  *         Otherwise, some actions may be ignored.
+  *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
+  *         for more details.
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CHSELR   SQ1            LL_ADC_REG_SetSequencerLength\n
+  *         CHSELR   SQ2            LL_ADC_REG_SetSequencerLength\n
+  *         CHSELR   SQ3            LL_ADC_REG_SetSequencerLength\n
+  *         CHSELR   SQ4            LL_ADC_REG_SetSequencerLength\n
+  *         CHSELR   SQ5            LL_ADC_REG_SetSequencerLength\n
+  *         CHSELR   SQ6            LL_ADC_REG_SetSequencerLength\n
+  *         CHSELR   SQ7            LL_ADC_REG_SetSequencerLength\n
+  *         CHSELR   SQ8            LL_ADC_REG_SetSequencerLength
+  * @param  ADCx ADC instance
+  * @param  SequencerNbRanks This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)
+{
+  SET_BIT(ADCx->CHSELR, SequencerNbRanks);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer length and scan direction.
+  * @note   Description of ADC group regular sequencer features:
+  *         - For devices with sequencer fully configurable
+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are configurable.
+  *           This function retrieves:
+  *           - Sequence length: Number of ranks in the scan sequence.
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from rank 1 to rank n).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerRanks()".
+  *         - For devices with sequencer not fully configurable
+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):
+  *           sequencer length and each rank affectation to a channel
+  *           are defined by channel number.
+  *           This function retrieves:
+  *           - Sequence length: Number of ranks in the scan sequence is
+  *             defined by number of channels set in the sequence,
+  *             rank of each channel is fixed by channel HW number.
+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *           - Sequence direction: Unless specified in parameters, sequencer
+  *             scan direction is forward (from lowest channel number to
+  *             highest channel number).
+  *           Sequencer ranks are selected using
+  *           function "LL_ADC_REG_SetSequencerChannels()".
+  *          To set scan direction differently, refer to function
+  *          @ref LL_ADC_REG_SetSequencerScanDirection().
+  * @note   On this STM32 series, ADC group regular sequencer both modes
+  *         "fully configurable" or "not fully configurable"
+  *         are available, they can be chosen using
+  *         function @ref LL_ADC_REG_SetSequencerConfigurable().
+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:
+  *         ADC conversion on only 1 channel.
+  * @rmtoll CHSELR   SQ1            LL_ADC_REG_GetSequencerLength\n
+  *         CHSELR   SQ2            LL_ADC_REG_GetSequencerLength\n
+  *         CHSELR   SQ3            LL_ADC_REG_GetSequencerLength\n
+  *         CHSELR   SQ4            LL_ADC_REG_GetSequencerLength\n
+  *         CHSELR   SQ5            LL_ADC_REG_GetSequencerLength\n
+  *         CHSELR   SQ6            LL_ADC_REG_GetSequencerLength\n
+  *         CHSELR   SQ7            LL_ADC_REG_GetSequencerLength\n
+  *         CHSELR   SQ8            LL_ADC_REG_GetSequencerLength
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx)
+{
+  __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL);
+  uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS;
+  uint32_t RankIndex;
+
+  /* Parse register for end of sequence identifier */
+  for (RankIndex = 0UL; RankIndex < (32U - 4U); RankIndex += 4U)
+  {
+    if ((ChannelsRanks & (ADC_CHSELR_SQ2 << RankIndex)) == (ADC_CHSELR_SQ2 << RankIndex))
+    {
+      SequencerLength = (ADC_CHSELR_SQ2 << RankIndex);
+      break;
+    }
+  }
+
+  return SequencerLength;
+}
+
+/**
+  * @brief  Set ADC group regular sequencer scan direction.
+  * @note   On this STM32 series, parameter relevant only is sequencer is set
+  *         to mode not fully configurable,
+  *         refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+  * @note   On some other STM32 series, this setting is not available and
+  *         the default scan direction is forward.
+  * @note   On this STM32 series, after modifying sequencer (functions
+  *         @ref LL_ADC_REG_SetSequencerLength()
+  *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
+  *         it is mandatory to wait for the assertion of CCRDY flag
+  *         using @ref LL_ADC_IsActiveFlag_CCRDY().
+  *         Otherwise, some actions may be ignored.
+  *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
+  *         for more details.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR1    SCANDIR        LL_ADC_REG_SetSequencerScanDirection
+  * @param  ADCx ADC instance
+  * @param  ScanDirection This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer scan direction.
+  * @note   On this STM32 series, parameter relevant only is sequencer is set
+  *         to mode not fully configurable,
+  *         refer to function @ref LL_ADC_REG_SetSequencerConfigurable().
+  * @note   On some other STM32 families, this setting is not available and
+  *         the default scan direction is forward.
+  * @rmtoll CFGR1    SCANDIR        LL_ADC_REG_GetSequencerScanDirection
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD
+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));
+}
+
+/**
+  * @brief  Set ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @note   It is not possible to enable both ADC group regular
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR1    DISCEN         LL_ADC_REG_SetSequencerDiscont\n
+  * @param  ADCx ADC instance
+  * @param  SeqDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);
+}
+
+/**
+  * @brief  Get ADC group regular sequencer discontinuous mode:
+  *         sequence subdivided and scan conversions interrupted every selected
+  *         number of ranks.
+  * @rmtoll CFGR1    DISCEN         LL_ADC_REG_GetSequencerDiscont\n
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE
+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));
+}
+
+/**
+  * @brief  Set ADC group regular sequence: channel on the selected
+  *         scan sequence rank.
+  * @note   This function performs configuration of:
+  *         - Channels ordering into each rank of scan sequence:
+  *           whatever channel can be placed into whatever rank.
+  * @note   On this STM32 series, ADC group regular sequencer is
+  *         fully configurable: sequencer length and each rank
+  *         affectation to a channel are configurable.
+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 series, after modifying sequencer (functions
+  *         @ref LL_ADC_REG_SetSequencerLength()
+  *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
+  *         it is mandatory to wait for the assertion of CCRDY flag
+  *         using @ref LL_ADC_IsActiveFlag_CCRDY().
+  *         Otherwise, some actions may be ignored.
+  *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
+  *         for more details.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CHSELR   SQ1            LL_ADC_REG_SetSequencerRanks\n
+  *         CHSELR   SQ2            LL_ADC_REG_SetSequencerRanks\n
+  *         CHSELR   SQ3            LL_ADC_REG_SetSequencerRanks\n
+  *         CHSELR   SQ4            LL_ADC_REG_SetSequencerRanks\n
+  *         CHSELR   SQ5            LL_ADC_REG_SetSequencerRanks\n
+  *         CHSELR   SQ6            LL_ADC_REG_SetSequencerRanks\n
+  *         CHSELR   SQ7            LL_ADC_REG_SetSequencerRanks\n
+  *         CHSELR   SQ8            LL_ADC_REG_SetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_RANK_1
+  *         @arg @ref LL_ADC_REG_RANK_2
+  *         @arg @ref LL_ADC_REG_RANK_3
+  *         @arg @ref LL_ADC_REG_RANK_4
+  *         @arg @ref LL_ADC_REG_RANK_5
+  *         @arg @ref LL_ADC_REG_RANK_6
+  *         @arg @ref LL_ADC_REG_RANK_7
+  *         @arg @ref LL_ADC_REG_RANK_8
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)
+{
+  /* Set bits with content of parameter "Channel" with bits position          */
+  /* in register depending on parameter "Rank".                               */
+  /* Parameters "Rank" and "Channel" are used with masks because containing   */
+  /* other bits reserved for other purpose.                                   */
+  MODIFY_REG(ADCx->CHSELR,
+             ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),
+             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+             << (Rank & ADC_REG_RANK_ID_SQRX_MASK));
+}
+
+/**
+  * @brief  Get ADC group regular sequence: channel on the selected
+  *         scan sequence rank.
+  * @note   On this STM32 series, ADC group regular sequencer is
+  *         fully configurable: sequencer length and each rank
+  *         affectation to a channel are configurable.
+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  * @rmtoll CHSELR   SQ1            LL_ADC_REG_GetSequencerRanks\n
+  *         CHSELR   SQ2            LL_ADC_REG_GetSequencerRanks\n
+  *         CHSELR   SQ3            LL_ADC_REG_GetSequencerRanks\n
+  *         CHSELR   SQ4            LL_ADC_REG_GetSequencerRanks\n
+  *         CHSELR   SQ5            LL_ADC_REG_GetSequencerRanks\n
+  *         CHSELR   SQ6            LL_ADC_REG_GetSequencerRanks\n
+  *         CHSELR   SQ7            LL_ADC_REG_GetSequencerRanks\n
+  *         CHSELR   SQ8            LL_ADC_REG_GetSequencerRanks
+  * @param  ADCx ADC instance
+  * @param  Rank This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_RANK_1
+  *         @arg @ref LL_ADC_REG_RANK_2
+  *         @arg @ref LL_ADC_REG_RANK_3
+  *         @arg @ref LL_ADC_REG_RANK_4
+  *         @arg @ref LL_ADC_REG_RANK_5
+  *         @arg @ref LL_ADC_REG_RANK_6
+  *         @arg @ref LL_ADC_REG_RANK_7
+  *         @arg @ref LL_ADC_REG_RANK_8
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank)
+{
+  return (uint32_t)((READ_BIT(ADCx->CHSELR,
+                              ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))
+                     >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)
+                    ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+                   );
+}
+
+/**
+  * @brief  Set ADC group regular sequence: channel on rank corresponding to
+  *         channel number.
+  * @note   This function performs:
+  *         - Channels ordering into each rank of scan sequence:
+  *           rank of each channel is fixed by channel HW number
+  *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *         - Set channels selected by overwriting the current sequencer
+  *           configuration.
+  * @note   On this STM32 series, ADC group regular sequencer both modes
+  *         "fully configurable" or "not fully configurable"
+  *         are available, they can be chosen using
+  *         function @ref LL_ADC_REG_SetSequencerConfigurable().
+  *         This function can be used with setting "not fully configurable".
+  *         Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
+  *         and @ref LL_ADC_REG_SetSequencerLength().
+  * @note   On this STM32 series, after modifying sequencer (functions
+  *         @ref LL_ADC_REG_SetSequencerLength()
+  *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
+  *         it is mandatory to wait for the assertion of CCRDY flag
+  *         using @ref LL_ADC_IsActiveFlag_CCRDY().
+  *         Otherwise, some actions may be ignored.
+  *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
+  *         for more details.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChannels\n
+  *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChannels
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be a combination of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
+}
+
+/**
+  * @brief  Add channel to ADC group regular sequence: channel on rank corresponding to
+  *         channel number.
+  * @note   This function performs:
+  *         - Channels ordering into each rank of scan sequence:
+  *           rank of each channel is fixed by channel HW number
+  *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *         - Set channels selected by adding them to the current sequencer
+  *           configuration.
+  * @note   On this STM32 series, ADC group regular sequencer both modes
+  *         "fully configurable" or "not fully configurable"
+  *         are available, they can be chosen using
+  *         function @ref LL_ADC_REG_SetSequencerConfigurable().
+  *         This function can be used with setting "not fully configurable".
+  *         Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
+  *         and @ref LL_ADC_REG_SetSequencerLength().
+  * @note   On this STM32 series, after modifying sequencer (functions
+  *         @ref LL_ADC_REG_SetSequencerLength()
+  *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
+  *         it is mandatory to wait for the assertion of CCRDY flag
+  *         using @ref LL_ADC_IsActiveFlag_CCRDY().
+  *         Otherwise, some actions may be ignored.
+  *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
+  *         for more details.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChAdd\n
+  *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChAdd
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be a combination of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
+}
+
+/**
+  * @brief  Remove channel to ADC group regular sequence: channel on rank corresponding to
+  *         channel number.
+  * @note   This function performs:
+  *         - Channels ordering into each rank of scan sequence:
+  *           rank of each channel is fixed by channel HW number
+  *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  *         - Set channels selected by removing them to the current sequencer
+  *           configuration.
+  * @note   On this STM32 series, ADC group regular sequencer both modes
+  *         "fully configurable" or "not fully configurable"
+  *         are available, they can be chosen using
+  *         function @ref LL_ADC_REG_SetSequencerConfigurable().
+  *         This function can be used with setting "not fully configurable".
+  *         Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
+  *         and @ref LL_ADC_REG_SetSequencerLength().
+  * @note   On this STM32 series, after modifying sequencer (functions
+  *         @ref LL_ADC_REG_SetSequencerLength()
+  *         @ref LL_ADC_REG_SetSequencerRanks(), ...)
+  *         it is mandatory to wait for the assertion of CCRDY flag
+  *         using @ref LL_ADC_IsActiveFlag_CCRDY().
+  *         Otherwise, some actions may be ignored.
+  *         Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY
+  *         for more details.
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @note   One or several values can be selected.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL1         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL2         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL3         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL4         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL5         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL6         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL7         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL8         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL9         LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL10        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL11        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL12        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL13        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL14        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL15        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL16        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL17        LL_ADC_REG_SetSequencerChRem\n
+  *         CHSELR   CHSEL18        LL_ADC_REG_SetSequencerChRem
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be a combination of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK));
+}
+
+/**
+  * @brief  Get ADC group regular sequence: channel on rank corresponding to
+  *         channel number.
+  * @note   This function performs:
+  *         - Channels order reading into each rank of scan sequence:
+  *           rank of each channel is fixed by channel HW number
+  *           (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).
+  * @note   On this STM32 series, ADC group regular sequencer both modes
+  *         "fully configurable" or "not fully configurable"
+  *         are available, they can be chosen using
+  *         function @ref LL_ADC_REG_SetSequencerConfigurable().
+  *         This function can be used with setting "not fully configurable".
+  *         Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable()
+  *         and @ref LL_ADC_REG_SetSequencerLength().
+  * @note   Depending on devices and packages, some channels may not be available.
+  *         Refer to device datasheet for channels availability.
+  * @note   On this STM32 series, to measure internal channels (VrefInt,
+  *         TempSensor, ...), measurement paths to internal channels must be
+  *         enabled separately.
+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @note   One or several values can be retrieved.
+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)
+  * @rmtoll CHSELR   CHSEL0         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL1         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL2         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL3         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL4         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL5         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL6         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL7         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL8         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL9         LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL10        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL11        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL12        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL13        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL14        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL15        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL16        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL17        LL_ADC_REG_GetSequencerChannels\n
+  *         CHSELR   CHSEL18        LL_ADC_REG_GetSequencerChannels
+  * @param  ADCx ADC instance
+  * @retval Returned value can be a combination of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx)
+{
+  uint32_t ChannelsBitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL);
+
+  return ((((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL19) >> ADC_CHSELR_CHSEL19_BITOFFSET_POS) * LL_ADC_CHANNEL_19)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL20) >> ADC_CHSELR_CHSEL20_BITOFFSET_POS) * LL_ADC_CHANNEL_20)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL21) >> ADC_CHSELR_CHSEL21_BITOFFSET_POS) * LL_ADC_CHANNEL_21)
+          | (((ChannelsBitfield & ADC_CHSELR_CHSEL22) >> ADC_CHSELR_CHSEL22_BITOFFSET_POS) * LL_ADC_CHANNEL_22)
+         );
+}
+
+/**
+  * @brief  Set ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @note   It is not possible to enable both ADC group regular
+  *         continuous mode and sequencer discontinuous mode.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR1    CONT           LL_ADC_REG_SetContinuousMode
+  * @param  ADCx ADC instance
+  * @param  Continuous This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);
+}
+
+/**
+  * @brief  Get ADC continuous conversion mode on ADC group regular.
+  * @note   Description of ADC continuous conversion mode:
+  *         - single mode: one conversion per trigger
+  *         - continuous mode: after the first trigger, following
+  *           conversions launched successively automatically.
+  * @rmtoll CFGR1    CONT           LL_ADC_REG_GetContinuousMode
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_CONV_SINGLE
+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));
+}
+
+/**
+  * @brief  Set ADC group regular conversion data transfer: no transfer or
+  *         transfer by DMA, and DMA requests mode.
+  * @note   If transfer by DMA selected, specifies the DMA requests
+  *         mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *        (overrun flag and interruption if enabled).
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_ADC_DMA_GetRegAddr().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR1    DMAEN          LL_ADC_REG_SetDMATransfer\n
+  *         CFGR1    DMACFG         LL_ADC_REG_SetDMATransfer
+  * @param  ADCx ADC instance
+  * @param  DMATransfer This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data transfer: no transfer or
+  *         transfer by DMA, and DMA requests mode.
+  * @note   If transfer by DMA selected, specifies the DMA requests
+  *         mode:
+  *         - Limited mode (One shot mode): DMA transfer requests are stopped
+  *           when number of DMA data transfers (number of
+  *           ADC conversions) is reached.
+  *           This ADC mode is intended to be used with DMA mode non-circular.
+  *         - Unlimited mode: DMA transfer requests are unlimited,
+  *           whatever number of DMA data transfers (number of
+  *           ADC conversions).
+  *           This ADC mode is intended to be used with DMA mode circular.
+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to
+  *         mode non-circular:
+  *         when DMA transfers size will be reached, DMA will stop transfers of
+  *         ADC conversions data ADC will raise an overrun error
+  *         (overrun flag and interruption if enabled).
+  * @note   To configure DMA source address (peripheral address),
+  *         use function @ref LL_ADC_DMA_GetRegAddr().
+  * @rmtoll CFGR1    DMAEN          LL_ADC_REG_GetDMATransfer\n
+  *         CFGR1    DMACFG         LL_ADC_REG_GetDMATransfer
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED
+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));
+}
+
+/**
+  * @brief  Set ADC group regular behavior in case of overrun:
+  *         data preserved or overwritten.
+  * @note   Compatibility with devices without feature overrun:
+  *         other devices without this feature have a behavior
+  *         equivalent to data overwritten.
+  *         The default setting of overrun is data preserved.
+  *         Therefore, for compatibility with all devices, parameter
+  *         overrun should be set to data overwritten.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR1    OVRMOD         LL_ADC_REG_SetOverrun
+  * @param  ADCx ADC instance
+  * @param  Overrun This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)
+{
+  MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);
+}
+
+/**
+  * @brief  Get ADC group regular behavior in case of overrun:
+  *         data preserved or overwritten.
+  * @rmtoll CFGR1    OVRMOD         LL_ADC_REG_GetOverrun
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED
+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels
+  * @{
+  */
+
+/**
+  * @brief  Set sampling time of the selected ADC channel
+  *         Unit: ADC clock cycles.
+  * @note   On this device, sampling time is on channel scope: independently
+  *         of channel mapped on ADC group regular or injected.
+  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be
+  *         converted:
+  *         sampling time constraints must be respected (sampling time can be
+  *         adjusted in function of ADC clock frequency and sampling time
+  *         setting).
+  *         Refer to device datasheet for timings values (parameters TS_vrefint,
+  *         TS_temp, ...).
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         Refer to reference manual for ADC processing time of
+  *         this STM32 series.
+  * @note   In case of ADC conversion of internal channel (VrefInt,
+  *         temperature sensor, ...), a sampling time minimum value
+  *         is required.
+  *         Refer to device datasheet.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll SMPR     SMPSEL0        LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL1        LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL2        LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL3        LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL4        LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL5        LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL6        LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL7        LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL8        LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL9        LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL10       LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL11       LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL12       LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL13       LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL14       LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL15       LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL16       LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL17       LL_ADC_SetChannelSamplingTime\n
+  *         SMPR     SMPSEL18       LL_ADC_SetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be a combination of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @param  SamplingTimeY This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY)
+{
+  /* Parameter "Channel" is used with masks because containing                */
+  /* other bits reserved for other purpose.                                   */
+  MODIFY_REG(ADCx->SMPR,
+             (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS),
+             (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK)
+            );
+}
+
+/**
+  * @brief  Get sampling time of the selected ADC channel
+  *         Unit: ADC clock cycles.
+  * @note   On this device, sampling time is on channel scope: independently
+  *         of channel mapped on ADC group regular or injected.
+  * @note   Conversion time is the addition of sampling time and processing time.
+  *         Refer to reference manual for ADC processing time of
+  *         this STM32 series.
+  * @rmtoll SMPR     SMPSEL0        LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL1        LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL2        LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL3        LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL4        LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL5        LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL6        LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL7        LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL8        LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL9        LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL10       LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL11       LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL12       LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL13       LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL14       LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL15       LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL16       LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL17       LL_ADC_GetChannelSamplingTime\n
+  *         SMPR     SMPSEL18       LL_ADC_GetChannelSamplingTime
+  * @param  ADCx ADC instance
+  * @param  Channel This parameter can be one of the following values:
+  *         @arg @ref ADC_CHANNEL_0
+  *         @arg @ref ADC_CHANNEL_1
+  *         @arg @ref ADC_CHANNEL_2
+  *         @arg @ref ADC_CHANNEL_3
+  *         @arg @ref ADC_CHANNEL_4
+  *         @arg @ref ADC_CHANNEL_5
+  *         @arg @ref ADC_CHANNEL_6
+  *         @arg @ref ADC_CHANNEL_7
+  *         @arg @ref ADC_CHANNEL_8           (1)
+  *         @arg @ref ADC_CHANNEL_9           (1)
+  *         @arg @ref ADC_CHANNEL_10
+  *         @arg @ref ADC_CHANNEL_11
+  *         @arg @ref ADC_CHANNEL_12
+  *         @arg @ref ADC_CHANNEL_13
+  *         @arg @ref ADC_CHANNEL_14
+  *         @arg @ref ADC_CHANNEL_15          (1)
+  *         @arg @ref ADC_CHANNEL_16          (1)
+  *         @arg @ref ADC_CHANNEL_17          (3)
+  *         @arg @ref ADC_CHANNEL_18          (3)
+  *         @arg @ref ADC_CHANNEL_19          (3)
+  *         @arg @ref ADC_CHANNEL_20          (3)
+  *         @arg @ref ADC_CHANNEL_21          (3)
+  *         @arg @ref ADC_CHANNEL_22          (3)
+  *         @arg @ref ADC_CHANNEL_VREFINT     (2)
+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR  (2)
+  *         @arg @ref ADC_CHANNEL_VDDA        (2)
+  *         @arg @ref ADC_CHANNEL_VSSA        (2)
+  *
+  *         (1) On STM32C0, parameter can be set in ADC group sequencer
+  *             only if sequencer is set in mode "not fully configurable",
+  *             refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n
+  *         (2) For ADC channel read back from ADC register,
+  *             comparison with internal channel parameter to be done
+  *             using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
+  *         (3) ADC channels available on STM32C031xx device only.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1
+  *         @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel)
+{
+  __IO uint32_t smpr = READ_REG(ADCx->SMPR);
+
+  /* Retrieve sampling time bit corresponding to the selected channel            */
+  /* and shift it to position 0.                                                 */
+  uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK)
+                                  >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)
+                                       + ADC_SMPR_SMPSEL0_BITOFFSET_POS)
+                                      & 0x1FUL));
+
+  /* Select sampling time bitfield depending on sampling time bit value 0 or 1.  */
+  return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1)
+          | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog
+  * @{
+  */
+
+/**
+  * @brief  Set ADC analog watchdog monitored channels:
+  *         a single channel or all channels,
+  *         on ADC group regular.
+  * @note   Once monitored channels are selected, analog watchdog
+  *         is enabled.
+  * @note   In case of need to define a single channel to monitor
+  *         with analog watchdog from sequencer channel definition,
+  *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().
+  * @note   On this STM32 series, there is only 1 kind of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC group regular.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR1    AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR1    AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n
+  *         CFGR1    AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n
+  *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n
+  *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDChannelGroup This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
+  *         @arg @ref LL_ADC_AWD_CH_VDDA_REG
+  *         @arg @ref LL_ADC_AWD_CH_VSSA_REG
+  *         (1) On STM32C0, parameter not available on all devices: only on STM32C031xx.
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)
+{
+  /* Set bits with content of parameter "AWDChannelGroup" with bits position  */
+  /* in register and register position depending on parameter "AWDy".         */
+  /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */
+  /* containing other bits reserved for other purpose.                        */
+  register __IO uint32_t *preg;
+
+  if (AWDy == LL_ADC_AWD1)
+  {
+    preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);
+  }
+  else
+  {
+    preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR,
+                                ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL));
+  }
+
+  MODIFY_REG(*preg,
+             (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),
+             AWDChannelGroup & AWDy);
+}
+
+/**
+  * @brief  Get ADC analog watchdog monitored channel.
+  * @note   Usage of the returned channel number:
+  *         - To reinject this channel into another function LL_ADC_xxx:
+  *           the returned channel number is only partly formatted on definition
+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared
+  *           with parts of literals LL_ADC_CHANNEL_x or using
+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Then the selected literal LL_ADC_CHANNEL_x can be used
+  *           as parameter for another function.
+  *         - To get the channel number in decimal format:
+  *           process the returned value with the helper macro
+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().
+  *           Applicable only when the analog watchdog is set to monitor
+  *           one channel.
+  * @note   On this STM32 series, there is only 1 kind of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC group regular.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CFGR1    AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR1    AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n
+  *         CFGR1    AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n
+  *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n
+  *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2 (1)
+  *         @arg @ref LL_ADC_AWD3 (1)
+  *
+  *         (1) On this AWD number, monitored channel can be retrieved
+  *             if only 1 channel is programmed (or none or all channels).
+  *             This function cannot retrieve monitored channel if
+  *             multiple channels are programmed simultaneously
+  *             by bitfield.
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_DISABLE
+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG
+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_20_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_21_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CHANNEL_22_REG          (1)
+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG
+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG
+  *         @arg @ref LL_ADC_AWD_CH_VDDA_REG
+  *         @arg @ref LL_ADC_AWD_CH_VSSA_REG
+  *         (1) On STM32C0, parameter not available on all devices: only on STM32C031xx.
+  */__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy)
+{
+  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1,
+                                                      ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)
+                                                      + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK)
+                                                         * ADC_AWD_CR12_REGOFFSETGAP_VAL));
+
+  register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);
+
+  /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */
+  /* (parameter value LL_ADC_AWD_DISABLE).                                    */
+  /* Else, the selected AWD is enabled and is monitoring a group of channels  */
+  /* or a single channel.                                                     */
+  if (AnalogWDMonitChannels != 0UL)
+  {
+    if (AWDy == LL_ADC_AWD1)
+    {
+      if ((AnalogWDMonitChannels & ADC_CFGR1_AWD1SGL) == 0UL)
+      {
+        /* AWD monitoring a group of channels */
+        AnalogWDMonitChannels = ((AnalogWDMonitChannels
+                                  | (ADC_AWD_CR23_CHANNEL_MASK)
+                                 )
+                                 & (~(ADC_CFGR1_AWD1CH))
+                                );
+      }
+      else
+      {
+        /* AWD monitoring a single channel */
+        AnalogWDMonitChannels = (AnalogWDMonitChannels
+                                 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR1_AWD1CH_Pos))
+                                );
+      }
+    }
+    else
+    {
+      if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)
+      {
+        /* AWD monitoring a group of channels */
+        AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK
+                                 | (ADC_CFGR1_AWD1EN)
+                                );
+      }
+      else
+      {
+        /* AWD monitoring a single channel */
+        /* AWD monitoring a group of channels */
+        AnalogWDMonitChannels = (AnalogWDMonitChannels
+                                 | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL)
+                                 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR1_AWD1CH_Pos)
+                                );
+      }
+    }
+  }
+
+  return AnalogWDMonitChannels;
+}
+/**
+  * @brief  Set ADC analog watchdog thresholds value of both thresholds
+  *         high and low.
+  * @note   If value of only one threshold high or low must be set,
+  *         use function @ref LL_ADC_SetAnalogWDThresholds().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @note   On this STM32 series, there is only 2 kind of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC group regular.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
+  *         impacted: the comparison of analog watchdog thresholds is done on
+  *         oversampling final computation (after ratio and shift application):
+  *         ADC data register bitfield [15:4] (12 most significant bits).
+  *         Examples:
+  *         - Oversampling ratio and shift selected to have ADC conversion data
+  *           on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
+  *           ADC analog watchdog thresholds must be divided by 16.
+  *         - Oversampling ratio and shift selected to have ADC conversion data
+  *           on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
+  *           ADC analog watchdog thresholds must be divided by 4.
+  *         - Oversampling ratio and shift selected to have ADC conversion data
+  *           on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
+  *           ADC analog watchdog thresholds match directly to ADC data register.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled or enabled without conversion on going
+  *         on group regular.
+  * @rmtoll AWD1TR   HT1            LL_ADC_ConfigAnalogWDThresholds\n
+  *         AWD2TR   HT2            LL_ADC_ConfigAnalogWDThresholds\n
+  *         AWD3TR   HT3            LL_ADC_ConfigAnalogWDThresholds\n
+  *         AWD1TR   LT1            LL_ADC_ConfigAnalogWDThresholds\n
+  *         AWD2TR   LT2            LL_ADC_ConfigAnalogWDThresholds\n
+  *         AWD3TR   LT3            LL_ADC_ConfigAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @param  AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue,
+                                                     uint32_t AWDThresholdLowValue)
+{
+  /* Set bits with content of parameter "AWDThresholdxxxValue" with bits      */
+  /* position in register and register position depending on parameter        */
+  /* "AWDy".                                                                  */
+  /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */
+  /* containing other bits reserved for other purpose.                        */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
+                                             (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
+                                              >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
+                                             + ((ADC_AWD_CR3_REGOFFSET & AWDy)
+                                                >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))
+                                            );
+
+  MODIFY_REG(*preg,
+             ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1,
+             (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue);
+}
+/**
+  * @brief  Set ADC analog watchdog threshold value of threshold
+  *         high or low.
+  * @note   If values of both thresholds high or low must be set,
+  *         use function @ref LL_ADC_ConfigAnalogWDThresholds().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().
+  * @note   On this STM32 series, there is only 2 kinds of analog watchdog
+  *         instance:
+  *         - AWD standard (instance AWD1):
+  *           - channels monitored: can monitor 1 channel or all channels.
+  *           - groups monitored: ADC group regular.
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  *         - AWD flexible (instances AWD2, AWD3):
+  *           - channels monitored: flexible on channels monitored, selection is
+  *             channel wise, from from 1 to all channels.
+  *             Specificity of this analog watchdog: Multiple channels can
+  *             be selected. For example:
+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)
+  *           - groups monitored: not selection possible (monitoring on both
+  *             groups regular and injected).
+  *             Channels selected are monitored on groups regular and injected:
+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters
+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)
+  *           - resolution: resolution is not limited (corresponds to
+  *             ADC resolution configured).
+  * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are
+  *         impacted: the comparison of analog watchdog thresholds is done on
+  *         oversampling final computation (after ratio and shift application):
+  *         ADC data register bitfield [15:4] (12 most significant bits).
+  *         Examples:
+  *         - Oversampling ratio and shift selected to have ADC conversion data
+  *           on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...):
+  *           ADC analog watchdog thresholds must be divided by 16.
+  *         - Oversampling ratio and shift selected to have ADC conversion data
+  *           on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...):
+  *           ADC analog watchdog thresholds must be divided by 4.
+  *         - Oversampling ratio and shift selected to have ADC conversion data
+  *           on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...):
+  *           ADC analog watchdog thresholds match directly to ADC data register.
+  * @note   On this STM32 series, setting of this feature is not conditioned to
+  *         ADC state:
+  *         ADC can be disabled, enabled with or without conversion on going
+  *         on ADC group regular.
+  * @rmtoll AWD1TR   HT1            LL_ADC_SetAnalogWDThresholds\n
+  *         AWD2TR   HT2            LL_ADC_SetAnalogWDThresholds\n
+  *         AWD3TR   HT3            LL_ADC_SetAnalogWDThresholds\n
+  *         AWD1TR   LT1            LL_ADC_SetAnalogWDThresholds\n
+  *         AWD2TR   LT2            LL_ADC_SetAnalogWDThresholds\n
+  *         AWD3TR   LT3            LL_ADC_SetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,
+                                                  uint32_t AWDThresholdValue)
+{
+  /* Set bits with content of parameter "AWDThresholdValue" with bits         */
+  /* position in register and register position depending on parameters       */
+  /* "AWDThresholdsHighLow" and "AWDy".                                       */
+  /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
+  /* containing other bits reserved for other purpose.                        */
+  __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
+                                             (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
+                                              >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
+                                             + ((ADC_AWD_CR3_REGOFFSET & AWDy)
+                                                >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
+
+  MODIFY_REG(*preg,
+             AWDThresholdsHighLow,
+             AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4));
+}
+
+/**
+  * @brief  Get ADC analog watchdog threshold value of threshold high,
+  *         threshold low or raw data with ADC thresholds high and low
+  *         concatenated.
+  * @note   If raw data with ADC thresholds high and low is retrieved,
+  *         the data of each threshold high or low can be isolated
+  *         using helper macro:
+  *         @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW().
+  * @note   In case of ADC resolution different of 12 bits,
+  *         analog watchdog thresholds data require a specific shift.
+  *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().
+  * @rmtoll AWD1TR   HT1            LL_ADC_GetAnalogWDThresholds\n
+  *         AWD2TR   HT2            LL_ADC_GetAnalogWDThresholds\n
+  *         AWD3TR   HT3            LL_ADC_GetAnalogWDThresholds\n
+  *         AWD1TR   LT1            LL_ADC_GetAnalogWDThresholds\n
+  *         AWD2TR   LT2            LL_ADC_GetAnalogWDThresholds\n
+  *         AWD3TR   LT3            LL_ADC_GetAnalogWDThresholds
+  * @param  ADCx ADC instance
+  * @param  AWDy This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD1
+  *         @arg @ref LL_ADC_AWD2
+  *         @arg @ref LL_ADC_AWD3
+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH
+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW
+  *         @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)
+{
+  /* Set bits with content of parameter "AWDThresholdValue" with bits         */
+  /* position in register and register position depending on parameters       */
+  /* "AWDThresholdsHighLow" and "AWDy".                                       */
+  /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */
+  /* containing other bits reserved for other purpose.                        */
+  const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR,
+                                                   (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK))
+                                                    >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS))
+                                                   + ((ADC_AWD_CR3_REGOFFSET & AWDy)
+                                                      >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)));
+
+  return (uint32_t)(READ_BIT(*preg,
+                             (AWDThresholdsHighLow | ADC_AWD1TR_LT1))
+                    >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~
+                        (AWDThresholdsHighLow & ADC_AWD1TR_LT1))
+                   );
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling
+  * @{
+  */
+
+/**
+  * @brief  Set ADC oversampling scope.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR2    OVSE           LL_ADC_SetOverSamplingScope
+  * @param  ADCx ADC instance
+  * @param  OvsScope This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_DISABLE
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope);
+}
+
+/**
+  * @brief  Get ADC oversampling scope.
+  * @rmtoll CFGR2    OVSE           LL_ADC_GetOverSamplingScope
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_DISABLE
+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE));
+}
+
+/**
+  * @brief  Set ADC oversampling discontinuous mode (triggered mode)
+  *         on the selected ADC group.
+  * @note   Number of oversampled conversions are done either in:
+  *         - continuous mode (all conversions of oversampling ratio
+  *           are done from 1 trigger)
+  *         - discontinuous mode (each conversion of oversampling ratio
+  *           needs a trigger)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR2    TOVS           LL_ADC_SetOverSamplingDiscont
+  * @param  ADCx ADC instance
+  * @param  OverSamplingDiscont This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_REG_CONT
+  *         @arg @ref LL_ADC_OVS_REG_DISCONT
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)
+{
+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont);
+}
+
+/**
+  * @brief  Get ADC oversampling discontinuous mode (triggered mode)
+  *         on the selected ADC group.
+  * @note   Number of oversampled conversions are done either in:
+  *         - continuous mode (all conversions of oversampling ratio
+  *           are done from 1 trigger)
+  *         - discontinuous mode (each conversion of oversampling ratio
+  *           needs a trigger)
+  * @rmtoll CFGR2    TOVS           LL_ADC_GetOverSamplingDiscont
+  * @param  ADCx ADC instance
+  * @retval Returned value can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_REG_CONT
+  *         @arg @ref LL_ADC_OVS_REG_DISCONT
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS));
+}
+
+/**
+  * @brief  Set ADC oversampling
+  * @note   This function set the 2 items of oversampling configuration:
+  *         - ratio
+  *         - shift
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be disabled.
+  * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n
+  *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift
+  * @param  ADCx ADC instance
+  * @param  Ratio This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_RATIO_2
+  *         @arg @ref LL_ADC_OVS_RATIO_4
+  *         @arg @ref LL_ADC_OVS_RATIO_8
+  *         @arg @ref LL_ADC_OVS_RATIO_16
+  *         @arg @ref LL_ADC_OVS_RATIO_32
+  *         @arg @ref LL_ADC_OVS_RATIO_64
+  *         @arg @ref LL_ADC_OVS_RATIO_128
+  *         @arg @ref LL_ADC_OVS_RATIO_256
+  * @param  Shift This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)
+{
+  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio));
+}
+
+/**
+  * @brief  Get ADC oversampling ratio
+  * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio
+  * @param  ADCx ADC instance
+  * @retval Ratio This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_RATIO_2
+  *         @arg @ref LL_ADC_OVS_RATIO_4
+  *         @arg @ref LL_ADC_OVS_RATIO_8
+  *         @arg @ref LL_ADC_OVS_RATIO_16
+  *         @arg @ref LL_ADC_OVS_RATIO_32
+  *         @arg @ref LL_ADC_OVS_RATIO_64
+  *         @arg @ref LL_ADC_OVS_RATIO_128
+  *         @arg @ref LL_ADC_OVS_RATIO_256
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR));
+}
+
+/**
+  * @brief  Get ADC oversampling shift
+  * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift
+  * @param  ADCx ADC instance
+  * @retval Shift This parameter can be one of the following values:
+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7
+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8
+  */
+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC instance internal voltage regulator.
+  * @note   On this STM32 series, there are three possibilities to enable
+  *         the voltage regulator:
+  *         - by enabling it manually
+  *           using function @ref LL_ADC_EnableInternalRegulator().
+  *         - by launching a calibration
+  *           using function @ref LL_ADC_StartCalibration().
+  *         - by enabling the ADC
+  *           using function @ref LL_ADC_Enable().
+  * @note   On this STM32 series, after ADC internal voltage regulator enable,
+  *         a delay for ADC internal voltage regulator stabilization
+  *         is required before performing a ADC calibration or ADC enable.
+  *         Refer to device datasheet, parameter "tADCVREG_STUP".
+  *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADVREGEN);
+}
+
+/**
+  * @brief  Disable ADC internal voltage regulator.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));
+}
+
+/**
+  * @brief  Get the selected ADC instance internal voltage regulator state.
+  * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Enable the selected ADC instance.
+  * @note   On this STM32 series, after ADC enable, a delay for
+  *         ADC internal analog stabilization is required before performing a
+  *         ADC conversion start.
+  *         Refer to device datasheet, parameter tSTAB.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled and ADC internal voltage regulator enabled.
+  * @rmtoll CR       ADEN           LL_ADC_Enable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADEN);
+}
+
+/**
+  * @brief  Disable the selected ADC instance.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be not disabled. Must be enabled without conversion on going
+  *         on group regular.
+  * @rmtoll CR       ADDIS          LL_ADC_Disable
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADDIS);
+}
+
+/**
+  * @brief  Get the selected ADC instance enable state.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll CR       ADEN           LL_ADC_IsEnabled
+  * @param  ADCx ADC instance
+  * @retval 0: ADC is disabled, 1: ADC is enabled.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get the selected ADC instance disable state.
+  * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no ADC disable command on going.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Start ADC calibration in the mode single-ended
+  *         or differential (for devices with differential mode available).
+  * @note   On this STM32 series, a minimum number of ADC clock cycles
+  *         are required between ADC end of calibration and ADC enable.
+  *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.
+  * @note   In case of usage of ADC with DMA transfer:
+  *         On this STM32 series, ADC DMA transfer request should be disabled
+  *         during calibration:
+  *         Calibration factor is available in data register
+  *         and also transferred by DMA.
+  *         To not insert ADC calibration factor among ADC conversion data
+  *         in array variable, DMA transfer must be disabled during
+  *         calibration.
+  *         (DMA transfer setting backup and disable before calibration,
+  *         DMA transfer setting restore after calibration.
+  *         Refer to functions @ref LL_ADC_REG_GetDMATransfer(),
+  *         @ref LL_ADC_REG_SetDMATransfer() ).
+  * @note   In case of usage of feature auto power-off:
+  *         This mode must be disabled during calibration
+  *         Refer to function @ref LL_ADC_SetLowPowerMode().
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be ADC disabled.
+  * @rmtoll CR       ADCAL          LL_ADC_StartCalibration
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADCAL);
+}
+
+/**
+  * @brief  Get ADC calibration state.
+  * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing
+  * @param  ADCx ADC instance
+  * @retval 0: calibration complete, 1: calibration in progress.
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular
+  * @{
+  */
+
+/**
+  * @brief  Start ADC group regular conversion.
+  * @note   On this STM32 series, this function is relevant for both
+  *         internal trigger (SW start) and external trigger:
+  *         - If ADC trigger has been set to software start, ADC conversion
+  *           starts immediately.
+  *         - If ADC trigger has been set to external trigger, ADC conversion
+  *           will start at next trigger event (on the selected trigger edge)
+  *           following the ADC start conversion command.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled without conversion on going on group regular,
+  *         without conversion stop command on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADSTART);
+}
+
+/**
+  * @brief  Stop ADC group regular conversion.
+  * @note   On this STM32 series, setting of this feature is conditioned to
+  *         ADC state:
+  *         ADC must be enabled with conversion on going on group regular,
+  *         without ADC disable command on going.
+  * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)
+{
+  /* Note: Write register with some additional bits forced to state reset     */
+  /*       instead of modifying only the selected bit for this function,      */
+  /*       to not interfere with bits with HW property "rs".                  */
+  MODIFY_REG(ADCx->CR,
+             ADC_CR_BITS_PROPERTY_RS,
+             ADC_CR_ADSTP);
+}
+
+/**
+  * @brief  Get ADC group regular conversion state.
+  * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no conversion is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get ADC group regular command of conversion stop state
+  * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing
+  * @param  ADCx ADC instance
+  * @retval 0: no command of conversion stop is on going on ADC group regular.
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         all ADC configurations: all ADC resolutions and
+  *         all oversampling increased data width (for devices
+  *         with feature oversampling).
+  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData32
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF
+  */
+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx)
+{
+  return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 12 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData12
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 10 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData10
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF
+  */
+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx)
+{
+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 8 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData8
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @brief  Get ADC group regular conversion data, range fit for
+  *         ADC resolution 6 bits.
+  * @note   For devices with feature oversampling: Oversampling
+  *         can increase data width, function for extended range
+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.
+  * @rmtoll DR       DATA           LL_ADC_REG_ReadConversionData6
+  * @param  ADCx ADC instance
+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F
+  */
+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx)
+{
+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management
+  * @{
+  */
+
+/**
+  * @brief  Get flag ADC ready.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC channel configuration ready.
+  * @note   On this STM32 series, after modifying sequencer
+  *         it is mandatory to wait for the assertion of CCRDY flag
+  *         using @ref LL_ADC_IsActiveFlag_CCRDY().
+  *         Otherwise, performing some actions (configuration update,
+  *         ADC conversion start, ... ) will be ignored.
+  *         Functions requiring wait for CCRDY flag are:
+  *         @ref LL_ADC_REG_SetSequencerLength()
+  *         @ref LL_ADC_REG_SetSequencerRanks()
+  *         @ref LL_ADC_REG_SetSequencerChannels()
+  *         @ref LL_ADC_REG_SetSequencerChAdd()
+  *         @ref LL_ADC_REG_SetSequencerChRem()
+  *         @ref LL_ADC_REG_SetSequencerScanDirection()
+  *         @ref LL_ADC_REG_SetSequencerConfigurable()
+  * @note   Duration of ADC channel configuration ready: CCRDY handshake
+  *         requires 1APB + 2 ADC + 3 APB cycles after the channel configuration
+  *         has been changed.
+  * @rmtoll ISR      CCRDY          LL_ADC_IsActiveFlag_CCRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular end of unitary conversion.
+  * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular end of sequence conversions.
+  * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular overrun.
+  * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC group regular end of sampling phase.
+  * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 1 flag
+  * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 2.
+  * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC analog watchdog 3.
+  * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get flag ADC end of calibration.
+  * @rmtoll ISR      EOCAL          LL_ADC_IsActiveFlag_EOCAL
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Clear flag ADC ready.
+  * @note   On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC
+  *         is enabled and when conversion clock is active.
+  *         (not only core clock: this ADC has a dual clock domain)
+  * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);
+}
+
+/**
+  * @brief  Clear flag ADC channel configuration ready.
+  * @rmtoll ISR      CCRDY          LL_ADC_ClearFlag_CCRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of unitary conversion.
+  * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of sequence conversions.
+  * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);
+}
+
+/**
+  * @brief  Clear flag ADC group regular overrun.
+  * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);
+}
+
+/**
+  * @brief  Clear flag ADC group regular end of sampling phase.
+  * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 1.
+  * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 2.
+  * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);
+}
+
+/**
+  * @brief  Clear flag ADC analog watchdog 3.
+  * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);
+}
+
+/**
+  * @brief  Clear flag ADC end of calibration.
+  * @rmtoll ISR      EOCAL          LL_ADC_ClearFlag_EOCAL
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx)
+{
+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_LL_EF_IT_Management ADC IT management
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+  * @brief  Enable interruption ADC channel configuration ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_CCRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of sequence conversions.
+  * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+  * @brief  Enable ADC group regular interruption overrun.
+  * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+  * @brief  Enable interruption ADC group regular end of sampling.
+  * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 1.
+  * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 2.
+  * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+  * @brief  Enable interruption ADC analog watchdog 3.
+  * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+/**
+  * @brief  Enable interruption ADC end of calibration.
+  * @rmtoll IER      EOCALIE        LL_ADC_EnableIT_EOCAL
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx)
+{
+  SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
+}
+
+/**
+  * @brief  Disable interruption ADC ready.
+  * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);
+}
+
+/**
+  * @brief  Disable interruption ADC channel configuration ready.
+  * @rmtoll IER      CCRDYIE        LL_ADC_DisableIT_CCRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of unitary conversion.
+  * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of sequence conversions.
+  * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular overrun.
+  * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);
+}
+
+/**
+  * @brief  Disable interruption ADC group regular end of sampling.
+  * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 1.
+  * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 2.
+  * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);
+}
+
+/**
+  * @brief  Disable interruption ADC analog watchdog 3.
+  * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);
+}
+
+/**
+  * @brief  Disable interruption ADC end of calibration.
+  * @rmtoll IER      EOCALIE        LL_ADC_DisableIT_EOCAL
+  * @param  ADCx ADC instance
+  * @retval None
+  */
+__STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx)
+{
+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL);
+}
+
+/**
+  * @brief  Get state of interruption ADC ready
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC channel configuration ready.
+  * @rmtoll IER      CCRDYIE        LL_ADC_IsEnabledIT_CCRDY
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of unitary conversion
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of sequence conversions
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular overrun
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC group regular end of sampling
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC analog watchdog 1
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption Get ADC analog watchdog 2
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption Get ADC analog watchdog 3
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);
+}
+
+/**
+  * @brief  Get state of interruption ADC end of calibration
+  *         (0: interrupt disabled, 1: interrupt enabled).
+  * @rmtoll IER      EOCALIE        LL_ADC_IsEnabledIT_EOCAL
+  * @param  ADCx ADC instance
+  * @retval State of bit (1 or 0).
+  */
+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx)
+{
+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL);
+}
+
+/**
+  * @}
+  */
+
+#if defined(USE_FULL_LL_DRIVER)
+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions
+  * @{
+  */
+
+/* Initialization of some features of ADC common parameters and multimode */
+ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON);
+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);
+
+/* De-initialization of ADC instance */
+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);
+/* Initialization of some features of ADC instance */
+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *ADC_InitStruct);
+void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);
+
+/* Initialization of some features of ADC instance and ADC group regular */
+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);
+
+/**
+  * @}
+  */
+#endif /* USE_FULL_LL_DRIVER */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* ADC1 */
+
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STM32C0xx_LL_ADC_H */
diff --git a/code/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c b/code/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c
new file mode 100644
index 0000000..c3c83e0
--- /dev/null
+++ b/code/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c
@@ -0,0 +1,3066 @@
+/**
+  ******************************************************************************
+  * @file    stm32c0xx_hal_adc.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Analog to Digital Converter (ADC)
+  *          peripheral:
+  *           + Initialization and de-initialization functions
+  *             ++ Initialization and Configuration of ADC
+  *           + Operation functions
+  *             ++ Start, stop, get result of conversions of regular
+  *                group, using 3 possible modes: polling, interruption or DMA.
+  *           + Control functions
+  *             ++ Channels configuration on regular group
+  *             ++ Analog Watchdog configuration
+  *           + State functions
+  *             ++ ADC state machine management
+  *             ++ Interrupts and flags management
+  *          Other functions (extended functions) are available in file
+  *          "stm32c0xx_hal_adc_ex.c".
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  ==============================================================================
+                     ##### ADC peripheral features #####
+  ==============================================================================
+  [..]
+  (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
+
+  (+) Interrupt generation at the end of regular conversion and in case of
+      analog watchdog or overrun events.
+
+  (+) Single and continuous conversion modes.
+
+  (+) Scan mode for conversion of several channels sequentially.
+
+  (+) Data alignment with in-built data coherency.
+
+  (+) Programmable sampling time (common to group of channels)
+
+  (+) External trigger (timer or EXTI) with configurable polarity
+
+  (+) DMA request generation for transfer of conversions data of regular group.
+
+  (+) ADC calibration
+
+  (+) ADC conversion of regular group.
+
+  (+) ADC supply requirements: 1.62 V to 3.6 V.
+
+  (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
+      Vdda or to an external voltage reference).
+
+
+                     ##### How to use this driver #####
+  ==============================================================================
+    [..]
+
+     *** Configuration of top level parameters related to ADC ***
+     ============================================================
+     [..]
+
+    (#) Enable the ADC interface
+        (++) As prerequisite, ADC clock must be configured at RCC top level.
+             Caution: On STM32C0, ADC clock frequency max is 35MHz (refer
+                      to device datasheet).
+                      Therefore, ADC clock source from RCC and ADC clock
+                      prescaler must be configured to remain below
+                      this maximum frequency.
+
+        (++) Two clock settings are mandatory:
+             (+++) ADC clock (core clock, also possibly conversion clock).
+
+             (+++) ADC clock (conversions clock).
+                   Four possible clock sources: synchronous clock from APB clock (same as ADC core clock)
+                   or asynchronous clock from RCC level: SYSCLK, HSI48.
+
+             (+++) Example:
+                   Into HAL_ADC_MspInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) __HAL_RCC_ADC_CLK_ENABLE();                  (mandatory: core clock)
+
+        (++) ADC clock source and clock prescaler are configured at ADC level with
+             parameter "ClockPrescaler" using function HAL_ADC_Init().
+
+    (#) ADC pins configuration
+         (++) Enable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_ENABLE()
+         (++) Configure these ADC pins in analog mode
+              using function HAL_GPIO_Init()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Configure the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+              into the function of corresponding ADC interruption vector
+              ADCx_IRQHandler().
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Configure the DMA (DMA channel, mode normal or circular, ...)
+              using function HAL_DMA_Init().
+         (++) Configure the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+         (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
+              into the function of corresponding DMA interruption vector
+              DMAx_Channelx_IRQHandler().
+
+     *** Configuration of ADC, group regular, channels parameters ***
+     ================================================================
+     [..]
+
+    (#) Configure the ADC parameters (resolution, data alignment, ...)
+        and regular group parameters (conversion trigger, sequencer, ...)
+        using function HAL_ADC_Init().
+
+    (#) Configure the channels for regular group parameters (channel number,
+        channel rank into sequencer, ..., into regular group)
+        using function HAL_ADC_ConfigChannel().
+
+    (#) Optionally, configure the analog watchdog parameters (channels
+        monitored, thresholds, ...)
+        using function HAL_ADC_AnalogWDGConfig().
+
+     *** Execution of ADC conversions ***
+     ====================================
+     [..]
+
+    (#) Optionally, perform an automatic ADC calibration to improve the
+        conversion accuracy
+        using function HAL_ADCEx_Calibration_Start().
+
+    (#) ADC driver can be used among three modes: polling, interruption,
+        transfer by DMA.
+
+        (++) ADC conversion by polling:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start()
+          (+++) Wait for ADC conversion completion
+                using function HAL_ADC_PollForConversion()
+          (+++) Retrieve conversion results
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral
+                using function HAL_ADC_Stop()
+
+        (++) ADC conversion by interruption:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_IT()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback()
+                (this function must be implemented in user program)
+          (+++) Retrieve conversion results
+                using function HAL_ADC_GetValue()
+          (+++) Stop conversion and disable the ADC peripheral
+                using function HAL_ADC_Stop_IT()
+
+        (++) ADC conversion with transfer by DMA:
+          (+++) Activate the ADC peripheral and start conversions
+                using function HAL_ADC_Start_DMA()
+          (+++) Wait for ADC conversion completion by call of function
+                HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
+                (these functions must be implemented in user program)
+          (+++) Conversion results are automatically transferred by DMA into
+                destination variable address.
+          (+++) Stop conversion and disable the ADC peripheral
+                using function HAL_ADC_Stop_DMA()
+
+     [..]
+
+    (@) Callback functions must be implemented in user program:
+      (+@) HAL_ADC_ErrorCallback()
+      (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
+      (+@) HAL_ADC_ConvCpltCallback()
+      (+@) HAL_ADC_ConvHalfCpltCallback
+
+     *** Deinitialization of ADC ***
+     ============================================================
+     [..]
+
+    (#) Disable the ADC interface
+      (++) ADC clock can be hard reset and disabled at RCC top level.
+        (++) Hard reset of ADC peripherals
+             using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
+        (++) ADC clock disable
+             using the equivalent macro/functions as configuration step.
+             (+++) Example:
+                   Into HAL_ADC_MspDeInit() (recommended code location) or with
+                   other device clock parameters configuration:
+               (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
+               (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
+               (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
+
+    (#) ADC pins configuration
+         (++) Disable the clock for the ADC GPIOs
+              using macro __HAL_RCC_GPIOx_CLK_DISABLE()
+
+    (#) Optionally, in case of usage of ADC with interruptions:
+         (++) Disable the NVIC for ADC
+              using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
+
+    (#) Optionally, in case of usage of DMA:
+         (++) Deinitialize the DMA
+              using function HAL_DMA_Init().
+         (++) Disable the NVIC for DMA
+              using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
+
+    [..]
+
+    *** Callback registration ***
+    =============================================
+    [..]
+
+     The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
+     allows the user to configure dynamically the driver callbacks.
+     Use Functions @ref HAL_ADC_RegisterCallback()
+     to register an interrupt callback.
+    [..]
+
+     Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+       (+) EndOfSamplingCallback          : ADC end of sampling callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     This function takes as parameters the HAL peripheral handle, the Callback ID
+     and a pointer to the user callback function.
+    [..]
+
+     Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
+     weak function.
+    [..]
+
+     @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
+     and the Callback ID.
+     This function allows to reset following callbacks:
+       (+) ConvCpltCallback               : ADC conversion complete callback
+       (+) ConvHalfCpltCallback           : ADC conversion DMA half-transfer callback
+       (+) LevelOutOfWindowCallback       : ADC analog watchdog 1 callback
+       (+) ErrorCallback                  : ADC error callback
+       (+) LevelOutOfWindow2Callback      : ADC analog watchdog 2 callback
+       (+) LevelOutOfWindow3Callback      : ADC analog watchdog 3 callback
+       (+) EndOfSamplingCallback          : ADC end of sampling callback
+       (+) MspInitCallback                : ADC Msp Init callback
+       (+) MspDeInitCallback              : ADC Msp DeInit callback
+     [..]
+
+     By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
+     all callbacks are set to the corresponding weak functions:
+     examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
+     Exception done for MspInit and MspDeInit functions that are
+     reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
+     these callbacks are null (not registered beforehand).
+    [..]
+
+     If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
+     keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
+     [..]
+
+     Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
+     Exception done MspInit/MspDeInit functions that can be registered/unregistered
+     in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
+     thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+    [..]
+
+     Then, the user first registers the MspInit/MspDeInit user callbacks
+     using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
+     or @ref HAL_ADC_Init() function.
+     [..]
+
+     When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
+     not defined, the callback registration feature is not available and all callbacks
+     are set to the corresponding weak functions.
+
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADC ADC
+  * @brief ADC HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Constants ADC Private Constants
+  * @{
+  */
+
+/* Fixed timeout values for ADC calibration, enable settling time, disable  */
+/* settling time.                                                           */
+/* Values defined to be higher than worst cases: low clock frequency,       */
+/* maximum prescaler.                                                       */
+/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
+/* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits.     */
+/* Unit: ms                                                                 */
+#define ADC_ENABLE_TIMEOUT              (2UL)
+#define ADC_DISABLE_TIMEOUT             (2UL)
+#define ADC_STOP_CONVERSION_TIMEOUT     (2UL)
+#define ADC_CHANNEL_CONF_RDY_TIMEOUT    (1UL)
+
+/* Register CHSELR bits corresponding to ranks 2 to 8 .                     */
+#define ADC_CHSELR_SQ2_TO_SQ8           (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | \
+                                         ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8)
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @defgroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
+static void ADC_DMAError(DMA_HandleTypeDef *hdma);
+/**
+  * @}
+  */
+
+/* Exported functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Functions ADC Exported Functions
+  * @{
+  */
+
+/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
+  * @brief    ADC Initialization and Configuration functions
+  *
+@verbatim
+ ===============================================================================
+              ##### Initialization and de-initialization functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Initialize and configure the ADC.
+      (+) De-initialize the ADC.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initialize the ADC peripheral and regular group according to
+  *         parameters specified in structure "ADC_InitTypeDef".
+  * @note   As prerequisite, ADC clock must be configured at RCC top level
+  *         (refer to description of RCC configuration for ADC
+  *         in header of this file).
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
+  *         coming from ADC state reset. Following calls to this function can
+  *         be used to reconfigure some parameters of ADC_InitTypeDef
+  *         structure on the fly, without modifying MSP configuration. If ADC
+  *         MSP has to be modified again, HAL_ADC_DeInit() must be called
+  *         before HAL_ADC_Init().
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure
+  *         "ADC_InitTypeDef".
+  * @note   This function configures the ADC within 2 scopes: scope of entire
+  *         ADC and scope of regular group. For parameters details, see comments
+  *         of structure "ADC_InitTypeDef".
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmpCFGR1 = 0UL;
+  uint32_t tmpCFGR2 = 0UL;
+  uint32_t tmp_adc_reg_is_conversion_on_going;
+  __IO uint32_t wait_loop_index = 0UL;
+
+  /* Check ADC handle */
+  if (hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
+  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
+  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
+  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
+  assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
+  assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+  assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff));
+  assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1));
+  assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2));
+  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
+
+  assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode));
+
+  if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
+  {
+    assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
+
+    if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+    {
+      assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+    }
+  }
+
+  /* ADC group regular discontinuous mode can be enabled only if              */
+  /* continuous mode is disabled.                                             */
+  assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
+
+  /* Actions performed only if ADC is coming from state reset:                */
+  /* - Initialization of ADC MSP                                              */
+  if (hadc->State == HAL_ADC_STATE_RESET)
+  {
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    /* Init the ADC Callback settings */
+    hadc->ConvCpltCallback              = HAL_ADC_ConvCpltCallback;                 /* Legacy weak callback */
+    hadc->ConvHalfCpltCallback          = HAL_ADC_ConvHalfCpltCallback;             /* Legacy weak callback */
+    hadc->LevelOutOfWindowCallback      = HAL_ADC_LevelOutOfWindowCallback;         /* Legacy weak callback */
+    hadc->ErrorCallback                 = HAL_ADC_ErrorCallback;                    /* Legacy weak callback */
+    hadc->LevelOutOfWindow2Callback     = HAL_ADCEx_LevelOutOfWindow2Callback;      /* Legacy weak callback */
+    hadc->LevelOutOfWindow3Callback     = HAL_ADCEx_LevelOutOfWindow3Callback;      /* Legacy weak callback */
+    hadc->EndOfSamplingCallback         = HAL_ADCEx_EndOfSamplingCallback;          /* Legacy weak callback */
+    hadc->CalibrationCpltCallback       = HAL_ADC_CalibrationCpltCallback;          /* Legacy weak callback */
+    hadc->ADCReadyCallback              = HAL_ADC_ADCReadyCallback;                 /* Legacy weak callback */
+    hadc->ChannelConfigReadyCallback    = HAL_ADCEx_ChannelConfigReadyCallback;     /* Legacy weak callback */
+
+    if (hadc->MspInitCallback == NULL)
+    {
+      hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit  */
+    }
+
+    /* Init the low level hardware */
+    hadc->MspInitCallback(hadc);
+#else
+    /* Init the low level hardware */
+    HAL_ADC_MspInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Set ADC error code to none */
+    ADC_CLEAR_ERRORCODE(hadc);
+
+    /* Initialize Lock */
+    hadc->Lock = HAL_UNLOCKED;
+  }
+
+  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+  {
+    /* Enable ADC internal voltage regulator */
+    LL_ADC_EnableInternalRegulator(hadc->Instance);
+
+    /* Delay for ADC stabilization time */
+    /* Wait loop initialization and execution */
+    /* Note: Variable divided by 2 to compensate partially              */
+    /*       CPU processing cycles, scaling in us split to not          */
+    /*       exceed 32 bits register capacity and handle low frequency. */
+    wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL)));
+    while (wait_loop_index != 0UL)
+    {
+      wait_loop_index--;
+    }
+  }
+
+  /* Verification that ADC voltage regulator is correctly enabled, whether    */
+  /* or not ADC is coming from state reset (if any potential problem of       */
+  /* clocking, voltage regulator would not be enabled).                       */
+  if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    /* Set ADC error code to ADC peripheral internal error */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Configuration of ADC parameters if previous preliminary actions are      */
+  /* correctly completed and if there is no conversion on going on regular    */
+  /* group (ADC may already be enabled at this point if HAL_ADC_Init() is     */
+  /* called to update a parameter on the fly).                                */
+  tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+
+  if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+      && (tmp_adc_reg_is_conversion_on_going == 0UL)
+     )
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+
+    /* Configuration of common ADC parameters                                 */
+
+    /* Parameters update conditioned to ADC state:                            */
+    /* Parameters that can be updated only when ADC is disabled:              */
+    /*  - Internal voltage regulator (no parameter in HAL ADC init structure) */
+    /*  - Clock configuration                                                 */
+    /*  - ADC resolution                                                      */
+    /*  - Oversampling                                                        */
+    /*  - discontinuous mode                                                  */
+    /*  - LowPowerAutoWait mode                                               */
+    /*  - LowPowerAutoPowerOff mode                                           */
+    /*  - continuous conversion mode                                          */
+    /*  - overrun                                                             */
+    /*  - external trigger to start conversion                                */
+    /*  - external trigger polarity                                           */
+    /*  - data alignment                                                      */
+    /*  - resolution                                                          */
+    /*  - scan direction                                                      */
+    /*  - DMA continuous request                                              */
+    /*  - Trigger frequency mode                                              */
+    /* Note: If low power mode AutoPowerOff is enabled, ADC enable            */
+    /*       and disable phases are performed automatically by hardware       */
+    /*       (in this case, flag ADC_FLAG_RDY is not set).                    */
+    if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+    {
+      /* Some parameters of this register are not reset, since they are set   */
+      /* by other functions and must be kept in case of usage of this         */
+      /* function on the fly (update of a parameter of ADC_InitTypeDef        */
+      /* without needing to reconfigure all other ADC groups/channels         */
+      /* parameters):                                                         */
+      /*   - internal measurement paths: temperature sensor, Vref             */
+      /*     (set into HAL_ADC_ConfigChannel() )                              */
+
+      tmpCFGR1 |= (hadc->Init.Resolution                                          |
+                   ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait)      |
+                   ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff)   |
+                   ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode)  |
+                   ADC_CFGR1_OVERRUN(hadc->Init.Overrun)                          |
+                   hadc->Init.DataAlign                                           |
+                   ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode)                     |
+                   ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
+
+      /* Update setting of discontinuous mode only if continuous mode is disabled */
+      if (hadc->Init.DiscontinuousConvMode == ENABLE)
+      {
+        if (hadc->Init.ContinuousConvMode == DISABLE)
+        {
+          /* Enable the selected ADC group regular discontinuous mode */
+          tmpCFGR1 |= ADC_CFGR1_DISCEN;
+        }
+        else
+        {
+          /* ADC regular group discontinuous was intended to be enabled,        */
+          /* but ADC regular group modes continuous and sequencer discontinuous */
+          /* cannot be enabled simultaneously.                                  */
+
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        }
+      }
+
+      /* Enable external trigger if trigger selection is different of software  */
+      /* start.                                                                 */
+      /* Note: This configuration keeps the hardware feature of parameter       */
+      /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
+      /*       software start.                                                  */
+      if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
+      {
+        tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) |
+                     hadc->Init.ExternalTrigConvEdge);
+      }
+
+      /* Update ADC configuration register with previous settings */
+      MODIFY_REG(hadc->Instance->CFGR1,
+                 ADC_CFGR1_RES     |
+                 ADC_CFGR1_DISCEN  |
+                 ADC_CFGR1_CHSELRMOD |
+                 ADC_CFGR1_AUTOFF  |
+                 ADC_CFGR1_WAIT    |
+                 ADC_CFGR1_CONT    |
+                 ADC_CFGR1_OVRMOD  |
+                 ADC_CFGR1_EXTSEL  |
+                 ADC_CFGR1_EXTEN   |
+                 ADC_CFGR1_ALIGN   |
+                 ADC_CFGR1_SCANDIR |
+                 ADC_CFGR1_DMACFG,
+                 tmpCFGR1);
+
+      tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
+                   hadc->Init.TriggerFrequencyMode
+                  );
+
+      if (hadc->Init.OversamplingMode == ENABLE)
+      {
+        tmpCFGR2 |= (ADC_CFGR2_OVSE |
+                     (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) |
+                     hadc->Init.Oversampling.Ratio         |
+                     hadc->Init.Oversampling.RightBitShift |
+                     hadc->Init.Oversampling.TriggeredMode
+                    );
+      }
+
+      MODIFY_REG(hadc->Instance->CFGR2,
+                 ADC_CFGR2_CKMODE |
+                 ADC_CFGR2_LFTRIG |
+                 ADC_CFGR2_OVSE   |
+                 ADC_CFGR2_OVSR   |
+                 ADC_CFGR2_OVSS   |
+                 ADC_CFGR2_TOVS,
+                 tmpCFGR2);
+
+      /* Configuration of ADC clock mode: asynchronous clock source           */
+      /* with selectable prescaler.                                           */
+      if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) &&
+          ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) &&
+          ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4))
+      {
+        MODIFY_REG(ADC1_COMMON->CCR,
+                   ADC_CCR_PRESC,
+                   hadc->Init.ClockPrescaler & ADC_CCR_PRESC);
+      }
+    }
+
+    /* Channel sampling time configuration */
+    LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1);
+    LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2);
+
+    /* Configuration of regular group sequencer:                              */
+    /* - if scan mode is disabled, regular channels sequence length is set to */
+    /*   0x00: 1 channel converted (channel on regular rank 1)                */
+    /*   Parameter "NbrOfConversion" is discarded.                            */
+    /*   Note: Scan mode is not present by hardware on this device, but       */
+    /*   emulated by software for alignment over all STM32 devices.           */
+    /* - if scan mode is enabled, regular channels sequence length is set to  */
+    /*   parameter "NbrOfConversion".                                         */
+    /*   Channels must be configured into each rank using function            */
+    /*   "HAL_ADC_ConfigChannel()".                                           */
+    if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
+    {
+      /* Set sequencer scan length by clearing ranks above rank 1             */
+      /* and do not modify rank 1 value.                                      */
+      SET_BIT(hadc->Instance->CHSELR,
+              ADC_CHSELR_SQ2_TO_SQ8);
+    }
+    else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
+    {
+      /* Set ADC group regular sequencer:                                   */
+      /*  - Set ADC group regular sequencer to value memorized              */
+      /*    in HAL ADC handle                                               */
+      /*    Note: This value maybe be initialized at a unknown value,       */
+      /*          therefore after the first call of "HAL_ADC_Init()",       */
+      /*          each rank corresponding to parameter "NbrOfConversion"    */
+      /*          must be set using "HAL_ADC_ConfigChannel()".              */
+      /*  - Set sequencer scan length by clearing ranks above maximum rank  */
+      /*    and do not modify other ranks value.                            */
+      MODIFY_REG(hadc->Instance->CHSELR,
+                 ADC_CHSELR_SQ_ALL,
+                 (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL))
+                 | (hadc->ADCGroupRegularSequencerRanks)
+                );
+    }
+    else
+    {
+      /* Nothing to do */
+    }
+    /* Check back that ADC registers have effectively been configured to      */
+    /* ensure of no potential problem of ADC core peripheral clocking.        */
+    if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1)
+        == hadc->Init.SamplingTimeCommon1)
+    {
+      /* Set ADC error code to none */
+      ADC_CLEAR_ERRORCODE(hadc);
+
+      /* Set the ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_BUSY_INTERNAL,
+                        HAL_ADC_STATE_READY);
+    }
+    else
+    {
+      /* Update ADC state machine to error */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_BUSY_INTERNAL,
+                        HAL_ADC_STATE_ERROR_INTERNAL);
+
+      /* Set ADC error code to ADC peripheral internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+      tmp_hal_status = HAL_ERROR;
+    }
+
+  }
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Deinitialize the ADC peripheral registers to their default reset
+  *         values, with deinitialization of the ADC MSP.
+  * @note   For devices with several ADCs: reset of ADC common registers is done
+  *         only if all ADCs sharing the same common group are disabled.
+  *         (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
+  *         all ADC instances use the same core clock at RCC level, disabling
+  *         the core clock reset all ADC instances).
+  *         If this is not the case, reset of these common parameters reset is
+  *         bypassed without error reporting: it can be the intended behavior in
+  *         case of reset of a single ADC while the other ADCs sharing the same
+  *         common group is still running.
+  * @note   By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
+  *         this saves more power by reducing leakage currents
+  *         and is particularly interesting before entering MCU low-power modes.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check ADC handle */
+  if (hadc == NULL)
+  {
+    return HAL_ERROR;
+  }
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
+
+  /* Stop potential conversion on going, on regular group */
+  tmp_hal_status = ADC_ConversionStop(hadc);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Change ADC state */
+      hadc->State = HAL_ADC_STATE_READY;
+    }
+
+    /* Disable ADC internal voltage regulator */
+    LL_ADC_DisableInternalRegulator(hadc->Instance);
+  }
+
+  /* Note: HAL ADC deInit is done independently of ADC conversion stop        */
+  /*       and disable return status. In case of status fail, attempt to      */
+  /*       perform deinitialization anyway and it is up user code in          */
+  /*       in HAL_ADC_MspDeInit() to reset the ADC peripheral using           */
+  /*       system RCC hard reset.                                             */
+
+  /* ========== Reset ADC registers ========== */
+
+  /* Reset register IER */
+  __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3  | ADC_IT_AWD2 |
+                              ADC_IT_AWD1  | ADC_IT_OVR  |
+                              ADC_IT_EOS   | ADC_IT_EOC  |
+                              ADC_IT_EOCAL | ADC_IT_EOSMP | ADC_IT_RDY));
+
+  /* Reset register ISR */
+  __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3  | ADC_FLAG_AWD2 |
+                              ADC_FLAG_AWD1  | ADC_FLAG_OVR  |
+                              ADC_FLAG_EOS   | ADC_FLAG_EOC  |
+                              ADC_FLAG_EOCAL | ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+
+  /* Reset register CR */
+  /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode     */
+  /* "read-set": no direct reset applicable.                                */
+
+  /* Reset register CFGR1 */
+  hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH  | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN |
+                             ADC_CFGR1_CHSELRMOD | ADC_CFGR1_AUTOFF |
+                             ADC_CFGR1_WAIT    | ADC_CFGR1_CONT   | ADC_CFGR1_OVRMOD  |
+                             ADC_CFGR1_EXTEN   | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN   | ADC_CFGR1_RES    |
+                             ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN);
+
+  /* Reset register CFGR2 */
+  /* Note: Update of ADC clock mode is conditioned to ADC state disabled:   */
+  /*       already done above.                                              */
+  hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE;
+
+  /* Reset register SMPR */
+  hadc->Instance->SMPR &= ~ADC_SMPR_SMP1;
+
+  /* Reset registers AWDxTR */
+  hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1);
+  hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2);
+  hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3);
+
+  /* Reset register CHSELR */
+  hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL);
+
+  /* Reset register DR */
+  /* bits in access mode read only, no direct reset applicable */
+
+  /* Reset register CCR */
+  ADC1_COMMON->CCR &= ~(ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_PRESC);
+
+  /* ========== Hard reset ADC peripheral ========== */
+  /* Performs a global reset of the entire ADC peripheral: ADC state is     */
+  /* forced to a similar state after device power-on.                       */
+  /* If needed, copy-paste and uncomment the following reset code into      */
+  /* function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)":            */
+  /*                                                                        */
+  /*  __HAL_RCC_ADC1_FORCE_RESET()                                          */
+  /*  __HAL_RCC_ADC1_RELEASE_RESET()                                        */
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  if (hadc->MspDeInitCallback == NULL)
+  {
+    hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit  */
+  }
+
+  /* DeInit the low level hardware */
+  hadc->MspDeInitCallback(hadc);
+#else
+  /* DeInit the low level hardware */
+  HAL_ADC_MspDeInit(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+  /* Reset HAL ADC handle variable */
+  hadc->ADCGroupRegularSequencerRanks = 0x00000000UL;
+
+  /* Set ADC error code to none */
+  ADC_CLEAR_ERRORCODE(hadc);
+
+  /* Set ADC state */
+  hadc->State = HAL_ADC_STATE_RESET;
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Initialize the ADC MSP.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspInit must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  DeInitialize the ADC MSP.
+  * @param hadc ADC handle
+  * @note   All ADC instances use the same core clock at RCC level, disabling
+  *         the core clock reset all ADC instances).
+  * @retval None
+  */
+__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_MspDeInit must be implemented in the user file.
+   */
+}
+
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+/**
+  * @brief  Register a User ADC Callback
+  *         To be used instead of the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be registered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
+  *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @param  pCallback pointer to the Callback function
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
+                                           pADC_CallbackTypeDef pCallback)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if (pCallback == NULL)
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    return HAL_ERROR;
+  }
+
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = pCallback;
+        break;
+
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+        hadc->LevelOutOfWindow2Callback = pCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+        hadc->LevelOutOfWindow3Callback = pCallback;
+        break;
+
+      case HAL_ADC_END_OF_SAMPLING_CB_ID :
+        hadc->EndOfSamplingCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = pCallback;
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = pCallback;
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status = HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+/**
+  * @brief  Unregister a ADC Callback
+  *         ADC callback is redirected to the weak predefined callback
+  * @param  hadc Pointer to a ADC_HandleTypeDef structure that contains
+  *                the configuration information for the specified ADC.
+  * @param  CallbackID ID of the callback to be unregistered
+  *         This parameter can be one of the following values:
+  *          @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID      ADC conversion complete callback ID
+  *          @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID          ADC conversion DMA half-transfer callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID    ADC analog watchdog 1 callback ID
+  *          @arg @ref HAL_ADC_ERROR_CB_ID                    ADC error callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID    ADC analog watchdog 2 callback ID
+  *          @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID    ADC analog watchdog 3 callback ID
+  *          @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID          ADC end of sampling callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID                  ADC Msp Init callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID                ADC Msp DeInit callback ID
+  *          @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
+  *          @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
+{
+  HAL_StatusTypeDef status = HAL_OK;
+
+  if ((hadc->State & HAL_ADC_STATE_READY) != 0)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
+        hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
+        break;
+
+      case HAL_ADC_CONVERSION_HALF_CB_ID :
+        hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
+        hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
+        break;
+
+      case HAL_ADC_ERROR_CB_ID :
+        hadc->ErrorCallback = HAL_ADC_ErrorCallback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
+        hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
+        break;
+
+      case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
+        hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
+        break;
+
+      case HAL_ADC_END_OF_SAMPLING_CB_ID :
+        hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
+        break;
+
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit              */
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else if (HAL_ADC_STATE_RESET == hadc->State)
+  {
+    switch (CallbackID)
+    {
+      case HAL_ADC_MSPINIT_CB_ID :
+        hadc->MspInitCallback = HAL_ADC_MspInit;                   /* Legacy weak MspInit              */
+        break;
+
+      case HAL_ADC_MSPDEINIT_CB_ID :
+        hadc->MspDeInitCallback = HAL_ADC_MspDeInit;               /* Legacy weak MspDeInit            */
+        break;
+
+      default :
+        /* Update the error code */
+        hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+        /* Return error status */
+        status =  HAL_ERROR;
+        break;
+    }
+  }
+  else
+  {
+    /* Update the error code */
+    hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
+
+    /* Return error status */
+    status =  HAL_ERROR;
+  }
+
+  return status;
+}
+
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
+  *  @brief    ADC IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Start conversion of regular group.
+      (+) Stop conversion of regular group.
+      (+) Poll for conversion complete on regular group.
+      (+) Poll for conversion event.
+      (+) Get result of regular channel conversion.
+      (+) Start conversion of regular group and enable interruptions.
+      (+) Stop conversion of regular group and disable interruptions.
+      (+) Handle ADC interrupt request
+      (+) Start conversion of regular group and enable DMA transfer.
+      (+) Stop conversion of regular group and disable ADC DMA transfer.
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enable ADC, start conversion of regular group.
+  * @note   Interruptions enabled in this function: None.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+
+      /* Set ADC error code */
+      /* Reset all ADC error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+
+      /* Clear ADC group regular conversion flag and overrun flag               */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      /* Start ADC group regular conversion */
+      LL_ADC_REG_StartConversion(hadc->Instance);
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected channels in
+  *         case of auto_injection mode), disable ADC peripheral.
+  * @note:  ADC peripheral disable is forcing stop of potential
+  *         conversion on injected group. If injected group is under use, it
+  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going, on ADC group regular */
+  tmp_hal_status = ADC_ConversionStop(hadc);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Wait for regular group conversion to be completed.
+  * @note   ADC conversion flags EOS (end of sequence) and EOC (end of
+  *         conversion) are cleared by this function, with an exception:
+  *         if low power feature "LowPowerAutoWait" is enabled, flags are
+  *         not cleared to not interfere with this feature until data register
+  *         is read using function HAL_ADC_GetValue().
+  * @note   This function cannot be used in a particular setup: ADC configured
+  *         in DMA mode and polling for end of each conversion (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
+  *         In this case, DMA resets the flag EOC and polling cannot be
+  *         performed on each conversion. Nevertheless, polling can still
+  *         be performed on the complete sequence (ADC init
+  *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
+  * @param hadc ADC handle
+  * @param Timeout Timeout value in millisecond.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
+{
+  uint32_t tickstart;
+  uint32_t tmp_Flag_End;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* If end of conversion selected to end of sequence conversions */
+  if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
+  {
+    tmp_Flag_End = ADC_FLAG_EOS;
+  }
+  /* If end of conversion selected to end of unitary conversion */
+  else /* ADC_EOC_SINGLE_CONV */
+  {
+    /* Verification that ADC configuration is compliant with polling for      */
+    /* each conversion:                                                       */
+    /* Particular case is ADC configured in DMA mode and ADC sequencer with   */
+    /* several ranks and polling for end of each conversion.                  */
+    /* For code simplicity sake, this particular case is generalized to       */
+    /* ADC configured in DMA mode and and polling for end of each conversion. */
+    if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) != 0UL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+      return HAL_ERROR;
+    }
+    else
+    {
+      tmp_Flag_End = (ADC_FLAG_EOC);
+    }
+  }
+
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+
+  /* Wait until End of unitary conversion or sequence conversions flag is raised */
+  while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        /* Update ADC state machine to timeout */
+        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  /* Update ADC state machine */
+  SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+  /* Determine whether any further conversion upcoming on group regular       */
+  /* by external trigger, continuous mode or scan sequence on going.          */
+  if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+      && (hadc->Init.ContinuousConvMode == DISABLE)
+     )
+  {
+    /* Check whether end of sequence is reached */
+    if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+    {
+      /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit             */
+      /* ADSTART==0 (no conversion on going)                                  */
+      if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+      {
+        /* Disable ADC end of single conversion interrupt on group regular */
+        /* Note: Overrun interrupt was enabled with EOC interrupt in          */
+        /* HAL_Start_IT(), but is not disabled here because can be used       */
+        /* by overrun IRQ process below.                                      */
+        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+        /* Set ADC state */
+        ADC_STATE_CLR_SET(hadc->State,
+                          HAL_ADC_STATE_REG_BUSY,
+                          HAL_ADC_STATE_READY);
+      }
+      else
+      {
+        /* Change ADC state to error state */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+        /* Set ADC error code to ADC peripheral internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+      }
+    }
+  }
+
+  /* Clear end of conversion flag of regular group if low power feature       */
+  /* "LowPowerAutoWait " is disabled, to not interfere with this feature      */
+  /* until data register is read using function HAL_ADC_GetValue().           */
+  if (hadc->Init.LowPowerAutoWait == DISABLE)
+  {
+    /* Clear regular group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Poll for ADC event.
+  * @param hadc ADC handle
+  * @param EventType the ADC event type.
+  *          This parameter can be one of the following values:
+  *            @arg @ref ADC_EOSMP_EVENT  ADC End of Sampling event
+  *            @arg @ref ADC_AWD1_EVENT   ADC Analog watchdog 1 event (main analog watchdog, present on
+  *                                       all STM32 devices)
+  *            @arg @ref ADC_AWD2_EVENT   ADC Analog watchdog 2 event (additional analog watchdog, not present on
+  *                                       all STM32 families)
+  *            @arg @ref ADC_AWD3_EVENT   ADC Analog watchdog 3 event (additional analog watchdog, not present on
+  *                                       all STM32 families)
+  *            @arg @ref ADC_OVR_EVENT    ADC Overrun event
+  * @param Timeout Timeout value in millisecond.
+  * @note   The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
+  *         Indeed, the latter is reset only if hadc->Init.Overrun field is set
+  *         to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
+  *         by a new converted data as soon as OVR is cleared.
+  *         To reset OVR flag once the preserved data is retrieved, the user can resort
+  *         to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EVENT_TYPE(EventType));
+
+  /* Get tick count */
+  tickstart = HAL_GetTick();
+
+  /* Check selected event flag */
+  while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
+  {
+    /* Check if timeout is disabled (set to infinite wait) */
+    if (Timeout != HAL_MAX_DELAY)
+    {
+      if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
+      {
+        /* Update ADC state machine to timeout */
+        SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
+
+        /* Process unlocked */
+        __HAL_UNLOCK(hadc);
+
+        return HAL_TIMEOUT;
+      }
+    }
+  }
+
+  switch (EventType)
+  {
+    /* End Of Sampling event */
+    case ADC_EOSMP_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+
+      /* Clear the End Of Sampling flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+
+      break;
+
+    /* Analog watchdog (level out of window) event */
+    /* Note: In case of several analog watchdog enabled, if needed to know      */
+    /* which one triggered and on which ADCx, test ADC state of analog watchdog */
+    /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()".        */
+    /* For example:                                                             */
+    /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "          */
+    /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) "          */
+    /*  " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) "          */
+
+    /* Check analog watchdog 1 flag */
+    case ADC_AWD_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+      /* Clear ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+
+      break;
+
+    /* Check analog watchdog 2 flag */
+    case ADC_AWD2_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+      /* Clear ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+
+      break;
+
+    /* Check analog watchdog 3 flag */
+    case ADC_AWD3_EVENT:
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+      /* Clear ADC analog watchdog flag */
+      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+
+      break;
+
+    /* Overrun event */
+    default: /* Case ADC_OVR_EVENT */
+      /* If overrun is set to overwrite previous data, overrun event is not     */
+      /* considered as an error.                                                */
+      /* (cf ref manual "Managing conversions without using the DMA and without */
+      /* overrun ")                                                             */
+      if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+      {
+        /* Set ADC state */
+        SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+        /* Set ADC error code to overrun */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+      }
+      else
+      {
+        /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
+           otherwise, data register is potentially overwritten by new converted data as soon
+           as OVR is cleared. */
+        __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+      }
+      break;
+  }
+
+  /* Return function status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of regular group with interruption.
+  * @note   Interruptions enabled in this function according to initialization
+  *         setting : EOC (end of conversion), EOS (end of sequence),
+  *         OVR overrun.
+  *         Each of these interruptions has its dedicated callback function.
+  * @note   To guarantee a proper reset of all interruptions once all the needed
+  *         conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
+  *         a correct stop of the IT-based conversions.
+  * @note   By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
+  *         interruption. If required (e.g. in case of oversampling with trigger
+  *         mode), the user must:
+  *          1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
+  *          2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
+  *          before calling HAL_ADC_Start_IT().
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+
+
+      /* Set ADC error code */
+      /* Reset all ADC error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+
+      /* Clear ADC group regular conversion flag and overrun flag               */
+      /* (To ensure of no unknown state from potential previous ADC operations) */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Disable all interruptions before enabling the desired ones */
+      __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+      /* Enable ADC end of conversion interrupt */
+      switch (hadc->Init.EOCSelection)
+      {
+        case ADC_EOC_SEQ_CONV:
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
+          break;
+        /* case ADC_EOC_SINGLE_CONV */
+        default:
+          __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
+          break;
+      }
+
+      /* Enable ADC overrun interrupt */
+      /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
+         ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
+         behavior and no CPU time is lost for a non-processed interruption */
+      if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+      {
+        __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+      }
+
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      /* Start ADC group regular conversion */
+      LL_ADC_REG_StartConversion(hadc->Instance);
+    }
+    else
+    {
+      /* Process unlocked */
+      __HAL_UNLOCK(hadc);
+    }
+
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable interrution of
+  *         end-of-conversion, disable ADC peripheral.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential conversion on going, on ADC group regular */
+  tmp_hal_status = ADC_ConversionStop(hadc);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable ADC end of conversion interrupt for regular group */
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
+
+    /* 2. Disable the ADC peripheral */
+    tmp_hal_status = ADC_Disable(hadc);
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Enable ADC, start conversion of regular group and transfer result through DMA.
+  * @note   Interruptions enabled in this function:
+  *         overrun (if applicable), DMA half transfer, DMA transfer complete.
+  *         Each of these interruptions has its dedicated callback function.
+  * @param hadc ADC handle
+  * @param pData Destination Buffer address.
+  * @param Length Number of data to be transferred from ADC peripheral to memory
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Perform ADC enable and conversion start if no conversion is on going */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Process locked */
+    __HAL_LOCK(hadc);
+
+    /* Specific case for first call occurrence of this function (DMA transfer */
+    /* not activated and ADC disabled), DMA transfer must be activated        */
+    /* with ADC disabled.                                                     */
+    if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) == 0UL)
+    {
+      if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+      {
+        /* Disable ADC */
+        LL_ADC_Disable(hadc->Instance);
+      }
+
+      /* Enable ADC DMA mode */
+      hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN;
+    }
+
+    /* Enable the ADC peripheral */
+    tmp_hal_status = ADC_Enable(hadc);
+
+    /* Start conversion if ADC is effectively enabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state                                                        */
+      /* - Clear state bitfield related to regular group conversion results   */
+      /* - Set state bitfield related to regular operation                    */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
+                        HAL_ADC_STATE_REG_BUSY);
+
+      /* Set ADC error code */
+      /* Reset all ADC error code fields */
+      ADC_CLEAR_ERRORCODE(hadc);
+
+      /* Set the DMA transfer complete callback */
+      hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
+
+      /* Set the DMA half transfer complete callback */
+      hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
+
+      /* Set the DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
+
+
+      /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC   */
+      /* start (in case of SW start):                                         */
+
+      /* Clear regular group conversion flag and overrun flag */
+      /* (To ensure of no unknown state from potential previous ADC           */
+      /* operations)                                                          */
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
+
+      /* Process unlocked */
+      /* Unlock before starting ADC conversions: in case of potential         */
+      /* interruption, to let the process to ADC IRQ Handler.                 */
+      __HAL_UNLOCK(hadc);
+
+      /* Enable ADC overrun interrupt */
+      __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
+
+      /* Start the DMA channel */
+      tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
+
+      /* Enable conversion of regular group.                                  */
+      /* If software start has been selected, conversion starts immediately.  */
+      /* If external trigger has been selected, conversion will start at next */
+      /* trigger event.                                                       */
+      /* Start ADC group regular conversion */
+      LL_ADC_REG_StartConversion(hadc->Instance);
+    }
+  }
+  else
+  {
+    tmp_hal_status = HAL_BUSY;
+  }
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Stop ADC conversion of regular group (and injected group in
+  *         case of auto_injection mode), disable ADC DMA transfer, disable
+  *         ADC peripheral.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* 1. Stop potential ADC group regular conversion on going */
+  tmp_hal_status = ADC_ConversionStop(hadc);
+
+  /* Disable ADC peripheral if conversions are effectively stopped */
+  if (tmp_hal_status == HAL_OK)
+  {
+    /* Disable the DMA channel (in case of DMA in circular mode or stop       */
+    /* while DMA transfer is on going)                                        */
+    if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
+    {
+      tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
+
+      /* Check if DMA channel effectively disabled */
+      if (tmp_hal_status != HAL_OK)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+      }
+    }
+
+    /* Disable ADC overrun interrupt */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
+
+    /* 2. Disable the ADC peripheral */
+    /* Update "tmp_hal_status" only if DMA channel disabling passed,          */
+    /* to keep in memory a potential failing status.                          */
+    if (tmp_hal_status == HAL_OK)
+    {
+      tmp_hal_status = ADC_Disable(hadc);
+    }
+    else
+    {
+      (void)ADC_Disable(hadc);
+    }
+
+    /* Check if ADC is effectively disabled */
+    if (tmp_hal_status == HAL_OK)
+    {
+      /* Set ADC state */
+      ADC_STATE_CLR_SET(hadc->State,
+                        HAL_ADC_STATE_REG_BUSY,
+                        HAL_ADC_STATE_READY);
+    }
+
+    /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
+    CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN);
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get ADC regular group conversion result.
+  * @note   Reading register DR automatically clears ADC flag EOC
+  *         (ADC group regular end of unitary conversion).
+  * @note   This function does not clear ADC flag EOS
+  *         (ADC group regular end of sequence conversion).
+  *         Occurrence of flag EOS rising:
+  *          - If sequencer is composed of 1 rank, flag EOS is equivalent
+  *            to flag EOC.
+  *          - If sequencer is composed of several ranks, during the scan
+  *            sequence flag EOC only is raised, at the end of the scan sequence
+  *            both flags EOC and EOS are raised.
+  *         To clear this flag, either use function:
+  *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
+  *         model polling: @ref HAL_ADC_PollForConversion()
+  *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
+  * @param hadc ADC handle
+  * @retval ADC group regular conversion data
+  */
+uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Note: EOC flag is not cleared here by software because automatically     */
+  /*       cleared by hardware when reading register DR.                      */
+
+  /* Return ADC converted value */
+  return hadc->Instance->DR;
+}
+
+/**
+  * @brief  Handle ADC interrupt request.
+  * @param hadc ADC handle
+  * @retval None
+  */
+void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
+{
+  uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
+  uint32_t tmp_isr = hadc->Instance->ISR;
+  uint32_t tmp_ier = hadc->Instance->IER;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
+
+  /* ========== Check End of Sampling flag for ADC group regular ========== */
+  if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
+  {
+    /* Update state machine on end of sampling status if not in error state */
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
+    }
+
+    /* End Of Sampling callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->EndOfSamplingCallback(hadc);
+#else
+    HAL_ADCEx_EndOfSamplingCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear regular group conversion flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
+  }
+
+  /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
+  if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
+      (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
+  {
+    /* Update state machine on conversion status if not in error state */
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+    }
+
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going         */
+    /* to disable interruption.                                               */
+    if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+        && (hadc->Init.ContinuousConvMode == DISABLE)
+       )
+    {
+      /* If End of Sequence is reached, disable interrupts */
+      if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+      {
+        /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
+        /* ADSTART==0 (no conversion on going)                                */
+        if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+        {
+          /* Disable ADC end of single conversion interrupt on group regular */
+          /* Note: Overrun interrupt was enabled with EOC interrupt in        */
+          /* HAL_Start_IT(), but is not disabled here because can be used     */
+          /* by overrun IRQ process below.                                    */
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+          /* Set ADC state */
+          ADC_STATE_CLR_SET(hadc->State,
+                            HAL_ADC_STATE_REG_BUSY,
+                            HAL_ADC_STATE_READY);
+        }
+        else
+        {
+          /* Change ADC state to error state */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        }
+      }
+    }
+
+    /* Conversion complete callback */
+    /* Note: Into callback function "HAL_ADC_ConvCpltCallback()",             */
+    /*       to determine if conversion has been triggered from EOC or EOS,   */
+    /*       possibility to use:                                              */
+    /*        " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) "               */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear regular group conversion flag */
+    /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of         */
+    /*       conversion flags clear induces the release of the preserved data.*/
+    /*       Therefore, if the preserved data value is needed, it must be     */
+    /*       read preliminarily into HAL_ADC_ConvCpltCallback().              */
+    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
+  }
+
+  /* ========== Check Analog watchdog 1 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+    /* Level out of window 1 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->LevelOutOfWindowCallback(hadc);
+#else
+    HAL_ADC_LevelOutOfWindowCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
+  }
+
+  /* ========== Check analog watchdog 2 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+    /* Level out of window 2 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->LevelOutOfWindow2Callback(hadc);
+#else
+    HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
+  }
+
+  /* ========== Check analog watchdog 3 flag ========== */
+  if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+    /* Level out of window 3 callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->LevelOutOfWindow3Callback(hadc);
+#else
+    HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
+  }
+  /* ========== Check Overrun flag ========== */
+  if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
+  {
+    /* If overrun is set to overwrite previous data (default setting),        */
+    /* overrun event is not considered as an error.                           */
+    /* (cf ref manual "Managing conversions without using the DMA and without */
+    /* overrun ")                                                             */
+    /* Exception for usage with DMA overrun event always considered as an     */
+    /* error.                                                                 */
+    if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
+    {
+      overrun_error = 1UL;
+    }
+    else
+    {
+      /* Check DMA configuration */
+      if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE)
+      {
+        overrun_error = 1UL;
+      }
+    }
+
+    if (overrun_error == 1UL)
+    {
+      /* Change ADC state to error state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
+
+      /* Set ADC error code to overrun */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
+
+      /* Error callback */
+      /* Note: In case of overrun, ADC conversion data is preserved until     */
+      /*       flag OVR is reset.                                             */
+      /*       Therefore, old ADC conversion data can be retrieved in         */
+      /*       function "HAL_ADC_ErrorCallback()".                            */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    }
+
+    /* Clear ADC overrun flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
+  }
+
+  /* ========== Check ADC Ready flag ========== */
+  if (((tmp_isr & ADC_FLAG_RDY) == ADC_FLAG_RDY) && ((tmp_ier & ADC_IT_RDY) == ADC_IT_RDY))
+  {
+    /* Update state machine on end of sampling status if not in error state */
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
+    {
+      /* Set ADC state */
+      SET_BIT(hadc->State, HAL_ADC_STATE_READY);
+    }
+
+    /* ADC Ready callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ADCReadyCallback(hadc);
+#else
+    HAL_ADC_ADCReadyCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Leave ADRDY flag up (used by HAL), disable interrupt source instead */
+    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_RDY);
+  }
+
+  /* ========== Check End of Calibration flag ========== */
+  if (((tmp_isr & ADC_FLAG_EOCAL) == ADC_FLAG_EOCAL) && ((tmp_ier & ADC_IT_EOCAL) == ADC_IT_EOCAL))
+  {
+    /* End Of Calibration callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->CalibrationCpltCallback(hadc);
+#else
+    HAL_ADC_CalibrationCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear end of calibration flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOCAL);
+  }
+
+  /* ========== Check channel configuration ready flag ========== */
+  if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY))
+  {
+    /* Channel configuration ready callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ChannelConfigReadyCallback(hadc);
+#else
+    HAL_ADCEx_ChannelConfigReadyCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+
+    /* Clear ADC analog watchdog flag */
+    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_CCRDY);
+  }
+}
+
+/**
+  * @brief  Conversion complete callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief  Conversion DMA half-transfer callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 1 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  ADC error callback in non-blocking mode
+  *         (ADC conversion with interruption or transfer by DMA).
+  * @note   In case of error due to overrun when using ADC with DMA transfer
+  *         (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
+  *         - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
+  *         - If needed, restart a new ADC conversion using function
+  *           "HAL_ADC_Start_DMA()"
+  *           (this function is also clearing overrun flag)
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ErrorCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Calibration complete callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_CalibrationCpltCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @brief ADC Ready callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADC_ADCReadyCallback must be implemented in the user file.
+   */
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
+  * @brief    Peripheral Control functions
+  *
+@verbatim
+ ===============================================================================
+             ##### Peripheral Control functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+      (+) Configure channels on regular group
+      (+) Configure the analog watchdog
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configure a channel to be assigned to ADC group regular.
+  * @note   In case of usage of internal measurement channels:
+  *         VrefInt/TempSensor.
+  *         These internal paths can be disabled using function
+  *         HAL_ADC_DeInit().
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes channel into ADC group regular,
+  *         following calls to this function can be used to reconfigure
+  *         some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
+  *         without resetting the ADC.
+  *         The setting of these parameters is conditioned to ADC state:
+  *         Refer to comments of structure "ADC_ChannelConfTypeDef".
+  * @param hadc ADC handle
+  * @param sConfig Structure of ADC channel assigned to ADC group regular.
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmp_config_internal_channel;
+  __IO uint32_t wait_loop_index = 0UL;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
+  assert_param(IS_ADC_SAMPLING_TIME_COMMON(sConfig->SamplingTime));
+
+  if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED)       ||
+      (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
+  {
+    assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(sConfig->Rank));
+  }
+  else
+  {
+    assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
+
+    assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on regular group:                                    */
+  /*  - Channel number                                                        */
+  /*  - Channel sampling time                                                 */
+  /*  - Management of internal measurement channels: VrefInt/TempSensor       */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Configure channel: depending on rank setting, add it or remove it from */
+    /* ADC sequencer.                                                         */
+    /* If sequencer set to not fully configurable with channel rank set to    */
+    /* none, remove the channel from the sequencer.                           */
+    /* Otherwise (sequencer set to fully configurable or to to not fully      */
+    /* configurable with channel rank to be set), configure the selected      */
+    /* channel.                                                               */
+    if (sConfig->Rank != ADC_RANK_NONE)
+    {
+      /* Regular sequence configuration */
+      /* Note: ADC channel configuration requires few ADC clock cycles        */
+      /*       to be ready. Processing of ADC settings in this function       */
+      /*       induce that a specific wait time is not necessary.             */
+      /*       For more details on ADC channel configuration ready,           */
+      /*       refer to function "LL_ADC_IsActiveFlag_CCRDY()".               */
+      if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED)       ||
+          (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
+      {
+        /* Sequencer set to not fully configurable:                           */
+        /* Set the channel by enabling the corresponding bitfield.            */
+        LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel);
+      }
+      else
+      {
+        /* Sequencer set to fully configurable:                               */
+        /* Set the channel by entering it into the selected rank.             */
+
+        /* Memorize the channel set into variable in HAL ADC handle */
+        MODIFY_REG(hadc->ADCGroupRegularSequencerRanks,
+                   ADC_CHSELR_SQ1 << (sConfig->Rank & 0x1FUL),
+                   __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) << (sConfig->Rank & 0x1FUL));
+
+        /* If the selected rank is below ADC group regular sequencer length,  */
+        /* apply the configuration in ADC register.                           */
+        /* Note: Otherwise, configuration is not applied.                     */
+        /*       To apply it, parameter'NbrOfConversion' must be increased.   */
+        if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion)
+        {
+          LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
+        }
+      }
+
+      /* Set sampling time of the selected ADC channel */
+      LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
+
+      /* Management of internal measurement channels: VrefInt/TempSensor      */
+      /* internal measurement paths enable: If internal channel selected,     */
+      /* enable dedicated internal buffers and path.                          */
+      /* Note: these internal measurement paths can be disabled using         */
+      /*       HAL_ADC_DeInit() or removing the channel from sequencer with   */
+      /*       channel configuration parameter "Rank".                        */
+      if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+      {
+        tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+        /* If the requested internal measurement path has already been enabled,   */
+        /* bypass the configuration processing.                                   */
+        if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) &&
+            ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                         LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
+
+          /* Delay for temperature sensor stabilization time */
+          /* Wait loop initialization and execution */
+          /* Note: Variable divided by 2 to compensate partially              */
+          /*       CPU processing cycles, scaling in us split to not          */
+          /*       exceed 32 bits register capacity and handle low frequency. */
+          wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL);
+          while (wait_loop_index != 0UL)
+          {
+            wait_loop_index--;
+          }
+        }
+        else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) &&
+                 ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                         LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
+        }
+        else
+        {
+          /* nothing to do */
+        }
+      }
+    }
+    else
+    {
+      /* Regular sequencer configuration */
+      /* Note: Case of sequencer set to fully configurable:                   */
+      /*       Sequencer rank cannot be disabled, only affected to            */
+      /*       another channel.                                               */
+      /*       To remove a rank, use parameter 'NbrOfConversion".             */
+      if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED)       ||
+          (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD))
+      {
+        /* Sequencer set to not fully configurable:                           */
+        /* Reset the channel by disabling the corresponding bitfield.         */
+        LL_ADC_REG_SetSequencerChRem(hadc->Instance, sConfig->Channel);
+      }
+
+      /* Management of internal measurement channels: VrefInt/TempSensor.       */
+      /* If internal channel selected, enable dedicated internal buffers and    */
+      /* paths.                                                                 */
+      if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
+      {
+        tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+        if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                         ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel);
+        }
+        else if (sConfig->Channel == ADC_CHANNEL_VREFINT)
+        {
+          LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
+                                         ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel);
+        }
+        else
+        {
+          /* nothing to do */
+        }
+      }
+    }
+  }
+
+  /* If a conversion is on going on regular group, no update on regular       */
+  /* channel could be done on neither of the channel configuration structure  */
+  /* parameters.                                                              */
+  else
+  {
+    /* Update ADC state machine to error */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Configure the analog watchdog.
+  * @note   Possibility to update parameters on the fly:
+  *         This function initializes the selected analog watchdog, successive
+  *         calls to this function can be used to reconfigure some parameters
+  *         of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
+  *         the ADC.
+  *         The setting of these parameters is conditioned to ADC state.
+  *         For parameters constraints, see comments of structure
+  *         "ADC_AnalogWDGConfTypeDef".
+  * @note   On this STM32 series, analog watchdog thresholds can be modified
+  *         while ADC conversion is on going.
+  *         In this case, some constraints must be taken into account:
+  *         the programmed threshold values are effective from the next
+  *         ADC EOC (end of unitary conversion).
+  *         Considering that registers write delay may happen due to
+  *         bus activity, this might cause an uncertainty on the
+  *         effective timing of the new programmed threshold values.
+  * @param hadc ADC handle
+  * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmpAWDHighThresholdShifted;
+  uint32_t tmpAWDLowThresholdShifted;
+  uint32_t backup_setting_adc_enable_state = 0UL;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
+  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
+  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
+
+  if (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)
+  {
+    assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
+  }
+
+  /* Verify thresholds range */
+  if (hadc->Init.OversamplingMode == ENABLE)
+  {
+    /* Case of oversampling enabled: depending on ratio and shift configuration,
+       analog watchdog thresholds can be higher than ADC resolution.
+       Verify if thresholds are within maximum thresholds range. */
+    assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
+    assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
+  }
+  else
+  {
+    /* Verify if thresholds are within the selected ADC resolution */
+    assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
+    assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Parameters update conditioned to ADC state:                              */
+  /* Parameters that can be updated when ADC is disabled or enabled without   */
+  /* conversion on going on ADC group regular:                                */
+  /*  - Analog watchdog channels                                              */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+  {
+    /* Analog watchdog configuration */
+    if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+    {
+      /* Constraint of ADC on this STM32 series: ADC must be disable
+         to modify bitfields of register ADC_CFGR1 */
+      if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+      {
+        backup_setting_adc_enable_state = 1UL;
+        tmp_hal_status = ADC_Disable(hadc);
+
+        /* Check if ADC is effectively disabled */
+        if (tmp_hal_status == HAL_OK)
+        {
+          /* Set ADC state */
+          ADC_STATE_CLR_SET(hadc->State,
+                            HAL_ADC_STATE_REG_BUSY,
+                            HAL_ADC_STATE_READY);
+        }
+      }
+
+      /* Configuration of analog watchdog:                                    */
+      /*  - Set the analog watchdog enable mode: one or overall group of      */
+      /*    channels.                                                         */
+      switch (AnalogWDGConfig->WatchdogMode)
+      {
+        case ADC_ANALOGWATCHDOG_SINGLE_REG:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1,
+                                          __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
+                                                                          LL_ADC_GROUP_REGULAR));
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_REG:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
+          break;
+
+        default: /* ADC_ANALOGWATCHDOG_NONE */
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
+          break;
+      }
+
+      if (backup_setting_adc_enable_state == 1UL)
+      {
+        tmp_hal_status = ADC_Enable(hadc);
+      }
+
+      /* Update state, clear previous result related to AWD1 */
+      CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
+
+      /* Clear flag ADC analog watchdog */
+      /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+      /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+      /* (in case left enabled by previous ADC operations).                 */
+      LL_ADC_ClearFlag_AWD1(hadc->Instance);
+
+      /* Configure ADC analog watchdog interrupt */
+      if (AnalogWDGConfig->ITMode == ENABLE)
+      {
+        LL_ADC_EnableIT_AWD1(hadc->Instance);
+      }
+      else
+      {
+        LL_ADC_DisableIT_AWD1(hadc->Instance);
+      }
+    }
+    /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
+    else
+    {
+      switch (AnalogWDGConfig->WatchdogMode)
+      {
+        case ADC_ANALOGWATCHDOG_SINGLE_REG:
+          /* Update AWD by bitfield to keep the possibility to monitor        */
+          /* several channels by successive calls of this function.           */
+          if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+          {
+            SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel)));
+          }
+          else
+          {
+            SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel)));
+          }
+          break;
+
+        case ADC_ANALOGWATCHDOG_ALL_REG:
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG);
+          break;
+
+        default: /* ADC_ANALOGWATCHDOG_NONE */
+          LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
+          break;
+      }
+
+      if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
+      {
+        /* Update state, clear previous result related to AWD2 */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
+
+        /* Clear flag ADC analog watchdog */
+        /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+        /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+        /* (in case left enabled by previous ADC operations).                 */
+        LL_ADC_ClearFlag_AWD2(hadc->Instance);
+
+        /* Configure ADC analog watchdog interrupt */
+        if (AnalogWDGConfig->ITMode == ENABLE)
+        {
+          LL_ADC_EnableIT_AWD2(hadc->Instance);
+        }
+        else
+        {
+          LL_ADC_DisableIT_AWD2(hadc->Instance);
+        }
+      }
+      /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
+      else
+      {
+        /* Update state, clear previous result related to AWD3 */
+        CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
+
+        /* Clear flag ADC analog watchdog */
+        /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready  */
+        /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent()          */
+        /* (in case left enabled by previous ADC operations).                 */
+        LL_ADC_ClearFlag_AWD3(hadc->Instance);
+
+        /* Configure ADC analog watchdog interrupt */
+        if (AnalogWDGConfig->ITMode == ENABLE)
+        {
+          LL_ADC_EnableIT_AWD3(hadc->Instance);
+        }
+        else
+        {
+          LL_ADC_DisableIT_AWD3(hadc->Instance);
+        }
+      }
+    }
+
+  }
+
+  /* Analog watchdog thresholds configuration */
+  if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
+  {
+    /* Shift the offset with respect to the selected ADC resolution:        */
+    /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
+    /* are set to 0.                                                        */
+    tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
+    tmpAWDLowThresholdShifted  = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
+  }
+  /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
+  else
+  {
+    /* No need to shift the offset with respect to the selected ADC resolution: */
+    /* Thresholds have to be left-aligned on bit 11, the LSB (right bits)   */
+    /* are set to 0.                                                        */
+    tmpAWDHighThresholdShifted = AnalogWDGConfig->HighThreshold;
+    tmpAWDLowThresholdShifted  = AnalogWDGConfig->LowThreshold;
+  }
+
+  /* Set ADC analog watchdog thresholds value of both thresholds high and low */
+  LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
+                                  tmpAWDLowThresholdShifted);
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
+  *  @brief    ADC Peripheral State functions
+  *
+@verbatim
+ ===============================================================================
+            ##### Peripheral state and errors functions #####
+ ===============================================================================
+    [..]
+    This subsection provides functions to get in run-time the status of the
+    peripheral.
+      (+) Check the ADC state
+      (+) Check the ADC error code
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Return the ADC handle state.
+  * @note   ADC state machine is managed by bitfields, ADC status must be
+  *         compared with states bits.
+  *         For example:
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
+  * @param hadc ADC handle
+  * @retval ADC handle state (bitfield on 32 bits)
+  */
+uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Return ADC handle state */
+  return hadc->State;
+}
+
+/**
+  * @brief  Return the ADC error code.
+  * @param hadc ADC handle
+  * @retval ADC error code (bitfield on 32 bits)
+  */
+uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  return hadc->ErrorCode;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Private_Functions ADC Private Functions
+  * @{
+  */
+
+/**
+  * @brief  Stop ADC conversion.
+  * @note   Prerequisite condition to use this function: ADC conversions must be
+  *         stopped to disable the ADC.
+  * @param  hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc)
+{
+  uint32_t tickstart;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Verification if ADC is not already stopped on regular group to bypass    */
+  /* this function if not needed.                                             */
+  if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
+  {
+    /* Stop potential conversion on going on regular group */
+    /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
+    if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
+    {
+      /* Stop ADC group regular conversion */
+      LL_ADC_REG_StopConversion(hadc->Instance);
+    }
+
+    /* Wait for conversion effectively stopped */
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+
+    while ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL)
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+        /* Set ADC error code to ADC peripheral internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+        return HAL_ERROR;
+      }
+    }
+
+  }
+
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Enable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC must be disabled
+  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
+{
+  uint32_t tickstart;
+  __IO uint32_t wait_loop_index = 0UL;
+
+  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
+  /* enabling phase not yet completed: flag ADC ready not yet set).           */
+  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
+  /* causes: ADC clock not running, ...).                                     */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    /* Check if conditions to enable the ADC are fulfilled */
+    if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+      /* Set ADC error code to ADC peripheral internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+      return HAL_ERROR;
+    }
+
+    /* Enable the ADC peripheral */
+    LL_ADC_Enable(hadc->Instance);
+
+    if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR)
+        != 0UL)
+    {
+      /* Delay for temperature sensor buffer stabilization time */
+      /* Wait loop initialization and execution */
+      /* Note: Variable divided by 2 to compensate partially              */
+      /*       CPU processing cycles, scaling in us split to not          */
+      /*       exceed 32 bits register capacity and handle low frequency. */
+      wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL)
+                         * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
+      while (wait_loop_index != 0UL)
+      {
+        wait_loop_index--;
+      }
+    }
+
+    /* If low power mode AutoPowerOff is enabled, power-on/off phases are     */
+    /* performed automatically by hardware and flag ADC ready is not set.     */
+    if (hadc->Init.LowPowerAutoPowerOff != ENABLE)
+    {
+      /* Wait for ADC effectively enabled */
+      tickstart = HAL_GetTick();
+
+      while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
+      {
+        /*  If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
+            has been cleared (after a calibration), ADEN bit is reset by the
+            calibration logic.
+            The workaround is to continue setting ADEN until ADRDY is becomes 1.
+            Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
+            4 ADC clock cycle duration */
+        /* Note: Test of ADC enabled required due to hardware constraint to     */
+        /*       not enable ADC if already enabled.                             */
+        if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+        {
+          LL_ADC_Enable(hadc->Instance);
+        }
+
+        if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+  }
+
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  Disable the selected ADC.
+  * @note   Prerequisite condition to use this function: ADC conversions must be
+  *         stopped.
+  * @param hadc ADC handle
+  * @retval HAL status.
+  */
+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
+{
+  uint32_t tickstart;
+  const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
+
+  /* Verification if ADC is not already disabled:                             */
+  /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already  */
+  /*       disabled.                                                          */
+  if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+      && (tmp_adc_is_disable_on_going == 0UL)
+     )
+  {
+    /* Check if conditions to disable the ADC are fulfilled */
+    if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
+    {
+      /* Disable the ADC peripheral */
+      LL_ADC_Disable(hadc->Instance);
+      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
+    }
+    else
+    {
+      /* Update ADC state machine to error */
+      SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+      /* Set ADC error code to ADC peripheral internal error */
+      SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+      return HAL_ERROR;
+    }
+
+    /* Wait for ADC effectively disabled */
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+
+    while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+      {
+        /* Update ADC state machine to error */
+        SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+        /* Set ADC error code to ADC peripheral internal error */
+        SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+        return HAL_ERROR;
+      }
+    }
+  }
+
+  /* Return HAL status */
+  return HAL_OK;
+}
+
+/**
+  * @brief  DMA transfer complete callback.
+  * @param hdma pointer to DMA handle.
+  * @retval None
+  */
+static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Update state machine on conversion status if not in error state */
+  if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
+  {
+    /* Set ADC state */
+    SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
+
+    /* Determine whether any further conversion upcoming on group regular     */
+    /* by external trigger, continuous mode or scan sequence on going         */
+    /* to disable interruption.                                               */
+    if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
+        && (hadc->Init.ContinuousConvMode == DISABLE)
+       )
+    {
+      /* If End of Sequence is reached, disable interrupts */
+      if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
+      {
+        /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit           */
+        /* ADSTART==0 (no conversion on going)                                */
+        if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
+        {
+          /* Disable ADC end of single conversion interrupt on group regular */
+          /* Note: Overrun interrupt was enabled with EOC interrupt in        */
+          /* HAL_Start_IT(), but is not disabled here because can be used     */
+          /* by overrun IRQ process below.                                    */
+          __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
+
+          /* Set ADC state */
+          ADC_STATE_CLR_SET(hadc->State,
+                            HAL_ADC_STATE_REG_BUSY,
+                            HAL_ADC_STATE_READY);
+        }
+        else
+        {
+          /* Change ADC state to error state */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+        }
+      }
+    }
+
+    /* Conversion complete callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+    hadc->ConvCpltCallback(hadc);
+#else
+    HAL_ADC_ConvCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+  }
+  else /* DMA and-or internal error occurred */
+  {
+    if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
+    {
+      /* Call HAL ADC Error Callback function */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+      hadc->ErrorCallback(hadc);
+#else
+      HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+    }
+    else
+    {
+      /* Call ADC DMA error callback */
+      hadc->DMA_Handle->XferErrorCallback(hdma);
+    }
+  }
+}
+
+/**
+  * @brief  DMA half transfer complete callback.
+  * @param hdma pointer to DMA handle.
+  * @retval None
+  */
+static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Half conversion callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ConvHalfCpltCallback(hadc);
+#else
+  HAL_ADC_ConvHalfCpltCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @brief  DMA error callback.
+  * @param hdma pointer to DMA handle.
+  * @retval None
+  */
+static void ADC_DMAError(DMA_HandleTypeDef *hdma)
+{
+  /* Retrieve ADC handle corresponding to current DMA handle */
+  ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
+
+  /* Set ADC state */
+  SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
+
+  /* Set ADC error code to DMA error */
+  SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
+
+  /* Error callback */
+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
+  hadc->ErrorCallback(hadc);
+#else
+  HAL_ADC_ErrorCallback(hadc);
+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
+}
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
diff --git a/code/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c b/code/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c
new file mode 100644
index 0000000..5b95c64
--- /dev/null
+++ b/code/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c
@@ -0,0 +1,419 @@
+/**
+  ******************************************************************************
+  * @file    stm32c0xx_hal_adc_ex.c
+  * @author  MCD Application Team
+  * @brief   This file provides firmware functions to manage the following
+  *          functionalities of the Analog to Digital Converter (ADC)
+  *          peripheral:
+  *           + Operation functions
+  *             ++ Calibration
+  *               +++ ADC automatic self-calibration
+  *               +++ Calibration factors get or set
+  *          Other functions (generic functions) are available in file
+  *          "stm32c0xx_hal_adc.c".
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * Copyright (c) 2022 STMicroelectronics.
+  * All rights reserved.
+  *
+  * This software is licensed under terms that can be found in the LICENSE file
+  * in the root directory of this software component.
+  * If no LICENSE file comes with this software, it is provided AS-IS.
+  *
+  ******************************************************************************
+  @verbatim
+  [..]
+  (@) Sections "ADC peripheral features" and "How to use this driver" are
+      available in file of generic functions "stm32c0xx_hal_adc.c".
+  [..]
+  @endverbatim
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32c0xx_hal.h"
+
+/** @addtogroup STM32C0xx_HAL_Driver
+  * @{
+  */
+
+/** @defgroup ADCEx ADCEx
+  * @brief ADC Extended HAL module driver
+  * @{
+  */
+
+#ifdef HAL_ADC_MODULE_ENABLED
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants
+  * @{
+  */
+
+/* Fixed timeout value for ADC calibration.                                   */
+/* Values defined to be higher than worst cases: maximum ratio between ADC    */
+/* and CPU clock frequencies.                                                 */
+/* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock    */
+/* source 8MHz, ADC clock prescaler 256), CPU frequency 48MHz.            */
+/* Calibration time max = 116 / fADC (refer to datasheet)                     */
+/*                      = 178 176 CPU cycles                                  */
+#define ADC_CALIBRATION_TIMEOUT         (178176UL)   /*!< ADC calibration time-out value (unit: CPU cycles) */
+#define ADC_DISABLE_TIMEOUT             (2UL)
+
+/**
+  * @}
+  */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions
+  * @{
+  */
+
+/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions
+  * @brief    Extended IO operation functions
+  *
+@verbatim
+ ===============================================================================
+                      ##### IO operation functions #####
+ ===============================================================================
+    [..]  This section provides functions allowing to:
+
+      (+) Perform the ADC self-calibration.
+      (+) Get calibration factors.
+      (+) Set calibration factors.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Perform an ADC automatic self-calibration
+  *         Calibration prerequisite: ADC must be disabled (execute this
+  *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
+  * @note   Calibration factor can be read after calibration, using function
+  *         HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]).
+  * @param  hadc       ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+  __IO uint32_t wait_loop_index = 0UL;
+  uint32_t backup_setting_cfgr1;
+  uint32_t calibration_index;
+  uint32_t calibration_factor_accumulated = 0;
+  uint32_t tickstart;
+  uint32_t adc_clk_async_presc;
+  __IO uint32_t delay_cpu_cycles;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Calibration prerequisite: ADC must be disabled. */
+
+  /* Disable the ADC (if not already disabled) */
+  tmp_hal_status = ADC_Disable(hadc);
+
+  /* Check if ADC is effectively disabled */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_REG_BUSY,
+                      HAL_ADC_STATE_BUSY_INTERNAL);
+
+    /* Manage settings impacting calibration                                  */
+    /* - Disable ADC mode auto power-off                                      */
+    /* - Disable ADC DMA transfer request during calibration                  */
+    /* Note: Specificity of this STM32 series: Calibration factor is          */
+    /*       available in data register and also transferred by DMA.          */
+    /*       To not insert ADC calibration factor among ADC conversion data   */
+    /*       in array variable, DMA transfer must be disabled during          */
+    /*       calibration.                                                     */
+    backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF);
+    CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF);
+
+    /* ADC calibration procedure */
+    /* Note: Perform an averaging of 8 calibrations for optimized accuracy */
+    for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++)
+    {
+      /* Start ADC calibration */
+      LL_ADC_StartCalibration(hadc->Instance);
+
+      /* Wait for calibration completion */
+      while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL)
+      {
+        wait_loop_index++;
+        if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT)
+        {
+          /* Update ADC state machine to error */
+          ADC_STATE_CLR_SET(hadc->State,
+                            HAL_ADC_STATE_BUSY_INTERNAL,
+                            HAL_ADC_STATE_ERROR_INTERNAL);
+
+          __HAL_UNLOCK(hadc);
+
+          return HAL_ERROR;
+        }
+      }
+      /* Read the calibration factor and increment by one */
+      calibration_factor_accumulated += (LL_ADC_GetCalibrationFactor(hadc->Instance) + 1UL);
+    }
+    /* Compute average (rounded up to the nearest integer) */
+    calibration_factor_accumulated += (calibration_index / 2UL);
+    calibration_factor_accumulated /= calibration_index;
+
+    /* Apply calibration factor (requires ADC enable and disable process) */
+    LL_ADC_Enable(hadc->Instance);
+
+    /* Case of ADC clocked at low frequency: Delay required between ADC enable and disable actions */
+    if (LL_ADC_GetClock(hadc->Instance) == LL_ADC_CLOCK_ASYNC)
+    {
+      adc_clk_async_presc = LL_ADC_GetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
+
+      if (adc_clk_async_presc >= LL_ADC_CLOCK_ASYNC_DIV16)
+      {
+        /* Delay loop initialization and execution */
+        /* Delay depends on ADC clock prescaler: Compute ADC clock asynchronous prescaler to decimal format */
+        delay_cpu_cycles = (1UL << ((adc_clk_async_presc >> ADC_CCR_PRESC_Pos) - 3UL));
+        /* Divide variable by 2 to compensate partially CPU processing cycles */
+        delay_cpu_cycles >>= 1UL;
+
+        while (delay_cpu_cycles != 0UL)
+        {
+          delay_cpu_cycles--;
+        }
+      }
+    }
+
+    LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated);
+    LL_ADC_Disable(hadc->Instance);
+
+    /* Wait for ADC effectively disabled before changing configuration */
+    /* Get tick count */
+    tickstart = HAL_GetTick();
+
+    while (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+    {
+      if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
+      {
+        /* New check to avoid false timeout detection in case of preemption */
+        if (LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+        {
+          /* Update ADC state machine to error */
+          SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+          /* Set ADC error code to ADC peripheral internal error */
+          SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+          return HAL_ERROR;
+        }
+      }
+    }
+
+    /* Restore configuration after calibration */
+    SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1);
+
+    /* Set ADC state */
+    ADC_STATE_CLR_SET(hadc->State,
+                      HAL_ADC_STATE_BUSY_INTERNAL,
+                      HAL_ADC_STATE_READY);
+  }
+  else
+  {
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
+
+    /* Note: No need to update variable "tmp_hal_status" here: already set    */
+    /*       to state "HAL_ERROR" by function disabling the ADC.              */
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Get the calibration factor.
+  * @param hadc ADC handle.
+  * @retval Calibration value.
+  */
+uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Return the selected ADC calibration value */
+  return ((hadc->Instance->CALFACT) & 0x0000007FU);
+}
+
+/**
+  * @brief  Set the calibration factor to overwrite automatic conversion result.
+  *         ADC must be enabled and no conversion is ongoing.
+  * @param hadc ADC handle
+  * @param CalibrationFactor Calibration factor (coded on 7 bits maximum)
+  * @retval HAL state
+  */
+HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor)
+{
+  HAL_StatusTypeDef tmp_hal_status = HAL_OK;
+  uint32_t tmp_adc_is_conversion_on_going_regular;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+  assert_param(IS_ADC_CALFACT(CalibrationFactor));
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
+
+  /* Verification of hardware constraints before modifying the calibration    */
+  /* factors register: ADC must be enabled, no conversion on going.           */
+  tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
+
+  if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
+      && (tmp_adc_is_conversion_on_going_regular == 0UL)
+     )
+  {
+    hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT;
+    hadc->Instance->CALFACT |= CalibrationFactor;
+  }
+  else
+  {
+    /* Update ADC state machine */
+    SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
+    /* Update ADC error code */
+    SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
+
+    /* Update ADC state machine to error */
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  /* Process unlocked */
+  __HAL_UNLOCK(hadc);
+
+  /* Return function status */
+  return tmp_hal_status;
+}
+
+/**
+  * @brief  Analog watchdog 2 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  Analog watchdog 3 callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file.
+  */
+}
+
+
+/**
+  * @brief  End Of Sampling callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @brief  ADC channel configuration ready callback in non-blocking mode.
+  * @param hadc ADC handle
+  * @retval None
+  */
+__weak void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hadc);
+
+  /* NOTE : This function should not be modified. When the callback is needed,
+            function HAL_ADCEx_ChannelConfigReadyCallback must be implemented in the user file.
+  */
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Disable ADC voltage regulator.
+  * @note   Disabling voltage regulator allows to save power. This operation can
+  *         be carried out only when ADC is disabled.
+  * @note   To enable again the voltage regulator, the user is expected to
+  *         resort to HAL_ADC_Init() API.
+  * @param hadc ADC handle
+  * @retval HAL status
+  */
+HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc)
+{
+  HAL_StatusTypeDef tmp_hal_status;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
+
+  /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */
+  if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
+  {
+    LL_ADC_DisableInternalRegulator(hadc->Instance);
+    tmp_hal_status = HAL_OK;
+  }
+  else
+  {
+    tmp_hal_status = HAL_ERROR;
+  }
+
+  return tmp_hal_status;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif /* HAL_ADC_MODULE_ENABLED */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
diff --git a/code/feeder_mk2.ioc b/code/feeder_mk2.ioc
index ed15e1c..b1707b8 100644
--- a/code/feeder_mk2.ioc
+++ b/code/feeder_mk2.ioc
@@ -1,4 +1,8 @@
 #MicroXplorer Configuration settings - do not modify
+ADC1.IPParameters=NbrOfConversionFlag,master,SelectedChannel
+ADC1.NbrOfConversionFlag=0
+ADC1.SelectedChannel=ADC_CHANNEL_7|ADC_CHANNEL_22
+ADC1.master=1
 CAD.formats=[]
 CAD.pinconfig=Dual
 CAD.provider=
@@ -44,51 +48,54 @@ GPIO.groupedBy=Group By Peripherals
 KeepUserPlacement=false
 Mcu.CPN=STM32C051C6T6
 Mcu.Family=STM32C0
-Mcu.IP0=CORTEX_M0+
-Mcu.IP1=DEBUG
-Mcu.IP10=TIM17
-Mcu.IP11=USART1
-Mcu.IP12=USART2
-Mcu.IP2=DMA
-Mcu.IP3=NVIC
-Mcu.IP4=RCC
-Mcu.IP5=SYS
-Mcu.IP6=TIM1
-Mcu.IP7=TIM3
-Mcu.IP8=TIM14
-Mcu.IP9=TIM16
-Mcu.IPNb=13
+Mcu.IP0=ADC1
+Mcu.IP1=CORTEX_M0+
+Mcu.IP10=TIM16
+Mcu.IP11=TIM17
+Mcu.IP12=USART1
+Mcu.IP13=USART2
+Mcu.IP2=DEBUG
+Mcu.IP3=DMA
+Mcu.IP4=NVIC
+Mcu.IP5=RCC
+Mcu.IP6=SYS
+Mcu.IP7=TIM1
+Mcu.IP8=TIM3
+Mcu.IP9=TIM14
+Mcu.IPNb=14
 Mcu.Name=STM32C051C6Tx
 Mcu.Package=LQFP48
 Mcu.Pin0=PF0-OSC_IN(PF0)
 Mcu.Pin1=PF1-OSC_OUT(PF1)
-Mcu.Pin10=PA9
-Mcu.Pin11=PC6
-Mcu.Pin12=PC7
-Mcu.Pin13=PA10
-Mcu.Pin14=PA13
-Mcu.Pin15=PA14-BOOT0
-Mcu.Pin16=PB3
-Mcu.Pin17=PB4
-Mcu.Pin18=PB5
-Mcu.Pin19=PB6
+Mcu.Pin10=PA7
+Mcu.Pin11=PB12
+Mcu.Pin12=PA8
+Mcu.Pin13=PA9
+Mcu.Pin14=PC6
+Mcu.Pin15=PC7
+Mcu.Pin16=PA13
+Mcu.Pin17=PA14-BOOT0
+Mcu.Pin18=PB3
+Mcu.Pin19=PB4
 Mcu.Pin2=PF2-NRST
-Mcu.Pin20=PB7
-Mcu.Pin21=PB8
-Mcu.Pin22=PB9
-Mcu.Pin23=VP_SYS_VS_Systick
-Mcu.Pin24=VP_TIM1_VS_ClockSourceINT
-Mcu.Pin25=VP_TIM14_VS_ClockSourceINT
-Mcu.Pin26=VP_TIM16_VS_ClockSourceINT
-Mcu.Pin27=VP_TIM17_VS_ClockSourceINT
+Mcu.Pin20=PB5
+Mcu.Pin21=PB6
+Mcu.Pin22=PB7
+Mcu.Pin23=PB8
+Mcu.Pin24=PB9
+Mcu.Pin25=VP_SYS_VS_Systick
+Mcu.Pin26=VP_TIM1_VS_ClockSourceINT
+Mcu.Pin27=VP_TIM14_VS_ClockSourceINT
+Mcu.Pin28=VP_TIM16_VS_ClockSourceINT
+Mcu.Pin29=VP_TIM17_VS_ClockSourceINT
 Mcu.Pin3=PA0
 Mcu.Pin4=PA1
 Mcu.Pin5=PA2
 Mcu.Pin6=PA3
 Mcu.Pin7=PA4
 Mcu.Pin8=PA5
-Mcu.Pin9=PA8
-Mcu.PinsNb=28
+Mcu.Pin9=PA6
+Mcu.PinsNb=30
 Mcu.ThirdPartyNb=0
 Mcu.UserConstants=
 Mcu.UserName=STM32C051C6Tx
@@ -106,6 +113,7 @@ NVIC.SysTick_IRQn=true\:3\:0\:false\:false\:true\:false\:true\:false
 NVIC.TIM14_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
 NVIC.TIM16_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
 NVIC.TIM17_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
+NVIC.USART2_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true
 PA0.GPIOParameters=GPIO_Label
 PA0.GPIO_Label=USART2_NRE
 PA0.Locked=true
@@ -113,10 +121,6 @@ PA0.Signal=GPIO_Output
 PA1.Locked=true
 PA1.Mode=Hardware Flow Control (RS485)
 PA1.Signal=USART2_DE
-PA10.GPIOParameters=GPIO_Label
-PA10.GPIO_Label=ONEWIRE
-PA10.Locked=true
-PA10.Signal=GPIO_Output
 PA13.Locked=true
 PA13.Mode=Serial_Wire
 PA13.Signal=DEBUG_SWDIO
@@ -137,6 +141,17 @@ PA4.Signal=USART2_TX
 PA5.Locked=true
 PA5.Mode=Asynchronous
 PA5.Signal=USART2_RX
+PA6.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultOutputPP
+PA6.GPIO_Label=ONEWIRE
+PA6.GPIO_ModeDefaultOutputPP=GPIO_MODE_OUTPUT_OD
+PA6.GPIO_PuPd=GPIO_NOPULL
+PA6.Locked=true
+PA6.Signal=GPIO_Output
+PA7.GPIOParameters=GPIO_Label
+PA7.GPIO_Label=IPROP_PEEL
+PA7.Locked=true
+PA7.Mode=IN7
+PA7.Signal=ADC1_IN7
 PA8.GPIOParameters=GPIO_Label
 PA8.GPIO_Label=DRIVE1
 PA8.Locked=true
@@ -145,6 +160,11 @@ PA9.GPIOParameters=GPIO_Label
 PA9.GPIO_Label=DRIVE2
 PA9.Locked=true
 PA9.Signal=S_TIM1_CH2
+PB12.GPIOParameters=GPIO_Label
+PB12.GPIO_Label=IPROP_DRIVE
+PB12.Locked=true
+PB12.Mode=IN22
+PB12.Signal=ADC1_IN22
 PB3.GPIOParameters=GPIO_Label
 PB3.GPIO_Label=LED_R
 PB3.Locked=true
@@ -276,9 +296,11 @@ TIM3.IPParameters=EncoderMode
 USART1.IPParameters=VirtualMode-Asynchronous
 USART1.VirtualMode-Asynchronous=VM_ASYNC
 USART2.BaudRate=57600
-USART2.IPParameters=VirtualMode-Asynchronous,VirtualMode-Hardware Flow Control (RS485),BaudRate,TXFIFOThreshold,RXFIFOThreshold
+USART2.IPParameters=VirtualMode-Asynchronous,VirtualMode-Hardware Flow Control (RS485),BaudRate,TXFIFOThreshold,RXFIFOThreshold,UART_DEAssertionTime,UART_DEDeassertionTime
 USART2.RXFIFOThreshold=RXFIFO_THRESHOLD_HALFFULL
 USART2.TXFIFOThreshold=TXFIFO_THRESHOLD_HALFFULL
+USART2.UART_DEAssertionTime=31
+USART2.UART_DEDeassertionTime=31
 USART2.VirtualMode-Asynchronous=VM_ASYNC
 USART2.VirtualMode-Hardware\ Flow\ Control\ (RS485)=VM_ASYNC
 VP_SYS_VS_Systick.Mode=SysTick
diff --git a/code/tools/__pycache__/feeder_monitor.cpython-313.pyc b/code/tools/__pycache__/feeder_monitor.cpython-313.pyc
new file mode 100644
index 0000000..dfe68a7
Binary files /dev/null and b/code/tools/__pycache__/feeder_monitor.cpython-313.pyc differ
diff --git a/code/tools/feeder_monitor.py b/code/tools/feeder_monitor.py
index ef6c55b..681b5ca 100644
--- a/code/tools/feeder_monitor.py
+++ b/code/tools/feeder_monitor.py
@@ -1,24 +1,25 @@
 #!/usr/bin/env python3
 """
-Photon Feeder Mk2 Serial Debug Monitor
-Console-based GUI for monitoring feeder diagnostics via USART1
+Photon Feeder Mk2 Serial Debug Monitor (Textual TUI)
 
 Usage: python feeder_monitor.py [COM_PORT] [BAUD_RATE]
        python feeder_monitor.py COM3
        python feeder_monitor.py /dev/ttyUSB0 115200
+       python feeder_monitor.py              (auto-detect)
 
 Controls:
-  q - Quit
-  c - Clear screen
-  p - Pause/Resume display
-  r - Reset statistics
+  q     - Quit
+  c     - Clear statistics
+  p     - Pause/Resume display
+  space - Toggle raw packet log
 """
 
+from __future__ import annotations
+
 import sys
-import os
 import time
-import threading
 from collections import deque
+from dataclasses import dataclass, field
 
 try:
     import serial
@@ -27,407 +28,619 @@ except ImportError:
     print("Error: pyserial not installed. Run: pip install pyserial")
     sys.exit(1)
 
-# ANSI color codes
-class Colors:
-    RESET = '\033[0m'
-    BOLD = '\033[1m'
-    RED = '\033[91m'
-    GREEN = '\033[92m'
-    YELLOW = '\033[93m'
-    BLUE = '\033[94m'
-    MAGENTA = '\033[95m'
-    CYAN = '\033[96m'
-    WHITE = '\033[97m'
-    DIM = '\033[2m'
+try:
+    from textual.app import App, ComposeResult
+    from textual.binding import Binding
+    from textual.containers import Horizontal, Vertical
+    from textual.reactive import reactive
+    from textual.widgets import Footer, Header, Label, RichLog, Sparkline, Static
+    from textual import work
+    from rich.text import Text
+except ImportError:
+    print("Error: textual not installed. Run: pip install textual")
+    sys.exit(1)
 
-# Enable ANSI on Windows
-if os.name == 'nt':
-    os.system('')
+# ============================================================================
+# Constants
+# ============================================================================
 
-def clear_screen():
-    os.system('cls' if os.name == 'nt' else 'clear')
+PWM_MAX = 2400
+BAUD_DEFAULT = 115200
+SPARKLINE_LEN = 200
 
-def move_cursor(row, col):
-    print(f'\033[{row};{col}H', end='')
+STATE_INFO = {
+    0: ("IDLE",      "dim"),
+    1: ("PEEL_FWD",  "#e5c07b"),
+    2: ("PEEL_BACK", "#e5c07b"),
+    3: ("UNPEEL",    "#e5c07b"),
+    4: ("DRIVING",   "#98c379"),
+    5: ("SLACK_REM", "#e5c07b"),
+    6: ("BACKLASH",  "#e5c07b"),
+    7: ("SETTLING",  "#56b6c2"),
+    8: ("COMPLETE",  "dim"),
+}
 
-def hide_cursor():
-    print('\033[?25l', end='')
+STATE_ABBREV = ["IDL", "PEF", "PEB", "UNP", "DRV", "SLK", "BAC", "SET", "CMP"]
 
-def show_cursor():
-    print('\033[?25h', end='')
+# ============================================================================
+# Data Model
+# ============================================================================
+
+@dataclass
+class FeederData:
+    position: int = 0
+    target: int = 0
+    error: int = 0
+    pid_output: int = 0
+    state: int = 0
+    is_initialized: bool = False
+    feed_in_progress: bool = False
+    beefy_tape: bool = False
+    address: str = "FF"
+    feed_ok_count: int = 0
+    feed_fail_count: int = 0
+    brake_time_tenths: int = 30
+    feed_retries: int = 0
+    crc_drops: int = 0
+    msg_handled: int = 0
+    uart_errors: int = 0
+    trap_size: int = 0
+    trap_hex: str = ""
+    trap_crc: str = ""
+    # Optional fields (may be absent)
+    sw1_pressed: bool = False
+    sw2_pressed: bool = False
+    drive_value: int = 0
+    drive_mode: int = 0
+    has_buttons: bool = False
+    has_drive: bool = False
+    has_mode: bool = False
 
 
-class FeederMonitor:
-    def __init__(self, port, baudrate=115200):
-        self.port = port
-        self.baudrate = baudrate
-        self.serial = None
-        self.running = False
-        self.paused = False
+class Statistics:
+    def __init__(self):
+        self.clear()
 
-        # Current data
-        self.position = 0
-        self.target = 0
-        self.error = 0
-        self.pid_output = 0
-        self.state = "UNKNOWN"
-        self.is_initialized = False
-        self.feed_in_progress = False
-        self.beefy_tape = False
-        self.address = 0xFF
-        self.sw1_pressed = False
-        self.sw2_pressed = False
-        self.drive_value = 0
-        self.drive_mode = 0
-
-        # Statistics
+    def clear(self):
         self.packet_count = 0
-        self.error_count = 0
+        self.parse_errors = 0
         self.start_time = time.time()
-        self.last_packet_time = 0
-        self.max_error = 0
-        self.min_error = 0
+        self.last_packet_time = 0.0
+        self.error_history: deque[float] = deque(maxlen=SPARKLINE_LEN)
+        self.pid_history: deque[float] = deque(maxlen=SPARKLINE_LEN)
 
-        # History for sparkline
-        self.error_history = deque(maxlen=50)
-        self.pid_history = deque(maxlen=50)
+    def update(self, data: FeederData):
+        self.packet_count += 1
+        self.last_packet_time = time.time()
+        self.error_history.append(float(data.error))
+        self.pid_history.append(float(data.pid_output))
 
-        # Lock for thread safety
-        self.lock = threading.Lock()
+    @property
+    def packet_rate(self) -> float:
+        elapsed = time.time() - self.start_time
+        return self.packet_count / elapsed if elapsed > 0 else 0
 
-    def connect(self):
-        try:
-            self.serial = serial.Serial(
-                port=self.port,
-                baudrate=self.baudrate,
-                timeout=0.1,
-                bytesize=serial.EIGHTBITS,
-                parity=serial.PARITY_NONE,
-                stopbits=serial.STOPBITS_ONE
-            )
-            return True
-        except serial.SerialException as e:
-            print(f"{Colors.RED}Error opening port {self.port}: {e}{Colors.RESET}")
-            return False
+    @property
+    def connection_age(self) -> float:
+        if self.last_packet_time == 0:
+            return 999.0
+        return time.time() - self.last_packet_time
 
-    def disconnect(self):
-        if self.serial and self.serial.is_open:
-            self.serial.close()
 
-    def parse_packet(self, line):
-        """Parse debug packet: $P:pos:tgt:err,I:pid,S:state,F:flags,A:addr,B:btns,D:drv*"""
-        try:
-            if not line.startswith('$') or not '*' in line:
-                return False
+# ============================================================================
+# Packet Parser
+# ============================================================================
 
-            # Remove $ and * markers
-            line = line[1:line.index('*')]
-
-            # State number to name mapping
-            state_names = {
-                0: "IDLE", 1: "PEEL_FWD", 2: "PEEL_BACK", 3: "UNPEEL",
-                4: "DRIVING", 5: "SLACK_REM", 6: "BACKLASH", 7: "SETTLING",
-                8: "COMPLETE", 9: "TIMEOUT"
-            }
-
-            parts = line.split(',')
-            for part in parts:
-                if part.startswith('P:'):
-                    values = part[2:].split(':')
-                    if len(values) >= 3:
-                        self.position = int(values[0])
-                        self.target = int(values[1])
-                        self.error = int(values[2])
-                        self.error_history.append(self.error)
-                        if abs(self.error) > abs(self.max_error):
-                            self.max_error = self.error
-                        if self.error < self.min_error:
-                            self.min_error = self.error
-
-                elif part.startswith('I:'):
-                    self.pid_output = int(part[2:])
-                    self.pid_history.append(self.pid_output)
-
-                elif part.startswith('S:'):
-                    state_num = int(part[2:])
-                    self.state = state_names.get(state_num, f"UNK({state_num})")
-
-                elif part.startswith('F:'):
+def parse_packet(line: str) -> FeederData | None:
+    try:
+        if not line.startswith("$") or "*" not in line:
+            return None
+        body = line[1:line.index("*")]
+        data = FeederData()
+        parts = body.split(",")
+        for part in parts:
+            try:
+                if part.startswith("P:"):
+                    vals = part[2:].split(":")
+                    if len(vals) >= 3:
+                        data.position = int(vals[0])
+                        data.target = int(vals[1])
+                        data.error = int(vals[2])
+                elif part.startswith("I:"):
+                    data.pid_output = int(part[2:])
+                elif part.startswith("S:"):
+                    data.state = int(part[2:])
+                elif part.startswith("F:"):
                     flags = part[2:]
+                    if len(flags) >= 2:
+                        data.is_initialized = flags[0] == "1"
+                        data.feed_in_progress = flags[1] == "1"
                     if len(flags) >= 3:
-                        self.is_initialized = flags[0] == '1'
-                        self.feed_in_progress = flags[1] == '1'
-                        self.beefy_tape = flags[2] == '1'
-
-                elif part.startswith('A:'):
-                    self.address = int(part[2:], 16)
-
-                elif part.startswith('B:'):
+                        data.beefy_tape = flags[2] == "1"
+                elif part.startswith("C:"):
+                    vals = part[2:].split(":")
+                    if len(vals) >= 2:
+                        data.feed_ok_count = int(vals[0])
+                        data.feed_fail_count = int(vals[1])
+                    if len(vals) >= 3:
+                        data.brake_time_tenths = int(vals[2])
+                    if len(vals) >= 4:
+                        data.feed_retries = int(vals[3])
+                elif part.startswith("A:"):
+                    data.address = part[2:]
+                elif part.startswith("R:"):
+                    vals = part[2:].split(":")
+                    if len(vals) >= 3:
+                        data.crc_drops = int(vals[0])
+                        data.msg_handled = int(vals[1])
+                        data.uart_errors = int(vals[2])
+                elif part.startswith("T:"):
+                    vals = part[2:].split(":")
+                    if len(vals) >= 1:
+                        data.trap_size = int(vals[0])
+                    if len(vals) >= 2:
+                        data.trap_hex = vals[1]
+                    if len(vals) >= 3:
+                        data.trap_crc = vals[2]
+                elif part.startswith("B:"):
                     btns = part[2:]
                     if len(btns) >= 2:
-                        self.sw1_pressed = btns[0] == '1'
-                        self.sw2_pressed = btns[1] == '1'
-
-                elif part.startswith('D:'):
-                    self.drive_value = int(part[2:])
-
-                elif part.startswith('M:'):
-                    self.drive_mode = int(part[2:])
-
-            self.packet_count += 1
-            self.last_packet_time = time.time()
-            return True
-
-        except (ValueError, IndexError) as e:
-            self.error_count += 1
-            return False
-
-    def read_thread(self):
-        """Background thread for reading serial data"""
-        buffer = ""
-        while self.running:
-            try:
-                if self.serial and self.serial.in_waiting:
-                    data = self.serial.read(self.serial.in_waiting)
-                    buffer += data.decode('utf-8', errors='ignore')
-
-                    while '\n' in buffer:
-                        line, buffer = buffer.split('\n', 1)
-                        line = line.strip()
-                        if line:
-                            with self.lock:
-                                self.parse_packet(line)
-                else:
-                    time.sleep(0.01)
-            except Exception as e:
-                time.sleep(0.1)
-
-    def make_sparkline(self, data, width=40, min_val=None, max_val=None):
-        """Create a text sparkline from data"""
-        if not data:
-            return ' ' * width
-
-        chars = '▁▂▃▄▅▆▇█'
-
-        if min_val is None:
-            min_val = min(data)
-        if max_val is None:
-            max_val = max(data)
-
-        if max_val == min_val:
-            return chars[4] * min(len(data), width)
-
-        result = []
-        step = max(1, len(data) // width)
-        for i in range(0, min(len(data), width * step), step):
-            val = data[min(i, len(data)-1)]
-            normalized = (val - min_val) / (max_val - min_val)
-            idx = min(int(normalized * (len(chars) - 1)), len(chars) - 1)
-            result.append(chars[idx])
-
-        return ''.join(result).ljust(width)
-
-    def make_bar(self, value, max_value, width=20, char='█'):
-        """Create a progress bar"""
-        if max_value == 0:
-            return ' ' * width
-        ratio = min(abs(value) / max_value, 1.0)
-        filled = int(ratio * width)
-        return (char * filled).ljust(width)
-
-    def display(self):
-        """Display the monitor interface"""
-        move_cursor(1, 1)
-
-        uptime = time.time() - self.start_time
-        pkt_rate = self.packet_count / uptime if uptime > 0 else 0
-        last_pkt_ago = time.time() - self.last_packet_time if self.last_packet_time > 0 else 999
-
-        with self.lock:
-            # Header
-            print(f"{Colors.BOLD}{Colors.CYAN}╔══════════════════════════════════════════════════════════════════════╗{Colors.RESET}")
-            print(f"{Colors.BOLD}{Colors.CYAN}║{Colors.WHITE}          PHOTON FEEDER Mk2 DEBUG MONITOR                             {Colors.CYAN}║{Colors.RESET}")
-            print(f"{Colors.BOLD}{Colors.CYAN}╠══════════════════════════════════════════════════════════════════════╣{Colors.RESET}")
-
-            # Connection status
-            conn_color = Colors.GREEN if last_pkt_ago < 1 else (Colors.YELLOW if last_pkt_ago < 5 else Colors.RED)
-            conn_status = "CONNECTED" if last_pkt_ago < 5 else "NO DATA"
-            print(f"{Colors.CYAN}║{Colors.RESET} Port: {Colors.YELLOW}{self.port:10}{Colors.RESET} @ {self.baudrate} baud  │  Status: {conn_color}{conn_status:10}{Colors.RESET}  {Colors.CYAN}║{Colors.RESET}")
-
-            print(f"{Colors.CYAN}╠══════════════════════════════════════════════════════════════════════╣{Colors.RESET}")
-
-            # Position section
-            print(f"{Colors.CYAN}║{Colors.RESET} {Colors.BOLD}POSITION{Colors.RESET}                                                             {Colors.CYAN}║{Colors.RESET}")
-            print(f"{Colors.CYAN}║{Colors.RESET}   Current: {Colors.GREEN}{self.position:>10}{Colors.RESET}  Target: {Colors.YELLOW}{self.target:>10}{Colors.RESET}  Error: {Colors.RED if abs(self.error) > 10 else Colors.GREEN}{self.error:>8}{Colors.RESET}   {Colors.CYAN}║{Colors.RESET}")
-
-            # Error sparkline
-            err_spark = self.make_sparkline(list(self.error_history), 50)
-            print(f"{Colors.CYAN}║{Colors.RESET}   Error:  [{Colors.DIM}{err_spark}{Colors.RESET}]        {Colors.CYAN}║{Colors.RESET}")
-
-            print(f"{Colors.CYAN}╠══════════════════════════════════════════════════════════════════════╣{Colors.RESET}")
-
-            # PID section
-            print(f"{Colors.CYAN}║{Colors.RESET} {Colors.BOLD}PID CONTROL{Colors.RESET}                                                          {Colors.CYAN}║{Colors.RESET}")
-            pid_color = Colors.GREEN if self.pid_output >= 0 else Colors.RED
-            pid_dir = "FWD" if self.pid_output >= 0 else "REV"
-            print(f"{Colors.CYAN}║{Colors.RESET}   Output: {pid_color}{self.pid_output:>6}{Colors.RESET} ({pid_dir})   Drive Value: {Colors.YELLOW}{self.drive_value:>3}{Colors.RESET}                     {Colors.CYAN}║{Colors.RESET}")
-
-            # PID sparkline
-            pid_spark = self.make_sparkline(list(self.pid_history), 50, -2400, 2400)
-            print(f"{Colors.CYAN}║{Colors.RESET}   Output: [{Colors.DIM}{pid_spark}{Colors.RESET}]        {Colors.CYAN}║{Colors.RESET}")
-
-            # PWM bar
-            pwm_bar = self.make_bar(self.pid_output, 2400, 30)
-            pwm_pct = abs(self.pid_output) / 2400 * 100
-            print(f"{Colors.CYAN}║{Colors.RESET}   PWM:    [{pid_color}{pwm_bar}{Colors.RESET}] {pwm_pct:5.1f}%               {Colors.CYAN}║{Colors.RESET}")
-
-            print(f"{Colors.CYAN}╠══════════════════════════════════════════════════════════════════════╣{Colors.RESET}")
-
-            # State section
-            print(f"{Colors.CYAN}║{Colors.RESET} {Colors.BOLD}FEED STATE{Colors.RESET}                                                           {Colors.CYAN}║{Colors.RESET}")
-
-            state_color = Colors.GREEN if self.state == "IDLE" else (Colors.YELLOW if self.state == "DRIVING" else Colors.CYAN)
-            print(f"{Colors.CYAN}║{Colors.RESET}   State: {state_color}{self.state:15}{Colors.RESET}                                      {Colors.CYAN}║{Colors.RESET}")
-
-            # State indicators
-            states = ["IDLE", "PEEL_FWD", "PEEL_BACK", "UNPEEL", "DRIVING", "SLACK_REM", "BACKLASH", "SETTLING"]
-            state_line = "   "
-            for s in states:
-                if s == self.state:
-                    state_line += f"{Colors.GREEN}[{s[:3]}]{Colors.RESET} "
-                else:
-                    state_line += f"{Colors.DIM}[{s[:3]}]{Colors.RESET} "
-            print(f"{Colors.CYAN}║{Colors.RESET}{state_line}    {Colors.CYAN}║{Colors.RESET}")
-
-            print(f"{Colors.CYAN}╠══════════════════════════════════════════════════════════════════════╣{Colors.RESET}")
-
-            # Flags section
-            print(f"{Colors.CYAN}║{Colors.RESET} {Colors.BOLD}STATUS FLAGS{Colors.RESET}                                                         {Colors.CYAN}║{Colors.RESET}")
-
-            init_icon = f"{Colors.GREEN}●{Colors.RESET}" if self.is_initialized else f"{Colors.RED}○{Colors.RESET}"
-            feed_icon = f"{Colors.YELLOW}●{Colors.RESET}" if self.feed_in_progress else f"{Colors.DIM}○{Colors.RESET}"
-            beefy_icon = f"{Colors.MAGENTA}●{Colors.RESET}" if self.beefy_tape else f"{Colors.DIM}○{Colors.RESET}"
-
-            mode_str = f"{Colors.YELLOW}PEEL{Colors.RESET}" if self.drive_mode else f"{Colors.BLUE}TAPE{Colors.RESET}"
-            print(f"{Colors.CYAN}║{Colors.RESET}   {init_icon} Initialized   {feed_icon} Feeding   {beefy_icon} Beefy Tape   Mode: {mode_str}     {Colors.CYAN}║{Colors.RESET}")
-
-            # Address and buttons
-            addr_str = f"0x{self.address:02X}" if self.address != 0xFF else "UNSET"
-            sw1_icon = f"{Colors.GREEN}[SW1]{Colors.RESET}" if self.sw1_pressed else f"{Colors.DIM}[SW1]{Colors.RESET}"
-            sw2_icon = f"{Colors.GREEN}[SW2]{Colors.RESET}" if self.sw2_pressed else f"{Colors.DIM}[SW2]{Colors.RESET}"
-
-            print(f"{Colors.CYAN}║{Colors.RESET}   Address: {Colors.YELLOW}{addr_str:6}{Colors.RESET}     Buttons: {sw1_icon} {sw2_icon}                    {Colors.CYAN}║{Colors.RESET}")
-
-            print(f"{Colors.CYAN}╠══════════════════════════════════════════════════════════════════════╣{Colors.RESET}")
-
-            # Statistics
-            print(f"{Colors.CYAN}║{Colors.RESET} {Colors.BOLD}STATISTICS{Colors.RESET}                                                           {Colors.CYAN}║{Colors.RESET}")
-            print(f"{Colors.CYAN}║{Colors.RESET}   Packets: {Colors.GREEN}{self.packet_count:>8}{Colors.RESET}  Errors: {Colors.RED}{self.error_count:>5}{Colors.RESET}  Rate: {Colors.CYAN}{pkt_rate:>5.1f}{Colors.RESET}/s           {Colors.CYAN}║{Colors.RESET}")
-            print(f"{Colors.CYAN}║{Colors.RESET}   Max Err: {Colors.RED}{self.max_error:>8}{Colors.RESET}  Min Err: {Colors.RED}{self.min_error:>8}{Colors.RESET}                      {Colors.CYAN}║{Colors.RESET}")
-
-            print(f"{Colors.CYAN}╠══════════════════════════════════════════════════════════════════════╣{Colors.RESET}")
-
-            # Controls
-            pause_status = f"{Colors.YELLOW}PAUSED{Colors.RESET}" if self.paused else ""
-            print(f"{Colors.CYAN}║{Colors.RESET} {Colors.DIM}[Q]uit  [C]lear  [P]ause  [R]eset Stats{Colors.RESET}  {pause_status:20}              {Colors.CYAN}║{Colors.RESET}")
-            print(f"{Colors.CYAN}╚══════════════════════════════════════════════════════════════════════╝{Colors.RESET}")
-
-        sys.stdout.flush()
-
-    def reset_stats(self):
-        with self.lock:
-            self.packet_count = 0
-            self.error_count = 0
-            self.start_time = time.time()
-            self.max_error = 0
-            self.min_error = 0
-            self.error_history.clear()
-            self.pid_history.clear()
-
-    def run(self):
-        if not self.connect():
-            return
-
-        self.running = True
-
-        # Start read thread
-        read_thread = threading.Thread(target=self.read_thread, daemon=True)
-        read_thread.start()
-
-        # Setup terminal
-        clear_screen()
-        hide_cursor()
-
-        # Input handling (non-blocking on Windows requires msvcrt)
-        if os.name == 'nt':
-            import msvcrt
-            def get_key():
-                if msvcrt.kbhit():
-                    return msvcrt.getch().decode('utf-8', errors='ignore').lower()
-                return None
-        else:
-            import select
-            import tty
-            import termios
-            old_settings = termios.tcgetattr(sys.stdin)
-            tty.setcbreak(sys.stdin.fileno())
-            def get_key():
-                if select.select([sys.stdin], [], [], 0)[0]:
-                    return sys.stdin.read(1).lower()
-                return None
-
-        try:
-            while self.running:
-                # Handle input
-                key = get_key()
-                if key == 'q':
-                    self.running = False
-                elif key == 'c':
-                    clear_screen()
-                elif key == 'p':
-                    self.paused = not self.paused
-                elif key == 'r':
-                    self.reset_stats()
-
-                # Update display
-                if not self.paused:
-                    self.display()
-
-                time.sleep(0.1)
-
-        except KeyboardInterrupt:
-            pass
-        finally:
-            self.running = False
-            show_cursor()
-            if os.name != 'nt':
-                termios.tcsetattr(sys.stdin, termios.TCSADRAIN, old_settings)
-            self.disconnect()
-            print(f"\n{Colors.CYAN}Disconnected from {self.port}{Colors.RESET}")
-
-
-def list_ports():
-    """List available serial ports"""
-    ports = serial.tools.list_ports.comports()
-    if not ports:
-        print(f"{Colors.YELLOW}No serial ports found{Colors.RESET}")
+                        data.sw1_pressed = btns[0] == "1"
+                        data.sw2_pressed = btns[1] == "1"
+                        data.has_buttons = True
+                elif part.startswith("G:"):
+                    pass  # GPIO raw state, not displayed
+                elif part.startswith("D:"):
+                    data.drive_value = int(part[2:])
+                    data.has_drive = True
+                elif part.startswith("M:"):
+                    data.drive_mode = int(part[2:])
+                    data.has_mode = True
+            except (ValueError, IndexError):
+                continue
+        return data
+    except Exception:
         return None
 
-    print(f"\n{Colors.CYAN}Available serial ports:{Colors.RESET}")
-    for i, port in enumerate(ports):
-        print(f"  {i+1}. {Colors.GREEN}{port.device}{Colors.RESET} - {port.description}")
 
-    print()
-    return ports
+# ============================================================================
+# Auto-detect COM port
+# ============================================================================
 
+def auto_detect_port() -> str | None:
+    ports = serial.tools.list_ports.comports()
+    keywords = ["CH340", "CH341", "USB-SERIAL", "FTDI", "CP210", "SILICON", "STM"]
+    for port in ports:
+        desc = (port.description or "").upper()
+        for kw in keywords:
+            if kw in desc:
+                return port.device
+    if len(ports) == 1:
+        return ports[0].device
+    return None
+
+
+# ============================================================================
+# Custom Widgets
+# ============================================================================
+
+class PWMBar(Static):
+    """Horizontal bar showing motor PWM output and direction."""
+
+    value: reactive[int] = reactive(0)
+
+    def render(self) -> Text:
+        width = max(self.size.width - 12, 10)
+        pct = min(abs(self.value) / PWM_MAX, 1.0) * 100
+        filled = int(abs(self.value) / PWM_MAX * width)
+        direction = "FWD" if self.value >= 0 else "REV"
+        color = "green" if self.value >= 0 else "red"
+        bar = "\u2588" * filled + "\u2591" * (width - filled)
+        return Text.assemble(
+            (f"{direction} ", color),
+            (bar[:filled], color),
+            (bar[filled:], "dim"),
+            f" {pct:5.1f}%",
+        )
+
+
+class ConnectionIndicator(Static):
+    """Shows connection status with colored dot."""
+
+    status: reactive[str] = reactive("disconnected")
+
+    def render(self) -> Text:
+        if self.status == "connected":
+            return Text.assemble(("\u25cf ", "green"), ("CONNECTED", "green"))
+        elif self.status == "stale":
+            return Text.assemble(("\u25cf ", "yellow"), ("STALE", "yellow"))
+        elif self.status == "no_data":
+            return Text.assemble(("\u25cf ", "red"), ("NO DATA", "red"))
+        else:
+            return Text.assemble(("\u25cf ", "red"), ("DISCONNECTED", "red"))
+
+
+class FlagIndicator(Static):
+    """Shows a labeled boolean flag."""
+
+    active: reactive[bool] = reactive(False)
+    label_text: str = ""
+
+    def __init__(self, label_text: str, **kwargs):
+        super().__init__(**kwargs)
+        self.label_text = label_text
+
+    def render(self) -> Text:
+        dot = "\u25cf" if self.active else "\u25cb"
+        color = "green" if self.active else "dim"
+        return Text.assemble((f"{dot} ", color), (self.label_text, color))
+
+
+class StateDisplay(Static):
+    """Shows the current feed state with color coding and indicator row."""
+
+    state: reactive[int] = reactive(0)
+
+    def render(self) -> Text:
+        name, color = STATE_INFO.get(self.state, ("UNKNOWN", "red"))
+        parts: list = [(f"  \u25b6 {name}\n", f"bold {color}")]
+        # Indicator row
+        for i, abbrev in enumerate(STATE_ABBREV):
+            if i == self.state:
+                parts.append((f"[{abbrev}]", f"bold {STATE_INFO.get(i, ('', 'white'))[1]}"))
+            else:
+                parts.append((f" {abbrev} ", "dim"))
+            parts.append((" ", ""))
+        return Text.assemble(*parts)
+
+
+# ============================================================================
+# Main App
+# ============================================================================
+
+class FeederMonitorApp(App):
+    TITLE = "Photon Feeder Mk2 Monitor"
+    BINDINGS = [
+        Binding("q", "quit", "Quit"),
+        Binding("c", "clear_stats", "Clear Stats"),
+        Binding("p", "toggle_pause", "Pause"),
+        Binding("space", "toggle_raw", "Raw Log"),
+    ]
+
+    CSS = """
+    Screen {
+        background: $surface;
+    }
+    #status-bar {
+        height: 1;
+        background: $primary-background;
+        padding: 0 1;
+    }
+    #status-bar Label {
+        width: auto;
+        margin: 0 2 0 0;
+    }
+    .panel {
+        border: solid $primary;
+        padding: 0 1;
+        height: auto;
+    }
+    .panel-title {
+        text-style: bold;
+        color: $accent;
+        margin: 0 0 0 0;
+    }
+    #top-row {
+        height: auto;
+        max-height: 12;
+    }
+    #position-panel {
+        width: 1fr;
+    }
+    #motor-panel {
+        width: 1fr;
+    }
+    #mid-row {
+        height: auto;
+        max-height: 8;
+    }
+    #state-panel {
+        width: 2fr;
+    }
+    #flags-panel {
+        width: 1fr;
+    }
+    #rs485-panel {
+        width: 1fr;
+    }
+    #stats-row {
+        height: 3;
+    }
+    #stats-panel {
+        width: 1fr;
+    }
+    .stat-label {
+        width: auto;
+        margin: 0 3 0 0;
+    }
+    #raw-panel {
+        height: 1fr;
+        min-height: 4;
+    }
+    #raw-panel.hidden {
+        display: none;
+    }
+    #raw-log {
+        height: 1fr;
+    }
+    #error-sparkline {
+        height: 3;
+    }
+    #pid-sparkline {
+        height: 3;
+    }
+    #pwm-bar {
+        height: 1;
+    }
+    .val-label {
+        width: auto;
+        margin: 0 2 0 0;
+    }
+    .flag-row {
+        height: 1;
+    }
+    #pause-label {
+        color: $warning;
+        text-style: bold;
+    }
+    """
+
+    def __init__(self, port: str, baudrate: int = BAUD_DEFAULT):
+        super().__init__()
+        self.port = port
+        self.baudrate = baudrate
+        self.stats = Statistics()
+        self.latest_data = FeederData()
+        self.paused = False
+        self._raw_lines: deque[str] = deque(maxlen=200)
+        self._raw_pending: list[str] = []
+        self._rs485_pending: list[str] = []
+        self._last_msg_handled = 0
+        self._last_trap_hex = ""
+        self._serial: serial.Serial | None = None
+
+    def compose(self) -> ComposeResult:
+        yield Header()
+
+        # Status bar
+        with Horizontal(id="status-bar"):
+            yield Label(f"{self.port} @ {self.baudrate}", id="port-label")
+            yield ConnectionIndicator(id="conn-indicator")
+            yield Label("0.0 pkt/s", id="rate-label")
+            yield Label("", id="pause-label")
+
+        # Top row: Position + Motor
+        with Horizontal(id="top-row"):
+            with Vertical(id="position-panel", classes="panel"):
+                yield Label("POSITION", classes="panel-title")
+                with Horizontal():
+                    yield Label("Pos: 0", id="pos-val", classes="val-label")
+                    yield Label("Tgt: 0", id="tgt-val", classes="val-label")
+                    yield Label("Err: 0", id="err-val", classes="val-label")
+                yield Sparkline([], id="error-sparkline")
+
+            with Vertical(id="motor-panel", classes="panel"):
+                yield Label("MOTOR", classes="panel-title")
+                yield Label("Output: 0", id="motor-val")
+                yield PWMBar(id="pwm-bar")
+                yield Sparkline([], id="pid-sparkline")
+
+        # Mid row: State + Flags + RS485
+        with Horizontal(id="mid-row"):
+            with Vertical(id="state-panel", classes="panel"):
+                yield Label("FEED STATE", classes="panel-title")
+                yield StateDisplay(id="state-display")
+
+            with Vertical(id="flags-panel", classes="panel"):
+                yield Label("FLAGS", classes="panel-title")
+                yield FlagIndicator("Initialized", id="flag-init")
+                yield FlagIndicator("Feeding", id="flag-feed")
+
+            with Vertical(id="rs485-panel", classes="panel"):
+                yield Label("RS485", classes="panel-title")
+                yield Label("Addr: --", id="rs485-addr")
+                yield Label("CRC Drops: 0", id="rs485-crc")
+                yield Label("Handled: 0", id="rs485-hdl")
+                yield Label("UART Err: 0", id="rs485-err")
+
+        # Stats row
+        with Horizontal(id="stats-row"):
+            with Horizontal(id="stats-panel", classes="panel"):
+                yield Label("Feeds: 0", id="stat-feeds", classes="stat-label")
+                yield Label("Timeouts: 0", id="stat-timeouts", classes="stat-label")
+                yield Label("Retries: 0", id="stat-retries", classes="stat-label")
+                yield Label("Brake: 3ms", id="stat-brake", classes="stat-label")
+                yield Label("Packets: 0", id="stat-pkts", classes="stat-label")
+
+        # RS485 message log
+        with Vertical(id="raw-panel", classes="panel"):
+            yield Label("RS485 MESSAGES", classes="panel-title")
+            yield RichLog(id="raw-log", max_lines=200, markup=True)
+
+        yield Footer()
+
+    def on_mount(self) -> None:
+        self.start_serial_reader()
+        self.set_interval(0.1, self.update_display)
+
+    # ---- Serial Worker ----
+
+    @work(thread=True, exclusive=True)
+    def start_serial_reader(self) -> None:
+        while True:
+            try:
+                self._serial = serial.Serial(
+                    port=self.port,
+                    baudrate=self.baudrate,
+                    timeout=0.1,
+                )
+                self.call_from_thread(self._set_connection, "connected")
+                buffer = ""
+                while True:
+                    try:
+                        data = self._serial.read(max(1, self._serial.in_waiting))
+                        if data:
+                            buffer += data.decode("ascii", errors="replace")
+                            while "\n" in buffer:
+                                line, buffer = buffer.split("\n", 1)
+                                line = line.strip()
+                                if line:
+                                    self.call_from_thread(self._handle_line, line)
+                    except serial.SerialException:
+                        break
+            except serial.SerialException:
+                self.call_from_thread(self._set_connection, "disconnected")
+            # Reconnect delay
+            if self._serial:
+                try:
+                    self._serial.close()
+                except Exception:
+                    pass
+                self._serial = None
+            time.sleep(2)
+
+    def _set_connection(self, status: str) -> None:
+        self.query_one("#conn-indicator", ConnectionIndicator).status = status
+
+    def _handle_line(self, line: str) -> None:
+        self._raw_lines.append(line)
+        parsed = parse_packet(line)
+        if parsed:
+            prev = self.latest_data
+            self.latest_data = parsed
+            self.stats.update(parsed)
+            # Detect RS485 events
+            if parsed.msg_handled != self._last_msg_handled:
+                diff = parsed.msg_handled - self._last_msg_handled
+                self._last_msg_handled = parsed.msg_handled
+                self._rs485_pending.append(
+                    f"[green]RX #{parsed.msg_handled}[/green] handled (+{diff})"
+                )
+            if parsed.uart_errors > 0 and parsed.uart_errors != getattr(self, '_last_uart_err', 0):
+                self._rs485_pending.append(
+                    f"[red]UART ERROR[/red] count: {parsed.uart_errors}"
+                )
+                self._last_uart_err = parsed.uart_errors
+            if parsed.trap_hex and parsed.trap_hex != self._last_trap_hex:
+                self._last_trap_hex = parsed.trap_hex
+                # Decode trap hex into spaced bytes
+                hex_str = parsed.trap_hex
+                spaced = " ".join(hex_str[i:i+2] for i in range(0, len(hex_str), 2))
+                self._rs485_pending.append(
+                    f"[cyan]TRAP[/cyan] size={parsed.trap_size} [{spaced}] crc={parsed.trap_crc}"
+                )
+            if parsed.crc_drops != getattr(self, '_last_crc_drops', 0):
+                self._rs485_pending.append(
+                    f"[yellow]CRC DROP[/yellow] total: {parsed.crc_drops}"
+                )
+                self._last_crc_drops = parsed.crc_drops
+        else:
+            self.stats.parse_errors += 1
+
+    # ---- Display Update ----
+
+    def update_display(self) -> None:
+        # Connection status
+        age = self.stats.connection_age
+        if age < 1:
+            status = "connected"
+        elif age < 5:
+            status = "stale"
+        elif age < 999:
+            status = "no_data"
+        else:
+            status = "disconnected"
+        self.query_one("#conn-indicator", ConnectionIndicator).status = status
+        self.query_one("#rate-label", Label).update(f"{self.stats.packet_rate:.1f} pkt/s")
+        self.query_one("#pause-label", Label).update("PAUSED" if self.paused else "")
+
+        if self.paused:
+            # Still flush raw log
+            self._flush_raw_log()
+            return
+
+        d = self.latest_data
+        s = self.stats
+
+        # Position
+        err_color = "green" if abs(d.error) <= 5 else ("yellow" if abs(d.error) <= 50 else "red")
+        self.query_one("#pos-val", Label).update(f"Pos: {d.position}")
+        self.query_one("#tgt-val", Label).update(f"Tgt: {d.target}")
+        err_label = self.query_one("#err-val", Label)
+        err_label.update(f"Err: {d.error}")
+        err_label.styles.color = err_color
+
+        # Sparklines
+        if s.error_history:
+            self.query_one("#error-sparkline", Sparkline).data = list(s.error_history)
+        if s.pid_history:
+            self.query_one("#pid-sparkline", Sparkline).data = list(s.pid_history)
+
+        # Motor
+        self.query_one("#motor-val", Label).update(f"Output: {d.pid_output}")
+        self.query_one("#pwm-bar", PWMBar).value = d.pid_output
+
+        # State
+        self.query_one("#state-display", StateDisplay).state = d.state
+
+        # Flags
+        self.query_one("#flag-init", FlagIndicator).active = d.is_initialized
+        self.query_one("#flag-feed", FlagIndicator).active = d.feed_in_progress
+
+        # RS485
+        self.query_one("#rs485-addr", Label).update(f"Addr: 0x{d.address}")
+        self.query_one("#rs485-crc", Label).update(f"CRC Drops: {d.crc_drops}")
+        self.query_one("#rs485-hdl", Label).update(f"Handled: {d.msg_handled}")
+        self.query_one("#rs485-err", Label).update(f"UART Err: {d.uart_errors}")
+
+        # Stats
+        self.query_one("#stat-feeds", Label).update(f"Feeds: {d.feed_ok_count}")
+        self.query_one("#stat-timeouts", Label).update(f"Timeouts: {d.feed_fail_count}")
+        self.query_one("#stat-retries", Label).update(f"Retries: {d.feed_retries}")
+        self.query_one("#stat-brake", Label).update(f"Brake: {d.brake_time_tenths/10:.1f}ms")
+        self.query_one("#stat-pkts", Label).update(f"Packets: {s.packet_count}")
+
+        # Raw log
+        self._flush_raw_log()
+
+    def _flush_raw_log(self) -> None:
+        if not self._rs485_pending:
+            return
+        raw_log = self.query_one("#raw-log", RichLog)
+        for msg in self._rs485_pending:
+            raw_log.write(msg)
+        self._rs485_pending.clear()
+
+    # ---- Actions ----
+
+    def action_clear_stats(self) -> None:
+        self.stats.clear()
+
+    def action_toggle_pause(self) -> None:
+        self.paused = not self.paused
+
+    def action_toggle_raw(self) -> None:
+        panel = self.query_one("#raw-panel")
+        panel.toggle_class("hidden")
+
+
+# ============================================================================
+# Main
+# ============================================================================
 
 def main():
-    print(f"{Colors.BOLD}{Colors.CYAN}Photon Feeder Mk2 Debug Monitor{Colors.RESET}")
-    print(f"{Colors.DIM}{'='*40}{Colors.RESET}\n")
-
-    # Parse arguments
     port = None
-    baudrate = 115200
+    baudrate = BAUD_DEFAULT
 
     if len(sys.argv) >= 2:
         port = sys.argv[1]
@@ -435,13 +648,22 @@ def main():
         try:
             baudrate = int(sys.argv[2])
         except ValueError:
-            print(f"{Colors.RED}Invalid baud rate: {sys.argv[2]}{Colors.RESET}")
+            print(f"Invalid baud rate: {sys.argv[2]}")
             sys.exit(1)
 
-    # If no port specified, list and prompt
     if port is None:
-        ports = list_ports()
-        if ports:
+        ports = serial.tools.list_ports.comports()
+        if not ports:
+            print("No serial ports found.")
+            sys.exit(1)
+        elif len(ports) == 1:
+            port = ports[0].device
+            print(f"Using: {port} ({ports[0].description})")
+        else:
+            print("Available serial ports:")
+            for i, p in enumerate(ports):
+                print(f"  {i + 1}. {p.device}: {p.description}")
+            print()
             try:
                 choice = input(f"Select port (1-{len(ports)}) or enter name: ").strip()
                 if choice.isdigit():
@@ -449,19 +671,16 @@ def main():
                     if 0 <= idx < len(ports):
                         port = ports[idx].device
                     else:
-                        print(f"{Colors.RED}Invalid selection{Colors.RESET}")
+                        print("Invalid selection.")
                         sys.exit(1)
                 else:
                     port = choice
             except (KeyboardInterrupt, EOFError):
-                print(f"\n{Colors.YELLOW}Cancelled{Colors.RESET}")
+                print("\nCancelled.")
                 sys.exit(0)
-        else:
-            sys.exit(1)
 
-    # Run monitor
-    monitor = FeederMonitor(port, baudrate)
-    monitor.run()
+    app = FeederMonitorApp(port, baudrate)
+    app.run()
 
 
 if __name__ == "__main__":
diff --git a/code/tools/requirements.txt b/code/tools/requirements.txt
index 7ad05ef..bbdfb81 100644
--- a/code/tools/requirements.txt
+++ b/code/tools/requirements.txt
@@ -1 +1,2 @@
 pyserial>=3.5
+textual>=1.0.0
diff --git a/code/tools/start_monitor.bat b/code/tools/start_monitor.bat
index dff7e70..1f16d25 100644
--- a/code/tools/start_monitor.bat
+++ b/code/tools/start_monitor.bat
@@ -22,6 +22,18 @@ if errorlevel 1 (
     )
 )
 
+:: Check if textual is installed
+python -c "import textual" >nul 2>&1
+if errorlevel 1 (
+    echo Installing textual...
+    pip install textual
+    if errorlevel 1 (
+        echo Error: Failed to install textual
+        pause
+        exit /b 1
+    )
+)
+
 :: Run the monitor
 cd /d "%~dp0"
 python feeder_monitor.py %*
diff --git a/pcb/mobo/#auto_saved_files# b/pcb/mobo/#auto_saved_files#
deleted file mode 100644
index 8ab9dc7..0000000
--- a/pcb/mobo/#auto_saved_files#
+++ /dev/null
@@ -1 +0,0 @@
-C:\Users\janik\feeder_mk2\pcb\mobo\_autosave-mobo.kicad_sch
diff --git a/pcb/mobo/mobo.kicad_pcb b/pcb/mobo/mobo.kicad_pcb
index 5f11060..4b1fb6f 100644
--- a/pcb/mobo/mobo.kicad_pcb
+++ b/pcb/mobo/mobo.kicad_pcb
@@ -182,7 +182,7 @@
 	(net 43 "unconnected-(U1-PB11-Pad23)")
 	(net 44 "unconnected-(U1-PA15-Pad37)")
 	(net 45 "unconnected-(U1-PB2-Pad21)")
-	(net 46 "unconnected-(U1-PA7-Pad18)")
+	(net 46 "IPROP_DRIVE")
 	(net 47 "unconnected-(U1-PF3-Pad4)")
 	(net 48 "unconnected-(U1-PD1-Pad39)")
 	(net 49 "unconnected-(U1-PB13-Pad25)")
@@ -193,41 +193,39 @@
 	(net 54 "unconnected-(U1-PB1-Pad20)")
 	(net 55 "unconnected-(U1-PB0-Pad19)")
 	(net 56 "unconnected-(U1-PB10-Pad22)")
-	(net 57 "unconnected-(U1-PB12-Pad24)")
+	(net 57 "IPROP_PEEL")
 	(net 58 "unconnected-(U1-PC13-Pad1)")
 	(net 59 "unconnected-(U1-PD2-Pad40)")
 	(net 60 "unconnected-(U1-PA10-Pad32)")
 	(net 61 "Net-(U3-FB)")
 	(net 62 "DRIVE1")
-	(net 63 "Net-(U4-IPROPI)")
-	(net 64 "DRIVE2")
-	(net 65 "PEEL1")
-	(net 66 "Net-(U5-IPROPI)")
-	(net 67 "PEEL2")
-	(net 68 "Net-(D1-RK)")
-	(net 69 "unconnected-(J8-Pin_2-Pad2)")
-	(net 70 "unconnected-(J8-Pin_6-Pad6)")
-	(net 71 "unconnected-(U1-PC15-OSCX_OUT-Pad3)")
-	(net 72 "unconnected-(U1-PC14-OSCX_IN-Pad2)")
-	(net 73 "unconnected-(U1-PA11[PA9]-Pad33)")
-	(net 74 "unconnected-(U1-PA12[PA10]-Pad34)")
-	(net 75 "Net-(U2-ILIMIT)")
-	(net 76 "unconnected-(J10-JTDO{slash}SWO-Pad8)")
-	(net 77 "unconnected-(J10-JRCLK{slash}NC-Pad9)")
-	(net 78 "unconnected-(J10-NC-Pad2)")
-	(net 79 "unconnected-(J10-JTDI{slash}NC-Pad10)")
-	(net 80 "unconnected-(J10-NC-Pad1)")
-	(net 81 "GND")
-	(net 82 "Net-(J4-Pin_1)")
-	(net 83 "Net-(J6-Pin_1)")
-	(net 84 "Net-(J7-Pin_1)")
-	(net 85 "nRE")
-	(net 86 "USART2_TX")
-	(net 87 "USART2_RX")
-	(net 88 "USART1_TX")
-	(net 89 "USART1_RX")
-	(net 90 "Net-(D5-A)")
-	(net 91 "Net-(D3-A)")
+	(net 63 "DRIVE2")
+	(net 64 "PEEL1")
+	(net 65 "PEEL2")
+	(net 66 "Net-(D1-RK)")
+	(net 67 "unconnected-(J8-Pin_2-Pad2)")
+	(net 68 "unconnected-(J8-Pin_6-Pad6)")
+	(net 69 "unconnected-(U1-PC15-OSCX_OUT-Pad3)")
+	(net 70 "unconnected-(U1-PC14-OSCX_IN-Pad2)")
+	(net 71 "unconnected-(U1-PA11[PA9]-Pad33)")
+	(net 72 "unconnected-(U1-PA12[PA10]-Pad34)")
+	(net 73 "Net-(U2-ILIMIT)")
+	(net 74 "unconnected-(J10-JTDO{slash}SWO-Pad8)")
+	(net 75 "unconnected-(J10-JRCLK{slash}NC-Pad9)")
+	(net 76 "unconnected-(J10-NC-Pad2)")
+	(net 77 "unconnected-(J10-JTDI{slash}NC-Pad10)")
+	(net 78 "unconnected-(J10-NC-Pad1)")
+	(net 79 "GND")
+	(net 80 "Net-(J4-Pin_1)")
+	(net 81 "Net-(J6-Pin_1)")
+	(net 82 "Net-(J7-Pin_1)")
+	(net 83 "nRE")
+	(net 84 "USART2_TX")
+	(net 85 "USART2_RX")
+	(net 86 "USART1_TX")
+	(net 87 "USART1_RX")
+	(net 88 "Net-(D5-A)")
+	(net 89 "Net-(D3-A)")
 	(footprint "Capacitor_SMD:C_1210_3225Metric"
 		(layer "F.Cu")
 		(uuid "02c2ac28-81ef-4f04-9f8e-c7a30ad54266")
@@ -570,7 +568,7 @@
 			(size 1.15 2.7)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.217391)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "3225f8a8-0c5b-4718-b075-f2d78972539b")
 		)
@@ -599,7 +597,7 @@
 	(footprint "Capacitor_SMD:C_0805_2012Metric"
 		(layer "F.Cu")
 		(uuid "05132602-d8ea-4775-b8b6-0d5f0e171994")
-		(at 127.6858 71.289801 90)
+		(at 128.33 71.289801 90)
 		(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C50"
@@ -791,7 +789,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "1d5a29cf-ad7e-43bd-8095-93cedf9351a3")
 		)
@@ -1372,7 +1370,7 @@
 			(at -1.35255 -0.950001 180)
 			(size 1.0033 0.5588)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "GND")
 			(pintype "power_out")
 			(uuid "a4529e67-1ca3-4e39-ac0a-b4ed5e276db2")
@@ -1621,7 +1619,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 83 "Net-(J6-Pin_1)")
+			(net 81 "Net-(J6-Pin_1)")
 			(pintype "passive")
 			(uuid "25a2126e-6eda-4563-af65-f545ddde44a9")
 		)
@@ -1842,7 +1840,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "37131de9-3435-45f3-9207-a96a2df71e6d")
 		)
@@ -2283,7 +2281,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "5e25fc0c-c229-416f-a8d5-e7a87ab06f0d")
 		)
@@ -3028,7 +3026,7 @@
 			(size 0.9 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "ac15743f-0f45-4e75-9525-f96ff15bbb75")
 		)
@@ -3240,7 +3238,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "b63206d9-f4d2-4361-9078-fa27da6860cd")
 		)
@@ -3590,7 +3588,7 @@
 			(size 1.475 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "common")
 			(pintype "input")
 			(uuid "a4be3632-75a2-42e5-bd20-6b745e7898b5")
@@ -5939,7 +5937,7 @@
 			(at -4.2164 -2.250001 270)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 72 "unconnected-(U1-PC14-OSCX_IN-Pad2)")
+			(net 70 "unconnected-(U1-PC14-OSCX_IN-Pad2)")
 			(pinfunction "PC14-OSCX_IN")
 			(pintype "bidirectional")
 			(uuid "abd9be82-8998-486b-98c2-ccca48f05636")
@@ -5948,7 +5946,7 @@
 			(at -4.2164 -1.749999 270)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 71 "unconnected-(U1-PC15-OSCX_OUT-Pad3)")
+			(net 69 "unconnected-(U1-PC15-OSCX_OUT-Pad3)")
 			(pinfunction "PC15-OSCX_OUT")
 			(pintype "bidirectional")
 			(uuid "7ecebb42-652d-4ffc-8ddb-b91ea86b2f1d")
@@ -5984,7 +5982,7 @@
 			(at -4.2164 0.25 270)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "VSS/VSSA")
 			(pintype "power_in")
 			(uuid "98de297f-92bc-4d50-beb1-1d44b8d27c69")
@@ -6020,7 +6018,7 @@
 			(at -4.2164 2.250001 270)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 85 "nRE")
+			(net 83 "nRE")
 			(pinfunction "PA0")
 			(pintype "bidirectional")
 			(uuid "afc0e418-36a3-435e-847c-33416687af25")
@@ -6038,7 +6036,7 @@
 			(at -2.75 4.2164 180)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 65 "PEEL1")
+			(net 64 "PEEL1")
 			(pinfunction "PA2")
 			(pintype "bidirectional")
 			(uuid "91bb3e51-1eef-45f9-aebb-6d38f317ff5f")
@@ -6047,7 +6045,7 @@
 			(at -2.250001 4.2164 180)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 67 "PEEL2")
+			(net 65 "PEEL2")
 			(pinfunction "PA3")
 			(pintype "bidirectional")
 			(uuid "6b9fa2b1-460c-4ae6-9ba0-f5f3dffa819b")
@@ -6056,7 +6054,7 @@
 			(at -1.749999 4.2164 180)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 86 "USART2_TX")
+			(net 84 "USART2_TX")
 			(pinfunction "PA4")
 			(pintype "bidirectional")
 			(uuid "b3c55b46-2db9-4d5e-888c-5effa5733562")
@@ -6065,7 +6063,7 @@
 			(at -1.25 4.2164 180)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 87 "USART2_RX")
+			(net 85 "USART2_RX")
 			(pinfunction "PA5")
 			(pintype "bidirectional")
 			(uuid "c29c6da6-1dcf-4d0c-9f8b-1fe539f34f71")
@@ -6083,7 +6081,7 @@
 			(at -0.25 4.2164 180)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 46 "unconnected-(U1-PA7-Pad18)")
+			(net 57 "IPROP_PEEL")
 			(pinfunction "PA7")
 			(pintype "bidirectional")
 			(uuid "d242c8da-4393-49ca-866a-3412d725b145")
@@ -6137,7 +6135,7 @@
 			(at 2.75 4.2164 180)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 57 "unconnected-(U1-PB12-Pad24)")
+			(net 46 "IPROP_DRIVE")
 			(pinfunction "PB12")
 			(pintype "bidirectional")
 			(uuid "231a7e5e-65b5-4339-a1be-57954b266a9e")
@@ -6182,7 +6180,7 @@
 			(at 4.2164 0.750001 270)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 64 "DRIVE2")
+			(net 63 "DRIVE2")
 			(pinfunction "PA9")
 			(pintype "bidirectional")
 			(uuid "3ef0e7ea-e525-417a-8059-67f767fc3754")
@@ -6191,7 +6189,7 @@
 			(at 4.2164 0.25 270)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 91 "Net-(D3-A)")
+			(net 89 "Net-(D3-A)")
 			(pinfunction "PC6")
 			(pintype "bidirectional")
 			(uuid "e2a0f9b6-0ca8-40da-9728-49f26e660122")
@@ -6200,7 +6198,7 @@
 			(at 4.2164 -0.25 270)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 90 "Net-(D5-A)")
+			(net 88 "Net-(D5-A)")
 			(pinfunction "PC7")
 			(pintype "bidirectional")
 			(uuid "a7c37f7d-4067-4013-bfd7-e4327f8299a5")
@@ -6218,7 +6216,7 @@
 			(at 4.2164 -1.25 270)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 73 "unconnected-(U1-PA11[PA9]-Pad33)")
+			(net 71 "unconnected-(U1-PA11[PA9]-Pad33)")
 			(pinfunction "PA11[PA9]")
 			(pintype "bidirectional")
 			(uuid "ca8540f8-57f1-47eb-9ffe-e1a8985a92d5")
@@ -6227,7 +6225,7 @@
 			(at 4.2164 -1.749999 270)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 74 "unconnected-(U1-PA12[PA10]-Pad34)")
+			(net 72 "unconnected-(U1-PA12[PA10]-Pad34)")
 			(pinfunction "PA12[PA10]")
 			(pintype "bidirectional")
 			(uuid "d7f47ba5-cbdf-444d-b972-d5ee560b906f")
@@ -6326,7 +6324,7 @@
 			(at -1.25 -4.2164 180)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 88 "USART1_TX")
+			(net 86 "USART1_TX")
 			(pinfunction "PB6")
 			(pintype "bidirectional")
 			(uuid "bcf78b28-6c2b-43d1-a388-6b53033d5df3")
@@ -6335,7 +6333,7 @@
 			(at -1.749999 -4.2164 180)
 			(size 0.2794 1.4732)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 89 "USART1_RX")
+			(net 87 "USART1_RX")
 			(pinfunction "PB7")
 			(pintype "bidirectional")
 			(uuid "1579f52a-9933-4faa-8d5b-53109c65f375")
@@ -6652,7 +6650,7 @@
 			(size 0.67 0.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "GND")
 			(pintype "power_in")
 			(uuid "63db6f66-c105-42cb-93d5-f315b09faa43")
@@ -7244,7 +7242,7 @@
 			(size 0.9 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "d81b338d-0f4c-4066-b706-6c813112af65")
 		)
@@ -7456,7 +7454,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "644a6541-e8db-46d0-a643-3bda5cb9e865")
 		)
@@ -7694,7 +7692,7 @@
 			(size 1.025 1.4)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.243902)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "edc3d94e-61ea-4d34-9dd1-5bfd897870f5")
 		)
@@ -8118,7 +8116,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 90 "Net-(D5-A)")
+			(net 88 "Net-(D5-A)")
 			(pintype "passive")
 			(uuid "67140eee-54e3-4bd0-9966-fa17c5588b07")
 		)
@@ -8366,7 +8364,7 @@
 			(size 0.5 0.25)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 66 "Net-(U5-IPROPI)")
+			(net 57 "IPROP_PEEL")
 			(pinfunction "IPROPI")
 			(pintype "output")
 			(uuid "e4c4b6bf-8563-43ea-9cc6-d32ea6e211ce")
@@ -8376,7 +8374,7 @@
 			(size 0.5 0.25)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 67 "PEEL2")
+			(net 65 "PEEL2")
 			(pinfunction "IN2")
 			(pintype "input")
 			(uuid "ecac3346-ba90-405c-942e-2e9a07ce2a69")
@@ -8386,7 +8384,7 @@
 			(size 0.5 0.25)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 65 "PEEL1")
+			(net 64 "PEEL1")
 			(pinfunction "IN1")
 			(pintype "input")
 			(uuid "610f7dc0-d7b1-4b6e-8809-f8c564600d3c")
@@ -8426,7 +8424,7 @@
 			(size 0.5 0.25)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "GND")
 			(pintype "power_in")
 			(uuid "f201a50e-b5fc-44ac-a636-6a08964377ee")
@@ -8445,7 +8443,7 @@
 			(at 0 0 180)
 			(size 0.9 1.6)
 			(layers "F.Cu" "F.Mask")
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "GND")
 			(pintype "passive")
 			(uuid "d282fc73-2a3d-4046-8007-56bf18facbdd")
@@ -8658,7 +8656,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 84 "Net-(J7-Pin_1)")
+			(net 82 "Net-(J7-Pin_1)")
 			(pintype "passive")
 			(uuid "46689cb8-b7fd-4e19-b32f-8d4257898b26")
 		)
@@ -8870,7 +8868,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "7ee0c5ca-3915-4915-a7a7-35af3b509cc2")
 		)
@@ -9082,7 +9080,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "9e228710-ba9c-47e3-a3a7-6d190f03fd78")
 		)
@@ -9285,7 +9283,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "506f80cc-5b24-4c7c-bf27-71c0b923256e")
 		)
@@ -9294,7 +9292,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 75 "Net-(U2-ILIMIT)")
+			(net 73 "Net-(U2-ILIMIT)")
 			(pintype "passive")
 			(uuid "95e11a42-8731-4352-8a64-10525560cabf")
 		)
@@ -9506,7 +9504,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "dbc145e3-c734-4ab3-b2ce-5fcb94afd1c7")
 		)
@@ -10079,7 +10077,7 @@
 			(at 1.7018 0 90)
 			(size 1.651 2.1844)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "A")
 			(pintype "passive")
 			(uuid "cb180cf1-1922-426f-bd32-b9e6f5ad0089")
@@ -10524,7 +10522,7 @@
 			(size 1.15 2.7)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.217391)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "356c30ff-d50f-4eb2-9d82-057cb71c27e6")
 		)
@@ -10745,7 +10743,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "824fd081-e1f5-493b-9556-8db0d2079264")
 		)
@@ -10948,7 +10946,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "d2b4bf71-485a-44ab-b322-f7bdbf14fe5b")
 		)
@@ -11169,7 +11167,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "dd137daa-7077-4228-8508-8bb2148eaea8")
 		)
@@ -11372,7 +11370,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "2d012c2a-51be-4f91-bafe-1a4b255fe1e1")
 		)
@@ -12034,7 +12032,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "66771fad-36b2-4e8b-b105-1496a6d9fc8e")
 		)
@@ -12255,7 +12253,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "24bfa7e6-0736-4179-99e6-baf5acb83fab")
 		)
@@ -12467,7 +12465,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "c3d5b452-4e9f-4a67-99cd-cc545e8ed1bc")
 		)
@@ -12992,7 +12990,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "9dd1fa64-dcc1-43d4-97c9-d25ba517bcca")
 		)
@@ -13351,7 +13349,7 @@
 			(size 0.9 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "779a91ea-cdf3-4381-a6be-ed351e2cadea")
 		)
@@ -13572,7 +13570,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "e511f663-3eb0-41dd-9a9f-c19f778fc680")
 		)
@@ -13802,7 +13800,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "b7004e04-773b-4e5d-9b34-e8f0f6a97f72")
 		)
@@ -13880,7 +13878,7 @@
 				)
 			)
 		)
-		(property "MPN" "RC0402FR-071K4L"
+		(property "MPN" "RT0603FRE071K4L"
 			(at 0 0 180)
 			(unlocked yes)
 			(layer "F.Fab")
@@ -14014,7 +14012,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 66 "Net-(U5-IPROPI)")
+			(net 57 "IPROP_PEEL")
 			(pintype "passive")
 			(uuid "a70c2b06-9002-44e4-9e37-f540d6152bc9")
 		)
@@ -14023,7 +14021,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "30c27f83-c054-4b40-aaab-c497a508f85f")
 		)
@@ -14440,7 +14438,7 @@
 			(size 0.54 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "07557ae7-825b-4d3c-8a15-4cd438628379")
 		)
@@ -14734,7 +14732,7 @@
 			(size 1 1)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 91 "Net-(D3-A)")
+			(net 89 "Net-(D3-A)")
 			(pinfunction "A")
 			(pintype "passive")
 			(uuid "41f5e726-9ffc-4e53-9fc8-369fa473c25d")
@@ -14755,7 +14753,7 @@
 	(footprint "Capacitor_SMD:C_0805_2012Metric"
 		(layer "F.Cu")
 		(uuid "5e633307-0cd6-4013-bb2d-343de090f54d")
-		(at 125.6538 71.289801 -90)
+		(at 126.298 71.289801 -90)
 		(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C48"
@@ -14938,7 +14936,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "70279d93-6068-4ed9-b8ca-201621817ab3")
 		)
@@ -15159,7 +15157,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 85 "nRE")
+			(net 83 "nRE")
 			(pintype "passive")
 			(uuid "9d928212-2699-4634-9538-8c2ab939323e")
 		)
@@ -15740,7 +15738,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "14f17e20-9371-43eb-b821-348501236cb2")
 		)
@@ -16282,7 +16280,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "9b6c1eee-89d6-4be3-96ac-ab9c84578429")
 		)
@@ -16642,7 +16640,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "9c536c5e-3223-4bc3-93e1-a1bafc4973c4")
 		)
@@ -16804,7 +16802,7 @@
 			(size 1.15 1)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.125)
-			(net 83 "Net-(J6-Pin_1)")
+			(net 81 "Net-(J6-Pin_1)")
 			(pinfunction "Pin_1")
 			(pintype "passive")
 			(uuid "c5455356-24fe-45b2-bf86-16d8c7787052")
@@ -16814,7 +16812,7 @@
 			(size 1.05 1)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.125)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "Pin_2")
 			(pintype "passive")
 			(uuid "85fd082b-ca84-4e64-bfd1-40c24041d678")
@@ -16824,7 +16822,7 @@
 			(size 1.2 1.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.125)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "Pin_3")
 			(pintype "passive")
 			(uuid "dae6831b-0891-4c3e-9e9d-16fbc95c4688")
@@ -16834,7 +16832,7 @@
 			(size 1.2 1.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.125)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "Pin_4")
 			(pintype "passive")
 			(uuid "ec6602cd-b387-403a-8b9a-c6de1af162c3")
@@ -17249,7 +17247,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "2c5a63fb-b7b3-4169-ae80-1cdd3c10e270")
 		)
@@ -17439,7 +17437,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "b60b7ef1-2021-4b50-af30-e1b446a3f1d0")
 		)
@@ -17660,7 +17658,7 @@
 			(size 0.54 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "5c2a891f-b544-41b0-b894-8caf4ce4a5eb")
 		)
@@ -17872,7 +17870,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 68 "Net-(D1-RK)")
+			(net 66 "Net-(D1-RK)")
 			(pintype "passive")
 			(uuid "f8e9b8eb-0a7e-488d-8d81-592d95561b8b")
 		)
@@ -18282,7 +18280,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "1ec2cff3-bfa1-4e82-9ede-5f7c2071105d")
 		)
@@ -18351,7 +18349,7 @@
 				)
 			)
 		)
-		(property "MPN" "RC0402FR-071K4L"
+		(property "MPN" "RT0603FRE071K4L"
 			(at 0 0 180)
 			(unlocked yes)
 			(layer "F.Fab")
@@ -18485,7 +18483,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 63 "Net-(U4-IPROPI)")
+			(net 46 "IPROP_DRIVE")
 			(pintype "passive")
 			(uuid "c5478e01-b9e4-405b-9d0c-2fa691c657d7")
 		)
@@ -18494,7 +18492,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "15532787-a294-45a7-9331-1bf7f28fc219")
 		)
@@ -18937,7 +18935,7 @@
 			(size 4.15 1.9)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.131579)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "a0fece7e-e9b5-44c3-bb8a-31c52d85ae2b")
 		)
@@ -19172,7 +19170,7 @@
 		(uuid "91b842db-38af-4f6c-88de-f23842890cfa")
 		(at 130.429 111.5822 180)
 		(property "Reference" "D1"
-			(at -0.0508 2.3368 180)
+			(at -3.341 0.0222 0)
 			(unlocked yes)
 			(layer "F.SilkS")
 			(uuid "2e762bb7-da40-48ee-943e-9ced1fce94ec")
@@ -19298,7 +19296,7 @@
 			(size 0.5 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.15)
-			(net 68 "Net-(D1-RK)")
+			(net 66 "Net-(D1-RK)")
 			(pinfunction "RK")
 			(pintype "passive")
 			(uuid "241f049e-d678-479d-8a22-75159a537f63")
@@ -19717,7 +19715,7 @@
 			(size 0.8 1.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "Pin_2")
 			(pintype "passive")
 			(uuid "690e4f5c-fce9-4722-8d28-e480b5609a58")
@@ -19924,7 +19922,7 @@
 			(size 1.15 1)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.125)
-			(net 84 "Net-(J7-Pin_1)")
+			(net 82 "Net-(J7-Pin_1)")
 			(pinfunction "Pin_1")
 			(pintype "passive")
 			(uuid "890658d1-02b2-4e0d-8bf0-b23c6a3355b9")
@@ -20156,7 +20154,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "a530cdf9-c8ac-48ae-a2c7-7cd8953468a2")
 		)
@@ -20368,7 +20366,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "4b01046b-1848-43f9-afd8-117a2ba009ec")
 		)
@@ -20580,7 +20578,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "2eae5e15-a3ca-4d11-9683-51b891fd534e")
 		)
@@ -20783,7 +20781,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 91 "Net-(D3-A)")
+			(net 89 "Net-(D3-A)")
 			(pintype "passive")
 			(uuid "58867fd8-d02b-42c8-b8aa-e0f1f08b3baf")
 		)
@@ -20813,7 +20811,7 @@
 		(locked yes)
 		(layer "F.Cu")
 		(uuid "a3e4f0ae-9f86-49e9-b386-ed8b42e012fb")
-		(at 117.7 69.5 180)
+		(at 118.5 69.5 180)
 		(descr "Molex PicoBlade series connector, 53261-0271 (http://www.molex.com/pdm_docs/sd/532610271_sd.pdf), generated with kicad-footprint-generator")
 		(tags "connector Molex PicoBlade top entry")
 		(property "Reference" "J2"
@@ -21449,7 +21447,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "e3e06b7e-ab85-4a84-accf-51e7dc32d8d1")
 		)
@@ -21605,7 +21603,7 @@
 			(size 1.4 1.2)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.208333)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "2")
 			(pintype "passive")
 			(uuid "c103468d-c65a-4fc2-aafb-1efd4780b73c")
@@ -21625,7 +21623,7 @@
 			(size 1.4 1.2)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.208333)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "4")
 			(pintype "passive")
 			(uuid "a59437b7-9fea-4db8-b58c-efcd5ad48f2f")
@@ -22353,7 +22351,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "7f69dc0c-796f-41ca-9c1d-bd9c5e055f03")
 		)
@@ -22565,7 +22563,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 91 "Net-(D3-A)")
+			(net 89 "Net-(D3-A)")
 			(pintype "passive")
 			(uuid "4501fefb-0cb6-44e0-bd49-d57a5ee96e92")
 		)
@@ -22574,7 +22572,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "a7f61768-2213-4e78-9d9c-2d12a704af79")
 		)
@@ -22907,7 +22905,7 @@
 			(size 1.95 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 87 "USART2_RX")
+			(net 85 "USART2_RX")
 			(pinfunction "RO")
 			(pintype "output")
 			(uuid "38ef457d-47b9-4680-b43b-f62dbb296302")
@@ -22917,7 +22915,7 @@
 			(size 1.95 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 85 "nRE")
+			(net 83 "nRE")
 			(pinfunction "~{RE}")
 			(pintype "input")
 			(uuid "15a7c9b1-fb37-4ece-9dd5-0deb07767c2f")
@@ -22937,7 +22935,7 @@
 			(size 1.95 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 86 "USART2_TX")
+			(net 84 "USART2_TX")
 			(pinfunction "DI")
 			(pintype "input")
 			(uuid "bcb1902d-c021-4ad4-aa14-aa93978ca701")
@@ -22947,7 +22945,7 @@
 			(size 1.95 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "GND")
 			(pintype "power_in")
 			(uuid "2b7e4067-0063-4e7d-9b69-74fea88205b1")
@@ -23419,7 +23417,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "c95fabba-5ef0-4e47-adc4-32e910374460")
 		)
@@ -23787,7 +23785,7 @@
 			(size 1.15 2.7)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.217391)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "149733da-caac-4d80-a3ad-fbf926053d25")
 		)
@@ -24191,7 +24189,7 @@
 			(size 1.1 1.1)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.2272727273)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "A")
 			(pintype "passive")
 			(uuid "e6495c2f-31d8-4435-86a3-69204dfbb098")
@@ -24382,7 +24380,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "233b9834-f95b-45f7-9638-7b4c46ae14d9")
 		)
@@ -24788,7 +24786,7 @@
 				)
 			)
 		)
-		(property "MPN" "RT0402BRE0711K5L"
+		(property "MPN" "RT0603FRE0711K5L"
 			(at 0 0 180)
 			(unlocked yes)
 			(layer "F.Fab")
@@ -25134,7 +25132,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "3c2dddeb-6741-40dc-9f29-1bec791fbc31")
 		)
@@ -25568,7 +25566,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "f06efa0d-ec4e-43ee-a51b-e1b4c32e5354")
 		)
@@ -25853,7 +25851,7 @@
 			(size 1 1)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 90 "Net-(D5-A)")
+			(net 88 "Net-(D5-A)")
 			(pinfunction "A")
 			(pintype "passive")
 			(uuid "e1b04377-c8e9-46b6-9dab-e842af0a4c59")
@@ -26066,7 +26064,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "944c7ac4-fe9a-47af-892a-b911bd96a685")
 		)
@@ -26425,7 +26423,7 @@
 			(size 1.15 2.7)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.217391)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "91880017-ddb2-4274-965b-c7e69cd26085")
 		)
@@ -26673,7 +26671,7 @@
 			(size 0.5 0.25)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 63 "Net-(U4-IPROPI)")
+			(net 46 "IPROP_DRIVE")
 			(pinfunction "IPROPI")
 			(pintype "output")
 			(uuid "b50c5c2f-1c24-4267-b056-ccfec0f78771")
@@ -26683,7 +26681,7 @@
 			(size 0.5 0.25)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 64 "DRIVE2")
+			(net 63 "DRIVE2")
 			(pinfunction "IN2")
 			(pintype "input")
 			(uuid "b590588f-3988-45a8-a589-2016cd9d934e")
@@ -26733,7 +26731,7 @@
 			(size 0.5 0.25)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "GND")
 			(pintype "power_in")
 			(uuid "4cc23fee-83f8-40f5-87d1-e09cafd146c4")
@@ -26752,7 +26750,7 @@
 			(at 0 0 180)
 			(size 0.9 1.6)
 			(layers "F.Cu" "F.Mask")
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "GND")
 			(pintype "passive")
 			(uuid "40ceebb5-ca30-4954-b307-5ecf1cd49644")
@@ -27079,7 +27077,7 @@
 			(size 1.325 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "GND")
 			(pintype "input")
 			(uuid "d988a79f-b0ef-402b-8d5f-bb9bb4864e20")
@@ -27089,7 +27087,7 @@
 			(size 1.325 0.6)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 75 "Net-(U2-ILIMIT)")
+			(net 73 "Net-(U2-ILIMIT)")
 			(pinfunction "ILIMIT")
 			(pintype "input")
 			(uuid "181f2303-5065-4dfd-82fb-209493055bd8")
@@ -27313,7 +27311,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 82 "Net-(J4-Pin_1)")
+			(net 80 "Net-(J4-Pin_1)")
 			(pintype "passive")
 			(uuid "c2f0e0b6-c536-44f1-9a9a-3134d55e1514")
 		)
@@ -27474,7 +27472,7 @@
 			(size 1.3 1.15)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "Pin_2")
 			(pintype "passive")
 			(uuid "183c8ab0-db35-4fb1-904d-66d6532bbf7d")
@@ -27514,7 +27512,7 @@
 			(size 1.5 2.15)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.1)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "Pin_6")
 			(pintype "passive")
 			(uuid "eb8efca8-bcd7-4657-a680-a530aae7ab88")
@@ -27524,7 +27522,7 @@
 			(size 1.5 2.15)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.1)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "Pin_7")
 			(pintype "passive")
 			(uuid "5e042896-88ad-4238-80b6-1feddea75ae3")
@@ -27754,7 +27752,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "110dac7c-d0ea-4a35-95e5-486a97134241")
 		)
@@ -27975,7 +27973,7 @@
 			(size 0.8 0.95)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "505b0d9a-11c7-4da6-baa7-bcbe4efe6542")
 		)
@@ -28340,7 +28338,7 @@
 			(size 1.15 1)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.125)
-			(net 82 "Net-(J4-Pin_1)")
+			(net 80 "Net-(J4-Pin_1)")
 			(pinfunction "Pin_1")
 			(pintype "passive")
 			(uuid "66746a22-7f8f-4462-916d-82d8011cf7f3")
@@ -28350,7 +28348,7 @@
 			(size 1.05 1)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.125)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "Pin_2")
 			(pintype "passive")
 			(uuid "bda5ab6b-01c0-461f-8476-7fcd869fc7fd")
@@ -28360,7 +28358,7 @@
 			(size 1.2 1.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.125)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "Pin_3")
 			(pintype "passive")
 			(uuid "13def6f4-ebce-471c-9c4d-d6c548ac5c0c")
@@ -28370,7 +28368,7 @@
 			(size 1.2 1.3)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.125)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "Pin_4")
 			(pintype "passive")
 			(uuid "039e4491-da8f-4ffd-bfc7-82ccf88f1fdd")
@@ -28380,7 +28378,7 @@
 	(footprint "Capacitor_SMD:C_0805_2012Metric"
 		(layer "F.Cu")
 		(uuid "ea55c410-2285-40aa-ac4b-e1a562479729")
-		(at 123.6218 71.289801 90)
+		(at 124.266 71.289801 90)
 		(descr "Capacitor SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf, https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
 		(tags "capacitor")
 		(property "Reference" "C49"
@@ -28572,7 +28570,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "5e95e53c-750b-488a-82d3-8b7b30a646b0")
 		)
@@ -28784,7 +28782,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "7042aab5-d805-46cb-8122-5f9f8041c1bb")
 		)
@@ -28996,7 +28994,7 @@
 			(size 1 1.45)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "b2110027-bfbd-4c84-b407-9a5267cdda9a")
 		)
@@ -29199,7 +29197,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 90 "Net-(D5-A)")
+			(net 88 "Net-(D5-A)")
 			(pintype "passive")
 			(uuid "154cfc52-17e4-43eb-af99-4eb19db4f42a")
 		)
@@ -29208,7 +29206,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "e1bff122-d6ec-4a3e-a4a1-ce71582e8ae0")
 		)
@@ -29225,244 +29223,6 @@
 			)
 		)
 	)
-	(footprint "Capacitor_SMD:C_0402_1005Metric"
-		(layer "F.Cu")
-		(uuid "f37c5ce7-0fa0-46a2-a45f-6981a80f0e2a")
-		(at 128.51 113.29)
-		(descr "Capacitor SMD 0402 (1005 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf), generated with kicad-footprint-generator")
-		(tags "capacitor")
-		(property "Reference" "C11"
-			(at 0 -1.16 0)
-			(layer "F.SilkS")
-			(uuid "4d30de71-27e2-4760-9ddc-0ba2b05fec5a")
-			(effects
-				(font
-					(size 1 1)
-					(thickness 0.15)
-				)
-			)
-		)
-		(property "Value" "4.7uF"
-			(at 0 1.16 0)
-			(layer "F.Fab")
-			(uuid "c2c6e41c-7826-4d95-acfa-519ee73d9f01")
-			(effects
-				(font
-					(size 1 1)
-					(thickness 0.15)
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-			)
-		)
-		(property "Datasheet" "~"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "92d877d8-64c8-4c68-a3c7-ac75b8ff857b")
-			(effects
-				(font
-					(size 1.27 1.27)
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-		(property "Description" ""
-			(at 0 0 0)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "2c21cdeb-b84d-4fd7-935d-93edbf39c4a9")
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-		(property "JLCPCB" "C49678"
-			(at 0 0 0)
-			(unlocked yes)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "031d7ad3-efe8-471d-a9f1-dac6554d466c")
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-		(property "LCSC" "C476766"
-			(at 0 0 0)
-			(unlocked yes)
-			(layer "F.Fab")
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-			(uuid "986e4834-88d8-4a59-8d7e-d08fe734e3d0")
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-		(property "MPN" "CC0402MRX5R6BB475"
-			(at 0 0 0)
-			(unlocked yes)
-			(layer "F.Fab")
-			(hide yes)
-			(uuid "384d81f7-6857-4d04-9c08-7101da73528e")
-			(effects
-				(font
-					(size 1 1)
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-		(property ki_fp_filters "C_*")
-		(path "/f1f8cbb4-1705-430d-a94d-a1fd91004fe6")
-		(sheetname "/")
-		(sheetfile "mobo.kicad_sch")
-		(attr smd)
-		(fp_line
-			(start -0.107836 -0.36)
-			(end 0.107836 -0.36)
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-				(width 0.12)
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-			(layer "F.SilkS")
-			(uuid "9fb4d648-d83d-4989-b6a2-2336965d06e8")
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-		(fp_line
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-				(type solid)
-			)
-			(layer "F.Fab")
-			(uuid "fa9adf88-e810-45bf-86ba-c7e55531f0f6")
-		)
-		(fp_line
-			(start -0.5 0.25)
-			(end -0.5 -0.25)
-			(stroke
-				(width 0.1)
-				(type solid)
-			)
-			(layer "F.Fab")
-			(uuid "acc11602-d2fe-4d8a-8fbb-3ffdb654124e")
-		)
-		(fp_line
-			(start 0.5 -0.25)
-			(end 0.5 0.25)
-			(stroke
-				(width 0.1)
-				(type solid)
-			)
-			(layer "F.Fab")
-			(uuid "29ddd823-31a8-4ba8-af23-ee7f8ee8334b")
-		)
-		(fp_line
-			(start 0.5 0.25)
-			(end -0.5 0.25)
-			(stroke
-				(width 0.1)
-				(type solid)
-			)
-			(layer "F.Fab")
-			(uuid "8a6f83d6-f129-4762-b91e-610361b58c76")
-		)
-		(fp_text user "${REFERENCE}"
-			(at 0 0 0)
-			(layer "F.Fab")
-			(uuid "3cfa55f8-8cc3-4053-a280-52c3f4250e6b")
-			(effects
-				(font
-					(size 0.25 0.25)
-					(thickness 0.04)
-				)
-			)
-		)
-		(pad "1" smd roundrect
-			(at -0.48 0)
-			(size 0.56 0.62)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 81 "GND")
-			(pintype "passive")
-			(uuid "bc9f27ec-4735-4d5a-a5fc-c84da3da4469")
-		)
-		(pad "2" smd roundrect
-			(at 0.48 0)
-			(size 0.56 0.62)
-			(layers "F.Cu" "F.Mask" "F.Paste")
-			(roundrect_rratio 0.25)
-			(net 1 "+3V3")
-			(pintype "passive")
-			(uuid "048dd017-1b4e-4285-a46b-080926ff2a56")
-		)
-		(embedded_fonts no)
-		(model "${KICAD9_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0402_1005Metric.step"
-			(offset
-				(xyz 0 0 0)
-			)
-			(scale
-				(xyz 1 1 1)
-			)
-			(rotate
-				(xyz 0 0 0)
-			)
-		)
-	)
 	(footprint "Capacitor_SMD:C_0402_1005Metric"
 		(layer "F.Cu")
 		(uuid "f5067260-7650-402b-885c-f5dda464e4b9")
@@ -29650,7 +29410,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "1555a96d-610f-47a5-875b-f1d0c09bdcc6")
 		)
@@ -29888,7 +29648,7 @@
 			(size 0.56 0.62)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "8688ad48-723f-4005-945f-506e96b161c5")
 		)
@@ -30265,7 +30025,7 @@
 			(size 0.54 0.64)
 			(layers "F.Cu" "F.Mask" "F.Paste")
 			(roundrect_rratio 0.25)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pintype "passive")
 			(uuid "fa63f1a0-ef30-4247-86bf-b94a378e42fa")
 		)
@@ -30511,7 +30271,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "Pin_1")
 			(pintype "passive")
 			(uuid "31cb1800-1c91-41a5-8b9c-b4718296b3e2")
@@ -30522,7 +30282,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 69 "unconnected-(J8-Pin_2-Pad2)")
+			(net 67 "unconnected-(J8-Pin_2-Pad2)")
 			(pinfunction "Pin_2")
 			(pintype "passive+no_connect")
 			(uuid "662e83f2-99ec-41d8-bf2a-87ba33399b58")
@@ -30544,7 +30304,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 89 "USART1_RX")
+			(net 87 "USART1_RX")
 			(pinfunction "Pin_4")
 			(pintype "passive")
 			(uuid "e5ea0713-0dd7-40e4-b661-3ff605900f22")
@@ -30555,7 +30315,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 88 "USART1_TX")
+			(net 86 "USART1_TX")
 			(pinfunction "Pin_5")
 			(pintype "passive")
 			(uuid "29c88324-b9d6-43a6-aa1b-715507c45752")
@@ -30566,7 +30326,7 @@
 			(drill 1)
 			(layers "*.Cu" "*.Mask")
 			(remove_unused_layers no)
-			(net 70 "unconnected-(J8-Pin_6-Pad6)")
+			(net 68 "unconnected-(J8-Pin_6-Pad6)")
 			(pinfunction "Pin_6")
 			(pintype "passive+no_connect")
 			(uuid "daf85798-844e-4057-8f2f-e029d3b6c850")
@@ -30820,7 +30580,7 @@
 			(at 1.27 -0.635 90)
 			(size 0.7874 0.7874)
 			(layers "B.Cu" "B.Mask")
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "Pin_5")
 			(pintype "passive")
 			(uuid "0291f655-2539-4a5f-a989-2e262d500d96")
@@ -31540,7 +31300,7 @@
 			(at -1.95 3.81 270)
 			(size 2.4 0.74)
 			(layers "B.Cu" "B.Mask" "B.Paste")
-			(net 80 "unconnected-(J10-NC-Pad1)")
+			(net 78 "unconnected-(J10-NC-Pad1)")
 			(pinfunction "NC")
 			(pintype "no_connect")
 			(uuid "d415382d-8aa6-4b28-90b5-e52bc1f8249a")
@@ -31549,7 +31309,7 @@
 			(at 1.95 3.81 270)
 			(size 2.4 0.74)
 			(layers "B.Cu" "B.Mask" "B.Paste")
-			(net 78 "unconnected-(J10-NC-Pad2)")
+			(net 76 "unconnected-(J10-NC-Pad2)")
 			(pinfunction "NC")
 			(pintype "no_connect")
 			(uuid "b34ced5f-5500-4ecc-baa5-4c4d86fa7ca4")
@@ -31576,7 +31336,7 @@
 			(at -1.95 1.27 270)
 			(size 2.4 0.74)
 			(layers "B.Cu" "B.Mask" "B.Paste")
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "GND")
 			(pintype "power_in")
 			(uuid "da5a4d82-1214-4f6c-b948-c038e7ec96e0")
@@ -31594,7 +31354,7 @@
 			(at -1.95 0 270)
 			(size 2.4 0.74)
 			(layers "B.Cu" "B.Mask" "B.Paste")
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "GND")
 			(pintype "passive")
 			(uuid "325dfe23-bebf-42e8-867d-30e8db7c26aa")
@@ -31603,7 +31363,7 @@
 			(at 1.95 0 270)
 			(size 2.4 0.74)
 			(layers "B.Cu" "B.Mask" "B.Paste")
-			(net 76 "unconnected-(J10-JTDO{slash}SWO-Pad8)")
+			(net 74 "unconnected-(J10-JTDO{slash}SWO-Pad8)")
 			(pinfunction "JTDO/SWO")
 			(pintype "input+no_connect")
 			(uuid "0cba4792-8021-41e0-b4ae-972e35453300")
@@ -31612,7 +31372,7 @@
 			(at -1.95 -1.27 270)
 			(size 2.4 0.74)
 			(layers "B.Cu" "B.Mask" "B.Paste")
-			(net 77 "unconnected-(J10-JRCLK{slash}NC-Pad9)")
+			(net 75 "unconnected-(J10-JRCLK{slash}NC-Pad9)")
 			(pinfunction "JRCLK/NC")
 			(pintype "input+no_connect")
 			(uuid "58d7aee7-9e0b-47a7-9467-9143cacf3568")
@@ -31621,7 +31381,7 @@
 			(at 1.95 -1.27 270)
 			(size 2.4 0.74)
 			(layers "B.Cu" "B.Mask" "B.Paste")
-			(net 79 "unconnected-(J10-JTDI{slash}NC-Pad10)")
+			(net 77 "unconnected-(J10-JTDI{slash}NC-Pad10)")
 			(pinfunction "JTDI/NC")
 			(pintype "output+no_connect")
 			(uuid "c485cde0-b1eb-477f-8247-8b56afd0bbb6")
@@ -31630,7 +31390,7 @@
 			(at -1.95 -2.54 270)
 			(size 2.4 0.74)
 			(layers "B.Cu" "B.Mask" "B.Paste")
-			(net 81 "GND")
+			(net 79 "GND")
 			(pinfunction "GNDDetect")
 			(pintype "passive")
 			(uuid "c03955fb-e376-4805-b280-2013c7a72b70")
@@ -31648,7 +31408,7 @@
 			(at -1.95 -3.81 270)
 			(size 2.4 0.74)
 			(layers "B.Cu" "B.Mask" "B.Paste")
-			(net 89 "USART1_RX")
+			(net 87 "USART1_RX")
 			(pinfunction "VCP_RX")
 			(pintype "output")
 			(uuid "ab025724-8da0-4ca0-8267-0eb00dec0361")
@@ -31657,7 +31417,7 @@
 			(at 1.95 -3.81 270)
 			(size 2.4 0.74)
 			(layers "B.Cu" "B.Mask" "B.Paste")
-			(net 88 "USART1_TX")
+			(net 86 "USART1_TX")
 			(pinfunction "VCP_TX")
 			(pintype "input")
 			(uuid "1d02cfc9-93ba-4955-b6a4-a72d41b41a49")
@@ -45369,20 +45129,20 @@
 		(uuid "f6746500-863a-4458-9552-ce8ad173e185")
 	)
 	(segment
-		(start 118.325 73.6464)
-		(end 118.325 71.9)
+		(start 119.125 74.4464)
+		(end 119.125 71.9)
 		(width 0.4)
 		(layer "F.Cu")
 		(net 12)
-		(uuid "cd6f4730-4403-4951-852a-9f388e97e030")
+		(uuid "4a104083-654a-4893-bd75-d0b53619ea0e")
 	)
 	(segment
 		(start 119.8706 75.192)
-		(end 118.325 73.6464)
+		(end 119.125 74.4464)
 		(width 0.4)
 		(layer "F.Cu")
 		(net 12)
-		(uuid "f2494160-7a11-4d4b-9e10-60510aeb92e2")
+		(uuid "cdaee52f-8412-45bd-8658-0a8b49e59d58")
 	)
 	(segment
 		(start 120.2994 75.192)
@@ -45393,20 +45153,20 @@
 		(uuid "f454da1d-d411-4a46-9203-13c53d2ef68f")
 	)
 	(segment
-		(start 117.075 73.7934)
-		(end 117.075 71.9)
+		(start 119.473601 76.192001)
+		(end 117.875 74.5934)
 		(width 0.4)
 		(layer "F.Cu")
 		(net 13)
-		(uuid "5d4b5fcf-12e1-4abf-8995-6b176349ec34")
+		(uuid "01793f20-f6e1-462f-b7fa-5e66761926d0")
 	)
 	(segment
-		(start 119.473601 76.192001)
-		(end 117.075 73.7934)
+		(start 117.875 74.5934)
+		(end 117.875 71.9)
 		(width 0.4)
 		(layer "F.Cu")
 		(net 13)
-		(uuid "853bd7f3-343b-4ef6-8e71-4f43d95ca98b")
+		(uuid "67f707c3-a6ed-4172-9159-b25fd28decd5")
 	)
 	(segment
 		(start 120.2994 76.192001)
@@ -45416,6 +45176,14 @@
 		(net 13)
 		(uuid "95417803-c84f-4cf7-8506-b1d74d420037")
 	)
+	(segment
+		(start 121.260054 84.735245)
+		(end 122.39797 85.873161)
+		(width 0.3)
+		(layer "F.Cu")
+		(net 14)
+		(uuid "27991f83-b20d-4a12-9c52-4021327a6d1f")
+	)
 	(segment
 		(start 104.6988 48.936835)
 		(end 104.58108 49.054555)
@@ -45432,6 +45200,22 @@
 		(net 14)
 		(uuid "4980b877-8ea9-4032-bb07-797d2435b62c")
 	)
+	(segment
+		(start 122.39797 85.873161)
+		(end 123.245039 85.873161)
+		(width 0.3)
+		(layer "F.Cu")
+		(net 14)
+		(uuid "59f34dbc-0fcf-4a60-83ef-1cf4fe8cca61")
+	)
+	(segment
+		(start 124.488202 84.629998)
+		(end 124.488202 83.2358)
+		(width 0.3)
+		(layer "F.Cu")
+		(net 14)
+		(uuid "77b05e75-68c2-40c3-9bca-0e923b9804dc")
+	)
 	(segment
 		(start 114.6321 64.5414)
 		(end 114.8099 64.7192)
@@ -45456,14 +45240,6 @@
 		(net 14)
 		(uuid "82ab4ee0-7f8f-49f8-a50a-dee70bc47517")
 	)
-	(segment
-		(start 123.2662 85.852)
-		(end 124.488202 84.629998)
-		(width 0.3)
-		(layer "F.Cu")
-		(net 14)
-		(uuid "aa2eae1c-e2f2-43a3-a618-d44ced8d3fd1")
-	)
 	(segment
 		(start 104.6988 46.6833)
 		(end 104.6988 47.8536)
@@ -45481,12 +45257,12 @@
 		(uuid "e14397e6-a042-4346-b48b-21c1ddb577f6")
 	)
 	(segment
-		(start 124.488202 84.629998)
-		(end 124.488202 83.2358)
+		(start 123.245039 85.873161)
+		(end 124.488202 84.629998)
 		(width 0.3)
 		(layer "F.Cu")
 		(net 14)
-		(uuid "fdf273e0-563d-47c3-b245-24874e6dcba6")
+		(uuid "f462d9b5-0102-4043-b70a-405183eb1d33")
 	)
 	(via
 		(at 113.157 64.5414)
@@ -45505,21 +45281,13 @@
 		(uuid "51b8f43a-2cc2-4bdf-a01f-98e6e2fa7a0e")
 	)
 	(via
-		(at 123.2662 85.852)
+		(at 121.260054 84.735245)
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(net 14)
 		(uuid "95d70e3c-49cc-4aab-9368-3c2f61ac379f")
 	)
-	(segment
-		(start 113.157 76.5048)
-		(end 117.7036 81.0514)
-		(width 0.3)
-		(layer "In2.Cu")
-		(net 14)
-		(uuid "253adaef-8af8-4577-8be6-99a31b3d9a3b")
-	)
 	(segment
 		(start 113.157 63.8556)
 		(end 113.157 64.5414)
@@ -45528,14 +45296,6 @@
 		(net 14)
 		(uuid "58f32797-45eb-42cc-8822-11ef283d9f80")
 	)
-	(segment
-		(start 117.7036 81.0514)
-		(end 122.5042 85.852)
-		(width 0.3)
-		(layer "In2.Cu")
-		(net 14)
-		(uuid "653f763a-cc84-4939-9be1-d9e9a4081b78")
-	)
 	(segment
 		(start 105.5624 56.261)
 		(end 111.3028 62.0014)
@@ -45544,14 +45304,6 @@
 		(net 14)
 		(uuid "6cbb6498-af6e-4b30-8947-193815221bf0")
 	)
-	(segment
-		(start 113.157 64.5414)
-		(end 113.157 76.5048)
-		(width 0.3)
-		(layer "In2.Cu")
-		(net 14)
-		(uuid "6e2de831-0793-4952-ae7b-3450396ab7bb")
-	)
 	(segment
 		(start 104.6988 47.8536)
 		(end 104.6988 51.5874)
@@ -45561,12 +45313,12 @@
 		(uuid "95980997-d1f4-4b83-8784-cdf586b61075")
 	)
 	(segment
-		(start 122.5042 85.852)
-		(end 123.2662 85.852)
+		(start 113.157 76.5048)
+		(end 113.157 64.5414)
 		(width 0.3)
 		(layer "In2.Cu")
 		(net 14)
-		(uuid "ab10380f-3028-478a-919a-ab62cb65f12e")
+		(uuid "a356087d-7d60-44d7-a1c2-6c00dedb3181")
 	)
 	(segment
 		(start 105.2322 52.1208)
@@ -45584,6 +45336,22 @@
 		(net 14)
 		(uuid "b8b4867d-512d-4fd9-ba20-ebab20f9c6b5")
 	)
+	(segment
+		(start 121.260054 84.735245)
+		(end 121.260054 84.607854)
+		(width 0.3)
+		(layer "In2.Cu")
+		(net 14)
+		(uuid "bb6e8815-0940-41ed-9683-95cd20d17eff")
+	)
+	(segment
+		(start 121.260054 84.607854)
+		(end 113.157 76.5048)
+		(width 0.3)
+		(layer "In2.Cu")
+		(net 14)
+		(uuid "ec1d66ef-7e10-47d6-8173-663d98df2e84")
+	)
 	(segment
 		(start 105.5624 52.451)
 		(end 105.5624 54.0512)
@@ -47464,37 +47232,37 @@
 		(net 41)
 		(uuid "7544f361-6645-446b-a06e-c0f9def0c6ce")
 	)
-	(segment
-		(start 121.793 76.3524)
-		(end 118.3 72.8594)
-		(width 0.2)
-		(layer "In2.Cu")
-		(net 41)
-		(uuid "053180c6-4ca7-4105-b45e-d4fea16681fd")
-	)
 	(segment
 		(start 125.349 84.7344)
-		(end 124.1806 83.566)
+		(end 124.98 84.3654)
 		(width 0.2)
 		(layer "In2.Cu")
 		(net 41)
-		(uuid "05dac4d1-b2ac-47bf-bcb2-d46e17cd9d0f")
+		(uuid "070d45b8-6494-4b1f-8b13-dfae8a10e2a2")
 	)
 	(segment
-		(start 124.1806 83.566)
-		(end 124.1806 81.0768)
+		(start 118.3 70.72)
+		(end 118.3 62.5724)
 		(width 0.2)
 		(layer "In2.Cu")
 		(net 41)
-		(uuid "8350ee6d-0aef-47c1-a599-2231829fde54")
+		(uuid "17f51a68-41f7-47a9-b934-d0861b6454e9")
 	)
 	(segment
-		(start 118.3 62.5724)
-		(end 109.1946 53.467)
+		(start 121.793 76.963)
+		(end 121.793 74.213)
 		(width 0.2)
 		(layer "In2.Cu")
 		(net 41)
-		(uuid "b5b6574e-7886-4f27-a50b-a6e469f89c90")
+		(uuid "34f21c2f-a22a-4448-bccf-84d811f54d30")
+	)
+	(segment
+		(start 124.98 81.805958)
+		(end 124.528847 81.354805)
+		(width 0.2)
+		(layer "In2.Cu")
+		(net 41)
+		(uuid "499c7efe-d341-4b30-a36c-21da6a11cc7c")
 	)
 	(segment
 		(start 109.1946 53.467)
@@ -47502,31 +47270,47 @@
 		(width 0.2)
 		(layer "In2.Cu")
 		(net 41)
-		(uuid "c45e8a35-332b-43f4-b657-addfffc16098")
+		(uuid "51fa0969-d76f-48ca-abf1-538d6f252f44")
 	)
 	(segment
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+		(start 118.3 62.5724)
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 		(width 0.2)
 		(layer "In2.Cu")
 		(net 41)
-		(uuid "c9b4aa9b-9484-4b37-a860-5446a4752cb3")
+		(uuid "6f7f35f4-ee6b-4acc-b77f-9de5dad9921c")
 	)
 	(segment
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 	(via
@@ -50411,16 +50299,16 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "7d6077cc-7f5a-4c15-815f-c73f5376aabb")
 	)
 	(via
-		(at 128.225 69.45)
+		(at 127.39 69.75)
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "7dba24b2-e13c-417c-b2fe-21ab8ca50449")
 	)
 	(via
@@ -50429,7 +50317,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "867f346b-adff-4278-87f7-e8a5116bf89d")
 	)
 	(via
@@ -50437,7 +50325,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "8700b274-a2c7-46c0-aa7c-0aa84c906d7a")
 	)
 	(via
@@ -50446,7 +50334,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "87382790-786a-42c8-9d3e-a54b5c0486a3")
 	)
 	(via
@@ -50455,7 +50343,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "876fdba7-f10a-42b1-b792-d933501d6348")
 	)
 	(via
@@ -50464,7 +50352,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "88f3c23f-22ae-4987-ab96-7c1c51a0955e")
 	)
 	(via
@@ -50473,7 +50361,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "895183fe-08b5-4537-b8ea-e9ac95da9937")
 	)
 	(via
@@ -50482,7 +50370,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "8b3dcee8-0a53-435d-acfc-3fefab058aac")
 	)
 	(via
@@ -50491,7 +50379,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "8eae1b81-4d3c-4996-b9f6-ed9579659863")
 	)
 	(via
@@ -50499,7 +50387,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "93fee16a-3e3c-4eeb-ab55-76561b77ada0")
 	)
 	(via
@@ -50507,7 +50395,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "943186aa-990d-457b-9336-38376a8d288f")
 	)
 	(via
@@ -50515,7 +50403,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "962509fb-f064-4721-9650-03f620bdf06f")
 	)
 	(via
@@ -50523,7 +50411,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "97990ad9-71d3-4cbc-8433-47b8ea5cf0c3")
 	)
 	(via
@@ -50532,7 +50420,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "99177348-08cd-470e-a3d7-3e2a396887aa")
 	)
 	(via
@@ -50540,7 +50428,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "991e0fec-d48d-4b58-8563-0db773e89d44")
 	)
 	(via
@@ -50549,7 +50437,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "9a8d6ae4-37d0-4597-8ca5-d95aab9dea1b")
 	)
 	(via
@@ -50557,7 +50445,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "9bc298df-55eb-481a-9ca6-2128586659a9")
 	)
 	(via
@@ -50566,7 +50454,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "9bf34ff4-2eb3-4704-b551-7d009b474f4e")
 	)
 	(via
@@ -50575,7 +50463,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "a0cf3892-0851-4634-9f70-f3634be73d25")
 	)
 	(via
@@ -50583,7 +50471,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "a3500aca-f557-4a56-970e-aae36a214ee0")
 	)
 	(via
@@ -50591,7 +50479,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "a539565a-d550-44b9-88d3-7e5378b8633b")
 	)
 	(via
@@ -50599,7 +50487,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "a5aaa32d-d6ee-4656-8be4-1fc13b360e36")
 	)
 	(via
@@ -50608,7 +50496,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "a5eace1e-8770-4ef4-acbc-22d4a1169e72")
 	)
 	(via
@@ -50617,7 +50505,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "a611b169-98c0-4e7b-a0d9-0235a8d62ff2")
 	)
 	(via
@@ -50625,7 +50513,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "a692ec81-b85a-4e3c-975f-2ae2c394e2d6")
 	)
 	(via
@@ -50633,7 +50521,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "a7fe9e8b-4c91-4463-8841-aab7eb3e83dc")
 	)
 	(via
@@ -50642,7 +50530,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "a8155ed3-2336-42bb-9c83-195d93dc45a1")
 	)
 	(via
@@ -50651,7 +50539,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "a9b37021-96e2-4e51-bc8d-62b8cdfa944c")
 	)
 	(via
@@ -50660,7 +50548,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "adbb888b-b9cd-432c-b020-279063d738ab")
 	)
 	(via
@@ -50669,7 +50557,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "b0135061-e6bf-4e1d-8ea0-d9af4656999c")
 	)
 	(via
@@ -50677,7 +50565,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "b24f61be-f854-481e-9a5a-8fbc9896c662")
 	)
 	(via
@@ -50686,7 +50574,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "b40f08cb-52bd-4d0a-a458-5562dc301767")
 	)
 	(via
@@ -50695,7 +50583,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "b4b54a27-d76a-4aaf-9134-f6585bddb165")
 	)
 	(via
@@ -50703,7 +50591,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "b5df483f-35a7-43fe-8996-d3f316c17856")
 	)
 	(via
@@ -50711,7 +50599,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "b606eaab-0ec5-4437-b820-463c21044abe")
 	)
 	(via
@@ -50719,7 +50607,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "b76e4436-7ed3-479c-8331-26dd313bc46d")
 	)
 	(via
@@ -50727,16 +50615,16 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "b7aed338-577b-4e26-8f59-819c594ff204")
 	)
 	(via
-		(at 125.35 68.58)
+		(at 124.9 68.56)
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "b9c5b2ea-cc9e-4f70-88db-62b3f45e3c65")
 	)
 	(via
@@ -50744,7 +50632,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "bae07888-740d-4558-a733-861be1ac0cee")
 	)
 	(via
@@ -50753,7 +50641,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "bb4505f4-3882-4b5a-8bd3-7a4ff73cb887")
 	)
 	(via
@@ -50761,7 +50649,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "bca90b28-d7e3-48f0-8cf5-99aeb4cb82a2")
 	)
 	(via
@@ -50770,7 +50658,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "bd5660d6-54dc-4ab1-ab6b-b4a600840cd5")
 	)
 	(via
@@ -50779,7 +50667,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "bf6ce1af-6c4a-4458-9139-e9298b46b6cb")
 	)
 	(via
@@ -50788,7 +50676,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "c1aae452-29db-4a10-a739-39530faeb702")
 	)
 	(via
@@ -50797,7 +50685,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "c5e2029b-d173-4ee2-ae54-de39cf9c7867")
 	)
 	(via
@@ -50805,7 +50693,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "c736e823-de00-44c3-b1c5-7d3d401eeda9")
 	)
 	(via
@@ -50813,7 +50701,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "cae6fb9a-4446-49e4-8ed1-e913552c9cad")
 	)
 	(via
@@ -50822,7 +50710,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "cf2b2a14-9527-4649-87c2-2ce1fda4e93f")
 	)
 	(via
@@ -50831,7 +50719,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "cf805ac3-1b48-4e96-8a45-56d6110b9b34")
 	)
 	(via
@@ -50840,7 +50728,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "d2677348-7de4-4dbf-8f6b-34591b55ed34")
 	)
 	(via
@@ -50848,7 +50736,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "d26a7b36-2769-4de1-bde8-e1487b6c6f10")
 	)
 	(via
@@ -50857,7 +50745,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "d3c10aaa-8fa8-42d4-bbcc-b4e267f82f7e")
 	)
 	(via
@@ -50866,7 +50754,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "d5c2c9c6-0ad6-47e2-9179-c69a30ba968b")
 	)
 	(via
@@ -50875,16 +50763,16 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "d88d4008-ea84-4ecd-b57b-c33a55e6042c")
 	)
 	(via
-		(at 126.675 69.775)
+		(at 126.24 69.5)
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "d9ad4e3d-4510-45da-8c22-1b97a594e8db")
 	)
 	(via
@@ -50893,7 +50781,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "da1345b9-5b6b-4b1a-aa2d-a8e47dfd6939")
 	)
 	(via
@@ -50902,7 +50790,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "db8a8e7a-2d42-493c-8765-fe634285b0d8")
 	)
 	(via
@@ -50911,7 +50799,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "dc893706-5796-4dc6-8764-1b417cf06fbe")
 	)
 	(via
@@ -50920,7 +50808,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "dd916fb1-60bd-4bb9-bf71-40d4fbd9a0d0")
 	)
 	(via
@@ -50928,7 +50816,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "e27a2dc2-d5cf-49af-9e9d-26559114c3b2")
 	)
 	(via
@@ -50936,7 +50824,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "e5d78f51-704b-4095-8e8b-441c6277d17a")
 	)
 	(via
@@ -50945,7 +50833,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "e642b80a-eb13-4629-84f5-e882e0be2ffb")
 	)
 	(via
@@ -50953,7 +50841,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "e7e098aa-0df2-49ce-9c43-dec47910ce15")
 	)
 	(via
@@ -50962,16 +50850,16 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "e8dbf9c6-e7d1-40ec-b4d5-6073021bd431")
 	)
 	(via
-		(at 126.125 69.15)
+		(at 126.35 68.78)
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "ea72163f-d1b2-49fe-8424-6e13145df0f7")
 	)
 	(via
@@ -50980,7 +50868,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "ea7662ae-a215-4836-8957-56eb8c15e137")
 	)
 	(via
@@ -50988,7 +50876,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "eba05ed4-d066-4c7a-affc-a71146e6cfb6")
 	)
 	(via
@@ -50997,7 +50885,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "ed217c5b-5aa9-493a-894c-908e5dfbcb0b")
 	)
 	(via
@@ -51005,7 +50893,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
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+		(net 79)
 		(uuid "f09f183d-0f0e-45bc-a8b3-ae57019f0102")
 	)
 	(via
@@ -51013,7 +50901,7 @@
 		(size 0.6)
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
-		(net 81)
+		(net 79)
 		(uuid "f0f77a4b-daec-4785-9ac3-39ce34f5fc9e")
 	)
 	(via
@@ -51022,7 +50910,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
-		(net 81)
+		(net 79)
 		(uuid "f1a6d95d-de2a-4256-ade0-6bebfc1bb4bd")
 	)
 	(via
@@ -51031,7 +50919,7 @@
 		(drill 0.3)
 		(layers "F.Cu" "B.Cu")
 		(free yes)
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diff --git a/pcb/mobo/mobo.kicad_sch b/pcb/mobo/mobo.kicad_sch
index e351451..eff7edc 100644
--- a/pcb/mobo/mobo.kicad_sch
+++ b/pcb/mobo/mobo.kicad_sch
@@ -5,7 +5,11 @@
 	(uuid "e502d1d5-04b0-4d4b-b5c3-8c52d09668e7")
 	(paper "A3")
 	(title_block
-		(title "LumenPnP Feeder Control Board")
+		(title "Improved LumenPnP Feeder Control Board")
+		(date "2026-03-30")
+		(rev "1.1")
+		(company "B4L Co. Ltd.")
+		(comment 1 "Janik Oltmanns")
 	)
 	(lib_symbols
 		(symbol "Connector:Conn_01x02_Female"
@@ -6770,27 +6774,6 @@
 		)
 		(uuid "167da701-8bda-4d70-bf9f-94ec72cae84b")
 	)
-	(text "RC0402FR-071K4L mismatch"
-		(exclude_from_sim no)
-		(at 204.724 -27.686 0)
-		(effects
-			(font
-				(size 7.62 7.62)
-			)
-		)
-		(uuid "18c1a8e1-04b3-4699-ae05-5f45c0b31efd")
-	)
-	(text "TODO: R22 footprint mismatch"
-		(exclude_from_sim no)
-		(at 119.634 -10.668 0)
-		(effects
-			(font
-				(size 7.62 7.62)
-			)
-			(justify left bottom)
-		)
-		(uuid "2a589dc4-ebbc-4012-90df-fda670568c32")
-	)
 	(text "RS485"
 		(exclude_from_sim no)
 		(at 243.332 137.922 0)
@@ -7356,12 +7339,6 @@
 		(color 0 0 0 0)
 		(uuid "bd476cda-6d5c-4446-8e4f-80117744bce7")
 	)
-	(junction
-		(at 179.07 133.35)
-		(diameter 0)
-		(color 0 0 0 0)
-		(uuid "be6c61ef-213f-4ba3-9fe5-7099e747dcbe")
-	)
 	(junction
 		(at 241.3 224.79)
 		(diameter 0)
@@ -7398,12 +7375,6 @@
 		(color 0 0 0 0)
 		(uuid "d4415b6c-9f46-4cbe-b824-930d37925d16")
 	)
-	(junction
-		(at 185.42 143.51)
-		(diameter 0)
-		(color 0 0 0 0)
-		(uuid "d7069750-8bd4-4e7a-879e-b21fe681195a")
-	)
 	(junction
 		(at 201.93 208.28)
 		(diameter 0)
@@ -8348,16 +8319,6 @@
 		)
 		(uuid "5688f0c1-7946-4fe3-9c8f-ca3305b0ea33")
 	)
-	(wire
-		(pts
-			(xy 185.42 140.97) (xy 185.42 143.51)
-		)
-		(stroke
-			(width 0)
-			(type default)
-		)
-		(uuid "56cb462c-2b5c-495f-be2a-f302d30ee4ad")
-	)
 	(wire
 		(pts
 			(xy 48.26 172.72) (xy 44.45 172.72)
@@ -8618,16 +8579,6 @@
 		)
 		(uuid "6e523d02-f914-47b9-adc4-a676cbc34590")
 	)
-	(wire
-		(pts
-			(xy 185.42 135.89) (xy 185.42 133.35)
-		)
-		(stroke
-			(width 0)
-			(type default)
-		)
-		(uuid "6f3f2ec5-9a8b-47a5-9b12-a8acb4c5c276")
-	)
 	(wire
 		(pts
 			(xy 240.03 161.29) (xy 241.3 161.29)
@@ -9678,16 +9629,6 @@
 		)
 		(uuid "e87738fc-e372-4c48-9de9-398fd8b4874c")
 	)
-	(wire
-		(pts
-			(xy 185.42 133.35) (xy 179.07 133.35)
-		)
-		(stroke
-			(width 0)
-			(type default)
-		)
-		(uuid "e9f8dcc2-a866-48f1-947a-1b556e57de0e")
-	)
 	(wire
 		(pts
 			(xy 237.49 161.29) (xy 240.03 161.29)
@@ -10482,6 +10423,50 @@
 			)
 		)
 	)
+	(global_label "IPROP_PEEL"
+		(shape input)
+		(at 71.12 66.04 180)
+		(fields_autoplaced yes)
+		(effects
+			(font
+				(size 1.27 1.27)
+			)
+			(justify right)
+		)
+		(uuid "50e3b4bc-4034-4d62-90b6-ca9e01c29c43")
+		(property "Intersheetrefs" "${INTERSHEET_REFS}"
+			(at 57.48 66.04 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify right)
+				(hide yes)
+			)
+		)
+	)
+	(global_label "IPROP_PEEL"
+		(shape input)
+		(at 262.89 110.49 0)
+		(fields_autoplaced yes)
+		(effects
+			(font
+				(size 1.27 1.27)
+			)
+			(justify left)
+		)
+		(uuid "5854c743-7115-4502-8243-263b6aca6156")
+		(property "Intersheetrefs" "${INTERSHEET_REFS}"
+			(at 276.53 110.49 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left)
+				(hide yes)
+			)
+		)
+	)
 	(global_label "PEEL1"
 		(shape input)
 		(at 71.12 53.34 180)
@@ -10525,6 +10510,28 @@
 			)
 		)
 	)
+	(global_label "IPROP_DRIVE"
+		(shape input)
+		(at 262.89 63.5 0)
+		(fields_autoplaced yes)
+		(effects
+			(font
+				(size 1.27 1.27)
+			)
+			(justify left)
+		)
+		(uuid "659c28a3-d2db-4e1d-bd18-182b1d0e1c34")
+		(property "Intersheetrefs" "${INTERSHEET_REFS}"
+			(at 277.3163 63.5 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify left)
+				(hide yes)
+			)
+		)
+	)
 	(global_label "SWDIO"
 		(shape input)
 		(at 71.12 81.28 180)
@@ -11070,6 +11077,28 @@
 			)
 		)
 	)
+	(global_label "IPROP_DRIVE"
+		(shape input)
+		(at 71.12 121.92 180)
+		(fields_autoplaced yes)
+		(effects
+			(font
+				(size 1.27 1.27)
+			)
+			(justify right)
+		)
+		(uuid "c43e7f30-1cca-4b51-81a7-879f9c3d066e")
+		(property "Intersheetrefs" "${INTERSHEET_REFS}"
+			(at 56.6937 121.92 0)
+			(effects
+				(font
+					(size 1.27 1.27)
+				)
+				(justify right)
+				(hide yes)
+			)
+		)
+	)
 	(global_label "SWCLK_BOOT0"
 		(shape input)
 		(at 29.21 201.93 180)
@@ -14441,7 +14470,7 @@
 				(hide yes)
 			)
 		)
-		(property "MPN" "RT0402BRE0711K5L"
+		(property "MPN" "RT0603FRE0711K5L"
 			(at 199.39 251.46 0)
 			(effects
 				(font
@@ -21103,7 +21132,7 @@
 				(hide yes)
 			)
 		)
-		(property "MPN" "RC0402FR-071K4L"
+		(property "MPN" "RT0603FRE071K4L"
 			(at 262.89 67.31 0)
 			(effects
 				(font
@@ -21182,7 +21211,7 @@
 				(hide yes)
 			)
 		)
-		(property "MPN" "RC0402FR-071K4L"
+		(property "MPN" "RT0603FRE071K4L"
 			(at 262.89 114.3 0)
 			(effects
 				(font
@@ -25968,101 +25997,6 @@
 			)
 		)
 	)
-	(symbol
-		(lib_id "Device:C_Small")
-		(at 185.42 138.43 180)
-		(unit 1)
-		(exclude_from_sim no)
-		(in_bom yes)
-		(on_board yes)
-		(dnp no)
-		(uuid "f1f8cbb4-1705-430d-a94d-a1fd91004fe6")
-		(property "Reference" "C11"
-			(at 189.865 137.795 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left)
-			)
-		)
-		(property "Value" "4.7uF"
-			(at 191.77 140.335 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(justify left)
-			)
-		)
-		(property "Footprint" "Capacitor_SMD:C_0402_1005Metric"
-			(at 185.42 138.43 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(hide yes)
-			)
-		)
-		(property "Datasheet" "~"
-			(at 185.42 138.43 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(hide yes)
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-		)
-		(property "Description" ""
-			(at 185.42 138.43 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-			)
-		)
-		(property "JLCPCB" "C49678"
-			(at 185.42 138.43 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(hide yes)
-			)
-		)
-		(property "LCSC" "C476766"
-			(at 185.42 138.43 0)
-			(effects
-				(font
-					(size 1.27 1.27)
-				)
-				(hide yes)
-			)
-		)
-		(property "MPN" "CC0402MRX5R6BB475"
-			(at 185.42 138.43 0)
-			(effects
-				(font
-					(size 1.27 1.27)
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-				(hide yes)
-			)
-		)
-		(pin "1"
-			(uuid "1d957ba9-a3e8-41ef-88ef-d2a04d87bcc2")
-		)
-		(pin "2"
-			(uuid "d939758d-0dc3-4efa-a1b7-0ed790d60909")
-		)
-		(instances
-			(project "mobo"
-				(path "/e502d1d5-04b0-4d4b-b5c3-8c52d09668e7"
-					(reference "C11")
-					(unit 1)
-				)
-			)
-		)
-	)
 	(symbol
 		(lib_id "Device:C")
 		(at 187.96 193.04 90)
diff --git a/pcb/mobo/~mobo.kicad_sch.lck b/pcb/mobo/~mobo.kicad_sch.lck
deleted file mode 100644
index 64ce498..0000000
--- a/pcb/mobo/~mobo.kicad_sch.lck
+++ /dev/null
@@ -1 +0,0 @@
-{"hostname":"SUPERDUPER","username":"janik"}
\ No newline at end of file
diff --git a/rs485.png b/rs485.png
new file mode 100644
index 0000000..08f7a82
Binary files /dev/null and b/rs485.png differ